xref: /titanic_41/usr/src/uts/i86pc/io/apix/apix.c (revision d169295fc4875fb20ee4283e587b4d306606a217)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
24  */
25 /*
26  * Copyright (c) 2010, Intel Corporation.
27  * All rights reserved.
28  */
29 /*
30  * Copyright (c) 2013, Joyent, Inc.  All rights reserved.
31  */
32 
33 /*
34  * To understand how the apix module interacts with the interrupt subsystem read
35  * the theory statement in uts/i86pc/os/intr.c.
36  */
37 
38 /*
39  * PSMI 1.1 extensions are supported only in 2.6 and later versions.
40  * PSMI 1.2 extensions are supported only in 2.7 and later versions.
41  * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
42  * PSMI 1.5 extensions are supported in Solaris Nevada.
43  * PSMI 1.6 extensions are supported in Solaris Nevada.
44  * PSMI 1.7 extensions are supported in Solaris Nevada.
45  */
46 #define	PSMI_1_7
47 
48 #include <sys/processor.h>
49 #include <sys/time.h>
50 #include <sys/psm.h>
51 #include <sys/smp_impldefs.h>
52 #include <sys/cram.h>
53 #include <sys/acpi/acpi.h>
54 #include <sys/acpica.h>
55 #include <sys/psm_common.h>
56 #include <sys/pit.h>
57 #include <sys/ddi.h>
58 #include <sys/sunddi.h>
59 #include <sys/ddi_impldefs.h>
60 #include <sys/pci.h>
61 #include <sys/promif.h>
62 #include <sys/x86_archext.h>
63 #include <sys/cpc_impl.h>
64 #include <sys/uadmin.h>
65 #include <sys/panic.h>
66 #include <sys/debug.h>
67 #include <sys/archsystm.h>
68 #include <sys/trap.h>
69 #include <sys/machsystm.h>
70 #include <sys/sysmacros.h>
71 #include <sys/cpuvar.h>
72 #include <sys/rm_platter.h>
73 #include <sys/privregs.h>
74 #include <sys/note.h>
75 #include <sys/pci_intr_lib.h>
76 #include <sys/spl.h>
77 #include <sys/clock.h>
78 #include <sys/cyclic.h>
79 #include <sys/dditypes.h>
80 #include <sys/sunddi.h>
81 #include <sys/x_call.h>
82 #include <sys/reboot.h>
83 #include <sys/mach_intr.h>
84 #include <sys/apix.h>
85 #include <sys/apix_irm_impl.h>
86 
87 static int apix_probe();
88 static void apix_init();
89 static void apix_picinit(void);
90 static int apix_intr_enter(int, int *);
91 static void apix_intr_exit(int, int);
92 static void apix_setspl(int);
93 static int apix_disable_intr(processorid_t);
94 static void apix_enable_intr(processorid_t);
95 static int apix_get_clkvect(int);
96 static int apix_get_ipivect(int, int);
97 static void apix_post_cyclic_setup(void *);
98 static int apix_post_cpu_start();
99 static int apix_intr_ops(dev_info_t *, ddi_intr_handle_impl_t *,
100     psm_intr_op_t, int *);
101 
102 /*
103  * Helper functions for apix_intr_ops()
104  */
105 static void apix_redistribute_compute(void);
106 static int apix_get_pending(apix_vector_t *);
107 static apix_vector_t *apix_get_req_vector(ddi_intr_handle_impl_t *, ushort_t);
108 static int apix_get_intr_info(ddi_intr_handle_impl_t *, apic_get_intr_t *);
109 static char *apix_get_apic_type(void);
110 static int apix_intx_get_pending(int);
111 static void apix_intx_set_mask(int irqno);
112 static void apix_intx_clear_mask(int irqno);
113 static int apix_intx_get_shared(int irqno);
114 static void apix_intx_set_shared(int irqno, int delta);
115 static apix_vector_t *apix_intx_xlate_vector(dev_info_t *, int,
116     struct intrspec *);
117 static int apix_intx_alloc_vector(dev_info_t *, int, struct intrspec *);
118 
119 extern int apic_clkinit(int);
120 
121 /* IRM initialization for APIX PSM module */
122 extern void apix_irm_init(void);
123 
124 extern int irm_enable;
125 
126 /*
127  *	Local static data
128  */
129 static struct	psm_ops apix_ops = {
130 	apix_probe,
131 
132 	apix_init,
133 	apix_picinit,
134 	apix_intr_enter,
135 	apix_intr_exit,
136 	apix_setspl,
137 	apix_addspl,
138 	apix_delspl,
139 	apix_disable_intr,
140 	apix_enable_intr,
141 	NULL,			/* psm_softlvl_to_irq */
142 	NULL,			/* psm_set_softintr */
143 
144 	apic_set_idlecpu,
145 	apic_unset_idlecpu,
146 
147 	apic_clkinit,
148 	apix_get_clkvect,
149 	NULL,			/* psm_hrtimeinit */
150 	apic_gethrtime,
151 
152 	apic_get_next_processorid,
153 	apic_cpu_start,
154 	apix_post_cpu_start,
155 	apic_shutdown,
156 	apix_get_ipivect,
157 	apic_send_ipi,
158 
159 	NULL,			/* psm_translate_irq */
160 	NULL,			/* psm_notify_error */
161 	NULL,			/* psm_notify_func */
162 	apic_timer_reprogram,
163 	apic_timer_enable,
164 	apic_timer_disable,
165 	apix_post_cyclic_setup,
166 	apic_preshutdown,
167 	apix_intr_ops,		/* Advanced DDI Interrupt framework */
168 	apic_state,		/* save, restore apic state for S3 */
169 	apic_cpu_ops,		/* CPU control interface. */
170 };
171 
172 struct psm_ops *psmops = &apix_ops;
173 
174 static struct	psm_info apix_psm_info = {
175 	PSM_INFO_VER01_7,			/* version */
176 	PSM_OWN_EXCLUSIVE,			/* ownership */
177 	&apix_ops,				/* operation */
178 	APIX_NAME,				/* machine name */
179 	"apix MPv1.4 compatible",
180 };
181 
182 static void *apix_hdlp;
183 
184 static int apix_is_enabled = 0;
185 
186 /*
187  * Flag to indicate if APIX is to be enabled only for platforms
188  * with specific hw feature(s).
189  */
190 int apix_hw_chk_enable = 1;
191 
192 /*
193  * Hw features that are checked for enabling APIX support.
194  */
195 #define	APIX_SUPPORT_X2APIC	0x00000001
196 uint_t apix_supported_hw = APIX_SUPPORT_X2APIC;
197 
198 /*
199  * apix_lock is used for cpu selection and vector re-binding
200  */
201 lock_t apix_lock;
202 apix_impl_t *apixs[NCPU];
203 /*
204  * Mapping between device interrupt and the allocated vector. Indexed
205  * by major number.
206  */
207 apix_dev_vector_t **apix_dev_vector;
208 /*
209  * Mapping between device major number and cpu id. It gets used
210  * when interrupt binding policy round robin with affinity is
211  * applied. With that policy, devices with the same major number
212  * will be bound to the same CPU.
213  */
214 processorid_t *apix_major_to_cpu;	/* major to cpu mapping */
215 kmutex_t apix_mutex;	/* for apix_dev_vector & apix_major_to_cpu */
216 
217 int apix_nipis = 16;	/* Maximum number of IPIs */
218 /*
219  * Maximum number of vectors in a CPU that can be used for interrupt
220  * allocation (including IPIs and the reserved vectors).
221  */
222 int apix_cpu_nvectors = APIX_NVECTOR;
223 
224 /* gcpu.h */
225 
226 extern void apic_do_interrupt(struct regs *rp, trap_trace_rec_t *ttp);
227 extern void apic_change_eoi();
228 
229 /*
230  *	This is the loadable module wrapper
231  */
232 
233 int
_init(void)234 _init(void)
235 {
236 	if (apic_coarse_hrtime)
237 		apix_ops.psm_gethrtime = &apic_gettime;
238 	return (psm_mod_init(&apix_hdlp, &apix_psm_info));
239 }
240 
241 int
_fini(void)242 _fini(void)
243 {
244 	return (psm_mod_fini(&apix_hdlp, &apix_psm_info));
245 }
246 
247 int
_info(struct modinfo * modinfop)248 _info(struct modinfo *modinfop)
249 {
250 	return (psm_mod_info(&apix_hdlp, &apix_psm_info, modinfop));
251 }
252 
253 static int
apix_probe()254 apix_probe()
255 {
256 	int rval;
257 
258 	if (apix_enable == 0)
259 		return (PSM_FAILURE);
260 
261 	/* check for hw features if specified  */
262 	if (apix_hw_chk_enable) {
263 		/* check if x2APIC mode is supported */
264 		if ((apix_supported_hw & APIX_SUPPORT_X2APIC) ==
265 		    APIX_SUPPORT_X2APIC) {
266 			if (!((apic_local_mode() == LOCAL_X2APIC) ||
267 			    apic_detect_x2apic())) {
268 				/* x2APIC mode is not supported in the hw */
269 				apix_enable = 0;
270 			}
271 		}
272 		if (apix_enable == 0)
273 			return (PSM_FAILURE);
274 	}
275 
276 	rval = apic_probe_common(apix_psm_info.p_mach_idstring);
277 	if (rval == PSM_SUCCESS)
278 		apix_is_enabled = 1;
279 	else
280 		apix_is_enabled = 0;
281 	return (rval);
282 }
283 
284 /*
285  * Initialize the data structures needed by pcplusmpx module.
286  * Specifically, the data structures used by addspl() and delspl()
287  * routines.
288  */
289 static void
apix_softinit()290 apix_softinit()
291 {
292 	int i, *iptr;
293 	apix_impl_t *hdlp;
294 	int nproc;
295 
296 	nproc = max(apic_nproc, apic_max_nproc);
297 
298 	hdlp = kmem_zalloc(nproc * sizeof (apix_impl_t), KM_SLEEP);
299 	for (i = 0; i < nproc; i++) {
300 		apixs[i] = &hdlp[i];
301 		apixs[i]->x_cpuid = i;
302 		LOCK_INIT_CLEAR(&apixs[i]->x_lock);
303 	}
304 
305 	/* cpu 0 is always up (for now) */
306 	apic_cpus[0].aci_status = APIC_CPU_ONLINE | APIC_CPU_INTR_ENABLE;
307 
308 	iptr = (int *)&apic_irq_table[0];
309 	for (i = 0; i <= APIC_MAX_VECTOR; i++) {
310 		apic_level_intr[i] = 0;
311 		*iptr++ = NULL;
312 	}
313 	mutex_init(&airq_mutex, NULL, MUTEX_DEFAULT, NULL);
314 
315 	apix_dev_vector = kmem_zalloc(sizeof (apix_dev_vector_t *) * devcnt,
316 	    KM_SLEEP);
317 
318 	if (apic_intr_policy == INTR_ROUND_ROBIN_WITH_AFFINITY) {
319 		apix_major_to_cpu = kmem_zalloc(sizeof (int) * devcnt,
320 		    KM_SLEEP);
321 		for (i = 0; i < devcnt; i++)
322 			apix_major_to_cpu[i] = IRQ_UNINIT;
323 	}
324 
325 	mutex_init(&apix_mutex, NULL, MUTEX_DEFAULT, NULL);
326 }
327 
328 static int
apix_get_pending_spl(void)329 apix_get_pending_spl(void)
330 {
331 	int cpuid = CPU->cpu_id;
332 
333 	return (bsrw_insn(apixs[cpuid]->x_intr_pending));
334 }
335 
336 static uintptr_t
apix_get_intr_handler(int cpu,short vec)337 apix_get_intr_handler(int cpu, short vec)
338 {
339 	apix_vector_t *apix_vector;
340 
341 	ASSERT(cpu < apic_nproc && vec < APIX_NVECTOR);
342 	if (cpu >= apic_nproc)
343 		return (NULL);
344 
345 	apix_vector = apixs[cpu]->x_vectbl[vec];
346 
347 	return ((uintptr_t)(apix_vector->v_autovect));
348 }
349 
350 static void
apix_init()351 apix_init()
352 {
353 	extern void (*do_interrupt_common)(struct regs *, trap_trace_rec_t *);
354 
355 	APIC_VERBOSE(INIT, (CE_CONT, "apix: psm_softinit\n"));
356 
357 	do_interrupt_common = apix_do_interrupt;
358 	addintr = apix_add_avintr;
359 	remintr = apix_rem_avintr;
360 	get_pending_spl = apix_get_pending_spl;
361 	get_intr_handler = apix_get_intr_handler;
362 	psm_get_localapicid = apic_get_localapicid;
363 	psm_get_ioapicid = apic_get_ioapicid;
364 
365 	apix_softinit();
366 
367 #if !defined(__amd64)
368 	if (cpuid_have_cr8access(CPU))
369 		apic_have_32bit_cr8 = 1;
370 #endif
371 
372 	/*
373 	 * Initialize IRM pool parameters
374 	 */
375 	if (irm_enable) {
376 		int	i;
377 		int	lowest_irq;
378 		int	highest_irq;
379 
380 		/* number of CPUs present */
381 		apix_irminfo.apix_ncpus = apic_nproc;
382 		/* total number of entries in all of the IOAPICs present */
383 		lowest_irq = apic_io_vectbase[0];
384 		highest_irq = apic_io_vectend[0];
385 		for (i = 1; i < apic_io_max; i++) {
386 			if (apic_io_vectbase[i] < lowest_irq)
387 				lowest_irq = apic_io_vectbase[i];
388 			if (apic_io_vectend[i] > highest_irq)
389 				highest_irq = apic_io_vectend[i];
390 		}
391 		apix_irminfo.apix_ioapic_max_vectors =
392 		    highest_irq - lowest_irq + 1;
393 		/*
394 		 * Number of available per-CPU vectors excluding
395 		 * reserved vectors for Dtrace, int80, system-call,
396 		 * fast-trap, etc.
397 		 */
398 		apix_irminfo.apix_per_cpu_vectors = APIX_NAVINTR -
399 		    APIX_SW_RESERVED_VECTORS;
400 
401 		/* Number of vectors (pre) allocated (SCI and HPET) */
402 		apix_irminfo.apix_vectors_allocated = 0;
403 		if (apic_hpet_vect != -1)
404 			apix_irminfo.apix_vectors_allocated++;
405 		if (apic_sci_vect != -1)
406 			apix_irminfo.apix_vectors_allocated++;
407 	}
408 }
409 
410 static void
apix_init_intr()411 apix_init_intr()
412 {
413 	processorid_t	cpun = psm_get_cpu_id();
414 	uint_t nlvt;
415 	uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
416 	extern void cmi_cmci_trap(void);
417 
418 	apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
419 
420 	if (apic_mode == LOCAL_APIC) {
421 		/*
422 		 * We are running APIC in MMIO mode.
423 		 */
424 		if (apic_flat_model) {
425 			apic_reg_ops->apic_write(APIC_FORMAT_REG,
426 			    APIC_FLAT_MODEL);
427 		} else {
428 			apic_reg_ops->apic_write(APIC_FORMAT_REG,
429 			    APIC_CLUSTER_MODEL);
430 		}
431 
432 		apic_reg_ops->apic_write(APIC_DEST_REG,
433 		    AV_HIGH_ORDER >> cpun);
434 	}
435 
436 	if (apic_directed_EOI_supported()) {
437 		/*
438 		 * Setting the 12th bit in the Spurious Interrupt Vector
439 		 * Register suppresses broadcast EOIs generated by the local
440 		 * APIC. The suppression of broadcast EOIs happens only when
441 		 * interrupts are level-triggered.
442 		 */
443 		svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
444 	}
445 
446 	/* need to enable APIC before unmasking NMI */
447 	apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
448 
449 	/*
450 	 * Presence of an invalid vector with delivery mode AV_FIXED can
451 	 * cause an error interrupt, even if the entry is masked...so
452 	 * write a valid vector to LVT entries along with the mask bit
453 	 */
454 
455 	/* All APICs have timer and LINT0/1 */
456 	apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
457 	apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
458 	apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI);	/* enable NMI */
459 
460 	/*
461 	 * On integrated APICs, the number of LVT entries is
462 	 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
463 	 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
464 	 */
465 
466 	if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
467 		nlvt = 3;
468 	} else {
469 		nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
470 		    0xFF) + 1;
471 	}
472 
473 	if (nlvt >= 5) {
474 		/* Enable performance counter overflow interrupt */
475 
476 		if (!is_x86_feature(x86_featureset, X86FSET_MSR))
477 			apic_enable_cpcovf_intr = 0;
478 		if (apic_enable_cpcovf_intr) {
479 			if (apic_cpcovf_vect == 0) {
480 				int ipl = APIC_PCINT_IPL;
481 
482 				apic_cpcovf_vect = apix_get_ipivect(ipl, -1);
483 				ASSERT(apic_cpcovf_vect);
484 
485 				(void) add_avintr(NULL, ipl,
486 				    (avfunc)kcpc_hw_overflow_intr,
487 				    "apic pcint", apic_cpcovf_vect,
488 				    NULL, NULL, NULL, NULL);
489 				kcpc_hw_overflow_intr_installed = 1;
490 				kcpc_hw_enable_cpc_intr =
491 				    apic_cpcovf_mask_clear;
492 			}
493 			apic_reg_ops->apic_write(APIC_PCINT_VECT,
494 			    apic_cpcovf_vect);
495 		}
496 	}
497 
498 	if (nlvt >= 6) {
499 		/* Only mask TM intr if the BIOS apparently doesn't use it */
500 
501 		uint32_t lvtval;
502 
503 		lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
504 		if (((lvtval & AV_MASK) == AV_MASK) ||
505 		    ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
506 			apic_reg_ops->apic_write(APIC_THERM_VECT,
507 			    AV_MASK|APIC_RESV_IRQ);
508 		}
509 	}
510 
511 	/* Enable error interrupt */
512 
513 	if (nlvt >= 4 && apic_enable_error_intr) {
514 		if (apic_errvect == 0) {
515 			int ipl = 0xf;	/* get highest priority intr */
516 			apic_errvect = apix_get_ipivect(ipl, -1);
517 			ASSERT(apic_errvect);
518 			/*
519 			 * Not PSMI compliant, but we are going to merge
520 			 * with ON anyway
521 			 */
522 			(void) add_avintr(NULL, ipl,
523 			    (avfunc)apic_error_intr, "apic error intr",
524 			    apic_errvect, NULL, NULL, NULL, NULL);
525 		}
526 		apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
527 		apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
528 		apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
529 	}
530 
531 	/* Enable CMCI interrupt */
532 	if (cmi_enable_cmci) {
533 		mutex_enter(&cmci_cpu_setup_lock);
534 		if (cmci_cpu_setup_registered == 0) {
535 			mutex_enter(&cpu_lock);
536 			register_cpu_setup_func(cmci_cpu_setup, NULL);
537 			mutex_exit(&cpu_lock);
538 			cmci_cpu_setup_registered = 1;
539 		}
540 		mutex_exit(&cmci_cpu_setup_lock);
541 
542 		if (apic_cmci_vect == 0) {
543 			int ipl = 0x2;
544 			apic_cmci_vect = apix_get_ipivect(ipl, -1);
545 			ASSERT(apic_cmci_vect);
546 
547 			(void) add_avintr(NULL, ipl,
548 			    (avfunc)cmi_cmci_trap, "apic cmci intr",
549 			    apic_cmci_vect, NULL, NULL, NULL, NULL);
550 		}
551 		apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect);
552 	}
553 
554 	apic_reg_ops->apic_write_task_reg(0);
555 }
556 
557 static void
apix_picinit(void)558 apix_picinit(void)
559 {
560 	int i, j;
561 	uint_t isr;
562 
563 	APIC_VERBOSE(INIT, (CE_CONT, "apix: psm_picinit\n"));
564 
565 	/*
566 	 * initialize interrupt remapping before apic
567 	 * hardware initialization
568 	 */
569 	apic_intrmap_init(apic_mode);
570 	if (apic_vt_ops == psm_vt_ops)
571 		apix_mul_ioapic_method = APIC_MUL_IOAPIC_IIR;
572 
573 	/*
574 	 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
575 	 * bit on without clearing it with EOI.  Since softint
576 	 * uses vector 0x20 to interrupt itself, so softint will
577 	 * not work on this machine.  In order to fix this problem
578 	 * a check is made to verify all the isr bits are clear.
579 	 * If not, EOIs are issued to clear the bits.
580 	 */
581 	for (i = 7; i >= 1; i--) {
582 		isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
583 		if (isr != 0)
584 			for (j = 0; ((j < 32) && (isr != 0)); j++)
585 				if (isr & (1 << j)) {
586 					apic_reg_ops->apic_write(
587 					    APIC_EOI_REG, 0);
588 					isr &= ~(1 << j);
589 					apic_error |= APIC_ERR_BOOT_EOI;
590 				}
591 	}
592 
593 	/* set a flag so we know we have run apic_picinit() */
594 	apic_picinit_called = 1;
595 	LOCK_INIT_CLEAR(&apic_gethrtime_lock);
596 	LOCK_INIT_CLEAR(&apic_ioapic_lock);
597 	LOCK_INIT_CLEAR(&apic_error_lock);
598 	LOCK_INIT_CLEAR(&apic_mode_switch_lock);
599 
600 	picsetup();	 /* initialise the 8259 */
601 
602 	/* add nmi handler - least priority nmi handler */
603 	LOCK_INIT_CLEAR(&apic_nmi_lock);
604 
605 	if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr,
606 	    "apix NMI handler", (caddr_t)NULL))
607 		cmn_err(CE_WARN, "apix: Unable to add nmi handler");
608 
609 	apix_init_intr();
610 
611 	/* enable apic mode if imcr present */
612 	if (apic_imcrp) {
613 		outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
614 		outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
615 	}
616 
617 	ioapix_init_intr(IOAPIC_MASK);
618 
619 	/* setup global IRM pool if applicable */
620 	if (irm_enable)
621 		apix_irm_init();
622 }
623 
624 static __inline__ void
apix_send_eoi(void)625 apix_send_eoi(void)
626 {
627 	if (apic_mode == LOCAL_APIC)
628 		LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
629 	else
630 		X2APIC_WRITE(APIC_EOI_REG, 0);
631 }
632 
633 /*
634  * platform_intr_enter
635  *
636  *	Called at the beginning of the interrupt service routine, but unlike
637  *	pcplusmp, does not mask interrupts. An EOI is given to the interrupt
638  *	controller to enable other HW interrupts but interrupts are still
639  * 	masked by the IF flag.
640  *
641  *	Return -1 for spurious interrupts
642  *
643  */
644 static int
apix_intr_enter(int ipl,int * vectorp)645 apix_intr_enter(int ipl, int *vectorp)
646 {
647 	struct cpu *cpu = CPU;
648 	uint32_t cpuid = CPU->cpu_id;
649 	apic_cpus_info_t *cpu_infop;
650 	uchar_t vector;
651 	apix_vector_t *vecp;
652 	int nipl = -1;
653 
654 	/*
655 	 * The real vector delivered is (*vectorp + 0x20), but our caller
656 	 * subtracts 0x20 from the vector before passing it to us.
657 	 * (That's why APIC_BASE_VECT is 0x20.)
658 	 */
659 	vector = *vectorp = (uchar_t)*vectorp + APIC_BASE_VECT;
660 
661 	cpu_infop = &apic_cpus[cpuid];
662 	if (vector == APIC_SPUR_INTR) {
663 		cpu_infop->aci_spur_cnt++;
664 		return (APIC_INT_SPURIOUS);
665 	}
666 
667 	vecp = xv_vector(cpuid, vector);
668 	if (vecp == NULL) {
669 		if (APIX_IS_FAKE_INTR(vector))
670 			nipl = apix_rebindinfo.i_pri;
671 		apix_send_eoi();
672 		return (nipl);
673 	}
674 	nipl = vecp->v_pri;
675 
676 	/* if interrupted by the clock, increment apic_nsec_since_boot */
677 	if (vector == (apic_clkvect + APIC_BASE_VECT)) {
678 		if (!apic_oneshot) {
679 			/* NOTE: this is not MT aware */
680 			apic_hrtime_stamp++;
681 			apic_nsec_since_boot += apic_nsec_per_intr;
682 			apic_hrtime_stamp++;
683 			last_count_read = apic_hertz_count;
684 			apix_redistribute_compute();
685 		}
686 
687 		apix_send_eoi();
688 
689 		return (nipl);
690 	}
691 
692 	ASSERT(vecp->v_state != APIX_STATE_OBSOLETED);
693 
694 	/* pre-EOI handling for level-triggered interrupts */
695 	if (!APIX_IS_DIRECTED_EOI(apix_mul_ioapic_method) &&
696 	    (vecp->v_type & APIX_TYPE_FIXED) && apic_level_intr[vecp->v_inum])
697 		apix_level_intr_pre_eoi(vecp->v_inum);
698 
699 	/* send back EOI */
700 	apix_send_eoi();
701 
702 	cpu_infop->aci_current[nipl] = vector;
703 	if ((nipl > ipl) && (nipl > cpu->cpu_base_spl)) {
704 		cpu_infop->aci_curipl = (uchar_t)nipl;
705 		cpu_infop->aci_ISR_in_progress |= 1 << nipl;
706 	}
707 
708 #ifdef	DEBUG
709 	if (vector >= APIX_IPI_MIN)
710 		return (nipl);	/* skip IPI */
711 
712 	APIC_DEBUG_BUF_PUT(vector);
713 	APIC_DEBUG_BUF_PUT(vecp->v_inum);
714 	APIC_DEBUG_BUF_PUT(nipl);
715 	APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
716 	if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
717 		drv_usecwait(apic_stretch_interrupts);
718 #endif /* DEBUG */
719 
720 	return (nipl);
721 }
722 
723 /*
724  * Any changes made to this function must also change X2APIC
725  * version of intr_exit.
726  */
727 static void
apix_intr_exit(int prev_ipl,int arg2)728 apix_intr_exit(int prev_ipl, int arg2)
729 {
730 	int cpuid = psm_get_cpu_id();
731 	apic_cpus_info_t *cpu_infop = &apic_cpus[cpuid];
732 	apix_impl_t *apixp = apixs[cpuid];
733 
734 	UNREFERENCED_1PARAMETER(arg2);
735 
736 	cpu_infop->aci_curipl = (uchar_t)prev_ipl;
737 	/* ISR above current pri could not be in progress */
738 	cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1;
739 
740 	if (apixp->x_obsoletes != NULL) {
741 		if (APIX_CPU_LOCK_HELD(cpuid))
742 			return;
743 
744 		APIX_ENTER_CPU_LOCK(cpuid);
745 		(void) apix_obsolete_vector(apixp->x_obsoletes);
746 		APIX_LEAVE_CPU_LOCK(cpuid);
747 	}
748 }
749 
750 /*
751  * The pcplusmp setspl code uses the TPR to mask all interrupts at or below the
752  * given ipl, but apix never uses the TPR and we never mask a subset of the
753  * interrupts. They are either all blocked by the IF flag or all can come in.
754  *
755  * For setspl, we mask all interrupts for XC_HI_PIL (15), otherwise, interrupts
756  * can come in if currently enabled by the IF flag. This table shows the state
757  * of the IF flag when we leave this function.
758  *
759  *    curr IF |	ipl == 15	ipl != 15
760  *    --------+---------------------------
761  *       0    |    0		    0
762  *       1    |    0		    1
763  */
764 static void
apix_setspl(int ipl)765 apix_setspl(int ipl)
766 {
767 	/*
768 	 * Interrupts at ipl above this cannot be in progress, so the following
769 	 * mask is ok.
770 	 */
771 	apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
772 
773 	if (ipl == XC_HI_PIL)
774 		cli();
775 }
776 
777 int
apix_addspl(int virtvec,int ipl,int min_ipl,int max_ipl)778 apix_addspl(int virtvec, int ipl, int min_ipl, int max_ipl)
779 {
780 	uint32_t cpuid = APIX_VIRTVEC_CPU(virtvec);
781 	uchar_t vector = (uchar_t)APIX_VIRTVEC_VECTOR(virtvec);
782 	apix_vector_t *vecp = xv_vector(cpuid, vector);
783 
784 	UNREFERENCED_3PARAMETER(ipl, min_ipl, max_ipl);
785 	ASSERT(vecp != NULL && LOCK_HELD(&apix_lock));
786 
787 	if (vecp->v_type == APIX_TYPE_FIXED)
788 		apix_intx_set_shared(vecp->v_inum, 1);
789 
790 	/* There are more interrupts, so it's already been enabled */
791 	if (vecp->v_share > 1)
792 		return (PSM_SUCCESS);
793 
794 	/* return if it is not hardware interrupt */
795 	if (vecp->v_type == APIX_TYPE_IPI)
796 		return (PSM_SUCCESS);
797 
798 	/*
799 	 * if apix_picinit() has not been called yet, just return.
800 	 * At the end of apic_picinit(), we will call setup_io_intr().
801 	 */
802 	if (!apic_picinit_called)
803 		return (PSM_SUCCESS);
804 
805 	(void) apix_setup_io_intr(vecp);
806 
807 	return (PSM_SUCCESS);
808 }
809 
810 int
apix_delspl(int virtvec,int ipl,int min_ipl,int max_ipl)811 apix_delspl(int virtvec, int ipl, int min_ipl, int max_ipl)
812 {
813 	uint32_t cpuid = APIX_VIRTVEC_CPU(virtvec);
814 	uchar_t vector = (uchar_t)APIX_VIRTVEC_VECTOR(virtvec);
815 	apix_vector_t *vecp = xv_vector(cpuid, vector);
816 
817 	UNREFERENCED_3PARAMETER(ipl, min_ipl, max_ipl);
818 	ASSERT(vecp != NULL && LOCK_HELD(&apix_lock));
819 
820 	if (vecp->v_type == APIX_TYPE_FIXED)
821 		apix_intx_set_shared(vecp->v_inum, -1);
822 
823 	/* There are more interrupts */
824 	if (vecp->v_share > 1)
825 		return (PSM_SUCCESS);
826 
827 	/* return if it is not hardware interrupt */
828 	if (vecp->v_type == APIX_TYPE_IPI)
829 		return (PSM_SUCCESS);
830 
831 	if (!apic_picinit_called) {
832 		cmn_err(CE_WARN, "apix: delete 0x%x before apic init",
833 		    virtvec);
834 		return (PSM_SUCCESS);
835 	}
836 
837 	apix_disable_vector(vecp);
838 
839 	return (PSM_SUCCESS);
840 }
841 
842 /*
843  * Try and disable all interrupts. We just assign interrupts to other
844  * processors based on policy. If any were bound by user request, we
845  * let them continue and return failure. We do not bother to check
846  * for cache affinity while rebinding.
847  */
848 static int
apix_disable_intr(processorid_t cpun)849 apix_disable_intr(processorid_t cpun)
850 {
851 	apix_impl_t *apixp = apixs[cpun];
852 	apix_vector_t *vecp, *newp;
853 	int bindcpu, i, hardbound = 0, errbound = 0, ret, loop, type;
854 
855 	lock_set(&apix_lock);
856 
857 	apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
858 	apic_cpus[cpun].aci_curipl = 0;
859 
860 	/* if this is for SUSPEND operation, skip rebinding */
861 	if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) {
862 		for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
863 			vecp = apixp->x_vectbl[i];
864 			if (!IS_VECT_ENABLED(vecp))
865 				continue;
866 
867 			apix_disable_vector(vecp);
868 		}
869 		lock_clear(&apix_lock);
870 		return (PSM_SUCCESS);
871 	}
872 
873 	for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
874 		vecp = apixp->x_vectbl[i];
875 		if (!IS_VECT_ENABLED(vecp))
876 			continue;
877 
878 		if (vecp->v_flags & APIX_VECT_USER_BOUND) {
879 			hardbound++;
880 			continue;
881 		}
882 		type = vecp->v_type;
883 
884 		/*
885 		 * If there are bound interrupts on this cpu, then
886 		 * rebind them to other processors.
887 		 */
888 		loop = 0;
889 		do {
890 			bindcpu = apic_find_cpu(APIC_CPU_INTR_ENABLE);
891 
892 			if (type != APIX_TYPE_MSI)
893 				newp = apix_set_cpu(vecp, bindcpu, &ret);
894 			else
895 				newp = apix_grp_set_cpu(vecp, bindcpu, &ret);
896 		} while ((newp == NULL) && (loop++ < apic_nproc));
897 
898 		if (loop >= apic_nproc) {
899 			errbound++;
900 			cmn_err(CE_WARN, "apix: failed to rebind vector %x/%x",
901 			    vecp->v_cpuid, vecp->v_vector);
902 		}
903 	}
904 
905 	lock_clear(&apix_lock);
906 
907 	if (hardbound || errbound) {
908 		cmn_err(CE_WARN, "Could not disable interrupts on %d"
909 		    "due to user bound interrupts or failed operation",
910 		    cpun);
911 		return (PSM_FAILURE);
912 	}
913 
914 	return (PSM_SUCCESS);
915 }
916 
917 /*
918  * Bind interrupts to specified CPU
919  */
920 static void
apix_enable_intr(processorid_t cpun)921 apix_enable_intr(processorid_t cpun)
922 {
923 	apix_vector_t *vecp;
924 	int i, ret;
925 	processorid_t n;
926 
927 	lock_set(&apix_lock);
928 
929 	apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
930 
931 	/* interrupt enabling for system resume */
932 	if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) {
933 		for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
934 			vecp = xv_vector(cpun, i);
935 			if (!IS_VECT_ENABLED(vecp))
936 				continue;
937 
938 			apix_enable_vector(vecp);
939 		}
940 		apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
941 	}
942 
943 	for (n = 0; n < apic_nproc; n++) {
944 		if (!apic_cpu_in_range(n) || n == cpun ||
945 		    (apic_cpus[n].aci_status & APIC_CPU_INTR_ENABLE) == 0)
946 			continue;
947 
948 		for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
949 			vecp = xv_vector(n, i);
950 			if (!IS_VECT_ENABLED(vecp) ||
951 			    vecp->v_bound_cpuid != cpun)
952 				continue;
953 
954 			if (vecp->v_type != APIX_TYPE_MSI)
955 				(void) apix_set_cpu(vecp, cpun, &ret);
956 			else
957 				(void) apix_grp_set_cpu(vecp, cpun, &ret);
958 		}
959 	}
960 
961 	lock_clear(&apix_lock);
962 }
963 
964 /*
965  * Allocate vector for IPI
966  * type == -1 indicates it is an internal request. Do not change
967  * resv_vector for these requests.
968  */
969 static int
apix_get_ipivect(int ipl,int type)970 apix_get_ipivect(int ipl, int type)
971 {
972 	uchar_t vector;
973 
974 	if ((vector = apix_alloc_ipi(ipl)) > 0) {
975 		if (type != -1)
976 			apic_resv_vector[ipl] = vector;
977 		return (vector);
978 	}
979 	apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
980 	return (-1);	/* shouldn't happen */
981 }
982 
983 static int
apix_get_clkvect(int ipl)984 apix_get_clkvect(int ipl)
985 {
986 	int vector;
987 
988 	if ((vector = apix_get_ipivect(ipl, -1)) == -1)
989 		return (-1);
990 
991 	apic_clkvect = vector - APIC_BASE_VECT;
992 	APIC_VERBOSE(IPI, (CE_CONT, "apix: clock vector = %x\n",
993 	    apic_clkvect));
994 	return (vector);
995 }
996 
997 static int
apix_post_cpu_start()998 apix_post_cpu_start()
999 {
1000 	int cpun;
1001 	static int cpus_started = 1;
1002 
1003 	/* We know this CPU + BSP  started successfully. */
1004 	cpus_started++;
1005 
1006 	/*
1007 	 * On BSP we would have enabled X2APIC, if supported by processor,
1008 	 * in acpi_probe(), but on AP we do it here.
1009 	 *
1010 	 * We enable X2APIC mode only if BSP is running in X2APIC & the
1011 	 * local APIC mode of the current CPU is MMIO (xAPIC).
1012 	 */
1013 	if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() &&
1014 	    apic_local_mode() == LOCAL_APIC) {
1015 		apic_enable_x2apic();
1016 	}
1017 
1018 	/*
1019 	 * Switch back to x2apic IPI sending method for performance when target
1020 	 * CPU has entered x2apic mode.
1021 	 */
1022 	if (apic_mode == LOCAL_X2APIC) {
1023 		apic_switch_ipi_callback(B_FALSE);
1024 	}
1025 
1026 	splx(ipltospl(LOCK_LEVEL));
1027 	apix_init_intr();
1028 
1029 	/*
1030 	 * since some systems don't enable the internal cache on the non-boot
1031 	 * cpus, so we have to enable them here
1032 	 */
1033 	setcr0(getcr0() & ~(CR0_CD | CR0_NW));
1034 
1035 #ifdef	DEBUG
1036 	APIC_AV_PENDING_SET();
1037 #else
1038 	if (apic_mode == LOCAL_APIC)
1039 		APIC_AV_PENDING_SET();
1040 #endif	/* DEBUG */
1041 
1042 	/*
1043 	 * We may be booting, or resuming from suspend; aci_status will
1044 	 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
1045 	 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
1046 	 */
1047 	cpun = psm_get_cpu_id();
1048 	apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
1049 
1050 	apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
1051 
1052 	return (PSM_SUCCESS);
1053 }
1054 
1055 /*
1056  * If this module needs a periodic handler for the interrupt distribution, it
1057  * can be added here. The argument to the periodic handler is not currently
1058  * used, but is reserved for future.
1059  */
1060 static void
apix_post_cyclic_setup(void * arg)1061 apix_post_cyclic_setup(void *arg)
1062 {
1063 	UNREFERENCED_1PARAMETER(arg);
1064 
1065 	cyc_handler_t cyh;
1066 	cyc_time_t cyt;
1067 
1068 	/* cpu_lock is held */
1069 	/* set up a periodic handler for intr redistribution */
1070 
1071 	/*
1072 	 * In peridoc mode intr redistribution processing is done in
1073 	 * apic_intr_enter during clk intr processing
1074 	 */
1075 	if (!apic_oneshot)
1076 		return;
1077 
1078 	/*
1079 	 * Register a periodical handler for the redistribution processing.
1080 	 * Though we would generally prefer to use the DDI interface for
1081 	 * periodic handler invocation, ddi_periodic_add(9F), we are
1082 	 * unfortunately already holding cpu_lock, which ddi_periodic_add will
1083 	 * attempt to take for us.  Thus, we add our own cyclic directly:
1084 	 */
1085 	cyh.cyh_func = (void (*)(void *))apix_redistribute_compute;
1086 	cyh.cyh_arg = NULL;
1087 	cyh.cyh_level = CY_LOW_LEVEL;
1088 
1089 	cyt.cyt_when = 0;
1090 	cyt.cyt_interval = apic_redistribute_sample_interval;
1091 
1092 	apic_cyclic_id = cyclic_add(&cyh, &cyt);
1093 }
1094 
1095 /*
1096  * Called the first time we enable x2apic mode on this cpu.
1097  * Update some of the function pointers to use x2apic routines.
1098  */
1099 void
x2apic_update_psm()1100 x2apic_update_psm()
1101 {
1102 	struct psm_ops *pops = &apix_ops;
1103 
1104 	ASSERT(pops != NULL);
1105 
1106 	/*
1107 	 * The pcplusmp module's version of x2apic_update_psm makes additional
1108 	 * changes that we do not have to make here. It needs to make those
1109 	 * changes because pcplusmp relies on the TPR register and the means of
1110 	 * addressing that changes when using the local apic versus the x2apic.
1111 	 * It's also worth noting that the apix driver specific function end up
1112 	 * being apix_foo as opposed to apic_foo and x2apic_foo.
1113 	 */
1114 	pops->psm_send_ipi = x2apic_send_ipi;
1115 
1116 	send_dirintf = pops->psm_send_ipi;
1117 
1118 	apic_mode = LOCAL_X2APIC;
1119 	apic_change_ops();
1120 }
1121 
1122 /*
1123  * This function provides external interface to the nexus for all
1124  * functionalities related to the new DDI interrupt framework.
1125  *
1126  * Input:
1127  * dip     - pointer to the dev_info structure of the requested device
1128  * hdlp    - pointer to the internal interrupt handle structure for the
1129  *	     requested interrupt
1130  * intr_op - opcode for this call
1131  * result  - pointer to the integer that will hold the result to be
1132  *	     passed back if return value is PSM_SUCCESS
1133  *
1134  * Output:
1135  * return value is either PSM_SUCCESS or PSM_FAILURE
1136  */
1137 static int
apix_intr_ops(dev_info_t * dip,ddi_intr_handle_impl_t * hdlp,psm_intr_op_t intr_op,int * result)1138 apix_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp,
1139     psm_intr_op_t intr_op, int *result)
1140 {
1141 	int		cap;
1142 	apix_vector_t	*vecp, *newvecp;
1143 	struct intrspec *ispec, intr_spec;
1144 	processorid_t target;
1145 
1146 	ispec = &intr_spec;
1147 	ispec->intrspec_pri = hdlp->ih_pri;
1148 	ispec->intrspec_vec = hdlp->ih_inum;
1149 	ispec->intrspec_func = hdlp->ih_cb_func;
1150 
1151 	switch (intr_op) {
1152 	case PSM_INTR_OP_ALLOC_VECTORS:
1153 		switch (hdlp->ih_type) {
1154 		case DDI_INTR_TYPE_MSI:
1155 			/* allocate MSI vectors */
1156 			*result = apix_alloc_msi(dip, hdlp->ih_inum,
1157 			    hdlp->ih_scratch1,
1158 			    (int)(uintptr_t)hdlp->ih_scratch2);
1159 			break;
1160 		case DDI_INTR_TYPE_MSIX:
1161 			/* allocate MSI-X vectors */
1162 			*result = apix_alloc_msix(dip, hdlp->ih_inum,
1163 			    hdlp->ih_scratch1,
1164 			    (int)(uintptr_t)hdlp->ih_scratch2);
1165 			break;
1166 		case DDI_INTR_TYPE_FIXED:
1167 			/* allocate or share vector for fixed */
1168 			if ((ihdl_plat_t *)hdlp->ih_private == NULL) {
1169 				return (PSM_FAILURE);
1170 			}
1171 			ispec = ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp;
1172 			*result = apix_intx_alloc_vector(dip, hdlp->ih_inum,
1173 			    ispec);
1174 			break;
1175 		default:
1176 			return (PSM_FAILURE);
1177 		}
1178 		break;
1179 	case PSM_INTR_OP_FREE_VECTORS:
1180 		apix_free_vectors(dip, hdlp->ih_inum, hdlp->ih_scratch1,
1181 		    hdlp->ih_type);
1182 		break;
1183 	case PSM_INTR_OP_XLATE_VECTOR:
1184 		/*
1185 		 * Vectors are allocated by ALLOC and freed by FREE.
1186 		 * XLATE finds and returns APIX_VIRTVEC_VECTOR(cpu, vector).
1187 		 */
1188 		*result = APIX_INVALID_VECT;
1189 		vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1190 		if (vecp != NULL) {
1191 			*result = APIX_VIRTVECTOR(vecp->v_cpuid,
1192 			    vecp->v_vector);
1193 			break;
1194 		}
1195 
1196 		/*
1197 		 * No vector to device mapping exists. If this is FIXED type
1198 		 * then check if this IRQ is already mapped for another device
1199 		 * then return the vector number for it (i.e. shared IRQ case).
1200 		 * Otherwise, return PSM_FAILURE.
1201 		 */
1202 		if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) {
1203 			vecp = apix_intx_xlate_vector(dip, hdlp->ih_inum,
1204 			    ispec);
1205 			*result = (vecp == NULL) ? APIX_INVALID_VECT :
1206 			    APIX_VIRTVECTOR(vecp->v_cpuid, vecp->v_vector);
1207 		}
1208 		if (*result == APIX_INVALID_VECT)
1209 			return (PSM_FAILURE);
1210 		break;
1211 	case PSM_INTR_OP_GET_PENDING:
1212 		vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1213 		if (vecp == NULL)
1214 			return (PSM_FAILURE);
1215 
1216 		*result = apix_get_pending(vecp);
1217 		break;
1218 	case PSM_INTR_OP_CLEAR_MASK:
1219 		if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
1220 			return (PSM_FAILURE);
1221 
1222 		vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1223 		if (vecp == NULL)
1224 			return (PSM_FAILURE);
1225 
1226 		apix_intx_clear_mask(vecp->v_inum);
1227 		break;
1228 	case PSM_INTR_OP_SET_MASK:
1229 		if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
1230 			return (PSM_FAILURE);
1231 
1232 		vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1233 		if (vecp == NULL)
1234 			return (PSM_FAILURE);
1235 
1236 		apix_intx_set_mask(vecp->v_inum);
1237 		break;
1238 	case PSM_INTR_OP_GET_SHARED:
1239 		if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
1240 			return (PSM_FAILURE);
1241 
1242 		vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1243 		if (vecp == NULL)
1244 			return (PSM_FAILURE);
1245 
1246 		*result = apix_intx_get_shared(vecp->v_inum);
1247 		break;
1248 	case PSM_INTR_OP_SET_PRI:
1249 		/*
1250 		 * Called prior to adding the interrupt handler or when
1251 		 * an interrupt handler is unassigned.
1252 		 */
1253 		if (hdlp->ih_type == DDI_INTR_TYPE_FIXED)
1254 			return (PSM_SUCCESS);
1255 
1256 		if (apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type) == NULL)
1257 			return (PSM_FAILURE);
1258 
1259 		break;
1260 	case PSM_INTR_OP_SET_CPU:
1261 	case PSM_INTR_OP_GRP_SET_CPU:
1262 		/*
1263 		 * The interrupt handle given here has been allocated
1264 		 * specifically for this command, and ih_private carries
1265 		 * a CPU value.
1266 		 */
1267 		*result = EINVAL;
1268 		target = (int)(intptr_t)hdlp->ih_private;
1269 		if (!apic_cpu_in_range(target)) {
1270 			DDI_INTR_IMPLDBG((CE_WARN,
1271 			    "[grp_]set_cpu: cpu out of range: %d\n", target));
1272 			return (PSM_FAILURE);
1273 		}
1274 
1275 		lock_set(&apix_lock);
1276 
1277 		vecp = apix_get_req_vector(hdlp, hdlp->ih_flags);
1278 		if (!IS_VECT_ENABLED(vecp)) {
1279 			DDI_INTR_IMPLDBG((CE_WARN,
1280 			    "[grp]_set_cpu: invalid vector 0x%x\n",
1281 			    hdlp->ih_vector));
1282 			lock_clear(&apix_lock);
1283 			return (PSM_FAILURE);
1284 		}
1285 
1286 		*result = 0;
1287 
1288 		if (intr_op == PSM_INTR_OP_SET_CPU)
1289 			newvecp = apix_set_cpu(vecp, target, result);
1290 		else
1291 			newvecp = apix_grp_set_cpu(vecp, target, result);
1292 
1293 		lock_clear(&apix_lock);
1294 
1295 		if (newvecp == NULL) {
1296 			*result = EIO;
1297 			return (PSM_FAILURE);
1298 		}
1299 		newvecp->v_bound_cpuid = target;
1300 		hdlp->ih_vector = APIX_VIRTVECTOR(newvecp->v_cpuid,
1301 		    newvecp->v_vector);
1302 		break;
1303 
1304 	case PSM_INTR_OP_GET_INTR:
1305 		/*
1306 		 * The interrupt handle given here has been allocated
1307 		 * specifically for this command, and ih_private carries
1308 		 * a pointer to a apic_get_intr_t.
1309 		 */
1310 		if (apix_get_intr_info(hdlp, hdlp->ih_private) != PSM_SUCCESS)
1311 			return (PSM_FAILURE);
1312 		break;
1313 
1314 	case PSM_INTR_OP_CHECK_MSI:
1315 		/*
1316 		 * Check MSI/X is supported or not at APIC level and
1317 		 * masked off the MSI/X bits in hdlp->ih_type if not
1318 		 * supported before return.  If MSI/X is supported,
1319 		 * leave the ih_type unchanged and return.
1320 		 *
1321 		 * hdlp->ih_type passed in from the nexus has all the
1322 		 * interrupt types supported by the device.
1323 		 */
1324 		if (apic_support_msi == 0) {	/* uninitialized */
1325 			/*
1326 			 * if apic_support_msi is not set, call
1327 			 * apic_check_msi_support() to check whether msi
1328 			 * is supported first
1329 			 */
1330 			if (apic_check_msi_support() == PSM_SUCCESS)
1331 				apic_support_msi = 1;	/* supported */
1332 			else
1333 				apic_support_msi = -1;	/* not-supported */
1334 		}
1335 		if (apic_support_msi == 1) {
1336 			if (apic_msix_enable)
1337 				*result = hdlp->ih_type;
1338 			else
1339 				*result = hdlp->ih_type & ~DDI_INTR_TYPE_MSIX;
1340 		} else
1341 			*result = hdlp->ih_type & ~(DDI_INTR_TYPE_MSI |
1342 			    DDI_INTR_TYPE_MSIX);
1343 		break;
1344 	case PSM_INTR_OP_GET_CAP:
1345 		cap = DDI_INTR_FLAG_PENDING;
1346 		if (hdlp->ih_type == DDI_INTR_TYPE_FIXED)
1347 			cap |= DDI_INTR_FLAG_MASKABLE;
1348 		*result = cap;
1349 		break;
1350 	case PSM_INTR_OP_APIC_TYPE:
1351 		((apic_get_type_t *)(hdlp->ih_private))->avgi_type =
1352 		    apix_get_apic_type();
1353 		((apic_get_type_t *)(hdlp->ih_private))->avgi_num_intr =
1354 		    APIX_IPI_MIN;
1355 		((apic_get_type_t *)(hdlp->ih_private))->avgi_num_cpu =
1356 		    apic_nproc;
1357 		hdlp->ih_ver = apic_get_apic_version();
1358 		break;
1359 	case PSM_INTR_OP_SET_CAP:
1360 	default:
1361 		return (PSM_FAILURE);
1362 	}
1363 
1364 	return (PSM_SUCCESS);
1365 }
1366 
1367 static void
apix_cleanup_busy(void)1368 apix_cleanup_busy(void)
1369 {
1370 	int i, j;
1371 	apix_vector_t *vecp;
1372 
1373 	for (i = 0; i < apic_nproc; i++) {
1374 		if (!apic_cpu_in_range(i))
1375 			continue;
1376 		apic_cpus[i].aci_busy = 0;
1377 		for (j = APIX_AVINTR_MIN; j < APIX_AVINTR_MAX; j++) {
1378 			if ((vecp = xv_vector(i, j)) != NULL)
1379 				vecp->v_busy = 0;
1380 		}
1381 	}
1382 }
1383 
1384 static void
apix_redistribute_compute(void)1385 apix_redistribute_compute(void)
1386 {
1387 	int	i, j, max_busy;
1388 
1389 	if (!apic_enable_dynamic_migration)
1390 		return;
1391 
1392 	if (++apic_nticks == apic_sample_factor_redistribution) {
1393 		/*
1394 		 * Time to call apic_intr_redistribute().
1395 		 * reset apic_nticks. This will cause max_busy
1396 		 * to be calculated below and if it is more than
1397 		 * apic_int_busy, we will do the whole thing
1398 		 */
1399 		apic_nticks = 0;
1400 	}
1401 	max_busy = 0;
1402 	for (i = 0; i < apic_nproc; i++) {
1403 		if (!apic_cpu_in_range(i))
1404 			continue;
1405 		/*
1406 		 * Check if curipl is non zero & if ISR is in
1407 		 * progress
1408 		 */
1409 		if (((j = apic_cpus[i].aci_curipl) != 0) &&
1410 		    (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
1411 
1412 			int	vect;
1413 			apic_cpus[i].aci_busy++;
1414 			vect = apic_cpus[i].aci_current[j];
1415 			apixs[i]->x_vectbl[vect]->v_busy++;
1416 		}
1417 
1418 		if (!apic_nticks &&
1419 		    (apic_cpus[i].aci_busy > max_busy))
1420 			max_busy = apic_cpus[i].aci_busy;
1421 	}
1422 	if (!apic_nticks) {
1423 		if (max_busy > apic_int_busy_mark) {
1424 		/*
1425 		 * We could make the following check be
1426 		 * skipped > 1 in which case, we get a
1427 		 * redistribution at half the busy mark (due to
1428 		 * double interval). Need to be able to collect
1429 		 * more empirical data to decide if that is a
1430 		 * good strategy. Punt for now.
1431 		 */
1432 			apix_cleanup_busy();
1433 			apic_skipped_redistribute = 0;
1434 		} else
1435 			apic_skipped_redistribute++;
1436 	}
1437 }
1438 
1439 /*
1440  * intr_ops() service routines
1441  */
1442 
1443 static int
apix_get_pending(apix_vector_t * vecp)1444 apix_get_pending(apix_vector_t *vecp)
1445 {
1446 	int bit, index, irr, pending;
1447 
1448 	/* need to get on the bound cpu */
1449 	mutex_enter(&cpu_lock);
1450 	affinity_set(vecp->v_cpuid);
1451 
1452 	index = vecp->v_vector / 32;
1453 	bit = vecp->v_vector % 32;
1454 	irr = apic_reg_ops->apic_read(APIC_IRR_REG + index);
1455 
1456 	affinity_clear();
1457 	mutex_exit(&cpu_lock);
1458 
1459 	pending = (irr & (1 << bit)) ? 1 : 0;
1460 	if (!pending && vecp->v_type == APIX_TYPE_FIXED)
1461 		pending = apix_intx_get_pending(vecp->v_inum);
1462 
1463 	return (pending);
1464 }
1465 
1466 static apix_vector_t *
apix_get_req_vector(ddi_intr_handle_impl_t * hdlp,ushort_t flags)1467 apix_get_req_vector(ddi_intr_handle_impl_t *hdlp, ushort_t flags)
1468 {
1469 	apix_vector_t *vecp;
1470 	processorid_t cpuid;
1471 	int32_t virt_vec = 0;
1472 
1473 	switch (flags & PSMGI_INTRBY_FLAGS) {
1474 	case PSMGI_INTRBY_IRQ:
1475 		return (apix_intx_get_vector(hdlp->ih_vector));
1476 	case PSMGI_INTRBY_VEC:
1477 		virt_vec = (virt_vec == 0) ? hdlp->ih_vector : virt_vec;
1478 
1479 		cpuid = APIX_VIRTVEC_CPU(virt_vec);
1480 		if (!apic_cpu_in_range(cpuid))
1481 			return (NULL);
1482 
1483 		vecp = xv_vector(cpuid, APIX_VIRTVEC_VECTOR(virt_vec));
1484 		break;
1485 	case PSMGI_INTRBY_DEFAULT:
1486 		vecp = apix_get_dev_map(hdlp->ih_dip, hdlp->ih_inum,
1487 		    hdlp->ih_type);
1488 		break;
1489 	default:
1490 		return (NULL);
1491 	}
1492 
1493 	return (vecp);
1494 }
1495 
1496 static int
apix_get_intr_info(ddi_intr_handle_impl_t * hdlp,apic_get_intr_t * intr_params_p)1497 apix_get_intr_info(ddi_intr_handle_impl_t *hdlp,
1498     apic_get_intr_t *intr_params_p)
1499 {
1500 	apix_vector_t *vecp;
1501 	struct autovec *av_dev;
1502 	int i;
1503 
1504 	vecp = apix_get_req_vector(hdlp, intr_params_p->avgi_req_flags);
1505 	if (IS_VECT_FREE(vecp)) {
1506 		intr_params_p->avgi_num_devs = 0;
1507 		intr_params_p->avgi_cpu_id = 0;
1508 		intr_params_p->avgi_req_flags = 0;
1509 		return (PSM_SUCCESS);
1510 	}
1511 
1512 	if (intr_params_p->avgi_req_flags & PSMGI_REQ_CPUID) {
1513 		intr_params_p->avgi_cpu_id = vecp->v_cpuid;
1514 
1515 		/* Return user bound info for intrd. */
1516 		if (intr_params_p->avgi_cpu_id & IRQ_USER_BOUND) {
1517 			intr_params_p->avgi_cpu_id &= ~IRQ_USER_BOUND;
1518 			intr_params_p->avgi_cpu_id |= PSMGI_CPU_USER_BOUND;
1519 		}
1520 	}
1521 
1522 	if (intr_params_p->avgi_req_flags & PSMGI_REQ_VECTOR)
1523 		intr_params_p->avgi_vector = vecp->v_vector;
1524 
1525 	if (intr_params_p->avgi_req_flags &
1526 	    (PSMGI_REQ_NUM_DEVS | PSMGI_REQ_GET_DEVS))
1527 		/* Get number of devices from apic_irq table shared field. */
1528 		intr_params_p->avgi_num_devs = vecp->v_share;
1529 
1530 	if (intr_params_p->avgi_req_flags &  PSMGI_REQ_GET_DEVS) {
1531 
1532 		intr_params_p->avgi_req_flags  |= PSMGI_REQ_NUM_DEVS;
1533 
1534 		/* Some devices have NULL dip.  Don't count these. */
1535 		if (intr_params_p->avgi_num_devs > 0) {
1536 			for (i = 0, av_dev = vecp->v_autovect; av_dev;
1537 			    av_dev = av_dev->av_link) {
1538 				if (av_dev->av_vector && av_dev->av_dip)
1539 					i++;
1540 			}
1541 			intr_params_p->avgi_num_devs =
1542 			    (uint8_t)MIN(intr_params_p->avgi_num_devs, i);
1543 		}
1544 
1545 		/* There are no viable dips to return. */
1546 		if (intr_params_p->avgi_num_devs == 0) {
1547 			intr_params_p->avgi_dip_list = NULL;
1548 
1549 		} else {	/* Return list of dips */
1550 
1551 			/* Allocate space in array for that number of devs. */
1552 			intr_params_p->avgi_dip_list = kmem_zalloc(
1553 			    intr_params_p->avgi_num_devs *
1554 			    sizeof (dev_info_t *),
1555 			    KM_NOSLEEP);
1556 			if (intr_params_p->avgi_dip_list == NULL) {
1557 				DDI_INTR_IMPLDBG((CE_WARN,
1558 				    "apix_get_vector_intr_info: no memory"));
1559 				return (PSM_FAILURE);
1560 			}
1561 
1562 			/*
1563 			 * Loop through the device list of the autovec table
1564 			 * filling in the dip array.
1565 			 *
1566 			 * Note that the autovect table may have some special
1567 			 * entries which contain NULL dips.  These will be
1568 			 * ignored.
1569 			 */
1570 			for (i = 0, av_dev = vecp->v_autovect; av_dev;
1571 			    av_dev = av_dev->av_link) {
1572 				if (av_dev->av_vector && av_dev->av_dip)
1573 					intr_params_p->avgi_dip_list[i++] =
1574 					    av_dev->av_dip;
1575 			}
1576 		}
1577 	}
1578 
1579 	return (PSM_SUCCESS);
1580 }
1581 
1582 static char *
apix_get_apic_type(void)1583 apix_get_apic_type(void)
1584 {
1585 	return (apix_psm_info.p_mach_idstring);
1586 }
1587 
1588 apix_vector_t *
apix_set_cpu(apix_vector_t * vecp,int new_cpu,int * result)1589 apix_set_cpu(apix_vector_t *vecp, int new_cpu, int *result)
1590 {
1591 	apix_vector_t *newp = NULL;
1592 	dev_info_t *dip;
1593 	int inum, cap_ptr;
1594 	ddi_acc_handle_t handle;
1595 	ddi_intr_msix_t *msix_p = NULL;
1596 	ushort_t msix_ctrl;
1597 	uintptr_t off;
1598 	uint32_t mask;
1599 
1600 	ASSERT(LOCK_HELD(&apix_lock));
1601 	*result = ENXIO;
1602 
1603 	/* Fail if this is an MSI intr and is part of a group. */
1604 	if (vecp->v_type == APIX_TYPE_MSI) {
1605 		if (i_ddi_intr_get_current_nintrs(APIX_GET_DIP(vecp)) > 1)
1606 			return (NULL);
1607 		else
1608 			return (apix_grp_set_cpu(vecp, new_cpu, result));
1609 	}
1610 
1611 	/*
1612 	 * Mask MSI-X. It's unmasked when MSI-X gets enabled.
1613 	 */
1614 	if (vecp->v_type == APIX_TYPE_MSIX && IS_VECT_ENABLED(vecp)) {
1615 		if ((dip = APIX_GET_DIP(vecp)) == NULL)
1616 			return (NULL);
1617 		inum = vecp->v_devp->dv_inum;
1618 
1619 		handle = i_ddi_get_pci_config_handle(dip);
1620 		cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip);
1621 		msix_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSIX_CTRL);
1622 		if ((msix_ctrl & PCI_MSIX_FUNCTION_MASK) == 0) {
1623 			/*
1624 			 * Function is not masked, then mask "inum"th
1625 			 * entry in the MSI-X table
1626 			 */
1627 			msix_p = i_ddi_get_msix(dip);
1628 			off = (uintptr_t)msix_p->msix_tbl_addr + (inum *
1629 			    PCI_MSIX_VECTOR_SIZE) + PCI_MSIX_VECTOR_CTRL_OFFSET;
1630 			mask = ddi_get32(msix_p->msix_tbl_hdl, (uint32_t *)off);
1631 			ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off,
1632 			    mask | 1);
1633 		}
1634 	}
1635 
1636 	*result = 0;
1637 	if ((newp = apix_rebind(vecp, new_cpu, 1)) == NULL)
1638 		*result = EIO;
1639 
1640 	/* Restore mask bit */
1641 	if (msix_p != NULL)
1642 		ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off, mask);
1643 
1644 	return (newp);
1645 }
1646 
1647 /*
1648  * Set cpu for MSIs
1649  */
1650 apix_vector_t *
apix_grp_set_cpu(apix_vector_t * vecp,int new_cpu,int * result)1651 apix_grp_set_cpu(apix_vector_t *vecp, int new_cpu, int *result)
1652 {
1653 	apix_vector_t *newp, *vp;
1654 	uint32_t orig_cpu = vecp->v_cpuid;
1655 	int orig_vect = vecp->v_vector;
1656 	int i, num_vectors, cap_ptr, msi_mask_off;
1657 	uint32_t msi_pvm;
1658 	ushort_t msi_ctrl;
1659 	ddi_acc_handle_t handle;
1660 	dev_info_t *dip;
1661 
1662 	APIC_VERBOSE(INTR, (CE_CONT, "apix_grp_set_cpu: oldcpu: %x, vector: %x,"
1663 	    " newcpu:%x\n", vecp->v_cpuid, vecp->v_vector, new_cpu));
1664 
1665 	ASSERT(LOCK_HELD(&apix_lock));
1666 
1667 	*result = ENXIO;
1668 
1669 	if (vecp->v_type != APIX_TYPE_MSI) {
1670 		DDI_INTR_IMPLDBG((CE_WARN, "set_grp: intr not MSI\n"));
1671 		return (NULL);
1672 	}
1673 
1674 	if ((dip = APIX_GET_DIP(vecp)) == NULL)
1675 		return (NULL);
1676 
1677 	num_vectors = i_ddi_intr_get_current_nintrs(dip);
1678 	if ((num_vectors < 1) || ((num_vectors - 1) & orig_vect)) {
1679 		APIC_VERBOSE(INTR, (CE_WARN,
1680 		    "set_grp: base vec not part of a grp or not aligned: "
1681 		    "vec:0x%x, num_vec:0x%x\n", orig_vect, num_vectors));
1682 		return (NULL);
1683 	}
1684 
1685 	if (vecp->v_inum != apix_get_min_dev_inum(dip, vecp->v_type))
1686 		return (NULL);
1687 
1688 	*result = EIO;
1689 	for (i = 1; i < num_vectors; i++) {
1690 		if ((vp = xv_vector(orig_cpu, orig_vect + i)) == NULL)
1691 			return (NULL);
1692 #ifdef DEBUG
1693 		/*
1694 		 * Sanity check: CPU and dip is the same for all entries.
1695 		 * May be called when first msi to be enabled, at this time
1696 		 * add_avintr() is not called for other msi
1697 		 */
1698 		if ((vp->v_share != 0) &&
1699 		    ((APIX_GET_DIP(vp) != dip) ||
1700 		    (vp->v_cpuid != vecp->v_cpuid))) {
1701 			APIC_VERBOSE(INTR, (CE_WARN,
1702 			    "set_grp: cpu or dip for vec 0x%x difft than for "
1703 			    "vec 0x%x\n", orig_vect, orig_vect + i));
1704 			APIC_VERBOSE(INTR, (CE_WARN,
1705 			    "  cpu: %d vs %d, dip: 0x%p vs 0x%p\n", orig_cpu,
1706 			    vp->v_cpuid, (void *)dip,
1707 			    (void *)APIX_GET_DIP(vp)));
1708 			return (NULL);
1709 		}
1710 #endif /* DEBUG */
1711 	}
1712 
1713 	cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip);
1714 	handle = i_ddi_get_pci_config_handle(dip);
1715 	msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL);
1716 
1717 	/* MSI Per vector masking is supported. */
1718 	if (msi_ctrl & PCI_MSI_PVM_MASK) {
1719 		if (msi_ctrl &  PCI_MSI_64BIT_MASK)
1720 			msi_mask_off = cap_ptr + PCI_MSI_64BIT_MASKBITS;
1721 		else
1722 			msi_mask_off = cap_ptr + PCI_MSI_32BIT_MASK;
1723 		msi_pvm = pci_config_get32(handle, msi_mask_off);
1724 		pci_config_put32(handle, msi_mask_off, (uint32_t)-1);
1725 		APIC_VERBOSE(INTR, (CE_CONT,
1726 		    "set_grp: pvm supported.  Mask set to 0x%x\n",
1727 		    pci_config_get32(handle, msi_mask_off)));
1728 	}
1729 
1730 	if ((newp = apix_rebind(vecp, new_cpu, num_vectors)) != NULL)
1731 		*result = 0;
1732 
1733 	/* Reenable vectors if per vector masking is supported. */
1734 	if (msi_ctrl & PCI_MSI_PVM_MASK) {
1735 		pci_config_put32(handle, msi_mask_off, msi_pvm);
1736 		APIC_VERBOSE(INTR, (CE_CONT,
1737 		    "set_grp: pvm supported.  Mask restored to 0x%x\n",
1738 		    pci_config_get32(handle, msi_mask_off)));
1739 	}
1740 
1741 	return (newp);
1742 }
1743 
1744 void
apix_intx_set_vector(int irqno,uint32_t cpuid,uchar_t vector)1745 apix_intx_set_vector(int irqno, uint32_t cpuid, uchar_t vector)
1746 {
1747 	apic_irq_t *irqp;
1748 
1749 	mutex_enter(&airq_mutex);
1750 	irqp = apic_irq_table[irqno];
1751 	irqp->airq_cpu = cpuid;
1752 	irqp->airq_vector = vector;
1753 	apic_record_rdt_entry(irqp, irqno);
1754 	mutex_exit(&airq_mutex);
1755 }
1756 
1757 apix_vector_t *
apix_intx_get_vector(int irqno)1758 apix_intx_get_vector(int irqno)
1759 {
1760 	apic_irq_t *irqp;
1761 	uint32_t cpuid;
1762 	uchar_t vector;
1763 
1764 	mutex_enter(&airq_mutex);
1765 	irqp = apic_irq_table[irqno & 0xff];
1766 	if (IS_IRQ_FREE(irqp) || (irqp->airq_cpu == IRQ_UNINIT)) {
1767 		mutex_exit(&airq_mutex);
1768 		return (NULL);
1769 	}
1770 	cpuid = irqp->airq_cpu;
1771 	vector = irqp->airq_vector;
1772 	mutex_exit(&airq_mutex);
1773 
1774 	return (xv_vector(cpuid, vector));
1775 }
1776 
1777 /*
1778  * Must called with interrupts disabled and apic_ioapic_lock held
1779  */
1780 void
apix_intx_enable(int irqno)1781 apix_intx_enable(int irqno)
1782 {
1783 	uchar_t ioapicindex, intin;
1784 	apic_irq_t *irqp = apic_irq_table[irqno];
1785 	ioapic_rdt_t irdt;
1786 	apic_cpus_info_t *cpu_infop;
1787 	apix_vector_t *vecp = xv_vector(irqp->airq_cpu, irqp->airq_vector);
1788 
1789 	ASSERT(LOCK_HELD(&apic_ioapic_lock) && !IS_IRQ_FREE(irqp));
1790 
1791 	ioapicindex = irqp->airq_ioapicindex;
1792 	intin = irqp->airq_intin_no;
1793 	cpu_infop =  &apic_cpus[irqp->airq_cpu];
1794 
1795 	irdt.ir_lo = AV_PDEST | AV_FIXED | irqp->airq_rdt_entry;
1796 	irdt.ir_hi = cpu_infop->aci_local_id;
1797 
1798 	apic_vt_ops->apic_intrmap_alloc_entry(&vecp->v_intrmap_private, NULL,
1799 	    vecp->v_type, 1, ioapicindex);
1800 	apic_vt_ops->apic_intrmap_map_entry(vecp->v_intrmap_private,
1801 	    (void *)&irdt, vecp->v_type, 1);
1802 	apic_vt_ops->apic_intrmap_record_rdt(vecp->v_intrmap_private, &irdt);
1803 
1804 	/* write RDT entry high dword - destination */
1805 	WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapicindex, intin,
1806 	    irdt.ir_hi);
1807 
1808 	/* Write the vector, trigger, and polarity portion of the RDT */
1809 	WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin, irdt.ir_lo);
1810 
1811 	vecp->v_state = APIX_STATE_ENABLED;
1812 
1813 	APIC_VERBOSE_IOAPIC((CE_CONT, "apix_intx_enable: ioapic 0x%x"
1814 	    " intin 0x%x rdt_low 0x%x rdt_high 0x%x\n",
1815 	    ioapicindex, intin, irdt.ir_lo, irdt.ir_hi));
1816 }
1817 
1818 /*
1819  * Must called with interrupts disabled and apic_ioapic_lock held
1820  */
1821 void
apix_intx_disable(int irqno)1822 apix_intx_disable(int irqno)
1823 {
1824 	apic_irq_t *irqp = apic_irq_table[irqno];
1825 	int ioapicindex, intin;
1826 
1827 	ASSERT(LOCK_HELD(&apic_ioapic_lock) && !IS_IRQ_FREE(irqp));
1828 	/*
1829 	 * The assumption here is that this is safe, even for
1830 	 * systems with IOAPICs that suffer from the hardware
1831 	 * erratum because all devices have been quiesced before
1832 	 * they unregister their interrupt handlers.  If that
1833 	 * assumption turns out to be false, this mask operation
1834 	 * can induce the same erratum result we're trying to
1835 	 * avoid.
1836 	 */
1837 	ioapicindex = irqp->airq_ioapicindex;
1838 	intin = irqp->airq_intin_no;
1839 	ioapic_write(ioapicindex, APIC_RDT_CMD + 2 * intin, AV_MASK);
1840 
1841 	APIC_VERBOSE_IOAPIC((CE_CONT, "apix_intx_disable: ioapic 0x%x"
1842 	    " intin 0x%x\n", ioapicindex, intin));
1843 }
1844 
1845 void
apix_intx_free(int irqno)1846 apix_intx_free(int irqno)
1847 {
1848 	apic_irq_t *irqp;
1849 
1850 	mutex_enter(&airq_mutex);
1851 	irqp = apic_irq_table[irqno];
1852 
1853 	if (IS_IRQ_FREE(irqp)) {
1854 		mutex_exit(&airq_mutex);
1855 		return;
1856 	}
1857 
1858 	irqp->airq_mps_intr_index = FREE_INDEX;
1859 	irqp->airq_cpu = IRQ_UNINIT;
1860 	irqp->airq_vector = APIX_INVALID_VECT;
1861 	mutex_exit(&airq_mutex);
1862 }
1863 
1864 #ifdef DEBUG
1865 int apix_intr_deliver_timeouts = 0;
1866 int apix_intr_rirr_timeouts = 0;
1867 int apix_intr_rirr_reset_failure = 0;
1868 #endif
1869 int apix_max_reps_irr_pending = 10;
1870 
1871 #define	GET_RDT_BITS(ioapic, intin, bits)	\
1872 	(READ_IOAPIC_RDT_ENTRY_LOW_DWORD((ioapic), (intin)) & (bits))
1873 #define	APIX_CHECK_IRR_DELAY	drv_usectohz(5000)
1874 
1875 int
apix_intx_rebind(int irqno,processorid_t cpuid,uchar_t vector)1876 apix_intx_rebind(int irqno, processorid_t cpuid, uchar_t vector)
1877 {
1878 	apic_irq_t *irqp = apic_irq_table[irqno];
1879 	ulong_t iflag;
1880 	int waited, ioapic_ix, intin_no, level, repeats, rdt_entry, masked;
1881 
1882 	ASSERT(irqp != NULL);
1883 
1884 	iflag = intr_clear();
1885 	lock_set(&apic_ioapic_lock);
1886 
1887 	ioapic_ix = irqp->airq_ioapicindex;
1888 	intin_no = irqp->airq_intin_no;
1889 	level = apic_level_intr[irqno];
1890 
1891 	/*
1892 	 * Wait for the delivery status bit to be cleared. This should
1893 	 * be a very small amount of time.
1894 	 */
1895 	repeats = 0;
1896 	do {
1897 		repeats++;
1898 
1899 		for (waited = 0; waited < apic_max_reps_clear_pending;
1900 		    waited++) {
1901 			if (GET_RDT_BITS(ioapic_ix, intin_no, AV_PENDING) == 0)
1902 				break;
1903 		}
1904 		if (!level)
1905 			break;
1906 
1907 		/*
1908 		 * Mask the RDT entry for level-triggered interrupts.
1909 		 */
1910 		irqp->airq_rdt_entry |= AV_MASK;
1911 		rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1912 		    intin_no);
1913 		if ((masked = (rdt_entry & AV_MASK)) == 0) {
1914 			/* Mask it */
1915 			WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no,
1916 			    AV_MASK | rdt_entry);
1917 		}
1918 
1919 		/*
1920 		 * If there was a race and an interrupt was injected
1921 		 * just before we masked, check for that case here.
1922 		 * Then, unmask the RDT entry and try again.  If we're
1923 		 * on our last try, don't unmask (because we want the
1924 		 * RDT entry to remain masked for the rest of the
1925 		 * function).
1926 		 */
1927 		rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1928 		    intin_no);
1929 		if ((masked == 0) && ((rdt_entry & AV_PENDING) != 0) &&
1930 		    (repeats < apic_max_reps_clear_pending)) {
1931 			/* Unmask it */
1932 			WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1933 			    intin_no, rdt_entry & ~AV_MASK);
1934 			irqp->airq_rdt_entry &= ~AV_MASK;
1935 		}
1936 	} while ((rdt_entry & AV_PENDING) &&
1937 	    (repeats < apic_max_reps_clear_pending));
1938 
1939 #ifdef DEBUG
1940 	if (GET_RDT_BITS(ioapic_ix, intin_no, AV_PENDING) != 0)
1941 		apix_intr_deliver_timeouts++;
1942 #endif
1943 
1944 	if (!level || !APIX_IS_MASK_RDT(apix_mul_ioapic_method))
1945 		goto done;
1946 
1947 	/*
1948 	 * wait for remote IRR to be cleared for level-triggered
1949 	 * interrupts
1950 	 */
1951 	repeats = 0;
1952 	do {
1953 		repeats++;
1954 
1955 		for (waited = 0; waited < apic_max_reps_clear_pending;
1956 		    waited++) {
1957 			if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR)
1958 			    == 0)
1959 				break;
1960 		}
1961 
1962 		if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) {
1963 			lock_clear(&apic_ioapic_lock);
1964 			intr_restore(iflag);
1965 
1966 			delay(APIX_CHECK_IRR_DELAY);
1967 
1968 			iflag = intr_clear();
1969 			lock_set(&apic_ioapic_lock);
1970 		}
1971 	} while (repeats < apix_max_reps_irr_pending);
1972 
1973 	if (repeats >= apix_max_reps_irr_pending) {
1974 #ifdef DEBUG
1975 		apix_intr_rirr_timeouts++;
1976 #endif
1977 
1978 		/*
1979 		 * If we waited and the Remote IRR bit is still not cleared,
1980 		 * AND if we've invoked the timeout APIC_REPROGRAM_MAX_TIMEOUTS
1981 		 * times for this interrupt, try the last-ditch workaround:
1982 		 */
1983 		if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) {
1984 			/*
1985 			 * Trying to clear the bit through normal
1986 			 * channels has failed.  So as a last-ditch
1987 			 * effort, try to set the trigger mode to
1988 			 * edge, then to level.  This has been
1989 			 * observed to work on many systems.
1990 			 */
1991 			WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1992 			    intin_no,
1993 			    READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1994 			    intin_no) & ~AV_LEVEL);
1995 			WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1996 			    intin_no,
1997 			    READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1998 			    intin_no) | AV_LEVEL);
1999 		}
2000 
2001 		if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) {
2002 #ifdef DEBUG
2003 			apix_intr_rirr_reset_failure++;
2004 #endif
2005 			lock_clear(&apic_ioapic_lock);
2006 			intr_restore(iflag);
2007 			prom_printf("apix: Remote IRR still "
2008 			    "not clear for IOAPIC %d intin %d.\n"
2009 			    "\tInterrupts to this pin may cease "
2010 			    "functioning.\n", ioapic_ix, intin_no);
2011 			return (1);	/* return failure */
2012 		}
2013 	}
2014 
2015 done:
2016 	/* change apic_irq_table */
2017 	lock_clear(&apic_ioapic_lock);
2018 	intr_restore(iflag);
2019 	apix_intx_set_vector(irqno, cpuid, vector);
2020 	iflag = intr_clear();
2021 	lock_set(&apic_ioapic_lock);
2022 
2023 	/* reprogramme IO-APIC RDT entry */
2024 	apix_intx_enable(irqno);
2025 
2026 	lock_clear(&apic_ioapic_lock);
2027 	intr_restore(iflag);
2028 
2029 	return (0);
2030 }
2031 
2032 static int
apix_intx_get_pending(int irqno)2033 apix_intx_get_pending(int irqno)
2034 {
2035 	apic_irq_t *irqp;
2036 	int intin, ioapicindex, pending;
2037 	ulong_t iflag;
2038 
2039 	mutex_enter(&airq_mutex);
2040 	irqp = apic_irq_table[irqno];
2041 	if (IS_IRQ_FREE(irqp)) {
2042 		mutex_exit(&airq_mutex);
2043 		return (0);
2044 	}
2045 
2046 	/* check IO-APIC delivery status */
2047 	intin = irqp->airq_intin_no;
2048 	ioapicindex = irqp->airq_ioapicindex;
2049 	mutex_exit(&airq_mutex);
2050 
2051 	iflag = intr_clear();
2052 	lock_set(&apic_ioapic_lock);
2053 
2054 	pending = (READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin) &
2055 	    AV_PENDING) ? 1 : 0;
2056 
2057 	lock_clear(&apic_ioapic_lock);
2058 	intr_restore(iflag);
2059 
2060 	return (pending);
2061 }
2062 
2063 /*
2064  * This function will mask the interrupt on the I/O APIC
2065  */
2066 static void
apix_intx_set_mask(int irqno)2067 apix_intx_set_mask(int irqno)
2068 {
2069 	int intin, ioapixindex, rdt_entry;
2070 	ulong_t iflag;
2071 	apic_irq_t *irqp;
2072 
2073 	mutex_enter(&airq_mutex);
2074 	irqp = apic_irq_table[irqno];
2075 
2076 	ASSERT(irqp->airq_mps_intr_index != FREE_INDEX);
2077 
2078 	intin = irqp->airq_intin_no;
2079 	ioapixindex = irqp->airq_ioapicindex;
2080 	mutex_exit(&airq_mutex);
2081 
2082 	iflag = intr_clear();
2083 	lock_set(&apic_ioapic_lock);
2084 
2085 	rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin);
2086 
2087 	/* clear mask */
2088 	WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin,
2089 	    (AV_MASK | rdt_entry));
2090 
2091 	lock_clear(&apic_ioapic_lock);
2092 	intr_restore(iflag);
2093 }
2094 
2095 /*
2096  * This function will clear the mask for the interrupt on the I/O APIC
2097  */
2098 static void
apix_intx_clear_mask(int irqno)2099 apix_intx_clear_mask(int irqno)
2100 {
2101 	int intin, ioapixindex, rdt_entry;
2102 	ulong_t iflag;
2103 	apic_irq_t *irqp;
2104 
2105 	mutex_enter(&airq_mutex);
2106 	irqp = apic_irq_table[irqno];
2107 
2108 	ASSERT(irqp->airq_mps_intr_index != FREE_INDEX);
2109 
2110 	intin = irqp->airq_intin_no;
2111 	ioapixindex = irqp->airq_ioapicindex;
2112 	mutex_exit(&airq_mutex);
2113 
2114 	iflag = intr_clear();
2115 	lock_set(&apic_ioapic_lock);
2116 
2117 	rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin);
2118 
2119 	/* clear mask */
2120 	WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin,
2121 	    ((~AV_MASK) & rdt_entry));
2122 
2123 	lock_clear(&apic_ioapic_lock);
2124 	intr_restore(iflag);
2125 }
2126 
2127 /*
2128  * For level-triggered interrupt, mask the IRQ line. Mask means
2129  * new interrupts will not be delivered. The interrupt already
2130  * accepted by a local APIC is not affected
2131  */
2132 void
apix_level_intr_pre_eoi(int irq)2133 apix_level_intr_pre_eoi(int irq)
2134 {
2135 	apic_irq_t *irqp = apic_irq_table[irq];
2136 	int apic_ix, intin_ix;
2137 
2138 	if (irqp == NULL)
2139 		return;
2140 
2141 	ASSERT(apic_level_intr[irq] == TRIGGER_MODE_LEVEL);
2142 
2143 	lock_set(&apic_ioapic_lock);
2144 
2145 	intin_ix = irqp->airq_intin_no;
2146 	apic_ix = irqp->airq_ioapicindex;
2147 
2148 	if (irqp->airq_cpu != CPU->cpu_id) {
2149 		if (!APIX_IS_MASK_RDT(apix_mul_ioapic_method))
2150 			ioapic_write_eoi(apic_ix, irqp->airq_vector);
2151 		lock_clear(&apic_ioapic_lock);
2152 		return;
2153 	}
2154 
2155 	if (apix_mul_ioapic_method == APIC_MUL_IOAPIC_IOXAPIC) {
2156 		/*
2157 		 * This is a IOxAPIC and there is EOI register:
2158 		 * 	Change the vector to reserved unused vector, so that
2159 		 * 	the EOI	from Local APIC won't clear the Remote IRR for
2160 		 * 	this level trigger interrupt. Instead, we'll manually
2161 		 * 	clear it in apix_post_hardint() after ISR handling.
2162 		 */
2163 		WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix,
2164 		    (irqp->airq_rdt_entry & (~0xff)) | APIX_RESV_VECTOR);
2165 	} else {
2166 		WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix,
2167 		    AV_MASK | irqp->airq_rdt_entry);
2168 	}
2169 
2170 	lock_clear(&apic_ioapic_lock);
2171 }
2172 
2173 /*
2174  * For level-triggered interrupt, unmask the IRQ line
2175  * or restore the original vector number.
2176  */
2177 void
apix_level_intr_post_dispatch(int irq)2178 apix_level_intr_post_dispatch(int irq)
2179 {
2180 	apic_irq_t *irqp = apic_irq_table[irq];
2181 	int apic_ix, intin_ix;
2182 
2183 	if (irqp == NULL)
2184 		return;
2185 
2186 	lock_set(&apic_ioapic_lock);
2187 
2188 	intin_ix = irqp->airq_intin_no;
2189 	apic_ix = irqp->airq_ioapicindex;
2190 
2191 	if (APIX_IS_DIRECTED_EOI(apix_mul_ioapic_method)) {
2192 		/*
2193 		 * Already sent EOI back to Local APIC.
2194 		 * Send EOI to IO-APIC
2195 		 */
2196 		ioapic_write_eoi(apic_ix, irqp->airq_vector);
2197 	} else {
2198 		/* clear the mask or restore the vector */
2199 		WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix,
2200 		    irqp->airq_rdt_entry);
2201 
2202 		/* send EOI to IOxAPIC */
2203 		if (apix_mul_ioapic_method == APIC_MUL_IOAPIC_IOXAPIC)
2204 			ioapic_write_eoi(apic_ix, irqp->airq_vector);
2205 	}
2206 
2207 	lock_clear(&apic_ioapic_lock);
2208 }
2209 
2210 static int
apix_intx_get_shared(int irqno)2211 apix_intx_get_shared(int irqno)
2212 {
2213 	apic_irq_t *irqp;
2214 	int share;
2215 
2216 	mutex_enter(&airq_mutex);
2217 	irqp = apic_irq_table[irqno];
2218 	if (IS_IRQ_FREE(irqp) || (irqp->airq_cpu == IRQ_UNINIT)) {
2219 		mutex_exit(&airq_mutex);
2220 		return (0);
2221 	}
2222 	share = irqp->airq_share;
2223 	mutex_exit(&airq_mutex);
2224 
2225 	return (share);
2226 }
2227 
2228 static void
apix_intx_set_shared(int irqno,int delta)2229 apix_intx_set_shared(int irqno, int delta)
2230 {
2231 	apic_irq_t *irqp;
2232 
2233 	mutex_enter(&airq_mutex);
2234 	irqp = apic_irq_table[irqno];
2235 	if (IS_IRQ_FREE(irqp)) {
2236 		mutex_exit(&airq_mutex);
2237 		return;
2238 	}
2239 	irqp->airq_share += delta;
2240 	mutex_exit(&airq_mutex);
2241 }
2242 
2243 /*
2244  * Setup IRQ table. Return IRQ no or -1 on failure
2245  */
2246 static int
apix_intx_setup(dev_info_t * dip,int inum,int irqno,struct apic_io_intr * intrp,struct intrspec * ispec,iflag_t * iflagp)2247 apix_intx_setup(dev_info_t *dip, int inum, int irqno,
2248     struct apic_io_intr *intrp, struct intrspec *ispec, iflag_t *iflagp)
2249 {
2250 	int origirq = ispec->intrspec_vec;
2251 	int newirq;
2252 	short intr_index;
2253 	uchar_t ipin, ioapic, ioapicindex;
2254 	apic_irq_t *irqp;
2255 
2256 	UNREFERENCED_1PARAMETER(inum);
2257 
2258 	if (intrp != NULL) {
2259 		intr_index = (short)(intrp - apic_io_intrp);
2260 		ioapic = intrp->intr_destid;
2261 		ipin = intrp->intr_destintin;
2262 
2263 		/* Find ioapicindex. If destid was ALL, we will exit with 0. */
2264 		for (ioapicindex = apic_io_max - 1; ioapicindex; ioapicindex--)
2265 			if (apic_io_id[ioapicindex] == ioapic)
2266 				break;
2267 		ASSERT((ioapic == apic_io_id[ioapicindex]) ||
2268 		    (ioapic == INTR_ALL_APIC));
2269 
2270 		/* check whether this intin# has been used by another irqno */
2271 		if ((newirq = apic_find_intin(ioapicindex, ipin)) != -1)
2272 			return (newirq);
2273 
2274 	} else if (iflagp != NULL) {	/* ACPI */
2275 		intr_index = ACPI_INDEX;
2276 		ioapicindex = acpi_find_ioapic(irqno);
2277 		ASSERT(ioapicindex != 0xFF);
2278 		ioapic = apic_io_id[ioapicindex];
2279 		ipin = irqno - apic_io_vectbase[ioapicindex];
2280 
2281 		if (apic_irq_table[irqno] &&
2282 		    apic_irq_table[irqno]->airq_mps_intr_index == ACPI_INDEX) {
2283 			ASSERT(apic_irq_table[irqno]->airq_intin_no == ipin &&
2284 			    apic_irq_table[irqno]->airq_ioapicindex ==
2285 			    ioapicindex);
2286 			return (irqno);
2287 		}
2288 
2289 	} else {	/* default configuration */
2290 		intr_index = DEFAULT_INDEX;
2291 		ioapicindex = 0;
2292 		ioapic = apic_io_id[ioapicindex];
2293 		ipin = (uchar_t)irqno;
2294 	}
2295 
2296 	/* allocate a new IRQ no */
2297 	if ((irqp = apic_irq_table[irqno]) == NULL) {
2298 		irqp = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP);
2299 		apic_irq_table[irqno] = irqp;
2300 	} else {
2301 		if (irqp->airq_mps_intr_index != FREE_INDEX) {
2302 			newirq = apic_allocate_irq(apic_first_avail_irq);
2303 			if (newirq == -1) {
2304 				return (-1);
2305 			}
2306 			irqno = newirq;
2307 			irqp = apic_irq_table[irqno];
2308 			ASSERT(irqp != NULL);
2309 		}
2310 	}
2311 	apic_max_device_irq = max(irqno, apic_max_device_irq);
2312 	apic_min_device_irq = min(irqno, apic_min_device_irq);
2313 
2314 	irqp->airq_mps_intr_index = intr_index;
2315 	irqp->airq_ioapicindex = ioapicindex;
2316 	irqp->airq_intin_no = ipin;
2317 	irqp->airq_dip = dip;
2318 	irqp->airq_origirq = (uchar_t)origirq;
2319 	if (iflagp != NULL)
2320 		irqp->airq_iflag = *iflagp;
2321 	irqp->airq_cpu = IRQ_UNINIT;
2322 	irqp->airq_vector = 0;
2323 
2324 	return (irqno);
2325 }
2326 
2327 /*
2328  * Setup IRQ table for non-pci devices. Return IRQ no or -1 on error
2329  */
2330 static int
apix_intx_setup_nonpci(dev_info_t * dip,int inum,int bustype,struct intrspec * ispec)2331 apix_intx_setup_nonpci(dev_info_t *dip, int inum, int bustype,
2332     struct intrspec *ispec)
2333 {
2334 	int irqno = ispec->intrspec_vec;
2335 	int newirq, i;
2336 	iflag_t intr_flag;
2337 	ACPI_SUBTABLE_HEADER	*hp;
2338 	ACPI_MADT_INTERRUPT_OVERRIDE *isop;
2339 	struct apic_io_intr *intrp;
2340 
2341 	if (!apic_enable_acpi || apic_use_acpi_madt_only) {
2342 		int busid;
2343 
2344 		if (bustype == 0)
2345 			bustype = eisa_level_intr_mask ? BUS_EISA : BUS_ISA;
2346 
2347 		/* loop checking BUS_ISA/BUS_EISA */
2348 		for (i = 0; i < 2; i++) {
2349 			if (((busid = apic_find_bus_id(bustype)) != -1) &&
2350 			    ((intrp = apic_find_io_intr_w_busid(irqno, busid))
2351 			    != NULL)) {
2352 				return (apix_intx_setup(dip, inum, irqno,
2353 				    intrp, ispec, NULL));
2354 			}
2355 			bustype = (bustype == BUS_EISA) ? BUS_ISA : BUS_EISA;
2356 		}
2357 
2358 		/* fall back to default configuration */
2359 		return (-1);
2360 	}
2361 
2362 	/* search iso entries first */
2363 	if (acpi_iso_cnt != 0) {
2364 		hp = (ACPI_SUBTABLE_HEADER *)acpi_isop;
2365 		i = 0;
2366 		while (i < acpi_iso_cnt) {
2367 			if (hp->Type == ACPI_MADT_TYPE_INTERRUPT_OVERRIDE) {
2368 				isop = (ACPI_MADT_INTERRUPT_OVERRIDE *) hp;
2369 				if (isop->Bus == 0 &&
2370 				    isop->SourceIrq == irqno) {
2371 					newirq = isop->GlobalIrq;
2372 					intr_flag.intr_po = isop->IntiFlags &
2373 					    ACPI_MADT_POLARITY_MASK;
2374 					intr_flag.intr_el = (isop->IntiFlags &
2375 					    ACPI_MADT_TRIGGER_MASK) >> 2;
2376 					intr_flag.bustype = BUS_ISA;
2377 
2378 					return (apix_intx_setup(dip, inum,
2379 					    newirq, NULL, ispec, &intr_flag));
2380 				}
2381 				i++;
2382 			}
2383 			hp = (ACPI_SUBTABLE_HEADER *)(((char *)hp) +
2384 			    hp->Length);
2385 		}
2386 	}
2387 	intr_flag.intr_po = INTR_PO_ACTIVE_HIGH;
2388 	intr_flag.intr_el = INTR_EL_EDGE;
2389 	intr_flag.bustype = BUS_ISA;
2390 	return (apix_intx_setup(dip, inum, irqno, NULL, ispec, &intr_flag));
2391 }
2392 
2393 
2394 /*
2395  * Setup IRQ table for pci devices. Return IRQ no or -1 on error
2396  */
2397 static int
apix_intx_setup_pci(dev_info_t * dip,int inum,int bustype,struct intrspec * ispec)2398 apix_intx_setup_pci(dev_info_t *dip, int inum, int bustype,
2399     struct intrspec *ispec)
2400 {
2401 	int busid, devid, pci_irq;
2402 	ddi_acc_handle_t cfg_handle;
2403 	uchar_t ipin;
2404 	iflag_t intr_flag;
2405 	struct apic_io_intr *intrp;
2406 
2407 	if (acpica_get_bdf(dip, &busid, &devid, NULL) != 0)
2408 		return (-1);
2409 
2410 	if (busid == 0 && apic_pci_bus_total == 1)
2411 		busid = (int)apic_single_pci_busid;
2412 
2413 	if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS)
2414 		return (-1);
2415 	ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA;
2416 	pci_config_teardown(&cfg_handle);
2417 
2418 	if (apic_enable_acpi && !apic_use_acpi_madt_only) {	/* ACPI */
2419 		if (apic_acpi_translate_pci_irq(dip, busid, devid,
2420 		    ipin, &pci_irq, &intr_flag) != ACPI_PSM_SUCCESS)
2421 			return (-1);
2422 
2423 		intr_flag.bustype = (uchar_t)bustype;
2424 		return (apix_intx_setup(dip, inum, pci_irq, NULL, ispec,
2425 		    &intr_flag));
2426 	}
2427 
2428 	/* MP configuration table */
2429 	pci_irq = ((devid & 0x1f) << 2) | (ipin & 0x3);
2430 	if ((intrp = apic_find_io_intr_w_busid(pci_irq, busid)) == NULL) {
2431 		pci_irq = apic_handle_pci_pci_bridge(dip, devid, ipin, &intrp);
2432 		if (pci_irq == -1)
2433 			return (-1);
2434 	}
2435 
2436 	return (apix_intx_setup(dip, inum, pci_irq, intrp, ispec, NULL));
2437 }
2438 
2439 /*
2440  * Translate and return IRQ no
2441  */
2442 static int
apix_intx_xlate_irq(dev_info_t * dip,int inum,struct intrspec * ispec)2443 apix_intx_xlate_irq(dev_info_t *dip, int inum, struct intrspec *ispec)
2444 {
2445 	int newirq, irqno = ispec->intrspec_vec;
2446 	int parent_is_pci_or_pciex = 0, child_is_pciex = 0;
2447 	int bustype = 0, dev_len;
2448 	char dev_type[16];
2449 
2450 	if (apic_defconf) {
2451 		mutex_enter(&airq_mutex);
2452 		goto defconf;
2453 	}
2454 
2455 	if ((dip == NULL) || (!apic_irq_translate && !apic_enable_acpi)) {
2456 		mutex_enter(&airq_mutex);
2457 		goto nonpci;
2458 	}
2459 
2460 	/*
2461 	 * use ddi_getlongprop_buf() instead of ddi_prop_lookup_string()
2462 	 * to avoid extra buffer allocation.
2463 	 */
2464 	dev_len = sizeof (dev_type);
2465 	if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(dip),
2466 	    DDI_PROP_DONTPASS, "device_type", (caddr_t)dev_type,
2467 	    &dev_len) == DDI_PROP_SUCCESS) {
2468 		if ((strcmp(dev_type, "pci") == 0) ||
2469 		    (strcmp(dev_type, "pciex") == 0))
2470 			parent_is_pci_or_pciex = 1;
2471 	}
2472 
2473 	if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip,
2474 	    DDI_PROP_DONTPASS, "compatible", (caddr_t)dev_type,
2475 	    &dev_len) == DDI_PROP_SUCCESS) {
2476 		if (strstr(dev_type, "pciex"))
2477 			child_is_pciex = 1;
2478 	}
2479 
2480 	mutex_enter(&airq_mutex);
2481 
2482 	if (parent_is_pci_or_pciex) {
2483 		bustype = child_is_pciex ? BUS_PCIE : BUS_PCI;
2484 		newirq = apix_intx_setup_pci(dip, inum, bustype, ispec);
2485 		if (newirq != -1)
2486 			goto done;
2487 		bustype = 0;
2488 	} else if (strcmp(dev_type, "isa") == 0)
2489 		bustype = BUS_ISA;
2490 	else if (strcmp(dev_type, "eisa") == 0)
2491 		bustype = BUS_EISA;
2492 
2493 nonpci:
2494 	newirq = apix_intx_setup_nonpci(dip, inum, bustype, ispec);
2495 	if (newirq != -1)
2496 		goto done;
2497 
2498 defconf:
2499 	newirq = apix_intx_setup(dip, inum, irqno, NULL, ispec, NULL);
2500 	if (newirq == -1) {
2501 		mutex_exit(&airq_mutex);
2502 		return (-1);
2503 	}
2504 done:
2505 	ASSERT(apic_irq_table[newirq]);
2506 	mutex_exit(&airq_mutex);
2507 	return (newirq);
2508 }
2509 
2510 static int
apix_intx_alloc_vector(dev_info_t * dip,int inum,struct intrspec * ispec)2511 apix_intx_alloc_vector(dev_info_t *dip, int inum, struct intrspec *ispec)
2512 {
2513 	int irqno;
2514 	apix_vector_t *vecp;
2515 
2516 	if ((irqno = apix_intx_xlate_irq(dip, inum, ispec)) == -1)
2517 		return (0);
2518 
2519 	if ((vecp = apix_alloc_intx(dip, inum, irqno)) == NULL)
2520 		return (0);
2521 
2522 	DDI_INTR_IMPLDBG((CE_CONT, "apix_intx_alloc_vector: dip=0x%p name=%s "
2523 	    "irqno=0x%x cpuid=%d vector=0x%x\n",
2524 	    (void *)dip, ddi_driver_name(dip), irqno,
2525 	    vecp->v_cpuid, vecp->v_vector));
2526 
2527 	return (1);
2528 }
2529 
2530 /*
2531  * Return the vector number if the translated IRQ for this device
2532  * has a vector mapping setup. If no IRQ setup exists or no vector is
2533  * allocated to it then return 0.
2534  */
2535 static apix_vector_t *
apix_intx_xlate_vector(dev_info_t * dip,int inum,struct intrspec * ispec)2536 apix_intx_xlate_vector(dev_info_t *dip, int inum, struct intrspec *ispec)
2537 {
2538 	int irqno;
2539 	apix_vector_t *vecp;
2540 
2541 	/* get the IRQ number */
2542 	if ((irqno = apix_intx_xlate_irq(dip, inum, ispec)) == -1)
2543 		return (NULL);
2544 
2545 	/* get the vector number if a vector is allocated to this irqno */
2546 	vecp = apix_intx_get_vector(irqno);
2547 
2548 	return (vecp);
2549 }
2550 
2551 /* stub function */
2552 int
apix_loaded(void)2553 apix_loaded(void)
2554 {
2555 	return (apix_is_enabled);
2556 }
2557