1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 * Copyright 2019 Joyent, Inc.
29 * Copyright 2020 Oxide Computer Company
30 */
31
32 /*
33 * To understand how the pcplusmp module interacts with the interrupt subsystem
34 * read the theory statement in uts/i86pc/os/intr.c.
35 */
36
37 /*
38 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
39 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
40 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
41 * PSMI 1.5 extensions are supported in Solaris Nevada.
42 * PSMI 1.6 extensions are supported in Solaris Nevada.
43 * PSMI 1.7 extensions are supported in Solaris Nevada.
44 */
45 #define PSMI_1_7
46
47 #include <sys/processor.h>
48 #include <sys/time.h>
49 #include <sys/psm.h>
50 #include <sys/smp_impldefs.h>
51 #include <sys/cram.h>
52 #include <sys/acpi/acpi.h>
53 #include <sys/acpica.h>
54 #include <sys/psm_common.h>
55 #include <sys/apic.h>
56 #include <sys/pit.h>
57 #include <sys/ddi.h>
58 #include <sys/sunddi.h>
59 #include <sys/ddi_impldefs.h>
60 #include <sys/pci.h>
61 #include <sys/promif.h>
62 #include <sys/prom_debug.h>
63 #include <sys/x86_archext.h>
64 #include <sys/cpc_impl.h>
65 #include <sys/uadmin.h>
66 #include <sys/panic.h>
67 #include <sys/debug.h>
68 #include <sys/archsystm.h>
69 #include <sys/trap.h>
70 #include <sys/machsystm.h>
71 #include <sys/sysmacros.h>
72 #include <sys/cpuvar.h>
73 #include <sys/rm_platter.h>
74 #include <sys/privregs.h>
75 #include <sys/note.h>
76 #include <sys/pci_intr_lib.h>
77 #include <sys/spl.h>
78 #include <sys/clock.h>
79 #include <sys/cyclic.h>
80 #include <sys/dditypes.h>
81 #include <sys/sunddi.h>
82 #include <sys/x_call.h>
83 #include <sys/reboot.h>
84 #include <sys/hpet.h>
85 #include <sys/apic_common.h>
86 #include <sys/apic_timer.h>
87 #include <sys/smt.h>
88
89 /*
90 * Local Function Prototypes
91 */
92 static void apic_init_intr(void);
93
94 /*
95 * standard MP entries
96 */
97 static int apic_probe(void);
98 static int apic_getclkirq(int ipl);
99 static void apic_init(void);
100 static void apic_picinit(void);
101 static int apic_post_cpu_start(void);
102 static int apic_intr_enter(int ipl, int *vect);
103 static void apic_setspl(int ipl);
104 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl);
105 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl);
106 static int apic_disable_intr(processorid_t cpun);
107 static void apic_enable_intr(processorid_t cpun);
108 static int apic_get_ipivect(int ipl, int type);
109 static void apic_post_cyclic_setup(void *arg);
110
111 /*
112 * The following vector assignments influence the value of ipltopri and
113 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program
114 * idle to 0 and IPL 0 to 0xf to differentiate idle in case
115 * we care to do so in future. Note some IPLs which are rarely used
116 * will share the vector ranges and heavily used IPLs (5 and 6) have
117 * a wide range.
118 *
119 * This array is used to initialize apic_ipls[] (in apic_init()).
120 *
121 * IPL Vector range. as passed to intr_enter
122 * 0 none.
123 * 1,2,3 0x20-0x2f 0x0-0xf
124 * 4 0x30-0x3f 0x10-0x1f
125 * 5 0x40-0x5f 0x20-0x3f
126 * 6 0x60-0x7f 0x40-0x5f
127 * 7,8,9 0x80-0x8f 0x60-0x6f
128 * 10 0x90-0x9f 0x70-0x7f
129 * 11 0xa0-0xaf 0x80-0x8f
130 * ... ...
131 * 15 0xe0-0xef 0xc0-0xcf
132 * 15 0xf0-0xff 0xd0-0xdf
133 */
134 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = {
135 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15
136 };
137 /*
138 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4]
139 * NOTE that this is vector as passed into intr_enter which is
140 * programmed vector - 0x20 (APIC_BASE_VECT)
141 */
142
143 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */
144 /* The taskpri to be programmed into apic to mask given ipl */
145
146 /*
147 * Correlation of the hardware vector to the IPL in use, initialized
148 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate
149 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines
150 * connected to errata-stricken IOAPICs
151 */
152 uchar_t apic_ipls[APIC_AVAIL_VECTOR];
153
154 /*
155 * Patchable global variables.
156 */
157 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */
158 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */
159
160 /*
161 * Local static data
162 */
163 static struct psm_ops apic_ops = {
164 apic_probe,
165
166 apic_init,
167 apic_picinit,
168 apic_intr_enter,
169 apic_intr_exit,
170 apic_setspl,
171 apic_addspl,
172 apic_delspl,
173 apic_disable_intr,
174 apic_enable_intr,
175 (int (*)(int))NULL, /* psm_softlvl_to_irq */
176 (void (*)(int))NULL, /* psm_set_softintr */
177
178 apic_set_idlecpu,
179 apic_unset_idlecpu,
180
181 apic_clkinit,
182 apic_getclkirq,
183 (void (*)(void))NULL, /* psm_hrtimeinit */
184 apic_gethrtime,
185
186 apic_get_next_processorid,
187 apic_cpu_start,
188 apic_post_cpu_start,
189 apic_shutdown,
190 apic_get_ipivect,
191 apic_send_ipi,
192
193 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */
194 (void (*)(int, char *))NULL, /* psm_notify_error */
195 (void (*)(int))NULL, /* psm_notify_func */
196 apic_timer_reprogram,
197 apic_timer_enable,
198 apic_timer_disable,
199 apic_post_cyclic_setup,
200 apic_preshutdown,
201 apic_intr_ops, /* Advanced DDI Interrupt framework */
202 apic_state, /* save, restore apic state for S3 */
203 apic_cpu_ops, /* CPU control interface. */
204
205 apic_get_pir_ipivect,
206 apic_send_pir_ipi,
207 apic_cmci_setup,
208 };
209
210 struct psm_ops *psmops = &apic_ops;
211
212 static struct psm_info apic_psm_info = {
213 PSM_INFO_VER01_7, /* version */
214 PSM_OWN_EXCLUSIVE, /* ownership */
215 (struct psm_ops *)&apic_ops, /* operation */
216 APIC_PCPLUSMP_NAME, /* machine name */
217 "pcplusmp v1.4 compatible",
218 };
219
220 static void *apic_hdlp;
221
222 /* to gather intr data and redistribute */
223 static void apic_redistribute_compute(void);
224
225 /*
226 * This is the loadable module wrapper
227 */
228
229 int
_init(void)230 _init(void)
231 {
232 if (apic_coarse_hrtime)
233 apic_ops.psm_gethrtime = &apic_gettime;
234 return (psm_mod_init(&apic_hdlp, &apic_psm_info));
235 }
236
237 int
_fini(void)238 _fini(void)
239 {
240 return (psm_mod_fini(&apic_hdlp, &apic_psm_info));
241 }
242
243 int
_info(struct modinfo * modinfop)244 _info(struct modinfo *modinfop)
245 {
246 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop));
247 }
248
249 static int
apic_probe(void)250 apic_probe(void)
251 {
252 PRM_POINT("apic_probe()");
253
254 /* check if apix is initialized */
255 if (apix_enable && apix_loaded()) {
256 PRM_POINT("apic_probe FAILURE: apix is loaded");
257 return (PSM_FAILURE);
258 }
259
260 /*
261 * Check whether x2APIC mode was activated by BIOS. We don't support
262 * that in pcplusmp as apix normally handles that.
263 */
264 PRM_POINT("apic_local_mode()");
265 if (apic_local_mode() == LOCAL_X2APIC) {
266 PRM_POINT("apic_probe FAILURE: in x2apic mode");
267 return (PSM_FAILURE);
268 }
269
270 /* continue using pcplusmp PSM */
271 apix_enable = 0;
272
273 return (apic_probe_common(apic_psm_info.p_mach_idstring));
274 }
275
276 static uchar_t
apic_xlate_vector_by_irq(uchar_t irq)277 apic_xlate_vector_by_irq(uchar_t irq)
278 {
279 if (apic_irq_table[irq] == NULL)
280 return (0);
281
282 return (apic_irq_table[irq]->airq_vector);
283 }
284
285 void
apic_init(void)286 apic_init(void)
287 {
288 int i;
289 int j = 1;
290
291 psm_get_ioapicid = apic_get_ioapicid;
292 psm_get_localapicid = apic_get_localapicid;
293 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq;
294
295 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */
296 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
297 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) &&
298 (apic_vectortoipl[i + 1] == apic_vectortoipl[i]))
299 /* get to highest vector at the same ipl */
300 continue;
301 for (; j <= apic_vectortoipl[i]; j++) {
302 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) +
303 APIC_BASE_VECT;
304 }
305 }
306 for (; j < MAXIPL + 1; j++)
307 /* fill up any empty ipltopri slots */
308 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT;
309 apic_init_common();
310
311 /*
312 * For pcplusmp, we'll keep things simple and always disable this.
313 */
314 smt_intr_alloc_pil(XC_CPUPOKE_PIL);
315
316 apic_pir_vect = apic_get_ipivect(XC_CPUPOKE_PIL, -1);
317
318 }
319
320 static void
apic_init_intr(void)321 apic_init_intr(void)
322 {
323 processorid_t cpun = psm_get_cpu_id();
324 uint_t nlvt;
325 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
326
327 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
328
329 ASSERT(apic_mode == LOCAL_APIC);
330
331 /*
332 * We are running APIC in MMIO mode.
333 */
334 if (apic_flat_model) {
335 apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_FLAT_MODEL);
336 } else {
337 apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_CLUSTER_MODEL);
338 }
339
340 apic_reg_ops->apic_write(APIC_DEST_REG, AV_HIGH_ORDER >> cpun);
341
342 if (apic_directed_EOI_supported()) {
343 /*
344 * Setting the 12th bit in the Spurious Interrupt Vector
345 * Register suppresses broadcast EOIs generated by the local
346 * APIC. The suppression of broadcast EOIs happens only when
347 * interrupts are level-triggered.
348 */
349 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
350 }
351
352 /* need to enable APIC before unmasking NMI */
353 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
354
355 /*
356 * Presence of an invalid vector with delivery mode AV_FIXED can
357 * cause an error interrupt, even if the entry is masked...so
358 * write a valid vector to LVT entries along with the mask bit
359 */
360
361 /* All APICs have timer and LINT0/1 */
362 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
363 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
364 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */
365
366 /*
367 * On integrated APICs, the number of LVT entries is
368 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
369 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
370 */
371
372 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
373 nlvt = 3;
374 } else {
375 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
376 0xFF) + 1;
377 }
378
379 if (nlvt >= 5) {
380 /* Enable performance counter overflow interrupt */
381
382 if (!is_x86_feature(x86_featureset, X86FSET_MSR))
383 apic_enable_cpcovf_intr = 0;
384 if (apic_enable_cpcovf_intr) {
385 if (apic_cpcovf_vect == 0) {
386 int ipl = APIC_PCINT_IPL;
387 int irq = apic_get_ipivect(ipl, -1);
388
389 ASSERT(irq != -1);
390 apic_cpcovf_vect =
391 apic_irq_table[irq]->airq_vector;
392 ASSERT(apic_cpcovf_vect);
393 (void) add_avintr(NULL, ipl,
394 (avfunc)kcpc_hw_overflow_intr,
395 "apic pcint", irq, NULL, NULL, NULL, NULL);
396 kcpc_hw_overflow_intr_installed = 1;
397 kcpc_hw_enable_cpc_intr =
398 apic_cpcovf_mask_clear;
399 }
400 apic_reg_ops->apic_write(APIC_PCINT_VECT,
401 apic_cpcovf_vect);
402 }
403 }
404
405 if (nlvt >= 6) {
406 /* Only mask TM intr if the BIOS apparently doesn't use it */
407
408 uint32_t lvtval;
409
410 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
411 if (((lvtval & AV_MASK) == AV_MASK) ||
412 ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
413 apic_reg_ops->apic_write(APIC_THERM_VECT,
414 AV_MASK|APIC_RESV_IRQ);
415 }
416 }
417
418 /* Enable error interrupt */
419
420 if (nlvt >= 4 && apic_enable_error_intr) {
421 if (apic_errvect == 0) {
422 int ipl = 0xf; /* get highest priority intr */
423 int irq = apic_get_ipivect(ipl, -1);
424
425 ASSERT(irq != -1);
426 apic_errvect = apic_irq_table[irq]->airq_vector;
427 ASSERT(apic_errvect);
428 /*
429 * Not PSMI compliant, but we are going to merge
430 * with ON anyway
431 */
432 (void) add_avintr((void *)NULL, ipl,
433 (avfunc)apic_error_intr, "apic error intr",
434 irq, NULL, NULL, NULL, NULL);
435 }
436 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
437 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
438 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
439 }
440
441 /*
442 * Ensure a CMCI interrupt is allocated, regardless of whether it is
443 * enabled or not.
444 */
445 if (apic_cmci_vect == 0) {
446 const int ipl = 0x2;
447 int irq = apic_get_ipivect(ipl, -1);
448
449 ASSERT(irq != -1);
450 apic_cmci_vect = apic_irq_table[irq]->airq_vector;
451 ASSERT(apic_cmci_vect);
452
453 (void) add_avintr(NULL, ipl,
454 (avfunc)cmi_cmci_trap,
455 "apic cmci intr", irq, NULL, NULL, NULL, NULL);
456 }
457 }
458
459 static void
apic_picinit(void)460 apic_picinit(void)
461 {
462 int i, j;
463 uint_t isr;
464
465 /*
466 * Initialize and enable interrupt remapping before apic
467 * hardware initialization
468 */
469 apic_intrmap_init(apic_mode);
470
471 /*
472 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
473 * bit on without clearing it with EOI. Since softint
474 * uses vector 0x20 to interrupt itself, so softint will
475 * not work on this machine. In order to fix this problem
476 * a check is made to verify all the isr bits are clear.
477 * If not, EOIs are issued to clear the bits.
478 */
479 for (i = 7; i >= 1; i--) {
480 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
481 if (isr != 0)
482 for (j = 0; ((j < 32) && (isr != 0)); j++)
483 if (isr & (1 << j)) {
484 apic_reg_ops->apic_write(
485 APIC_EOI_REG, 0);
486 isr &= ~(1 << j);
487 apic_error |= APIC_ERR_BOOT_EOI;
488 }
489 }
490
491 /* set a flag so we know we have run apic_picinit() */
492 apic_picinit_called = 1;
493 LOCK_INIT_CLEAR(&apic_gethrtime_lock);
494 LOCK_INIT_CLEAR(&apic_ioapic_lock);
495 LOCK_INIT_CLEAR(&apic_error_lock);
496 LOCK_INIT_CLEAR(&apic_mode_switch_lock);
497
498 picsetup(); /* initialise the 8259 */
499
500 /* add nmi handler - least priority nmi handler */
501 LOCK_INIT_CLEAR(&apic_nmi_lock);
502
503 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr,
504 "pcplusmp NMI handler", (caddr_t)NULL))
505 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler");
506
507 /*
508 * Check for directed-EOI capability in the local APIC.
509 */
510 if (apic_directed_EOI_supported() == 1) {
511 apic_set_directed_EOI_handler();
512 }
513
514 apic_init_intr();
515
516 /* enable apic mode if imcr present */
517 if (apic_imcrp) {
518 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
519 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
520 }
521
522 ioapic_init_intr(IOAPIC_MASK);
523 }
524
525 #ifdef DEBUG
526 void
apic_break(void)527 apic_break(void)
528 {
529 }
530 #endif /* DEBUG */
531
532 /*
533 * platform_intr_enter
534 *
535 * Called at the beginning of the interrupt service routine to
536 * mask all level equal to and below the interrupt priority
537 * of the interrupting vector. An EOI should be given to
538 * the interrupt controller to enable other HW interrupts.
539 *
540 * Return -1 for spurious interrupts
541 *
542 */
543 /*ARGSUSED*/
544 static int
apic_intr_enter(int ipl,int * vectorp)545 apic_intr_enter(int ipl, int *vectorp)
546 {
547 uchar_t vector;
548 int nipl;
549 int irq;
550 ulong_t iflag;
551 apic_cpus_info_t *cpu_infop;
552
553 /*
554 * The real vector delivered is (*vectorp + 0x20), but our caller
555 * subtracts 0x20 from the vector before passing it to us.
556 * (That's why APIC_BASE_VECT is 0x20.)
557 */
558 vector = (uchar_t)*vectorp;
559
560 /* if interrupted by the clock, increment apic_nsec_since_boot */
561 if (vector == apic_clkvect) {
562 if (!apic_oneshot) {
563 /* NOTE: this is not MT aware */
564 apic_hrtime_stamp++;
565 apic_nsec_since_boot += apic_nsec_per_intr;
566 apic_hrtime_stamp++;
567 last_count_read = apic_hertz_count;
568 apic_redistribute_compute();
569 }
570
571 /* We will avoid all the book keeping overhead for clock */
572 nipl = apic_ipls[vector];
573
574 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT];
575
576 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
577 apic_reg_ops->apic_send_eoi(0);
578
579 return (nipl);
580 }
581
582 cpu_infop = &apic_cpus[psm_get_cpu_id()];
583
584 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) {
585 cpu_infop->aci_spur_cnt++;
586 return (APIC_INT_SPURIOUS);
587 }
588
589 /* Check if the vector we got is really what we need */
590 if (apic_revector_pending) {
591 /*
592 * Disable interrupts for the duration of
593 * the vector translation to prevent a self-race for
594 * the apic_revector_lock. This cannot be done
595 * in apic_xlate_vector because it is recursive and
596 * we want the vector translation to be atomic with
597 * respect to other (higher-priority) interrupts.
598 */
599 iflag = intr_clear();
600 vector = apic_xlate_vector(vector + APIC_BASE_VECT) -
601 APIC_BASE_VECT;
602 intr_restore(iflag);
603 }
604
605 nipl = apic_ipls[vector];
606 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT];
607
608 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
609
610 cpu_infop->aci_current[nipl] = (uchar_t)irq;
611 cpu_infop->aci_curipl = (uchar_t)nipl;
612 cpu_infop->aci_ISR_in_progress |= 1 << nipl;
613
614 /*
615 * apic_level_intr could have been assimilated into the irq struct.
616 * but, having it as a character array is more efficient in terms of
617 * cache usage. So, we leave it as is.
618 */
619 if (!apic_level_intr[irq]) {
620 apic_reg_ops->apic_send_eoi(0);
621 }
622
623 #ifdef DEBUG
624 APIC_DEBUG_BUF_PUT(vector);
625 APIC_DEBUG_BUF_PUT(irq);
626 APIC_DEBUG_BUF_PUT(nipl);
627 APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
628 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
629 drv_usecwait(apic_stretch_interrupts);
630
631 if (apic_break_on_cpu == psm_get_cpu_id())
632 apic_break();
633 #endif /* DEBUG */
634 return (nipl);
635 }
636
637 void
apic_intr_exit(int prev_ipl,int irq)638 apic_intr_exit(int prev_ipl, int irq)
639 {
640 apic_cpus_info_t *cpu_infop;
641
642 apic_reg_ops->apic_write_task_reg(apic_ipltopri[prev_ipl]);
643
644 cpu_infop = &apic_cpus[psm_get_cpu_id()];
645 if (apic_level_intr[irq])
646 apic_reg_ops->apic_send_eoi(irq);
647 cpu_infop->aci_curipl = (uchar_t)prev_ipl;
648 /* ISR above current pri could not be in progress */
649 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1;
650 }
651
652 intr_exit_fn_t
psm_intr_exit_fn(void)653 psm_intr_exit_fn(void)
654 {
655 return (apic_intr_exit);
656 }
657
658 /*
659 * Mask all interrupts below or equal to the given IPL.
660 */
661 static void
apic_setspl(int ipl)662 apic_setspl(int ipl)
663 {
664 apic_reg_ops->apic_write_task_reg(apic_ipltopri[ipl]);
665
666 /* interrupts at ipl above this cannot be in progress */
667 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
668 /*
669 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts
670 * have enough time to come in before the priority is raised again
671 * during the idle() loop.
672 */
673 if (apic_setspl_delay)
674 (void) apic_reg_ops->apic_get_pri();
675 }
676
677 /*ARGSUSED*/
678 static int
apic_addspl(int irqno,int ipl,int min_ipl,int max_ipl)679 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl)
680 {
681 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl));
682 }
683
684 static int
apic_delspl(int irqno,int ipl,int min_ipl,int max_ipl)685 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl)
686 {
687 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl));
688 }
689
690 static int
apic_post_cpu_start(void)691 apic_post_cpu_start(void)
692 {
693 int cpun;
694 static int cpus_started = 1;
695
696 /* We know this CPU + BSP started successfully. */
697 cpus_started++;
698
699 splx(ipltospl(LOCK_LEVEL));
700 apic_init_intr();
701
702 APIC_AV_PENDING_SET();
703
704 /*
705 * We may be booting, or resuming from suspend; aci_status will
706 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
707 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
708 */
709 cpun = psm_get_cpu_id();
710 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
711
712 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
713 return (PSM_SUCCESS);
714 }
715
716 /*
717 * type == -1 indicates it is an internal request. Do not change
718 * resv_vector for these requests
719 */
720 static int
apic_get_ipivect(int ipl,int type)721 apic_get_ipivect(int ipl, int type)
722 {
723 uchar_t vector;
724 int irq;
725
726 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) {
727 if ((vector = apic_allocate_vector(ipl, irq, 1))) {
728 apic_irq_table[irq]->airq_mps_intr_index =
729 RESERVE_INDEX;
730 apic_irq_table[irq]->airq_vector = vector;
731 if (type != -1) {
732 apic_resv_vector[ipl] = vector;
733 }
734 return (irq);
735 }
736 }
737 apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
738 return (-1); /* shouldn't happen */
739 }
740
741 static int
apic_getclkirq(int ipl)742 apic_getclkirq(int ipl)
743 {
744 int irq;
745
746 if ((irq = apic_get_ipivect(ipl, -1)) == -1)
747 return (-1);
748 /*
749 * Note the vector in apic_clkvect for per clock handling.
750 */
751 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT;
752 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n",
753 apic_clkvect));
754 return (irq);
755 }
756
757 /*
758 * Try and disable all interrupts. We just assign interrupts to other
759 * processors based on policy. If any were bound by user request, we
760 * let them continue and return failure. We do not bother to check
761 * for cache affinity while rebinding.
762 */
763
764 static int
apic_disable_intr(processorid_t cpun)765 apic_disable_intr(processorid_t cpun)
766 {
767 int bind_cpu = 0, i, hardbound = 0;
768 apic_irq_t *irq_ptr;
769 ulong_t iflag;
770
771 iflag = intr_clear();
772 lock_set(&apic_ioapic_lock);
773
774 for (i = 0; i <= APIC_MAX_VECTOR; i++) {
775 if (apic_reprogram_info[i].done == B_FALSE) {
776 if (apic_reprogram_info[i].bindcpu == cpun) {
777 /*
778 * CPU is busy -- it's the target of
779 * a pending reprogramming attempt
780 */
781 lock_clear(&apic_ioapic_lock);
782 intr_restore(iflag);
783 return (PSM_FAILURE);
784 }
785 }
786 }
787
788 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
789
790 apic_cpus[cpun].aci_curipl = 0;
791
792 i = apic_min_device_irq;
793 for (; i <= apic_max_device_irq; i++) {
794 /*
795 * If there are bound interrupts on this cpu, then
796 * rebind them to other processors.
797 */
798 if ((irq_ptr = apic_irq_table[i]) != NULL) {
799 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) ||
800 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) ||
801 (apic_cpu_in_range(irq_ptr->airq_temp_cpu)));
802
803 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) {
804 hardbound = 1;
805 continue;
806 }
807
808 if (irq_ptr->airq_temp_cpu == cpun) {
809 do {
810 bind_cpu =
811 apic_find_cpu(APIC_CPU_INTR_ENABLE);
812 } while (apic_rebind_all(irq_ptr, bind_cpu));
813 }
814 }
815 }
816
817 lock_clear(&apic_ioapic_lock);
818 intr_restore(iflag);
819
820 if (hardbound) {
821 cmn_err(CE_WARN, "Could not disable interrupts on %d"
822 "due to user bound interrupts", cpun);
823 return (PSM_FAILURE);
824 }
825 else
826 return (PSM_SUCCESS);
827 }
828
829 /*
830 * Bind interrupts to the CPU's local APIC.
831 * Interrupts should not be bound to a CPU's local APIC until the CPU
832 * is ready to receive interrupts.
833 */
834 static void
apic_enable_intr(processorid_t cpun)835 apic_enable_intr(processorid_t cpun)
836 {
837 int i;
838 apic_irq_t *irq_ptr;
839 ulong_t iflag;
840
841 iflag = intr_clear();
842 lock_set(&apic_ioapic_lock);
843
844 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
845
846 i = apic_min_device_irq;
847 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
848 if ((irq_ptr = apic_irq_table[i]) != NULL) {
849 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) {
850 (void) apic_rebind_all(irq_ptr,
851 irq_ptr->airq_cpu);
852 }
853 }
854 }
855
856 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND)
857 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
858
859 lock_clear(&apic_ioapic_lock);
860 intr_restore(iflag);
861 }
862
863 /*
864 * If this module needs a periodic handler for the interrupt distribution, it
865 * can be added here. The argument to the periodic handler is not currently
866 * used, but is reserved for future.
867 */
868 static void
apic_post_cyclic_setup(void * arg)869 apic_post_cyclic_setup(void *arg)
870 {
871 _NOTE(ARGUNUSED(arg))
872
873 cyc_handler_t cyh;
874 cyc_time_t cyt;
875
876 /* cpu_lock is held */
877 /* set up a periodic handler for intr redistribution */
878
879 /*
880 * In peridoc mode intr redistribution processing is done in
881 * apic_intr_enter during clk intr processing
882 */
883 if (!apic_oneshot)
884 return;
885
886 /*
887 * Register a periodical handler for the redistribution processing.
888 * Though we would generally prefer to use the DDI interface for
889 * periodic handler invocation, ddi_periodic_add(9F), we are
890 * unfortunately already holding cpu_lock, which ddi_periodic_add will
891 * attempt to take for us. Thus, we add our own cyclic directly:
892 */
893 cyh.cyh_func = (void (*)(void *))apic_redistribute_compute;
894 cyh.cyh_arg = NULL;
895 cyh.cyh_level = CY_LOW_LEVEL;
896
897 cyt.cyt_when = 0;
898 cyt.cyt_interval = apic_redistribute_sample_interval;
899
900 apic_cyclic_id = cyclic_add(&cyh, &cyt);
901 }
902
903 static void
apic_redistribute_compute(void)904 apic_redistribute_compute(void)
905 {
906 int i, j, max_busy;
907
908 if (apic_enable_dynamic_migration) {
909 if (++apic_nticks == apic_sample_factor_redistribution) {
910 /*
911 * Time to call apic_intr_redistribute().
912 * reset apic_nticks. This will cause max_busy
913 * to be calculated below and if it is more than
914 * apic_int_busy, we will do the whole thing
915 */
916 apic_nticks = 0;
917 }
918 max_busy = 0;
919 for (i = 0; i < apic_nproc; i++) {
920 if (!apic_cpu_in_range(i))
921 continue;
922
923 /*
924 * Check if curipl is non zero & if ISR is in
925 * progress
926 */
927 if (((j = apic_cpus[i].aci_curipl) != 0) &&
928 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
929
930 int irq;
931 apic_cpus[i].aci_busy++;
932 irq = apic_cpus[i].aci_current[j];
933 apic_irq_table[irq]->airq_busy++;
934 }
935
936 if (!apic_nticks &&
937 (apic_cpus[i].aci_busy > max_busy))
938 max_busy = apic_cpus[i].aci_busy;
939 }
940 if (!apic_nticks) {
941 if (max_busy > apic_int_busy_mark) {
942 /*
943 * We could make the following check be
944 * skipped > 1 in which case, we get a
945 * redistribution at half the busy mark (due to
946 * double interval). Need to be able to collect
947 * more empirical data to decide if that is a
948 * good strategy. Punt for now.
949 */
950 if (apic_skipped_redistribute) {
951 apic_cleanup_busy();
952 apic_skipped_redistribute = 0;
953 } else {
954 apic_intr_redistribute();
955 }
956 } else
957 apic_skipped_redistribute++;
958 }
959 }
960 }
961
962
963 /*
964 * The following functions are in the platform specific file so that they
965 * can be different functions depending on whether we are running on
966 * bare metal or a hypervisor.
967 */
968
969 /*
970 * Check to make sure there are enough irq slots
971 */
972 int
apic_check_free_irqs(int count)973 apic_check_free_irqs(int count)
974 {
975 int i, avail;
976
977 avail = 0;
978 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
979 if ((apic_irq_table[i] == NULL) ||
980 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) {
981 if (++avail >= count)
982 return (PSM_SUCCESS);
983 }
984 }
985 return (PSM_FAILURE);
986 }
987
988 /*
989 * This function allocates "count" MSI vector(s) for the given "dip/pri/type"
990 */
991 int
apic_alloc_msi_vectors(dev_info_t * dip,int inum,int count,int pri,int behavior)992 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri,
993 int behavior)
994 {
995 int rcount, i;
996 uchar_t start, irqno;
997 uint32_t cpu = 0;
998 major_t major;
999 apic_irq_t *irqptr;
1000
1001 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p "
1002 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n",
1003 (void *)dip, inum, pri, count, behavior));
1004
1005 if (count > 1) {
1006 if (behavior == DDI_INTR_ALLOC_STRICT &&
1007 apic_multi_msi_enable == 0)
1008 return (0);
1009 if (apic_multi_msi_enable == 0)
1010 count = 1;
1011 }
1012
1013 if ((rcount = apic_navail_vector(dip, pri)) > count)
1014 rcount = count;
1015 else if (rcount == 0 || (rcount < count &&
1016 behavior == DDI_INTR_ALLOC_STRICT))
1017 return (0);
1018
1019 /* if not ISP2, then round it down */
1020 if (!ISP2(rcount))
1021 rcount = 1 << (highbit(rcount) - 1);
1022
1023 mutex_enter(&airq_mutex);
1024
1025 for (start = 0; rcount > 0; rcount >>= 1) {
1026 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 ||
1027 behavior == DDI_INTR_ALLOC_STRICT)
1028 break;
1029 }
1030
1031 if (start == 0) {
1032 /* no vector available */
1033 mutex_exit(&airq_mutex);
1034 return (0);
1035 }
1036
1037 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1038 /* not enough free irq slots available */
1039 mutex_exit(&airq_mutex);
1040 return (0);
1041 }
1042
1043 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1044 for (i = 0; i < rcount; i++) {
1045 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1046 (uchar_t)-1) {
1047 /*
1048 * shouldn't happen because of the
1049 * apic_check_free_irqs() check earlier
1050 */
1051 mutex_exit(&airq_mutex);
1052 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1053 "apic_allocate_irq failed\n"));
1054 return (i);
1055 }
1056 apic_max_device_irq = max(irqno, apic_max_device_irq);
1057 apic_min_device_irq = min(irqno, apic_min_device_irq);
1058 irqptr = apic_irq_table[irqno];
1059 #ifdef DEBUG
1060 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ)
1061 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1062 "apic_vector_to_irq is not APIC_RESV_IRQ\n"));
1063 #endif
1064 apic_vector_to_irq[start + i] = (uchar_t)irqno;
1065
1066 irqptr->airq_vector = (uchar_t)(start + i);
1067 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */
1068 irqptr->airq_intin_no = (uchar_t)rcount;
1069 ASSERT(pri >= 0 && pri <= UCHAR_MAX);
1070 irqptr->airq_ipl = (uchar_t)pri;
1071 irqptr->airq_vector = start + i;
1072 irqptr->airq_origirq = (uchar_t)(inum + i);
1073 irqptr->airq_share_id = 0;
1074 irqptr->airq_mps_intr_index = MSI_INDEX;
1075 irqptr->airq_dip = dip;
1076 irqptr->airq_major = major;
1077 if (i == 0) /* they all bound to the same cpu */
1078 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno,
1079 0xff, 0xff);
1080 else
1081 irqptr->airq_cpu = cpu;
1082 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x "
1083 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno,
1084 (void *)irqptr->airq_dip, irqptr->airq_vector,
1085 irqptr->airq_origirq, pri));
1086 }
1087 mutex_exit(&airq_mutex);
1088 return (rcount);
1089 }
1090
1091 /*
1092 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type"
1093 */
1094 int
apic_alloc_msix_vectors(dev_info_t * dip,int inum,int count,int pri,int behavior)1095 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri,
1096 int behavior)
1097 {
1098 int rcount, i;
1099 major_t major;
1100
1101 mutex_enter(&airq_mutex);
1102
1103 if ((rcount = apic_navail_vector(dip, pri)) > count)
1104 rcount = count;
1105 else if (rcount == 0 || (rcount < count &&
1106 behavior == DDI_INTR_ALLOC_STRICT)) {
1107 rcount = 0;
1108 goto out;
1109 }
1110
1111 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1112 /* not enough free irq slots available */
1113 rcount = 0;
1114 goto out;
1115 }
1116
1117 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1118 for (i = 0; i < rcount; i++) {
1119 uchar_t vector, irqno;
1120 apic_irq_t *irqptr;
1121
1122 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1123 (uchar_t)-1) {
1124 /*
1125 * shouldn't happen because of the
1126 * apic_check_free_irqs() check earlier
1127 */
1128 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1129 "apic_allocate_irq failed\n"));
1130 rcount = i;
1131 goto out;
1132 }
1133 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) {
1134 /*
1135 * shouldn't happen because of the
1136 * apic_navail_vector() call earlier
1137 */
1138 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1139 "apic_allocate_vector failed\n"));
1140 rcount = i;
1141 goto out;
1142 }
1143 apic_max_device_irq = max(irqno, apic_max_device_irq);
1144 apic_min_device_irq = min(irqno, apic_min_device_irq);
1145 irqptr = apic_irq_table[irqno];
1146 irqptr->airq_vector = (uchar_t)vector;
1147 ASSERT(pri >= 0 && pri <= UCHAR_MAX);
1148 irqptr->airq_ipl = (uchar_t)pri;
1149 irqptr->airq_origirq = (uchar_t)(inum + i);
1150 irqptr->airq_share_id = 0;
1151 irqptr->airq_mps_intr_index = MSIX_INDEX;
1152 irqptr->airq_dip = dip;
1153 irqptr->airq_major = major;
1154 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff);
1155 }
1156 out:
1157 mutex_exit(&airq_mutex);
1158 return (rcount);
1159 }
1160
1161 /*
1162 * Allocate a free vector for irq at ipl. Takes care of merging of multiple
1163 * IPLs into a single APIC level as well as stretching some IPLs onto multiple
1164 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority
1165 * requests and allocated only when pri is set.
1166 */
1167 uchar_t
apic_allocate_vector(int ipl,int irq,int pri)1168 apic_allocate_vector(int ipl, int irq, int pri)
1169 {
1170 int lowest, highest, i;
1171
1172 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK;
1173 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL;
1174
1175 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */
1176 lowest -= APIC_VECTOR_PER_IPL;
1177
1178 #ifdef DEBUG
1179 if (apic_restrict_vector) /* for testing shared interrupt logic */
1180 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS;
1181 #endif /* DEBUG */
1182 if (pri == 0)
1183 highest -= APIC_HI_PRI_VECTS;
1184
1185 for (i = lowest; i <= highest; i++) {
1186 if (APIC_CHECK_RESERVE_VECTORS(i))
1187 continue;
1188 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) {
1189 apic_vector_to_irq[i] = (uchar_t)irq;
1190 ASSERT(i >= 0 && i <= UCHAR_MAX);
1191 return ((uchar_t)i);
1192 }
1193 }
1194
1195 return (0);
1196 }
1197
1198 /* Mark vector as not being used by any irq */
1199 void
apic_free_vector(uchar_t vector)1200 apic_free_vector(uchar_t vector)
1201 {
1202 apic_vector_to_irq[vector] = APIC_RESV_IRQ;
1203 }
1204
1205 /*
1206 * Call rebind to do the actual programming.
1207 * Must be called with interrupts disabled and apic_ioapic_lock held
1208 * 'p' is polymorphic -- if this function is called to process a deferred
1209 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which
1210 * the irq pointer is retrieved. If not doing deferred reprogramming,
1211 * p is of the type 'apic_irq_t *'.
1212 *
1213 * apic_ioapic_lock must be held across this call, as it protects apic_rebind
1214 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be
1215 * taken offline after a cpu is selected, but before apic_rebind is called to
1216 * bind interrupts to it.
1217 */
1218 int
apic_setup_io_intr(void * p,int irq,boolean_t deferred)1219 apic_setup_io_intr(void *p, int irq, boolean_t deferred)
1220 {
1221 apic_irq_t *irqptr;
1222 struct ioapic_reprogram_data *drep = NULL;
1223 int rv;
1224
1225 if (deferred) {
1226 drep = (struct ioapic_reprogram_data *)p;
1227 ASSERT(drep != NULL);
1228 irqptr = drep->irqp;
1229 } else
1230 irqptr = (apic_irq_t *)p;
1231
1232 ASSERT(irqptr != NULL);
1233
1234 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep);
1235 if (rv) {
1236 /*
1237 * CPU is not up or interrupts are disabled. Fall back to
1238 * the first available CPU
1239 */
1240 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE),
1241 drep);
1242 }
1243
1244 return (rv);
1245 }
1246
1247
1248 uchar_t
apic_modify_vector(uchar_t vector,int irq)1249 apic_modify_vector(uchar_t vector, int irq)
1250 {
1251 apic_vector_to_irq[vector] = (uchar_t)irq;
1252 return (vector);
1253 }
1254
1255 char *
apic_get_apic_type(void)1256 apic_get_apic_type(void)
1257 {
1258 return (apic_psm_info.p_mach_idstring);
1259 }
1260
1261 void
apic_switch_ipi_callback(boolean_t enter)1262 apic_switch_ipi_callback(boolean_t enter)
1263 {
1264 ASSERT(enter == B_TRUE);
1265 }
1266
1267 int
apic_detect_x2apic(void)1268 apic_detect_x2apic(void)
1269 {
1270 return (0);
1271 }
1272
1273 void
apic_enable_x2apic(void)1274 apic_enable_x2apic(void)
1275 {
1276 cmn_err(CE_PANIC, "apic_enable_x2apic() called in pcplusmp");
1277 }
1278
1279 void
x2apic_update_psm(void)1280 x2apic_update_psm(void)
1281 {
1282 cmn_err(CE_PANIC, "x2apic_update_psm() called in pcplusmp");
1283 }
1284