1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Audio and Music Data Transmission Protocol (IEC 61883-6) streams
4 * with Common Isochronous Packet (IEC 61883-1) headers
5 *
6 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
7 */
8
9 #include <linux/device.h>
10 #include <linux/err.h>
11 #include <linux/firewire.h>
12 #include <linux/firewire-constants.h>
13 #include <linux/module.h>
14 #include <linux/slab.h>
15 #include <sound/pcm.h>
16 #include <sound/pcm_params.h>
17 #include "amdtp-stream.h"
18
19 #define TICKS_PER_CYCLE 3072
20 #define CYCLES_PER_SECOND 8000
21 #define TICKS_PER_SECOND (TICKS_PER_CYCLE * CYCLES_PER_SECOND)
22
23 #define OHCI_SECOND_MODULUS 8
24
25 /* Always support Linux tracing subsystem. */
26 #define CREATE_TRACE_POINTS
27 #include "amdtp-stream-trace.h"
28
29 #define TRANSFER_DELAY_TICKS 0x2e00 /* 479.17 microseconds */
30
31 /* isochronous header parameters */
32 #define ISO_DATA_LENGTH_SHIFT 16
33 #define TAG_NO_CIP_HEADER 0
34 #define TAG_CIP 1
35
36 // Common Isochronous Packet (CIP) header parameters. Use two quadlets CIP header when supported.
37 #define CIP_HEADER_QUADLETS 2
38 #define CIP_EOH_SHIFT 31
39 #define CIP_EOH (1u << CIP_EOH_SHIFT)
40 #define CIP_EOH_MASK 0x80000000
41 #define CIP_SID_SHIFT 24
42 #define CIP_SID_MASK 0x3f000000
43 #define CIP_DBS_MASK 0x00ff0000
44 #define CIP_DBS_SHIFT 16
45 #define CIP_SPH_MASK 0x00000400
46 #define CIP_SPH_SHIFT 10
47 #define CIP_DBC_MASK 0x000000ff
48 #define CIP_FMT_SHIFT 24
49 #define CIP_FMT_MASK 0x3f000000
50 #define CIP_FDF_MASK 0x00ff0000
51 #define CIP_FDF_SHIFT 16
52 #define CIP_FDF_NO_DATA 0xff
53 #define CIP_SYT_MASK 0x0000ffff
54 #define CIP_SYT_NO_INFO 0xffff
55 #define CIP_SYT_CYCLE_MODULUS 16
56 #define CIP_NO_DATA ((CIP_FDF_NO_DATA << CIP_FDF_SHIFT) | CIP_SYT_NO_INFO)
57
58 #define CIP_HEADER_SIZE (sizeof(__be32) * CIP_HEADER_QUADLETS)
59
60 /* Audio and Music transfer protocol specific parameters */
61 #define CIP_FMT_AM 0x10
62 #define AMDTP_FDF_NO_DATA 0xff
63
64 // For iso header and tstamp.
65 #define IR_CTX_HEADER_DEFAULT_QUADLETS 2
66 // Add nothing.
67 #define IR_CTX_HEADER_SIZE_NO_CIP (sizeof(__be32) * IR_CTX_HEADER_DEFAULT_QUADLETS)
68 // Add two quadlets CIP header.
69 #define IR_CTX_HEADER_SIZE_CIP (IR_CTX_HEADER_SIZE_NO_CIP + CIP_HEADER_SIZE)
70 #define HEADER_TSTAMP_MASK 0x0000ffff
71
72 #define IT_PKT_HEADER_SIZE_CIP CIP_HEADER_SIZE
73 #define IT_PKT_HEADER_SIZE_NO_CIP 0 // Nothing.
74
75 // The initial firmware of OXFW970 can postpone transmission of packet during finishing
76 // asynchronous transaction. This module accepts 5 cycles to skip as maximum to avoid buffer
77 // overrun. Actual device can skip more, then this module stops the packet streaming.
78 #define IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES 5
79
80 static void pcm_period_work(struct work_struct *work);
81
82 /**
83 * amdtp_stream_init - initialize an AMDTP stream structure
84 * @s: the AMDTP stream to initialize
85 * @unit: the target of the stream
86 * @dir: the direction of stream
87 * @flags: the details of the streaming protocol consist of cip_flags enumeration-constants.
88 * @fmt: the value of fmt field in CIP header
89 * @process_ctx_payloads: callback handler to process payloads of isoc context
90 * @protocol_size: the size to allocate newly for protocol
91 */
amdtp_stream_init(struct amdtp_stream * s,struct fw_unit * unit,enum amdtp_stream_direction dir,unsigned int flags,unsigned int fmt,amdtp_stream_process_ctx_payloads_t process_ctx_payloads,unsigned int protocol_size)92 int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit,
93 enum amdtp_stream_direction dir, unsigned int flags,
94 unsigned int fmt,
95 amdtp_stream_process_ctx_payloads_t process_ctx_payloads,
96 unsigned int protocol_size)
97 {
98 if (process_ctx_payloads == NULL)
99 return -EINVAL;
100
101 s->protocol = kzalloc(protocol_size, GFP_KERNEL);
102 if (!s->protocol)
103 return -ENOMEM;
104
105 s->unit = unit;
106 s->direction = dir;
107 s->flags = flags;
108 s->context = ERR_PTR(-1);
109 mutex_init(&s->mutex);
110 INIT_WORK(&s->period_work, pcm_period_work);
111 s->packet_index = 0;
112
113 init_waitqueue_head(&s->ready_wait);
114
115 s->fmt = fmt;
116 s->process_ctx_payloads = process_ctx_payloads;
117
118 return 0;
119 }
120 EXPORT_SYMBOL(amdtp_stream_init);
121
122 /**
123 * amdtp_stream_destroy - free stream resources
124 * @s: the AMDTP stream to destroy
125 */
amdtp_stream_destroy(struct amdtp_stream * s)126 void amdtp_stream_destroy(struct amdtp_stream *s)
127 {
128 /* Not initialized. */
129 if (s->protocol == NULL)
130 return;
131
132 WARN_ON(amdtp_stream_running(s));
133 kfree(s->protocol);
134 mutex_destroy(&s->mutex);
135 }
136 EXPORT_SYMBOL(amdtp_stream_destroy);
137
138 const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT] = {
139 [CIP_SFC_32000] = 8,
140 [CIP_SFC_44100] = 8,
141 [CIP_SFC_48000] = 8,
142 [CIP_SFC_88200] = 16,
143 [CIP_SFC_96000] = 16,
144 [CIP_SFC_176400] = 32,
145 [CIP_SFC_192000] = 32,
146 };
147 EXPORT_SYMBOL(amdtp_syt_intervals);
148
149 const unsigned int amdtp_rate_table[CIP_SFC_COUNT] = {
150 [CIP_SFC_32000] = 32000,
151 [CIP_SFC_44100] = 44100,
152 [CIP_SFC_48000] = 48000,
153 [CIP_SFC_88200] = 88200,
154 [CIP_SFC_96000] = 96000,
155 [CIP_SFC_176400] = 176400,
156 [CIP_SFC_192000] = 192000,
157 };
158 EXPORT_SYMBOL(amdtp_rate_table);
159
apply_constraint_to_size(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)160 static int apply_constraint_to_size(struct snd_pcm_hw_params *params,
161 struct snd_pcm_hw_rule *rule)
162 {
163 struct snd_interval *s = hw_param_interval(params, rule->var);
164 const struct snd_interval *r =
165 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE);
166 struct snd_interval t = {0};
167 unsigned int step = 0;
168 int i;
169
170 for (i = 0; i < CIP_SFC_COUNT; ++i) {
171 if (snd_interval_test(r, amdtp_rate_table[i]))
172 step = max(step, amdtp_syt_intervals[i]);
173 }
174
175 t.min = roundup(s->min, step);
176 t.max = rounddown(s->max, step);
177 t.integer = 1;
178
179 return snd_interval_refine(s, &t);
180 }
181
182 /**
183 * amdtp_stream_add_pcm_hw_constraints - add hw constraints for PCM substream
184 * @s: the AMDTP stream, which must be initialized.
185 * @runtime: the PCM substream runtime
186 */
amdtp_stream_add_pcm_hw_constraints(struct amdtp_stream * s,struct snd_pcm_runtime * runtime)187 int amdtp_stream_add_pcm_hw_constraints(struct amdtp_stream *s,
188 struct snd_pcm_runtime *runtime)
189 {
190 struct snd_pcm_hardware *hw = &runtime->hw;
191 unsigned int ctx_header_size;
192 unsigned int maximum_usec_per_period;
193 int err;
194
195 hw->info = SNDRV_PCM_INFO_BLOCK_TRANSFER |
196 SNDRV_PCM_INFO_INTERLEAVED |
197 SNDRV_PCM_INFO_JOINT_DUPLEX |
198 SNDRV_PCM_INFO_MMAP |
199 SNDRV_PCM_INFO_MMAP_VALID |
200 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP;
201
202 hw->periods_min = 2;
203 hw->periods_max = UINT_MAX;
204
205 /* bytes for a frame */
206 hw->period_bytes_min = 4 * hw->channels_max;
207
208 /* Just to prevent from allocating much pages. */
209 hw->period_bytes_max = hw->period_bytes_min * 2048;
210 hw->buffer_bytes_max = hw->period_bytes_max * hw->periods_min;
211
212 // Linux driver for 1394 OHCI controller voluntarily flushes isoc
213 // context when total size of accumulated context header reaches
214 // PAGE_SIZE. This kicks work for the isoc context and brings
215 // callback in the middle of scheduled interrupts.
216 // Although AMDTP streams in the same domain use the same events per
217 // IRQ, use the largest size of context header between IT/IR contexts.
218 // Here, use the value of context header in IR context is for both
219 // contexts.
220 if (!(s->flags & CIP_NO_HEADER))
221 ctx_header_size = IR_CTX_HEADER_SIZE_CIP;
222 else
223 ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP;
224 maximum_usec_per_period = USEC_PER_SEC * PAGE_SIZE /
225 CYCLES_PER_SECOND / ctx_header_size;
226
227 // In IEC 61883-6, one isoc packet can transfer events up to the value
228 // of syt interval. This comes from the interval of isoc cycle. As 1394
229 // OHCI controller can generate hardware IRQ per isoc packet, the
230 // interval is 125 usec.
231 // However, there are two ways of transmission in IEC 61883-6; blocking
232 // and non-blocking modes. In blocking mode, the sequence of isoc packet
233 // includes 'empty' or 'NODATA' packets which include no event. In
234 // non-blocking mode, the number of events per packet is variable up to
235 // the syt interval.
236 // Due to the above protocol design, the minimum PCM frames per
237 // interrupt should be double of the value of syt interval, thus it is
238 // 250 usec.
239 err = snd_pcm_hw_constraint_minmax(runtime,
240 SNDRV_PCM_HW_PARAM_PERIOD_TIME,
241 250, maximum_usec_per_period);
242 if (err < 0)
243 goto end;
244
245 /* Non-Blocking stream has no more constraints */
246 if (!(s->flags & CIP_BLOCKING))
247 goto end;
248
249 /*
250 * One AMDTP packet can include some frames. In blocking mode, the
251 * number equals to SYT_INTERVAL. So the number is 8, 16 or 32,
252 * depending on its sampling rate. For accurate period interrupt, it's
253 * preferrable to align period/buffer sizes to current SYT_INTERVAL.
254 */
255 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
256 apply_constraint_to_size, NULL,
257 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
258 SNDRV_PCM_HW_PARAM_RATE, -1);
259 if (err < 0)
260 goto end;
261 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
262 apply_constraint_to_size, NULL,
263 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
264 SNDRV_PCM_HW_PARAM_RATE, -1);
265 if (err < 0)
266 goto end;
267 end:
268 return err;
269 }
270 EXPORT_SYMBOL(amdtp_stream_add_pcm_hw_constraints);
271
272 /**
273 * amdtp_stream_set_parameters - set stream parameters
274 * @s: the AMDTP stream to configure
275 * @rate: the sample rate
276 * @data_block_quadlets: the size of a data block in quadlet unit
277 * @pcm_frame_multiplier: the multiplier to compute the number of PCM frames by the number of AMDTP
278 * events.
279 *
280 * The parameters must be set before the stream is started, and must not be
281 * changed while the stream is running.
282 */
amdtp_stream_set_parameters(struct amdtp_stream * s,unsigned int rate,unsigned int data_block_quadlets,unsigned int pcm_frame_multiplier)283 int amdtp_stream_set_parameters(struct amdtp_stream *s, unsigned int rate,
284 unsigned int data_block_quadlets, unsigned int pcm_frame_multiplier)
285 {
286 unsigned int sfc;
287
288 for (sfc = 0; sfc < ARRAY_SIZE(amdtp_rate_table); ++sfc) {
289 if (amdtp_rate_table[sfc] == rate)
290 break;
291 }
292 if (sfc == ARRAY_SIZE(amdtp_rate_table))
293 return -EINVAL;
294
295 s->sfc = sfc;
296 s->data_block_quadlets = data_block_quadlets;
297 s->syt_interval = amdtp_syt_intervals[sfc];
298
299 // default buffering in the device.
300 s->transfer_delay = TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE;
301
302 // additional buffering needed to adjust for no-data packets.
303 if (s->flags & CIP_BLOCKING)
304 s->transfer_delay += TICKS_PER_SECOND * s->syt_interval / rate;
305
306 s->pcm_frame_multiplier = pcm_frame_multiplier;
307
308 return 0;
309 }
310 EXPORT_SYMBOL(amdtp_stream_set_parameters);
311
312 // The CIP header is processed in context header apart from context payload.
amdtp_stream_get_max_ctx_payload_size(struct amdtp_stream * s)313 static int amdtp_stream_get_max_ctx_payload_size(struct amdtp_stream *s)
314 {
315 unsigned int multiplier;
316
317 if (s->flags & CIP_JUMBO_PAYLOAD)
318 multiplier = IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES;
319 else
320 multiplier = 1;
321
322 return s->syt_interval * s->data_block_quadlets * sizeof(__be32) * multiplier;
323 }
324
325 /**
326 * amdtp_stream_get_max_payload - get the stream's packet size
327 * @s: the AMDTP stream
328 *
329 * This function must not be called before the stream has been configured
330 * with amdtp_stream_set_parameters().
331 */
amdtp_stream_get_max_payload(struct amdtp_stream * s)332 unsigned int amdtp_stream_get_max_payload(struct amdtp_stream *s)
333 {
334 unsigned int cip_header_size;
335
336 if (!(s->flags & CIP_NO_HEADER))
337 cip_header_size = CIP_HEADER_SIZE;
338 else
339 cip_header_size = 0;
340
341 return cip_header_size + amdtp_stream_get_max_ctx_payload_size(s);
342 }
343 EXPORT_SYMBOL(amdtp_stream_get_max_payload);
344
345 /**
346 * amdtp_stream_pcm_prepare - prepare PCM device for running
347 * @s: the AMDTP stream
348 *
349 * This function should be called from the PCM device's .prepare callback.
350 */
amdtp_stream_pcm_prepare(struct amdtp_stream * s)351 void amdtp_stream_pcm_prepare(struct amdtp_stream *s)
352 {
353 cancel_work_sync(&s->period_work);
354 s->pcm_buffer_pointer = 0;
355 s->pcm_period_pointer = 0;
356 }
357 EXPORT_SYMBOL(amdtp_stream_pcm_prepare);
358
359 #define prev_packet_desc(s, desc) \
360 list_prev_entry_circular(desc, &s->packet_descs_list, link)
361
pool_blocking_data_blocks(struct amdtp_stream * s,struct seq_desc * descs,unsigned int size,unsigned int pos,unsigned int count)362 static void pool_blocking_data_blocks(struct amdtp_stream *s, struct seq_desc *descs,
363 unsigned int size, unsigned int pos, unsigned int count)
364 {
365 const unsigned int syt_interval = s->syt_interval;
366 int i;
367
368 for (i = 0; i < count; ++i) {
369 struct seq_desc *desc = descs + pos;
370
371 if (desc->syt_offset != CIP_SYT_NO_INFO)
372 desc->data_blocks = syt_interval;
373 else
374 desc->data_blocks = 0;
375
376 pos = (pos + 1) % size;
377 }
378 }
379
pool_ideal_nonblocking_data_blocks(struct amdtp_stream * s,struct seq_desc * descs,unsigned int size,unsigned int pos,unsigned int count)380 static void pool_ideal_nonblocking_data_blocks(struct amdtp_stream *s, struct seq_desc *descs,
381 unsigned int size, unsigned int pos,
382 unsigned int count)
383 {
384 const enum cip_sfc sfc = s->sfc;
385 unsigned int state = s->ctx_data.rx.data_block_state;
386 int i;
387
388 for (i = 0; i < count; ++i) {
389 struct seq_desc *desc = descs + pos;
390
391 if (!cip_sfc_is_base_44100(sfc)) {
392 // Sample_rate / 8000 is an integer, and precomputed.
393 desc->data_blocks = state;
394 } else {
395 unsigned int phase = state;
396
397 /*
398 * This calculates the number of data blocks per packet so that
399 * 1) the overall rate is correct and exactly synchronized to
400 * the bus clock, and
401 * 2) packets with a rounded-up number of blocks occur as early
402 * as possible in the sequence (to prevent underruns of the
403 * device's buffer).
404 */
405 if (sfc == CIP_SFC_44100)
406 /* 6 6 5 6 5 6 5 ... */
407 desc->data_blocks = 5 + ((phase & 1) ^ (phase == 0 || phase >= 40));
408 else
409 /* 12 11 11 11 11 ... or 23 22 22 22 22 ... */
410 desc->data_blocks = 11 * (sfc >> 1) + (phase == 0);
411 if (++phase >= (80 >> (sfc >> 1)))
412 phase = 0;
413 state = phase;
414 }
415
416 pos = (pos + 1) % size;
417 }
418
419 s->ctx_data.rx.data_block_state = state;
420 }
421
calculate_syt_offset(unsigned int * last_syt_offset,unsigned int * syt_offset_state,enum cip_sfc sfc)422 static unsigned int calculate_syt_offset(unsigned int *last_syt_offset,
423 unsigned int *syt_offset_state, enum cip_sfc sfc)
424 {
425 unsigned int syt_offset;
426
427 if (*last_syt_offset < TICKS_PER_CYCLE) {
428 if (!cip_sfc_is_base_44100(sfc))
429 syt_offset = *last_syt_offset + *syt_offset_state;
430 else {
431 /*
432 * The time, in ticks, of the n'th SYT_INTERVAL sample is:
433 * n * SYT_INTERVAL * 24576000 / sample_rate
434 * Modulo TICKS_PER_CYCLE, the difference between successive
435 * elements is about 1386.23. Rounding the results of this
436 * formula to the SYT precision results in a sequence of
437 * differences that begins with:
438 * 1386 1386 1387 1386 1386 1386 1387 1386 1386 1386 1387 ...
439 * This code generates _exactly_ the same sequence.
440 */
441 unsigned int phase = *syt_offset_state;
442 unsigned int index = phase % 13;
443
444 syt_offset = *last_syt_offset;
445 syt_offset += 1386 + ((index && !(index & 3)) ||
446 phase == 146);
447 if (++phase >= 147)
448 phase = 0;
449 *syt_offset_state = phase;
450 }
451 } else
452 syt_offset = *last_syt_offset - TICKS_PER_CYCLE;
453 *last_syt_offset = syt_offset;
454
455 if (syt_offset >= TICKS_PER_CYCLE)
456 syt_offset = CIP_SYT_NO_INFO;
457
458 return syt_offset;
459 }
460
pool_ideal_syt_offsets(struct amdtp_stream * s,struct seq_desc * descs,unsigned int size,unsigned int pos,unsigned int count)461 static void pool_ideal_syt_offsets(struct amdtp_stream *s, struct seq_desc *descs,
462 unsigned int size, unsigned int pos, unsigned int count)
463 {
464 const enum cip_sfc sfc = s->sfc;
465 unsigned int last = s->ctx_data.rx.last_syt_offset;
466 unsigned int state = s->ctx_data.rx.syt_offset_state;
467 int i;
468
469 for (i = 0; i < count; ++i) {
470 struct seq_desc *desc = descs + pos;
471
472 desc->syt_offset = calculate_syt_offset(&last, &state, sfc);
473
474 pos = (pos + 1) % size;
475 }
476
477 s->ctx_data.rx.last_syt_offset = last;
478 s->ctx_data.rx.syt_offset_state = state;
479 }
480
compute_syt_offset(unsigned int syt,unsigned int cycle,unsigned int transfer_delay)481 static unsigned int compute_syt_offset(unsigned int syt, unsigned int cycle,
482 unsigned int transfer_delay)
483 {
484 unsigned int cycle_lo = (cycle % CYCLES_PER_SECOND) & 0x0f;
485 unsigned int syt_cycle_lo = (syt & 0xf000) >> 12;
486 unsigned int syt_offset;
487
488 // Round up.
489 if (syt_cycle_lo < cycle_lo)
490 syt_cycle_lo += CIP_SYT_CYCLE_MODULUS;
491 syt_cycle_lo -= cycle_lo;
492
493 // Subtract transfer delay so that the synchronization offset is not so large
494 // at transmission.
495 syt_offset = syt_cycle_lo * TICKS_PER_CYCLE + (syt & 0x0fff);
496 if (syt_offset < transfer_delay)
497 syt_offset += CIP_SYT_CYCLE_MODULUS * TICKS_PER_CYCLE;
498
499 return syt_offset - transfer_delay;
500 }
501
502 // Both of the producer and consumer of the queue runs in the same clock of IEEE 1394 bus.
503 // Additionally, the sequence of tx packets is severely checked against any discontinuity
504 // before filling entries in the queue. The calculation is safe even if it looks fragile by
505 // overrun.
calculate_cached_cycle_count(struct amdtp_stream * s,unsigned int head)506 static unsigned int calculate_cached_cycle_count(struct amdtp_stream *s, unsigned int head)
507 {
508 const unsigned int cache_size = s->ctx_data.tx.cache.size;
509 unsigned int cycles = s->ctx_data.tx.cache.pos;
510
511 if (cycles < head)
512 cycles += cache_size;
513 cycles -= head;
514
515 return cycles;
516 }
517
cache_seq(struct amdtp_stream * s,const struct pkt_desc * src,unsigned int desc_count)518 static void cache_seq(struct amdtp_stream *s, const struct pkt_desc *src, unsigned int desc_count)
519 {
520 const unsigned int transfer_delay = s->transfer_delay;
521 const unsigned int cache_size = s->ctx_data.tx.cache.size;
522 struct seq_desc *cache = s->ctx_data.tx.cache.descs;
523 unsigned int cache_pos = s->ctx_data.tx.cache.pos;
524 bool aware_syt = !(s->flags & CIP_UNAWARE_SYT);
525 int i;
526
527 for (i = 0; i < desc_count; ++i) {
528 struct seq_desc *dst = cache + cache_pos;
529
530 if (aware_syt && src->syt != CIP_SYT_NO_INFO)
531 dst->syt_offset = compute_syt_offset(src->syt, src->cycle, transfer_delay);
532 else
533 dst->syt_offset = CIP_SYT_NO_INFO;
534 dst->data_blocks = src->data_blocks;
535
536 cache_pos = (cache_pos + 1) % cache_size;
537 src = amdtp_stream_next_packet_desc(s, src);
538 }
539
540 s->ctx_data.tx.cache.pos = cache_pos;
541 }
542
pool_ideal_seq_descs(struct amdtp_stream * s,struct seq_desc * descs,unsigned int size,unsigned int pos,unsigned int count)543 static void pool_ideal_seq_descs(struct amdtp_stream *s, struct seq_desc *descs, unsigned int size,
544 unsigned int pos, unsigned int count)
545 {
546 pool_ideal_syt_offsets(s, descs, size, pos, count);
547
548 if (s->flags & CIP_BLOCKING)
549 pool_blocking_data_blocks(s, descs, size, pos, count);
550 else
551 pool_ideal_nonblocking_data_blocks(s, descs, size, pos, count);
552 }
553
pool_replayed_seq(struct amdtp_stream * s,struct seq_desc * descs,unsigned int size,unsigned int pos,unsigned int count)554 static void pool_replayed_seq(struct amdtp_stream *s, struct seq_desc *descs, unsigned int size,
555 unsigned int pos, unsigned int count)
556 {
557 struct amdtp_stream *target = s->ctx_data.rx.replay_target;
558 const struct seq_desc *cache = target->ctx_data.tx.cache.descs;
559 const unsigned int cache_size = target->ctx_data.tx.cache.size;
560 unsigned int cache_pos = s->ctx_data.rx.cache_pos;
561 int i;
562
563 for (i = 0; i < count; ++i) {
564 descs[pos] = cache[cache_pos];
565 cache_pos = (cache_pos + 1) % cache_size;
566 pos = (pos + 1) % size;
567 }
568
569 s->ctx_data.rx.cache_pos = cache_pos;
570 }
571
pool_seq_descs(struct amdtp_stream * s,struct seq_desc * descs,unsigned int size,unsigned int pos,unsigned int count)572 static void pool_seq_descs(struct amdtp_stream *s, struct seq_desc *descs, unsigned int size,
573 unsigned int pos, unsigned int count)
574 {
575 struct amdtp_domain *d = s->domain;
576 void (*pool_seq_descs)(struct amdtp_stream *s, struct seq_desc *descs, unsigned int size,
577 unsigned int pos, unsigned int count);
578
579 if (!d->replay.enable || !s->ctx_data.rx.replay_target) {
580 pool_seq_descs = pool_ideal_seq_descs;
581 } else {
582 if (!d->replay.on_the_fly) {
583 pool_seq_descs = pool_replayed_seq;
584 } else {
585 struct amdtp_stream *tx = s->ctx_data.rx.replay_target;
586 const unsigned int cache_size = tx->ctx_data.tx.cache.size;
587 const unsigned int cache_pos = s->ctx_data.rx.cache_pos;
588 unsigned int cached_cycles = calculate_cached_cycle_count(tx, cache_pos);
589
590 if (cached_cycles > count && cached_cycles > cache_size / 2)
591 pool_seq_descs = pool_replayed_seq;
592 else
593 pool_seq_descs = pool_ideal_seq_descs;
594 }
595 }
596
597 pool_seq_descs(s, descs, size, pos, count);
598 }
599
update_pcm_pointers(struct amdtp_stream * s,struct snd_pcm_substream * pcm,unsigned int frames)600 static void update_pcm_pointers(struct amdtp_stream *s,
601 struct snd_pcm_substream *pcm,
602 unsigned int frames)
603 {
604 unsigned int ptr;
605
606 ptr = s->pcm_buffer_pointer + frames;
607 if (ptr >= pcm->runtime->buffer_size)
608 ptr -= pcm->runtime->buffer_size;
609 WRITE_ONCE(s->pcm_buffer_pointer, ptr);
610
611 s->pcm_period_pointer += frames;
612 if (s->pcm_period_pointer >= pcm->runtime->period_size) {
613 s->pcm_period_pointer -= pcm->runtime->period_size;
614
615 // The program in user process should periodically check the status of intermediate
616 // buffer associated to PCM substream to process PCM frames in the buffer, instead
617 // of receiving notification of period elapsed by poll wait.
618 if (!pcm->runtime->no_period_wakeup)
619 queue_work(system_highpri_wq, &s->period_work);
620 }
621 }
622
pcm_period_work(struct work_struct * work)623 static void pcm_period_work(struct work_struct *work)
624 {
625 struct amdtp_stream *s = container_of(work, struct amdtp_stream,
626 period_work);
627 struct snd_pcm_substream *pcm = READ_ONCE(s->pcm);
628
629 if (pcm)
630 snd_pcm_period_elapsed(pcm);
631 }
632
queue_packet(struct amdtp_stream * s,struct fw_iso_packet * params,bool sched_irq)633 static int queue_packet(struct amdtp_stream *s, struct fw_iso_packet *params,
634 bool sched_irq)
635 {
636 int err;
637
638 params->interrupt = sched_irq;
639 params->tag = s->tag;
640 params->sy = 0;
641
642 err = fw_iso_context_queue(s->context, params, &s->buffer.iso_buffer,
643 s->buffer.packets[s->packet_index].offset);
644 if (err < 0) {
645 dev_err(&s->unit->device, "queueing error: %d\n", err);
646 goto end;
647 }
648
649 if (++s->packet_index >= s->queue_size)
650 s->packet_index = 0;
651 end:
652 return err;
653 }
654
queue_out_packet(struct amdtp_stream * s,struct fw_iso_packet * params,bool sched_irq)655 static inline int queue_out_packet(struct amdtp_stream *s,
656 struct fw_iso_packet *params, bool sched_irq)
657 {
658 params->skip =
659 !!(params->header_length == 0 && params->payload_length == 0);
660 return queue_packet(s, params, sched_irq);
661 }
662
queue_in_packet(struct amdtp_stream * s,struct fw_iso_packet * params)663 static inline int queue_in_packet(struct amdtp_stream *s,
664 struct fw_iso_packet *params)
665 {
666 // Queue one packet for IR context.
667 params->header_length = s->ctx_data.tx.ctx_header_size;
668 params->payload_length = s->ctx_data.tx.max_ctx_payload_length;
669 params->skip = false;
670 return queue_packet(s, params, false);
671 }
672
generate_cip_header(struct amdtp_stream * s,__be32 cip_header[2],unsigned int data_block_counter,unsigned int syt)673 static void generate_cip_header(struct amdtp_stream *s, __be32 cip_header[2],
674 unsigned int data_block_counter, unsigned int syt)
675 {
676 cip_header[0] = cpu_to_be32(READ_ONCE(s->source_node_id_field) |
677 (s->data_block_quadlets << CIP_DBS_SHIFT) |
678 ((s->sph << CIP_SPH_SHIFT) & CIP_SPH_MASK) |
679 data_block_counter);
680 cip_header[1] = cpu_to_be32(CIP_EOH |
681 ((s->fmt << CIP_FMT_SHIFT) & CIP_FMT_MASK) |
682 ((s->ctx_data.rx.fdf << CIP_FDF_SHIFT) & CIP_FDF_MASK) |
683 (syt & CIP_SYT_MASK));
684 }
685
build_it_pkt_header(struct amdtp_stream * s,unsigned int cycle,struct fw_iso_packet * params,unsigned int header_length,unsigned int data_blocks,unsigned int data_block_counter,unsigned int syt,unsigned int index,u32 curr_cycle_time)686 static void build_it_pkt_header(struct amdtp_stream *s, unsigned int cycle,
687 struct fw_iso_packet *params, unsigned int header_length,
688 unsigned int data_blocks,
689 unsigned int data_block_counter,
690 unsigned int syt, unsigned int index, u32 curr_cycle_time)
691 {
692 unsigned int payload_length;
693 __be32 *cip_header;
694
695 payload_length = data_blocks * sizeof(__be32) * s->data_block_quadlets;
696 params->payload_length = payload_length;
697
698 if (header_length > 0) {
699 cip_header = (__be32 *)params->header;
700 generate_cip_header(s, cip_header, data_block_counter, syt);
701 params->header_length = header_length;
702 } else {
703 cip_header = NULL;
704 }
705
706 trace_amdtp_packet(s, cycle, cip_header, payload_length + header_length, data_blocks,
707 data_block_counter, s->packet_index, index, curr_cycle_time);
708 }
709
check_cip_header(struct amdtp_stream * s,const __be32 * buf,unsigned int payload_length,unsigned int * data_blocks,unsigned int * data_block_counter,unsigned int * syt)710 static int check_cip_header(struct amdtp_stream *s, const __be32 *buf,
711 unsigned int payload_length,
712 unsigned int *data_blocks,
713 unsigned int *data_block_counter, unsigned int *syt)
714 {
715 u32 cip_header[2];
716 unsigned int sph;
717 unsigned int fmt;
718 unsigned int fdf;
719 unsigned int dbc;
720 bool lost;
721
722 cip_header[0] = be32_to_cpu(buf[0]);
723 cip_header[1] = be32_to_cpu(buf[1]);
724
725 /*
726 * This module supports 'Two-quadlet CIP header with SYT field'.
727 * For convenience, also check FMT field is AM824 or not.
728 */
729 if ((((cip_header[0] & CIP_EOH_MASK) == CIP_EOH) ||
730 ((cip_header[1] & CIP_EOH_MASK) != CIP_EOH)) &&
731 (!(s->flags & CIP_HEADER_WITHOUT_EOH))) {
732 dev_info_ratelimited(&s->unit->device,
733 "Invalid CIP header for AMDTP: %08X:%08X\n",
734 cip_header[0], cip_header[1]);
735 return -EAGAIN;
736 }
737
738 /* Check valid protocol or not. */
739 sph = (cip_header[0] & CIP_SPH_MASK) >> CIP_SPH_SHIFT;
740 fmt = (cip_header[1] & CIP_FMT_MASK) >> CIP_FMT_SHIFT;
741 if (sph != s->sph || fmt != s->fmt) {
742 dev_info_ratelimited(&s->unit->device,
743 "Detect unexpected protocol: %08x %08x\n",
744 cip_header[0], cip_header[1]);
745 return -EAGAIN;
746 }
747
748 /* Calculate data blocks */
749 fdf = (cip_header[1] & CIP_FDF_MASK) >> CIP_FDF_SHIFT;
750 if (payload_length == 0 || (fmt == CIP_FMT_AM && fdf == AMDTP_FDF_NO_DATA)) {
751 *data_blocks = 0;
752 } else {
753 unsigned int data_block_quadlets =
754 (cip_header[0] & CIP_DBS_MASK) >> CIP_DBS_SHIFT;
755 /* avoid division by zero */
756 if (data_block_quadlets == 0) {
757 dev_err(&s->unit->device,
758 "Detect invalid value in dbs field: %08X\n",
759 cip_header[0]);
760 return -EPROTO;
761 }
762 if (s->flags & CIP_WRONG_DBS)
763 data_block_quadlets = s->data_block_quadlets;
764
765 *data_blocks = payload_length / sizeof(__be32) / data_block_quadlets;
766 }
767
768 /* Check data block counter continuity */
769 dbc = cip_header[0] & CIP_DBC_MASK;
770 if (*data_blocks == 0 && (s->flags & CIP_EMPTY_HAS_WRONG_DBC) &&
771 *data_block_counter != UINT_MAX)
772 dbc = *data_block_counter;
773
774 if ((dbc == 0x00 && (s->flags & CIP_SKIP_DBC_ZERO_CHECK)) ||
775 *data_block_counter == UINT_MAX) {
776 lost = false;
777 } else if (!(s->flags & CIP_DBC_IS_END_EVENT)) {
778 lost = dbc != *data_block_counter;
779 } else {
780 unsigned int dbc_interval;
781
782 if (!(s->flags & CIP_DBC_IS_PAYLOAD_QUADLETS)) {
783 if (*data_blocks > 0 && s->ctx_data.tx.dbc_interval > 0)
784 dbc_interval = s->ctx_data.tx.dbc_interval;
785 else
786 dbc_interval = *data_blocks;
787 } else {
788 dbc_interval = payload_length / sizeof(__be32);
789 }
790
791 lost = dbc != ((*data_block_counter + dbc_interval) & 0xff);
792 }
793
794 if (lost) {
795 dev_err(&s->unit->device,
796 "Detect discontinuity of CIP: %02X %02X\n",
797 *data_block_counter, dbc);
798 return -EIO;
799 }
800
801 *data_block_counter = dbc;
802
803 if (!(s->flags & CIP_UNAWARE_SYT))
804 *syt = cip_header[1] & CIP_SYT_MASK;
805
806 return 0;
807 }
808
parse_ir_ctx_header(struct amdtp_stream * s,unsigned int cycle,const __be32 * ctx_header,unsigned int * data_blocks,unsigned int * data_block_counter,unsigned int * syt,unsigned int packet_index,unsigned int index,u32 curr_cycle_time)809 static int parse_ir_ctx_header(struct amdtp_stream *s, unsigned int cycle,
810 const __be32 *ctx_header,
811 unsigned int *data_blocks,
812 unsigned int *data_block_counter,
813 unsigned int *syt, unsigned int packet_index, unsigned int index,
814 u32 curr_cycle_time)
815 {
816 unsigned int payload_length;
817 const __be32 *cip_header;
818 unsigned int cip_header_size;
819
820 payload_length = be32_to_cpu(ctx_header[0]) >> ISO_DATA_LENGTH_SHIFT;
821
822 if (!(s->flags & CIP_NO_HEADER))
823 cip_header_size = CIP_HEADER_SIZE;
824 else
825 cip_header_size = 0;
826
827 if (payload_length > cip_header_size + s->ctx_data.tx.max_ctx_payload_length) {
828 dev_err(&s->unit->device,
829 "Detect jumbo payload: %04x %04x\n",
830 payload_length, cip_header_size + s->ctx_data.tx.max_ctx_payload_length);
831 return -EIO;
832 }
833
834 if (cip_header_size > 0) {
835 if (payload_length >= cip_header_size) {
836 int err;
837
838 cip_header = ctx_header + IR_CTX_HEADER_DEFAULT_QUADLETS;
839 err = check_cip_header(s, cip_header, payload_length - cip_header_size,
840 data_blocks, data_block_counter, syt);
841 if (err < 0)
842 return err;
843 } else {
844 // Handle the cycle so that empty packet arrives.
845 cip_header = NULL;
846 *data_blocks = 0;
847 *syt = 0;
848 }
849 } else {
850 cip_header = NULL;
851 *data_blocks = payload_length / sizeof(__be32) / s->data_block_quadlets;
852 *syt = 0;
853
854 if (*data_block_counter == UINT_MAX)
855 *data_block_counter = 0;
856 }
857
858 trace_amdtp_packet(s, cycle, cip_header, payload_length, *data_blocks,
859 *data_block_counter, packet_index, index, curr_cycle_time);
860
861 return 0;
862 }
863
864 // In CYCLE_TIMER register of IEEE 1394, 7 bits are used to represent second. On
865 // the other hand, in DMA descriptors of 1394 OHCI, 3 bits are used to represent
866 // it. Thus, via Linux firewire subsystem, we can get the 3 bits for second.
compute_ohci_iso_ctx_cycle_count(u32 tstamp)867 static inline u32 compute_ohci_iso_ctx_cycle_count(u32 tstamp)
868 {
869 return (((tstamp >> 13) & 0x07) * CYCLES_PER_SECOND) + (tstamp & 0x1fff);
870 }
871
compute_ohci_cycle_count(__be32 ctx_header_tstamp)872 static inline u32 compute_ohci_cycle_count(__be32 ctx_header_tstamp)
873 {
874 u32 tstamp = be32_to_cpu(ctx_header_tstamp) & HEADER_TSTAMP_MASK;
875 return compute_ohci_iso_ctx_cycle_count(tstamp);
876 }
877
increment_ohci_cycle_count(u32 cycle,unsigned int addend)878 static inline u32 increment_ohci_cycle_count(u32 cycle, unsigned int addend)
879 {
880 cycle += addend;
881 if (cycle >= OHCI_SECOND_MODULUS * CYCLES_PER_SECOND)
882 cycle -= OHCI_SECOND_MODULUS * CYCLES_PER_SECOND;
883 return cycle;
884 }
885
decrement_ohci_cycle_count(u32 minuend,u32 subtrahend)886 static inline u32 decrement_ohci_cycle_count(u32 minuend, u32 subtrahend)
887 {
888 if (minuend < subtrahend)
889 minuend += OHCI_SECOND_MODULUS * CYCLES_PER_SECOND;
890
891 return minuend - subtrahend;
892 }
893
compare_ohci_cycle_count(u32 lval,u32 rval)894 static int compare_ohci_cycle_count(u32 lval, u32 rval)
895 {
896 if (lval == rval)
897 return 0;
898 else if (lval < rval && rval - lval < OHCI_SECOND_MODULUS * CYCLES_PER_SECOND / 2)
899 return -1;
900 else
901 return 1;
902 }
903
904 // Align to actual cycle count for the packet which is going to be scheduled.
905 // This module queued the same number of isochronous cycle as the size of queue
906 // to kip isochronous cycle, therefore it's OK to just increment the cycle by
907 // the size of queue for scheduled cycle.
compute_ohci_it_cycle(const __be32 ctx_header_tstamp,unsigned int queue_size)908 static inline u32 compute_ohci_it_cycle(const __be32 ctx_header_tstamp,
909 unsigned int queue_size)
910 {
911 u32 cycle = compute_ohci_cycle_count(ctx_header_tstamp);
912 return increment_ohci_cycle_count(cycle, queue_size);
913 }
914
generate_tx_packet_descs(struct amdtp_stream * s,struct pkt_desc * desc,const __be32 * ctx_header,unsigned int packet_count,unsigned int * desc_count)915 static int generate_tx_packet_descs(struct amdtp_stream *s, struct pkt_desc *desc,
916 const __be32 *ctx_header, unsigned int packet_count,
917 unsigned int *desc_count)
918 {
919 unsigned int next_cycle = s->next_cycle;
920 unsigned int dbc = s->data_block_counter;
921 unsigned int packet_index = s->packet_index;
922 unsigned int queue_size = s->queue_size;
923 u32 curr_cycle_time = 0;
924 int i;
925 int err;
926
927 if (trace_amdtp_packet_enabled())
928 (void)fw_card_read_cycle_time(fw_parent_device(s->unit)->card, &curr_cycle_time);
929
930 *desc_count = 0;
931 for (i = 0; i < packet_count; ++i) {
932 unsigned int cycle;
933 bool lost;
934 unsigned int data_blocks;
935 unsigned int syt;
936
937 cycle = compute_ohci_cycle_count(ctx_header[1]);
938 lost = (next_cycle != cycle);
939 if (lost) {
940 if (s->flags & CIP_NO_HEADER) {
941 // Fireface skips transmission just for an isoc cycle corresponding
942 // to empty packet.
943 unsigned int prev_cycle = next_cycle;
944
945 next_cycle = increment_ohci_cycle_count(next_cycle, 1);
946 lost = (next_cycle != cycle);
947 if (!lost) {
948 // Prepare a description for the skipped cycle for
949 // sequence replay.
950 desc->cycle = prev_cycle;
951 desc->syt = 0;
952 desc->data_blocks = 0;
953 desc->data_block_counter = dbc;
954 desc->ctx_payload = NULL;
955 desc = amdtp_stream_next_packet_desc(s, desc);
956 ++(*desc_count);
957 }
958 } else if (s->flags & CIP_JUMBO_PAYLOAD) {
959 // OXFW970 skips transmission for several isoc cycles during
960 // asynchronous transaction. The sequence replay is impossible due
961 // to the reason.
962 unsigned int safe_cycle = increment_ohci_cycle_count(next_cycle,
963 IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES);
964 lost = (compare_ohci_cycle_count(safe_cycle, cycle) < 0);
965 }
966 if (lost) {
967 dev_err(&s->unit->device, "Detect discontinuity of cycle: %d %d\n",
968 next_cycle, cycle);
969 return -EIO;
970 }
971 }
972
973 err = parse_ir_ctx_header(s, cycle, ctx_header, &data_blocks, &dbc, &syt,
974 packet_index, i, curr_cycle_time);
975 if (err < 0)
976 return err;
977
978 desc->cycle = cycle;
979 desc->syt = syt;
980 desc->data_blocks = data_blocks;
981 desc->data_block_counter = dbc;
982 desc->ctx_payload = s->buffer.packets[packet_index].buffer;
983
984 if (!(s->flags & CIP_DBC_IS_END_EVENT))
985 dbc = (dbc + desc->data_blocks) & 0xff;
986
987 next_cycle = increment_ohci_cycle_count(next_cycle, 1);
988 desc = amdtp_stream_next_packet_desc(s, desc);
989 ++(*desc_count);
990 ctx_header += s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header);
991 packet_index = (packet_index + 1) % queue_size;
992 }
993
994 s->next_cycle = next_cycle;
995 s->data_block_counter = dbc;
996
997 return 0;
998 }
999
compute_syt(unsigned int syt_offset,unsigned int cycle,unsigned int transfer_delay)1000 static unsigned int compute_syt(unsigned int syt_offset, unsigned int cycle,
1001 unsigned int transfer_delay)
1002 {
1003 unsigned int syt;
1004
1005 syt_offset += transfer_delay;
1006 syt = ((cycle + syt_offset / TICKS_PER_CYCLE) << 12) |
1007 (syt_offset % TICKS_PER_CYCLE);
1008 return syt & CIP_SYT_MASK;
1009 }
1010
generate_rx_packet_descs(struct amdtp_stream * s,struct pkt_desc * desc,const __be32 * ctx_header,unsigned int packet_count)1011 static void generate_rx_packet_descs(struct amdtp_stream *s, struct pkt_desc *desc,
1012 const __be32 *ctx_header, unsigned int packet_count)
1013 {
1014 struct seq_desc *seq_descs = s->ctx_data.rx.seq.descs;
1015 unsigned int seq_size = s->ctx_data.rx.seq.size;
1016 unsigned int seq_pos = s->ctx_data.rx.seq.pos;
1017 unsigned int dbc = s->data_block_counter;
1018 bool aware_syt = !(s->flags & CIP_UNAWARE_SYT);
1019 int i;
1020
1021 pool_seq_descs(s, seq_descs, seq_size, seq_pos, packet_count);
1022
1023 for (i = 0; i < packet_count; ++i) {
1024 unsigned int index = (s->packet_index + i) % s->queue_size;
1025 const struct seq_desc *seq = seq_descs + seq_pos;
1026
1027 desc->cycle = compute_ohci_it_cycle(*ctx_header, s->queue_size);
1028
1029 if (aware_syt && seq->syt_offset != CIP_SYT_NO_INFO)
1030 desc->syt = compute_syt(seq->syt_offset, desc->cycle, s->transfer_delay);
1031 else
1032 desc->syt = CIP_SYT_NO_INFO;
1033
1034 desc->data_blocks = seq->data_blocks;
1035
1036 if (s->flags & CIP_DBC_IS_END_EVENT)
1037 dbc = (dbc + desc->data_blocks) & 0xff;
1038
1039 desc->data_block_counter = dbc;
1040
1041 if (!(s->flags & CIP_DBC_IS_END_EVENT))
1042 dbc = (dbc + desc->data_blocks) & 0xff;
1043
1044 desc->ctx_payload = s->buffer.packets[index].buffer;
1045
1046 seq_pos = (seq_pos + 1) % seq_size;
1047 desc = amdtp_stream_next_packet_desc(s, desc);
1048
1049 ++ctx_header;
1050 }
1051
1052 s->data_block_counter = dbc;
1053 s->ctx_data.rx.seq.pos = seq_pos;
1054 }
1055
cancel_stream(struct amdtp_stream * s)1056 static inline void cancel_stream(struct amdtp_stream *s)
1057 {
1058 s->packet_index = -1;
1059 if (in_softirq())
1060 amdtp_stream_pcm_abort(s);
1061 WRITE_ONCE(s->pcm_buffer_pointer, SNDRV_PCM_POS_XRUN);
1062 }
1063
compute_pcm_extra_delay(struct amdtp_stream * s,const struct pkt_desc * desc,unsigned int count)1064 static snd_pcm_sframes_t compute_pcm_extra_delay(struct amdtp_stream *s,
1065 const struct pkt_desc *desc, unsigned int count)
1066 {
1067 unsigned int data_block_count = 0;
1068 u32 latest_cycle;
1069 u32 cycle_time;
1070 u32 curr_cycle;
1071 u32 cycle_gap;
1072 int i, err;
1073
1074 if (count == 0)
1075 goto end;
1076
1077 // Forward to the latest record.
1078 for (i = 0; i < count - 1; ++i)
1079 desc = amdtp_stream_next_packet_desc(s, desc);
1080 latest_cycle = desc->cycle;
1081
1082 err = fw_card_read_cycle_time(fw_parent_device(s->unit)->card, &cycle_time);
1083 if (err < 0)
1084 goto end;
1085
1086 // Compute cycle count with lower 3 bits of second field and cycle field like timestamp
1087 // format of 1394 OHCI isochronous context.
1088 curr_cycle = compute_ohci_iso_ctx_cycle_count((cycle_time >> 12) & 0x0000ffff);
1089
1090 if (s->direction == AMDTP_IN_STREAM) {
1091 // NOTE: The AMDTP packet descriptor should be for the past isochronous cycle since
1092 // it corresponds to arrived isochronous packet.
1093 if (compare_ohci_cycle_count(latest_cycle, curr_cycle) > 0)
1094 goto end;
1095 cycle_gap = decrement_ohci_cycle_count(curr_cycle, latest_cycle);
1096
1097 // NOTE: estimate delay by recent history of arrived AMDTP packets. The estimated
1098 // value expectedly corresponds to a few packets (0-2) since the packet arrived at
1099 // the most recent isochronous cycle has been already processed.
1100 for (i = 0; i < cycle_gap; ++i) {
1101 desc = amdtp_stream_next_packet_desc(s, desc);
1102 data_block_count += desc->data_blocks;
1103 }
1104 } else {
1105 // NOTE: The AMDTP packet descriptor should be for the future isochronous cycle
1106 // since it was already scheduled.
1107 if (compare_ohci_cycle_count(latest_cycle, curr_cycle) < 0)
1108 goto end;
1109 cycle_gap = decrement_ohci_cycle_count(latest_cycle, curr_cycle);
1110
1111 // NOTE: use history of scheduled packets.
1112 for (i = 0; i < cycle_gap; ++i) {
1113 data_block_count += desc->data_blocks;
1114 desc = prev_packet_desc(s, desc);
1115 }
1116 }
1117 end:
1118 return data_block_count * s->pcm_frame_multiplier;
1119 }
1120
process_ctx_payloads(struct amdtp_stream * s,const struct pkt_desc * desc,unsigned int count)1121 static void process_ctx_payloads(struct amdtp_stream *s,
1122 const struct pkt_desc *desc,
1123 unsigned int count)
1124 {
1125 struct snd_pcm_substream *pcm;
1126 int i;
1127
1128 pcm = READ_ONCE(s->pcm);
1129 s->process_ctx_payloads(s, desc, count, pcm);
1130
1131 if (pcm) {
1132 unsigned int data_block_count = 0;
1133
1134 pcm->runtime->delay = compute_pcm_extra_delay(s, desc, count);
1135
1136 for (i = 0; i < count; ++i) {
1137 data_block_count += desc->data_blocks;
1138 desc = amdtp_stream_next_packet_desc(s, desc);
1139 }
1140
1141 update_pcm_pointers(s, pcm, data_block_count * s->pcm_frame_multiplier);
1142 }
1143 }
1144
process_rx_packets(struct fw_iso_context * context,u32 tstamp,size_t header_length,void * header,void * private_data)1145 static void process_rx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1146 void *header, void *private_data)
1147 {
1148 struct amdtp_stream *s = private_data;
1149 const struct amdtp_domain *d = s->domain;
1150 const __be32 *ctx_header = header;
1151 const unsigned int events_per_period = d->events_per_period;
1152 unsigned int event_count = s->ctx_data.rx.event_count;
1153 struct pkt_desc *desc = s->packet_descs_cursor;
1154 unsigned int pkt_header_length;
1155 unsigned int packets;
1156 u32 curr_cycle_time;
1157 bool need_hw_irq;
1158 int i;
1159
1160 if (s->packet_index < 0)
1161 return;
1162
1163 // Calculate the number of packets in buffer and check XRUN.
1164 packets = header_length / sizeof(*ctx_header);
1165
1166 generate_rx_packet_descs(s, desc, ctx_header, packets);
1167
1168 process_ctx_payloads(s, desc, packets);
1169
1170 if (!(s->flags & CIP_NO_HEADER))
1171 pkt_header_length = IT_PKT_HEADER_SIZE_CIP;
1172 else
1173 pkt_header_length = 0;
1174
1175 if (s == d->irq_target) {
1176 // At NO_PERIOD_WAKEUP mode, the packets for all IT/IR contexts are processed by
1177 // the tasks of user process operating ALSA PCM character device by calling ioctl(2)
1178 // with some requests, instead of scheduled hardware IRQ of an IT context.
1179 struct snd_pcm_substream *pcm = READ_ONCE(s->pcm);
1180 need_hw_irq = !pcm || !pcm->runtime->no_period_wakeup;
1181 } else {
1182 need_hw_irq = false;
1183 }
1184
1185 if (trace_amdtp_packet_enabled())
1186 (void)fw_card_read_cycle_time(fw_parent_device(s->unit)->card, &curr_cycle_time);
1187
1188 for (i = 0; i < packets; ++i) {
1189 DEFINE_RAW_FLEX(struct fw_iso_packet, template, header, CIP_HEADER_QUADLETS);
1190 bool sched_irq = false;
1191
1192 build_it_pkt_header(s, desc->cycle, template, pkt_header_length,
1193 desc->data_blocks, desc->data_block_counter,
1194 desc->syt, i, curr_cycle_time);
1195
1196 if (s == s->domain->irq_target) {
1197 event_count += desc->data_blocks;
1198 if (event_count >= events_per_period) {
1199 event_count -= events_per_period;
1200 sched_irq = need_hw_irq;
1201 }
1202 }
1203
1204 if (queue_out_packet(s, template, sched_irq) < 0) {
1205 cancel_stream(s);
1206 return;
1207 }
1208
1209 desc = amdtp_stream_next_packet_desc(s, desc);
1210 }
1211
1212 s->ctx_data.rx.event_count = event_count;
1213 s->packet_descs_cursor = desc;
1214 }
1215
skip_rx_packets(struct fw_iso_context * context,u32 tstamp,size_t header_length,void * header,void * private_data)1216 static void skip_rx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1217 void *header, void *private_data)
1218 {
1219 struct amdtp_stream *s = private_data;
1220 struct amdtp_domain *d = s->domain;
1221 const __be32 *ctx_header = header;
1222 unsigned int packets;
1223 unsigned int cycle;
1224 int i;
1225
1226 if (s->packet_index < 0)
1227 return;
1228
1229 packets = header_length / sizeof(*ctx_header);
1230
1231 cycle = compute_ohci_it_cycle(ctx_header[packets - 1], s->queue_size);
1232 s->next_cycle = increment_ohci_cycle_count(cycle, 1);
1233
1234 for (i = 0; i < packets; ++i) {
1235 struct fw_iso_packet params = {
1236 .header_length = 0,
1237 .payload_length = 0,
1238 };
1239 bool sched_irq = (s == d->irq_target && i == packets - 1);
1240
1241 if (queue_out_packet(s, ¶ms, sched_irq) < 0) {
1242 cancel_stream(s);
1243 return;
1244 }
1245 }
1246 }
1247
1248 static void irq_target_callback(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1249 void *header, void *private_data);
1250
process_rx_packets_intermediately(struct fw_iso_context * context,u32 tstamp,size_t header_length,void * header,void * private_data)1251 static void process_rx_packets_intermediately(struct fw_iso_context *context, u32 tstamp,
1252 size_t header_length, void *header, void *private_data)
1253 {
1254 struct amdtp_stream *s = private_data;
1255 struct amdtp_domain *d = s->domain;
1256 __be32 *ctx_header = header;
1257 const unsigned int queue_size = s->queue_size;
1258 unsigned int packets;
1259 unsigned int offset;
1260
1261 if (s->packet_index < 0)
1262 return;
1263
1264 packets = header_length / sizeof(*ctx_header);
1265
1266 offset = 0;
1267 while (offset < packets) {
1268 unsigned int cycle = compute_ohci_it_cycle(ctx_header[offset], queue_size);
1269
1270 if (compare_ohci_cycle_count(cycle, d->processing_cycle.rx_start) >= 0)
1271 break;
1272
1273 ++offset;
1274 }
1275
1276 if (offset > 0) {
1277 unsigned int length = sizeof(*ctx_header) * offset;
1278
1279 skip_rx_packets(context, tstamp, length, ctx_header, private_data);
1280 if (amdtp_streaming_error(s))
1281 return;
1282
1283 ctx_header += offset;
1284 header_length -= length;
1285 }
1286
1287 if (offset < packets) {
1288 s->ready_processing = true;
1289 wake_up(&s->ready_wait);
1290
1291 if (d->replay.enable)
1292 s->ctx_data.rx.cache_pos = 0;
1293
1294 process_rx_packets(context, tstamp, header_length, ctx_header, private_data);
1295 if (amdtp_streaming_error(s))
1296 return;
1297
1298 if (s == d->irq_target)
1299 s->context->callback.sc = irq_target_callback;
1300 else
1301 s->context->callback.sc = process_rx_packets;
1302 }
1303 }
1304
process_tx_packets(struct fw_iso_context * context,u32 tstamp,size_t header_length,void * header,void * private_data)1305 static void process_tx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1306 void *header, void *private_data)
1307 {
1308 struct amdtp_stream *s = private_data;
1309 __be32 *ctx_header = header;
1310 struct pkt_desc *desc = s->packet_descs_cursor;
1311 unsigned int packet_count;
1312 unsigned int desc_count;
1313 int i;
1314 int err;
1315
1316 if (s->packet_index < 0)
1317 return;
1318
1319 // Calculate the number of packets in buffer and check XRUN.
1320 packet_count = header_length / s->ctx_data.tx.ctx_header_size;
1321
1322 desc_count = 0;
1323 err = generate_tx_packet_descs(s, desc, ctx_header, packet_count, &desc_count);
1324 if (err < 0) {
1325 if (err != -EAGAIN) {
1326 cancel_stream(s);
1327 return;
1328 }
1329 } else {
1330 struct amdtp_domain *d = s->domain;
1331
1332 process_ctx_payloads(s, desc, desc_count);
1333
1334 if (d->replay.enable)
1335 cache_seq(s, desc, desc_count);
1336
1337 for (i = 0; i < desc_count; ++i)
1338 desc = amdtp_stream_next_packet_desc(s, desc);
1339 s->packet_descs_cursor = desc;
1340 }
1341
1342 for (i = 0; i < packet_count; ++i) {
1343 struct fw_iso_packet params = {0};
1344
1345 if (queue_in_packet(s, ¶ms) < 0) {
1346 cancel_stream(s);
1347 return;
1348 }
1349 }
1350 }
1351
drop_tx_packets(struct fw_iso_context * context,u32 tstamp,size_t header_length,void * header,void * private_data)1352 static void drop_tx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1353 void *header, void *private_data)
1354 {
1355 struct amdtp_stream *s = private_data;
1356 const __be32 *ctx_header = header;
1357 unsigned int packets;
1358 unsigned int cycle;
1359 int i;
1360
1361 if (s->packet_index < 0)
1362 return;
1363
1364 packets = header_length / s->ctx_data.tx.ctx_header_size;
1365
1366 ctx_header += (packets - 1) * s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header);
1367 cycle = compute_ohci_cycle_count(ctx_header[1]);
1368 s->next_cycle = increment_ohci_cycle_count(cycle, 1);
1369
1370 for (i = 0; i < packets; ++i) {
1371 struct fw_iso_packet params = {0};
1372
1373 if (queue_in_packet(s, ¶ms) < 0) {
1374 cancel_stream(s);
1375 return;
1376 }
1377 }
1378 }
1379
process_tx_packets_intermediately(struct fw_iso_context * context,u32 tstamp,size_t header_length,void * header,void * private_data)1380 static void process_tx_packets_intermediately(struct fw_iso_context *context, u32 tstamp,
1381 size_t header_length, void *header, void *private_data)
1382 {
1383 struct amdtp_stream *s = private_data;
1384 struct amdtp_domain *d = s->domain;
1385 __be32 *ctx_header;
1386 unsigned int packets;
1387 unsigned int offset;
1388
1389 if (s->packet_index < 0)
1390 return;
1391
1392 packets = header_length / s->ctx_data.tx.ctx_header_size;
1393
1394 offset = 0;
1395 ctx_header = header;
1396 while (offset < packets) {
1397 unsigned int cycle = compute_ohci_cycle_count(ctx_header[1]);
1398
1399 if (compare_ohci_cycle_count(cycle, d->processing_cycle.tx_start) >= 0)
1400 break;
1401
1402 ctx_header += s->ctx_data.tx.ctx_header_size / sizeof(__be32);
1403 ++offset;
1404 }
1405
1406 ctx_header = header;
1407
1408 if (offset > 0) {
1409 size_t length = s->ctx_data.tx.ctx_header_size * offset;
1410
1411 drop_tx_packets(context, tstamp, length, ctx_header, s);
1412 if (amdtp_streaming_error(s))
1413 return;
1414
1415 ctx_header += length / sizeof(*ctx_header);
1416 header_length -= length;
1417 }
1418
1419 if (offset < packets) {
1420 s->ready_processing = true;
1421 wake_up(&s->ready_wait);
1422
1423 process_tx_packets(context, tstamp, header_length, ctx_header, s);
1424 if (amdtp_streaming_error(s))
1425 return;
1426
1427 context->callback.sc = process_tx_packets;
1428 }
1429 }
1430
drop_tx_packets_initially(struct fw_iso_context * context,u32 tstamp,size_t header_length,void * header,void * private_data)1431 static void drop_tx_packets_initially(struct fw_iso_context *context, u32 tstamp,
1432 size_t header_length, void *header, void *private_data)
1433 {
1434 struct amdtp_stream *s = private_data;
1435 struct amdtp_domain *d = s->domain;
1436 __be32 *ctx_header;
1437 unsigned int count;
1438 unsigned int events;
1439 int i;
1440
1441 if (s->packet_index < 0)
1442 return;
1443
1444 count = header_length / s->ctx_data.tx.ctx_header_size;
1445
1446 // Attempt to detect any event in the batch of packets.
1447 events = 0;
1448 ctx_header = header;
1449 for (i = 0; i < count; ++i) {
1450 unsigned int payload_quads =
1451 (be32_to_cpu(*ctx_header) >> ISO_DATA_LENGTH_SHIFT) / sizeof(__be32);
1452 unsigned int data_blocks;
1453
1454 if (s->flags & CIP_NO_HEADER) {
1455 data_blocks = payload_quads / s->data_block_quadlets;
1456 } else {
1457 __be32 *cip_headers = ctx_header + IR_CTX_HEADER_DEFAULT_QUADLETS;
1458
1459 if (payload_quads < CIP_HEADER_QUADLETS) {
1460 data_blocks = 0;
1461 } else {
1462 payload_quads -= CIP_HEADER_QUADLETS;
1463
1464 if (s->flags & CIP_UNAWARE_SYT) {
1465 data_blocks = payload_quads / s->data_block_quadlets;
1466 } else {
1467 u32 cip1 = be32_to_cpu(cip_headers[1]);
1468
1469 // NODATA packet can includes any data blocks but they are
1470 // not available as event.
1471 if ((cip1 & CIP_NO_DATA) == CIP_NO_DATA)
1472 data_blocks = 0;
1473 else
1474 data_blocks = payload_quads / s->data_block_quadlets;
1475 }
1476 }
1477 }
1478
1479 events += data_blocks;
1480
1481 ctx_header += s->ctx_data.tx.ctx_header_size / sizeof(__be32);
1482 }
1483
1484 drop_tx_packets(context, tstamp, header_length, header, s);
1485
1486 if (events > 0)
1487 s->ctx_data.tx.event_starts = true;
1488
1489 // Decide the cycle count to begin processing content of packet in IR contexts.
1490 {
1491 unsigned int stream_count = 0;
1492 unsigned int event_starts_count = 0;
1493 unsigned int cycle = UINT_MAX;
1494
1495 list_for_each_entry(s, &d->streams, list) {
1496 if (s->direction == AMDTP_IN_STREAM) {
1497 ++stream_count;
1498 if (s->ctx_data.tx.event_starts)
1499 ++event_starts_count;
1500 }
1501 }
1502
1503 if (stream_count == event_starts_count) {
1504 unsigned int next_cycle;
1505
1506 list_for_each_entry(s, &d->streams, list) {
1507 if (s->direction != AMDTP_IN_STREAM)
1508 continue;
1509
1510 next_cycle = increment_ohci_cycle_count(s->next_cycle,
1511 d->processing_cycle.tx_init_skip);
1512 if (cycle == UINT_MAX ||
1513 compare_ohci_cycle_count(next_cycle, cycle) > 0)
1514 cycle = next_cycle;
1515
1516 s->context->callback.sc = process_tx_packets_intermediately;
1517 }
1518
1519 d->processing_cycle.tx_start = cycle;
1520 }
1521 }
1522 }
1523
process_ctxs_in_domain(struct amdtp_domain * d)1524 static void process_ctxs_in_domain(struct amdtp_domain *d)
1525 {
1526 struct amdtp_stream *s;
1527
1528 list_for_each_entry(s, &d->streams, list) {
1529 if (s != d->irq_target && amdtp_stream_running(s))
1530 fw_iso_context_flush_completions(s->context);
1531
1532 if (amdtp_streaming_error(s))
1533 goto error;
1534 }
1535
1536 return;
1537 error:
1538 if (amdtp_stream_running(d->irq_target))
1539 cancel_stream(d->irq_target);
1540
1541 list_for_each_entry(s, &d->streams, list) {
1542 if (amdtp_stream_running(s))
1543 cancel_stream(s);
1544 }
1545 }
1546
irq_target_callback(struct fw_iso_context * context,u32 tstamp,size_t header_length,void * header,void * private_data)1547 static void irq_target_callback(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1548 void *header, void *private_data)
1549 {
1550 struct amdtp_stream *s = private_data;
1551 struct amdtp_domain *d = s->domain;
1552
1553 process_rx_packets(context, tstamp, header_length, header, private_data);
1554 process_ctxs_in_domain(d);
1555 }
1556
irq_target_callback_intermediately(struct fw_iso_context * context,u32 tstamp,size_t header_length,void * header,void * private_data)1557 static void irq_target_callback_intermediately(struct fw_iso_context *context, u32 tstamp,
1558 size_t header_length, void *header, void *private_data)
1559 {
1560 struct amdtp_stream *s = private_data;
1561 struct amdtp_domain *d = s->domain;
1562
1563 process_rx_packets_intermediately(context, tstamp, header_length, header, private_data);
1564 process_ctxs_in_domain(d);
1565 }
1566
irq_target_callback_skip(struct fw_iso_context * context,u32 tstamp,size_t header_length,void * header,void * private_data)1567 static void irq_target_callback_skip(struct fw_iso_context *context, u32 tstamp,
1568 size_t header_length, void *header, void *private_data)
1569 {
1570 struct amdtp_stream *s = private_data;
1571 struct amdtp_domain *d = s->domain;
1572 bool ready_to_start;
1573
1574 skip_rx_packets(context, tstamp, header_length, header, private_data);
1575 process_ctxs_in_domain(d);
1576
1577 if (d->replay.enable && !d->replay.on_the_fly) {
1578 unsigned int rx_count = 0;
1579 unsigned int rx_ready_count = 0;
1580 struct amdtp_stream *rx;
1581
1582 list_for_each_entry(rx, &d->streams, list) {
1583 struct amdtp_stream *tx;
1584 unsigned int cached_cycles;
1585
1586 if (rx->direction != AMDTP_OUT_STREAM)
1587 continue;
1588 ++rx_count;
1589
1590 tx = rx->ctx_data.rx.replay_target;
1591 cached_cycles = calculate_cached_cycle_count(tx, 0);
1592 if (cached_cycles > tx->ctx_data.tx.cache.size / 2)
1593 ++rx_ready_count;
1594 }
1595
1596 ready_to_start = (rx_count == rx_ready_count);
1597 } else {
1598 ready_to_start = true;
1599 }
1600
1601 // Decide the cycle count to begin processing content of packet in IT contexts. All of IT
1602 // contexts are expected to start and get callback when reaching here.
1603 if (ready_to_start) {
1604 unsigned int cycle = s->next_cycle;
1605 list_for_each_entry(s, &d->streams, list) {
1606 if (s->direction != AMDTP_OUT_STREAM)
1607 continue;
1608
1609 if (compare_ohci_cycle_count(s->next_cycle, cycle) > 0)
1610 cycle = s->next_cycle;
1611
1612 if (s == d->irq_target)
1613 s->context->callback.sc = irq_target_callback_intermediately;
1614 else
1615 s->context->callback.sc = process_rx_packets_intermediately;
1616 }
1617
1618 d->processing_cycle.rx_start = cycle;
1619 }
1620 }
1621
1622 // This is executed one time. For in-stream, first packet has come. For out-stream, prepared to
1623 // transmit first packet.
amdtp_stream_first_callback(struct fw_iso_context * context,u32 tstamp,size_t header_length,void * header,void * private_data)1624 static void amdtp_stream_first_callback(struct fw_iso_context *context,
1625 u32 tstamp, size_t header_length,
1626 void *header, void *private_data)
1627 {
1628 struct amdtp_stream *s = private_data;
1629 struct amdtp_domain *d = s->domain;
1630
1631 if (s->direction == AMDTP_IN_STREAM) {
1632 context->callback.sc = drop_tx_packets_initially;
1633 } else {
1634 if (s == d->irq_target)
1635 context->callback.sc = irq_target_callback_skip;
1636 else
1637 context->callback.sc = skip_rx_packets;
1638 }
1639
1640 context->callback.sc(context, tstamp, header_length, header, s);
1641 }
1642
1643 /**
1644 * amdtp_stream_start - start transferring packets
1645 * @s: the AMDTP stream to start
1646 * @channel: the isochronous channel on the bus
1647 * @speed: firewire speed code
1648 * @queue_size: The number of packets in the queue.
1649 * @idle_irq_interval: the interval to queue packet during initial state.
1650 *
1651 * The stream cannot be started until it has been configured with
1652 * amdtp_stream_set_parameters() and it must be started before any PCM or MIDI
1653 * device can be started.
1654 */
amdtp_stream_start(struct amdtp_stream * s,int channel,int speed,unsigned int queue_size,unsigned int idle_irq_interval)1655 static int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed,
1656 unsigned int queue_size, unsigned int idle_irq_interval)
1657 {
1658 bool is_irq_target = (s == s->domain->irq_target);
1659 unsigned int ctx_header_size;
1660 unsigned int max_ctx_payload_size;
1661 enum dma_data_direction dir;
1662 struct pkt_desc *descs;
1663 int i, type, tag, err;
1664
1665 mutex_lock(&s->mutex);
1666
1667 if (WARN_ON(amdtp_stream_running(s) ||
1668 (s->data_block_quadlets < 1))) {
1669 err = -EBADFD;
1670 goto err_unlock;
1671 }
1672
1673 if (s->direction == AMDTP_IN_STREAM) {
1674 // NOTE: IT context should be used for constant IRQ.
1675 if (is_irq_target) {
1676 err = -EINVAL;
1677 goto err_unlock;
1678 }
1679
1680 s->data_block_counter = UINT_MAX;
1681 } else {
1682 s->data_block_counter = 0;
1683 }
1684
1685 // initialize packet buffer.
1686 if (s->direction == AMDTP_IN_STREAM) {
1687 dir = DMA_FROM_DEVICE;
1688 type = FW_ISO_CONTEXT_RECEIVE;
1689 if (!(s->flags & CIP_NO_HEADER))
1690 ctx_header_size = IR_CTX_HEADER_SIZE_CIP;
1691 else
1692 ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP;
1693 } else {
1694 dir = DMA_TO_DEVICE;
1695 type = FW_ISO_CONTEXT_TRANSMIT;
1696 ctx_header_size = 0; // No effect for IT context.
1697 }
1698 max_ctx_payload_size = amdtp_stream_get_max_ctx_payload_size(s);
1699
1700 err = iso_packets_buffer_init(&s->buffer, s->unit, queue_size, max_ctx_payload_size, dir);
1701 if (err < 0)
1702 goto err_unlock;
1703 s->queue_size = queue_size;
1704
1705 s->context = fw_iso_context_create(fw_parent_device(s->unit)->card,
1706 type, channel, speed, ctx_header_size,
1707 amdtp_stream_first_callback, s);
1708 if (IS_ERR(s->context)) {
1709 err = PTR_ERR(s->context);
1710 if (err == -EBUSY)
1711 dev_err(&s->unit->device,
1712 "no free stream on this controller\n");
1713 goto err_buffer;
1714 }
1715
1716 amdtp_stream_update(s);
1717
1718 if (s->direction == AMDTP_IN_STREAM) {
1719 s->ctx_data.tx.max_ctx_payload_length = max_ctx_payload_size;
1720 s->ctx_data.tx.ctx_header_size = ctx_header_size;
1721 s->ctx_data.tx.event_starts = false;
1722
1723 if (s->domain->replay.enable) {
1724 // struct fw_iso_context.drop_overflow_headers is false therefore it's
1725 // possible to cache much unexpectedly.
1726 s->ctx_data.tx.cache.size = max_t(unsigned int, s->syt_interval * 2,
1727 queue_size * 3 / 2);
1728 s->ctx_data.tx.cache.pos = 0;
1729 s->ctx_data.tx.cache.descs = kcalloc(s->ctx_data.tx.cache.size,
1730 sizeof(*s->ctx_data.tx.cache.descs), GFP_KERNEL);
1731 if (!s->ctx_data.tx.cache.descs) {
1732 err = -ENOMEM;
1733 goto err_context;
1734 }
1735 }
1736 } else {
1737 static const struct {
1738 unsigned int data_block;
1739 unsigned int syt_offset;
1740 } *entry, initial_state[] = {
1741 [CIP_SFC_32000] = { 4, 3072 },
1742 [CIP_SFC_48000] = { 6, 1024 },
1743 [CIP_SFC_96000] = { 12, 1024 },
1744 [CIP_SFC_192000] = { 24, 1024 },
1745 [CIP_SFC_44100] = { 0, 67 },
1746 [CIP_SFC_88200] = { 0, 67 },
1747 [CIP_SFC_176400] = { 0, 67 },
1748 };
1749
1750 s->ctx_data.rx.seq.descs = kcalloc(queue_size, sizeof(*s->ctx_data.rx.seq.descs), GFP_KERNEL);
1751 if (!s->ctx_data.rx.seq.descs) {
1752 err = -ENOMEM;
1753 goto err_context;
1754 }
1755 s->ctx_data.rx.seq.size = queue_size;
1756 s->ctx_data.rx.seq.pos = 0;
1757
1758 entry = &initial_state[s->sfc];
1759 s->ctx_data.rx.data_block_state = entry->data_block;
1760 s->ctx_data.rx.syt_offset_state = entry->syt_offset;
1761 s->ctx_data.rx.last_syt_offset = TICKS_PER_CYCLE;
1762
1763 s->ctx_data.rx.event_count = 0;
1764 }
1765
1766 if (s->flags & CIP_NO_HEADER)
1767 s->tag = TAG_NO_CIP_HEADER;
1768 else
1769 s->tag = TAG_CIP;
1770
1771 // NOTE: When operating without hardIRQ/softIRQ, applications tends to call ioctl request
1772 // for runtime of PCM substream in the interval equivalent to the size of PCM buffer. It
1773 // could take a round over queue of AMDTP packet descriptors and small loss of history. For
1774 // safe, keep more 8 elements for the queue, equivalent to 1 ms.
1775 descs = kcalloc(s->queue_size + 8, sizeof(*descs), GFP_KERNEL);
1776 if (!descs) {
1777 err = -ENOMEM;
1778 goto err_context;
1779 }
1780 s->packet_descs = descs;
1781
1782 INIT_LIST_HEAD(&s->packet_descs_list);
1783 for (i = 0; i < s->queue_size; ++i) {
1784 INIT_LIST_HEAD(&descs->link);
1785 list_add_tail(&descs->link, &s->packet_descs_list);
1786 ++descs;
1787 }
1788 s->packet_descs_cursor = list_first_entry(&s->packet_descs_list, struct pkt_desc, link);
1789
1790 s->packet_index = 0;
1791 do {
1792 struct fw_iso_packet params;
1793
1794 if (s->direction == AMDTP_IN_STREAM) {
1795 err = queue_in_packet(s, ¶ms);
1796 } else {
1797 bool sched_irq = false;
1798
1799 params.header_length = 0;
1800 params.payload_length = 0;
1801
1802 if (is_irq_target) {
1803 sched_irq = !((s->packet_index + 1) %
1804 idle_irq_interval);
1805 }
1806
1807 err = queue_out_packet(s, ¶ms, sched_irq);
1808 }
1809 if (err < 0)
1810 goto err_pkt_descs;
1811 } while (s->packet_index > 0);
1812
1813 /* NOTE: TAG1 matches CIP. This just affects in stream. */
1814 tag = FW_ISO_CONTEXT_MATCH_TAG1;
1815 if ((s->flags & CIP_EMPTY_WITH_TAG0) || (s->flags & CIP_NO_HEADER))
1816 tag |= FW_ISO_CONTEXT_MATCH_TAG0;
1817
1818 s->ready_processing = false;
1819 err = fw_iso_context_start(s->context, -1, 0, tag);
1820 if (err < 0)
1821 goto err_pkt_descs;
1822
1823 mutex_unlock(&s->mutex);
1824
1825 return 0;
1826 err_pkt_descs:
1827 kfree(s->packet_descs);
1828 s->packet_descs = NULL;
1829 err_context:
1830 if (s->direction == AMDTP_OUT_STREAM) {
1831 kfree(s->ctx_data.rx.seq.descs);
1832 } else {
1833 if (s->domain->replay.enable)
1834 kfree(s->ctx_data.tx.cache.descs);
1835 }
1836 fw_iso_context_destroy(s->context);
1837 s->context = ERR_PTR(-1);
1838 err_buffer:
1839 iso_packets_buffer_destroy(&s->buffer, s->unit);
1840 err_unlock:
1841 mutex_unlock(&s->mutex);
1842
1843 return err;
1844 }
1845
1846 /**
1847 * amdtp_domain_stream_pcm_pointer - get the PCM buffer position
1848 * @d: the AMDTP domain.
1849 * @s: the AMDTP stream that transports the PCM data
1850 *
1851 * Returns the current buffer position, in frames.
1852 */
amdtp_domain_stream_pcm_pointer(struct amdtp_domain * d,struct amdtp_stream * s)1853 unsigned long amdtp_domain_stream_pcm_pointer(struct amdtp_domain *d,
1854 struct amdtp_stream *s)
1855 {
1856 struct amdtp_stream *irq_target = d->irq_target;
1857
1858 if (irq_target && amdtp_stream_running(irq_target)) {
1859 // use wq to prevent AB/BA deadlock competition for
1860 // substream lock:
1861 // fw_iso_context_flush_completions() acquires
1862 // lock by ohci_flush_iso_completions(),
1863 // amdtp-stream process_rx_packets() attempts to
1864 // acquire same lock by snd_pcm_elapsed()
1865 if (current_work() != &s->period_work)
1866 fw_iso_context_flush_completions(irq_target->context);
1867 }
1868
1869 return READ_ONCE(s->pcm_buffer_pointer);
1870 }
1871 EXPORT_SYMBOL_GPL(amdtp_domain_stream_pcm_pointer);
1872
1873 /**
1874 * amdtp_domain_stream_pcm_ack - acknowledge queued PCM frames
1875 * @d: the AMDTP domain.
1876 * @s: the AMDTP stream that transfers the PCM frames
1877 *
1878 * Returns zero always.
1879 */
amdtp_domain_stream_pcm_ack(struct amdtp_domain * d,struct amdtp_stream * s)1880 int amdtp_domain_stream_pcm_ack(struct amdtp_domain *d, struct amdtp_stream *s)
1881 {
1882 struct amdtp_stream *irq_target = d->irq_target;
1883
1884 // Process isochronous packets for recent isochronous cycle to handle
1885 // queued PCM frames.
1886 if (irq_target && amdtp_stream_running(irq_target))
1887 fw_iso_context_flush_completions(irq_target->context);
1888
1889 return 0;
1890 }
1891 EXPORT_SYMBOL_GPL(amdtp_domain_stream_pcm_ack);
1892
1893 /**
1894 * amdtp_stream_update - update the stream after a bus reset
1895 * @s: the AMDTP stream
1896 */
amdtp_stream_update(struct amdtp_stream * s)1897 void amdtp_stream_update(struct amdtp_stream *s)
1898 {
1899 /* Precomputing. */
1900 WRITE_ONCE(s->source_node_id_field,
1901 (fw_parent_device(s->unit)->card->node_id << CIP_SID_SHIFT) & CIP_SID_MASK);
1902 }
1903 EXPORT_SYMBOL(amdtp_stream_update);
1904
1905 /**
1906 * amdtp_stream_stop - stop sending packets
1907 * @s: the AMDTP stream to stop
1908 *
1909 * All PCM and MIDI devices of the stream must be stopped before the stream
1910 * itself can be stopped.
1911 */
amdtp_stream_stop(struct amdtp_stream * s)1912 static void amdtp_stream_stop(struct amdtp_stream *s)
1913 {
1914 mutex_lock(&s->mutex);
1915
1916 if (!amdtp_stream_running(s)) {
1917 mutex_unlock(&s->mutex);
1918 return;
1919 }
1920
1921 cancel_work_sync(&s->period_work);
1922 fw_iso_context_stop(s->context);
1923 fw_iso_context_destroy(s->context);
1924 s->context = ERR_PTR(-1);
1925 iso_packets_buffer_destroy(&s->buffer, s->unit);
1926 kfree(s->packet_descs);
1927 s->packet_descs = NULL;
1928
1929 if (s->direction == AMDTP_OUT_STREAM) {
1930 kfree(s->ctx_data.rx.seq.descs);
1931 } else {
1932 if (s->domain->replay.enable)
1933 kfree(s->ctx_data.tx.cache.descs);
1934 }
1935
1936 mutex_unlock(&s->mutex);
1937 }
1938
1939 /**
1940 * amdtp_stream_pcm_abort - abort the running PCM device
1941 * @s: the AMDTP stream about to be stopped
1942 *
1943 * If the isochronous stream needs to be stopped asynchronously, call this
1944 * function first to stop the PCM device.
1945 */
amdtp_stream_pcm_abort(struct amdtp_stream * s)1946 void amdtp_stream_pcm_abort(struct amdtp_stream *s)
1947 {
1948 struct snd_pcm_substream *pcm;
1949
1950 pcm = READ_ONCE(s->pcm);
1951 if (pcm)
1952 snd_pcm_stop_xrun(pcm);
1953 }
1954 EXPORT_SYMBOL(amdtp_stream_pcm_abort);
1955
1956 /**
1957 * amdtp_domain_init - initialize an AMDTP domain structure
1958 * @d: the AMDTP domain to initialize.
1959 */
amdtp_domain_init(struct amdtp_domain * d)1960 int amdtp_domain_init(struct amdtp_domain *d)
1961 {
1962 INIT_LIST_HEAD(&d->streams);
1963
1964 d->events_per_period = 0;
1965
1966 return 0;
1967 }
1968 EXPORT_SYMBOL_GPL(amdtp_domain_init);
1969
1970 /**
1971 * amdtp_domain_destroy - destroy an AMDTP domain structure
1972 * @d: the AMDTP domain to destroy.
1973 */
amdtp_domain_destroy(struct amdtp_domain * d)1974 void amdtp_domain_destroy(struct amdtp_domain *d)
1975 {
1976 // At present nothing to do.
1977 return;
1978 }
1979 EXPORT_SYMBOL_GPL(amdtp_domain_destroy);
1980
1981 /**
1982 * amdtp_domain_add_stream - register isoc context into the domain.
1983 * @d: the AMDTP domain.
1984 * @s: the AMDTP stream.
1985 * @channel: the isochronous channel on the bus.
1986 * @speed: firewire speed code.
1987 */
amdtp_domain_add_stream(struct amdtp_domain * d,struct amdtp_stream * s,int channel,int speed)1988 int amdtp_domain_add_stream(struct amdtp_domain *d, struct amdtp_stream *s,
1989 int channel, int speed)
1990 {
1991 struct amdtp_stream *tmp;
1992
1993 list_for_each_entry(tmp, &d->streams, list) {
1994 if (s == tmp)
1995 return -EBUSY;
1996 }
1997
1998 list_add(&s->list, &d->streams);
1999
2000 s->channel = channel;
2001 s->speed = speed;
2002 s->domain = d;
2003
2004 return 0;
2005 }
2006 EXPORT_SYMBOL_GPL(amdtp_domain_add_stream);
2007
2008 // Make the reference from rx stream to tx stream for sequence replay. When the number of tx streams
2009 // is less than the number of rx streams, the first tx stream is selected.
make_association(struct amdtp_domain * d)2010 static int make_association(struct amdtp_domain *d)
2011 {
2012 unsigned int dst_index = 0;
2013 struct amdtp_stream *rx;
2014
2015 // Make association to replay target.
2016 list_for_each_entry(rx, &d->streams, list) {
2017 if (rx->direction == AMDTP_OUT_STREAM) {
2018 unsigned int src_index = 0;
2019 struct amdtp_stream *tx = NULL;
2020 struct amdtp_stream *s;
2021
2022 list_for_each_entry(s, &d->streams, list) {
2023 if (s->direction == AMDTP_IN_STREAM) {
2024 if (dst_index == src_index) {
2025 tx = s;
2026 break;
2027 }
2028
2029 ++src_index;
2030 }
2031 }
2032 if (!tx) {
2033 // Select the first entry.
2034 list_for_each_entry(s, &d->streams, list) {
2035 if (s->direction == AMDTP_IN_STREAM) {
2036 tx = s;
2037 break;
2038 }
2039 }
2040 // No target is available to replay sequence.
2041 if (!tx)
2042 return -EINVAL;
2043 }
2044
2045 rx->ctx_data.rx.replay_target = tx;
2046
2047 ++dst_index;
2048 }
2049 }
2050
2051 return 0;
2052 }
2053
2054 /**
2055 * amdtp_domain_start - start sending packets for isoc context in the domain.
2056 * @d: the AMDTP domain.
2057 * @tx_init_skip_cycles: the number of cycles to skip processing packets at initial stage of IR
2058 * contexts.
2059 * @replay_seq: whether to replay the sequence of packet in IR context for the sequence of packet in
2060 * IT context.
2061 * @replay_on_the_fly: transfer rx packets according to nominal frequency, then begin to replay
2062 * according to arrival of events in tx packets.
2063 */
amdtp_domain_start(struct amdtp_domain * d,unsigned int tx_init_skip_cycles,bool replay_seq,bool replay_on_the_fly)2064 int amdtp_domain_start(struct amdtp_domain *d, unsigned int tx_init_skip_cycles, bool replay_seq,
2065 bool replay_on_the_fly)
2066 {
2067 unsigned int events_per_buffer = d->events_per_buffer;
2068 unsigned int events_per_period = d->events_per_period;
2069 unsigned int queue_size;
2070 struct amdtp_stream *s;
2071 bool found = false;
2072 int err;
2073
2074 if (replay_seq) {
2075 err = make_association(d);
2076 if (err < 0)
2077 return err;
2078 }
2079 d->replay.enable = replay_seq;
2080 d->replay.on_the_fly = replay_on_the_fly;
2081
2082 // Select an IT context as IRQ target.
2083 list_for_each_entry(s, &d->streams, list) {
2084 if (s->direction == AMDTP_OUT_STREAM) {
2085 found = true;
2086 break;
2087 }
2088 }
2089 if (!found)
2090 return -ENXIO;
2091 d->irq_target = s;
2092
2093 d->processing_cycle.tx_init_skip = tx_init_skip_cycles;
2094
2095 // This is a case that AMDTP streams in domain run just for MIDI
2096 // substream. Use the number of events equivalent to 10 msec as
2097 // interval of hardware IRQ.
2098 if (events_per_period == 0)
2099 events_per_period = amdtp_rate_table[d->irq_target->sfc] / 100;
2100 if (events_per_buffer == 0)
2101 events_per_buffer = events_per_period * 3;
2102
2103 queue_size = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_buffer,
2104 amdtp_rate_table[d->irq_target->sfc]);
2105
2106 list_for_each_entry(s, &d->streams, list) {
2107 unsigned int idle_irq_interval = 0;
2108
2109 if (s->direction == AMDTP_OUT_STREAM && s == d->irq_target) {
2110 idle_irq_interval = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_period,
2111 amdtp_rate_table[d->irq_target->sfc]);
2112 }
2113
2114 // Starts immediately but actually DMA context starts several hundred cycles later.
2115 err = amdtp_stream_start(s, s->channel, s->speed, queue_size, idle_irq_interval);
2116 if (err < 0)
2117 goto error;
2118 }
2119
2120 return 0;
2121 error:
2122 list_for_each_entry(s, &d->streams, list)
2123 amdtp_stream_stop(s);
2124 return err;
2125 }
2126 EXPORT_SYMBOL_GPL(amdtp_domain_start);
2127
2128 /**
2129 * amdtp_domain_stop - stop sending packets for isoc context in the same domain.
2130 * @d: the AMDTP domain to which the isoc contexts belong.
2131 */
amdtp_domain_stop(struct amdtp_domain * d)2132 void amdtp_domain_stop(struct amdtp_domain *d)
2133 {
2134 struct amdtp_stream *s, *next;
2135
2136 if (d->irq_target)
2137 amdtp_stream_stop(d->irq_target);
2138
2139 list_for_each_entry_safe(s, next, &d->streams, list) {
2140 list_del(&s->list);
2141
2142 if (s != d->irq_target)
2143 amdtp_stream_stop(s);
2144 }
2145
2146 d->events_per_period = 0;
2147 d->irq_target = NULL;
2148 }
2149 EXPORT_SYMBOL_GPL(amdtp_domain_stop);
2150