1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_RING_H__ 25 #define __AMDGPU_RING_H__ 26 27 #include <drm/amdgpu_drm.h> 28 #include <drm/gpu_scheduler.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_suballoc.h> 31 32 struct amdgpu_device; 33 struct amdgpu_ring; 34 struct amdgpu_ib; 35 struct amdgpu_cs_parser; 36 struct amdgpu_job; 37 struct amdgpu_vm; 38 39 /* max number of rings */ 40 #define AMDGPU_MAX_RINGS 149 41 #define AMDGPU_MAX_HWIP_RINGS 64 42 #define AMDGPU_MAX_GFX_RINGS 2 43 #define AMDGPU_MAX_SW_GFX_RINGS 2 44 #define AMDGPU_MAX_COMPUTE_RINGS 8 45 #define AMDGPU_MAX_VCE_RINGS 3 46 #define AMDGPU_MAX_UVD_ENC_RINGS 2 47 #define AMDGPU_MAX_VPE_RINGS 2 48 49 enum amdgpu_ring_priority_level { 50 AMDGPU_RING_PRIO_0, 51 AMDGPU_RING_PRIO_1, 52 AMDGPU_RING_PRIO_DEFAULT = 1, 53 AMDGPU_RING_PRIO_2, 54 AMDGPU_RING_PRIO_MAX 55 }; 56 57 /* some special values for the owner field */ 58 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul) 59 #define AMDGPU_FENCE_OWNER_VM ((void *)1ul) 60 #define AMDGPU_FENCE_OWNER_KFD ((void *)2ul) 61 62 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 63 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 64 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2) 65 #define AMDGPU_FENCE_FLAG_EXEC (1 << 3) 66 67 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched) 68 69 #define AMDGPU_IB_POOL_SIZE (1024 * 1024) 70 71 enum amdgpu_ring_type { 72 AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX, 73 AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE, 74 AMDGPU_RING_TYPE_SDMA = AMDGPU_HW_IP_DMA, 75 AMDGPU_RING_TYPE_UVD = AMDGPU_HW_IP_UVD, 76 AMDGPU_RING_TYPE_VCE = AMDGPU_HW_IP_VCE, 77 AMDGPU_RING_TYPE_UVD_ENC = AMDGPU_HW_IP_UVD_ENC, 78 AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC, 79 AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC, 80 AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG, 81 AMDGPU_RING_TYPE_VPE = AMDGPU_HW_IP_VPE, 82 AMDGPU_RING_TYPE_KIQ, 83 AMDGPU_RING_TYPE_MES, 84 AMDGPU_RING_TYPE_UMSCH_MM, 85 AMDGPU_RING_TYPE_CPER, 86 AMDGPU_RING_TYPE_MAX, 87 }; 88 89 enum amdgpu_ib_pool_type { 90 /* Normal submissions to the top of the pipeline. */ 91 AMDGPU_IB_POOL_DELAYED, 92 /* Immediate submissions to the bottom of the pipeline. */ 93 AMDGPU_IB_POOL_IMMEDIATE, 94 /* Direct submission to the ring buffer during init and reset. */ 95 AMDGPU_IB_POOL_DIRECT, 96 97 AMDGPU_IB_POOL_MAX 98 }; 99 100 struct amdgpu_ib { 101 struct drm_suballoc *sa_bo; 102 uint32_t length_dw; 103 uint64_t gpu_addr; 104 uint32_t *ptr; 105 uint32_t flags; 106 }; 107 108 struct amdgpu_sched { 109 u32 num_scheds; 110 struct drm_gpu_scheduler *sched[AMDGPU_MAX_HWIP_RINGS]; 111 }; 112 113 /* 114 * Fences. 115 */ 116 struct amdgpu_fence_driver { 117 uint64_t gpu_addr; 118 uint32_t *cpu_addr; 119 /* sync_seq is protected by ring emission lock */ 120 uint32_t sync_seq; 121 atomic_t last_seq; 122 u64 signalled_wptr; 123 bool initialized; 124 struct amdgpu_irq_src *irq_src; 125 unsigned irq_type; 126 struct timer_list fallback_timer; 127 unsigned num_fences_mask; 128 spinlock_t lock; 129 struct dma_fence **fences; 130 }; 131 132 /* 133 * Fences mark an event in the GPUs pipeline and are used 134 * for GPU/CPU synchronization. When the fence is written, 135 * it is expected that all buffers associated with that fence 136 * are no longer in use by the associated ring on the GPU and 137 * that the relevant GPU caches have been flushed. 138 */ 139 140 struct amdgpu_fence { 141 struct dma_fence base; 142 143 /* RB, DMA, etc. */ 144 struct amdgpu_ring *ring; 145 ktime_t start_timestamp; 146 147 /* wptr for the fence for resets */ 148 u64 wptr; 149 /* fence context for resets */ 150 u64 context; 151 }; 152 153 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 154 155 void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error); 156 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); 157 void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af); 158 void amdgpu_fence_save_wptr(struct amdgpu_fence *af); 159 160 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 161 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 162 struct amdgpu_irq_src *irq_src, 163 unsigned irq_type); 164 void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev); 165 void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev); 166 int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev); 167 void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev); 168 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, 169 unsigned int flags); 170 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s, 171 uint32_t timeout); 172 bool amdgpu_fence_process(struct amdgpu_ring *ring); 173 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 174 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 175 uint32_t wait_seq, 176 signed long timeout); 177 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 178 179 void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop); 180 181 u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring); 182 void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq, 183 ktime_t timestamp); 184 185 /* 186 * Rings. 187 */ 188 189 /* provided by hw blocks that expose a ring buffer for commands */ 190 struct amdgpu_ring_funcs { 191 /** 192 * @type: 193 * 194 * GFX, Compute, SDMA, UVD, VCE, VCN, VPE, KIQ, MES, UMSCH, and CPER 195 * use ring buffers. The type field just identifies which component the 196 * ring buffer is associated with. 197 */ 198 enum amdgpu_ring_type type; 199 uint32_t align_mask; 200 201 /** 202 * @nop: 203 * 204 * Every block in the amdgpu has no-op instructions (e.g., GFX 10 205 * uses PACKET3(PACKET3_NOP, 0x3FFF), VCN 5 uses VCN_ENC_CMD_NO_OP, 206 * etc). This field receives the specific no-op for the component 207 * that initializes the ring. 208 */ 209 u32 nop; 210 bool support_64bit_ptrs; 211 bool no_user_fence; 212 bool secure_submission_supported; 213 214 /** 215 * @extra_bytes: 216 * 217 * Optional extra space in bytes that is added to the ring size 218 * when allocating the BO that holds the contents of the ring. 219 * This space isn't used for command submission to the ring, 220 * but is just there to satisfy some hardware requirements or 221 * implement workarounds. It's up to the implementation of each 222 * specific ring to initialize this space. 223 */ 224 unsigned extra_bytes; 225 226 /* ring read/write ptr handling */ 227 u64 (*get_rptr)(struct amdgpu_ring *ring); 228 u64 (*get_wptr)(struct amdgpu_ring *ring); 229 void (*set_wptr)(struct amdgpu_ring *ring); 230 /* validating and patching of IBs */ 231 int (*parse_cs)(struct amdgpu_cs_parser *p, 232 struct amdgpu_job *job, 233 struct amdgpu_ib *ib); 234 int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, 235 struct amdgpu_job *job, 236 struct amdgpu_ib *ib); 237 /* constants to calculate how many DW are needed for an emit */ 238 unsigned emit_frame_size; 239 unsigned emit_ib_size; 240 /* command emit functions */ 241 void (*emit_ib)(struct amdgpu_ring *ring, 242 struct amdgpu_job *job, 243 struct amdgpu_ib *ib, 244 uint32_t flags); 245 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 246 uint64_t seq, unsigned flags); 247 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 248 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, 249 uint64_t pd_addr); 250 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 251 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 252 uint32_t gds_base, uint32_t gds_size, 253 uint32_t gws_base, uint32_t gws_size, 254 uint32_t oa_base, uint32_t oa_size); 255 /* testing functions */ 256 int (*test_ring)(struct amdgpu_ring *ring); 257 int (*test_ib)(struct amdgpu_ring *ring, long timeout); 258 /* insert NOP packets */ 259 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 260 void (*insert_start)(struct amdgpu_ring *ring); 261 void (*insert_end)(struct amdgpu_ring *ring); 262 /* pad the indirect buffer to the necessary number of dw */ 263 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 264 unsigned (*init_cond_exec)(struct amdgpu_ring *ring, uint64_t addr); 265 /* note usage for clock and power gating */ 266 void (*begin_use)(struct amdgpu_ring *ring); 267 void (*end_use)(struct amdgpu_ring *ring); 268 void (*emit_switch_buffer) (struct amdgpu_ring *ring); 269 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); 270 void (*emit_gfx_shadow)(struct amdgpu_ring *ring, u64 shadow_va, u64 csa_va, 271 u64 gds_va, bool init_shadow, int vmid); 272 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg, 273 uint32_t reg_val_offs); 274 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); 275 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg, 276 uint32_t val, uint32_t mask); 277 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring, 278 uint32_t reg0, uint32_t reg1, 279 uint32_t ref, uint32_t mask); 280 void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start, 281 bool secure); 282 /* Try to soft recover the ring to make the fence signal */ 283 void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid); 284 int (*preempt_ib)(struct amdgpu_ring *ring); 285 void (*emit_mem_sync)(struct amdgpu_ring *ring); 286 void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable); 287 void (*patch_cntl)(struct amdgpu_ring *ring, unsigned offset); 288 void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset); 289 void (*patch_de)(struct amdgpu_ring *ring, unsigned offset); 290 int (*reset)(struct amdgpu_ring *ring, unsigned int vmid, 291 struct amdgpu_fence *timedout_fence); 292 void (*emit_cleaner_shader)(struct amdgpu_ring *ring); 293 }; 294 295 /** 296 * amdgpu_ring - Holds ring information 297 */ 298 struct amdgpu_ring { 299 struct amdgpu_device *adev; 300 const struct amdgpu_ring_funcs *funcs; 301 struct amdgpu_fence_driver fence_drv; 302 struct drm_gpu_scheduler sched; 303 304 struct amdgpu_bo *ring_obj; 305 uint32_t *ring; 306 /* backups for resets */ 307 uint32_t *ring_backup; 308 unsigned int ring_backup_entries_to_copy; 309 unsigned rptr_offs; 310 u64 rptr_gpu_addr; 311 u32 *rptr_cpu_addr; 312 313 /** 314 * @wptr: 315 * 316 * This is part of the Ring buffer implementation and represents the 317 * write pointer. The wptr determines where the host has written. 318 */ 319 u64 wptr; 320 321 /** 322 * @wptr_old: 323 * 324 * Before update wptr with the new value, usually the old value is 325 * stored in the wptr_old. 326 */ 327 u64 wptr_old; 328 unsigned ring_size; 329 330 /** 331 * @max_dw: 332 * 333 * Maximum number of DWords for ring allocation. This information is 334 * provided at the ring initialization time, and each IP block can 335 * specify a specific value. Check places that invoke 336 * amdgpu_ring_init() to see the maximum size per block. 337 */ 338 unsigned max_dw; 339 340 /** 341 * @count_dw: 342 * 343 * This value starts with the maximum amount of DWords supported by the 344 * ring. This value is updated based on the ring manipulation. 345 */ 346 int count_dw; 347 uint64_t gpu_addr; 348 349 /** 350 * @ptr_mask: 351 * 352 * Some IPs provide support for 64-bit pointers and others for 32-bit 353 * only; this behavior is component-specific and defined by the field 354 * support_64bit_ptr. If the IP block supports 64-bits, the mask 355 * 0xffffffffffffffff is set; otherwise, this value assumes buf_mask. 356 * Notice that this field is used to keep wptr under a valid range. 357 */ 358 uint64_t ptr_mask; 359 360 /** 361 * @buf_mask: 362 * 363 * Buffer mask is a value used to keep wptr count under its 364 * thresholding. Buffer mask initialized during the ring buffer 365 * initialization time, and it is defined as (ring_size / 4) -1. 366 */ 367 uint32_t buf_mask; 368 u32 idx; 369 u32 xcc_id; 370 u32 xcp_id; 371 u32 me; 372 u32 pipe; 373 u32 queue; 374 struct amdgpu_bo *mqd_obj; 375 uint64_t mqd_gpu_addr; 376 void *mqd_ptr; 377 unsigned mqd_size; 378 uint64_t eop_gpu_addr; 379 u32 doorbell_index; 380 bool use_doorbell; 381 bool use_pollmem; 382 unsigned wptr_offs; 383 u64 wptr_gpu_addr; 384 385 /** 386 * @wptr_cpu_addr: 387 * 388 * This is the CPU address pointer in the writeback slot. This is used 389 * to commit changes to the GPU. 390 */ 391 u32 *wptr_cpu_addr; 392 unsigned fence_offs; 393 u64 fence_gpu_addr; 394 u32 *fence_cpu_addr; 395 uint64_t current_ctx; 396 char name[16]; 397 u32 trail_seq; 398 unsigned trail_fence_offs; 399 u64 trail_fence_gpu_addr; 400 u32 *trail_fence_cpu_addr; 401 unsigned cond_exe_offs; 402 u64 cond_exe_gpu_addr; 403 u32 *cond_exe_cpu_addr; 404 unsigned int set_q_mode_offs; 405 u32 *set_q_mode_ptr; 406 u64 set_q_mode_token; 407 unsigned vm_hub; 408 unsigned vm_inv_eng; 409 struct dma_fence *vmid_wait; 410 bool has_compute_vm_bug; 411 bool no_scheduler; 412 bool no_user_submission; 413 int hw_prio; 414 unsigned num_hw_submission; 415 atomic_t *sched_score; 416 417 bool is_sw_ring; 418 unsigned int entry_index; 419 /* store the cached rptr to restore after reset */ 420 uint64_t cached_rptr; 421 }; 422 423 #define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib))) 424 #define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib))) 425 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 426 #define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0) 427 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 428 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 429 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 430 #define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags))) 431 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 432 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 433 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 434 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 435 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 436 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 437 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 438 #define amdgpu_ring_emit_gfx_shadow(r, s, c, g, i, v) ((r)->funcs->emit_gfx_shadow((r), (s), (c), (g), (i), (v))) 439 #define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o)) 440 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 441 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m)) 442 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m)) 443 #define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s)) 444 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 445 #define amdgpu_ring_init_cond_exec(r, a) (r)->funcs->init_cond_exec((r), (a)) 446 #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r) 447 #define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o))) 448 #define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o))) 449 #define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o))) 450 #define amdgpu_ring_reset(r, v, f) (r)->funcs->reset((r), (v), (f)) 451 452 unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type); 453 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 454 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring); 455 void amdgpu_ring_ib_end(struct amdgpu_ring *ring); 456 void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring); 457 void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring); 458 void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring); 459 460 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 461 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 462 void amdgpu_ring_commit(struct amdgpu_ring *ring); 463 void amdgpu_ring_undo(struct amdgpu_ring *ring); 464 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 465 unsigned int max_dw, struct amdgpu_irq_src *irq_src, 466 unsigned int irq_type, unsigned int hw_prio, 467 atomic_t *sched_score); 468 void amdgpu_ring_fini(struct amdgpu_ring *ring); 469 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, 470 uint32_t reg0, uint32_t val0, 471 uint32_t reg1, uint32_t val1); 472 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, 473 struct dma_fence *fence); 474 475 static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring, 476 bool cond_exec) 477 { 478 *ring->cond_exe_cpu_addr = cond_exec; 479 } 480 481 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) 482 { 483 memset32(ring->ring, ring->funcs->nop, ring->buf_mask + 1); 484 } 485 486 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 487 { 488 ring->ring[ring->wptr++ & ring->buf_mask] = v; 489 ring->wptr &= ring->ptr_mask; 490 ring->count_dw--; 491 } 492 493 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, 494 void *src, int count_dw) 495 { 496 unsigned occupied, chunk1, chunk2; 497 498 occupied = ring->wptr & ring->buf_mask; 499 chunk1 = ring->buf_mask + 1 - occupied; 500 chunk1 = (chunk1 >= count_dw) ? count_dw : chunk1; 501 chunk2 = count_dw - chunk1; 502 chunk1 <<= 2; 503 chunk2 <<= 2; 504 505 if (chunk1) 506 memcpy(&ring->ring[occupied], src, chunk1); 507 508 if (chunk2) { 509 src += chunk1; 510 memcpy(ring->ring, src, chunk2); 511 } 512 513 ring->wptr += count_dw; 514 ring->wptr &= ring->ptr_mask; 515 ring->count_dw -= count_dw; 516 } 517 518 /** 519 * amdgpu_ring_patch_cond_exec - patch dw count of conditional execute 520 * @ring: amdgpu_ring structure 521 * @offset: offset returned by amdgpu_ring_init_cond_exec 522 * 523 * Calculate the dw count and patch it into a cond_exec command. 524 */ 525 static inline void amdgpu_ring_patch_cond_exec(struct amdgpu_ring *ring, 526 unsigned int offset) 527 { 528 unsigned cur; 529 530 if (!ring->funcs->init_cond_exec) 531 return; 532 533 WARN_ON(offset > ring->buf_mask); 534 WARN_ON(ring->ring[offset] != 0); 535 536 cur = (ring->wptr - 1) & ring->buf_mask; 537 if (cur < offset) 538 cur += ring->ring_size >> 2; 539 ring->ring[offset] = cur - offset; 540 } 541 542 int amdgpu_ring_test_helper(struct amdgpu_ring *ring); 543 544 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, 545 struct amdgpu_ring *ring); 546 547 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring); 548 549 static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, int idx) 550 { 551 return ib->ptr[idx]; 552 } 553 554 static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, int idx, 555 uint32_t value) 556 { 557 ib->ptr[idx] = value; 558 } 559 560 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 561 unsigned size, 562 enum amdgpu_ib_pool_type pool, 563 struct amdgpu_ib *ib); 564 void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f); 565 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 566 struct amdgpu_ib *ibs, struct amdgpu_job *job, 567 struct dma_fence **f); 568 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 569 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 570 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 571 bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring); 572 void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring, 573 struct amdgpu_fence *guilty_fence); 574 void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring, 575 struct amdgpu_fence *guilty_fence); 576 int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring, 577 struct amdgpu_fence *guilty_fence); 578 bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring, 579 u32 reset_type); 580 #endif 581