xref: /linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c (revision 220994d61cebfc04f071d69049127657c7e8191b)
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include "amdgpu_ras_eeprom.h"
25 #include "amdgpu.h"
26 #include "amdgpu_ras.h"
27 #include <linux/bits.h>
28 #include "atom.h"
29 #include "amdgpu_eeprom.h"
30 #include "amdgpu_atomfirmware.h"
31 #include <linux/debugfs.h>
32 #include <linux/uaccess.h>
33 
34 #include "amdgpu_reset.h"
35 
36 /* These are memory addresses as would be seen by one or more EEPROM
37  * chips strung on the I2C bus, usually by manipulating pins 1-3 of a
38  * set of EEPROM devices. They form a continuous memory space.
39  *
40  * The I2C device address includes the device type identifier, 1010b,
41  * which is a reserved value and indicates that this is an I2C EEPROM
42  * device. It also includes the top 3 bits of the 19 bit EEPROM memory
43  * address, namely bits 18, 17, and 16. This makes up the 7 bit
44  * address sent on the I2C bus with bit 0 being the direction bit,
45  * which is not represented here, and sent by the hardware directly.
46  *
47  * For instance,
48  *   50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0.
49  *   54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h.
50  *   56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h.
51  * Depending on the size of the I2C EEPROM device(s), bits 18:16 may
52  * address memory in a device or a device on the I2C bus, depending on
53  * the status of pins 1-3. See top of amdgpu_eeprom.c.
54  *
55  * The RAS table lives either at address 0 or address 40000h of EEPROM.
56  */
57 #define EEPROM_I2C_MADDR_0      0x0
58 #define EEPROM_I2C_MADDR_4      0x40000
59 
60 /*
61  * The 2 macros below represent the actual size in bytes that
62  * those entities occupy in the EEPROM memory.
63  * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which
64  * uses uint64 to store 6b fields such as retired_page.
65  */
66 #define RAS_TABLE_HEADER_SIZE   20
67 #define RAS_TABLE_RECORD_SIZE   24
68 
69 /* Table hdr is 'AMDR' */
70 #define RAS_TABLE_HDR_VAL       0x414d4452
71 
72 /* Bad GPU tag ‘BADG’ */
73 #define RAS_TABLE_HDR_BAD       0x42414447
74 
75 /*
76  * EEPROM Table structure v1
77  * ---------------------------------
78  * |                               |
79  * |     EEPROM TABLE HEADER       |
80  * |      ( size 20 Bytes )        |
81  * |                               |
82  * ---------------------------------
83  * |                               |
84  * |    BAD PAGE RECORD AREA       |
85  * |                               |
86  * ---------------------------------
87  */
88 
89 /* Assume 2-Mbit size EEPROM and take up the whole space. */
90 #define RAS_TBL_SIZE_BYTES      (256 * 1024)
91 #define RAS_TABLE_START         0
92 #define RAS_HDR_START           RAS_TABLE_START
93 #define RAS_RECORD_START        (RAS_HDR_START + RAS_TABLE_HEADER_SIZE)
94 #define RAS_MAX_RECORD_COUNT    ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \
95 				 / RAS_TABLE_RECORD_SIZE)
96 
97 /*
98  * EEPROM Table structrue v2.1
99  * ---------------------------------
100  * |                               |
101  * |     EEPROM TABLE HEADER       |
102  * |      ( size 20 Bytes )        |
103  * |                               |
104  * ---------------------------------
105  * |                               |
106  * |     EEPROM TABLE RAS INFO     |
107  * | (available info size 4 Bytes) |
108  * |  ( reserved size 252 Bytes )  |
109  * |                               |
110  * ---------------------------------
111  * |                               |
112  * |     BAD PAGE RECORD AREA      |
113  * |                               |
114  * ---------------------------------
115  */
116 
117 /* EEPROM Table V2_1 */
118 #define RAS_TABLE_V2_1_INFO_SIZE       256
119 #define RAS_TABLE_V2_1_INFO_START      RAS_TABLE_HEADER_SIZE
120 #define RAS_RECORD_START_V2_1          (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \
121 					RAS_TABLE_V2_1_INFO_SIZE)
122 #define RAS_MAX_RECORD_COUNT_V2_1      ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \
123 					RAS_TABLE_V2_1_INFO_SIZE) \
124 					/ RAS_TABLE_RECORD_SIZE)
125 
126 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM
127  * offset off of RAS_TABLE_START.  That is, this is something you can
128  * add to control->i2c_address, and then tell I2C layer to read
129  * from/write to there. _N is the so called absolute index,
130  * because it starts right after the table header.
131  */
132 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \
133 				     (_N) * RAS_TABLE_RECORD_SIZE)
134 
135 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \
136 				      (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE)
137 
138 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off
139  * of "fri", return the absolute record index off of the end of
140  * the table header.
141  */
142 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \
143 			      (_C)->ras_max_record_count)
144 
145 #define RAS_NUM_RECS(_tbl_hdr)  (((_tbl_hdr)->tbl_size - \
146 				  RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE)
147 
148 #define RAS_NUM_RECS_V2_1(_tbl_hdr)  (((_tbl_hdr)->tbl_size - \
149 				       RAS_TABLE_HEADER_SIZE - \
150 				       RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE)
151 
152 #define to_amdgpu_device(x) ((container_of(x, struct amdgpu_ras, eeprom_control))->adev)
153 
__is_ras_eeprom_supported(struct amdgpu_device * adev)154 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)
155 {
156 	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
157 	case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */
158 	case IP_VERSION(11, 0, 7): /* Sienna cichlid */
159 	case IP_VERSION(13, 0, 0):
160 	case IP_VERSION(13, 0, 2): /* Aldebaran */
161 	case IP_VERSION(13, 0, 10):
162 		return true;
163 	case IP_VERSION(13, 0, 6):
164 	case IP_VERSION(13, 0, 12):
165 	case IP_VERSION(13, 0, 14):
166 		return (adev->gmc.is_app_apu) ? false : true;
167 	default:
168 		return false;
169 	}
170 }
171 
__get_eeprom_i2c_addr(struct amdgpu_device * adev,struct amdgpu_ras_eeprom_control * control)172 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
173 				  struct amdgpu_ras_eeprom_control *control)
174 {
175 	struct atom_context *atom_ctx = adev->mode_info.atom_context;
176 	u8 i2c_addr;
177 
178 	if (!control)
179 		return false;
180 
181 	if (adev->bios && amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) {
182 		/* The address given by VBIOS is an 8-bit, wire-format
183 		 * address, i.e. the most significant byte.
184 		 *
185 		 * Normalize it to a 19-bit EEPROM address. Remove the
186 		 * device type identifier and make it a 7-bit address;
187 		 * then make it a 19-bit EEPROM address. See top of
188 		 * amdgpu_eeprom.c.
189 		 */
190 		i2c_addr = (i2c_addr & 0x0F) >> 1;
191 		control->i2c_address = ((u32) i2c_addr) << 16;
192 
193 		return true;
194 	}
195 
196 	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
197 	case IP_VERSION(11, 0, 2):
198 		/* VEGA20 and ARCTURUS */
199 		if (adev->asic_type == CHIP_VEGA20)
200 			control->i2c_address = EEPROM_I2C_MADDR_0;
201 		else if (strnstr(atom_ctx->vbios_pn,
202 				 "D342",
203 				 sizeof(atom_ctx->vbios_pn)))
204 			control->i2c_address = EEPROM_I2C_MADDR_0;
205 		else
206 			control->i2c_address = EEPROM_I2C_MADDR_4;
207 		return true;
208 	case IP_VERSION(11, 0, 7):
209 		control->i2c_address = EEPROM_I2C_MADDR_0;
210 		return true;
211 	case IP_VERSION(13, 0, 2):
212 		if (strnstr(atom_ctx->vbios_pn, "D673",
213 			    sizeof(atom_ctx->vbios_pn)))
214 			control->i2c_address = EEPROM_I2C_MADDR_4;
215 		else
216 			control->i2c_address = EEPROM_I2C_MADDR_0;
217 		return true;
218 	case IP_VERSION(13, 0, 0):
219 		if (strnstr(atom_ctx->vbios_pn, "D707",
220 			    sizeof(atom_ctx->vbios_pn)))
221 			control->i2c_address = EEPROM_I2C_MADDR_0;
222 		else
223 			control->i2c_address = EEPROM_I2C_MADDR_4;
224 		return true;
225 	case IP_VERSION(13, 0, 6):
226 	case IP_VERSION(13, 0, 10):
227 	case IP_VERSION(13, 0, 12):
228 	case IP_VERSION(13, 0, 14):
229 		control->i2c_address = EEPROM_I2C_MADDR_4;
230 		return true;
231 	default:
232 		return false;
233 	}
234 }
235 
236 static void
__encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header * hdr,unsigned char * buf)237 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr,
238 			     unsigned char *buf)
239 {
240 	u32 *pp = (uint32_t *)buf;
241 
242 	pp[0] = cpu_to_le32(hdr->header);
243 	pp[1] = cpu_to_le32(hdr->version);
244 	pp[2] = cpu_to_le32(hdr->first_rec_offset);
245 	pp[3] = cpu_to_le32(hdr->tbl_size);
246 	pp[4] = cpu_to_le32(hdr->checksum);
247 }
248 
249 static void
__decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header * hdr,unsigned char * buf)250 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr,
251 			       unsigned char *buf)
252 {
253 	u32 *pp = (uint32_t *)buf;
254 
255 	hdr->header	      = le32_to_cpu(pp[0]);
256 	hdr->version	      = le32_to_cpu(pp[1]);
257 	hdr->first_rec_offset = le32_to_cpu(pp[2]);
258 	hdr->tbl_size	      = le32_to_cpu(pp[3]);
259 	hdr->checksum	      = le32_to_cpu(pp[4]);
260 }
261 
__write_table_header(struct amdgpu_ras_eeprom_control * control)262 static int __write_table_header(struct amdgpu_ras_eeprom_control *control)
263 {
264 	u8 buf[RAS_TABLE_HEADER_SIZE];
265 	struct amdgpu_device *adev = to_amdgpu_device(control);
266 	int res;
267 
268 	memset(buf, 0, sizeof(buf));
269 	__encode_table_header_to_buf(&control->tbl_hdr, buf);
270 
271 	/* i2c may be unstable in gpu reset */
272 	down_read(&adev->reset_domain->sem);
273 	res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
274 				  control->i2c_address +
275 				  control->ras_header_offset,
276 				  buf, RAS_TABLE_HEADER_SIZE);
277 	up_read(&adev->reset_domain->sem);
278 
279 	if (res < 0) {
280 		dev_err(adev->dev, "Failed to write EEPROM table header:%d",
281 			res);
282 	} else if (res < RAS_TABLE_HEADER_SIZE) {
283 		dev_err(adev->dev, "Short write:%d out of %d\n", res,
284 			RAS_TABLE_HEADER_SIZE);
285 		res = -EIO;
286 	} else {
287 		res = 0;
288 	}
289 
290 	return res;
291 }
292 
293 static void
__encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info * rai,unsigned char * buf)294 __encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info *rai,
295 			       unsigned char *buf)
296 {
297 	u32 *pp = (uint32_t *)buf;
298 	u32 tmp;
299 
300 	tmp = ((uint32_t)(rai->rma_status) & 0xFF) |
301 	      (((uint32_t)(rai->health_percent) << 8) & 0xFF00) |
302 	      (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000);
303 	pp[0] = cpu_to_le32(tmp);
304 }
305 
306 static void
__decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info * rai,unsigned char * buf)307 __decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info *rai,
308 				 unsigned char *buf)
309 {
310 	u32 *pp = (uint32_t *)buf;
311 	u32 tmp;
312 
313 	tmp = le32_to_cpu(pp[0]);
314 	rai->rma_status = tmp & 0xFF;
315 	rai->health_percent = (tmp >> 8) & 0xFF;
316 	rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF;
317 }
318 
__write_table_ras_info(struct amdgpu_ras_eeprom_control * control)319 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control)
320 {
321 	struct amdgpu_device *adev = to_amdgpu_device(control);
322 	u8 *buf;
323 	int res;
324 
325 	buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL);
326 	if (!buf) {
327 		dev_err(adev->dev,
328 			"Failed to alloc buf to write table ras info\n");
329 		return -ENOMEM;
330 	}
331 
332 	__encode_table_ras_info_to_buf(&control->tbl_rai, buf);
333 
334 	/* i2c may be unstable in gpu reset */
335 	down_read(&adev->reset_domain->sem);
336 	res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
337 				  control->i2c_address +
338 				  control->ras_info_offset,
339 				  buf, RAS_TABLE_V2_1_INFO_SIZE);
340 	up_read(&adev->reset_domain->sem);
341 
342 	if (res < 0) {
343 		dev_err(adev->dev, "Failed to write EEPROM table ras info:%d",
344 			res);
345 	} else if (res < RAS_TABLE_V2_1_INFO_SIZE) {
346 		dev_err(adev->dev, "Short write:%d out of %d\n", res,
347 			RAS_TABLE_V2_1_INFO_SIZE);
348 		res = -EIO;
349 	} else {
350 		res = 0;
351 	}
352 
353 	kfree(buf);
354 
355 	return res;
356 }
357 
__calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control * control)358 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control)
359 {
360 	int ii;
361 	u8  *pp, csum;
362 	size_t sz;
363 
364 	/* Header checksum, skip checksum field in the calculation */
365 	sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum);
366 	pp = (u8 *) &control->tbl_hdr;
367 	csum = 0;
368 	for (ii = 0; ii < sz; ii++, pp++)
369 		csum += *pp;
370 
371 	return csum;
372 }
373 
__calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control * control)374 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control)
375 {
376 	int ii;
377 	u8  *pp, csum;
378 	size_t sz;
379 
380 	sz = sizeof(control->tbl_rai);
381 	pp = (u8 *) &control->tbl_rai;
382 	csum = 0;
383 	for (ii = 0; ii < sz; ii++, pp++)
384 		csum += *pp;
385 
386 	return csum;
387 }
388 
amdgpu_ras_eeprom_correct_header_tag(struct amdgpu_ras_eeprom_control * control,uint32_t header)389 static int amdgpu_ras_eeprom_correct_header_tag(
390 	struct amdgpu_ras_eeprom_control *control,
391 	uint32_t header)
392 {
393 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
394 	u8 *hh;
395 	int res;
396 	u8 csum;
397 
398 	csum = -hdr->checksum;
399 
400 	hh = (void *) &hdr->header;
401 	csum -= (hh[0] + hh[1] + hh[2] + hh[3]);
402 	hh = (void *) &header;
403 	csum += hh[0] + hh[1] + hh[2] + hh[3];
404 	csum = -csum;
405 	mutex_lock(&control->ras_tbl_mutex);
406 	hdr->header = header;
407 	hdr->checksum = csum;
408 	res = __write_table_header(control);
409 	mutex_unlock(&control->ras_tbl_mutex);
410 
411 	return res;
412 }
413 
amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control * control)414 static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control)
415 {
416 	struct amdgpu_device *adev = to_amdgpu_device(control);
417 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
418 
419 	switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
420 	case IP_VERSION(8, 10, 0):
421 		hdr->version = RAS_TABLE_VER_V2_1;
422 		return;
423 	case IP_VERSION(12, 0, 0):
424 	case IP_VERSION(12, 5, 0):
425 		hdr->version = RAS_TABLE_VER_V3;
426 		return;
427 	default:
428 		hdr->version = RAS_TABLE_VER_V1;
429 		return;
430 	}
431 }
432 
433 /**
434  * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table
435  * @control: pointer to control structure
436  *
437  * Reset the contents of the header of the RAS EEPROM table.
438  * Return 0 on success, -errno on error.
439  */
amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control * control)440 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
441 {
442 	struct amdgpu_device *adev = to_amdgpu_device(control);
443 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
444 	struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai;
445 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
446 	u8 csum;
447 	int res;
448 
449 	mutex_lock(&control->ras_tbl_mutex);
450 
451 	hdr->header = RAS_TABLE_HDR_VAL;
452 	amdgpu_ras_set_eeprom_table_version(control);
453 
454 	if (hdr->version >= RAS_TABLE_VER_V2_1) {
455 		hdr->first_rec_offset = RAS_RECORD_START_V2_1;
456 		hdr->tbl_size = RAS_TABLE_HEADER_SIZE +
457 				RAS_TABLE_V2_1_INFO_SIZE;
458 		rai->rma_status = GPU_HEALTH_USABLE;
459 		/**
460 		 * GPU health represented as a percentage.
461 		 * 0 means worst health, 100 means fully health.
462 		 */
463 		rai->health_percent = 100;
464 		/* ecc_page_threshold = 0 means disable bad page retirement */
465 		rai->ecc_page_threshold = con->bad_page_cnt_threshold;
466 	} else {
467 		hdr->first_rec_offset = RAS_RECORD_START;
468 		hdr->tbl_size = RAS_TABLE_HEADER_SIZE;
469 	}
470 
471 	csum = __calc_hdr_byte_sum(control);
472 	if (hdr->version >= RAS_TABLE_VER_V2_1)
473 		csum += __calc_ras_info_byte_sum(control);
474 	csum = -csum;
475 	hdr->checksum = csum;
476 	res = __write_table_header(control);
477 	if (!res && hdr->version > RAS_TABLE_VER_V1)
478 		res = __write_table_ras_info(control);
479 
480 	control->ras_num_recs = 0;
481 	control->ras_num_bad_pages = 0;
482 	control->ras_num_mca_recs = 0;
483 	control->ras_num_pa_recs = 0;
484 	control->ras_fri = 0;
485 
486 	amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_bad_pages);
487 
488 	control->bad_channel_bitmap = 0;
489 	amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap);
490 	con->update_channel_flag = false;
491 
492 	amdgpu_ras_debugfs_set_ret_size(control);
493 
494 	mutex_unlock(&control->ras_tbl_mutex);
495 
496 	return res;
497 }
498 
499 static void
__encode_table_record_to_buf(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,unsigned char * buf)500 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control,
501 			     struct eeprom_table_record *record,
502 			     unsigned char *buf)
503 {
504 	__le64 tmp = 0;
505 	int i = 0;
506 
507 	/* Next are all record fields according to EEPROM page spec in LE foramt */
508 	buf[i++] = record->err_type;
509 
510 	buf[i++] = record->bank;
511 
512 	tmp = cpu_to_le64(record->ts);
513 	memcpy(buf + i, &tmp, 8);
514 	i += 8;
515 
516 	tmp = cpu_to_le64((record->offset & 0xffffffffffff));
517 	memcpy(buf + i, &tmp, 6);
518 	i += 6;
519 
520 	buf[i++] = record->mem_channel;
521 	buf[i++] = record->mcumc_id;
522 
523 	tmp = cpu_to_le64((record->retired_page & 0xffffffffffff));
524 	memcpy(buf + i, &tmp, 6);
525 }
526 
527 static void
__decode_table_record_from_buf(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,unsigned char * buf)528 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control,
529 			       struct eeprom_table_record *record,
530 			       unsigned char *buf)
531 {
532 	__le64 tmp = 0;
533 	int i =  0;
534 
535 	/* Next are all record fields according to EEPROM page spec in LE foramt */
536 	record->err_type = buf[i++];
537 
538 	record->bank = buf[i++];
539 
540 	memcpy(&tmp, buf + i, 8);
541 	record->ts = le64_to_cpu(tmp);
542 	i += 8;
543 
544 	memcpy(&tmp, buf + i, 6);
545 	record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
546 	i += 6;
547 
548 	record->mem_channel = buf[i++];
549 	record->mcumc_id = buf[i++];
550 
551 	memcpy(&tmp, buf + i,  6);
552 	record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
553 }
554 
amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device * adev)555 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev)
556 {
557 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
558 
559 	if (!__is_ras_eeprom_supported(adev) ||
560 	    !amdgpu_bad_page_threshold)
561 		return false;
562 
563 	/* skip check eeprom table for VEGA20 Gaming */
564 	if (!con)
565 		return false;
566 	else
567 		if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC)))
568 			return false;
569 
570 	if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) {
571 		if (con->eeprom_control.ras_num_bad_pages > con->bad_page_cnt_threshold)
572 			dev_warn(adev->dev, "RAS records:%d exceed threshold:%d",
573 				 con->eeprom_control.ras_num_bad_pages, con->bad_page_cnt_threshold);
574 		if ((amdgpu_bad_page_threshold == -1) ||
575 		    (amdgpu_bad_page_threshold == -2)) {
576 			dev_warn(adev->dev,
577 				 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures.\n");
578 			return false;
579 		} else {
580 			dev_warn(adev->dev,
581 				 "Please consider adjusting the customized threshold.\n");
582 			return true;
583 		}
584 	}
585 
586 	return false;
587 }
588 
589 /**
590  * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM
591  * @control: pointer to control structure
592  * @buf: pointer to buffer containing data to write
593  * @fri: start writing at this index
594  * @num: number of records to write
595  *
596  * The caller must hold the table mutex in @control.
597  * Return 0 on success, -errno otherwise.
598  */
__amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control * control,u8 * buf,const u32 fri,const u32 num)599 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control,
600 				     u8 *buf, const u32 fri, const u32 num)
601 {
602 	struct amdgpu_device *adev = to_amdgpu_device(control);
603 	u32 buf_size;
604 	int res;
605 
606 	/* i2c may be unstable in gpu reset */
607 	down_read(&adev->reset_domain->sem);
608 	buf_size = num * RAS_TABLE_RECORD_SIZE;
609 	res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
610 				  control->i2c_address +
611 				  RAS_INDEX_TO_OFFSET(control, fri),
612 				  buf, buf_size);
613 	up_read(&adev->reset_domain->sem);
614 	if (res < 0) {
615 		dev_err(adev->dev, "Writing %d EEPROM table records error:%d",
616 			num, res);
617 	} else if (res < buf_size) {
618 		/* Short write, return error.
619 		 */
620 		dev_err(adev->dev, "Wrote %d records out of %d",
621 			res / RAS_TABLE_RECORD_SIZE, num);
622 		res = -EIO;
623 	} else {
624 		res = 0;
625 	}
626 
627 	return res;
628 }
629 
630 static int
amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,const u32 num)631 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,
632 			       struct eeprom_table_record *record,
633 			       const u32 num)
634 {
635 	struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control));
636 	struct amdgpu_device *adev = to_amdgpu_device(control);
637 	u32 a, b, i;
638 	u8 *buf, *pp;
639 	int res;
640 
641 	buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
642 	if (!buf)
643 		return -ENOMEM;
644 
645 	/* Encode all of them in one go.
646 	 */
647 	pp = buf;
648 	for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) {
649 		__encode_table_record_to_buf(control, &record[i], pp);
650 
651 		/* update bad channel bitmap */
652 		if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) &&
653 		    !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {
654 			control->bad_channel_bitmap |= 1 << record[i].mem_channel;
655 			con->update_channel_flag = true;
656 		}
657 	}
658 
659 	/* a, first record index to write into.
660 	 * b, last record index to write into.
661 	 * a = first index to read (fri) + number of records in the table,
662 	 * b = a + @num - 1.
663 	 * Let N = control->ras_max_num_record_count, then we have,
664 	 * case 0: 0 <= a <= b < N,
665 	 *   just append @num records starting at a;
666 	 * case 1: 0 <= a < N <= b,
667 	 *   append (N - a) records starting at a, and
668 	 *   append the remainder,  b % N + 1, starting at 0.
669 	 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases,
670 	 * case 2a: 0 <= a <= b < N
671 	 *   append num records starting at a; and fix fri if b overwrote it,
672 	 *   and since a <= b, if b overwrote it then a must've also,
673 	 *   and if b didn't overwrite it, then a didn't also.
674 	 * case 2b: 0 <= b < a < N
675 	 *   write num records starting at a, which wraps around 0=N
676 	 *   and overwrite fri unconditionally. Now from case 2a,
677 	 *   this means that b eclipsed fri to overwrite it and wrap
678 	 *   around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally
679 	 *   set fri = b + 1 (mod N).
680 	 * Now, since fri is updated in every case, except the trivial case 0,
681 	 * the number of records present in the table after writing, is,
682 	 * num_recs - 1 = b - fri (mod N), and we take the positive value,
683 	 * by adding an arbitrary multiple of N before taking the modulo N
684 	 * as shown below.
685 	 */
686 	a = control->ras_fri + control->ras_num_recs;
687 	b = a + num  - 1;
688 	if (b < control->ras_max_record_count) {
689 		res = __amdgpu_ras_eeprom_write(control, buf, a, num);
690 	} else if (a < control->ras_max_record_count) {
691 		u32 g0, g1;
692 
693 		g0 = control->ras_max_record_count - a;
694 		g1 = b % control->ras_max_record_count + 1;
695 		res = __amdgpu_ras_eeprom_write(control, buf, a, g0);
696 		if (res)
697 			goto Out;
698 		res = __amdgpu_ras_eeprom_write(control,
699 						buf + g0 * RAS_TABLE_RECORD_SIZE,
700 						0, g1);
701 		if (res)
702 			goto Out;
703 		if (g1 > control->ras_fri)
704 			control->ras_fri = g1 % control->ras_max_record_count;
705 	} else {
706 		a %= control->ras_max_record_count;
707 		b %= control->ras_max_record_count;
708 
709 		if (a <= b) {
710 			/* Note that, b - a + 1 = num. */
711 			res = __amdgpu_ras_eeprom_write(control, buf, a, num);
712 			if (res)
713 				goto Out;
714 			if (b >= control->ras_fri)
715 				control->ras_fri = (b + 1) % control->ras_max_record_count;
716 		} else {
717 			u32 g0, g1;
718 
719 			/* b < a, which means, we write from
720 			 * a to the end of the table, and from
721 			 * the start of the table to b.
722 			 */
723 			g0 = control->ras_max_record_count - a;
724 			g1 = b + 1;
725 			res = __amdgpu_ras_eeprom_write(control, buf, a, g0);
726 			if (res)
727 				goto Out;
728 			res = __amdgpu_ras_eeprom_write(control,
729 							buf + g0 * RAS_TABLE_RECORD_SIZE,
730 							0, g1);
731 			if (res)
732 				goto Out;
733 			control->ras_fri = g1 % control->ras_max_record_count;
734 		}
735 	}
736 	control->ras_num_recs = 1 + (control->ras_max_record_count + b
737 				     - control->ras_fri)
738 		% control->ras_max_record_count;
739 
740 	/*old asics only save pa to eeprom like before*/
741 	if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12)
742 		control->ras_num_pa_recs += num;
743 	else
744 		control->ras_num_mca_recs += num;
745 
746 	control->ras_num_bad_pages = control->ras_num_pa_recs +
747 				control->ras_num_mca_recs * adev->umc.retire_unit;
748 Out:
749 	kfree(buf);
750 	return res;
751 }
752 
753 static int
amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control * control)754 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control)
755 {
756 	struct amdgpu_device *adev = to_amdgpu_device(control);
757 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
758 	u8 *buf, *pp, csum;
759 	u32 buf_size;
760 	int res;
761 
762 	/* Modify the header if it exceeds.
763 	 */
764 	if (amdgpu_bad_page_threshold != 0 &&
765 	    control->ras_num_bad_pages > ras->bad_page_cnt_threshold) {
766 		dev_warn(adev->dev,
767 			"Saved bad pages %d reaches threshold value %d\n",
768 			control->ras_num_bad_pages, ras->bad_page_cnt_threshold);
769 		if ((amdgpu_bad_page_threshold != -1) &&
770 		    (amdgpu_bad_page_threshold != -2)) {
771 			control->tbl_hdr.header = RAS_TABLE_HDR_BAD;
772 			if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) {
773 				control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD;
774 				control->tbl_rai.health_percent = 0;
775 			}
776 			ras->is_rma = true;
777 			/* ignore the -ENOTSUPP return value */
778 			amdgpu_dpm_send_rma_reason(adev);
779 		}
780 	}
781 
782 	if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1)
783 		control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE +
784 					    RAS_TABLE_V2_1_INFO_SIZE +
785 					    control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
786 	else
787 		control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE +
788 					    control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
789 	control->tbl_hdr.checksum = 0;
790 
791 	buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
792 	buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
793 	if (!buf) {
794 		dev_err(adev->dev,
795 			"allocating memory for table of size %d bytes failed\n",
796 			control->tbl_hdr.tbl_size);
797 		res = -ENOMEM;
798 		goto Out;
799 	}
800 
801 	down_read(&adev->reset_domain->sem);
802 	res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
803 				 control->i2c_address +
804 				 control->ras_record_offset,
805 				 buf, buf_size);
806 	up_read(&adev->reset_domain->sem);
807 	if (res < 0) {
808 		dev_err(adev->dev, "EEPROM failed reading records:%d\n", res);
809 		goto Out;
810 	} else if (res < buf_size) {
811 		dev_err(adev->dev, "EEPROM read %d out of %d bytes\n", res,
812 			buf_size);
813 		res = -EIO;
814 		goto Out;
815 	}
816 
817 	/**
818 	 * bad page records have been stored in eeprom,
819 	 * now calculate gpu health percent
820 	 */
821 	if (amdgpu_bad_page_threshold != 0 &&
822 	    control->tbl_hdr.version >= RAS_TABLE_VER_V2_1 &&
823 	    control->ras_num_bad_pages <= ras->bad_page_cnt_threshold)
824 		control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold -
825 						   control->ras_num_bad_pages) * 100) /
826 						   ras->bad_page_cnt_threshold;
827 
828 	/* Recalc the checksum.
829 	 */
830 	csum = 0;
831 	for (pp = buf; pp < buf + buf_size; pp++)
832 		csum += *pp;
833 
834 	csum += __calc_hdr_byte_sum(control);
835 	if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1)
836 		csum += __calc_ras_info_byte_sum(control);
837 	/* avoid sign extension when assigning to "checksum" */
838 	csum = -csum;
839 	control->tbl_hdr.checksum = csum;
840 	res = __write_table_header(control);
841 	if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1)
842 		res = __write_table_ras_info(control);
843 Out:
844 	kfree(buf);
845 	return res;
846 }
847 
848 /**
849  * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table
850  * @control: pointer to control structure
851  * @record: array of records to append
852  * @num: number of records in @record array
853  *
854  * Append @num records to the table, calculate the checksum and write
855  * the table back to EEPROM. The maximum number of records that
856  * can be appended is between 1 and control->ras_max_record_count,
857  * regardless of how many records are already stored in the table.
858  *
859  * Return 0 on success or if EEPROM is not supported, -errno on error.
860  */
amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,const u32 num)861 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
862 			     struct eeprom_table_record *record,
863 			     const u32 num)
864 {
865 	struct amdgpu_device *adev = to_amdgpu_device(control);
866 	int res, i;
867 	uint64_t nps = AMDGPU_NPS1_PARTITION_MODE;
868 
869 	if (!__is_ras_eeprom_supported(adev))
870 		return 0;
871 
872 	if (num == 0) {
873 		dev_err(adev->dev, "will not append 0 records\n");
874 		return -EINVAL;
875 	} else if (num > control->ras_max_record_count) {
876 		dev_err(adev->dev,
877 			"cannot append %d records than the size of table %d\n",
878 			num, control->ras_max_record_count);
879 		return -EINVAL;
880 	}
881 
882 	if (adev->gmc.gmc_funcs->query_mem_partition_mode)
883 		nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
884 
885 	/* set the new channel index flag */
886 	for (i = 0; i < num; i++)
887 		record[i].retired_page |= (nps << UMC_NPS_SHIFT);
888 
889 	mutex_lock(&control->ras_tbl_mutex);
890 
891 	res = amdgpu_ras_eeprom_append_table(control, record, num);
892 	if (!res)
893 		res = amdgpu_ras_eeprom_update_header(control);
894 	if (!res)
895 		amdgpu_ras_debugfs_set_ret_size(control);
896 
897 	mutex_unlock(&control->ras_tbl_mutex);
898 
899 	/* clear channel index flag, the flag is only saved on eeprom */
900 	for (i = 0; i < num; i++)
901 		record[i].retired_page &= ~(nps << UMC_NPS_SHIFT);
902 
903 	return res;
904 }
905 
906 /**
907  * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer
908  * @control: pointer to control structure
909  * @buf: pointer to buffer to read into
910  * @fri: first record index, start reading at this index, absolute index
911  * @num: number of records to read
912  *
913  * The caller must hold the table mutex in @control.
914  * Return 0 on success, -errno otherwise.
915  */
__amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control * control,u8 * buf,const u32 fri,const u32 num)916 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
917 				    u8 *buf, const u32 fri, const u32 num)
918 {
919 	struct amdgpu_device *adev = to_amdgpu_device(control);
920 	u32 buf_size;
921 	int res;
922 
923 	/* i2c may be unstable in gpu reset */
924 	down_read(&adev->reset_domain->sem);
925 	buf_size = num * RAS_TABLE_RECORD_SIZE;
926 	res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
927 				 control->i2c_address +
928 				 RAS_INDEX_TO_OFFSET(control, fri),
929 				 buf, buf_size);
930 	up_read(&adev->reset_domain->sem);
931 	if (res < 0) {
932 		dev_err(adev->dev, "Reading %d EEPROM table records error:%d",
933 			num, res);
934 	} else if (res < buf_size) {
935 		/* Short read, return error.
936 		 */
937 		dev_err(adev->dev, "Read %d records out of %d",
938 			res / RAS_TABLE_RECORD_SIZE, num);
939 		res = -EIO;
940 	} else {
941 		res = 0;
942 	}
943 
944 	return res;
945 }
946 
947 /**
948  * amdgpu_ras_eeprom_read -- read EEPROM
949  * @control: pointer to control structure
950  * @record: array of records to read into
951  * @num: number of records in @record
952  *
953  * Reads num records from the RAS table in EEPROM and
954  * writes the data into @record array.
955  *
956  * Returns 0 on success, -errno on error.
957  */
amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,const u32 num)958 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
959 			   struct eeprom_table_record *record,
960 			   const u32 num)
961 {
962 	struct amdgpu_device *adev = to_amdgpu_device(control);
963 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
964 	int i, res;
965 	u8 *buf, *pp;
966 	u32 g0, g1;
967 
968 	if (!__is_ras_eeprom_supported(adev))
969 		return 0;
970 
971 	if (num == 0) {
972 		dev_err(adev->dev, "will not read 0 records\n");
973 		return -EINVAL;
974 	} else if (num > control->ras_num_recs) {
975 		dev_err(adev->dev, "too many records to read:%d available:%d\n",
976 			num, control->ras_num_recs);
977 		return -EINVAL;
978 	}
979 
980 	buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
981 	if (!buf)
982 		return -ENOMEM;
983 
984 	/* Determine how many records to read, from the first record
985 	 * index, fri, to the end of the table, and from the beginning
986 	 * of the table, such that the total number of records is
987 	 * @num, and we handle wrap around when fri > 0 and
988 	 * fri + num > RAS_MAX_RECORD_COUNT.
989 	 *
990 	 * First we compute the index of the last element
991 	 * which would be fetched from each region,
992 	 * g0 is in [fri, fri + num - 1], and
993 	 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1].
994 	 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of
995 	 * the last element to fetch, we set g0 to _the number_
996 	 * of elements to fetch, @num, since we know that the last
997 	 * indexed to be fetched does not exceed the table.
998 	 *
999 	 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then
1000 	 * we set g0 to the number of elements to read
1001 	 * until the end of the table, and g1 to the number of
1002 	 * elements to read from the beginning of the table.
1003 	 */
1004 	g0 = control->ras_fri + num - 1;
1005 	g1 = g0 % control->ras_max_record_count;
1006 	if (g0 < control->ras_max_record_count) {
1007 		g0 = num;
1008 		g1 = 0;
1009 	} else {
1010 		g0 = control->ras_max_record_count - control->ras_fri;
1011 		g1 += 1;
1012 	}
1013 
1014 	mutex_lock(&control->ras_tbl_mutex);
1015 	res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0);
1016 	if (res)
1017 		goto Out;
1018 	if (g1) {
1019 		res = __amdgpu_ras_eeprom_read(control,
1020 					       buf + g0 * RAS_TABLE_RECORD_SIZE,
1021 					       0, g1);
1022 		if (res)
1023 			goto Out;
1024 	}
1025 
1026 	res = 0;
1027 
1028 	/* Read up everything? Then transform.
1029 	 */
1030 	pp = buf;
1031 	for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) {
1032 		__decode_table_record_from_buf(control, &record[i], pp);
1033 
1034 		/* update bad channel bitmap */
1035 		if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) &&
1036 		    !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {
1037 			control->bad_channel_bitmap |= 1 << record[i].mem_channel;
1038 			con->update_channel_flag = true;
1039 		}
1040 	}
1041 Out:
1042 	kfree(buf);
1043 	mutex_unlock(&control->ras_tbl_mutex);
1044 
1045 	return res;
1046 }
1047 
amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control * control)1048 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control)
1049 {
1050 	/* get available eeprom table version first before eeprom table init */
1051 	amdgpu_ras_set_eeprom_table_version(control);
1052 
1053 	if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1)
1054 		return RAS_MAX_RECORD_COUNT_V2_1;
1055 	else
1056 		return RAS_MAX_RECORD_COUNT;
1057 }
1058 
1059 static ssize_t
amdgpu_ras_debugfs_eeprom_size_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1060 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf,
1061 				    size_t size, loff_t *pos)
1062 {
1063 	struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1064 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1065 	struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
1066 	u8 data[50];
1067 	int res;
1068 
1069 	if (!size)
1070 		return size;
1071 
1072 	if (!ras || !control) {
1073 		res = snprintf(data, sizeof(data), "Not supported\n");
1074 	} else {
1075 		res = snprintf(data, sizeof(data), "%d bytes or %d records\n",
1076 			       RAS_TBL_SIZE_BYTES, control->ras_max_record_count);
1077 	}
1078 
1079 	if (*pos >= res)
1080 		return 0;
1081 
1082 	res -= *pos;
1083 	res = min_t(size_t, res, size);
1084 
1085 	if (copy_to_user(buf, &data[*pos], res))
1086 		return -EFAULT;
1087 
1088 	*pos += res;
1089 
1090 	return res;
1091 }
1092 
1093 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = {
1094 	.owner = THIS_MODULE,
1095 	.read = amdgpu_ras_debugfs_eeprom_size_read,
1096 	.write = NULL,
1097 	.llseek = default_llseek,
1098 };
1099 
1100 static const char *tbl_hdr_str = " Signature    Version  FirstOffs       Size   Checksum\n";
1101 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n";
1102 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1)
1103 static const char *rec_hdr_str = "Index  Offset ErrType Bank/CU          TimeStamp      Offs/Addr MemChl MCUMCID    RetiredPage\n";
1104 static const char *rec_hdr_fmt = "%5d 0x%05X %7s    0x%02X 0x%016llX 0x%012llX   0x%02X    0x%02X 0x%012llX\n";
1105 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1)
1106 
1107 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = {
1108 	"ignore",
1109 	"re",
1110 	"ue",
1111 };
1112 
amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control * control)1113 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control)
1114 {
1115 	return strlen(tbl_hdr_str) + tbl_hdr_fmt_size +
1116 		strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs;
1117 }
1118 
amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control * control)1119 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control)
1120 {
1121 	struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras,
1122 					      eeprom_control);
1123 	struct dentry *de = ras->de_ras_eeprom_table;
1124 
1125 	if (de)
1126 		d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control);
1127 }
1128 
amdgpu_ras_debugfs_table_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1129 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf,
1130 					     size_t size, loff_t *pos)
1131 {
1132 	struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1133 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1134 	struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control;
1135 	const size_t orig_size = size;
1136 	int res = -EFAULT;
1137 	size_t data_len;
1138 
1139 	mutex_lock(&control->ras_tbl_mutex);
1140 
1141 	/* We want *pos - data_len > 0, which means there's
1142 	 * bytes to be printed from data.
1143 	 */
1144 	data_len = strlen(tbl_hdr_str);
1145 	if (*pos < data_len) {
1146 		data_len -= *pos;
1147 		data_len = min_t(size_t, data_len, size);
1148 		if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len))
1149 			goto Out;
1150 		buf += data_len;
1151 		size -= data_len;
1152 		*pos += data_len;
1153 	}
1154 
1155 	data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size;
1156 	if (*pos < data_len && size > 0) {
1157 		u8 data[tbl_hdr_fmt_size + 1];
1158 		loff_t lpos;
1159 
1160 		snprintf(data, sizeof(data), tbl_hdr_fmt,
1161 			 control->tbl_hdr.header,
1162 			 control->tbl_hdr.version,
1163 			 control->tbl_hdr.first_rec_offset,
1164 			 control->tbl_hdr.tbl_size,
1165 			 control->tbl_hdr.checksum);
1166 
1167 		data_len -= *pos;
1168 		data_len = min_t(size_t, data_len, size);
1169 		lpos = *pos - strlen(tbl_hdr_str);
1170 		if (copy_to_user(buf, &data[lpos], data_len))
1171 			goto Out;
1172 		buf += data_len;
1173 		size -= data_len;
1174 		*pos += data_len;
1175 	}
1176 
1177 	data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str);
1178 	if (*pos < data_len && size > 0) {
1179 		loff_t lpos;
1180 
1181 		data_len -= *pos;
1182 		data_len = min_t(size_t, data_len, size);
1183 		lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size;
1184 		if (copy_to_user(buf, &rec_hdr_str[lpos], data_len))
1185 			goto Out;
1186 		buf += data_len;
1187 		size -= data_len;
1188 		*pos += data_len;
1189 	}
1190 
1191 	data_len = amdgpu_ras_debugfs_table_size(control);
1192 	if (*pos < data_len && size > 0) {
1193 		u8 dare[RAS_TABLE_RECORD_SIZE];
1194 		u8 data[rec_hdr_fmt_size + 1];
1195 		struct eeprom_table_record record;
1196 		int s, r;
1197 
1198 		/* Find the starting record index
1199 		 */
1200 		s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
1201 			strlen(rec_hdr_str);
1202 		s = s / rec_hdr_fmt_size;
1203 		r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
1204 			strlen(rec_hdr_str);
1205 		r = r % rec_hdr_fmt_size;
1206 
1207 		for ( ; size > 0 && s < control->ras_num_recs; s++) {
1208 			u32 ai = RAS_RI_TO_AI(control, s);
1209 			/* Read a single record
1210 			 */
1211 			res = __amdgpu_ras_eeprom_read(control, dare, ai, 1);
1212 			if (res)
1213 				goto Out;
1214 			__decode_table_record_from_buf(control, &record, dare);
1215 			snprintf(data, sizeof(data), rec_hdr_fmt,
1216 				 s,
1217 				 RAS_INDEX_TO_OFFSET(control, ai),
1218 				 record_err_type_str[record.err_type],
1219 				 record.bank,
1220 				 record.ts,
1221 				 record.offset,
1222 				 record.mem_channel,
1223 				 record.mcumc_id,
1224 				 record.retired_page);
1225 
1226 			data_len = min_t(size_t, rec_hdr_fmt_size - r, size);
1227 			if (copy_to_user(buf, &data[r], data_len)) {
1228 				res = -EFAULT;
1229 				goto Out;
1230 			}
1231 			buf += data_len;
1232 			size -= data_len;
1233 			*pos += data_len;
1234 			r = 0;
1235 		}
1236 	}
1237 	res = 0;
1238 Out:
1239 	mutex_unlock(&control->ras_tbl_mutex);
1240 	return res < 0 ? res : orig_size - size;
1241 }
1242 
1243 static ssize_t
amdgpu_ras_debugfs_eeprom_table_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1244 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf,
1245 				     size_t size, loff_t *pos)
1246 {
1247 	struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1248 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1249 	struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
1250 	u8 data[81];
1251 	int res;
1252 
1253 	if (!size)
1254 		return size;
1255 
1256 	if (!ras || !control) {
1257 		res = snprintf(data, sizeof(data), "Not supported\n");
1258 		if (*pos >= res)
1259 			return 0;
1260 
1261 		res -= *pos;
1262 		res = min_t(size_t, res, size);
1263 
1264 		if (copy_to_user(buf, &data[*pos], res))
1265 			return -EFAULT;
1266 
1267 		*pos += res;
1268 
1269 		return res;
1270 	} else {
1271 		return amdgpu_ras_debugfs_table_read(f, buf, size, pos);
1272 	}
1273 }
1274 
1275 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = {
1276 	.owner = THIS_MODULE,
1277 	.read = amdgpu_ras_debugfs_eeprom_table_read,
1278 	.write = NULL,
1279 	.llseek = default_llseek,
1280 };
1281 
1282 /**
1283  * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum
1284  * @control: pointer to control structure
1285  *
1286  * Check the checksum of the stored in EEPROM RAS table.
1287  *
1288  * Return 0 if the checksum is correct,
1289  * positive if it is not correct, and
1290  * -errno on I/O error.
1291  */
__verify_ras_table_checksum(struct amdgpu_ras_eeprom_control * control)1292 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control)
1293 {
1294 	struct amdgpu_device *adev = to_amdgpu_device(control);
1295 	int buf_size, res;
1296 	u8  csum, *buf, *pp;
1297 
1298 	if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1)
1299 		buf_size = RAS_TABLE_HEADER_SIZE +
1300 			   RAS_TABLE_V2_1_INFO_SIZE +
1301 			   control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
1302 	else
1303 		buf_size = RAS_TABLE_HEADER_SIZE +
1304 			   control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
1305 
1306 	buf = kzalloc(buf_size, GFP_KERNEL);
1307 	if (!buf) {
1308 		dev_err(adev->dev,
1309 			"Out of memory checking RAS table checksum.\n");
1310 		return -ENOMEM;
1311 	}
1312 
1313 	res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
1314 				 control->i2c_address +
1315 				 control->ras_header_offset,
1316 				 buf, buf_size);
1317 	if (res < buf_size) {
1318 		dev_err(adev->dev, "Partial read for checksum, res:%d\n", res);
1319 		/* On partial reads, return -EIO.
1320 		 */
1321 		if (res >= 0)
1322 			res = -EIO;
1323 		goto Out;
1324 	}
1325 
1326 	csum = 0;
1327 	for (pp = buf; pp < buf + buf_size; pp++)
1328 		csum += *pp;
1329 Out:
1330 	kfree(buf);
1331 	return res < 0 ? res : csum;
1332 }
1333 
__read_table_ras_info(struct amdgpu_ras_eeprom_control * control)1334 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control)
1335 {
1336 	struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai;
1337 	struct amdgpu_device *adev = to_amdgpu_device(control);
1338 	unsigned char *buf;
1339 	int res;
1340 
1341 	buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL);
1342 	if (!buf) {
1343 		dev_err(adev->dev,
1344 			"Failed to alloc buf to read EEPROM table ras info\n");
1345 		return -ENOMEM;
1346 	}
1347 
1348 	/**
1349 	 * EEPROM table V2_1 supports ras info,
1350 	 * read EEPROM table ras info
1351 	 */
1352 	res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
1353 				 control->i2c_address + control->ras_info_offset,
1354 				 buf, RAS_TABLE_V2_1_INFO_SIZE);
1355 	if (res < RAS_TABLE_V2_1_INFO_SIZE) {
1356 		dev_err(adev->dev,
1357 			"Failed to read EEPROM table ras info, res:%d", res);
1358 		res = res >= 0 ? -EIO : res;
1359 		goto Out;
1360 	}
1361 
1362 	__decode_table_ras_info_from_buf(rai, buf);
1363 
1364 Out:
1365 	kfree(buf);
1366 	return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res;
1367 }
1368 
amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control * control)1369 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
1370 {
1371 	struct amdgpu_device *adev = to_amdgpu_device(control);
1372 	unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 };
1373 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
1374 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1375 	int res;
1376 
1377 	ras->is_rma = false;
1378 
1379 	if (!__is_ras_eeprom_supported(adev))
1380 		return 0;
1381 
1382 	/* Verify i2c adapter is initialized */
1383 	if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo)
1384 		return -ENOENT;
1385 
1386 	if (!__get_eeprom_i2c_addr(adev, control))
1387 		return -EINVAL;
1388 
1389 	control->ras_header_offset = RAS_HDR_START;
1390 	control->ras_info_offset = RAS_TABLE_V2_1_INFO_START;
1391 	mutex_init(&control->ras_tbl_mutex);
1392 
1393 	/* Read the table header from EEPROM address */
1394 	res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
1395 				 control->i2c_address + control->ras_header_offset,
1396 				 buf, RAS_TABLE_HEADER_SIZE);
1397 	if (res < RAS_TABLE_HEADER_SIZE) {
1398 		dev_err(adev->dev, "Failed to read EEPROM table header, res:%d",
1399 			res);
1400 		return res >= 0 ? -EIO : res;
1401 	}
1402 
1403 	__decode_table_header_from_buf(hdr, buf);
1404 
1405 	if (hdr->header != RAS_TABLE_HDR_VAL &&
1406 	    hdr->header != RAS_TABLE_HDR_BAD) {
1407 		dev_info(adev->dev, "Creating a new EEPROM table");
1408 		return amdgpu_ras_eeprom_reset_table(control);
1409 	}
1410 
1411 	switch (hdr->version) {
1412 	case RAS_TABLE_VER_V2_1:
1413 	case RAS_TABLE_VER_V3:
1414 		control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr);
1415 		control->ras_record_offset = RAS_RECORD_START_V2_1;
1416 		control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1;
1417 		break;
1418 	case RAS_TABLE_VER_V1:
1419 		control->ras_num_recs = RAS_NUM_RECS(hdr);
1420 		control->ras_record_offset = RAS_RECORD_START;
1421 		control->ras_max_record_count = RAS_MAX_RECORD_COUNT;
1422 		break;
1423 	default:
1424 		dev_err(adev->dev,
1425 			"RAS header invalid, unsupported version: %u",
1426 			hdr->version);
1427 		return -EINVAL;
1428 	}
1429 
1430 	if (control->ras_num_recs > control->ras_max_record_count) {
1431 		dev_err(adev->dev,
1432 			"RAS header invalid, records in header: %u max allowed :%u",
1433 			control->ras_num_recs, control->ras_max_record_count);
1434 		return -EINVAL;
1435 	}
1436 
1437 	control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset);
1438 	control->ras_num_mca_recs = 0;
1439 	control->ras_num_pa_recs = 0;
1440 	return 0;
1441 }
1442 
amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control * control)1443 int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control)
1444 {
1445 	struct amdgpu_device *adev = to_amdgpu_device(control);
1446 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
1447 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1448 	int res = 0;
1449 
1450 	if (!__is_ras_eeprom_supported(adev))
1451 		return 0;
1452 
1453 	/* Verify i2c adapter is initialized */
1454 	if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo)
1455 		return -ENOENT;
1456 
1457 	if (!__get_eeprom_i2c_addr(adev, control))
1458 		return -EINVAL;
1459 
1460 	control->ras_num_bad_pages = control->ras_num_pa_recs +
1461 			control->ras_num_mca_recs * adev->umc.retire_unit;
1462 
1463 	if (hdr->header == RAS_TABLE_HDR_VAL) {
1464 		dev_dbg(adev->dev,
1465 			"Found existing EEPROM table with %d records",
1466 			control->ras_num_bad_pages);
1467 
1468 		if (hdr->version >= RAS_TABLE_VER_V2_1) {
1469 			res = __read_table_ras_info(control);
1470 			if (res)
1471 				return res;
1472 		}
1473 
1474 		res = __verify_ras_table_checksum(control);
1475 		if (res)
1476 			dev_err(adev->dev,
1477 				"RAS table incorrect checksum or error:%d\n",
1478 				res);
1479 
1480 		/* Warn if we are at 90% of the threshold or above
1481 		 */
1482 		if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold)
1483 			dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d",
1484 					control->ras_num_bad_pages,
1485 					ras->bad_page_cnt_threshold);
1486 	} else if (hdr->header == RAS_TABLE_HDR_BAD &&
1487 		   amdgpu_bad_page_threshold != 0) {
1488 		if (hdr->version >= RAS_TABLE_VER_V2_1) {
1489 			res = __read_table_ras_info(control);
1490 			if (res)
1491 				return res;
1492 		}
1493 
1494 		res = __verify_ras_table_checksum(control);
1495 		if (res) {
1496 			dev_err(adev->dev,
1497 				"RAS Table incorrect checksum or error:%d\n",
1498 				res);
1499 			return -EINVAL;
1500 		}
1501 		if (ras->bad_page_cnt_threshold >= control->ras_num_bad_pages) {
1502 			/* This means that, the threshold was increased since
1503 			 * the last time the system was booted, and now,
1504 			 * ras->bad_page_cnt_threshold - control->num_recs > 0,
1505 			 * so that at least one more record can be saved,
1506 			 * before the page count threshold is reached.
1507 			 */
1508 			dev_info(adev->dev,
1509 				 "records:%d threshold:%d, resetting "
1510 				 "RAS table header signature",
1511 				 control->ras_num_bad_pages,
1512 				 ras->bad_page_cnt_threshold);
1513 			res = amdgpu_ras_eeprom_correct_header_tag(control,
1514 								   RAS_TABLE_HDR_VAL);
1515 		} else {
1516 			dev_warn(adev->dev,
1517 				"RAS records:%d exceed threshold:%d\n",
1518 				control->ras_num_bad_pages, ras->bad_page_cnt_threshold);
1519 			if ((amdgpu_bad_page_threshold == -1) ||
1520 			    (amdgpu_bad_page_threshold == -2)) {
1521 				res = 0;
1522 				dev_warn(adev->dev,
1523 					 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n");
1524 			} else {
1525 				ras->is_rma = true;
1526 				dev_warn(adev->dev,
1527 					 "User defined threshold is set, runtime service will be halt when threshold is reached\n");
1528 			}
1529 		}
1530 	}
1531 
1532 	return res < 0 ? res : 0;
1533 }
1534 
amdgpu_ras_eeprom_check_and_recover(struct amdgpu_device * adev)1535 void amdgpu_ras_eeprom_check_and_recover(struct amdgpu_device *adev)
1536 {
1537 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1538 	struct amdgpu_ras_eeprom_control *control;
1539 	int res;
1540 
1541 	if (!__is_ras_eeprom_supported(adev) || !ras)
1542 		return;
1543 	control = &ras->eeprom_control;
1544 	if (!control->is_eeprom_valid)
1545 		return;
1546 	res = __verify_ras_table_checksum(control);
1547 	if (res) {
1548 		dev_warn(adev->dev,
1549 			"RAS table incorrect checksum or error:%d, try to recover\n",
1550 			res);
1551 		if (!amdgpu_ras_eeprom_reset_table(control))
1552 			if (!amdgpu_ras_save_bad_pages(adev, NULL))
1553 				if (!__verify_ras_table_checksum(control)) {
1554 					dev_info(adev->dev, "RAS table recovery succeed\n");
1555 					return;
1556 				}
1557 		dev_err(adev->dev, "RAS table recovery failed\n");
1558 		control->is_eeprom_valid = false;
1559 	}
1560 	return;
1561 }