1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/ktime.h>
29 #include <linux/module.h>
30 #include <linux/pagemap.h>
31 #include <linux/pci.h>
32 #include <linux/dma-buf.h>
33
34 #include <drm/amdgpu_drm.h>
35 #include <drm/drm_drv.h>
36 #include <drm/drm_exec.h>
37 #include <drm/drm_gem_ttm_helper.h>
38 #include <drm/ttm/ttm_tt.h>
39
40 #include "amdgpu.h"
41 #include "amdgpu_display.h"
42 #include "amdgpu_dma_buf.h"
43 #include "amdgpu_hmm.h"
44 #include "amdgpu_xgmi.h"
45
46 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs;
47
amdgpu_gem_fault(struct vm_fault * vmf)48 static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf)
49 {
50 struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
51 struct drm_device *ddev = bo->base.dev;
52 vm_fault_t ret;
53 int idx;
54
55 ret = ttm_bo_vm_reserve(bo, vmf);
56 if (ret)
57 return ret;
58
59 if (drm_dev_enter(ddev, &idx)) {
60 ret = amdgpu_bo_fault_reserve_notify(bo);
61 if (ret) {
62 drm_dev_exit(idx);
63 goto unlock;
64 }
65
66 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
67 TTM_BO_VM_NUM_PREFAULT);
68
69 drm_dev_exit(idx);
70 } else {
71 ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot);
72 }
73 if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
74 return ret;
75
76 unlock:
77 dma_resv_unlock(bo->base.resv);
78 return ret;
79 }
80
81 static const struct vm_operations_struct amdgpu_gem_vm_ops = {
82 .fault = amdgpu_gem_fault,
83 .open = ttm_bo_vm_open,
84 .close = ttm_bo_vm_close,
85 .access = ttm_bo_vm_access
86 };
87
amdgpu_gem_object_free(struct drm_gem_object * gobj)88 static void amdgpu_gem_object_free(struct drm_gem_object *gobj)
89 {
90 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
91
92 if (robj) {
93 amdgpu_hmm_unregister(robj);
94 amdgpu_bo_unref(&robj);
95 }
96 }
97
amdgpu_gem_object_create(struct amdgpu_device * adev,unsigned long size,int alignment,u32 initial_domain,u64 flags,enum ttm_bo_type type,struct dma_resv * resv,struct drm_gem_object ** obj,int8_t xcp_id_plus1)98 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
99 int alignment, u32 initial_domain,
100 u64 flags, enum ttm_bo_type type,
101 struct dma_resv *resv,
102 struct drm_gem_object **obj, int8_t xcp_id_plus1)
103 {
104 struct amdgpu_bo *bo;
105 struct amdgpu_bo_user *ubo;
106 struct amdgpu_bo_param bp;
107 int r;
108
109 memset(&bp, 0, sizeof(bp));
110 *obj = NULL;
111 flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
112
113 bp.size = size;
114 bp.byte_align = alignment;
115 bp.type = type;
116 bp.resv = resv;
117 bp.preferred_domain = initial_domain;
118 bp.flags = flags;
119 bp.domain = initial_domain;
120 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
121 bp.xcp_id_plus1 = xcp_id_plus1;
122
123 r = amdgpu_bo_create_user(adev, &bp, &ubo);
124 if (r)
125 return r;
126
127 bo = &ubo->bo;
128 *obj = &bo->tbo.base;
129 (*obj)->funcs = &amdgpu_gem_object_funcs;
130
131 return 0;
132 }
133
amdgpu_gem_force_release(struct amdgpu_device * adev)134 void amdgpu_gem_force_release(struct amdgpu_device *adev)
135 {
136 struct drm_device *ddev = adev_to_drm(adev);
137 struct drm_file *file;
138
139 mutex_lock(&ddev->filelist_mutex);
140
141 list_for_each_entry(file, &ddev->filelist, lhead) {
142 struct drm_gem_object *gobj;
143 int handle;
144
145 WARN_ONCE(1, "Still active user space clients!\n");
146 spin_lock(&file->table_lock);
147 idr_for_each_entry(&file->object_idr, gobj, handle) {
148 WARN_ONCE(1, "And also active allocations!\n");
149 drm_gem_object_put(gobj);
150 }
151 idr_destroy(&file->object_idr);
152 spin_unlock(&file->table_lock);
153 }
154
155 mutex_unlock(&ddev->filelist_mutex);
156 }
157
158 /*
159 * Call from drm_gem_handle_create which appear in both new and open ioctl
160 * case.
161 */
amdgpu_gem_object_open(struct drm_gem_object * obj,struct drm_file * file_priv)162 static int amdgpu_gem_object_open(struct drm_gem_object *obj,
163 struct drm_file *file_priv)
164 {
165 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
166 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
167 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
168 struct amdgpu_vm *vm = &fpriv->vm;
169 struct amdgpu_bo_va *bo_va;
170 struct mm_struct *mm;
171 int r;
172
173 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
174 if (mm && mm != current->mm)
175 return -EPERM;
176
177 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
178 !amdgpu_vm_is_bo_always_valid(vm, abo))
179 return -EPERM;
180
181 r = amdgpu_bo_reserve(abo, false);
182 if (r)
183 return r;
184
185 bo_va = amdgpu_vm_bo_find(vm, abo);
186 if (!bo_va)
187 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
188 else
189 ++bo_va->ref_count;
190 amdgpu_bo_unreserve(abo);
191
192 /* Validate and add eviction fence to DMABuf imports with dynamic
193 * attachment in compute VMs. Re-validation will be done by
194 * amdgpu_vm_validate. Fences are on the reservation shared with the
195 * export, which is currently required to be validated and fenced
196 * already by amdgpu_amdkfd_gpuvm_restore_process_bos.
197 *
198 * Nested locking below for the case that a GEM object is opened in
199 * kfd_mem_export_dmabuf. Since the lock below is only taken for imports,
200 * but not for export, this is a different lock class that cannot lead to
201 * circular lock dependencies.
202 */
203 if (!vm->is_compute_context || !vm->process_info)
204 return 0;
205 if (!obj->import_attach ||
206 !dma_buf_is_dynamic(obj->import_attach->dmabuf))
207 return 0;
208 mutex_lock_nested(&vm->process_info->lock, 1);
209 if (!WARN_ON(!vm->process_info->eviction_fence)) {
210 r = amdgpu_amdkfd_bo_validate_and_fence(abo, AMDGPU_GEM_DOMAIN_GTT,
211 &vm->process_info->eviction_fence->base);
212 if (r) {
213 struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm);
214
215 dev_warn(adev->dev, "validate_and_fence failed: %d\n", r);
216 if (ti) {
217 dev_warn(adev->dev, "pid %d\n", ti->pid);
218 amdgpu_vm_put_task_info(ti);
219 }
220 }
221 }
222 mutex_unlock(&vm->process_info->lock);
223
224 return r;
225 }
226
amdgpu_gem_object_close(struct drm_gem_object * obj,struct drm_file * file_priv)227 static void amdgpu_gem_object_close(struct drm_gem_object *obj,
228 struct drm_file *file_priv)
229 {
230 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
231 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
232 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
233 struct amdgpu_vm *vm = &fpriv->vm;
234
235 struct dma_fence *fence = NULL;
236 struct amdgpu_bo_va *bo_va;
237 struct drm_exec exec;
238 long r;
239
240 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
241 drm_exec_until_all_locked(&exec) {
242 r = drm_exec_prepare_obj(&exec, &bo->tbo.base, 1);
243 drm_exec_retry_on_contention(&exec);
244 if (unlikely(r))
245 goto out_unlock;
246
247 r = amdgpu_vm_lock_pd(vm, &exec, 0);
248 drm_exec_retry_on_contention(&exec);
249 if (unlikely(r))
250 goto out_unlock;
251 }
252
253 bo_va = amdgpu_vm_bo_find(vm, bo);
254 if (!bo_va || --bo_va->ref_count)
255 goto out_unlock;
256
257 amdgpu_vm_bo_del(adev, bo_va);
258 if (!amdgpu_vm_ready(vm))
259 goto out_unlock;
260
261 r = amdgpu_vm_clear_freed(adev, vm, &fence);
262 if (unlikely(r < 0))
263 dev_err(adev->dev, "failed to clear page "
264 "tables on GEM object close (%ld)\n", r);
265 if (r || !fence)
266 goto out_unlock;
267
268 amdgpu_bo_fence(bo, fence, true);
269 dma_fence_put(fence);
270
271 out_unlock:
272 if (r)
273 dev_err(adev->dev, "leaking bo va (%ld)\n", r);
274 drm_exec_fini(&exec);
275 }
276
amdgpu_gem_object_mmap(struct drm_gem_object * obj,struct vm_area_struct * vma)277 static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
278 {
279 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
280
281 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
282 return -EPERM;
283 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
284 return -EPERM;
285
286 /* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings
287 * for debugger access to invisible VRAM. Should have used MAP_SHARED
288 * instead. Clearing VM_MAYWRITE prevents the mapping from ever
289 * becoming writable and makes is_cow_mapping(vm_flags) false.
290 */
291 if (is_cow_mapping(vma->vm_flags) &&
292 !(vma->vm_flags & VM_ACCESS_FLAGS))
293 vm_flags_clear(vma, VM_MAYWRITE);
294
295 return drm_gem_ttm_mmap(obj, vma);
296 }
297
298 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = {
299 .free = amdgpu_gem_object_free,
300 .open = amdgpu_gem_object_open,
301 .close = amdgpu_gem_object_close,
302 .export = amdgpu_gem_prime_export,
303 .vmap = drm_gem_ttm_vmap,
304 .vunmap = drm_gem_ttm_vunmap,
305 .mmap = amdgpu_gem_object_mmap,
306 .vm_ops = &amdgpu_gem_vm_ops,
307 };
308
309 /*
310 * GEM ioctls.
311 */
amdgpu_gem_create_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)312 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
313 struct drm_file *filp)
314 {
315 struct amdgpu_device *adev = drm_to_adev(dev);
316 struct amdgpu_fpriv *fpriv = filp->driver_priv;
317 struct amdgpu_vm *vm = &fpriv->vm;
318 union drm_amdgpu_gem_create *args = data;
319 uint64_t flags = args->in.domain_flags;
320 uint64_t size = args->in.bo_size;
321 struct dma_resv *resv = NULL;
322 struct drm_gem_object *gobj;
323 uint32_t handle, initial_domain;
324 int r;
325
326 /* reject DOORBELLs until userspace code to use it is available */
327 if (args->in.domains & AMDGPU_GEM_DOMAIN_DOORBELL)
328 return -EINVAL;
329
330 /* reject invalid gem flags */
331 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
332 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
333 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
334 AMDGPU_GEM_CREATE_VRAM_CLEARED |
335 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
336 AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
337 AMDGPU_GEM_CREATE_ENCRYPTED |
338 AMDGPU_GEM_CREATE_GFX12_DCC |
339 AMDGPU_GEM_CREATE_DISCARDABLE))
340 return -EINVAL;
341
342 /* reject invalid gem domains */
343 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
344 return -EINVAL;
345
346 if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
347 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n");
348 return -EINVAL;
349 }
350
351 /* always clear VRAM */
352 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
353
354 /* create a gem object to contain this object in */
355 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
356 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
357 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
358 /* if gds bo is created from user space, it must be
359 * passed to bo list
360 */
361 DRM_ERROR("GDS bo cannot be per-vm-bo\n");
362 return -EINVAL;
363 }
364 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
365 }
366
367 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
368 r = amdgpu_bo_reserve(vm->root.bo, false);
369 if (r)
370 return r;
371
372 resv = vm->root.bo->tbo.base.resv;
373 }
374
375 initial_domain = (u32)(0xffffffff & args->in.domains);
376 retry:
377 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
378 initial_domain,
379 flags, ttm_bo_type_device, resv, &gobj, fpriv->xcp_id + 1);
380 if (r && r != -ERESTARTSYS) {
381 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
382 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
383 goto retry;
384 }
385
386 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
387 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
388 goto retry;
389 }
390 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",
391 size, initial_domain, args->in.alignment, r);
392 }
393
394 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
395 if (!r) {
396 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
397
398 abo->parent = amdgpu_bo_ref(vm->root.bo);
399 }
400 amdgpu_bo_unreserve(vm->root.bo);
401 }
402 if (r)
403 return r;
404
405 r = drm_gem_handle_create(filp, gobj, &handle);
406 /* drop reference from allocate - handle holds it now */
407 drm_gem_object_put(gobj);
408 if (r)
409 return r;
410
411 memset(args, 0, sizeof(*args));
412 args->out.handle = handle;
413 return 0;
414 }
415
amdgpu_gem_userptr_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)416 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
417 struct drm_file *filp)
418 {
419 struct ttm_operation_ctx ctx = { true, false };
420 struct amdgpu_device *adev = drm_to_adev(dev);
421 struct drm_amdgpu_gem_userptr *args = data;
422 struct amdgpu_fpriv *fpriv = filp->driver_priv;
423 struct drm_gem_object *gobj;
424 struct hmm_range *range;
425 struct amdgpu_bo *bo;
426 uint32_t handle;
427 int r;
428
429 args->addr = untagged_addr(args->addr);
430
431 if (offset_in_page(args->addr | args->size))
432 return -EINVAL;
433
434 /* reject unknown flag values */
435 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
436 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
437 AMDGPU_GEM_USERPTR_REGISTER))
438 return -EINVAL;
439
440 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
441 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
442
443 /* if we want to write to it we must install a MMU notifier */
444 return -EACCES;
445 }
446
447 /* create a gem object to contain this object in */
448 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
449 0, ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1);
450 if (r)
451 return r;
452
453 bo = gem_to_amdgpu_bo(gobj);
454 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
455 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
456 r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags);
457 if (r)
458 goto release_object;
459
460 r = amdgpu_hmm_register(bo, args->addr);
461 if (r)
462 goto release_object;
463
464 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
465 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
466 &range);
467 if (r)
468 goto release_object;
469
470 r = amdgpu_bo_reserve(bo, true);
471 if (r)
472 goto user_pages_done;
473
474 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
475 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
476 amdgpu_bo_unreserve(bo);
477 if (r)
478 goto user_pages_done;
479 }
480
481 r = drm_gem_handle_create(filp, gobj, &handle);
482 if (r)
483 goto user_pages_done;
484
485 args->handle = handle;
486
487 user_pages_done:
488 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
489 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
490
491 release_object:
492 drm_gem_object_put(gobj);
493
494 return r;
495 }
496
amdgpu_mode_dumb_mmap(struct drm_file * filp,struct drm_device * dev,uint32_t handle,uint64_t * offset_p)497 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
498 struct drm_device *dev,
499 uint32_t handle, uint64_t *offset_p)
500 {
501 struct drm_gem_object *gobj;
502 struct amdgpu_bo *robj;
503
504 gobj = drm_gem_object_lookup(filp, handle);
505 if (!gobj)
506 return -ENOENT;
507
508 robj = gem_to_amdgpu_bo(gobj);
509 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
510 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
511 drm_gem_object_put(gobj);
512 return -EPERM;
513 }
514 *offset_p = amdgpu_bo_mmap_offset(robj);
515 drm_gem_object_put(gobj);
516 return 0;
517 }
518
amdgpu_gem_mmap_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)519 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
520 struct drm_file *filp)
521 {
522 union drm_amdgpu_gem_mmap *args = data;
523 uint32_t handle = args->in.handle;
524
525 memset(args, 0, sizeof(*args));
526 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
527 }
528
529 /**
530 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
531 *
532 * @timeout_ns: timeout in ns
533 *
534 * Calculate the timeout in jiffies from an absolute timeout in ns.
535 */
amdgpu_gem_timeout(uint64_t timeout_ns)536 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
537 {
538 unsigned long timeout_jiffies;
539 ktime_t timeout;
540
541 /* clamp timeout if it's to large */
542 if (((int64_t)timeout_ns) < 0)
543 return MAX_SCHEDULE_TIMEOUT;
544
545 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
546 if (ktime_to_ns(timeout) < 0)
547 return 0;
548
549 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
550 /* clamp timeout to avoid unsigned-> signed overflow */
551 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT)
552 return MAX_SCHEDULE_TIMEOUT - 1;
553
554 return timeout_jiffies;
555 }
556
amdgpu_gem_wait_idle_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)557 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
558 struct drm_file *filp)
559 {
560 union drm_amdgpu_gem_wait_idle *args = data;
561 struct drm_gem_object *gobj;
562 struct amdgpu_bo *robj;
563 uint32_t handle = args->in.handle;
564 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
565 int r = 0;
566 long ret;
567
568 gobj = drm_gem_object_lookup(filp, handle);
569 if (!gobj)
570 return -ENOENT;
571
572 robj = gem_to_amdgpu_bo(gobj);
573 ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ,
574 true, timeout);
575
576 /* ret == 0 means not signaled,
577 * ret > 0 means signaled
578 * ret < 0 means interrupted before timeout
579 */
580 if (ret >= 0) {
581 memset(args, 0, sizeof(*args));
582 args->out.status = (ret == 0);
583 } else
584 r = ret;
585
586 drm_gem_object_put(gobj);
587 return r;
588 }
589
amdgpu_gem_metadata_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)590 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
591 struct drm_file *filp)
592 {
593 struct drm_amdgpu_gem_metadata *args = data;
594 struct drm_gem_object *gobj;
595 struct amdgpu_bo *robj;
596 int r = -1;
597
598 DRM_DEBUG("%d\n", args->handle);
599 gobj = drm_gem_object_lookup(filp, args->handle);
600 if (gobj == NULL)
601 return -ENOENT;
602 robj = gem_to_amdgpu_bo(gobj);
603
604 r = amdgpu_bo_reserve(robj, false);
605 if (unlikely(r != 0))
606 goto out;
607
608 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
609 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
610 r = amdgpu_bo_get_metadata(robj, args->data.data,
611 sizeof(args->data.data),
612 &args->data.data_size_bytes,
613 &args->data.flags);
614 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
615 if (args->data.data_size_bytes > sizeof(args->data.data)) {
616 r = -EINVAL;
617 goto unreserve;
618 }
619 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
620 if (!r)
621 r = amdgpu_bo_set_metadata(robj, args->data.data,
622 args->data.data_size_bytes,
623 args->data.flags);
624 }
625
626 unreserve:
627 amdgpu_bo_unreserve(robj);
628 out:
629 drm_gem_object_put(gobj);
630 return r;
631 }
632
633 /**
634 * amdgpu_gem_va_update_vm -update the bo_va in its VM
635 *
636 * @adev: amdgpu_device pointer
637 * @vm: vm to update
638 * @bo_va: bo_va to update
639 * @operation: map, unmap or clear
640 *
641 * Update the bo_va directly after setting its address. Errors are not
642 * vital here, so they are not reported back to userspace.
643 */
amdgpu_gem_va_update_vm(struct amdgpu_device * adev,struct amdgpu_vm * vm,struct amdgpu_bo_va * bo_va,uint32_t operation)644 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
645 struct amdgpu_vm *vm,
646 struct amdgpu_bo_va *bo_va,
647 uint32_t operation)
648 {
649 int r;
650
651 if (!amdgpu_vm_ready(vm))
652 return;
653
654 r = amdgpu_vm_clear_freed(adev, vm, NULL);
655 if (r)
656 goto error;
657
658 if (operation == AMDGPU_VA_OP_MAP ||
659 operation == AMDGPU_VA_OP_REPLACE) {
660 r = amdgpu_vm_bo_update(adev, bo_va, false);
661 if (r)
662 goto error;
663 }
664
665 r = amdgpu_vm_update_pdes(adev, vm, false);
666
667 error:
668 if (r && r != -ERESTARTSYS)
669 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
670 }
671
672 /**
673 * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags
674 *
675 * @adev: amdgpu_device pointer
676 * @flags: GEM UAPI flags
677 *
678 * Returns the GEM UAPI flags mapped into hardware for the ASIC.
679 */
amdgpu_gem_va_map_flags(struct amdgpu_device * adev,uint32_t flags)680 uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags)
681 {
682 uint64_t pte_flag = 0;
683
684 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
685 pte_flag |= AMDGPU_PTE_EXECUTABLE;
686 if (flags & AMDGPU_VM_PAGE_READABLE)
687 pte_flag |= AMDGPU_PTE_READABLE;
688 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
689 pte_flag |= AMDGPU_PTE_WRITEABLE;
690 if (flags & AMDGPU_VM_PAGE_PRT)
691 pte_flag |= AMDGPU_PTE_PRT_FLAG(adev);
692 if (flags & AMDGPU_VM_PAGE_NOALLOC)
693 pte_flag |= AMDGPU_PTE_NOALLOC;
694
695 if (adev->gmc.gmc_funcs->map_mtype)
696 pte_flag |= amdgpu_gmc_map_mtype(adev,
697 flags & AMDGPU_VM_MTYPE_MASK);
698
699 return pte_flag;
700 }
701
amdgpu_gem_va_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)702 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
703 struct drm_file *filp)
704 {
705 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
706 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
707 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK |
708 AMDGPU_VM_PAGE_NOALLOC;
709 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
710 AMDGPU_VM_PAGE_PRT;
711
712 struct drm_amdgpu_gem_va *args = data;
713 struct drm_gem_object *gobj;
714 struct amdgpu_device *adev = drm_to_adev(dev);
715 struct amdgpu_fpriv *fpriv = filp->driver_priv;
716 struct amdgpu_bo *abo;
717 struct amdgpu_bo_va *bo_va;
718 struct drm_exec exec;
719 uint64_t va_flags;
720 uint64_t vm_size;
721 int r = 0;
722
723 if (args->va_address < AMDGPU_VA_RESERVED_BOTTOM) {
724 dev_dbg(dev->dev,
725 "va_address 0x%llx is in reserved area 0x%llx\n",
726 args->va_address, AMDGPU_VA_RESERVED_BOTTOM);
727 return -EINVAL;
728 }
729
730 if (args->va_address >= AMDGPU_GMC_HOLE_START &&
731 args->va_address < AMDGPU_GMC_HOLE_END) {
732 dev_dbg(dev->dev,
733 "va_address 0x%llx is in VA hole 0x%llx-0x%llx\n",
734 args->va_address, AMDGPU_GMC_HOLE_START,
735 AMDGPU_GMC_HOLE_END);
736 return -EINVAL;
737 }
738
739 args->va_address &= AMDGPU_GMC_HOLE_MASK;
740
741 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
742 vm_size -= AMDGPU_VA_RESERVED_TOP;
743 if (args->va_address + args->map_size > vm_size) {
744 dev_dbg(dev->dev,
745 "va_address 0x%llx is in top reserved area 0x%llx\n",
746 args->va_address + args->map_size, vm_size);
747 return -EINVAL;
748 }
749
750 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
751 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n",
752 args->flags);
753 return -EINVAL;
754 }
755
756 switch (args->operation) {
757 case AMDGPU_VA_OP_MAP:
758 case AMDGPU_VA_OP_UNMAP:
759 case AMDGPU_VA_OP_CLEAR:
760 case AMDGPU_VA_OP_REPLACE:
761 break;
762 default:
763 dev_dbg(dev->dev, "unsupported operation %d\n",
764 args->operation);
765 return -EINVAL;
766 }
767
768 if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
769 !(args->flags & AMDGPU_VM_PAGE_PRT)) {
770 gobj = drm_gem_object_lookup(filp, args->handle);
771 if (gobj == NULL)
772 return -ENOENT;
773 abo = gem_to_amdgpu_bo(gobj);
774 } else {
775 gobj = NULL;
776 abo = NULL;
777 }
778
779 drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
780 DRM_EXEC_IGNORE_DUPLICATES, 0);
781 drm_exec_until_all_locked(&exec) {
782 if (gobj) {
783 r = drm_exec_lock_obj(&exec, gobj);
784 drm_exec_retry_on_contention(&exec);
785 if (unlikely(r))
786 goto error;
787 }
788
789 r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 2);
790 drm_exec_retry_on_contention(&exec);
791 if (unlikely(r))
792 goto error;
793 }
794
795 if (abo) {
796 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
797 if (!bo_va) {
798 r = -ENOENT;
799 goto error;
800 }
801 } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
802 bo_va = fpriv->prt_va;
803 } else {
804 bo_va = NULL;
805 }
806
807 switch (args->operation) {
808 case AMDGPU_VA_OP_MAP:
809 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
810 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
811 args->offset_in_bo, args->map_size,
812 va_flags);
813 break;
814 case AMDGPU_VA_OP_UNMAP:
815 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
816 break;
817
818 case AMDGPU_VA_OP_CLEAR:
819 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
820 args->va_address,
821 args->map_size);
822 break;
823 case AMDGPU_VA_OP_REPLACE:
824 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
825 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
826 args->offset_in_bo, args->map_size,
827 va_flags);
828 break;
829 default:
830 break;
831 }
832 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !adev->debug_vm)
833 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
834 args->operation);
835
836 error:
837 drm_exec_fini(&exec);
838 drm_gem_object_put(gobj);
839 return r;
840 }
841
amdgpu_gem_op_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)842 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
843 struct drm_file *filp)
844 {
845 struct amdgpu_device *adev = drm_to_adev(dev);
846 struct drm_amdgpu_gem_op *args = data;
847 struct drm_gem_object *gobj;
848 struct amdgpu_vm_bo_base *base;
849 struct amdgpu_bo *robj;
850 int r;
851
852 gobj = drm_gem_object_lookup(filp, args->handle);
853 if (!gobj)
854 return -ENOENT;
855
856 robj = gem_to_amdgpu_bo(gobj);
857
858 r = amdgpu_bo_reserve(robj, false);
859 if (unlikely(r))
860 goto out;
861
862 switch (args->op) {
863 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
864 struct drm_amdgpu_gem_create_in info;
865 void __user *out = u64_to_user_ptr(args->value);
866
867 info.bo_size = robj->tbo.base.size;
868 info.alignment = robj->tbo.page_alignment << PAGE_SHIFT;
869 info.domains = robj->preferred_domains;
870 info.domain_flags = robj->flags;
871 amdgpu_bo_unreserve(robj);
872 if (copy_to_user(out, &info, sizeof(info)))
873 r = -EFAULT;
874 break;
875 }
876 case AMDGPU_GEM_OP_SET_PLACEMENT:
877 if (robj->tbo.base.import_attach &&
878 args->value & AMDGPU_GEM_DOMAIN_VRAM) {
879 r = -EINVAL;
880 amdgpu_bo_unreserve(robj);
881 break;
882 }
883 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
884 r = -EPERM;
885 amdgpu_bo_unreserve(robj);
886 break;
887 }
888 for (base = robj->vm_bo; base; base = base->next)
889 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev),
890 amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) {
891 r = -EINVAL;
892 amdgpu_bo_unreserve(robj);
893 goto out;
894 }
895
896
897 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
898 AMDGPU_GEM_DOMAIN_GTT |
899 AMDGPU_GEM_DOMAIN_CPU);
900 robj->allowed_domains = robj->preferred_domains;
901 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
902 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
903
904 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
905 amdgpu_vm_bo_invalidate(adev, robj, true);
906
907 amdgpu_bo_unreserve(robj);
908 break;
909 default:
910 amdgpu_bo_unreserve(robj);
911 r = -EINVAL;
912 }
913
914 out:
915 drm_gem_object_put(gobj);
916 return r;
917 }
918
amdgpu_gem_align_pitch(struct amdgpu_device * adev,int width,int cpp,bool tiled)919 static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
920 int width,
921 int cpp,
922 bool tiled)
923 {
924 int aligned = width;
925 int pitch_mask = 0;
926
927 switch (cpp) {
928 case 1:
929 pitch_mask = 255;
930 break;
931 case 2:
932 pitch_mask = 127;
933 break;
934 case 3:
935 case 4:
936 pitch_mask = 63;
937 break;
938 }
939
940 aligned += pitch_mask;
941 aligned &= ~pitch_mask;
942 return aligned * cpp;
943 }
944
amdgpu_mode_dumb_create(struct drm_file * file_priv,struct drm_device * dev,struct drm_mode_create_dumb * args)945 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
946 struct drm_device *dev,
947 struct drm_mode_create_dumb *args)
948 {
949 struct amdgpu_device *adev = drm_to_adev(dev);
950 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
951 struct drm_gem_object *gobj;
952 uint32_t handle;
953 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
954 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
955 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
956 u32 domain;
957 int r;
958
959 /*
960 * The buffer returned from this function should be cleared, but
961 * it can only be done if the ring is enabled or we'll fail to
962 * create the buffer.
963 */
964 if (adev->mman.buffer_funcs_enabled)
965 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
966
967 args->pitch = amdgpu_gem_align_pitch(adev, args->width,
968 DIV_ROUND_UP(args->bpp, 8), 0);
969 args->size = (u64)args->pitch * args->height;
970 args->size = ALIGN(args->size, PAGE_SIZE);
971 domain = amdgpu_bo_get_preferred_domain(adev,
972 amdgpu_display_supported_domains(adev, flags));
973 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
974 ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1);
975 if (r)
976 return -ENOMEM;
977
978 r = drm_gem_handle_create(file_priv, gobj, &handle);
979 /* drop reference from allocate - handle holds it now */
980 drm_gem_object_put(gobj);
981 if (r)
982 return r;
983
984 args->handle = handle;
985 return 0;
986 }
987
988 #if defined(CONFIG_DEBUG_FS)
amdgpu_debugfs_gem_info_show(struct seq_file * m,void * unused)989 static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused)
990 {
991 struct amdgpu_device *adev = m->private;
992 struct drm_device *dev = adev_to_drm(adev);
993 struct drm_file *file;
994 int r;
995
996 r = mutex_lock_interruptible(&dev->filelist_mutex);
997 if (r)
998 return r;
999
1000 list_for_each_entry(file, &dev->filelist, lhead) {
1001 struct task_struct *task;
1002 struct drm_gem_object *gobj;
1003 struct pid *pid;
1004 int id;
1005
1006 /*
1007 * Although we have a valid reference on file->pid, that does
1008 * not guarantee that the task_struct who called get_pid() is
1009 * still alive (e.g. get_pid(current) => fork() => exit()).
1010 * Therefore, we need to protect this ->comm access using RCU.
1011 */
1012 rcu_read_lock();
1013 pid = rcu_dereference(file->pid);
1014 task = pid_task(pid, PIDTYPE_TGID);
1015 seq_printf(m, "pid %8d command %s:\n", pid_nr(pid),
1016 task ? task->comm : "<unknown>");
1017 rcu_read_unlock();
1018
1019 spin_lock(&file->table_lock);
1020 idr_for_each_entry(&file->object_idr, gobj, id) {
1021 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
1022
1023 amdgpu_bo_print_info(id, bo, m);
1024 }
1025 spin_unlock(&file->table_lock);
1026 }
1027
1028 mutex_unlock(&dev->filelist_mutex);
1029 return 0;
1030 }
1031
1032 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info);
1033
1034 #endif
1035
amdgpu_debugfs_gem_init(struct amdgpu_device * adev)1036 void amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
1037 {
1038 #if defined(CONFIG_DEBUG_FS)
1039 struct drm_minor *minor = adev_to_drm(adev)->primary;
1040 struct dentry *root = minor->debugfs_root;
1041
1042 debugfs_create_file("amdgpu_gem_info", 0444, root, adev,
1043 &amdgpu_debugfs_gem_info_fops);
1044 #endif
1045 }
1046