1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26 #include <drm/drm_vblank.h>
27 #include <drm/drm_atomic_helper.h>
28
29 #include "dc.h"
30 #include "amdgpu.h"
31 #include "amdgpu_dm_psr.h"
32 #include "amdgpu_dm_replay.h"
33 #include "amdgpu_dm_crtc.h"
34 #include "amdgpu_dm_plane.h"
35 #include "amdgpu_dm_trace.h"
36 #include "amdgpu_dm_debugfs.h"
37
38 #define HPD_DETECTION_PERIOD_uS 2000000
39 #define HPD_DETECTION_TIME_uS 100000
40
amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc * acrtc)41 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
42 {
43 struct drm_crtc *crtc = &acrtc->base;
44 struct drm_device *dev = crtc->dev;
45 unsigned long flags;
46
47 drm_crtc_handle_vblank(crtc);
48
49 spin_lock_irqsave(&dev->event_lock, flags);
50
51 /* Send completion event for cursor-only commits */
52 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
53 drm_crtc_send_vblank_event(crtc, acrtc->event);
54 drm_crtc_vblank_put(crtc);
55 acrtc->event = NULL;
56 }
57
58 spin_unlock_irqrestore(&dev->event_lock, flags);
59 }
60
amdgpu_dm_crtc_modeset_required(struct drm_crtc_state * crtc_state,struct dc_stream_state * new_stream,struct dc_stream_state * old_stream)61 bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,
62 struct dc_stream_state *new_stream,
63 struct dc_stream_state *old_stream)
64 {
65 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
66 }
67
amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc * acrtc)68 bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc)
69
70 {
71 return acrtc->dm_irq_params.freesync_config.state ==
72 VRR_STATE_ACTIVE_VARIABLE ||
73 acrtc->dm_irq_params.freesync_config.state ==
74 VRR_STATE_ACTIVE_FIXED;
75 }
76
amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc * crtc,bool enable)77 int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
78 {
79 enum dc_irq_source irq_source;
80 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
81 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
82 int rc;
83
84 if (acrtc->otg_inst == -1)
85 return 0;
86
87 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
88
89 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
90
91 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
92 acrtc->crtc_id, enable ? "en" : "dis", rc);
93 return rc;
94 }
95
amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state * dm_state)96 bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state)
97 {
98 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
99 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
100 }
101
102 /**
103 * amdgpu_dm_crtc_set_panel_sr_feature() - Manage panel self-refresh features.
104 *
105 * @vblank_work: is a pointer to a struct vblank_control_work object.
106 * @vblank_enabled: indicates whether the DRM vblank counter is currently
107 * enabled (true) or disabled (false).
108 * @allow_sr_entry: represents whether entry into the self-refresh mode is
109 * allowed (true) or not allowed (false).
110 *
111 * The DRM vblank counter enable/disable action is used as the trigger to enable
112 * or disable various panel self-refresh features:
113 *
114 * Panel Replay and PSR SU
115 * - Enable when:
116 * - VRR is disabled
117 * - vblank counter is disabled
118 * - entry is allowed: usermode demonstrates an adequate number of fast
119 * commits)
120 * - CRC capture window isn't active
121 * - Keep enabled even when vblank counter gets enabled
122 *
123 * PSR1
124 * - Enable condition same as above
125 * - Disable when vblank counter is enabled
126 */
amdgpu_dm_crtc_set_panel_sr_feature(struct vblank_control_work * vblank_work,bool vblank_enabled,bool allow_sr_entry)127 static void amdgpu_dm_crtc_set_panel_sr_feature(
128 struct vblank_control_work *vblank_work,
129 bool vblank_enabled, bool allow_sr_entry)
130 {
131 struct dc_link *link = vblank_work->stream->link;
132 bool is_sr_active = (link->replay_settings.replay_allow_active ||
133 link->psr_settings.psr_allow_active);
134 bool is_crc_window_active = false;
135 bool vrr_active = amdgpu_dm_crtc_vrr_active_irq(vblank_work->acrtc);
136
137 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
138 is_crc_window_active =
139 amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base);
140 #endif
141
142 if (link->replay_settings.replay_feature_enabled && !vrr_active &&
143 allow_sr_entry && !is_sr_active && !is_crc_window_active) {
144 amdgpu_dm_replay_enable(vblank_work->stream, true);
145 } else if (vblank_enabled) {
146 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active)
147 amdgpu_dm_psr_disable(vblank_work->stream, false);
148 } else if (link->psr_settings.psr_feature_enabled && !vrr_active &&
149 allow_sr_entry && !is_sr_active && !is_crc_window_active) {
150
151 struct amdgpu_dm_connector *aconn =
152 (struct amdgpu_dm_connector *) vblank_work->stream->dm_stream_context;
153
154 if (!aconn->disallow_edp_enter_psr) {
155 struct amdgpu_display_manager *dm = vblank_work->dm;
156
157 amdgpu_dm_psr_enable(vblank_work->stream);
158 if (dm->idle_workqueue &&
159 (dm->dc->config.disable_ips == DMUB_IPS_ENABLE) &&
160 dm->dc->idle_optimizations_allowed &&
161 dm->idle_workqueue->enable &&
162 !dm->idle_workqueue->running)
163 schedule_work(&dm->idle_workqueue->work);
164 }
165 }
166 }
167
amdgpu_dm_is_headless(struct amdgpu_device * adev)168 bool amdgpu_dm_is_headless(struct amdgpu_device *adev)
169 {
170 struct drm_connector *connector;
171 struct drm_connector_list_iter iter;
172 struct drm_device *dev;
173 bool is_headless = true;
174
175 if (adev == NULL)
176 return true;
177
178 dev = adev->dm.ddev;
179
180 drm_connector_list_iter_begin(dev, &iter);
181 drm_for_each_connector_iter(connector, &iter) {
182
183 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
184 continue;
185
186 if (connector->status == connector_status_connected) {
187 is_headless = false;
188 break;
189 }
190 }
191 drm_connector_list_iter_end(&iter);
192 return is_headless;
193 }
194
amdgpu_dm_idle_worker(struct work_struct * work)195 static void amdgpu_dm_idle_worker(struct work_struct *work)
196 {
197 struct idle_workqueue *idle_work;
198
199 idle_work = container_of(work, struct idle_workqueue, work);
200 idle_work->dm->idle_workqueue->running = true;
201
202 while (idle_work->enable) {
203 fsleep(HPD_DETECTION_PERIOD_uS);
204 mutex_lock(&idle_work->dm->dc_lock);
205 if (!idle_work->dm->dc->idle_optimizations_allowed) {
206 mutex_unlock(&idle_work->dm->dc_lock);
207 break;
208 }
209 dc_allow_idle_optimizations(idle_work->dm->dc, false);
210
211 mutex_unlock(&idle_work->dm->dc_lock);
212 fsleep(HPD_DETECTION_TIME_uS);
213 mutex_lock(&idle_work->dm->dc_lock);
214
215 if (!amdgpu_dm_is_headless(idle_work->dm->adev) &&
216 !amdgpu_dm_psr_is_active_allowed(idle_work->dm)) {
217 mutex_unlock(&idle_work->dm->dc_lock);
218 break;
219 }
220
221 if (idle_work->enable)
222 dc_allow_idle_optimizations(idle_work->dm->dc, true);
223 mutex_unlock(&idle_work->dm->dc_lock);
224 }
225 idle_work->dm->idle_workqueue->running = false;
226 }
227
idle_create_workqueue(struct amdgpu_device * adev)228 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev)
229 {
230 struct idle_workqueue *idle_work;
231
232 idle_work = kzalloc(sizeof(*idle_work), GFP_KERNEL);
233 if (ZERO_OR_NULL_PTR(idle_work))
234 return NULL;
235
236 idle_work->dm = &adev->dm;
237 idle_work->enable = false;
238 idle_work->running = false;
239 INIT_WORK(&idle_work->work, amdgpu_dm_idle_worker);
240
241 return idle_work;
242 }
243
amdgpu_dm_crtc_vblank_control_worker(struct work_struct * work)244 static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
245 {
246 struct vblank_control_work *vblank_work =
247 container_of(work, struct vblank_control_work, work);
248 struct amdgpu_display_manager *dm = vblank_work->dm;
249
250 mutex_lock(&dm->dc_lock);
251
252 if (vblank_work->enable)
253 dm->active_vblank_irq_count++;
254 else if (dm->active_vblank_irq_count)
255 dm->active_vblank_irq_count--;
256
257 if (dm->active_vblank_irq_count > 0)
258 dc_allow_idle_optimizations(dm->dc, false);
259
260 /*
261 * Control PSR based on vblank requirements from OS
262 *
263 * If panel supports PSR SU, there's no need to disable PSR when OS is
264 * submitting fast atomic commits (we infer this by whether the OS
265 * requests vblank events). Fast atomic commits will simply trigger a
266 * full-frame-update (FFU); a specific case of selective-update (SU)
267 * where the SU region is the full hactive*vactive region. See
268 * fill_dc_dirty_rects().
269 */
270 if (vblank_work->stream && vblank_work->stream->link && vblank_work->acrtc) {
271 amdgpu_dm_crtc_set_panel_sr_feature(
272 vblank_work, vblank_work->enable,
273 vblank_work->acrtc->dm_irq_params.allow_sr_entry);
274 }
275
276 if (dm->active_vblank_irq_count == 0)
277 dc_allow_idle_optimizations(dm->dc, true);
278
279 mutex_unlock(&dm->dc_lock);
280
281 dc_stream_release(vblank_work->stream);
282
283 kfree(vblank_work);
284 }
285
amdgpu_dm_crtc_set_vblank(struct drm_crtc * crtc,bool enable)286 static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
287 {
288 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
289 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
290 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
291 struct amdgpu_display_manager *dm = &adev->dm;
292 struct vblank_control_work *work;
293 int irq_type;
294 int rc = 0;
295
296 if (acrtc->otg_inst == -1)
297 goto skip;
298
299 irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
300
301 if (enable) {
302 struct dc *dc = adev->dm.dc;
303 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
304 struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
305 struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;
306 bool sr_supported = (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED) ||
307 pr->config.replay_supported;
308
309 /*
310 * IPS & self-refresh feature can cause vblank counter resets between
311 * vblank disable and enable.
312 * It may cause system stuck due to waiting for the vblank counter.
313 * Call this function to estimate missed vblanks by using timestamps and
314 * update the vblank counter in DRM.
315 */
316 if (dc->caps.ips_support &&
317 dc->config.disable_ips != DMUB_IPS_DISABLE_ALL &&
318 sr_supported && vblank->config.disable_immediate)
319 drm_crtc_vblank_restore(crtc);
320
321 /* vblank irq on -> Only need vupdate irq in vrr mode */
322 if (amdgpu_dm_crtc_vrr_active(acrtc_state))
323 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);
324 } else {
325 /* vblank irq off -> vupdate irq off */
326 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false);
327 }
328
329 if (rc)
330 return rc;
331
332 /* crtc vblank or vstartup interrupt */
333 if (enable) {
334 rc = amdgpu_irq_get(adev, &adev->crtc_irq, irq_type);
335 drm_dbg_vbl(crtc->dev, "Get crtc_irq ret=%d\n", rc);
336 } else {
337 rc = amdgpu_irq_put(adev, &adev->crtc_irq, irq_type);
338 drm_dbg_vbl(crtc->dev, "Put crtc_irq ret=%d\n", rc);
339 }
340
341 if (rc)
342 return rc;
343
344 /*
345 * hubp surface flip interrupt
346 *
347 * We have no guarantee that the frontend index maps to the same
348 * backend index - some even map to more than one.
349 *
350 * TODO: Use a different interrupt or check DC itself for the mapping.
351 */
352 if (enable) {
353 rc = amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type);
354 drm_dbg_vbl(crtc->dev, "Get pageflip_irq ret=%d\n", rc);
355 } else {
356 rc = amdgpu_irq_put(adev, &adev->pageflip_irq, irq_type);
357 drm_dbg_vbl(crtc->dev, "Put pageflip_irq ret=%d\n", rc);
358 }
359
360 if (rc)
361 return rc;
362
363 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
364 /* crtc vline0 interrupt, only available on DCN+ */
365 if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) {
366 if (enable) {
367 rc = amdgpu_irq_get(adev, &adev->vline0_irq, irq_type);
368 drm_dbg_vbl(crtc->dev, "Get vline0_irq ret=%d\n", rc);
369 } else {
370 rc = amdgpu_irq_put(adev, &adev->vline0_irq, irq_type);
371 drm_dbg_vbl(crtc->dev, "Put vline0_irq ret=%d\n", rc);
372 }
373
374 if (rc)
375 return rc;
376 }
377 #endif
378 skip:
379 if (amdgpu_in_reset(adev))
380 return 0;
381
382 if (dm->vblank_control_workqueue) {
383 work = kzalloc(sizeof(*work), GFP_ATOMIC);
384 if (!work)
385 return -ENOMEM;
386
387 INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker);
388 work->dm = dm;
389 work->acrtc = acrtc;
390 work->enable = enable;
391
392 if (acrtc_state->stream) {
393 dc_stream_retain(acrtc_state->stream);
394 work->stream = acrtc_state->stream;
395 }
396
397 queue_work(dm->vblank_control_workqueue, &work->work);
398 }
399
400 return 0;
401 }
402
amdgpu_dm_crtc_enable_vblank(struct drm_crtc * crtc)403 int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc)
404 {
405 return amdgpu_dm_crtc_set_vblank(crtc, true);
406 }
407
amdgpu_dm_crtc_disable_vblank(struct drm_crtc * crtc)408 void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc)
409 {
410 amdgpu_dm_crtc_set_vblank(crtc, false);
411 }
412
amdgpu_dm_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)413 static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc,
414 struct drm_crtc_state *state)
415 {
416 struct dm_crtc_state *cur = to_dm_crtc_state(state);
417
418 /* TODO Destroy dc_stream objects are stream object is flattened */
419 if (cur->stream)
420 dc_stream_release(cur->stream);
421
422
423 __drm_atomic_helper_crtc_destroy_state(state);
424
425
426 kfree(state);
427 }
428
amdgpu_dm_crtc_duplicate_state(struct drm_crtc * crtc)429 static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc)
430 {
431 struct dm_crtc_state *state, *cur;
432
433 cur = to_dm_crtc_state(crtc->state);
434
435 if (WARN_ON(!crtc->state))
436 return NULL;
437
438 state = kzalloc(sizeof(*state), GFP_KERNEL);
439 if (!state)
440 return NULL;
441
442 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
443
444 if (cur->stream) {
445 state->stream = cur->stream;
446 dc_stream_retain(state->stream);
447 }
448
449 state->active_planes = cur->active_planes;
450 state->vrr_infopacket = cur->vrr_infopacket;
451 state->abm_level = cur->abm_level;
452 state->vrr_supported = cur->vrr_supported;
453 state->freesync_config = cur->freesync_config;
454 state->cm_has_degamma = cur->cm_has_degamma;
455 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
456 state->regamma_tf = cur->regamma_tf;
457 state->crc_skip_count = cur->crc_skip_count;
458 state->mpo_requested = cur->mpo_requested;
459 state->cursor_mode = cur->cursor_mode;
460 /* TODO Duplicate dc_stream after objects are stream object is flattened */
461
462 return &state->base;
463 }
464
amdgpu_dm_crtc_destroy(struct drm_crtc * crtc)465 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
466 {
467 drm_crtc_cleanup(crtc);
468 kfree(crtc);
469 }
470
amdgpu_dm_crtc_reset_state(struct drm_crtc * crtc)471 static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc)
472 {
473 struct dm_crtc_state *state;
474
475 if (crtc->state)
476 amdgpu_dm_crtc_destroy_state(crtc, crtc->state);
477
478 state = kzalloc(sizeof(*state), GFP_KERNEL);
479 if (WARN_ON(!state))
480 return;
481
482 __drm_atomic_helper_crtc_reset(crtc, &state->base);
483 }
484
485 #ifdef CONFIG_DEBUG_FS
amdgpu_dm_crtc_late_register(struct drm_crtc * crtc)486 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
487 {
488 crtc_debugfs_init(crtc);
489
490 return 0;
491 }
492 #endif
493
494 #ifdef AMD_PRIVATE_COLOR
495 /**
496 * dm_crtc_additional_color_mgmt - enable additional color properties
497 * @crtc: DRM CRTC
498 *
499 * This function lets the driver enable post-blending CRTC regamma transfer
500 * function property in addition to DRM CRTC gamma LUT. Default value means
501 * linear transfer function, which is the default CRTC gamma LUT behaviour
502 * without this property.
503 */
504 static void
dm_crtc_additional_color_mgmt(struct drm_crtc * crtc)505 dm_crtc_additional_color_mgmt(struct drm_crtc *crtc)
506 {
507 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
508
509 if (adev->dm.dc->caps.color.mpc.ogam_ram)
510 drm_object_attach_property(&crtc->base,
511 adev->mode_info.regamma_tf_property,
512 AMDGPU_TRANSFER_FUNCTION_DEFAULT);
513 }
514
515 static int
amdgpu_dm_atomic_crtc_set_property(struct drm_crtc * crtc,struct drm_crtc_state * state,struct drm_property * property,uint64_t val)516 amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc,
517 struct drm_crtc_state *state,
518 struct drm_property *property,
519 uint64_t val)
520 {
521 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
522 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
523
524 if (property == adev->mode_info.regamma_tf_property) {
525 if (acrtc_state->regamma_tf != val) {
526 acrtc_state->regamma_tf = val;
527 acrtc_state->base.color_mgmt_changed |= 1;
528 }
529 } else {
530 drm_dbg_atomic(crtc->dev,
531 "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n",
532 crtc->base.id, crtc->name,
533 property->base.id, property->name);
534 return -EINVAL;
535 }
536
537 return 0;
538 }
539
540 static int
amdgpu_dm_atomic_crtc_get_property(struct drm_crtc * crtc,const struct drm_crtc_state * state,struct drm_property * property,uint64_t * val)541 amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc,
542 const struct drm_crtc_state *state,
543 struct drm_property *property,
544 uint64_t *val)
545 {
546 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
547 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
548
549 if (property == adev->mode_info.regamma_tf_property)
550 *val = acrtc_state->regamma_tf;
551 else
552 return -EINVAL;
553
554 return 0;
555 }
556 #endif
557
558 /* Implemented only the options currently available for the driver */
559 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
560 .reset = amdgpu_dm_crtc_reset_state,
561 .destroy = amdgpu_dm_crtc_destroy,
562 .set_config = drm_atomic_helper_set_config,
563 .page_flip = drm_atomic_helper_page_flip,
564 .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state,
565 .atomic_destroy_state = amdgpu_dm_crtc_destroy_state,
566 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
567 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
568 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
569 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
570 .enable_vblank = amdgpu_dm_crtc_enable_vblank,
571 .disable_vblank = amdgpu_dm_crtc_disable_vblank,
572 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
573 #if defined(CONFIG_DEBUG_FS)
574 .late_register = amdgpu_dm_crtc_late_register,
575 #endif
576 #ifdef AMD_PRIVATE_COLOR
577 .atomic_set_property = amdgpu_dm_atomic_crtc_set_property,
578 .atomic_get_property = amdgpu_dm_atomic_crtc_get_property,
579 #endif
580 };
581
amdgpu_dm_crtc_helper_disable(struct drm_crtc * crtc)582 static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc)
583 {
584 }
585
amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state * new_crtc_state)586 static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
587 {
588 struct drm_atomic_state *state = new_crtc_state->state;
589 struct drm_plane *plane;
590 int num_active = 0;
591
592 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
593 struct drm_plane_state *new_plane_state;
594
595 /* Cursor planes are "fake". */
596 if (plane->type == DRM_PLANE_TYPE_CURSOR)
597 continue;
598
599 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
600
601 if (!new_plane_state) {
602 /*
603 * The plane is enable on the CRTC and hasn't changed
604 * state. This means that it previously passed
605 * validation and is therefore enabled.
606 */
607 num_active += 1;
608 continue;
609 }
610
611 /* We need a framebuffer to be considered enabled. */
612 num_active += (new_plane_state->fb != NULL);
613 }
614
615 return num_active;
616 }
617
amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc * crtc,struct drm_crtc_state * new_crtc_state)618 static void amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc *crtc,
619 struct drm_crtc_state *new_crtc_state)
620 {
621 struct dm_crtc_state *dm_new_crtc_state =
622 to_dm_crtc_state(new_crtc_state);
623
624 dm_new_crtc_state->active_planes = 0;
625
626 if (!dm_new_crtc_state->stream)
627 return;
628
629 dm_new_crtc_state->active_planes =
630 amdgpu_dm_crtc_count_crtc_active_planes(new_crtc_state);
631 }
632
amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)633 static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
634 const struct drm_display_mode *mode,
635 struct drm_display_mode *adjusted_mode)
636 {
637 return true;
638 }
639
amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)640 static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
641 struct drm_atomic_state *state)
642 {
643 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
644 crtc);
645 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
646 struct dc *dc = adev->dm.dc;
647 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
648 int ret = -EINVAL;
649
650 trace_amdgpu_dm_crtc_atomic_check(crtc_state);
651
652 amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state);
653
654 if (WARN_ON(unlikely(!dm_crtc_state->stream &&
655 amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) {
656 return ret;
657 }
658
659 /*
660 * We require the primary plane to be enabled whenever the CRTC is, otherwise
661 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
662 * planes are disabled, which is not supported by the hardware. And there is legacy
663 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
664 */
665 if (crtc_state->enable &&
666 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
667 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
668 return -EINVAL;
669 }
670
671 /*
672 * Only allow async flips for fast updates that don't change the FB
673 * pitch, the DCC state, rotation, etc.
674 */
675 if (crtc_state->async_flip &&
676 dm_crtc_state->update_type != UPDATE_TYPE_FAST) {
677 drm_dbg_atomic(crtc->dev,
678 "[CRTC:%d:%s] async flips are only supported for fast updates\n",
679 crtc->base.id, crtc->name);
680 return -EINVAL;
681 }
682
683 if (!state->legacy_cursor_update && amdgpu_dm_crtc_vrr_active(dm_crtc_state)) {
684 struct drm_plane_state *primary_state;
685
686 /* Pull in primary plane for correct VRR handling */
687 primary_state = drm_atomic_get_plane_state(state, crtc->primary);
688 if (IS_ERR(primary_state))
689 return PTR_ERR(primary_state);
690 }
691
692 /* In some use cases, like reset, no stream is attached */
693 if (!dm_crtc_state->stream)
694 return 0;
695
696 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
697 return 0;
698
699 DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
700 return ret;
701 }
702
703 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
704 .disable = amdgpu_dm_crtc_helper_disable,
705 .atomic_check = amdgpu_dm_crtc_helper_atomic_check,
706 .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup,
707 .get_scanout_position = amdgpu_crtc_get_scanout_position,
708 };
709
amdgpu_dm_crtc_init(struct amdgpu_display_manager * dm,struct drm_plane * plane,uint32_t crtc_index)710 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
711 struct drm_plane *plane,
712 uint32_t crtc_index)
713 {
714 struct amdgpu_crtc *acrtc = NULL;
715 struct drm_plane *cursor_plane;
716 bool is_dcn;
717 int res = -ENOMEM;
718
719 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
720 if (!cursor_plane)
721 goto fail;
722
723 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
724 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
725
726 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
727 if (!acrtc)
728 goto fail;
729
730 res = drm_crtc_init_with_planes(
731 dm->ddev,
732 &acrtc->base,
733 plane,
734 cursor_plane,
735 &amdgpu_dm_crtc_funcs, NULL);
736
737 if (res)
738 goto fail;
739
740 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
741
742 /* Create (reset) the plane state */
743 if (acrtc->base.funcs->reset)
744 acrtc->base.funcs->reset(&acrtc->base);
745
746 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
747 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
748
749 acrtc->crtc_id = crtc_index;
750 acrtc->base.enabled = false;
751 acrtc->otg_inst = -1;
752
753 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
754
755 /* Don't enable DRM CRTC degamma property for DCE since it doesn't
756 * support programmable degamma anywhere.
757 */
758 is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch;
759 /* Dont't enable DRM CRTC degamma property for DCN401 since the
760 * pre-blending degamma LUT doesn't apply to cursor, and therefore
761 * can't work similar to a post-blending degamma LUT as in other hw
762 * versions.
763 * TODO: revisit it once KMS plane color API is merged.
764 */
765 drm_crtc_enable_color_mgmt(&acrtc->base,
766 (is_dcn &&
767 dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01) ?
768 MAX_COLOR_LUT_ENTRIES : 0,
769 true, MAX_COLOR_LUT_ENTRIES);
770
771 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
772
773 #ifdef AMD_PRIVATE_COLOR
774 dm_crtc_additional_color_mgmt(&acrtc->base);
775 #endif
776 return 0;
777
778 fail:
779 kfree(acrtc);
780 kfree(cursor_plane);
781 return res;
782 }
783
784