1 /*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 /*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32 #include <linux/list.h>
33 #include <linux/slab.h>
34 #include <linux/dma-buf.h>
35
36 #include <drm/drm_drv.h>
37 #include <drm/amdgpu_drm.h>
38 #include <drm/drm_cache.h>
39 #include "amdgpu.h"
40 #include "amdgpu_trace.h"
41 #include "amdgpu_amdkfd.h"
42 #include "amdgpu_vram_mgr.h"
43
44 /**
45 * DOC: amdgpu_object
46 *
47 * This defines the interfaces to operate on an &amdgpu_bo buffer object which
48 * represents memory used by driver (VRAM, system memory, etc.). The driver
49 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces
50 * to create/destroy/set buffer object which are then managed by the kernel TTM
51 * memory manager.
52 * The interfaces are also used internally by kernel clients, including gfx,
53 * uvd, etc. for kernel managed allocations used by the GPU.
54 *
55 */
56
amdgpu_bo_destroy(struct ttm_buffer_object * tbo)57 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
58 {
59 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
60
61 amdgpu_bo_kunmap(bo);
62
63 if (bo->tbo.base.import_attach)
64 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
65 drm_gem_object_release(&bo->tbo.base);
66 amdgpu_bo_unref(&bo->parent);
67 kvfree(bo);
68 }
69
amdgpu_bo_user_destroy(struct ttm_buffer_object * tbo)70 static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo)
71 {
72 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
73 struct amdgpu_bo_user *ubo;
74
75 ubo = to_amdgpu_bo_user(bo);
76 kfree(ubo->metadata);
77 amdgpu_bo_destroy(tbo);
78 }
79
amdgpu_bo_vm_destroy(struct ttm_buffer_object * tbo)80 static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo)
81 {
82 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
83 struct amdgpu_bo *shadow_bo = ttm_to_amdgpu_bo(tbo), *bo;
84 struct amdgpu_bo_vm *vmbo;
85
86 bo = shadow_bo->parent;
87 vmbo = to_amdgpu_bo_vm(bo);
88 /* in case amdgpu_device_recover_vram got NULL of bo->parent */
89 if (!list_empty(&vmbo->shadow_list)) {
90 mutex_lock(&adev->shadow_list_lock);
91 list_del_init(&vmbo->shadow_list);
92 mutex_unlock(&adev->shadow_list_lock);
93 }
94
95 amdgpu_bo_destroy(tbo);
96 }
97
98 /**
99 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo
100 * @bo: buffer object to be checked
101 *
102 * Uses destroy function associated with the object to determine if this is
103 * an &amdgpu_bo.
104 *
105 * Returns:
106 * true if the object belongs to &amdgpu_bo, false if not.
107 */
amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object * bo)108 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
109 {
110 if (bo->destroy == &amdgpu_bo_destroy ||
111 bo->destroy == &amdgpu_bo_user_destroy ||
112 bo->destroy == &amdgpu_bo_vm_destroy)
113 return true;
114
115 return false;
116 }
117
118 /**
119 * amdgpu_bo_placement_from_domain - set buffer's placement
120 * @abo: &amdgpu_bo buffer object whose placement is to be set
121 * @domain: requested domain
122 *
123 * Sets buffer's placement according to requested domain and the buffer's
124 * flags.
125 */
amdgpu_bo_placement_from_domain(struct amdgpu_bo * abo,u32 domain)126 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
127 {
128 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
129 struct ttm_placement *placement = &abo->placement;
130 struct ttm_place *places = abo->placements;
131 u64 flags = abo->flags;
132 u32 c = 0;
133
134 if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
135 unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
136 int8_t mem_id = KFD_XCP_MEM_ID(adev, abo->xcp_id);
137
138 if (adev->gmc.mem_partitions && mem_id >= 0) {
139 places[c].fpfn = adev->gmc.mem_partitions[mem_id].range.fpfn;
140 /*
141 * memory partition range lpfn is inclusive start + size - 1
142 * TTM place lpfn is exclusive start + size
143 */
144 places[c].lpfn = adev->gmc.mem_partitions[mem_id].range.lpfn + 1;
145 } else {
146 places[c].fpfn = 0;
147 places[c].lpfn = 0;
148 }
149 places[c].mem_type = TTM_PL_VRAM;
150 places[c].flags = 0;
151
152 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
153 places[c].lpfn = min_not_zero(places[c].lpfn, visible_pfn);
154 else
155 places[c].flags |= TTM_PL_FLAG_TOPDOWN;
156
157 if (abo->tbo.type == ttm_bo_type_kernel &&
158 flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
159 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
160
161 c++;
162 }
163
164 if (domain & AMDGPU_GEM_DOMAIN_DOORBELL) {
165 places[c].fpfn = 0;
166 places[c].lpfn = 0;
167 places[c].mem_type = AMDGPU_PL_DOORBELL;
168 places[c].flags = 0;
169 c++;
170 }
171
172 if (domain & AMDGPU_GEM_DOMAIN_GTT) {
173 places[c].fpfn = 0;
174 places[c].lpfn = 0;
175 places[c].mem_type =
176 abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ?
177 AMDGPU_PL_PREEMPT : TTM_PL_TT;
178 places[c].flags = 0;
179 /*
180 * When GTT is just an alternative to VRAM make sure that we
181 * only use it as fallback and still try to fill up VRAM first.
182 */
183 if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM)
184 places[c].flags |= TTM_PL_FLAG_FALLBACK;
185 c++;
186 }
187
188 if (domain & AMDGPU_GEM_DOMAIN_CPU) {
189 places[c].fpfn = 0;
190 places[c].lpfn = 0;
191 places[c].mem_type = TTM_PL_SYSTEM;
192 places[c].flags = 0;
193 c++;
194 }
195
196 if (domain & AMDGPU_GEM_DOMAIN_GDS) {
197 places[c].fpfn = 0;
198 places[c].lpfn = 0;
199 places[c].mem_type = AMDGPU_PL_GDS;
200 places[c].flags = 0;
201 c++;
202 }
203
204 if (domain & AMDGPU_GEM_DOMAIN_GWS) {
205 places[c].fpfn = 0;
206 places[c].lpfn = 0;
207 places[c].mem_type = AMDGPU_PL_GWS;
208 places[c].flags = 0;
209 c++;
210 }
211
212 if (domain & AMDGPU_GEM_DOMAIN_OA) {
213 places[c].fpfn = 0;
214 places[c].lpfn = 0;
215 places[c].mem_type = AMDGPU_PL_OA;
216 places[c].flags = 0;
217 c++;
218 }
219
220 if (!c) {
221 places[c].fpfn = 0;
222 places[c].lpfn = 0;
223 places[c].mem_type = TTM_PL_SYSTEM;
224 places[c].flags = 0;
225 c++;
226 }
227
228 BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS);
229
230 placement->num_placement = c;
231 placement->placement = places;
232 }
233
234 /**
235 * amdgpu_bo_create_reserved - create reserved BO for kernel use
236 *
237 * @adev: amdgpu device object
238 * @size: size for the new BO
239 * @align: alignment for the new BO
240 * @domain: where to place it
241 * @bo_ptr: used to initialize BOs in structures
242 * @gpu_addr: GPU addr of the pinned BO
243 * @cpu_addr: optional CPU address mapping
244 *
245 * Allocates and pins a BO for kernel internal use, and returns it still
246 * reserved.
247 *
248 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
249 *
250 * Returns:
251 * 0 on success, negative error code otherwise.
252 */
amdgpu_bo_create_reserved(struct amdgpu_device * adev,unsigned long size,int align,u32 domain,struct amdgpu_bo ** bo_ptr,u64 * gpu_addr,void ** cpu_addr)253 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
254 unsigned long size, int align,
255 u32 domain, struct amdgpu_bo **bo_ptr,
256 u64 *gpu_addr, void **cpu_addr)
257 {
258 struct amdgpu_bo_param bp;
259 bool free = false;
260 int r;
261
262 if (!size) {
263 amdgpu_bo_unref(bo_ptr);
264 return 0;
265 }
266
267 memset(&bp, 0, sizeof(bp));
268 bp.size = size;
269 bp.byte_align = align;
270 bp.domain = domain;
271 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
272 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
273 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
274 bp.type = ttm_bo_type_kernel;
275 bp.resv = NULL;
276 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
277
278 if (!*bo_ptr) {
279 r = amdgpu_bo_create(adev, &bp, bo_ptr);
280 if (r) {
281 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
282 r);
283 return r;
284 }
285 free = true;
286 }
287
288 r = amdgpu_bo_reserve(*bo_ptr, false);
289 if (r) {
290 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
291 goto error_free;
292 }
293
294 r = amdgpu_bo_pin(*bo_ptr, domain);
295 if (r) {
296 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
297 goto error_unreserve;
298 }
299
300 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo);
301 if (r) {
302 dev_err(adev->dev, "%p bind failed\n", *bo_ptr);
303 goto error_unpin;
304 }
305
306 if (gpu_addr)
307 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr);
308
309 if (cpu_addr) {
310 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
311 if (r) {
312 dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
313 goto error_unpin;
314 }
315 }
316
317 return 0;
318
319 error_unpin:
320 amdgpu_bo_unpin(*bo_ptr);
321 error_unreserve:
322 amdgpu_bo_unreserve(*bo_ptr);
323
324 error_free:
325 if (free)
326 amdgpu_bo_unref(bo_ptr);
327
328 return r;
329 }
330
331 /**
332 * amdgpu_bo_create_kernel - create BO for kernel use
333 *
334 * @adev: amdgpu device object
335 * @size: size for the new BO
336 * @align: alignment for the new BO
337 * @domain: where to place it
338 * @bo_ptr: used to initialize BOs in structures
339 * @gpu_addr: GPU addr of the pinned BO
340 * @cpu_addr: optional CPU address mapping
341 *
342 * Allocates and pins a BO for kernel internal use.
343 *
344 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
345 *
346 * Returns:
347 * 0 on success, negative error code otherwise.
348 */
amdgpu_bo_create_kernel(struct amdgpu_device * adev,unsigned long size,int align,u32 domain,struct amdgpu_bo ** bo_ptr,u64 * gpu_addr,void ** cpu_addr)349 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
350 unsigned long size, int align,
351 u32 domain, struct amdgpu_bo **bo_ptr,
352 u64 *gpu_addr, void **cpu_addr)
353 {
354 int r;
355
356 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
357 gpu_addr, cpu_addr);
358
359 if (r)
360 return r;
361
362 if (*bo_ptr)
363 amdgpu_bo_unreserve(*bo_ptr);
364
365 return 0;
366 }
367
368 /**
369 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location
370 *
371 * @adev: amdgpu device object
372 * @offset: offset of the BO
373 * @size: size of the BO
374 * @bo_ptr: used to initialize BOs in structures
375 * @cpu_addr: optional CPU address mapping
376 *
377 * Creates a kernel BO at a specific offset in VRAM.
378 *
379 * Returns:
380 * 0 on success, negative error code otherwise.
381 */
amdgpu_bo_create_kernel_at(struct amdgpu_device * adev,uint64_t offset,uint64_t size,struct amdgpu_bo ** bo_ptr,void ** cpu_addr)382 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
383 uint64_t offset, uint64_t size,
384 struct amdgpu_bo **bo_ptr, void **cpu_addr)
385 {
386 struct ttm_operation_ctx ctx = { false, false };
387 unsigned int i;
388 int r;
389
390 offset &= PAGE_MASK;
391 size = ALIGN(size, PAGE_SIZE);
392
393 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE,
394 AMDGPU_GEM_DOMAIN_VRAM, bo_ptr, NULL,
395 cpu_addr);
396 if (r)
397 return r;
398
399 if ((*bo_ptr) == NULL)
400 return 0;
401
402 /*
403 * Remove the original mem node and create a new one at the request
404 * position.
405 */
406 if (cpu_addr)
407 amdgpu_bo_kunmap(*bo_ptr);
408
409 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource);
410
411 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
412 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT;
413 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
414 }
415 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
416 &(*bo_ptr)->tbo.resource, &ctx);
417 if (r)
418 goto error;
419
420 if (cpu_addr) {
421 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
422 if (r)
423 goto error;
424 }
425
426 amdgpu_bo_unreserve(*bo_ptr);
427 return 0;
428
429 error:
430 amdgpu_bo_unreserve(*bo_ptr);
431 amdgpu_bo_unref(bo_ptr);
432 return r;
433 }
434
435 /**
436 * amdgpu_bo_free_kernel - free BO for kernel use
437 *
438 * @bo: amdgpu BO to free
439 * @gpu_addr: pointer to where the BO's GPU memory space address was stored
440 * @cpu_addr: pointer to where the BO's CPU memory space address was stored
441 *
442 * unmaps and unpin a BO for kernel internal use.
443 */
amdgpu_bo_free_kernel(struct amdgpu_bo ** bo,u64 * gpu_addr,void ** cpu_addr)444 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
445 void **cpu_addr)
446 {
447 if (*bo == NULL)
448 return;
449
450 WARN_ON(amdgpu_ttm_adev((*bo)->tbo.bdev)->in_suspend);
451
452 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
453 if (cpu_addr)
454 amdgpu_bo_kunmap(*bo);
455
456 amdgpu_bo_unpin(*bo);
457 amdgpu_bo_unreserve(*bo);
458 }
459 amdgpu_bo_unref(bo);
460
461 if (gpu_addr)
462 *gpu_addr = 0;
463
464 if (cpu_addr)
465 *cpu_addr = NULL;
466 }
467
468 /* Validate bo size is bit bigger than the request domain */
amdgpu_bo_validate_size(struct amdgpu_device * adev,unsigned long size,u32 domain)469 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
470 unsigned long size, u32 domain)
471 {
472 struct ttm_resource_manager *man = NULL;
473
474 /*
475 * If GTT is part of requested domains the check must succeed to
476 * allow fall back to GTT.
477 */
478 if (domain & AMDGPU_GEM_DOMAIN_GTT)
479 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
480 else if (domain & AMDGPU_GEM_DOMAIN_VRAM)
481 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
482 else
483 return true;
484
485 if (!man) {
486 if (domain & AMDGPU_GEM_DOMAIN_GTT)
487 WARN_ON_ONCE("GTT domain requested but GTT mem manager uninitialized");
488 return false;
489 }
490
491 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU, _DOMAIN_DOORBELL */
492 if (size < man->size)
493 return true;
494
495 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, man->size);
496 return false;
497 }
498
amdgpu_bo_support_uswc(u64 bo_flags)499 bool amdgpu_bo_support_uswc(u64 bo_flags)
500 {
501
502 #ifdef CONFIG_X86_32
503 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
504 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
505 */
506 return false;
507 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
508 /* Don't try to enable write-combining when it can't work, or things
509 * may be slow
510 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
511 */
512
513 #ifndef CONFIG_COMPILE_TEST
514 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
515 thanks to write-combining
516 #endif
517
518 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
519 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
520 "better performance thanks to write-combining\n");
521 return false;
522 #else
523 /* For architectures that don't support WC memory,
524 * mask out the WC flag from the BO
525 */
526 if (!drm_arch_can_wc_memory())
527 return false;
528
529 return true;
530 #endif
531 }
532
533 /**
534 * amdgpu_bo_create - create an &amdgpu_bo buffer object
535 * @adev: amdgpu device object
536 * @bp: parameters to be used for the buffer object
537 * @bo_ptr: pointer to the buffer object pointer
538 *
539 * Creates an &amdgpu_bo buffer object.
540 *
541 * Returns:
542 * 0 for success or a negative error code on failure.
543 */
amdgpu_bo_create(struct amdgpu_device * adev,struct amdgpu_bo_param * bp,struct amdgpu_bo ** bo_ptr)544 int amdgpu_bo_create(struct amdgpu_device *adev,
545 struct amdgpu_bo_param *bp,
546 struct amdgpu_bo **bo_ptr)
547 {
548 struct ttm_operation_ctx ctx = {
549 .interruptible = (bp->type != ttm_bo_type_kernel),
550 .no_wait_gpu = bp->no_wait_gpu,
551 /* We opt to avoid OOM on system pages allocations */
552 .gfp_retry_mayfail = true,
553 .allow_res_evict = bp->type != ttm_bo_type_kernel,
554 .resv = bp->resv
555 };
556 struct amdgpu_bo *bo;
557 unsigned long page_align, size = bp->size;
558 int r;
559
560 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */
561 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
562 /* GWS and OA don't need any alignment. */
563 page_align = bp->byte_align;
564 size <<= PAGE_SHIFT;
565
566 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
567 /* Both size and alignment must be a multiple of 4. */
568 page_align = ALIGN(bp->byte_align, 4);
569 size = ALIGN(size, 4) << PAGE_SHIFT;
570 } else {
571 /* Memory should be aligned at least to a page size. */
572 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
573 size = ALIGN(size, PAGE_SIZE);
574 }
575
576 if (!amdgpu_bo_validate_size(adev, size, bp->domain))
577 return -ENOMEM;
578
579 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo));
580
581 *bo_ptr = NULL;
582 bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL);
583 if (bo == NULL)
584 return -ENOMEM;
585 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);
586 bo->vm_bo = NULL;
587 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
588 bp->domain;
589 bo->allowed_domains = bo->preferred_domains;
590 if (bp->type != ttm_bo_type_kernel &&
591 !(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE) &&
592 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
593 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
594
595 bo->flags = bp->flags;
596
597 if (adev->gmc.mem_partitions)
598 /* For GPUs with spatial partitioning, bo->xcp_id=-1 means any partition */
599 bo->xcp_id = bp->xcp_id_plus1 - 1;
600 else
601 /* For GPUs without spatial partitioning */
602 bo->xcp_id = 0;
603
604 if (!amdgpu_bo_support_uswc(bo->flags))
605 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
606
607 bo->tbo.bdev = &adev->mman.bdev;
608 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
609 AMDGPU_GEM_DOMAIN_GDS))
610 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
611 else
612 amdgpu_bo_placement_from_domain(bo, bp->domain);
613 if (bp->type == ttm_bo_type_kernel)
614 bo->tbo.priority = 2;
615 else if (!(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE))
616 bo->tbo.priority = 1;
617
618 if (!bp->destroy)
619 bp->destroy = &amdgpu_bo_destroy;
620
621 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, bp->type,
622 &bo->placement, page_align, &ctx, NULL,
623 bp->resv, bp->destroy);
624 if (unlikely(r != 0))
625 return r;
626
627 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
628 amdgpu_res_cpu_visible(adev, bo->tbo.resource))
629 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
630 ctx.bytes_moved);
631 else
632 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
633
634 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
635 bo->tbo.resource->mem_type == TTM_PL_VRAM) {
636 struct dma_fence *fence;
637
638 r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence);
639 if (unlikely(r))
640 goto fail_unreserve;
641
642 dma_resv_add_fence(bo->tbo.base.resv, fence,
643 DMA_RESV_USAGE_KERNEL);
644 dma_fence_put(fence);
645 }
646 if (!bp->resv)
647 amdgpu_bo_unreserve(bo);
648 *bo_ptr = bo;
649
650 trace_amdgpu_bo_create(bo);
651
652 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
653 if (bp->type == ttm_bo_type_device)
654 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
655
656 return 0;
657
658 fail_unreserve:
659 if (!bp->resv)
660 dma_resv_unlock(bo->tbo.base.resv);
661 amdgpu_bo_unref(&bo);
662 return r;
663 }
664
665 /**
666 * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object
667 * @adev: amdgpu device object
668 * @bp: parameters to be used for the buffer object
669 * @ubo_ptr: pointer to the buffer object pointer
670 *
671 * Create a BO to be used by user application;
672 *
673 * Returns:
674 * 0 for success or a negative error code on failure.
675 */
676
amdgpu_bo_create_user(struct amdgpu_device * adev,struct amdgpu_bo_param * bp,struct amdgpu_bo_user ** ubo_ptr)677 int amdgpu_bo_create_user(struct amdgpu_device *adev,
678 struct amdgpu_bo_param *bp,
679 struct amdgpu_bo_user **ubo_ptr)
680 {
681 struct amdgpu_bo *bo_ptr;
682 int r;
683
684 bp->bo_ptr_size = sizeof(struct amdgpu_bo_user);
685 bp->destroy = &amdgpu_bo_user_destroy;
686 r = amdgpu_bo_create(adev, bp, &bo_ptr);
687 if (r)
688 return r;
689
690 *ubo_ptr = to_amdgpu_bo_user(bo_ptr);
691 return r;
692 }
693
694 /**
695 * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object
696 * @adev: amdgpu device object
697 * @bp: parameters to be used for the buffer object
698 * @vmbo_ptr: pointer to the buffer object pointer
699 *
700 * Create a BO to be for GPUVM.
701 *
702 * Returns:
703 * 0 for success or a negative error code on failure.
704 */
705
amdgpu_bo_create_vm(struct amdgpu_device * adev,struct amdgpu_bo_param * bp,struct amdgpu_bo_vm ** vmbo_ptr)706 int amdgpu_bo_create_vm(struct amdgpu_device *adev,
707 struct amdgpu_bo_param *bp,
708 struct amdgpu_bo_vm **vmbo_ptr)
709 {
710 struct amdgpu_bo *bo_ptr;
711 int r;
712
713 /* bo_ptr_size will be determined by the caller and it depends on
714 * num of amdgpu_vm_pt entries.
715 */
716 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm));
717 r = amdgpu_bo_create(adev, bp, &bo_ptr);
718 if (r)
719 return r;
720
721 *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr);
722 return r;
723 }
724
725 /**
726 * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list
727 *
728 * @vmbo: BO that will be inserted into the shadow list
729 *
730 * Insert a BO to the shadow list.
731 */
amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm * vmbo)732 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo)
733 {
734 struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev);
735
736 mutex_lock(&adev->shadow_list_lock);
737 list_add_tail(&vmbo->shadow_list, &adev->shadow_list);
738 vmbo->shadow->parent = amdgpu_bo_ref(&vmbo->bo);
739 vmbo->shadow->tbo.destroy = &amdgpu_bo_vm_destroy;
740 mutex_unlock(&adev->shadow_list_lock);
741 }
742
743 /**
744 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow
745 *
746 * @shadow: &amdgpu_bo shadow to be restored
747 * @fence: dma_fence associated with the operation
748 *
749 * Copies a buffer object's shadow content back to the object.
750 * This is used for recovering a buffer from its shadow in case of a gpu
751 * reset where vram context may be lost.
752 *
753 * Returns:
754 * 0 for success or a negative error code on failure.
755 */
amdgpu_bo_restore_shadow(struct amdgpu_bo * shadow,struct dma_fence ** fence)756 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence)
757
758 {
759 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev);
760 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
761 uint64_t shadow_addr, parent_addr;
762
763 shadow_addr = amdgpu_bo_gpu_offset(shadow);
764 parent_addr = amdgpu_bo_gpu_offset(shadow->parent);
765
766 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr,
767 amdgpu_bo_size(shadow), NULL, fence,
768 true, false, 0);
769 }
770
771 /**
772 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object
773 * @bo: &amdgpu_bo buffer object to be mapped
774 * @ptr: kernel virtual address to be returned
775 *
776 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls
777 * amdgpu_bo_kptr() to get the kernel virtual address.
778 *
779 * Returns:
780 * 0 for success or a negative error code on failure.
781 */
amdgpu_bo_kmap(struct amdgpu_bo * bo,void ** ptr)782 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
783 {
784 void *kptr;
785 long r;
786
787 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
788 return -EPERM;
789
790 r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL,
791 false, MAX_SCHEDULE_TIMEOUT);
792 if (r < 0)
793 return r;
794
795 kptr = amdgpu_bo_kptr(bo);
796 if (kptr) {
797 if (ptr)
798 *ptr = kptr;
799 return 0;
800 }
801
802 r = ttm_bo_kmap(&bo->tbo, 0, PFN_UP(bo->tbo.base.size), &bo->kmap);
803 if (r)
804 return r;
805
806 if (ptr)
807 *ptr = amdgpu_bo_kptr(bo);
808
809 return 0;
810 }
811
812 /**
813 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object
814 * @bo: &amdgpu_bo buffer object
815 *
816 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address
817 *
818 * Returns:
819 * the virtual address of a buffer object area.
820 */
amdgpu_bo_kptr(struct amdgpu_bo * bo)821 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
822 {
823 bool is_iomem;
824
825 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
826 }
827
828 /**
829 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object
830 * @bo: &amdgpu_bo buffer object to be unmapped
831 *
832 * Unmaps a kernel map set up by amdgpu_bo_kmap().
833 */
amdgpu_bo_kunmap(struct amdgpu_bo * bo)834 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
835 {
836 if (bo->kmap.bo)
837 ttm_bo_kunmap(&bo->kmap);
838 }
839
840 /**
841 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object
842 * @bo: &amdgpu_bo buffer object
843 *
844 * References the contained &ttm_buffer_object.
845 *
846 * Returns:
847 * a refcounted pointer to the &amdgpu_bo buffer object.
848 */
amdgpu_bo_ref(struct amdgpu_bo * bo)849 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
850 {
851 if (bo == NULL)
852 return NULL;
853
854 ttm_bo_get(&bo->tbo);
855 return bo;
856 }
857
858 /**
859 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object
860 * @bo: &amdgpu_bo buffer object
861 *
862 * Unreferences the contained &ttm_buffer_object and clear the pointer
863 */
amdgpu_bo_unref(struct amdgpu_bo ** bo)864 void amdgpu_bo_unref(struct amdgpu_bo **bo)
865 {
866 struct ttm_buffer_object *tbo;
867
868 if ((*bo) == NULL)
869 return;
870
871 tbo = &((*bo)->tbo);
872 ttm_bo_put(tbo);
873 *bo = NULL;
874 }
875
876 /**
877 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object
878 * @bo: &amdgpu_bo buffer object to be pinned
879 * @domain: domain to be pinned to
880 * @min_offset: the start of requested address range
881 * @max_offset: the end of requested address range
882 *
883 * Pins the buffer object according to requested domain and address range. If
884 * the memory is unbound gart memory, binds the pages into gart table. Adjusts
885 * pin_count and pin_size accordingly.
886 *
887 * Pinning means to lock pages in memory along with keeping them at a fixed
888 * offset. It is required when a buffer can not be moved, for example, when
889 * a display buffer is being scanned out.
890 *
891 * Compared with amdgpu_bo_pin(), this function gives more flexibility on
892 * where to pin a buffer if there are specific restrictions on where a buffer
893 * must be located.
894 *
895 * Returns:
896 * 0 for success or a negative error code on failure.
897 */
amdgpu_bo_pin_restricted(struct amdgpu_bo * bo,u32 domain,u64 min_offset,u64 max_offset)898 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
899 u64 min_offset, u64 max_offset)
900 {
901 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
902 struct ttm_operation_ctx ctx = { false, false };
903 int r, i;
904
905 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
906 return -EPERM;
907
908 if (WARN_ON_ONCE(min_offset > max_offset))
909 return -EINVAL;
910
911 /* Check domain to be pinned to against preferred domains */
912 if (bo->preferred_domains & domain)
913 domain = bo->preferred_domains & domain;
914
915 /* A shared bo cannot be migrated to VRAM */
916 if (bo->tbo.base.import_attach) {
917 if (domain & AMDGPU_GEM_DOMAIN_GTT)
918 domain = AMDGPU_GEM_DOMAIN_GTT;
919 else
920 return -EINVAL;
921 }
922
923 if (bo->tbo.pin_count) {
924 uint32_t mem_type = bo->tbo.resource->mem_type;
925 uint32_t mem_flags = bo->tbo.resource->placement;
926
927 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
928 return -EINVAL;
929
930 if ((mem_type == TTM_PL_VRAM) &&
931 (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) &&
932 !(mem_flags & TTM_PL_FLAG_CONTIGUOUS))
933 return -EINVAL;
934
935 ttm_bo_pin(&bo->tbo);
936
937 if (max_offset != 0) {
938 u64 domain_start = amdgpu_ttm_domain_start(adev,
939 mem_type);
940 WARN_ON_ONCE(max_offset <
941 (amdgpu_bo_gpu_offset(bo) - domain_start));
942 }
943
944 return 0;
945 }
946
947 /* This assumes only APU display buffers are pinned with (VRAM|GTT).
948 * See function amdgpu_display_supported_domains()
949 */
950 domain = amdgpu_bo_get_preferred_domain(adev, domain);
951
952 if (bo->tbo.base.import_attach)
953 dma_buf_pin(bo->tbo.base.import_attach);
954
955 /* force to pin into visible video ram */
956 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
957 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
958 amdgpu_bo_placement_from_domain(bo, domain);
959 for (i = 0; i < bo->placement.num_placement; i++) {
960 unsigned int fpfn, lpfn;
961
962 fpfn = min_offset >> PAGE_SHIFT;
963 lpfn = max_offset >> PAGE_SHIFT;
964
965 if (fpfn > bo->placements[i].fpfn)
966 bo->placements[i].fpfn = fpfn;
967 if (!bo->placements[i].lpfn ||
968 (lpfn && lpfn < bo->placements[i].lpfn))
969 bo->placements[i].lpfn = lpfn;
970
971 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS &&
972 bo->placements[i].mem_type == TTM_PL_VRAM)
973 bo->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS;
974 }
975
976 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
977 if (unlikely(r)) {
978 dev_err(adev->dev, "%p pin failed\n", bo);
979 goto error;
980 }
981
982 ttm_bo_pin(&bo->tbo);
983
984 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) {
985 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size);
986 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo),
987 &adev->visible_pin_size);
988 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) {
989 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size);
990 }
991
992 error:
993 return r;
994 }
995
996 /**
997 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object
998 * @bo: &amdgpu_bo buffer object to be pinned
999 * @domain: domain to be pinned to
1000 *
1001 * A simple wrapper to amdgpu_bo_pin_restricted().
1002 * Provides a simpler API for buffers that do not have any strict restrictions
1003 * on where a buffer must be located.
1004 *
1005 * Returns:
1006 * 0 for success or a negative error code on failure.
1007 */
amdgpu_bo_pin(struct amdgpu_bo * bo,u32 domain)1008 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)
1009 {
1010 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1011 return amdgpu_bo_pin_restricted(bo, domain, 0, 0);
1012 }
1013
1014 /**
1015 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object
1016 * @bo: &amdgpu_bo buffer object to be unpinned
1017 *
1018 * Decreases the pin_count, and clears the flags if pin_count reaches 0.
1019 * Changes placement and pin size accordingly.
1020 *
1021 * Returns:
1022 * 0 for success or a negative error code on failure.
1023 */
amdgpu_bo_unpin(struct amdgpu_bo * bo)1024 void amdgpu_bo_unpin(struct amdgpu_bo *bo)
1025 {
1026 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1027
1028 ttm_bo_unpin(&bo->tbo);
1029 if (bo->tbo.pin_count)
1030 return;
1031
1032 if (bo->tbo.base.import_attach)
1033 dma_buf_unpin(bo->tbo.base.import_attach);
1034
1035 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) {
1036 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size);
1037 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo),
1038 &adev->visible_pin_size);
1039 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) {
1040 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);
1041 }
1042
1043 }
1044
1045 static const char * const amdgpu_vram_names[] = {
1046 "UNKNOWN",
1047 "GDDR1",
1048 "DDR2",
1049 "GDDR3",
1050 "GDDR4",
1051 "GDDR5",
1052 "HBM",
1053 "DDR3",
1054 "DDR4",
1055 "GDDR6",
1056 "DDR5",
1057 "LPDDR4",
1058 "LPDDR5"
1059 };
1060
1061 /**
1062 * amdgpu_bo_init - initialize memory manager
1063 * @adev: amdgpu device object
1064 *
1065 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager.
1066 *
1067 * Returns:
1068 * 0 for success or a negative error code on failure.
1069 */
amdgpu_bo_init(struct amdgpu_device * adev)1070 int amdgpu_bo_init(struct amdgpu_device *adev)
1071 {
1072 /* On A+A platform, VRAM can be mapped as WB */
1073 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
1074 /* reserve PAT memory space to WC for VRAM */
1075 int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base,
1076 adev->gmc.aper_size);
1077
1078 if (r) {
1079 DRM_ERROR("Unable to set WC memtype for the aperture base\n");
1080 return r;
1081 }
1082
1083 /* Add an MTRR for the VRAM */
1084 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
1085 adev->gmc.aper_size);
1086 }
1087
1088 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
1089 adev->gmc.mc_vram_size >> 20,
1090 (unsigned long long)adev->gmc.aper_size >> 20);
1091 DRM_INFO("RAM width %dbits %s\n",
1092 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
1093 return amdgpu_ttm_init(adev);
1094 }
1095
1096 /**
1097 * amdgpu_bo_fini - tear down memory manager
1098 * @adev: amdgpu device object
1099 *
1100 * Reverses amdgpu_bo_init() to tear down memory manager.
1101 */
amdgpu_bo_fini(struct amdgpu_device * adev)1102 void amdgpu_bo_fini(struct amdgpu_device *adev)
1103 {
1104 int idx;
1105
1106 amdgpu_ttm_fini(adev);
1107
1108 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
1109 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
1110 arch_phys_wc_del(adev->gmc.vram_mtrr);
1111 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
1112 }
1113 drm_dev_exit(idx);
1114 }
1115 }
1116
1117 /**
1118 * amdgpu_bo_set_tiling_flags - set tiling flags
1119 * @bo: &amdgpu_bo buffer object
1120 * @tiling_flags: new flags
1121 *
1122 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or
1123 * kernel driver to set the tiling flags on a buffer.
1124 *
1125 * Returns:
1126 * 0 for success or a negative error code on failure.
1127 */
amdgpu_bo_set_tiling_flags(struct amdgpu_bo * bo,u64 tiling_flags)1128 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
1129 {
1130 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1131 struct amdgpu_bo_user *ubo;
1132
1133 BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1134 if (adev->family <= AMDGPU_FAMILY_CZ &&
1135 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
1136 return -EINVAL;
1137
1138 ubo = to_amdgpu_bo_user(bo);
1139 ubo->tiling_flags = tiling_flags;
1140 return 0;
1141 }
1142
1143 /**
1144 * amdgpu_bo_get_tiling_flags - get tiling flags
1145 * @bo: &amdgpu_bo buffer object
1146 * @tiling_flags: returned flags
1147 *
1148 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to
1149 * set the tiling flags on a buffer.
1150 */
amdgpu_bo_get_tiling_flags(struct amdgpu_bo * bo,u64 * tiling_flags)1151 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
1152 {
1153 struct amdgpu_bo_user *ubo;
1154
1155 BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1156 dma_resv_assert_held(bo->tbo.base.resv);
1157 ubo = to_amdgpu_bo_user(bo);
1158
1159 if (tiling_flags)
1160 *tiling_flags = ubo->tiling_flags;
1161 }
1162
1163 /**
1164 * amdgpu_bo_set_metadata - set metadata
1165 * @bo: &amdgpu_bo buffer object
1166 * @metadata: new metadata
1167 * @metadata_size: size of the new metadata
1168 * @flags: flags of the new metadata
1169 *
1170 * Sets buffer object's metadata, its size and flags.
1171 * Used via GEM ioctl.
1172 *
1173 * Returns:
1174 * 0 for success or a negative error code on failure.
1175 */
amdgpu_bo_set_metadata(struct amdgpu_bo * bo,void * metadata,u32 metadata_size,uint64_t flags)1176 int amdgpu_bo_set_metadata(struct amdgpu_bo *bo, void *metadata,
1177 u32 metadata_size, uint64_t flags)
1178 {
1179 struct amdgpu_bo_user *ubo;
1180 void *buffer;
1181
1182 BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1183 ubo = to_amdgpu_bo_user(bo);
1184 if (!metadata_size) {
1185 if (ubo->metadata_size) {
1186 kfree(ubo->metadata);
1187 ubo->metadata = NULL;
1188 ubo->metadata_size = 0;
1189 }
1190 return 0;
1191 }
1192
1193 if (metadata == NULL)
1194 return -EINVAL;
1195
1196 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
1197 if (buffer == NULL)
1198 return -ENOMEM;
1199
1200 kfree(ubo->metadata);
1201 ubo->metadata_flags = flags;
1202 ubo->metadata = buffer;
1203 ubo->metadata_size = metadata_size;
1204
1205 return 0;
1206 }
1207
1208 /**
1209 * amdgpu_bo_get_metadata - get metadata
1210 * @bo: &amdgpu_bo buffer object
1211 * @buffer: returned metadata
1212 * @buffer_size: size of the buffer
1213 * @metadata_size: size of the returned metadata
1214 * @flags: flags of the returned metadata
1215 *
1216 * Gets buffer object's metadata, its size and flags. buffer_size shall not be
1217 * less than metadata_size.
1218 * Used via GEM ioctl.
1219 *
1220 * Returns:
1221 * 0 for success or a negative error code on failure.
1222 */
amdgpu_bo_get_metadata(struct amdgpu_bo * bo,void * buffer,size_t buffer_size,uint32_t * metadata_size,uint64_t * flags)1223 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
1224 size_t buffer_size, uint32_t *metadata_size,
1225 uint64_t *flags)
1226 {
1227 struct amdgpu_bo_user *ubo;
1228
1229 if (!buffer && !metadata_size)
1230 return -EINVAL;
1231
1232 BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1233 ubo = to_amdgpu_bo_user(bo);
1234 if (metadata_size)
1235 *metadata_size = ubo->metadata_size;
1236
1237 if (buffer) {
1238 if (buffer_size < ubo->metadata_size)
1239 return -EINVAL;
1240
1241 if (ubo->metadata_size)
1242 memcpy(buffer, ubo->metadata, ubo->metadata_size);
1243 }
1244
1245 if (flags)
1246 *flags = ubo->metadata_flags;
1247
1248 return 0;
1249 }
1250
1251 /**
1252 * amdgpu_bo_move_notify - notification about a memory move
1253 * @bo: pointer to a buffer object
1254 * @evict: if this move is evicting the buffer from the graphics address space
1255 * @new_mem: new resource for backing the BO
1256 *
1257 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs
1258 * bookkeeping.
1259 * TTM driver callback which is called when ttm moves a buffer.
1260 */
amdgpu_bo_move_notify(struct ttm_buffer_object * bo,bool evict,struct ttm_resource * new_mem)1261 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
1262 bool evict,
1263 struct ttm_resource *new_mem)
1264 {
1265 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1266 struct ttm_resource *old_mem = bo->resource;
1267 struct amdgpu_bo *abo;
1268
1269 if (!amdgpu_bo_is_amdgpu_bo(bo))
1270 return;
1271
1272 abo = ttm_to_amdgpu_bo(bo);
1273 amdgpu_vm_bo_invalidate(adev, abo, evict);
1274
1275 amdgpu_bo_kunmap(abo);
1276
1277 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach &&
1278 old_mem && old_mem->mem_type != TTM_PL_SYSTEM)
1279 dma_buf_move_notify(abo->tbo.base.dma_buf);
1280
1281 /* move_notify is called before move happens */
1282 trace_amdgpu_bo_move(abo, new_mem ? new_mem->mem_type : -1,
1283 old_mem ? old_mem->mem_type : -1);
1284 }
1285
amdgpu_bo_get_memory(struct amdgpu_bo * bo,struct amdgpu_mem_stats * stats)1286 void amdgpu_bo_get_memory(struct amdgpu_bo *bo,
1287 struct amdgpu_mem_stats *stats)
1288 {
1289 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1290 struct ttm_resource *res = bo->tbo.resource;
1291 uint64_t size = amdgpu_bo_size(bo);
1292 struct drm_gem_object *obj;
1293 bool shared;
1294
1295 /* Abort if the BO doesn't currently have a backing store */
1296 if (!res)
1297 return;
1298
1299 obj = &bo->tbo.base;
1300 shared = drm_gem_object_is_shared_for_memory_stats(obj);
1301
1302 switch (res->mem_type) {
1303 case TTM_PL_VRAM:
1304 stats->vram += size;
1305 if (amdgpu_res_cpu_visible(adev, res))
1306 stats->visible_vram += size;
1307 if (shared)
1308 stats->vram_shared += size;
1309 break;
1310 case TTM_PL_TT:
1311 stats->gtt += size;
1312 if (shared)
1313 stats->gtt_shared += size;
1314 break;
1315 case TTM_PL_SYSTEM:
1316 default:
1317 stats->cpu += size;
1318 if (shared)
1319 stats->cpu_shared += size;
1320 break;
1321 }
1322
1323 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) {
1324 stats->requested_vram += size;
1325 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
1326 stats->requested_visible_vram += size;
1327
1328 if (res->mem_type != TTM_PL_VRAM) {
1329 stats->evicted_vram += size;
1330 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
1331 stats->evicted_visible_vram += size;
1332 }
1333 } else if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_GTT) {
1334 stats->requested_gtt += size;
1335 }
1336 }
1337
1338 /**
1339 * amdgpu_bo_release_notify - notification about a BO being released
1340 * @bo: pointer to a buffer object
1341 *
1342 * Wipes VRAM buffers whose contents should not be leaked before the
1343 * memory is released.
1344 */
amdgpu_bo_release_notify(struct ttm_buffer_object * bo)1345 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
1346 {
1347 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1348 struct dma_fence *fence = NULL;
1349 struct amdgpu_bo *abo;
1350 int r;
1351
1352 if (!amdgpu_bo_is_amdgpu_bo(bo))
1353 return;
1354
1355 abo = ttm_to_amdgpu_bo(bo);
1356
1357 WARN_ON(abo->vm_bo);
1358
1359 if (abo->kfd_bo)
1360 amdgpu_amdkfd_release_notify(abo);
1361
1362 /* We only remove the fence if the resv has individualized. */
1363 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel
1364 && bo->base.resv != &bo->base._resv);
1365 if (bo->base.resv == &bo->base._resv)
1366 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);
1367
1368 if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM ||
1369 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) ||
1370 adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev)))
1371 return;
1372
1373 if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv)))
1374 return;
1375
1376 r = amdgpu_fill_buffer(abo, 0, bo->base.resv, &fence, true);
1377 if (!WARN_ON(r)) {
1378 amdgpu_vram_mgr_set_cleared(bo->resource);
1379 amdgpu_bo_fence(abo, fence, false);
1380 dma_fence_put(fence);
1381 }
1382
1383 dma_resv_unlock(bo->base.resv);
1384 }
1385
1386 /**
1387 * amdgpu_bo_fault_reserve_notify - notification about a memory fault
1388 * @bo: pointer to a buffer object
1389 *
1390 * Notifies the driver we are taking a fault on this BO and have reserved it,
1391 * also performs bookkeeping.
1392 * TTM driver callback for dealing with vm faults.
1393 *
1394 * Returns:
1395 * 0 for success or a negative error code on failure.
1396 */
amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object * bo)1397 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
1398 {
1399 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1400 struct ttm_operation_ctx ctx = { false, false };
1401 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1402 int r;
1403
1404 /* Remember that this BO was accessed by the CPU */
1405 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1406
1407 if (amdgpu_res_cpu_visible(adev, bo->resource))
1408 return 0;
1409
1410 /* Can't move a pinned BO to visible VRAM */
1411 if (abo->tbo.pin_count > 0)
1412 return VM_FAULT_SIGBUS;
1413
1414 /* hurrah the memory is not visible ! */
1415 atomic64_inc(&adev->num_vram_cpu_page_faults);
1416 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
1417 AMDGPU_GEM_DOMAIN_GTT);
1418
1419 /* Avoid costly evictions; only set GTT as a busy placement */
1420 abo->placements[0].flags |= TTM_PL_FLAG_DESIRED;
1421
1422 r = ttm_bo_validate(bo, &abo->placement, &ctx);
1423 if (unlikely(r == -EBUSY || r == -ERESTARTSYS))
1424 return VM_FAULT_NOPAGE;
1425 else if (unlikely(r))
1426 return VM_FAULT_SIGBUS;
1427
1428 /* this should never happen */
1429 if (bo->resource->mem_type == TTM_PL_VRAM &&
1430 !amdgpu_res_cpu_visible(adev, bo->resource))
1431 return VM_FAULT_SIGBUS;
1432
1433 ttm_bo_move_to_lru_tail_unlocked(bo);
1434 return 0;
1435 }
1436
1437 /**
1438 * amdgpu_bo_fence - add fence to buffer object
1439 *
1440 * @bo: buffer object in question
1441 * @fence: fence to add
1442 * @shared: true if fence should be added shared
1443 *
1444 */
amdgpu_bo_fence(struct amdgpu_bo * bo,struct dma_fence * fence,bool shared)1445 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1446 bool shared)
1447 {
1448 struct dma_resv *resv = bo->tbo.base.resv;
1449 int r;
1450
1451 r = dma_resv_reserve_fences(resv, 1);
1452 if (r) {
1453 /* As last resort on OOM we block for the fence */
1454 dma_fence_wait(fence, false);
1455 return;
1456 }
1457
1458 dma_resv_add_fence(resv, fence, shared ? DMA_RESV_USAGE_READ :
1459 DMA_RESV_USAGE_WRITE);
1460 }
1461
1462 /**
1463 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences
1464 *
1465 * @adev: amdgpu device pointer
1466 * @resv: reservation object to sync to
1467 * @sync_mode: synchronization mode
1468 * @owner: fence owner
1469 * @intr: Whether the wait is interruptible
1470 *
1471 * Extract the fences from the reservation object and waits for them to finish.
1472 *
1473 * Returns:
1474 * 0 on success, errno otherwise.
1475 */
amdgpu_bo_sync_wait_resv(struct amdgpu_device * adev,struct dma_resv * resv,enum amdgpu_sync_mode sync_mode,void * owner,bool intr)1476 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
1477 enum amdgpu_sync_mode sync_mode, void *owner,
1478 bool intr)
1479 {
1480 struct amdgpu_sync sync;
1481 int r;
1482
1483 amdgpu_sync_create(&sync);
1484 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);
1485 r = amdgpu_sync_wait(&sync, intr);
1486 amdgpu_sync_free(&sync);
1487 return r;
1488 }
1489
1490 /**
1491 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv
1492 * @bo: buffer object to wait for
1493 * @owner: fence owner
1494 * @intr: Whether the wait is interruptible
1495 *
1496 * Wrapper to wait for fences in a BO.
1497 * Returns:
1498 * 0 on success, errno otherwise.
1499 */
amdgpu_bo_sync_wait(struct amdgpu_bo * bo,void * owner,bool intr)1500 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
1501 {
1502 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1503
1504 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,
1505 AMDGPU_SYNC_NE_OWNER, owner, intr);
1506 }
1507
1508 /**
1509 * amdgpu_bo_gpu_offset - return GPU offset of bo
1510 * @bo: amdgpu object for which we query the offset
1511 *
1512 * Note: object should either be pinned or reserved when calling this
1513 * function, it might be useful to add check for this for debugging.
1514 *
1515 * Returns:
1516 * current GPU offset of the object.
1517 */
amdgpu_bo_gpu_offset(struct amdgpu_bo * bo)1518 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1519 {
1520 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM);
1521 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) &&
1522 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel);
1523 WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET);
1524 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM &&
1525 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1526
1527 return amdgpu_bo_gpu_offset_no_check(bo);
1528 }
1529
1530 /**
1531 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo
1532 * @bo: amdgpu object for which we query the offset
1533 *
1534 * Returns:
1535 * current GPU offset of the object without raising warnings.
1536 */
amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo * bo)1537 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
1538 {
1539 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1540 uint64_t offset = AMDGPU_BO_INVALID_OFFSET;
1541
1542 if (bo->tbo.resource->mem_type == TTM_PL_TT)
1543 offset = amdgpu_gmc_agp_addr(&bo->tbo);
1544
1545 if (offset == AMDGPU_BO_INVALID_OFFSET)
1546 offset = (bo->tbo.resource->start << PAGE_SHIFT) +
1547 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
1548
1549 return amdgpu_gmc_sign_extend(offset);
1550 }
1551
1552 /**
1553 * amdgpu_bo_get_preferred_domain - get preferred domain
1554 * @adev: amdgpu device object
1555 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>`
1556 *
1557 * Returns:
1558 * Which of the allowed domains is preferred for allocating the BO.
1559 */
amdgpu_bo_get_preferred_domain(struct amdgpu_device * adev,uint32_t domain)1560 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
1561 uint32_t domain)
1562 {
1563 if ((domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) &&
1564 ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY))) {
1565 domain = AMDGPU_GEM_DOMAIN_VRAM;
1566 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
1567 domain = AMDGPU_GEM_DOMAIN_GTT;
1568 }
1569 return domain;
1570 }
1571
1572 #if defined(CONFIG_DEBUG_FS)
1573 #define amdgpu_bo_print_flag(m, bo, flag) \
1574 do { \
1575 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \
1576 seq_printf((m), " " #flag); \
1577 } \
1578 } while (0)
1579
1580 /**
1581 * amdgpu_bo_print_info - print BO info in debugfs file
1582 *
1583 * @id: Index or Id of the BO
1584 * @bo: Requested BO for printing info
1585 * @m: debugfs file
1586 *
1587 * Print BO information in debugfs file
1588 *
1589 * Returns:
1590 * Size of the BO in bytes.
1591 */
amdgpu_bo_print_info(int id,struct amdgpu_bo * bo,struct seq_file * m)1592 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)
1593 {
1594 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1595 struct dma_buf_attachment *attachment;
1596 struct dma_buf *dma_buf;
1597 const char *placement;
1598 unsigned int pin_count;
1599 u64 size;
1600
1601 if (dma_resv_trylock(bo->tbo.base.resv)) {
1602 if (!bo->tbo.resource) {
1603 placement = "NONE";
1604 } else {
1605 switch (bo->tbo.resource->mem_type) {
1606 case TTM_PL_VRAM:
1607 if (amdgpu_res_cpu_visible(adev, bo->tbo.resource))
1608 placement = "VRAM VISIBLE";
1609 else
1610 placement = "VRAM";
1611 break;
1612 case TTM_PL_TT:
1613 placement = "GTT";
1614 break;
1615 case AMDGPU_PL_GDS:
1616 placement = "GDS";
1617 break;
1618 case AMDGPU_PL_GWS:
1619 placement = "GWS";
1620 break;
1621 case AMDGPU_PL_OA:
1622 placement = "OA";
1623 break;
1624 case AMDGPU_PL_PREEMPT:
1625 placement = "PREEMPTIBLE";
1626 break;
1627 case AMDGPU_PL_DOORBELL:
1628 placement = "DOORBELL";
1629 break;
1630 case TTM_PL_SYSTEM:
1631 default:
1632 placement = "CPU";
1633 break;
1634 }
1635 }
1636 dma_resv_unlock(bo->tbo.base.resv);
1637 } else {
1638 placement = "UNKNOWN";
1639 }
1640
1641 size = amdgpu_bo_size(bo);
1642 seq_printf(m, "\t\t0x%08x: %12lld byte %s",
1643 id, size, placement);
1644
1645 pin_count = READ_ONCE(bo->tbo.pin_count);
1646 if (pin_count)
1647 seq_printf(m, " pin count %d", pin_count);
1648
1649 dma_buf = READ_ONCE(bo->tbo.base.dma_buf);
1650 attachment = READ_ONCE(bo->tbo.base.import_attach);
1651
1652 if (attachment)
1653 seq_printf(m, " imported from ino:%lu", file_inode(dma_buf->file)->i_ino);
1654 else if (dma_buf)
1655 seq_printf(m, " exported as ino:%lu", file_inode(dma_buf->file)->i_ino);
1656
1657 amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
1658 amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS);
1659 amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC);
1660 amdgpu_bo_print_flag(m, bo, VRAM_CLEARED);
1661 amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
1662 amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID);
1663 amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC);
1664
1665 seq_puts(m, "\n");
1666
1667 return size;
1668 }
1669 #endif
1670