1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/endian.h>
36 #include <sys/kernel.h>
37 #include <sys/lock.h>
38 #include <sys/malloc.h>
39 #include <sys/mbuf.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/rman.h>
43 #include <sys/queue.h>
44 #include <sys/socket.h>
45 #include <sys/sockio.h>
46 #include <sys/sysctl.h>
47 #include <sys/taskqueue.h>
48
49 #include <net/bpf.h>
50 #include <net/debugnet.h>
51 #include <net/if.h>
52 #include <net/if_var.h>
53 #include <net/if_arp.h>
54 #include <net/ethernet.h>
55 #include <net/if_dl.h>
56 #include <net/if_llc.h>
57 #include <net/if_media.h>
58 #include <net/if_types.h>
59 #include <net/if_vlan_var.h>
60
61 #include <netinet/in.h>
62 #include <netinet/in_systm.h>
63 #include <netinet/ip.h>
64 #include <netinet/tcp.h>
65
66 #include <dev/mii/mii.h>
67 #include <dev/mii/miivar.h>
68
69 #include <dev/pci/pcireg.h>
70 #include <dev/pci/pcivar.h>
71
72 #include <machine/bus.h>
73 #include <machine/in_cksum.h>
74
75 #include <dev/alc/if_alcreg.h>
76 #include <dev/alc/if_alcvar.h>
77
78 /* "device miibus" required. See GENERIC if you get errors here. */
79 #include "miibus_if.h"
80 #undef ALC_USE_CUSTOM_CSUM
81
82 #ifdef ALC_USE_CUSTOM_CSUM
83 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
84 #else
85 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
86 #endif
87
88 MODULE_DEPEND(alc, pci, 1, 1, 1);
89 MODULE_DEPEND(alc, ether, 1, 1, 1);
90 MODULE_DEPEND(alc, miibus, 1, 1, 1);
91
92 /* Tunables. */
93 static int msi_disable = 0;
94 TUNABLE_INT("hw.alc.msi_disable", &msi_disable);
95
96 /*
97 * The default value of msix_disable is 2, which means to decide whether to
98 * enable MSI-X in alc_attach() depending on the card type. The operator can
99 * set this to 0 or 1 to override the default.
100 */
101 static int msix_disable = 2;
102 TUNABLE_INT("hw.alc.msix_disable", &msix_disable);
103
104 /*
105 * Devices supported by this driver.
106 */
107 static struct alc_ident alc_ident_table[] = {
108 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024,
109 "Atheros AR8131 PCIe Gigabit Ethernet" },
110 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024,
111 "Atheros AR8132 PCIe Fast Ethernet" },
112 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024,
113 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" },
114 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024,
115 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" },
116 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024,
117 "Atheros AR8152 v1.1 PCIe Fast Ethernet" },
118 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024,
119 "Atheros AR8152 v2.0 PCIe Fast Ethernet" },
120 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024,
121 "Atheros AR8161 PCIe Gigabit Ethernet" },
122 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024,
123 "Atheros AR8162 PCIe Fast Ethernet" },
124 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024,
125 "Atheros AR8171 PCIe Gigabit Ethernet" },
126 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024,
127 "Atheros AR8172 PCIe Fast Ethernet" },
128 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024,
129 "Killer E2200 Gigabit Ethernet" },
130 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024,
131 "Killer E2400 Gigabit Ethernet" },
132 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024,
133 "Killer E2500 Gigabit Ethernet" },
134 { 0, 0, 0, NULL}
135 };
136
137 static void alc_aspm(struct alc_softc *, int, int);
138 static void alc_aspm_813x(struct alc_softc *, int);
139 static void alc_aspm_816x(struct alc_softc *, int);
140 static int alc_attach(device_t);
141 static int alc_check_boundary(struct alc_softc *);
142 static void alc_config_msi(struct alc_softc *);
143 static int alc_detach(device_t);
144 static void alc_disable_l0s_l1(struct alc_softc *);
145 static int alc_dma_alloc(struct alc_softc *);
146 static void alc_dma_free(struct alc_softc *);
147 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int);
148 static void alc_dsp_fixup(struct alc_softc *, int);
149 static int alc_encap(struct alc_softc *, struct mbuf **);
150 static struct alc_ident *
151 alc_find_ident(device_t);
152 #ifndef __NO_STRICT_ALIGNMENT
153 static struct mbuf *
154 alc_fixup_rx(if_t, struct mbuf *);
155 #endif
156 static void alc_get_macaddr(struct alc_softc *);
157 static void alc_get_macaddr_813x(struct alc_softc *);
158 static void alc_get_macaddr_816x(struct alc_softc *);
159 static void alc_get_macaddr_par(struct alc_softc *);
160 static void alc_init(void *);
161 static void alc_init_cmb(struct alc_softc *);
162 static void alc_init_locked(struct alc_softc *);
163 static void alc_init_rr_ring(struct alc_softc *);
164 static int alc_init_rx_ring(struct alc_softc *);
165 static void alc_init_smb(struct alc_softc *);
166 static void alc_init_tx_ring(struct alc_softc *);
167 static void alc_int_task(void *, int);
168 static int alc_intr(void *);
169 static int alc_ioctl(if_t, u_long, caddr_t);
170 static void alc_mac_config(struct alc_softc *);
171 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int);
172 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int);
173 static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int);
174 static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int);
175 static int alc_miibus_readreg(device_t, int, int);
176 static void alc_miibus_statchg(device_t);
177 static int alc_miibus_writereg(device_t, int, int, int);
178 static uint32_t alc_miidbg_readreg(struct alc_softc *, int);
179 static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int);
180 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int);
181 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int);
182 static int alc_mediachange(if_t);
183 static int alc_mediachange_locked(struct alc_softc *);
184 static void alc_mediastatus(if_t, struct ifmediareq *);
185 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *);
186 static void alc_osc_reset(struct alc_softc *);
187 static void alc_phy_down(struct alc_softc *);
188 static void alc_phy_reset(struct alc_softc *);
189 static void alc_phy_reset_813x(struct alc_softc *);
190 static void alc_phy_reset_816x(struct alc_softc *);
191 static int alc_probe(device_t);
192 static void alc_reset(struct alc_softc *);
193 static int alc_resume(device_t);
194 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *);
195 static int alc_rxintr(struct alc_softc *, int);
196 static void alc_rxfilter(struct alc_softc *);
197 static void alc_rxvlan(struct alc_softc *);
198 static void alc_setlinkspeed(struct alc_softc *);
199 static void alc_setwol(struct alc_softc *);
200 static void alc_setwol_813x(struct alc_softc *);
201 static void alc_setwol_816x(struct alc_softc *);
202 static int alc_shutdown(device_t);
203 static void alc_start(if_t);
204 static void alc_start_locked(if_t);
205 static void alc_start_queue(struct alc_softc *);
206 static void alc_start_tx(struct alc_softc *);
207 static void alc_stats_clear(struct alc_softc *);
208 static void alc_stats_update(struct alc_softc *);
209 static void alc_stop(struct alc_softc *);
210 static void alc_stop_mac(struct alc_softc *);
211 static void alc_stop_queue(struct alc_softc *);
212 static int alc_suspend(device_t);
213 static void alc_sysctl_node(struct alc_softc *);
214 static void alc_tick(void *);
215 static void alc_txeof(struct alc_softc *);
216 static void alc_watchdog(struct alc_softc *);
217 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
218 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS);
219 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS);
220
221 DEBUGNET_DEFINE(alc);
222
223 static device_method_t alc_methods[] = {
224 /* Device interface. */
225 DEVMETHOD(device_probe, alc_probe),
226 DEVMETHOD(device_attach, alc_attach),
227 DEVMETHOD(device_detach, alc_detach),
228 DEVMETHOD(device_shutdown, alc_shutdown),
229 DEVMETHOD(device_suspend, alc_suspend),
230 DEVMETHOD(device_resume, alc_resume),
231
232 /* MII interface. */
233 DEVMETHOD(miibus_readreg, alc_miibus_readreg),
234 DEVMETHOD(miibus_writereg, alc_miibus_writereg),
235 DEVMETHOD(miibus_statchg, alc_miibus_statchg),
236
237 DEVMETHOD_END
238 };
239
240 static driver_t alc_driver = {
241 "alc",
242 alc_methods,
243 sizeof(struct alc_softc)
244 };
245
246 DRIVER_MODULE(alc, pci, alc_driver, 0, 0);
247 MODULE_PNP_INFO("U16:vendor;U16:device", pci, alc, alc_ident_table,
248 nitems(alc_ident_table) - 1);
249 DRIVER_MODULE(miibus, alc, miibus_driver, 0, 0);
250
251 static struct resource_spec alc_res_spec_mem[] = {
252 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
253 { -1, 0, 0 }
254 };
255
256 static struct resource_spec alc_irq_spec_legacy[] = {
257 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
258 { -1, 0, 0 }
259 };
260
261 static struct resource_spec alc_irq_spec_msi[] = {
262 { SYS_RES_IRQ, 1, RF_ACTIVE },
263 { -1, 0, 0 }
264 };
265
266 static struct resource_spec alc_irq_spec_msix[] = {
267 { SYS_RES_IRQ, 1, RF_ACTIVE },
268 { -1, 0, 0 }
269 };
270
271 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 };
272
273 static int
alc_miibus_readreg(device_t dev,int phy,int reg)274 alc_miibus_readreg(device_t dev, int phy, int reg)
275 {
276 struct alc_softc *sc;
277 int v;
278
279 sc = device_get_softc(dev);
280 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
281 v = alc_mii_readreg_816x(sc, phy, reg);
282 else
283 v = alc_mii_readreg_813x(sc, phy, reg);
284 return (v);
285 }
286
287 static uint32_t
alc_mii_readreg_813x(struct alc_softc * sc,int phy,int reg)288 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg)
289 {
290 uint32_t v;
291 int i;
292
293 /*
294 * For AR8132 fast ethernet controller, do not report 1000baseT
295 * capability to mii(4). Even though AR8132 uses the same
296 * model/revision number of F1 gigabit PHY, the PHY has no
297 * ability to establish 1000baseT link.
298 */
299 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 &&
300 reg == MII_EXTSR)
301 return (0);
302
303 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
304 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
305 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
306 DELAY(5);
307 v = CSR_READ_4(sc, ALC_MDIO);
308 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
309 break;
310 }
311
312 if (i == 0) {
313 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg);
314 return (0);
315 }
316
317 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
318 }
319
320 static uint32_t
alc_mii_readreg_816x(struct alc_softc * sc,int phy,int reg)321 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg)
322 {
323 uint32_t clk, v;
324 int i;
325
326 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
327 clk = MDIO_CLK_25_128;
328 else
329 clk = MDIO_CLK_25_4;
330 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
331 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg));
332 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
333 DELAY(5);
334 v = CSR_READ_4(sc, ALC_MDIO);
335 if ((v & MDIO_OP_BUSY) == 0)
336 break;
337 }
338
339 if (i == 0) {
340 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg);
341 return (0);
342 }
343
344 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
345 }
346
347 static int
alc_miibus_writereg(device_t dev,int phy,int reg,int val)348 alc_miibus_writereg(device_t dev, int phy, int reg, int val)
349 {
350 struct alc_softc *sc;
351 int v;
352
353 sc = device_get_softc(dev);
354 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
355 v = alc_mii_writereg_816x(sc, phy, reg, val);
356 else
357 v = alc_mii_writereg_813x(sc, phy, reg, val);
358 return (v);
359 }
360
361 static uint32_t
alc_mii_writereg_813x(struct alc_softc * sc,int phy,int reg,int val)362 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val)
363 {
364 uint32_t v;
365 int i;
366
367 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
368 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
369 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
370 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
371 DELAY(5);
372 v = CSR_READ_4(sc, ALC_MDIO);
373 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
374 break;
375 }
376
377 if (i == 0)
378 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg);
379
380 return (0);
381 }
382
383 static uint32_t
alc_mii_writereg_816x(struct alc_softc * sc,int phy,int reg,int val)384 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val)
385 {
386 uint32_t clk, v;
387 int i;
388
389 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
390 clk = MDIO_CLK_25_128;
391 else
392 clk = MDIO_CLK_25_4;
393 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
394 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) |
395 MDIO_SUP_PREAMBLE | clk);
396 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
397 DELAY(5);
398 v = CSR_READ_4(sc, ALC_MDIO);
399 if ((v & MDIO_OP_BUSY) == 0)
400 break;
401 }
402
403 if (i == 0)
404 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg);
405
406 return (0);
407 }
408
409 static void
alc_miibus_statchg(device_t dev)410 alc_miibus_statchg(device_t dev)
411 {
412 struct alc_softc *sc;
413 struct mii_data *mii;
414 if_t ifp;
415 uint32_t reg;
416
417 sc = device_get_softc(dev);
418
419 mii = device_get_softc(sc->alc_miibus);
420 ifp = sc->alc_ifp;
421 if (mii == NULL || ifp == NULL ||
422 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
423 return;
424
425 sc->alc_flags &= ~ALC_FLAG_LINK;
426 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
427 (IFM_ACTIVE | IFM_AVALID)) {
428 switch (IFM_SUBTYPE(mii->mii_media_active)) {
429 case IFM_10_T:
430 case IFM_100_TX:
431 sc->alc_flags |= ALC_FLAG_LINK;
432 break;
433 case IFM_1000_T:
434 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
435 sc->alc_flags |= ALC_FLAG_LINK;
436 break;
437 default:
438 break;
439 }
440 }
441 /* Stop Rx/Tx MACs. */
442 alc_stop_mac(sc);
443
444 /* Program MACs with resolved speed/duplex/flow-control. */
445 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
446 alc_start_queue(sc);
447 alc_mac_config(sc);
448 /* Re-enable Tx/Rx MACs. */
449 reg = CSR_READ_4(sc, ALC_MAC_CFG);
450 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
451 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
452 }
453 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active));
454 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active));
455 }
456
457 static uint32_t
alc_miidbg_readreg(struct alc_softc * sc,int reg)458 alc_miidbg_readreg(struct alc_softc *sc, int reg)
459 {
460
461 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
462 reg);
463 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
464 ALC_MII_DBG_DATA));
465 }
466
467 static uint32_t
alc_miidbg_writereg(struct alc_softc * sc,int reg,int val)468 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val)
469 {
470
471 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
472 reg);
473 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
474 ALC_MII_DBG_DATA, val));
475 }
476
477 static uint32_t
alc_miiext_readreg(struct alc_softc * sc,int devaddr,int reg)478 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg)
479 {
480 uint32_t clk, v;
481 int i;
482
483 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |
484 EXT_MDIO_DEVADDR(devaddr));
485 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
486 clk = MDIO_CLK_25_128;
487 else
488 clk = MDIO_CLK_25_4;
489 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
490 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT);
491 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
492 DELAY(5);
493 v = CSR_READ_4(sc, ALC_MDIO);
494 if ((v & MDIO_OP_BUSY) == 0)
495 break;
496 }
497
498 if (i == 0) {
499 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n",
500 devaddr, reg);
501 return (0);
502 }
503
504 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
505 }
506
507 static uint32_t
alc_miiext_writereg(struct alc_softc * sc,int devaddr,int reg,int val)508 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val)
509 {
510 uint32_t clk, v;
511 int i;
512
513 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |
514 EXT_MDIO_DEVADDR(devaddr));
515 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
516 clk = MDIO_CLK_25_128;
517 else
518 clk = MDIO_CLK_25_4;
519 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
520 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) |
521 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT);
522 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
523 DELAY(5);
524 v = CSR_READ_4(sc, ALC_MDIO);
525 if ((v & MDIO_OP_BUSY) == 0)
526 break;
527 }
528
529 if (i == 0)
530 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n",
531 devaddr, reg);
532
533 return (0);
534 }
535
536 static void
alc_dsp_fixup(struct alc_softc * sc,int media)537 alc_dsp_fixup(struct alc_softc *sc, int media)
538 {
539 uint16_t agc, len, val;
540
541 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
542 return;
543 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0)
544 return;
545
546 /*
547 * Vendor PHY magic.
548 * 1000BT/AZ, wrong cable length
549 */
550 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
551 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6);
552 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) &
553 EXT_CLDCTL6_CAB_LEN_MASK;
554 agc = alc_miidbg_readreg(sc, MII_DBG_AGC);
555 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK;
556 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G &&
557 agc > DBG_AGC_LONG1G_LIMT) ||
558 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT &&
559 agc > DBG_AGC_LONG1G_LIMT)) {
560 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT,
561 DBG_AZ_ANADECT_LONG);
562 val = alc_miiext_readreg(sc, MII_EXT_ANEG,
563 MII_EXT_ANEG_AFE);
564 val |= ANEG_AFEE_10BT_100M_TH;
565 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE,
566 val);
567 } else {
568 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT,
569 DBG_AZ_ANADECT_DEFAULT);
570 val = alc_miiext_readreg(sc, MII_EXT_ANEG,
571 MII_EXT_ANEG_AFE);
572 val &= ~ANEG_AFEE_10BT_100M_TH;
573 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE,
574 val);
575 }
576 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 &&
577 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) {
578 if (media == IFM_1000_T) {
579 /*
580 * Giga link threshold, raise the tolerance of
581 * noise 50%.
582 */
583 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB);
584 val &= ~DBG_MSE20DB_TH_MASK;
585 val |= (DBG_MSE20DB_TH_HI <<
586 DBG_MSE20DB_TH_SHIFT);
587 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val);
588 } else if (media == IFM_100_TX)
589 alc_miidbg_writereg(sc, MII_DBG_MSE16DB,
590 DBG_MSE16DB_UP);
591 }
592 } else {
593 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE);
594 val &= ~ANEG_AFEE_10BT_100M_TH;
595 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val);
596 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 &&
597 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) {
598 alc_miidbg_writereg(sc, MII_DBG_MSE16DB,
599 DBG_MSE16DB_DOWN);
600 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB);
601 val &= ~DBG_MSE20DB_TH_MASK;
602 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT);
603 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val);
604 }
605 }
606 }
607
608 static void
alc_mediastatus(if_t ifp,struct ifmediareq * ifmr)609 alc_mediastatus(if_t ifp, struct ifmediareq *ifmr)
610 {
611 struct alc_softc *sc;
612 struct mii_data *mii;
613
614 sc = if_getsoftc(ifp);
615 ALC_LOCK(sc);
616 if ((if_getflags(ifp) & IFF_UP) == 0) {
617 ALC_UNLOCK(sc);
618 return;
619 }
620 mii = device_get_softc(sc->alc_miibus);
621
622 mii_pollstat(mii);
623 ifmr->ifm_status = mii->mii_media_status;
624 ifmr->ifm_active = mii->mii_media_active;
625 ALC_UNLOCK(sc);
626 }
627
628 static int
alc_mediachange(if_t ifp)629 alc_mediachange(if_t ifp)
630 {
631 struct alc_softc *sc;
632 int error;
633
634 sc = if_getsoftc(ifp);
635 ALC_LOCK(sc);
636 error = alc_mediachange_locked(sc);
637 ALC_UNLOCK(sc);
638
639 return (error);
640 }
641
642 static int
alc_mediachange_locked(struct alc_softc * sc)643 alc_mediachange_locked(struct alc_softc *sc)
644 {
645 struct mii_data *mii;
646 struct mii_softc *miisc;
647 int error;
648
649 ALC_LOCK_ASSERT(sc);
650
651 mii = device_get_softc(sc->alc_miibus);
652 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
653 PHY_RESET(miisc);
654 error = mii_mediachg(mii);
655
656 return (error);
657 }
658
659 static struct alc_ident *
alc_find_ident(device_t dev)660 alc_find_ident(device_t dev)
661 {
662 struct alc_ident *ident;
663 uint16_t vendor, devid;
664
665 vendor = pci_get_vendor(dev);
666 devid = pci_get_device(dev);
667 for (ident = alc_ident_table; ident->name != NULL; ident++) {
668 if (vendor == ident->vendorid && devid == ident->deviceid)
669 return (ident);
670 }
671
672 return (NULL);
673 }
674
675 static int
alc_probe(device_t dev)676 alc_probe(device_t dev)
677 {
678 struct alc_ident *ident;
679
680 ident = alc_find_ident(dev);
681 if (ident != NULL) {
682 device_set_desc(dev, ident->name);
683 return (BUS_PROBE_DEFAULT);
684 }
685
686 return (ENXIO);
687 }
688
689 static void
alc_get_macaddr(struct alc_softc * sc)690 alc_get_macaddr(struct alc_softc *sc)
691 {
692
693 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
694 alc_get_macaddr_816x(sc);
695 else
696 alc_get_macaddr_813x(sc);
697 }
698
699 static void
alc_get_macaddr_813x(struct alc_softc * sc)700 alc_get_macaddr_813x(struct alc_softc *sc)
701 {
702 uint32_t opt;
703 uint16_t val;
704 int eeprom, i;
705
706 eeprom = 0;
707 opt = CSR_READ_4(sc, ALC_OPT_CFG);
708 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&
709 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
710 /*
711 * EEPROM found, let TWSI reload EEPROM configuration.
712 * This will set ethernet address of controller.
713 */
714 eeprom++;
715 switch (sc->alc_ident->deviceid) {
716 case DEVICEID_ATHEROS_AR8131:
717 case DEVICEID_ATHEROS_AR8132:
718 if ((opt & OPT_CFG_CLK_ENB) == 0) {
719 opt |= OPT_CFG_CLK_ENB;
720 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
721 CSR_READ_4(sc, ALC_OPT_CFG);
722 DELAY(1000);
723 }
724 break;
725 case DEVICEID_ATHEROS_AR8151:
726 case DEVICEID_ATHEROS_AR8151_V2:
727 case DEVICEID_ATHEROS_AR8152_B:
728 case DEVICEID_ATHEROS_AR8152_B2:
729 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
730 ALC_MII_DBG_ADDR, 0x00);
731 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
732 ALC_MII_DBG_DATA);
733 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
734 ALC_MII_DBG_DATA, val & 0xFF7F);
735 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
736 ALC_MII_DBG_ADDR, 0x3B);
737 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
738 ALC_MII_DBG_DATA);
739 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
740 ALC_MII_DBG_DATA, val | 0x0008);
741 DELAY(20);
742 break;
743 }
744
745 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
746 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
747 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
748 CSR_READ_4(sc, ALC_WOL_CFG);
749
750 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
751 TWSI_CFG_SW_LD_START);
752 for (i = 100; i > 0; i--) {
753 DELAY(1000);
754 if ((CSR_READ_4(sc, ALC_TWSI_CFG) &
755 TWSI_CFG_SW_LD_START) == 0)
756 break;
757 }
758 if (i == 0)
759 device_printf(sc->alc_dev,
760 "reloading EEPROM timeout!\n");
761 } else {
762 if (bootverbose)
763 device_printf(sc->alc_dev, "EEPROM not found!\n");
764 }
765 if (eeprom != 0) {
766 switch (sc->alc_ident->deviceid) {
767 case DEVICEID_ATHEROS_AR8131:
768 case DEVICEID_ATHEROS_AR8132:
769 if ((opt & OPT_CFG_CLK_ENB) != 0) {
770 opt &= ~OPT_CFG_CLK_ENB;
771 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
772 CSR_READ_4(sc, ALC_OPT_CFG);
773 DELAY(1000);
774 }
775 break;
776 case DEVICEID_ATHEROS_AR8151:
777 case DEVICEID_ATHEROS_AR8151_V2:
778 case DEVICEID_ATHEROS_AR8152_B:
779 case DEVICEID_ATHEROS_AR8152_B2:
780 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
781 ALC_MII_DBG_ADDR, 0x00);
782 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
783 ALC_MII_DBG_DATA);
784 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
785 ALC_MII_DBG_DATA, val | 0x0080);
786 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
787 ALC_MII_DBG_ADDR, 0x3B);
788 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
789 ALC_MII_DBG_DATA);
790 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
791 ALC_MII_DBG_DATA, val & 0xFFF7);
792 DELAY(20);
793 break;
794 }
795 }
796
797 alc_get_macaddr_par(sc);
798 }
799
800 static void
alc_get_macaddr_816x(struct alc_softc * sc)801 alc_get_macaddr_816x(struct alc_softc *sc)
802 {
803 uint32_t reg;
804 int i, reloaded;
805
806 reloaded = 0;
807 /* Try to reload station address via TWSI. */
808 for (i = 100; i > 0; i--) {
809 reg = CSR_READ_4(sc, ALC_SLD);
810 if ((reg & (SLD_PROGRESS | SLD_START)) == 0)
811 break;
812 DELAY(1000);
813 }
814 if (i != 0) {
815 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START);
816 for (i = 100; i > 0; i--) {
817 DELAY(1000);
818 reg = CSR_READ_4(sc, ALC_SLD);
819 if ((reg & SLD_START) == 0)
820 break;
821 }
822 if (i != 0)
823 reloaded++;
824 else if (bootverbose)
825 device_printf(sc->alc_dev,
826 "reloading station address via TWSI timed out!\n");
827 }
828
829 /* Try to reload station address from EEPROM or FLASH. */
830 if (reloaded == 0) {
831 reg = CSR_READ_4(sc, ALC_EEPROM_LD);
832 if ((reg & (EEPROM_LD_EEPROM_EXIST |
833 EEPROM_LD_FLASH_EXIST)) != 0) {
834 for (i = 100; i > 0; i--) {
835 reg = CSR_READ_4(sc, ALC_EEPROM_LD);
836 if ((reg & (EEPROM_LD_PROGRESS |
837 EEPROM_LD_START)) == 0)
838 break;
839 DELAY(1000);
840 }
841 if (i != 0) {
842 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg |
843 EEPROM_LD_START);
844 for (i = 100; i > 0; i--) {
845 DELAY(1000);
846 reg = CSR_READ_4(sc, ALC_EEPROM_LD);
847 if ((reg & EEPROM_LD_START) == 0)
848 break;
849 }
850 } else if (bootverbose)
851 device_printf(sc->alc_dev,
852 "reloading EEPROM/FLASH timed out!\n");
853 }
854 }
855
856 alc_get_macaddr_par(sc);
857 }
858
859 static void
alc_get_macaddr_par(struct alc_softc * sc)860 alc_get_macaddr_par(struct alc_softc *sc)
861 {
862 uint32_t ea[2];
863
864 ea[0] = CSR_READ_4(sc, ALC_PAR0);
865 ea[1] = CSR_READ_4(sc, ALC_PAR1);
866 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF;
867 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF;
868 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF;
869 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF;
870 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF;
871 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF;
872 }
873
874 static void
alc_disable_l0s_l1(struct alc_softc * sc)875 alc_disable_l0s_l1(struct alc_softc *sc)
876 {
877 uint32_t pmcfg;
878
879 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
880 /* Another magic from vendor. */
881 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
882 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 |
883 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB |
884 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1);
885 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB |
886 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB;
887 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
888 }
889 }
890
891 static void
alc_phy_reset(struct alc_softc * sc)892 alc_phy_reset(struct alc_softc *sc)
893 {
894
895 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
896 alc_phy_reset_816x(sc);
897 else
898 alc_phy_reset_813x(sc);
899 }
900
901 static void
alc_phy_reset_813x(struct alc_softc * sc)902 alc_phy_reset_813x(struct alc_softc *sc)
903 {
904 uint16_t data;
905
906 /* Reset magic from Linux. */
907 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET);
908 CSR_READ_2(sc, ALC_GPHY_CFG);
909 DELAY(10 * 1000);
910
911 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |
912 GPHY_CFG_SEL_ANA_RESET);
913 CSR_READ_2(sc, ALC_GPHY_CFG);
914 DELAY(10 * 1000);
915
916 /* DSP fixup, Vendor magic. */
917 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) {
918 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
919 ALC_MII_DBG_ADDR, 0x000A);
920 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
921 ALC_MII_DBG_DATA);
922 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
923 ALC_MII_DBG_DATA, data & 0xDFFF);
924 }
925 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
926 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
927 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
928 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
929 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
930 ALC_MII_DBG_ADDR, 0x003B);
931 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
932 ALC_MII_DBG_DATA);
933 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
934 ALC_MII_DBG_DATA, data & 0xFFF7);
935 DELAY(20 * 1000);
936 }
937 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) {
938 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
939 ALC_MII_DBG_ADDR, 0x0029);
940 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
941 ALC_MII_DBG_DATA, 0x929D);
942 }
943 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 ||
944 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 ||
945 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
946 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
947 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
948 ALC_MII_DBG_ADDR, 0x0029);
949 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
950 ALC_MII_DBG_DATA, 0xB6DD);
951 }
952
953 /* Load DSP codes, vendor magic. */
954 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
955 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK);
956 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
957 ALC_MII_DBG_ADDR, MII_ANA_CFG18);
958 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
959 ALC_MII_DBG_DATA, data);
960
961 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) |
962 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL |
963 ANA_SERDES_EN_LCKDT;
964 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
965 ALC_MII_DBG_ADDR, MII_ANA_CFG5);
966 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
967 ALC_MII_DBG_DATA, data);
968
969 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) &
970 ANA_LONG_CABLE_TH_100_MASK) |
971 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) &
972 ANA_SHORT_CABLE_TH_100_SHIFT) |
973 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW;
974 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
975 ALC_MII_DBG_ADDR, MII_ANA_CFG54);
976 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
977 ALC_MII_DBG_DATA, data);
978
979 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) |
980 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) |
981 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) |
982 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK);
983 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
984 ALC_MII_DBG_ADDR, MII_ANA_CFG4);
985 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
986 ALC_MII_DBG_DATA, data);
987
988 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) |
989 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB |
990 ANA_OEN_125M;
991 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
992 ALC_MII_DBG_ADDR, MII_ANA_CFG0);
993 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
994 ALC_MII_DBG_DATA, data);
995 DELAY(1000);
996
997 /* Disable hibernation. */
998 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
999 0x0029);
1000 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
1001 ALC_MII_DBG_DATA);
1002 data &= ~0x8000;
1003 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA,
1004 data);
1005
1006 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
1007 0x000B);
1008 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
1009 ALC_MII_DBG_DATA);
1010 data &= ~0x8000;
1011 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA,
1012 data);
1013 }
1014
1015 static void
alc_phy_reset_816x(struct alc_softc * sc)1016 alc_phy_reset_816x(struct alc_softc *sc)
1017 {
1018 uint32_t val;
1019
1020 val = CSR_READ_4(sc, ALC_GPHY_CFG);
1021 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE |
1022 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON |
1023 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB);
1024 val |= GPHY_CFG_SEL_ANA_RESET;
1025 #ifdef notyet
1026 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET;
1027 #else
1028 /* Disable PHY hibernation. */
1029 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN);
1030 #endif
1031 CSR_WRITE_4(sc, ALC_GPHY_CFG, val);
1032 DELAY(10);
1033 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET);
1034 DELAY(800);
1035
1036 /* Vendor PHY magic. */
1037 #ifdef notyet
1038 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT);
1039 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT);
1040 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS,
1041 EXT_VDRVBIAS_DEFAULT);
1042 #else
1043 /* Disable PHY hibernation. */
1044 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS,
1045 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB);
1046 alc_miidbg_writereg(sc, MII_DBG_HIBNEG,
1047 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE));
1048 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT);
1049 #endif
1050
1051 /* XXX Disable EEE. */
1052 val = CSR_READ_4(sc, ALC_LPI_CTL);
1053 val &= ~LPI_CTL_ENB;
1054 CSR_WRITE_4(sc, ALC_LPI_CTL, val);
1055 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0);
1056
1057 /* PHY power saving. */
1058 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT);
1059 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT);
1060 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT);
1061 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT);
1062 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2);
1063 val &= ~DBG_GREENCFG2_GATE_DFSE_EN;
1064 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val);
1065
1066 /* RTL8139C, 120m issue. */
1067 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78,
1068 ANEG_NLP78_120M_DEFAULT);
1069 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10,
1070 ANEG_S3DIG10_DEFAULT);
1071
1072 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) {
1073 /* Turn off half amplitude. */
1074 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3);
1075 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT;
1076 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val);
1077 /* Turn off Green feature. */
1078 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2);
1079 val |= DBG_GREENCFG2_BP_GREEN;
1080 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val);
1081 /* Turn off half bias. */
1082 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5);
1083 val |= EXT_CLDCTL5_BP_VD_HLFBIAS;
1084 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val);
1085 }
1086 }
1087
1088 static void
alc_phy_down(struct alc_softc * sc)1089 alc_phy_down(struct alc_softc *sc)
1090 {
1091 uint32_t gphy;
1092
1093 switch (sc->alc_ident->deviceid) {
1094 case DEVICEID_ATHEROS_AR8161:
1095 case DEVICEID_ATHEROS_E2200:
1096 case DEVICEID_ATHEROS_E2400:
1097 case DEVICEID_ATHEROS_E2500:
1098 case DEVICEID_ATHEROS_AR8162:
1099 case DEVICEID_ATHEROS_AR8171:
1100 case DEVICEID_ATHEROS_AR8172:
1101 gphy = CSR_READ_4(sc, ALC_GPHY_CFG);
1102 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE |
1103 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON);
1104 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
1105 GPHY_CFG_SEL_ANA_RESET;
1106 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW;
1107 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy);
1108 break;
1109 case DEVICEID_ATHEROS_AR8151:
1110 case DEVICEID_ATHEROS_AR8151_V2:
1111 case DEVICEID_ATHEROS_AR8152_B:
1112 case DEVICEID_ATHEROS_AR8152_B2:
1113 /*
1114 * GPHY power down caused more problems on AR8151 v2.0.
1115 * When driver is reloaded after GPHY power down,
1116 * accesses to PHY/MAC registers hung the system. Only
1117 * cold boot recovered from it. I'm not sure whether
1118 * AR8151 v1.0 also requires this one though. I don't
1119 * have AR8151 v1.0 controller in hand.
1120 * The only option left is to isolate the PHY and
1121 * initiates power down the PHY which in turn saves
1122 * more power when driver is unloaded.
1123 */
1124 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
1125 MII_BMCR, BMCR_ISO | BMCR_PDOWN);
1126 break;
1127 default:
1128 /* Force PHY down. */
1129 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |
1130 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ |
1131 GPHY_CFG_PWDOWN_HW);
1132 DELAY(1000);
1133 break;
1134 }
1135 }
1136
1137 static void
alc_aspm(struct alc_softc * sc,int init,int media)1138 alc_aspm(struct alc_softc *sc, int init, int media)
1139 {
1140
1141 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
1142 alc_aspm_816x(sc, init);
1143 else
1144 alc_aspm_813x(sc, media);
1145 }
1146
1147 static void
alc_aspm_813x(struct alc_softc * sc,int media)1148 alc_aspm_813x(struct alc_softc *sc, int media)
1149 {
1150 uint32_t pmcfg;
1151 uint16_t linkcfg;
1152
1153 if ((sc->alc_flags & ALC_FLAG_LINK) == 0)
1154 return;
1155
1156 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
1157 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) ==
1158 (ALC_FLAG_APS | ALC_FLAG_PCIE))
1159 linkcfg = CSR_READ_2(sc, sc->alc_expcap +
1160 PCIER_LINK_CTL);
1161 else
1162 linkcfg = 0;
1163 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1;
1164 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK);
1165 pmcfg |= PM_CFG_MAC_ASPM_CHK;
1166 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT);
1167 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
1168
1169 if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
1170 /* Disable extended sync except AR8152 B v1.0 */
1171 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC;
1172 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B &&
1173 sc->alc_rev == ATHEROS_AR8152_B_V10)
1174 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC;
1175 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL,
1176 linkcfg);
1177 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB |
1178 PM_CFG_HOTRST);
1179 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT <<
1180 PM_CFG_L1_ENTRY_TIMER_SHIFT);
1181 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
1182 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT <<
1183 PM_CFG_PM_REQ_TIMER_SHIFT);
1184 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV;
1185 }
1186
1187 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
1188 if ((sc->alc_flags & ALC_FLAG_L0S) != 0)
1189 pmcfg |= PM_CFG_ASPM_L0S_ENB;
1190 if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
1191 pmcfg |= PM_CFG_ASPM_L1_ENB;
1192 if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
1193 if (sc->alc_ident->deviceid ==
1194 DEVICEID_ATHEROS_AR8152_B)
1195 pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
1196 pmcfg &= ~(PM_CFG_SERDES_L1_ENB |
1197 PM_CFG_SERDES_PLL_L1_ENB |
1198 PM_CFG_SERDES_BUDS_RX_L1_ENB);
1199 pmcfg |= PM_CFG_CLK_SWH_L1;
1200 if (media == IFM_100_TX || media == IFM_1000_T) {
1201 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
1202 switch (sc->alc_ident->deviceid) {
1203 case DEVICEID_ATHEROS_AR8152_B:
1204 pmcfg |= (7 <<
1205 PM_CFG_L1_ENTRY_TIMER_SHIFT);
1206 break;
1207 case DEVICEID_ATHEROS_AR8152_B2:
1208 case DEVICEID_ATHEROS_AR8151_V2:
1209 pmcfg |= (4 <<
1210 PM_CFG_L1_ENTRY_TIMER_SHIFT);
1211 break;
1212 default:
1213 pmcfg |= (15 <<
1214 PM_CFG_L1_ENTRY_TIMER_SHIFT);
1215 break;
1216 }
1217 }
1218 } else {
1219 pmcfg |= PM_CFG_SERDES_L1_ENB |
1220 PM_CFG_SERDES_PLL_L1_ENB |
1221 PM_CFG_SERDES_BUDS_RX_L1_ENB;
1222 pmcfg &= ~(PM_CFG_CLK_SWH_L1 |
1223 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
1224 }
1225 } else {
1226 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB |
1227 PM_CFG_SERDES_PLL_L1_ENB);
1228 pmcfg |= PM_CFG_CLK_SWH_L1;
1229 if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
1230 pmcfg |= PM_CFG_ASPM_L1_ENB;
1231 }
1232 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
1233 }
1234
1235 static void
alc_aspm_816x(struct alc_softc * sc,int init)1236 alc_aspm_816x(struct alc_softc *sc, int init)
1237 {
1238 uint32_t pmcfg;
1239
1240 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
1241 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK;
1242 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT;
1243 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
1244 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT;
1245 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK;
1246 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT;
1247 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV;
1248 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S |
1249 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB |
1250 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB |
1251 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB |
1252 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST);
1253 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
1254 (sc->alc_rev & 0x01) != 0)
1255 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB;
1256 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
1257 /* Link up, enable both L0s, L1s. */
1258 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB |
1259 PM_CFG_MAC_ASPM_CHK;
1260 } else {
1261 if (init != 0)
1262 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB |
1263 PM_CFG_MAC_ASPM_CHK;
1264 else if ((if_getdrvflags(sc->alc_ifp) & IFF_DRV_RUNNING) != 0)
1265 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK;
1266 }
1267 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
1268 }
1269
1270 static void
alc_init_pcie(struct alc_softc * sc)1271 alc_init_pcie(struct alc_softc *sc)
1272 {
1273 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" };
1274 uint32_t cap, ctl, val;
1275 int state;
1276
1277 /* Clear data link and flow-control protocol error. */
1278 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
1279 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP);
1280 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
1281
1282 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
1283 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
1284 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
1285 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC,
1286 CSR_READ_4(sc, ALC_PCIE_PHYMISC) |
1287 PCIE_PHYMISC_FORCE_RCV_DET);
1288 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B &&
1289 sc->alc_rev == ATHEROS_AR8152_B_V10) {
1290 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);
1291 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK |
1292 PCIE_PHYMISC2_SERDES_TH_MASK);
1293 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT;
1294 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
1295 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val);
1296 }
1297 /* Disable ASPM L0S and L1. */
1298 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP);
1299 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
1300 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL);
1301 if ((ctl & PCIEM_LINK_CTL_RCB) != 0)
1302 sc->alc_rcb = DMA_CFG_RCB_128;
1303 if (bootverbose)
1304 device_printf(sc->alc_dev, "RCB %u bytes\n",
1305 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128);
1306 state = ctl & PCIEM_LINK_CTL_ASPMC;
1307 if (state & PCIEM_LINK_CTL_ASPMC_L0S)
1308 sc->alc_flags |= ALC_FLAG_L0S;
1309 if (state & PCIEM_LINK_CTL_ASPMC_L1)
1310 sc->alc_flags |= ALC_FLAG_L1S;
1311 if (bootverbose)
1312 device_printf(sc->alc_dev, "ASPM %s %s\n",
1313 aspm_state[state],
1314 state == 0 ? "disabled" : "enabled");
1315 alc_disable_l0s_l1(sc);
1316 } else {
1317 if (bootverbose)
1318 device_printf(sc->alc_dev,
1319 "no ASPM support\n");
1320 }
1321 } else {
1322 val = CSR_READ_4(sc, ALC_PDLL_TRNS1);
1323 val &= ~PDLL_TRNS1_D3PLLOFF_ENB;
1324 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val);
1325 val = CSR_READ_4(sc, ALC_MASTER_CFG);
1326 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
1327 (sc->alc_rev & 0x01) != 0) {
1328 if ((val & MASTER_WAKEN_25M) == 0 ||
1329 (val & MASTER_CLK_SEL_DIS) == 0) {
1330 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS;
1331 CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
1332 }
1333 } else {
1334 if ((val & MASTER_WAKEN_25M) == 0 ||
1335 (val & MASTER_CLK_SEL_DIS) != 0) {
1336 val |= MASTER_WAKEN_25M;
1337 val &= ~MASTER_CLK_SEL_DIS;
1338 CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
1339 }
1340 }
1341 }
1342 alc_aspm(sc, 1, IFM_UNKNOWN);
1343 }
1344
1345 static void
alc_config_msi(struct alc_softc * sc)1346 alc_config_msi(struct alc_softc *sc)
1347 {
1348 uint32_t ctl, mod;
1349
1350 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
1351 /*
1352 * It seems interrupt moderation is controlled by
1353 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active.
1354 * Driver uses RX interrupt moderation parameter to
1355 * program ALC_MSI_RETRANS_TIMER register.
1356 */
1357 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER);
1358 ctl &= ~MSI_RETRANS_TIMER_MASK;
1359 ctl &= ~MSI_RETRANS_MASK_SEL_LINE;
1360 mod = ALC_USECS(sc->alc_int_rx_mod);
1361 if (mod == 0)
1362 mod = 1;
1363 ctl |= mod;
1364 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
1365 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl |
1366 MSI_RETRANS_MASK_SEL_STD);
1367 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
1368 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl |
1369 MSI_RETRANS_MASK_SEL_LINE);
1370 else
1371 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0);
1372 }
1373 }
1374
1375 static int
alc_attach(device_t dev)1376 alc_attach(device_t dev)
1377 {
1378 struct alc_softc *sc;
1379 if_t ifp;
1380 int base, error, i, msic, msixc;
1381 uint16_t burst;
1382
1383 error = 0;
1384 sc = device_get_softc(dev);
1385 sc->alc_dev = dev;
1386 sc->alc_rev = pci_get_revid(dev);
1387
1388 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1389 MTX_DEF);
1390 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0);
1391 NET_TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc);
1392 sc->alc_ident = alc_find_ident(dev);
1393
1394 /* Map the device. */
1395 pci_enable_busmaster(dev);
1396 sc->alc_res_spec = alc_res_spec_mem;
1397 sc->alc_irq_spec = alc_irq_spec_legacy;
1398 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res);
1399 if (error != 0) {
1400 device_printf(dev, "cannot allocate memory resources.\n");
1401 goto fail;
1402 }
1403
1404 /* Set PHY address. */
1405 sc->alc_phyaddr = ALC_PHY_ADDR;
1406
1407 /*
1408 * One odd thing is AR8132 uses the same PHY hardware(F1
1409 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports
1410 * the PHY supports 1000Mbps but that's not true. The PHY
1411 * used in AR8132 can't establish gigabit link even if it
1412 * shows the same PHY model/revision number of AR8131.
1413 */
1414 switch (sc->alc_ident->deviceid) {
1415 case DEVICEID_ATHEROS_E2200:
1416 case DEVICEID_ATHEROS_E2400:
1417 case DEVICEID_ATHEROS_E2500:
1418 sc->alc_flags |= ALC_FLAG_E2X00;
1419
1420 /*
1421 * Disable MSI-X by default on Killer devices, since this is
1422 * reported by several users to not work well.
1423 */
1424 if (msix_disable == 2)
1425 msix_disable = 1;
1426
1427 /* FALLTHROUGH */
1428 case DEVICEID_ATHEROS_AR8161:
1429 if (pci_get_subvendor(dev) == VENDORID_ATHEROS &&
1430 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0)
1431 sc->alc_flags |= ALC_FLAG_LINK_WAR;
1432 /* FALLTHROUGH */
1433 case DEVICEID_ATHEROS_AR8171:
1434 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY;
1435 break;
1436 case DEVICEID_ATHEROS_AR8162:
1437 case DEVICEID_ATHEROS_AR8172:
1438 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY;
1439 break;
1440 case DEVICEID_ATHEROS_AR8152_B:
1441 case DEVICEID_ATHEROS_AR8152_B2:
1442 sc->alc_flags |= ALC_FLAG_APS;
1443 /* FALLTHROUGH */
1444 case DEVICEID_ATHEROS_AR8132:
1445 sc->alc_flags |= ALC_FLAG_FASTETHER;
1446 break;
1447 case DEVICEID_ATHEROS_AR8151:
1448 case DEVICEID_ATHEROS_AR8151_V2:
1449 sc->alc_flags |= ALC_FLAG_APS;
1450 if (CSR_READ_4(sc, ALC_MT_MAGIC) == MT_MAGIC)
1451 sc->alc_flags |= ALC_FLAG_MT;
1452 /* FALLTHROUGH */
1453 default:
1454 break;
1455 }
1456
1457 /*
1458 * The default value of msix_disable is 2, which means auto-detect. If
1459 * we didn't auto-detect it, default to enabling it.
1460 */
1461 if (msix_disable == 2)
1462 msix_disable = 0;
1463
1464 sc->alc_flags |= ALC_FLAG_JUMBO;
1465
1466 /*
1467 * It seems that AR813x/AR815x has silicon bug for SMB. In
1468 * addition, Atheros said that enabling SMB wouldn't improve
1469 * performance. However I think it's bad to access lots of
1470 * registers to extract MAC statistics.
1471 */
1472 sc->alc_flags |= ALC_FLAG_SMB_BUG;
1473 /*
1474 * Don't use Tx CMB. It is known to have silicon bug.
1475 */
1476 sc->alc_flags |= ALC_FLAG_CMB_BUG;
1477 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >>
1478 MASTER_CHIP_REV_SHIFT;
1479 if (bootverbose) {
1480 device_printf(dev, "PCI device revision : 0x%04x\n",
1481 sc->alc_rev);
1482 device_printf(dev, "Chip id/revision : 0x%04x\n",
1483 sc->alc_chip_rev);
1484 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
1485 device_printf(dev, "AR816x revision : 0x%x\n",
1486 AR816X_REV(sc->alc_rev));
1487 }
1488 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n",
1489 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8,
1490 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8);
1491
1492 /* Initialize DMA parameters. */
1493 sc->alc_dma_rd_burst = 0;
1494 sc->alc_dma_wr_burst = 0;
1495 sc->alc_rcb = DMA_CFG_RCB_64;
1496 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) {
1497 sc->alc_flags |= ALC_FLAG_PCIE;
1498 sc->alc_expcap = base;
1499 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL);
1500 sc->alc_dma_rd_burst =
1501 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12;
1502 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5;
1503 if (bootverbose) {
1504 device_printf(dev, "Read request size : %u bytes.\n",
1505 alc_dma_burst[sc->alc_dma_rd_burst]);
1506 device_printf(dev, "TLP payload size : %u bytes.\n",
1507 alc_dma_burst[sc->alc_dma_wr_burst]);
1508 }
1509 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024)
1510 sc->alc_dma_rd_burst = 3;
1511 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024)
1512 sc->alc_dma_wr_burst = 3;
1513 /*
1514 * Force maximum payload size to 128 bytes for
1515 * E2200/E2400/E2500/AR8162/AR8171/AR8172.
1516 * Otherwise it triggers DMA write error.
1517 */
1518 if ((sc->alc_flags &
1519 (ALC_FLAG_E2X00 | ALC_FLAG_AR816X_FAMILY)) != 0)
1520 sc->alc_dma_wr_burst = 0;
1521 alc_init_pcie(sc);
1522 }
1523
1524 /* Reset PHY. */
1525 alc_phy_reset(sc);
1526
1527 /* Reset the ethernet controller. */
1528 alc_stop_mac(sc);
1529 alc_reset(sc);
1530
1531 /* Allocate IRQ resources. */
1532 msixc = pci_msix_count(dev);
1533 msic = pci_msi_count(dev);
1534 if (bootverbose) {
1535 device_printf(dev, "MSIX count : %d\n", msixc);
1536 device_printf(dev, "MSI count : %d\n", msic);
1537 }
1538 if (msixc > 1)
1539 msixc = 1;
1540 if (msic > 1)
1541 msic = 1;
1542 /*
1543 * Prefer MSIX over MSI.
1544 * AR816x controller has a silicon bug that MSI interrupt
1545 * does not assert if PCIM_CMD_INTxDIS bit of command
1546 * register is set. pci(4) was taught to handle that case.
1547 */
1548 if (msix_disable == 0 || msi_disable == 0) {
1549 if (msix_disable == 0 && msixc > 0 &&
1550 pci_alloc_msix(dev, &msixc) == 0) {
1551 if (msic == 1) {
1552 device_printf(dev,
1553 "Using %d MSIX message(s).\n", msixc);
1554 sc->alc_flags |= ALC_FLAG_MSIX;
1555 sc->alc_irq_spec = alc_irq_spec_msix;
1556 } else
1557 pci_release_msi(dev);
1558 }
1559 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 &&
1560 msic > 0 && pci_alloc_msi(dev, &msic) == 0) {
1561 if (msic == 1) {
1562 device_printf(dev,
1563 "Using %d MSI message(s).\n", msic);
1564 sc->alc_flags |= ALC_FLAG_MSI;
1565 sc->alc_irq_spec = alc_irq_spec_msi;
1566 } else
1567 pci_release_msi(dev);
1568 }
1569 }
1570
1571 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq);
1572 if (error != 0) {
1573 device_printf(dev, "cannot allocate IRQ resources.\n");
1574 goto fail;
1575 }
1576
1577 /* Create device sysctl node. */
1578 alc_sysctl_node(sc);
1579
1580 if ((error = alc_dma_alloc(sc)) != 0)
1581 goto fail;
1582
1583 /* Load station address. */
1584 alc_get_macaddr(sc);
1585
1586 ifp = sc->alc_ifp = if_alloc(IFT_ETHER);
1587 if_setsoftc(ifp, sc);
1588 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1589 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1590 if_setioctlfn(ifp, alc_ioctl);
1591 if_setstartfn(ifp, alc_start);
1592 if_setinitfn(ifp, alc_init);
1593 if_setsendqlen(ifp, ALC_TX_RING_CNT - 1);
1594 if_setsendqready(ifp);
1595 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_TSO4);
1596 if_sethwassist(ifp, ALC_CSUM_FEATURES | CSUM_TSO);
1597 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) {
1598 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0);
1599 sc->alc_flags |= ALC_FLAG_PM;
1600 sc->alc_pmcap = base;
1601 }
1602 if_setcapenable(ifp, if_getcapabilities(ifp));
1603
1604 /* Set up MII bus. */
1605 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange,
1606 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY,
1607 MIIF_DOPAUSE);
1608 if (error != 0) {
1609 device_printf(dev, "attaching PHYs failed\n");
1610 goto fail;
1611 }
1612
1613 ether_ifattach(ifp, sc->alc_eaddr);
1614
1615 /* VLAN capability setup. */
1616 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
1617 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
1618 if_setcapenable(ifp, if_getcapabilities(ifp));
1619 /*
1620 * XXX
1621 * It seems enabling Tx checksum offloading makes more trouble.
1622 * Sometimes the controller does not receive any frames when
1623 * Tx checksum offloading is enabled. I'm not sure whether this
1624 * is a bug in Tx checksum offloading logic or I got broken
1625 * sample boards. To safety, don't enable Tx checksum offloading
1626 * by default but give chance to users to toggle it if they know
1627 * their controllers work without problems.
1628 * Fortunately, Tx checksum offloading for AR816x family
1629 * seems to work.
1630 */
1631 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
1632 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM);
1633 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES);
1634 }
1635
1636 /* Tell the upper layer(s) we support long frames. */
1637 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
1638
1639 /* Create local taskq. */
1640 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK,
1641 taskqueue_thread_enqueue, &sc->alc_tq);
1642 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq",
1643 device_get_nameunit(sc->alc_dev));
1644
1645 alc_config_msi(sc);
1646 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
1647 msic = ALC_MSIX_MESSAGES;
1648 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
1649 msic = ALC_MSI_MESSAGES;
1650 else
1651 msic = 1;
1652 for (i = 0; i < msic; i++) {
1653 error = bus_setup_intr(dev, sc->alc_irq[i],
1654 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc,
1655 &sc->alc_intrhand[i]);
1656 if (error != 0)
1657 break;
1658 }
1659 if (error != 0) {
1660 device_printf(dev, "could not set up interrupt handler.\n");
1661 taskqueue_free(sc->alc_tq);
1662 sc->alc_tq = NULL;
1663 ether_ifdetach(ifp);
1664 goto fail;
1665 }
1666
1667 /* Attach driver debugnet methods. */
1668 DEBUGNET_SET(ifp, alc);
1669
1670 fail:
1671 if (error != 0)
1672 alc_detach(dev);
1673
1674 return (error);
1675 }
1676
1677 static int
alc_detach(device_t dev)1678 alc_detach(device_t dev)
1679 {
1680 struct alc_softc *sc;
1681 if_t ifp;
1682 int i, msic;
1683
1684 sc = device_get_softc(dev);
1685
1686 ifp = sc->alc_ifp;
1687 if (device_is_attached(dev)) {
1688 ether_ifdetach(ifp);
1689 ALC_LOCK(sc);
1690 alc_stop(sc);
1691 ALC_UNLOCK(sc);
1692 callout_drain(&sc->alc_tick_ch);
1693 taskqueue_drain(sc->alc_tq, &sc->alc_int_task);
1694 }
1695
1696 if (sc->alc_tq != NULL) {
1697 taskqueue_drain(sc->alc_tq, &sc->alc_int_task);
1698 taskqueue_free(sc->alc_tq);
1699 sc->alc_tq = NULL;
1700 }
1701
1702 if (sc->alc_miibus != NULL) {
1703 device_delete_child(dev, sc->alc_miibus);
1704 sc->alc_miibus = NULL;
1705 }
1706 bus_generic_detach(dev);
1707 alc_dma_free(sc);
1708
1709 if (ifp != NULL) {
1710 if_free(ifp);
1711 sc->alc_ifp = NULL;
1712 }
1713
1714 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
1715 msic = ALC_MSIX_MESSAGES;
1716 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
1717 msic = ALC_MSI_MESSAGES;
1718 else
1719 msic = 1;
1720 for (i = 0; i < msic; i++) {
1721 if (sc->alc_intrhand[i] != NULL) {
1722 bus_teardown_intr(dev, sc->alc_irq[i],
1723 sc->alc_intrhand[i]);
1724 sc->alc_intrhand[i] = NULL;
1725 }
1726 }
1727 if (sc->alc_res[0] != NULL)
1728 alc_phy_down(sc);
1729 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq);
1730 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0)
1731 pci_release_msi(dev);
1732 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res);
1733 mtx_destroy(&sc->alc_mtx);
1734
1735 return (0);
1736 }
1737
1738 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \
1739 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
1740 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \
1741 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
1742
1743 static void
alc_sysctl_node(struct alc_softc * sc)1744 alc_sysctl_node(struct alc_softc *sc)
1745 {
1746 struct sysctl_ctx_list *ctx;
1747 struct sysctl_oid_list *child, *parent;
1748 struct sysctl_oid *tree;
1749 struct alc_hw_stats *stats;
1750 int error;
1751
1752 stats = &sc->alc_stats;
1753 ctx = device_get_sysctl_ctx(sc->alc_dev);
1754 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev));
1755
1756 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
1757 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_rx_mod,
1758 0, sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation");
1759 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
1760 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_tx_mod,
1761 0, sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation");
1762 /* Pull in device tunables. */
1763 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT;
1764 error = resource_int_value(device_get_name(sc->alc_dev),
1765 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod);
1766 if (error == 0) {
1767 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN ||
1768 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) {
1769 device_printf(sc->alc_dev, "int_rx_mod value out of "
1770 "range; using default: %d\n",
1771 ALC_IM_RX_TIMER_DEFAULT);
1772 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT;
1773 }
1774 }
1775 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT;
1776 error = resource_int_value(device_get_name(sc->alc_dev),
1777 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod);
1778 if (error == 0) {
1779 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN ||
1780 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) {
1781 device_printf(sc->alc_dev, "int_tx_mod value out of "
1782 "range; using default: %d\n",
1783 ALC_IM_TX_TIMER_DEFAULT);
1784 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT;
1785 }
1786 }
1787 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
1788 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1789 &sc->alc_process_limit, 0, sysctl_hw_alc_proc_limit, "I",
1790 "max number of Rx events to process");
1791 /* Pull in device tunables. */
1792 sc->alc_process_limit = ALC_PROC_DEFAULT;
1793 error = resource_int_value(device_get_name(sc->alc_dev),
1794 device_get_unit(sc->alc_dev), "process_limit",
1795 &sc->alc_process_limit);
1796 if (error == 0) {
1797 if (sc->alc_process_limit < ALC_PROC_MIN ||
1798 sc->alc_process_limit > ALC_PROC_MAX) {
1799 device_printf(sc->alc_dev,
1800 "process_limit value out of range; "
1801 "using default: %d\n", ALC_PROC_DEFAULT);
1802 sc->alc_process_limit = ALC_PROC_DEFAULT;
1803 }
1804 }
1805
1806 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
1807 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ALC statistics");
1808 parent = SYSCTL_CHILDREN(tree);
1809
1810 /* Rx statistics. */
1811 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx",
1812 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics");
1813 child = SYSCTL_CHILDREN(tree);
1814 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1815 &stats->rx_frames, "Good frames");
1816 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
1817 &stats->rx_bcast_frames, "Good broadcast frames");
1818 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
1819 &stats->rx_mcast_frames, "Good multicast frames");
1820 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
1821 &stats->rx_pause_frames, "Pause control frames");
1822 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
1823 &stats->rx_control_frames, "Control frames");
1824 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
1825 &stats->rx_crcerrs, "CRC errors");
1826 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
1827 &stats->rx_lenerrs, "Frames with length mismatched");
1828 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
1829 &stats->rx_bytes, "Good octets");
1830 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
1831 &stats->rx_bcast_bytes, "Good broadcast octets");
1832 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
1833 &stats->rx_mcast_bytes, "Good multicast octets");
1834 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts",
1835 &stats->rx_runts, "Too short frames");
1836 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments",
1837 &stats->rx_fragments, "Fragmented frames");
1838 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
1839 &stats->rx_pkts_64, "64 bytes frames");
1840 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
1841 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
1842 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
1843 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
1844 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
1845 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
1846 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
1847 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
1848 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
1849 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
1850 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
1851 &stats->rx_pkts_1519_max, "1519 to max frames");
1852 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
1853 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
1854 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
1855 &stats->rx_fifo_oflows, "FIFO overflows");
1856 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
1857 &stats->rx_rrs_errs, "Return status write-back errors");
1858 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
1859 &stats->rx_alignerrs, "Alignment errors");
1860 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered",
1861 &stats->rx_pkts_filtered,
1862 "Frames dropped due to address filtering");
1863
1864 /* Tx statistics. */
1865 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
1866 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics");
1867 child = SYSCTL_CHILDREN(tree);
1868 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1869 &stats->tx_frames, "Good frames");
1870 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
1871 &stats->tx_bcast_frames, "Good broadcast frames");
1872 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
1873 &stats->tx_mcast_frames, "Good multicast frames");
1874 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
1875 &stats->tx_pause_frames, "Pause control frames");
1876 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
1877 &stats->tx_control_frames, "Control frames");
1878 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
1879 &stats->tx_excess_defer, "Frames with excessive derferrals");
1880 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers",
1881 &stats->tx_excess_defer, "Frames with derferrals");
1882 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
1883 &stats->tx_bytes, "Good octets");
1884 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
1885 &stats->tx_bcast_bytes, "Good broadcast octets");
1886 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
1887 &stats->tx_mcast_bytes, "Good multicast octets");
1888 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
1889 &stats->tx_pkts_64, "64 bytes frames");
1890 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
1891 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
1892 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
1893 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
1894 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
1895 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
1896 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
1897 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
1898 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
1899 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
1900 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
1901 &stats->tx_pkts_1519_max, "1519 to max frames");
1902 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
1903 &stats->tx_single_colls, "Single collisions");
1904 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
1905 &stats->tx_multi_colls, "Multiple collisions");
1906 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
1907 &stats->tx_late_colls, "Late collisions");
1908 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
1909 &stats->tx_excess_colls, "Excessive collisions");
1910 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns",
1911 &stats->tx_underrun, "FIFO underruns");
1912 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
1913 &stats->tx_desc_underrun, "Descriptor write-back errors");
1914 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
1915 &stats->tx_lenerrs, "Frames with length mismatched");
1916 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
1917 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
1918 }
1919
1920 #undef ALC_SYSCTL_STAT_ADD32
1921 #undef ALC_SYSCTL_STAT_ADD64
1922
1923 struct alc_dmamap_arg {
1924 bus_addr_t alc_busaddr;
1925 };
1926
1927 static void
alc_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)1928 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1929 {
1930 struct alc_dmamap_arg *ctx;
1931
1932 if (error != 0)
1933 return;
1934
1935 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1936
1937 ctx = (struct alc_dmamap_arg *)arg;
1938 ctx->alc_busaddr = segs[0].ds_addr;
1939 }
1940
1941 /*
1942 * Normal and high Tx descriptors shares single Tx high address.
1943 * Four Rx descriptor/return rings and CMB shares the same Rx
1944 * high address.
1945 */
1946 static int
alc_check_boundary(struct alc_softc * sc)1947 alc_check_boundary(struct alc_softc *sc)
1948 {
1949 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end;
1950
1951 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ;
1952 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ;
1953 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ;
1954 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ;
1955
1956 /* 4GB boundary crossing is not allowed. */
1957 if ((ALC_ADDR_HI(rx_ring_end) !=
1958 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) ||
1959 (ALC_ADDR_HI(rr_ring_end) !=
1960 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) ||
1961 (ALC_ADDR_HI(cmb_end) !=
1962 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) ||
1963 (ALC_ADDR_HI(tx_ring_end) !=
1964 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr)))
1965 return (EFBIG);
1966 /*
1967 * Make sure Rx return descriptor/Rx descriptor/CMB use
1968 * the same high address.
1969 */
1970 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) ||
1971 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end)))
1972 return (EFBIG);
1973
1974 return (0);
1975 }
1976
1977 static int
alc_dma_alloc(struct alc_softc * sc)1978 alc_dma_alloc(struct alc_softc *sc)
1979 {
1980 struct alc_txdesc *txd;
1981 struct alc_rxdesc *rxd;
1982 bus_addr_t lowaddr;
1983 struct alc_dmamap_arg ctx;
1984 int error, i;
1985
1986 lowaddr = BUS_SPACE_MAXADDR;
1987 if (sc->alc_flags & ALC_FLAG_MT)
1988 lowaddr = BUS_SPACE_MAXSIZE_32BIT;
1989 again:
1990 /* Create parent DMA tag. */
1991 error = bus_dma_tag_create(
1992 bus_get_dma_tag(sc->alc_dev), /* parent */
1993 1, 0, /* alignment, boundary */
1994 lowaddr, /* lowaddr */
1995 BUS_SPACE_MAXADDR, /* highaddr */
1996 NULL, NULL, /* filter, filterarg */
1997 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1998 0, /* nsegments */
1999 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
2000 0, /* flags */
2001 NULL, NULL, /* lockfunc, lockarg */
2002 &sc->alc_cdata.alc_parent_tag);
2003 if (error != 0) {
2004 device_printf(sc->alc_dev,
2005 "could not create parent DMA tag.\n");
2006 goto fail;
2007 }
2008
2009 /* Create DMA tag for Tx descriptor ring. */
2010 error = bus_dma_tag_create(
2011 sc->alc_cdata.alc_parent_tag, /* parent */
2012 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */
2013 BUS_SPACE_MAXADDR, /* lowaddr */
2014 BUS_SPACE_MAXADDR, /* highaddr */
2015 NULL, NULL, /* filter, filterarg */
2016 ALC_TX_RING_SZ, /* maxsize */
2017 1, /* nsegments */
2018 ALC_TX_RING_SZ, /* maxsegsize */
2019 0, /* flags */
2020 NULL, NULL, /* lockfunc, lockarg */
2021 &sc->alc_cdata.alc_tx_ring_tag);
2022 if (error != 0) {
2023 device_printf(sc->alc_dev,
2024 "could not create Tx ring DMA tag.\n");
2025 goto fail;
2026 }
2027
2028 /* Create DMA tag for Rx free descriptor ring. */
2029 error = bus_dma_tag_create(
2030 sc->alc_cdata.alc_parent_tag, /* parent */
2031 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */
2032 BUS_SPACE_MAXADDR, /* lowaddr */
2033 BUS_SPACE_MAXADDR, /* highaddr */
2034 NULL, NULL, /* filter, filterarg */
2035 ALC_RX_RING_SZ, /* maxsize */
2036 1, /* nsegments */
2037 ALC_RX_RING_SZ, /* maxsegsize */
2038 0, /* flags */
2039 NULL, NULL, /* lockfunc, lockarg */
2040 &sc->alc_cdata.alc_rx_ring_tag);
2041 if (error != 0) {
2042 device_printf(sc->alc_dev,
2043 "could not create Rx ring DMA tag.\n");
2044 goto fail;
2045 }
2046 /* Create DMA tag for Rx return descriptor ring. */
2047 error = bus_dma_tag_create(
2048 sc->alc_cdata.alc_parent_tag, /* parent */
2049 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */
2050 BUS_SPACE_MAXADDR, /* lowaddr */
2051 BUS_SPACE_MAXADDR, /* highaddr */
2052 NULL, NULL, /* filter, filterarg */
2053 ALC_RR_RING_SZ, /* maxsize */
2054 1, /* nsegments */
2055 ALC_RR_RING_SZ, /* maxsegsize */
2056 0, /* flags */
2057 NULL, NULL, /* lockfunc, lockarg */
2058 &sc->alc_cdata.alc_rr_ring_tag);
2059 if (error != 0) {
2060 device_printf(sc->alc_dev,
2061 "could not create Rx return ring DMA tag.\n");
2062 goto fail;
2063 }
2064
2065 /* Create DMA tag for coalescing message block. */
2066 error = bus_dma_tag_create(
2067 sc->alc_cdata.alc_parent_tag, /* parent */
2068 ALC_CMB_ALIGN, 0, /* alignment, boundary */
2069 BUS_SPACE_MAXADDR, /* lowaddr */
2070 BUS_SPACE_MAXADDR, /* highaddr */
2071 NULL, NULL, /* filter, filterarg */
2072 ALC_CMB_SZ, /* maxsize */
2073 1, /* nsegments */
2074 ALC_CMB_SZ, /* maxsegsize */
2075 0, /* flags */
2076 NULL, NULL, /* lockfunc, lockarg */
2077 &sc->alc_cdata.alc_cmb_tag);
2078 if (error != 0) {
2079 device_printf(sc->alc_dev,
2080 "could not create CMB DMA tag.\n");
2081 goto fail;
2082 }
2083 /* Create DMA tag for status message block. */
2084 error = bus_dma_tag_create(
2085 sc->alc_cdata.alc_parent_tag, /* parent */
2086 ALC_SMB_ALIGN, 0, /* alignment, boundary */
2087 BUS_SPACE_MAXADDR, /* lowaddr */
2088 BUS_SPACE_MAXADDR, /* highaddr */
2089 NULL, NULL, /* filter, filterarg */
2090 ALC_SMB_SZ, /* maxsize */
2091 1, /* nsegments */
2092 ALC_SMB_SZ, /* maxsegsize */
2093 0, /* flags */
2094 NULL, NULL, /* lockfunc, lockarg */
2095 &sc->alc_cdata.alc_smb_tag);
2096 if (error != 0) {
2097 device_printf(sc->alc_dev,
2098 "could not create SMB DMA tag.\n");
2099 goto fail;
2100 }
2101
2102 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
2103 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag,
2104 (void **)&sc->alc_rdata.alc_tx_ring,
2105 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2106 &sc->alc_cdata.alc_tx_ring_map);
2107 if (error != 0) {
2108 device_printf(sc->alc_dev,
2109 "could not allocate DMA'able memory for Tx ring.\n");
2110 goto fail;
2111 }
2112 ctx.alc_busaddr = 0;
2113 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag,
2114 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring,
2115 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0);
2116 if (error != 0 || ctx.alc_busaddr == 0) {
2117 device_printf(sc->alc_dev,
2118 "could not load DMA'able memory for Tx ring.\n");
2119 goto fail;
2120 }
2121 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr;
2122
2123 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
2124 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag,
2125 (void **)&sc->alc_rdata.alc_rx_ring,
2126 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2127 &sc->alc_cdata.alc_rx_ring_map);
2128 if (error != 0) {
2129 device_printf(sc->alc_dev,
2130 "could not allocate DMA'able memory for Rx ring.\n");
2131 goto fail;
2132 }
2133 ctx.alc_busaddr = 0;
2134 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag,
2135 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring,
2136 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0);
2137 if (error != 0 || ctx.alc_busaddr == 0) {
2138 device_printf(sc->alc_dev,
2139 "could not load DMA'able memory for Rx ring.\n");
2140 goto fail;
2141 }
2142 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr;
2143
2144 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */
2145 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag,
2146 (void **)&sc->alc_rdata.alc_rr_ring,
2147 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2148 &sc->alc_cdata.alc_rr_ring_map);
2149 if (error != 0) {
2150 device_printf(sc->alc_dev,
2151 "could not allocate DMA'able memory for Rx return ring.\n");
2152 goto fail;
2153 }
2154 ctx.alc_busaddr = 0;
2155 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag,
2156 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring,
2157 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0);
2158 if (error != 0 || ctx.alc_busaddr == 0) {
2159 device_printf(sc->alc_dev,
2160 "could not load DMA'able memory for Tx ring.\n");
2161 goto fail;
2162 }
2163 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr;
2164
2165 /* Allocate DMA'able memory and load the DMA map for CMB. */
2166 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag,
2167 (void **)&sc->alc_rdata.alc_cmb,
2168 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2169 &sc->alc_cdata.alc_cmb_map);
2170 if (error != 0) {
2171 device_printf(sc->alc_dev,
2172 "could not allocate DMA'able memory for CMB.\n");
2173 goto fail;
2174 }
2175 ctx.alc_busaddr = 0;
2176 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag,
2177 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb,
2178 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0);
2179 if (error != 0 || ctx.alc_busaddr == 0) {
2180 device_printf(sc->alc_dev,
2181 "could not load DMA'able memory for CMB.\n");
2182 goto fail;
2183 }
2184 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr;
2185
2186 /* Allocate DMA'able memory and load the DMA map for SMB. */
2187 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag,
2188 (void **)&sc->alc_rdata.alc_smb,
2189 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2190 &sc->alc_cdata.alc_smb_map);
2191 if (error != 0) {
2192 device_printf(sc->alc_dev,
2193 "could not allocate DMA'able memory for SMB.\n");
2194 goto fail;
2195 }
2196 ctx.alc_busaddr = 0;
2197 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag,
2198 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb,
2199 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0);
2200 if (error != 0 || ctx.alc_busaddr == 0) {
2201 device_printf(sc->alc_dev,
2202 "could not load DMA'able memory for CMB.\n");
2203 goto fail;
2204 }
2205 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr;
2206
2207 /* Make sure we've not crossed 4GB boundary. */
2208 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
2209 (error = alc_check_boundary(sc)) != 0) {
2210 device_printf(sc->alc_dev, "4GB boundary crossed, "
2211 "switching to 32bit DMA addressing mode.\n");
2212 alc_dma_free(sc);
2213 /*
2214 * Limit max allowable DMA address space to 32bit
2215 * and try again.
2216 */
2217 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2218 goto again;
2219 }
2220
2221 /*
2222 * Create Tx buffer parent tag.
2223 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers
2224 * so it needs separate parent DMA tag as parent DMA address
2225 * space could be restricted to be within 32bit address space
2226 * by 4GB boundary crossing.
2227 */
2228 error = bus_dma_tag_create(
2229 bus_get_dma_tag(sc->alc_dev), /* parent */
2230 1, 0, /* alignment, boundary */
2231 lowaddr, /* lowaddr */
2232 BUS_SPACE_MAXADDR, /* highaddr */
2233 NULL, NULL, /* filter, filterarg */
2234 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
2235 0, /* nsegments */
2236 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
2237 0, /* flags */
2238 NULL, NULL, /* lockfunc, lockarg */
2239 &sc->alc_cdata.alc_buffer_tag);
2240 if (error != 0) {
2241 device_printf(sc->alc_dev,
2242 "could not create parent buffer DMA tag.\n");
2243 goto fail;
2244 }
2245
2246 /* Create DMA tag for Tx buffers. */
2247 error = bus_dma_tag_create(
2248 sc->alc_cdata.alc_buffer_tag, /* parent */
2249 1, 0, /* alignment, boundary */
2250 BUS_SPACE_MAXADDR, /* lowaddr */
2251 BUS_SPACE_MAXADDR, /* highaddr */
2252 NULL, NULL, /* filter, filterarg */
2253 ALC_TSO_MAXSIZE, /* maxsize */
2254 ALC_MAXTXSEGS, /* nsegments */
2255 ALC_TSO_MAXSEGSIZE, /* maxsegsize */
2256 0, /* flags */
2257 NULL, NULL, /* lockfunc, lockarg */
2258 &sc->alc_cdata.alc_tx_tag);
2259 if (error != 0) {
2260 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n");
2261 goto fail;
2262 }
2263
2264 /* Create DMA tag for Rx buffers. */
2265 error = bus_dma_tag_create(
2266 sc->alc_cdata.alc_buffer_tag, /* parent */
2267 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */
2268 BUS_SPACE_MAXADDR, /* lowaddr */
2269 BUS_SPACE_MAXADDR, /* highaddr */
2270 NULL, NULL, /* filter, filterarg */
2271 MCLBYTES, /* maxsize */
2272 1, /* nsegments */
2273 MCLBYTES, /* maxsegsize */
2274 0, /* flags */
2275 NULL, NULL, /* lockfunc, lockarg */
2276 &sc->alc_cdata.alc_rx_tag);
2277 if (error != 0) {
2278 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n");
2279 goto fail;
2280 }
2281 /* Create DMA maps for Tx buffers. */
2282 for (i = 0; i < ALC_TX_RING_CNT; i++) {
2283 txd = &sc->alc_cdata.alc_txdesc[i];
2284 txd->tx_m = NULL;
2285 txd->tx_dmamap = NULL;
2286 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0,
2287 &txd->tx_dmamap);
2288 if (error != 0) {
2289 device_printf(sc->alc_dev,
2290 "could not create Tx dmamap.\n");
2291 goto fail;
2292 }
2293 }
2294 /* Create DMA maps for Rx buffers. */
2295 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0,
2296 &sc->alc_cdata.alc_rx_sparemap)) != 0) {
2297 device_printf(sc->alc_dev,
2298 "could not create spare Rx dmamap.\n");
2299 goto fail;
2300 }
2301 for (i = 0; i < ALC_RX_RING_CNT; i++) {
2302 rxd = &sc->alc_cdata.alc_rxdesc[i];
2303 rxd->rx_m = NULL;
2304 rxd->rx_dmamap = NULL;
2305 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0,
2306 &rxd->rx_dmamap);
2307 if (error != 0) {
2308 device_printf(sc->alc_dev,
2309 "could not create Rx dmamap.\n");
2310 goto fail;
2311 }
2312 }
2313
2314 fail:
2315 return (error);
2316 }
2317
2318 static void
alc_dma_free(struct alc_softc * sc)2319 alc_dma_free(struct alc_softc *sc)
2320 {
2321 struct alc_txdesc *txd;
2322 struct alc_rxdesc *rxd;
2323 int i;
2324
2325 /* Tx buffers. */
2326 if (sc->alc_cdata.alc_tx_tag != NULL) {
2327 for (i = 0; i < ALC_TX_RING_CNT; i++) {
2328 txd = &sc->alc_cdata.alc_txdesc[i];
2329 if (txd->tx_dmamap != NULL) {
2330 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag,
2331 txd->tx_dmamap);
2332 txd->tx_dmamap = NULL;
2333 }
2334 }
2335 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag);
2336 sc->alc_cdata.alc_tx_tag = NULL;
2337 }
2338 /* Rx buffers */
2339 if (sc->alc_cdata.alc_rx_tag != NULL) {
2340 for (i = 0; i < ALC_RX_RING_CNT; i++) {
2341 rxd = &sc->alc_cdata.alc_rxdesc[i];
2342 if (rxd->rx_dmamap != NULL) {
2343 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag,
2344 rxd->rx_dmamap);
2345 rxd->rx_dmamap = NULL;
2346 }
2347 }
2348 if (sc->alc_cdata.alc_rx_sparemap != NULL) {
2349 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag,
2350 sc->alc_cdata.alc_rx_sparemap);
2351 sc->alc_cdata.alc_rx_sparemap = NULL;
2352 }
2353 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag);
2354 sc->alc_cdata.alc_rx_tag = NULL;
2355 }
2356 /* Tx descriptor ring. */
2357 if (sc->alc_cdata.alc_tx_ring_tag != NULL) {
2358 if (sc->alc_rdata.alc_tx_ring_paddr != 0)
2359 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag,
2360 sc->alc_cdata.alc_tx_ring_map);
2361 if (sc->alc_rdata.alc_tx_ring != NULL)
2362 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag,
2363 sc->alc_rdata.alc_tx_ring,
2364 sc->alc_cdata.alc_tx_ring_map);
2365 sc->alc_rdata.alc_tx_ring_paddr = 0;
2366 sc->alc_rdata.alc_tx_ring = NULL;
2367 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag);
2368 sc->alc_cdata.alc_tx_ring_tag = NULL;
2369 }
2370 /* Rx ring. */
2371 if (sc->alc_cdata.alc_rx_ring_tag != NULL) {
2372 if (sc->alc_rdata.alc_rx_ring_paddr != 0)
2373 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag,
2374 sc->alc_cdata.alc_rx_ring_map);
2375 if (sc->alc_rdata.alc_rx_ring != NULL)
2376 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag,
2377 sc->alc_rdata.alc_rx_ring,
2378 sc->alc_cdata.alc_rx_ring_map);
2379 sc->alc_rdata.alc_rx_ring_paddr = 0;
2380 sc->alc_rdata.alc_rx_ring = NULL;
2381 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag);
2382 sc->alc_cdata.alc_rx_ring_tag = NULL;
2383 }
2384 /* Rx return ring. */
2385 if (sc->alc_cdata.alc_rr_ring_tag != NULL) {
2386 if (sc->alc_rdata.alc_rr_ring_paddr != 0)
2387 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag,
2388 sc->alc_cdata.alc_rr_ring_map);
2389 if (sc->alc_rdata.alc_rr_ring != NULL)
2390 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag,
2391 sc->alc_rdata.alc_rr_ring,
2392 sc->alc_cdata.alc_rr_ring_map);
2393 sc->alc_rdata.alc_rr_ring_paddr = 0;
2394 sc->alc_rdata.alc_rr_ring = NULL;
2395 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag);
2396 sc->alc_cdata.alc_rr_ring_tag = NULL;
2397 }
2398 /* CMB block */
2399 if (sc->alc_cdata.alc_cmb_tag != NULL) {
2400 if (sc->alc_rdata.alc_cmb_paddr != 0)
2401 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag,
2402 sc->alc_cdata.alc_cmb_map);
2403 if (sc->alc_rdata.alc_cmb != NULL)
2404 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag,
2405 sc->alc_rdata.alc_cmb,
2406 sc->alc_cdata.alc_cmb_map);
2407 sc->alc_rdata.alc_cmb_paddr = 0;
2408 sc->alc_rdata.alc_cmb = NULL;
2409 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag);
2410 sc->alc_cdata.alc_cmb_tag = NULL;
2411 }
2412 /* SMB block */
2413 if (sc->alc_cdata.alc_smb_tag != NULL) {
2414 if (sc->alc_rdata.alc_smb_paddr != 0)
2415 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag,
2416 sc->alc_cdata.alc_smb_map);
2417 if (sc->alc_rdata.alc_smb != NULL)
2418 bus_dmamem_free(sc->alc_cdata.alc_smb_tag,
2419 sc->alc_rdata.alc_smb,
2420 sc->alc_cdata.alc_smb_map);
2421 sc->alc_rdata.alc_smb_paddr = 0;
2422 sc->alc_rdata.alc_smb = NULL;
2423 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag);
2424 sc->alc_cdata.alc_smb_tag = NULL;
2425 }
2426 if (sc->alc_cdata.alc_buffer_tag != NULL) {
2427 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag);
2428 sc->alc_cdata.alc_buffer_tag = NULL;
2429 }
2430 if (sc->alc_cdata.alc_parent_tag != NULL) {
2431 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag);
2432 sc->alc_cdata.alc_parent_tag = NULL;
2433 }
2434 }
2435
2436 static int
alc_shutdown(device_t dev)2437 alc_shutdown(device_t dev)
2438 {
2439
2440 return (alc_suspend(dev));
2441 }
2442
2443 /*
2444 * Note, this driver resets the link speed to 10/100Mbps by
2445 * restarting auto-negotiation in suspend/shutdown phase but we
2446 * don't know whether that auto-negotiation would succeed or not
2447 * as driver has no control after powering off/suspend operation.
2448 * If the renegotiation fail WOL may not work. Running at 1Gbps
2449 * will draw more power than 375mA at 3.3V which is specified in
2450 * PCI specification and that would result in complete
2451 * shutdowning power to ethernet controller.
2452 *
2453 * TODO
2454 * Save current negotiated media speed/duplex/flow-control to
2455 * softc and restore the same link again after resuming. PHY
2456 * handling such as power down/resetting to 100Mbps may be better
2457 * handled in suspend method in phy driver.
2458 */
2459 static void
alc_setlinkspeed(struct alc_softc * sc)2460 alc_setlinkspeed(struct alc_softc *sc)
2461 {
2462 struct mii_data *mii;
2463 int aneg, i;
2464
2465 mii = device_get_softc(sc->alc_miibus);
2466 mii_pollstat(mii);
2467 aneg = 0;
2468 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
2469 (IFM_ACTIVE | IFM_AVALID)) {
2470 switch IFM_SUBTYPE(mii->mii_media_active) {
2471 case IFM_10_T:
2472 case IFM_100_TX:
2473 return;
2474 case IFM_1000_T:
2475 aneg++;
2476 break;
2477 default:
2478 break;
2479 }
2480 }
2481 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0);
2482 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
2483 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
2484 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
2485 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
2486 DELAY(1000);
2487 if (aneg != 0) {
2488 /*
2489 * Poll link state until alc(4) get a 10/100Mbps link.
2490 */
2491 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
2492 mii_pollstat(mii);
2493 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
2494 == (IFM_ACTIVE | IFM_AVALID)) {
2495 switch (IFM_SUBTYPE(
2496 mii->mii_media_active)) {
2497 case IFM_10_T:
2498 case IFM_100_TX:
2499 alc_mac_config(sc);
2500 return;
2501 default:
2502 break;
2503 }
2504 }
2505 ALC_UNLOCK(sc);
2506 pause("alclnk", hz);
2507 ALC_LOCK(sc);
2508 }
2509 if (i == MII_ANEGTICKS_GIGE)
2510 device_printf(sc->alc_dev,
2511 "establishing a link failed, WOL may not work!");
2512 }
2513 /*
2514 * No link, force MAC to have 100Mbps, full-duplex link.
2515 * This is the last resort and may/may not work.
2516 */
2517 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
2518 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
2519 alc_mac_config(sc);
2520 }
2521
2522 static void
alc_setwol(struct alc_softc * sc)2523 alc_setwol(struct alc_softc *sc)
2524 {
2525
2526 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
2527 alc_setwol_816x(sc);
2528 else
2529 alc_setwol_813x(sc);
2530 }
2531
2532 static void
alc_setwol_813x(struct alc_softc * sc)2533 alc_setwol_813x(struct alc_softc *sc)
2534 {
2535 if_t ifp;
2536 uint32_t reg, pmcs;
2537 uint16_t pmstat;
2538
2539 ALC_LOCK_ASSERT(sc);
2540
2541 alc_disable_l0s_l1(sc);
2542 ifp = sc->alc_ifp;
2543 if ((sc->alc_flags & ALC_FLAG_PM) == 0) {
2544 /* Disable WOL. */
2545 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
2546 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);
2547 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
2548 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
2549 /* Force PHY power down. */
2550 alc_phy_down(sc);
2551 CSR_WRITE_4(sc, ALC_MASTER_CFG,
2552 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
2553 return;
2554 }
2555
2556 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
2557 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
2558 alc_setlinkspeed(sc);
2559 CSR_WRITE_4(sc, ALC_MASTER_CFG,
2560 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS);
2561 }
2562
2563 pmcs = 0;
2564 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
2565 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
2566 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs);
2567 reg = CSR_READ_4(sc, ALC_MAC_CFG);
2568 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
2569 MAC_CFG_BCAST);
2570 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0)
2571 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
2572 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
2573 reg |= MAC_CFG_RX_ENB;
2574 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
2575
2576 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);
2577 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
2578 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
2579 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) {
2580 /* WOL disabled, PHY power down. */
2581 alc_phy_down(sc);
2582 CSR_WRITE_4(sc, ALC_MASTER_CFG,
2583 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
2584 }
2585 /* Request PME. */
2586 pmstat = pci_read_config(sc->alc_dev,
2587 sc->alc_pmcap + PCIR_POWER_STATUS, 2);
2588 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2589 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
2590 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2591 pci_write_config(sc->alc_dev,
2592 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2);
2593 }
2594
2595 static void
alc_setwol_816x(struct alc_softc * sc)2596 alc_setwol_816x(struct alc_softc *sc)
2597 {
2598 if_t ifp;
2599 uint32_t gphy, mac, master, pmcs, reg;
2600 uint16_t pmstat;
2601
2602 ALC_LOCK_ASSERT(sc);
2603
2604 ifp = sc->alc_ifp;
2605 master = CSR_READ_4(sc, ALC_MASTER_CFG);
2606 master &= ~MASTER_CLK_SEL_DIS;
2607 gphy = CSR_READ_4(sc, ALC_GPHY_CFG);
2608 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB |
2609 GPHY_CFG_PHY_PLL_ON);
2610 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET;
2611 if ((sc->alc_flags & ALC_FLAG_PM) == 0) {
2612 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
2613 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW;
2614 mac = CSR_READ_4(sc, ALC_MAC_CFG);
2615 } else {
2616 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
2617 gphy |= GPHY_CFG_EXT_RESET;
2618 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
2619 alc_setlinkspeed(sc);
2620 }
2621 pmcs = 0;
2622 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
2623 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
2624 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs);
2625 mac = CSR_READ_4(sc, ALC_MAC_CFG);
2626 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
2627 MAC_CFG_BCAST);
2628 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0)
2629 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
2630 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
2631 mac |= MAC_CFG_RX_ENB;
2632 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10,
2633 ANEG_S3DIG10_SL);
2634 }
2635
2636 /* Enable OSC. */
2637 reg = CSR_READ_4(sc, ALC_MISC);
2638 reg &= ~MISC_INTNLOSC_OPEN;
2639 CSR_WRITE_4(sc, ALC_MISC, reg);
2640 reg |= MISC_INTNLOSC_OPEN;
2641 CSR_WRITE_4(sc, ALC_MISC, reg);
2642 CSR_WRITE_4(sc, ALC_MASTER_CFG, master);
2643 CSR_WRITE_4(sc, ALC_MAC_CFG, mac);
2644 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy);
2645 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1);
2646 reg |= PDLL_TRNS1_D3PLLOFF_ENB;
2647 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg);
2648
2649 if ((sc->alc_flags & ALC_FLAG_PM) != 0) {
2650 /* Request PME. */
2651 pmstat = pci_read_config(sc->alc_dev,
2652 sc->alc_pmcap + PCIR_POWER_STATUS, 2);
2653 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2654 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
2655 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2656 pci_write_config(sc->alc_dev,
2657 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2);
2658 }
2659 }
2660
2661 static int
alc_suspend(device_t dev)2662 alc_suspend(device_t dev)
2663 {
2664 struct alc_softc *sc;
2665
2666 sc = device_get_softc(dev);
2667
2668 ALC_LOCK(sc);
2669 alc_stop(sc);
2670 alc_setwol(sc);
2671 ALC_UNLOCK(sc);
2672
2673 return (0);
2674 }
2675
2676 static int
alc_resume(device_t dev)2677 alc_resume(device_t dev)
2678 {
2679 struct alc_softc *sc;
2680 if_t ifp;
2681 uint16_t pmstat;
2682
2683 sc = device_get_softc(dev);
2684
2685 ALC_LOCK(sc);
2686 if ((sc->alc_flags & ALC_FLAG_PM) != 0) {
2687 /* Disable PME and clear PME status. */
2688 pmstat = pci_read_config(sc->alc_dev,
2689 sc->alc_pmcap + PCIR_POWER_STATUS, 2);
2690 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
2691 pmstat &= ~PCIM_PSTAT_PMEENABLE;
2692 pci_write_config(sc->alc_dev,
2693 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2);
2694 }
2695 }
2696 /* Reset PHY. */
2697 alc_phy_reset(sc);
2698 ifp = sc->alc_ifp;
2699 if ((if_getflags(ifp) & IFF_UP) != 0) {
2700 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2701 alc_init_locked(sc);
2702 }
2703 ALC_UNLOCK(sc);
2704
2705 return (0);
2706 }
2707
2708 static int
alc_encap(struct alc_softc * sc,struct mbuf ** m_head)2709 alc_encap(struct alc_softc *sc, struct mbuf **m_head)
2710 {
2711 struct alc_txdesc *txd, *txd_last;
2712 struct tx_desc *desc;
2713 struct mbuf *m;
2714 struct ip *ip;
2715 struct tcphdr *tcp;
2716 bus_dma_segment_t txsegs[ALC_MAXTXSEGS];
2717 bus_dmamap_t map;
2718 uint32_t cflags, hdrlen, ip_off, poff, vtag;
2719 int error, idx, nsegs, prod;
2720
2721 ALC_LOCK_ASSERT(sc);
2722
2723 M_ASSERTPKTHDR((*m_head));
2724
2725 m = *m_head;
2726 ip = NULL;
2727 tcp = NULL;
2728 ip_off = poff = 0;
2729 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) {
2730 /*
2731 * AR81[3567]x requires offset of TCP/UDP header in its
2732 * Tx descriptor to perform Tx checksum offloading. TSO
2733 * also requires TCP header offset and modification of
2734 * IP/TCP header. This kind of operation takes many CPU
2735 * cycles on FreeBSD so fast host CPU is required to get
2736 * smooth TSO performance.
2737 */
2738 struct ether_header *eh;
2739
2740 if (M_WRITABLE(m) == 0) {
2741 /* Get a writable copy. */
2742 m = m_dup(*m_head, M_NOWAIT);
2743 /* Release original mbufs. */
2744 m_freem(*m_head);
2745 if (m == NULL) {
2746 *m_head = NULL;
2747 return (ENOBUFS);
2748 }
2749 *m_head = m;
2750 }
2751
2752 ip_off = sizeof(struct ether_header);
2753 m = m_pullup(m, ip_off);
2754 if (m == NULL) {
2755 *m_head = NULL;
2756 return (ENOBUFS);
2757 }
2758 eh = mtod(m, struct ether_header *);
2759 /*
2760 * Check if hardware VLAN insertion is off.
2761 * Additional check for LLC/SNAP frame?
2762 */
2763 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2764 ip_off = sizeof(struct ether_vlan_header);
2765 m = m_pullup(m, ip_off);
2766 if (m == NULL) {
2767 *m_head = NULL;
2768 return (ENOBUFS);
2769 }
2770 }
2771 m = m_pullup(m, ip_off + sizeof(struct ip));
2772 if (m == NULL) {
2773 *m_head = NULL;
2774 return (ENOBUFS);
2775 }
2776 ip = (struct ip *)(mtod(m, char *) + ip_off);
2777 poff = ip_off + (ip->ip_hl << 2);
2778 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2779 m = m_pullup(m, poff + sizeof(struct tcphdr));
2780 if (m == NULL) {
2781 *m_head = NULL;
2782 return (ENOBUFS);
2783 }
2784 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
2785 m = m_pullup(m, poff + (tcp->th_off << 2));
2786 if (m == NULL) {
2787 *m_head = NULL;
2788 return (ENOBUFS);
2789 }
2790 /*
2791 * Due to strict adherence of Microsoft NDIS
2792 * Large Send specification, hardware expects
2793 * a pseudo TCP checksum inserted by upper
2794 * stack. Unfortunately the pseudo TCP
2795 * checksum that NDIS refers to does not include
2796 * TCP payload length so driver should recompute
2797 * the pseudo checksum here. Hopefully this
2798 * wouldn't be much burden on modern CPUs.
2799 *
2800 * Reset IP checksum and recompute TCP pseudo
2801 * checksum as NDIS specification said.
2802 */
2803 ip = (struct ip *)(mtod(m, char *) + ip_off);
2804 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
2805 ip->ip_sum = 0;
2806 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
2807 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2808 }
2809 *m_head = m;
2810 }
2811
2812 prod = sc->alc_cdata.alc_tx_prod;
2813 txd = &sc->alc_cdata.alc_txdesc[prod];
2814 txd_last = txd;
2815 map = txd->tx_dmamap;
2816
2817 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map,
2818 *m_head, txsegs, &nsegs, 0);
2819 if (error == EFBIG) {
2820 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS);
2821 if (m == NULL) {
2822 m_freem(*m_head);
2823 *m_head = NULL;
2824 return (ENOMEM);
2825 }
2826 *m_head = m;
2827 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map,
2828 *m_head, txsegs, &nsegs, 0);
2829 if (error != 0) {
2830 m_freem(*m_head);
2831 *m_head = NULL;
2832 return (error);
2833 }
2834 } else if (error != 0)
2835 return (error);
2836 if (nsegs == 0) {
2837 m_freem(*m_head);
2838 *m_head = NULL;
2839 return (EIO);
2840 }
2841
2842 /* Check descriptor overrun. */
2843 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) {
2844 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map);
2845 return (ENOBUFS);
2846 }
2847 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE);
2848
2849 m = *m_head;
2850 cflags = TD_ETHERNET;
2851 vtag = 0;
2852 desc = NULL;
2853 idx = 0;
2854 /* Configure VLAN hardware tag insertion. */
2855 if ((m->m_flags & M_VLANTAG) != 0) {
2856 vtag = htons(m->m_pkthdr.ether_vtag);
2857 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK;
2858 cflags |= TD_INS_VLAN_TAG;
2859 }
2860 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2861 /* Request TSO and set MSS. */
2862 cflags |= TD_TSO | TD_TSO_DESCV1;
2863 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) &
2864 TD_MSS_MASK;
2865 /* Set TCP header offset. */
2866 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) &
2867 TD_TCPHDR_OFFSET_MASK;
2868 /*
2869 * AR81[3567]x requires the first buffer should
2870 * only hold IP/TCP header data. Payload should
2871 * be handled in other descriptors.
2872 */
2873 hdrlen = poff + (tcp->th_off << 2);
2874 desc = &sc->alc_rdata.alc_tx_ring[prod];
2875 desc->len = htole32(TX_BYTES(hdrlen | vtag));
2876 desc->flags = htole32(cflags);
2877 desc->addr = htole64(txsegs[0].ds_addr);
2878 sc->alc_cdata.alc_tx_cnt++;
2879 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
2880 if (m->m_len - hdrlen > 0) {
2881 /* Handle remaining payload of the first fragment. */
2882 desc = &sc->alc_rdata.alc_tx_ring[prod];
2883 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) |
2884 vtag));
2885 desc->flags = htole32(cflags);
2886 desc->addr = htole64(txsegs[0].ds_addr + hdrlen);
2887 sc->alc_cdata.alc_tx_cnt++;
2888 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
2889 }
2890 /* Handle remaining fragments. */
2891 idx = 1;
2892 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) {
2893 /* Configure Tx checksum offload. */
2894 #ifdef ALC_USE_CUSTOM_CSUM
2895 cflags |= TD_CUSTOM_CSUM;
2896 /* Set checksum start offset. */
2897 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) &
2898 TD_PLOAD_OFFSET_MASK;
2899 /* Set checksum insertion position of TCP/UDP. */
2900 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) <<
2901 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK;
2902 #else
2903 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
2904 cflags |= TD_IPCSUM;
2905 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
2906 cflags |= TD_TCPCSUM;
2907 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2908 cflags |= TD_UDPCSUM;
2909 /* Set TCP/UDP header offset. */
2910 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) &
2911 TD_L4HDR_OFFSET_MASK;
2912 #endif
2913 }
2914 for (; idx < nsegs; idx++) {
2915 desc = &sc->alc_rdata.alc_tx_ring[prod];
2916 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag);
2917 desc->flags = htole32(cflags);
2918 desc->addr = htole64(txsegs[idx].ds_addr);
2919 sc->alc_cdata.alc_tx_cnt++;
2920 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
2921 }
2922 /* Update producer index. */
2923 sc->alc_cdata.alc_tx_prod = prod;
2924
2925 /* Finally set EOP on the last descriptor. */
2926 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT;
2927 desc = &sc->alc_rdata.alc_tx_ring[prod];
2928 desc->flags |= htole32(TD_EOP);
2929
2930 /* Swap dmamap of the first and the last. */
2931 txd = &sc->alc_cdata.alc_txdesc[prod];
2932 map = txd_last->tx_dmamap;
2933 txd_last->tx_dmamap = txd->tx_dmamap;
2934 txd->tx_dmamap = map;
2935 txd->tx_m = m;
2936
2937 return (0);
2938 }
2939
2940 static void
alc_start(if_t ifp)2941 alc_start(if_t ifp)
2942 {
2943 struct alc_softc *sc;
2944
2945 sc = if_getsoftc(ifp);
2946 ALC_LOCK(sc);
2947 alc_start_locked(ifp);
2948 ALC_UNLOCK(sc);
2949 }
2950
2951 static void
alc_start_locked(if_t ifp)2952 alc_start_locked(if_t ifp)
2953 {
2954 struct alc_softc *sc;
2955 struct mbuf *m_head;
2956 int enq;
2957
2958 sc = if_getsoftc(ifp);
2959
2960 ALC_LOCK_ASSERT(sc);
2961
2962 /* Reclaim transmitted frames. */
2963 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT)
2964 alc_txeof(sc);
2965
2966 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2967 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0)
2968 return;
2969
2970 for (enq = 0; !if_sendq_empty(ifp); ) {
2971 m_head = if_dequeue(ifp);
2972 if (m_head == NULL)
2973 break;
2974 /*
2975 * Pack the data into the transmit ring. If we
2976 * don't have room, set the OACTIVE flag and wait
2977 * for the NIC to drain the ring.
2978 */
2979 if (alc_encap(sc, &m_head)) {
2980 if (m_head == NULL)
2981 break;
2982 if_sendq_prepend(ifp, m_head);
2983 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
2984 break;
2985 }
2986
2987 enq++;
2988 /*
2989 * If there's a BPF listener, bounce a copy of this frame
2990 * to him.
2991 */
2992 ETHER_BPF_MTAP(ifp, m_head);
2993 }
2994
2995 if (enq > 0)
2996 alc_start_tx(sc);
2997 }
2998
2999 static void
alc_start_tx(struct alc_softc * sc)3000 alc_start_tx(struct alc_softc *sc)
3001 {
3002
3003 /* Sync descriptors. */
3004 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
3005 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE);
3006 /* Kick. Assume we're using normal Tx priority queue. */
3007 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
3008 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX,
3009 (uint16_t)sc->alc_cdata.alc_tx_prod);
3010 else
3011 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX,
3012 (sc->alc_cdata.alc_tx_prod <<
3013 MBOX_TD_PROD_LO_IDX_SHIFT) &
3014 MBOX_TD_PROD_LO_IDX_MASK);
3015 /* Set a timeout in case the chip goes out to lunch. */
3016 sc->alc_watchdog_timer = ALC_TX_TIMEOUT;
3017 }
3018
3019 static void
alc_watchdog(struct alc_softc * sc)3020 alc_watchdog(struct alc_softc *sc)
3021 {
3022 if_t ifp;
3023
3024 ALC_LOCK_ASSERT(sc);
3025
3026 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer)
3027 return;
3028
3029 ifp = sc->alc_ifp;
3030 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) {
3031 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n");
3032 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3033 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
3034 alc_init_locked(sc);
3035 return;
3036 }
3037 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n");
3038 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3039 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
3040 alc_init_locked(sc);
3041 if (!if_sendq_empty(ifp))
3042 alc_start_locked(ifp);
3043 }
3044
3045 static int
alc_ioctl(if_t ifp,u_long cmd,caddr_t data)3046 alc_ioctl(if_t ifp, u_long cmd, caddr_t data)
3047 {
3048 struct alc_softc *sc;
3049 struct ifreq *ifr;
3050 struct mii_data *mii;
3051 int error, mask;
3052
3053 sc = if_getsoftc(ifp);
3054 ifr = (struct ifreq *)data;
3055 error = 0;
3056 switch (cmd) {
3057 case SIOCSIFMTU:
3058 if (ifr->ifr_mtu < ETHERMIN ||
3059 ifr->ifr_mtu > (sc->alc_ident->max_framelen -
3060 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) ||
3061 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 &&
3062 ifr->ifr_mtu > ETHERMTU))
3063 error = EINVAL;
3064 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
3065 ALC_LOCK(sc);
3066 if_setmtu(ifp, ifr->ifr_mtu);
3067 /* AR81[3567]x has 13 bits MSS field. */
3068 if (if_getmtu(ifp) > ALC_TSO_MTU &&
3069 (if_getcapenable(ifp) & IFCAP_TSO4) != 0) {
3070 if_setcapenablebit(ifp, 0, IFCAP_TSO4);
3071 if_sethwassistbits(ifp, 0, CSUM_TSO);
3072 VLAN_CAPABILITIES(ifp);
3073 }
3074 ALC_UNLOCK(sc);
3075 }
3076 break;
3077 case SIOCSIFFLAGS:
3078 ALC_LOCK(sc);
3079 if ((if_getflags(ifp) & IFF_UP) != 0) {
3080 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 &&
3081 ((if_getflags(ifp) ^ sc->alc_if_flags) &
3082 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
3083 alc_rxfilter(sc);
3084 else
3085 alc_init_locked(sc);
3086 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
3087 alc_stop(sc);
3088 sc->alc_if_flags = if_getflags(ifp);
3089 ALC_UNLOCK(sc);
3090 break;
3091 case SIOCADDMULTI:
3092 case SIOCDELMULTI:
3093 ALC_LOCK(sc);
3094 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
3095 alc_rxfilter(sc);
3096 ALC_UNLOCK(sc);
3097 break;
3098 case SIOCSIFMEDIA:
3099 case SIOCGIFMEDIA:
3100 mii = device_get_softc(sc->alc_miibus);
3101 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
3102 break;
3103 case SIOCSIFCAP:
3104 ALC_LOCK(sc);
3105 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
3106 if ((mask & IFCAP_TXCSUM) != 0 &&
3107 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
3108 if_togglecapenable(ifp, IFCAP_TXCSUM);
3109 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
3110 if_sethwassistbits(ifp, ALC_CSUM_FEATURES, 0);
3111 else
3112 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES);
3113 }
3114 if ((mask & IFCAP_TSO4) != 0 &&
3115 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
3116 if_togglecapenable(ifp, IFCAP_TSO4);
3117 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) {
3118 /* AR81[3567]x has 13 bits MSS field. */
3119 if (if_getmtu(ifp) > ALC_TSO_MTU) {
3120 if_setcapenablebit(ifp, 0, IFCAP_TSO4);
3121 if_sethwassistbits(ifp, 0, CSUM_TSO);
3122 } else
3123 if_sethwassistbits(ifp, CSUM_TSO, 0);
3124 } else
3125 if_sethwassistbits(ifp, 0, CSUM_TSO);
3126 }
3127 if ((mask & IFCAP_WOL_MCAST) != 0 &&
3128 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0)
3129 if_togglecapenable(ifp, IFCAP_WOL_MCAST);
3130 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
3131 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
3132 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
3133 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3134 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
3135 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
3136 alc_rxvlan(sc);
3137 }
3138 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
3139 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
3140 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
3141 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
3142 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
3143 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
3144 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
3145 if_setcapenablebit(ifp, 0,
3146 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
3147 ALC_UNLOCK(sc);
3148 VLAN_CAPABILITIES(ifp);
3149 break;
3150 default:
3151 error = ether_ioctl(ifp, cmd, data);
3152 break;
3153 }
3154
3155 return (error);
3156 }
3157
3158 static void
alc_mac_config(struct alc_softc * sc)3159 alc_mac_config(struct alc_softc *sc)
3160 {
3161 struct mii_data *mii;
3162 uint32_t reg;
3163
3164 ALC_LOCK_ASSERT(sc);
3165
3166 mii = device_get_softc(sc->alc_miibus);
3167 reg = CSR_READ_4(sc, ALC_MAC_CFG);
3168 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
3169 MAC_CFG_SPEED_MASK);
3170 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
3171 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
3172 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
3173 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2)
3174 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
3175 /* Reprogram MAC with resolved speed/duplex. */
3176 switch (IFM_SUBTYPE(mii->mii_media_active)) {
3177 case IFM_10_T:
3178 case IFM_100_TX:
3179 reg |= MAC_CFG_SPEED_10_100;
3180 break;
3181 case IFM_1000_T:
3182 reg |= MAC_CFG_SPEED_1000;
3183 break;
3184 }
3185 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
3186 reg |= MAC_CFG_FULL_DUPLEX;
3187 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
3188 reg |= MAC_CFG_TX_FC;
3189 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
3190 reg |= MAC_CFG_RX_FC;
3191 }
3192 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3193 }
3194
3195 static void
alc_stats_clear(struct alc_softc * sc)3196 alc_stats_clear(struct alc_softc *sc)
3197 {
3198 struct smb sb, *smb;
3199 uint32_t *reg;
3200 int i;
3201
3202 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
3203 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
3204 sc->alc_cdata.alc_smb_map,
3205 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3206 smb = sc->alc_rdata.alc_smb;
3207 /* Update done, clear. */
3208 smb->updated = 0;
3209 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
3210 sc->alc_cdata.alc_smb_map,
3211 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3212 } else {
3213 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
3214 reg++) {
3215 CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
3216 i += sizeof(uint32_t);
3217 }
3218 /* Read Tx statistics. */
3219 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
3220 reg++) {
3221 CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
3222 i += sizeof(uint32_t);
3223 }
3224 }
3225 }
3226
3227 static void
alc_stats_update(struct alc_softc * sc)3228 alc_stats_update(struct alc_softc *sc)
3229 {
3230 struct alc_hw_stats *stat;
3231 struct smb sb, *smb;
3232 if_t ifp;
3233 uint32_t *reg;
3234 int i;
3235
3236 ALC_LOCK_ASSERT(sc);
3237
3238 ifp = sc->alc_ifp;
3239 stat = &sc->alc_stats;
3240 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
3241 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
3242 sc->alc_cdata.alc_smb_map,
3243 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3244 smb = sc->alc_rdata.alc_smb;
3245 if (smb->updated == 0)
3246 return;
3247 } else {
3248 smb = &sb;
3249 /* Read Rx statistics. */
3250 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
3251 reg++) {
3252 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
3253 i += sizeof(uint32_t);
3254 }
3255 /* Read Tx statistics. */
3256 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
3257 reg++) {
3258 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
3259 i += sizeof(uint32_t);
3260 }
3261 }
3262
3263 /* Rx stats. */
3264 stat->rx_frames += smb->rx_frames;
3265 stat->rx_bcast_frames += smb->rx_bcast_frames;
3266 stat->rx_mcast_frames += smb->rx_mcast_frames;
3267 stat->rx_pause_frames += smb->rx_pause_frames;
3268 stat->rx_control_frames += smb->rx_control_frames;
3269 stat->rx_crcerrs += smb->rx_crcerrs;
3270 stat->rx_lenerrs += smb->rx_lenerrs;
3271 stat->rx_bytes += smb->rx_bytes;
3272 stat->rx_runts += smb->rx_runts;
3273 stat->rx_fragments += smb->rx_fragments;
3274 stat->rx_pkts_64 += smb->rx_pkts_64;
3275 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
3276 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
3277 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
3278 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
3279 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
3280 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
3281 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
3282 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
3283 stat->rx_rrs_errs += smb->rx_rrs_errs;
3284 stat->rx_alignerrs += smb->rx_alignerrs;
3285 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
3286 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
3287 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
3288
3289 /* Tx stats. */
3290 stat->tx_frames += smb->tx_frames;
3291 stat->tx_bcast_frames += smb->tx_bcast_frames;
3292 stat->tx_mcast_frames += smb->tx_mcast_frames;
3293 stat->tx_pause_frames += smb->tx_pause_frames;
3294 stat->tx_excess_defer += smb->tx_excess_defer;
3295 stat->tx_control_frames += smb->tx_control_frames;
3296 stat->tx_deferred += smb->tx_deferred;
3297 stat->tx_bytes += smb->tx_bytes;
3298 stat->tx_pkts_64 += smb->tx_pkts_64;
3299 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
3300 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
3301 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
3302 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
3303 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
3304 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
3305 stat->tx_single_colls += smb->tx_single_colls;
3306 stat->tx_multi_colls += smb->tx_multi_colls;
3307 stat->tx_late_colls += smb->tx_late_colls;
3308 stat->tx_excess_colls += smb->tx_excess_colls;
3309 stat->tx_underrun += smb->tx_underrun;
3310 stat->tx_desc_underrun += smb->tx_desc_underrun;
3311 stat->tx_lenerrs += smb->tx_lenerrs;
3312 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
3313 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
3314 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
3315
3316 /* Update counters in ifnet. */
3317 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames);
3318
3319 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls +
3320 smb->tx_multi_colls * 2 + smb->tx_late_colls +
3321 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT);
3322
3323 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls +
3324 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated);
3325
3326 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames);
3327
3328 if_inc_counter(ifp, IFCOUNTER_IERRORS,
3329 smb->rx_crcerrs + smb->rx_lenerrs +
3330 smb->rx_runts + smb->rx_pkts_truncated +
3331 smb->rx_fifo_oflows + smb->rx_rrs_errs +
3332 smb->rx_alignerrs);
3333
3334 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
3335 /* Update done, clear. */
3336 smb->updated = 0;
3337 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
3338 sc->alc_cdata.alc_smb_map,
3339 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3340 }
3341 }
3342
3343 static int
alc_intr(void * arg)3344 alc_intr(void *arg)
3345 {
3346 struct alc_softc *sc;
3347 uint32_t status;
3348
3349 sc = (struct alc_softc *)arg;
3350
3351 if (sc->alc_flags & ALC_FLAG_MT) {
3352 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task);
3353 return (FILTER_HANDLED);
3354 }
3355
3356 status = CSR_READ_4(sc, ALC_INTR_STATUS);
3357 if ((status & ALC_INTRS) == 0)
3358 return (FILTER_STRAY);
3359 /* Disable interrupts. */
3360 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT);
3361 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task);
3362
3363 return (FILTER_HANDLED);
3364 }
3365
3366 static void
alc_int_task(void * arg,int pending)3367 alc_int_task(void *arg, int pending)
3368 {
3369 struct alc_softc *sc;
3370 if_t ifp;
3371 uint32_t status;
3372 int more;
3373
3374 sc = (struct alc_softc *)arg;
3375 ifp = sc->alc_ifp;
3376
3377 status = CSR_READ_4(sc, ALC_INTR_STATUS);
3378 ALC_LOCK(sc);
3379 if (sc->alc_morework != 0) {
3380 sc->alc_morework = 0;
3381 status |= INTR_RX_PKT;
3382 }
3383 if ((status & ALC_INTRS) == 0)
3384 goto done;
3385
3386 /* Acknowledge interrupts but still disable interrupts. */
3387 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT);
3388
3389 more = 0;
3390 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
3391 if ((status & INTR_RX_PKT) != 0) {
3392 more = alc_rxintr(sc, sc->alc_process_limit);
3393 if (more == EAGAIN)
3394 sc->alc_morework = 1;
3395 else if (more == EIO) {
3396 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
3397 alc_init_locked(sc);
3398 ALC_UNLOCK(sc);
3399 return;
3400 }
3401 }
3402 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |
3403 INTR_TXQ_TO_RST)) != 0) {
3404 if ((status & INTR_DMA_RD_TO_RST) != 0)
3405 device_printf(sc->alc_dev,
3406 "DMA read error! -- resetting\n");
3407 if ((status & INTR_DMA_WR_TO_RST) != 0)
3408 device_printf(sc->alc_dev,
3409 "DMA write error! -- resetting\n");
3410 if ((status & INTR_TXQ_TO_RST) != 0)
3411 device_printf(sc->alc_dev,
3412 "TxQ reset! -- resetting\n");
3413 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
3414 alc_init_locked(sc);
3415 ALC_UNLOCK(sc);
3416 return;
3417 }
3418 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 &&
3419 !if_sendq_empty(ifp))
3420 alc_start_locked(ifp);
3421 }
3422
3423 if (more == EAGAIN ||
3424 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) {
3425 ALC_UNLOCK(sc);
3426 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task);
3427 return;
3428 }
3429
3430 done:
3431 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
3432 /* Re-enable interrupts if we're running. */
3433 if (sc->alc_flags & ALC_FLAG_MT)
3434 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0);
3435 else
3436 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF);
3437 }
3438 ALC_UNLOCK(sc);
3439 }
3440
3441 static void
alc_txeof(struct alc_softc * sc)3442 alc_txeof(struct alc_softc *sc)
3443 {
3444 if_t ifp;
3445 struct alc_txdesc *txd;
3446 uint32_t cons, prod;
3447
3448 ALC_LOCK_ASSERT(sc);
3449
3450 ifp = sc->alc_ifp;
3451
3452 if (sc->alc_cdata.alc_tx_cnt == 0)
3453 return;
3454 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
3455 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE);
3456 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
3457 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag,
3458 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD);
3459 prod = sc->alc_rdata.alc_cmb->cons;
3460 } else {
3461 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
3462 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX);
3463 else {
3464 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX);
3465 /* Assume we're using normal Tx priority queue. */
3466 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >>
3467 MBOX_TD_CONS_LO_IDX_SHIFT;
3468 }
3469 }
3470 cons = sc->alc_cdata.alc_tx_cons;
3471 /*
3472 * Go through our Tx list and free mbufs for those
3473 * frames which have been transmitted.
3474 */
3475 for (; cons != prod; ALC_DESC_INC(cons, ALC_TX_RING_CNT)) {
3476 if (sc->alc_cdata.alc_tx_cnt <= 0)
3477 break;
3478 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
3479 sc->alc_cdata.alc_tx_cnt--;
3480 txd = &sc->alc_cdata.alc_txdesc[cons];
3481 if (txd->tx_m != NULL) {
3482 /* Reclaim transmitted mbufs. */
3483 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag,
3484 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3485 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag,
3486 txd->tx_dmamap);
3487 m_freem(txd->tx_m);
3488 txd->tx_m = NULL;
3489 }
3490 }
3491
3492 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
3493 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag,
3494 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD);
3495 sc->alc_cdata.alc_tx_cons = cons;
3496 /*
3497 * Unarm watchdog timer only when there is no pending
3498 * frames in Tx queue.
3499 */
3500 if (sc->alc_cdata.alc_tx_cnt == 0)
3501 sc->alc_watchdog_timer = 0;
3502 }
3503
3504 static int
alc_newbuf(struct alc_softc * sc,struct alc_rxdesc * rxd)3505 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd)
3506 {
3507 struct mbuf *m;
3508 bus_dma_segment_t segs[1];
3509 bus_dmamap_t map;
3510 int nsegs;
3511
3512 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
3513 if (m == NULL)
3514 return (ENOBUFS);
3515 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX;
3516 #ifndef __NO_STRICT_ALIGNMENT
3517 m_adj(m, sizeof(uint64_t));
3518 #endif
3519
3520 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag,
3521 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3522 m_freem(m);
3523 return (ENOBUFS);
3524 }
3525 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3526
3527 if (rxd->rx_m != NULL) {
3528 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap,
3529 BUS_DMASYNC_POSTREAD);
3530 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap);
3531 }
3532 map = rxd->rx_dmamap;
3533 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap;
3534 sc->alc_cdata.alc_rx_sparemap = map;
3535 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap,
3536 BUS_DMASYNC_PREREAD);
3537 rxd->rx_m = m;
3538 rxd->rx_desc->addr = htole64(segs[0].ds_addr);
3539 return (0);
3540 }
3541
3542 static int
alc_rxintr(struct alc_softc * sc,int count)3543 alc_rxintr(struct alc_softc *sc, int count)
3544 {
3545 if_t ifp;
3546 struct rx_rdesc *rrd;
3547 uint32_t nsegs, status;
3548 int rr_cons, prog;
3549
3550 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
3551 sc->alc_cdata.alc_rr_ring_map,
3552 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3553 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
3554 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE);
3555 rr_cons = sc->alc_cdata.alc_rr_cons;
3556 ifp = sc->alc_ifp;
3557 for (prog = 0; (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0;) {
3558 if (count-- <= 0)
3559 break;
3560 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons];
3561 status = le32toh(rrd->status);
3562 if ((status & RRD_VALID) == 0)
3563 break;
3564 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo));
3565 if (nsegs == 0) {
3566 /* This should not happen! */
3567 device_printf(sc->alc_dev,
3568 "unexpected segment count -- resetting\n");
3569 return (EIO);
3570 }
3571 alc_rxeof(sc, rrd);
3572 /* Clear Rx return status. */
3573 rrd->status = 0;
3574 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT);
3575 sc->alc_cdata.alc_rx_cons += nsegs;
3576 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT;
3577 prog += nsegs;
3578 }
3579
3580 if (prog > 0) {
3581 /* Update the consumer index. */
3582 sc->alc_cdata.alc_rr_cons = rr_cons;
3583 /* Sync Rx return descriptors. */
3584 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
3585 sc->alc_cdata.alc_rr_ring_map,
3586 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3587 /*
3588 * Sync updated Rx descriptors such that controller see
3589 * modified buffer addresses.
3590 */
3591 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
3592 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE);
3593 /*
3594 * Let controller know availability of new Rx buffers.
3595 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors
3596 * it may be possible to update ALC_MBOX_RD0_PROD_IDX
3597 * only when Rx buffer pre-fetching is required. In
3598 * addition we already set ALC_RX_RD_FREE_THRESH to
3599 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However
3600 * it still seems that pre-fetching needs more
3601 * experimentation.
3602 */
3603 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
3604 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX,
3605 (uint16_t)sc->alc_cdata.alc_rx_cons);
3606 else
3607 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
3608 sc->alc_cdata.alc_rx_cons);
3609 }
3610
3611 return (count > 0 ? 0 : EAGAIN);
3612 }
3613
3614 #ifndef __NO_STRICT_ALIGNMENT
3615 static struct mbuf *
alc_fixup_rx(if_t ifp,struct mbuf * m)3616 alc_fixup_rx(if_t ifp, struct mbuf *m)
3617 {
3618 struct mbuf *n;
3619 int i;
3620 uint16_t *src, *dst;
3621
3622 src = mtod(m, uint16_t *);
3623 dst = src - 3;
3624
3625 if (m->m_next == NULL) {
3626 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
3627 *dst++ = *src++;
3628 m->m_data -= 6;
3629 return (m);
3630 }
3631 /*
3632 * Append a new mbuf to received mbuf chain and copy ethernet
3633 * header from the mbuf chain. This can save lots of CPU
3634 * cycles for jumbo frame.
3635 */
3636 MGETHDR(n, M_NOWAIT, MT_DATA);
3637 if (n == NULL) {
3638 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
3639 m_freem(m);
3640 return (NULL);
3641 }
3642 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
3643 m->m_data += ETHER_HDR_LEN;
3644 m->m_len -= ETHER_HDR_LEN;
3645 n->m_len = ETHER_HDR_LEN;
3646 M_MOVE_PKTHDR(n, m);
3647 n->m_next = m;
3648 return (n);
3649 }
3650 #endif
3651
3652 /* Receive a frame. */
3653 static void
alc_rxeof(struct alc_softc * sc,struct rx_rdesc * rrd)3654 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd)
3655 {
3656 struct alc_rxdesc *rxd;
3657 if_t ifp;
3658 struct mbuf *mp, *m;
3659 uint32_t rdinfo, status, vtag;
3660 int count, nsegs, rx_cons;
3661
3662 ifp = sc->alc_ifp;
3663 status = le32toh(rrd->status);
3664 rdinfo = le32toh(rrd->rdinfo);
3665 rx_cons = RRD_RD_IDX(rdinfo);
3666 nsegs = RRD_RD_CNT(rdinfo);
3667
3668 sc->alc_cdata.alc_rxlen = RRD_BYTES(status);
3669 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) {
3670 /*
3671 * We want to pass the following frames to upper
3672 * layer regardless of error status of Rx return
3673 * ring.
3674 *
3675 * o IP/TCP/UDP checksum is bad.
3676 * o frame length and protocol specific length
3677 * does not match.
3678 *
3679 * Force network stack compute checksum for
3680 * errored frames.
3681 */
3682 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK;
3683 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN |
3684 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0)
3685 return;
3686 }
3687
3688 for (count = 0; count < nsegs; count++,
3689 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) {
3690 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons];
3691 mp = rxd->rx_m;
3692 /* Add a new receive buffer to the ring. */
3693 if (alc_newbuf(sc, rxd) != 0) {
3694 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
3695 /* Reuse Rx buffers. */
3696 if (sc->alc_cdata.alc_rxhead != NULL)
3697 m_freem(sc->alc_cdata.alc_rxhead);
3698 break;
3699 }
3700
3701 /*
3702 * Assume we've received a full sized frame.
3703 * Actual size is fixed when we encounter the end of
3704 * multi-segmented frame.
3705 */
3706 mp->m_len = sc->alc_buf_size;
3707
3708 /* Chain received mbufs. */
3709 if (sc->alc_cdata.alc_rxhead == NULL) {
3710 sc->alc_cdata.alc_rxhead = mp;
3711 sc->alc_cdata.alc_rxtail = mp;
3712 } else {
3713 mp->m_flags &= ~M_PKTHDR;
3714 sc->alc_cdata.alc_rxprev_tail =
3715 sc->alc_cdata.alc_rxtail;
3716 sc->alc_cdata.alc_rxtail->m_next = mp;
3717 sc->alc_cdata.alc_rxtail = mp;
3718 }
3719
3720 if (count == nsegs - 1) {
3721 /* Last desc. for this frame. */
3722 m = sc->alc_cdata.alc_rxhead;
3723 m->m_flags |= M_PKTHDR;
3724 /*
3725 * It seems that L1C/L2C controller has no way
3726 * to tell hardware to strip CRC bytes.
3727 */
3728 m->m_pkthdr.len =
3729 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN;
3730 if (nsegs > 1) {
3731 /* Set last mbuf size. */
3732 mp->m_len = sc->alc_cdata.alc_rxlen -
3733 (nsegs - 1) * sc->alc_buf_size;
3734 /* Remove the CRC bytes in chained mbufs. */
3735 if (mp->m_len <= ETHER_CRC_LEN) {
3736 sc->alc_cdata.alc_rxtail =
3737 sc->alc_cdata.alc_rxprev_tail;
3738 sc->alc_cdata.alc_rxtail->m_len -=
3739 (ETHER_CRC_LEN - mp->m_len);
3740 sc->alc_cdata.alc_rxtail->m_next = NULL;
3741 m_freem(mp);
3742 } else {
3743 mp->m_len -= ETHER_CRC_LEN;
3744 }
3745 } else
3746 m->m_len = m->m_pkthdr.len;
3747 m->m_pkthdr.rcvif = ifp;
3748 /*
3749 * Due to hardware bugs, Rx checksum offloading
3750 * was intentionally disabled.
3751 */
3752 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 &&
3753 (status & RRD_VLAN_TAG) != 0) {
3754 vtag = RRD_VLAN(le32toh(rrd->vtag));
3755 m->m_pkthdr.ether_vtag = ntohs(vtag);
3756 m->m_flags |= M_VLANTAG;
3757 }
3758 #ifndef __NO_STRICT_ALIGNMENT
3759 m = alc_fixup_rx(ifp, m);
3760 if (m != NULL)
3761 #endif
3762 {
3763 /* Pass it on. */
3764 ALC_UNLOCK(sc);
3765 if_input(ifp, m);
3766 ALC_LOCK(sc);
3767 }
3768 }
3769 }
3770 /* Reset mbuf chains. */
3771 ALC_RXCHAIN_RESET(sc);
3772 }
3773
3774 static void
alc_tick(void * arg)3775 alc_tick(void *arg)
3776 {
3777 struct alc_softc *sc;
3778 struct mii_data *mii;
3779
3780 sc = (struct alc_softc *)arg;
3781
3782 ALC_LOCK_ASSERT(sc);
3783
3784 mii = device_get_softc(sc->alc_miibus);
3785 mii_tick(mii);
3786 alc_stats_update(sc);
3787 /*
3788 * alc(4) does not rely on Tx completion interrupts to reclaim
3789 * transferred buffers. Instead Tx completion interrupts are
3790 * used to hint for scheduling Tx task. So it's necessary to
3791 * release transmitted buffers by kicking Tx completion
3792 * handler. This limits the maximum reclamation delay to a hz.
3793 */
3794 alc_txeof(sc);
3795 alc_watchdog(sc);
3796 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc);
3797 }
3798
3799 static void
alc_osc_reset(struct alc_softc * sc)3800 alc_osc_reset(struct alc_softc *sc)
3801 {
3802 uint32_t reg;
3803
3804 reg = CSR_READ_4(sc, ALC_MISC3);
3805 reg &= ~MISC3_25M_BY_SW;
3806 reg |= MISC3_25M_NOTO_INTNL;
3807 CSR_WRITE_4(sc, ALC_MISC3, reg);
3808
3809 reg = CSR_READ_4(sc, ALC_MISC);
3810 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) {
3811 /*
3812 * Restore over-current protection default value.
3813 * This value could be reset by MAC reset.
3814 */
3815 reg &= ~MISC_PSW_OCP_MASK;
3816 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT);
3817 reg &= ~MISC_INTNLOSC_OPEN;
3818 CSR_WRITE_4(sc, ALC_MISC, reg);
3819 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);
3820 reg = CSR_READ_4(sc, ALC_MISC2);
3821 reg &= ~MISC2_CALB_START;
3822 CSR_WRITE_4(sc, ALC_MISC2, reg);
3823 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START);
3824
3825 } else {
3826 reg &= ~MISC_INTNLOSC_OPEN;
3827 /* Disable isolate for revision A devices. */
3828 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1)
3829 reg &= ~MISC_ISO_ENB;
3830 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);
3831 CSR_WRITE_4(sc, ALC_MISC, reg);
3832 }
3833
3834 DELAY(20);
3835 }
3836
3837 static void
alc_reset(struct alc_softc * sc)3838 alc_reset(struct alc_softc *sc)
3839 {
3840 uint32_t pmcfg, reg;
3841 int i;
3842
3843 pmcfg = 0;
3844 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3845 /* Reset workaround. */
3846 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1);
3847 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
3848 (sc->alc_rev & 0x01) != 0) {
3849 /* Disable L0s/L1s before reset. */
3850 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
3851 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB))
3852 != 0) {
3853 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB |
3854 PM_CFG_ASPM_L1_ENB);
3855 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
3856 }
3857 }
3858 }
3859 reg = CSR_READ_4(sc, ALC_MASTER_CFG);
3860 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET;
3861 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
3862
3863 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3864 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
3865 DELAY(10);
3866 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0)
3867 break;
3868 }
3869 if (i == 0)
3870 device_printf(sc->alc_dev, "MAC reset timeout!\n");
3871 }
3872 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
3873 DELAY(10);
3874 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
3875 break;
3876 }
3877 if (i == 0)
3878 device_printf(sc->alc_dev, "master reset timeout!\n");
3879
3880 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
3881 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
3882 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC |
3883 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
3884 break;
3885 DELAY(10);
3886 }
3887 if (i == 0)
3888 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg);
3889
3890 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3891 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
3892 (sc->alc_rev & 0x01) != 0) {
3893 reg = CSR_READ_4(sc, ALC_MASTER_CFG);
3894 reg |= MASTER_CLK_SEL_DIS;
3895 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
3896 /* Restore L0s/L1s config. */
3897 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB))
3898 != 0)
3899 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
3900 }
3901
3902 alc_osc_reset(sc);
3903 reg = CSR_READ_4(sc, ALC_MISC3);
3904 reg &= ~MISC3_25M_BY_SW;
3905 reg |= MISC3_25M_NOTO_INTNL;
3906 CSR_WRITE_4(sc, ALC_MISC3, reg);
3907 reg = CSR_READ_4(sc, ALC_MISC);
3908 reg &= ~MISC_INTNLOSC_OPEN;
3909 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1)
3910 reg &= ~MISC_ISO_ENB;
3911 CSR_WRITE_4(sc, ALC_MISC, reg);
3912 DELAY(20);
3913 }
3914 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
3915 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
3916 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2)
3917 CSR_WRITE_4(sc, ALC_SERDES_LOCK,
3918 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN |
3919 SERDES_PHY_CLK_SLOWDOWN);
3920 }
3921
3922 static void
alc_init(void * xsc)3923 alc_init(void *xsc)
3924 {
3925 struct alc_softc *sc;
3926
3927 sc = (struct alc_softc *)xsc;
3928 ALC_LOCK(sc);
3929 alc_init_locked(sc);
3930 ALC_UNLOCK(sc);
3931 }
3932
3933 static void
alc_init_locked(struct alc_softc * sc)3934 alc_init_locked(struct alc_softc *sc)
3935 {
3936 if_t ifp;
3937 uint8_t eaddr[ETHER_ADDR_LEN];
3938 bus_addr_t paddr;
3939 uint32_t reg, rxf_hi, rxf_lo;
3940
3941 ALC_LOCK_ASSERT(sc);
3942
3943 ifp = sc->alc_ifp;
3944
3945 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
3946 return;
3947 /*
3948 * Cancel any pending I/O.
3949 */
3950 alc_stop(sc);
3951 /*
3952 * Reset the chip to a known state.
3953 */
3954 alc_reset(sc);
3955
3956 /* Initialize Rx descriptors. */
3957 if (alc_init_rx_ring(sc) != 0) {
3958 device_printf(sc->alc_dev, "no memory for Rx buffers.\n");
3959 alc_stop(sc);
3960 return;
3961 }
3962 alc_init_rr_ring(sc);
3963 alc_init_tx_ring(sc);
3964 alc_init_cmb(sc);
3965 alc_init_smb(sc);
3966
3967 /* Enable all clocks. */
3968 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3969 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB |
3970 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB |
3971 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB |
3972 CLK_GATING_RXMAC_ENB);
3973 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0)
3974 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER,
3975 IDLE_DECISN_TIMER_DEFAULT_1MS);
3976 } else
3977 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0);
3978
3979 /* Reprogram the station address. */
3980 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN);
3981 CSR_WRITE_4(sc, ALC_PAR0,
3982 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
3983 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]);
3984 /*
3985 * Clear WOL status and disable all WOL feature as WOL
3986 * would interfere Rx operation under normal environments.
3987 */
3988 CSR_READ_4(sc, ALC_WOL_CFG);
3989 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
3990 /* Set Tx descriptor base addresses. */
3991 paddr = sc->alc_rdata.alc_tx_ring_paddr;
3992 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
3993 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
3994 /* We don't use high priority ring. */
3995 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0);
3996 /* Set Tx descriptor counter. */
3997 CSR_WRITE_4(sc, ALC_TD_RING_CNT,
3998 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK);
3999 /* Set Rx descriptor base addresses. */
4000 paddr = sc->alc_rdata.alc_rx_ring_paddr;
4001 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
4002 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
4003 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4004 /* We use one Rx ring. */
4005 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0);
4006 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0);
4007 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0);
4008 }
4009 /* Set Rx descriptor counter. */
4010 CSR_WRITE_4(sc, ALC_RD_RING_CNT,
4011 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK);
4012
4013 /*
4014 * Let hardware split jumbo frames into alc_max_buf_sized chunks.
4015 * if it do not fit the buffer size. Rx return descriptor holds
4016 * a counter that indicates how many fragments were made by the
4017 * hardware. The buffer size should be multiple of 8 bytes.
4018 * Since hardware has limit on the size of buffer size, always
4019 * use the maximum value.
4020 * For strict-alignment architectures make sure to reduce buffer
4021 * size by 8 bytes to make room for alignment fixup.
4022 */
4023 #ifndef __NO_STRICT_ALIGNMENT
4024 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t);
4025 #else
4026 sc->alc_buf_size = RX_BUF_SIZE_MAX;
4027 #endif
4028 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size);
4029
4030 paddr = sc->alc_rdata.alc_rr_ring_paddr;
4031 /* Set Rx return descriptor base addresses. */
4032 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
4033 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4034 /* We use one Rx return ring. */
4035 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0);
4036 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0);
4037 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0);
4038 }
4039 /* Set Rx return descriptor counter. */
4040 CSR_WRITE_4(sc, ALC_RRD_RING_CNT,
4041 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK);
4042 paddr = sc->alc_rdata.alc_cmb_paddr;
4043 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
4044 paddr = sc->alc_rdata.alc_smb_paddr;
4045 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
4046 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
4047
4048 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) {
4049 /* Reconfigure SRAM - Vendor magic. */
4050 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0);
4051 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100);
4052 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000);
4053 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0);
4054 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0);
4055 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0);
4056 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000);
4057 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000);
4058 }
4059
4060 /* Tell hardware that we're ready to load DMA blocks. */
4061 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD);
4062
4063 /* Configure interrupt moderation timer. */
4064 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;
4065 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0)
4066 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;
4067 CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
4068 /*
4069 * We don't want to automatic interrupt clear as task queue
4070 * for the interrupt should know interrupt status.
4071 */
4072 reg = CSR_READ_4(sc, ALC_MASTER_CFG);
4073 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
4074 reg |= MASTER_SA_TIMER_ENB;
4075 if (ALC_USECS(sc->alc_int_rx_mod) != 0)
4076 reg |= MASTER_IM_RX_TIMER_ENB;
4077 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 &&
4078 ALC_USECS(sc->alc_int_tx_mod) != 0)
4079 reg |= MASTER_IM_TX_TIMER_ENB;
4080 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
4081 /*
4082 * Disable interrupt re-trigger timer. We don't want automatic
4083 * re-triggering of un-ACKed interrupts.
4084 */
4085 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0));
4086 /* Configure CMB. */
4087 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4088 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3);
4089 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER,
4090 ALC_USECS(sc->alc_int_tx_mod));
4091 } else {
4092 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
4093 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4);
4094 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000));
4095 } else
4096 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0));
4097 }
4098 /*
4099 * Hardware can be configured to issue SMB interrupt based
4100 * on programmed interval. Since there is a callout that is
4101 * invoked for every hz in driver we use that instead of
4102 * relying on periodic SMB interrupt.
4103 */
4104 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0));
4105 /* Clear MAC statistics. */
4106 alc_stats_clear(sc);
4107
4108 /*
4109 * Always use maximum frame size that controller can support.
4110 * Otherwise received frames that has larger frame length
4111 * than alc(4) MTU would be silently dropped in hardware. This
4112 * would make path-MTU discovery hard as sender wouldn't get
4113 * any responses from receiver. alc(4) supports
4114 * multi-fragmented frames on Rx path so it has no issue on
4115 * assembling fragmented frames. Using maximum frame size also
4116 * removes the need to reinitialize hardware when interface
4117 * MTU configuration was changed.
4118 *
4119 * Be conservative in what you do, be liberal in what you
4120 * accept from others - RFC 793.
4121 */
4122 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen);
4123
4124 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4125 /* Disable header split(?) */
4126 CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
4127
4128 /* Configure IPG/IFG parameters. */
4129 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG,
4130 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) &
4131 IPG_IFG_IPGT_MASK) |
4132 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) &
4133 IPG_IFG_MIFG_MASK) |
4134 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) &
4135 IPG_IFG_IPG1_MASK) |
4136 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) &
4137 IPG_IFG_IPG2_MASK));
4138 /* Set parameters for half-duplex media. */
4139 CSR_WRITE_4(sc, ALC_HDPX_CFG,
4140 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
4141 HDPX_CFG_LCOL_MASK) |
4142 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
4143 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
4144 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
4145 HDPX_CFG_ABEBT_MASK) |
4146 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
4147 HDPX_CFG_JAMIPG_MASK));
4148 }
4149
4150 /*
4151 * Set TSO/checksum offload threshold. For frames that is
4152 * larger than this threshold, hardware wouldn't do
4153 * TSO/checksum offloading.
4154 */
4155 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
4156 TSO_OFFLOAD_THRESH_MASK;
4157 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
4158 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB;
4159 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg);
4160 /* Configure TxQ. */
4161 reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<
4162 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK;
4163 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
4164 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2)
4165 reg >>= 1;
4166 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &
4167 TXQ_CFG_TD_BURST_MASK;
4168 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB;
4169 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
4170 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4171 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT |
4172 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT |
4173 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT |
4174 HQTD_CFG_BURST_ENB);
4175 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg);
4176 reg = WRR_PRI_RESTRICT_NONE;
4177 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT |
4178 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT |
4179 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT |
4180 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT);
4181 CSR_WRITE_4(sc, ALC_WRR, reg);
4182 } else {
4183 /* Configure Rx free descriptor pre-fetching. */
4184 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH,
4185 ((RX_RD_FREE_THRESH_HI_DEFAULT <<
4186 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) |
4187 ((RX_RD_FREE_THRESH_LO_DEFAULT <<
4188 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK));
4189 }
4190
4191 /*
4192 * Configure flow control parameters.
4193 * XON : 80% of Rx FIFO
4194 * XOFF : 30% of Rx FIFO
4195 */
4196 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4197 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
4198 reg &= SRAM_RX_FIFO_LEN_MASK;
4199 reg *= 8;
4200 if (reg > 8 * 1024)
4201 reg -= RX_FIFO_PAUSE_816X_RSVD;
4202 else
4203 reg -= RX_BUF_SIZE_MAX;
4204 reg /= 8;
4205 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
4206 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
4207 RX_FIFO_PAUSE_THRESH_LO_MASK) |
4208 (((RX_FIFO_PAUSE_816X_RSVD / 8) <<
4209 RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
4210 RX_FIFO_PAUSE_THRESH_HI_MASK));
4211 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 ||
4212 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) {
4213 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
4214 rxf_hi = (reg * 8) / 10;
4215 rxf_lo = (reg * 3) / 10;
4216 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
4217 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
4218 RX_FIFO_PAUSE_THRESH_LO_MASK) |
4219 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
4220 RX_FIFO_PAUSE_THRESH_HI_MASK));
4221 }
4222
4223 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4224 /* Disable RSS until I understand L1C/L2C's RSS logic. */
4225 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
4226 CSR_WRITE_4(sc, ALC_RSS_CPU, 0);
4227 }
4228
4229 /* Configure RxQ. */
4230 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
4231 RXQ_CFG_RD_BURST_MASK;
4232 reg |= RXQ_CFG_RSS_MODE_DIS;
4233 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4234 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT <<
4235 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) &
4236 RXQ_CFG_816X_IDT_TBL_SIZE_MASK;
4237 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
4238 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
4239 } else {
4240 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 &&
4241 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2)
4242 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
4243 }
4244 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
4245
4246 /* Configure DMA parameters. */
4247 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;
4248 reg |= sc->alc_rcb;
4249 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
4250 reg |= DMA_CFG_CMB_ENB;
4251 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0)
4252 reg |= DMA_CFG_SMB_ENB;
4253 else
4254 reg |= DMA_CFG_SMB_DIS;
4255 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) <<
4256 DMA_CFG_RD_BURST_SHIFT;
4257 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) <<
4258 DMA_CFG_WR_BURST_SHIFT;
4259 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
4260 DMA_CFG_RD_DELAY_CNT_MASK;
4261 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
4262 DMA_CFG_WR_DELAY_CNT_MASK;
4263 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4264 switch (AR816X_REV(sc->alc_rev)) {
4265 case AR816X_REV_A0:
4266 case AR816X_REV_A1:
4267 reg |= DMA_CFG_RD_CHNL_SEL_2;
4268 break;
4269 case AR816X_REV_B0:
4270 /* FALLTHROUGH */
4271 default:
4272 reg |= DMA_CFG_RD_CHNL_SEL_4;
4273 break;
4274 }
4275 }
4276 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
4277
4278 /*
4279 * Configure Tx/Rx MACs.
4280 * - Auto-padding for short frames.
4281 * - Enable CRC generation.
4282 * Actual reconfiguration of MAC for resolved speed/duplex
4283 * is followed after detection of link establishment.
4284 * AR813x/AR815x always does checksum computation regardless
4285 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to
4286 * have bug in protocol field in Rx return structure so
4287 * these controllers can't handle fragmented frames. Disable
4288 * Rx checksum offloading until there is a newer controller
4289 * that has sane implementation.
4290 */
4291 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
4292 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
4293 MAC_CFG_PREAMBLE_MASK);
4294 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
4295 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
4296 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
4297 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2)
4298 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
4299 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0)
4300 reg |= MAC_CFG_SPEED_10_100;
4301 else
4302 reg |= MAC_CFG_SPEED_1000;
4303 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
4304
4305 /* Set up the receive filter. */
4306 alc_rxfilter(sc);
4307 alc_rxvlan(sc);
4308
4309 /* Acknowledge all pending interrupts and clear it. */
4310 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS);
4311 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
4312 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0);
4313
4314 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
4315 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
4316
4317 sc->alc_flags &= ~ALC_FLAG_LINK;
4318 /* Switch to the current media. */
4319 alc_mediachange_locked(sc);
4320
4321 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc);
4322 }
4323
4324 static void
alc_stop(struct alc_softc * sc)4325 alc_stop(struct alc_softc *sc)
4326 {
4327 if_t ifp;
4328 struct alc_txdesc *txd;
4329 struct alc_rxdesc *rxd;
4330 uint32_t reg;
4331 int i;
4332
4333 ALC_LOCK_ASSERT(sc);
4334 /*
4335 * Mark the interface down and cancel the watchdog timer.
4336 */
4337 ifp = sc->alc_ifp;
4338 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
4339 sc->alc_flags &= ~ALC_FLAG_LINK;
4340 callout_stop(&sc->alc_tick_ch);
4341 sc->alc_watchdog_timer = 0;
4342 alc_stats_update(sc);
4343 /* Disable interrupts. */
4344 CSR_WRITE_4(sc, ALC_INTR_MASK, 0);
4345 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
4346 /* Disable DMA. */
4347 reg = CSR_READ_4(sc, ALC_DMA_CFG);
4348 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB);
4349 reg |= DMA_CFG_SMB_DIS;
4350 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
4351 DELAY(1000);
4352 /* Stop Rx/Tx MACs. */
4353 alc_stop_mac(sc);
4354 /* Disable interrupts which might be touched in taskq handler. */
4355 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
4356 /* Disable L0s/L1s */
4357 alc_aspm(sc, 0, IFM_UNKNOWN);
4358 /* Reclaim Rx buffers that have been processed. */
4359 if (sc->alc_cdata.alc_rxhead != NULL)
4360 m_freem(sc->alc_cdata.alc_rxhead);
4361 ALC_RXCHAIN_RESET(sc);
4362 /*
4363 * Free Tx/Rx mbufs still in the queues.
4364 */
4365 for (i = 0; i < ALC_RX_RING_CNT; i++) {
4366 rxd = &sc->alc_cdata.alc_rxdesc[i];
4367 if (rxd->rx_m != NULL) {
4368 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag,
4369 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4370 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag,
4371 rxd->rx_dmamap);
4372 m_freem(rxd->rx_m);
4373 rxd->rx_m = NULL;
4374 }
4375 }
4376 for (i = 0; i < ALC_TX_RING_CNT; i++) {
4377 txd = &sc->alc_cdata.alc_txdesc[i];
4378 if (txd->tx_m != NULL) {
4379 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag,
4380 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
4381 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag,
4382 txd->tx_dmamap);
4383 m_freem(txd->tx_m);
4384 txd->tx_m = NULL;
4385 }
4386 }
4387 }
4388
4389 static void
alc_stop_mac(struct alc_softc * sc)4390 alc_stop_mac(struct alc_softc *sc)
4391 {
4392 uint32_t reg;
4393 int i;
4394
4395 alc_stop_queue(sc);
4396 /* Disable Rx/Tx MAC. */
4397 reg = CSR_READ_4(sc, ALC_MAC_CFG);
4398 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
4399 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
4400 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
4401 }
4402 for (i = ALC_TIMEOUT; i > 0; i--) {
4403 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
4404 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0)
4405 break;
4406 DELAY(10);
4407 }
4408 if (i == 0)
4409 device_printf(sc->alc_dev,
4410 "could not disable Rx/Tx MAC(0x%08x)!\n", reg);
4411 }
4412
4413 static void
alc_start_queue(struct alc_softc * sc)4414 alc_start_queue(struct alc_softc *sc)
4415 {
4416 uint32_t qcfg[] = {
4417 0,
4418 RXQ_CFG_QUEUE0_ENB,
4419 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB,
4420 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB,
4421 RXQ_CFG_ENB
4422 };
4423 uint32_t cfg;
4424
4425 ALC_LOCK_ASSERT(sc);
4426
4427 /* Enable RxQ. */
4428 cfg = CSR_READ_4(sc, ALC_RXQ_CFG);
4429 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4430 cfg &= ~RXQ_CFG_ENB;
4431 cfg |= qcfg[1];
4432 } else
4433 cfg |= RXQ_CFG_QUEUE0_ENB;
4434 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg);
4435 /* Enable TxQ. */
4436 cfg = CSR_READ_4(sc, ALC_TXQ_CFG);
4437 cfg |= TXQ_CFG_ENB;
4438 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg);
4439 }
4440
4441 static void
alc_stop_queue(struct alc_softc * sc)4442 alc_stop_queue(struct alc_softc *sc)
4443 {
4444 uint32_t reg;
4445 int i;
4446
4447 /* Disable RxQ. */
4448 reg = CSR_READ_4(sc, ALC_RXQ_CFG);
4449 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4450 if ((reg & RXQ_CFG_ENB) != 0) {
4451 reg &= ~RXQ_CFG_ENB;
4452 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
4453 }
4454 } else {
4455 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) {
4456 reg &= ~RXQ_CFG_QUEUE0_ENB;
4457 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
4458 }
4459 }
4460 /* Disable TxQ. */
4461 reg = CSR_READ_4(sc, ALC_TXQ_CFG);
4462 if ((reg & TXQ_CFG_ENB) != 0) {
4463 reg &= ~TXQ_CFG_ENB;
4464 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg);
4465 }
4466 DELAY(40);
4467 for (i = ALC_TIMEOUT; i > 0; i--) {
4468 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
4469 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
4470 break;
4471 DELAY(10);
4472 }
4473 if (i == 0)
4474 device_printf(sc->alc_dev,
4475 "could not disable RxQ/TxQ (0x%08x)!\n", reg);
4476 }
4477
4478 static void
alc_init_tx_ring(struct alc_softc * sc)4479 alc_init_tx_ring(struct alc_softc *sc)
4480 {
4481 struct alc_ring_data *rd;
4482 struct alc_txdesc *txd;
4483 int i;
4484
4485 ALC_LOCK_ASSERT(sc);
4486
4487 sc->alc_cdata.alc_tx_prod = 0;
4488 sc->alc_cdata.alc_tx_cons = 0;
4489 sc->alc_cdata.alc_tx_cnt = 0;
4490
4491 rd = &sc->alc_rdata;
4492 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ);
4493 for (i = 0; i < ALC_TX_RING_CNT; i++) {
4494 txd = &sc->alc_cdata.alc_txdesc[i];
4495 txd->tx_m = NULL;
4496 }
4497
4498 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
4499 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE);
4500 }
4501
4502 static int
alc_init_rx_ring(struct alc_softc * sc)4503 alc_init_rx_ring(struct alc_softc *sc)
4504 {
4505 struct alc_ring_data *rd;
4506 struct alc_rxdesc *rxd;
4507 int i;
4508
4509 ALC_LOCK_ASSERT(sc);
4510
4511 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1;
4512 sc->alc_morework = 0;
4513 rd = &sc->alc_rdata;
4514 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ);
4515 for (i = 0; i < ALC_RX_RING_CNT; i++) {
4516 rxd = &sc->alc_cdata.alc_rxdesc[i];
4517 rxd->rx_m = NULL;
4518 rxd->rx_desc = &rd->alc_rx_ring[i];
4519 if (alc_newbuf(sc, rxd) != 0)
4520 return (ENOBUFS);
4521 }
4522
4523 /*
4524 * Since controller does not update Rx descriptors, driver
4525 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE
4526 * is enough to ensure coherence.
4527 */
4528 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
4529 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE);
4530 /* Let controller know availability of new Rx buffers. */
4531 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons);
4532
4533 return (0);
4534 }
4535
4536 static void
alc_init_rr_ring(struct alc_softc * sc)4537 alc_init_rr_ring(struct alc_softc *sc)
4538 {
4539 struct alc_ring_data *rd;
4540
4541 ALC_LOCK_ASSERT(sc);
4542
4543 sc->alc_cdata.alc_rr_cons = 0;
4544 ALC_RXCHAIN_RESET(sc);
4545
4546 rd = &sc->alc_rdata;
4547 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ);
4548 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
4549 sc->alc_cdata.alc_rr_ring_map,
4550 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4551 }
4552
4553 static void
alc_init_cmb(struct alc_softc * sc)4554 alc_init_cmb(struct alc_softc *sc)
4555 {
4556 struct alc_ring_data *rd;
4557
4558 ALC_LOCK_ASSERT(sc);
4559
4560 rd = &sc->alc_rdata;
4561 bzero(rd->alc_cmb, ALC_CMB_SZ);
4562 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map,
4563 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4564 }
4565
4566 static void
alc_init_smb(struct alc_softc * sc)4567 alc_init_smb(struct alc_softc *sc)
4568 {
4569 struct alc_ring_data *rd;
4570
4571 ALC_LOCK_ASSERT(sc);
4572
4573 rd = &sc->alc_rdata;
4574 bzero(rd->alc_smb, ALC_SMB_SZ);
4575 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map,
4576 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4577 }
4578
4579 static void
alc_rxvlan(struct alc_softc * sc)4580 alc_rxvlan(struct alc_softc *sc)
4581 {
4582 if_t ifp;
4583 uint32_t reg;
4584
4585 ALC_LOCK_ASSERT(sc);
4586
4587 ifp = sc->alc_ifp;
4588 reg = CSR_READ_4(sc, ALC_MAC_CFG);
4589 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
4590 reg |= MAC_CFG_VLAN_TAG_STRIP;
4591 else
4592 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
4593 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
4594 }
4595
4596 static u_int
alc_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)4597 alc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
4598 {
4599 uint32_t *mchash = arg;
4600 uint32_t crc;
4601
4602 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
4603 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
4604
4605 return (1);
4606 }
4607
4608 static void
alc_rxfilter(struct alc_softc * sc)4609 alc_rxfilter(struct alc_softc *sc)
4610 {
4611 if_t ifp;
4612 uint32_t mchash[2];
4613 uint32_t rxcfg;
4614
4615 ALC_LOCK_ASSERT(sc);
4616
4617 ifp = sc->alc_ifp;
4618
4619 bzero(mchash, sizeof(mchash));
4620 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG);
4621 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
4622 if ((if_getflags(ifp) & IFF_BROADCAST) != 0)
4623 rxcfg |= MAC_CFG_BCAST;
4624 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
4625 if ((if_getflags(ifp) & IFF_PROMISC) != 0)
4626 rxcfg |= MAC_CFG_PROMISC;
4627 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0)
4628 rxcfg |= MAC_CFG_ALLMULTI;
4629 mchash[0] = 0xFFFFFFFF;
4630 mchash[1] = 0xFFFFFFFF;
4631 goto chipit;
4632 }
4633
4634 if_foreach_llmaddr(ifp, alc_hash_maddr, mchash);
4635
4636 chipit:
4637 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]);
4638 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]);
4639 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg);
4640 }
4641
4642 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)4643 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
4644 {
4645 int error, value;
4646
4647 if (arg1 == NULL)
4648 return (EINVAL);
4649 value = *(int *)arg1;
4650 error = sysctl_handle_int(oidp, &value, 0, req);
4651 if (error || req->newptr == NULL)
4652 return (error);
4653 if (value < low || value > high)
4654 return (EINVAL);
4655 *(int *)arg1 = value;
4656
4657 return (0);
4658 }
4659
4660 static int
sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS)4661 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS)
4662 {
4663 return (sysctl_int_range(oidp, arg1, arg2, req,
4664 ALC_PROC_MIN, ALC_PROC_MAX));
4665 }
4666
4667 static int
sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS)4668 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS)
4669 {
4670
4671 return (sysctl_int_range(oidp, arg1, arg2, req,
4672 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX));
4673 }
4674
4675 #ifdef DEBUGNET
4676 static void
alc_debugnet_init(if_t ifp,int * nrxr,int * ncl,int * clsize)4677 alc_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
4678 {
4679 struct alc_softc *sc __diagused;
4680
4681 sc = if_getsoftc(ifp);
4682 KASSERT(sc->alc_buf_size <= MCLBYTES, ("incorrect cluster size"));
4683
4684 *nrxr = ALC_RX_RING_CNT;
4685 *ncl = DEBUGNET_MAX_IN_FLIGHT;
4686 *clsize = MCLBYTES;
4687 }
4688
4689 static void
alc_debugnet_event(if_t ifp __unused,enum debugnet_ev event __unused)4690 alc_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused)
4691 {
4692 }
4693
4694 static int
alc_debugnet_transmit(if_t ifp,struct mbuf * m)4695 alc_debugnet_transmit(if_t ifp, struct mbuf *m)
4696 {
4697 struct alc_softc *sc;
4698 int error;
4699
4700 sc = if_getsoftc(ifp);
4701 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4702 IFF_DRV_RUNNING)
4703 return (EBUSY);
4704
4705 error = alc_encap(sc, &m);
4706 if (error == 0)
4707 alc_start_tx(sc);
4708 return (error);
4709 }
4710
4711 static int
alc_debugnet_poll(if_t ifp,int count)4712 alc_debugnet_poll(if_t ifp, int count)
4713 {
4714 struct alc_softc *sc;
4715
4716 sc = if_getsoftc(ifp);
4717 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4718 IFF_DRV_RUNNING)
4719 return (EBUSY);
4720
4721 alc_txeof(sc);
4722 return (alc_rxintr(sc, count));
4723 }
4724 #endif /* DEBUGNET */
4725