1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD717x and AD411x family SPI ADC driver
4 *
5 * Supported devices:
6 * AD4111/AD4112/AD4113/AD4114/AD4115/AD4116
7 * AD7172-2/AD7172-4/AD7173-8/AD7175-2
8 * AD7175-8/AD7176-2/AD7177-2
9 *
10 * Copyright (C) 2015, 2024 Analog Devices, Inc.
11 */
12
13 #include <linux/array_size.h>
14 #include <linux/bitfield.h>
15 #include <linux/bitmap.h>
16 #include <linux/container_of.h>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/delay.h>
20 #include <linux/device.h>
21 #include <linux/err.h>
22 #include <linux/gpio/driver.h>
23 #include <linux/gpio/regmap.h>
24 #include <linux/idr.h>
25 #include <linux/interrupt.h>
26 #include <linux/math64.h>
27 #include <linux/module.h>
28 #include <linux/mod_devicetable.h>
29 #include <linux/property.h>
30 #include <linux/regmap.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/slab.h>
33 #include <linux/spi/spi.h>
34 #include <linux/types.h>
35 #include <linux/units.h>
36
37 #include <linux/iio/buffer.h>
38 #include <linux/iio/iio.h>
39 #include <linux/iio/trigger_consumer.h>
40 #include <linux/iio/triggered_buffer.h>
41
42 #include <linux/iio/adc/ad_sigma_delta.h>
43
44 #define AD7173_REG_COMMS 0x00
45 #define AD7173_REG_ADC_MODE 0x01
46 #define AD7173_REG_INTERFACE_MODE 0x02
47 #define AD7173_REG_CRC 0x03
48 #define AD7173_REG_DATA 0x04
49 #define AD7173_REG_GPIO 0x06
50 #define AD7173_REG_ID 0x07
51 #define AD7173_REG_CH(x) (0x10 + (x))
52 #define AD7173_REG_SETUP(x) (0x20 + (x))
53 #define AD7173_REG_FILTER(x) (0x28 + (x))
54 #define AD7173_REG_OFFSET(x) (0x30 + (x))
55 #define AD7173_REG_GAIN(x) (0x38 + (x))
56
57 #define AD7173_RESET_LENGTH BITS_TO_BYTES(64)
58
59 #define AD7173_CH_ENABLE BIT(15)
60 #define AD7173_CH_SETUP_SEL_MASK GENMASK(14, 12)
61 #define AD7173_CH_SETUP_AINPOS_MASK GENMASK(9, 5)
62 #define AD7173_CH_SETUP_AINNEG_MASK GENMASK(4, 0)
63
64 #define AD7173_NO_AINS_PER_CHANNEL 2
65 #define AD7173_CH_ADDRESS(pos, neg) \
66 (FIELD_PREP(AD7173_CH_SETUP_AINPOS_MASK, pos) | \
67 FIELD_PREP(AD7173_CH_SETUP_AINNEG_MASK, neg))
68 #define AD7173_AIN_TEMP_POS 17
69 #define AD7173_AIN_TEMP_NEG 18
70 #define AD7173_AIN_POW_MON_POS 19
71 #define AD7173_AIN_POW_MON_NEG 20
72 #define AD7173_AIN_REF_POS 21
73 #define AD7173_AIN_REF_NEG 22
74
75 #define AD7173_IS_REF_INPUT(x) ((x) == AD7173_AIN_REF_POS || \
76 (x) == AD7173_AIN_REF_NEG)
77
78 #define AD7172_2_ID 0x00d0
79 #define AD7176_ID 0x0c90
80 #define AD7175_ID 0x0cd0
81 #define AD7175_2_ID 0x0cd0
82 #define AD7172_4_ID 0x2050
83 #define AD7173_ID 0x30d0
84 #define AD4111_ID AD7173_ID
85 #define AD4112_ID AD7173_ID
86 #define AD4114_ID AD7173_ID
87 #define AD4113_ID 0x31d0
88 #define AD4116_ID 0x34d0
89 #define AD4115_ID 0x38d0
90 #define AD7175_8_ID 0x3cd0
91 #define AD7177_ID 0x4fd0
92 #define AD7173_ID_MASK GENMASK(15, 4)
93
94 #define AD7173_ADC_MODE_REF_EN BIT(15)
95 #define AD7173_ADC_MODE_SING_CYC BIT(13)
96 #define AD7173_ADC_MODE_MODE_MASK GENMASK(6, 4)
97 #define AD7173_ADC_MODE_CLOCKSEL_MASK GENMASK(3, 2)
98 #define AD7173_ADC_MODE_CLOCKSEL_INT 0x0
99 #define AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT 0x1
100 #define AD7173_ADC_MODE_CLOCKSEL_EXT 0x2
101 #define AD7173_ADC_MODE_CLOCKSEL_XTAL 0x3
102
103 #define AD7173_GPIO_PDSW BIT(14)
104 #define AD7173_GPIO_OP_EN2_3 BIT(13)
105 #define AD7173_GPIO_MUX_IO BIT(12)
106 #define AD7173_GPIO_SYNC_EN BIT(11)
107 #define AD7173_GPIO_ERR_EN BIT(10)
108 #define AD7173_GPIO_ERR_DAT BIT(9)
109 #define AD7173_GPIO_GP_DATA3 BIT(7)
110 #define AD7173_GPIO_GP_DATA2 BIT(6)
111 #define AD7173_GPIO_IP_EN1 BIT(5)
112 #define AD7173_GPIO_IP_EN0 BIT(4)
113 #define AD7173_GPIO_OP_EN1 BIT(3)
114 #define AD7173_GPIO_OP_EN0 BIT(2)
115 #define AD7173_GPIO_GP_DATA1 BIT(1)
116 #define AD7173_GPIO_GP_DATA0 BIT(0)
117
118 #define AD7173_GPO12_DATA(x) BIT((x) + 0)
119 #define AD7173_GPO23_DATA(x) BIT((x) + 4)
120 #define AD4111_GPO01_DATA(x) BIT((x) + 6)
121 #define AD7173_GPO_DATA(x) ((x) < 2 ? AD7173_GPO12_DATA(x) : AD7173_GPO23_DATA(x))
122
123 #define AD7173_INTERFACE_DATA_STAT BIT(6)
124 #define AD7173_INTERFACE_DATA_STAT_EN(x) \
125 FIELD_PREP(AD7173_INTERFACE_DATA_STAT, x)
126
127 #define AD7173_SETUP_BIPOLAR BIT(12)
128 #define AD7173_SETUP_AREF_BUF_MASK GENMASK(11, 10)
129 #define AD7173_SETUP_AIN_BUF_MASK GENMASK(9, 8)
130
131 #define AD7173_SETUP_REF_SEL_MASK GENMASK(5, 4)
132 #define AD7173_SETUP_REF_SEL_AVDD1_AVSS 0x3
133 #define AD7173_SETUP_REF_SEL_INT_REF 0x2
134 #define AD7173_SETUP_REF_SEL_EXT_REF2 0x1
135 #define AD7173_SETUP_REF_SEL_EXT_REF 0x0
136 #define AD7173_VOLTAGE_INT_REF_uV 2500000
137 #define AD7173_TEMP_SENSIIVITY_uV_per_C 477
138 #define AD7177_ODR_START_VALUE 0x07
139 #define AD4111_SHUNT_RESISTOR_OHM 50
140 #define AD4111_DIVIDER_RATIO 10
141 #define AD4111_CURRENT_CHAN_CUTOFF 16
142 #define AD4111_VINCOM_INPUT 0x10
143
144 /* pin < num_voltage_in is a normal voltage input */
145 /* pin >= num_voltage_in_div is a voltage input without a divider */
146 #define AD4111_IS_VINCOM_MISMATCH(pin1, pin2) ((pin1) == AD4111_VINCOM_INPUT && \
147 (pin2) < st->info->num_voltage_in && \
148 (pin2) >= st->info->num_voltage_in_div)
149
150 #define AD7173_FILTER_ODR0_MASK GENMASK(5, 0)
151 #define AD7173_MAX_CONFIGS 8
152
153 #define AD7173_MODE_CAL_INT_ZERO 0x4 /* Internal Zero-Scale Calibration */
154 #define AD7173_MODE_CAL_INT_FULL 0x5 /* Internal Full-Scale Calibration */
155 #define AD7173_MODE_CAL_SYS_ZERO 0x6 /* System Zero-Scale Calibration */
156 #define AD7173_MODE_CAL_SYS_FULL 0x7 /* System Full-Scale Calibration */
157
158 struct ad7173_device_info {
159 const unsigned int *sinc5_data_rates;
160 unsigned int num_sinc5_data_rates;
161 unsigned int odr_start_value;
162 /*
163 * AD4116 has both inputs with a voltage divider and without.
164 * These inputs cannot be mixed in the channel configuration.
165 * Does not include the VINCOM input.
166 */
167 unsigned int num_voltage_in_div;
168 unsigned int num_channels;
169 unsigned int num_configs;
170 unsigned int num_voltage_in;
171 unsigned int clock;
172 unsigned int id;
173 char *name;
174 bool has_current_inputs;
175 bool has_vincom_input;
176 bool has_temp;
177 /* ((AVDD1 − AVSS)/5) */
178 bool has_pow_supply_monitoring;
179 bool data_reg_only_16bit;
180 bool has_input_buf;
181 bool has_int_ref;
182 bool has_ref2;
183 bool has_internal_fs_calibration;
184 bool higher_gpio_bits;
185 u8 num_gpios;
186 };
187
188 struct ad7173_channel_config {
189 u8 cfg_slot;
190 bool live;
191
192 /* Following fields are used to compare equality. */
193 struct_group(config_props,
194 bool bipolar;
195 bool input_buf;
196 u8 odr;
197 u8 ref_sel;
198 );
199 };
200
201 struct ad7173_channel {
202 unsigned int ain;
203 struct ad7173_channel_config cfg;
204 u8 syscalib_mode;
205 };
206
207 struct ad7173_state {
208 struct ad_sigma_delta sd;
209 struct ad_sigma_delta_info sigma_delta_info;
210 const struct ad7173_device_info *info;
211 struct ad7173_channel *channels;
212 struct regulator_bulk_data regulators[3];
213 unsigned int adc_mode;
214 unsigned int interface_mode;
215 unsigned int num_channels;
216 struct ida cfg_slots_status;
217 unsigned long long config_usage_counter;
218 unsigned long long *config_cnts;
219 struct clk *ext_clk;
220 struct clk_hw int_clk_hw;
221 #if IS_ENABLED(CONFIG_GPIOLIB)
222 struct regmap *reg_gpiocon_regmap;
223 struct gpio_regmap *gpio_regmap;
224 #endif
225 };
226
227 static unsigned int ad4115_sinc5_data_rates[] = {
228 24845000, 24845000, 20725000, 20725000, /* 0-3 */
229 15564000, 13841000, 10390000, 10390000, /* 4-7 */
230 4994000, 2499000, 1000000, 500000, /* 8-11 */
231 395500, 200000, 100000, 59890, /* 12-15 */
232 49920, 20000, 16660, 10000, /* 16-19 */
233 5000, 2500, 2500, /* 20-22 */
234 };
235
236 static unsigned int ad4116_sinc5_data_rates[] = {
237 12422360, 12422360, 12422360, 12422360, /* 0-3 */
238 10362690, 10362690, 7782100, 6290530, /* 4-7 */
239 5194800, 2496900, 1007600, 499900, /* 8-11 */
240 390600, 200300, 100000, 59750, /* 12-15 */
241 49840, 20000, 16650, 10000, /* 16-19 */
242 5000, 2500, 1250, /* 20-22 */
243 };
244
245 static const unsigned int ad7173_sinc5_data_rates[] = {
246 6211000, 6211000, 6211000, 6211000, 6211000, 6211000, 5181000, 4444000, /* 0-7 */
247 3115000, 2597000, 1007000, 503800, 381000, 200300, 100500, 59520, /* 8-15 */
248 49680, 20010, 16333, 10000, 5000, 2500, 1250, /* 16-22 */
249 };
250
251 static const unsigned int ad7175_sinc5_data_rates[] = {
252 50000000, 41667000, 31250000, 27778000, /* 0-3 */
253 20833000, 17857000, 12500000, 10000000, /* 4-7 */
254 5000000, 2500000, 1000000, 500000, /* 8-11 */
255 397500, 200000, 100000, 59920, /* 12-15 */
256 49960, 20000, 16666, 10000, /* 16-19 */
257 5000, /* 20 */
258 };
259
260 static unsigned int ad4111_current_channel_config[] = {
261 /* Ain sel: pos neg */
262 0x1E8, /* 15:IIN0+ 8:IIN0− */
263 0x1C9, /* 14:IIN1+ 9:IIN1− */
264 0x1AA, /* 13:IIN2+ 10:IIN2− */
265 0x18B, /* 12:IIN3+ 11:IIN3− */
266 };
267
268 static const struct ad7173_device_info ad4111_device_info = {
269 .name = "ad4111",
270 .id = AD4111_ID,
271 .num_voltage_in_div = 8,
272 .num_channels = 16,
273 .num_configs = 8,
274 .num_voltage_in = 8,
275 .num_gpios = 2,
276 .higher_gpio_bits = true,
277 .has_temp = true,
278 .has_vincom_input = true,
279 .has_input_buf = true,
280 .has_current_inputs = true,
281 .has_int_ref = true,
282 .has_internal_fs_calibration = true,
283 .clock = 2 * HZ_PER_MHZ,
284 .sinc5_data_rates = ad7173_sinc5_data_rates,
285 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
286 };
287
288 static const struct ad7173_device_info ad4112_device_info = {
289 .name = "ad4112",
290 .id = AD4112_ID,
291 .num_voltage_in_div = 8,
292 .num_channels = 16,
293 .num_configs = 8,
294 .num_voltage_in = 8,
295 .num_gpios = 2,
296 .higher_gpio_bits = true,
297 .has_vincom_input = true,
298 .has_temp = true,
299 .has_input_buf = true,
300 .has_current_inputs = true,
301 .has_int_ref = true,
302 .has_internal_fs_calibration = true,
303 .clock = 2 * HZ_PER_MHZ,
304 .sinc5_data_rates = ad7173_sinc5_data_rates,
305 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
306 };
307
308 static const struct ad7173_device_info ad4113_device_info = {
309 .name = "ad4113",
310 .id = AD4113_ID,
311 .num_voltage_in_div = 8,
312 .num_channels = 16,
313 .num_configs = 8,
314 .num_voltage_in = 8,
315 .num_gpios = 2,
316 .data_reg_only_16bit = true,
317 .higher_gpio_bits = true,
318 .has_vincom_input = true,
319 .has_input_buf = true,
320 .has_int_ref = true,
321 .clock = 2 * HZ_PER_MHZ,
322 .sinc5_data_rates = ad7173_sinc5_data_rates,
323 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
324 };
325
326 static const struct ad7173_device_info ad4114_device_info = {
327 .name = "ad4114",
328 .id = AD4114_ID,
329 .num_voltage_in_div = 16,
330 .num_channels = 16,
331 .num_configs = 8,
332 .num_voltage_in = 16,
333 .num_gpios = 4,
334 .has_vincom_input = true,
335 .has_temp = true,
336 .has_input_buf = true,
337 .has_int_ref = true,
338 .has_internal_fs_calibration = true,
339 .clock = 2 * HZ_PER_MHZ,
340 .sinc5_data_rates = ad7173_sinc5_data_rates,
341 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
342 };
343
344 static const struct ad7173_device_info ad4115_device_info = {
345 .name = "ad4115",
346 .id = AD4115_ID,
347 .num_voltage_in_div = 16,
348 .num_channels = 16,
349 .num_configs = 8,
350 .num_voltage_in = 16,
351 .num_gpios = 4,
352 .has_vincom_input = true,
353 .has_temp = true,
354 .has_input_buf = true,
355 .has_int_ref = true,
356 .has_internal_fs_calibration = true,
357 .clock = 8 * HZ_PER_MHZ,
358 .sinc5_data_rates = ad4115_sinc5_data_rates,
359 .num_sinc5_data_rates = ARRAY_SIZE(ad4115_sinc5_data_rates),
360 };
361
362 static const struct ad7173_device_info ad4116_device_info = {
363 .name = "ad4116",
364 .id = AD4116_ID,
365 .num_voltage_in_div = 11,
366 .num_channels = 16,
367 .num_configs = 8,
368 .num_voltage_in = 16,
369 .num_gpios = 4,
370 .has_vincom_input = true,
371 .has_temp = true,
372 .has_input_buf = true,
373 .has_int_ref = true,
374 .has_internal_fs_calibration = true,
375 .clock = 4 * HZ_PER_MHZ,
376 .sinc5_data_rates = ad4116_sinc5_data_rates,
377 .num_sinc5_data_rates = ARRAY_SIZE(ad4116_sinc5_data_rates),
378 };
379
380 static const struct ad7173_device_info ad7172_2_device_info = {
381 .name = "ad7172-2",
382 .id = AD7172_2_ID,
383 .num_voltage_in = 5,
384 .num_channels = 4,
385 .num_configs = 4,
386 .num_gpios = 2,
387 .has_temp = true,
388 .has_input_buf = true,
389 .has_int_ref = true,
390 .has_pow_supply_monitoring = true,
391 .clock = 2 * HZ_PER_MHZ,
392 .sinc5_data_rates = ad7173_sinc5_data_rates,
393 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
394 };
395
396 static const struct ad7173_device_info ad7172_4_device_info = {
397 .name = "ad7172-4",
398 .id = AD7172_4_ID,
399 .num_voltage_in = 9,
400 .num_channels = 8,
401 .num_configs = 8,
402 .num_gpios = 4,
403 .has_input_buf = true,
404 .has_ref2 = true,
405 .has_pow_supply_monitoring = true,
406 .clock = 2 * HZ_PER_MHZ,
407 .sinc5_data_rates = ad7173_sinc5_data_rates,
408 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
409 };
410
411 static const struct ad7173_device_info ad7173_8_device_info = {
412 .name = "ad7173-8",
413 .id = AD7173_ID,
414 .num_voltage_in = 17,
415 .num_channels = 16,
416 .num_configs = 8,
417 .num_gpios = 4,
418 .has_temp = true,
419 .has_input_buf = true,
420 .has_int_ref = true,
421 .has_ref2 = true,
422 .clock = 2 * HZ_PER_MHZ,
423 .sinc5_data_rates = ad7173_sinc5_data_rates,
424 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
425 };
426
427 static const struct ad7173_device_info ad7175_2_device_info = {
428 .name = "ad7175-2",
429 .id = AD7175_2_ID,
430 .num_voltage_in = 5,
431 .num_channels = 4,
432 .num_configs = 4,
433 .num_gpios = 2,
434 .has_temp = true,
435 .has_input_buf = true,
436 .has_int_ref = true,
437 .has_pow_supply_monitoring = true,
438 .clock = 16 * HZ_PER_MHZ,
439 .sinc5_data_rates = ad7175_sinc5_data_rates,
440 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
441 };
442
443 static const struct ad7173_device_info ad7175_8_device_info = {
444 .name = "ad7175-8",
445 .id = AD7175_8_ID,
446 .num_voltage_in = 17,
447 .num_channels = 16,
448 .num_configs = 8,
449 .num_gpios = 4,
450 .has_temp = true,
451 .has_input_buf = true,
452 .has_int_ref = true,
453 .has_ref2 = true,
454 .has_pow_supply_monitoring = true,
455 .clock = 16 * HZ_PER_MHZ,
456 .sinc5_data_rates = ad7175_sinc5_data_rates,
457 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
458 };
459
460 static const struct ad7173_device_info ad7176_2_device_info = {
461 .name = "ad7176-2",
462 .id = AD7176_ID,
463 .num_voltage_in = 5,
464 .num_channels = 4,
465 .num_configs = 4,
466 .num_gpios = 2,
467 .has_int_ref = true,
468 .clock = 16 * HZ_PER_MHZ,
469 .sinc5_data_rates = ad7175_sinc5_data_rates,
470 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
471 };
472
473 static const struct ad7173_device_info ad7177_2_device_info = {
474 .name = "ad7177-2",
475 .id = AD7177_ID,
476 .num_voltage_in = 5,
477 .num_channels = 4,
478 .num_configs = 4,
479 .num_gpios = 2,
480 .has_temp = true,
481 .has_input_buf = true,
482 .has_int_ref = true,
483 .has_pow_supply_monitoring = true,
484 .clock = 16 * HZ_PER_MHZ,
485 .odr_start_value = AD7177_ODR_START_VALUE,
486 .sinc5_data_rates = ad7175_sinc5_data_rates,
487 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
488 };
489
490 static const char *const ad7173_ref_sel_str[] = {
491 [AD7173_SETUP_REF_SEL_EXT_REF] = "vref",
492 [AD7173_SETUP_REF_SEL_EXT_REF2] = "vref2",
493 [AD7173_SETUP_REF_SEL_INT_REF] = "refout-avss",
494 [AD7173_SETUP_REF_SEL_AVDD1_AVSS] = "avdd",
495 };
496
497 static const char *const ad7173_clk_sel[] = {
498 "ext-clk", "xtal"
499 };
500
501 #if IS_ENABLED(CONFIG_GPIOLIB)
502
503 static const struct regmap_range ad7173_range_gpio[] = {
504 regmap_reg_range(AD7173_REG_GPIO, AD7173_REG_GPIO),
505 };
506
507 static const struct regmap_access_table ad7173_access_table = {
508 .yes_ranges = ad7173_range_gpio,
509 .n_yes_ranges = ARRAY_SIZE(ad7173_range_gpio),
510 };
511
512 static const struct regmap_config ad7173_regmap_config = {
513 .reg_bits = 8,
514 .val_bits = 16,
515 .rd_table = &ad7173_access_table,
516 .wr_table = &ad7173_access_table,
517 .read_flag_mask = BIT(6),
518 };
519
520 enum {
521 AD7173_SYSCALIB_ZERO_SCALE,
522 AD7173_SYSCALIB_FULL_SCALE,
523 };
524
525 static const char * const ad7173_syscalib_modes[] = {
526 [AD7173_SYSCALIB_ZERO_SCALE] = "zero_scale",
527 [AD7173_SYSCALIB_FULL_SCALE] = "full_scale",
528 };
529
ad7173_set_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)530 static int ad7173_set_syscalib_mode(struct iio_dev *indio_dev,
531 const struct iio_chan_spec *chan,
532 unsigned int mode)
533 {
534 struct ad7173_state *st = iio_priv(indio_dev);
535
536 st->channels[chan->channel].syscalib_mode = mode;
537
538 return 0;
539 }
540
ad7173_get_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)541 static int ad7173_get_syscalib_mode(struct iio_dev *indio_dev,
542 const struct iio_chan_spec *chan)
543 {
544 struct ad7173_state *st = iio_priv(indio_dev);
545
546 return st->channels[chan->channel].syscalib_mode;
547 }
548
ad7173_write_syscalib(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)549 static ssize_t ad7173_write_syscalib(struct iio_dev *indio_dev,
550 uintptr_t private,
551 const struct iio_chan_spec *chan,
552 const char *buf, size_t len)
553 {
554 struct ad7173_state *st = iio_priv(indio_dev);
555 bool sys_calib;
556 int ret, mode;
557
558 ret = kstrtobool(buf, &sys_calib);
559 if (ret)
560 return ret;
561
562 mode = st->channels[chan->channel].syscalib_mode;
563 if (sys_calib) {
564 if (mode == AD7173_SYSCALIB_ZERO_SCALE)
565 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_SYS_ZERO,
566 chan->address);
567 else
568 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_SYS_FULL,
569 chan->address);
570 }
571
572 return ret ? : len;
573 }
574
575 static const struct iio_enum ad7173_syscalib_mode_enum = {
576 .items = ad7173_syscalib_modes,
577 .num_items = ARRAY_SIZE(ad7173_syscalib_modes),
578 .set = ad7173_set_syscalib_mode,
579 .get = ad7173_get_syscalib_mode
580 };
581
582 static const struct iio_chan_spec_ext_info ad7173_calibsys_ext_info[] = {
583 {
584 .name = "sys_calibration",
585 .write = ad7173_write_syscalib,
586 .shared = IIO_SEPARATE,
587 },
588 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
589 &ad7173_syscalib_mode_enum),
590 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE,
591 &ad7173_syscalib_mode_enum),
592 { }
593 };
594
ad7173_calibrate_all(struct ad7173_state * st,struct iio_dev * indio_dev)595 static int ad7173_calibrate_all(struct ad7173_state *st, struct iio_dev *indio_dev)
596 {
597 int ret;
598 int i;
599
600 for (i = 0; i < st->num_channels; i++) {
601 if (indio_dev->channels[i].type != IIO_VOLTAGE)
602 continue;
603
604 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_ZERO, st->channels[i].ain);
605 if (ret < 0)
606 return ret;
607
608 if (st->info->has_internal_fs_calibration) {
609 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_FULL,
610 st->channels[i].ain);
611 if (ret < 0)
612 return ret;
613 }
614 }
615
616 return 0;
617 }
618
ad7173_mask_xlate(struct gpio_regmap * gpio,unsigned int base,unsigned int offset,unsigned int * reg,unsigned int * mask)619 static int ad7173_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
620 unsigned int offset, unsigned int *reg,
621 unsigned int *mask)
622 {
623 *mask = AD7173_GPO_DATA(offset);
624 *reg = base;
625 return 0;
626 }
627
ad4111_mask_xlate(struct gpio_regmap * gpio,unsigned int base,unsigned int offset,unsigned int * reg,unsigned int * mask)628 static int ad4111_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
629 unsigned int offset, unsigned int *reg,
630 unsigned int *mask)
631 {
632 *mask = AD4111_GPO01_DATA(offset);
633 *reg = base;
634 return 0;
635 }
636
ad7173_gpio_disable(void * data)637 static void ad7173_gpio_disable(void *data)
638 {
639 struct ad7173_state *st = data;
640 unsigned int mask;
641
642 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3;
643 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, ~mask);
644 }
645
ad7173_gpio_init(struct ad7173_state * st)646 static int ad7173_gpio_init(struct ad7173_state *st)
647 {
648 struct gpio_regmap_config gpio_regmap = {};
649 struct device *dev = &st->sd.spi->dev;
650 unsigned int mask;
651 int ret;
652
653 st->reg_gpiocon_regmap = devm_regmap_init_spi(st->sd.spi, &ad7173_regmap_config);
654 ret = PTR_ERR_OR_ZERO(st->reg_gpiocon_regmap);
655 if (ret)
656 return dev_err_probe(dev, ret, "Unable to init regmap\n");
657
658 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3;
659 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, mask);
660
661 ret = devm_add_action_or_reset(dev, ad7173_gpio_disable, st);
662 if (ret)
663 return ret;
664
665 gpio_regmap.parent = dev;
666 gpio_regmap.regmap = st->reg_gpiocon_regmap;
667 gpio_regmap.ngpio = st->info->num_gpios;
668 gpio_regmap.reg_set_base = AD7173_REG_GPIO;
669 if (st->info->higher_gpio_bits)
670 gpio_regmap.reg_mask_xlate = ad4111_mask_xlate;
671 else
672 gpio_regmap.reg_mask_xlate = ad7173_mask_xlate;
673
674 st->gpio_regmap = devm_gpio_regmap_register(dev, &gpio_regmap);
675 ret = PTR_ERR_OR_ZERO(st->gpio_regmap);
676 if (ret)
677 return dev_err_probe(dev, ret, "Unable to init gpio-regmap\n");
678
679 return 0;
680 }
681 #else
ad7173_gpio_init(struct ad7173_state * st)682 static int ad7173_gpio_init(struct ad7173_state *st)
683 {
684 return 0;
685 }
686 #endif /* CONFIG_GPIOLIB */
687
ad_sigma_delta_to_ad7173(struct ad_sigma_delta * sd)688 static struct ad7173_state *ad_sigma_delta_to_ad7173(struct ad_sigma_delta *sd)
689 {
690 return container_of(sd, struct ad7173_state, sd);
691 }
692
clk_hw_to_ad7173(struct clk_hw * hw)693 static struct ad7173_state *clk_hw_to_ad7173(struct clk_hw *hw)
694 {
695 return container_of(hw, struct ad7173_state, int_clk_hw);
696 }
697
ad7173_ida_destroy(void * data)698 static void ad7173_ida_destroy(void *data)
699 {
700 struct ad7173_state *st = data;
701
702 ida_destroy(&st->cfg_slots_status);
703 }
704
ad7173_reset_usage_cnts(struct ad7173_state * st)705 static void ad7173_reset_usage_cnts(struct ad7173_state *st)
706 {
707 memset64(st->config_cnts, 0, st->info->num_configs);
708 st->config_usage_counter = 0;
709 }
710
711 static struct ad7173_channel_config *
ad7173_find_live_config(struct ad7173_state * st,struct ad7173_channel_config * cfg)712 ad7173_find_live_config(struct ad7173_state *st, struct ad7173_channel_config *cfg)
713 {
714 struct ad7173_channel_config *cfg_aux;
715 ptrdiff_t cmp_size;
716 int i;
717
718 cmp_size = sizeof_field(struct ad7173_channel_config, config_props);
719 for (i = 0; i < st->num_channels; i++) {
720 cfg_aux = &st->channels[i].cfg;
721
722 if (cfg_aux->live &&
723 !memcmp(&cfg->config_props, &cfg_aux->config_props, cmp_size))
724 return cfg_aux;
725 }
726 return NULL;
727 }
728
729 /* Could be replaced with a generic LRU implementation */
ad7173_free_config_slot_lru(struct ad7173_state * st)730 static int ad7173_free_config_slot_lru(struct ad7173_state *st)
731 {
732 int i, lru_position = 0;
733
734 for (i = 1; i < st->info->num_configs; i++)
735 if (st->config_cnts[i] < st->config_cnts[lru_position])
736 lru_position = i;
737
738 for (i = 0; i < st->num_channels; i++)
739 if (st->channels[i].cfg.cfg_slot == lru_position)
740 st->channels[i].cfg.live = false;
741
742 ida_free(&st->cfg_slots_status, lru_position);
743 return ida_alloc(&st->cfg_slots_status, GFP_KERNEL);
744 }
745
746 /* Could be replaced with a generic LRU implementation */
ad7173_load_config(struct ad7173_state * st,struct ad7173_channel_config * cfg)747 static int ad7173_load_config(struct ad7173_state *st,
748 struct ad7173_channel_config *cfg)
749 {
750 unsigned int config;
751 int free_cfg_slot, ret;
752
753 free_cfg_slot = ida_alloc_range(&st->cfg_slots_status, 0,
754 st->info->num_configs - 1, GFP_KERNEL);
755 if (free_cfg_slot < 0)
756 free_cfg_slot = ad7173_free_config_slot_lru(st);
757
758 cfg->cfg_slot = free_cfg_slot;
759 config = FIELD_PREP(AD7173_SETUP_REF_SEL_MASK, cfg->ref_sel);
760
761 if (cfg->bipolar)
762 config |= AD7173_SETUP_BIPOLAR;
763
764 if (cfg->input_buf)
765 config |= AD7173_SETUP_AIN_BUF_MASK;
766
767 ret = ad_sd_write_reg(&st->sd, AD7173_REG_SETUP(free_cfg_slot), 2, config);
768 if (ret)
769 return ret;
770
771 return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2,
772 AD7173_FILTER_ODR0_MASK & cfg->odr);
773 }
774
ad7173_config_channel(struct ad7173_state * st,int addr)775 static int ad7173_config_channel(struct ad7173_state *st, int addr)
776 {
777 struct ad7173_channel_config *cfg = &st->channels[addr].cfg;
778 struct ad7173_channel_config *live_cfg;
779 int ret;
780
781 if (!cfg->live) {
782 live_cfg = ad7173_find_live_config(st, cfg);
783 if (live_cfg) {
784 cfg->cfg_slot = live_cfg->cfg_slot;
785 } else {
786 ret = ad7173_load_config(st, cfg);
787 if (ret)
788 return ret;
789 cfg->live = true;
790 }
791 }
792
793 if (st->config_usage_counter == U64_MAX)
794 ad7173_reset_usage_cnts(st);
795
796 st->config_usage_counter++;
797 st->config_cnts[cfg->cfg_slot] = st->config_usage_counter;
798
799 return 0;
800 }
801
ad7173_set_channel(struct ad_sigma_delta * sd,unsigned int channel)802 static int ad7173_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
803 {
804 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
805 unsigned int val;
806 int ret;
807
808 ret = ad7173_config_channel(st, channel);
809 if (ret)
810 return ret;
811
812 val = AD7173_CH_ENABLE |
813 FIELD_PREP(AD7173_CH_SETUP_SEL_MASK, st->channels[channel].cfg.cfg_slot) |
814 st->channels[channel].ain;
815
816 return ad_sd_write_reg(&st->sd, AD7173_REG_CH(channel), 2, val);
817 }
818
ad7173_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)819 static int ad7173_set_mode(struct ad_sigma_delta *sd,
820 enum ad_sigma_delta_mode mode)
821 {
822 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
823
824 st->adc_mode &= ~AD7173_ADC_MODE_MODE_MASK;
825 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_MODE_MASK, mode);
826
827 return ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 2, st->adc_mode);
828 }
829
ad7173_append_status(struct ad_sigma_delta * sd,bool append)830 static int ad7173_append_status(struct ad_sigma_delta *sd, bool append)
831 {
832 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
833 unsigned int interface_mode = st->interface_mode;
834 int ret;
835
836 interface_mode &= ~AD7173_INTERFACE_DATA_STAT;
837 interface_mode |= AD7173_INTERFACE_DATA_STAT_EN(append);
838 ret = ad_sd_write_reg(&st->sd, AD7173_REG_INTERFACE_MODE, 2, interface_mode);
839 if (ret)
840 return ret;
841
842 st->interface_mode = interface_mode;
843
844 return 0;
845 }
846
ad7173_disable_all(struct ad_sigma_delta * sd)847 static int ad7173_disable_all(struct ad_sigma_delta *sd)
848 {
849 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
850 int ret;
851 int i;
852
853 for (i = 0; i < st->num_channels; i++) {
854 ret = ad_sd_write_reg(sd, AD7173_REG_CH(i), 2, 0);
855 if (ret < 0)
856 return ret;
857 }
858
859 return 0;
860 }
861
ad7173_disable_one(struct ad_sigma_delta * sd,unsigned int chan)862 static int ad7173_disable_one(struct ad_sigma_delta *sd, unsigned int chan)
863 {
864 return ad_sd_write_reg(sd, AD7173_REG_CH(chan), 2, 0);
865 }
866
867 static const struct ad_sigma_delta_info ad7173_sigma_delta_info = {
868 .set_channel = ad7173_set_channel,
869 .append_status = ad7173_append_status,
870 .disable_all = ad7173_disable_all,
871 .disable_one = ad7173_disable_one,
872 .set_mode = ad7173_set_mode,
873 .has_registers = true,
874 .addr_shift = 0,
875 .read_mask = BIT(6),
876 .status_ch_mask = GENMASK(3, 0),
877 .data_reg = AD7173_REG_DATA,
878 .num_resetclks = 64,
879 };
880
ad7173_setup(struct iio_dev * indio_dev)881 static int ad7173_setup(struct iio_dev *indio_dev)
882 {
883 struct ad7173_state *st = iio_priv(indio_dev);
884 struct device *dev = &st->sd.spi->dev;
885 u8 buf[AD7173_RESET_LENGTH];
886 unsigned int id;
887 int ret;
888
889 /* reset the serial interface */
890 memset(buf, 0xff, AD7173_RESET_LENGTH);
891 ret = spi_write_then_read(st->sd.spi, buf, sizeof(buf), NULL, 0);
892 if (ret < 0)
893 return ret;
894
895 /* datasheet recommends a delay of at least 500us after reset */
896 fsleep(500);
897
898 ret = ad_sd_read_reg(&st->sd, AD7173_REG_ID, 2, &id);
899 if (ret)
900 return ret;
901
902 id &= AD7173_ID_MASK;
903 if (id != st->info->id)
904 dev_warn(dev, "Unexpected device id: 0x%04X, expected: 0x%04X\n",
905 id, st->info->id);
906
907 st->adc_mode |= AD7173_ADC_MODE_SING_CYC;
908 st->interface_mode = 0x0;
909
910 st->config_usage_counter = 0;
911 st->config_cnts = devm_kcalloc(dev, st->info->num_configs,
912 sizeof(*st->config_cnts), GFP_KERNEL);
913 if (!st->config_cnts)
914 return -ENOMEM;
915
916 ret = ad7173_calibrate_all(st, indio_dev);
917 if (ret)
918 return ret;
919
920 /* All channels are enabled by default after a reset */
921 return ad7173_disable_all(&st->sd);
922 }
923
ad7173_get_ref_voltage_milli(struct ad7173_state * st,u8 reference_select)924 static unsigned int ad7173_get_ref_voltage_milli(struct ad7173_state *st,
925 u8 reference_select)
926 {
927 int vref;
928
929 switch (reference_select) {
930 case AD7173_SETUP_REF_SEL_EXT_REF:
931 vref = regulator_get_voltage(st->regulators[0].consumer);
932 break;
933
934 case AD7173_SETUP_REF_SEL_EXT_REF2:
935 vref = regulator_get_voltage(st->regulators[1].consumer);
936 break;
937
938 case AD7173_SETUP_REF_SEL_INT_REF:
939 vref = AD7173_VOLTAGE_INT_REF_uV;
940 break;
941
942 case AD7173_SETUP_REF_SEL_AVDD1_AVSS:
943 vref = regulator_get_voltage(st->regulators[2].consumer);
944 break;
945
946 default:
947 return -EINVAL;
948 }
949
950 if (vref < 0)
951 return vref;
952
953 return vref / (MICRO / MILLI);
954 }
955
ad7173_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)956 static int ad7173_read_raw(struct iio_dev *indio_dev,
957 struct iio_chan_spec const *chan,
958 int *val, int *val2, long info)
959 {
960 struct ad7173_state *st = iio_priv(indio_dev);
961 struct ad7173_channel *ch = &st->channels[chan->address];
962 unsigned int reg;
963 u64 temp;
964 int ret;
965
966 switch (info) {
967 case IIO_CHAN_INFO_RAW:
968 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
969 if (ret < 0)
970 return ret;
971
972 return IIO_VAL_INT;
973 case IIO_CHAN_INFO_SCALE:
974
975 switch (chan->type) {
976 case IIO_TEMP:
977 temp = AD7173_VOLTAGE_INT_REF_uV * MILLI;
978 temp /= AD7173_TEMP_SENSIIVITY_uV_per_C;
979 *val = temp;
980 *val2 = chan->scan_type.realbits;
981 return IIO_VAL_FRACTIONAL_LOG2;
982 case IIO_VOLTAGE:
983 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel);
984 *val2 = chan->scan_type.realbits - !!(ch->cfg.bipolar);
985
986 if (chan->channel < st->info->num_voltage_in_div)
987 *val *= AD4111_DIVIDER_RATIO;
988 return IIO_VAL_FRACTIONAL_LOG2;
989 case IIO_CURRENT:
990 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel);
991 *val /= AD4111_SHUNT_RESISTOR_OHM;
992 *val2 = chan->scan_type.realbits - ch->cfg.bipolar;
993 return IIO_VAL_FRACTIONAL_LOG2;
994 default:
995 return -EINVAL;
996 }
997 case IIO_CHAN_INFO_OFFSET:
998
999 switch (chan->type) {
1000 case IIO_TEMP:
1001 /* 0 Kelvin -> raw sample */
1002 temp = -ABSOLUTE_ZERO_MILLICELSIUS;
1003 temp *= AD7173_TEMP_SENSIIVITY_uV_per_C;
1004 temp <<= chan->scan_type.realbits;
1005 temp = DIV_U64_ROUND_CLOSEST(temp,
1006 AD7173_VOLTAGE_INT_REF_uV *
1007 MILLI);
1008 *val = -temp;
1009 return IIO_VAL_INT;
1010 case IIO_VOLTAGE:
1011 case IIO_CURRENT:
1012 *val = -BIT(chan->scan_type.realbits - 1);
1013 return IIO_VAL_INT;
1014 default:
1015 return -EINVAL;
1016 }
1017 case IIO_CHAN_INFO_SAMP_FREQ:
1018 reg = st->channels[chan->address].cfg.odr;
1019
1020 *val = st->info->sinc5_data_rates[reg] / MILLI;
1021 *val2 = (st->info->sinc5_data_rates[reg] % MILLI) * (MICRO / MILLI);
1022
1023 return IIO_VAL_INT_PLUS_MICRO;
1024 default:
1025 return -EINVAL;
1026 }
1027 }
1028
ad7173_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)1029 static int ad7173_write_raw(struct iio_dev *indio_dev,
1030 struct iio_chan_spec const *chan,
1031 int val, int val2, long info)
1032 {
1033 struct ad7173_state *st = iio_priv(indio_dev);
1034 struct ad7173_channel_config *cfg;
1035 unsigned int freq, i;
1036 int ret;
1037
1038 ret = iio_device_claim_direct_mode(indio_dev);
1039 if (ret)
1040 return ret;
1041
1042 switch (info) {
1043 /*
1044 * This attribute sets the sampling frequency for each channel individually.
1045 * There are no issues for raw or buffered reads of an individual channel.
1046 *
1047 * When multiple channels are enabled in buffered mode, the effective
1048 * sampling rate of a channel is lowered in correlation to the number
1049 * of channels enabled and the sampling rate of the other channels.
1050 *
1051 * Example: 3 channels enabled with rates CH1:6211sps CH2,CH3:10sps
1052 * While the reading of CH1 takes only 0.16ms, the reading of CH2 and CH3
1053 * will take 100ms each.
1054 *
1055 * This will cause the reading of CH1 to be actually done once every
1056 * 200.16ms, an effective rate of 4.99sps.
1057 */
1058 case IIO_CHAN_INFO_SAMP_FREQ:
1059 freq = val * MILLI + val2 / MILLI;
1060 for (i = st->info->odr_start_value; i < st->info->num_sinc5_data_rates - 1; i++)
1061 if (freq >= st->info->sinc5_data_rates[i])
1062 break;
1063
1064 cfg = &st->channels[chan->address].cfg;
1065 cfg->odr = i;
1066 cfg->live = false;
1067 break;
1068
1069 default:
1070 ret = -EINVAL;
1071 break;
1072 }
1073
1074 iio_device_release_direct_mode(indio_dev);
1075 return ret;
1076 }
1077
ad7173_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)1078 static int ad7173_update_scan_mode(struct iio_dev *indio_dev,
1079 const unsigned long *scan_mask)
1080 {
1081 struct ad7173_state *st = iio_priv(indio_dev);
1082 int i, ret;
1083
1084 for (i = 0; i < indio_dev->num_channels; i++) {
1085 if (test_bit(i, scan_mask))
1086 ret = ad7173_set_channel(&st->sd, i);
1087 else
1088 ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(i), 2, 0);
1089 if (ret < 0)
1090 return ret;
1091 }
1092
1093 return 0;
1094 }
1095
ad7173_debug_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)1096 static int ad7173_debug_reg_access(struct iio_dev *indio_dev, unsigned int reg,
1097 unsigned int writeval, unsigned int *readval)
1098 {
1099 struct ad7173_state *st = iio_priv(indio_dev);
1100 u8 reg_size;
1101
1102 if (reg == AD7173_REG_COMMS)
1103 reg_size = 1;
1104 else if (reg == AD7173_REG_CRC || reg == AD7173_REG_DATA ||
1105 reg >= AD7173_REG_OFFSET(0))
1106 reg_size = 3;
1107 else
1108 reg_size = 2;
1109
1110 if (readval)
1111 return ad_sd_read_reg(&st->sd, reg, reg_size, readval);
1112
1113 return ad_sd_write_reg(&st->sd, reg, reg_size, writeval);
1114 }
1115
1116 static const struct iio_info ad7173_info = {
1117 .read_raw = &ad7173_read_raw,
1118 .write_raw = &ad7173_write_raw,
1119 .debugfs_reg_access = &ad7173_debug_reg_access,
1120 .validate_trigger = ad_sd_validate_trigger,
1121 .update_scan_mode = ad7173_update_scan_mode,
1122 };
1123
1124 static const struct iio_scan_type ad4113_scan_type = {
1125 .sign = 'u',
1126 .realbits = 16,
1127 .storagebits = 16,
1128 .endianness = IIO_BE,
1129 };
1130
1131 static const struct iio_chan_spec ad7173_channel_template = {
1132 .type = IIO_VOLTAGE,
1133 .indexed = 1,
1134 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1135 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
1136 .scan_type = {
1137 .sign = 'u',
1138 .realbits = 24,
1139 .storagebits = 32,
1140 .endianness = IIO_BE,
1141 },
1142 .ext_info = ad7173_calibsys_ext_info,
1143 };
1144
1145 static const struct iio_chan_spec ad7173_temp_iio_channel_template = {
1146 .type = IIO_TEMP,
1147 .channel = AD7173_AIN_TEMP_POS,
1148 .channel2 = AD7173_AIN_TEMP_NEG,
1149 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1150 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) |
1151 BIT(IIO_CHAN_INFO_SAMP_FREQ),
1152 .scan_type = {
1153 .sign = 'u',
1154 .realbits = 24,
1155 .storagebits = 32,
1156 .endianness = IIO_BE,
1157 },
1158 };
1159
ad7173_disable_regulators(void * data)1160 static void ad7173_disable_regulators(void *data)
1161 {
1162 struct ad7173_state *st = data;
1163
1164 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators);
1165 }
1166
ad7173_clk_disable_unprepare(void * clk)1167 static void ad7173_clk_disable_unprepare(void *clk)
1168 {
1169 clk_disable_unprepare(clk);
1170 }
1171
ad7173_sel_clk(struct ad7173_state * st,unsigned int clk_sel)1172 static unsigned long ad7173_sel_clk(struct ad7173_state *st,
1173 unsigned int clk_sel)
1174 {
1175 int ret;
1176
1177 st->adc_mode &= ~AD7173_ADC_MODE_CLOCKSEL_MASK;
1178 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, clk_sel);
1179 ret = ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 0x2, st->adc_mode);
1180
1181 return ret;
1182 }
1183
ad7173_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1184 static unsigned long ad7173_clk_recalc_rate(struct clk_hw *hw,
1185 unsigned long parent_rate)
1186 {
1187 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1188
1189 return st->info->clock / HZ_PER_KHZ;
1190 }
1191
ad7173_clk_output_is_enabled(struct clk_hw * hw)1192 static int ad7173_clk_output_is_enabled(struct clk_hw *hw)
1193 {
1194 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1195 u32 clk_sel;
1196
1197 clk_sel = FIELD_GET(AD7173_ADC_MODE_CLOCKSEL_MASK, st->adc_mode);
1198 return clk_sel == AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT;
1199 }
1200
ad7173_clk_output_prepare(struct clk_hw * hw)1201 static int ad7173_clk_output_prepare(struct clk_hw *hw)
1202 {
1203 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1204
1205 return ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT);
1206 }
1207
ad7173_clk_output_unprepare(struct clk_hw * hw)1208 static void ad7173_clk_output_unprepare(struct clk_hw *hw)
1209 {
1210 struct ad7173_state *st = clk_hw_to_ad7173(hw);
1211
1212 ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT);
1213 }
1214
1215 static const struct clk_ops ad7173_int_clk_ops = {
1216 .recalc_rate = ad7173_clk_recalc_rate,
1217 .is_enabled = ad7173_clk_output_is_enabled,
1218 .prepare = ad7173_clk_output_prepare,
1219 .unprepare = ad7173_clk_output_unprepare,
1220 };
1221
ad7173_register_clk_provider(struct iio_dev * indio_dev)1222 static int ad7173_register_clk_provider(struct iio_dev *indio_dev)
1223 {
1224 struct ad7173_state *st = iio_priv(indio_dev);
1225 struct device *dev = indio_dev->dev.parent;
1226 struct fwnode_handle *fwnode = dev_fwnode(dev);
1227 struct clk_init_data init = {};
1228 int ret;
1229
1230 if (!IS_ENABLED(CONFIG_COMMON_CLK))
1231 return 0;
1232
1233 init.name = fwnode_get_name(fwnode);
1234 init.ops = &ad7173_int_clk_ops;
1235
1236 st->int_clk_hw.init = &init;
1237 ret = devm_clk_hw_register(dev, &st->int_clk_hw);
1238 if (ret)
1239 return ret;
1240
1241 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
1242 &st->int_clk_hw);
1243 }
1244
ad4111_validate_current_ain(struct ad7173_state * st,const unsigned int ain[AD7173_NO_AINS_PER_CHANNEL])1245 static int ad4111_validate_current_ain(struct ad7173_state *st,
1246 const unsigned int ain[AD7173_NO_AINS_PER_CHANNEL])
1247 {
1248 struct device *dev = &st->sd.spi->dev;
1249
1250 if (!st->info->has_current_inputs)
1251 return dev_err_probe(dev, -EINVAL,
1252 "Model %s does not support current channels\n",
1253 st->info->name);
1254
1255 if (ain[0] >= ARRAY_SIZE(ad4111_current_channel_config))
1256 return dev_err_probe(dev, -EINVAL,
1257 "For current channels single-channel must be <[0-3]>\n");
1258
1259 return 0;
1260 }
1261
ad7173_validate_voltage_ain_inputs(struct ad7173_state * st,unsigned int ain0,unsigned int ain1)1262 static int ad7173_validate_voltage_ain_inputs(struct ad7173_state *st,
1263 unsigned int ain0, unsigned int ain1)
1264 {
1265 struct device *dev = &st->sd.spi->dev;
1266 bool special_input0, special_input1;
1267
1268 /* (AVDD1-AVSS)/5 power supply monitoring */
1269 if (ain0 == AD7173_AIN_POW_MON_POS && ain1 == AD7173_AIN_POW_MON_NEG &&
1270 st->info->has_pow_supply_monitoring)
1271 return 0;
1272
1273 special_input0 = AD7173_IS_REF_INPUT(ain0) ||
1274 (ain0 == AD4111_VINCOM_INPUT && st->info->has_vincom_input);
1275 special_input1 = AD7173_IS_REF_INPUT(ain1) ||
1276 (ain1 == AD4111_VINCOM_INPUT && st->info->has_vincom_input);
1277
1278 if ((ain0 >= st->info->num_voltage_in && !special_input0) ||
1279 (ain1 >= st->info->num_voltage_in && !special_input1)) {
1280 if (ain0 == AD4111_VINCOM_INPUT || ain1 == AD4111_VINCOM_INPUT)
1281 return dev_err_probe(dev, -EINVAL,
1282 "VINCOM not supported for %s\n", st->info->name);
1283
1284 return dev_err_probe(dev, -EINVAL,
1285 "Input pin number out of range for pair (%d %d).\n",
1286 ain0, ain1);
1287 }
1288
1289 if (AD4111_IS_VINCOM_MISMATCH(ain0, ain1) ||
1290 AD4111_IS_VINCOM_MISMATCH(ain1, ain0))
1291 return dev_err_probe(dev, -EINVAL,
1292 "VINCOM must be paired with inputs having divider.\n");
1293
1294 if (!special_input0 && !special_input1 &&
1295 ((ain0 >= st->info->num_voltage_in_div) !=
1296 (ain1 >= st->info->num_voltage_in_div)))
1297 return dev_err_probe(dev, -EINVAL,
1298 "Both inputs must either have a voltage divider or not have: (%d %d).\n",
1299 ain0, ain1);
1300
1301 return 0;
1302 }
1303
ad7173_validate_reference(struct ad7173_state * st,int ref_sel)1304 static int ad7173_validate_reference(struct ad7173_state *st, int ref_sel)
1305 {
1306 struct device *dev = &st->sd.spi->dev;
1307 int ret;
1308
1309 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF && !st->info->has_int_ref)
1310 return dev_err_probe(dev, -EINVAL,
1311 "Internal reference is not available on current model.\n");
1312
1313 if (ref_sel == AD7173_SETUP_REF_SEL_EXT_REF2 && !st->info->has_ref2)
1314 return dev_err_probe(dev, -EINVAL,
1315 "External reference 2 is not available on current model.\n");
1316
1317 ret = ad7173_get_ref_voltage_milli(st, ref_sel);
1318 if (ret < 0)
1319 return dev_err_probe(dev, ret, "Cannot use reference %u\n",
1320 ref_sel);
1321
1322 return 0;
1323 }
1324
ad7173_fw_parse_channel_config(struct iio_dev * indio_dev)1325 static int ad7173_fw_parse_channel_config(struct iio_dev *indio_dev)
1326 {
1327 struct ad7173_channel *chans_st_arr, *chan_st_priv;
1328 struct ad7173_state *st = iio_priv(indio_dev);
1329 struct device *dev = indio_dev->dev.parent;
1330 struct iio_chan_spec *chan_arr, *chan;
1331 unsigned int ain[AD7173_NO_AINS_PER_CHANNEL], chan_index = 0;
1332 int ref_sel, ret, num_channels;
1333
1334 num_channels = device_get_child_node_count(dev);
1335
1336 if (st->info->has_temp)
1337 num_channels++;
1338
1339 if (num_channels == 0)
1340 return dev_err_probe(dev, -ENODATA, "No channels specified\n");
1341
1342 if (num_channels > st->info->num_channels)
1343 return dev_err_probe(dev, -EINVAL,
1344 "Too many channels specified. Maximum is %d, not including temperature channel if supported.\n",
1345 st->info->num_channels);
1346
1347 indio_dev->num_channels = num_channels;
1348 st->num_channels = num_channels;
1349
1350 chan_arr = devm_kcalloc(dev, sizeof(*indio_dev->channels),
1351 st->num_channels, GFP_KERNEL);
1352 if (!chan_arr)
1353 return -ENOMEM;
1354
1355 chans_st_arr = devm_kcalloc(dev, st->num_channels, sizeof(*st->channels),
1356 GFP_KERNEL);
1357 if (!chans_st_arr)
1358 return -ENOMEM;
1359
1360 indio_dev->channels = chan_arr;
1361 st->channels = chans_st_arr;
1362
1363 if (st->info->has_temp) {
1364 chan_arr[chan_index] = ad7173_temp_iio_channel_template;
1365 chan_st_priv = &chans_st_arr[chan_index];
1366 chan_st_priv->ain =
1367 AD7173_CH_ADDRESS(chan_arr[chan_index].channel,
1368 chan_arr[chan_index].channel2);
1369 chan_st_priv->cfg.bipolar = false;
1370 chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1371 chan_st_priv->cfg.ref_sel = AD7173_SETUP_REF_SEL_INT_REF;
1372 st->adc_mode |= AD7173_ADC_MODE_REF_EN;
1373 if (st->info->data_reg_only_16bit)
1374 chan_arr[chan_index].scan_type = ad4113_scan_type;
1375
1376 chan_index++;
1377 }
1378
1379 device_for_each_child_node_scoped(dev, child) {
1380 bool is_current_chan = false;
1381
1382 chan = &chan_arr[chan_index];
1383 *chan = ad7173_channel_template;
1384 chan_st_priv = &chans_st_arr[chan_index];
1385 ret = fwnode_property_read_u32_array(child, "diff-channels",
1386 ain, ARRAY_SIZE(ain));
1387 if (ret) {
1388 ret = fwnode_property_read_u32(child, "single-channel",
1389 ain);
1390 if (ret)
1391 return dev_err_probe(dev, ret,
1392 "Channel must define one of diff-channels or single-channel.\n");
1393
1394 is_current_chan = fwnode_property_read_bool(child, "adi,current-channel");
1395 } else {
1396 chan->differential = true;
1397 }
1398
1399 if (is_current_chan) {
1400 ret = ad4111_validate_current_ain(st, ain);
1401 if (ret)
1402 return ret;
1403 } else {
1404 if (!chan->differential) {
1405 ret = fwnode_property_read_u32(child,
1406 "common-mode-channel", ain + 1);
1407 if (ret)
1408 return dev_err_probe(dev, ret,
1409 "common-mode-channel must be defined for single-ended channels.\n");
1410 }
1411 ret = ad7173_validate_voltage_ain_inputs(st, ain[0], ain[1]);
1412 if (ret)
1413 return ret;
1414 }
1415
1416 ret = fwnode_property_match_property_string(child,
1417 "adi,reference-select",
1418 ad7173_ref_sel_str,
1419 ARRAY_SIZE(ad7173_ref_sel_str));
1420 if (ret < 0)
1421 ref_sel = AD7173_SETUP_REF_SEL_INT_REF;
1422 else
1423 ref_sel = ret;
1424
1425 ret = ad7173_validate_reference(st, ref_sel);
1426 if (ret)
1427 return ret;
1428
1429 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF)
1430 st->adc_mode |= AD7173_ADC_MODE_REF_EN;
1431 chan_st_priv->cfg.ref_sel = ref_sel;
1432
1433 chan->address = chan_index;
1434 chan->scan_index = chan_index;
1435 chan->channel = ain[0];
1436 chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1437 chan_st_priv->cfg.odr = 0;
1438
1439 chan_st_priv->cfg.bipolar = fwnode_property_read_bool(child, "bipolar");
1440 if (chan_st_priv->cfg.bipolar)
1441 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_OFFSET);
1442
1443 if (is_current_chan) {
1444 chan->type = IIO_CURRENT;
1445 chan->differential = false;
1446 chan->channel2 = 0;
1447 chan_st_priv->ain = ad4111_current_channel_config[ain[0]];
1448 } else {
1449 chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1450 chan->channel2 = ain[1];
1451 chan_st_priv->ain = AD7173_CH_ADDRESS(ain[0], ain[1]);
1452 }
1453
1454 if (st->info->data_reg_only_16bit)
1455 chan_arr[chan_index].scan_type = ad4113_scan_type;
1456
1457 chan_index++;
1458 }
1459 return 0;
1460 }
1461
ad7173_fw_parse_device_config(struct iio_dev * indio_dev)1462 static int ad7173_fw_parse_device_config(struct iio_dev *indio_dev)
1463 {
1464 struct ad7173_state *st = iio_priv(indio_dev);
1465 struct device *dev = indio_dev->dev.parent;
1466 int ret;
1467
1468 st->regulators[0].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF];
1469 st->regulators[1].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF2];
1470 st->regulators[2].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_AVDD1_AVSS];
1471
1472 /*
1473 * If a regulator is not available, it will be set to a dummy regulator.
1474 * Each channel reference is checked with regulator_get_voltage() before
1475 * setting attributes so if any channel uses a dummy supply the driver
1476 * probe will fail.
1477 */
1478 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators),
1479 st->regulators);
1480 if (ret)
1481 return dev_err_probe(dev, ret, "Failed to get regulators\n");
1482
1483 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators);
1484 if (ret)
1485 return dev_err_probe(dev, ret, "Failed to enable regulators\n");
1486
1487 ret = devm_add_action_or_reset(dev, ad7173_disable_regulators, st);
1488 if (ret)
1489 return dev_err_probe(dev, ret,
1490 "Failed to add regulators disable action\n");
1491
1492 ret = device_property_match_property_string(dev, "clock-names",
1493 ad7173_clk_sel,
1494 ARRAY_SIZE(ad7173_clk_sel));
1495 if (ret < 0) {
1496 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK,
1497 AD7173_ADC_MODE_CLOCKSEL_INT);
1498 ad7173_register_clk_provider(indio_dev);
1499 } else {
1500 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK,
1501 AD7173_ADC_MODE_CLOCKSEL_EXT + ret);
1502 st->ext_clk = devm_clk_get(dev, ad7173_clk_sel[ret]);
1503 if (IS_ERR(st->ext_clk))
1504 return dev_err_probe(dev, PTR_ERR(st->ext_clk),
1505 "Failed to get external clock\n");
1506
1507 ret = clk_prepare_enable(st->ext_clk);
1508 if (ret)
1509 return dev_err_probe(dev, ret,
1510 "Failed to enable external clock\n");
1511
1512 ret = devm_add_action_or_reset(dev, ad7173_clk_disable_unprepare,
1513 st->ext_clk);
1514 if (ret)
1515 return ret;
1516 }
1517
1518 ret = fwnode_irq_get_byname(dev_fwnode(dev), "rdy");
1519 if (ret < 0)
1520 return dev_err_probe(dev, ret, "Interrupt 'rdy' is required\n");
1521
1522 st->sigma_delta_info.irq_line = ret;
1523
1524 return ad7173_fw_parse_channel_config(indio_dev);
1525 }
1526
ad7173_probe(struct spi_device * spi)1527 static int ad7173_probe(struct spi_device *spi)
1528 {
1529 struct device *dev = &spi->dev;
1530 struct ad7173_state *st;
1531 struct iio_dev *indio_dev;
1532 int ret;
1533
1534 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1535 if (!indio_dev)
1536 return -ENOMEM;
1537
1538 st = iio_priv(indio_dev);
1539 st->info = spi_get_device_match_data(spi);
1540 if (!st->info)
1541 return -ENODEV;
1542
1543 ida_init(&st->cfg_slots_status);
1544 ret = devm_add_action_or_reset(dev, ad7173_ida_destroy, st);
1545 if (ret)
1546 return ret;
1547
1548 indio_dev->name = st->info->name;
1549 indio_dev->modes = INDIO_DIRECT_MODE;
1550 indio_dev->info = &ad7173_info;
1551
1552 spi->mode = SPI_MODE_3;
1553 spi_setup(spi);
1554
1555 st->sigma_delta_info = ad7173_sigma_delta_info;
1556 st->sigma_delta_info.num_slots = st->info->num_configs;
1557 ret = ad_sd_init(&st->sd, indio_dev, spi, &st->sigma_delta_info);
1558 if (ret)
1559 return ret;
1560
1561 ret = ad7173_fw_parse_device_config(indio_dev);
1562 if (ret)
1563 return ret;
1564
1565 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev);
1566 if (ret)
1567 return ret;
1568
1569 ret = ad7173_setup(indio_dev);
1570 if (ret)
1571 return ret;
1572
1573 ret = devm_iio_device_register(dev, indio_dev);
1574 if (ret)
1575 return ret;
1576
1577 if (IS_ENABLED(CONFIG_GPIOLIB))
1578 return ad7173_gpio_init(st);
1579
1580 return 0;
1581 }
1582
1583 static const struct of_device_id ad7173_of_match[] = {
1584 { .compatible = "adi,ad4111", .data = &ad4111_device_info },
1585 { .compatible = "adi,ad4112", .data = &ad4112_device_info },
1586 { .compatible = "adi,ad4113", .data = &ad4113_device_info },
1587 { .compatible = "adi,ad4114", .data = &ad4114_device_info },
1588 { .compatible = "adi,ad4115", .data = &ad4115_device_info },
1589 { .compatible = "adi,ad4116", .data = &ad4116_device_info },
1590 { .compatible = "adi,ad7172-2", .data = &ad7172_2_device_info },
1591 { .compatible = "adi,ad7172-4", .data = &ad7172_4_device_info },
1592 { .compatible = "adi,ad7173-8", .data = &ad7173_8_device_info },
1593 { .compatible = "adi,ad7175-2", .data = &ad7175_2_device_info },
1594 { .compatible = "adi,ad7175-8", .data = &ad7175_8_device_info },
1595 { .compatible = "adi,ad7176-2", .data = &ad7176_2_device_info },
1596 { .compatible = "adi,ad7177-2", .data = &ad7177_2_device_info },
1597 { }
1598 };
1599 MODULE_DEVICE_TABLE(of, ad7173_of_match);
1600
1601 static const struct spi_device_id ad7173_id_table[] = {
1602 { "ad4111", (kernel_ulong_t)&ad4111_device_info },
1603 { "ad4112", (kernel_ulong_t)&ad4112_device_info },
1604 { "ad4113", (kernel_ulong_t)&ad4113_device_info },
1605 { "ad4114", (kernel_ulong_t)&ad4114_device_info },
1606 { "ad4115", (kernel_ulong_t)&ad4115_device_info },
1607 { "ad4116", (kernel_ulong_t)&ad4116_device_info },
1608 { "ad7172-2", (kernel_ulong_t)&ad7172_2_device_info },
1609 { "ad7172-4", (kernel_ulong_t)&ad7172_4_device_info },
1610 { "ad7173-8", (kernel_ulong_t)&ad7173_8_device_info },
1611 { "ad7175-2", (kernel_ulong_t)&ad7175_2_device_info },
1612 { "ad7175-8", (kernel_ulong_t)&ad7175_8_device_info },
1613 { "ad7176-2", (kernel_ulong_t)&ad7176_2_device_info },
1614 { "ad7177-2", (kernel_ulong_t)&ad7177_2_device_info },
1615 { }
1616 };
1617 MODULE_DEVICE_TABLE(spi, ad7173_id_table);
1618
1619 static struct spi_driver ad7173_driver = {
1620 .driver = {
1621 .name = "ad7173",
1622 .of_match_table = ad7173_of_match,
1623 },
1624 .probe = ad7173_probe,
1625 .id_table = ad7173_id_table,
1626 };
1627 module_spi_driver(ad7173_driver);
1628
1629 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA");
1630 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafo.de>");
1631 MODULE_AUTHOR("Dumitru Ceclan <dumitru.ceclan@analog.com>");
1632 MODULE_DESCRIPTION("Analog Devices AD7173 and similar ADC driver");
1633 MODULE_LICENSE("GPL");
1634