1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ahci.c - AHCI SATA support
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <scsi/scsi_host.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <linux/libata.h>
32 #include <linux/ahci-remap.h>
33 #include <linux/io-64-nonatomic-lo-hi.h>
34 #include "ahci.h"
35
36 #define DRV_NAME "ahci"
37 #define DRV_VERSION "3.0"
38
39 enum {
40 AHCI_PCI_BAR_STA2X11 = 0,
41 AHCI_PCI_BAR_CAVIUM = 0,
42 AHCI_PCI_BAR_LOONGSON = 0,
43 AHCI_PCI_BAR_ENMOTUS = 2,
44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
45 AHCI_PCI_BAR_STANDARD = 5,
46 };
47
48 enum board_ids {
49 /* board IDs by feature in alphabetical order */
50 board_ahci,
51 board_ahci_43bit_dma,
52 board_ahci_ign_iferr,
53 board_ahci_no_debounce_delay,
54 board_ahci_no_msi,
55 /*
56 * board_ahci_pcs_quirk is for legacy Intel platforms.
57 * Modern Intel platforms should use board_ahci instead.
58 * (Some modern Intel platforms might have been added with
59 * board_ahci_pcs_quirk, however, we cannot change them to board_ahci
60 * without testing that the platform actually works without the quirk.)
61 */
62 board_ahci_pcs_quirk,
63 board_ahci_pcs_quirk_no_devslp,
64 board_ahci_pcs_quirk_no_sntf,
65 board_ahci_yes_fbs,
66
67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_al,
69 board_ahci_avn,
70 board_ahci_mcp65,
71 board_ahci_mcp77,
72 board_ahci_mcp89,
73 board_ahci_mv,
74 board_ahci_sb600,
75 board_ahci_sb700, /* for SB700 and SB800 */
76 board_ahci_vt8251,
77
78 /* aliases */
79 board_ahci_mcp_linux = board_ahci_mcp65,
80 board_ahci_mcp67 = board_ahci_mcp65,
81 board_ahci_mcp73 = board_ahci_mcp65,
82 board_ahci_mcp79 = board_ahci_mcp77,
83 };
84
85 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
86 static void ahci_remove_one(struct pci_dev *dev);
87 static void ahci_shutdown_one(struct pci_dev *dev);
88 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
89 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
92 unsigned long deadline);
93 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
94 static bool is_mcp89_apple(struct pci_dev *pdev);
95 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
96 unsigned long deadline);
97 #ifdef CONFIG_PM
98 static int ahci_pci_device_runtime_suspend(struct device *dev);
99 static int ahci_pci_device_runtime_resume(struct device *dev);
100 #ifdef CONFIG_PM_SLEEP
101 static int ahci_pci_device_suspend(struct device *dev);
102 static int ahci_pci_device_resume(struct device *dev);
103 #endif
104 #endif /* CONFIG_PM */
105
106 static const struct scsi_host_template ahci_sht = {
107 AHCI_SHT("ahci"),
108 };
109
110 static struct ata_port_operations ahci_vt8251_ops = {
111 .inherits = &ahci_ops,
112 .hardreset = ahci_vt8251_hardreset,
113 };
114
115 static struct ata_port_operations ahci_p5wdh_ops = {
116 .inherits = &ahci_ops,
117 .hardreset = ahci_p5wdh_hardreset,
118 };
119
120 static struct ata_port_operations ahci_avn_ops = {
121 .inherits = &ahci_ops,
122 .hardreset = ahci_avn_hardreset,
123 };
124
125 static const struct ata_port_info ahci_port_info[] = {
126 /* by features */
127 [board_ahci] = {
128 .flags = AHCI_FLAG_COMMON,
129 .pio_mask = ATA_PIO4,
130 .udma_mask = ATA_UDMA6,
131 .port_ops = &ahci_ops,
132 },
133 [board_ahci_43bit_dma] = {
134 AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
139 },
140 [board_ahci_ign_iferr] = {
141 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
142 .flags = AHCI_FLAG_COMMON,
143 .pio_mask = ATA_PIO4,
144 .udma_mask = ATA_UDMA6,
145 .port_ops = &ahci_ops,
146 },
147 [board_ahci_no_debounce_delay] = {
148 .flags = AHCI_FLAG_COMMON,
149 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
153 },
154 [board_ahci_no_msi] = {
155 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
156 .flags = AHCI_FLAG_COMMON,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
160 },
161 [board_ahci_pcs_quirk] = {
162 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK),
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
167 },
168 [board_ahci_pcs_quirk_no_devslp] = {
169 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK |
170 AHCI_HFLAG_NO_DEVSLP),
171 .flags = AHCI_FLAG_COMMON,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
175 },
176 [board_ahci_pcs_quirk_no_sntf] = {
177 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK |
178 AHCI_HFLAG_NO_SNTF),
179 .flags = AHCI_FLAG_COMMON,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_ops,
183 },
184 [board_ahci_yes_fbs] = {
185 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
186 .flags = AHCI_FLAG_COMMON,
187 .pio_mask = ATA_PIO4,
188 .udma_mask = ATA_UDMA6,
189 .port_ops = &ahci_ops,
190 },
191 /* by chipsets */
192 [board_ahci_al] = {
193 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
194 .flags = AHCI_FLAG_COMMON,
195 .pio_mask = ATA_PIO4,
196 .udma_mask = ATA_UDMA6,
197 .port_ops = &ahci_ops,
198 },
199 [board_ahci_avn] = {
200 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK),
201 .flags = AHCI_FLAG_COMMON,
202 .pio_mask = ATA_PIO4,
203 .udma_mask = ATA_UDMA6,
204 .port_ops = &ahci_avn_ops,
205 },
206 [board_ahci_mcp65] = {
207 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
208 AHCI_HFLAG_YES_NCQ),
209 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
210 .pio_mask = ATA_PIO4,
211 .udma_mask = ATA_UDMA6,
212 .port_ops = &ahci_ops,
213 },
214 [board_ahci_mcp77] = {
215 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
216 .flags = AHCI_FLAG_COMMON,
217 .pio_mask = ATA_PIO4,
218 .udma_mask = ATA_UDMA6,
219 .port_ops = &ahci_ops,
220 },
221 [board_ahci_mcp89] = {
222 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
223 .flags = AHCI_FLAG_COMMON,
224 .pio_mask = ATA_PIO4,
225 .udma_mask = ATA_UDMA6,
226 .port_ops = &ahci_ops,
227 },
228 [board_ahci_mv] = {
229 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
230 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
231 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
232 .pio_mask = ATA_PIO4,
233 .udma_mask = ATA_UDMA6,
234 .port_ops = &ahci_ops,
235 },
236 [board_ahci_sb600] = {
237 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
238 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
239 AHCI_HFLAG_32BIT_ONLY),
240 .flags = AHCI_FLAG_COMMON,
241 .pio_mask = ATA_PIO4,
242 .udma_mask = ATA_UDMA6,
243 .port_ops = &ahci_pmp_retry_srst_ops,
244 },
245 [board_ahci_sb700] = { /* for SB700 and SB800 */
246 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
247 .flags = AHCI_FLAG_COMMON,
248 .pio_mask = ATA_PIO4,
249 .udma_mask = ATA_UDMA6,
250 .port_ops = &ahci_pmp_retry_srst_ops,
251 },
252 [board_ahci_vt8251] = {
253 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
254 .flags = AHCI_FLAG_COMMON,
255 .pio_mask = ATA_PIO4,
256 .udma_mask = ATA_UDMA6,
257 .port_ops = &ahci_vt8251_ops,
258 },
259 };
260
261 static const struct pci_device_id ahci_pci_tbl[] = {
262 /* Intel */
263 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci_pcs_quirk }, /* Comet Lake PCH-H RAID */
264 { PCI_VDEVICE(INTEL, 0x2652), board_ahci_pcs_quirk }, /* ICH6 */
265 { PCI_VDEVICE(INTEL, 0x2653), board_ahci_pcs_quirk }, /* ICH6M */
266 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci_pcs_quirk }, /* ICH7 */
267 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci_pcs_quirk }, /* ICH7M */
268 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci_pcs_quirk }, /* ICH7R */
269 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
270 { PCI_VDEVICE(INTEL, 0x2681), board_ahci_pcs_quirk }, /* ESB2 */
271 { PCI_VDEVICE(INTEL, 0x2682), board_ahci_pcs_quirk }, /* ESB2 */
272 { PCI_VDEVICE(INTEL, 0x2683), board_ahci_pcs_quirk }, /* ESB2 */
273 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci_pcs_quirk }, /* ICH7-M DH */
274 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pcs_quirk }, /* ICH8 */
275 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pcs_quirk_no_sntf }, /* ICH8/Lewisburg RAID*/
276 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pcs_quirk }, /* ICH8 */
277 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pcs_quirk }, /* ICH8M */
278 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pcs_quirk }, /* ICH8M */
279 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pcs_quirk }, /* ICH9 */
280 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pcs_quirk }, /* ICH9 */
281 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pcs_quirk }, /* ICH9 */
282 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pcs_quirk }, /* ICH9 */
283 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pcs_quirk }, /* ICH9 */
284 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pcs_quirk }, /* ICH9M */
285 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pcs_quirk }, /* ICH9M */
286 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pcs_quirk }, /* ICH9M */
287 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pcs_quirk }, /* ICH9M */
288 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pcs_quirk }, /* ICH9M */
289 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pcs_quirk }, /* ICH9 */
290 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pcs_quirk }, /* ICH9M */
291 { PCI_VDEVICE(INTEL, 0x502a), board_ahci_pcs_quirk }, /* Tolapai */
292 { PCI_VDEVICE(INTEL, 0x502b), board_ahci_pcs_quirk }, /* Tolapai */
293 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci_pcs_quirk }, /* ICH10 */
294 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci_pcs_quirk }, /* ICH10 */
295 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci_pcs_quirk }, /* ICH10 */
296 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci_pcs_quirk }, /* PCH AHCI */
297 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci_pcs_quirk }, /* PCH AHCI */
298 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci_pcs_quirk }, /* PCH RAID */
299 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci_pcs_quirk }, /* PCH RAID */
300 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_pcs_quirk }, /* PCH M AHCI */
301 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci_pcs_quirk }, /* PCH RAID */
302 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_pcs_quirk }, /* PCH M RAID */
303 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci_pcs_quirk }, /* PCH AHCI */
304 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
311 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
312 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
313 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
316 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
317 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
318 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
319 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
320 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
321 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
322 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
323 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
324 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci_pcs_quirk }, /* CPT AHCI */
325 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_pcs_quirk }, /* CPT M AHCI */
326 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci_pcs_quirk }, /* CPT RAID */
327 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_pcs_quirk }, /* CPT M RAID */
328 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci_pcs_quirk }, /* CPT RAID */
329 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci_pcs_quirk }, /* CPT RAID */
330 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci_pcs_quirk }, /* PBG AHCI */
331 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci_pcs_quirk }, /* PBG RAID */
332 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci_pcs_quirk }, /* PBG RAID */
333 { PCI_VDEVICE(INTEL, 0x2323), board_ahci_pcs_quirk }, /* DH89xxCC AHCI */
334 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci_pcs_quirk }, /* Panther Point AHCI */
335 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_pcs_quirk }, /* Panther M AHCI */
336 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci_pcs_quirk }, /* Panther Point RAID */
337 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci_pcs_quirk }, /* Panther Point RAID */
338 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci_pcs_quirk }, /* Panther Point RAID */
339 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_pcs_quirk }, /* Panther M RAID */
340 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci_pcs_quirk }, /* Panther Point RAID */
341 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci_pcs_quirk }, /* Lynx Point AHCI */
342 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_pcs_quirk }, /* Lynx M AHCI */
343 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci_pcs_quirk }, /* Lynx Point RAID */
344 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_pcs_quirk }, /* Lynx M RAID */
345 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci_pcs_quirk }, /* Lynx Point RAID */
346 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_pcs_quirk }, /* Lynx M RAID */
347 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci_pcs_quirk }, /* Lynx Point RAID */
348 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_pcs_quirk }, /* Lynx M RAID */
349 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_pcs_quirk }, /* Lynx LP AHCI */
350 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_pcs_quirk }, /* Lynx LP AHCI */
351 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_pcs_quirk }, /* Lynx LP RAID */
352 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_pcs_quirk }, /* Lynx LP RAID */
353 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_pcs_quirk }, /* Lynx LP RAID */
354 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_pcs_quirk }, /* Lynx LP RAID */
355 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_pcs_quirk }, /* Lynx LP RAID */
356 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_pcs_quirk }, /* Lynx LP RAID */
357 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_pcs_quirk }, /* Cannon Lake PCH-LP AHCI */
358 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci_pcs_quirk }, /* Avoton AHCI */
359 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci_pcs_quirk }, /* Avoton AHCI */
360 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci_pcs_quirk }, /* Avoton RAID */
361 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci_pcs_quirk }, /* Avoton RAID */
362 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci_pcs_quirk }, /* Avoton RAID */
363 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci_pcs_quirk }, /* Avoton RAID */
364 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci_pcs_quirk }, /* Avoton RAID */
365 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci_pcs_quirk }, /* Avoton RAID */
366 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
367 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
368 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
369 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
370 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
371 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
372 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
373 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
374 { PCI_VDEVICE(INTEL, 0x2823), board_ahci_pcs_quirk }, /* Wellsburg/Lewisburg AHCI*/
375 { PCI_VDEVICE(INTEL, 0x2826), board_ahci_pcs_quirk }, /* *burg SATA0 'RAID' */
376 { PCI_VDEVICE(INTEL, 0x2827), board_ahci_pcs_quirk }, /* *burg SATA1 'RAID' */
377 { PCI_VDEVICE(INTEL, 0x282f), board_ahci_pcs_quirk }, /* *burg SATA2 'RAID' */
378 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
379 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
380 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
381 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
382 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci_pcs_quirk }, /* Wellsburg AHCI */
383 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci_pcs_quirk }, /* Wellsburg RAID */
384 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci_pcs_quirk }, /* Wellsburg RAID */
385 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci_pcs_quirk }, /* Wellsburg RAID */
386 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci_pcs_quirk }, /* Wellsburg AHCI */
387 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci_pcs_quirk }, /* Wellsburg RAID */
388 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci_pcs_quirk }, /* Wellsburg RAID */
389 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci_pcs_quirk }, /* Wellsburg RAID */
390 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci_pcs_quirk }, /* Coleto Creek AHCI */
391 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_pcs_quirk }, /* Wildcat LP AHCI */
392 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_pcs_quirk }, /* Wildcat LP RAID */
393 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_pcs_quirk }, /* Wildcat LP RAID */
394 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_pcs_quirk }, /* Wildcat LP RAID */
395 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci_pcs_quirk }, /* 9 Series AHCI */
396 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_pcs_quirk }, /* 9 Series M AHCI */
397 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci_pcs_quirk }, /* 9 Series RAID */
398 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_pcs_quirk }, /* 9 Series M RAID */
399 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci_pcs_quirk }, /* 9 Series RAID */
400 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_pcs_quirk }, /* 9 Series M RAID */
401 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci_pcs_quirk }, /* 9 Series RAID */
402 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_pcs_quirk }, /* 9 Series M RAID */
403 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_pcs_quirk }, /* Sunrise LP AHCI */
404 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_pcs_quirk }, /* Sunrise LP RAID */
405 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_pcs_quirk }, /* Sunrise LP RAID */
406 { PCI_VDEVICE(INTEL, 0xa102), board_ahci_pcs_quirk }, /* Sunrise Point-H AHCI */
407 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_pcs_quirk }, /* Sunrise M AHCI */
408 { PCI_VDEVICE(INTEL, 0xa105), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
409 { PCI_VDEVICE(INTEL, 0xa106), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
410 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_pcs_quirk }, /* Sunrise M RAID */
411 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
412 { PCI_VDEVICE(INTEL, 0xa182), board_ahci_pcs_quirk }, /* Lewisburg AHCI*/
413 { PCI_VDEVICE(INTEL, 0xa186), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
414 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
415 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
416 { PCI_VDEVICE(INTEL, 0xa202), board_ahci_pcs_quirk }, /* Lewisburg AHCI*/
417 { PCI_VDEVICE(INTEL, 0xa206), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
418 { PCI_VDEVICE(INTEL, 0xa252), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
419 { PCI_VDEVICE(INTEL, 0xa256), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
420 { PCI_VDEVICE(INTEL, 0xa356), board_ahci_pcs_quirk }, /* Cannon Lake PCH-H RAID */
421 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci_pcs_quirk }, /* Comet Lake-H RAID */
422 { PCI_VDEVICE(INTEL, 0xa386), board_ahci_pcs_quirk }, /* Comet Lake PCH-V RAID */
423 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_pcs_quirk }, /* Bay Trail AHCI */
424 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_pcs_quirk_no_devslp }, /* Bay Trail AHCI */
425 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_pcs_quirk }, /* Cherry Tr. AHCI */
426 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_pcs_quirk }, /* ApolloLake AHCI */
427 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_pcs_quirk }, /* Ice Lake LP AHCI */
428 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_pcs_quirk }, /* Comet Lake PCH-U AHCI */
429 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_pcs_quirk }, /* Comet Lake PCH RAID */
430 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
431 { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_pcs_quirk }, /* Elkhart Lake AHCI */
432
433 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
434 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
435 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
436 /* JMicron 362B and 362C have an AHCI function with IDE class code */
437 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
438 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
439 /* May need to update quirk_jmicron_async_suspend() for additions */
440
441 /* ATI */
442 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
443 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
444 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
445 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
446 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
447 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
448 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
449
450 /* Amazon's Annapurna Labs support */
451 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
452 .class = PCI_CLASS_STORAGE_SATA_AHCI,
453 .class_mask = 0xffffff,
454 board_ahci_al },
455 /* AMD */
456 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
457 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
458 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
459 { PCI_VDEVICE(AMD, 0x7901), board_ahci }, /* AMD Green Sardine */
460 /* AMD is using RAID class only for ahci controllers */
461 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
462 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
463
464 /* Dell S140/S150 */
465 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
466 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci_pcs_quirk },
467
468 /* VIA */
469 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
470 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
471
472 /* NVIDIA */
473 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
474 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
475 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
476 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
477 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
478 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
479 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
480 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
481 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
482 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
483 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
484 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
485 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
486 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
487 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
488 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
489 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
490 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
491 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
492 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
493 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
494 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
495 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
496 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
497 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
498 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
499 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
500 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
501 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
502 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
503 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
504 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
505 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
506 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
507 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
508 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
509 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
510 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
511 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
512 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
513 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
514 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
515 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
516 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
517 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
518 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
519 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
520 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
521 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
522 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
523 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
524 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
525 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
526 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
527 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
528 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
529 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
530 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
531 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
532 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
533 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
534 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
535 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
536 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
537 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
538 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
539 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
540 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
541 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
542 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
543 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
544 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
545 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
546 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
547 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
548 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
549 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
550 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
551 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
552 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
553 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
554 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
555 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
556 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
557
558 /* SiS */
559 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
560 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
561 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
562
563 /* ST Microelectronics */
564 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
565
566 /* Marvell */
567 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
568 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
569 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
570 .class = PCI_CLASS_STORAGE_SATA_AHCI,
571 .class_mask = 0xffffff,
572 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
573 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
574 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
575 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
576 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
577 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
578 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
579 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
580 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
581 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
582 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
583 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
584 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
585 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
586 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
587 .driver_data = board_ahci_yes_fbs },
588 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
589 .driver_data = board_ahci_yes_fbs },
590 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
591 .driver_data = board_ahci_yes_fbs },
592 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
593 .driver_data = board_ahci_yes_fbs },
594 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
595 .driver_data = board_ahci_no_debounce_delay },
596 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
597 .driver_data = board_ahci_yes_fbs },
598 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
599 .driver_data = board_ahci_yes_fbs },
600
601 /* Promise */
602 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
603 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
604
605 /* ASMedia */
606 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci_43bit_dma }, /* ASM1060 */
607 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci_43bit_dma }, /* ASM1060 */
608 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci_43bit_dma }, /* ASM1061 */
609 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci_43bit_dma }, /* ASM1061/1062 */
610 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci_43bit_dma }, /* ASM1061R */
611 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci_43bit_dma }, /* ASM1062R */
612 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci_43bit_dma }, /* ASM1062+JMB575 */
613 { PCI_VDEVICE(ASMEDIA, 0x1062), board_ahci }, /* ASM1062A */
614 { PCI_VDEVICE(ASMEDIA, 0x1064), board_ahci }, /* ASM1064 */
615 { PCI_VDEVICE(ASMEDIA, 0x1164), board_ahci }, /* ASM1164 */
616 { PCI_VDEVICE(ASMEDIA, 0x1165), board_ahci }, /* ASM1165 */
617 { PCI_VDEVICE(ASMEDIA, 0x1166), board_ahci }, /* ASM1166 */
618
619 /*
620 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
621 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
622 */
623 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_no_msi },
624 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_no_msi },
625
626 /* Enmotus */
627 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
628
629 /* Loongson */
630 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
631
632 /* Generic, PCI class code for AHCI */
633 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
634 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
635
636 { } /* terminate list */
637 };
638
639 static const struct dev_pm_ops ahci_pci_pm_ops = {
640 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
641 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
642 ahci_pci_device_runtime_resume, NULL)
643 };
644
645 static struct pci_driver ahci_pci_driver = {
646 .name = DRV_NAME,
647 .id_table = ahci_pci_tbl,
648 .probe = ahci_init_one,
649 .remove = ahci_remove_one,
650 .shutdown = ahci_shutdown_one,
651 .driver = {
652 .pm = &ahci_pci_pm_ops,
653 },
654 };
655
656 #if IS_ENABLED(CONFIG_PATA_MARVELL)
657 static int marvell_enable;
658 #else
659 static int marvell_enable = 1;
660 #endif
661 module_param(marvell_enable, int, 0644);
662 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
663
664 static int mobile_lpm_policy = -1;
665 module_param(mobile_lpm_policy, int, 0644);
666 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
667
668 static char *ahci_mask_port_map;
669 module_param_named(mask_port_map, ahci_mask_port_map, charp, 0444);
670 MODULE_PARM_DESC(mask_port_map,
671 "32-bits port map masks to ignore controllers ports. "
672 "Valid values are: "
673 "\"<mask>\" to apply the same mask to all AHCI controller "
674 "devices, and \"<pci_dev>=<mask>,<pci_dev>=<mask>,...\" to "
675 "specify different masks for the controllers specified, "
676 "where <pci_dev> is the PCI ID of an AHCI controller in the "
677 "form \"domain:bus:dev.func\"");
678
ahci_apply_port_map_mask(struct device * dev,struct ahci_host_priv * hpriv,char * mask_s)679 static void ahci_apply_port_map_mask(struct device *dev,
680 struct ahci_host_priv *hpriv, char *mask_s)
681 {
682 unsigned int mask;
683
684 if (kstrtouint(mask_s, 0, &mask)) {
685 dev_err(dev, "Invalid port map mask\n");
686 return;
687 }
688
689 hpriv->mask_port_map = mask;
690 }
691
ahci_get_port_map_mask(struct device * dev,struct ahci_host_priv * hpriv)692 static void ahci_get_port_map_mask(struct device *dev,
693 struct ahci_host_priv *hpriv)
694 {
695 char *param, *end, *str, *mask_s;
696 char *name;
697
698 if (!strlen(ahci_mask_port_map))
699 return;
700
701 str = kstrdup(ahci_mask_port_map, GFP_KERNEL);
702 if (!str)
703 return;
704
705 /* Handle single mask case */
706 if (!strchr(str, '=')) {
707 ahci_apply_port_map_mask(dev, hpriv, str);
708 goto free;
709 }
710
711 /*
712 * Mask list case: parse the parameter to apply the mask only if
713 * the device name matches.
714 */
715 param = str;
716 end = param + strlen(param);
717 while (param && param < end && *param) {
718 name = param;
719 param = strchr(name, '=');
720 if (!param)
721 break;
722
723 *param = '\0';
724 param++;
725 if (param >= end)
726 break;
727
728 if (strcmp(dev_name(dev), name) != 0) {
729 param = strchr(param, ',');
730 if (param)
731 param++;
732 continue;
733 }
734
735 mask_s = param;
736 param = strchr(mask_s, ',');
737 if (param) {
738 *param = '\0';
739 param++;
740 }
741
742 ahci_apply_port_map_mask(dev, hpriv, mask_s);
743 }
744
745 free:
746 kfree(str);
747 }
748
ahci_pci_save_initial_config(struct pci_dev * pdev,struct ahci_host_priv * hpriv)749 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
750 struct ahci_host_priv *hpriv)
751 {
752 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
753 dev_info(&pdev->dev, "JMB361 has only one port\n");
754 hpriv->saved_port_map = 1;
755 }
756
757 /*
758 * Temporary Marvell 6145 hack: PATA port presence
759 * is asserted through the standard AHCI port
760 * presence register, as bit 4 (counting from 0)
761 */
762 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
763 if (pdev->device == 0x6121)
764 hpriv->mask_port_map = 0x3;
765 else
766 hpriv->mask_port_map = 0xf;
767 dev_info(&pdev->dev,
768 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
769 }
770
771 /* Handle port map masks passed as module parameter. */
772 if (ahci_mask_port_map)
773 ahci_get_port_map_mask(&pdev->dev, hpriv);
774
775 ahci_save_initial_config(&pdev->dev, hpriv);
776 }
777
ahci_pci_reset_controller(struct ata_host * host)778 static int ahci_pci_reset_controller(struct ata_host *host)
779 {
780 struct pci_dev *pdev = to_pci_dev(host->dev);
781 struct ahci_host_priv *hpriv = host->private_data;
782 int rc;
783
784 rc = ahci_reset_controller(host);
785 if (rc)
786 return rc;
787
788 /*
789 * If platform firmware failed to enable ports, try to enable
790 * them here.
791 */
792 ahci_intel_pcs_quirk(pdev, hpriv);
793
794 return 0;
795 }
796
ahci_pci_init_controller(struct ata_host * host)797 static void ahci_pci_init_controller(struct ata_host *host)
798 {
799 struct ahci_host_priv *hpriv = host->private_data;
800 struct pci_dev *pdev = to_pci_dev(host->dev);
801 void __iomem *port_mmio;
802 u32 tmp;
803 int mv;
804
805 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
806 if (pdev->device == 0x6121)
807 mv = 2;
808 else
809 mv = 4;
810 port_mmio = __ahci_port_base(hpriv, mv);
811
812 writel(0, port_mmio + PORT_IRQ_MASK);
813
814 /* clear port IRQ */
815 tmp = readl(port_mmio + PORT_IRQ_STAT);
816 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
817 if (tmp)
818 writel(tmp, port_mmio + PORT_IRQ_STAT);
819 }
820
821 ahci_init_controller(host);
822 }
823
ahci_vt8251_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)824 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
825 unsigned long deadline)
826 {
827 struct ata_port *ap = link->ap;
828 struct ahci_host_priv *hpriv = ap->host->private_data;
829 bool online;
830 int rc;
831
832 hpriv->stop_engine(ap);
833
834 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
835 deadline, &online, NULL);
836
837 hpriv->start_engine(ap);
838
839 /* vt8251 doesn't clear BSY on signature FIS reception,
840 * request follow-up softreset.
841 */
842 return online ? -EAGAIN : rc;
843 }
844
ahci_p5wdh_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)845 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
846 unsigned long deadline)
847 {
848 struct ata_port *ap = link->ap;
849 struct ahci_port_priv *pp = ap->private_data;
850 struct ahci_host_priv *hpriv = ap->host->private_data;
851 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
852 struct ata_taskfile tf;
853 bool online;
854 int rc;
855
856 hpriv->stop_engine(ap);
857
858 /* clear D2H reception area to properly wait for D2H FIS */
859 ata_tf_init(link->device, &tf);
860 tf.status = ATA_BUSY;
861 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
862
863 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
864 deadline, &online, NULL);
865
866 hpriv->start_engine(ap);
867
868 /* The pseudo configuration device on SIMG4726 attached to
869 * ASUS P5W-DH Deluxe doesn't send signature FIS after
870 * hardreset if no device is attached to the first downstream
871 * port && the pseudo device locks up on SRST w/ PMP==0. To
872 * work around this, wait for !BSY only briefly. If BSY isn't
873 * cleared, perform CLO and proceed to IDENTIFY (achieved by
874 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
875 *
876 * Wait for two seconds. Devices attached to downstream port
877 * which can't process the following IDENTIFY after this will
878 * have to be reset again. For most cases, this should
879 * suffice while making probing snappish enough.
880 */
881 if (online) {
882 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
883 ahci_check_ready);
884 if (rc)
885 ahci_kick_engine(ap);
886 }
887 return rc;
888 }
889
890 /*
891 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
892 *
893 * It has been observed with some SSDs that the timing of events in the
894 * link synchronization phase can leave the port in a state that can not
895 * be recovered by a SATA-hard-reset alone. The failing signature is
896 * SStatus.DET stuck at 1 ("Device presence detected but Phy
897 * communication not established"). It was found that unloading and
898 * reloading the driver when this problem occurs allows the drive
899 * connection to be recovered (DET advanced to 0x3). The critical
900 * component of reloading the driver is that the port state machines are
901 * reset by bouncing "port enable" in the AHCI PCS configuration
902 * register. So, reproduce that effect by bouncing a port whenever we
903 * see DET==1 after a reset.
904 */
ahci_avn_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)905 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
906 unsigned long deadline)
907 {
908 const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
909 struct ata_port *ap = link->ap;
910 struct ahci_port_priv *pp = ap->private_data;
911 struct ahci_host_priv *hpriv = ap->host->private_data;
912 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
913 unsigned long tmo = deadline - jiffies;
914 struct ata_taskfile tf;
915 bool online;
916 int rc, i;
917
918 hpriv->stop_engine(ap);
919
920 for (i = 0; i < 2; i++) {
921 u16 val;
922 u32 sstatus;
923 int port = ap->port_no;
924 struct ata_host *host = ap->host;
925 struct pci_dev *pdev = to_pci_dev(host->dev);
926
927 /* clear D2H reception area to properly wait for D2H FIS */
928 ata_tf_init(link->device, &tf);
929 tf.status = ATA_BUSY;
930 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
931
932 rc = sata_link_hardreset(link, timing, deadline, &online,
933 ahci_check_ready);
934
935 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
936 (sstatus & 0xf) != 1)
937 break;
938
939 ata_link_info(link, "avn bounce port%d\n", port);
940
941 pci_read_config_word(pdev, 0x92, &val);
942 val &= ~(1 << port);
943 pci_write_config_word(pdev, 0x92, val);
944 ata_msleep(ap, 1000);
945 val |= 1 << port;
946 pci_write_config_word(pdev, 0x92, val);
947 deadline += tmo;
948 }
949
950 hpriv->start_engine(ap);
951
952 if (online)
953 *class = ahci_dev_classify(ap);
954
955 return rc;
956 }
957
958
959 #ifdef CONFIG_PM
ahci_pci_disable_interrupts(struct ata_host * host)960 static void ahci_pci_disable_interrupts(struct ata_host *host)
961 {
962 struct ahci_host_priv *hpriv = host->private_data;
963 void __iomem *mmio = hpriv->mmio;
964 u32 ctl;
965
966 /* AHCI spec rev1.1 section 8.3.3:
967 * Software must disable interrupts prior to requesting a
968 * transition of the HBA to D3 state.
969 */
970 ctl = readl(mmio + HOST_CTL);
971 ctl &= ~HOST_IRQ_EN;
972 writel(ctl, mmio + HOST_CTL);
973 readl(mmio + HOST_CTL); /* flush */
974 }
975
ahci_pci_device_runtime_suspend(struct device * dev)976 static int ahci_pci_device_runtime_suspend(struct device *dev)
977 {
978 struct pci_dev *pdev = to_pci_dev(dev);
979 struct ata_host *host = pci_get_drvdata(pdev);
980
981 ahci_pci_disable_interrupts(host);
982 return 0;
983 }
984
ahci_pci_device_runtime_resume(struct device * dev)985 static int ahci_pci_device_runtime_resume(struct device *dev)
986 {
987 struct pci_dev *pdev = to_pci_dev(dev);
988 struct ata_host *host = pci_get_drvdata(pdev);
989 int rc;
990
991 rc = ahci_pci_reset_controller(host);
992 if (rc)
993 return rc;
994 ahci_pci_init_controller(host);
995 return 0;
996 }
997
998 #ifdef CONFIG_PM_SLEEP
ahci_pci_device_suspend(struct device * dev)999 static int ahci_pci_device_suspend(struct device *dev)
1000 {
1001 struct pci_dev *pdev = to_pci_dev(dev);
1002 struct ata_host *host = pci_get_drvdata(pdev);
1003 struct ahci_host_priv *hpriv = host->private_data;
1004
1005 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
1006 dev_err(&pdev->dev,
1007 "BIOS update required for suspend/resume\n");
1008 return -EIO;
1009 }
1010
1011 ahci_pci_disable_interrupts(host);
1012 ata_host_suspend(host, PMSG_SUSPEND);
1013 return 0;
1014 }
1015
ahci_pci_device_resume(struct device * dev)1016 static int ahci_pci_device_resume(struct device *dev)
1017 {
1018 struct pci_dev *pdev = to_pci_dev(dev);
1019 struct ata_host *host = pci_get_drvdata(pdev);
1020 int rc;
1021
1022 /* Apple BIOS helpfully mangles the registers on resume */
1023 if (is_mcp89_apple(pdev))
1024 ahci_mcp89_apple_enable(pdev);
1025
1026 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1027 rc = ahci_pci_reset_controller(host);
1028 if (rc)
1029 return rc;
1030
1031 ahci_pci_init_controller(host);
1032 }
1033
1034 ata_host_resume(host);
1035
1036 return 0;
1037 }
1038 #endif
1039
1040 #endif /* CONFIG_PM */
1041
ahci_configure_dma_masks(struct pci_dev * pdev,struct ahci_host_priv * hpriv)1042 static int ahci_configure_dma_masks(struct pci_dev *pdev,
1043 struct ahci_host_priv *hpriv)
1044 {
1045 int dma_bits;
1046 int rc;
1047
1048 if (hpriv->cap & HOST_CAP_64) {
1049 dma_bits = 64;
1050 if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY)
1051 dma_bits = 43;
1052 } else {
1053 dma_bits = 32;
1054 }
1055
1056 /*
1057 * If the device fixup already set the dma_mask to some non-standard
1058 * value, don't extend it here. This happens on STA2X11, for example.
1059 *
1060 * XXX: manipulating the DMA mask from platform code is completely
1061 * bogus, platform code should use dev->bus_dma_limit instead..
1062 */
1063 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
1064 return 0;
1065
1066 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
1067 if (rc)
1068 dev_err(&pdev->dev, "DMA enable failed\n");
1069 return rc;
1070 }
1071
ahci_pci_print_info(struct ata_host * host)1072 static void ahci_pci_print_info(struct ata_host *host)
1073 {
1074 struct pci_dev *pdev = to_pci_dev(host->dev);
1075 u16 cc;
1076 const char *scc_s;
1077
1078 pci_read_config_word(pdev, 0x0a, &cc);
1079 if (cc == PCI_CLASS_STORAGE_IDE)
1080 scc_s = "IDE";
1081 else if (cc == PCI_CLASS_STORAGE_SATA)
1082 scc_s = "SATA";
1083 else if (cc == PCI_CLASS_STORAGE_RAID)
1084 scc_s = "RAID";
1085 else
1086 scc_s = "unknown";
1087
1088 ahci_print_info(host, scc_s);
1089 }
1090
1091 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
1092 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
1093 * support PMP and the 4726 either directly exports the device
1094 * attached to the first downstream port or acts as a hardware storage
1095 * controller and emulate a single ATA device (can be RAID 0/1 or some
1096 * other configuration).
1097 *
1098 * When there's no device attached to the first downstream port of the
1099 * 4726, "Config Disk" appears, which is a pseudo ATA device to
1100 * configure the 4726. However, ATA emulation of the device is very
1101 * lame. It doesn't send signature D2H Reg FIS after the initial
1102 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
1103 *
1104 * The following function works around the problem by always using
1105 * hardreset on the port and not depending on receiving signature FIS
1106 * afterward. If signature FIS isn't received soon, ATA class is
1107 * assumed without follow-up softreset.
1108 */
ahci_p5wdh_workaround(struct ata_host * host)1109 static void ahci_p5wdh_workaround(struct ata_host *host)
1110 {
1111 static const struct dmi_system_id sysids[] = {
1112 {
1113 .ident = "P5W DH Deluxe",
1114 .matches = {
1115 DMI_MATCH(DMI_SYS_VENDOR,
1116 "ASUSTEK COMPUTER INC"),
1117 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1118 },
1119 },
1120 { }
1121 };
1122 struct pci_dev *pdev = to_pci_dev(host->dev);
1123
1124 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1125 dmi_check_system(sysids)) {
1126 struct ata_port *ap = host->ports[1];
1127
1128 dev_info(&pdev->dev,
1129 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1130
1131 ap->ops = &ahci_p5wdh_ops;
1132 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1133 }
1134 }
1135
1136 /*
1137 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1138 * booting in BIOS compatibility mode. We restore the registers but not ID.
1139 */
ahci_mcp89_apple_enable(struct pci_dev * pdev)1140 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1141 {
1142 u32 val;
1143
1144 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1145
1146 pci_read_config_dword(pdev, 0xf8, &val);
1147 val |= 1 << 0x1b;
1148 /* the following changes the device ID, but appears not to affect function */
1149 /* val = (val & ~0xf0000000) | 0x80000000; */
1150 pci_write_config_dword(pdev, 0xf8, val);
1151
1152 pci_read_config_dword(pdev, 0x54c, &val);
1153 val |= 1 << 0xc;
1154 pci_write_config_dword(pdev, 0x54c, val);
1155
1156 pci_read_config_dword(pdev, 0x4a4, &val);
1157 val &= 0xff;
1158 val |= 0x01060100;
1159 pci_write_config_dword(pdev, 0x4a4, val);
1160
1161 pci_read_config_dword(pdev, 0x54c, &val);
1162 val &= ~(1 << 0xc);
1163 pci_write_config_dword(pdev, 0x54c, val);
1164
1165 pci_read_config_dword(pdev, 0xf8, &val);
1166 val &= ~(1 << 0x1b);
1167 pci_write_config_dword(pdev, 0xf8, val);
1168 }
1169
is_mcp89_apple(struct pci_dev * pdev)1170 static bool is_mcp89_apple(struct pci_dev *pdev)
1171 {
1172 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1173 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1174 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1175 pdev->subsystem_device == 0xcb89;
1176 }
1177
1178 /* only some SB600 ahci controllers can do 64bit DMA */
ahci_sb600_enable_64bit(struct pci_dev * pdev)1179 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1180 {
1181 static const struct dmi_system_id sysids[] = {
1182 /*
1183 * The oldest version known to be broken is 0901 and
1184 * working is 1501 which was released on 2007-10-26.
1185 * Enable 64bit DMA on 1501 and anything newer.
1186 *
1187 * Please read bko#9412 for more info.
1188 */
1189 {
1190 .ident = "ASUS M2A-VM",
1191 .matches = {
1192 DMI_MATCH(DMI_BOARD_VENDOR,
1193 "ASUSTeK Computer INC."),
1194 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1195 },
1196 .driver_data = "20071026", /* yyyymmdd */
1197 },
1198 /*
1199 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1200 * support 64bit DMA.
1201 *
1202 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1203 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1204 * This spelling mistake was fixed in BIOS version 1.5, so
1205 * 1.5 and later have the Manufacturer as
1206 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1207 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1208 *
1209 * BIOS versions earlier than 1.9 had a Board Product Name
1210 * DMI field of "MS-7376". This was changed to be
1211 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1212 * match on DMI_BOARD_NAME of "MS-7376".
1213 */
1214 {
1215 .ident = "MSI K9A2 Platinum",
1216 .matches = {
1217 DMI_MATCH(DMI_BOARD_VENDOR,
1218 "MICRO-STAR INTER"),
1219 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1220 },
1221 },
1222 /*
1223 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1224 * 64bit DMA.
1225 *
1226 * This board also had the typo mentioned above in the
1227 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1228 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1229 */
1230 {
1231 .ident = "MSI K9AGM2",
1232 .matches = {
1233 DMI_MATCH(DMI_BOARD_VENDOR,
1234 "MICRO-STAR INTER"),
1235 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1236 },
1237 },
1238 /*
1239 * All BIOS versions for the Asus M3A support 64bit DMA.
1240 * (all release versions from 0301 to 1206 were tested)
1241 */
1242 {
1243 .ident = "ASUS M3A",
1244 .matches = {
1245 DMI_MATCH(DMI_BOARD_VENDOR,
1246 "ASUSTeK Computer INC."),
1247 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1248 },
1249 },
1250 { }
1251 };
1252 const struct dmi_system_id *match;
1253 int year, month, date;
1254 char buf[9];
1255
1256 match = dmi_first_match(sysids);
1257 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1258 !match)
1259 return false;
1260
1261 if (!match->driver_data)
1262 goto enable_64bit;
1263
1264 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1265 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1266
1267 if (strcmp(buf, match->driver_data) >= 0)
1268 goto enable_64bit;
1269 else {
1270 dev_warn(&pdev->dev,
1271 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1272 match->ident);
1273 return false;
1274 }
1275
1276 enable_64bit:
1277 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1278 return true;
1279 }
1280
ahci_broken_system_poweroff(struct pci_dev * pdev)1281 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1282 {
1283 static const struct dmi_system_id broken_systems[] = {
1284 {
1285 .ident = "HP Compaq nx6310",
1286 .matches = {
1287 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1288 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1289 },
1290 /* PCI slot number of the controller */
1291 .driver_data = (void *)0x1FUL,
1292 },
1293 {
1294 .ident = "HP Compaq 6720s",
1295 .matches = {
1296 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1297 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1298 },
1299 /* PCI slot number of the controller */
1300 .driver_data = (void *)0x1FUL,
1301 },
1302
1303 { } /* terminate list */
1304 };
1305 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1306
1307 if (dmi) {
1308 unsigned long slot = (unsigned long)dmi->driver_data;
1309 /* apply the quirk only to on-board controllers */
1310 return slot == PCI_SLOT(pdev->devfn);
1311 }
1312
1313 return false;
1314 }
1315
ahci_broken_suspend(struct pci_dev * pdev)1316 static bool ahci_broken_suspend(struct pci_dev *pdev)
1317 {
1318 static const struct dmi_system_id sysids[] = {
1319 /*
1320 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1321 * to the harddisk doesn't become online after
1322 * resuming from STR. Warn and fail suspend.
1323 *
1324 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1325 *
1326 * Use dates instead of versions to match as HP is
1327 * apparently recycling both product and version
1328 * strings.
1329 *
1330 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1331 */
1332 {
1333 .ident = "dv4",
1334 .matches = {
1335 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1336 DMI_MATCH(DMI_PRODUCT_NAME,
1337 "HP Pavilion dv4 Notebook PC"),
1338 },
1339 .driver_data = "20090105", /* F.30 */
1340 },
1341 {
1342 .ident = "dv5",
1343 .matches = {
1344 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1345 DMI_MATCH(DMI_PRODUCT_NAME,
1346 "HP Pavilion dv5 Notebook PC"),
1347 },
1348 .driver_data = "20090506", /* F.16 */
1349 },
1350 {
1351 .ident = "dv6",
1352 .matches = {
1353 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1354 DMI_MATCH(DMI_PRODUCT_NAME,
1355 "HP Pavilion dv6 Notebook PC"),
1356 },
1357 .driver_data = "20090423", /* F.21 */
1358 },
1359 {
1360 .ident = "HDX18",
1361 .matches = {
1362 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1363 DMI_MATCH(DMI_PRODUCT_NAME,
1364 "HP HDX18 Notebook PC"),
1365 },
1366 .driver_data = "20090430", /* F.23 */
1367 },
1368 /*
1369 * Acer eMachines G725 has the same problem. BIOS
1370 * V1.03 is known to be broken. V3.04 is known to
1371 * work. Between, there are V1.06, V2.06 and V3.03
1372 * that we don't have much idea about. For now,
1373 * assume that anything older than V3.04 is broken.
1374 *
1375 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1376 */
1377 {
1378 .ident = "G725",
1379 .matches = {
1380 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1381 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1382 },
1383 .driver_data = "20091216", /* V3.04 */
1384 },
1385 { } /* terminate list */
1386 };
1387 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1388 int year, month, date;
1389 char buf[9];
1390
1391 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1392 return false;
1393
1394 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1395 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1396
1397 return strcmp(buf, dmi->driver_data) < 0;
1398 }
1399
ahci_broken_lpm(struct pci_dev * pdev)1400 static bool ahci_broken_lpm(struct pci_dev *pdev)
1401 {
1402 static const struct dmi_system_id sysids[] = {
1403 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1404 {
1405 .matches = {
1406 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1407 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1408 },
1409 .driver_data = "20180406", /* 1.31 */
1410 },
1411 {
1412 .matches = {
1413 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1414 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1415 },
1416 .driver_data = "20180420", /* 1.28 */
1417 },
1418 {
1419 .matches = {
1420 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1421 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1422 },
1423 .driver_data = "20180315", /* 1.33 */
1424 },
1425 {
1426 .matches = {
1427 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1428 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1429 },
1430 /*
1431 * Note date based on release notes, 2.35 has been
1432 * reported to be good, but I've been unable to get
1433 * a hold of the reporter to get the DMI BIOS date.
1434 * TODO: fix this.
1435 */
1436 .driver_data = "20180310", /* 2.35 */
1437 },
1438 { } /* terminate list */
1439 };
1440 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1441 int year, month, date;
1442 char buf[9];
1443
1444 if (!dmi)
1445 return false;
1446
1447 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1448 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1449
1450 return strcmp(buf, dmi->driver_data) < 0;
1451 }
1452
ahci_broken_online(struct pci_dev * pdev)1453 static bool ahci_broken_online(struct pci_dev *pdev)
1454 {
1455 #define ENCODE_BUSDEVFN(bus, slot, func) \
1456 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1457 static const struct dmi_system_id sysids[] = {
1458 /*
1459 * There are several gigabyte boards which use
1460 * SIMG5723s configured as hardware RAID. Certain
1461 * 5723 firmware revisions shipped there keep the link
1462 * online but fail to answer properly to SRST or
1463 * IDENTIFY when no device is attached downstream
1464 * causing libata to retry quite a few times leading
1465 * to excessive detection delay.
1466 *
1467 * As these firmwares respond to the second reset try
1468 * with invalid device signature, considering unknown
1469 * sig as offline works around the problem acceptably.
1470 */
1471 {
1472 .ident = "EP45-DQ6",
1473 .matches = {
1474 DMI_MATCH(DMI_BOARD_VENDOR,
1475 "Gigabyte Technology Co., Ltd."),
1476 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1477 },
1478 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1479 },
1480 {
1481 .ident = "EP45-DS5",
1482 .matches = {
1483 DMI_MATCH(DMI_BOARD_VENDOR,
1484 "Gigabyte Technology Co., Ltd."),
1485 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1486 },
1487 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1488 },
1489 { } /* terminate list */
1490 };
1491 #undef ENCODE_BUSDEVFN
1492 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1493 unsigned int val;
1494
1495 if (!dmi)
1496 return false;
1497
1498 val = (unsigned long)dmi->driver_data;
1499
1500 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1501 }
1502
1503 #ifdef CONFIG_ATA_ACPI
ahci_gtf_filter_workaround(struct ata_host * host)1504 static void ahci_gtf_filter_workaround(struct ata_host *host)
1505 {
1506 static const struct dmi_system_id sysids[] = {
1507 /*
1508 * Aspire 3810T issues a bunch of SATA enable commands
1509 * via _GTF including an invalid one and one which is
1510 * rejected by the device. Among the successful ones
1511 * is FPDMA non-zero offset enable which when enabled
1512 * only on the drive side leads to NCQ command
1513 * failures. Filter it out.
1514 */
1515 {
1516 .ident = "Aspire 3810T",
1517 .matches = {
1518 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1519 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1520 },
1521 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1522 },
1523 { }
1524 };
1525 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1526 unsigned int filter;
1527 int i;
1528
1529 if (!dmi)
1530 return;
1531
1532 filter = (unsigned long)dmi->driver_data;
1533 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1534 filter, dmi->ident);
1535
1536 for (i = 0; i < host->n_ports; i++) {
1537 struct ata_port *ap = host->ports[i];
1538 struct ata_link *link;
1539 struct ata_device *dev;
1540
1541 ata_for_each_link(link, ap, EDGE)
1542 ata_for_each_dev(dev, link, ALL)
1543 dev->gtf_filter |= filter;
1544 }
1545 }
1546 #else
ahci_gtf_filter_workaround(struct ata_host * host)1547 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1548 {}
1549 #endif
1550
1551 /*
1552 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1553 * as DUMMY, or detected but eventually get a "link down" and never get up
1554 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1555 * port_map may hold a value of 0x00.
1556 *
1557 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1558 * and can significantly reduce the occurrence of the problem.
1559 *
1560 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1561 */
acer_sa5_271_workaround(struct ahci_host_priv * hpriv,struct pci_dev * pdev)1562 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1563 struct pci_dev *pdev)
1564 {
1565 static const struct dmi_system_id sysids[] = {
1566 {
1567 .ident = "Acer Switch Alpha 12",
1568 .matches = {
1569 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1570 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1571 },
1572 },
1573 { }
1574 };
1575
1576 if (dmi_check_system(sysids)) {
1577 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1578 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1579 hpriv->port_map = 0x7;
1580 hpriv->cap = 0xC734FF02;
1581 }
1582 }
1583 }
1584
1585 #ifdef CONFIG_ARM64
1586 /*
1587 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1588 * Workaround is to make sure all pending IRQs are served before leaving
1589 * handler.
1590 */
ahci_thunderx_irq_handler(int irq,void * dev_instance)1591 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1592 {
1593 struct ata_host *host = dev_instance;
1594 struct ahci_host_priv *hpriv;
1595 unsigned int rc = 0;
1596 void __iomem *mmio;
1597 u32 irq_stat, irq_masked;
1598 unsigned int handled = 1;
1599
1600 hpriv = host->private_data;
1601 mmio = hpriv->mmio;
1602 irq_stat = readl(mmio + HOST_IRQ_STAT);
1603 if (!irq_stat)
1604 return IRQ_NONE;
1605
1606 do {
1607 irq_masked = irq_stat & hpriv->port_map;
1608 spin_lock(&host->lock);
1609 rc = ahci_handle_port_intr(host, irq_masked);
1610 if (!rc)
1611 handled = 0;
1612 writel(irq_stat, mmio + HOST_IRQ_STAT);
1613 irq_stat = readl(mmio + HOST_IRQ_STAT);
1614 spin_unlock(&host->lock);
1615 } while (irq_stat);
1616
1617 return IRQ_RETVAL(handled);
1618 }
1619 #endif
1620
ahci_remap_check(struct pci_dev * pdev,int bar,struct ahci_host_priv * hpriv)1621 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1622 struct ahci_host_priv *hpriv)
1623 {
1624 int i;
1625 u32 cap;
1626
1627 /*
1628 * Check if this device might have remapped nvme devices.
1629 */
1630 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1631 pci_resource_len(pdev, bar) < SZ_512K ||
1632 bar != AHCI_PCI_BAR_STANDARD ||
1633 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1634 return;
1635
1636 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1637 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1638 if ((cap & (1 << i)) == 0)
1639 continue;
1640 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1641 != PCI_CLASS_STORAGE_EXPRESS)
1642 continue;
1643
1644 /* We've found a remapped device */
1645 hpriv->remapped_nvme++;
1646 }
1647
1648 if (!hpriv->remapped_nvme)
1649 return;
1650
1651 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1652 hpriv->remapped_nvme);
1653 dev_warn(&pdev->dev,
1654 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1655
1656 /*
1657 * Don't rely on the msi-x capability in the remap case,
1658 * share the legacy interrupt across ahci and remapped devices.
1659 */
1660 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1661 }
1662
ahci_get_irq_vector(struct ata_host * host,int port)1663 static int ahci_get_irq_vector(struct ata_host *host, int port)
1664 {
1665 return pci_irq_vector(to_pci_dev(host->dev), port);
1666 }
1667
ahci_init_msi(struct pci_dev * pdev,unsigned int n_ports,struct ahci_host_priv * hpriv)1668 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1669 struct ahci_host_priv *hpriv)
1670 {
1671 int nvec;
1672
1673 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1674 return -ENODEV;
1675
1676 /*
1677 * If number of MSIs is less than number of ports then Sharing Last
1678 * Message mode could be enforced. In this case assume that advantage
1679 * of multipe MSIs is negated and use single MSI mode instead.
1680 */
1681 if (n_ports > 1) {
1682 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1683 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1684 if (nvec > 0) {
1685 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1686 hpriv->get_irq_vector = ahci_get_irq_vector;
1687 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1688 return nvec;
1689 }
1690
1691 /*
1692 * Fallback to single MSI mode if the controller
1693 * enforced MRSM mode.
1694 */
1695 printk(KERN_INFO
1696 "ahci: MRSM is on, fallback to single MSI\n");
1697 pci_free_irq_vectors(pdev);
1698 }
1699 }
1700
1701 /*
1702 * If the host is not capable of supporting per-port vectors, fall
1703 * back to single MSI before finally attempting single MSI-X.
1704 */
1705 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1706 if (nvec == 1)
1707 return nvec;
1708 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1709 }
1710
ahci_mark_external_port(struct ata_port * ap)1711 static void ahci_mark_external_port(struct ata_port *ap)
1712 {
1713 struct ahci_host_priv *hpriv = ap->host->private_data;
1714 void __iomem *port_mmio = ahci_port_base(ap);
1715 u32 tmp;
1716
1717 /* mark external ports (hotplug-capable, eSATA) */
1718 tmp = readl(port_mmio + PORT_CMD);
1719 if (((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) ||
1720 (tmp & PORT_CMD_HPCP))
1721 ap->pflags |= ATA_PFLAG_EXTERNAL;
1722 }
1723
ahci_update_initial_lpm_policy(struct ata_port * ap)1724 static void ahci_update_initial_lpm_policy(struct ata_port *ap)
1725 {
1726 struct ahci_host_priv *hpriv = ap->host->private_data;
1727 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1728
1729 /*
1730 * AHCI contains a known incompatibility between LPM and hot-plug
1731 * removal events, see 7.3.1 Hot Plug Removal Detection and Power
1732 * Management Interaction in AHCI 1.3.1. Therefore, do not enable
1733 * LPM if the port advertises itself as an external port.
1734 */
1735 if (ap->pflags & ATA_PFLAG_EXTERNAL) {
1736 ata_port_dbg(ap, "external port, not enabling LPM\n");
1737 return;
1738 }
1739
1740 /* If no LPM states are supported by the HBA, do not bother with LPM */
1741 if ((ap->host->flags & ATA_HOST_NO_PART) &&
1742 (ap->host->flags & ATA_HOST_NO_SSC) &&
1743 (ap->host->flags & ATA_HOST_NO_DEVSLP)) {
1744 ata_port_dbg(ap, "no LPM states supported, not enabling LPM\n");
1745 return;
1746 }
1747
1748 /* user modified policy via module param */
1749 if (mobile_lpm_policy != -1) {
1750 policy = mobile_lpm_policy;
1751 goto update_policy;
1752 }
1753
1754 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) {
1755 if (hpriv->cap & HOST_CAP_PART)
1756 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1757 else if (hpriv->cap & HOST_CAP_SSC)
1758 policy = ATA_LPM_MIN_POWER;
1759 }
1760
1761 update_policy:
1762 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1763 ap->target_lpm_policy = policy;
1764 }
1765
ahci_intel_pcs_quirk(struct pci_dev * pdev,struct ahci_host_priv * hpriv)1766 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1767 {
1768 u16 tmp16;
1769
1770 if (!(hpriv->flags & AHCI_HFLAG_INTEL_PCS_QUIRK))
1771 return;
1772
1773 /*
1774 * port_map is determined from PORTS_IMPL PCI register which is
1775 * implemented as write or write-once register. If the register
1776 * isn't programmed, ahci automatically generates it from number
1777 * of ports, which is good enough for PCS programming. It is
1778 * otherwise expected that platform firmware enables the ports
1779 * before the OS boots.
1780 */
1781 pci_read_config_word(pdev, PCS_6, &tmp16);
1782 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1783 tmp16 |= hpriv->port_map;
1784 pci_write_config_word(pdev, PCS_6, tmp16);
1785 }
1786 }
1787
remapped_nvme_show(struct device * dev,struct device_attribute * attr,char * buf)1788 static ssize_t remapped_nvme_show(struct device *dev,
1789 struct device_attribute *attr,
1790 char *buf)
1791 {
1792 struct ata_host *host = dev_get_drvdata(dev);
1793 struct ahci_host_priv *hpriv = host->private_data;
1794
1795 return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme);
1796 }
1797
1798 static DEVICE_ATTR_RO(remapped_nvme);
1799
ahci_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1800 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1801 {
1802 unsigned int board_id = ent->driver_data;
1803 struct ata_port_info pi = ahci_port_info[board_id];
1804 const struct ata_port_info *ppi[] = { &pi, NULL };
1805 struct device *dev = &pdev->dev;
1806 struct ahci_host_priv *hpriv;
1807 struct ata_host *host;
1808 int n_ports, i, rc;
1809 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1810
1811 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1812
1813 ata_print_version_once(&pdev->dev, DRV_VERSION);
1814
1815 /* The AHCI driver can only drive the SATA ports, the PATA driver
1816 can drive them all so if both drivers are selected make sure
1817 AHCI stays out of the way */
1818 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1819 return -ENODEV;
1820
1821 /* Apple BIOS on MCP89 prevents us using AHCI */
1822 if (is_mcp89_apple(pdev))
1823 ahci_mcp89_apple_enable(pdev);
1824
1825 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1826 * At the moment, we can only use the AHCI mode. Let the users know
1827 * that for SAS drives they're out of luck.
1828 */
1829 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1830 dev_info(&pdev->dev,
1831 "PDC42819 can only drive SATA devices with this driver\n");
1832
1833 /* Some devices use non-standard BARs */
1834 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1835 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1836 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1837 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1838 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1839 if (pdev->device == 0xa01c)
1840 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1841 if (pdev->device == 0xa084)
1842 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1843 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1844 if (pdev->device == 0x7a08)
1845 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1846 }
1847
1848 /* acquire resources */
1849 rc = pcim_enable_device(pdev);
1850 if (rc)
1851 return rc;
1852
1853 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1854 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1855 u8 map;
1856
1857 /* ICH6s share the same PCI ID for both piix and ahci
1858 * modes. Enabling ahci mode while MAP indicates
1859 * combined mode is a bad idea. Yield to ata_piix.
1860 */
1861 pci_read_config_byte(pdev, ICH_MAP, &map);
1862 if (map & 0x3) {
1863 dev_info(&pdev->dev,
1864 "controller is in combined mode, can't enable AHCI mode\n");
1865 return -ENODEV;
1866 }
1867 }
1868
1869 /* AHCI controllers often implement SFF compatible interface.
1870 * Grab all PCI BARs just in case.
1871 */
1872 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1873 if (rc == -EBUSY)
1874 pcim_pin_device(pdev);
1875 if (rc)
1876 return rc;
1877
1878 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1879 if (!hpriv)
1880 return -ENOMEM;
1881 hpriv->flags |= (unsigned long)pi.private_data;
1882
1883 /* MCP65 revision A1 and A2 can't do MSI */
1884 if (board_id == board_ahci_mcp65 &&
1885 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1886 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1887
1888 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1889 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1890 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1891
1892 /* only some SB600s can do 64bit DMA */
1893 if (ahci_sb600_enable_64bit(pdev))
1894 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1895
1896 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1897
1898 /* detect remapped nvme devices */
1899 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1900
1901 sysfs_add_file_to_group(&pdev->dev.kobj,
1902 &dev_attr_remapped_nvme.attr,
1903 NULL);
1904
1905 #ifdef CONFIG_ARM64
1906 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1907 pdev->device == 0xa235 &&
1908 pdev->revision < 0x30)
1909 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1910
1911 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1912 hpriv->irq_handler = ahci_thunderx_irq_handler;
1913 #endif
1914
1915 /* save initial config */
1916 ahci_pci_save_initial_config(pdev, hpriv);
1917
1918 /* prepare host */
1919 if (hpriv->cap & HOST_CAP_NCQ) {
1920 pi.flags |= ATA_FLAG_NCQ;
1921 /*
1922 * Auto-activate optimization is supposed to be
1923 * supported on all AHCI controllers indicating NCQ
1924 * capability, but it seems to be broken on some
1925 * chipsets including NVIDIAs.
1926 */
1927 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1928 pi.flags |= ATA_FLAG_FPDMA_AA;
1929
1930 /*
1931 * All AHCI controllers should be forward-compatible
1932 * with the new auxiliary field. This code should be
1933 * conditionalized if any buggy AHCI controllers are
1934 * encountered.
1935 */
1936 pi.flags |= ATA_FLAG_FPDMA_AUX;
1937 }
1938
1939 if (hpriv->cap & HOST_CAP_PMP)
1940 pi.flags |= ATA_FLAG_PMP;
1941
1942 ahci_set_em_messages(hpriv, &pi);
1943
1944 if (ahci_broken_system_poweroff(pdev)) {
1945 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1946 dev_info(&pdev->dev,
1947 "quirky BIOS, skipping spindown on poweroff\n");
1948 }
1949
1950 if (ahci_broken_lpm(pdev)) {
1951 pi.flags |= ATA_FLAG_NO_LPM;
1952 dev_warn(&pdev->dev,
1953 "BIOS update required for Link Power Management support\n");
1954 }
1955
1956 if (ahci_broken_suspend(pdev)) {
1957 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1958 dev_warn(&pdev->dev,
1959 "BIOS update required for suspend/resume\n");
1960 }
1961
1962 if (ahci_broken_online(pdev)) {
1963 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1964 dev_info(&pdev->dev,
1965 "online status unreliable, applying workaround\n");
1966 }
1967
1968
1969 /* Acer SA5-271 workaround modifies private_data */
1970 acer_sa5_271_workaround(hpriv, pdev);
1971
1972 /* CAP.NP sometimes indicate the index of the last enabled
1973 * port, at other times, that of the last possible port, so
1974 * determining the maximum port number requires looking at
1975 * both CAP.NP and port_map.
1976 */
1977 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1978
1979 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1980 if (!host) {
1981 rc = -ENOMEM;
1982 goto err_rm_sysfs_file;
1983 }
1984 host->private_data = hpriv;
1985
1986 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1987 /* legacy intx interrupts */
1988 pci_intx(pdev, 1);
1989 }
1990 hpriv->irq = pci_irq_vector(pdev, 0);
1991
1992 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1993 host->flags |= ATA_HOST_PARALLEL_SCAN;
1994 else
1995 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1996
1997 if (!(hpriv->cap & HOST_CAP_PART))
1998 host->flags |= ATA_HOST_NO_PART;
1999
2000 if (!(hpriv->cap & HOST_CAP_SSC))
2001 host->flags |= ATA_HOST_NO_SSC;
2002
2003 if (!(hpriv->cap2 & HOST_CAP2_SDS))
2004 host->flags |= ATA_HOST_NO_DEVSLP;
2005
2006 if (pi.flags & ATA_FLAG_EM)
2007 ahci_reset_em(host);
2008
2009 for (i = 0; i < host->n_ports; i++) {
2010 struct ata_port *ap = host->ports[i];
2011
2012 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
2013 ata_port_pbar_desc(ap, ahci_pci_bar,
2014 0x100 + ap->port_no * 0x80, "port");
2015
2016 /* set enclosure management message type */
2017 if (ap->flags & ATA_FLAG_EM)
2018 ap->em_message_type = hpriv->em_msg_type;
2019
2020 ahci_mark_external_port(ap);
2021
2022 ahci_update_initial_lpm_policy(ap);
2023
2024 /* disabled/not-implemented port */
2025 if (!(hpriv->port_map & (1 << i)))
2026 ap->ops = &ata_dummy_port_ops;
2027 }
2028
2029 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2030 ahci_p5wdh_workaround(host);
2031
2032 /* apply gtf filter quirk */
2033 ahci_gtf_filter_workaround(host);
2034
2035 /* initialize adapter */
2036 rc = ahci_configure_dma_masks(pdev, hpriv);
2037 if (rc)
2038 goto err_rm_sysfs_file;
2039
2040 rc = ahci_pci_reset_controller(host);
2041 if (rc)
2042 goto err_rm_sysfs_file;
2043
2044 ahci_pci_init_controller(host);
2045 ahci_pci_print_info(host);
2046
2047 pci_set_master(pdev);
2048
2049 rc = ahci_host_activate(host, &ahci_sht);
2050 if (rc)
2051 goto err_rm_sysfs_file;
2052
2053 pm_runtime_put_noidle(&pdev->dev);
2054 return 0;
2055
2056 err_rm_sysfs_file:
2057 sysfs_remove_file_from_group(&pdev->dev.kobj,
2058 &dev_attr_remapped_nvme.attr, NULL);
2059 return rc;
2060 }
2061
ahci_shutdown_one(struct pci_dev * pdev)2062 static void ahci_shutdown_one(struct pci_dev *pdev)
2063 {
2064 ata_pci_shutdown_one(pdev);
2065 }
2066
ahci_remove_one(struct pci_dev * pdev)2067 static void ahci_remove_one(struct pci_dev *pdev)
2068 {
2069 sysfs_remove_file_from_group(&pdev->dev.kobj,
2070 &dev_attr_remapped_nvme.attr,
2071 NULL);
2072 pm_runtime_get_noresume(&pdev->dev);
2073 ata_pci_remove_one(pdev);
2074 }
2075
2076 module_pci_driver(ahci_pci_driver);
2077
2078 MODULE_AUTHOR("Jeff Garzik");
2079 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2080 MODULE_LICENSE("GPL");
2081 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2082 MODULE_VERSION(DRV_VERSION);
2083