xref: /titanic_41/usr/src/uts/common/io/arn/arn_hw.h (revision c0c934808d1b7d058148814255f32064a0e09555)
1 /*
2  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
3  * Use is subject to license terms.
4  */
5 
6 /*
7  * Copyright (c) 2008 Atheros Communications Inc.
8  *
9  * Permission to use, copy, modify, and/or distribute this software for any
10  * purpose with or without fee is hereby granted, provided that the above
11  * copyright notice and this permission notice appear in all copies.
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20  */
21 
22 #ifndef	_ARN_HW_H
23 #define	_ARN_HW_H
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
29 #pragma pack(1)
30 struct ar5416_desc {
31 	uint32_t ds_link;
32 	uint32_t ds_data;
33 	uint32_t ds_ctl0;
34 	uint32_t ds_ctl1;
35 	union {
36 		struct {
37 			uint32_t ctl2;
38 			uint32_t ctl3;
39 			uint32_t ctl4;
40 			uint32_t ctl5;
41 			uint32_t ctl6;
42 			uint32_t ctl7;
43 			uint32_t ctl8;
44 			uint32_t ctl9;
45 			uint32_t ctl10;
46 			uint32_t ctl11;
47 			uint32_t status0;
48 			uint32_t status1;
49 			uint32_t status2;
50 			uint32_t status3;
51 			uint32_t status4;
52 			uint32_t status5;
53 			uint32_t status6;
54 			uint32_t status7;
55 			uint32_t status8;
56 			uint32_t status9;
57 		} tx;
58 		struct {
59 			uint32_t status0;
60 			uint32_t status1;
61 			uint32_t status2;
62 			uint32_t status3;
63 			uint32_t status4;
64 			uint32_t status5;
65 			uint32_t status6;
66 			uint32_t status7;
67 			uint32_t status8;
68 		} rx;
69 	} u;
70 };
71 #pragma pack()
72 
73 #define	AR5416DESC(_ds)		((struct ar5416_desc *)(_ds))
74 #define	AR5416DESC_CONST(_ds)	((const struct ar5416_desc *)(_ds))
75 
76 #define	ds_ctl2		u.tx.ctl2
77 #define	ds_ctl3		u.tx.ctl3
78 #define	ds_ctl4		u.tx.ctl4
79 #define	ds_ctl5		u.tx.ctl5
80 #define	ds_ctl6		u.tx.ctl6
81 #define	ds_ctl7		u.tx.ctl7
82 #define	ds_ctl8		u.tx.ctl8
83 #define	ds_ctl9		u.tx.ctl9
84 #define	ds_ctl10	u.tx.ctl10
85 #define	ds_ctl11	u.tx.ctl11
86 
87 #define	ds_txstatus0	u.tx.status0
88 #define	ds_txstatus1	u.tx.status1
89 #define	ds_txstatus2	u.tx.status2
90 #define	ds_txstatus3	u.tx.status3
91 #define	ds_txstatus4	u.tx.status4
92 #define	ds_txstatus5	u.tx.status5
93 #define	ds_txstatus6	u.tx.status6
94 #define	ds_txstatus7	u.tx.status7
95 #define	ds_txstatus8	u.tx.status8
96 #define	ds_txstatus9	u.tx.status9
97 
98 #define	ds_rxstatus0	u.rx.status0
99 #define	ds_rxstatus1	u.rx.status1
100 #define	ds_rxstatus2	u.rx.status2
101 #define	ds_rxstatus3	u.rx.status3
102 #define	ds_rxstatus4	u.rx.status4
103 #define	ds_rxstatus5	u.rx.status5
104 #define	ds_rxstatus6	u.rx.status6
105 #define	ds_rxstatus7	u.rx.status7
106 #define	ds_rxstatus8	u.rx.status8
107 
108 #define	AR_FrameLen	0x00000fff
109 #define	AR_VirtMoreFrag	0x00001000
110 #define	AR_TxCtlRsvd00	0x0000e000
111 #define	AR_XmitPower	0x003f0000
112 #define	AR_XmitPower_S	16
113 #define	AR_RTSEnable	0x00400000
114 #define	AR_VEOL		0x00800000
115 #define	AR_ClrDestMask	0x01000000
116 #define	AR_TxCtlRsvd01	0x1e000000
117 #define	AR_TxIntrReq	0x20000000
118 #define	AR_DestIdxValid	0x40000000
119 #define	AR_CTSEnable	0x80000000
120 
121 #define	AR_BufLen		0x00000fff
122 #define	AR_TxMore		0x00001000
123 #define	AR_DestIdx		0x000fe000
124 #define	AR_DestIdx_S		13
125 #define	AR_FrameType		0x00f00000
126 #define	AR_FrameType_S		20
127 #define	AR_NoAck		0x01000000
128 #define	AR_InsertTS		0x02000000
129 #define	AR_CorruptFCS		0x04000000
130 #define	AR_ExtOnly		0x08000000
131 #define	AR_ExtAndCtl		0x10000000
132 #define	AR_MoreAggr		0x20000000
133 #define	AR_IsAggr		0x40000000
134 
135 #define	AR_BurstDur		0x00007fff
136 #define	AR_BurstDur_S		0
137 #define	AR_DurUpdateEna		0x00008000
138 #define	AR_XmitDataTries0	0x000f0000
139 #define	AR_XmitDataTries0_S	16
140 #define	AR_XmitDataTries1	0x00f00000
141 #define	AR_XmitDataTries1_S	20
142 #define	AR_XmitDataTries2	0x0f000000
143 #define	AR_XmitDataTries2_S	24
144 #define	AR_XmitDataTries3	0xf0000000
145 #define	AR_XmitDataTries3_S	28
146 
147 #define	AR_XmitRate0		0x000000ff
148 #define	AR_XmitRate0_S		0
149 #define	AR_XmitRate1		0x0000ff00
150 #define	AR_XmitRate1_S		8
151 #define	AR_XmitRate2		0x00ff0000
152 #define	AR_XmitRate2_S		16
153 #define	AR_XmitRate3		0xff000000
154 #define	AR_XmitRate3_S		24
155 
156 #define	AR_PacketDur0		0x00007fff
157 #define	AR_PacketDur0_S		0
158 #define	AR_RTSCTSQual0		0x00008000
159 #define	AR_PacketDur1		0x7fff0000
160 #define	AR_PacketDur1_S		16
161 #define	AR_RTSCTSQual1		0x80000000
162 
163 #define	AR_PacketDur2		0x00007fff
164 #define	AR_PacketDur2_S		0
165 #define	AR_RTSCTSQual2		0x00008000
166 #define	AR_PacketDur3		0x7fff0000
167 #define	AR_PacketDur3_S		16
168 #define	AR_RTSCTSQual3		0x80000000
169 
170 #define	AR_AggrLen		0x0000ffff
171 #define	AR_AggrLen_S		0
172 #define	AR_TxCtlRsvd60		0x00030000
173 #define	AR_PadDelim		0x03fc0000
174 #define	AR_PadDelim_S		18
175 #define	AR_EncrType		0x0c000000
176 #define	AR_EncrType_S		26
177 #define	AR_TxCtlRsvd61		0xf0000000
178 
179 #define	AR_2040_0		0x00000001
180 #define	AR_GI0			0x00000002
181 #define	AR_ChainSel0		0x0000001c
182 #define	AR_ChainSel0_S		2
183 #define	AR_2040_1		0x00000020
184 #define	AR_GI1			0x00000040
185 #define	AR_ChainSel1		0x00000380
186 #define	AR_ChainSel1_S		7
187 #define	AR_2040_2		0x00000400
188 #define	AR_GI2			0x00000800
189 #define	AR_ChainSel2		0x00007000
190 #define	AR_ChainSel2_S		12
191 #define	AR_2040_3		0x00008000
192 #define	AR_GI3			0x00010000
193 #define	AR_ChainSel3		0x000e0000
194 #define	AR_ChainSel3_S		17
195 #define	AR_RTSCTSRate		0x0ff00000
196 #define	AR_RTSCTSRate_S		20
197 #define	AR_TxCtlRsvd70		0xf0000000
198 
199 #define	AR_TxRSSIAnt00		0x000000ff
200 #define	AR_TxRSSIAnt00_S	0
201 #define	AR_TxRSSIAnt01		0x0000ff00
202 #define	AR_TxRSSIAnt01_S	8
203 #define	AR_TxRSSIAnt02		0x00ff0000
204 #define	AR_TxRSSIAnt02_S	16
205 #define	AR_TxStatusRsvd00	0x3f000000
206 #define	AR_TxBaStatus		0x40000000
207 #define	AR_TxStatusRsvd01	0x80000000
208 
209 #define	AR_FrmXmitOK		0x00000001
210 #define	AR_ExcessiveRetries	0x00000002
211 #define	AR_FIFOUnderrun		0x00000004
212 #define	AR_Filtered		0x00000008
213 #define	AR_RTSFailCnt		0x000000f0
214 #define	AR_RTSFailCnt_S		4
215 #define	AR_DataFailCnt		0x00000f00
216 #define	AR_DataFailCnt_S	8
217 #define	AR_VirtRetryCnt		0x0000f000
218 #define	AR_VirtRetryCnt_S	12
219 #define	AR_TxDelimUnderrun	0x00010000
220 #define	AR_TxDataUnderrun	0x00020000
221 #define	AR_DescCfgErr		0x00040000
222 #define	AR_TxTimerExpired	0x00080000
223 #define	AR_TxStatusRsvd10	0xfff00000
224 
225 #define	AR_SendTimestamp	ds_txstatus2
226 #define	AR_BaBitmapLow		ds_txstatus3
227 #define	AR_BaBitmapHigh		ds_txstatus4
228 
229 #define	AR_TxRSSIAnt10		0x000000ff
230 #define	AR_TxRSSIAnt10_S	0
231 #define	AR_TxRSSIAnt11		0x0000ff00
232 #define	AR_TxRSSIAnt11_S	8
233 #define	AR_TxRSSIAnt12		0x00ff0000
234 #define	AR_TxRSSIAnt12_S	16
235 #define	AR_TxRSSICombined	0xff000000
236 #define	AR_TxRSSICombined_S	24
237 
238 #define	AR_TxEVM0		ds_txstatus5
239 #define	AR_TxEVM1		ds_txstatus6
240 #define	AR_TxEVM2		ds_txstatus7
241 
242 #define	AR_TxDone		0x00000001
243 #define	AR_SeqNum		0x00001ffe
244 #define	AR_SeqNum_S		1
245 #define	AR_TxStatusRsvd80	0x0001e000
246 #define	AR_TxOpExceeded		0x00020000
247 #define	AR_TxStatusRsvd81	0x001c0000
248 #define	AR_FinalTxIdx		0x00600000
249 #define	AR_FinalTxIdx_S		21
250 #define	AR_TxStatusRsvd82	0x01800000
251 #define	AR_PowerMgmt		0x02000000
252 #define	AR_TxStatusRsvd83	0xfc000000
253 
254 #define	AR_RxCTLRsvd00		0xffffffff
255 
256 #define	AR_BufLen		0x00000fff
257 #define	AR_RxCtlRsvd00		0x00001000
258 #define	AR_RxIntrReq		0x00002000
259 #define	AR_RxCtlRsvd01		0xffffc000
260 
261 #define	AR_RxRSSIAnt00		0x000000ff
262 #define	AR_RxRSSIAnt00_S	0
263 #define	AR_RxRSSIAnt01		0x0000ff00
264 #define	AR_RxRSSIAnt01_S	8
265 #define	AR_RxRSSIAnt02		0x00ff0000
266 #define	AR_RxRSSIAnt02_S	16
267 #define	AR_RxRate		0xff000000
268 #define	AR_RxRate_S		24
269 #define	AR_RxStatusRsvd00	0xff000000
270 
271 #define	AR_DataLen		0x00000fff
272 #define	AR_RxMore		0x00001000
273 #define	AR_NumDelim		0x003fc000
274 #define	AR_NumDelim_S		14
275 #define	AR_RxStatusRsvd10	0xff800000
276 
277 #define	AR_RcvTimestamp		ds_rxstatus2
278 
279 #define	AR_GI			0x00000001
280 #define	AR_2040			0x00000002
281 #define	AR_Parallel40		0x00000004
282 #define	AR_Parallel40_S		2
283 #define	AR_RxStatusRsvd30	0x000000f8
284 #define	AR_RxAntenna		0xffffff00
285 #define	AR_RxAntenna_S		8
286 
287 #define	AR_RxRSSIAnt10		0x000000ff
288 #define	AR_RxRSSIAnt10_S	0
289 #define	AR_RxRSSIAnt11		0x0000ff00
290 #define	AR_RxRSSIAnt11_S	8
291 #define	AR_RxRSSIAnt12		0x00ff0000
292 #define	AR_RxRSSIAnt12_S	16
293 #define	AR_RxRSSICombined	0xff000000
294 #define	AR_RxRSSICombined_S	24
295 
296 #define	AR_RxEVM0		ds_rxstatus4
297 #define	AR_RxEVM1		ds_rxstatus5
298 #define	AR_RxEVM2		ds_rxstatus6
299 
300 #define	AR_RxDone		0x00000001
301 #define	AR_RxFrameOK		0x00000002
302 #define	AR_CRCErr		0x00000004
303 #define	AR_DecryptCRCErr	0x00000008
304 #define	AR_PHYErr		0x00000010
305 #define	AR_MichaelErr		0x00000020
306 #define	AR_PreDelimCRCErr	0x00000040
307 #define	AR_RxStatusRsvd70	0x00000080
308 #define	AR_RxKeyIdxValid	0x00000100
309 #define	AR_KeyIdx		0x0000fe00
310 #define	AR_KeyIdx_S		9
311 #define	AR_PHYErrCode		0x0000ff00
312 #define	AR_PHYErrCode_S		8
313 #define	AR_RxMoreAggr		0x00010000
314 #define	AR_RxAggr		0x00020000
315 #define	AR_PostDelimCRCErr	0x00040000
316 #define	AR_RxStatusRsvd71	0x3ff80000
317 #define	AR_DecryptBusyErr	0x40000000
318 #define	AR_KeyMiss		0x80000000
319 
320 #define	AR5416_MAGIC	0x19641014
321 
322 #define	RXSTATUS_RATE(ah, ads)	(AR_SREV_5416_V20_OR_LATER(ah) ?	\
323 	MS(ads->ds_rxstatus0, AR_RxRate) :				\
324 	(ads->ds_rxstatus3 >> 2) & 0xFF)
325 
326 #define	set11nTries(_series, _index)	\
327 	(SM((_series)[_index].Tries, AR_XmitDataTries##_index))
328 
329 #define	set11nRate(_series, _index)	\
330 	(SM((_series)[_index].Rate, AR_XmitRate##_index))
331 
332 #define	set11nPktDurRTSCTS(_series, _index)				\
333 	(SM((_series)[_index].PktDuration, AR_PacketDur##_index) |	\
334 	((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS   ?	\
335 	    AR_RTSCTSQual##_index : 0))
336 
337 #define	set11nRateFlags(_series, _index)				\
338 	(((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ?		\
339 	    AR_2040_##_index : 0)					\
340 	|((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ?	\
341 	    AR_GI##_index : 0)						\
342 	|SM((_series)[_index].ChSel, AR_ChainSel##_index))
343 
344 #define	AR_SREV_9100(ah)	((ah->ah_macVersion) == AR_SREV_VERSION_9100)
345 
346 #define	INIT_CONFIG_STATUS	0x00000000
347 #define	INIT_RSSI_THR		0x00000700
348 #define	INIT_BCON_CNTRL_REG	0x00000000
349 
350 #define	MIN_TX_FIFO_THRESHOLD	0x1
351 #define	MAX_TX_FIFO_THRESHOLD	((4096 / 64) - 1)
352 #define	INIT_TX_FIFO_THRESHOLD	MIN_TX_FIFO_THRESHOLD
353 
354 struct ar5416AniState {
355 	struct ath9k_channel c;
356 	uint8_t noiseImmunityLevel;
357 	uint8_t spurImmunityLevel;
358 	uint8_t firstepLevel;
359 	uint8_t ofdmWeakSigDetectOff;
360 	uint8_t cckWeakSigThreshold;
361 	uint32_t listenTime;
362 	uint32_t ofdmTrigHigh;
363 	uint32_t ofdmTrigLow;
364 	int32_t cckTrigHigh;
365 	int32_t cckTrigLow;
366 	int32_t rssiThrLow;
367 	int32_t rssiThrHigh;
368 	uint32_t noiseFloor;
369 	uint32_t txFrameCount;
370 	uint32_t rxFrameCount;
371 	uint32_t cycleCount;
372 	uint32_t ofdmPhyErrCount;
373 	uint32_t cckPhyErrCount;
374 	uint32_t ofdmPhyErrBase;
375 	uint32_t cckPhyErrBase;
376 	int16_t pktRssi[2];
377 	int16_t ofdmErrRssi[2];
378 	int16_t cckErrRssi[2];
379 };
380 
381 #define	HAL_PROCESS_ANI	0x00000001
382 #define	DO_ANI(ah) \
383 	((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI))
384 
385 struct ar5416Stats {
386 	uint32_t ast_ani_niup;
387 	uint32_t ast_ani_nidown;
388 	uint32_t ast_ani_spurup;
389 	uint32_t ast_ani_spurdown;
390 	uint32_t ast_ani_ofdmon;
391 	uint32_t ast_ani_ofdmoff;
392 	uint32_t ast_ani_cckhigh;
393 	uint32_t ast_ani_ccklow;
394 	uint32_t ast_ani_stepup;
395 	uint32_t ast_ani_stepdown;
396 	uint32_t ast_ani_ofdmerrs;
397 	uint32_t ast_ani_cckerrs;
398 	uint32_t ast_ani_reset;
399 	uint32_t ast_ani_lzero;
400 	uint32_t ast_ani_lneg;
401 	struct ath9k_mib_stats ast_mibstats;
402 	struct ath9k_node_stats ast_nodestats;
403 };
404 
405 #define	AR5416_OPFLAGS_11A		0x01
406 #define	AR5416_OPFLAGS_11G		0x02
407 #define	AR5416_OPFLAGS_N_5G_HT40	0x04
408 #define	AR5416_OPFLAGS_N_2G_HT40	0x08
409 #define	AR5416_OPFLAGS_N_5G_HT20	0x10
410 #define	AR5416_OPFLAGS_N_2G_HT20	0x20
411 
412 #define	EEP_RFSILENT_ENABLED		0x0001
413 #define	EEP_RFSILENT_ENABLED_S		0
414 #define	EEP_RFSILENT_POLARITY		0x0002
415 #define	EEP_RFSILENT_POLARITY_S		1
416 #define	EEP_RFSILENT_GPIO_SEL		0x001c
417 #define	EEP_RFSILENT_GPIO_SEL_S		2
418 
419 #define	AR5416_EEP_NO_BACK_VER		0x1
420 #define	AR5416_EEP_VER			0xE
421 #define	AR5416_EEP_VER_MINOR_MASK	0x0FFF
422 #define	AR5416_EEP_MINOR_VER_2		0x2
423 #define	AR5416_EEP_MINOR_VER_3		0x3
424 #define	AR5416_EEP_MINOR_VER_7		0x7
425 #define	AR5416_EEP_MINOR_VER_9		0x9
426 #define	AR5416_EEP_MINOR_VER_16		0x10
427 #define	AR5416_EEP_MINOR_VER_17		0x11
428 #define	AR5416_EEP_MINOR_VER_19		0x13
429 /* 2.6.30 */
430 #define	AR5416_EEP_MINOR_VER_20		0x14
431 #define	AR5416_EEP_MINOR_VER_22		0x16
432 
433 #define	AR5416_NUM_5G_CAL_PIERS		8
434 #define	AR5416_NUM_2G_CAL_PIERS		4
435 #define	AR5416_NUM_5G_20_TARGET_POWERS	8
436 #define	AR5416_NUM_5G_40_TARGET_POWERS	8
437 #define	AR5416_NUM_2G_CCK_TARGET_POWERS	3
438 #define	AR5416_NUM_2G_20_TARGET_POWERS	4
439 #define	AR5416_NUM_2G_40_TARGET_POWERS	4
440 #define	AR5416_NUM_CTLS			24
441 #define	AR5416_NUM_BAND_EDGES		8
442 #define	AR5416_NUM_PD_GAINS		4
443 #define	AR5416_PD_GAINS_IN_MASK		4
444 #define	AR5416_PD_GAIN_ICEPTS		5
445 #define	AR5416_EEPROM_MODAL_SPURS	5
446 #define	AR5416_MAX_RATE_POWER		63
447 #define	AR5416_NUM_PDADC_VALUES		128
448 #define	AR5416_BCHAN_UNUSED		0xFF
449 #define	AR5416_MAX_PWR_RANGE_IN_HALF_DB	64
450 #define	AR5416_MAX_CHAINS		3
451 #define	AR5416_PWR_TABLE_OFFSET		-5
452 
453 /* Rx gain type values */
454 #define	AR5416_EEP_RXGAIN_23DB_BACKOFF	0
455 #define	AR5416_EEP_RXGAIN_13DB_BACKOFF	1
456 #define	AR5416_EEP_RXGAIN_ORIG		2
457 
458 /* Tx gain type values */
459 #define	AR5416_EEP_TXGAIN_ORIGINAL	0
460 #define	AR5416_EEP_TXGAIN_HIGH_POWER	1
461 
462 #define	AR5416_EEP4K_START_LOC					64
463 #define	AR5416_EEP4K_NUM_2G_CAL_PIERS			3
464 #define	AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS	3
465 #define	AR5416_EEP4K_NUM_2G_20_TARGET_POWERS	3
466 #define	AR5416_EEP4K_NUM_2G_40_TARGET_POWERS	3
467 #define	AR5416_EEP4K_NUM_CTLS					12
468 #define	AR5416_EEP4K_NUM_BAND_EDGES				4
469 #define	AR5416_EEP4K_NUM_PD_GAINS				2
470 #define	AR5416_EEP4K_PD_GAINS_IN_MASK			4
471 #define	AR5416_EEP4K_PD_GAIN_ICEPTS				5
472 #define	AR5416_EEP4K_MAX_CHAINS					1
473 
474 enum eeprom_param {
475 	EEP_NFTHRESH_5,
476 	EEP_NFTHRESH_2,
477 	EEP_MAC_MSW,
478 	EEP_MAC_MID,
479 	EEP_MAC_LSW,
480 	EEP_REG_0,
481 	EEP_REG_1,
482 	EEP_OP_CAP,
483 	EEP_OP_MODE,
484 	EEP_RF_SILENT,
485 	EEP_OB_5,
486 	EEP_DB_5,
487 	EEP_OB_2,
488 	EEP_DB_2,
489 	EEP_MINOR_REV,
490 	EEP_TX_MASK,
491 	EEP_RX_MASK,
492 	EEP_RXGAIN_TYPE,
493 	EEP_TXGAIN_TYPE,
494 	EEP_OL_PWRCTRL,
495 	EEP_RC_CHAIN_MASK,
496 	EEP_DAC_HPWR_5G,
497 	EEP_FRAC_N_5G
498 };
499 
500 enum ar5416_rates {
501 	rate6mb, rate9mb, rate12mb, rate18mb,
502 	rate24mb, rate36mb, rate48mb, rate54mb,
503 	rate1l, rate2l, rate2s, rate5_5l,
504 	rate5_5s, rate11l, rate11s, rateXr,
505 	rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
506 	rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
507 	rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
508 	rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
509 	rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
510 	Ar5416RateSize
511 };
512 
513 enum ath9k_hal_freq_band {
514 	ATH9K_HAL_FREQ_BAND_5GHZ = 0,
515 	ATH9K_HAL_FREQ_BAND_2GHZ = 1
516 };
517 
518 #pragma pack(1)
519 /* 2.6.30 */
520 struct base_eep_header {
521 	uint16_t length;
522 	uint16_t checksum;
523 	uint16_t version;
524 	uint8_t opCapFlags;
525 	uint8_t eepMisc;
526 	uint16_t regDmn[2];
527 	uint8_t macAddr[6];
528 	uint8_t rxMask;
529 	uint8_t txMask;
530 	uint16_t rfSilent;
531 	uint16_t blueToothOptions;
532 	uint16_t deviceCap;
533 	uint32_t binBuildNumber;
534 	uint8_t deviceType;
535 	uint8_t pwdclkind;
536 	uint8_t futureBase_1[2];
537 	uint8_t rxGainType;
538 	uint8_t dacHiPwrMode_5G;
539 	uint8_t openLoopPwrCntl;
540 	uint8_t dacLpMode;
541 	uint8_t txGainType;
542 	uint8_t rcChainMask;
543 	uint8_t desiredScaleCCK;
544 	uint8_t power_table_offset;
545 	uint8_t frac_n_5g;
546 	uint8_t futureBase_3[21];
547 };
548 
549 struct base_eep_header_4k {
550 	uint16_t length;
551 	uint16_t checksum;
552 	uint16_t version;
553 	uint8_t opCapFlags;
554 	uint8_t eepMisc;
555 	uint16_t regDmn[2];
556 	uint8_t macAddr[6];
557 	uint8_t rxMask;
558 	uint8_t txMask;
559 	uint16_t rfSilent;
560 	uint16_t blueToothOptions;
561 	uint16_t deviceCap;
562 	uint32_t binBuildNumber;
563 	uint8_t deviceType;
564 	uint8_t futureBase[1];
565 };
566 
567 struct spur_chan {
568 	uint16_t spurChan;
569 	uint8_t spurRangeLow;
570 	uint8_t spurRangeHigh;
571 };
572 
573 struct modal_eep_header {
574 	uint32_t antCtrlChain[AR5416_MAX_CHAINS];
575 	uint32_t antCtrlCommon;
576 	uint8_t antennaGainCh[AR5416_MAX_CHAINS];
577 	uint8_t switchSettling;
578 	uint8_t txRxAttenCh[AR5416_MAX_CHAINS];
579 	uint8_t rxTxMarginCh[AR5416_MAX_CHAINS];
580 	uint8_t adcDesiredSize;
581 	uint8_t pgaDesiredSize;
582 	uint8_t xlnaGainCh[AR5416_MAX_CHAINS];
583 	uint8_t txEndToXpaOff;
584 	uint8_t txEndToRxOn;
585 	uint8_t txFrameToXpaOn;
586 	uint8_t thresh62;
587 	uint8_t noiseFloorThreshCh[AR5416_MAX_CHAINS];
588 	uint8_t xpdGain;
589 	uint8_t xpd;
590 	uint8_t iqCalICh[AR5416_MAX_CHAINS];
591 	uint8_t iqCalQCh[AR5416_MAX_CHAINS];
592 	uint8_t pdGainOverlap;
593 	uint8_t ob;
594 	uint8_t db;
595 	uint8_t xpaBiasLvl;
596 	uint8_t pwrDecreaseFor2Chain;
597 	uint8_t pwrDecreaseFor3Chain;
598 	uint8_t txFrameToDataStart;
599 	uint8_t txFrameToPaOn;
600 	uint8_t ht40PowerIncForPdadc;
601 	uint8_t bswAtten[AR5416_MAX_CHAINS];
602 	uint8_t bswMargin[AR5416_MAX_CHAINS];
603 	uint8_t swSettleHt40;
604 	uint8_t xatten2Db[AR5416_MAX_CHAINS];
605 	uint8_t xatten2Margin[AR5416_MAX_CHAINS];
606 	uint8_t ob_ch1;
607 	uint8_t db_ch1;
608 	uint8_t useAnt1:1,
609 	    force_xpaon:1,
610 	    local_bias:1,
611 	    femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
612 	uint8_t futureModalar9280;
613 	uint16_t xpaBiasLvlFreq[3];
614 	uint8_t futureModal[6];
615 
616 	struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
617 };
618 
619 struct modal_eep_4k_header {
620     uint32_t  antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
621     uint32_t  antCtrlCommon;
622     uint8_t   antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
623     uint8_t   switchSettling;
624     uint8_t   txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
625     uint8_t   rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
626     uint8_t   adcDesiredSize;
627     uint8_t   pgaDesiredSize;
628     uint8_t   xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
629     uint8_t   txEndToXpaOff;
630     uint8_t   txEndToRxOn;
631     uint8_t   txFrameToXpaOn;
632     uint8_t   thresh62;
633     uint8_t   noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
634     uint8_t   xpdGain;
635     uint8_t   xpd;
636     uint8_t   iqCalICh[AR5416_EEP4K_MAX_CHAINS];
637     uint8_t   iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
638     uint8_t   pdGainOverlap;
639     uint8_t   ob_01;
640     uint8_t   db1_01;
641     uint8_t   xpaBiasLvl;
642     uint8_t   txFrameToDataStart;
643     uint8_t   txFrameToPaOn;
644     uint8_t   ht40PowerIncForPdadc;
645     uint8_t   bswAtten[AR5416_EEP4K_MAX_CHAINS];
646     uint8_t   bswMargin[AR5416_EEP4K_MAX_CHAINS];
647     uint8_t   swSettleHt40;
648     uint8_t   xatten2Db[AR5416_EEP4K_MAX_CHAINS];
649     uint8_t   xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
650     uint8_t   db2_01;
651     uint8_t   version;
652     uint16_t  ob_234;
653     uint16_t  db1_234;
654     uint16_t  db2_234;
655     uint8_t   futureModal[4];
656 
657     struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
658 };
659 
660 struct cal_data_per_freq {
661 	uint8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
662 	uint8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
663 };
664 
665 struct cal_data_per_freq_4k {
666 	uint8_t pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
667 	uint8_t vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
668 };
669 
670 struct cal_target_power_leg {
671 	uint8_t bChannel;
672 	uint8_t tPow2x[4];
673 };
674 
675 struct cal_target_power_ht {
676 	uint8_t bChannel;
677 	uint8_t tPow2x[8];
678 };
679 
680 #ifdef __BIG_ENDIAN_BITFIELD
681 struct cal_ctl_edges {
682 	uint8_t bChannel;
683 	uint8_t flag:2, tPower:6;
684 };
685 #else
686 struct cal_ctl_edges {
687 	uint8_t bChannel;
688 	uint8_t tPower:6, flag:2;
689 };
690 #endif
691 
692 struct cal_ctl_data {
693 	struct cal_ctl_edges
694 	    ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
695 };
696 
697 struct cal_ctl_data_4k {
698 	struct cal_ctl_edges
699 	ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
700 };
701 
702 struct ar5416_eeprom_def {
703 	struct base_eep_header baseEepHeader;
704 	uint8_t custData[64];
705 	struct modal_eep_header modalHeader[2];
706 	uint8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
707 	uint8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
708 	struct cal_data_per_freq
709 	    calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
710 	struct cal_data_per_freq
711 	    calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
712 	struct cal_target_power_leg
713 	    calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
714 	struct cal_target_power_ht
715 	    calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
716 	struct cal_target_power_ht
717 	    calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
718 	struct cal_target_power_leg
719 	    calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
720 	struct cal_target_power_leg
721 	    calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
722 	struct cal_target_power_ht
723 	    calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
724 	struct cal_target_power_ht
725 	    calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
726 	uint8_t ctlIndex[AR5416_NUM_CTLS];
727 	struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
728 	uint8_t padding;
729 };
730 
731 struct ar5416_eeprom_4k {
732 	struct base_eep_header_4k baseEepHeader;
733 	uint8_t custData[20];
734 	struct modal_eep_4k_header modalHeader;
735 	uint8_t calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
736 	struct cal_data_per_freq_4k
737 	calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
738 	struct cal_target_power_leg
739 	calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
740 	struct cal_target_power_leg
741 	calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
742 	struct cal_target_power_ht
743 	calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
744 	struct cal_target_power_ht
745 	calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
746 	uint8_t ctlIndex[AR5416_EEP4K_NUM_CTLS];
747 	struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
748 	uint8_t padding;
749 };
750 #pragma pack()
751 
752 struct ar5416IniArray {
753 	uint32_t *ia_array;
754 	uint32_t ia_rows;
755 	uint32_t ia_columns;
756 };
757 
758 #define	INIT_INI_ARRAY(iniarray, array, rows, columns) do {	\
759 		(iniarray)->ia_array = (uint32_t *)(array);		\
760 		(iniarray)->ia_rows = (rows);			\
761 		(iniarray)->ia_columns = (columns);		\
762 		_NOTE(CONSTCOND) \
763 	} while (0)
764 
765 #define	INI_RA(iniarray, row, column) \
766 	(((iniarray)->ia_array)[(row) *	((iniarray)->ia_columns) + (column)])
767 
768 #define	INIT_CAL(_perCal) do {				\
769 		(_perCal)->calState = CAL_WAITING;	\
770 		(_perCal)->calNext = NULL;		\
771 	} while (0)
772 
773 #define	INSERT_CAL(_ahp, _perCal)					\
774 	do {								\
775 		if ((_ahp)->ah_cal_list_last == NULL) {			\
776 			(_ahp)->ah_cal_list =				\
777 				(_ahp)->ah_cal_list_last = (_perCal);	\
778 			((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
779 		} else {						\
780 			((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
781 			(_ahp)->ah_cal_list_last = (_perCal);		\
782 			(_perCal)->calNext = (_ahp)->ah_cal_list;	\
783 		}							\
784 	} while (0)
785 
786 enum hal_cal_types {
787 	ADC_DC_INIT_CAL = 0x1,
788 	ADC_GAIN_CAL = 0x2,
789 	ADC_DC_CAL = 0x4,
790 	IQ_MISMATCH_CAL = 0x8
791 };
792 
793 enum hal_cal_state {
794 	CAL_INACTIVE,
795 	CAL_WAITING,
796 	CAL_RUNNING,
797 	CAL_DONE
798 };
799 
800 #define	MIN_CAL_SAMPLES		1
801 #define	MAX_CAL_SAMPLES		64
802 #define	INIT_LOG_COUNT		5
803 #define	PER_MIN_LOG_COUNT	2
804 #define	PER_MAX_LOG_COUNT	10
805 
806 struct hal_percal_data {
807 	enum hal_cal_types calType;
808 	uint32_t calNumSamples;
809 	uint32_t calCountMax;
810 	void (*calCollect) (struct ath_hal *);
811 	void (*calPostProc) (struct ath_hal *, uint8_t);
812 };
813 
814 struct hal_cal_list {
815 	const struct hal_percal_data *calData;
816 	enum hal_cal_state calState;
817 	struct hal_cal_list *calNext;
818 };
819 
820 /*
821  * Enum to indentify the eeprom mappings
822  */
823 enum hal_eep_map {
824 	EEP_MAP_DEFAULT = 0x0,
825 	EEP_MAP_4KBITS,
826 	EEP_MAP_MAX
827 };
828 
829 struct ath_hal_5416 {
830 	struct ath_hal ah;
831 	union {
832 		struct ar5416_eeprom_def def;
833 		struct ar5416_eeprom_4k map4k;
834 	} ah_eeprom;
835 	struct ar5416Stats ah_stats;
836 	struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES];
837 
838 	uint8_t ah_macaddr[IEEE80211_ADDR_LEN];
839 	uint8_t ah_bssid[IEEE80211_ADDR_LEN];
840 	uint8_t ah_bssidmask[IEEE80211_ADDR_LEN];
841 	uint16_t ah_assocId;
842 
843 	int16_t ah_curchanRadIndex;
844 	uint32_t ah_maskReg;
845 	uint32_t ah_txOkInterruptMask;
846 	uint32_t ah_txErrInterruptMask;
847 	uint32_t ah_txDescInterruptMask;
848 	uint32_t ah_txEolInterruptMask;
849 	uint32_t ah_txUrnInterruptMask;
850 	boolean_t ah_chipFullSleep;
851 	uint32_t ah_atimWindow;
852 	uint16_t ah_antennaSwitchSwap;
853 	enum ath9k_power_mode ah_powerMode;
854 	enum ath9k_ant_setting ah_diversityControl;
855 
856 	/* Calibration */
857 	enum hal_cal_types ah_suppCals;
858 	struct hal_cal_list ah_iqCalData;
859 	struct hal_cal_list ah_adcGainCalData;
860 	struct hal_cal_list ah_adcDcCalInitData;
861 	struct hal_cal_list ah_adcDcCalData;
862 	struct hal_cal_list *ah_cal_list;
863 	struct hal_cal_list *ah_cal_list_last;
864 	struct hal_cal_list *ah_cal_list_curr;
865 #define	ah_totalPowerMeasI ah_Meas0.unsign
866 #define	ah_totalPowerMeasQ ah_Meas1.unsign
867 #define	ah_totalIqCorrMeas ah_Meas2.sign
868 #define	ah_totalAdcIOddPhase  ah_Meas0.unsign
869 #define	ah_totalAdcIEvenPhase ah_Meas1.unsign
870 #define	ah_totalAdcQOddPhase  ah_Meas2.unsign
871 #define	ah_totalAdcQEvenPhase ah_Meas3.unsign
872 #define	ah_totalAdcDcOffsetIOddPhase  ah_Meas0.sign
873 #define	ah_totalAdcDcOffsetIEvenPhase ah_Meas1.sign
874 #define	ah_totalAdcDcOffsetQOddPhase  ah_Meas2.sign
875 #define	ah_totalAdcDcOffsetQEvenPhase ah_Meas3.sign
876 	union {
877 		uint32_t unsign[AR5416_MAX_CHAINS];
878 		int32_t sign[AR5416_MAX_CHAINS];
879 	} ah_Meas0;
880 	union {
881 		uint32_t unsign[AR5416_MAX_CHAINS];
882 		int32_t sign[AR5416_MAX_CHAINS];
883 	} ah_Meas1;
884 	union {
885 		uint32_t unsign[AR5416_MAX_CHAINS];
886 		int32_t sign[AR5416_MAX_CHAINS];
887 	} ah_Meas2;
888 	union {
889 		uint32_t unsign[AR5416_MAX_CHAINS];
890 		int32_t sign[AR5416_MAX_CHAINS];
891 	} ah_Meas3;
892 	uint16_t ah_CalSamples;
893 
894 	uint32_t ah_staId1Defaults;
895 	uint32_t ah_miscMode;
896 	enum {
897 		AUTO_32KHZ,
898 		USE_32KHZ,
899 		DONT_USE_32KHZ,
900 	} ah_enable32kHzClock;
901 
902 	/* RF */
903 	uint32_t *ah_analogBank0Data;
904 	uint32_t *ah_analogBank1Data;
905 	uint32_t *ah_analogBank2Data;
906 	uint32_t *ah_analogBank3Data;
907 	uint32_t *ah_analogBank6Data;
908 	uint32_t *ah_analogBank6TPCData;
909 	uint32_t *ah_analogBank7Data;
910 	uint32_t *ah_addac5416_21;
911 	uint32_t *ah_bank6Temp;
912 
913 	int16_t ah_txPowerIndexOffset;
914 	uint32_t ah_beaconInterval;
915 	uint32_t ah_slottime;
916 	uint32_t ah_acktimeout;
917 	uint32_t ah_ctstimeout;
918 	uint32_t ah_globaltxtimeout;
919 	uint8_t ah_gBeaconRate;
920 	uint32_t ah_gpioSelect;
921 	uint32_t ah_polarity;
922 	uint32_t ah_gpioBit;
923 
924 	/* ANI */
925 	uint32_t ah_procPhyErr;
926 	boolean_t ah_hasHwPhyCounters;
927 	uint32_t ah_aniPeriod;
928 	struct ar5416AniState *ah_curani;
929 	struct ar5416AniState ah_ani[255];
930 	int ah_totalSizeDesired[5];
931 	int ah_coarseHigh[5];
932 	int ah_coarseLow[5];
933 	int ah_firpwr[5];
934 	enum ath9k_ani_cmd ah_ani_function;
935 
936 	uint32_t ah_intrTxqs;
937 	boolean_t ah_intrMitigation;
938 	enum ath9k_ht_extprotspacing ah_extprotspacing;
939 	uint8_t ah_txchainmask;
940 	uint8_t ah_rxchainmask;
941 
942 	struct ar5416IniArray ah_iniModes;
943 	struct ar5416IniArray ah_iniCommon;
944 	struct ar5416IniArray ah_iniBank0;
945 	struct ar5416IniArray ah_iniBB_RfGain;
946 	struct ar5416IniArray ah_iniBank1;
947 	struct ar5416IniArray ah_iniBank2;
948 	struct ar5416IniArray ah_iniBank3;
949 	struct ar5416IniArray ah_iniBank6;
950 	struct ar5416IniArray ah_iniBank6TPC;
951 	struct ar5416IniArray ah_iniBank7;
952 	struct ar5416IniArray ah_iniAddac;
953 	struct ar5416IniArray ah_iniPcieSerdes;
954 	struct ar5416IniArray ah_iniModesAdditional;
955 	struct ar5416IniArray ah_iniModesRxGain;
956 	struct ar5416IniArray ah_iniModesTxGain;
957 	/* To indicate EEPROM mapping used */
958 	enum hal_eep_map ah_eep_map;
959 };
960 #define	AH5416(_ah) ((struct ath_hal_5416 *)(_ah))
961 
962 #define	FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
963 
964 #define	ar5416RfDetach(ah) do {					\
965 		if (AH5416(ah)->ah_rfHal.rfDetach != NULL)	\
966 			AH5416(ah)->ah_rfHal.rfDetach(ah);	\
967 	} while (0)
968 
969 #define	ath9k_hw_use_flash(_ah)	\
970 	(!(_ah->ah_flags & AH_USE_EEPROM))
971 
972 /* 2.6.30 */
973 #define	AR5416_VER_MASK	(eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
974 #define	OLC_FOR_AR9280_20_LATER	(AR_SREV_9280_20_OR_LATER(ah) && \
975 	ath9k_hw_get_eeprom(ah, EEP_OL_PWRCTRL))
976 
977 #define	DO_DELAY(x) do {			\
978 		if ((++(x) % 64) == 0)          \
979 			drv_usecwait(1);	\
980 	} while (0)
981 
982 #define	REG_WRITE_ARRAY(iniarray, column, regWr) do {                   \
983 		int r;							\
984 		for (r = 0; r < ((iniarray)->ia_rows); r++) {		\
985 			REG_WRITE(ah, INI_RA((iniarray), (r), 0),	\
986 			    INI_RA((iniarray), r, (column)));		\
987 			DO_DELAY(regWr);				\
988 		}							\
989 	} while (0)
990 
991 #define	BASE_ACTIVATE_DELAY		100
992 #define	RTC_PLL_SETTLE_DELAY		1000
993 #define	COEF_SCALE_S			24
994 #define	HT40_CHANNEL_CENTER_SHIFT	10
995 
996 #define	AR5416_EEPROM_MAGIC_OFFSET	0x0
997 
998 #define	AR5416_EEPROM_S			2
999 #define	AR5416_EEPROM_OFFSET		0x2000
1000 #define	AR5416_EEPROM_START_ADDR	\
1001 	(AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
1002 #define	AR5416_EEPROM_MAX	0xae0
1003 #define	ar5416_get_eep_ver(_ahp)	\
1004 	(((_ahp)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF)
1005 #define	ar5416_get_eep_rev(_ahp)	\
1006 	(((_ahp)->ah_eeprom.def.baseEepHeader.version) & 0xFFF)
1007 #define	ar5416_get_ntxchains(_txchainmask)	\
1008 	(((_txchainmask >> 2) & 1) +	\
1009 	((_txchainmask >> 1) & 1) + (_txchainmask & 1))
1010 
1011 /* EEPROM 4K bit map definations */
1012 #define	ar5416_get_eep4k_ver(_ahp)   \
1013 	(((_ahp)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF)
1014 #define	ar5416_get_eep4k_rev(_ahp)   \
1015 	(((_ahp)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF)
1016 
1017 #ifdef __BIG_ENDIAN
1018 #define	AR5416_EEPROM_MAGIC	0x5aa5
1019 #else
1020 #define	AR5416_EEPROM_MAGIC	0xa55a
1021 #endif
1022 
1023 #define	ATH9K_POW_SM(_r, _s)		(((_r) & 0x3f) << (_s))
1024 
1025 #define	ATH9K_ANTENNA0_CHAINMASK	0x1
1026 #define	ATH9K_ANTENNA1_CHAINMASK	0x2
1027 
1028 #define	ATH9K_NUM_DMA_DEBUG_REGS	8
1029 #define	ATH9K_NUM_QUEUES		10
1030 
1031 #define	HAL_NOISE_IMMUNE_MAX		4
1032 #define	HAL_SPUR_IMMUNE_MAX		7
1033 #define	HAL_FIRST_STEP_MAX		2
1034 
1035 #define	ATH9K_ANI_OFDM_TRIG_HIGH	500
1036 #define	ATH9K_ANI_OFDM_TRIG_LOW		200
1037 #define	ATH9K_ANI_CCK_TRIG_HIGH		200
1038 #define	ATH9K_ANI_CCK_TRIG_LOW		100
1039 #define	ATH9K_ANI_NOISE_IMMUNE_LVL	4
1040 #define	ATH9K_ANI_USE_OFDM_WEAK_SIG	B_TRUE
1041 #define	ATH9K_ANI_CCK_WEAK_SIG_THR	B_FALSE
1042 #define	ATH9K_ANI_SPUR_IMMUNE_LVL	7
1043 #define	ATH9K_ANI_FIRSTEP_LVL		0
1044 #define	ATH9K_ANI_RSSI_THR_HIGH		40
1045 #define	ATH9K_ANI_RSSI_THR_LOW		7
1046 #define	ATH9K_ANI_PERIOD		100
1047 
1048 #define	AR_GPIOD_MASK		0x00001FFF
1049 #define	AR_GPIO_BIT(_gpio)	(1 << (_gpio))
1050 
1051 #define	HAL_EP_RND(x, mul)	\
1052 	((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
1053 #define	BEACON_RSSI(ahp)	\
1054 	HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi,	\
1055 	ATH9K_RSSI_EP_MULTIPLIER)
1056 
1057 #define	ah_mibStats	ah_stats.ast_mibstats
1058 
1059 #define	AH_TIMEOUT	100000
1060 #define	AH_TIME_QUANTUM	10
1061 
1062 #define	AR_KEYTABLE_SIZE	128
1063 #define	POWER_UP_TIME		200000
1064 
1065 #define	EXT_ADDITIVE	(0x8000)
1066 #define	CTL_11A_EXT	(CTL_11A | EXT_ADDITIVE)
1067 #define	CTL_11G_EXT	(CTL_11G | EXT_ADDITIVE)
1068 #define	CTL_11B_EXT	(CTL_11B | EXT_ADDITIVE)
1069 
1070 #define	SUB_NUM_CTL_MODES_AT_5G_40	2
1071 #define	SUB_NUM_CTL_MODES_AT_2G_40	3
1072 #define	SPUR_RSSI_THRESH		40
1073 
1074 #define	TU_TO_USEC(_tu)		((_tu) << 10)
1075 
1076 #define	CAB_TIMEOUT_VAL		10
1077 #define	BEACON_TIMEOUT_VAL	10
1078 #define	MIN_BEACON_TIMEOUT_VAL	1
1079 #define	SLEEP_SLOP		3
1080 
1081 #define	CCK_SIFS_TIME		10
1082 #define	CCK_PREAMBLE_BITS	144
1083 #define	CCK_PLCP_BITS		48
1084 
1085 #define	OFDM_SIFS_TIME		16
1086 #define	OFDM_PREAMBLE_TIME	20
1087 #define	OFDM_PLCP_BITS		22
1088 #define	OFDM_SYMBOL_TIME	4
1089 
1090 #define	OFDM_SIFS_TIME_HALF	32
1091 #define	OFDM_PREAMBLE_TIME_HALF	40
1092 #define	OFDM_PLCP_BITS_HALF	22
1093 #define	OFDM_SYMBOL_TIME_HALF	8
1094 
1095 #define	OFDM_SIFS_TIME_QUARTER		64
1096 #define	OFDM_PREAMBLE_TIME_QUARTER	80
1097 #define	OFDM_PLCP_BITS_QUARTER		22
1098 #define	OFDM_SYMBOL_TIME_QUARTER	16
1099 
1100 uint32_t ath9k_hw_get_eeprom(struct ath_hal *ah,
1101     enum eeprom_param param);
1102 
1103 #ifdef	__cplusplus
1104 }
1105 #endif
1106 
1107 #endif	/* _ARN_HW_H */
1108