1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/endian.h>
36 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/mbuf.h>
39 #include <sys/rman.h>
40 #include <sys/module.h>
41 #include <sys/queue.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
46
47 #include <net/bpf.h>
48 #include <net/if.h>
49 #include <net/if_var.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/if_types.h>
55 #include <net/if_vlan_var.h>
56
57 #include <netinet/in.h>
58 #include <netinet/in_systm.h>
59 #include <netinet/ip.h>
60 #include <netinet/tcp.h>
61
62 #include <dev/mii/mii.h>
63 #include <dev/mii/miivar.h>
64
65 #include <dev/pci/pcireg.h>
66 #include <dev/pci/pcivar.h>
67
68 #include <machine/bus.h>
69 #include <machine/in_cksum.h>
70
71 #include <dev/age/if_agereg.h>
72 #include <dev/age/if_agevar.h>
73
74 /* "device miibus" required. See GENERIC if you get errors here. */
75 #include "miibus_if.h"
76
77 #define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
78
79 MODULE_DEPEND(age, pci, 1, 1, 1);
80 MODULE_DEPEND(age, ether, 1, 1, 1);
81 MODULE_DEPEND(age, miibus, 1, 1, 1);
82
83 /* Tunables. */
84 static int msi_disable = 0;
85 static int msix_disable = 0;
86 TUNABLE_INT("hw.age.msi_disable", &msi_disable);
87 TUNABLE_INT("hw.age.msix_disable", &msix_disable);
88
89 /*
90 * Devices supported by this driver.
91 */
92 static struct age_dev {
93 uint16_t age_vendorid;
94 uint16_t age_deviceid;
95 const char *age_name;
96 } age_devs[] = {
97 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1,
98 "Attansic Technology Corp, L1 Gigabit Ethernet" },
99 };
100
101 static int age_miibus_readreg(device_t, int, int);
102 static int age_miibus_writereg(device_t, int, int, int);
103 static void age_miibus_statchg(device_t);
104 static void age_mediastatus(if_t, struct ifmediareq *);
105 static int age_mediachange(if_t);
106 static int age_probe(device_t);
107 static void age_get_macaddr(struct age_softc *);
108 static void age_phy_reset(struct age_softc *);
109 static int age_attach(device_t);
110 static int age_detach(device_t);
111 static void age_sysctl_node(struct age_softc *);
112 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int);
113 static int age_check_boundary(struct age_softc *);
114 static int age_dma_alloc(struct age_softc *);
115 static void age_dma_free(struct age_softc *);
116 static int age_shutdown(device_t);
117 static void age_setwol(struct age_softc *);
118 static int age_suspend(device_t);
119 static int age_resume(device_t);
120 static int age_encap(struct age_softc *, struct mbuf **);
121 static void age_start(if_t);
122 static void age_start_locked(if_t);
123 static void age_watchdog(struct age_softc *);
124 static int age_ioctl(if_t, u_long, caddr_t);
125 static void age_mac_config(struct age_softc *);
126 static void age_link_task(void *, int);
127 static void age_stats_update(struct age_softc *);
128 static int age_intr(void *);
129 static void age_int_task(void *, int);
130 static void age_txintr(struct age_softc *, int);
131 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *);
132 static int age_rxintr(struct age_softc *, int, int);
133 static void age_tick(void *);
134 static void age_reset(struct age_softc *);
135 static void age_init(void *);
136 static void age_init_locked(struct age_softc *);
137 static void age_stop(struct age_softc *);
138 static void age_stop_txmac(struct age_softc *);
139 static void age_stop_rxmac(struct age_softc *);
140 static void age_init_tx_ring(struct age_softc *);
141 static int age_init_rx_ring(struct age_softc *);
142 static void age_init_rr_ring(struct age_softc *);
143 static void age_init_cmb_block(struct age_softc *);
144 static void age_init_smb_block(struct age_softc *);
145 #ifndef __NO_STRICT_ALIGNMENT
146 static struct mbuf *age_fixup_rx(if_t, struct mbuf *);
147 #endif
148 static int age_newbuf(struct age_softc *, struct age_rxdesc *);
149 static void age_rxvlan(struct age_softc *);
150 static void age_rxfilter(struct age_softc *);
151 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS);
152 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
153 static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS);
154 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS);
155
156 static device_method_t age_methods[] = {
157 /* Device interface. */
158 DEVMETHOD(device_probe, age_probe),
159 DEVMETHOD(device_attach, age_attach),
160 DEVMETHOD(device_detach, age_detach),
161 DEVMETHOD(device_shutdown, age_shutdown),
162 DEVMETHOD(device_suspend, age_suspend),
163 DEVMETHOD(device_resume, age_resume),
164
165 /* MII interface. */
166 DEVMETHOD(miibus_readreg, age_miibus_readreg),
167 DEVMETHOD(miibus_writereg, age_miibus_writereg),
168 DEVMETHOD(miibus_statchg, age_miibus_statchg),
169 { NULL, NULL }
170 };
171
172 static driver_t age_driver = {
173 "age",
174 age_methods,
175 sizeof(struct age_softc)
176 };
177
178 DRIVER_MODULE(age, pci, age_driver, 0, 0);
179 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, age, age_devs,
180 nitems(age_devs));
181 DRIVER_MODULE(miibus, age, miibus_driver, 0, 0);
182
183 static struct resource_spec age_res_spec_mem[] = {
184 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
185 { -1, 0, 0 }
186 };
187
188 static struct resource_spec age_irq_spec_legacy[] = {
189 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
190 { -1, 0, 0 }
191 };
192
193 static struct resource_spec age_irq_spec_msi[] = {
194 { SYS_RES_IRQ, 1, RF_ACTIVE },
195 { -1, 0, 0 }
196 };
197
198 static struct resource_spec age_irq_spec_msix[] = {
199 { SYS_RES_IRQ, 1, RF_ACTIVE },
200 { -1, 0, 0 }
201 };
202
203 /*
204 * Read a PHY register on the MII of the L1.
205 */
206 static int
age_miibus_readreg(device_t dev,int phy,int reg)207 age_miibus_readreg(device_t dev, int phy, int reg)
208 {
209 struct age_softc *sc;
210 uint32_t v;
211 int i;
212
213 sc = device_get_softc(dev);
214
215 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
216 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
217 for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
218 DELAY(1);
219 v = CSR_READ_4(sc, AGE_MDIO);
220 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
221 break;
222 }
223
224 if (i == 0) {
225 device_printf(sc->age_dev, "phy read timeout : %d\n", reg);
226 return (0);
227 }
228
229 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
230 }
231
232 /*
233 * Write a PHY register on the MII of the L1.
234 */
235 static int
age_miibus_writereg(device_t dev,int phy,int reg,int val)236 age_miibus_writereg(device_t dev, int phy, int reg, int val)
237 {
238 struct age_softc *sc;
239 uint32_t v;
240 int i;
241
242 sc = device_get_softc(dev);
243
244 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
245 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
246 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
247 for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
248 DELAY(1);
249 v = CSR_READ_4(sc, AGE_MDIO);
250 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
251 break;
252 }
253
254 if (i == 0)
255 device_printf(sc->age_dev, "phy write timeout : %d\n", reg);
256
257 return (0);
258 }
259
260 /*
261 * Callback from MII layer when media changes.
262 */
263 static void
age_miibus_statchg(device_t dev)264 age_miibus_statchg(device_t dev)
265 {
266 struct age_softc *sc;
267
268 sc = device_get_softc(dev);
269 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task);
270 }
271
272 /*
273 * Get the current interface media status.
274 */
275 static void
age_mediastatus(if_t ifp,struct ifmediareq * ifmr)276 age_mediastatus(if_t ifp, struct ifmediareq *ifmr)
277 {
278 struct age_softc *sc;
279 struct mii_data *mii;
280
281 sc = if_getsoftc(ifp);
282 AGE_LOCK(sc);
283 mii = device_get_softc(sc->age_miibus);
284
285 mii_pollstat(mii);
286 ifmr->ifm_status = mii->mii_media_status;
287 ifmr->ifm_active = mii->mii_media_active;
288 AGE_UNLOCK(sc);
289 }
290
291 /*
292 * Set hardware to newly-selected media.
293 */
294 static int
age_mediachange(if_t ifp)295 age_mediachange(if_t ifp)
296 {
297 struct age_softc *sc;
298 struct mii_data *mii;
299 struct mii_softc *miisc;
300 int error;
301
302 sc = if_getsoftc(ifp);
303 AGE_LOCK(sc);
304 mii = device_get_softc(sc->age_miibus);
305 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
306 PHY_RESET(miisc);
307 error = mii_mediachg(mii);
308 AGE_UNLOCK(sc);
309
310 return (error);
311 }
312
313 static int
age_probe(device_t dev)314 age_probe(device_t dev)
315 {
316 struct age_dev *sp;
317 int i;
318 uint16_t vendor, devid;
319
320 vendor = pci_get_vendor(dev);
321 devid = pci_get_device(dev);
322 sp = age_devs;
323 for (i = 0; i < nitems(age_devs); i++, sp++) {
324 if (vendor == sp->age_vendorid &&
325 devid == sp->age_deviceid) {
326 device_set_desc(dev, sp->age_name);
327 return (BUS_PROBE_DEFAULT);
328 }
329 }
330
331 return (ENXIO);
332 }
333
334 static void
age_get_macaddr(struct age_softc * sc)335 age_get_macaddr(struct age_softc *sc)
336 {
337 uint32_t ea[2], reg;
338 int i, vpdc;
339
340 reg = CSR_READ_4(sc, AGE_SPI_CTRL);
341 if ((reg & SPI_VPD_ENB) != 0) {
342 /* Get VPD stored in TWSI EEPROM. */
343 reg &= ~SPI_VPD_ENB;
344 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
345 }
346
347 if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) {
348 /*
349 * PCI VPD capability found, let TWSI reload EEPROM.
350 * This will set ethernet address of controller.
351 */
352 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
353 TWSI_CTRL_SW_LD_START);
354 for (i = 100; i > 0; i--) {
355 DELAY(1000);
356 reg = CSR_READ_4(sc, AGE_TWSI_CTRL);
357 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
358 break;
359 }
360 if (i == 0)
361 device_printf(sc->age_dev,
362 "reloading EEPROM timeout!\n");
363 } else {
364 if (bootverbose)
365 device_printf(sc->age_dev,
366 "PCI VPD capability not found!\n");
367 }
368
369 ea[0] = CSR_READ_4(sc, AGE_PAR0);
370 ea[1] = CSR_READ_4(sc, AGE_PAR1);
371 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF;
372 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF;
373 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF;
374 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF;
375 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF;
376 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF;
377 }
378
379 static void
age_phy_reset(struct age_softc * sc)380 age_phy_reset(struct age_softc *sc)
381 {
382 uint16_t reg, pn;
383 int i, linkup;
384
385 /* Reset PHY. */
386 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST);
387 DELAY(2000);
388 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR);
389 DELAY(2000);
390
391 #define ATPHY_DBG_ADDR 0x1D
392 #define ATPHY_DBG_DATA 0x1E
393 #define ATPHY_CDTC 0x16
394 #define PHY_CDTC_ENB 0x0001
395 #define PHY_CDTC_POFF 8
396 #define ATPHY_CDTS 0x1C
397 #define PHY_CDTS_STAT_OK 0x0000
398 #define PHY_CDTS_STAT_SHORT 0x0100
399 #define PHY_CDTS_STAT_OPEN 0x0200
400 #define PHY_CDTS_STAT_INVAL 0x0300
401 #define PHY_CDTS_STAT_MASK 0x0300
402
403 /* Check power saving mode. Magic from Linux. */
404 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET);
405 for (linkup = 0, pn = 0; pn < 4; pn++) {
406 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC,
407 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB);
408 for (i = 200; i > 0; i--) {
409 DELAY(1000);
410 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
411 ATPHY_CDTC);
412 if ((reg & PHY_CDTC_ENB) == 0)
413 break;
414 }
415 DELAY(1000);
416 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
417 ATPHY_CDTS);
418 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) {
419 linkup++;
420 break;
421 }
422 }
423 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR,
424 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
425 if (linkup == 0) {
426 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
427 ATPHY_DBG_ADDR, 0);
428 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
429 ATPHY_DBG_DATA, 0x124E);
430 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
431 ATPHY_DBG_ADDR, 1);
432 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
433 ATPHY_DBG_DATA);
434 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
435 ATPHY_DBG_DATA, reg | 0x03);
436 /* XXX */
437 DELAY(1500 * 1000);
438 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
439 ATPHY_DBG_ADDR, 0);
440 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
441 ATPHY_DBG_DATA, 0x024E);
442 }
443
444 #undef ATPHY_DBG_ADDR
445 #undef ATPHY_DBG_DATA
446 #undef ATPHY_CDTC
447 #undef PHY_CDTC_ENB
448 #undef PHY_CDTC_POFF
449 #undef ATPHY_CDTS
450 #undef PHY_CDTS_STAT_OK
451 #undef PHY_CDTS_STAT_SHORT
452 #undef PHY_CDTS_STAT_OPEN
453 #undef PHY_CDTS_STAT_INVAL
454 #undef PHY_CDTS_STAT_MASK
455 }
456
457 static int
age_attach(device_t dev)458 age_attach(device_t dev)
459 {
460 struct age_softc *sc;
461 if_t ifp;
462 uint16_t burst;
463 int error, i, msic, msixc, pmc;
464
465 error = 0;
466 sc = device_get_softc(dev);
467 sc->age_dev = dev;
468
469 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
470 MTX_DEF);
471 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0);
472 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc);
473 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc);
474
475 /* Map the device. */
476 pci_enable_busmaster(dev);
477 sc->age_res_spec = age_res_spec_mem;
478 sc->age_irq_spec = age_irq_spec_legacy;
479 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res);
480 if (error != 0) {
481 device_printf(dev, "cannot allocate memory resources.\n");
482 goto fail;
483 }
484
485 /* Set PHY address. */
486 sc->age_phyaddr = AGE_PHY_ADDR;
487
488 /* Reset PHY. */
489 age_phy_reset(sc);
490
491 /* Reset the ethernet controller. */
492 age_reset(sc);
493
494 /* Get PCI and chip id/revision. */
495 sc->age_rev = pci_get_revid(dev);
496 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
497 MASTER_CHIP_REV_SHIFT;
498 if (bootverbose) {
499 device_printf(dev, "PCI device revision : 0x%04x\n",
500 sc->age_rev);
501 device_printf(dev, "Chip id/revision : 0x%04x\n",
502 sc->age_chip_rev);
503 }
504
505 /*
506 * XXX
507 * Unintialized hardware returns an invalid chip id/revision
508 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that
509 * unplugged cable results in putting hardware into automatic
510 * power down mode which in turn returns invalld chip revision.
511 */
512 if (sc->age_chip_rev == 0xFFFF) {
513 device_printf(dev,"invalid chip revision : 0x%04x -- "
514 "not initialized?\n", sc->age_chip_rev);
515 error = ENXIO;
516 goto fail;
517 }
518
519 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n",
520 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),
521 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN));
522
523 /* Allocate IRQ resources. */
524 msixc = pci_msix_count(dev);
525 msic = pci_msi_count(dev);
526 if (bootverbose) {
527 device_printf(dev, "MSIX count : %d\n", msixc);
528 device_printf(dev, "MSI count : %d\n", msic);
529 }
530
531 /* Prefer MSIX over MSI. */
532 if (msix_disable == 0 || msi_disable == 0) {
533 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES &&
534 pci_alloc_msix(dev, &msixc) == 0) {
535 if (msic == AGE_MSIX_MESSAGES) {
536 device_printf(dev, "Using %d MSIX messages.\n",
537 msixc);
538 sc->age_flags |= AGE_FLAG_MSIX;
539 sc->age_irq_spec = age_irq_spec_msix;
540 } else
541 pci_release_msi(dev);
542 }
543 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 &&
544 msic == AGE_MSI_MESSAGES &&
545 pci_alloc_msi(dev, &msic) == 0) {
546 if (msic == AGE_MSI_MESSAGES) {
547 device_printf(dev, "Using %d MSI messages.\n",
548 msic);
549 sc->age_flags |= AGE_FLAG_MSI;
550 sc->age_irq_spec = age_irq_spec_msi;
551 } else
552 pci_release_msi(dev);
553 }
554 }
555
556 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq);
557 if (error != 0) {
558 device_printf(dev, "cannot allocate IRQ resources.\n");
559 goto fail;
560 }
561
562 /* Get DMA parameters from PCIe device control register. */
563 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
564 sc->age_flags |= AGE_FLAG_PCIE;
565 burst = pci_read_config(dev, i + 0x08, 2);
566 /* Max read request size. */
567 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) <<
568 DMA_CFG_RD_BURST_SHIFT;
569 /* Max payload size. */
570 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) <<
571 DMA_CFG_WR_BURST_SHIFT;
572 if (bootverbose) {
573 device_printf(dev, "Read request size : %d bytes.\n",
574 128 << ((burst >> 12) & 0x07));
575 device_printf(dev, "TLP payload size : %d bytes.\n",
576 128 << ((burst >> 5) & 0x07));
577 }
578 } else {
579 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128;
580 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128;
581 }
582
583 /* Create device sysctl node. */
584 age_sysctl_node(sc);
585
586 if ((error = age_dma_alloc(sc)) != 0)
587 goto fail;
588
589 /* Load station address. */
590 age_get_macaddr(sc);
591
592 ifp = sc->age_ifp = if_alloc(IFT_ETHER);
593 if_setsoftc(ifp, sc);
594 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
595 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
596 if_setioctlfn(ifp, age_ioctl);
597 if_setstartfn(ifp, age_start);
598 if_setinitfn(ifp, age_init);
599 if_setsendqlen(ifp, AGE_TX_RING_CNT - 1);
600 if_setsendqready(ifp);
601 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_TSO4);
602 if_sethwassist(ifp, AGE_CSUM_FEATURES | CSUM_TSO);
603 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
604 sc->age_flags |= AGE_FLAG_PMCAP;
605 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0);
606 }
607 if_setcapenable(ifp, if_getcapabilities(ifp));
608
609 /* Set up MII bus. */
610 error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange,
611 age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY,
612 0);
613 if (error != 0) {
614 device_printf(dev, "attaching PHYs failed\n");
615 goto fail;
616 }
617
618 ether_ifattach(ifp, sc->age_eaddr);
619
620 /* VLAN capability setup. */
621 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
622 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
623 if_setcapenable(ifp, if_getcapabilities(ifp));
624
625 /* Tell the upper layer(s) we support long frames. */
626 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
627
628 /* Create local taskq. */
629 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK,
630 taskqueue_thread_enqueue, &sc->age_tq);
631 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq",
632 device_get_nameunit(sc->age_dev));
633
634 if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
635 msic = AGE_MSIX_MESSAGES;
636 else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
637 msic = AGE_MSI_MESSAGES;
638 else
639 msic = 1;
640 for (i = 0; i < msic; i++) {
641 error = bus_setup_intr(dev, sc->age_irq[i],
642 INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc,
643 &sc->age_intrhand[i]);
644 if (error != 0)
645 break;
646 }
647 if (error != 0) {
648 device_printf(dev, "could not set up interrupt handler.\n");
649 taskqueue_free(sc->age_tq);
650 sc->age_tq = NULL;
651 ether_ifdetach(ifp);
652 goto fail;
653 }
654
655 fail:
656 if (error != 0)
657 age_detach(dev);
658
659 return (error);
660 }
661
662 static int
age_detach(device_t dev)663 age_detach(device_t dev)
664 {
665 struct age_softc *sc;
666 if_t ifp;
667 int i, msic;
668
669 sc = device_get_softc(dev);
670
671 ifp = sc->age_ifp;
672 if (device_is_attached(dev)) {
673 AGE_LOCK(sc);
674 sc->age_flags |= AGE_FLAG_DETACH;
675 age_stop(sc);
676 AGE_UNLOCK(sc);
677 callout_drain(&sc->age_tick_ch);
678 taskqueue_drain(sc->age_tq, &sc->age_int_task);
679 taskqueue_drain(taskqueue_swi, &sc->age_link_task);
680 ether_ifdetach(ifp);
681 }
682
683 if (sc->age_tq != NULL) {
684 taskqueue_drain(sc->age_tq, &sc->age_int_task);
685 taskqueue_free(sc->age_tq);
686 sc->age_tq = NULL;
687 }
688
689 if (sc->age_miibus != NULL) {
690 device_delete_child(dev, sc->age_miibus);
691 sc->age_miibus = NULL;
692 }
693 bus_generic_detach(dev);
694 age_dma_free(sc);
695
696 if (ifp != NULL) {
697 if_free(ifp);
698 sc->age_ifp = NULL;
699 }
700
701 if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
702 msic = AGE_MSIX_MESSAGES;
703 else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
704 msic = AGE_MSI_MESSAGES;
705 else
706 msic = 1;
707 for (i = 0; i < msic; i++) {
708 if (sc->age_intrhand[i] != NULL) {
709 bus_teardown_intr(dev, sc->age_irq[i],
710 sc->age_intrhand[i]);
711 sc->age_intrhand[i] = NULL;
712 }
713 }
714
715 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq);
716 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0)
717 pci_release_msi(dev);
718 bus_release_resources(dev, sc->age_res_spec, sc->age_res);
719 mtx_destroy(&sc->age_mtx);
720
721 return (0);
722 }
723
724 static void
age_sysctl_node(struct age_softc * sc)725 age_sysctl_node(struct age_softc *sc)
726 {
727 int error;
728
729 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
730 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
731 "stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
732 sc, 0, sysctl_age_stats, "I", "Statistics");
733
734 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
735 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
736 "int_mod", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
737 &sc->age_int_mod, 0, sysctl_hw_age_int_mod, "I",
738 "age interrupt moderation");
739
740 /* Pull in device tunables. */
741 sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
742 error = resource_int_value(device_get_name(sc->age_dev),
743 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod);
744 if (error == 0) {
745 if (sc->age_int_mod < AGE_IM_TIMER_MIN ||
746 sc->age_int_mod > AGE_IM_TIMER_MAX) {
747 device_printf(sc->age_dev,
748 "int_mod value out of range; using default: %d\n",
749 AGE_IM_TIMER_DEFAULT);
750 sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
751 }
752 }
753
754 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
755 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
756 "process_limit", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
757 &sc->age_process_limit, 0, sysctl_hw_age_proc_limit, "I",
758 "max number of Rx events to process");
759
760 /* Pull in device tunables. */
761 sc->age_process_limit = AGE_PROC_DEFAULT;
762 error = resource_int_value(device_get_name(sc->age_dev),
763 device_get_unit(sc->age_dev), "process_limit",
764 &sc->age_process_limit);
765 if (error == 0) {
766 if (sc->age_process_limit < AGE_PROC_MIN ||
767 sc->age_process_limit > AGE_PROC_MAX) {
768 device_printf(sc->age_dev,
769 "process_limit value out of range; "
770 "using default: %d\n", AGE_PROC_DEFAULT);
771 sc->age_process_limit = AGE_PROC_DEFAULT;
772 }
773 }
774 }
775
776 struct age_dmamap_arg {
777 bus_addr_t age_busaddr;
778 };
779
780 static void
age_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)781 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
782 {
783 struct age_dmamap_arg *ctx;
784
785 if (error != 0)
786 return;
787
788 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
789
790 ctx = (struct age_dmamap_arg *)arg;
791 ctx->age_busaddr = segs[0].ds_addr;
792 }
793
794 /*
795 * Attansic L1 controller have single register to specify high
796 * address part of DMA blocks. So all descriptor structures and
797 * DMA memory blocks should have the same high address of given
798 * 4GB address space(i.e. crossing 4GB boundary is not allowed).
799 */
800 static int
age_check_boundary(struct age_softc * sc)801 age_check_boundary(struct age_softc *sc)
802 {
803 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end;
804 bus_addr_t cmb_block_end, smb_block_end;
805
806 /* Tx/Rx descriptor queue should reside within 4GB boundary. */
807 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ;
808 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ;
809 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ;
810 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ;
811 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ;
812
813 if ((AGE_ADDR_HI(tx_ring_end) !=
814 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) ||
815 (AGE_ADDR_HI(rx_ring_end) !=
816 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) ||
817 (AGE_ADDR_HI(rr_ring_end) !=
818 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) ||
819 (AGE_ADDR_HI(cmb_block_end) !=
820 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) ||
821 (AGE_ADDR_HI(smb_block_end) !=
822 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr)))
823 return (EFBIG);
824
825 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) ||
826 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) ||
827 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) ||
828 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end)))
829 return (EFBIG);
830
831 return (0);
832 }
833
834 static int
age_dma_alloc(struct age_softc * sc)835 age_dma_alloc(struct age_softc *sc)
836 {
837 struct age_txdesc *txd;
838 struct age_rxdesc *rxd;
839 bus_addr_t lowaddr;
840 struct age_dmamap_arg ctx;
841 int error, i;
842
843 lowaddr = BUS_SPACE_MAXADDR;
844
845 again:
846 /* Create parent ring/DMA block tag. */
847 error = bus_dma_tag_create(
848 bus_get_dma_tag(sc->age_dev), /* parent */
849 1, 0, /* alignment, boundary */
850 lowaddr, /* lowaddr */
851 BUS_SPACE_MAXADDR, /* highaddr */
852 NULL, NULL, /* filter, filterarg */
853 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
854 0, /* nsegments */
855 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
856 0, /* flags */
857 NULL, NULL, /* lockfunc, lockarg */
858 &sc->age_cdata.age_parent_tag);
859 if (error != 0) {
860 device_printf(sc->age_dev,
861 "could not create parent DMA tag.\n");
862 goto fail;
863 }
864
865 /* Create tag for Tx ring. */
866 error = bus_dma_tag_create(
867 sc->age_cdata.age_parent_tag, /* parent */
868 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */
869 BUS_SPACE_MAXADDR, /* lowaddr */
870 BUS_SPACE_MAXADDR, /* highaddr */
871 NULL, NULL, /* filter, filterarg */
872 AGE_TX_RING_SZ, /* maxsize */
873 1, /* nsegments */
874 AGE_TX_RING_SZ, /* maxsegsize */
875 0, /* flags */
876 NULL, NULL, /* lockfunc, lockarg */
877 &sc->age_cdata.age_tx_ring_tag);
878 if (error != 0) {
879 device_printf(sc->age_dev,
880 "could not create Tx ring DMA tag.\n");
881 goto fail;
882 }
883
884 /* Create tag for Rx ring. */
885 error = bus_dma_tag_create(
886 sc->age_cdata.age_parent_tag, /* parent */
887 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */
888 BUS_SPACE_MAXADDR, /* lowaddr */
889 BUS_SPACE_MAXADDR, /* highaddr */
890 NULL, NULL, /* filter, filterarg */
891 AGE_RX_RING_SZ, /* maxsize */
892 1, /* nsegments */
893 AGE_RX_RING_SZ, /* maxsegsize */
894 0, /* flags */
895 NULL, NULL, /* lockfunc, lockarg */
896 &sc->age_cdata.age_rx_ring_tag);
897 if (error != 0) {
898 device_printf(sc->age_dev,
899 "could not create Rx ring DMA tag.\n");
900 goto fail;
901 }
902
903 /* Create tag for Rx return ring. */
904 error = bus_dma_tag_create(
905 sc->age_cdata.age_parent_tag, /* parent */
906 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */
907 BUS_SPACE_MAXADDR, /* lowaddr */
908 BUS_SPACE_MAXADDR, /* highaddr */
909 NULL, NULL, /* filter, filterarg */
910 AGE_RR_RING_SZ, /* maxsize */
911 1, /* nsegments */
912 AGE_RR_RING_SZ, /* maxsegsize */
913 0, /* flags */
914 NULL, NULL, /* lockfunc, lockarg */
915 &sc->age_cdata.age_rr_ring_tag);
916 if (error != 0) {
917 device_printf(sc->age_dev,
918 "could not create Rx return ring DMA tag.\n");
919 goto fail;
920 }
921
922 /* Create tag for coalesing message block. */
923 error = bus_dma_tag_create(
924 sc->age_cdata.age_parent_tag, /* parent */
925 AGE_CMB_ALIGN, 0, /* alignment, boundary */
926 BUS_SPACE_MAXADDR, /* lowaddr */
927 BUS_SPACE_MAXADDR, /* highaddr */
928 NULL, NULL, /* filter, filterarg */
929 AGE_CMB_BLOCK_SZ, /* maxsize */
930 1, /* nsegments */
931 AGE_CMB_BLOCK_SZ, /* maxsegsize */
932 0, /* flags */
933 NULL, NULL, /* lockfunc, lockarg */
934 &sc->age_cdata.age_cmb_block_tag);
935 if (error != 0) {
936 device_printf(sc->age_dev,
937 "could not create CMB DMA tag.\n");
938 goto fail;
939 }
940
941 /* Create tag for statistics message block. */
942 error = bus_dma_tag_create(
943 sc->age_cdata.age_parent_tag, /* parent */
944 AGE_SMB_ALIGN, 0, /* alignment, boundary */
945 BUS_SPACE_MAXADDR, /* lowaddr */
946 BUS_SPACE_MAXADDR, /* highaddr */
947 NULL, NULL, /* filter, filterarg */
948 AGE_SMB_BLOCK_SZ, /* maxsize */
949 1, /* nsegments */
950 AGE_SMB_BLOCK_SZ, /* maxsegsize */
951 0, /* flags */
952 NULL, NULL, /* lockfunc, lockarg */
953 &sc->age_cdata.age_smb_block_tag);
954 if (error != 0) {
955 device_printf(sc->age_dev,
956 "could not create SMB DMA tag.\n");
957 goto fail;
958 }
959
960 /* Allocate DMA'able memory and load the DMA map. */
961 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag,
962 (void **)&sc->age_rdata.age_tx_ring,
963 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
964 &sc->age_cdata.age_tx_ring_map);
965 if (error != 0) {
966 device_printf(sc->age_dev,
967 "could not allocate DMA'able memory for Tx ring.\n");
968 goto fail;
969 }
970 ctx.age_busaddr = 0;
971 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag,
972 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring,
973 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0);
974 if (error != 0 || ctx.age_busaddr == 0) {
975 device_printf(sc->age_dev,
976 "could not load DMA'able memory for Tx ring.\n");
977 goto fail;
978 }
979 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr;
980 /* Rx ring */
981 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag,
982 (void **)&sc->age_rdata.age_rx_ring,
983 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
984 &sc->age_cdata.age_rx_ring_map);
985 if (error != 0) {
986 device_printf(sc->age_dev,
987 "could not allocate DMA'able memory for Rx ring.\n");
988 goto fail;
989 }
990 ctx.age_busaddr = 0;
991 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag,
992 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring,
993 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0);
994 if (error != 0 || ctx.age_busaddr == 0) {
995 device_printf(sc->age_dev,
996 "could not load DMA'able memory for Rx ring.\n");
997 goto fail;
998 }
999 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr;
1000 /* Rx return ring */
1001 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag,
1002 (void **)&sc->age_rdata.age_rr_ring,
1003 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1004 &sc->age_cdata.age_rr_ring_map);
1005 if (error != 0) {
1006 device_printf(sc->age_dev,
1007 "could not allocate DMA'able memory for Rx return ring.\n");
1008 goto fail;
1009 }
1010 ctx.age_busaddr = 0;
1011 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag,
1012 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring,
1013 AGE_RR_RING_SZ, age_dmamap_cb,
1014 &ctx, 0);
1015 if (error != 0 || ctx.age_busaddr == 0) {
1016 device_printf(sc->age_dev,
1017 "could not load DMA'able memory for Rx return ring.\n");
1018 goto fail;
1019 }
1020 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr;
1021 /* CMB block */
1022 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag,
1023 (void **)&sc->age_rdata.age_cmb_block,
1024 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1025 &sc->age_cdata.age_cmb_block_map);
1026 if (error != 0) {
1027 device_printf(sc->age_dev,
1028 "could not allocate DMA'able memory for CMB block.\n");
1029 goto fail;
1030 }
1031 ctx.age_busaddr = 0;
1032 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag,
1033 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block,
1034 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1035 if (error != 0 || ctx.age_busaddr == 0) {
1036 device_printf(sc->age_dev,
1037 "could not load DMA'able memory for CMB block.\n");
1038 goto fail;
1039 }
1040 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr;
1041 /* SMB block */
1042 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag,
1043 (void **)&sc->age_rdata.age_smb_block,
1044 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1045 &sc->age_cdata.age_smb_block_map);
1046 if (error != 0) {
1047 device_printf(sc->age_dev,
1048 "could not allocate DMA'able memory for SMB block.\n");
1049 goto fail;
1050 }
1051 ctx.age_busaddr = 0;
1052 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag,
1053 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block,
1054 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1055 if (error != 0 || ctx.age_busaddr == 0) {
1056 device_printf(sc->age_dev,
1057 "could not load DMA'able memory for SMB block.\n");
1058 goto fail;
1059 }
1060 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr;
1061
1062 /*
1063 * All ring buffer and DMA blocks should have the same
1064 * high address part of 64bit DMA address space.
1065 */
1066 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1067 (error = age_check_boundary(sc)) != 0) {
1068 device_printf(sc->age_dev, "4GB boundary crossed, "
1069 "switching to 32bit DMA addressing mode.\n");
1070 age_dma_free(sc);
1071 /* Limit DMA address space to 32bit and try again. */
1072 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1073 goto again;
1074 }
1075
1076 /*
1077 * Create Tx/Rx buffer parent tag.
1078 * L1 supports full 64bit DMA addressing in Tx/Rx buffers
1079 * so it needs separate parent DMA tag.
1080 * XXX
1081 * It seems enabling 64bit DMA causes data corruption. Limit
1082 * DMA address space to 32bit.
1083 */
1084 error = bus_dma_tag_create(
1085 bus_get_dma_tag(sc->age_dev), /* parent */
1086 1, 0, /* alignment, boundary */
1087 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1088 BUS_SPACE_MAXADDR, /* highaddr */
1089 NULL, NULL, /* filter, filterarg */
1090 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1091 0, /* nsegments */
1092 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1093 0, /* flags */
1094 NULL, NULL, /* lockfunc, lockarg */
1095 &sc->age_cdata.age_buffer_tag);
1096 if (error != 0) {
1097 device_printf(sc->age_dev,
1098 "could not create parent buffer DMA tag.\n");
1099 goto fail;
1100 }
1101
1102 /* Create tag for Tx buffers. */
1103 error = bus_dma_tag_create(
1104 sc->age_cdata.age_buffer_tag, /* parent */
1105 1, 0, /* alignment, boundary */
1106 BUS_SPACE_MAXADDR, /* lowaddr */
1107 BUS_SPACE_MAXADDR, /* highaddr */
1108 NULL, NULL, /* filter, filterarg */
1109 AGE_TSO_MAXSIZE, /* maxsize */
1110 AGE_MAXTXSEGS, /* nsegments */
1111 AGE_TSO_MAXSEGSIZE, /* maxsegsize */
1112 0, /* flags */
1113 NULL, NULL, /* lockfunc, lockarg */
1114 &sc->age_cdata.age_tx_tag);
1115 if (error != 0) {
1116 device_printf(sc->age_dev, "could not create Tx DMA tag.\n");
1117 goto fail;
1118 }
1119
1120 /* Create tag for Rx buffers. */
1121 error = bus_dma_tag_create(
1122 sc->age_cdata.age_buffer_tag, /* parent */
1123 AGE_RX_BUF_ALIGN, 0, /* alignment, boundary */
1124 BUS_SPACE_MAXADDR, /* lowaddr */
1125 BUS_SPACE_MAXADDR, /* highaddr */
1126 NULL, NULL, /* filter, filterarg */
1127 MCLBYTES, /* maxsize */
1128 1, /* nsegments */
1129 MCLBYTES, /* maxsegsize */
1130 0, /* flags */
1131 NULL, NULL, /* lockfunc, lockarg */
1132 &sc->age_cdata.age_rx_tag);
1133 if (error != 0) {
1134 device_printf(sc->age_dev, "could not create Rx DMA tag.\n");
1135 goto fail;
1136 }
1137
1138 /* Create DMA maps for Tx buffers. */
1139 for (i = 0; i < AGE_TX_RING_CNT; i++) {
1140 txd = &sc->age_cdata.age_txdesc[i];
1141 txd->tx_m = NULL;
1142 txd->tx_dmamap = NULL;
1143 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0,
1144 &txd->tx_dmamap);
1145 if (error != 0) {
1146 device_printf(sc->age_dev,
1147 "could not create Tx dmamap.\n");
1148 goto fail;
1149 }
1150 }
1151 /* Create DMA maps for Rx buffers. */
1152 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1153 &sc->age_cdata.age_rx_sparemap)) != 0) {
1154 device_printf(sc->age_dev,
1155 "could not create spare Rx dmamap.\n");
1156 goto fail;
1157 }
1158 for (i = 0; i < AGE_RX_RING_CNT; i++) {
1159 rxd = &sc->age_cdata.age_rxdesc[i];
1160 rxd->rx_m = NULL;
1161 rxd->rx_dmamap = NULL;
1162 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1163 &rxd->rx_dmamap);
1164 if (error != 0) {
1165 device_printf(sc->age_dev,
1166 "could not create Rx dmamap.\n");
1167 goto fail;
1168 }
1169 }
1170
1171 fail:
1172 return (error);
1173 }
1174
1175 static void
age_dma_free(struct age_softc * sc)1176 age_dma_free(struct age_softc *sc)
1177 {
1178 struct age_txdesc *txd;
1179 struct age_rxdesc *rxd;
1180 int i;
1181
1182 /* Tx buffers */
1183 if (sc->age_cdata.age_tx_tag != NULL) {
1184 for (i = 0; i < AGE_TX_RING_CNT; i++) {
1185 txd = &sc->age_cdata.age_txdesc[i];
1186 if (txd->tx_dmamap != NULL) {
1187 bus_dmamap_destroy(sc->age_cdata.age_tx_tag,
1188 txd->tx_dmamap);
1189 txd->tx_dmamap = NULL;
1190 }
1191 }
1192 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag);
1193 sc->age_cdata.age_tx_tag = NULL;
1194 }
1195 /* Rx buffers */
1196 if (sc->age_cdata.age_rx_tag != NULL) {
1197 for (i = 0; i < AGE_RX_RING_CNT; i++) {
1198 rxd = &sc->age_cdata.age_rxdesc[i];
1199 if (rxd->rx_dmamap != NULL) {
1200 bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1201 rxd->rx_dmamap);
1202 rxd->rx_dmamap = NULL;
1203 }
1204 }
1205 if (sc->age_cdata.age_rx_sparemap != NULL) {
1206 bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1207 sc->age_cdata.age_rx_sparemap);
1208 sc->age_cdata.age_rx_sparemap = NULL;
1209 }
1210 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag);
1211 sc->age_cdata.age_rx_tag = NULL;
1212 }
1213 /* Tx ring. */
1214 if (sc->age_cdata.age_tx_ring_tag != NULL) {
1215 if (sc->age_rdata.age_tx_ring_paddr != 0)
1216 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag,
1217 sc->age_cdata.age_tx_ring_map);
1218 if (sc->age_rdata.age_tx_ring != NULL)
1219 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag,
1220 sc->age_rdata.age_tx_ring,
1221 sc->age_cdata.age_tx_ring_map);
1222 sc->age_rdata.age_tx_ring_paddr = 0;
1223 sc->age_rdata.age_tx_ring = NULL;
1224 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag);
1225 sc->age_cdata.age_tx_ring_tag = NULL;
1226 }
1227 /* Rx ring. */
1228 if (sc->age_cdata.age_rx_ring_tag != NULL) {
1229 if (sc->age_rdata.age_rx_ring_paddr != 0)
1230 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag,
1231 sc->age_cdata.age_rx_ring_map);
1232 if (sc->age_rdata.age_rx_ring != NULL)
1233 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag,
1234 sc->age_rdata.age_rx_ring,
1235 sc->age_cdata.age_rx_ring_map);
1236 sc->age_rdata.age_rx_ring_paddr = 0;
1237 sc->age_rdata.age_rx_ring = NULL;
1238 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag);
1239 sc->age_cdata.age_rx_ring_tag = NULL;
1240 }
1241 /* Rx return ring. */
1242 if (sc->age_cdata.age_rr_ring_tag != NULL) {
1243 if (sc->age_rdata.age_rr_ring_paddr != 0)
1244 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag,
1245 sc->age_cdata.age_rr_ring_map);
1246 if (sc->age_rdata.age_rr_ring != NULL)
1247 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag,
1248 sc->age_rdata.age_rr_ring,
1249 sc->age_cdata.age_rr_ring_map);
1250 sc->age_rdata.age_rr_ring_paddr = 0;
1251 sc->age_rdata.age_rr_ring = NULL;
1252 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag);
1253 sc->age_cdata.age_rr_ring_tag = NULL;
1254 }
1255 /* CMB block */
1256 if (sc->age_cdata.age_cmb_block_tag != NULL) {
1257 if (sc->age_rdata.age_cmb_block_paddr != 0)
1258 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag,
1259 sc->age_cdata.age_cmb_block_map);
1260 if (sc->age_rdata.age_cmb_block != NULL)
1261 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag,
1262 sc->age_rdata.age_cmb_block,
1263 sc->age_cdata.age_cmb_block_map);
1264 sc->age_rdata.age_cmb_block_paddr = 0;
1265 sc->age_rdata.age_cmb_block = NULL;
1266 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag);
1267 sc->age_cdata.age_cmb_block_tag = NULL;
1268 }
1269 /* SMB block */
1270 if (sc->age_cdata.age_smb_block_tag != NULL) {
1271 if (sc->age_rdata.age_smb_block_paddr != 0)
1272 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag,
1273 sc->age_cdata.age_smb_block_map);
1274 if (sc->age_rdata.age_smb_block != NULL)
1275 bus_dmamem_free(sc->age_cdata.age_smb_block_tag,
1276 sc->age_rdata.age_smb_block,
1277 sc->age_cdata.age_smb_block_map);
1278 sc->age_rdata.age_smb_block_paddr = 0;
1279 sc->age_rdata.age_smb_block = NULL;
1280 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag);
1281 sc->age_cdata.age_smb_block_tag = NULL;
1282 }
1283
1284 if (sc->age_cdata.age_buffer_tag != NULL) {
1285 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag);
1286 sc->age_cdata.age_buffer_tag = NULL;
1287 }
1288 if (sc->age_cdata.age_parent_tag != NULL) {
1289 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag);
1290 sc->age_cdata.age_parent_tag = NULL;
1291 }
1292 }
1293
1294 /*
1295 * Make sure the interface is stopped at reboot time.
1296 */
1297 static int
age_shutdown(device_t dev)1298 age_shutdown(device_t dev)
1299 {
1300
1301 return (age_suspend(dev));
1302 }
1303
1304 static void
age_setwol(struct age_softc * sc)1305 age_setwol(struct age_softc *sc)
1306 {
1307 if_t ifp;
1308 struct mii_data *mii;
1309 uint32_t reg, pmcs;
1310 uint16_t pmstat;
1311 int aneg, i, pmc;
1312
1313 AGE_LOCK_ASSERT(sc);
1314
1315 if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) {
1316 CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
1317 /*
1318 * No PME capability, PHY power down.
1319 * XXX
1320 * Due to an unknown reason powering down PHY resulted
1321 * in unexpected results such as inaccessbility of
1322 * hardware of freshly rebooted system. Disable
1323 * powering down PHY until I got more information for
1324 * Attansic/Atheros PHY hardwares.
1325 */
1326 #ifdef notyet
1327 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1328 MII_BMCR, BMCR_PDOWN);
1329 #endif
1330 return;
1331 }
1332
1333 ifp = sc->age_ifp;
1334 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
1335 /*
1336 * Note, this driver resets the link speed to 10/100Mbps with
1337 * auto-negotiation but we don't know whether that operation
1338 * would succeed or not as it have no control after powering
1339 * off. If the renegotiation fail WOL may not work. Running
1340 * at 1Gbps will draw more power than 375mA at 3.3V which is
1341 * specified in PCI specification and that would result in
1342 * complete shutdowning power to ethernet controller.
1343 *
1344 * TODO
1345 * Save current negotiated media speed/duplex/flow-control
1346 * to softc and restore the same link again after resuming.
1347 * PHY handling such as power down/resetting to 100Mbps
1348 * may be better handled in suspend method in phy driver.
1349 */
1350 mii = device_get_softc(sc->age_miibus);
1351 mii_pollstat(mii);
1352 aneg = 0;
1353 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1354 switch IFM_SUBTYPE(mii->mii_media_active) {
1355 case IFM_10_T:
1356 case IFM_100_TX:
1357 goto got_link;
1358 case IFM_1000_T:
1359 aneg++;
1360 default:
1361 break;
1362 }
1363 }
1364 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1365 MII_100T2CR, 0);
1366 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1367 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD |
1368 ANAR_10 | ANAR_CSMA);
1369 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1370 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1371 DELAY(1000);
1372 if (aneg != 0) {
1373 /* Poll link state until age(4) get a 10/100 link. */
1374 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1375 mii_pollstat(mii);
1376 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1377 switch (IFM_SUBTYPE(
1378 mii->mii_media_active)) {
1379 case IFM_10_T:
1380 case IFM_100_TX:
1381 age_mac_config(sc);
1382 goto got_link;
1383 default:
1384 break;
1385 }
1386 }
1387 AGE_UNLOCK(sc);
1388 pause("agelnk", hz);
1389 AGE_LOCK(sc);
1390 }
1391 if (i == MII_ANEGTICKS_GIGE)
1392 device_printf(sc->age_dev,
1393 "establishing link failed, "
1394 "WOL may not work!");
1395 }
1396 /*
1397 * No link, force MAC to have 100Mbps, full-duplex link.
1398 * This is the last resort and may/may not work.
1399 */
1400 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1401 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1402 age_mac_config(sc);
1403 }
1404
1405 got_link:
1406 pmcs = 0;
1407 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
1408 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1409 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs);
1410 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1411 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC);
1412 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST);
1413 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0)
1414 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1415 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
1416 reg |= MAC_CFG_RX_ENB;
1417 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1418 }
1419
1420 /* Request PME. */
1421 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2);
1422 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1423 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
1424 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1425 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1426 #ifdef notyet
1427 /* See above for powering down PHY issues. */
1428 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) {
1429 /* No WOL, PHY power down. */
1430 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1431 MII_BMCR, BMCR_PDOWN);
1432 }
1433 #endif
1434 }
1435
1436 static int
age_suspend(device_t dev)1437 age_suspend(device_t dev)
1438 {
1439 struct age_softc *sc;
1440
1441 sc = device_get_softc(dev);
1442
1443 AGE_LOCK(sc);
1444 age_stop(sc);
1445 age_setwol(sc);
1446 AGE_UNLOCK(sc);
1447
1448 return (0);
1449 }
1450
1451 static int
age_resume(device_t dev)1452 age_resume(device_t dev)
1453 {
1454 struct age_softc *sc;
1455 if_t ifp;
1456
1457 sc = device_get_softc(dev);
1458
1459 AGE_LOCK(sc);
1460 age_phy_reset(sc);
1461 ifp = sc->age_ifp;
1462 if ((if_getflags(ifp) & IFF_UP) != 0)
1463 age_init_locked(sc);
1464
1465 AGE_UNLOCK(sc);
1466
1467 return (0);
1468 }
1469
1470 static int
age_encap(struct age_softc * sc,struct mbuf ** m_head)1471 age_encap(struct age_softc *sc, struct mbuf **m_head)
1472 {
1473 struct age_txdesc *txd, *txd_last;
1474 struct tx_desc *desc;
1475 struct mbuf *m;
1476 struct ip *ip;
1477 struct tcphdr *tcp;
1478 bus_dma_segment_t txsegs[AGE_MAXTXSEGS];
1479 bus_dmamap_t map;
1480 uint32_t cflags, hdrlen, ip_off, poff, vtag;
1481 int error, i, nsegs, prod, si;
1482
1483 AGE_LOCK_ASSERT(sc);
1484
1485 M_ASSERTPKTHDR((*m_head));
1486
1487 m = *m_head;
1488 ip = NULL;
1489 tcp = NULL;
1490 cflags = vtag = 0;
1491 ip_off = poff = 0;
1492 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1493 /*
1494 * L1 requires offset of TCP/UDP payload in its Tx
1495 * descriptor to perform hardware Tx checksum offload.
1496 * Additionally, TSO requires IP/TCP header size and
1497 * modification of IP/TCP header in order to make TSO
1498 * engine work. This kind of operation takes many CPU
1499 * cycles on FreeBSD so fast host CPU is needed to get
1500 * smooth TSO performance.
1501 */
1502 struct ether_header *eh;
1503
1504 if (M_WRITABLE(m) == 0) {
1505 /* Get a writable copy. */
1506 m = m_dup(*m_head, M_NOWAIT);
1507 /* Release original mbufs. */
1508 m_freem(*m_head);
1509 if (m == NULL) {
1510 *m_head = NULL;
1511 return (ENOBUFS);
1512 }
1513 *m_head = m;
1514 }
1515 ip_off = sizeof(struct ether_header);
1516 m = m_pullup(m, ip_off);
1517 if (m == NULL) {
1518 *m_head = NULL;
1519 return (ENOBUFS);
1520 }
1521 eh = mtod(m, struct ether_header *);
1522 /*
1523 * Check if hardware VLAN insertion is off.
1524 * Additional check for LLC/SNAP frame?
1525 */
1526 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1527 ip_off = sizeof(struct ether_vlan_header);
1528 m = m_pullup(m, ip_off);
1529 if (m == NULL) {
1530 *m_head = NULL;
1531 return (ENOBUFS);
1532 }
1533 }
1534 m = m_pullup(m, ip_off + sizeof(struct ip));
1535 if (m == NULL) {
1536 *m_head = NULL;
1537 return (ENOBUFS);
1538 }
1539 ip = (struct ip *)(mtod(m, char *) + ip_off);
1540 poff = ip_off + (ip->ip_hl << 2);
1541 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1542 m = m_pullup(m, poff + sizeof(struct tcphdr));
1543 if (m == NULL) {
1544 *m_head = NULL;
1545 return (ENOBUFS);
1546 }
1547 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1548 m = m_pullup(m, poff + (tcp->th_off << 2));
1549 if (m == NULL) {
1550 *m_head = NULL;
1551 return (ENOBUFS);
1552 }
1553 /*
1554 * L1 requires IP/TCP header size and offset as
1555 * well as TCP pseudo checksum which complicates
1556 * TSO configuration. I guess this comes from the
1557 * adherence to Microsoft NDIS Large Send
1558 * specification which requires insertion of
1559 * pseudo checksum by upper stack. The pseudo
1560 * checksum that NDIS refers to doesn't include
1561 * TCP payload length so age(4) should recompute
1562 * the pseudo checksum here. Hopefully this wouldn't
1563 * be much burden on modern CPUs.
1564 * Reset IP checksum and recompute TCP pseudo
1565 * checksum as NDIS specification said.
1566 */
1567 ip = (struct ip *)(mtod(m, char *) + ip_off);
1568 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1569 ip->ip_sum = 0;
1570 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1571 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1572 }
1573 *m_head = m;
1574 }
1575
1576 si = prod = sc->age_cdata.age_tx_prod;
1577 txd = &sc->age_cdata.age_txdesc[prod];
1578 txd_last = txd;
1579 map = txd->tx_dmamap;
1580
1581 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1582 *m_head, txsegs, &nsegs, 0);
1583 if (error == EFBIG) {
1584 m = m_collapse(*m_head, M_NOWAIT, AGE_MAXTXSEGS);
1585 if (m == NULL) {
1586 m_freem(*m_head);
1587 *m_head = NULL;
1588 return (ENOMEM);
1589 }
1590 *m_head = m;
1591 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1592 *m_head, txsegs, &nsegs, 0);
1593 if (error != 0) {
1594 m_freem(*m_head);
1595 *m_head = NULL;
1596 return (error);
1597 }
1598 } else if (error != 0)
1599 return (error);
1600 if (nsegs == 0) {
1601 m_freem(*m_head);
1602 *m_head = NULL;
1603 return (EIO);
1604 }
1605
1606 /* Check descriptor overrun. */
1607 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) {
1608 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map);
1609 return (ENOBUFS);
1610 }
1611
1612 m = *m_head;
1613 /* Configure VLAN hardware tag insertion. */
1614 if ((m->m_flags & M_VLANTAG) != 0) {
1615 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1616 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK);
1617 cflags |= AGE_TD_INSERT_VLAN_TAG;
1618 }
1619
1620 desc = NULL;
1621 i = 0;
1622 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1623 /* Request TSO and set MSS. */
1624 cflags |= AGE_TD_TSO_IPV4;
1625 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM;
1626 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz <<
1627 AGE_TD_TSO_MSS_SHIFT);
1628 /* Set IP/TCP header size. */
1629 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT;
1630 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT;
1631 /*
1632 * L1 requires the first buffer should only hold IP/TCP
1633 * header data. TCP payload should be handled in other
1634 * descriptors.
1635 */
1636 hdrlen = poff + (tcp->th_off << 2);
1637 desc = &sc->age_rdata.age_tx_ring[prod];
1638 desc->addr = htole64(txsegs[0].ds_addr);
1639 desc->len = htole32(AGE_TX_BYTES(hdrlen) | vtag);
1640 desc->flags = htole32(cflags);
1641 sc->age_cdata.age_tx_cnt++;
1642 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1643 if (m->m_len - hdrlen > 0) {
1644 /* Handle remaining payload of the 1st fragment. */
1645 desc = &sc->age_rdata.age_tx_ring[prod];
1646 desc->addr = htole64(txsegs[0].ds_addr + hdrlen);
1647 desc->len = htole32(AGE_TX_BYTES(m->m_len - hdrlen) |
1648 vtag);
1649 desc->flags = htole32(cflags);
1650 sc->age_cdata.age_tx_cnt++;
1651 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1652 }
1653 /* Handle remaining fragments. */
1654 i = 1;
1655 } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) {
1656 /* Configure Tx IP/TCP/UDP checksum offload. */
1657 cflags |= AGE_TD_CSUM;
1658 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1659 cflags |= AGE_TD_TCPCSUM;
1660 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1661 cflags |= AGE_TD_UDPCSUM;
1662 /* Set checksum start offset. */
1663 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT);
1664 /* Set checksum insertion position of TCP/UDP. */
1665 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1666 AGE_TD_CSUM_XSUMOFFSET_SHIFT);
1667 }
1668 for (; i < nsegs; i++) {
1669 desc = &sc->age_rdata.age_tx_ring[prod];
1670 desc->addr = htole64(txsegs[i].ds_addr);
1671 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag);
1672 desc->flags = htole32(cflags);
1673 sc->age_cdata.age_tx_cnt++;
1674 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1675 }
1676 /* Update producer index. */
1677 sc->age_cdata.age_tx_prod = prod;
1678
1679 /* Set EOP on the last descriptor. */
1680 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT;
1681 desc = &sc->age_rdata.age_tx_ring[prod];
1682 desc->flags |= htole32(AGE_TD_EOP);
1683
1684 /* Lastly set TSO header and modify IP/TCP header for TSO operation. */
1685 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1686 desc = &sc->age_rdata.age_tx_ring[si];
1687 desc->flags |= htole32(AGE_TD_TSO_HDR);
1688 }
1689
1690 /* Swap dmamap of the first and the last. */
1691 txd = &sc->age_cdata.age_txdesc[prod];
1692 map = txd_last->tx_dmamap;
1693 txd_last->tx_dmamap = txd->tx_dmamap;
1694 txd->tx_dmamap = map;
1695 txd->tx_m = m;
1696
1697 /* Sync descriptors. */
1698 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE);
1699 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
1700 sc->age_cdata.age_tx_ring_map,
1701 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1702
1703 return (0);
1704 }
1705
1706 static void
age_start(if_t ifp)1707 age_start(if_t ifp)
1708 {
1709 struct age_softc *sc;
1710
1711 sc = if_getsoftc(ifp);
1712 AGE_LOCK(sc);
1713 age_start_locked(ifp);
1714 AGE_UNLOCK(sc);
1715 }
1716
1717 static void
age_start_locked(if_t ifp)1718 age_start_locked(if_t ifp)
1719 {
1720 struct age_softc *sc;
1721 struct mbuf *m_head;
1722 int enq;
1723
1724 sc = if_getsoftc(ifp);
1725
1726 AGE_LOCK_ASSERT(sc);
1727
1728 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1729 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0)
1730 return;
1731
1732 for (enq = 0; !if_sendq_empty(ifp); ) {
1733 m_head = if_dequeue(ifp);
1734 if (m_head == NULL)
1735 break;
1736 /*
1737 * Pack the data into the transmit ring. If we
1738 * don't have room, set the OACTIVE flag and wait
1739 * for the NIC to drain the ring.
1740 */
1741 if (age_encap(sc, &m_head)) {
1742 if (m_head == NULL)
1743 break;
1744 if_sendq_prepend(ifp, m_head);
1745 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1746 break;
1747 }
1748
1749 enq++;
1750 /*
1751 * If there's a BPF listener, bounce a copy of this frame
1752 * to him.
1753 */
1754 ETHER_BPF_MTAP(ifp, m_head);
1755 }
1756
1757 if (enq > 0) {
1758 /* Update mbox. */
1759 AGE_COMMIT_MBOX(sc);
1760 /* Set a timeout in case the chip goes out to lunch. */
1761 sc->age_watchdog_timer = AGE_TX_TIMEOUT;
1762 }
1763 }
1764
1765 static void
age_watchdog(struct age_softc * sc)1766 age_watchdog(struct age_softc *sc)
1767 {
1768 if_t ifp;
1769
1770 AGE_LOCK_ASSERT(sc);
1771
1772 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer)
1773 return;
1774
1775 ifp = sc->age_ifp;
1776 if ((sc->age_flags & AGE_FLAG_LINK) == 0) {
1777 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n");
1778 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1779 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1780 age_init_locked(sc);
1781 return;
1782 }
1783 if (sc->age_cdata.age_tx_cnt == 0) {
1784 if_printf(sc->age_ifp,
1785 "watchdog timeout (missed Tx interrupts) -- recovering\n");
1786 if (!if_sendq_empty(ifp))
1787 age_start_locked(ifp);
1788 return;
1789 }
1790 if_printf(sc->age_ifp, "watchdog timeout\n");
1791 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1792 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1793 age_init_locked(sc);
1794 if (!if_sendq_empty(ifp))
1795 age_start_locked(ifp);
1796 }
1797
1798 static int
age_ioctl(if_t ifp,u_long cmd,caddr_t data)1799 age_ioctl(if_t ifp, u_long cmd, caddr_t data)
1800 {
1801 struct age_softc *sc;
1802 struct ifreq *ifr;
1803 struct mii_data *mii;
1804 uint32_t reg;
1805 int error, mask;
1806
1807 sc = if_getsoftc(ifp);
1808 ifr = (struct ifreq *)data;
1809 error = 0;
1810 switch (cmd) {
1811 case SIOCSIFMTU:
1812 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU)
1813 error = EINVAL;
1814 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
1815 AGE_LOCK(sc);
1816 if_setmtu(ifp, ifr->ifr_mtu);
1817 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1818 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1819 age_init_locked(sc);
1820 }
1821 AGE_UNLOCK(sc);
1822 }
1823 break;
1824 case SIOCSIFFLAGS:
1825 AGE_LOCK(sc);
1826 if ((if_getflags(ifp) & IFF_UP) != 0) {
1827 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1828 if (((if_getflags(ifp) ^ sc->age_if_flags)
1829 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1830 age_rxfilter(sc);
1831 } else {
1832 if ((sc->age_flags & AGE_FLAG_DETACH) == 0)
1833 age_init_locked(sc);
1834 }
1835 } else {
1836 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1837 age_stop(sc);
1838 }
1839 sc->age_if_flags = if_getflags(ifp);
1840 AGE_UNLOCK(sc);
1841 break;
1842 case SIOCADDMULTI:
1843 case SIOCDELMULTI:
1844 AGE_LOCK(sc);
1845 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1846 age_rxfilter(sc);
1847 AGE_UNLOCK(sc);
1848 break;
1849 case SIOCSIFMEDIA:
1850 case SIOCGIFMEDIA:
1851 mii = device_get_softc(sc->age_miibus);
1852 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1853 break;
1854 case SIOCSIFCAP:
1855 AGE_LOCK(sc);
1856 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1857 if ((mask & IFCAP_TXCSUM) != 0 &&
1858 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
1859 if_togglecapenable(ifp, IFCAP_TXCSUM);
1860 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1861 if_sethwassistbits(ifp, AGE_CSUM_FEATURES, 0);
1862 else
1863 if_sethwassistbits(ifp, 0, AGE_CSUM_FEATURES);
1864 }
1865 if ((mask & IFCAP_RXCSUM) != 0 &&
1866 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {
1867 if_togglecapenable(ifp, IFCAP_RXCSUM);
1868 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1869 reg &= ~MAC_CFG_RXCSUM_ENB;
1870 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
1871 reg |= MAC_CFG_RXCSUM_ENB;
1872 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1873 }
1874 if ((mask & IFCAP_TSO4) != 0 &&
1875 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
1876 if_togglecapenable(ifp, IFCAP_TSO4);
1877 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
1878 if_sethwassistbits(ifp, CSUM_TSO, 0);
1879 else
1880 if_sethwassistbits(ifp, 0, CSUM_TSO);
1881 }
1882
1883 if ((mask & IFCAP_WOL_MCAST) != 0 &&
1884 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0)
1885 if_togglecapenable(ifp, IFCAP_WOL_MCAST);
1886 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1887 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
1888 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
1889 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1890 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
1891 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
1892 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1893 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
1894 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
1895 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1896 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
1897 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
1898 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
1899 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
1900 age_rxvlan(sc);
1901 }
1902 AGE_UNLOCK(sc);
1903 VLAN_CAPABILITIES(ifp);
1904 break;
1905 default:
1906 error = ether_ioctl(ifp, cmd, data);
1907 break;
1908 }
1909
1910 return (error);
1911 }
1912
1913 static void
age_mac_config(struct age_softc * sc)1914 age_mac_config(struct age_softc *sc)
1915 {
1916 struct mii_data *mii;
1917 uint32_t reg;
1918
1919 AGE_LOCK_ASSERT(sc);
1920
1921 mii = device_get_softc(sc->age_miibus);
1922 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1923 reg &= ~MAC_CFG_FULL_DUPLEX;
1924 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC);
1925 reg &= ~MAC_CFG_SPEED_MASK;
1926 /* Reprogram MAC with resolved speed/duplex. */
1927 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1928 case IFM_10_T:
1929 case IFM_100_TX:
1930 reg |= MAC_CFG_SPEED_10_100;
1931 break;
1932 case IFM_1000_T:
1933 reg |= MAC_CFG_SPEED_1000;
1934 break;
1935 }
1936 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1937 reg |= MAC_CFG_FULL_DUPLEX;
1938 #ifdef notyet
1939 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1940 reg |= MAC_CFG_TX_FC;
1941 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1942 reg |= MAC_CFG_RX_FC;
1943 #endif
1944 }
1945
1946 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1947 }
1948
1949 static void
age_link_task(void * arg,int pending)1950 age_link_task(void *arg, int pending)
1951 {
1952 struct age_softc *sc;
1953 struct mii_data *mii;
1954 if_t ifp;
1955 uint32_t reg;
1956
1957 sc = (struct age_softc *)arg;
1958
1959 AGE_LOCK(sc);
1960 mii = device_get_softc(sc->age_miibus);
1961 ifp = sc->age_ifp;
1962 if (mii == NULL || ifp == NULL ||
1963 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
1964 AGE_UNLOCK(sc);
1965 return;
1966 }
1967
1968 sc->age_flags &= ~AGE_FLAG_LINK;
1969 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1970 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1971 case IFM_10_T:
1972 case IFM_100_TX:
1973 case IFM_1000_T:
1974 sc->age_flags |= AGE_FLAG_LINK;
1975 break;
1976 default:
1977 break;
1978 }
1979 }
1980
1981 /* Stop Rx/Tx MACs. */
1982 age_stop_rxmac(sc);
1983 age_stop_txmac(sc);
1984
1985 /* Program MACs with resolved speed/duplex/flow-control. */
1986 if ((sc->age_flags & AGE_FLAG_LINK) != 0) {
1987 age_mac_config(sc);
1988 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1989 /* Restart DMA engine and Tx/Rx MAC. */
1990 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
1991 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB);
1992 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
1993 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1994 }
1995
1996 AGE_UNLOCK(sc);
1997 }
1998
1999 static void
age_stats_update(struct age_softc * sc)2000 age_stats_update(struct age_softc *sc)
2001 {
2002 struct age_stats *stat;
2003 struct smb *smb;
2004 if_t ifp;
2005
2006 AGE_LOCK_ASSERT(sc);
2007
2008 stat = &sc->age_stat;
2009
2010 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2011 sc->age_cdata.age_smb_block_map,
2012 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2013
2014 smb = sc->age_rdata.age_smb_block;
2015 if (smb->updated == 0)
2016 return;
2017
2018 ifp = sc->age_ifp;
2019 /* Rx stats. */
2020 stat->rx_frames += smb->rx_frames;
2021 stat->rx_bcast_frames += smb->rx_bcast_frames;
2022 stat->rx_mcast_frames += smb->rx_mcast_frames;
2023 stat->rx_pause_frames += smb->rx_pause_frames;
2024 stat->rx_control_frames += smb->rx_control_frames;
2025 stat->rx_crcerrs += smb->rx_crcerrs;
2026 stat->rx_lenerrs += smb->rx_lenerrs;
2027 stat->rx_bytes += smb->rx_bytes;
2028 stat->rx_runts += smb->rx_runts;
2029 stat->rx_fragments += smb->rx_fragments;
2030 stat->rx_pkts_64 += smb->rx_pkts_64;
2031 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2032 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2033 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2034 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2035 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2036 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2037 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2038 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2039 stat->rx_desc_oflows += smb->rx_desc_oflows;
2040 stat->rx_alignerrs += smb->rx_alignerrs;
2041 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2042 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2043 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2044
2045 /* Tx stats. */
2046 stat->tx_frames += smb->tx_frames;
2047 stat->tx_bcast_frames += smb->tx_bcast_frames;
2048 stat->tx_mcast_frames += smb->tx_mcast_frames;
2049 stat->tx_pause_frames += smb->tx_pause_frames;
2050 stat->tx_excess_defer += smb->tx_excess_defer;
2051 stat->tx_control_frames += smb->tx_control_frames;
2052 stat->tx_deferred += smb->tx_deferred;
2053 stat->tx_bytes += smb->tx_bytes;
2054 stat->tx_pkts_64 += smb->tx_pkts_64;
2055 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2056 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2057 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2058 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2059 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2060 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2061 stat->tx_single_colls += smb->tx_single_colls;
2062 stat->tx_multi_colls += smb->tx_multi_colls;
2063 stat->tx_late_colls += smb->tx_late_colls;
2064 stat->tx_excess_colls += smb->tx_excess_colls;
2065 stat->tx_underrun += smb->tx_underrun;
2066 stat->tx_desc_underrun += smb->tx_desc_underrun;
2067 stat->tx_lenerrs += smb->tx_lenerrs;
2068 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2069 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2070 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2071
2072 /* Update counters in ifnet. */
2073 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames);
2074
2075 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls +
2076 smb->tx_multi_colls + smb->tx_late_colls +
2077 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT);
2078
2079 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_excess_colls +
2080 smb->tx_late_colls + smb->tx_underrun +
2081 smb->tx_pkts_truncated);
2082
2083 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames);
2084
2085 if_inc_counter(ifp, IFCOUNTER_IERRORS, smb->rx_crcerrs +
2086 smb->rx_lenerrs + smb->rx_runts + smb->rx_pkts_truncated +
2087 smb->rx_fifo_oflows + smb->rx_desc_oflows +
2088 smb->rx_alignerrs);
2089
2090 /* Update done, clear. */
2091 smb->updated = 0;
2092
2093 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2094 sc->age_cdata.age_smb_block_map,
2095 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2096 }
2097
2098 static int
age_intr(void * arg)2099 age_intr(void *arg)
2100 {
2101 struct age_softc *sc;
2102 uint32_t status;
2103
2104 sc = (struct age_softc *)arg;
2105
2106 status = CSR_READ_4(sc, AGE_INTR_STATUS);
2107 if (status == 0 || (status & AGE_INTRS) == 0)
2108 return (FILTER_STRAY);
2109 /* Disable interrupts. */
2110 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT);
2111 taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2112
2113 return (FILTER_HANDLED);
2114 }
2115
2116 static void
age_int_task(void * arg,int pending)2117 age_int_task(void *arg, int pending)
2118 {
2119 struct age_softc *sc;
2120 if_t ifp;
2121 struct cmb *cmb;
2122 uint32_t status;
2123
2124 sc = (struct age_softc *)arg;
2125
2126 AGE_LOCK(sc);
2127
2128 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2129 sc->age_cdata.age_cmb_block_map,
2130 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2131 cmb = sc->age_rdata.age_cmb_block;
2132 status = le32toh(cmb->intr_status);
2133 if (sc->age_morework != 0)
2134 status |= INTR_CMB_RX;
2135 if ((status & AGE_INTRS) == 0)
2136 goto done;
2137
2138 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >>
2139 TPD_CONS_SHIFT;
2140 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >>
2141 RRD_PROD_SHIFT;
2142 /* Let hardware know CMB was served. */
2143 cmb->intr_status = 0;
2144 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2145 sc->age_cdata.age_cmb_block_map,
2146 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2147
2148 ifp = sc->age_ifp;
2149 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2150 if ((status & INTR_CMB_RX) != 0)
2151 sc->age_morework = age_rxintr(sc, sc->age_rr_prod,
2152 sc->age_process_limit);
2153 if ((status & INTR_CMB_TX) != 0)
2154 age_txintr(sc, sc->age_tpd_cons);
2155 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2156 if ((status & INTR_DMA_RD_TO_RST) != 0)
2157 device_printf(sc->age_dev,
2158 "DMA read error! -- resetting\n");
2159 if ((status & INTR_DMA_WR_TO_RST) != 0)
2160 device_printf(sc->age_dev,
2161 "DMA write error! -- resetting\n");
2162 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2163 age_init_locked(sc);
2164 }
2165 if (!if_sendq_empty(ifp))
2166 age_start_locked(ifp);
2167 if ((status & INTR_SMB) != 0)
2168 age_stats_update(sc);
2169 }
2170
2171 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */
2172 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2173 sc->age_cdata.age_cmb_block_map,
2174 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2175 status = le32toh(cmb->intr_status);
2176 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) {
2177 taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2178 AGE_UNLOCK(sc);
2179 return;
2180 }
2181
2182 done:
2183 /* Re-enable interrupts. */
2184 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2185 AGE_UNLOCK(sc);
2186 }
2187
2188 static void
age_txintr(struct age_softc * sc,int tpd_cons)2189 age_txintr(struct age_softc *sc, int tpd_cons)
2190 {
2191 if_t ifp;
2192 struct age_txdesc *txd;
2193 int cons, prog;
2194
2195 AGE_LOCK_ASSERT(sc);
2196
2197 ifp = sc->age_ifp;
2198
2199 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2200 sc->age_cdata.age_tx_ring_map,
2201 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2202
2203 /*
2204 * Go through our Tx list and free mbufs for those
2205 * frames which have been transmitted.
2206 */
2207 cons = sc->age_cdata.age_tx_cons;
2208 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) {
2209 if (sc->age_cdata.age_tx_cnt <= 0)
2210 break;
2211 prog++;
2212 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2213 sc->age_cdata.age_tx_cnt--;
2214 txd = &sc->age_cdata.age_txdesc[cons];
2215 /*
2216 * Clear Tx descriptors, it's not required but would
2217 * help debugging in case of Tx issues.
2218 */
2219 txd->tx_desc->addr = 0;
2220 txd->tx_desc->len = 0;
2221 txd->tx_desc->flags = 0;
2222
2223 if (txd->tx_m == NULL)
2224 continue;
2225 /* Reclaim transmitted mbufs. */
2226 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap,
2227 BUS_DMASYNC_POSTWRITE);
2228 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap);
2229 m_freem(txd->tx_m);
2230 txd->tx_m = NULL;
2231 }
2232
2233 if (prog > 0) {
2234 sc->age_cdata.age_tx_cons = cons;
2235
2236 /*
2237 * Unarm watchdog timer only when there are no pending
2238 * Tx descriptors in queue.
2239 */
2240 if (sc->age_cdata.age_tx_cnt == 0)
2241 sc->age_watchdog_timer = 0;
2242 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2243 sc->age_cdata.age_tx_ring_map,
2244 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2245 }
2246 }
2247
2248 #ifndef __NO_STRICT_ALIGNMENT
2249 static struct mbuf *
age_fixup_rx(if_t ifp,struct mbuf * m)2250 age_fixup_rx(if_t ifp, struct mbuf *m)
2251 {
2252 struct mbuf *n;
2253 int i;
2254 uint16_t *src, *dst;
2255
2256 src = mtod(m, uint16_t *);
2257 dst = src - 3;
2258
2259 if (m->m_next == NULL) {
2260 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
2261 *dst++ = *src++;
2262 m->m_data -= 6;
2263 return (m);
2264 }
2265 /*
2266 * Append a new mbuf to received mbuf chain and copy ethernet
2267 * header from the mbuf chain. This can save lots of CPU
2268 * cycles for jumbo frame.
2269 */
2270 MGETHDR(n, M_NOWAIT, MT_DATA);
2271 if (n == NULL) {
2272 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2273 m_freem(m);
2274 return (NULL);
2275 }
2276 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
2277 m->m_data += ETHER_HDR_LEN;
2278 m->m_len -= ETHER_HDR_LEN;
2279 n->m_len = ETHER_HDR_LEN;
2280 M_MOVE_PKTHDR(n, m);
2281 n->m_next = m;
2282 return (n);
2283 }
2284 #endif
2285
2286 /* Receive a frame. */
2287 static void
age_rxeof(struct age_softc * sc,struct rx_rdesc * rxrd)2288 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd)
2289 {
2290 struct age_rxdesc *rxd;
2291 if_t ifp;
2292 struct mbuf *mp, *m;
2293 uint32_t status, index, vtag;
2294 int count, nsegs;
2295 int rx_cons;
2296
2297 AGE_LOCK_ASSERT(sc);
2298
2299 ifp = sc->age_ifp;
2300 status = le32toh(rxrd->flags);
2301 index = le32toh(rxrd->index);
2302 rx_cons = AGE_RX_CONS(index);
2303 nsegs = AGE_RX_NSEGS(index);
2304
2305 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len));
2306 if ((status & (AGE_RRD_ERROR | AGE_RRD_LENGTH_NOK)) != 0) {
2307 /*
2308 * We want to pass the following frames to upper
2309 * layer regardless of error status of Rx return
2310 * ring.
2311 *
2312 * o IP/TCP/UDP checksum is bad.
2313 * o frame length and protocol specific length
2314 * does not match.
2315 */
2316 status |= AGE_RRD_IPCSUM_NOK | AGE_RRD_TCP_UDPCSUM_NOK;
2317 if ((status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE |
2318 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0)
2319 return;
2320 }
2321
2322 for (count = 0; count < nsegs; count++,
2323 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) {
2324 rxd = &sc->age_cdata.age_rxdesc[rx_cons];
2325 mp = rxd->rx_m;
2326 /* Add a new receive buffer to the ring. */
2327 if (age_newbuf(sc, rxd) != 0) {
2328 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2329 /* Reuse Rx buffers. */
2330 if (sc->age_cdata.age_rxhead != NULL)
2331 m_freem(sc->age_cdata.age_rxhead);
2332 break;
2333 }
2334
2335 /*
2336 * Assume we've received a full sized frame.
2337 * Actual size is fixed when we encounter the end of
2338 * multi-segmented frame.
2339 */
2340 mp->m_len = AGE_RX_BUF_SIZE;
2341
2342 /* Chain received mbufs. */
2343 if (sc->age_cdata.age_rxhead == NULL) {
2344 sc->age_cdata.age_rxhead = mp;
2345 sc->age_cdata.age_rxtail = mp;
2346 } else {
2347 mp->m_flags &= ~M_PKTHDR;
2348 sc->age_cdata.age_rxprev_tail =
2349 sc->age_cdata.age_rxtail;
2350 sc->age_cdata.age_rxtail->m_next = mp;
2351 sc->age_cdata.age_rxtail = mp;
2352 }
2353
2354 if (count == nsegs - 1) {
2355 /* Last desc. for this frame. */
2356 m = sc->age_cdata.age_rxhead;
2357 m->m_flags |= M_PKTHDR;
2358 /*
2359 * It seems that L1 controller has no way
2360 * to tell hardware to strip CRC bytes.
2361 */
2362 m->m_pkthdr.len = sc->age_cdata.age_rxlen -
2363 ETHER_CRC_LEN;
2364 if (nsegs > 1) {
2365 /* Set last mbuf size. */
2366 mp->m_len = sc->age_cdata.age_rxlen -
2367 ((nsegs - 1) * AGE_RX_BUF_SIZE);
2368 /* Remove the CRC bytes in chained mbufs. */
2369 if (mp->m_len <= ETHER_CRC_LEN) {
2370 sc->age_cdata.age_rxtail =
2371 sc->age_cdata.age_rxprev_tail;
2372 sc->age_cdata.age_rxtail->m_len -=
2373 (ETHER_CRC_LEN - mp->m_len);
2374 sc->age_cdata.age_rxtail->m_next = NULL;
2375 m_freem(mp);
2376 } else {
2377 mp->m_len -= ETHER_CRC_LEN;
2378 }
2379 } else
2380 m->m_len = m->m_pkthdr.len;
2381 m->m_pkthdr.rcvif = ifp;
2382 /*
2383 * Set checksum information.
2384 * It seems that L1 controller can compute partial
2385 * checksum. The partial checksum value can be used
2386 * to accelerate checksum computation for fragmented
2387 * TCP/UDP packets. Upper network stack already
2388 * takes advantage of the partial checksum value in
2389 * IP reassembly stage. But I'm not sure the
2390 * correctness of the partial hardware checksum
2391 * assistance due to lack of data sheet. If it is
2392 * proven to work on L1 I'll enable it.
2393 */
2394 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 &&
2395 (status & AGE_RRD_IPV4) != 0) {
2396 if ((status & AGE_RRD_IPCSUM_NOK) == 0)
2397 m->m_pkthdr.csum_flags |=
2398 CSUM_IP_CHECKED | CSUM_IP_VALID;
2399 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) &&
2400 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) {
2401 m->m_pkthdr.csum_flags |=
2402 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2403 m->m_pkthdr.csum_data = 0xffff;
2404 }
2405 /*
2406 * Don't mark bad checksum for TCP/UDP frames
2407 * as fragmented frames may always have set
2408 * bad checksummed bit of descriptor status.
2409 */
2410 }
2411
2412 /* Check for VLAN tagged frames. */
2413 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 &&
2414 (status & AGE_RRD_VLAN) != 0) {
2415 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags));
2416 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag);
2417 m->m_flags |= M_VLANTAG;
2418 }
2419 #ifndef __NO_STRICT_ALIGNMENT
2420 m = age_fixup_rx(ifp, m);
2421 if (m != NULL)
2422 #endif
2423 {
2424 /* Pass it on. */
2425 AGE_UNLOCK(sc);
2426 if_input(ifp, m);
2427 AGE_LOCK(sc);
2428 }
2429 }
2430 }
2431
2432 /* Reset mbuf chains. */
2433 AGE_RXCHAIN_RESET(sc);
2434 }
2435
2436 static int
age_rxintr(struct age_softc * sc,int rr_prod,int count)2437 age_rxintr(struct age_softc *sc, int rr_prod, int count)
2438 {
2439 struct rx_rdesc *rxrd;
2440 int rr_cons, nsegs, pktlen, prog;
2441
2442 AGE_LOCK_ASSERT(sc);
2443
2444 rr_cons = sc->age_cdata.age_rr_cons;
2445 if (rr_cons == rr_prod)
2446 return (0);
2447
2448 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2449 sc->age_cdata.age_rr_ring_map,
2450 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2451 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2452 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE);
2453
2454 for (prog = 0; rr_cons != rr_prod; prog++) {
2455 if (count-- <= 0)
2456 break;
2457 rxrd = &sc->age_rdata.age_rr_ring[rr_cons];
2458 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index));
2459 if (nsegs == 0)
2460 break;
2461 /*
2462 * Check number of segments against received bytes.
2463 * Non-matching value would indicate that hardware
2464 * is still trying to update Rx return descriptors.
2465 * I'm not sure whether this check is really needed.
2466 */
2467 pktlen = AGE_RX_BYTES(le32toh(rxrd->len));
2468 if (nsegs != howmany(pktlen, AGE_RX_BUF_SIZE))
2469 break;
2470
2471 /* Received a frame. */
2472 age_rxeof(sc, rxrd);
2473 /* Clear return ring. */
2474 rxrd->index = 0;
2475 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT);
2476 sc->age_cdata.age_rx_cons += nsegs;
2477 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT;
2478 }
2479
2480 if (prog > 0) {
2481 /* Update the consumer index. */
2482 sc->age_cdata.age_rr_cons = rr_cons;
2483
2484 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2485 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE);
2486 /* Sync descriptors. */
2487 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2488 sc->age_cdata.age_rr_ring_map,
2489 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2490
2491 /* Notify hardware availability of new Rx buffers. */
2492 AGE_COMMIT_MBOX(sc);
2493 }
2494
2495 return (count > 0 ? 0 : EAGAIN);
2496 }
2497
2498 static void
age_tick(void * arg)2499 age_tick(void *arg)
2500 {
2501 struct age_softc *sc;
2502 struct mii_data *mii;
2503
2504 sc = (struct age_softc *)arg;
2505
2506 AGE_LOCK_ASSERT(sc);
2507
2508 mii = device_get_softc(sc->age_miibus);
2509 mii_tick(mii);
2510 age_watchdog(sc);
2511 callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2512 }
2513
2514 static void
age_reset(struct age_softc * sc)2515 age_reset(struct age_softc *sc)
2516 {
2517 uint32_t reg;
2518 int i;
2519
2520 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET);
2521 CSR_READ_4(sc, AGE_MASTER_CFG);
2522 DELAY(1000);
2523 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2524 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2525 break;
2526 DELAY(10);
2527 }
2528
2529 if (i == 0)
2530 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg);
2531 /* Initialize PCIe module. From Linux. */
2532 CSR_WRITE_4(sc, 0x12FC, 0x6500);
2533 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2534 }
2535
2536 static void
age_init(void * xsc)2537 age_init(void *xsc)
2538 {
2539 struct age_softc *sc;
2540
2541 sc = (struct age_softc *)xsc;
2542 AGE_LOCK(sc);
2543 age_init_locked(sc);
2544 AGE_UNLOCK(sc);
2545 }
2546
2547 static void
age_init_locked(struct age_softc * sc)2548 age_init_locked(struct age_softc *sc)
2549 {
2550 if_t ifp;
2551 struct mii_data *mii;
2552 uint8_t eaddr[ETHER_ADDR_LEN];
2553 bus_addr_t paddr;
2554 uint32_t reg, fsize;
2555 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo;
2556 int error;
2557
2558 AGE_LOCK_ASSERT(sc);
2559
2560 ifp = sc->age_ifp;
2561 mii = device_get_softc(sc->age_miibus);
2562
2563 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2564 return;
2565
2566 /*
2567 * Cancel any pending I/O.
2568 */
2569 age_stop(sc);
2570
2571 /*
2572 * Reset the chip to a known state.
2573 */
2574 age_reset(sc);
2575
2576 /* Initialize descriptors. */
2577 error = age_init_rx_ring(sc);
2578 if (error != 0) {
2579 device_printf(sc->age_dev, "no memory for Rx buffers.\n");
2580 age_stop(sc);
2581 return;
2582 }
2583 age_init_rr_ring(sc);
2584 age_init_tx_ring(sc);
2585 age_init_cmb_block(sc);
2586 age_init_smb_block(sc);
2587
2588 /* Reprogram the station address. */
2589 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN);
2590 CSR_WRITE_4(sc, AGE_PAR0,
2591 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2592 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]);
2593
2594 /* Set descriptor base addresses. */
2595 paddr = sc->age_rdata.age_tx_ring_paddr;
2596 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr));
2597 paddr = sc->age_rdata.age_rx_ring_paddr;
2598 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr));
2599 paddr = sc->age_rdata.age_rr_ring_paddr;
2600 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr));
2601 paddr = sc->age_rdata.age_tx_ring_paddr;
2602 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr));
2603 paddr = sc->age_rdata.age_cmb_block_paddr;
2604 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr));
2605 paddr = sc->age_rdata.age_smb_block_paddr;
2606 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr));
2607 /* Set Rx/Rx return descriptor counter. */
2608 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT,
2609 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) &
2610 DESC_RRD_CNT_MASK) |
2611 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK));
2612 /* Set Tx descriptor counter. */
2613 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT,
2614 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK);
2615
2616 /* Tell hardware that we're ready to load descriptors. */
2617 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD);
2618
2619 /*
2620 * Initialize mailbox register.
2621 * Updated producer/consumer index information is exchanged
2622 * through this mailbox register. However Tx producer and
2623 * Rx return consumer/Rx producer are all shared such that
2624 * it's hard to separate code path between Tx and Rx without
2625 * locking. If L1 hardware have a separate mail box register
2626 * for Tx and Rx consumer/producer management we could have
2627 * independent Tx/Rx handler which in turn Rx handler could have
2628 * been run without any locking.
2629 */
2630 AGE_COMMIT_MBOX(sc);
2631
2632 /* Configure IPG/IFG parameters. */
2633 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG,
2634 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) |
2635 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2636 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2637 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK));
2638
2639 /* Set parameters for half-duplex media. */
2640 CSR_WRITE_4(sc, AGE_HDPX_CFG,
2641 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2642 HDPX_CFG_LCOL_MASK) |
2643 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2644 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2645 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2646 HDPX_CFG_ABEBT_MASK) |
2647 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2648 HDPX_CFG_JAMIPG_MASK));
2649
2650 /* Configure interrupt moderation timer. */
2651 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod));
2652 reg = CSR_READ_4(sc, AGE_MASTER_CFG);
2653 reg &= ~MASTER_MTIMER_ENB;
2654 if (AGE_USECS(sc->age_int_mod) == 0)
2655 reg &= ~MASTER_ITIMER_ENB;
2656 else
2657 reg |= MASTER_ITIMER_ENB;
2658 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);
2659 if (bootverbose)
2660 device_printf(sc->age_dev, "interrupt moderation is %d us.\n",
2661 sc->age_int_mod);
2662 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000));
2663
2664 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */
2665 if (if_getmtu(ifp) < ETHERMTU)
2666 sc->age_max_frame_size = ETHERMTU;
2667 else
2668 sc->age_max_frame_size = if_getmtu(ifp);
2669 sc->age_max_frame_size += ETHER_HDR_LEN +
2670 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN;
2671 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size);
2672 /* Configure jumbo frame. */
2673 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t));
2674 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG,
2675 (((fsize / sizeof(uint64_t)) <<
2676 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) |
2677 ((RXQ_JUMBO_CFG_LKAH_DEFAULT <<
2678 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) |
2679 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) &
2680 RXQ_JUMBO_CFG_RRD_TIMER_MASK));
2681
2682 /* Configure flow-control parameters. From Linux. */
2683 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) {
2684 /*
2685 * Magic workaround for old-L1.
2686 * Don't know which hw revision requires this magic.
2687 */
2688 CSR_WRITE_4(sc, 0x12FC, 0x6500);
2689 /*
2690 * Another magic workaround for flow-control mode
2691 * change. From Linux.
2692 */
2693 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2694 }
2695 /*
2696 * TODO
2697 * Should understand pause parameter relationships between FIFO
2698 * size and number of Rx descriptors and Rx return descriptors.
2699 *
2700 * Magic parameters came from Linux.
2701 */
2702 switch (sc->age_chip_rev) {
2703 case 0x8001:
2704 case 0x9001:
2705 case 0x9002:
2706 case 0x9003:
2707 rxf_hi = AGE_RX_RING_CNT / 16;
2708 rxf_lo = (AGE_RX_RING_CNT * 7) / 8;
2709 rrd_hi = (AGE_RR_RING_CNT * 7) / 8;
2710 rrd_lo = AGE_RR_RING_CNT / 16;
2711 break;
2712 default:
2713 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);
2714 rxf_lo = reg / 16;
2715 if (rxf_lo < 192)
2716 rxf_lo = 192;
2717 rxf_hi = (reg * 7) / 8;
2718 if (rxf_hi < rxf_lo)
2719 rxf_hi = rxf_lo + 16;
2720 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);
2721 rrd_lo = reg / 8;
2722 rrd_hi = (reg * 7) / 8;
2723 if (rrd_lo < 2)
2724 rrd_lo = 2;
2725 if (rrd_hi < rrd_lo)
2726 rrd_hi = rrd_lo + 3;
2727 break;
2728 }
2729 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH,
2730 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) &
2731 RXQ_FIFO_PAUSE_THRESH_LO_MASK) |
2732 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) &
2733 RXQ_FIFO_PAUSE_THRESH_HI_MASK));
2734 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH,
2735 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) &
2736 RXQ_RRD_PAUSE_THRESH_LO_MASK) |
2737 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) &
2738 RXQ_RRD_PAUSE_THRESH_HI_MASK));
2739
2740 /* Configure RxQ. */
2741 CSR_WRITE_4(sc, AGE_RXQ_CFG,
2742 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
2743 RXQ_CFG_RD_BURST_MASK) |
2744 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT <<
2745 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) |
2746 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT <<
2747 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) |
2748 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2749
2750 /* Configure TxQ. */
2751 CSR_WRITE_4(sc, AGE_TXQ_CFG,
2752 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2753 TXQ_CFG_TPD_BURST_MASK) |
2754 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) &
2755 TXQ_CFG_TX_FIFO_BURST_MASK) |
2756 ((TXQ_CFG_TPD_FETCH_DEFAULT <<
2757 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) |
2758 TXQ_CFG_ENB);
2759
2760 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG,
2761 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) &
2762 TX_JUMBO_TPD_TH_MASK) |
2763 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) &
2764 TX_JUMBO_TPD_IPG_MASK));
2765 /* Configure DMA parameters. */
2766 CSR_WRITE_4(sc, AGE_DMA_CFG,
2767 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 |
2768 sc->age_dma_rd_burst | DMA_CFG_RD_ENB |
2769 sc->age_dma_wr_burst | DMA_CFG_WR_ENB);
2770
2771 /* Configure CMB DMA write threshold. */
2772 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH,
2773 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) &
2774 CMB_WR_THRESH_RRD_MASK) |
2775 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) &
2776 CMB_WR_THRESH_TPD_MASK));
2777
2778 /* Set CMB/SMB timer and enable them. */
2779 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER,
2780 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) |
2781 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK));
2782 /* Request SMB updates for every seconds. */
2783 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000));
2784 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB);
2785
2786 /*
2787 * Disable all WOL bits as WOL can interfere normal Rx
2788 * operation.
2789 */
2790 CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
2791
2792 /*
2793 * Configure Tx/Rx MACs.
2794 * - Auto-padding for short frames.
2795 * - Enable CRC generation.
2796 * Start with full-duplex/1000Mbps media. Actual reconfiguration
2797 * of MAC is followed after link establishment.
2798 */
2799 CSR_WRITE_4(sc, AGE_MAC_CFG,
2800 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD |
2801 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 |
2802 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2803 MAC_CFG_PREAMBLE_MASK));
2804 /* Set up the receive filter. */
2805 age_rxfilter(sc);
2806 age_rxvlan(sc);
2807
2808 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2809 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
2810 reg |= MAC_CFG_RXCSUM_ENB;
2811
2812 /* Ack all pending interrupts and clear it. */
2813 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2814 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS);
2815
2816 /* Finally enable Tx/Rx MAC. */
2817 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2818
2819 sc->age_flags &= ~AGE_FLAG_LINK;
2820 /* Switch to the current media. */
2821 mii_mediachg(mii);
2822
2823 callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2824
2825 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
2826 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2827 }
2828
2829 static void
age_stop(struct age_softc * sc)2830 age_stop(struct age_softc *sc)
2831 {
2832 if_t ifp;
2833 struct age_txdesc *txd;
2834 struct age_rxdesc *rxd;
2835 uint32_t reg;
2836 int i;
2837
2838 AGE_LOCK_ASSERT(sc);
2839 /*
2840 * Mark the interface down and cancel the watchdog timer.
2841 */
2842 ifp = sc->age_ifp;
2843 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2844 sc->age_flags &= ~AGE_FLAG_LINK;
2845 callout_stop(&sc->age_tick_ch);
2846 sc->age_watchdog_timer = 0;
2847
2848 /*
2849 * Disable interrupts.
2850 */
2851 CSR_WRITE_4(sc, AGE_INTR_MASK, 0);
2852 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF);
2853 /* Stop CMB/SMB updates. */
2854 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0);
2855 /* Stop Rx/Tx MAC. */
2856 age_stop_rxmac(sc);
2857 age_stop_txmac(sc);
2858 /* Stop DMA. */
2859 CSR_WRITE_4(sc, AGE_DMA_CFG,
2860 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB));
2861 /* Stop TxQ/RxQ. */
2862 CSR_WRITE_4(sc, AGE_TXQ_CFG,
2863 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB);
2864 CSR_WRITE_4(sc, AGE_RXQ_CFG,
2865 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB);
2866 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2867 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2868 break;
2869 DELAY(10);
2870 }
2871 if (i == 0)
2872 device_printf(sc->age_dev,
2873 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg);
2874
2875 /* Reclaim Rx buffers that have been processed. */
2876 if (sc->age_cdata.age_rxhead != NULL)
2877 m_freem(sc->age_cdata.age_rxhead);
2878 AGE_RXCHAIN_RESET(sc);
2879 /*
2880 * Free RX and TX mbufs still in the queues.
2881 */
2882 for (i = 0; i < AGE_RX_RING_CNT; i++) {
2883 rxd = &sc->age_cdata.age_rxdesc[i];
2884 if (rxd->rx_m != NULL) {
2885 bus_dmamap_sync(sc->age_cdata.age_rx_tag,
2886 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2887 bus_dmamap_unload(sc->age_cdata.age_rx_tag,
2888 rxd->rx_dmamap);
2889 m_freem(rxd->rx_m);
2890 rxd->rx_m = NULL;
2891 }
2892 }
2893 for (i = 0; i < AGE_TX_RING_CNT; i++) {
2894 txd = &sc->age_cdata.age_txdesc[i];
2895 if (txd->tx_m != NULL) {
2896 bus_dmamap_sync(sc->age_cdata.age_tx_tag,
2897 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2898 bus_dmamap_unload(sc->age_cdata.age_tx_tag,
2899 txd->tx_dmamap);
2900 m_freem(txd->tx_m);
2901 txd->tx_m = NULL;
2902 }
2903 }
2904 }
2905
2906 static void
age_stop_txmac(struct age_softc * sc)2907 age_stop_txmac(struct age_softc *sc)
2908 {
2909 uint32_t reg;
2910 int i;
2911
2912 AGE_LOCK_ASSERT(sc);
2913
2914 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2915 if ((reg & MAC_CFG_TX_ENB) != 0) {
2916 reg &= ~MAC_CFG_TX_ENB;
2917 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2918 }
2919 /* Stop Tx DMA engine. */
2920 reg = CSR_READ_4(sc, AGE_DMA_CFG);
2921 if ((reg & DMA_CFG_RD_ENB) != 0) {
2922 reg &= ~DMA_CFG_RD_ENB;
2923 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2924 }
2925 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2926 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2927 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0)
2928 break;
2929 DELAY(10);
2930 }
2931 if (i == 0)
2932 device_printf(sc->age_dev, "stopping TxMAC timeout!\n");
2933 }
2934
2935 static void
age_stop_rxmac(struct age_softc * sc)2936 age_stop_rxmac(struct age_softc *sc)
2937 {
2938 uint32_t reg;
2939 int i;
2940
2941 AGE_LOCK_ASSERT(sc);
2942
2943 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2944 if ((reg & MAC_CFG_RX_ENB) != 0) {
2945 reg &= ~MAC_CFG_RX_ENB;
2946 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2947 }
2948 /* Stop Rx DMA engine. */
2949 reg = CSR_READ_4(sc, AGE_DMA_CFG);
2950 if ((reg & DMA_CFG_WR_ENB) != 0) {
2951 reg &= ~DMA_CFG_WR_ENB;
2952 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2953 }
2954 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2955 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2956 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0)
2957 break;
2958 DELAY(10);
2959 }
2960 if (i == 0)
2961 device_printf(sc->age_dev, "stopping RxMAC timeout!\n");
2962 }
2963
2964 static void
age_init_tx_ring(struct age_softc * sc)2965 age_init_tx_ring(struct age_softc *sc)
2966 {
2967 struct age_ring_data *rd;
2968 struct age_txdesc *txd;
2969 int i;
2970
2971 AGE_LOCK_ASSERT(sc);
2972
2973 sc->age_cdata.age_tx_prod = 0;
2974 sc->age_cdata.age_tx_cons = 0;
2975 sc->age_cdata.age_tx_cnt = 0;
2976
2977 rd = &sc->age_rdata;
2978 bzero(rd->age_tx_ring, AGE_TX_RING_SZ);
2979 for (i = 0; i < AGE_TX_RING_CNT; i++) {
2980 txd = &sc->age_cdata.age_txdesc[i];
2981 txd->tx_desc = &rd->age_tx_ring[i];
2982 txd->tx_m = NULL;
2983 }
2984
2985 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2986 sc->age_cdata.age_tx_ring_map,
2987 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2988 }
2989
2990 static int
age_init_rx_ring(struct age_softc * sc)2991 age_init_rx_ring(struct age_softc *sc)
2992 {
2993 struct age_ring_data *rd;
2994 struct age_rxdesc *rxd;
2995 int i;
2996
2997 AGE_LOCK_ASSERT(sc);
2998
2999 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1;
3000 sc->age_morework = 0;
3001 rd = &sc->age_rdata;
3002 bzero(rd->age_rx_ring, AGE_RX_RING_SZ);
3003 for (i = 0; i < AGE_RX_RING_CNT; i++) {
3004 rxd = &sc->age_cdata.age_rxdesc[i];
3005 rxd->rx_m = NULL;
3006 rxd->rx_desc = &rd->age_rx_ring[i];
3007 if (age_newbuf(sc, rxd) != 0)
3008 return (ENOBUFS);
3009 }
3010
3011 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
3012 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE);
3013
3014 return (0);
3015 }
3016
3017 static void
age_init_rr_ring(struct age_softc * sc)3018 age_init_rr_ring(struct age_softc *sc)
3019 {
3020 struct age_ring_data *rd;
3021
3022 AGE_LOCK_ASSERT(sc);
3023
3024 sc->age_cdata.age_rr_cons = 0;
3025 AGE_RXCHAIN_RESET(sc);
3026
3027 rd = &sc->age_rdata;
3028 bzero(rd->age_rr_ring, AGE_RR_RING_SZ);
3029 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
3030 sc->age_cdata.age_rr_ring_map,
3031 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3032 }
3033
3034 static void
age_init_cmb_block(struct age_softc * sc)3035 age_init_cmb_block(struct age_softc *sc)
3036 {
3037 struct age_ring_data *rd;
3038
3039 AGE_LOCK_ASSERT(sc);
3040
3041 rd = &sc->age_rdata;
3042 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ);
3043 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
3044 sc->age_cdata.age_cmb_block_map,
3045 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3046 }
3047
3048 static void
age_init_smb_block(struct age_softc * sc)3049 age_init_smb_block(struct age_softc *sc)
3050 {
3051 struct age_ring_data *rd;
3052
3053 AGE_LOCK_ASSERT(sc);
3054
3055 rd = &sc->age_rdata;
3056 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ);
3057 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
3058 sc->age_cdata.age_smb_block_map,
3059 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3060 }
3061
3062 static int
age_newbuf(struct age_softc * sc,struct age_rxdesc * rxd)3063 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd)
3064 {
3065 struct rx_desc *desc;
3066 struct mbuf *m;
3067 bus_dma_segment_t segs[1];
3068 bus_dmamap_t map;
3069 int nsegs;
3070
3071 AGE_LOCK_ASSERT(sc);
3072
3073 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
3074 if (m == NULL)
3075 return (ENOBUFS);
3076 m->m_len = m->m_pkthdr.len = MCLBYTES;
3077 #ifndef __NO_STRICT_ALIGNMENT
3078 m_adj(m, AGE_RX_BUF_ALIGN);
3079 #endif
3080
3081 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag,
3082 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3083 m_freem(m);
3084 return (ENOBUFS);
3085 }
3086 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3087
3088 if (rxd->rx_m != NULL) {
3089 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3090 BUS_DMASYNC_POSTREAD);
3091 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap);
3092 }
3093 map = rxd->rx_dmamap;
3094 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap;
3095 sc->age_cdata.age_rx_sparemap = map;
3096 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3097 BUS_DMASYNC_PREREAD);
3098 rxd->rx_m = m;
3099
3100 desc = rxd->rx_desc;
3101 desc->addr = htole64(segs[0].ds_addr);
3102 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) <<
3103 AGE_RD_LEN_SHIFT);
3104 return (0);
3105 }
3106
3107 static void
age_rxvlan(struct age_softc * sc)3108 age_rxvlan(struct age_softc *sc)
3109 {
3110 if_t ifp;
3111 uint32_t reg;
3112
3113 AGE_LOCK_ASSERT(sc);
3114
3115 ifp = sc->age_ifp;
3116 reg = CSR_READ_4(sc, AGE_MAC_CFG);
3117 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3118 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
3119 reg |= MAC_CFG_VLAN_TAG_STRIP;
3120 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
3121 }
3122
3123 static u_int
age_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)3124 age_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
3125 {
3126 uint32_t *mchash = arg;
3127 uint32_t crc;
3128
3129 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
3130 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3131
3132 return (1);
3133 }
3134
3135 static void
age_rxfilter(struct age_softc * sc)3136 age_rxfilter(struct age_softc *sc)
3137 {
3138 if_t ifp;
3139 uint32_t mchash[2];
3140 uint32_t rxcfg;
3141
3142 AGE_LOCK_ASSERT(sc);
3143
3144 ifp = sc->age_ifp;
3145
3146 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG);
3147 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3148 if ((if_getflags(ifp) & IFF_BROADCAST) != 0)
3149 rxcfg |= MAC_CFG_BCAST;
3150 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3151 if ((if_getflags(ifp) & IFF_PROMISC) != 0)
3152 rxcfg |= MAC_CFG_PROMISC;
3153 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0)
3154 rxcfg |= MAC_CFG_ALLMULTI;
3155 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF);
3156 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF);
3157 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3158 return;
3159 }
3160
3161 /* Program new filter. */
3162 bzero(mchash, sizeof(mchash));
3163 if_foreach_llmaddr(ifp, age_hash_maddr, mchash);
3164
3165 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]);
3166 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]);
3167 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3168 }
3169
3170 static int
sysctl_age_stats(SYSCTL_HANDLER_ARGS)3171 sysctl_age_stats(SYSCTL_HANDLER_ARGS)
3172 {
3173 struct age_softc *sc;
3174 struct age_stats *stats;
3175 int error, result;
3176
3177 result = -1;
3178 error = sysctl_handle_int(oidp, &result, 0, req);
3179
3180 if (error != 0 || req->newptr == NULL)
3181 return (error);
3182
3183 if (result != 1)
3184 return (error);
3185
3186 sc = (struct age_softc *)arg1;
3187 stats = &sc->age_stat;
3188 printf("%s statistics:\n", device_get_nameunit(sc->age_dev));
3189 printf("Transmit good frames : %ju\n",
3190 (uintmax_t)stats->tx_frames);
3191 printf("Transmit good broadcast frames : %ju\n",
3192 (uintmax_t)stats->tx_bcast_frames);
3193 printf("Transmit good multicast frames : %ju\n",
3194 (uintmax_t)stats->tx_mcast_frames);
3195 printf("Transmit pause control frames : %u\n",
3196 stats->tx_pause_frames);
3197 printf("Transmit control frames : %u\n",
3198 stats->tx_control_frames);
3199 printf("Transmit frames with excessive deferrals : %u\n",
3200 stats->tx_excess_defer);
3201 printf("Transmit deferrals : %u\n",
3202 stats->tx_deferred);
3203 printf("Transmit good octets : %ju\n",
3204 (uintmax_t)stats->tx_bytes);
3205 printf("Transmit good broadcast octets : %ju\n",
3206 (uintmax_t)stats->tx_bcast_bytes);
3207 printf("Transmit good multicast octets : %ju\n",
3208 (uintmax_t)stats->tx_mcast_bytes);
3209 printf("Transmit frames 64 bytes : %ju\n",
3210 (uintmax_t)stats->tx_pkts_64);
3211 printf("Transmit frames 65 to 127 bytes : %ju\n",
3212 (uintmax_t)stats->tx_pkts_65_127);
3213 printf("Transmit frames 128 to 255 bytes : %ju\n",
3214 (uintmax_t)stats->tx_pkts_128_255);
3215 printf("Transmit frames 256 to 511 bytes : %ju\n",
3216 (uintmax_t)stats->tx_pkts_256_511);
3217 printf("Transmit frames 512 to 1024 bytes : %ju\n",
3218 (uintmax_t)stats->tx_pkts_512_1023);
3219 printf("Transmit frames 1024 to 1518 bytes : %ju\n",
3220 (uintmax_t)stats->tx_pkts_1024_1518);
3221 printf("Transmit frames 1519 to MTU bytes : %ju\n",
3222 (uintmax_t)stats->tx_pkts_1519_max);
3223 printf("Transmit single collisions : %u\n",
3224 stats->tx_single_colls);
3225 printf("Transmit multiple collisions : %u\n",
3226 stats->tx_multi_colls);
3227 printf("Transmit late collisions : %u\n",
3228 stats->tx_late_colls);
3229 printf("Transmit abort due to excessive collisions : %u\n",
3230 stats->tx_excess_colls);
3231 printf("Transmit underruns due to FIFO underruns : %u\n",
3232 stats->tx_underrun);
3233 printf("Transmit descriptor write-back errors : %u\n",
3234 stats->tx_desc_underrun);
3235 printf("Transmit frames with length mismatched frame size : %u\n",
3236 stats->tx_lenerrs);
3237 printf("Transmit frames with truncated due to MTU size : %u\n",
3238 stats->tx_lenerrs);
3239
3240 printf("Receive good frames : %ju\n",
3241 (uintmax_t)stats->rx_frames);
3242 printf("Receive good broadcast frames : %ju\n",
3243 (uintmax_t)stats->rx_bcast_frames);
3244 printf("Receive good multicast frames : %ju\n",
3245 (uintmax_t)stats->rx_mcast_frames);
3246 printf("Receive pause control frames : %u\n",
3247 stats->rx_pause_frames);
3248 printf("Receive control frames : %u\n",
3249 stats->rx_control_frames);
3250 printf("Receive CRC errors : %u\n",
3251 stats->rx_crcerrs);
3252 printf("Receive frames with length errors : %u\n",
3253 stats->rx_lenerrs);
3254 printf("Receive good octets : %ju\n",
3255 (uintmax_t)stats->rx_bytes);
3256 printf("Receive good broadcast octets : %ju\n",
3257 (uintmax_t)stats->rx_bcast_bytes);
3258 printf("Receive good multicast octets : %ju\n",
3259 (uintmax_t)stats->rx_mcast_bytes);
3260 printf("Receive frames too short : %u\n",
3261 stats->rx_runts);
3262 printf("Receive fragmented frames : %ju\n",
3263 (uintmax_t)stats->rx_fragments);
3264 printf("Receive frames 64 bytes : %ju\n",
3265 (uintmax_t)stats->rx_pkts_64);
3266 printf("Receive frames 65 to 127 bytes : %ju\n",
3267 (uintmax_t)stats->rx_pkts_65_127);
3268 printf("Receive frames 128 to 255 bytes : %ju\n",
3269 (uintmax_t)stats->rx_pkts_128_255);
3270 printf("Receive frames 256 to 511 bytes : %ju\n",
3271 (uintmax_t)stats->rx_pkts_256_511);
3272 printf("Receive frames 512 to 1024 bytes : %ju\n",
3273 (uintmax_t)stats->rx_pkts_512_1023);
3274 printf("Receive frames 1024 to 1518 bytes : %ju\n",
3275 (uintmax_t)stats->rx_pkts_1024_1518);
3276 printf("Receive frames 1519 to MTU bytes : %ju\n",
3277 (uintmax_t)stats->rx_pkts_1519_max);
3278 printf("Receive frames too long : %ju\n",
3279 (uint64_t)stats->rx_pkts_truncated);
3280 printf("Receive frames with FIFO overflow : %u\n",
3281 stats->rx_fifo_oflows);
3282 printf("Receive frames with return descriptor overflow : %u\n",
3283 stats->rx_desc_oflows);
3284 printf("Receive frames with alignment errors : %u\n",
3285 stats->rx_alignerrs);
3286 printf("Receive frames dropped due to address filtering : %ju\n",
3287 (uint64_t)stats->rx_pkts_filtered);
3288
3289 return (error);
3290 }
3291
3292 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)3293 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3294 {
3295 int error, value;
3296
3297 if (arg1 == NULL)
3298 return (EINVAL);
3299 value = *(int *)arg1;
3300 error = sysctl_handle_int(oidp, &value, 0, req);
3301 if (error || req->newptr == NULL)
3302 return (error);
3303 if (value < low || value > high)
3304 return (EINVAL);
3305 *(int *)arg1 = value;
3306
3307 return (0);
3308 }
3309
3310 static int
sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS)3311 sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS)
3312 {
3313 return (sysctl_int_range(oidp, arg1, arg2, req,
3314 AGE_PROC_MIN, AGE_PROC_MAX));
3315 }
3316
3317 static int
sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS)3318 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS)
3319 {
3320
3321 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN,
3322 AGE_IM_TIMER_MAX));
3323 }
3324