1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices ADV7511 HDMI Transmitter Device Driver
4 *
5 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6 */
7
8 /*
9 * This file is named adv7511-v4l2.c so it doesn't conflict with the Analog
10 * Device ADV7511 (config fragment CONFIG_DRM_I2C_ADV7511).
11 */
12
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/slab.h>
17 #include <linux/i2c.h>
18 #include <linux/delay.h>
19 #include <linux/videodev2.h>
20 #include <linux/workqueue.h>
21 #include <linux/hdmi.h>
22 #include <linux/v4l2-dv-timings.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-common.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-dv-timings.h>
27 #include <media/i2c/adv7511.h>
28 #include <media/cec.h>
29
30 static int debug;
31 module_param(debug, int, 0644);
32 MODULE_PARM_DESC(debug, "debug level (0-2)");
33
34 MODULE_DESCRIPTION("Analog Devices ADV7511 HDMI Transmitter Device Driver");
35 MODULE_AUTHOR("Hans Verkuil");
36 MODULE_LICENSE("GPL v2");
37
38 #define MASK_ADV7511_EDID_RDY_INT 0x04
39 #define MASK_ADV7511_MSEN_INT 0x40
40 #define MASK_ADV7511_HPD_INT 0x80
41
42 #define MASK_ADV7511_HPD_DETECT 0x40
43 #define MASK_ADV7511_MSEN_DETECT 0x20
44 #define MASK_ADV7511_EDID_RDY 0x10
45
46 #define EDID_MAX_RETRIES (8)
47 #define EDID_DELAY 250
48 #define EDID_MAX_SEGM 8
49
50 #define ADV7511_MAX_WIDTH 1920
51 #define ADV7511_MAX_HEIGHT 1200
52 #define ADV7511_MIN_PIXELCLOCK 20000000
53 #define ADV7511_MAX_PIXELCLOCK 225000000
54
55 #define ADV7511_MAX_ADDRS (3)
56
57 /*
58 **********************************************************************
59 *
60 * Arrays with configuration parameters for the ADV7511
61 *
62 **********************************************************************
63 */
64
65 struct adv7511_state_edid {
66 /* total number of blocks */
67 u32 blocks;
68 /* Number of segments read */
69 u32 segments;
70 u8 data[EDID_MAX_SEGM * 256];
71 /* Number of EDID read retries left */
72 unsigned read_retries;
73 bool complete;
74 };
75
76 struct adv7511_state {
77 struct adv7511_platform_data pdata;
78 struct v4l2_subdev sd;
79 struct media_pad pad;
80 struct v4l2_ctrl_handler hdl;
81 int chip_revision;
82 u8 i2c_edid_addr;
83 u8 i2c_pktmem_addr;
84 u8 i2c_cec_addr;
85
86 struct i2c_client *i2c_cec;
87 struct cec_adapter *cec_adap;
88 u8 cec_addr[ADV7511_MAX_ADDRS];
89 u8 cec_valid_addrs;
90 bool cec_enabled_adap;
91
92 /* Is the adv7511 powered on? */
93 bool power_on;
94 /* Did we receive hotplug and rx-sense signals? */
95 bool have_monitor;
96 bool enabled_irq;
97 /* timings from s_dv_timings */
98 struct v4l2_dv_timings dv_timings;
99 u32 fmt_code;
100 u32 colorspace;
101 u32 ycbcr_enc;
102 u32 quantization;
103 u32 xfer_func;
104 u32 content_type;
105 /* controls */
106 struct v4l2_ctrl *hdmi_mode_ctrl;
107 struct v4l2_ctrl *hotplug_ctrl;
108 struct v4l2_ctrl *rx_sense_ctrl;
109 struct v4l2_ctrl *have_edid0_ctrl;
110 struct v4l2_ctrl *rgb_quantization_range_ctrl;
111 struct v4l2_ctrl *content_type_ctrl;
112 struct i2c_client *i2c_edid;
113 struct i2c_client *i2c_pktmem;
114 struct adv7511_state_edid edid;
115 /* Running counter of the number of detected EDIDs (for debugging) */
116 unsigned edid_detect_counter;
117 struct workqueue_struct *work_queue;
118 struct delayed_work edid_handler; /* work entry */
119
120 struct dentry *debugfs_dir;
121 struct v4l2_debugfs_if *infoframes;
122 };
123
124 static void adv7511_check_monitor_present_status(struct v4l2_subdev *sd);
125 static bool adv7511_check_edid_status(struct v4l2_subdev *sd);
126 static void adv7511_setup(struct v4l2_subdev *sd);
127 static int adv7511_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq);
128 static int adv7511_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
129
130
131 static const struct v4l2_dv_timings_cap adv7511_timings_cap = {
132 .type = V4L2_DV_BT_656_1120,
133 /* keep this initialization for compatibility with GCC < 4.4.6 */
134 .reserved = { 0 },
135 V4L2_INIT_BT_TIMINGS(640, ADV7511_MAX_WIDTH, 350, ADV7511_MAX_HEIGHT,
136 ADV7511_MIN_PIXELCLOCK, ADV7511_MAX_PIXELCLOCK,
137 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
138 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
139 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
140 V4L2_DV_BT_CAP_CUSTOM)
141 };
142
get_adv7511_state(struct v4l2_subdev * sd)143 static inline struct adv7511_state *get_adv7511_state(struct v4l2_subdev *sd)
144 {
145 return container_of(sd, struct adv7511_state, sd);
146 }
147
to_sd(struct v4l2_ctrl * ctrl)148 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
149 {
150 return &container_of(ctrl->handler, struct adv7511_state, hdl)->sd;
151 }
152
153 /* ------------------------ I2C ----------------------------------------------- */
154
adv_smbus_read_byte_data_check(struct i2c_client * client,u8 command,bool check)155 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
156 u8 command, bool check)
157 {
158 union i2c_smbus_data data;
159
160 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
161 I2C_SMBUS_READ, command,
162 I2C_SMBUS_BYTE_DATA, &data))
163 return data.byte;
164 if (check)
165 v4l_err(client, "error reading %02x, %02x\n",
166 client->addr, command);
167 return -1;
168 }
169
adv_smbus_read_byte_data(struct i2c_client * client,u8 command)170 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
171 {
172 int i;
173 for (i = 0; i < 3; i++) {
174 int ret = adv_smbus_read_byte_data_check(client, command, true);
175 if (ret >= 0) {
176 if (i)
177 v4l_err(client, "read ok after %d retries\n", i);
178 return ret;
179 }
180 }
181 v4l_err(client, "read failed\n");
182 return -1;
183 }
184
adv7511_rd(struct v4l2_subdev * sd,u8 reg)185 static int adv7511_rd(struct v4l2_subdev *sd, u8 reg)
186 {
187 struct i2c_client *client = v4l2_get_subdevdata(sd);
188
189 return adv_smbus_read_byte_data(client, reg);
190 }
191
adv7511_wr(struct v4l2_subdev * sd,u8 reg,u8 val)192 static int adv7511_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
193 {
194 struct i2c_client *client = v4l2_get_subdevdata(sd);
195 int ret;
196 int i;
197
198 for (i = 0; i < 3; i++) {
199 ret = i2c_smbus_write_byte_data(client, reg, val);
200 if (ret == 0)
201 return 0;
202 }
203 v4l2_err(sd, "%s: i2c write error\n", __func__);
204 return ret;
205 }
206
207 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
208 and then the value-mask (to be OR-ed). */
adv7511_wr_and_or(struct v4l2_subdev * sd,u8 reg,u8 clr_mask,u8 val_mask)209 static inline void adv7511_wr_and_or(struct v4l2_subdev *sd, u8 reg, u8 clr_mask, u8 val_mask)
210 {
211 adv7511_wr(sd, reg, (adv7511_rd(sd, reg) & clr_mask) | val_mask);
212 }
213
adv7511_edid_rd(struct v4l2_subdev * sd,uint16_t len,uint8_t * buf)214 static int adv7511_edid_rd(struct v4l2_subdev *sd, uint16_t len, uint8_t *buf)
215 {
216 struct adv7511_state *state = get_adv7511_state(sd);
217 int i;
218
219 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
220
221 for (i = 0; i < len; i += I2C_SMBUS_BLOCK_MAX) {
222 s32 ret;
223
224 ret = i2c_smbus_read_i2c_block_data(state->i2c_edid, i,
225 I2C_SMBUS_BLOCK_MAX, buf + i);
226 if (ret < 0) {
227 v4l2_err(sd, "%s: i2c read error\n", __func__);
228 return ret;
229 }
230 }
231
232 return 0;
233 }
234
adv7511_cec_read(struct v4l2_subdev * sd,u8 reg)235 static inline int adv7511_cec_read(struct v4l2_subdev *sd, u8 reg)
236 {
237 struct adv7511_state *state = get_adv7511_state(sd);
238
239 return i2c_smbus_read_byte_data(state->i2c_cec, reg);
240 }
241
adv7511_cec_write(struct v4l2_subdev * sd,u8 reg,u8 val)242 static int adv7511_cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
243 {
244 struct adv7511_state *state = get_adv7511_state(sd);
245 int ret;
246 int i;
247
248 for (i = 0; i < 3; i++) {
249 ret = i2c_smbus_write_byte_data(state->i2c_cec, reg, val);
250 if (ret == 0)
251 return 0;
252 }
253 v4l2_err(sd, "%s: I2C Write Problem\n", __func__);
254 return ret;
255 }
256
adv7511_cec_write_and_or(struct v4l2_subdev * sd,u8 reg,u8 mask,u8 val)257 static inline int adv7511_cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask,
258 u8 val)
259 {
260 return adv7511_cec_write(sd, reg, (adv7511_cec_read(sd, reg) & mask) | val);
261 }
262
adv7511_pktmem_rd(struct v4l2_subdev * sd,u8 reg)263 static int adv7511_pktmem_rd(struct v4l2_subdev *sd, u8 reg)
264 {
265 struct adv7511_state *state = get_adv7511_state(sd);
266
267 return adv_smbus_read_byte_data(state->i2c_pktmem, reg);
268 }
269
adv7511_have_hotplug(struct v4l2_subdev * sd)270 static inline bool adv7511_have_hotplug(struct v4l2_subdev *sd)
271 {
272 return adv7511_rd(sd, 0x42) & MASK_ADV7511_HPD_DETECT;
273 }
274
adv7511_have_rx_sense(struct v4l2_subdev * sd)275 static inline bool adv7511_have_rx_sense(struct v4l2_subdev *sd)
276 {
277 return adv7511_rd(sd, 0x42) & MASK_ADV7511_MSEN_DETECT;
278 }
279
adv7511_csc_conversion_mode(struct v4l2_subdev * sd,u8 mode)280 static void adv7511_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode)
281 {
282 adv7511_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5);
283 }
284
adv7511_csc_coeff(struct v4l2_subdev * sd,u16 A1,u16 A2,u16 A3,u16 A4,u16 B1,u16 B2,u16 B3,u16 B4,u16 C1,u16 C2,u16 C3,u16 C4)285 static void adv7511_csc_coeff(struct v4l2_subdev *sd,
286 u16 A1, u16 A2, u16 A3, u16 A4,
287 u16 B1, u16 B2, u16 B3, u16 B4,
288 u16 C1, u16 C2, u16 C3, u16 C4)
289 {
290 /* A */
291 adv7511_wr_and_or(sd, 0x18, 0xe0, A1>>8);
292 adv7511_wr(sd, 0x19, A1);
293 adv7511_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
294 adv7511_wr(sd, 0x1B, A2);
295 adv7511_wr_and_or(sd, 0x1c, 0xe0, A3>>8);
296 adv7511_wr(sd, 0x1d, A3);
297 adv7511_wr_and_or(sd, 0x1e, 0xe0, A4>>8);
298 adv7511_wr(sd, 0x1f, A4);
299
300 /* B */
301 adv7511_wr_and_or(sd, 0x20, 0xe0, B1>>8);
302 adv7511_wr(sd, 0x21, B1);
303 adv7511_wr_and_or(sd, 0x22, 0xe0, B2>>8);
304 adv7511_wr(sd, 0x23, B2);
305 adv7511_wr_and_or(sd, 0x24, 0xe0, B3>>8);
306 adv7511_wr(sd, 0x25, B3);
307 adv7511_wr_and_or(sd, 0x26, 0xe0, B4>>8);
308 adv7511_wr(sd, 0x27, B4);
309
310 /* C */
311 adv7511_wr_and_or(sd, 0x28, 0xe0, C1>>8);
312 adv7511_wr(sd, 0x29, C1);
313 adv7511_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
314 adv7511_wr(sd, 0x2B, C2);
315 adv7511_wr_and_or(sd, 0x2C, 0xe0, C3>>8);
316 adv7511_wr(sd, 0x2D, C3);
317 adv7511_wr_and_or(sd, 0x2E, 0xe0, C4>>8);
318 adv7511_wr(sd, 0x2F, C4);
319 }
320
adv7511_csc_rgb_full2limit(struct v4l2_subdev * sd,bool enable)321 static void adv7511_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable)
322 {
323 if (enable) {
324 u8 csc_mode = 0;
325 adv7511_csc_conversion_mode(sd, csc_mode);
326 adv7511_csc_coeff(sd,
327 4096-564, 0, 0, 256,
328 0, 4096-564, 0, 256,
329 0, 0, 4096-564, 256);
330 /* enable CSC */
331 adv7511_wr_and_or(sd, 0x18, 0x7f, 0x80);
332 /* AVI infoframe: Limited range RGB (16-235) */
333 adv7511_wr_and_or(sd, 0x57, 0xf3, 0x04);
334 } else {
335 /* disable CSC */
336 adv7511_wr_and_or(sd, 0x18, 0x7f, 0x0);
337 /* AVI infoframe: Full range RGB (0-255) */
338 adv7511_wr_and_or(sd, 0x57, 0xf3, 0x08);
339 }
340 }
341
adv7511_set_rgb_quantization_mode(struct v4l2_subdev * sd,struct v4l2_ctrl * ctrl)342 static void adv7511_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl)
343 {
344 struct adv7511_state *state = get_adv7511_state(sd);
345
346 /* Only makes sense for RGB formats */
347 if (state->fmt_code != MEDIA_BUS_FMT_RGB888_1X24) {
348 /* so just keep quantization */
349 adv7511_csc_rgb_full2limit(sd, false);
350 return;
351 }
352
353 switch (ctrl->val) {
354 case V4L2_DV_RGB_RANGE_AUTO:
355 /* automatic */
356 if (state->dv_timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
357 /* CE format, RGB limited range (16-235) */
358 adv7511_csc_rgb_full2limit(sd, true);
359 } else {
360 /* not CE format, RGB full range (0-255) */
361 adv7511_csc_rgb_full2limit(sd, false);
362 }
363 break;
364 case V4L2_DV_RGB_RANGE_LIMITED:
365 /* RGB limited range (16-235) */
366 adv7511_csc_rgb_full2limit(sd, true);
367 break;
368 case V4L2_DV_RGB_RANGE_FULL:
369 /* RGB full range (0-255) */
370 adv7511_csc_rgb_full2limit(sd, false);
371 break;
372 }
373 }
374
375 /* ------------------------------ CTRL OPS ------------------------------ */
376
adv7511_s_ctrl(struct v4l2_ctrl * ctrl)377 static int adv7511_s_ctrl(struct v4l2_ctrl *ctrl)
378 {
379 struct v4l2_subdev *sd = to_sd(ctrl);
380 struct adv7511_state *state = get_adv7511_state(sd);
381
382 v4l2_dbg(1, debug, sd, "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val);
383
384 if (state->hdmi_mode_ctrl == ctrl) {
385 /* Set HDMI or DVI-D */
386 adv7511_wr_and_or(sd, 0xaf, 0xfd, ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00);
387 return 0;
388 }
389 if (state->rgb_quantization_range_ctrl == ctrl) {
390 adv7511_set_rgb_quantization_mode(sd, ctrl);
391 return 0;
392 }
393 if (state->content_type_ctrl == ctrl) {
394 u8 itc, cn;
395
396 state->content_type = ctrl->val;
397 itc = state->content_type != V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
398 cn = itc ? state->content_type : V4L2_DV_IT_CONTENT_TYPE_GRAPHICS;
399 adv7511_wr_and_or(sd, 0x57, 0x7f, itc << 7);
400 adv7511_wr_and_or(sd, 0x59, 0xcf, cn << 4);
401 return 0;
402 }
403
404 return -EINVAL;
405 }
406
407 static const struct v4l2_ctrl_ops adv7511_ctrl_ops = {
408 .s_ctrl = adv7511_s_ctrl,
409 };
410
411 /* ---------------------------- CORE OPS ------------------------------------------- */
412
413 #ifdef CONFIG_VIDEO_ADV_DEBUG
adv7511_inv_register(struct v4l2_subdev * sd)414 static void adv7511_inv_register(struct v4l2_subdev *sd)
415 {
416 struct adv7511_state *state = get_adv7511_state(sd);
417
418 v4l2_info(sd, "0x000-0x0ff: Main Map\n");
419 if (state->i2c_cec)
420 v4l2_info(sd, "0x100-0x1ff: CEC Map\n");
421 }
422
adv7511_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)423 static int adv7511_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
424 {
425 struct adv7511_state *state = get_adv7511_state(sd);
426
427 reg->size = 1;
428 switch (reg->reg >> 8) {
429 case 0:
430 reg->val = adv7511_rd(sd, reg->reg & 0xff);
431 break;
432 case 1:
433 if (state->i2c_cec) {
434 reg->val = adv7511_cec_read(sd, reg->reg & 0xff);
435 break;
436 }
437 fallthrough;
438 default:
439 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
440 adv7511_inv_register(sd);
441 break;
442 }
443 return 0;
444 }
445
adv7511_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)446 static int adv7511_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
447 {
448 struct adv7511_state *state = get_adv7511_state(sd);
449
450 switch (reg->reg >> 8) {
451 case 0:
452 adv7511_wr(sd, reg->reg & 0xff, reg->val & 0xff);
453 break;
454 case 1:
455 if (state->i2c_cec) {
456 adv7511_cec_write(sd, reg->reg & 0xff, reg->val & 0xff);
457 break;
458 }
459 fallthrough;
460 default:
461 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
462 adv7511_inv_register(sd);
463 break;
464 }
465 return 0;
466 }
467 #endif
468
469 struct adv7511_cfg_read_infoframe {
470 const char *desc;
471 u8 present_reg;
472 u8 present_mask;
473 u8 header[3];
474 u16 payload_addr;
475 };
476
hdmi_infoframe_checksum(u8 * ptr,size_t size)477 static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size)
478 {
479 u8 csum = 0;
480 size_t i;
481
482 /* compute checksum */
483 for (i = 0; i < size; i++)
484 csum += ptr[i];
485
486 return 256 - csum;
487 }
488
read_infoframe(struct v4l2_subdev * sd,const struct adv7511_cfg_read_infoframe * cri,u8 * buffer)489 static int read_infoframe(struct v4l2_subdev *sd,
490 const struct adv7511_cfg_read_infoframe *cri,
491 u8 *buffer)
492 {
493 u8 len;
494 int i;
495
496 if (!(adv7511_rd(sd, cri->present_reg) & cri->present_mask)) {
497 v4l2_info(sd, "%s infoframe not transmitted\n", cri->desc);
498 return 0;
499 }
500
501 memcpy(buffer, cri->header, sizeof(cri->header));
502
503 len = buffer[2];
504
505 if (len + 4 > V4L2_DEBUGFS_IF_MAX_LEN) {
506 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);
507 return 0;
508 }
509
510 if (cri->payload_addr >= 0x100) {
511 for (i = 0; i < len; i++)
512 buffer[i + 4] = adv7511_pktmem_rd(sd, cri->payload_addr + i - 0x100);
513 } else {
514 for (i = 0; i < len; i++)
515 buffer[i + 4] = adv7511_rd(sd, cri->payload_addr + i);
516 }
517 buffer[3] = 0;
518 buffer[3] = hdmi_infoframe_checksum(buffer, len + 4);
519
520 return len + 4;
521 }
522
log_infoframe(struct v4l2_subdev * sd,const struct adv7511_cfg_read_infoframe * cri)523 static void log_infoframe(struct v4l2_subdev *sd,
524 const struct adv7511_cfg_read_infoframe *cri)
525 {
526 union hdmi_infoframe frame;
527 struct i2c_client *client = v4l2_get_subdevdata(sd);
528 struct device *dev = &client->dev;
529 u8 buffer[V4L2_DEBUGFS_IF_MAX_LEN] = {};
530 int len = read_infoframe(sd, cri, buffer);
531
532 if (len <= 0)
533 return;
534
535 if (hdmi_infoframe_unpack(&frame, buffer, len) < 0) {
536 v4l2_err(sd, "%s: unpack of %s infoframe failed\n",
537 __func__, cri->desc);
538 return;
539 }
540
541 hdmi_infoframe_log(KERN_INFO, dev, &frame);
542 }
543
544 static const struct adv7511_cfg_read_infoframe cri[] = {
545 { "AVI", 0x44, 0x10, { 0x82, 2, 13 }, 0x55 },
546 { "Audio", 0x44, 0x08, { 0x84, 1, 10 }, 0x73 },
547 { "SDP", 0x40, 0x40, { 0x83, 1, 25 }, 0x103 },
548 };
549
adv7511_log_infoframes(struct v4l2_subdev * sd)550 static void adv7511_log_infoframes(struct v4l2_subdev *sd)
551 {
552 int i;
553
554 for (i = 0; i < ARRAY_SIZE(cri); i++)
555 log_infoframe(sd, &cri[i]);
556 }
557
adv7511_log_status(struct v4l2_subdev * sd)558 static int adv7511_log_status(struct v4l2_subdev *sd)
559 {
560 struct adv7511_state *state = get_adv7511_state(sd);
561 struct adv7511_state_edid *edid = &state->edid;
562 int i;
563
564 static const char * const states[] = {
565 "in reset",
566 "reading EDID",
567 "idle",
568 "initializing HDCP",
569 "HDCP enabled",
570 "initializing HDCP repeater",
571 "6", "7", "8", "9", "A", "B", "C", "D", "E", "F"
572 };
573 static const char * const errors[] = {
574 "no error",
575 "bad receiver BKSV",
576 "Ri mismatch",
577 "Pj mismatch",
578 "i2c error",
579 "timed out",
580 "max repeater cascade exceeded",
581 "hash check failed",
582 "too many devices",
583 "9", "A", "B", "C", "D", "E", "F"
584 };
585
586 v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off");
587 v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n",
588 (adv7511_rd(sd, 0x42) & MASK_ADV7511_HPD_DETECT) ? "detected" : "no",
589 (adv7511_rd(sd, 0x42) & MASK_ADV7511_MSEN_DETECT) ? "detected" : "no",
590 edid->segments ? "found" : "no",
591 edid->blocks);
592 v4l2_info(sd, "%s output %s\n",
593 (adv7511_rd(sd, 0xaf) & 0x02) ?
594 "HDMI" : "DVI-D",
595 (adv7511_rd(sd, 0xa1) & 0x3c) ?
596 "disabled" : "enabled");
597 v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n",
598 states[adv7511_rd(sd, 0xc8) & 0xf],
599 errors[adv7511_rd(sd, 0xc8) >> 4], state->edid_detect_counter,
600 adv7511_rd(sd, 0x94), adv7511_rd(sd, 0x96));
601 v4l2_info(sd, "RGB quantization: %s range\n", adv7511_rd(sd, 0x18) & 0x80 ? "limited" : "full");
602 if (adv7511_rd(sd, 0xaf) & 0x02) {
603 /* HDMI only */
604 u8 manual_cts = adv7511_rd(sd, 0x0a) & 0x80;
605 u32 N = (adv7511_rd(sd, 0x01) & 0xf) << 16 |
606 adv7511_rd(sd, 0x02) << 8 |
607 adv7511_rd(sd, 0x03);
608 u8 vic_detect = adv7511_rd(sd, 0x3e) >> 2;
609 u8 vic_sent = adv7511_rd(sd, 0x3d) & 0x3f;
610 u32 CTS;
611
612 if (manual_cts)
613 CTS = (adv7511_rd(sd, 0x07) & 0xf) << 16 |
614 adv7511_rd(sd, 0x08) << 8 |
615 adv7511_rd(sd, 0x09);
616 else
617 CTS = (adv7511_rd(sd, 0x04) & 0xf) << 16 |
618 adv7511_rd(sd, 0x05) << 8 |
619 adv7511_rd(sd, 0x06);
620 v4l2_info(sd, "CTS %s mode: N %d, CTS %d\n",
621 manual_cts ? "manual" : "automatic", N, CTS);
622 v4l2_info(sd, "VIC: detected %d, sent %d\n",
623 vic_detect, vic_sent);
624 adv7511_log_infoframes(sd);
625 }
626 if (state->dv_timings.type == V4L2_DV_BT_656_1120)
627 v4l2_print_dv_timings(sd->name, "timings: ",
628 &state->dv_timings, false);
629 else
630 v4l2_info(sd, "no timings set\n");
631 v4l2_info(sd, "i2c edid addr: 0x%x\n", state->i2c_edid_addr);
632
633 if (state->i2c_cec == NULL)
634 return 0;
635
636 v4l2_info(sd, "i2c cec addr: 0x%x\n", state->i2c_cec_addr);
637
638 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
639 "enabled" : "disabled");
640 if (state->cec_enabled_adap) {
641 for (i = 0; i < ADV7511_MAX_ADDRS; i++) {
642 bool is_valid = state->cec_valid_addrs & (1 << i);
643
644 if (is_valid)
645 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
646 state->cec_addr[i]);
647 }
648 }
649 v4l2_info(sd, "i2c pktmem addr: 0x%x\n", state->i2c_pktmem_addr);
650 return 0;
651 }
652
653 /* Power up/down adv7511 */
adv7511_s_power(struct v4l2_subdev * sd,int on)654 static int adv7511_s_power(struct v4l2_subdev *sd, int on)
655 {
656 struct adv7511_state *state = get_adv7511_state(sd);
657 const int retries = 20;
658 int i;
659
660 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
661
662 state->power_on = on;
663
664 if (!on) {
665 /* Power down */
666 adv7511_wr_and_or(sd, 0x41, 0xbf, 0x40);
667 return true;
668 }
669
670 /* Power up */
671 /* The adv7511 does not always come up immediately.
672 Retry multiple times. */
673 for (i = 0; i < retries; i++) {
674 adv7511_wr_and_or(sd, 0x41, 0xbf, 0x0);
675 if ((adv7511_rd(sd, 0x41) & 0x40) == 0)
676 break;
677 adv7511_wr_and_or(sd, 0x41, 0xbf, 0x40);
678 msleep(10);
679 }
680 if (i == retries) {
681 v4l2_dbg(1, debug, sd, "%s: failed to powerup the adv7511!\n", __func__);
682 adv7511_s_power(sd, 0);
683 return false;
684 }
685 if (i > 1)
686 v4l2_dbg(1, debug, sd, "%s: needed %d retries to powerup the adv7511\n", __func__, i);
687
688 /* Reserved registers that must be set */
689 adv7511_wr(sd, 0x98, 0x03);
690 adv7511_wr_and_or(sd, 0x9a, 0xfe, 0x70);
691 adv7511_wr(sd, 0x9c, 0x30);
692 adv7511_wr_and_or(sd, 0x9d, 0xfc, 0x01);
693 adv7511_wr(sd, 0xa2, 0xa4);
694 adv7511_wr(sd, 0xa3, 0xa4);
695 adv7511_wr(sd, 0xe0, 0xd0);
696 adv7511_wr(sd, 0xf9, 0x00);
697
698 adv7511_wr(sd, 0x43, state->i2c_edid_addr);
699 adv7511_wr(sd, 0x45, state->i2c_pktmem_addr);
700
701 /* Set number of attempts to read the EDID */
702 adv7511_wr(sd, 0xc9, 0xf);
703 return true;
704 }
705
706 #if IS_ENABLED(CONFIG_VIDEO_ADV7511_CEC)
adv7511_cec_adap_enable(struct cec_adapter * adap,bool enable)707 static int adv7511_cec_adap_enable(struct cec_adapter *adap, bool enable)
708 {
709 struct adv7511_state *state = cec_get_drvdata(adap);
710 struct v4l2_subdev *sd = &state->sd;
711
712 if (state->i2c_cec == NULL)
713 return -EIO;
714
715 if (!state->cec_enabled_adap && enable) {
716 /* power up cec section */
717 adv7511_cec_write_and_or(sd, 0x4e, 0xfc, 0x01);
718 /* legacy mode and clear all rx buffers */
719 adv7511_cec_write(sd, 0x4a, 0x00);
720 adv7511_cec_write(sd, 0x4a, 0x07);
721 adv7511_cec_write_and_or(sd, 0x11, 0xfe, 0); /* initially disable tx */
722 /* enabled irqs: */
723 /* tx: ready */
724 /* tx: arbitration lost */
725 /* tx: retry timeout */
726 /* rx: ready 1 */
727 if (state->enabled_irq)
728 adv7511_wr_and_or(sd, 0x95, 0xc0, 0x39);
729 } else if (state->cec_enabled_adap && !enable) {
730 if (state->enabled_irq)
731 adv7511_wr_and_or(sd, 0x95, 0xc0, 0x00);
732 /* disable address mask 1-3 */
733 adv7511_cec_write_and_or(sd, 0x4b, 0x8f, 0x00);
734 /* power down cec section */
735 adv7511_cec_write_and_or(sd, 0x4e, 0xfc, 0x00);
736 state->cec_valid_addrs = 0;
737 }
738 state->cec_enabled_adap = enable;
739 return 0;
740 }
741
adv7511_cec_adap_log_addr(struct cec_adapter * adap,u8 addr)742 static int adv7511_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
743 {
744 struct adv7511_state *state = cec_get_drvdata(adap);
745 struct v4l2_subdev *sd = &state->sd;
746 unsigned int i, free_idx = ADV7511_MAX_ADDRS;
747
748 if (!state->cec_enabled_adap)
749 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
750
751 if (addr == CEC_LOG_ADDR_INVALID) {
752 adv7511_cec_write_and_or(sd, 0x4b, 0x8f, 0);
753 state->cec_valid_addrs = 0;
754 return 0;
755 }
756
757 for (i = 0; i < ADV7511_MAX_ADDRS; i++) {
758 bool is_valid = state->cec_valid_addrs & (1 << i);
759
760 if (free_idx == ADV7511_MAX_ADDRS && !is_valid)
761 free_idx = i;
762 if (is_valid && state->cec_addr[i] == addr)
763 return 0;
764 }
765 if (i == ADV7511_MAX_ADDRS) {
766 i = free_idx;
767 if (i == ADV7511_MAX_ADDRS)
768 return -ENXIO;
769 }
770 state->cec_addr[i] = addr;
771 state->cec_valid_addrs |= 1 << i;
772
773 switch (i) {
774 case 0:
775 /* enable address mask 0 */
776 adv7511_cec_write_and_or(sd, 0x4b, 0xef, 0x10);
777 /* set address for mask 0 */
778 adv7511_cec_write_and_or(sd, 0x4c, 0xf0, addr);
779 break;
780 case 1:
781 /* enable address mask 1 */
782 adv7511_cec_write_and_or(sd, 0x4b, 0xdf, 0x20);
783 /* set address for mask 1 */
784 adv7511_cec_write_and_or(sd, 0x4c, 0x0f, addr << 4);
785 break;
786 case 2:
787 /* enable address mask 2 */
788 adv7511_cec_write_and_or(sd, 0x4b, 0xbf, 0x40);
789 /* set address for mask 1 */
790 adv7511_cec_write_and_or(sd, 0x4d, 0xf0, addr);
791 break;
792 }
793 return 0;
794 }
795
adv7511_cec_adap_transmit(struct cec_adapter * adap,u8 attempts,u32 signal_free_time,struct cec_msg * msg)796 static int adv7511_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
797 u32 signal_free_time, struct cec_msg *msg)
798 {
799 struct adv7511_state *state = cec_get_drvdata(adap);
800 struct v4l2_subdev *sd = &state->sd;
801 u8 len = msg->len;
802 unsigned int i;
803
804 v4l2_dbg(1, debug, sd, "%s: len %d\n", __func__, len);
805
806 if (len > 16) {
807 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
808 return -EINVAL;
809 }
810
811 /*
812 * The number of retries is the number of attempts - 1, but retry
813 * at least once. It's not clear if a value of 0 is allowed, so
814 * let's do at least one retry.
815 */
816 adv7511_cec_write_and_or(sd, 0x12, ~0x70, max(1, attempts - 1) << 4);
817
818 /* clear cec tx irq status */
819 adv7511_wr(sd, 0x97, 0x38);
820
821 /* write data */
822 for (i = 0; i < len; i++)
823 adv7511_cec_write(sd, i, msg->msg[i]);
824
825 /* set length (data + header) */
826 adv7511_cec_write(sd, 0x10, len);
827 /* start transmit, enable tx */
828 adv7511_cec_write(sd, 0x11, 0x01);
829 return 0;
830 }
831
adv_cec_tx_raw_status(struct v4l2_subdev * sd,u8 tx_raw_status)832 static void adv_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
833 {
834 struct adv7511_state *state = get_adv7511_state(sd);
835
836 if ((adv7511_cec_read(sd, 0x11) & 0x01) == 0) {
837 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
838 return;
839 }
840
841 if (tx_raw_status & 0x10) {
842 v4l2_dbg(1, debug, sd,
843 "%s: tx raw: arbitration lost\n", __func__);
844 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
845 1, 0, 0, 0);
846 return;
847 }
848 if (tx_raw_status & 0x08) {
849 u8 status;
850 u8 nack_cnt;
851 u8 low_drive_cnt;
852
853 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
854 /*
855 * We set this status bit since this hardware performs
856 * retransmissions.
857 */
858 status = CEC_TX_STATUS_MAX_RETRIES;
859 nack_cnt = adv7511_cec_read(sd, 0x14) & 0xf;
860 if (nack_cnt)
861 status |= CEC_TX_STATUS_NACK;
862 low_drive_cnt = adv7511_cec_read(sd, 0x14) >> 4;
863 if (low_drive_cnt)
864 status |= CEC_TX_STATUS_LOW_DRIVE;
865 cec_transmit_done(state->cec_adap, status,
866 0, nack_cnt, low_drive_cnt, 0);
867 return;
868 }
869 if (tx_raw_status & 0x20) {
870 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
871 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
872 return;
873 }
874 }
875
876 static const struct cec_adap_ops adv7511_cec_adap_ops = {
877 .adap_enable = adv7511_cec_adap_enable,
878 .adap_log_addr = adv7511_cec_adap_log_addr,
879 .adap_transmit = adv7511_cec_adap_transmit,
880 };
881 #endif
882
883 /* Enable interrupts */
adv7511_set_isr(struct v4l2_subdev * sd,bool enable)884 static void adv7511_set_isr(struct v4l2_subdev *sd, bool enable)
885 {
886 struct adv7511_state *state = get_adv7511_state(sd);
887 u8 irqs = MASK_ADV7511_HPD_INT | MASK_ADV7511_MSEN_INT;
888 u8 irqs_rd;
889 int retries = 100;
890
891 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ? "enable" : "disable");
892
893 if (state->enabled_irq == enable)
894 return;
895 state->enabled_irq = enable;
896
897 /* The datasheet says that the EDID ready interrupt should be
898 disabled if there is no hotplug. */
899 if (!enable)
900 irqs = 0;
901 else if (adv7511_have_hotplug(sd))
902 irqs |= MASK_ADV7511_EDID_RDY_INT;
903
904 /*
905 * This i2c write can fail (approx. 1 in 1000 writes). But it
906 * is essential that this register is correct, so retry it
907 * multiple times.
908 *
909 * Note that the i2c write does not report an error, but the readback
910 * clearly shows the wrong value.
911 */
912 do {
913 adv7511_wr(sd, 0x94, irqs);
914 irqs_rd = adv7511_rd(sd, 0x94);
915 } while (retries-- && irqs_rd != irqs);
916
917 if (irqs_rd != irqs)
918 v4l2_err(sd, "Could not set interrupts: hw failure?\n");
919
920 adv7511_wr_and_or(sd, 0x95, 0xc0,
921 (state->cec_enabled_adap && enable) ? 0x39 : 0x00);
922 }
923
924 /* Interrupt handler */
adv7511_isr(struct v4l2_subdev * sd,u32 status,bool * handled)925 static int adv7511_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
926 {
927 u8 irq_status;
928 u8 cec_irq;
929
930 /* disable interrupts to prevent a race condition */
931 adv7511_set_isr(sd, false);
932 irq_status = adv7511_rd(sd, 0x96);
933 cec_irq = adv7511_rd(sd, 0x97);
934 /* clear detected interrupts */
935 adv7511_wr(sd, 0x96, irq_status);
936 adv7511_wr(sd, 0x97, cec_irq);
937
938 v4l2_dbg(1, debug, sd, "%s: irq 0x%x, cec-irq 0x%x\n", __func__,
939 irq_status, cec_irq);
940
941 if (irq_status & (MASK_ADV7511_HPD_INT | MASK_ADV7511_MSEN_INT))
942 adv7511_check_monitor_present_status(sd);
943 if (irq_status & MASK_ADV7511_EDID_RDY_INT)
944 adv7511_check_edid_status(sd);
945
946 #if IS_ENABLED(CONFIG_VIDEO_ADV7511_CEC)
947 if (cec_irq & 0x38)
948 adv_cec_tx_raw_status(sd, cec_irq);
949
950 if (cec_irq & 1) {
951 struct adv7511_state *state = get_adv7511_state(sd);
952 struct cec_msg msg;
953
954 msg.len = adv7511_cec_read(sd, 0x25) & 0x1f;
955
956 v4l2_dbg(1, debug, sd, "%s: cec msg len %d\n", __func__,
957 msg.len);
958
959 if (msg.len > CEC_MAX_MSG_SIZE)
960 msg.len = CEC_MAX_MSG_SIZE;
961
962 if (msg.len) {
963 u8 i;
964
965 for (i = 0; i < msg.len; i++)
966 msg.msg[i] = adv7511_cec_read(sd, i + 0x15);
967
968 adv7511_cec_write(sd, 0x4a, 0); /* toggle to re-enable rx 1 */
969 adv7511_cec_write(sd, 0x4a, 1);
970 cec_received_msg(state->cec_adap, &msg);
971 }
972 }
973 #endif
974
975 /* enable interrupts */
976 adv7511_set_isr(sd, true);
977
978 if (handled)
979 *handled = true;
980 return 0;
981 }
982
983 static const struct v4l2_subdev_core_ops adv7511_core_ops = {
984 .log_status = adv7511_log_status,
985 #ifdef CONFIG_VIDEO_ADV_DEBUG
986 .g_register = adv7511_g_register,
987 .s_register = adv7511_s_register,
988 #endif
989 .s_power = adv7511_s_power,
990 .interrupt_service_routine = adv7511_isr,
991 };
992
993 /* ------------------------------ VIDEO OPS ------------------------------ */
994
995 /* Enable/disable adv7511 output */
adv7511_s_stream(struct v4l2_subdev * sd,int enable)996 static int adv7511_s_stream(struct v4l2_subdev *sd, int enable)
997 {
998 struct adv7511_state *state = get_adv7511_state(sd);
999
1000 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
1001 adv7511_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c));
1002 if (enable) {
1003 adv7511_check_monitor_present_status(sd);
1004 } else {
1005 adv7511_s_power(sd, 0);
1006 state->have_monitor = false;
1007 }
1008 return 0;
1009 }
1010
adv7511_s_dv_timings(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_dv_timings * timings)1011 static int adv7511_s_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
1012 struct v4l2_dv_timings *timings)
1013 {
1014 struct adv7511_state *state = get_adv7511_state(sd);
1015 struct v4l2_bt_timings *bt = &timings->bt;
1016 u32 fps;
1017
1018 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1019
1020 if (pad != 0)
1021 return -EINVAL;
1022
1023 /* quick sanity check */
1024 if (!v4l2_valid_dv_timings(timings, &adv7511_timings_cap, NULL, NULL))
1025 return -EINVAL;
1026
1027 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1028 if the format is one of the CEA or DMT timings. */
1029 v4l2_find_dv_timings_cap(timings, &adv7511_timings_cap, 0, NULL, NULL);
1030
1031 /* save timings */
1032 state->dv_timings = *timings;
1033
1034 /* set h/vsync polarities */
1035 adv7511_wr_and_or(sd, 0x17, 0x9f,
1036 ((bt->polarities & V4L2_DV_VSYNC_POS_POL) ? 0 : 0x40) |
1037 ((bt->polarities & V4L2_DV_HSYNC_POS_POL) ? 0 : 0x20));
1038
1039 fps = (u32)bt->pixelclock / (V4L2_DV_BT_FRAME_WIDTH(bt) * V4L2_DV_BT_FRAME_HEIGHT(bt));
1040 switch (fps) {
1041 case 24:
1042 adv7511_wr_and_or(sd, 0xfb, 0xf9, 1 << 1);
1043 break;
1044 case 25:
1045 adv7511_wr_and_or(sd, 0xfb, 0xf9, 2 << 1);
1046 break;
1047 case 30:
1048 adv7511_wr_and_or(sd, 0xfb, 0xf9, 3 << 1);
1049 break;
1050 default:
1051 adv7511_wr_and_or(sd, 0xfb, 0xf9, 0);
1052 break;
1053 }
1054
1055 /* update quantization range based on new dv_timings */
1056 adv7511_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
1057
1058 return 0;
1059 }
1060
adv7511_g_dv_timings(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_dv_timings * timings)1061 static int adv7511_g_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
1062 struct v4l2_dv_timings *timings)
1063 {
1064 struct adv7511_state *state = get_adv7511_state(sd);
1065
1066 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1067
1068 if (pad != 0)
1069 return -EINVAL;
1070
1071 if (!timings)
1072 return -EINVAL;
1073
1074 *timings = state->dv_timings;
1075
1076 return 0;
1077 }
1078
adv7511_enum_dv_timings(struct v4l2_subdev * sd,struct v4l2_enum_dv_timings * timings)1079 static int adv7511_enum_dv_timings(struct v4l2_subdev *sd,
1080 struct v4l2_enum_dv_timings *timings)
1081 {
1082 if (timings->pad != 0)
1083 return -EINVAL;
1084
1085 return v4l2_enum_dv_timings_cap(timings, &adv7511_timings_cap, NULL, NULL);
1086 }
1087
adv7511_dv_timings_cap(struct v4l2_subdev * sd,struct v4l2_dv_timings_cap * cap)1088 static int adv7511_dv_timings_cap(struct v4l2_subdev *sd,
1089 struct v4l2_dv_timings_cap *cap)
1090 {
1091 if (cap->pad != 0)
1092 return -EINVAL;
1093
1094 *cap = adv7511_timings_cap;
1095 return 0;
1096 }
1097
1098 static const struct v4l2_subdev_video_ops adv7511_video_ops = {
1099 .s_stream = adv7511_s_stream,
1100 };
1101
1102 /* ------------------------------ AUDIO OPS ------------------------------ */
adv7511_s_audio_stream(struct v4l2_subdev * sd,int enable)1103 static int adv7511_s_audio_stream(struct v4l2_subdev *sd, int enable)
1104 {
1105 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
1106
1107 if (enable)
1108 adv7511_wr_and_or(sd, 0x4b, 0x3f, 0x80);
1109 else
1110 adv7511_wr_and_or(sd, 0x4b, 0x3f, 0x40);
1111
1112 return 0;
1113 }
1114
adv7511_s_clock_freq(struct v4l2_subdev * sd,u32 freq)1115 static int adv7511_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
1116 {
1117 u32 N;
1118
1119 switch (freq) {
1120 case 32000: N = 4096; break;
1121 case 44100: N = 6272; break;
1122 case 48000: N = 6144; break;
1123 case 88200: N = 12544; break;
1124 case 96000: N = 12288; break;
1125 case 176400: N = 25088; break;
1126 case 192000: N = 24576; break;
1127 default:
1128 return -EINVAL;
1129 }
1130
1131 /* Set N (used with CTS to regenerate the audio clock) */
1132 adv7511_wr(sd, 0x01, (N >> 16) & 0xf);
1133 adv7511_wr(sd, 0x02, (N >> 8) & 0xff);
1134 adv7511_wr(sd, 0x03, N & 0xff);
1135
1136 return 0;
1137 }
1138
adv7511_s_i2s_clock_freq(struct v4l2_subdev * sd,u32 freq)1139 static int adv7511_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq)
1140 {
1141 u32 i2s_sf;
1142
1143 switch (freq) {
1144 case 32000: i2s_sf = 0x30; break;
1145 case 44100: i2s_sf = 0x00; break;
1146 case 48000: i2s_sf = 0x20; break;
1147 case 88200: i2s_sf = 0x80; break;
1148 case 96000: i2s_sf = 0xa0; break;
1149 case 176400: i2s_sf = 0xc0; break;
1150 case 192000: i2s_sf = 0xe0; break;
1151 default:
1152 return -EINVAL;
1153 }
1154
1155 /* Set sampling frequency for I2S audio to 48 kHz */
1156 adv7511_wr_and_or(sd, 0x15, 0xf, i2s_sf);
1157
1158 return 0;
1159 }
1160
adv7511_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)1161 static int adv7511_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config)
1162 {
1163 /* Only 2 channels in use for application */
1164 adv7511_wr_and_or(sd, 0x73, 0xf8, 0x1);
1165 /* Speaker mapping */
1166 adv7511_wr(sd, 0x76, 0x00);
1167
1168 /* 16 bit audio word length */
1169 adv7511_wr_and_or(sd, 0x14, 0xf0, 0x02);
1170
1171 return 0;
1172 }
1173
1174 static const struct v4l2_subdev_audio_ops adv7511_audio_ops = {
1175 .s_stream = adv7511_s_audio_stream,
1176 .s_clock_freq = adv7511_s_clock_freq,
1177 .s_i2s_clock_freq = adv7511_s_i2s_clock_freq,
1178 .s_routing = adv7511_s_routing,
1179 };
1180
1181 /* ---------------------------- PAD OPS ------------------------------------- */
1182
adv7511_get_edid(struct v4l2_subdev * sd,struct v4l2_edid * edid)1183 static int adv7511_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1184 {
1185 struct adv7511_state *state = get_adv7511_state(sd);
1186
1187 memset(edid->reserved, 0, sizeof(edid->reserved));
1188
1189 if (edid->pad != 0)
1190 return -EINVAL;
1191
1192 if (edid->start_block == 0 && edid->blocks == 0) {
1193 edid->blocks = state->edid.blocks;
1194 return 0;
1195 }
1196
1197 if (state->edid.blocks == 0)
1198 return -ENODATA;
1199
1200 if (edid->start_block >= state->edid.blocks)
1201 return -EINVAL;
1202
1203 if (edid->start_block + edid->blocks > state->edid.blocks)
1204 edid->blocks = state->edid.blocks - edid->start_block;
1205
1206 memcpy(edid->edid, &state->edid.data[edid->start_block * 128],
1207 128 * edid->blocks);
1208
1209 return 0;
1210 }
1211
adv7511_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)1212 static int adv7511_enum_mbus_code(struct v4l2_subdev *sd,
1213 struct v4l2_subdev_state *sd_state,
1214 struct v4l2_subdev_mbus_code_enum *code)
1215 {
1216 if (code->pad != 0)
1217 return -EINVAL;
1218
1219 switch (code->index) {
1220 case 0:
1221 code->code = MEDIA_BUS_FMT_RGB888_1X24;
1222 break;
1223 case 1:
1224 code->code = MEDIA_BUS_FMT_YUYV8_1X16;
1225 break;
1226 case 2:
1227 code->code = MEDIA_BUS_FMT_UYVY8_1X16;
1228 break;
1229 default:
1230 return -EINVAL;
1231 }
1232 return 0;
1233 }
1234
adv7511_fill_format(struct adv7511_state * state,struct v4l2_mbus_framefmt * format)1235 static void adv7511_fill_format(struct adv7511_state *state,
1236 struct v4l2_mbus_framefmt *format)
1237 {
1238 format->width = state->dv_timings.bt.width;
1239 format->height = state->dv_timings.bt.height;
1240 format->field = V4L2_FIELD_NONE;
1241 }
1242
adv7511_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1243 static int adv7511_get_fmt(struct v4l2_subdev *sd,
1244 struct v4l2_subdev_state *sd_state,
1245 struct v4l2_subdev_format *format)
1246 {
1247 struct adv7511_state *state = get_adv7511_state(sd);
1248
1249 if (format->pad != 0)
1250 return -EINVAL;
1251
1252 memset(&format->format, 0, sizeof(format->format));
1253 adv7511_fill_format(state, &format->format);
1254
1255 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1256 struct v4l2_mbus_framefmt *fmt;
1257
1258 fmt = v4l2_subdev_state_get_format(sd_state, format->pad);
1259 format->format.code = fmt->code;
1260 format->format.colorspace = fmt->colorspace;
1261 format->format.ycbcr_enc = fmt->ycbcr_enc;
1262 format->format.quantization = fmt->quantization;
1263 format->format.xfer_func = fmt->xfer_func;
1264 } else {
1265 format->format.code = state->fmt_code;
1266 format->format.colorspace = state->colorspace;
1267 format->format.ycbcr_enc = state->ycbcr_enc;
1268 format->format.quantization = state->quantization;
1269 format->format.xfer_func = state->xfer_func;
1270 }
1271
1272 return 0;
1273 }
1274
adv7511_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1275 static int adv7511_set_fmt(struct v4l2_subdev *sd,
1276 struct v4l2_subdev_state *sd_state,
1277 struct v4l2_subdev_format *format)
1278 {
1279 struct adv7511_state *state = get_adv7511_state(sd);
1280 /*
1281 * Bitfield namings come the CEA-861-F standard, table 8 "Auxiliary
1282 * Video Information (AVI) InfoFrame Format"
1283 *
1284 * c = Colorimetry
1285 * ec = Extended Colorimetry
1286 * y = RGB or YCbCr
1287 * q = RGB Quantization Range
1288 * yq = YCC Quantization Range
1289 */
1290 u8 c = HDMI_COLORIMETRY_NONE;
1291 u8 ec = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1292 u8 y = HDMI_COLORSPACE_RGB;
1293 u8 q = HDMI_QUANTIZATION_RANGE_DEFAULT;
1294 u8 yq = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
1295 u8 itc = state->content_type != V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1296 u8 cn = itc ? state->content_type : V4L2_DV_IT_CONTENT_TYPE_GRAPHICS;
1297
1298 if (format->pad != 0)
1299 return -EINVAL;
1300 switch (format->format.code) {
1301 case MEDIA_BUS_FMT_UYVY8_1X16:
1302 case MEDIA_BUS_FMT_YUYV8_1X16:
1303 case MEDIA_BUS_FMT_RGB888_1X24:
1304 break;
1305 default:
1306 return -EINVAL;
1307 }
1308
1309 adv7511_fill_format(state, &format->format);
1310 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1311 struct v4l2_mbus_framefmt *fmt;
1312
1313 fmt = v4l2_subdev_state_get_format(sd_state, format->pad);
1314 fmt->code = format->format.code;
1315 fmt->colorspace = format->format.colorspace;
1316 fmt->ycbcr_enc = format->format.ycbcr_enc;
1317 fmt->quantization = format->format.quantization;
1318 fmt->xfer_func = format->format.xfer_func;
1319 return 0;
1320 }
1321
1322 switch (format->format.code) {
1323 case MEDIA_BUS_FMT_UYVY8_1X16:
1324 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x01);
1325 adv7511_wr_and_or(sd, 0x16, 0x03, 0xb8);
1326 y = HDMI_COLORSPACE_YUV422;
1327 break;
1328 case MEDIA_BUS_FMT_YUYV8_1X16:
1329 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x01);
1330 adv7511_wr_and_or(sd, 0x16, 0x03, 0xbc);
1331 y = HDMI_COLORSPACE_YUV422;
1332 break;
1333 case MEDIA_BUS_FMT_RGB888_1X24:
1334 default:
1335 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x00);
1336 adv7511_wr_and_or(sd, 0x16, 0x03, 0x00);
1337 break;
1338 }
1339 state->fmt_code = format->format.code;
1340 state->colorspace = format->format.colorspace;
1341 state->ycbcr_enc = format->format.ycbcr_enc;
1342 state->quantization = format->format.quantization;
1343 state->xfer_func = format->format.xfer_func;
1344
1345 switch (format->format.colorspace) {
1346 case V4L2_COLORSPACE_OPRGB:
1347 c = HDMI_COLORIMETRY_EXTENDED;
1348 ec = y ? HDMI_EXTENDED_COLORIMETRY_OPYCC_601 :
1349 HDMI_EXTENDED_COLORIMETRY_OPRGB;
1350 break;
1351 case V4L2_COLORSPACE_SMPTE170M:
1352 c = y ? HDMI_COLORIMETRY_ITU_601 : HDMI_COLORIMETRY_NONE;
1353 if (y && format->format.ycbcr_enc == V4L2_YCBCR_ENC_XV601) {
1354 c = HDMI_COLORIMETRY_EXTENDED;
1355 ec = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1356 }
1357 break;
1358 case V4L2_COLORSPACE_REC709:
1359 c = y ? HDMI_COLORIMETRY_ITU_709 : HDMI_COLORIMETRY_NONE;
1360 if (y && format->format.ycbcr_enc == V4L2_YCBCR_ENC_XV709) {
1361 c = HDMI_COLORIMETRY_EXTENDED;
1362 ec = HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1363 }
1364 break;
1365 case V4L2_COLORSPACE_SRGB:
1366 c = y ? HDMI_COLORIMETRY_EXTENDED : HDMI_COLORIMETRY_NONE;
1367 ec = y ? HDMI_EXTENDED_COLORIMETRY_S_YCC_601 :
1368 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1369 break;
1370 case V4L2_COLORSPACE_BT2020:
1371 c = HDMI_COLORIMETRY_EXTENDED;
1372 if (y && format->format.ycbcr_enc == V4L2_YCBCR_ENC_BT2020_CONST_LUM)
1373 ec = 5; /* Not yet available in hdmi.h */
1374 else
1375 ec = 6; /* Not yet available in hdmi.h */
1376 break;
1377 default:
1378 break;
1379 }
1380
1381 /*
1382 * CEA-861-F says that for RGB formats the YCC range must match the
1383 * RGB range, although sources should ignore the YCC range.
1384 *
1385 * The RGB quantization range shouldn't be non-zero if the EDID doesn't
1386 * have the Q bit set in the Video Capabilities Data Block, however this
1387 * isn't checked at the moment. The assumption is that the application
1388 * knows the EDID and can detect this.
1389 *
1390 * The same is true for the YCC quantization range: non-standard YCC
1391 * quantization ranges should only be sent if the EDID has the YQ bit
1392 * set in the Video Capabilities Data Block.
1393 */
1394 switch (format->format.quantization) {
1395 case V4L2_QUANTIZATION_FULL_RANGE:
1396 q = y ? HDMI_QUANTIZATION_RANGE_DEFAULT :
1397 HDMI_QUANTIZATION_RANGE_FULL;
1398 yq = q ? q - 1 : HDMI_YCC_QUANTIZATION_RANGE_FULL;
1399 break;
1400 case V4L2_QUANTIZATION_LIM_RANGE:
1401 q = y ? HDMI_QUANTIZATION_RANGE_DEFAULT :
1402 HDMI_QUANTIZATION_RANGE_LIMITED;
1403 yq = q ? q - 1 : HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
1404 break;
1405 }
1406
1407 adv7511_wr_and_or(sd, 0x4a, 0xbf, 0);
1408 adv7511_wr_and_or(sd, 0x55, 0x9f, y << 5);
1409 adv7511_wr_and_or(sd, 0x56, 0x3f, c << 6);
1410 adv7511_wr_and_or(sd, 0x57, 0x83, (ec << 4) | (q << 2) | (itc << 7));
1411 adv7511_wr_and_or(sd, 0x59, 0x0f, (yq << 6) | (cn << 4));
1412 adv7511_wr_and_or(sd, 0x4a, 0xff, 1);
1413 adv7511_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
1414
1415 return 0;
1416 }
1417
1418 static const struct v4l2_subdev_pad_ops adv7511_pad_ops = {
1419 .get_edid = adv7511_get_edid,
1420 .enum_mbus_code = adv7511_enum_mbus_code,
1421 .get_fmt = adv7511_get_fmt,
1422 .set_fmt = adv7511_set_fmt,
1423 .s_dv_timings = adv7511_s_dv_timings,
1424 .g_dv_timings = adv7511_g_dv_timings,
1425 .enum_dv_timings = adv7511_enum_dv_timings,
1426 .dv_timings_cap = adv7511_dv_timings_cap,
1427 };
1428
1429 /* --------------------- SUBDEV OPS --------------------------------------- */
1430
1431 static const struct v4l2_subdev_ops adv7511_ops = {
1432 .core = &adv7511_core_ops,
1433 .pad = &adv7511_pad_ops,
1434 .video = &adv7511_video_ops,
1435 .audio = &adv7511_audio_ops,
1436 };
1437
1438 /* ----------------------------------------------------------------------- */
adv7511_dbg_dump_edid(int lvl,int debug,struct v4l2_subdev * sd,int segment,u8 * buf)1439 static void adv7511_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd, int segment, u8 *buf)
1440 {
1441 if (debug >= lvl) {
1442 int i, j;
1443 v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment);
1444 for (i = 0; i < 256; i += 16) {
1445 u8 b[128];
1446 u8 *bp = b;
1447 if (i == 128)
1448 v4l2_dbg(lvl, debug, sd, "\n");
1449 for (j = i; j < i + 16; j++) {
1450 sprintf(bp, "0x%02x, ", buf[j]);
1451 bp += 6;
1452 }
1453 bp[0] = '\0';
1454 v4l2_dbg(lvl, debug, sd, "%s\n", b);
1455 }
1456 }
1457 }
1458
adv7511_notify_no_edid(struct v4l2_subdev * sd)1459 static void adv7511_notify_no_edid(struct v4l2_subdev *sd)
1460 {
1461 struct adv7511_state *state = get_adv7511_state(sd);
1462 struct adv7511_edid_detect ed;
1463
1464 /* We failed to read the EDID, so send an event for this. */
1465 ed.present = false;
1466 ed.segment = adv7511_rd(sd, 0xc4);
1467 ed.phys_addr = CEC_PHYS_ADDR_INVALID;
1468 cec_s_phys_addr(state->cec_adap, ed.phys_addr, false);
1469 v4l2_subdev_notify(sd, ADV7511_EDID_DETECT, (void *)&ed);
1470 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, 0x0);
1471 }
1472
adv7511_edid_handler(struct work_struct * work)1473 static void adv7511_edid_handler(struct work_struct *work)
1474 {
1475 struct delayed_work *dwork = to_delayed_work(work);
1476 struct adv7511_state *state = container_of(dwork, struct adv7511_state, edid_handler);
1477 struct v4l2_subdev *sd = &state->sd;
1478
1479 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1480
1481 if (adv7511_check_edid_status(sd)) {
1482 /* Return if we received the EDID. */
1483 return;
1484 }
1485
1486 if (adv7511_have_hotplug(sd)) {
1487 /* We must retry reading the EDID several times, it is possible
1488 * that initially the EDID couldn't be read due to i2c errors
1489 * (DVI connectors are particularly prone to this problem). */
1490 if (state->edid.read_retries) {
1491 state->edid.read_retries--;
1492 v4l2_dbg(1, debug, sd, "%s: edid read failed\n", __func__);
1493 state->have_monitor = false;
1494 adv7511_s_power(sd, false);
1495 adv7511_s_power(sd, true);
1496 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY);
1497 return;
1498 }
1499 }
1500
1501 /* We failed to read the EDID, so send an event for this. */
1502 adv7511_notify_no_edid(sd);
1503 v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__);
1504 }
1505
adv7511_audio_setup(struct v4l2_subdev * sd)1506 static void adv7511_audio_setup(struct v4l2_subdev *sd)
1507 {
1508 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1509
1510 adv7511_s_i2s_clock_freq(sd, 48000);
1511 adv7511_s_clock_freq(sd, 48000);
1512 adv7511_s_routing(sd, 0, 0, 0);
1513 }
1514
1515 /* Configure hdmi transmitter. */
adv7511_setup(struct v4l2_subdev * sd)1516 static void adv7511_setup(struct v4l2_subdev *sd)
1517 {
1518 struct adv7511_state *state = get_adv7511_state(sd);
1519 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1520
1521 /* Input format: RGB 4:4:4 */
1522 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x0);
1523 /* Output format: RGB 4:4:4 */
1524 adv7511_wr_and_or(sd, 0x16, 0x7f, 0x0);
1525 /* 1st order interpolation 4:2:2 -> 4:4:4 up conversion, Aspect ratio: 16:9 */
1526 adv7511_wr_and_or(sd, 0x17, 0xf9, 0x06);
1527 /* Disable pixel repetition */
1528 adv7511_wr_and_or(sd, 0x3b, 0x9f, 0x0);
1529 /* Disable CSC */
1530 adv7511_wr_and_or(sd, 0x18, 0x7f, 0x0);
1531 /* Output format: RGB 4:4:4, Active Format Information is valid,
1532 * underscanned */
1533 adv7511_wr_and_or(sd, 0x55, 0x9c, 0x12);
1534 /* AVI Info frame packet enable, Audio Info frame disable */
1535 adv7511_wr_and_or(sd, 0x44, 0xe7, 0x10);
1536 /* Colorimetry, Active format aspect ratio: same as picure. */
1537 adv7511_wr(sd, 0x56, 0xa8);
1538 /* No encryption */
1539 adv7511_wr_and_or(sd, 0xaf, 0xed, 0x0);
1540
1541 /* Positive clk edge capture for input video clock */
1542 adv7511_wr_and_or(sd, 0xba, 0x1f, 0x60);
1543
1544 adv7511_audio_setup(sd);
1545
1546 v4l2_ctrl_handler_setup(&state->hdl);
1547 }
1548
adv7511_notify_monitor_detect(struct v4l2_subdev * sd)1549 static void adv7511_notify_monitor_detect(struct v4l2_subdev *sd)
1550 {
1551 struct adv7511_monitor_detect mdt;
1552 struct adv7511_state *state = get_adv7511_state(sd);
1553
1554 mdt.present = state->have_monitor;
1555 v4l2_subdev_notify(sd, ADV7511_MONITOR_DETECT, (void *)&mdt);
1556 }
1557
adv7511_check_monitor_present_status(struct v4l2_subdev * sd)1558 static void adv7511_check_monitor_present_status(struct v4l2_subdev *sd)
1559 {
1560 struct adv7511_state *state = get_adv7511_state(sd);
1561 /* read hotplug and rx-sense state */
1562 u8 status = adv7511_rd(sd, 0x42);
1563
1564 v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n",
1565 __func__,
1566 status,
1567 status & MASK_ADV7511_HPD_DETECT ? ", hotplug" : "",
1568 status & MASK_ADV7511_MSEN_DETECT ? ", rx-sense" : "");
1569
1570 /* update read only ctrls */
1571 v4l2_ctrl_s_ctrl(state->hotplug_ctrl, adv7511_have_hotplug(sd) ? 0x1 : 0x0);
1572 v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, adv7511_have_rx_sense(sd) ? 0x1 : 0x0);
1573
1574 if ((status & MASK_ADV7511_HPD_DETECT) && ((status & MASK_ADV7511_MSEN_DETECT) || state->edid.segments)) {
1575 v4l2_dbg(1, debug, sd, "%s: hotplug and (rx-sense or edid)\n", __func__);
1576 if (!state->have_monitor) {
1577 v4l2_dbg(1, debug, sd, "%s: monitor detected\n", __func__);
1578 state->have_monitor = true;
1579 adv7511_set_isr(sd, true);
1580 if (!adv7511_s_power(sd, true)) {
1581 v4l2_dbg(1, debug, sd, "%s: monitor detected, powerup failed\n", __func__);
1582 return;
1583 }
1584 adv7511_setup(sd);
1585 adv7511_notify_monitor_detect(sd);
1586 state->edid.read_retries = EDID_MAX_RETRIES;
1587 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY);
1588 }
1589 } else if (status & MASK_ADV7511_HPD_DETECT) {
1590 v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__);
1591 state->edid.read_retries = EDID_MAX_RETRIES;
1592 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY);
1593 } else if (!(status & MASK_ADV7511_HPD_DETECT)) {
1594 v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__);
1595 if (state->have_monitor) {
1596 v4l2_dbg(1, debug, sd, "%s: monitor not detected\n", __func__);
1597 state->have_monitor = false;
1598 adv7511_notify_monitor_detect(sd);
1599 }
1600 adv7511_s_power(sd, false);
1601 memset(&state->edid, 0, sizeof(struct adv7511_state_edid));
1602 adv7511_notify_no_edid(sd);
1603 }
1604 }
1605
edid_block_verify_crc(u8 * edid_block)1606 static bool edid_block_verify_crc(u8 *edid_block)
1607 {
1608 u8 sum = 0;
1609 int i;
1610
1611 for (i = 0; i < 128; i++)
1612 sum += edid_block[i];
1613 return sum == 0;
1614 }
1615
edid_verify_crc(struct v4l2_subdev * sd,u32 segment)1616 static bool edid_verify_crc(struct v4l2_subdev *sd, u32 segment)
1617 {
1618 struct adv7511_state *state = get_adv7511_state(sd);
1619 u32 blocks = state->edid.blocks;
1620 u8 *data = state->edid.data;
1621
1622 if (!edid_block_verify_crc(&data[segment * 256]))
1623 return false;
1624 if ((segment + 1) * 2 <= blocks)
1625 return edid_block_verify_crc(&data[segment * 256 + 128]);
1626 return true;
1627 }
1628
edid_verify_header(struct v4l2_subdev * sd,u32 segment)1629 static bool edid_verify_header(struct v4l2_subdev *sd, u32 segment)
1630 {
1631 static const u8 hdmi_header[] = {
1632 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1633 };
1634 struct adv7511_state *state = get_adv7511_state(sd);
1635 u8 *data = state->edid.data;
1636
1637 if (segment != 0)
1638 return true;
1639 return !memcmp(data, hdmi_header, sizeof(hdmi_header));
1640 }
1641
adv7511_check_edid_status(struct v4l2_subdev * sd)1642 static bool adv7511_check_edid_status(struct v4l2_subdev *sd)
1643 {
1644 struct adv7511_state *state = get_adv7511_state(sd);
1645 u8 edidRdy = adv7511_rd(sd, 0xc5);
1646
1647 v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n",
1648 __func__, EDID_MAX_RETRIES - state->edid.read_retries);
1649
1650 if (state->edid.complete)
1651 return true;
1652
1653 if (edidRdy & MASK_ADV7511_EDID_RDY) {
1654 int segment = adv7511_rd(sd, 0xc4);
1655 struct adv7511_edid_detect ed;
1656 int err;
1657
1658 if (segment >= EDID_MAX_SEGM) {
1659 v4l2_err(sd, "edid segment number too big\n");
1660 return false;
1661 }
1662 v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment);
1663 err = adv7511_edid_rd(sd, 256, &state->edid.data[segment * 256]);
1664 if (!err) {
1665 adv7511_dbg_dump_edid(2, debug, sd, segment, &state->edid.data[segment * 256]);
1666 if (segment == 0) {
1667 state->edid.blocks = state->edid.data[0x7e] + 1;
1668 v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n",
1669 __func__, state->edid.blocks);
1670 }
1671 }
1672
1673 if (err || !edid_verify_crc(sd, segment) || !edid_verify_header(sd, segment)) {
1674 /* Couldn't read EDID or EDID is invalid. Force retry! */
1675 if (!err)
1676 v4l2_err(sd, "%s: edid crc or header error\n", __func__);
1677 state->have_monitor = false;
1678 adv7511_s_power(sd, false);
1679 adv7511_s_power(sd, true);
1680 return false;
1681 }
1682 /* one more segment read ok */
1683 state->edid.segments = segment + 1;
1684 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, 0x1);
1685 if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) {
1686 /* Request next EDID segment */
1687 v4l2_dbg(1, debug, sd, "%s: request segment %d\n", __func__, state->edid.segments);
1688 adv7511_wr(sd, 0xc9, 0xf);
1689 adv7511_wr(sd, 0xc4, state->edid.segments);
1690 state->edid.read_retries = EDID_MAX_RETRIES;
1691 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY);
1692 return false;
1693 }
1694
1695 v4l2_dbg(1, debug, sd, "%s: edid complete with %d segment(s)\n", __func__, state->edid.segments);
1696 state->edid.complete = true;
1697 ed.phys_addr = cec_get_edid_phys_addr(state->edid.data,
1698 state->edid.segments * 256,
1699 NULL);
1700 /* report when we have all segments
1701 but report only for segment 0
1702 */
1703 ed.present = true;
1704 ed.segment = 0;
1705 state->edid_detect_counter++;
1706 cec_s_phys_addr(state->cec_adap, ed.phys_addr, false);
1707 v4l2_subdev_notify(sd, ADV7511_EDID_DETECT, (void *)&ed);
1708 return ed.present;
1709 }
1710
1711 return false;
1712 }
1713
1714 static ssize_t
adv7511_debugfs_if_read(u32 type,void * priv,struct file * filp,char __user * ubuf,size_t count,loff_t * ppos)1715 adv7511_debugfs_if_read(u32 type, void *priv,
1716 struct file *filp, char __user *ubuf, size_t count, loff_t *ppos)
1717 {
1718 u8 buf[V4L2_DEBUGFS_IF_MAX_LEN] = {};
1719 struct v4l2_subdev *sd = priv;
1720 int index;
1721 int len;
1722
1723 switch (type) {
1724 case V4L2_DEBUGFS_IF_AVI:
1725 index = 0;
1726 break;
1727 case V4L2_DEBUGFS_IF_AUDIO:
1728 index = 1;
1729 break;
1730 case V4L2_DEBUGFS_IF_SPD:
1731 index = 2;
1732 break;
1733 default:
1734 return 0;
1735 }
1736 len = read_infoframe(sd, &cri[index], buf);
1737 if (len > 0)
1738 len = simple_read_from_buffer(ubuf, count, ppos, buf, len);
1739 return len < 0 ? 0 : len;
1740 }
1741
adv7511_registered(struct v4l2_subdev * sd)1742 static int adv7511_registered(struct v4l2_subdev *sd)
1743 {
1744 struct adv7511_state *state = get_adv7511_state(sd);
1745 struct i2c_client *client = v4l2_get_subdevdata(sd);
1746 int err;
1747
1748 err = cec_register_adapter(state->cec_adap, &client->dev);
1749 if (err) {
1750 cec_delete_adapter(state->cec_adap);
1751 return err;
1752 }
1753
1754 state->debugfs_dir = debugfs_create_dir(sd->name, v4l2_debugfs_root());
1755 state->infoframes = v4l2_debugfs_if_alloc(state->debugfs_dir,
1756 V4L2_DEBUGFS_IF_AVI | V4L2_DEBUGFS_IF_AUDIO |
1757 V4L2_DEBUGFS_IF_SPD, sd, adv7511_debugfs_if_read);
1758 return 0;
1759 }
1760
adv7511_unregistered(struct v4l2_subdev * sd)1761 static void adv7511_unregistered(struct v4l2_subdev *sd)
1762 {
1763 struct adv7511_state *state = get_adv7511_state(sd);
1764
1765 cec_unregister_adapter(state->cec_adap);
1766 v4l2_debugfs_if_free(state->infoframes);
1767 state->infoframes = NULL;
1768 debugfs_remove_recursive(state->debugfs_dir);
1769 state->debugfs_dir = NULL;
1770 }
1771
1772 static const struct v4l2_subdev_internal_ops adv7511_int_ops = {
1773 .registered = adv7511_registered,
1774 .unregistered = adv7511_unregistered,
1775 };
1776
1777 /* ----------------------------------------------------------------------- */
1778 /* Setup ADV7511 */
adv7511_init_setup(struct v4l2_subdev * sd)1779 static void adv7511_init_setup(struct v4l2_subdev *sd)
1780 {
1781 struct adv7511_state *state = get_adv7511_state(sd);
1782 struct adv7511_state_edid *edid = &state->edid;
1783 u32 cec_clk = state->pdata.cec_clk;
1784 u8 ratio;
1785
1786 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1787
1788 /* clear all interrupts */
1789 adv7511_wr(sd, 0x96, 0xff);
1790 adv7511_wr(sd, 0x97, 0xff);
1791 /*
1792 * Stop HPD from resetting a lot of registers.
1793 * It might leave the chip in a partly un-initialized state,
1794 * in particular with regards to hotplug bounces.
1795 */
1796 adv7511_wr_and_or(sd, 0xd6, 0x3f, 0xc0);
1797 memset(edid, 0, sizeof(struct adv7511_state_edid));
1798 state->have_monitor = false;
1799 adv7511_set_isr(sd, false);
1800 adv7511_s_stream(sd, false);
1801 adv7511_s_audio_stream(sd, false);
1802
1803 if (state->i2c_cec == NULL)
1804 return;
1805
1806 v4l2_dbg(1, debug, sd, "%s: cec_clk %d\n", __func__, cec_clk);
1807
1808 /* cec soft reset */
1809 adv7511_cec_write(sd, 0x50, 0x01);
1810 adv7511_cec_write(sd, 0x50, 0x00);
1811
1812 /* legacy mode */
1813 adv7511_cec_write(sd, 0x4a, 0x00);
1814 adv7511_cec_write(sd, 0x4a, 0x07);
1815
1816 if (cec_clk % 750000 != 0)
1817 v4l2_err(sd, "%s: cec_clk %d, not multiple of 750 Khz\n",
1818 __func__, cec_clk);
1819
1820 ratio = (cec_clk / 750000) - 1;
1821 adv7511_cec_write(sd, 0x4e, ratio << 2);
1822 }
1823
adv7511_probe(struct i2c_client * client)1824 static int adv7511_probe(struct i2c_client *client)
1825 {
1826 struct adv7511_state *state;
1827 struct adv7511_platform_data *pdata = client->dev.platform_data;
1828 struct v4l2_ctrl_handler *hdl;
1829 struct v4l2_subdev *sd;
1830 u8 chip_id[2];
1831 int err = -EIO;
1832
1833 /* Check if the adapter supports the needed features */
1834 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1835 return -EIO;
1836
1837 state = devm_kzalloc(&client->dev, sizeof(struct adv7511_state), GFP_KERNEL);
1838 if (!state)
1839 return -ENOMEM;
1840
1841 /* Platform data */
1842 if (!pdata) {
1843 v4l_err(client, "No platform data!\n");
1844 return -ENODEV;
1845 }
1846 memcpy(&state->pdata, pdata, sizeof(state->pdata));
1847 state->fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
1848 state->colorspace = V4L2_COLORSPACE_SRGB;
1849
1850 sd = &state->sd;
1851
1852 v4l2_dbg(1, debug, sd, "detecting adv7511 client on address 0x%x\n",
1853 client->addr << 1);
1854
1855 v4l2_i2c_subdev_init(sd, client, &adv7511_ops);
1856 sd->internal_ops = &adv7511_int_ops;
1857
1858 hdl = &state->hdl;
1859 v4l2_ctrl_handler_init(hdl, 10);
1860 /* add in ascending ID order */
1861 state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7511_ctrl_ops,
1862 V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI,
1863 0, V4L2_DV_TX_MODE_DVI_D);
1864 state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1865 V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0);
1866 state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1867 V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0);
1868 state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1869 V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0);
1870 state->rgb_quantization_range_ctrl =
1871 v4l2_ctrl_new_std_menu(hdl, &adv7511_ctrl_ops,
1872 V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1873 0, V4L2_DV_RGB_RANGE_AUTO);
1874 state->content_type_ctrl =
1875 v4l2_ctrl_new_std_menu(hdl, &adv7511_ctrl_ops,
1876 V4L2_CID_DV_TX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
1877 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
1878 sd->ctrl_handler = hdl;
1879 if (hdl->error) {
1880 err = hdl->error;
1881 goto err_hdl;
1882 }
1883 state->pad.flags = MEDIA_PAD_FL_SINK;
1884 sd->entity.function = MEDIA_ENT_F_DV_ENCODER;
1885 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
1886 if (err)
1887 goto err_hdl;
1888
1889 /* EDID and CEC i2c addr */
1890 state->i2c_edid_addr = state->pdata.i2c_edid << 1;
1891 state->i2c_cec_addr = state->pdata.i2c_cec << 1;
1892 state->i2c_pktmem_addr = state->pdata.i2c_pktmem << 1;
1893
1894 state->chip_revision = adv7511_rd(sd, 0x0);
1895 chip_id[0] = adv7511_rd(sd, 0xf5);
1896 chip_id[1] = adv7511_rd(sd, 0xf6);
1897 if (chip_id[0] != 0x75 || chip_id[1] != 0x11) {
1898 v4l2_err(sd, "chip_id != 0x7511, read 0x%02x%02x\n", chip_id[0],
1899 chip_id[1]);
1900 err = -EIO;
1901 goto err_entity;
1902 }
1903
1904 state->i2c_edid = i2c_new_dummy_device(client->adapter,
1905 state->i2c_edid_addr >> 1);
1906 if (IS_ERR(state->i2c_edid)) {
1907 v4l2_err(sd, "failed to register edid i2c client\n");
1908 err = PTR_ERR(state->i2c_edid);
1909 goto err_entity;
1910 }
1911
1912 adv7511_wr(sd, 0xe1, state->i2c_cec_addr);
1913 if (state->pdata.cec_clk < 3000000 ||
1914 state->pdata.cec_clk > 100000000) {
1915 v4l2_err(sd, "%s: cec_clk %u outside range, disabling cec\n",
1916 __func__, state->pdata.cec_clk);
1917 state->pdata.cec_clk = 0;
1918 }
1919
1920 if (state->pdata.cec_clk) {
1921 state->i2c_cec = i2c_new_dummy_device(client->adapter,
1922 state->i2c_cec_addr >> 1);
1923 if (IS_ERR(state->i2c_cec)) {
1924 v4l2_err(sd, "failed to register cec i2c client\n");
1925 err = PTR_ERR(state->i2c_cec);
1926 goto err_unreg_edid;
1927 }
1928 adv7511_wr(sd, 0xe2, 0x00); /* power up cec section */
1929 } else {
1930 adv7511_wr(sd, 0xe2, 0x01); /* power down cec section */
1931 }
1932
1933 state->i2c_pktmem = i2c_new_dummy_device(client->adapter, state->i2c_pktmem_addr >> 1);
1934 if (IS_ERR(state->i2c_pktmem)) {
1935 v4l2_err(sd, "failed to register pktmem i2c client\n");
1936 err = PTR_ERR(state->i2c_pktmem);
1937 goto err_unreg_cec;
1938 }
1939
1940 state->work_queue = create_singlethread_workqueue(sd->name);
1941 if (state->work_queue == NULL) {
1942 v4l2_err(sd, "could not create workqueue\n");
1943 err = -ENOMEM;
1944 goto err_unreg_pktmem;
1945 }
1946
1947 INIT_DELAYED_WORK(&state->edid_handler, adv7511_edid_handler);
1948
1949 adv7511_init_setup(sd);
1950
1951 #if IS_ENABLED(CONFIG_VIDEO_ADV7511_CEC)
1952 state->cec_adap = cec_allocate_adapter(&adv7511_cec_adap_ops,
1953 state, dev_name(&client->dev), CEC_CAP_DEFAULTS,
1954 ADV7511_MAX_ADDRS);
1955 err = PTR_ERR_OR_ZERO(state->cec_adap);
1956 if (err) {
1957 destroy_workqueue(state->work_queue);
1958 goto err_unreg_pktmem;
1959 }
1960 #endif
1961
1962 adv7511_set_isr(sd, true);
1963 adv7511_check_monitor_present_status(sd);
1964
1965 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1966 client->addr << 1, client->adapter->name);
1967 return 0;
1968
1969 err_unreg_pktmem:
1970 i2c_unregister_device(state->i2c_pktmem);
1971 err_unreg_cec:
1972 i2c_unregister_device(state->i2c_cec);
1973 err_unreg_edid:
1974 i2c_unregister_device(state->i2c_edid);
1975 err_entity:
1976 media_entity_cleanup(&sd->entity);
1977 err_hdl:
1978 v4l2_ctrl_handler_free(&state->hdl);
1979 return err;
1980 }
1981
1982 /* ----------------------------------------------------------------------- */
1983
adv7511_remove(struct i2c_client * client)1984 static void adv7511_remove(struct i2c_client *client)
1985 {
1986 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1987 struct adv7511_state *state = get_adv7511_state(sd);
1988
1989 state->chip_revision = -1;
1990
1991 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
1992 client->addr << 1, client->adapter->name);
1993
1994 adv7511_set_isr(sd, false);
1995 adv7511_init_setup(sd);
1996 cancel_delayed_work_sync(&state->edid_handler);
1997 i2c_unregister_device(state->i2c_edid);
1998 i2c_unregister_device(state->i2c_cec);
1999 i2c_unregister_device(state->i2c_pktmem);
2000 destroy_workqueue(state->work_queue);
2001 v4l2_device_unregister_subdev(sd);
2002 media_entity_cleanup(&sd->entity);
2003 v4l2_ctrl_handler_free(sd->ctrl_handler);
2004 }
2005
2006 /* ----------------------------------------------------------------------- */
2007
2008 static const struct i2c_device_id adv7511_id[] = {
2009 { "adv7511-v4l2" },
2010 { }
2011 };
2012 MODULE_DEVICE_TABLE(i2c, adv7511_id);
2013
2014 static struct i2c_driver adv7511_driver = {
2015 .driver = {
2016 .name = "adv7511-v4l2",
2017 },
2018 .probe = adv7511_probe,
2019 .remove = adv7511_remove,
2020 .id_table = adv7511_id,
2021 };
2022
2023 module_i2c_driver(adv7511_driver);
2024