1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2023 Intel Corporation
4 */
5
6 #include <drm/intel/i915_pciids.h>
7 #include <drm/drm_color_mgmt.h>
8 #include <linux/pci.h>
9
10 #include "i915_drv.h"
11 #include "i915_reg.h"
12 #include "intel_de.h"
13 #include "intel_display.h"
14 #include "intel_display_device.h"
15 #include "intel_display_params.h"
16 #include "intel_display_power.h"
17 #include "intel_display_reg_defs.h"
18 #include "intel_fbc.h"
19 #include "intel_step.h"
20
21 __diag_push();
22 __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info");
23
24 struct stepping_desc {
25 const enum intel_step *map; /* revid to step map */
26 size_t size; /* map size */
27 };
28
29 #define STEP_INFO(_map) \
30 .step_info.map = _map, \
31 .step_info.size = ARRAY_SIZE(_map)
32
33 struct subplatform_desc {
34 enum intel_display_subplatform subplatform;
35 const char *name;
36 const u16 *pciidlist;
37 struct stepping_desc step_info;
38 };
39
40 struct platform_desc {
41 enum intel_display_platform platform;
42 const char *name;
43 const struct subplatform_desc *subplatforms;
44 const struct intel_display_device_info *info; /* NULL for GMD ID */
45 struct stepping_desc step_info;
46 };
47
48 #define PLATFORM(_platform) \
49 .platform = (INTEL_DISPLAY_##_platform), \
50 .name = #_platform
51
52 #define ID(id) (id)
53
54 static const struct intel_display_device_info no_display = {};
55
56 #define PIPE_A_OFFSET 0x70000
57 #define PIPE_B_OFFSET 0x71000
58 #define PIPE_C_OFFSET 0x72000
59 #define PIPE_D_OFFSET 0x73000
60 #define CHV_PIPE_C_OFFSET 0x74000
61 /*
62 * There's actually no pipe EDP. Some pipe registers have
63 * simply shifted from the pipe to the transcoder, while
64 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
65 * to access such registers in transcoder EDP.
66 */
67 #define PIPE_EDP_OFFSET 0x7f000
68
69 /* ICL DSI 0 and 1 */
70 #define PIPE_DSI0_OFFSET 0x7b000
71 #define PIPE_DSI1_OFFSET 0x7b800
72
73 #define TRANSCODER_A_OFFSET 0x60000
74 #define TRANSCODER_B_OFFSET 0x61000
75 #define TRANSCODER_C_OFFSET 0x62000
76 #define CHV_TRANSCODER_C_OFFSET 0x63000
77 #define TRANSCODER_D_OFFSET 0x63000
78 #define TRANSCODER_EDP_OFFSET 0x6f000
79 #define TRANSCODER_DSI0_OFFSET 0x6b000
80 #define TRANSCODER_DSI1_OFFSET 0x6b800
81
82 #define CURSOR_A_OFFSET 0x70080
83 #define CURSOR_B_OFFSET 0x700c0
84 #define CHV_CURSOR_C_OFFSET 0x700e0
85 #define IVB_CURSOR_B_OFFSET 0x71080
86 #define IVB_CURSOR_C_OFFSET 0x72080
87 #define TGL_CURSOR_D_OFFSET 0x73080
88
89 #define I845_PIPE_OFFSETS \
90 .pipe_offsets = { \
91 [TRANSCODER_A] = PIPE_A_OFFSET, \
92 }, \
93 .trans_offsets = { \
94 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
95 }
96
97 #define I9XX_PIPE_OFFSETS \
98 .pipe_offsets = { \
99 [TRANSCODER_A] = PIPE_A_OFFSET, \
100 [TRANSCODER_B] = PIPE_B_OFFSET, \
101 }, \
102 .trans_offsets = { \
103 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
104 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
105 }
106
107 #define IVB_PIPE_OFFSETS \
108 .pipe_offsets = { \
109 [TRANSCODER_A] = PIPE_A_OFFSET, \
110 [TRANSCODER_B] = PIPE_B_OFFSET, \
111 [TRANSCODER_C] = PIPE_C_OFFSET, \
112 }, \
113 .trans_offsets = { \
114 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
115 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
116 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
117 }
118
119 #define HSW_PIPE_OFFSETS \
120 .pipe_offsets = { \
121 [TRANSCODER_A] = PIPE_A_OFFSET, \
122 [TRANSCODER_B] = PIPE_B_OFFSET, \
123 [TRANSCODER_C] = PIPE_C_OFFSET, \
124 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
125 }, \
126 .trans_offsets = { \
127 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
128 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
129 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
130 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
131 }
132
133 #define CHV_PIPE_OFFSETS \
134 .pipe_offsets = { \
135 [TRANSCODER_A] = PIPE_A_OFFSET, \
136 [TRANSCODER_B] = PIPE_B_OFFSET, \
137 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
138 }, \
139 .trans_offsets = { \
140 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
141 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
142 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
143 }
144
145 #define I845_CURSOR_OFFSETS \
146 .cursor_offsets = { \
147 [PIPE_A] = CURSOR_A_OFFSET, \
148 }
149
150 #define I9XX_CURSOR_OFFSETS \
151 .cursor_offsets = { \
152 [PIPE_A] = CURSOR_A_OFFSET, \
153 [PIPE_B] = CURSOR_B_OFFSET, \
154 }
155
156 #define CHV_CURSOR_OFFSETS \
157 .cursor_offsets = { \
158 [PIPE_A] = CURSOR_A_OFFSET, \
159 [PIPE_B] = CURSOR_B_OFFSET, \
160 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
161 }
162
163 #define IVB_CURSOR_OFFSETS \
164 .cursor_offsets = { \
165 [PIPE_A] = CURSOR_A_OFFSET, \
166 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
167 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
168 }
169
170 #define TGL_CURSOR_OFFSETS \
171 .cursor_offsets = { \
172 [PIPE_A] = CURSOR_A_OFFSET, \
173 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
174 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
175 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
176 }
177
178 #define I845_COLORS \
179 .color = { .gamma_lut_size = 256 }
180 #define I9XX_COLORS \
181 .color = { .gamma_lut_size = 129, \
182 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
183 }
184 #define ILK_COLORS \
185 .color = { .gamma_lut_size = 1024 }
186 #define IVB_COLORS \
187 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
188 #define CHV_COLORS \
189 .color = { \
190 .degamma_lut_size = 65, .gamma_lut_size = 257, \
191 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
192 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
193 }
194 #define GLK_COLORS \
195 .color = { \
196 .degamma_lut_size = 33, .gamma_lut_size = 1024, \
197 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
198 DRM_COLOR_LUT_EQUAL_CHANNELS, \
199 }
200 #define ICL_COLORS \
201 .color = { \
202 .degamma_lut_size = 33, .gamma_lut_size = 262145, \
203 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
204 DRM_COLOR_LUT_EQUAL_CHANNELS, \
205 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
206 }
207
208 #define I830_DISPLAY \
209 .has_overlay = 1, \
210 .cursor_needs_physical = 1, \
211 .overlay_needs_physical = 1, \
212 .has_gmch = 1, \
213 I9XX_PIPE_OFFSETS, \
214 I9XX_CURSOR_OFFSETS, \
215 I9XX_COLORS, \
216 \
217 .__runtime_defaults.ip.ver = 2, \
218 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
219 .__runtime_defaults.cpu_transcoder_mask = \
220 BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
221
222 #define I845_DISPLAY \
223 .has_overlay = 1, \
224 .overlay_needs_physical = 1, \
225 .has_gmch = 1, \
226 I845_PIPE_OFFSETS, \
227 I845_CURSOR_OFFSETS, \
228 I845_COLORS, \
229 \
230 .__runtime_defaults.ip.ver = 2, \
231 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
232 .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
233
234 static const struct platform_desc i830_desc = {
235 PLATFORM(I830),
236 .info = &(const struct intel_display_device_info) {
237 I830_DISPLAY,
238
239 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */
240 },
241 };
242
243 static const struct platform_desc i845_desc = {
244 PLATFORM(I845G),
245 .info = &(const struct intel_display_device_info) {
246 I845_DISPLAY,
247
248 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
249 },
250 };
251
252 static const struct platform_desc i85x_desc = {
253 PLATFORM(I85X),
254 .info = &(const struct intel_display_device_info) {
255 I830_DISPLAY,
256
257 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
258 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
259 },
260 };
261
262 static const struct platform_desc i865g_desc = {
263 PLATFORM(I865G),
264 .info = &(const struct intel_display_device_info) {
265 I845_DISPLAY,
266
267 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
268 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
269 },
270 };
271
272 #define GEN3_DISPLAY \
273 .has_gmch = 1, \
274 .has_overlay = 1, \
275 I9XX_PIPE_OFFSETS, \
276 I9XX_CURSOR_OFFSETS, \
277 \
278 .__runtime_defaults.ip.ver = 3, \
279 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
280 .__runtime_defaults.cpu_transcoder_mask = \
281 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
282 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
283
284 static const struct platform_desc i915g_desc = {
285 PLATFORM(I915G),
286 .info = &(const struct intel_display_device_info) {
287 GEN3_DISPLAY,
288 I845_COLORS,
289 .cursor_needs_physical = 1,
290 .overlay_needs_physical = 1,
291 },
292 };
293
294 static const struct platform_desc i915gm_desc = {
295 PLATFORM(I915GM),
296 .info = &(const struct intel_display_device_info) {
297 GEN3_DISPLAY,
298 I9XX_COLORS,
299 .cursor_needs_physical = 1,
300 .overlay_needs_physical = 1,
301 .supports_tv = 1,
302
303 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
304 },
305 };
306
307 static const struct platform_desc i945g_desc = {
308 PLATFORM(I945G),
309 .info = &(const struct intel_display_device_info) {
310 GEN3_DISPLAY,
311 I845_COLORS,
312 .has_hotplug = 1,
313 .cursor_needs_physical = 1,
314 .overlay_needs_physical = 1,
315 },
316 };
317
318 static const struct platform_desc i945gm_desc = {
319 PLATFORM(I915GM),
320 .info = &(const struct intel_display_device_info) {
321 GEN3_DISPLAY,
322 I9XX_COLORS,
323 .has_hotplug = 1,
324 .cursor_needs_physical = 1,
325 .overlay_needs_physical = 1,
326 .supports_tv = 1,
327
328 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
329 },
330 };
331
332 static const struct platform_desc g33_desc = {
333 PLATFORM(G33),
334 .info = &(const struct intel_display_device_info) {
335 GEN3_DISPLAY,
336 I845_COLORS,
337 .has_hotplug = 1,
338 },
339 };
340
341 static const struct platform_desc pnv_desc = {
342 PLATFORM(PINEVIEW),
343 .info = &(const struct intel_display_device_info) {
344 GEN3_DISPLAY,
345 I9XX_COLORS,
346 .has_hotplug = 1,
347 },
348 };
349
350 #define GEN4_DISPLAY \
351 .has_hotplug = 1, \
352 .has_gmch = 1, \
353 I9XX_PIPE_OFFSETS, \
354 I9XX_CURSOR_OFFSETS, \
355 I9XX_COLORS, \
356 \
357 .__runtime_defaults.ip.ver = 4, \
358 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
359 .__runtime_defaults.cpu_transcoder_mask = \
360 BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
361
362 static const struct platform_desc i965g_desc = {
363 PLATFORM(I965G),
364 .info = &(const struct intel_display_device_info) {
365 GEN4_DISPLAY,
366 .has_overlay = 1,
367
368 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
369 },
370 };
371
372 static const struct platform_desc i965gm_desc = {
373 PLATFORM(I965GM),
374 .info = &(const struct intel_display_device_info) {
375 GEN4_DISPLAY,
376 .has_overlay = 1,
377 .supports_tv = 1,
378
379 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
380 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
381 },
382 };
383
384 static const struct platform_desc g45_desc = {
385 PLATFORM(G45),
386 .info = &(const struct intel_display_device_info) {
387 GEN4_DISPLAY,
388
389 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */
390 },
391 };
392
393 static const struct platform_desc gm45_desc = {
394 PLATFORM(GM45),
395 .info = &(const struct intel_display_device_info) {
396 GEN4_DISPLAY,
397 .supports_tv = 1,
398
399 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */
400 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
401 },
402 };
403
404 #define ILK_DISPLAY \
405 .has_hotplug = 1, \
406 I9XX_PIPE_OFFSETS, \
407 I9XX_CURSOR_OFFSETS, \
408 ILK_COLORS, \
409 \
410 .__runtime_defaults.ip.ver = 5, \
411 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
412 .__runtime_defaults.cpu_transcoder_mask = \
413 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
414 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
415
416 static const struct platform_desc ilk_d_desc = {
417 PLATFORM(IRONLAKE),
418 .info = &(const struct intel_display_device_info) {
419 ILK_DISPLAY,
420 },
421 };
422
423 static const struct platform_desc ilk_m_desc = {
424 PLATFORM(IRONLAKE),
425 .info = &(const struct intel_display_device_info) {
426 ILK_DISPLAY,
427
428 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
429 },
430 };
431
432 static const struct platform_desc snb_desc = {
433 PLATFORM(SANDYBRIDGE),
434 .info = &(const struct intel_display_device_info) {
435 .has_hotplug = 1,
436 I9XX_PIPE_OFFSETS,
437 I9XX_CURSOR_OFFSETS,
438 ILK_COLORS,
439
440 .__runtime_defaults.ip.ver = 6,
441 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
442 .__runtime_defaults.cpu_transcoder_mask =
443 BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
444 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
445 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
446 },
447 };
448
449 static const struct platform_desc ivb_desc = {
450 PLATFORM(IVYBRIDGE),
451 .info = &(const struct intel_display_device_info) {
452 .has_hotplug = 1,
453 IVB_PIPE_OFFSETS,
454 IVB_CURSOR_OFFSETS,
455 IVB_COLORS,
456
457 .__runtime_defaults.ip.ver = 7,
458 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
459 .__runtime_defaults.cpu_transcoder_mask =
460 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
461 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
462 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
463 },
464 };
465
466 static const struct platform_desc vlv_desc = {
467 PLATFORM(VALLEYVIEW),
468 .info = &(const struct intel_display_device_info) {
469 .has_gmch = 1,
470 .has_hotplug = 1,
471 .mmio_offset = VLV_DISPLAY_BASE,
472 I9XX_PIPE_OFFSETS,
473 I9XX_CURSOR_OFFSETS,
474 I9XX_COLORS,
475
476 .__runtime_defaults.ip.ver = 7,
477 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
478 .__runtime_defaults.cpu_transcoder_mask =
479 BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
480 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */
481 },
482 };
483
484 static const u16 hsw_ult_ids[] = {
485 INTEL_HSW_ULT_GT1_IDS(ID),
486 INTEL_HSW_ULT_GT2_IDS(ID),
487 INTEL_HSW_ULT_GT3_IDS(ID),
488 0
489 };
490
491 static const u16 hsw_ulx_ids[] = {
492 INTEL_HSW_ULX_GT1_IDS(ID),
493 INTEL_HSW_ULX_GT2_IDS(ID),
494 0
495 };
496
497 static const struct platform_desc hsw_desc = {
498 PLATFORM(HASWELL),
499 .subplatforms = (const struct subplatform_desc[]) {
500 { INTEL_DISPLAY_HASWELL_ULT, "ULT", hsw_ult_ids },
501 { INTEL_DISPLAY_HASWELL_ULX, "ULX", hsw_ulx_ids },
502 {},
503 },
504 .info = &(const struct intel_display_device_info) {
505 .has_ddi = 1,
506 .has_dp_mst = 1,
507 .has_fpga_dbg = 1,
508 .has_hotplug = 1,
509 .has_psr = 1,
510 .has_psr_hw_tracking = 1,
511 HSW_PIPE_OFFSETS,
512 IVB_CURSOR_OFFSETS,
513 IVB_COLORS,
514
515 .__runtime_defaults.ip.ver = 7,
516 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
517 .__runtime_defaults.cpu_transcoder_mask =
518 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
519 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
520 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
521 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
522 },
523 };
524
525 static const u16 bdw_ult_ids[] = {
526 INTEL_BDW_ULT_GT1_IDS(ID),
527 INTEL_BDW_ULT_GT2_IDS(ID),
528 INTEL_BDW_ULT_GT3_IDS(ID),
529 INTEL_BDW_ULT_RSVD_IDS(ID),
530 0
531 };
532
533 static const u16 bdw_ulx_ids[] = {
534 INTEL_BDW_ULX_GT1_IDS(ID),
535 INTEL_BDW_ULX_GT2_IDS(ID),
536 INTEL_BDW_ULX_GT3_IDS(ID),
537 INTEL_BDW_ULX_RSVD_IDS(ID),
538 0
539 };
540
541 static const struct platform_desc bdw_desc = {
542 PLATFORM(BROADWELL),
543 .subplatforms = (const struct subplatform_desc[]) {
544 { INTEL_DISPLAY_BROADWELL_ULT, "ULT", bdw_ult_ids },
545 { INTEL_DISPLAY_BROADWELL_ULX, "ULX", bdw_ulx_ids },
546 {},
547 },
548 .info = &(const struct intel_display_device_info) {
549 .has_ddi = 1,
550 .has_dp_mst = 1,
551 .has_fpga_dbg = 1,
552 .has_hotplug = 1,
553 .has_psr = 1,
554 .has_psr_hw_tracking = 1,
555 HSW_PIPE_OFFSETS,
556 IVB_CURSOR_OFFSETS,
557 IVB_COLORS,
558
559 .__runtime_defaults.ip.ver = 8,
560 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
561 .__runtime_defaults.cpu_transcoder_mask =
562 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
563 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
564 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
565 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
566 },
567 };
568
569 static const struct platform_desc chv_desc = {
570 PLATFORM(CHERRYVIEW),
571 .info = &(const struct intel_display_device_info) {
572 .has_hotplug = 1,
573 .has_gmch = 1,
574 .mmio_offset = VLV_DISPLAY_BASE,
575 CHV_PIPE_OFFSETS,
576 CHV_CURSOR_OFFSETS,
577 CHV_COLORS,
578
579 .__runtime_defaults.ip.ver = 8,
580 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
581 .__runtime_defaults.cpu_transcoder_mask =
582 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
583 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */
584 },
585 };
586
587 static const struct intel_display_device_info skl_display = {
588 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */
589 .dbuf.slice_mask = BIT(DBUF_S1),
590 .has_ddi = 1,
591 .has_dp_mst = 1,
592 .has_fpga_dbg = 1,
593 .has_hotplug = 1,
594 .has_ipc = 1,
595 .has_psr = 1,
596 .has_psr_hw_tracking = 1,
597 HSW_PIPE_OFFSETS,
598 IVB_CURSOR_OFFSETS,
599 IVB_COLORS,
600
601 .__runtime_defaults.ip.ver = 9,
602 .__runtime_defaults.has_dmc = 1,
603 .__runtime_defaults.has_hdcp = 1,
604 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
605 .__runtime_defaults.cpu_transcoder_mask =
606 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
607 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
608 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
609 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
610 };
611
612 static const u16 skl_ult_ids[] = {
613 INTEL_SKL_ULT_GT1_IDS(ID),
614 INTEL_SKL_ULT_GT2_IDS(ID),
615 INTEL_SKL_ULT_GT3_IDS(ID),
616 0
617 };
618
619 static const u16 skl_ulx_ids[] = {
620 INTEL_SKL_ULX_GT1_IDS(ID),
621 INTEL_SKL_ULX_GT2_IDS(ID),
622 0
623 };
624
625 static const enum intel_step skl_steppings[] = {
626 [0x6] = STEP_G0,
627 [0x7] = STEP_H0,
628 [0x9] = STEP_J0,
629 [0xA] = STEP_I1,
630 };
631
632 static const struct platform_desc skl_desc = {
633 PLATFORM(SKYLAKE),
634 .subplatforms = (const struct subplatform_desc[]) {
635 { INTEL_DISPLAY_SKYLAKE_ULT, "ULT", skl_ult_ids },
636 { INTEL_DISPLAY_SKYLAKE_ULX, "ULX", skl_ulx_ids },
637 {},
638 },
639 .info = &skl_display,
640 STEP_INFO(skl_steppings),
641 };
642
643 static const u16 kbl_ult_ids[] = {
644 INTEL_KBL_ULT_GT1_IDS(ID),
645 INTEL_KBL_ULT_GT2_IDS(ID),
646 INTEL_KBL_ULT_GT3_IDS(ID),
647 0
648 };
649
650 static const u16 kbl_ulx_ids[] = {
651 INTEL_KBL_ULX_GT1_IDS(ID),
652 INTEL_KBL_ULX_GT2_IDS(ID),
653 INTEL_AML_KBL_GT2_IDS(ID),
654 0
655 };
656
657 static const enum intel_step kbl_steppings[] = {
658 [1] = STEP_B0,
659 [2] = STEP_B0,
660 [3] = STEP_B0,
661 [4] = STEP_C0,
662 [5] = STEP_B1,
663 [6] = STEP_B1,
664 [7] = STEP_C0,
665 };
666
667 static const struct platform_desc kbl_desc = {
668 PLATFORM(KABYLAKE),
669 .subplatforms = (const struct subplatform_desc[]) {
670 { INTEL_DISPLAY_KABYLAKE_ULT, "ULT", kbl_ult_ids },
671 { INTEL_DISPLAY_KABYLAKE_ULX, "ULX", kbl_ulx_ids },
672 {},
673 },
674 .info = &skl_display,
675 STEP_INFO(kbl_steppings),
676 };
677
678 static const u16 cfl_ult_ids[] = {
679 INTEL_CFL_U_GT2_IDS(ID),
680 INTEL_CFL_U_GT3_IDS(ID),
681 INTEL_WHL_U_GT1_IDS(ID),
682 INTEL_WHL_U_GT2_IDS(ID),
683 INTEL_WHL_U_GT3_IDS(ID),
684 0
685 };
686
687 static const u16 cfl_ulx_ids[] = {
688 INTEL_AML_CFL_GT2_IDS(ID),
689 0
690 };
691
692 static const struct platform_desc cfl_desc = {
693 PLATFORM(COFFEELAKE),
694 .subplatforms = (const struct subplatform_desc[]) {
695 { INTEL_DISPLAY_COFFEELAKE_ULT, "ULT", cfl_ult_ids },
696 { INTEL_DISPLAY_COFFEELAKE_ULX, "ULX", cfl_ulx_ids },
697 {},
698 },
699 .info = &skl_display,
700 };
701
702 static const u16 cml_ult_ids[] = {
703 INTEL_CML_U_GT1_IDS(ID),
704 INTEL_CML_U_GT2_IDS(ID),
705 0
706 };
707
708 static const struct platform_desc cml_desc = {
709 PLATFORM(COMETLAKE),
710 .subplatforms = (const struct subplatform_desc[]) {
711 { INTEL_DISPLAY_COMETLAKE_ULT, "ULT", cml_ult_ids },
712 {},
713 },
714 .info = &skl_display,
715 };
716
717 #define GEN9_LP_DISPLAY \
718 .dbuf.slice_mask = BIT(DBUF_S1), \
719 .has_dp_mst = 1, \
720 .has_ddi = 1, \
721 .has_fpga_dbg = 1, \
722 .has_hotplug = 1, \
723 .has_ipc = 1, \
724 .has_psr = 1, \
725 .has_psr_hw_tracking = 1, \
726 HSW_PIPE_OFFSETS, \
727 IVB_CURSOR_OFFSETS, \
728 IVB_COLORS, \
729 \
730 .__runtime_defaults.has_dmc = 1, \
731 .__runtime_defaults.has_hdcp = 1, \
732 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
733 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
734 .__runtime_defaults.cpu_transcoder_mask = \
735 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
736 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
737 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
738 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
739
740 static const enum intel_step bxt_steppings[] = {
741 [0xA] = STEP_C0,
742 [0xB] = STEP_C0,
743 [0xC] = STEP_D0,
744 [0xD] = STEP_E0,
745 };
746
747 static const struct platform_desc bxt_desc = {
748 PLATFORM(BROXTON),
749 .info = &(const struct intel_display_device_info) {
750 GEN9_LP_DISPLAY,
751 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
752
753 .__runtime_defaults.ip.ver = 9,
754 },
755 STEP_INFO(bxt_steppings),
756 };
757
758 static const enum intel_step glk_steppings[] = {
759 [3] = STEP_B0,
760 };
761
762 static const struct platform_desc glk_desc = {
763 PLATFORM(GEMINILAKE),
764 .info = &(const struct intel_display_device_info) {
765 GEN9_LP_DISPLAY,
766 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
767 GLK_COLORS,
768
769 .__runtime_defaults.ip.ver = 10,
770 },
771 STEP_INFO(glk_steppings),
772 };
773
774 #define ICL_DISPLAY \
775 .abox_mask = BIT(0), \
776 .dbuf.size = 2048, \
777 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
778 .has_ddi = 1, \
779 .has_dp_mst = 1, \
780 .has_fpga_dbg = 1, \
781 .has_hotplug = 1, \
782 .has_ipc = 1, \
783 .has_psr = 1, \
784 .has_psr_hw_tracking = 1, \
785 .pipe_offsets = { \
786 [TRANSCODER_A] = PIPE_A_OFFSET, \
787 [TRANSCODER_B] = PIPE_B_OFFSET, \
788 [TRANSCODER_C] = PIPE_C_OFFSET, \
789 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
790 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
791 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
792 }, \
793 .trans_offsets = { \
794 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
795 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
796 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
797 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
798 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
799 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
800 }, \
801 IVB_CURSOR_OFFSETS, \
802 ICL_COLORS, \
803 \
804 .__runtime_defaults.ip.ver = 11, \
805 .__runtime_defaults.has_dmc = 1, \
806 .__runtime_defaults.has_dsc = 1, \
807 .__runtime_defaults.has_hdcp = 1, \
808 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
809 .__runtime_defaults.cpu_transcoder_mask = \
810 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
811 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
812 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
813 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
814
815 static const u16 icl_port_f_ids[] = {
816 INTEL_ICL_PORT_F_IDS(ID),
817 0
818 };
819
820 static const enum intel_step icl_steppings[] = {
821 [7] = STEP_D0,
822 };
823
824 static const struct platform_desc icl_desc = {
825 PLATFORM(ICELAKE),
826 .subplatforms = (const struct subplatform_desc[]) {
827 { INTEL_DISPLAY_ICELAKE_PORT_F, "Port F", icl_port_f_ids },
828 {},
829 },
830 .info = &(const struct intel_display_device_info) {
831 ICL_DISPLAY,
832
833 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
834 },
835 STEP_INFO(icl_steppings),
836 };
837
838 static const struct intel_display_device_info jsl_ehl_display = {
839 ICL_DISPLAY,
840
841 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D),
842 };
843
844 static const enum intel_step jsl_ehl_steppings[] = {
845 [0] = STEP_A0,
846 [1] = STEP_B0,
847 };
848
849 static const struct platform_desc jsl_desc = {
850 PLATFORM(JASPERLAKE),
851 .info = &jsl_ehl_display,
852 STEP_INFO(jsl_ehl_steppings),
853 };
854
855 static const struct platform_desc ehl_desc = {
856 PLATFORM(ELKHARTLAKE),
857 .info = &jsl_ehl_display,
858 STEP_INFO(jsl_ehl_steppings),
859 };
860
861 #define XE_D_DISPLAY \
862 .abox_mask = GENMASK(2, 1), \
863 .dbuf.size = 2048, \
864 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
865 .has_ddi = 1, \
866 .has_dp_mst = 1, \
867 .has_dsb = 1, \
868 .has_fpga_dbg = 1, \
869 .has_hotplug = 1, \
870 .has_ipc = 1, \
871 .has_psr = 1, \
872 .has_psr_hw_tracking = 1, \
873 .pipe_offsets = { \
874 [TRANSCODER_A] = PIPE_A_OFFSET, \
875 [TRANSCODER_B] = PIPE_B_OFFSET, \
876 [TRANSCODER_C] = PIPE_C_OFFSET, \
877 [TRANSCODER_D] = PIPE_D_OFFSET, \
878 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
879 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
880 }, \
881 .trans_offsets = { \
882 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
883 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
884 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
885 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
886 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
887 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
888 }, \
889 TGL_CURSOR_OFFSETS, \
890 ICL_COLORS, \
891 \
892 .__runtime_defaults.ip.ver = 12, \
893 .__runtime_defaults.has_dmc = 1, \
894 .__runtime_defaults.has_dsc = 1, \
895 .__runtime_defaults.has_hdcp = 1, \
896 .__runtime_defaults.pipe_mask = \
897 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
898 .__runtime_defaults.cpu_transcoder_mask = \
899 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
900 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
901 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
902 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
903
904 static const u16 tgl_uy_ids[] = {
905 INTEL_TGL_GT2_IDS(ID),
906 0
907 };
908
909 static const enum intel_step tgl_steppings[] = {
910 [0] = STEP_B0,
911 [1] = STEP_D0,
912 };
913
914 static const enum intel_step tgl_uy_steppings[] = {
915 [0] = STEP_A0,
916 [1] = STEP_C0,
917 [2] = STEP_C0,
918 [3] = STEP_D0,
919 };
920
921 static const struct platform_desc tgl_desc = {
922 PLATFORM(TIGERLAKE),
923 .subplatforms = (const struct subplatform_desc[]) {
924 { INTEL_DISPLAY_TIGERLAKE_UY, "UY", tgl_uy_ids,
925 STEP_INFO(tgl_uy_steppings) },
926 {},
927 },
928 .info = &(const struct intel_display_device_info) {
929 XE_D_DISPLAY,
930
931 /*
932 * FIXME DDI C/combo PHY C missing due to combo PHY
933 * code making a mess on SKUs where the PHY is missing.
934 */
935 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
936 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) | BIT(PORT_TC5) | BIT(PORT_TC6),
937 },
938 STEP_INFO(tgl_steppings),
939 };
940
941 static const enum intel_step dg1_steppings[] = {
942 [0] = STEP_A0,
943 [1] = STEP_B0,
944 };
945
946 static const struct platform_desc dg1_desc = {
947 PLATFORM(DG1),
948 .info = &(const struct intel_display_device_info) {
949 XE_D_DISPLAY,
950
951 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
952 BIT(PORT_TC1) | BIT(PORT_TC2),
953 },
954 STEP_INFO(dg1_steppings),
955 };
956
957 static const enum intel_step rkl_steppings[] = {
958 [0] = STEP_A0,
959 [1] = STEP_B0,
960 [4] = STEP_C0,
961 };
962
963 static const struct platform_desc rkl_desc = {
964 PLATFORM(ROCKETLAKE),
965 .info = &(const struct intel_display_device_info) {
966 XE_D_DISPLAY,
967 .abox_mask = BIT(0),
968 .has_hti = 1,
969 .has_psr_hw_tracking = 0,
970
971 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
972 .__runtime_defaults.cpu_transcoder_mask =
973 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
974 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
975 BIT(PORT_TC1) | BIT(PORT_TC2),
976 },
977 STEP_INFO(rkl_steppings),
978 };
979
980 static const u16 adls_rpls_ids[] = {
981 INTEL_RPLS_IDS(ID),
982 0
983 };
984
985 static const enum intel_step adl_s_steppings[] = {
986 [0x0] = STEP_A0,
987 [0x1] = STEP_A2,
988 [0x4] = STEP_B0,
989 [0x8] = STEP_B0,
990 [0xC] = STEP_C0,
991 };
992
993 static const enum intel_step adl_s_rpl_s_steppings[] = {
994 [0x4] = STEP_D0,
995 [0xC] = STEP_C0,
996 };
997
998 static const struct platform_desc adl_s_desc = {
999 PLATFORM(ALDERLAKE_S),
1000 .subplatforms = (const struct subplatform_desc[]) {
1001 { INTEL_DISPLAY_ALDERLAKE_S_RAPTORLAKE_S, "RPL-S", adls_rpls_ids,
1002 STEP_INFO(adl_s_rpl_s_steppings) },
1003 {},
1004 },
1005 .info = &(const struct intel_display_device_info) {
1006 XE_D_DISPLAY,
1007 .has_hti = 1,
1008 .has_psr_hw_tracking = 0,
1009
1010 .__runtime_defaults.port_mask = BIT(PORT_A) |
1011 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
1012 },
1013 STEP_INFO(adl_s_steppings),
1014 };
1015
1016 #define XE_LPD_FEATURES \
1017 .abox_mask = GENMASK(1, 0), \
1018 .color = { \
1019 .degamma_lut_size = 129, .gamma_lut_size = 1024, \
1020 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
1021 DRM_COLOR_LUT_EQUAL_CHANNELS, \
1022 }, \
1023 .dbuf.size = 4096, \
1024 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
1025 BIT(DBUF_S4), \
1026 .has_ddi = 1, \
1027 .has_dp_mst = 1, \
1028 .has_dsb = 1, \
1029 .has_fpga_dbg = 1, \
1030 .has_hotplug = 1, \
1031 .has_ipc = 1, \
1032 .has_psr = 1, \
1033 .pipe_offsets = { \
1034 [TRANSCODER_A] = PIPE_A_OFFSET, \
1035 [TRANSCODER_B] = PIPE_B_OFFSET, \
1036 [TRANSCODER_C] = PIPE_C_OFFSET, \
1037 [TRANSCODER_D] = PIPE_D_OFFSET, \
1038 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
1039 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
1040 }, \
1041 .trans_offsets = { \
1042 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
1043 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
1044 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
1045 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
1046 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
1047 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
1048 }, \
1049 TGL_CURSOR_OFFSETS, \
1050 \
1051 .__runtime_defaults.ip.ver = 13, \
1052 .__runtime_defaults.has_dmc = 1, \
1053 .__runtime_defaults.has_dsc = 1, \
1054 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
1055 .__runtime_defaults.has_hdcp = 1, \
1056 .__runtime_defaults.pipe_mask = \
1057 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
1058
1059 static const struct intel_display_device_info xe_lpd_display = {
1060 XE_LPD_FEATURES,
1061 .has_cdclk_crawl = 1,
1062 .has_psr_hw_tracking = 0,
1063
1064 .__runtime_defaults.cpu_transcoder_mask =
1065 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
1066 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
1067 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
1068 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1069 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
1070 };
1071
1072 static const u16 adlp_adln_ids[] = {
1073 INTEL_ADLN_IDS(ID),
1074 0
1075 };
1076
1077 static const u16 adlp_rplu_ids[] = {
1078 INTEL_RPLU_IDS(ID),
1079 0
1080 };
1081
1082 static const u16 adlp_rplp_ids[] = {
1083 INTEL_RPLP_IDS(ID),
1084 0
1085 };
1086
1087 static const enum intel_step adl_p_steppings[] = {
1088 [0x0] = STEP_A0,
1089 [0x4] = STEP_B0,
1090 [0x8] = STEP_C0,
1091 [0xC] = STEP_D0,
1092 };
1093
1094 static const enum intel_step adl_p_adl_n_steppings[] = {
1095 [0x0] = STEP_D0,
1096 };
1097
1098 static const enum intel_step adl_p_rpl_pu_steppings[] = {
1099 [0x4] = STEP_E0,
1100 };
1101
1102 static const struct platform_desc adl_p_desc = {
1103 PLATFORM(ALDERLAKE_P),
1104 .subplatforms = (const struct subplatform_desc[]) {
1105 { INTEL_DISPLAY_ALDERLAKE_P_ALDERLAKE_N, "ADL-N", adlp_adln_ids,
1106 STEP_INFO(adl_p_adl_n_steppings) },
1107 { INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_P, "RPL-P", adlp_rplp_ids,
1108 STEP_INFO(adl_p_rpl_pu_steppings) },
1109 { INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_U, "RPL-U", adlp_rplu_ids,
1110 STEP_INFO(adl_p_rpl_pu_steppings) },
1111 {},
1112 },
1113 .info = &xe_lpd_display,
1114 STEP_INFO(adl_p_steppings),
1115 };
1116
1117 static const struct intel_display_device_info xe_hpd_display = {
1118 XE_LPD_FEATURES,
1119 .has_cdclk_squash = 1,
1120
1121 .__runtime_defaults.cpu_transcoder_mask =
1122 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
1123 BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
1124 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D_XELPD) |
1125 BIT(PORT_TC1),
1126 };
1127
1128 static const u16 dg2_g10_ids[] = {
1129 INTEL_DG2_G10_IDS(ID),
1130 0
1131 };
1132
1133 static const u16 dg2_g11_ids[] = {
1134 INTEL_DG2_G11_IDS(ID),
1135 0
1136 };
1137
1138 static const u16 dg2_g12_ids[] = {
1139 INTEL_DG2_G12_IDS(ID),
1140 0
1141 };
1142
1143 static const enum intel_step dg2_g10_steppings[] = {
1144 [0x0] = STEP_A0,
1145 [0x1] = STEP_A0,
1146 [0x4] = STEP_B0,
1147 [0x8] = STEP_C0,
1148 };
1149
1150 static const enum intel_step dg2_g11_steppings[] = {
1151 [0x0] = STEP_B0,
1152 [0x4] = STEP_C0,
1153 [0x5] = STEP_C0,
1154 };
1155
1156 static const enum intel_step dg2_g12_steppings[] = {
1157 [0x0] = STEP_C0,
1158 [0x1] = STEP_C0,
1159 };
1160
1161 static const struct platform_desc dg2_desc = {
1162 PLATFORM(DG2),
1163 .subplatforms = (const struct subplatform_desc[]) {
1164 { INTEL_DISPLAY_DG2_G10, "G10", dg2_g10_ids,
1165 STEP_INFO(dg2_g10_steppings) },
1166 { INTEL_DISPLAY_DG2_G11, "G11", dg2_g11_ids,
1167 STEP_INFO(dg2_g11_steppings) },
1168 { INTEL_DISPLAY_DG2_G12, "G12", dg2_g12_ids,
1169 STEP_INFO(dg2_g12_steppings) },
1170 {},
1171 },
1172 .info = &xe_hpd_display,
1173 };
1174
1175 #define XE_LPDP_FEATURES \
1176 .abox_mask = GENMASK(1, 0), \
1177 .color = { \
1178 .degamma_lut_size = 129, .gamma_lut_size = 1024, \
1179 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
1180 DRM_COLOR_LUT_EQUAL_CHANNELS, \
1181 }, \
1182 .dbuf.size = 4096, \
1183 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
1184 BIT(DBUF_S4), \
1185 .has_cdclk_crawl = 1, \
1186 .has_cdclk_squash = 1, \
1187 .has_ddi = 1, \
1188 .has_dp_mst = 1, \
1189 .has_dsb = 1, \
1190 .has_fpga_dbg = 1, \
1191 .has_hotplug = 1, \
1192 .has_ipc = 1, \
1193 .has_psr = 1, \
1194 .pipe_offsets = { \
1195 [TRANSCODER_A] = PIPE_A_OFFSET, \
1196 [TRANSCODER_B] = PIPE_B_OFFSET, \
1197 [TRANSCODER_C] = PIPE_C_OFFSET, \
1198 [TRANSCODER_D] = PIPE_D_OFFSET, \
1199 }, \
1200 .trans_offsets = { \
1201 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
1202 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
1203 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
1204 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
1205 }, \
1206 TGL_CURSOR_OFFSETS, \
1207 \
1208 .__runtime_defaults.cpu_transcoder_mask = \
1209 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
1210 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
1211 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), \
1212 .__runtime_defaults.has_dmc = 1, \
1213 .__runtime_defaults.has_dsc = 1, \
1214 .__runtime_defaults.has_hdcp = 1, \
1215 .__runtime_defaults.pipe_mask = \
1216 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
1217 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \
1218 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4)
1219
1220 static const struct intel_display_device_info xe_lpdp_display = {
1221 XE_LPDP_FEATURES,
1222 };
1223
1224 static const struct intel_display_device_info xe2_lpd_display = {
1225 XE_LPDP_FEATURES,
1226
1227 .__runtime_defaults.fbc_mask =
1228 BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
1229 BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
1230 };
1231
1232 static const struct intel_display_device_info xe2_hpd_display = {
1233 XE_LPDP_FEATURES,
1234 .__runtime_defaults.port_mask = BIT(PORT_A) |
1235 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
1236 };
1237
1238 /*
1239 * Do not initialize the .info member of the platform desc for GMD ID based
1240 * platforms. Their display will be probed automatically based on the IP version
1241 * reported by the hardware.
1242 */
1243 static const struct platform_desc mtl_desc = {
1244 PLATFORM(METEORLAKE),
1245 };
1246
1247 static const struct platform_desc lnl_desc = {
1248 PLATFORM(LUNARLAKE),
1249 };
1250
1251 static const struct platform_desc bmg_desc = {
1252 PLATFORM(BATTLEMAGE),
1253 };
1254
1255 __diag_pop();
1256
1257 /*
1258 * Separate detection for no display cases to keep the display id array simple.
1259 *
1260 * IVB Q requires subvendor and subdevice matching to differentiate from IVB D
1261 * GT2 server.
1262 */
has_no_display(struct pci_dev * pdev)1263 static bool has_no_display(struct pci_dev *pdev)
1264 {
1265 static const struct pci_device_id ids[] = {
1266 INTEL_IVB_Q_IDS(INTEL_VGA_DEVICE, 0),
1267 {}
1268 };
1269
1270 return pci_match_id(ids, pdev);
1271 }
1272
1273 #define INTEL_DISPLAY_DEVICE(_id, _desc) { .devid = (_id), .desc = (_desc) }
1274
1275 static const struct {
1276 u32 devid;
1277 const struct platform_desc *desc;
1278 } intel_display_ids[] = {
1279 INTEL_I830_IDS(INTEL_DISPLAY_DEVICE, &i830_desc),
1280 INTEL_I845G_IDS(INTEL_DISPLAY_DEVICE, &i845_desc),
1281 INTEL_I85X_IDS(INTEL_DISPLAY_DEVICE, &i85x_desc),
1282 INTEL_I865G_IDS(INTEL_DISPLAY_DEVICE, &i865g_desc),
1283 INTEL_I915G_IDS(INTEL_DISPLAY_DEVICE, &i915g_desc),
1284 INTEL_I915GM_IDS(INTEL_DISPLAY_DEVICE, &i915gm_desc),
1285 INTEL_I945G_IDS(INTEL_DISPLAY_DEVICE, &i945g_desc),
1286 INTEL_I945GM_IDS(INTEL_DISPLAY_DEVICE, &i945gm_desc),
1287 INTEL_I965G_IDS(INTEL_DISPLAY_DEVICE, &i965g_desc),
1288 INTEL_G33_IDS(INTEL_DISPLAY_DEVICE, &g33_desc),
1289 INTEL_I965GM_IDS(INTEL_DISPLAY_DEVICE, &i965gm_desc),
1290 INTEL_GM45_IDS(INTEL_DISPLAY_DEVICE, &gm45_desc),
1291 INTEL_G45_IDS(INTEL_DISPLAY_DEVICE, &g45_desc),
1292 INTEL_PNV_IDS(INTEL_DISPLAY_DEVICE, &pnv_desc),
1293 INTEL_ILK_D_IDS(INTEL_DISPLAY_DEVICE, &ilk_d_desc),
1294 INTEL_ILK_M_IDS(INTEL_DISPLAY_DEVICE, &ilk_m_desc),
1295 INTEL_SNB_IDS(INTEL_DISPLAY_DEVICE, &snb_desc),
1296 INTEL_IVB_IDS(INTEL_DISPLAY_DEVICE, &ivb_desc),
1297 INTEL_HSW_IDS(INTEL_DISPLAY_DEVICE, &hsw_desc),
1298 INTEL_VLV_IDS(INTEL_DISPLAY_DEVICE, &vlv_desc),
1299 INTEL_BDW_IDS(INTEL_DISPLAY_DEVICE, &bdw_desc),
1300 INTEL_CHV_IDS(INTEL_DISPLAY_DEVICE, &chv_desc),
1301 INTEL_SKL_IDS(INTEL_DISPLAY_DEVICE, &skl_desc),
1302 INTEL_BXT_IDS(INTEL_DISPLAY_DEVICE, &bxt_desc),
1303 INTEL_GLK_IDS(INTEL_DISPLAY_DEVICE, &glk_desc),
1304 INTEL_KBL_IDS(INTEL_DISPLAY_DEVICE, &kbl_desc),
1305 INTEL_CFL_IDS(INTEL_DISPLAY_DEVICE, &cfl_desc),
1306 INTEL_WHL_IDS(INTEL_DISPLAY_DEVICE, &cfl_desc),
1307 INTEL_CML_IDS(INTEL_DISPLAY_DEVICE, &cml_desc),
1308 INTEL_ICL_IDS(INTEL_DISPLAY_DEVICE, &icl_desc),
1309 INTEL_EHL_IDS(INTEL_DISPLAY_DEVICE, &ehl_desc),
1310 INTEL_JSL_IDS(INTEL_DISPLAY_DEVICE, &jsl_desc),
1311 INTEL_TGL_IDS(INTEL_DISPLAY_DEVICE, &tgl_desc),
1312 INTEL_DG1_IDS(INTEL_DISPLAY_DEVICE, &dg1_desc),
1313 INTEL_RKL_IDS(INTEL_DISPLAY_DEVICE, &rkl_desc),
1314 INTEL_ADLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_desc),
1315 INTEL_RPLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_desc),
1316 INTEL_ADLP_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc),
1317 INTEL_ADLN_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc),
1318 INTEL_RPLU_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc),
1319 INTEL_RPLP_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc),
1320 INTEL_DG2_IDS(INTEL_DISPLAY_DEVICE, &dg2_desc),
1321 INTEL_MTL_IDS(INTEL_DISPLAY_DEVICE, &mtl_desc),
1322 INTEL_LNL_IDS(INTEL_DISPLAY_DEVICE, &lnl_desc),
1323 INTEL_BMG_IDS(INTEL_DISPLAY_DEVICE, &bmg_desc),
1324 };
1325
1326 static const struct {
1327 u16 ver;
1328 u16 rel;
1329 const struct intel_display_device_info *display;
1330 } gmdid_display_map[] = {
1331 { 14, 0, &xe_lpdp_display },
1332 { 14, 1, &xe2_hpd_display },
1333 { 20, 0, &xe2_lpd_display },
1334 };
1335
1336 static const struct intel_display_device_info *
probe_gmdid_display(struct drm_i915_private * i915,struct intel_display_ip_ver * ip_ver)1337 probe_gmdid_display(struct drm_i915_private *i915, struct intel_display_ip_ver *ip_ver)
1338 {
1339 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
1340 struct intel_display_ip_ver gmd_id;
1341 void __iomem *addr;
1342 u32 val;
1343 int i;
1344
1345 addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32));
1346 if (!addr) {
1347 drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n");
1348 return NULL;
1349 }
1350
1351 val = ioread32(addr);
1352 pci_iounmap(pdev, addr);
1353
1354 if (val == 0) {
1355 drm_dbg_kms(&i915->drm, "Device doesn't have display\n");
1356 return NULL;
1357 }
1358
1359 gmd_id.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
1360 gmd_id.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
1361 gmd_id.step = REG_FIELD_GET(GMD_ID_STEP, val);
1362
1363 for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) {
1364 if (gmd_id.ver == gmdid_display_map[i].ver &&
1365 gmd_id.rel == gmdid_display_map[i].rel) {
1366 *ip_ver = gmd_id;
1367 return gmdid_display_map[i].display;
1368 }
1369 }
1370
1371 drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n",
1372 gmd_id.ver, gmd_id.rel);
1373 return NULL;
1374 }
1375
find_platform_desc(struct pci_dev * pdev)1376 static const struct platform_desc *find_platform_desc(struct pci_dev *pdev)
1377 {
1378 int i;
1379
1380 for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
1381 if (intel_display_ids[i].devid == pdev->device)
1382 return intel_display_ids[i].desc;
1383 }
1384
1385 return NULL;
1386 }
1387
1388 static const struct subplatform_desc *
find_subplatform_desc(struct pci_dev * pdev,const struct platform_desc * desc)1389 find_subplatform_desc(struct pci_dev *pdev, const struct platform_desc *desc)
1390 {
1391 const struct subplatform_desc *sp;
1392 const u16 *id;
1393
1394 for (sp = desc->subplatforms; sp && sp->subplatform; sp++)
1395 for (id = sp->pciidlist; *id; id++)
1396 if (*id == pdev->device)
1397 return sp;
1398
1399 return NULL;
1400 }
1401
get_pre_gmdid_step(struct intel_display * display,const struct stepping_desc * main,const struct stepping_desc * sub)1402 static enum intel_step get_pre_gmdid_step(struct intel_display *display,
1403 const struct stepping_desc *main,
1404 const struct stepping_desc *sub)
1405 {
1406 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
1407 const enum intel_step *map = main->map;
1408 int size = main->size;
1409 int revision = pdev->revision;
1410 enum intel_step step;
1411
1412 /* subplatform stepping info trumps main platform info */
1413 if (sub && sub->map && sub->size) {
1414 map = sub->map;
1415 size = sub->size;
1416 }
1417
1418 /* not all platforms define steppings, and it's fine */
1419 if (!map || !size)
1420 return STEP_NONE;
1421
1422 if (revision < size && map[revision] != STEP_NONE) {
1423 step = map[revision];
1424 } else {
1425 drm_warn(display->drm, "Unknown revision 0x%02x\n", revision);
1426
1427 /*
1428 * If we hit a gap in the revision to step map, use the information
1429 * for the next revision.
1430 *
1431 * This may be wrong in all sorts of ways, especially if the
1432 * steppings in the array are not monotonically increasing, but
1433 * it's better than defaulting to 0.
1434 */
1435 while (revision < size && map[revision] == STEP_NONE)
1436 revision++;
1437
1438 if (revision < size) {
1439 drm_dbg_kms(display->drm, "Using display stepping for revision 0x%02x\n",
1440 revision);
1441 step = map[revision];
1442 } else {
1443 drm_dbg_kms(display->drm, "Using future display stepping\n");
1444 step = STEP_FUTURE;
1445 }
1446 }
1447
1448 drm_WARN_ON(display->drm, step == STEP_NONE);
1449
1450 return step;
1451 }
1452
intel_display_device_probe(struct drm_i915_private * i915)1453 void intel_display_device_probe(struct drm_i915_private *i915)
1454 {
1455 struct intel_display *display = &i915->display;
1456 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
1457 const struct intel_display_device_info *info;
1458 struct intel_display_ip_ver ip_ver = {};
1459 const struct platform_desc *desc;
1460 const struct subplatform_desc *subdesc;
1461 enum intel_step step;
1462
1463 /* Add drm device backpointer as early as possible. */
1464 i915->display.drm = &i915->drm;
1465
1466 intel_display_params_copy(&i915->display.params);
1467
1468 if (has_no_display(pdev)) {
1469 drm_dbg_kms(&i915->drm, "Device doesn't have display\n");
1470 goto no_display;
1471 }
1472
1473 desc = find_platform_desc(pdev);
1474 if (!desc) {
1475 drm_dbg_kms(&i915->drm, "Unknown device ID %04x; disabling display.\n",
1476 pdev->device);
1477 goto no_display;
1478 }
1479
1480 info = desc->info;
1481 if (!info)
1482 info = probe_gmdid_display(i915, &ip_ver);
1483 if (!info)
1484 goto no_display;
1485
1486 DISPLAY_INFO(i915) = info;
1487
1488 memcpy(DISPLAY_RUNTIME_INFO(i915),
1489 &DISPLAY_INFO(i915)->__runtime_defaults,
1490 sizeof(*DISPLAY_RUNTIME_INFO(i915)));
1491
1492 drm_WARN_ON(&i915->drm, !desc->platform || !desc->name);
1493 DISPLAY_RUNTIME_INFO(i915)->platform = desc->platform;
1494
1495 subdesc = find_subplatform_desc(pdev, desc);
1496 if (subdesc) {
1497 drm_WARN_ON(&i915->drm, !subdesc->subplatform || !subdesc->name);
1498 DISPLAY_RUNTIME_INFO(i915)->subplatform = subdesc->subplatform;
1499 }
1500
1501 if (ip_ver.ver || ip_ver.rel || ip_ver.step) {
1502 DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver;
1503 step = STEP_A0 + ip_ver.step;
1504 if (step > STEP_FUTURE) {
1505 drm_dbg_kms(display->drm, "Using future display stepping\n");
1506 step = STEP_FUTURE;
1507 }
1508 } else {
1509 step = get_pre_gmdid_step(display, &desc->step_info,
1510 subdesc ? &subdesc->step_info : NULL);
1511 }
1512
1513 DISPLAY_RUNTIME_INFO(i915)->step = step;
1514
1515 drm_info(&i915->drm, "Found %s%s%s (device ID %04x) display version %u.%02u stepping %s\n",
1516 desc->name, subdesc ? "/" : "", subdesc ? subdesc->name : "",
1517 pdev->device, DISPLAY_RUNTIME_INFO(i915)->ip.ver,
1518 DISPLAY_RUNTIME_INFO(i915)->ip.rel,
1519 step != STEP_NONE ? intel_step_name(step) : "N/A");
1520
1521 return;
1522
1523 no_display:
1524 DISPLAY_INFO(i915) = &no_display;
1525 }
1526
intel_display_device_remove(struct drm_i915_private * i915)1527 void intel_display_device_remove(struct drm_i915_private *i915)
1528 {
1529 intel_display_params_free(&i915->display.params);
1530 }
1531
__intel_display_device_info_runtime_init(struct drm_i915_private * i915)1532 static void __intel_display_device_info_runtime_init(struct drm_i915_private *i915)
1533 {
1534 struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915);
1535 enum pipe pipe;
1536
1537 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES);
1538 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->cpu_transcoder_mask) < I915_MAX_TRANSCODERS);
1539 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < I915_MAX_PORTS);
1540
1541 /* This covers both ULT and ULX */
1542 if (IS_HASWELL_ULT(i915) || IS_BROADWELL_ULT(i915))
1543 display_runtime->port_mask &= ~BIT(PORT_D);
1544
1545 if (IS_ICL_WITH_PORT_F(i915))
1546 display_runtime->port_mask |= BIT(PORT_F);
1547
1548 /* Wa_14011765242: adl-s A0,A1 */
1549 if (IS_ALDERLAKE_S(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
1550 for_each_pipe(i915, pipe)
1551 display_runtime->num_scalers[pipe] = 0;
1552 else if (DISPLAY_VER(i915) >= 11) {
1553 for_each_pipe(i915, pipe)
1554 display_runtime->num_scalers[pipe] = 2;
1555 } else if (DISPLAY_VER(i915) >= 9) {
1556 display_runtime->num_scalers[PIPE_A] = 2;
1557 display_runtime->num_scalers[PIPE_B] = 2;
1558 display_runtime->num_scalers[PIPE_C] = 1;
1559 }
1560
1561 if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
1562 for_each_pipe(i915, pipe)
1563 display_runtime->num_sprites[pipe] = 4;
1564 else if (DISPLAY_VER(i915) >= 11)
1565 for_each_pipe(i915, pipe)
1566 display_runtime->num_sprites[pipe] = 6;
1567 else if (DISPLAY_VER(i915) == 10)
1568 for_each_pipe(i915, pipe)
1569 display_runtime->num_sprites[pipe] = 3;
1570 else if (IS_BROXTON(i915)) {
1571 /*
1572 * Skylake and Broxton currently don't expose the topmost plane as its
1573 * use is exclusive with the legacy cursor and we only want to expose
1574 * one of those, not both. Until we can safely expose the topmost plane
1575 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
1576 * we don't expose the topmost plane at all to prevent ABI breakage
1577 * down the line.
1578 */
1579
1580 display_runtime->num_sprites[PIPE_A] = 2;
1581 display_runtime->num_sprites[PIPE_B] = 2;
1582 display_runtime->num_sprites[PIPE_C] = 1;
1583 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
1584 for_each_pipe(i915, pipe)
1585 display_runtime->num_sprites[pipe] = 2;
1586 } else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) {
1587 for_each_pipe(i915, pipe)
1588 display_runtime->num_sprites[pipe] = 1;
1589 }
1590
1591 if ((IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) &&
1592 !(intel_de_read(i915, GU_CNTL_PROTECTED) & DEPRESENT)) {
1593 drm_info(&i915->drm, "Display not present, disabling\n");
1594 goto display_fused_off;
1595 }
1596
1597 if (IS_DISPLAY_VER(i915, 7, 8) && HAS_PCH_SPLIT(i915)) {
1598 u32 fuse_strap = intel_de_read(i915, FUSE_STRAP);
1599 u32 sfuse_strap = intel_de_read(i915, SFUSE_STRAP);
1600
1601 /*
1602 * SFUSE_STRAP is supposed to have a bit signalling the display
1603 * is fused off. Unfortunately it seems that, at least in
1604 * certain cases, fused off display means that PCH display
1605 * reads don't land anywhere. In that case, we read 0s.
1606 *
1607 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1608 * should be set when taking over after the firmware.
1609 */
1610 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
1611 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
1612 (HAS_PCH_CPT(i915) &&
1613 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
1614 drm_info(&i915->drm,
1615 "Display fused off, disabling\n");
1616 goto display_fused_off;
1617 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
1618 drm_info(&i915->drm, "PipeC fused off\n");
1619 display_runtime->pipe_mask &= ~BIT(PIPE_C);
1620 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
1621 }
1622 } else if (DISPLAY_VER(i915) >= 9) {
1623 u32 dfsm = intel_de_read(i915, SKL_DFSM);
1624
1625 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
1626 display_runtime->pipe_mask &= ~BIT(PIPE_A);
1627 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
1628 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
1629 }
1630 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
1631 display_runtime->pipe_mask &= ~BIT(PIPE_B);
1632 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
1633 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B);
1634 }
1635 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
1636 display_runtime->pipe_mask &= ~BIT(PIPE_C);
1637 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
1638 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C);
1639 }
1640
1641 if (DISPLAY_VER(i915) >= 12 &&
1642 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
1643 display_runtime->pipe_mask &= ~BIT(PIPE_D);
1644 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
1645 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D);
1646 }
1647
1648 if (!display_runtime->pipe_mask)
1649 goto display_fused_off;
1650
1651 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
1652 display_runtime->has_hdcp = 0;
1653
1654 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
1655 display_runtime->fbc_mask = 0;
1656
1657 if (DISPLAY_VER(i915) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
1658 display_runtime->has_dmc = 0;
1659
1660 if (IS_DISPLAY_VER(i915, 10, 12) &&
1661 (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
1662 display_runtime->has_dsc = 0;
1663 }
1664
1665 if (DISPLAY_VER(i915) >= 20) {
1666 u32 cap = intel_de_read(i915, XE2LPD_DE_CAP);
1667
1668 if (REG_FIELD_GET(XE2LPD_DE_CAP_DSC_MASK, cap) ==
1669 XE2LPD_DE_CAP_DSC_REMOVED)
1670 display_runtime->has_dsc = 0;
1671
1672 if (REG_FIELD_GET(XE2LPD_DE_CAP_SCALER_MASK, cap) ==
1673 XE2LPD_DE_CAP_SCALER_SINGLE) {
1674 for_each_pipe(i915, pipe)
1675 if (display_runtime->num_scalers[pipe])
1676 display_runtime->num_scalers[pipe] = 1;
1677 }
1678 }
1679
1680 display_runtime->rawclk_freq = intel_read_rawclk(i915);
1681 drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq);
1682
1683 return;
1684
1685 display_fused_off:
1686 memset(display_runtime, 0, sizeof(*display_runtime));
1687 }
1688
intel_display_device_info_runtime_init(struct drm_i915_private * i915)1689 void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
1690 {
1691 if (HAS_DISPLAY(i915))
1692 __intel_display_device_info_runtime_init(i915);
1693
1694 /* Display may have been disabled by runtime init */
1695 if (!HAS_DISPLAY(i915)) {
1696 i915->drm.driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC);
1697 i915->display.info.__device_info = &no_display;
1698 }
1699
1700 /* Disable nuclear pageflip by default on pre-g4x */
1701 if (!i915->display.params.nuclear_pageflip &&
1702 DISPLAY_VER(i915) < 5 && !IS_G4X(i915))
1703 i915->drm.driver_features &= ~DRIVER_ATOMIC;
1704 }
1705
intel_display_device_info_print(const struct intel_display_device_info * info,const struct intel_display_runtime_info * runtime,struct drm_printer * p)1706 void intel_display_device_info_print(const struct intel_display_device_info *info,
1707 const struct intel_display_runtime_info *runtime,
1708 struct drm_printer *p)
1709 {
1710 if (runtime->ip.rel)
1711 drm_printf(p, "display version: %u.%02u\n",
1712 runtime->ip.ver,
1713 runtime->ip.rel);
1714 else
1715 drm_printf(p, "display version: %u\n",
1716 runtime->ip.ver);
1717
1718 drm_printf(p, "display stepping: %s\n", intel_step_name(runtime->step));
1719
1720 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
1721 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
1722 #undef PRINT_FLAG
1723
1724 drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
1725 drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
1726 drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
1727
1728 drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
1729 }
1730
1731 /*
1732 * Assuming the device has display hardware, should it be enabled?
1733 *
1734 * It's an error to call this function if the device does not have display
1735 * hardware.
1736 *
1737 * Disabling display means taking over the display hardware, putting it to
1738 * sleep, and preventing connectors from being connected via any means.
1739 */
intel_display_device_enabled(struct drm_i915_private * i915)1740 bool intel_display_device_enabled(struct drm_i915_private *i915)
1741 {
1742 struct intel_display *display = &i915->display;
1743
1744 /* Only valid when HAS_DISPLAY() is true */
1745 drm_WARN_ON(display->drm, !HAS_DISPLAY(display));
1746
1747 return !display->params.disable_display &&
1748 !intel_opregion_headless_sku(display);
1749 }
1750