1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) 2 /* Copyright(c) 2015 - 2021 Intel Corporation */ 3 #include <adf_accel_devices.h> 4 #include <adf_common_drv.h> 5 #include <adf_gen2_config.h> 6 #include <adf_gen2_dc.h> 7 #include <adf_gen2_hw_csr_data.h> 8 #include <adf_gen2_hw_data.h> 9 #include <adf_gen2_pfvf.h> 10 #include <adf_pfvf_vf_msg.h> 11 #include "adf_c62xvf_hw_data.h" 12 13 static struct adf_hw_device_class c62xiov_class = { 14 .name = ADF_C62XVF_DEVICE_NAME, 15 .type = DEV_C62XVF, 16 .instances = 0 17 }; 18 get_accel_mask(struct adf_hw_device_data * self)19static u32 get_accel_mask(struct adf_hw_device_data *self) 20 { 21 return ADF_C62XIOV_ACCELERATORS_MASK; 22 } 23 get_ae_mask(struct adf_hw_device_data * self)24static u32 get_ae_mask(struct adf_hw_device_data *self) 25 { 26 return ADF_C62XIOV_ACCELENGINES_MASK; 27 } 28 get_num_accels(struct adf_hw_device_data * self)29static u32 get_num_accels(struct adf_hw_device_data *self) 30 { 31 return ADF_C62XIOV_MAX_ACCELERATORS; 32 } 33 get_num_aes(struct adf_hw_device_data * self)34static u32 get_num_aes(struct adf_hw_device_data *self) 35 { 36 return ADF_C62XIOV_MAX_ACCELENGINES; 37 } 38 get_misc_bar_id(struct adf_hw_device_data * self)39static u32 get_misc_bar_id(struct adf_hw_device_data *self) 40 { 41 return ADF_C62XIOV_PMISC_BAR; 42 } 43 get_etr_bar_id(struct adf_hw_device_data * self)44static u32 get_etr_bar_id(struct adf_hw_device_data *self) 45 { 46 return ADF_C62XIOV_ETR_BAR; 47 } 48 get_sku(struct adf_hw_device_data * self)49static enum dev_sku_info get_sku(struct adf_hw_device_data *self) 50 { 51 return DEV_SKU_VF; 52 } 53 adf_vf_int_noop(struct adf_accel_dev * accel_dev)54static int adf_vf_int_noop(struct adf_accel_dev *accel_dev) 55 { 56 return 0; 57 } 58 adf_vf_void_noop(struct adf_accel_dev * accel_dev)59static void adf_vf_void_noop(struct adf_accel_dev *accel_dev) 60 { 61 } 62 adf_init_hw_data_c62xiov(struct adf_hw_device_data * hw_data)63void adf_init_hw_data_c62xiov(struct adf_hw_device_data *hw_data) 64 { 65 hw_data->dev_class = &c62xiov_class; 66 hw_data->num_banks = ADF_C62XIOV_ETR_MAX_BANKS; 67 hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK; 68 hw_data->num_accel = ADF_C62XIOV_MAX_ACCELERATORS; 69 hw_data->num_logical_accel = 1; 70 hw_data->num_engines = ADF_C62XIOV_MAX_ACCELENGINES; 71 hw_data->tx_rx_gap = ADF_C62XIOV_RX_RINGS_OFFSET; 72 hw_data->tx_rings_mask = ADF_C62XIOV_TX_RINGS_MASK; 73 hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP; 74 hw_data->alloc_irq = adf_vf_isr_resource_alloc; 75 hw_data->free_irq = adf_vf_isr_resource_free; 76 hw_data->enable_error_correction = adf_vf_void_noop; 77 hw_data->init_admin_comms = adf_vf_int_noop; 78 hw_data->exit_admin_comms = adf_vf_void_noop; 79 hw_data->send_admin_init = adf_vf2pf_notify_init; 80 hw_data->init_arb = adf_vf_int_noop; 81 hw_data->exit_arb = adf_vf_void_noop; 82 hw_data->disable_iov = adf_vf2pf_notify_shutdown; 83 hw_data->get_accel_mask = get_accel_mask; 84 hw_data->get_ae_mask = get_ae_mask; 85 hw_data->get_num_accels = get_num_accels; 86 hw_data->get_num_aes = get_num_aes; 87 hw_data->get_etr_bar_id = get_etr_bar_id; 88 hw_data->get_misc_bar_id = get_misc_bar_id; 89 hw_data->get_sku = get_sku; 90 hw_data->enable_ints = adf_vf_void_noop; 91 hw_data->dev_class->instances++; 92 hw_data->dev_config = adf_gen2_dev_config; 93 adf_devmgr_update_class_index(hw_data); 94 adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops); 95 adf_gen2_init_hw_csr_ops(&hw_data->csr_ops); 96 adf_gen2_init_dc_ops(&hw_data->dc_ops); 97 } 98 adf_clean_hw_data_c62xiov(struct adf_hw_device_data * hw_data)99void adf_clean_hw_data_c62xiov(struct adf_hw_device_data *hw_data) 100 { 101 hw_data->dev_class->instances--; 102 adf_devmgr_update_class_index(hw_data); 103 } 104