1 /*- 2 * Copyright (c) 2013 Cedric GROSS <cg@cgross.info> 3 * Copyright (c) 2011 Intel Corporation 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef __IF_IWN_CHIP_CFG_H__ 19 #define __IF_IWN_CHIP_CFG_H__ 20 21 /* ========================================================================== 22 * NIC PARAMETERS 23 * 24 * ========================================================================== 25 */ 26 27 /* 28 * Flags for managing calibration result. See calib_need 29 * in iwn_base_params struct 30 * 31 * These are bitmasks that determine which indexes in the calibcmd 32 * array are pushed up. 33 */ 34 #define IWN_FLG_NEED_PHY_CALIB_DC (1<<0) 35 #define IWN_FLG_NEED_PHY_CALIB_LO (1<<1) 36 #define IWN_FLG_NEED_PHY_CALIB_TX_IQ (1<<2) 37 #define IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC (1<<3) 38 #define IWN_FLG_NEED_PHY_CALIB_BASE_BAND (1<<4) 39 /* 40 * These aren't (yet) included in the calibcmd array, but 41 * are used as flags for which calibrations to use. 42 * 43 * XXX I think they should be named differently and 44 * stuffed in a different member in the config struct! 45 */ 46 #define IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET (1<<5) 47 #define IWN_FLG_NEED_PHY_CALIB_CRYSTAL (1<<6) 48 #define IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2 (1<<7) 49 50 /* 51 * Each chip has a different threshold for PLCP errors that should trigger a 52 * retune. 53 */ 54 #define IWN_PLCP_ERR_DEFAULT_THRESHOLD 50 55 #define IWN_PLCP_ERR_LONG_THRESHOLD 100 56 #define IWN_PLCP_ERR_EXT_LONG_THRESHOLD 200 57 58 /* 59 * Define some parameters for managing different NIC. 60 * Refer to linux specific file like iwl-xxxx.c to determine correct value 61 * for NIC. 62 * 63 * @max_ll_items: max number of OTP blocks 64 * @shadow_ram_support: shadow support for OTP memory 65 * @shadow_reg_enable: HW shadhow register bit 66 * @no_idle_support: do not support idle mode 67 * @advanced_bt_coexist : Advanced BT management 68 * @bt_session_2 : NIC need a new struct for configure BT coexistence. Needed 69 * only if advanced_bt_coexist is true 70 * @bt_sco_disable : 71 * @additional_nic_config: For 6005 series 72 * @iq_invert : ? But need it for N 2000 series 73 * @regulatory_bands : XXX 74 * @enhanced_TX_power : EEPROM Has advanced TX power options. Set 'True' 75 * if update_enhanced_txpower = iwl_eeprom_enhanced_txpower. 76 * See iwl-agn-devices.c file to determine that(enhanced_txpower) 77 * @need_temp_offset_calib : Need to compute some temp offset for calibration. 78 * @calib_need : Use IWN_FLG_NEED_PHY_CALIB_* flags to specify which 79 * calibration data ucode need. See calib_init_cfg in iwl-xxxx.c 80 * linux kernel file 81 * @support_hostap: Define IEEE80211_C_HOSTAP for ic_caps 82 * @no_multi_vaps: See iwn_vap_create 83 * @additional_gp_drv_bit : Specific bit to defined during nic_config 84 * @bt_mode: BT configuration mode 85 */ 86 enum bt_mode_enum { 87 IWN_BT_NONE, 88 IWN_BT_SIMPLE, 89 IWN_BT_ADVANCED 90 }; 91 92 struct iwn_base_params { 93 uint32_t pll_cfg_val; 94 const uint16_t max_ll_items; 95 #define IWN_OTP_MAX_LL_ITEMS_1000 (3) /* OTP blocks for 1000 */ 96 #define IWN_OTP_MAX_LL_ITEMS_6x00 (4) /* OTP blocks for 6x00 */ 97 #define IWN_OTP_MAX_LL_ITEMS_6x50 (7) /* OTP blocks for 6x50 */ 98 #define IWN_OTP_MAX_LL_ITEMS_2x00 (4) /* OTP blocks for 2x00 */ 99 const bool shadow_ram_support; 100 const bool shadow_reg_enable; 101 const bool bt_session_2; 102 const bool bt_sco_disable; 103 const bool additional_nic_config; 104 const uint32_t *regulatory_bands; 105 const bool enhanced_TX_power; 106 const uint16_t calib_need; 107 const bool support_hostap; 108 const bool no_multi_vaps; 109 uint8_t additional_gp_drv_bit; 110 enum bt_mode_enum bt_mode; 111 uint32_t plcp_err_threshold; 112 }; 113 114 static const struct iwn_base_params iwn5000_base_params = { 115 .pll_cfg_val = IWN_ANA_PLL_INIT, /* pll_cfg_val; */ 116 .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, /* max_ll_items */ 117 .shadow_ram_support = false, /* shadow_ram_support */ 118 .shadow_reg_enable = false, /* shadow_reg_enable */ 119 .bt_session_2 = false, /* bt_session_2 */ 120 .bt_sco_disable = true, /* bt_sco_disable */ 121 .additional_nic_config = false, /* additional_nic_config */ 122 .regulatory_bands = iwn5000_regulatory_bands, /* regulatory_bands */ 123 .enhanced_TX_power = false, /* enhanced_TX_power */ 124 .calib_need = 125 ( IWN_FLG_NEED_PHY_CALIB_LO 126 | IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC 127 | IWN_FLG_NEED_PHY_CALIB_TX_IQ 128 | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ), 129 .support_hostap = false, /* support_hostap */ 130 .no_multi_vaps = true, /* no_multi_vaps */ 131 .additional_gp_drv_bit = IWN_GP_DRIVER_NONE, /* additional_gp_drv_bit */ 132 .bt_mode = IWN_BT_NONE, /* bt_mode */ 133 .plcp_err_threshold = IWN_PLCP_ERR_LONG_THRESHOLD, 134 }; 135 136 /* 137 * 4965 support 138 */ 139 static const struct iwn_base_params iwn4965_base_params = { 140 .pll_cfg_val = 0, /* pll_cfg_val; */ 141 .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, /* max_ll_items - ignored for 4965 */ 142 .shadow_ram_support = true, /* shadow_ram_support */ 143 .shadow_reg_enable = false, /* shadow_reg_enable */ 144 .bt_session_2 = false, /* bt_session_2 XXX unknown? */ 145 .bt_sco_disable = true, /* bt_sco_disable XXX unknown? */ 146 .additional_nic_config = false, /* additional_nic_config - not for 4965 */ 147 .regulatory_bands = iwn5000_regulatory_bands, /* regulatory_bands */ 148 .enhanced_TX_power = false, /* enhanced_TX_power - not for 4965 */ 149 .calib_need = 150 (IWN_FLG_NEED_PHY_CALIB_DC 151 | IWN_FLG_NEED_PHY_CALIB_LO 152 | IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC 153 | IWN_FLG_NEED_PHY_CALIB_TX_IQ 154 | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ), 155 .support_hostap = false, /* support_hostap - XXX should work on fixing! */ 156 .no_multi_vaps = true, /* no_multi_vaps - XXX should work on fixing! */ 157 .additional_gp_drv_bit = IWN_GP_DRIVER_NONE, /* additional_gp_drv_bit */ 158 .bt_mode = IWN_BT_SIMPLE, /* bt_mode */ 159 .plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD, 160 }; 161 162 163 static const struct iwn_base_params iwn2000_base_params = { 164 .pll_cfg_val = 0, 165 .max_ll_items = IWN_OTP_MAX_LL_ITEMS_2x00, 166 .shadow_ram_support = true, 167 .shadow_reg_enable = false, 168 .bt_session_2 = false, 169 .bt_sco_disable = true, 170 .additional_nic_config = false, 171 .regulatory_bands = iwn2030_regulatory_bands, 172 .enhanced_TX_power = true, 173 .calib_need = 174 (IWN_FLG_NEED_PHY_CALIB_DC 175 | IWN_FLG_NEED_PHY_CALIB_LO 176 | IWN_FLG_NEED_PHY_CALIB_TX_IQ 177 | IWN_FLG_NEED_PHY_CALIB_BASE_BAND 178 | IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2 ), 179 .support_hostap = true, 180 .no_multi_vaps = false, 181 .additional_gp_drv_bit = IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT, 182 .bt_mode = IWN_BT_NONE, 183 .plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD, 184 }; 185 186 static const struct iwn_base_params iwn2030_base_params = { 187 .pll_cfg_val = 0, 188 .max_ll_items = IWN_OTP_MAX_LL_ITEMS_2x00, 189 .shadow_ram_support = true, 190 .shadow_reg_enable = false, /* XXX check? */ 191 .bt_session_2 = true, 192 .bt_sco_disable = true, 193 .additional_nic_config = false, 194 .regulatory_bands = iwn2030_regulatory_bands, 195 .enhanced_TX_power = true, 196 .calib_need = 197 (IWN_FLG_NEED_PHY_CALIB_DC 198 | IWN_FLG_NEED_PHY_CALIB_LO 199 | IWN_FLG_NEED_PHY_CALIB_TX_IQ 200 | IWN_FLG_NEED_PHY_CALIB_BASE_BAND 201 | IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2 ), 202 .support_hostap = true, 203 .no_multi_vaps = false, 204 .additional_gp_drv_bit = IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT, 205 .bt_mode = IWN_BT_ADVANCED, 206 .plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD, 207 }; 208 209 static const struct iwn_base_params iwn1000_base_params = { 210 .pll_cfg_val = IWN_ANA_PLL_INIT, 211 .max_ll_items = IWN_OTP_MAX_LL_ITEMS_1000, 212 .shadow_ram_support = false, 213 .shadow_reg_enable = false, /* XXX check? */ 214 .bt_session_2 = false, 215 .bt_sco_disable = false, 216 .additional_nic_config = false, 217 .regulatory_bands = iwn5000_regulatory_bands, 218 .enhanced_TX_power = false, 219 .calib_need = 220 ( IWN_FLG_NEED_PHY_CALIB_LO 221 | IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC 222 | IWN_FLG_NEED_PHY_CALIB_TX_IQ 223 | IWN_FLG_NEED_PHY_CALIB_BASE_BAND 224 ), 225 .support_hostap = false, 226 .no_multi_vaps = true, 227 .additional_gp_drv_bit = IWN_GP_DRIVER_NONE, 228 /* XXX 1000 - no BT */ 229 .bt_mode = IWN_BT_SIMPLE, 230 .plcp_err_threshold = IWN_PLCP_ERR_EXT_LONG_THRESHOLD, 231 }; 232 static const struct iwn_base_params iwn_6000_base_params = { 233 .pll_cfg_val = 0, 234 .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, 235 .shadow_ram_support = true, 236 .shadow_reg_enable = true, 237 .bt_session_2 = false, 238 .bt_sco_disable = false, 239 .additional_nic_config = false, 240 .regulatory_bands = iwn6000_regulatory_bands, 241 .enhanced_TX_power = true, 242 .calib_need = 243 (IWN_FLG_NEED_PHY_CALIB_DC 244 | IWN_FLG_NEED_PHY_CALIB_LO 245 | IWN_FLG_NEED_PHY_CALIB_TX_IQ 246 | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ), 247 .support_hostap = false, 248 .no_multi_vaps = true, 249 .additional_gp_drv_bit = IWN_GP_DRIVER_NONE, 250 .bt_mode = IWN_BT_SIMPLE, 251 .plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD, 252 }; 253 static const struct iwn_base_params iwn_6000i_base_params = { 254 .pll_cfg_val = 0, 255 .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, 256 .shadow_ram_support = true, 257 .shadow_reg_enable = true, 258 .bt_session_2 = false, 259 .bt_sco_disable = true, 260 .additional_nic_config = false, 261 .regulatory_bands = iwn6000_regulatory_bands, 262 .enhanced_TX_power = true, 263 .calib_need = 264 (IWN_FLG_NEED_PHY_CALIB_DC 265 | IWN_FLG_NEED_PHY_CALIB_LO 266 | IWN_FLG_NEED_PHY_CALIB_TX_IQ 267 | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ), 268 .support_hostap = false, 269 .no_multi_vaps = true, 270 .additional_gp_drv_bit = IWN_GP_DRIVER_NONE, 271 .bt_mode = IWN_BT_SIMPLE, 272 .plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD, 273 }; 274 static const struct iwn_base_params iwn_6000g2_base_params = { 275 .pll_cfg_val = 0, 276 .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, 277 .shadow_ram_support = true, 278 .shadow_reg_enable = true, 279 .bt_session_2 = false, 280 .bt_sco_disable = true, 281 .additional_nic_config = false, 282 .regulatory_bands = iwn6000_regulatory_bands, 283 .enhanced_TX_power = true, 284 .calib_need = 285 (IWN_FLG_NEED_PHY_CALIB_DC 286 | IWN_FLG_NEED_PHY_CALIB_LO 287 | IWN_FLG_NEED_PHY_CALIB_TX_IQ 288 | IWN_FLG_NEED_PHY_CALIB_BASE_BAND 289 | IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET ), 290 .support_hostap = false, 291 .no_multi_vaps = true, 292 .additional_gp_drv_bit = 0, 293 .bt_mode = IWN_BT_SIMPLE, 294 .plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD, 295 }; 296 297 static const struct iwn_base_params iwn_6050_base_params = { 298 .pll_cfg_val = 0, 299 .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x50, 300 .shadow_ram_support = true, 301 .shadow_reg_enable = true, 302 .bt_session_2 = false, 303 .bt_sco_disable = true, 304 .additional_nic_config = true, 305 .regulatory_bands = iwn6000_regulatory_bands, 306 .enhanced_TX_power = true, 307 .calib_need = 308 (IWN_FLG_NEED_PHY_CALIB_LO 309 | IWN_FLG_NEED_PHY_CALIB_TX_IQ 310 | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ), 311 .support_hostap = false, 312 .no_multi_vaps = true, 313 .additional_gp_drv_bit = IWN_GP_DRIVER_NONE, 314 .bt_mode = IWN_BT_SIMPLE, 315 .plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD, 316 }; 317 static const struct iwn_base_params iwn_6150_base_params = { 318 .pll_cfg_val = 0, 319 .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x50, 320 .shadow_ram_support = true, 321 .shadow_reg_enable = true, 322 .bt_session_2 = false, 323 .bt_sco_disable = true, 324 .additional_nic_config = true, 325 .regulatory_bands = iwn6000_regulatory_bands, 326 .enhanced_TX_power = true, 327 .calib_need = 328 (IWN_FLG_NEED_PHY_CALIB_LO 329 | IWN_FLG_NEED_PHY_CALIB_TX_IQ 330 | IWN_FLG_NEED_PHY_CALIB_BASE_BAND), 331 .support_hostap = false, 332 .no_multi_vaps = true, 333 .additional_gp_drv_bit = IWN_GP_DRIVER_6050_1X2, 334 .bt_mode = IWN_BT_SIMPLE, 335 .plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD, 336 }; 337 338 /* IWL_DEVICE_6035 & IWL_DEVICE_6030 */ 339 static const struct iwn_base_params iwn_6000g2b_base_params = { 340 .pll_cfg_val = 0, 341 .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, 342 .shadow_ram_support = true, 343 .shadow_reg_enable = true, 344 .bt_session_2 = false, 345 .bt_sco_disable = true, 346 .additional_nic_config = false, 347 .regulatory_bands = iwn6000_regulatory_bands, 348 .enhanced_TX_power = true, 349 .calib_need = 350 (IWN_FLG_NEED_PHY_CALIB_DC 351 | IWN_FLG_NEED_PHY_CALIB_LO 352 | IWN_FLG_NEED_PHY_CALIB_TX_IQ 353 | IWN_FLG_NEED_PHY_CALIB_BASE_BAND 354 | IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET ), 355 .support_hostap = false, 356 .no_multi_vaps = true, 357 .additional_gp_drv_bit = IWN_GP_DRIVER_NONE, 358 .bt_mode = IWN_BT_ADVANCED, 359 .plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD, 360 }; 361 362 /* 363 * 6235 series NICs. 364 */ 365 static const struct iwn_base_params iwn_6235_base_params = { 366 .pll_cfg_val = 0, 367 .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, 368 .shadow_ram_support = true, 369 .shadow_reg_enable = true, 370 .bt_session_2 = false, 371 .bt_sco_disable = true, 372 .additional_nic_config = true, 373 .regulatory_bands = iwn6000_regulatory_bands, 374 .enhanced_TX_power = true, 375 .calib_need = 376 (IWN_FLG_NEED_PHY_CALIB_DC 377 | IWN_FLG_NEED_PHY_CALIB_LO 378 | IWN_FLG_NEED_PHY_CALIB_TX_IQ 379 | IWN_FLG_NEED_PHY_CALIB_BASE_BAND 380 | IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET ), 381 .support_hostap = false, 382 .no_multi_vaps = true, 383 .additional_gp_drv_bit = 0, 384 .bt_mode = IWN_BT_ADVANCED, 385 .plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD, 386 }; 387 388 static const struct iwn_base_params iwn_5x50_base_params = { 389 .pll_cfg_val = IWN_ANA_PLL_INIT, 390 .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, 391 .shadow_ram_support = true, 392 .shadow_reg_enable = false, 393 .bt_session_2 = false, 394 .bt_sco_disable = true, 395 .additional_nic_config = false, 396 .regulatory_bands = iwn5000_regulatory_bands, 397 .enhanced_TX_power =false, 398 .calib_need = 399 (IWN_FLG_NEED_PHY_CALIB_DC 400 | IWN_FLG_NEED_PHY_CALIB_LO 401 | IWN_FLG_NEED_PHY_CALIB_TX_IQ 402 | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ), 403 .support_hostap = false, 404 .no_multi_vaps = true, 405 .additional_gp_drv_bit = IWN_GP_DRIVER_NONE, 406 .bt_mode = IWN_BT_SIMPLE, 407 .plcp_err_threshold = IWN_PLCP_ERR_LONG_THRESHOLD, 408 }; 409 410 #endif /* __IF_IWN_CHIP_CFG_H__ */ 411