1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD7124 SPI ADC driver
4 *
5 * Copyright 2018 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/kfifo.h>
16 #include <linux/module.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/property.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spi/spi.h>
21
22 #include <linux/iio/iio.h>
23 #include <linux/iio/adc/ad_sigma_delta.h>
24 #include <linux/iio/sysfs.h>
25
26 /* AD7124 registers */
27 #define AD7124_COMMS 0x00
28 #define AD7124_STATUS 0x00
29 #define AD7124_ADC_CONTROL 0x01
30 #define AD7124_DATA 0x02
31 #define AD7124_IO_CONTROL_1 0x03
32 #define AD7124_IO_CONTROL_2 0x04
33 #define AD7124_ID 0x05
34 #define AD7124_ERROR 0x06
35 #define AD7124_ERROR_EN 0x07
36 #define AD7124_MCLK_COUNT 0x08
37 #define AD7124_CHANNEL(x) (0x09 + (x))
38 #define AD7124_CONFIG(x) (0x19 + (x))
39 #define AD7124_FILTER(x) (0x21 + (x))
40 #define AD7124_OFFSET(x) (0x29 + (x))
41 #define AD7124_GAIN(x) (0x31 + (x))
42
43 /* AD7124_STATUS */
44 #define AD7124_STATUS_POR_FLAG_MSK BIT(4)
45
46 /* AD7124_ADC_CONTROL */
47 #define AD7124_ADC_STATUS_EN_MSK BIT(10)
48 #define AD7124_ADC_STATUS_EN(x) FIELD_PREP(AD7124_ADC_STATUS_EN_MSK, x)
49 #define AD7124_ADC_CTRL_REF_EN_MSK BIT(8)
50 #define AD7124_ADC_CTRL_REF_EN(x) FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
51 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
52 #define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
53 #define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2)
54 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
55
56 /* AD7124 ID */
57 #define AD7124_DEVICE_ID_MSK GENMASK(7, 4)
58 #define AD7124_DEVICE_ID_GET(x) FIELD_GET(AD7124_DEVICE_ID_MSK, x)
59 #define AD7124_SILICON_REV_MSK GENMASK(3, 0)
60 #define AD7124_SILICON_REV_GET(x) FIELD_GET(AD7124_SILICON_REV_MSK, x)
61
62 #define CHIPID_AD7124_4 0x0
63 #define CHIPID_AD7124_8 0x1
64
65 /* AD7124_CHANNEL_X */
66 #define AD7124_CHANNEL_EN_MSK BIT(15)
67 #define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
68 #define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12)
69 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
70 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
71 #define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
72 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
73 #define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
74
75 /* AD7124_CONFIG_X */
76 #define AD7124_CONFIG_BIPOLAR_MSK BIT(11)
77 #define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
78 #define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3)
79 #define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
80 #define AD7124_CONFIG_PGA_MSK GENMASK(2, 0)
81 #define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
82 #define AD7124_CONFIG_IN_BUFF_MSK GENMASK(6, 5)
83 #define AD7124_CONFIG_IN_BUFF(x) FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
84
85 /* AD7124_FILTER_X */
86 #define AD7124_FILTER_FS_MSK GENMASK(10, 0)
87 #define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x)
88 #define AD7124_FILTER_TYPE_MSK GENMASK(23, 21)
89 #define AD7124_FILTER_TYPE_SEL(x) FIELD_PREP(AD7124_FILTER_TYPE_MSK, x)
90
91 #define AD7124_SINC3_FILTER 2
92 #define AD7124_SINC4_FILTER 0
93
94 #define AD7124_CONF_ADDR_OFFSET 20
95 #define AD7124_MAX_CONFIGS 8
96 #define AD7124_MAX_CHANNELS 16
97
98 enum ad7124_ids {
99 ID_AD7124_4,
100 ID_AD7124_8,
101 };
102
103 enum ad7124_ref_sel {
104 AD7124_REFIN1,
105 AD7124_REFIN2,
106 AD7124_INT_REF,
107 AD7124_AVDD_REF,
108 };
109
110 enum ad7124_power_mode {
111 AD7124_LOW_POWER,
112 AD7124_MID_POWER,
113 AD7124_FULL_POWER,
114 };
115
116 static const unsigned int ad7124_gain[8] = {
117 1, 2, 4, 8, 16, 32, 64, 128
118 };
119
120 static const unsigned int ad7124_reg_size[] = {
121 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
122 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
123 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
124 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
125 3, 3, 3, 3, 3
126 };
127
128 static const int ad7124_master_clk_freq_hz[3] = {
129 [AD7124_LOW_POWER] = 76800,
130 [AD7124_MID_POWER] = 153600,
131 [AD7124_FULL_POWER] = 614400,
132 };
133
134 static const char * const ad7124_ref_names[] = {
135 [AD7124_REFIN1] = "refin1",
136 [AD7124_REFIN2] = "refin2",
137 [AD7124_INT_REF] = "int",
138 [AD7124_AVDD_REF] = "avdd",
139 };
140
141 struct ad7124_chip_info {
142 const char *name;
143 unsigned int chip_id;
144 unsigned int num_inputs;
145 };
146
147 struct ad7124_channel_config {
148 bool live;
149 unsigned int cfg_slot;
150 /* Following fields are used to compare equality. */
151 struct_group(config_props,
152 enum ad7124_ref_sel refsel;
153 bool bipolar;
154 bool buf_positive;
155 bool buf_negative;
156 unsigned int vref_mv;
157 unsigned int pga_bits;
158 unsigned int odr;
159 unsigned int odr_sel_bits;
160 unsigned int filter_type;
161 );
162 };
163
164 struct ad7124_channel {
165 unsigned int nr;
166 struct ad7124_channel_config cfg;
167 unsigned int ain;
168 unsigned int slot;
169 };
170
171 struct ad7124_state {
172 const struct ad7124_chip_info *chip_info;
173 struct ad_sigma_delta sd;
174 struct ad7124_channel *channels;
175 struct regulator *vref[4];
176 struct clk *mclk;
177 unsigned int adc_control;
178 unsigned int num_channels;
179 struct mutex cfgs_lock; /* lock for configs access */
180 unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */
181 DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS);
182 };
183
184 static const struct iio_chan_spec ad7124_channel_template = {
185 .type = IIO_VOLTAGE,
186 .indexed = 1,
187 .differential = 1,
188 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
189 BIT(IIO_CHAN_INFO_SCALE) |
190 BIT(IIO_CHAN_INFO_OFFSET) |
191 BIT(IIO_CHAN_INFO_SAMP_FREQ) |
192 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
193 .scan_type = {
194 .sign = 'u',
195 .realbits = 24,
196 .storagebits = 32,
197 .endianness = IIO_BE,
198 },
199 };
200
201 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
202 [ID_AD7124_4] = {
203 .name = "ad7124-4",
204 .chip_id = CHIPID_AD7124_4,
205 .num_inputs = 8,
206 },
207 [ID_AD7124_8] = {
208 .name = "ad7124-8",
209 .chip_id = CHIPID_AD7124_8,
210 .num_inputs = 16,
211 },
212 };
213
ad7124_find_closest_match(const int * array,unsigned int size,int val)214 static int ad7124_find_closest_match(const int *array,
215 unsigned int size, int val)
216 {
217 int i, idx;
218 unsigned int diff_new, diff_old;
219
220 diff_old = U32_MAX;
221 idx = 0;
222
223 for (i = 0; i < size; i++) {
224 diff_new = abs(val - array[i]);
225 if (diff_new < diff_old) {
226 diff_old = diff_new;
227 idx = i;
228 }
229 }
230
231 return idx;
232 }
233
ad7124_spi_write_mask(struct ad7124_state * st,unsigned int addr,unsigned long mask,unsigned int val,unsigned int bytes)234 static int ad7124_spi_write_mask(struct ad7124_state *st,
235 unsigned int addr,
236 unsigned long mask,
237 unsigned int val,
238 unsigned int bytes)
239 {
240 unsigned int readval;
241 int ret;
242
243 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
244 if (ret < 0)
245 return ret;
246
247 readval &= ~mask;
248 readval |= val;
249
250 return ad_sd_write_reg(&st->sd, addr, bytes, readval);
251 }
252
ad7124_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)253 static int ad7124_set_mode(struct ad_sigma_delta *sd,
254 enum ad_sigma_delta_mode mode)
255 {
256 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
257
258 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
259 st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
260
261 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
262 }
263
ad7124_set_channel_odr(struct ad7124_state * st,unsigned int channel,unsigned int odr)264 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel, unsigned int odr)
265 {
266 unsigned int fclk, odr_sel_bits;
267
268 fclk = clk_get_rate(st->mclk);
269 /*
270 * FS[10:0] = fCLK / (fADC x 32) where:
271 * fADC is the output data rate
272 * fCLK is the master clock frequency
273 * FS[10:0] are the bits in the filter register
274 * FS[10:0] can have a value from 1 to 2047
275 */
276 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
277 if (odr_sel_bits < 1)
278 odr_sel_bits = 1;
279 else if (odr_sel_bits > 2047)
280 odr_sel_bits = 2047;
281
282 if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits)
283 st->channels[channel].cfg.live = false;
284
285 /* fADC = fCLK / (FS[10:0] x 32) */
286 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
287 st->channels[channel].cfg.odr_sel_bits = odr_sel_bits;
288 }
289
ad7124_get_3db_filter_freq(struct ad7124_state * st,unsigned int channel)290 static int ad7124_get_3db_filter_freq(struct ad7124_state *st,
291 unsigned int channel)
292 {
293 unsigned int fadc;
294
295 fadc = st->channels[channel].cfg.odr;
296
297 switch (st->channels[channel].cfg.filter_type) {
298 case AD7124_SINC3_FILTER:
299 return DIV_ROUND_CLOSEST(fadc * 230, 1000);
300 case AD7124_SINC4_FILTER:
301 return DIV_ROUND_CLOSEST(fadc * 262, 1000);
302 default:
303 return -EINVAL;
304 }
305 }
306
ad7124_set_3db_filter_freq(struct ad7124_state * st,unsigned int channel,unsigned int freq)307 static void ad7124_set_3db_filter_freq(struct ad7124_state *st, unsigned int channel,
308 unsigned int freq)
309 {
310 unsigned int sinc4_3db_odr;
311 unsigned int sinc3_3db_odr;
312 unsigned int new_filter;
313 unsigned int new_odr;
314
315 sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230);
316 sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262);
317
318 if (sinc4_3db_odr > sinc3_3db_odr) {
319 new_filter = AD7124_SINC3_FILTER;
320 new_odr = sinc4_3db_odr;
321 } else {
322 new_filter = AD7124_SINC4_FILTER;
323 new_odr = sinc3_3db_odr;
324 }
325
326 if (new_odr != st->channels[channel].cfg.odr)
327 st->channels[channel].cfg.live = false;
328
329 st->channels[channel].cfg.filter_type = new_filter;
330 st->channels[channel].cfg.odr = new_odr;
331 }
332
ad7124_find_similar_live_cfg(struct ad7124_state * st,struct ad7124_channel_config * cfg)333 static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st,
334 struct ad7124_channel_config *cfg)
335 {
336 struct ad7124_channel_config *cfg_aux;
337 ptrdiff_t cmp_size;
338 int i;
339
340 cmp_size = sizeof_field(struct ad7124_channel_config, config_props);
341 for (i = 0; i < st->num_channels; i++) {
342 cfg_aux = &st->channels[i].cfg;
343
344 if (cfg_aux->live &&
345 !memcmp(&cfg->config_props, &cfg_aux->config_props, cmp_size))
346 return cfg_aux;
347 }
348
349 return NULL;
350 }
351
ad7124_find_free_config_slot(struct ad7124_state * st)352 static int ad7124_find_free_config_slot(struct ad7124_state *st)
353 {
354 unsigned int free_cfg_slot;
355
356 free_cfg_slot = find_first_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS);
357 if (free_cfg_slot == AD7124_MAX_CONFIGS)
358 return -1;
359
360 return free_cfg_slot;
361 }
362
ad7124_init_config_vref(struct ad7124_state * st,struct ad7124_channel_config * cfg)363 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg)
364 {
365 unsigned int refsel = cfg->refsel;
366
367 switch (refsel) {
368 case AD7124_REFIN1:
369 case AD7124_REFIN2:
370 case AD7124_AVDD_REF:
371 if (IS_ERR(st->vref[refsel])) {
372 dev_err(&st->sd.spi->dev,
373 "Error, trying to use external voltage reference without a %s regulator.\n",
374 ad7124_ref_names[refsel]);
375 return PTR_ERR(st->vref[refsel]);
376 }
377 cfg->vref_mv = regulator_get_voltage(st->vref[refsel]);
378 /* Conversion from uV to mV */
379 cfg->vref_mv /= 1000;
380 return 0;
381 case AD7124_INT_REF:
382 cfg->vref_mv = 2500;
383 st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
384 st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
385 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL,
386 2, st->adc_control);
387 default:
388 dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
389 return -EINVAL;
390 }
391 }
392
ad7124_write_config(struct ad7124_state * st,struct ad7124_channel_config * cfg,unsigned int cfg_slot)393 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg,
394 unsigned int cfg_slot)
395 {
396 unsigned int tmp;
397 unsigned int val;
398 int ret;
399
400 cfg->cfg_slot = cfg_slot;
401
402 tmp = (cfg->buf_positive << 1) + cfg->buf_negative;
403 val = AD7124_CONFIG_BIPOLAR(cfg->bipolar) | AD7124_CONFIG_REF_SEL(cfg->refsel) |
404 AD7124_CONFIG_IN_BUFF(tmp);
405 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val);
406 if (ret < 0)
407 return ret;
408
409 tmp = AD7124_FILTER_TYPE_SEL(cfg->filter_type);
410 ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_TYPE_MSK,
411 tmp, 3);
412 if (ret < 0)
413 return ret;
414
415 ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_FS_MSK,
416 AD7124_FILTER_FS(cfg->odr_sel_bits), 3);
417 if (ret < 0)
418 return ret;
419
420 return ad7124_spi_write_mask(st, AD7124_CONFIG(cfg->cfg_slot), AD7124_CONFIG_PGA_MSK,
421 AD7124_CONFIG_PGA(cfg->pga_bits), 2);
422 }
423
ad7124_pop_config(struct ad7124_state * st)424 static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st)
425 {
426 struct ad7124_channel_config *lru_cfg;
427 struct ad7124_channel_config *cfg;
428 int ret;
429 int i;
430
431 /*
432 * Pop least recently used config from the fifo
433 * in order to make room for the new one
434 */
435 ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg);
436 if (ret <= 0)
437 return NULL;
438
439 lru_cfg->live = false;
440
441 /* mark slot as free */
442 assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0);
443
444 /* invalidate all other configs that pointed to this one */
445 for (i = 0; i < st->num_channels; i++) {
446 cfg = &st->channels[i].cfg;
447
448 if (cfg->cfg_slot == lru_cfg->cfg_slot)
449 cfg->live = false;
450 }
451
452 return lru_cfg;
453 }
454
ad7124_push_config(struct ad7124_state * st,struct ad7124_channel_config * cfg)455 static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg)
456 {
457 struct ad7124_channel_config *lru_cfg;
458 int free_cfg_slot;
459
460 free_cfg_slot = ad7124_find_free_config_slot(st);
461 if (free_cfg_slot >= 0) {
462 /* push the new config in configs queue */
463 kfifo_put(&st->live_cfgs_fifo, cfg);
464 } else {
465 /* pop one config to make room for the new one */
466 lru_cfg = ad7124_pop_config(st);
467 if (!lru_cfg)
468 return -EINVAL;
469
470 /* push the new config in configs queue */
471 free_cfg_slot = lru_cfg->cfg_slot;
472 kfifo_put(&st->live_cfgs_fifo, cfg);
473 }
474
475 /* mark slot as used */
476 assign_bit(free_cfg_slot, &st->cfg_slots_status, 1);
477
478 return ad7124_write_config(st, cfg, free_cfg_slot);
479 }
480
ad7124_enable_channel(struct ad7124_state * st,struct ad7124_channel * ch)481 static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch)
482 {
483 ch->cfg.live = true;
484 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain |
485 AD7124_CHANNEL_SETUP(ch->cfg.cfg_slot) | AD7124_CHANNEL_EN(1));
486 }
487
ad7124_prepare_read(struct ad7124_state * st,int address)488 static int ad7124_prepare_read(struct ad7124_state *st, int address)
489 {
490 struct ad7124_channel_config *cfg = &st->channels[address].cfg;
491 struct ad7124_channel_config *live_cfg;
492
493 /*
494 * Before doing any reads assign the channel a configuration.
495 * Check if channel's config is on the device
496 */
497 if (!cfg->live) {
498 /* check if config matches another one */
499 live_cfg = ad7124_find_similar_live_cfg(st, cfg);
500 if (!live_cfg)
501 ad7124_push_config(st, cfg);
502 else
503 cfg->cfg_slot = live_cfg->cfg_slot;
504 }
505
506 /* point channel to the config slot and enable */
507 return ad7124_enable_channel(st, &st->channels[address]);
508 }
509
__ad7124_set_channel(struct ad_sigma_delta * sd,unsigned int channel)510 static int __ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
511 {
512 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
513
514 return ad7124_prepare_read(st, channel);
515 }
516
ad7124_set_channel(struct ad_sigma_delta * sd,unsigned int channel)517 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
518 {
519 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
520 int ret;
521
522 mutex_lock(&st->cfgs_lock);
523 ret = __ad7124_set_channel(sd, channel);
524 mutex_unlock(&st->cfgs_lock);
525
526 return ret;
527 }
528
ad7124_append_status(struct ad_sigma_delta * sd,bool append)529 static int ad7124_append_status(struct ad_sigma_delta *sd, bool append)
530 {
531 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
532 unsigned int adc_control = st->adc_control;
533 int ret;
534
535 adc_control &= ~AD7124_ADC_STATUS_EN_MSK;
536 adc_control |= AD7124_ADC_STATUS_EN(append);
537
538 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, adc_control);
539 if (ret < 0)
540 return ret;
541
542 st->adc_control = adc_control;
543
544 return 0;
545 }
546
ad7124_disable_all(struct ad_sigma_delta * sd)547 static int ad7124_disable_all(struct ad_sigma_delta *sd)
548 {
549 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
550 int ret;
551 int i;
552
553 for (i = 0; i < st->num_channels; i++) {
554 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK, 0, 2);
555 if (ret < 0)
556 return ret;
557 }
558
559 return 0;
560 }
561
ad7124_disable_one(struct ad_sigma_delta * sd,unsigned int chan)562 static int ad7124_disable_one(struct ad_sigma_delta *sd, unsigned int chan)
563 {
564 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
565
566 return ad7124_spi_write_mask(st, AD7124_CHANNEL(chan), AD7124_CHANNEL_EN_MSK, 0, 2);
567 }
568
569 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
570 .set_channel = ad7124_set_channel,
571 .append_status = ad7124_append_status,
572 .disable_all = ad7124_disable_all,
573 .disable_one = ad7124_disable_one,
574 .set_mode = ad7124_set_mode,
575 .has_registers = true,
576 .addr_shift = 0,
577 .read_mask = BIT(6),
578 .status_ch_mask = GENMASK(3, 0),
579 .data_reg = AD7124_DATA,
580 .num_slots = 8,
581 .irq_flags = IRQF_TRIGGER_FALLING,
582 };
583
ad7124_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)584 static int ad7124_read_raw(struct iio_dev *indio_dev,
585 struct iio_chan_spec const *chan,
586 int *val, int *val2, long info)
587 {
588 struct ad7124_state *st = iio_priv(indio_dev);
589 int idx, ret;
590
591 switch (info) {
592 case IIO_CHAN_INFO_RAW:
593 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
594 if (ret < 0)
595 return ret;
596
597 return IIO_VAL_INT;
598 case IIO_CHAN_INFO_SCALE:
599 mutex_lock(&st->cfgs_lock);
600
601 idx = st->channels[chan->address].cfg.pga_bits;
602 *val = st->channels[chan->address].cfg.vref_mv;
603 if (st->channels[chan->address].cfg.bipolar)
604 *val2 = chan->scan_type.realbits - 1 + idx;
605 else
606 *val2 = chan->scan_type.realbits + idx;
607
608 mutex_unlock(&st->cfgs_lock);
609 return IIO_VAL_FRACTIONAL_LOG2;
610 case IIO_CHAN_INFO_OFFSET:
611 mutex_lock(&st->cfgs_lock);
612 if (st->channels[chan->address].cfg.bipolar)
613 *val = -(1 << (chan->scan_type.realbits - 1));
614 else
615 *val = 0;
616
617 mutex_unlock(&st->cfgs_lock);
618 return IIO_VAL_INT;
619 case IIO_CHAN_INFO_SAMP_FREQ:
620 mutex_lock(&st->cfgs_lock);
621 *val = st->channels[chan->address].cfg.odr;
622 mutex_unlock(&st->cfgs_lock);
623
624 return IIO_VAL_INT;
625 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
626 mutex_lock(&st->cfgs_lock);
627 *val = ad7124_get_3db_filter_freq(st, chan->scan_index);
628 mutex_unlock(&st->cfgs_lock);
629
630 return IIO_VAL_INT;
631 default:
632 return -EINVAL;
633 }
634 }
635
ad7124_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)636 static int ad7124_write_raw(struct iio_dev *indio_dev,
637 struct iio_chan_spec const *chan,
638 int val, int val2, long info)
639 {
640 struct ad7124_state *st = iio_priv(indio_dev);
641 unsigned int res, gain, full_scale, vref;
642 int ret = 0;
643
644 mutex_lock(&st->cfgs_lock);
645
646 switch (info) {
647 case IIO_CHAN_INFO_SAMP_FREQ:
648 if (val2 != 0) {
649 ret = -EINVAL;
650 break;
651 }
652
653 ad7124_set_channel_odr(st, chan->address, val);
654 break;
655 case IIO_CHAN_INFO_SCALE:
656 if (val != 0) {
657 ret = -EINVAL;
658 break;
659 }
660
661 if (st->channels[chan->address].cfg.bipolar)
662 full_scale = 1 << (chan->scan_type.realbits - 1);
663 else
664 full_scale = 1 << chan->scan_type.realbits;
665
666 vref = st->channels[chan->address].cfg.vref_mv * 1000000LL;
667 res = DIV_ROUND_CLOSEST(vref, full_scale);
668 gain = DIV_ROUND_CLOSEST(res, val2);
669 res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain);
670
671 if (st->channels[chan->address].cfg.pga_bits != res)
672 st->channels[chan->address].cfg.live = false;
673
674 st->channels[chan->address].cfg.pga_bits = res;
675 break;
676 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
677 if (val2 != 0) {
678 ret = -EINVAL;
679 break;
680 }
681
682 ad7124_set_3db_filter_freq(st, chan->address, val);
683 break;
684 default:
685 ret = -EINVAL;
686 }
687
688 mutex_unlock(&st->cfgs_lock);
689 return ret;
690 }
691
ad7124_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)692 static int ad7124_reg_access(struct iio_dev *indio_dev,
693 unsigned int reg,
694 unsigned int writeval,
695 unsigned int *readval)
696 {
697 struct ad7124_state *st = iio_priv(indio_dev);
698 int ret;
699
700 if (reg >= ARRAY_SIZE(ad7124_reg_size))
701 return -EINVAL;
702
703 if (readval)
704 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
705 readval);
706 else
707 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
708 writeval);
709
710 return ret;
711 }
712
713 static IIO_CONST_ATTR(in_voltage_scale_available,
714 "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
715
716 static struct attribute *ad7124_attributes[] = {
717 &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
718 NULL,
719 };
720
721 static const struct attribute_group ad7124_attrs_group = {
722 .attrs = ad7124_attributes,
723 };
724
ad7124_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)725 static int ad7124_update_scan_mode(struct iio_dev *indio_dev,
726 const unsigned long *scan_mask)
727 {
728 struct ad7124_state *st = iio_priv(indio_dev);
729 bool bit_set;
730 int ret;
731 int i;
732
733 mutex_lock(&st->cfgs_lock);
734 for (i = 0; i < st->num_channels; i++) {
735 bit_set = test_bit(i, scan_mask);
736 if (bit_set)
737 ret = __ad7124_set_channel(&st->sd, i);
738 else
739 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK,
740 0, 2);
741 if (ret < 0) {
742 mutex_unlock(&st->cfgs_lock);
743
744 return ret;
745 }
746 }
747
748 mutex_unlock(&st->cfgs_lock);
749
750 return 0;
751 }
752
753 static const struct iio_info ad7124_info = {
754 .read_raw = ad7124_read_raw,
755 .write_raw = ad7124_write_raw,
756 .debugfs_reg_access = &ad7124_reg_access,
757 .validate_trigger = ad_sd_validate_trigger,
758 .update_scan_mode = ad7124_update_scan_mode,
759 .attrs = &ad7124_attrs_group,
760 };
761
ad7124_soft_reset(struct ad7124_state * st)762 static int ad7124_soft_reset(struct ad7124_state *st)
763 {
764 unsigned int readval, timeout;
765 int ret;
766
767 ret = ad_sd_reset(&st->sd, 64);
768 if (ret < 0)
769 return ret;
770
771 fsleep(200);
772 timeout = 100;
773 do {
774 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
775 if (ret < 0)
776 return ret;
777
778 if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
779 return 0;
780
781 /* The AD7124 requires typically 2ms to power up and settle */
782 usleep_range(100, 2000);
783 } while (--timeout);
784
785 dev_err(&st->sd.spi->dev, "Soft reset failed\n");
786
787 return -EIO;
788 }
789
ad7124_check_chip_id(struct ad7124_state * st)790 static int ad7124_check_chip_id(struct ad7124_state *st)
791 {
792 unsigned int readval, chip_id, silicon_rev;
793 int ret;
794
795 ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
796 if (ret < 0)
797 return ret;
798
799 chip_id = AD7124_DEVICE_ID_GET(readval);
800 silicon_rev = AD7124_SILICON_REV_GET(readval);
801
802 if (chip_id != st->chip_info->chip_id) {
803 dev_err(&st->sd.spi->dev,
804 "Chip ID mismatch: expected %u, got %u\n",
805 st->chip_info->chip_id, chip_id);
806 return -ENODEV;
807 }
808
809 if (silicon_rev == 0) {
810 dev_err(&st->sd.spi->dev,
811 "Silicon revision empty. Chip may not be present\n");
812 return -ENODEV;
813 }
814
815 return 0;
816 }
817
ad7124_parse_channel_config(struct iio_dev * indio_dev,struct device * dev)818 static int ad7124_parse_channel_config(struct iio_dev *indio_dev,
819 struct device *dev)
820 {
821 struct ad7124_state *st = iio_priv(indio_dev);
822 struct ad7124_channel_config *cfg;
823 struct ad7124_channel *channels;
824 struct iio_chan_spec *chan;
825 unsigned int ain[2], channel = 0, tmp;
826 int ret;
827
828 st->num_channels = device_get_child_node_count(dev);
829 if (!st->num_channels)
830 return dev_err_probe(dev, -ENODEV, "no channel children\n");
831
832 chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
833 sizeof(*chan), GFP_KERNEL);
834 if (!chan)
835 return -ENOMEM;
836
837 channels = devm_kcalloc(indio_dev->dev.parent, st->num_channels, sizeof(*channels),
838 GFP_KERNEL);
839 if (!channels)
840 return -ENOMEM;
841
842 indio_dev->channels = chan;
843 indio_dev->num_channels = st->num_channels;
844 st->channels = channels;
845
846 device_for_each_child_node_scoped(dev, child) {
847 ret = fwnode_property_read_u32(child, "reg", &channel);
848 if (ret)
849 return ret;
850
851 if (channel >= indio_dev->num_channels)
852 return dev_err_probe(dev, -EINVAL,
853 "Channel index >= number of channels\n");
854
855 ret = fwnode_property_read_u32_array(child, "diff-channels",
856 ain, 2);
857 if (ret)
858 return ret;
859
860 st->channels[channel].nr = channel;
861 st->channels[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
862 AD7124_CHANNEL_AINM(ain[1]);
863
864 cfg = &st->channels[channel].cfg;
865 cfg->bipolar = fwnode_property_read_bool(child, "bipolar");
866
867 ret = fwnode_property_read_u32(child, "adi,reference-select", &tmp);
868 if (ret)
869 cfg->refsel = AD7124_INT_REF;
870 else
871 cfg->refsel = tmp;
872
873 cfg->buf_positive =
874 fwnode_property_read_bool(child, "adi,buffered-positive");
875 cfg->buf_negative =
876 fwnode_property_read_bool(child, "adi,buffered-negative");
877
878 chan[channel] = ad7124_channel_template;
879 chan[channel].address = channel;
880 chan[channel].scan_index = channel;
881 chan[channel].channel = ain[0];
882 chan[channel].channel2 = ain[1];
883 }
884
885 return 0;
886 }
887
ad7124_setup(struct ad7124_state * st)888 static int ad7124_setup(struct ad7124_state *st)
889 {
890 unsigned int fclk, power_mode;
891 int i, ret;
892
893 fclk = clk_get_rate(st->mclk);
894 if (!fclk)
895 return -EINVAL;
896
897 /* The power mode changes the master clock frequency */
898 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
899 ARRAY_SIZE(ad7124_master_clk_freq_hz),
900 fclk);
901 if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
902 ret = clk_set_rate(st->mclk, fclk);
903 if (ret)
904 return ret;
905 }
906
907 /* Set the power mode */
908 st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
909 st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
910 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
911 if (ret < 0)
912 return ret;
913
914 mutex_init(&st->cfgs_lock);
915 INIT_KFIFO(st->live_cfgs_fifo);
916 for (i = 0; i < st->num_channels; i++) {
917
918 ret = ad7124_init_config_vref(st, &st->channels[i].cfg);
919 if (ret < 0)
920 return ret;
921
922 /*
923 * 9.38 SPS is the minimum output data rate supported
924 * regardless of the selected power mode. Round it up to 10 and
925 * set all channels to this default value.
926 */
927 ad7124_set_channel_odr(st, i, 10);
928 }
929
930 return ret;
931 }
932
ad7124_reg_disable(void * r)933 static void ad7124_reg_disable(void *r)
934 {
935 regulator_disable(r);
936 }
937
ad7124_probe(struct spi_device * spi)938 static int ad7124_probe(struct spi_device *spi)
939 {
940 const struct ad7124_chip_info *info;
941 struct ad7124_state *st;
942 struct iio_dev *indio_dev;
943 int i, ret;
944
945 info = spi_get_device_match_data(spi);
946 if (!info)
947 return -ENODEV;
948
949 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
950 if (!indio_dev)
951 return -ENOMEM;
952
953 st = iio_priv(indio_dev);
954
955 st->chip_info = info;
956
957 indio_dev->name = st->chip_info->name;
958 indio_dev->modes = INDIO_DIRECT_MODE;
959 indio_dev->info = &ad7124_info;
960
961 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
962 if (ret < 0)
963 return ret;
964
965 ret = ad7124_parse_channel_config(indio_dev, &spi->dev);
966 if (ret < 0)
967 return ret;
968
969 for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
970 if (i == AD7124_INT_REF)
971 continue;
972
973 st->vref[i] = devm_regulator_get_optional(&spi->dev,
974 ad7124_ref_names[i]);
975 if (PTR_ERR(st->vref[i]) == -ENODEV)
976 continue;
977 else if (IS_ERR(st->vref[i]))
978 return PTR_ERR(st->vref[i]);
979
980 ret = regulator_enable(st->vref[i]);
981 if (ret)
982 return ret;
983
984 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
985 st->vref[i]);
986 if (ret)
987 return ret;
988 }
989
990 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
991 if (IS_ERR(st->mclk))
992 return PTR_ERR(st->mclk);
993
994 ret = ad7124_soft_reset(st);
995 if (ret < 0)
996 return ret;
997
998 ret = ad7124_check_chip_id(st);
999 if (ret)
1000 return ret;
1001
1002 ret = ad7124_setup(st);
1003 if (ret < 0)
1004 return ret;
1005
1006 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
1007 if (ret < 0)
1008 return ret;
1009
1010 return devm_iio_device_register(&spi->dev, indio_dev);
1011
1012 }
1013
1014 static const struct of_device_id ad7124_of_match[] = {
1015 { .compatible = "adi,ad7124-4",
1016 .data = &ad7124_chip_info_tbl[ID_AD7124_4], },
1017 { .compatible = "adi,ad7124-8",
1018 .data = &ad7124_chip_info_tbl[ID_AD7124_8], },
1019 { },
1020 };
1021 MODULE_DEVICE_TABLE(of, ad7124_of_match);
1022
1023 static const struct spi_device_id ad71124_ids[] = {
1024 { "ad7124-4", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_4] },
1025 { "ad7124-8", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_8] },
1026 {}
1027 };
1028 MODULE_DEVICE_TABLE(spi, ad71124_ids);
1029
1030 static struct spi_driver ad71124_driver = {
1031 .driver = {
1032 .name = "ad7124",
1033 .of_match_table = ad7124_of_match,
1034 },
1035 .probe = ad7124_probe,
1036 .id_table = ad71124_ids,
1037 };
1038 module_spi_driver(ad71124_driver);
1039
1040 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
1041 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
1042 MODULE_LICENSE("GPL");
1043 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);
1044