xref: /linux/drivers/iio/dac/ad5360.c (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Analog devices AD5360, AD5361, AD5362, AD5363, AD5370, AD5371, AD5373
4  * multi-channel Digital to Analog Converters driver
5  *
6  * Copyright 2011 Analog Devices Inc.
7  */
8 
9 #include <linux/device.h>
10 #include <linux/err.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/spi/spi.h>
14 #include <linux/slab.h>
15 #include <linux/sysfs.h>
16 #include <linux/regulator/consumer.h>
17 
18 #include <linux/iio/iio.h>
19 #include <linux/iio/sysfs.h>
20 
21 #define AD5360_CMD(x)				((x) << 22)
22 #define AD5360_ADDR(x)				((x) << 16)
23 
24 #define AD5360_READBACK_TYPE(x)			((x) << 13)
25 #define AD5360_READBACK_ADDR(x)			((x) << 7)
26 
27 #define AD5360_CHAN_ADDR(chan)			((chan) + 0x8)
28 
29 #define AD5360_CMD_WRITE_DATA			0x3
30 #define AD5360_CMD_WRITE_OFFSET			0x2
31 #define AD5360_CMD_WRITE_GAIN			0x1
32 #define AD5360_CMD_SPECIAL_FUNCTION		0x0
33 
34 /* Special function register addresses */
35 #define AD5360_REG_SF_NOP			0x0
36 #define AD5360_REG_SF_CTRL			0x1
37 #define AD5360_REG_SF_OFS(x)			(0x2 + (x))
38 #define AD5360_REG_SF_READBACK			0x5
39 
40 #define AD5360_SF_CTRL_PWR_DOWN			BIT(0)
41 
42 #define AD5360_READBACK_X1A			0x0
43 #define AD5360_READBACK_X1B			0x1
44 #define AD5360_READBACK_OFFSET			0x2
45 #define AD5360_READBACK_GAIN			0x3
46 #define AD5360_READBACK_SF			0x4
47 
48 
49 /**
50  * struct ad5360_chip_info - chip specific information
51  * @channel_template:	channel specification template
52  * @num_channels:	number of channels
53  * @channels_per_group:	number of channels per group
54  * @num_vrefs:		number of vref supplies for the chip
55 */
56 
57 struct ad5360_chip_info {
58 	struct iio_chan_spec	channel_template;
59 	unsigned int		num_channels;
60 	unsigned int		channels_per_group;
61 	unsigned int		num_vrefs;
62 };
63 
64 /**
65  * struct ad5360_state - driver instance specific data
66  * @spi:		spi_device
67  * @chip_info:		chip model specific constants, available modes etc
68  * @vref_reg:		vref supply regulators
69  * @ctrl:		control register cache
70  * @lock:		lock to protect the data buffer during SPI ops
71  * @data:		spi transfer buffers
72  */
73 
74 struct ad5360_state {
75 	struct spi_device		*spi;
76 	const struct ad5360_chip_info	*chip_info;
77 	struct regulator_bulk_data	vref_reg[3];
78 	unsigned int			ctrl;
79 	struct mutex			lock;
80 
81 	/*
82 	 * DMA (thus cache coherency maintenance) may require the
83 	 * transfer buffers to live in their own cache lines.
84 	 */
85 	union {
86 		__be32 d32;
87 		u8 d8[4];
88 	} data[2] __aligned(IIO_DMA_MINALIGN);
89 };
90 
91 enum ad5360_type {
92 	ID_AD5360,
93 	ID_AD5361,
94 	ID_AD5362,
95 	ID_AD5363,
96 	ID_AD5370,
97 	ID_AD5371,
98 	ID_AD5372,
99 	ID_AD5373,
100 };
101 
102 #define AD5360_CHANNEL(bits) {					\
103 	.type = IIO_VOLTAGE,					\
104 	.indexed = 1,						\
105 	.output = 1,						\
106 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
107 		BIT(IIO_CHAN_INFO_SCALE) |				\
108 		BIT(IIO_CHAN_INFO_OFFSET) |				\
109 		BIT(IIO_CHAN_INFO_CALIBSCALE) |			\
110 		BIT(IIO_CHAN_INFO_CALIBBIAS),			\
111 	.scan_type = {						\
112 		.sign = 'u',					\
113 		.realbits = (bits),				\
114 		.storagebits = 16,				\
115 		.shift = 16 - (bits),				\
116 	},							\
117 }
118 
119 static const struct ad5360_chip_info ad5360_chip_info_tbl[] = {
120 	[ID_AD5360] = {
121 		.channel_template = AD5360_CHANNEL(16),
122 		.num_channels = 16,
123 		.channels_per_group = 8,
124 		.num_vrefs = 2,
125 	},
126 	[ID_AD5361] = {
127 		.channel_template = AD5360_CHANNEL(14),
128 		.num_channels = 16,
129 		.channels_per_group = 8,
130 		.num_vrefs = 2,
131 	},
132 	[ID_AD5362] = {
133 		.channel_template = AD5360_CHANNEL(16),
134 		.num_channels = 8,
135 		.channels_per_group = 4,
136 		.num_vrefs = 2,
137 	},
138 	[ID_AD5363] = {
139 		.channel_template = AD5360_CHANNEL(14),
140 		.num_channels = 8,
141 		.channels_per_group = 4,
142 		.num_vrefs = 2,
143 	},
144 	[ID_AD5370] = {
145 		.channel_template = AD5360_CHANNEL(16),
146 		.num_channels = 40,
147 		.channels_per_group = 8,
148 		.num_vrefs = 2,
149 	},
150 	[ID_AD5371] = {
151 		.channel_template = AD5360_CHANNEL(14),
152 		.num_channels = 40,
153 		.channels_per_group = 8,
154 		.num_vrefs = 3,
155 	},
156 	[ID_AD5372] = {
157 		.channel_template = AD5360_CHANNEL(16),
158 		.num_channels = 32,
159 		.channels_per_group = 8,
160 		.num_vrefs = 2,
161 	},
162 	[ID_AD5373] = {
163 		.channel_template = AD5360_CHANNEL(14),
164 		.num_channels = 32,
165 		.channels_per_group = 8,
166 		.num_vrefs = 2,
167 	},
168 };
169 
ad5360_get_channel_vref_index(struct ad5360_state * st,unsigned int channel)170 static unsigned int ad5360_get_channel_vref_index(struct ad5360_state *st,
171 	unsigned int channel)
172 {
173 	unsigned int i;
174 
175 	/* The first groups have their own vref, while the remaining groups
176 	 * share the last vref */
177 	i = channel / st->chip_info->channels_per_group;
178 	if (i >= st->chip_info->num_vrefs)
179 		i = st->chip_info->num_vrefs - 1;
180 
181 	return i;
182 }
183 
ad5360_get_channel_vref(struct ad5360_state * st,unsigned int channel)184 static int ad5360_get_channel_vref(struct ad5360_state *st,
185 	unsigned int channel)
186 {
187 	unsigned int i = ad5360_get_channel_vref_index(st, channel);
188 
189 	return regulator_get_voltage(st->vref_reg[i].consumer);
190 }
191 
192 
ad5360_write_unlocked(struct iio_dev * indio_dev,unsigned int cmd,unsigned int addr,unsigned int val,unsigned int shift)193 static int ad5360_write_unlocked(struct iio_dev *indio_dev,
194 	unsigned int cmd, unsigned int addr, unsigned int val,
195 	unsigned int shift)
196 {
197 	struct ad5360_state *st = iio_priv(indio_dev);
198 
199 	val <<= shift;
200 	val |= AD5360_CMD(cmd) | AD5360_ADDR(addr);
201 	st->data[0].d32 = cpu_to_be32(val);
202 
203 	return spi_write(st->spi, &st->data[0].d8[1], 3);
204 }
205 
ad5360_write(struct iio_dev * indio_dev,unsigned int cmd,unsigned int addr,unsigned int val,unsigned int shift)206 static int ad5360_write(struct iio_dev *indio_dev, unsigned int cmd,
207 	unsigned int addr, unsigned int val, unsigned int shift)
208 {
209 	int ret;
210 	struct ad5360_state *st = iio_priv(indio_dev);
211 
212 	mutex_lock(&st->lock);
213 	ret = ad5360_write_unlocked(indio_dev, cmd, addr, val, shift);
214 	mutex_unlock(&st->lock);
215 
216 	return ret;
217 }
218 
ad5360_read(struct iio_dev * indio_dev,unsigned int type,unsigned int addr)219 static int ad5360_read(struct iio_dev *indio_dev, unsigned int type,
220 	unsigned int addr)
221 {
222 	struct ad5360_state *st = iio_priv(indio_dev);
223 	int ret;
224 	struct spi_transfer t[] = {
225 		{
226 			.tx_buf = &st->data[0].d8[1],
227 			.len = 3,
228 			.cs_change = 1,
229 		}, {
230 			.rx_buf = &st->data[1].d8[1],
231 			.len = 3,
232 		},
233 	};
234 
235 	mutex_lock(&st->lock);
236 
237 	st->data[0].d32 = cpu_to_be32(AD5360_CMD(AD5360_CMD_SPECIAL_FUNCTION) |
238 		AD5360_ADDR(AD5360_REG_SF_READBACK) |
239 		AD5360_READBACK_TYPE(type) |
240 		AD5360_READBACK_ADDR(addr));
241 
242 	ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
243 	if (ret >= 0)
244 		ret = be32_to_cpu(st->data[1].d32) & 0xffff;
245 
246 	mutex_unlock(&st->lock);
247 
248 	return ret;
249 }
250 
ad5360_read_dac_powerdown(struct device * dev,struct device_attribute * attr,char * buf)251 static ssize_t ad5360_read_dac_powerdown(struct device *dev,
252 					   struct device_attribute *attr,
253 					   char *buf)
254 {
255 	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
256 	struct ad5360_state *st = iio_priv(indio_dev);
257 
258 	return sysfs_emit(buf, "%d\n", (bool)(st->ctrl & AD5360_SF_CTRL_PWR_DOWN));
259 }
260 
ad5360_update_ctrl(struct iio_dev * indio_dev,unsigned int set,unsigned int clr)261 static int ad5360_update_ctrl(struct iio_dev *indio_dev, unsigned int set,
262 	unsigned int clr)
263 {
264 	struct ad5360_state *st = iio_priv(indio_dev);
265 	unsigned int ret;
266 
267 	mutex_lock(&st->lock);
268 
269 	st->ctrl |= set;
270 	st->ctrl &= ~clr;
271 
272 	ret = ad5360_write_unlocked(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
273 			AD5360_REG_SF_CTRL, st->ctrl, 0);
274 
275 	mutex_unlock(&st->lock);
276 
277 	return ret;
278 }
279 
ad5360_write_dac_powerdown(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)280 static ssize_t ad5360_write_dac_powerdown(struct device *dev,
281 	struct device_attribute *attr, const char *buf, size_t len)
282 {
283 	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
284 	bool pwr_down;
285 	int ret;
286 
287 	ret = kstrtobool(buf, &pwr_down);
288 	if (ret)
289 		return ret;
290 
291 	if (pwr_down)
292 		ret = ad5360_update_ctrl(indio_dev, AD5360_SF_CTRL_PWR_DOWN, 0);
293 	else
294 		ret = ad5360_update_ctrl(indio_dev, 0, AD5360_SF_CTRL_PWR_DOWN);
295 
296 	return ret ? ret : len;
297 }
298 
299 static IIO_DEVICE_ATTR(out_voltage_powerdown,
300 			S_IRUGO | S_IWUSR,
301 			ad5360_read_dac_powerdown,
302 			ad5360_write_dac_powerdown, 0);
303 
304 static struct attribute *ad5360_attributes[] = {
305 	&iio_dev_attr_out_voltage_powerdown.dev_attr.attr,
306 	NULL,
307 };
308 
309 static const struct attribute_group ad5360_attribute_group = {
310 	.attrs = ad5360_attributes,
311 };
312 
ad5360_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)313 static int ad5360_write_raw(struct iio_dev *indio_dev,
314 			       struct iio_chan_spec const *chan,
315 			       int val,
316 			       int val2,
317 			       long mask)
318 {
319 	struct ad5360_state *st = iio_priv(indio_dev);
320 	int max_val = (1 << chan->scan_type.realbits);
321 	unsigned int ofs_index;
322 
323 	switch (mask) {
324 	case IIO_CHAN_INFO_RAW:
325 		if (val >= max_val || val < 0)
326 			return -EINVAL;
327 
328 		return ad5360_write(indio_dev, AD5360_CMD_WRITE_DATA,
329 				 chan->address, val, chan->scan_type.shift);
330 
331 	case IIO_CHAN_INFO_CALIBBIAS:
332 		if (val >= max_val || val < 0)
333 			return -EINVAL;
334 
335 		return ad5360_write(indio_dev, AD5360_CMD_WRITE_OFFSET,
336 				 chan->address, val, chan->scan_type.shift);
337 
338 	case IIO_CHAN_INFO_CALIBSCALE:
339 		if (val >= max_val || val < 0)
340 			return -EINVAL;
341 
342 		return ad5360_write(indio_dev, AD5360_CMD_WRITE_GAIN,
343 				 chan->address, val, chan->scan_type.shift);
344 
345 	case IIO_CHAN_INFO_OFFSET:
346 		if (val <= -max_val || val > 0)
347 			return -EINVAL;
348 
349 		val = -val;
350 
351 		/* offset is supposed to have the same scale as raw, but it
352 		 * is always 14bits wide, so on a chip where the raw value has
353 		 * more bits, we need to shift offset. */
354 		val >>= (chan->scan_type.realbits - 14);
355 
356 		/* There is one DAC offset register per vref. Changing one
357 		 * channels offset will also change the offset for all other
358 		 * channels which share the same vref supply. */
359 		ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
360 		return ad5360_write(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
361 				 AD5360_REG_SF_OFS(ofs_index), val, 0);
362 	default:
363 		break;
364 	}
365 
366 	return -EINVAL;
367 }
368 
ad5360_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)369 static int ad5360_read_raw(struct iio_dev *indio_dev,
370 			   struct iio_chan_spec const *chan,
371 			   int *val,
372 			   int *val2,
373 			   long m)
374 {
375 	struct ad5360_state *st = iio_priv(indio_dev);
376 	unsigned int ofs_index;
377 	int scale_uv;
378 	int ret;
379 
380 	switch (m) {
381 	case IIO_CHAN_INFO_RAW:
382 		ret = ad5360_read(indio_dev, AD5360_READBACK_X1A,
383 			chan->address);
384 		if (ret < 0)
385 			return ret;
386 		*val = ret >> chan->scan_type.shift;
387 		return IIO_VAL_INT;
388 	case IIO_CHAN_INFO_SCALE:
389 		scale_uv = ad5360_get_channel_vref(st, chan->channel);
390 		if (scale_uv < 0)
391 			return scale_uv;
392 
393 		/* vout = 4 * vref * dac_code */
394 		*val = scale_uv * 4 / 1000;
395 		*val2 = chan->scan_type.realbits;
396 		return IIO_VAL_FRACTIONAL_LOG2;
397 	case IIO_CHAN_INFO_CALIBBIAS:
398 		ret = ad5360_read(indio_dev, AD5360_READBACK_OFFSET,
399 			chan->address);
400 		if (ret < 0)
401 			return ret;
402 		*val = ret;
403 		return IIO_VAL_INT;
404 	case IIO_CHAN_INFO_CALIBSCALE:
405 		ret = ad5360_read(indio_dev, AD5360_READBACK_GAIN,
406 			chan->address);
407 		if (ret < 0)
408 			return ret;
409 		*val = ret;
410 		return IIO_VAL_INT;
411 	case IIO_CHAN_INFO_OFFSET:
412 		ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
413 		ret = ad5360_read(indio_dev, AD5360_READBACK_SF,
414 			AD5360_REG_SF_OFS(ofs_index));
415 		if (ret < 0)
416 			return ret;
417 
418 		ret <<= (chan->scan_type.realbits - 14);
419 		*val = -ret;
420 		return IIO_VAL_INT;
421 	}
422 
423 	return -EINVAL;
424 }
425 
426 static const struct iio_info ad5360_info = {
427 	.read_raw = ad5360_read_raw,
428 	.write_raw = ad5360_write_raw,
429 	.attrs = &ad5360_attribute_group,
430 };
431 
432 static const char * const ad5360_vref_name[] = {
433 	 "vref0", "vref1", "vref2"
434 };
435 
ad5360_alloc_channels(struct iio_dev * indio_dev)436 static int ad5360_alloc_channels(struct iio_dev *indio_dev)
437 {
438 	struct ad5360_state *st = iio_priv(indio_dev);
439 	struct iio_chan_spec *channels;
440 	unsigned int i;
441 
442 	channels = kcalloc(st->chip_info->num_channels,
443 			   sizeof(struct iio_chan_spec), GFP_KERNEL);
444 
445 	if (!channels)
446 		return -ENOMEM;
447 
448 	for (i = 0; i < st->chip_info->num_channels; ++i) {
449 		channels[i] = st->chip_info->channel_template;
450 		channels[i].channel = i;
451 		channels[i].address = AD5360_CHAN_ADDR(i);
452 	}
453 
454 	indio_dev->channels = channels;
455 
456 	return 0;
457 }
458 
ad5360_probe(struct spi_device * spi)459 static int ad5360_probe(struct spi_device *spi)
460 {
461 	enum ad5360_type type = spi_get_device_id(spi)->driver_data;
462 	struct iio_dev *indio_dev;
463 	struct ad5360_state *st;
464 	unsigned int i;
465 	int ret;
466 
467 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
468 	if (indio_dev == NULL) {
469 		dev_err(&spi->dev, "Failed to allocate iio device\n");
470 		return  -ENOMEM;
471 	}
472 
473 	st = iio_priv(indio_dev);
474 	spi_set_drvdata(spi, indio_dev);
475 
476 	st->chip_info = &ad5360_chip_info_tbl[type];
477 	st->spi = spi;
478 
479 	indio_dev->name = spi_get_device_id(spi)->name;
480 	indio_dev->info = &ad5360_info;
481 	indio_dev->modes = INDIO_DIRECT_MODE;
482 	indio_dev->num_channels = st->chip_info->num_channels;
483 
484 	mutex_init(&st->lock);
485 
486 	ret = ad5360_alloc_channels(indio_dev);
487 	if (ret) {
488 		dev_err(&spi->dev, "Failed to allocate channel spec: %d\n", ret);
489 		return ret;
490 	}
491 
492 	for (i = 0; i < st->chip_info->num_vrefs; ++i)
493 		st->vref_reg[i].supply = ad5360_vref_name[i];
494 
495 	ret = devm_regulator_bulk_get(&st->spi->dev, st->chip_info->num_vrefs,
496 		st->vref_reg);
497 	if (ret) {
498 		dev_err(&spi->dev, "Failed to request vref regulators: %d\n", ret);
499 		goto error_free_channels;
500 	}
501 
502 	ret = regulator_bulk_enable(st->chip_info->num_vrefs, st->vref_reg);
503 	if (ret) {
504 		dev_err(&spi->dev, "Failed to enable vref regulators: %d\n", ret);
505 		goto error_free_channels;
506 	}
507 
508 	ret = iio_device_register(indio_dev);
509 	if (ret) {
510 		dev_err(&spi->dev, "Failed to register iio device: %d\n", ret);
511 		goto error_disable_reg;
512 	}
513 
514 	return 0;
515 
516 error_disable_reg:
517 	regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
518 error_free_channels:
519 	kfree(indio_dev->channels);
520 
521 	return ret;
522 }
523 
ad5360_remove(struct spi_device * spi)524 static void ad5360_remove(struct spi_device *spi)
525 {
526 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
527 	struct ad5360_state *st = iio_priv(indio_dev);
528 
529 	iio_device_unregister(indio_dev);
530 
531 	kfree(indio_dev->channels);
532 
533 	regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
534 }
535 
536 static const struct spi_device_id ad5360_ids[] = {
537 	{ "ad5360", ID_AD5360 },
538 	{ "ad5361", ID_AD5361 },
539 	{ "ad5362", ID_AD5362 },
540 	{ "ad5363", ID_AD5363 },
541 	{ "ad5370", ID_AD5370 },
542 	{ "ad5371", ID_AD5371 },
543 	{ "ad5372", ID_AD5372 },
544 	{ "ad5373", ID_AD5373 },
545 	{}
546 };
547 MODULE_DEVICE_TABLE(spi, ad5360_ids);
548 
549 static struct spi_driver ad5360_driver = {
550 	.driver = {
551 		   .name = "ad5360",
552 	},
553 	.probe = ad5360_probe,
554 	.remove = ad5360_remove,
555 	.id_table = ad5360_ids,
556 };
557 module_spi_driver(ad5360_driver);
558 
559 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
560 MODULE_DESCRIPTION("Analog Devices AD5360/61/62/63/70/71/72/73 DAC");
561 MODULE_LICENSE("GPL v2");
562