xref: /titanic_41/usr/src/uts/common/sys/scsi/adapters/pmcs/pmcs.h (revision 1f81b46471e38fdeb9ab74c25510b2f903f8af12)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
23  */
24 /*
25  * This file is the principle header file for the PMCS driver
26  */
27 #ifndef _PMCS_H
28 #define	_PMCS_H
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 
34 #include <sys/cpuvar.h>
35 #include <sys/ddi.h>
36 #include <sys/sunddi.h>
37 #include <sys/modctl.h>
38 #include <sys/pci.h>
39 #include <sys/pcie.h>
40 #include <sys/file.h>
41 #include <sys/isa_defs.h>
42 #include <sys/sunmdi.h>
43 #include <sys/mdi_impldefs.h>
44 #include <sys/scsi/scsi.h>
45 #include <sys/scsi/impl/scsi_reset_notify.h>
46 #include <sys/scsi/impl/scsi_sas.h>
47 #include <sys/scsi/impl/smp_transport.h>
48 #include <sys/scsi/generic/sas.h>
49 #include <sys/scsi/generic/smp_frames.h>
50 #include <sys/atomic.h>
51 #include <sys/byteorder.h>
52 #include <sys/sysmacros.h>
53 #include <sys/bitmap.h>
54 #include <sys/queue.h>
55 #include <sys/sdt.h>
56 #include <sys/ddifm.h>
57 #include <sys/fm/protocol.h>
58 #include <sys/fm/util.h>
59 #include <sys/fm/io/ddi.h>
60 #include <sys/scsi/impl/spc3_types.h>
61 
62 typedef struct pmcs_hw pmcs_hw_t;
63 typedef struct pmcs_iport pmcs_iport_t;
64 typedef struct pmcs_phy pmcs_phy_t;
65 typedef struct lsas_cmd lsas_cmd_t;
66 typedef struct lsas_result lsas_result_t;
67 typedef struct lsata_cmd lsata_cmd_t;
68 typedef struct lsata_result lsata_result_t;
69 typedef struct pmcwork pmcwork_t;
70 typedef struct pmcs_cmd pmcs_cmd_t;
71 typedef	struct pmcs_xscsi pmcs_xscsi_t;
72 typedef	struct pmcs_lun pmcs_lun_t;
73 typedef struct pmcs_chunk pmcs_chunk_t;
74 
75 #include <sys/scsi/adapters/pmcs/pmcs_param.h>
76 #include <sys/scsi/adapters/pmcs/pmcs_reg.h>
77 #include <sys/scsi/adapters/pmcs/pmcs_mpi.h>
78 #include <sys/scsi/adapters/pmcs/pmcs_iomb.h>
79 #include <sys/scsi/adapters/pmcs/pmcs_sgl.h>
80 
81 #include <sys/scsi/adapters/pmcs/ata.h>
82 #include <sys/scsi/adapters/pmcs/pmcs_def.h>
83 #include <sys/scsi/adapters/pmcs/pmcs_proto.h>
84 #include <sys/scsi/adapters/pmcs/pmcs_scsa.h>
85 #include <sys/scsi/adapters/pmcs/pmcs_smhba.h>
86 
87 #define	PMCS_MAX_UA_SIZE	32
88 
89 struct pmcs_xscsi {
90 	uint32_t
91 		ca		:	1,		/* SATA specific */
92 		ncq		:	1,		/* SATA specific */
93 		pio		:	1,		/* SATA specific */
94 		special_needed	:	1,		/* SATA specific */
95 		special_running	:	1,		/* SATA specific */
96 		reset_success	:	1,		/* last reset ok */
97 		reset_wait	:	1,		/* wait for reset */
98 		resetting	:	1,		/* now resetting */
99 		recover_wait	:	1,		/* wait for recovery */
100 		recovering	:	1,		/* now recovering */
101 		event_recovery	:	1,		/* event recovery */
102 		draining	:	1,
103 		new		:	1,
104 		assigned	:	1,
105 		dev_gone	:	1,
106 		phy_addressable	:	1,		/* Direct attach SATA */
107 		dev_state	:	4;
108 	uint16_t			maxdepth;
109 	uint16_t			qdepth;
110 	uint16_t			actv_cnt;	/* Pkts ON CHIP */
111 	uint16_t			actv_pkts;	/* Pkts in driver */
112 	uint16_t			target_num;
113 	/* statlock protects both target stats and the special queue (sq) */
114 	kmutex_t			statlock;
115 	int32_t				ref_count;
116 	dev_info_t 			*dip;	/* Solaris device dip */
117 	pmcs_phy_t			*phy;
118 	STAILQ_HEAD(wqh, pmcs_cmd)	wq;
119 	pmcs_cmd_t			*wq_recovery_tail;	/* See below */
120 	kmutex_t			wqlock;
121 	STAILQ_HEAD(aqh, pmcs_cmd)	aq;
122 	kmutex_t			aqlock;
123 	STAILQ_HEAD(sqh, pmcs_cmd)	sq;		/* SATA specific */
124 	uint32_t			tagmap;		/* SATA specific */
125 	pmcs_hw_t			*pwp;
126 	ddi_soft_state_bystr		*lun_sstate;
127 	uint64_t			capacity;	/* SATA specific */
128 	char				unit_address[PMCS_MAX_UA_SIZE];
129 	kcondvar_t			reset_cv;
130 	kcondvar_t			abort_cv;
131 	char				*ua;
132 	pmcs_dtype_t			dtype;
133 	list_t				lun_list;	/* list of LUNs */
134 	struct smp_device		*smpd;		/* Ptr to smp_device */
135 };
136 
137 /*
138  * wq_recovery_tail in the pmcs_xscsi structure is a pointer to a command in
139  * the wait queue (wq).  That pointer is the last command in the wait queue
140  * that needs to be reissued after device state recovery is complete.  Commands
141  * that need to be retried are reinserted into the wq after wq_recovery_tail
142  * to maintain the order in which the commands were originally submitted.
143  */
144 
145 #define	PMCS_INVALID_TARGET_NUM		(uint16_t)-1
146 
147 #define	PMCS_TGT_WAIT_QUEUE		0x01
148 #define	PMCS_TGT_ACTIVE_QUEUE		0x02
149 #define	PMCS_TGT_SPECIAL_QUEUE		0x04
150 #define	PMCS_TGT_ALL_QUEUES		0xff
151 
152 /*
153  * LUN representation.  Just a LUN (number) and pointer to the target
154  * structure (pmcs_xscsi).
155  */
156 
157 struct pmcs_lun {
158 	list_node_t		lun_list_next;
159 	pmcs_xscsi_t		*target;
160 	struct scsi_device	*sd;
161 	uint64_t		lun_num;	/* lun64 */
162 	scsi_lun_t		scsi_lun;	/* Wire format */
163 	char			unit_address[PMCS_MAX_UA_SIZE];
164 };
165 
166 /*
167  * Interrupt coalescing values
168  */
169 #define	PMCS_MAX_IO_COMPS_PER_INTR	12
170 #define	PMCS_MAX_IO_COMPS_HIWAT_SHIFT	6
171 #define	PMCS_MAX_IO_COMPS_LOWAT_SHIFT	10
172 #define	PMCS_QUANTUM_TIME_USECS		(1000000 / 10)	/* 1/10th sec. */
173 #define	PMCS_MAX_COAL_TIMER		0x200	/* Don't set > than this */
174 #define	PMCS_MAX_CQ_THREADS		4
175 #define	PMCS_COAL_TIMER_GRAN		2	/* Go up/down by 2 usecs */
176 #define	PMCS_INTR_THRESHOLD(x)		((x) * 6 / 10)
177 
178 /*
179  * This structure is used to maintain state with regard to I/O interrupt
180  * coalescing.
181  */
182 
183 typedef struct pmcs_io_intr_coal_s {
184 	hrtime_t	nsecs_between_intrs;
185 	hrtime_t	last_io_comp;
186 	clock_t		quantum;
187 	uint32_t	num_io_completions;
188 	uint32_t	num_intrs;
189 	uint32_t	max_io_completions;
190 	uint32_t	intr_latency;
191 	uint32_t	intr_threshold;
192 	uint16_t	intr_coal_timer;
193 	boolean_t	timer_on;
194 	boolean_t	stop_thread;
195 	boolean_t	int_cleared;
196 } pmcs_io_intr_coal_t;
197 
198 typedef struct pmcs_cq_thr_info_s {
199 	kthread_t	*cq_thread;
200 	kmutex_t	cq_thr_lock;
201 	kcondvar_t	cq_cv;
202 	pmcs_hw_t	*cq_pwp;
203 } pmcs_cq_thr_info_t;
204 
205 typedef struct pmcs_cq_info_s {
206 	uint32_t		cq_threads;
207 	uint32_t		cq_next_disp_thr;
208 	boolean_t		cq_stop;
209 	pmcs_cq_thr_info_t	*cq_thr_info;
210 } pmcs_cq_info_t;
211 
212 typedef struct pmcs_iocomp_cb_s {
213 	pmcwork_t		*pwrk;
214 	char			iomb[PMCS_QENTRY_SIZE << 1];
215 	struct pmcs_iocomp_cb_s	*next;
216 } pmcs_iocomp_cb_t;
217 
218 typedef struct pmcs_iqp_trace_s {
219 	char		*head;
220 	char		*curpos;
221 	uint32_t	size_left;
222 } pmcs_iqp_trace_t;
223 
224 /*
225  * Used by string-based softstate as hint to possible size.
226  */
227 
228 #define	PMCS_TGT_SSTATE_SZ		64
229 #define	PMCS_LUN_SSTATE_SZ		4
230 
231 /*
232  * HBA iport node softstate
233  */
234 #define	PMCS_IPORT_INVALID_PORT_ID	0xf
235 
236 struct pmcs_iport {
237 	kmutex_t	lock;		/* iport lock */
238 	list_node_t	list_node;	/* list node for pwp->iports list_t */
239 	kmutex_t	refcnt_lock;	/* refcnt lock */
240 	kcondvar_t	refcnt_cv;	/* refcnt cv */
241 	int		refcnt;		/* refcnt for this iport */
242 	dev_info_t	*dip;		/* iport dip */
243 	pmcs_hw_t	*pwp;		/* back pointer to HBA state */
244 	pmcs_phy_t	*pptr;		/* pointer to this port's primary phy */
245 	enum {				/* unit address state in the phymap */
246 		UA_INACTIVE,
247 		UA_PEND_ACTIVATE,
248 		UA_ACTIVE,
249 		UA_PEND_DEACTIVATE
250 	} ua_state;
251 	char		*ua;		/* unit address (phy mask) */
252 	int		portid;		/* portid */
253 	int		report_skip;	/* skip or report during discovery */
254 	list_t		phys;		/* list of phys on this port */
255 	int		nphy;		/* number of phys in this port */
256 	scsi_hba_tgtmap_t	*iss_tgtmap;	/* tgtmap */
257 	ddi_soft_state_bystr	*tgt_sstate;	/* tgt softstate */
258 	/* SMP serialization */
259 	kmutex_t	smp_lock;
260 	kcondvar_t	smp_cv;
261 	boolean_t	smp_active;
262 	kthread_t	*smp_active_thread;
263 };
264 
265 struct pmcs_chunk {
266 	pmcs_chunk_t		*next;
267 	ddi_acc_handle_t	acc_handle;
268 	ddi_dma_handle_t	dma_handle;
269 	uint8_t			*addrp;
270 	uint64_t		dma_addr;
271 };
272 
273 /*
274  * HBA node (i.e. non-iport) softstate
275  */
276 struct pmcs_hw {
277 	/*
278 	 * Identity
279 	 */
280 	dev_info_t	*dip;
281 
282 	/*
283 	 * 16 possible initiator PHY WWNs
284 	 */
285 	uint64_t	sas_wwns[PMCS_MAX_PORTS];
286 
287 	/*
288 	 * Card State
289 	 */
290 	enum pwpstate {
291 		STATE_NIL,
292 		STATE_PROBING,
293 		STATE_RUNNING,
294 		STATE_UNPROBING,
295 		STATE_IN_RESET,
296 		STATE_DEAD
297 	} state;
298 
299 	/*
300 	 * Last reason for a soft reset
301 	 */
302 	enum pwp_last_reset_reason {
303 		PMCS_LAST_RST_UNINIT,
304 		PMCS_LAST_RST_ATTACH,
305 		PMCS_LAST_RST_FW_UPGRADE,
306 		PMCS_LAST_RST_FATAL_ERROR,
307 		PMCS_LAST_RST_STALL,
308 		PMCS_LAST_RST_QUIESCE,
309 		PMCS_LAST_RST_DETACH
310 	} last_reset_reason;
311 
312 	uint32_t
313 		fw_disable_update	: 1,
314 		fw_force_update		: 1,
315 		blocked			: 1,
316 		stuck			: 1,
317 		locks_initted		: 1,
318 		mpi_table_setup		: 1,
319 		hba_attached		: 1,
320 		iports_attached		: 1,
321 		suspended		: 1,
322 		separate_ports		: 1,
323 		fwlog			: 4,
324 		phymode			: 3,
325 		physpeed		: 3,
326 		resource_limited	: 1,
327 		configuring		: 1,
328 		ds_err_recovering	: 1,
329 		quiesced		: 1,
330 		fwlog_file		: 1,
331 		fw_active_img		: 1;	/* 1='A', 0='B' */
332 
333 	/*
334 	 * This HBA instance's iportmap and list of iport states.
335 	 * Note: iports_lock protects iports, iports_attached, and
336 	 * num_iports on the HBA softstate.
337 	 */
338 	krwlock_t		iports_lock;
339 	scsi_hba_iportmap_t	*hss_iportmap;
340 	list_t			iports;
341 	int			num_iports;
342 
343 	sas_phymap_t		*hss_phymap;
344 	int			phymap_active;
345 
346 	/*
347 	 * Locks
348 	 */
349 	kmutex_t	lock;
350 	kmutex_t	dma_lock;
351 	kmutex_t	axil_lock;
352 	kcondvar_t	drain_cv;
353 
354 	/*
355 	 * FMA Capabilities
356 	 */
357 	int		fm_capabilities;
358 
359 	/*
360 	 * Register Access Handles
361 	 */
362 	ddi_device_acc_attr_t 	dev_acc_attr;
363 	ddi_device_acc_attr_t	reg_acc_attr;
364 	ddi_acc_handle_t 	pci_acc_handle;
365 	ddi_acc_handle_t 	msg_acc_handle;
366 	ddi_acc_handle_t 	top_acc_handle;
367 	ddi_acc_handle_t	mpi_acc_handle;
368 	ddi_acc_handle_t	gsm_acc_handle;
369 	ddi_acc_handle_t	iqp_acchdls[PMCS_MAX_IQ];
370 	ddi_acc_handle_t	oqp_acchdls[PMCS_MAX_IQ];
371 	ddi_acc_handle_t	cip_acchdls;
372 	ddi_acc_handle_t	fwlog_acchdl;
373 	ddi_acc_handle_t	regdump_acchdl;
374 
375 	/*
376 	 * DMA Handles
377 	 */
378 	ddi_dma_attr_t		iqp_dma_attr;
379 	ddi_dma_attr_t		oqp_dma_attr;
380 	ddi_dma_attr_t		cip_dma_attr;
381 	ddi_dma_attr_t		fwlog_dma_attr;
382 	ddi_dma_attr_t		regdump_dma_attr;
383 	ddi_dma_handle_t 	iqp_handles[PMCS_MAX_IQ];
384 	ddi_dma_handle_t 	oqp_handles[PMCS_MAX_OQ];
385 	ddi_dma_handle_t	cip_handles;
386 	ddi_dma_handle_t	fwlog_hndl;
387 	ddi_dma_handle_t	regdump_hndl;
388 
389 	/*
390 	 * Register Pointers
391 	 */
392 	uint32_t	*msg_regs;	/* message unit registers */
393 	uint32_t	*top_regs;	/* top unit registers */
394 	uint32_t	*mpi_regs;	/* message passing unit registers */
395 	uint32_t	*gsm_regs;	/* GSM registers */
396 
397 	/*
398 	 * Message Passing and other offsets.
399 	 *
400 	 * mpi_offset is the offset within the fourth register set (mpi_regs)
401 	 * that contains the base of the MPI structures. Since this is actually
402 	 * set by the card firmware, it can change from startup to startup.
403 	 *
404 	 * The other offsets (gst, iqc, oqc) are for similar tables in
405 	 * MPI space, typically only accessed during setup.
406 	 */
407 	uint32_t	mpi_offset;
408 	uint32_t	mpi_gst_offset;
409 	uint32_t	mpi_iqc_offset;
410 	uint32_t	mpi_oqc_offset;
411 
412 	/*
413 	 * Inbound and outbound queue depth
414 	 */
415 	uint32_t	ioq_depth;
416 
417 	/*
418 	 * Kernel addresses and offsets for Inbound Queue Producer Indices
419 	 *
420 	 * See comments in pmcs_iomb.h about Inbound Queues. Since it
421 	 * is relatively expensive to go across the PCIe bus to read or
422 	 * write inside the card, we maintain shadow copies in kernel
423 	 * memory and update the card as needed.
424 	 */
425 	uint32_t	shadow_iqpi[PMCS_MAX_IQ];
426 	uint32_t	iqpi_offset[PMCS_MAX_IQ];
427 	uint32_t	last_iqci[PMCS_MAX_IQ];
428 	uint32_t	last_htag[PMCS_MAX_IQ];
429 	uint32_t	*iqp[PMCS_MAX_IQ];
430 	kmutex_t	iqp_lock[PMCS_NIQ];
431 
432 	pmcs_iqp_trace_t	*iqpt;
433 
434 	/*
435 	 * Kernel addresses and offsets for Outbound Queue Consumer Indices
436 	 */
437 	uint32_t	*oqp[PMCS_MAX_OQ];
438 	uint32_t	oqci_offset[PMCS_MAX_OQ];
439 
440 	/*
441 	 * Driver's copy of the outbound queue indices
442 	 */
443 
444 	uint32_t	oqci[PMCS_NOQ];
445 	uint32_t	oqpi[PMCS_NOQ];
446 
447 	/*
448 	 * DMA addresses for both Inbound and Outbound queues.
449 	 */
450 	uint64_t	oqaddr[PMCS_MAX_OQ];
451 	uint64_t	iqaddr[PMCS_MAX_IQ];
452 
453 	/*
454 	 * Producer/Queue Host Memory Pointers and scratch areas,
455 	 * as well as DMA scatter/gather chunk areas.
456 	 *
457 	 * See discussion in pmcs_def.h about how this is laid out.
458 	 */
459 	uint8_t		*cip;
460 	uint64_t	ciaddr;
461 
462 	/*
463 	 * Scratch area pointer and DMA addrress for SATA and SMP operations.
464 	 */
465 	void			*scratch;
466 	uint64_t		scratch_dma;
467 	volatile uint8_t	scratch_locked;	/* Scratch area ownership */
468 
469 	/*
470 	 * Firmware info
471 	 *
472 	 * fwlogp: Pointer to block of memory mapped for the event logs
473 	 * fwlogp_aap1: Pointer to the beginning of the AAP1 event log
474 	 * fwlogp_iop: Pointer to the beginning of the IOP event log
475 	 * fwaddr: The physical address of fwlogp
476 	 *
477 	 * fwlogfile_aap1/iop: Path to the saved AAP1/IOP event logs
478 	 * fwlog_max_entries_aap1/iop: Max # of entries in each log
479 	 * fwlog_oldest_idx_aap1/iop: Index of oldest entry in each log
480 	 * fwlog_latest_idx_aap1/iop: Index of newest entry in each log
481 	 * fwlog_threshold_aap1/iop: % full at which we save the event log
482 	 * fwlog_findex_aap1/iop: Suffix to each event log's next filename
483 	 *
484 	 * Firmware event logs are written out to the filenames specified in
485 	 * fwlogp_aap1/iop when the number of entries in the in-memory copy
486 	 * reaches or exceeds the threshold value.  The filenames are suffixed
487 	 * with .X where X is an integer ranging from 0 to 4.  This allows us
488 	 * to save up to 5MB of event log data for each log.
489 	 */
490 	uint32_t	*fwlogp;
491 	pmcs_fw_event_hdr_t *fwlogp_aap1;
492 	pmcs_fw_event_hdr_t *fwlogp_iop;
493 	uint64_t	fwaddr;
494 	char		fwlogfile_aap1[MAXPATHLEN + 1];
495 	uint32_t	fwlog_max_entries_aap1;
496 	uint32_t	fwlog_oldest_idx_aap1;
497 	uint32_t	fwlog_latest_idx_aap1;
498 	uint32_t	fwlog_threshold_aap1;
499 	uint32_t	fwlog_findex_aap1;
500 	char		fwlogfile_iop[MAXPATHLEN + 1];
501 	uint32_t	fwlog_max_entries_iop;
502 	uint32_t	fwlog_oldest_idx_iop;
503 	uint32_t	fwlog_latest_idx_iop;
504 	uint32_t	fwlog_threshold_iop;
505 	uint32_t	fwlog_findex_iop;
506 
507 	/*
508 	 * Internal register dump region and flash chunk DMA info
509 	 */
510 
511 	caddr_t		regdumpp;
512 	uint32_t	*flash_chunkp;
513 	uint64_t	flash_chunk_addr;
514 
515 	/*
516 	 * Copies of the last read MSGU and IOP heartbeats.
517 	 */
518 	uint32_t	last_msgu_tick;
519 	uint32_t	last_iop_tick;
520 
521 	/*
522 	 * Card information, some determined during MPI setup
523 	 */
524 	uint32_t	fw;		/* firmware version */
525 	uint32_t	ila_ver;	/* ILA version */
526 	uint8_t		max_iq;		/* maximum inbound queues this card */
527 	uint8_t 	max_oq;		/* "" outbound "" */
528 	uint8_t		nphy;		/* number of phys this card */
529 	uint8_t		chiprev;	/* chip revision */
530 	uint16_t	max_cmd;	/* max number of commands supported */
531 	uint16_t	max_dev;	/* max number of devices supported */
532 	uint16_t	last_wq_dev;	/* last dev whose wq was serviced */
533 
534 	/*
535 	 * Counter for the number of times watchdog fires.  We can use this
536 	 * to throttle events which fire off of the watchdog, such as the
537 	 * forward progress detection routine.
538 	 */
539 	uint8_t		watchdog_count;
540 
541 	/*
542 	 * Interrupt Setup stuff.
543 	 *
544 	 * int_type defines the kind of interrupt we're using with this card.
545 	 * oqvec defines the relationship between an Outbound Queue Number and
546 	 * a MSI-X vector.
547 	 */
548 	enum {
549 		PMCS_INT_NONE,
550 		PMCS_INT_TIMER,
551 		PMCS_INT_MSI,
552 		PMCS_INT_MSIX,
553 		PMCS_INT_FIXED
554 	} int_type;
555 	uint8_t			oqvec[PMCS_NOQ];
556 
557 	/*
558 	 * Interrupt handle table and size
559 	 */
560 	ddi_intr_handle_t	*ih_table;
561 	size_t			ih_table_size;
562 
563 	timeout_id_t		wdhandle;
564 	uint32_t		intr_mask;
565 	int			intr_cnt;
566 	int			intr_cap;
567 	uint32_t		odb_auto_clear;
568 
569 	/*
570 	 * DMA S/G chunk list
571 	 */
572 	int		nchunks;
573 	pmcs_chunk_t	*dma_chunklist;
574 
575 	/*
576 	 * Front of the DMA S/G chunk freelist
577 	 */
578 	pmcs_dmachunk_t	*dma_freelist;
579 
580 	/*
581 	 * PHY and Discovery Related Stuff
582 	 *
583 	 * The PMC chip can have up to 16 local phys. We build a level-first
584 	 * traversal tree of phys starting with the physical phys on the
585 	 * chip itself (i.e., treating the chip as if it were an expander).
586 	 *
587 	 * Our discovery process goes through a level and discovers what
588 	 * each entity is (and it's phy number within that expander's
589 	 * address space). It then configures each non-empty item (SAS,
590 	 * SATA/STP, EXPANDER). For expanders, it then performs
591 	 * discover on that expander itself via REPORT GENERAL and
592 	 * DISCOVERY SMP commands, attaching the discovered entities
593 	 * to the next level. Then we step down a level and continue
594 	 * (and so on).
595 	 *
596 	 * The PMC chip maintains an I_T_NEXUS notion based upon our
597 	 * registering each new device found (getting back a device handle).
598 	 *
599 	 * Like with the number of physical PHYS being a maximum of 16,
600 	 * there are a maximum number of PORTS also being 16. Some
601 	 * events apply to PORTS entirely, so we track PORTS as well.
602 	 */
603 	pmcs_phy_t		*root_phys;	/* HBA PHYs (level 0) */
604 	pmcs_phy_t		*ports[PMCS_MAX_PORTS];
605 	kmutex_t		dead_phylist_lock;	/* Protects dead_phys */
606 	pmcs_phy_t		*dead_phys;	/* PHYs waiting to be freed */
607 
608 	kmem_cache_t		*phy_cache;
609 
610 	/*
611 	 * Discovery-related items.
612 	 * config_lock: Protects config_changed and should never be held
613 	 * outside of getting or setting the value of config_changed or
614 	 * configuring.
615 	 * config_changed: Boolean indicating whether discovery needs to
616 	 * be restarted.
617 	 * configuring: 1 = discovery is running, 0 = discovery not running.
618 	 * NOTE: configuring is now in the bitfield above.
619 	 * config_restart_time is set by the tgtmap_[de]activate callbacks each
620 	 * time we decide we want SCSA to retry enumeration on some device.
621 	 * The watchdog timer will not fire discovery unless it has reached
622 	 * config_restart_time and config_restart is TRUE.  This ensures that
623 	 * we don't ask SCSA to retry enumerating devices while it is still
624 	 * running.
625 	 * config_cv can be used by any thread waiting on the configuring
626 	 * bit to clear.
627 	 */
628 	kmutex_t		config_lock;
629 	volatile boolean_t	config_changed;
630 	boolean_t		config_restart;
631 	clock_t			config_restart_time;
632 	kcondvar_t		config_cv;
633 
634 	/*
635 	 * Work Related Stuff
636 	 *
637 	 * Each command given to the PMC chip has an associated work structure.
638 	 * See the discussion in pmcs_def.h about work structures.
639 	 */
640 	pmcwork_t	*work;		/* pool of work structures */
641 	STAILQ_HEAD(wfh, pmcwork) wf;	/* current freelist */
642 	STAILQ_HEAD(pfh, pmcwork) pf;	/* current pending freelist */
643 	uint16_t	wserno;		/* rolling serial number */
644 	kmutex_t	wfree_lock;	/* freelist/actvlist/wserno lock */
645 	kmutex_t	pfree_lock;	/* freelist/actvlist/wserno lock */
646 
647 	/*
648 	 * Solaris/SCSA items.
649 	 */
650 	scsi_hba_tran_t		*tran;
651 	smp_hba_tran_t		*smp_tran;
652 	struct scsi_reset_notify_entry	*reset_notify_listf;
653 
654 	/*
655 	 * Thread Level stuff.
656 	 *
657 	 * A number of tasks are done off worker thread taskq.
658 	 */
659 	ddi_taskq_t 		*tq;		/* For the worker thread */
660 	volatile ulong_t	work_flags;
661 
662 	/*
663 	 * Solaris target representation.
664 	 * targets = array of pointers to xscsi structures
665 	 * allocated by ssoftstate.
666 	 */
667 	pmcs_xscsi_t			**targets;
668 
669 	STAILQ_HEAD(dqh, pmcs_cmd)	dq;	/* dead commands */
670 	STAILQ_HEAD(cqh, pmcs_cmd)	cq;	/* completed commands */
671 	kmutex_t			cq_lock;
672 	kmem_cache_t			*iocomp_cb_cache;
673 	pmcs_iocomp_cb_t		*iocomp_cb_head;
674 	pmcs_iocomp_cb_t		*iocomp_cb_tail;
675 
676 	uint16_t			debug_mask;
677 	uint16_t			phyid_block_mask;
678 	uint16_t			phys_started;
679 	uint16_t			open_retry_interval;
680 	uint32_t			hipri_queue;
681 	uint32_t			mpibar;
682 	uint32_t			intr_pri;
683 
684 	pmcs_io_intr_coal_t		io_intr_coal;
685 	pmcs_cq_info_t			cq_info;
686 	kmutex_t			ict_lock;
687 	kcondvar_t			ict_cv;
688 	kthread_t			*ict_thread;
689 
690 	/*
691 	 * Receptacle information - FMA
692 	 */
693 	char				*recept_labels[PMCS_NUM_RECEPTACLES];
694 	char				*recept_pm[PMCS_NUM_RECEPTACLES];
695 
696 	/*
697 	 * fw_timestamp: Firmware timestamp taken after PHYs are started
698 	 * sys_timestamp: System timestamp taken at roughly the same time
699 	 * hrtimestamp is the hrtime at roughly the same time
700 	 * All of these are protected by the global pmcs_trace_lock.
701 	 */
702 	uint64_t	fw_timestamp;
703 	timespec_t	sys_timestamp;
704 	hrtime_t	hrtimestamp;
705 
706 #ifdef	DEBUG
707 	kmutex_t	dbglock;
708 	uint32_t	ltags[256];
709 	uint32_t	ftags[256];
710 	hrtime_t	ltime[256];
711 	hrtime_t	ftime[256];
712 	uint16_t	ftag_lines[256];
713 	uint8_t		lti;			/* last tag index */
714 	uint8_t		fti;			/* first tag index */
715 #endif
716 };
717 
718 extern void 		*pmcs_softc_state;
719 extern void 		*pmcs_iport_softstate;
720 
721 /*
722  * Some miscellaneous, oft used strings
723  */
724 extern const char pmcs_nowrk[];
725 extern const char pmcs_nomsg[];
726 extern const char pmcs_timeo[];
727 
728 /*
729  * Other externs
730  */
731 extern int modrootloaded;
732 
733 #ifdef	__cplusplus
734 }
735 #endif
736 #endif	/* _PMCS_H */
737