1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/drivers/clocksource/acpi_pm.c
4 *
5 * This file contains the ACPI PM based clocksource.
6 *
7 * This code was largely moved from the i386 timer_pm.c file
8 * which was (C) Dominik Brodowski <linux@brodo.de> 2003
9 * and contained the following comments:
10 *
11 * Driver to use the Power Management Timer (PMTMR) available in some
12 * southbridges as primary timing source for the Linux kernel.
13 *
14 * Based on parts of linux/drivers/acpi/hardware/hwtimer.c, timer_pit.c,
15 * timer_hpet.c, and on Arjan van de Ven's implementation for 2.4.
16 */
17
18 #include <linux/acpi_pmtmr.h>
19 #include <linux/clocksource.h>
20 #include <linux/timex.h>
21 #include <linux/errno.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <asm/io.h>
26 #include <asm/time.h>
27
28 static void *suspend_resume_cb_data;
29
30 static void (*suspend_resume_callback)(void *data, bool suspend);
31
32 /*
33 * The I/O port the PMTMR resides at.
34 * The location is detected during setup_arch(),
35 * in arch/i386/kernel/acpi/boot.c
36 */
37 u32 pmtmr_ioport __read_mostly;
38
read_pmtmr(void)39 static inline u32 read_pmtmr(void)
40 {
41 /* mask the output to 24 bits */
42 return inl(pmtmr_ioport) & ACPI_PM_MASK;
43 }
44
acpi_pm_read_verified(void)45 u32 acpi_pm_read_verified(void)
46 {
47 u32 v1 = 0, v2 = 0, v3 = 0;
48
49 /*
50 * It has been reported that because of various broken
51 * chipsets (ICH4, PIIX4 and PIIX4E) where the ACPI PM clock
52 * source is not latched, you must read it multiple
53 * times to ensure a safe value is read:
54 */
55 do {
56 v1 = read_pmtmr();
57 v2 = read_pmtmr();
58 v3 = read_pmtmr();
59 } while (unlikely((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1)
60 || (v3 > v1 && v3 < v2)));
61
62 return v2;
63 }
64
acpi_pmtmr_register_suspend_resume_callback(void (* cb)(void * data,bool suspend),void * data)65 void acpi_pmtmr_register_suspend_resume_callback(void (*cb)(void *data, bool suspend), void *data)
66 {
67 suspend_resume_callback = cb;
68 suspend_resume_cb_data = data;
69 }
70 EXPORT_SYMBOL_GPL(acpi_pmtmr_register_suspend_resume_callback);
71
acpi_pmtmr_unregister_suspend_resume_callback(void)72 void acpi_pmtmr_unregister_suspend_resume_callback(void)
73 {
74 suspend_resume_callback = NULL;
75 suspend_resume_cb_data = NULL;
76 }
77 EXPORT_SYMBOL_GPL(acpi_pmtmr_unregister_suspend_resume_callback);
78
acpi_pm_suspend(struct clocksource * cs)79 static void acpi_pm_suspend(struct clocksource *cs)
80 {
81 if (suspend_resume_callback)
82 suspend_resume_callback(suspend_resume_cb_data, true);
83 }
84
acpi_pm_resume(struct clocksource * cs)85 static void acpi_pm_resume(struct clocksource *cs)
86 {
87 if (suspend_resume_callback)
88 suspend_resume_callback(suspend_resume_cb_data, false);
89 }
90
acpi_pm_read(struct clocksource * cs)91 static u64 acpi_pm_read(struct clocksource *cs)
92 {
93 return (u64)read_pmtmr();
94 }
95
96 static struct clocksource clocksource_acpi_pm = {
97 .name = "acpi_pm",
98 .rating = 200,
99 .read = acpi_pm_read,
100 .mask = (u64)ACPI_PM_MASK,
101 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
102 .suspend = acpi_pm_suspend,
103 .resume = acpi_pm_resume,
104 };
105
106
107 #ifdef CONFIG_PCI
108 static int acpi_pm_good;
acpi_pm_good_setup(char * __str)109 static int __init acpi_pm_good_setup(char *__str)
110 {
111 acpi_pm_good = 1;
112 return 1;
113 }
114 __setup("acpi_pm_good", acpi_pm_good_setup);
115
acpi_pm_read_slow(struct clocksource * cs)116 static u64 acpi_pm_read_slow(struct clocksource *cs)
117 {
118 return (u64)acpi_pm_read_verified();
119 }
120
acpi_pm_need_workaround(void)121 static inline void acpi_pm_need_workaround(void)
122 {
123 clocksource_acpi_pm.read = acpi_pm_read_slow;
124 clocksource_acpi_pm.rating = 120;
125 }
126
127 /*
128 * PIIX4 Errata:
129 *
130 * The power management timer may return improper results when read.
131 * Although the timer value settles properly after incrementing,
132 * while incrementing there is a 3 ns window every 69.8 ns where the
133 * timer value is indeterminate (a 4.2% chance that the data will be
134 * incorrect when read). As a result, the ACPI free running count up
135 * timer specification is violated due to erroneous reads.
136 */
acpi_pm_check_blacklist(struct pci_dev * dev)137 static void acpi_pm_check_blacklist(struct pci_dev *dev)
138 {
139 if (acpi_pm_good)
140 return;
141
142 /* the bug has been fixed in PIIX4M */
143 if (dev->revision < 3) {
144 pr_warn("* Found PM-Timer Bug on the chipset. Due to workarounds for a bug,\n"
145 "* this clock source is slow. Consider trying other clock sources\n");
146
147 acpi_pm_need_workaround();
148 }
149 }
150 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
151 acpi_pm_check_blacklist);
152
acpi_pm_check_graylist(struct pci_dev * dev)153 static void acpi_pm_check_graylist(struct pci_dev *dev)
154 {
155 if (acpi_pm_good)
156 return;
157
158 pr_warn("* The chipset may have PM-Timer Bug. Due to workarounds for a bug,\n"
159 "* this clock source is slow. If you are sure your timer does not have\n"
160 "* this bug, please use \"acpi_pm_good\" to disable the workaround\n");
161
162 acpi_pm_need_workaround();
163 }
164 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
165 acpi_pm_check_graylist);
166 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE,
167 acpi_pm_check_graylist);
168 #endif
169
170 #ifndef CONFIG_X86_64
171 #include <asm/mach_timer.h>
172 #define PMTMR_EXPECTED_RATE \
173 ((CALIBRATE_LATCH * (PMTMR_TICKS_PER_SEC >> 10)) / (PIT_TICK_RATE>>10))
174 /*
175 * Some boards have the PMTMR running way too fast. We check
176 * the PMTMR rate against PIT channel 2 to catch these cases.
177 */
verify_pmtmr_rate(void)178 static int verify_pmtmr_rate(void)
179 {
180 u64 value1, value2;
181 unsigned long count, delta;
182
183 mach_prepare_counter();
184 value1 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
185 mach_countup(&count);
186 value2 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
187 delta = (value2 - value1) & ACPI_PM_MASK;
188
189 /* Check that the PMTMR delta is within 5% of what we expect */
190 if (delta < (PMTMR_EXPECTED_RATE * 19) / 20 ||
191 delta > (PMTMR_EXPECTED_RATE * 21) / 20) {
192 pr_info("PM-Timer running at invalid rate: %lu%% of normal - aborting.\n",
193 100UL * delta / PMTMR_EXPECTED_RATE);
194 return -1;
195 }
196
197 return 0;
198 }
199 #else
200 #define verify_pmtmr_rate() (0)
201 #endif
202
203 /* Number of monotonicity checks to perform during initialization */
204 #define ACPI_PM_MONOTONICITY_CHECKS 10
205 /* Number of reads we try to get two different values */
206 #define ACPI_PM_READ_CHECKS 10000
207
init_acpi_pm_clocksource(void)208 static int __init init_acpi_pm_clocksource(void)
209 {
210 u64 value1, value2;
211 unsigned int i, j = 0;
212
213 if (!pmtmr_ioport)
214 return -ENODEV;
215
216 /* "verify" this timing source: */
217 for (j = 0; j < ACPI_PM_MONOTONICITY_CHECKS; j++) {
218 udelay(100 * j);
219 value1 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
220 for (i = 0; i < ACPI_PM_READ_CHECKS; i++) {
221 value2 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
222 if (value2 == value1)
223 continue;
224 if (value2 > value1)
225 break;
226 if ((value2 < value1) && ((value2) < 0xFFF))
227 break;
228 pr_info("PM-Timer had inconsistent results: %#llx, %#llx - aborting.\n",
229 value1, value2);
230 pmtmr_ioport = 0;
231 return -EINVAL;
232 }
233 if (i == ACPI_PM_READ_CHECKS) {
234 pr_info("PM-Timer failed consistency check (%#llx) - aborting.\n",
235 value1);
236 pmtmr_ioport = 0;
237 return -ENODEV;
238 }
239 }
240
241 if (verify_pmtmr_rate() != 0){
242 pmtmr_ioport = 0;
243 return -ENODEV;
244 }
245
246 if (tsc_clocksource_watchdog_disabled())
247 clocksource_acpi_pm.flags |= CLOCK_SOURCE_MUST_VERIFY;
248 return clocksource_register_hz(&clocksource_acpi_pm, PMTMR_TICKS_PER_SEC);
249 }
250
251 /* We use fs_initcall because we want the PCI fixups to have run
252 * but we still need to load before device_initcall
253 */
254 fs_initcall(init_acpi_pm_clocksource);
255
256 /*
257 * Allow an override of the IOPort. Stupid BIOSes do not tell us about
258 * the PMTimer, but we might know where it is.
259 */
parse_pmtmr(char * arg)260 static int __init parse_pmtmr(char *arg)
261 {
262 unsigned int base;
263 int ret;
264
265 ret = kstrtouint(arg, 16, &base);
266 if (ret) {
267 pr_warn("PMTMR: invalid 'pmtmr=' value: '%s'\n", arg);
268 return 1;
269 }
270
271 pr_info("PMTMR IOPort override: 0x%04x -> 0x%04x\n", pmtmr_ioport,
272 base);
273 pmtmr_ioport = base;
274
275 return 1;
276 }
277 __setup("pmtmr=", parse_pmtmr);
278