1 /*-
2 * Copyright (c) 2003-2005 Nate Lawson (SDG)
3 * Copyright (c) 2001 Michael Smith
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include "opt_acpi.h"
30 #include <sys/param.h>
31 #include <sys/bus.h>
32 #include <sys/cpu.h>
33 #include <sys/kernel.h>
34 #include <sys/malloc.h>
35 #include <sys/module.h>
36 #include <sys/pcpu.h>
37 #include <sys/power.h>
38 #include <sys/proc.h>
39 #include <sys/sched.h>
40 #include <sys/sbuf.h>
41 #include <sys/smp.h>
42
43 #include <dev/pci/pcivar.h>
44 #include <machine/atomic.h>
45 #include <machine/bus.h>
46 #if defined(__amd64__) || defined(__i386__)
47 #include <machine/clock.h>
48 #include <machine/specialreg.h>
49 #include <machine/md_var.h>
50 #endif
51 #include <sys/rman.h>
52
53 #include <contrib/dev/acpica/include/acpi.h>
54 #include <contrib/dev/acpica/include/accommon.h>
55
56 #include <dev/acpica/acpivar.h>
57
58 /*
59 * Support for ACPI Processor devices, including C[1-3] sleep states.
60 */
61
62 /* Hooks for the ACPI CA debugging infrastructure */
63 #define _COMPONENT ACPI_PROCESSOR
64 ACPI_MODULE_NAME("PROCESSOR")
65
66 struct acpi_cx {
67 struct resource *p_lvlx; /* Register to read to enter state. */
68 uint32_t type; /* C1-3 (C4 and up treated as C3). */
69 uint32_t trans_lat; /* Transition latency (usec). */
70 uint32_t power; /* Power consumed (mW). */
71 int res_type; /* Resource type for p_lvlx. */
72 int res_rid; /* Resource ID for p_lvlx. */
73 bool do_mwait;
74 uint32_t mwait_hint;
75 bool mwait_hw_coord;
76 bool mwait_bm_avoidance;
77 };
78 #define MAX_CX_STATES 8
79
80 struct acpi_cpu_softc {
81 device_t cpu_dev;
82 ACPI_HANDLE cpu_handle;
83 struct pcpu *cpu_pcpu;
84 uint32_t cpu_acpi_id; /* ACPI processor id */
85 uint32_t cpu_p_blk; /* ACPI P_BLK location */
86 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */
87 struct acpi_cx cpu_cx_states[MAX_CX_STATES];
88 int cpu_cx_count; /* Number of valid Cx states. */
89 int cpu_prev_sleep;/* Last idle sleep duration. */
90 int cpu_features; /* Child driver supported features. */
91 /* Runtime state. */
92 int cpu_non_c2; /* Index of lowest non-C2 state. */
93 int cpu_non_c3; /* Index of lowest non-C3 state. */
94 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */
95 /* Values for sysctl. */
96 struct sysctl_ctx_list cpu_sysctl_ctx;
97 struct sysctl_oid *cpu_sysctl_tree;
98 int cpu_cx_lowest;
99 int cpu_cx_lowest_lim;
100 int cpu_disable_idle; /* Disable entry to idle function */
101 char cpu_cx_supported[64];
102 };
103
104 struct acpi_cpu_device {
105 struct resource_list ad_rl;
106 };
107
108 #define CPU_GET_REG(reg, width) \
109 (bus_space_read_ ## width(rman_get_bustag((reg)), \
110 rman_get_bushandle((reg)), 0))
111 #define CPU_SET_REG(reg, width, val) \
112 (bus_space_write_ ## width(rman_get_bustag((reg)), \
113 rman_get_bushandle((reg)), 0, (val)))
114
115 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */
116
117 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */
118 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */
119
120 #define PCI_VENDOR_INTEL 0x8086
121 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */
122 #define PCI_REVISION_A_STEP 0
123 #define PCI_REVISION_B_STEP 1
124 #define PCI_REVISION_4E 2
125 #define PCI_REVISION_4M 3
126 #define PIIX4_DEVACTB_REG 0x58
127 #define PIIX4_BRLD_EN_IRQ0 (1<<0)
128 #define PIIX4_BRLD_EN_IRQ (1<<1)
129 #define PIIX4_BRLD_EN_IRQ8 (1<<5)
130 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8)
131 #define PIIX4_PCNTRL_BST_EN (1<<10)
132
133 #define CST_FFH_VENDOR_INTEL 1
134 #define CST_FFH_VENDOR_AMD 2
135 #define CST_FFH_INTEL_CL_C1IO 1
136 #define CST_FFH_INTEL_CL_MWAIT 2
137 #define CST_FFH_MWAIT_HW_COORD 0x0001
138 #define CST_FFH_MWAIT_BM_AVOID 0x0002
139
140 #define CPUDEV_DEVICE_ID "ACPI0007"
141
142 /* Knob to disable acpi_cpu devices */
143 bool acpi_cpu_disabled = false;
144
145 /* Platform hardware resource information. */
146 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */
147 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */
148 static int cpu_quirks; /* Indicate any hardware bugs. */
149
150 /* Values for sysctl. */
151 static struct sysctl_ctx_list cpu_sysctl_ctx;
152 static struct sysctl_oid *cpu_sysctl_tree;
153 static int cpu_cx_generic;
154 static int cpu_cx_lowest_lim;
155 #if defined(__i386__) || defined(__amd64__)
156 static bool cppc_notify;
157 #endif
158
159 static struct acpi_cpu_softc **cpu_softc;
160 ACPI_SERIAL_DECL(cpu, "ACPI CPU");
161
162 static int acpi_cpu_probe(device_t dev);
163 static int acpi_cpu_attach(device_t dev);
164 static int acpi_cpu_suspend(device_t dev);
165 static int acpi_cpu_resume(device_t dev);
166 static int acpi_pcpu_get_id(device_t dev, uint32_t acpi_id,
167 u_int *cpu_id);
168 static struct resource_list *acpi_cpu_get_rlist(device_t dev, device_t child);
169 static device_t acpi_cpu_add_child(device_t dev, u_int order, const char *name,
170 int unit);
171 static int acpi_cpu_read_ivar(device_t dev, device_t child, int index,
172 uintptr_t *result);
173 static int acpi_cpu_shutdown(device_t dev);
174 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc);
175 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc);
176 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc);
177 static void acpi_cpu_startup(void *arg);
178 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc);
179 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc);
180 #if defined(__i386__) || defined(__amd64__)
181 static void acpi_cpu_idle(sbintime_t sbt);
182 #endif
183 static void acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context);
184 static void acpi_cpu_quirks(void);
185 static void acpi_cpu_quirks_piix4(void);
186 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS);
187 static int acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS);
188 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc);
189 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS);
190 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS);
191 #if defined(__i386__) || defined(__amd64__)
192 static int acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS);
193 #endif
194
195 static device_method_t acpi_cpu_methods[] = {
196 /* Device interface */
197 DEVMETHOD(device_probe, acpi_cpu_probe),
198 DEVMETHOD(device_attach, acpi_cpu_attach),
199 DEVMETHOD(device_detach, bus_generic_detach),
200 DEVMETHOD(device_shutdown, acpi_cpu_shutdown),
201 DEVMETHOD(device_suspend, acpi_cpu_suspend),
202 DEVMETHOD(device_resume, acpi_cpu_resume),
203
204 /* Bus interface */
205 DEVMETHOD(bus_add_child, acpi_cpu_add_child),
206 DEVMETHOD(bus_read_ivar, acpi_cpu_read_ivar),
207 DEVMETHOD(bus_get_resource_list, acpi_cpu_get_rlist),
208 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
209 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
210 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource),
211 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
212 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
213 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
214 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
215 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
216
217 DEVMETHOD_END
218 };
219
220 static driver_t acpi_cpu_driver = {
221 "cpu",
222 acpi_cpu_methods,
223 sizeof(struct acpi_cpu_softc),
224 };
225
226 DRIVER_MODULE(cpu, acpi, acpi_cpu_driver, 0, 0);
227 MODULE_DEPEND(cpu, acpi, 1, 1, 1);
228
229 static int
acpi_cpu_probe(device_t dev)230 acpi_cpu_probe(device_t dev)
231 {
232 static char *cpudev_ids[] = { CPUDEV_DEVICE_ID, NULL };
233 int acpi_id, cpu_id;
234 ACPI_BUFFER buf;
235 ACPI_HANDLE handle;
236 ACPI_OBJECT *obj;
237 ACPI_STATUS status;
238 ACPI_OBJECT_TYPE type;
239
240 if (acpi_disabled("cpu") || acpi_cpu_disabled)
241 return (ENXIO);
242 type = acpi_get_type(dev);
243 if (type != ACPI_TYPE_PROCESSOR && type != ACPI_TYPE_DEVICE)
244 return (ENXIO);
245 if (type == ACPI_TYPE_DEVICE &&
246 ACPI_ID_PROBE(device_get_parent(dev), dev, cpudev_ids, NULL) >= 0)
247 return (ENXIO);
248
249 handle = acpi_get_handle(dev);
250 if (cpu_softc == NULL)
251 cpu_softc = malloc(sizeof(struct acpi_cpu_softc *) *
252 (mp_maxid + 1), M_TEMP /* XXX */, M_WAITOK | M_ZERO);
253
254 if (type == ACPI_TYPE_PROCESSOR) {
255 /* Get our Processor object. */
256 buf.Pointer = NULL;
257 buf.Length = ACPI_ALLOCATE_BUFFER;
258 status = AcpiEvaluateObject(handle, NULL, NULL, &buf);
259 if (ACPI_FAILURE(status)) {
260 device_printf(dev, "probe failed to get Processor obj - %s\n",
261 AcpiFormatException(status));
262 return (ENXIO);
263 }
264 obj = (ACPI_OBJECT *)buf.Pointer;
265 if (obj->Type != ACPI_TYPE_PROCESSOR) {
266 device_printf(dev, "Processor object has bad type %d\n",
267 obj->Type);
268 AcpiOsFree(obj);
269 return (ENXIO);
270 }
271
272 /*
273 * Find the processor associated with our unit. We could use the
274 * ProcId as a key, however, some boxes do not have the same values
275 * in their Processor object as the ProcId values in the MADT.
276 */
277 acpi_id = obj->Processor.ProcId;
278 AcpiOsFree(obj);
279 } else {
280 status = acpi_GetInteger(handle, "_UID", &acpi_id);
281 if (ACPI_FAILURE(status)) {
282 device_printf(dev, "Device object has bad value - %s\n",
283 AcpiFormatException(status));
284 return (ENXIO);
285 }
286 }
287 if (acpi_pcpu_get_id(dev, acpi_id, &cpu_id) != 0) {
288 if (bootverbose && (type != ACPI_TYPE_PROCESSOR || acpi_id != 255))
289 printf("ACPI: Processor %s (ACPI ID %u) ignored\n",
290 acpi_name(acpi_get_handle(dev)), acpi_id);
291 return (ENXIO);
292 }
293
294 if (device_set_unit(dev, cpu_id) != 0)
295 return (ENXIO);
296
297 device_set_desc(dev, "ACPI CPU");
298
299 if (!bootverbose && device_get_unit(dev) != 0) {
300 device_quiet(dev);
301 device_quiet_children(dev);
302 }
303
304 return (BUS_PROBE_DEFAULT);
305 }
306
307 static int
acpi_cpu_attach(device_t dev)308 acpi_cpu_attach(device_t dev)
309 {
310 ACPI_BUFFER buf;
311 ACPI_OBJECT arg, *obj;
312 ACPI_OBJECT_LIST arglist;
313 struct pcpu *pcpu_data;
314 struct acpi_cpu_softc *sc;
315 struct acpi_softc *acpi_sc;
316 ACPI_STATUS status;
317 u_int features;
318 int cpu_id, drv_count, i;
319 driver_t **drivers;
320 uint32_t cap_set[3];
321
322 /* UUID needed by _OSC evaluation */
323 static uint8_t cpu_oscuuid[16] = { 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29,
324 0xBE, 0x47, 0x9E, 0xBD, 0xD8, 0x70,
325 0x58, 0x71, 0x39, 0x53 };
326
327 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
328
329 sc = device_get_softc(dev);
330 sc->cpu_dev = dev;
331 sc->cpu_handle = acpi_get_handle(dev);
332 cpu_id = device_get_unit(dev);
333 cpu_softc[cpu_id] = sc;
334 pcpu_data = pcpu_find(cpu_id);
335 pcpu_data->pc_device = dev;
336 sc->cpu_pcpu = pcpu_data;
337 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand;
338 cpu_cst_cnt = AcpiGbl_FADT.CstControl;
339
340 if (acpi_get_type(dev) == ACPI_TYPE_PROCESSOR) {
341 buf.Pointer = NULL;
342 buf.Length = ACPI_ALLOCATE_BUFFER;
343 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf);
344 if (ACPI_FAILURE(status)) {
345 device_printf(dev, "attach failed to get Processor obj - %s\n",
346 AcpiFormatException(status));
347 return (ENXIO);
348 }
349 obj = (ACPI_OBJECT *)buf.Pointer;
350 sc->cpu_p_blk = obj->Processor.PblkAddress;
351 sc->cpu_p_blk_len = obj->Processor.PblkLength;
352 sc->cpu_acpi_id = obj->Processor.ProcId;
353 AcpiOsFree(obj);
354 } else {
355 KASSERT(acpi_get_type(dev) == ACPI_TYPE_DEVICE,
356 ("Unexpected ACPI object"));
357 status = acpi_GetInteger(sc->cpu_handle, "_UID", &sc->cpu_acpi_id);
358 if (ACPI_FAILURE(status)) {
359 device_printf(dev, "Device object has bad value - %s\n",
360 AcpiFormatException(status));
361 return (ENXIO);
362 }
363 sc->cpu_p_blk = 0;
364 sc->cpu_p_blk_len = 0;
365 }
366 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n",
367 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len));
368
369 /*
370 * If this is the first cpu we attach, create and initialize the generic
371 * resources that will be used by all acpi cpu devices.
372 */
373 if (device_get_unit(dev) == 0) {
374 /* Assume we won't be using generic Cx mode by default */
375 cpu_cx_generic = FALSE;
376
377 /* Install hw.acpi.cpu sysctl tree */
378 acpi_sc = acpi_device_get_parent_softc(dev);
379 sysctl_ctx_init(&cpu_sysctl_ctx);
380 cpu_sysctl_tree = SYSCTL_ADD_NODE(&cpu_sysctl_ctx,
381 SYSCTL_CHILDREN(acpi_sc->acpi_sysctl_tree), OID_AUTO, "cpu",
382 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "node for CPU children");
383
384 #if defined(__i386__) || defined(__amd64__)
385 /* Add sysctl handler to control registering for CPPC notifications */
386 cppc_notify = 1;
387 SYSCTL_ADD_BOOL(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree),
388 OID_AUTO, "cppc_notify", CTLFLAG_RDTUN | CTLFLAG_MPSAFE,
389 &cppc_notify, 0, "Register for CPPC Notifications");
390 #endif
391 }
392
393 /*
394 * Before calling any CPU methods, collect child driver feature hints
395 * and notify ACPI of them. We support unified SMP power control
396 * so advertise this ourselves. Note this is not the same as independent
397 * SMP control where each CPU can have different settings.
398 */
399 sc->cpu_features = ACPI_CAP_SMP_SAME | ACPI_CAP_SMP_SAME_C3 |
400 ACPI_CAP_C1_IO_HALT;
401
402 #if defined(__i386__) || defined(__amd64__)
403 /*
404 * Ask for MWAIT modes if not disabled and interrupts work
405 * reasonable with MWAIT.
406 */
407 if (!acpi_disabled("mwait") && cpu_mwait_usable())
408 sc->cpu_features |= ACPI_CAP_SMP_C1_NATIVE | ACPI_CAP_SMP_C3_NATIVE;
409
410 /*
411 * Work around a lingering SMM bug which leads to freezes when handling
412 * CPPC notifications. Tell the SMM we will handle any CPPC notifications.
413 */
414 if ((cpu_power_eax & CPUTPM1_HWP_NOTIFICATION) && cppc_notify)
415 sc->cpu_features |= ACPI_CAP_INTR_CPPC;
416 #endif
417
418 if (devclass_get_drivers(device_get_devclass(dev), &drivers,
419 &drv_count) == 0) {
420 for (i = 0; i < drv_count; i++) {
421 if (ACPI_GET_FEATURES(drivers[i], &features) == 0)
422 sc->cpu_features |= features;
423 }
424 free(drivers, M_TEMP);
425 }
426
427 /*
428 * CPU capabilities are specified in
429 * Intel Processor Vendor-Specific ACPI Interface Specification.
430 */
431 if (sc->cpu_features) {
432 cap_set[1] = sc->cpu_features;
433 status = acpi_EvaluateOSC(sc->cpu_handle, cpu_oscuuid, 1, 2, cap_set,
434 cap_set, false);
435 if (ACPI_SUCCESS(status)) {
436 if (cap_set[0] != 0)
437 device_printf(dev, "_OSC returned status %#x\n", cap_set[0]);
438 }
439 else {
440 arglist.Pointer = &arg;
441 arglist.Count = 1;
442 arg.Type = ACPI_TYPE_BUFFER;
443 arg.Buffer.Length = sizeof(cap_set);
444 arg.Buffer.Pointer = (uint8_t *)cap_set;
445 cap_set[0] = 1; /* revision */
446 cap_set[1] = 1; /* number of capabilities integers */
447 cap_set[2] = sc->cpu_features;
448 AcpiEvaluateObject(sc->cpu_handle, "_PDC", &arglist, NULL);
449 }
450 }
451
452 /* Probe for Cx state support. */
453 acpi_cpu_cx_probe(sc);
454
455 return (0);
456 }
457
458 static void
acpi_cpu_postattach(void * unused __unused)459 acpi_cpu_postattach(void *unused __unused)
460 {
461 struct acpi_cpu_softc *sc;
462 int attached = 0, i;
463
464 if (cpu_softc == NULL)
465 return;
466
467 bus_topo_lock();
468 CPU_FOREACH(i) {
469 if ((sc = cpu_softc[i]) != NULL)
470 bus_generic_probe(sc->cpu_dev);
471 }
472 CPU_FOREACH(i) {
473 if ((sc = cpu_softc[i]) != NULL) {
474 bus_generic_attach(sc->cpu_dev);
475 attached = 1;
476 }
477 }
478 bus_topo_unlock();
479
480 if (attached) {
481 #ifdef EARLY_AP_STARTUP
482 acpi_cpu_startup(NULL);
483 #else
484 /* Queue post cpu-probing task handler */
485 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL);
486 #endif
487 }
488 }
489
490 SYSINIT(acpi_cpu, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE,
491 acpi_cpu_postattach, NULL);
492
493 static void
disable_idle(struct acpi_cpu_softc * sc)494 disable_idle(struct acpi_cpu_softc *sc)
495 {
496 cpuset_t cpuset;
497
498 CPU_SETOF(sc->cpu_pcpu->pc_cpuid, &cpuset);
499 sc->cpu_disable_idle = TRUE;
500
501 /*
502 * Ensure that the CPU is not in idle state or in acpi_cpu_idle().
503 * Note that this code depends on the fact that the rendezvous IPI
504 * can not penetrate context where interrupts are disabled and acpi_cpu_idle
505 * is called and executed in such a context with interrupts being re-enabled
506 * right before return.
507 */
508 smp_rendezvous_cpus(cpuset, smp_no_rendezvous_barrier, NULL,
509 smp_no_rendezvous_barrier, NULL);
510 }
511
512 static void
enable_idle(struct acpi_cpu_softc * sc)513 enable_idle(struct acpi_cpu_softc *sc)
514 {
515
516 if (sc->cpu_cx_count > sc->cpu_non_c3 + 1 &&
517 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0)
518 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1);
519 sc->cpu_disable_idle = FALSE;
520 }
521
522 #if defined(__i386__) || defined(__amd64__)
523 static int
is_idle_disabled(struct acpi_cpu_softc * sc)524 is_idle_disabled(struct acpi_cpu_softc *sc)
525 {
526
527 return (sc->cpu_disable_idle);
528 }
529 #endif
530
531 /*
532 * Disable any entry to the idle function during suspend and re-enable it
533 * during resume.
534 */
535 static int
acpi_cpu_suspend(device_t dev)536 acpi_cpu_suspend(device_t dev)
537 {
538 int error;
539
540 error = bus_generic_suspend(dev);
541 if (error)
542 return (error);
543 disable_idle(device_get_softc(dev));
544 return (0);
545 }
546
547 static int
acpi_cpu_resume(device_t dev)548 acpi_cpu_resume(device_t dev)
549 {
550
551 enable_idle(device_get_softc(dev));
552 return (bus_generic_resume(dev));
553 }
554
555 /*
556 * Find the processor associated with a given ACPI ID.
557 */
558 static int
acpi_pcpu_get_id(device_t dev,uint32_t acpi_id,u_int * cpu_id)559 acpi_pcpu_get_id(device_t dev, uint32_t acpi_id, u_int *cpu_id)
560 {
561 struct pcpu *pc;
562 u_int i;
563
564 CPU_FOREACH(i) {
565 pc = pcpu_find(i);
566 if (pc->pc_acpi_id == acpi_id) {
567 *cpu_id = pc->pc_cpuid;
568 return (0);
569 }
570 }
571
572 /*
573 * If pc_acpi_id for CPU 0 is not initialized (e.g. a non-APIC
574 * UP box) use the ACPI ID from the first processor we find.
575 */
576 if (mp_ncpus == 1) {
577 pc = pcpu_find(0);
578 if (pc->pc_acpi_id == 0xffffffff)
579 pc->pc_acpi_id = acpi_id;
580 *cpu_id = 0;
581 return (0);
582 }
583
584 return (ESRCH);
585 }
586
587 static struct resource_list *
acpi_cpu_get_rlist(device_t dev,device_t child)588 acpi_cpu_get_rlist(device_t dev, device_t child)
589 {
590 struct acpi_cpu_device *ad;
591
592 ad = device_get_ivars(child);
593 if (ad == NULL)
594 return (NULL);
595 return (&ad->ad_rl);
596 }
597
598 static device_t
acpi_cpu_add_child(device_t dev,u_int order,const char * name,int unit)599 acpi_cpu_add_child(device_t dev, u_int order, const char *name, int unit)
600 {
601 struct acpi_cpu_device *ad;
602 device_t child;
603
604 if ((ad = malloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL)
605 return (NULL);
606
607 resource_list_init(&ad->ad_rl);
608
609 child = device_add_child_ordered(dev, order, name, unit);
610 if (child != NULL)
611 device_set_ivars(child, ad);
612 else
613 free(ad, M_TEMP);
614 return (child);
615 }
616
617 static int
acpi_cpu_read_ivar(device_t dev,device_t child,int index,uintptr_t * result)618 acpi_cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result)
619 {
620 struct acpi_cpu_softc *sc;
621
622 sc = device_get_softc(dev);
623 switch (index) {
624 case ACPI_IVAR_HANDLE:
625 *result = (uintptr_t)sc->cpu_handle;
626 break;
627 case CPU_IVAR_PCPU:
628 *result = (uintptr_t)sc->cpu_pcpu;
629 break;
630 #if defined(__amd64__) || defined(__i386__)
631 case CPU_IVAR_NOMINAL_MHZ:
632 if (tsc_is_invariant) {
633 *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) / 1000000);
634 break;
635 }
636 /* FALLTHROUGH */
637 #endif
638 default:
639 return (ENOENT);
640 }
641 return (0);
642 }
643
644 static int
acpi_cpu_shutdown(device_t dev)645 acpi_cpu_shutdown(device_t dev)
646 {
647 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
648
649 /* Allow children to shutdown first. */
650 bus_generic_shutdown(dev);
651
652 /*
653 * Disable any entry to the idle function.
654 */
655 disable_idle(device_get_softc(dev));
656
657 /*
658 * CPU devices are not truly detached and remain referenced,
659 * so their resources are not freed.
660 */
661
662 return_VALUE (0);
663 }
664
665 static void
acpi_cpu_cx_probe(struct acpi_cpu_softc * sc)666 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc)
667 {
668 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
669
670 /* Use initial sleep value of 1 sec. to start with lowest idle state. */
671 sc->cpu_prev_sleep = 1000000;
672 sc->cpu_cx_lowest = 0;
673 sc->cpu_cx_lowest_lim = 0;
674
675 /*
676 * Check for the ACPI 2.0 _CST sleep states object. If we can't find
677 * any, we'll revert to generic FADT/P_BLK Cx control method which will
678 * be handled by acpi_cpu_startup. We need to defer to after having
679 * probed all the cpus in the system before probing for generic Cx
680 * states as we may already have found cpus with valid _CST packages
681 */
682 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) {
683 /*
684 * We were unable to find a _CST package for this cpu or there
685 * was an error parsing it. Switch back to generic mode.
686 */
687 cpu_cx_generic = TRUE;
688 if (bootverbose)
689 device_printf(sc->cpu_dev, "switching to generic Cx mode\n");
690 }
691
692 /*
693 * TODO: _CSD Package should be checked here.
694 */
695 }
696
697 static void
acpi_cpu_generic_cx_probe(struct acpi_cpu_softc * sc)698 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc)
699 {
700 ACPI_GENERIC_ADDRESS gas;
701 struct acpi_cx *cx_ptr;
702
703 sc->cpu_cx_count = 0;
704 cx_ptr = sc->cpu_cx_states;
705
706 /* Use initial sleep value of 1 sec. to start with lowest idle state. */
707 sc->cpu_prev_sleep = 1000000;
708
709 /* C1 has been required since just after ACPI 1.0 */
710 cx_ptr->type = ACPI_STATE_C1;
711 cx_ptr->trans_lat = 0;
712 cx_ptr++;
713 sc->cpu_non_c2 = sc->cpu_cx_count;
714 sc->cpu_non_c3 = sc->cpu_cx_count;
715 sc->cpu_cx_count++;
716
717 /*
718 * The spec says P_BLK must be 6 bytes long. However, some systems
719 * use it to indicate a fractional set of features present so we
720 * take 5 as C2. Some may also have a value of 7 to indicate
721 * another C3 but most use _CST for this (as required) and having
722 * "only" C1-C3 is not a hardship.
723 */
724 if (sc->cpu_p_blk_len < 5)
725 return;
726
727 /* Validate and allocate resources for C2 (P_LVL2). */
728 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO;
729 gas.BitWidth = 8;
730 if (AcpiGbl_FADT.C2Latency <= 100) {
731 gas.Address = sc->cpu_p_blk + 4;
732 cx_ptr->res_rid = 0;
733 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid,
734 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE);
735 if (cx_ptr->p_lvlx != NULL) {
736 cx_ptr->type = ACPI_STATE_C2;
737 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency;
738 cx_ptr++;
739 sc->cpu_non_c3 = sc->cpu_cx_count;
740 sc->cpu_cx_count++;
741 }
742 }
743 if (sc->cpu_p_blk_len < 6)
744 return;
745
746 /* Validate and allocate resources for C3 (P_LVL3). */
747 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) {
748 gas.Address = sc->cpu_p_blk + 5;
749 cx_ptr->res_rid = 1;
750 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid,
751 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE);
752 if (cx_ptr->p_lvlx != NULL) {
753 cx_ptr->type = ACPI_STATE_C3;
754 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency;
755 cx_ptr++;
756 sc->cpu_cx_count++;
757 }
758 }
759 }
760
761 #if defined(__i386__) || defined(__amd64__)
762 static void
acpi_cpu_cx_cst_mwait(struct acpi_cx * cx_ptr,uint64_t address,int accsize)763 acpi_cpu_cx_cst_mwait(struct acpi_cx *cx_ptr, uint64_t address, int accsize)
764 {
765
766 cx_ptr->do_mwait = true;
767 cx_ptr->mwait_hint = address & 0xffffffff;
768 cx_ptr->mwait_hw_coord = (accsize & CST_FFH_MWAIT_HW_COORD) != 0;
769 cx_ptr->mwait_bm_avoidance = (accsize & CST_FFH_MWAIT_BM_AVOID) != 0;
770 }
771 #endif
772
773 static void
acpi_cpu_cx_cst_free_plvlx(device_t cpu_dev,struct acpi_cx * cx_ptr)774 acpi_cpu_cx_cst_free_plvlx(device_t cpu_dev, struct acpi_cx *cx_ptr)
775 {
776
777 if (cx_ptr->p_lvlx == NULL)
778 return;
779 bus_release_resource(cpu_dev, cx_ptr->res_type, cx_ptr->res_rid,
780 cx_ptr->p_lvlx);
781 cx_ptr->p_lvlx = NULL;
782 }
783
784 /*
785 * Parse a _CST package and set up its Cx states. Since the _CST object
786 * can change dynamically, our notify handler may call this function
787 * to clean up and probe the new _CST package.
788 */
789 static int
acpi_cpu_cx_cst(struct acpi_cpu_softc * sc)790 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc)
791 {
792 struct acpi_cx *cx_ptr;
793 ACPI_STATUS status;
794 ACPI_BUFFER buf;
795 ACPI_OBJECT *top;
796 ACPI_OBJECT *pkg;
797 uint32_t count;
798 int i;
799 #if defined(__i386__) || defined(__amd64__)
800 uint64_t address;
801 int vendor, class, accsize;
802 #endif
803
804 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
805
806 buf.Pointer = NULL;
807 buf.Length = ACPI_ALLOCATE_BUFFER;
808 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf);
809 if (ACPI_FAILURE(status))
810 return (ENXIO);
811
812 /* _CST is a package with a count and at least one Cx package. */
813 top = (ACPI_OBJECT *)buf.Pointer;
814 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) {
815 device_printf(sc->cpu_dev, "invalid _CST package\n");
816 AcpiOsFree(buf.Pointer);
817 return (ENXIO);
818 }
819 if (count != top->Package.Count - 1) {
820 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n",
821 count, top->Package.Count - 1);
822 count = top->Package.Count - 1;
823 }
824 if (count > MAX_CX_STATES) {
825 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count);
826 count = MAX_CX_STATES;
827 }
828
829 sc->cpu_non_c2 = 0;
830 sc->cpu_non_c3 = 0;
831 sc->cpu_cx_count = 0;
832 cx_ptr = sc->cpu_cx_states;
833
834 /*
835 * C1 has been required since just after ACPI 1.0.
836 * Reserve the first slot for it.
837 */
838 cx_ptr->type = ACPI_STATE_C0;
839 cx_ptr++;
840 sc->cpu_cx_count++;
841
842 /* Set up all valid states. */
843 for (i = 0; i < count; i++) {
844 pkg = &top->Package.Elements[i + 1];
845 if (!ACPI_PKG_VALID(pkg, 4) ||
846 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 ||
847 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 ||
848 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) {
849 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n");
850 continue;
851 }
852
853 /* Validate the state to see if we should use it. */
854 switch (cx_ptr->type) {
855 case ACPI_STATE_C1:
856 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr);
857 #if defined(__i386__) || defined(__amd64__)
858 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address,
859 &accsize) == 0 &&
860 (vendor == CST_FFH_VENDOR_INTEL || vendor == CST_FFH_VENDOR_AMD)) {
861 if (class == CST_FFH_INTEL_CL_C1IO) {
862 /* C1 I/O then Halt */
863 cx_ptr->res_rid = sc->cpu_cx_count;
864 bus_set_resource(sc->cpu_dev, SYS_RES_IOPORT,
865 cx_ptr->res_rid, address, 1);
866 cx_ptr->p_lvlx = bus_alloc_resource_any(sc->cpu_dev,
867 SYS_RES_IOPORT, &cx_ptr->res_rid, RF_ACTIVE |
868 RF_SHAREABLE);
869 if (cx_ptr->p_lvlx == NULL) {
870 bus_delete_resource(sc->cpu_dev, SYS_RES_IOPORT,
871 cx_ptr->res_rid);
872 device_printf(sc->cpu_dev,
873 "C1 I/O failed to allocate port %d, "
874 "degrading to C1 Halt", (int)address);
875 }
876 } else if (class == CST_FFH_INTEL_CL_MWAIT) {
877 if (vendor == CST_FFH_VENDOR_INTEL ||
878 (vendor == CST_FFH_VENDOR_AMD && cpu_mon_mwait_edx != 0))
879 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize);
880 }
881 }
882 #endif
883 if (sc->cpu_cx_states[0].type == ACPI_STATE_C0) {
884 /* This is the first C1 state. Use the reserved slot. */
885 sc->cpu_cx_states[0] = *cx_ptr;
886 } else {
887 sc->cpu_non_c2 = sc->cpu_cx_count;
888 sc->cpu_non_c3 = sc->cpu_cx_count;
889 cx_ptr++;
890 sc->cpu_cx_count++;
891 }
892 continue;
893 case ACPI_STATE_C2:
894 sc->cpu_non_c3 = sc->cpu_cx_count;
895 break;
896 case ACPI_STATE_C3:
897 default:
898 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) {
899 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
900 "acpi_cpu%d: C3[%d] not available.\n",
901 device_get_unit(sc->cpu_dev), i));
902 continue;
903 }
904 break;
905 }
906
907 /* Free up any previous register. */
908 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr);
909
910 /* Allocate the control register for C2 or C3. */
911 #if defined(__i386__) || defined(__amd64__)
912 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address,
913 &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL &&
914 class == CST_FFH_INTEL_CL_MWAIT) {
915 /* Native C State Instruction use (mwait) */
916 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize);
917 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
918 "acpi_cpu%d: Got C%d/mwait - %d latency\n",
919 device_get_unit(sc->cpu_dev), cx_ptr->type, cx_ptr->trans_lat));
920 cx_ptr++;
921 sc->cpu_cx_count++;
922 } else
923 #endif
924 {
925 cx_ptr->res_rid = sc->cpu_cx_count;
926 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type,
927 &cx_ptr->res_rid, &cx_ptr->p_lvlx, RF_SHAREABLE);
928 if (cx_ptr->p_lvlx) {
929 cx_ptr->do_mwait = false;
930 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
931 "acpi_cpu%d: Got C%d - %d latency\n",
932 device_get_unit(sc->cpu_dev), cx_ptr->type,
933 cx_ptr->trans_lat));
934 cx_ptr++;
935 sc->cpu_cx_count++;
936 }
937 }
938 }
939 AcpiOsFree(buf.Pointer);
940
941 /* If C1 state was not found, we need one now. */
942 cx_ptr = sc->cpu_cx_states;
943 if (cx_ptr->type == ACPI_STATE_C0) {
944 cx_ptr->type = ACPI_STATE_C1;
945 cx_ptr->trans_lat = 0;
946 }
947
948 return (0);
949 }
950
951 /*
952 * Call this *after* all CPUs have been attached.
953 */
954 static void
acpi_cpu_startup(void * arg)955 acpi_cpu_startup(void *arg)
956 {
957 struct acpi_cpu_softc *sc;
958 int i;
959
960 /*
961 * Setup any quirks that might necessary now that we have probed
962 * all the CPUs
963 */
964 acpi_cpu_quirks();
965
966 if (cpu_cx_generic) {
967 /*
968 * We are using generic Cx mode, probe for available Cx states
969 * for all processors.
970 */
971 CPU_FOREACH(i) {
972 if ((sc = cpu_softc[i]) != NULL)
973 acpi_cpu_generic_cx_probe(sc);
974 }
975 } else {
976 /*
977 * We are using _CST mode, remove C3 state if necessary.
978 * As we now know for sure that we will be using _CST mode
979 * install our notify handler.
980 */
981 CPU_FOREACH(i) {
982 if ((sc = cpu_softc[i]) == NULL)
983 continue;
984 if (cpu_quirks & CPU_QUIRK_NO_C3) {
985 sc->cpu_cx_count = min(sc->cpu_cx_count, sc->cpu_non_c3 + 1);
986 }
987 AcpiInstallNotifyHandler(sc->cpu_handle, ACPI_DEVICE_NOTIFY,
988 acpi_cpu_notify, sc);
989 }
990 }
991
992 /* Perform Cx final initialization. */
993 CPU_FOREACH(i) {
994 if ((sc = cpu_softc[i]) != NULL)
995 acpi_cpu_startup_cx(sc);
996 }
997
998 /* Add a sysctl handler to handle global Cx lowest setting */
999 SYSCTL_ADD_PROC(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree),
1000 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE,
1001 NULL, 0, acpi_cpu_global_cx_lowest_sysctl, "A",
1002 "Global lowest Cx sleep state to use");
1003
1004 /* Take over idling from cpu_idle_default(). */
1005 cpu_cx_lowest_lim = 0;
1006 CPU_FOREACH(i) {
1007 if ((sc = cpu_softc[i]) != NULL)
1008 enable_idle(sc);
1009 }
1010 #if defined(__i386__) || defined(__amd64__)
1011 cpu_idle_hook = acpi_cpu_idle;
1012 #endif
1013 }
1014
1015 static void
acpi_cpu_cx_list(struct acpi_cpu_softc * sc)1016 acpi_cpu_cx_list(struct acpi_cpu_softc *sc)
1017 {
1018 struct sbuf sb;
1019 int i;
1020
1021 /*
1022 * Set up the list of Cx states
1023 */
1024 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported),
1025 SBUF_FIXEDLEN);
1026 for (i = 0; i < sc->cpu_cx_count; i++)
1027 sbuf_printf(&sb, "C%d/%d/%d ", i + 1, sc->cpu_cx_states[i].type,
1028 sc->cpu_cx_states[i].trans_lat);
1029 sbuf_trim(&sb);
1030 sbuf_finish(&sb);
1031 }
1032
1033 static void
acpi_cpu_startup_cx(struct acpi_cpu_softc * sc)1034 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc)
1035 {
1036 acpi_cpu_cx_list(sc);
1037
1038 SYSCTL_ADD_STRING(&sc->cpu_sysctl_ctx,
1039 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)),
1040 OID_AUTO, "cx_supported", CTLFLAG_RD,
1041 sc->cpu_cx_supported, 0,
1042 "Cx/microsecond values for supported Cx states");
1043 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx,
1044 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO,
1045 "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE,
1046 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A",
1047 "lowest Cx sleep state to use");
1048 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx,
1049 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO,
1050 "cx_usage", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
1051 (void *)sc, 0, acpi_cpu_usage_sysctl, "A",
1052 "percent usage for each Cx state");
1053 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx,
1054 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO,
1055 "cx_usage_counters", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
1056 (void *)sc, 0, acpi_cpu_usage_counters_sysctl, "A",
1057 "Cx sleep state counters");
1058 #if defined(__i386__) || defined(__amd64__)
1059 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx,
1060 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO,
1061 "cx_method", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
1062 (void *)sc, 0, acpi_cpu_method_sysctl, "A", "Cx entrance methods");
1063 #endif
1064
1065 /* Signal platform that we can handle _CST notification. */
1066 if (!cpu_cx_generic && cpu_cst_cnt != 0) {
1067 ACPI_LOCK(acpi);
1068 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8);
1069 ACPI_UNLOCK(acpi);
1070 }
1071 }
1072
1073 #if defined(__i386__) || defined(__amd64__)
1074 /*
1075 * Idle the CPU in the lowest state possible. This function is called with
1076 * interrupts disabled. Note that once it re-enables interrupts, a task
1077 * switch can occur so do not access shared data (i.e. the softc) after
1078 * interrupts are re-enabled.
1079 */
1080 static void
acpi_cpu_idle(sbintime_t sbt)1081 acpi_cpu_idle(sbintime_t sbt)
1082 {
1083 struct acpi_cpu_softc *sc;
1084 struct acpi_cx *cx_next;
1085 uint64_t start_ticks, end_ticks;
1086 uint32_t start_time, end_time;
1087 ACPI_STATUS status;
1088 int bm_active, cx_next_idx, i, us;
1089
1090 /*
1091 * Look up our CPU id to get our softc. If it's NULL, we'll use C1
1092 * since there is no ACPI processor object for this CPU. This occurs
1093 * for logical CPUs in the HTT case.
1094 */
1095 sc = cpu_softc[PCPU_GET(cpuid)];
1096 if (sc == NULL) {
1097 acpi_cpu_c1();
1098 return;
1099 }
1100
1101 /* If disabled, take the safe path. */
1102 if (is_idle_disabled(sc)) {
1103 acpi_cpu_c1();
1104 return;
1105 }
1106
1107 /* Find the lowest state that has small enough latency. */
1108 us = sc->cpu_prev_sleep;
1109 if (sbt >= 0 && us > (sbt >> 12))
1110 us = (sbt >> 12);
1111 cx_next_idx = 0;
1112 if (cpu_disable_c2_sleep)
1113 i = min(sc->cpu_cx_lowest, sc->cpu_non_c2);
1114 else if (cpu_disable_c3_sleep)
1115 i = min(sc->cpu_cx_lowest, sc->cpu_non_c3);
1116 else
1117 i = sc->cpu_cx_lowest;
1118 for (; i >= 0; i--) {
1119 if (sc->cpu_cx_states[i].trans_lat * 3 <= us) {
1120 cx_next_idx = i;
1121 break;
1122 }
1123 }
1124
1125 /*
1126 * Check for bus master activity. If there was activity, clear
1127 * the bit and use the lowest non-C3 state. Note that the USB
1128 * driver polling for new devices keeps this bit set all the
1129 * time if USB is loaded.
1130 */
1131 cx_next = &sc->cpu_cx_states[cx_next_idx];
1132 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0 &&
1133 cx_next_idx > sc->cpu_non_c3 &&
1134 (!cx_next->do_mwait || cx_next->mwait_bm_avoidance)) {
1135 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active);
1136 if (ACPI_SUCCESS(status) && bm_active != 0) {
1137 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1);
1138 cx_next_idx = sc->cpu_non_c3;
1139 cx_next = &sc->cpu_cx_states[cx_next_idx];
1140 }
1141 }
1142
1143 /* Select the next state and update statistics. */
1144 sc->cpu_cx_stats[cx_next_idx]++;
1145 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep"));
1146
1147 /*
1148 * Execute HLT (or equivalent) and wait for an interrupt. We can't
1149 * precisely calculate the time spent in C1 since the place we wake up
1150 * is an ISR. Assume we slept no more then half of quantum, unless
1151 * we are called inside critical section, delaying context switch.
1152 */
1153 if (cx_next->type == ACPI_STATE_C1) {
1154 start_ticks = cpu_ticks();
1155 if (cx_next->p_lvlx != NULL) {
1156 /* C1 I/O then Halt */
1157 CPU_GET_REG(cx_next->p_lvlx, 1);
1158 }
1159 if (cx_next->do_mwait)
1160 acpi_cpu_idle_mwait(cx_next->mwait_hint);
1161 else
1162 acpi_cpu_c1();
1163 end_ticks = cpu_ticks();
1164 /* acpi_cpu_c1() returns with interrupts enabled. */
1165 if (cx_next->do_mwait)
1166 ACPI_ENABLE_IRQS();
1167 end_time = ((end_ticks - start_ticks) << 20) / cpu_tickrate();
1168 if (!cx_next->do_mwait && curthread->td_critnest == 0)
1169 end_time = min(end_time, 500000 / hz);
1170 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4;
1171 return;
1172 }
1173
1174 /*
1175 * For C3, disable bus master arbitration if BM control is available.
1176 * CPU may have to wake up to handle it. Otherwise flush the CPU cache.
1177 */
1178 if (cx_next->type == ACPI_STATE_C3) {
1179 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0)
1180 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1);
1181 else
1182 ACPI_FLUSH_CPU_CACHE();
1183 }
1184
1185 /*
1186 * Read from P_LVLx to enter C2(+), checking time spent asleep.
1187 * Use the ACPI timer for measuring sleep time. Since we need to
1188 * get the time very close to the CPU start/stop clock logic, this
1189 * is the only reliable time source.
1190 */
1191 if (cx_next->type == ACPI_STATE_C3) {
1192 AcpiGetTimer(&start_time);
1193 start_ticks = 0;
1194 } else {
1195 start_time = 0;
1196 start_ticks = cpu_ticks();
1197 }
1198 if (cx_next->do_mwait) {
1199 acpi_cpu_idle_mwait(cx_next->mwait_hint);
1200 } else {
1201 CPU_GET_REG(cx_next->p_lvlx, 1);
1202 /*
1203 * Read the end time twice. Since it may take an arbitrary time
1204 * to enter the idle state, the first read may be executed before
1205 * the processor has stopped. Doing it again provides enough
1206 * margin that we are certain to have a correct value.
1207 */
1208 AcpiGetTimer(&end_time);
1209 }
1210
1211 if (cx_next->type == ACPI_STATE_C3)
1212 AcpiGetTimer(&end_time);
1213 else
1214 end_ticks = cpu_ticks();
1215
1216 /* Enable bus master arbitration. */
1217 if (cx_next->type == ACPI_STATE_C3 &&
1218 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0)
1219 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0);
1220 ACPI_ENABLE_IRQS();
1221
1222 if (cx_next->type == ACPI_STATE_C3)
1223 AcpiGetTimerDuration(start_time, end_time, &end_time);
1224 else
1225 end_time = ((end_ticks - start_ticks) << 20) / cpu_tickrate();
1226 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4;
1227 }
1228 #endif
1229
1230 /*
1231 * Re-evaluate the _CST object when we are notified that it changed.
1232 */
1233 static void
acpi_cpu_notify(ACPI_HANDLE h,UINT32 notify,void * context)1234 acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context)
1235 {
1236 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)context;
1237
1238 if (notify != ACPI_NOTIFY_CX_STATES)
1239 return;
1240
1241 /*
1242 * C-state data for target CPU is going to be in flux while we execute
1243 * acpi_cpu_cx_cst, so disable entering acpi_cpu_idle.
1244 * Also, it may happen that multiple ACPI taskqueues may concurrently
1245 * execute notifications for the same CPU. ACPI_SERIAL is used to
1246 * protect against that.
1247 */
1248 ACPI_SERIAL_BEGIN(cpu);
1249 disable_idle(sc);
1250
1251 /* Update the list of Cx states. */
1252 acpi_cpu_cx_cst(sc);
1253 acpi_cpu_cx_list(sc);
1254 acpi_cpu_set_cx_lowest(sc);
1255
1256 enable_idle(sc);
1257 ACPI_SERIAL_END(cpu);
1258
1259 acpi_UserNotify("PROCESSOR", sc->cpu_handle, notify);
1260 }
1261
1262 static void
acpi_cpu_quirks(void)1263 acpi_cpu_quirks(void)
1264 {
1265 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
1266
1267 /*
1268 * Bus mastering arbitration control is needed to keep caches coherent
1269 * while sleeping in C3. If it's not present but a working flush cache
1270 * instruction is present, flush the caches before entering C3 instead.
1271 * Otherwise, just disable C3 completely.
1272 */
1273 if (AcpiGbl_FADT.Pm2ControlBlock == 0 ||
1274 AcpiGbl_FADT.Pm2ControlLength == 0) {
1275 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) &&
1276 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) {
1277 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
1278 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1279 "acpi_cpu: no BM control, using flush cache method\n"));
1280 } else {
1281 cpu_quirks |= CPU_QUIRK_NO_C3;
1282 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1283 "acpi_cpu: no BM control, C3 not available\n"));
1284 }
1285 }
1286
1287 /*
1288 * If we are using generic Cx mode, C3 on multiple CPUs requires using
1289 * the expensive flush cache instruction.
1290 */
1291 if (cpu_cx_generic && mp_ncpus > 1) {
1292 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
1293 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1294 "acpi_cpu: SMP, using flush cache mode for C3\n"));
1295 }
1296
1297 /* Look for various quirks of the PIIX4 part. */
1298 acpi_cpu_quirks_piix4();
1299 }
1300
1301 static void
acpi_cpu_quirks_piix4(void)1302 acpi_cpu_quirks_piix4(void)
1303 {
1304 #ifdef __i386__
1305 device_t acpi_dev;
1306 uint32_t val;
1307 ACPI_STATUS status;
1308
1309 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3);
1310 if (acpi_dev != NULL) {
1311 switch (pci_get_revid(acpi_dev)) {
1312 /*
1313 * Disable C3 support for all PIIX4 chipsets. Some of these parts
1314 * do not report the BMIDE status to the BM status register and
1315 * others have a livelock bug if Type-F DMA is enabled. Linux
1316 * works around the BMIDE bug by reading the BM status directly
1317 * but we take the simpler approach of disabling C3 for these
1318 * parts.
1319 *
1320 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA
1321 * Livelock") from the January 2002 PIIX4 specification update.
1322 * Applies to all PIIX4 models.
1323 *
1324 * Also, make sure that all interrupts cause a "Stop Break"
1325 * event to exit from C2 state.
1326 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak)
1327 * should be set to zero, otherwise it causes C2 to short-sleep.
1328 * PIIX4 doesn't properly support C3 and bus master activity
1329 * need not break out of C2.
1330 */
1331 case PCI_REVISION_A_STEP:
1332 case PCI_REVISION_B_STEP:
1333 case PCI_REVISION_4E:
1334 case PCI_REVISION_4M:
1335 cpu_quirks |= CPU_QUIRK_NO_C3;
1336 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1337 "acpi_cpu: working around PIIX4 bug, disabling C3\n"));
1338
1339 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4);
1340 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) {
1341 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1342 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n"));
1343 val |= PIIX4_STOP_BREAK_MASK;
1344 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4);
1345 }
1346 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val);
1347 if (ACPI_SUCCESS(status) && val != 0) {
1348 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1349 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n"));
1350 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
1351 }
1352 break;
1353 default:
1354 break;
1355 }
1356 }
1357 #endif
1358 }
1359
1360 static int
acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS)1361 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS)
1362 {
1363 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)arg1;
1364 struct sbuf sb;
1365 char buf[128];
1366 int error, i;
1367 uintmax_t fract, sum, whole;
1368
1369 sbuf_new_for_sysctl(&sb, buf, sizeof(buf), req);
1370 sum = 0;
1371 for (i = 0; i < sc->cpu_cx_count; i++)
1372 sum += sc->cpu_cx_stats[i];
1373 for (i = 0; i < sc->cpu_cx_count; i++) {
1374 if (sum > 0) {
1375 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100;
1376 fract = (whole % sum) * 100;
1377 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum),
1378 (u_int)(fract / sum));
1379 } else
1380 sbuf_printf(&sb, "0.00%% ");
1381 }
1382 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep);
1383 error = sbuf_finish(&sb);
1384 sbuf_delete(&sb);
1385 return (error);
1386 }
1387
1388 /*
1389 * XXX TODO: actually add support to count each entry/exit
1390 * from the Cx states.
1391 */
1392 static int
acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS)1393 acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS)
1394 {
1395 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)arg1;
1396 struct sbuf sb;
1397 char buf[128];
1398 int error, i;
1399
1400 sbuf_new_for_sysctl(&sb, buf, sizeof(buf), req);
1401 for (i = 0; i < sc->cpu_cx_count; i++) {
1402 if (i > 0)
1403 sbuf_putc(&sb, ' ');
1404 sbuf_printf(&sb, "%u", sc->cpu_cx_stats[i]);
1405 }
1406 error = sbuf_finish(&sb);
1407 sbuf_delete(&sb);
1408 return (error);
1409 }
1410
1411 #if defined(__i386__) || defined(__amd64__)
1412 static int
acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS)1413 acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS)
1414 {
1415 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)arg1;
1416 struct acpi_cx *cx;
1417 struct sbuf sb;
1418 char buf[128];
1419 int error, i;
1420
1421 sbuf_new_for_sysctl(&sb, buf, sizeof(buf), req);
1422 for (i = 0; i < sc->cpu_cx_count; i++) {
1423 cx = &sc->cpu_cx_states[i];
1424 if (i > 0)
1425 sbuf_putc(&sb, ' ');
1426 sbuf_printf(&sb, "C%d/", i + 1);
1427 if (cx->do_mwait) {
1428 sbuf_cat(&sb, "mwait");
1429 if (cx->mwait_hw_coord)
1430 sbuf_cat(&sb, "/hwc");
1431 if (cx->mwait_bm_avoidance)
1432 sbuf_cat(&sb, "/bma");
1433 } else if (cx->type == ACPI_STATE_C1) {
1434 sbuf_cat(&sb, "hlt");
1435 } else {
1436 sbuf_cat(&sb, "io");
1437 }
1438 if (cx->type == ACPI_STATE_C1 && cx->p_lvlx != NULL)
1439 sbuf_cat(&sb, "/iohlt");
1440 }
1441 error = sbuf_finish(&sb);
1442 sbuf_delete(&sb);
1443 return (error);
1444 }
1445 #endif
1446
1447 static int
acpi_cpu_set_cx_lowest(struct acpi_cpu_softc * sc)1448 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc)
1449 {
1450 int i;
1451
1452 ACPI_SERIAL_ASSERT(cpu);
1453 sc->cpu_cx_lowest = min(sc->cpu_cx_lowest_lim, sc->cpu_cx_count - 1);
1454
1455 /* If not disabling, cache the new lowest non-C3 state. */
1456 sc->cpu_non_c3 = 0;
1457 for (i = sc->cpu_cx_lowest; i >= 0; i--) {
1458 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) {
1459 sc->cpu_non_c3 = i;
1460 break;
1461 }
1462 }
1463
1464 /* Reset the statistics counters. */
1465 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats));
1466 return (0);
1467 }
1468
1469 static int
acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS)1470 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS)
1471 {
1472 struct acpi_cpu_softc *sc;
1473 char state[8];
1474 int val, error;
1475
1476 sc = (struct acpi_cpu_softc *) arg1;
1477 snprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest_lim + 1);
1478 error = sysctl_handle_string(oidp, state, sizeof(state), req);
1479 if (error != 0 || req->newptr == NULL)
1480 return (error);
1481 if (strlen(state) < 2 || toupper(state[0]) != 'C')
1482 return (EINVAL);
1483 if (strcasecmp(state, "Cmax") == 0)
1484 val = MAX_CX_STATES;
1485 else {
1486 val = (int) strtol(state + 1, NULL, 10);
1487 if (val < 1 || val > MAX_CX_STATES)
1488 return (EINVAL);
1489 }
1490
1491 ACPI_SERIAL_BEGIN(cpu);
1492 sc->cpu_cx_lowest_lim = val - 1;
1493 acpi_cpu_set_cx_lowest(sc);
1494 ACPI_SERIAL_END(cpu);
1495
1496 return (0);
1497 }
1498
1499 static int
acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS)1500 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS)
1501 {
1502 struct acpi_cpu_softc *sc;
1503 char state[8];
1504 int val, error, i;
1505
1506 snprintf(state, sizeof(state), "C%d", cpu_cx_lowest_lim + 1);
1507 error = sysctl_handle_string(oidp, state, sizeof(state), req);
1508 if (error != 0 || req->newptr == NULL)
1509 return (error);
1510 if (strlen(state) < 2 || toupper(state[0]) != 'C')
1511 return (EINVAL);
1512 if (strcasecmp(state, "Cmax") == 0)
1513 val = MAX_CX_STATES;
1514 else {
1515 val = (int) strtol(state + 1, NULL, 10);
1516 if (val < 1 || val > MAX_CX_STATES)
1517 return (EINVAL);
1518 }
1519
1520 /* Update the new lowest useable Cx state for all CPUs. */
1521 ACPI_SERIAL_BEGIN(cpu);
1522 cpu_cx_lowest_lim = val - 1;
1523 CPU_FOREACH(i) {
1524 if ((sc = cpu_softc[i]) == NULL)
1525 continue;
1526 sc->cpu_cx_lowest_lim = cpu_cx_lowest_lim;
1527 acpi_cpu_set_cx_lowest(sc);
1528 }
1529 ACPI_SERIAL_END(cpu);
1530
1531 return (0);
1532 }
1533