1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2023, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-msm8939.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/interconnect/qcom,msm8939.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/reset/qcom,gcc-msm8939.h> 13#include <dt-bindings/soc/qcom,apr.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 /* 20 * Stock LK wants address-cells/size-cells = 2 21 * A number of our drivers want address/size cells = 1 22 * hence the disparity between top-level and /soc below. 23 */ 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <19200000>; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32768>; 38 }; 39 }; 40 41 cpus { 42 #address-cells = <1>; 43 #size-cells = <0>; 44 45 CPU0: cpu@100 { 46 compatible = "arm,cortex-a53"; 47 device_type = "cpu"; 48 enable-method = "spin-table"; 49 reg = <0x100>; 50 next-level-cache = <&L2_1>; 51 qcom,acc = <&acc0>; 52 qcom,saw = <&saw0>; 53 cpu-idle-states = <&CPU_SLEEP_0>; 54 clocks = <&apcs1_mbox>; 55 #cooling-cells = <2>; 56 L2_1: l2-cache { 57 compatible = "cache"; 58 cache-level = <2>; 59 cache-unified; 60 }; 61 }; 62 63 CPU1: cpu@101 { 64 compatible = "arm,cortex-a53"; 65 device_type = "cpu"; 66 enable-method = "spin-table"; 67 reg = <0x101>; 68 next-level-cache = <&L2_1>; 69 qcom,acc = <&acc1>; 70 qcom,saw = <&saw1>; 71 cpu-idle-states = <&CPU_SLEEP_0>; 72 clocks = <&apcs1_mbox>; 73 #cooling-cells = <2>; 74 }; 75 76 CPU2: cpu@102 { 77 compatible = "arm,cortex-a53"; 78 device_type = "cpu"; 79 enable-method = "spin-table"; 80 reg = <0x102>; 81 next-level-cache = <&L2_1>; 82 qcom,acc = <&acc2>; 83 qcom,saw = <&saw2>; 84 cpu-idle-states = <&CPU_SLEEP_0>; 85 clocks = <&apcs1_mbox>; 86 #cooling-cells = <2>; 87 }; 88 89 CPU3: cpu@103 { 90 compatible = "arm,cortex-a53"; 91 device_type = "cpu"; 92 enable-method = "spin-table"; 93 reg = <0x103>; 94 next-level-cache = <&L2_1>; 95 qcom,acc = <&acc3>; 96 qcom,saw = <&saw3>; 97 cpu-idle-states = <&CPU_SLEEP_0>; 98 clocks = <&apcs1_mbox>; 99 #cooling-cells = <2>; 100 }; 101 102 CPU4: cpu@0 { 103 compatible = "arm,cortex-a53"; 104 device_type = "cpu"; 105 enable-method = "spin-table"; 106 reg = <0x0>; 107 qcom,acc = <&acc4>; 108 qcom,saw = <&saw4>; 109 cpu-idle-states = <&CPU_SLEEP_0>; 110 clocks = <&apcs0_mbox>; 111 #cooling-cells = <2>; 112 next-level-cache = <&L2_0>; 113 L2_0: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-unified; 117 }; 118 }; 119 120 CPU5: cpu@1 { 121 compatible = "arm,cortex-a53"; 122 device_type = "cpu"; 123 enable-method = "spin-table"; 124 reg = <0x1>; 125 next-level-cache = <&L2_0>; 126 qcom,acc = <&acc5>; 127 qcom,saw = <&saw5>; 128 cpu-idle-states = <&CPU_SLEEP_0>; 129 clocks = <&apcs0_mbox>; 130 #cooling-cells = <2>; 131 }; 132 133 CPU6: cpu@2 { 134 compatible = "arm,cortex-a53"; 135 device_type = "cpu"; 136 enable-method = "spin-table"; 137 reg = <0x2>; 138 next-level-cache = <&L2_0>; 139 qcom,acc = <&acc6>; 140 qcom,saw = <&saw6>; 141 cpu-idle-states = <&CPU_SLEEP_0>; 142 clocks = <&apcs0_mbox>; 143 #cooling-cells = <2>; 144 }; 145 146 CPU7: cpu@3 { 147 compatible = "arm,cortex-a53"; 148 device_type = "cpu"; 149 enable-method = "spin-table"; 150 reg = <0x3>; 151 next-level-cache = <&L2_0>; 152 qcom,acc = <&acc7>; 153 qcom,saw = <&saw7>; 154 cpu-idle-states = <&CPU_SLEEP_0>; 155 clocks = <&apcs0_mbox>; 156 #cooling-cells = <2>; 157 }; 158 159 idle-states { 160 CPU_SLEEP_0: cpu-sleep-0 { 161 compatible = "arm,idle-state"; 162 entry-latency-us = <130>; 163 exit-latency-us = <150>; 164 min-residency-us = <2000>; 165 local-timer-stop; 166 }; 167 }; 168 }; 169 170 /* 171 * MSM8939 has a big.LITTLE heterogeneous computing architecture, 172 * consisting of two clusters of four ARM Cortex-A53s each. The 173 * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs 174 * at 1.5-1.7GHz. 175 * 176 * The enable method used here is spin-table which presupposes use 177 * of a 2nd stage boot shim such as lk2nd to have installed a 178 * spin-table, the downstream non-psci/non-spin-table method that 179 * default msm8916/msm8936/msm8939 will not be supported upstream. 180 */ 181 cpu-map { 182 /* LITTLE (efficiency) cluster */ 183 cluster0 { 184 core0 { 185 cpu = <&CPU4>; 186 }; 187 188 core1 { 189 cpu = <&CPU5>; 190 }; 191 192 core2 { 193 cpu = <&CPU6>; 194 }; 195 196 core3 { 197 cpu = <&CPU7>; 198 }; 199 }; 200 201 /* big (performance) cluster */ 202 /* Boot CPU is cluster 1 core 0 */ 203 cluster1 { 204 core0 { 205 cpu = <&CPU0>; 206 }; 207 208 core1 { 209 cpu = <&CPU1>; 210 }; 211 212 core2 { 213 cpu = <&CPU2>; 214 }; 215 216 core3 { 217 cpu = <&CPU3>; 218 }; 219 }; 220 }; 221 222 firmware { 223 scm: scm { 224 compatible = "qcom,scm-msm8916", "qcom,scm"; 225 clocks = <&gcc GCC_CRYPTO_CLK>, 226 <&gcc GCC_CRYPTO_AXI_CLK>, 227 <&gcc GCC_CRYPTO_AHB_CLK>; 228 clock-names = "core", "bus", "iface"; 229 #reset-cells = <1>; 230 231 qcom,dload-mode = <&tcsr 0x6100>; 232 }; 233 }; 234 235 memory@80000000 { 236 device_type = "memory"; 237 /* We expect the bootloader to fill in the reg */ 238 reg = <0x0 0x80000000 0x0 0x0>; 239 }; 240 241 pmu { 242 compatible = "arm,cortex-a53-pmu"; 243 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 244 }; 245 246 rpm: remoteproc { 247 compatible = "qcom,msm8936-rpm-proc", "qcom,rpm-proc"; 248 249 smd-edge { 250 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 251 qcom,ipc = <&apcs1_mbox 8 0>; 252 qcom,smd-edge = <15>; 253 254 rpm_requests: rpm-requests { 255 compatible = "qcom,rpm-msm8936"; 256 qcom,smd-channels = "rpm_requests"; 257 258 rpmcc: clock-controller { 259 compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc"; 260 #clock-cells = <1>; 261 clock-names = "xo"; 262 clocks = <&xo_board>; 263 }; 264 265 rpmpd: power-controller { 266 compatible = "qcom,msm8939-rpmpd"; 267 #power-domain-cells = <1>; 268 operating-points-v2 = <&rpmpd_opp_table>; 269 270 rpmpd_opp_table: opp-table { 271 compatible = "operating-points-v2"; 272 273 rpmpd_opp_ret: opp1 { 274 opp-level = <1>; 275 }; 276 277 rpmpd_opp_svs_krait: opp2 { 278 opp-level = <2>; 279 }; 280 281 rpmpd_opp_svs_soc: opp3 { 282 opp-level = <3>; 283 }; 284 285 rpmpd_opp_nom: opp4 { 286 opp-level = <4>; 287 }; 288 289 rpmpd_opp_turbo: opp5 { 290 opp-level = <5>; 291 }; 292 293 rpmpd_opp_super_turbo: opp6 { 294 opp-level = <6>; 295 }; 296 }; 297 }; 298 }; 299 }; 300 }; 301 302 reserved-memory { 303 #address-cells = <2>; 304 #size-cells = <2>; 305 ranges; 306 307 tz-apps@86000000 { 308 reg = <0x0 0x86000000 0x0 0x300000>; 309 no-map; 310 }; 311 312 smem@86300000 { 313 compatible = "qcom,smem"; 314 reg = <0x0 0x86300000 0x0 0x100000>; 315 no-map; 316 317 hwlocks = <&tcsr_mutex 3>; 318 qcom,rpm-msg-ram = <&rpm_msg_ram>; 319 }; 320 321 hypervisor@86400000 { 322 reg = <0x0 0x86400000 0x0 0x100000>; 323 no-map; 324 }; 325 326 tz@86500000 { 327 reg = <0x0 0x86500000 0x0 0x180000>; 328 no-map; 329 }; 330 331 reserved@86680000 { 332 reg = <0x0 0x86680000 0x0 0x80000>; 333 no-map; 334 }; 335 336 rmtfs@86700000 { 337 compatible = "qcom,rmtfs-mem"; 338 reg = <0x0 0x86700000 0x0 0xe0000>; 339 no-map; 340 341 qcom,client-id = <1>; 342 }; 343 344 rfsa@867e0000 { 345 reg = <0x0 0x867e0000 0x0 0x20000>; 346 no-map; 347 }; 348 349 mpss_mem: mpss@86800000 { 350 /* 351 * The memory region for the mpss firmware is generally 352 * relocatable and could be allocated dynamically. 353 * However, many firmware versions tend to fail when 354 * loaded to some special addresses, so it is hard to 355 * define reliable alloc-ranges. 356 * 357 * alignment = <0x0 0x400000>; 358 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 359 */ 360 reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */ 361 no-map; 362 status = "disabled"; 363 }; 364 365 wcnss_mem: wcnss { 366 size = <0x0 0x600000>; 367 alignment = <0x0 0x100000>; 368 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 369 no-map; 370 status = "disabled"; 371 }; 372 373 venus_mem: venus { 374 size = <0x0 0x500000>; 375 alignment = <0x0 0x100000>; 376 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 377 no-map; 378 status = "disabled"; 379 }; 380 381 mba_mem: mba { 382 size = <0x0 0x100000>; 383 alignment = <0x0 0x100000>; 384 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 385 no-map; 386 status = "disabled"; 387 }; 388 }; 389 390 smp2p-hexagon { 391 compatible = "qcom,smp2p"; 392 qcom,smem = <435>, <428>; 393 394 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 395 396 mboxes = <&apcs1_mbox 14>; 397 398 qcom,local-pid = <0>; 399 qcom,remote-pid = <1>; 400 401 hexagon_smp2p_out: master-kernel { 402 qcom,entry-name = "master-kernel"; 403 404 #qcom,smem-state-cells = <1>; 405 }; 406 407 hexagon_smp2p_in: slave-kernel { 408 qcom,entry-name = "slave-kernel"; 409 410 interrupt-controller; 411 #interrupt-cells = <2>; 412 }; 413 }; 414 415 smp2p-wcnss { 416 compatible = "qcom,smp2p"; 417 qcom,smem = <451>, <431>; 418 419 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 420 421 mboxes = <&apcs1_mbox 18>; 422 423 qcom,local-pid = <0>; 424 qcom,remote-pid = <4>; 425 426 wcnss_smp2p_in: slave-kernel { 427 qcom,entry-name = "slave-kernel"; 428 429 interrupt-controller; 430 #interrupt-cells = <2>; 431 }; 432 433 wcnss_smp2p_out: master-kernel { 434 qcom,entry-name = "master-kernel"; 435 436 #qcom,smem-state-cells = <1>; 437 }; 438 }; 439 440 smsm { 441 compatible = "qcom,smsm"; 442 443 #address-cells = <1>; 444 #size-cells = <0>; 445 446 qcom,ipc-1 = <&apcs1_mbox 8 13>; 447 qcom,ipc-3 = <&apcs1_mbox 8 19>; 448 449 apps_smsm: apps@0 { 450 reg = <0>; 451 452 #qcom,smem-state-cells = <1>; 453 }; 454 455 hexagon_smsm: hexagon@1 { 456 reg = <1>; 457 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 458 459 interrupt-controller; 460 #interrupt-cells = <2>; 461 }; 462 463 wcnss_smsm: wcnss@6 { 464 reg = <6>; 465 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 466 467 interrupt-controller; 468 #interrupt-cells = <2>; 469 }; 470 }; 471 472 soc: soc@0 { 473 compatible = "simple-bus"; 474 #address-cells = <1>; 475 #size-cells = <1>; 476 ranges = <0 0 0 0xffffffff>; 477 478 rng@22000 { 479 compatible = "qcom,prng"; 480 reg = <0x00022000 0x200>; 481 clocks = <&gcc GCC_PRNG_AHB_CLK>; 482 clock-names = "core"; 483 }; 484 485 qfprom: qfprom@5c000 { 486 compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; 487 reg = <0x0005c000 0x1000>; 488 #address-cells = <1>; 489 #size-cells = <1>; 490 491 tsens_base1: base1@a0 { 492 reg = <0xa0 0x1>; 493 bits = <0 8>; 494 }; 495 496 tsens_s6_p1: s6-p1@a1 { 497 reg = <0xa1 0x1>; 498 bits = <0 6>; 499 }; 500 501 tsens_s6_p2: s6-p2@a1 { 502 reg = <0xa1 0x2>; 503 bits = <6 6>; 504 }; 505 506 tsens_s7_p1: s7-p1@a2 { 507 reg = <0xa2 0x2>; 508 bits = <4 6>; 509 }; 510 511 tsens_s7_p2: s7-p2@a3 { 512 reg = <0xa3 0x1>; 513 bits = <2 6>; 514 }; 515 516 tsens_s8_p1: s8-p1@a4 { 517 reg = <0xa4 0x1>; 518 bits = <0 6>; 519 }; 520 521 tsens_s8_p2: s8-p2@a4 { 522 reg = <0xa4 0x2>; 523 bits = <6 6>; 524 }; 525 526 tsens_s9_p1: s9-p1@a5 { 527 reg = <0xa5 0x2>; 528 bits = <4 6>; 529 }; 530 531 tsens_s9_p2: s9-p2@a6 { 532 reg = <0xa6 0x1>; 533 bits = <2 6>; 534 }; 535 536 tsens_base2: base2@a7 { 537 reg = <0xa7 0x1>; 538 bits = <0 8>; 539 }; 540 541 tsens_mode: mode@d0 { 542 reg = <0xd0 0x1>; 543 bits = <0 3>; 544 }; 545 546 tsens_s0_p1: s0-p1@d0 { 547 reg = <0xd0 0x2>; 548 bits = <3 6>; 549 }; 550 551 tsens_s0_p2: s0-p1@d1 { 552 reg = <0xd1 0x1>; 553 bits = <1 6>; 554 }; 555 556 tsens_s1_p1: s1-p1@d1 { 557 reg = <0xd1 0x2>; 558 bits = <7 6>; 559 }; 560 561 tsens_s1_p2: s1-p2@d2 { 562 reg = <0xd2 0x2>; 563 bits = <5 6>; 564 }; 565 566 tsens_s2_p1: s2-p1@d3 { 567 reg = <0xd3 0x2>; 568 bits = <3 6>; 569 }; 570 571 tsens_s2_p2: s2-p2@d4 { 572 reg = <0xd4 0x1>; 573 bits = <1 6>; 574 }; 575 576 tsens_s3_p1: s3-p1@d4 { 577 reg = <0xd4 0x2>; 578 bits = <7 6>; 579 }; 580 581 tsens_s3_p2: s3-p2@d5 { 582 reg = <0xd5 0x2>; 583 bits = <5 6>; 584 }; 585 586 tsens_s5_p1: s5-p1@d6 { 587 reg = <0xd6 0x2>; 588 bits = <3 6>; 589 }; 590 591 tsens_s5_p2: s5-p2@d7 { 592 reg = <0xd7 0x1>; 593 bits = <1 6>; 594 }; 595 }; 596 597 rpm_msg_ram: sram@60000 { 598 compatible = "qcom,rpm-msg-ram"; 599 reg = <0x00060000 0x8000>; 600 }; 601 602 bimc: interconnect@400000 { 603 compatible = "qcom,msm8939-bimc"; 604 reg = <0x00400000 0x62000>; 605 #interconnect-cells = <1>; 606 }; 607 608 tsens: thermal-sensor@4a9000 { 609 compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1"; 610 reg = <0x004a9000 0x1000>, /* TM */ 611 <0x004a8000 0x1000>; /* SROT */ 612 nvmem-cells = <&tsens_mode>, 613 <&tsens_base1>, <&tsens_base2>, 614 <&tsens_s0_p1>, <&tsens_s0_p2>, 615 <&tsens_s1_p1>, <&tsens_s1_p2>, 616 <&tsens_s2_p1>, <&tsens_s2_p2>, 617 <&tsens_s3_p1>, <&tsens_s3_p2>, 618 <&tsens_s5_p1>, <&tsens_s5_p2>, 619 <&tsens_s6_p1>, <&tsens_s6_p2>, 620 <&tsens_s7_p1>, <&tsens_s7_p2>, 621 <&tsens_s8_p1>, <&tsens_s8_p2>, 622 <&tsens_s9_p1>, <&tsens_s9_p2>; 623 nvmem-cell-names = "mode", 624 "base1", "base2", 625 "s0_p1", "s0_p2", 626 "s1_p1", "s1_p2", 627 "s2_p1", "s2_p2", 628 "s3_p1", "s3_p2", 629 "s5_p1", "s5_p2", 630 "s6_p1", "s6_p2", 631 "s7_p1", "s7_p2", 632 "s8_p1", "s8_p2", 633 "s9_p1", "s9_p2"; 634 #qcom,sensors = <9>; 635 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 636 interrupt-names = "uplow"; 637 #thermal-sensor-cells = <1>; 638 }; 639 640 restart@4ab000 { 641 compatible = "qcom,pshold"; 642 reg = <0x004ab000 0x4>; 643 }; 644 645 pcnoc: interconnect@500000 { 646 compatible = "qcom,msm8939-pcnoc"; 647 reg = <0x00500000 0x11000>; 648 #interconnect-cells = <1>; 649 }; 650 651 snoc: interconnect@580000 { 652 compatible = "qcom,msm8939-snoc"; 653 reg = <0x00580000 0x14080>; 654 #interconnect-cells = <1>; 655 656 snoc_mm: interconnect-snoc { 657 compatible = "qcom,msm8939-snoc-mm"; 658 #interconnect-cells = <1>; 659 }; 660 }; 661 662 tlmm: pinctrl@1000000 { 663 compatible = "qcom,msm8916-pinctrl"; 664 reg = <0x01000000 0x300000>; 665 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 666 gpio-controller; 667 gpio-ranges = <&tlmm 0 0 122>; 668 #gpio-cells = <2>; 669 interrupt-controller; 670 #interrupt-cells = <2>; 671 672 blsp_i2c1_default: blsp-i2c1-default-state { 673 pins = "gpio2", "gpio3"; 674 function = "blsp_i2c1"; 675 drive-strength = <2>; 676 bias-disable; 677 }; 678 679 blsp_i2c1_sleep: blsp-i2c1-sleep-state { 680 pins = "gpio2", "gpio3"; 681 function = "gpio"; 682 drive-strength = <2>; 683 bias-disable; 684 }; 685 686 blsp_i2c2_default: blsp-i2c2-default-state { 687 pins = "gpio6", "gpio7"; 688 function = "blsp_i2c2"; 689 drive-strength = <2>; 690 bias-disable; 691 }; 692 693 blsp_i2c2_sleep: blsp-i2c2-sleep-state { 694 pins = "gpio6", "gpio7"; 695 function = "gpio"; 696 drive-strength = <2>; 697 bias-disable; 698 }; 699 700 blsp_i2c3_default: blsp-i2c3-default-state { 701 pins = "gpio10", "gpio11"; 702 function = "blsp_i2c3"; 703 drive-strength = <2>; 704 bias-disable; 705 }; 706 707 blsp_i2c3_sleep: blsp-i2c3-sleep-state { 708 pins = "gpio10", "gpio11"; 709 function = "gpio"; 710 drive-strength = <2>; 711 bias-disable; 712 }; 713 714 blsp_i2c4_default: blsp-i2c4-default-state { 715 pins = "gpio14", "gpio15"; 716 function = "blsp_i2c4"; 717 drive-strength = <2>; 718 bias-disable; 719 }; 720 721 blsp_i2c4_sleep: blsp-i2c4-sleep-state { 722 pins = "gpio14", "gpio15"; 723 function = "gpio"; 724 drive-strength = <2>; 725 bias-disable; 726 }; 727 728 blsp_i2c5_default: blsp-i2c5-default-state { 729 pins = "gpio18", "gpio19"; 730 function = "blsp_i2c5"; 731 drive-strength = <2>; 732 bias-disable; 733 }; 734 735 blsp_i2c5_sleep: blsp-i2c5-sleep-state { 736 pins = "gpio18", "gpio19"; 737 function = "gpio"; 738 drive-strength = <2>; 739 bias-disable; 740 }; 741 742 blsp_i2c6_default: blsp-i2c6-default-state { 743 pins = "gpio22", "gpio23"; 744 function = "blsp_i2c6"; 745 drive-strength = <2>; 746 bias-disable; 747 }; 748 749 blsp_i2c6_sleep: blsp-i2c6-sleep-state { 750 pins = "gpio22", "gpio23"; 751 function = "gpio"; 752 drive-strength = <2>; 753 bias-disable; 754 }; 755 756 blsp_spi1_default: blsp-spi1-default-state { 757 spi-pins { 758 pins = "gpio0", "gpio1", "gpio3"; 759 function = "blsp_spi1"; 760 drive-strength = <12>; 761 bias-disable; 762 }; 763 764 cs-pins { 765 pins = "gpio2"; 766 function = "gpio"; 767 drive-strength = <16>; 768 bias-disable; 769 output-high; 770 }; 771 }; 772 773 blsp_spi1_sleep: blsp-spi1-sleep-state { 774 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 775 function = "gpio"; 776 drive-strength = <2>; 777 bias-pull-down; 778 }; 779 780 blsp_spi2_default: blsp-spi2-default-state { 781 spi-pins { 782 pins = "gpio4", "gpio5", "gpio7"; 783 function = "blsp_spi2"; 784 drive-strength = <12>; 785 bias-disable; 786 }; 787 788 cs-pins { 789 pins = "gpio6"; 790 function = "gpio"; 791 drive-strength = <16>; 792 bias-disable; 793 output-high; 794 }; 795 }; 796 797 blsp_spi2_sleep: blsp-spi2-sleep-state { 798 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 799 function = "gpio"; 800 drive-strength = <2>; 801 bias-pull-down; 802 }; 803 804 blsp_spi3_default: blsp-spi3-default-state { 805 spi-pins { 806 pins = "gpio8", "gpio9", "gpio11"; 807 function = "blsp_spi3"; 808 drive-strength = <12>; 809 bias-disable; 810 }; 811 812 cs-pins { 813 pins = "gpio10"; 814 function = "gpio"; 815 drive-strength = <16>; 816 bias-disable; 817 output-high; 818 }; 819 }; 820 821 blsp_spi3_sleep: blsp-spi3-sleep-state { 822 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 823 function = "gpio"; 824 drive-strength = <2>; 825 bias-pull-down; 826 }; 827 828 blsp_spi4_default: blsp-spi4-default-state { 829 spi-pins { 830 pins = "gpio12", "gpio13", "gpio15"; 831 function = "blsp_spi4"; 832 drive-strength = <12>; 833 bias-disable; 834 }; 835 836 cs-pins { 837 pins = "gpio14"; 838 function = "gpio"; 839 drive-strength = <16>; 840 bias-disable; 841 output-high; 842 }; 843 }; 844 845 blsp_spi4_sleep: blsp-spi4-sleep-state { 846 pins = "gpio12", "gpio13", "gpio14", "gpio15"; 847 function = "gpio"; 848 drive-strength = <2>; 849 bias-pull-down; 850 }; 851 852 blsp_spi5_default: blsp-spi5-default-state { 853 spi-pins { 854 pins = "gpio16", "gpio17", "gpio19"; 855 function = "blsp_spi5"; 856 drive-strength = <12>; 857 bias-disable; 858 }; 859 860 cs-pins { 861 pins = "gpio18"; 862 function = "gpio"; 863 drive-strength = <16>; 864 bias-disable; 865 output-high; 866 }; 867 }; 868 869 blsp_spi5_sleep: blsp-spi5-sleep-state { 870 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 871 function = "gpio"; 872 drive-strength = <2>; 873 bias-pull-down; 874 }; 875 876 blsp_spi6_default: blsp-spi6-default-state { 877 spi-pins { 878 pins = "gpio20", "gpio21", "gpio23"; 879 function = "blsp_spi6"; 880 drive-strength = <12>; 881 bias-disable; 882 }; 883 884 cs-pins { 885 pins = "gpio22"; 886 function = "gpio"; 887 drive-strength = <16>; 888 bias-disable; 889 output-high; 890 }; 891 }; 892 893 blsp_spi6_sleep: blsp-spi6-sleep-state { 894 pins = "gpio20", "gpio21", "gpio22", "gpio23"; 895 function = "gpio"; 896 drive-strength = <2>; 897 bias-pull-down; 898 }; 899 900 blsp_uart1_default: blsp-uart1-default-state { 901 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 902 function = "blsp_uart1"; 903 drive-strength = <16>; 904 bias-disable; 905 }; 906 907 blsp_uart1_sleep: blsp-uart1-sleep-state { 908 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 909 function = "gpio"; 910 drive-strength = <2>; 911 bias-pull-down; 912 }; 913 914 blsp_uart2_default: blsp-uart2-default-state { 915 pins = "gpio4", "gpio5"; 916 function = "blsp_uart2"; 917 drive-strength = <16>; 918 bias-disable; 919 }; 920 921 blsp_uart2_sleep: blsp-uart2-sleep-state { 922 pins = "gpio4", "gpio5"; 923 function = "gpio"; 924 drive-strength = <2>; 925 bias-pull-down; 926 }; 927 928 camera_front_default: camera-front-default-state { 929 pwdn-pins { 930 pins = "gpio33"; 931 function = "gpio"; 932 drive-strength = <16>; 933 bias-disable; 934 }; 935 936 rst-pins { 937 pins = "gpio28"; 938 function = "gpio"; 939 drive-strength = <16>; 940 bias-disable; 941 }; 942 943 mclk1-pins { 944 pins = "gpio27"; 945 function = "cam_mclk1"; 946 drive-strength = <16>; 947 bias-disable; 948 }; 949 }; 950 951 camera_rear_default: camera-rear-default-state { 952 pwdn-pins { 953 pins = "gpio34"; 954 function = "gpio"; 955 drive-strength = <16>; 956 bias-disable; 957 }; 958 959 rst-pins { 960 pins = "gpio35"; 961 function = "gpio"; 962 drive-strength = <16>; 963 bias-disable; 964 }; 965 966 mclk0-pins { 967 pins = "gpio26"; 968 function = "cam_mclk0"; 969 drive-strength = <16>; 970 bias-disable; 971 }; 972 }; 973 974 cci0_default: cci0-default-state { 975 pins = "gpio29", "gpio30"; 976 function = "cci_i2c"; 977 drive-strength = <16>; 978 bias-disable; 979 }; 980 981 cdc_dmic_default: cdc-dmic-default-state { 982 clk-pins { 983 pins = "gpio0"; 984 function = "dmic0_clk"; 985 drive-strength = <8>; 986 }; 987 988 data-pins { 989 pins = "gpio1"; 990 function = "dmic0_data"; 991 drive-strength = <8>; 992 }; 993 }; 994 995 cdc_dmic_sleep: cdc-dmic-sleep-state { 996 clk-pins { 997 pins = "gpio0"; 998 function = "dmic0_clk"; 999 drive-strength = <2>; 1000 bias-disable; 1001 }; 1002 1003 data-pins { 1004 pins = "gpio1"; 1005 function = "dmic0_data"; 1006 drive-strength = <2>; 1007 bias-disable; 1008 }; 1009 }; 1010 1011 cdc_pdm_default: cdc-pdm-default-state { 1012 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1013 "gpio67", "gpio68"; 1014 function = "cdc_pdm0"; 1015 drive-strength = <8>; 1016 bias-disable; 1017 }; 1018 1019 cdc_pdm_sleep: cdc-pdm-sleep-state { 1020 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1021 "gpio67", "gpio68"; 1022 function = "cdc_pdm0"; 1023 drive-strength = <2>; 1024 bias-pull-down; 1025 }; 1026 1027 pri_mi2s_default: mi2s-pri-default-state { 1028 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1029 function = "pri_mi2s"; 1030 drive-strength = <8>; 1031 bias-disable; 1032 }; 1033 1034 pri_mi2s_sleep: mi2s-pri-sleep-state { 1035 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1036 function = "pri_mi2s"; 1037 drive-strength = <2>; 1038 bias-disable; 1039 }; 1040 1041 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state { 1042 pins = "gpio116"; 1043 function = "pri_mi2s"; 1044 drive-strength = <8>; 1045 bias-disable; 1046 }; 1047 1048 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state { 1049 pins = "gpio116"; 1050 function = "pri_mi2s"; 1051 drive-strength = <2>; 1052 bias-disable; 1053 }; 1054 1055 pri_mi2s_ws_default: mi2s-pri-ws-default-state { 1056 pins = "gpio110"; 1057 function = "pri_mi2s_ws"; 1058 drive-strength = <8>; 1059 bias-disable; 1060 }; 1061 1062 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state { 1063 pins = "gpio110"; 1064 function = "pri_mi2s_ws"; 1065 drive-strength = <2>; 1066 bias-disable; 1067 }; 1068 1069 sec_mi2s_default: mi2s-sec-default-state { 1070 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1071 function = "sec_mi2s"; 1072 drive-strength = <8>; 1073 bias-disable; 1074 }; 1075 1076 sec_mi2s_sleep: mi2s-sec-sleep-state { 1077 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1078 function = "sec_mi2s"; 1079 drive-strength = <2>; 1080 bias-disable; 1081 }; 1082 1083 sdc1_default: sdc1-default-state { 1084 clk-pins { 1085 pins = "sdc1_clk"; 1086 bias-disable; 1087 drive-strength = <16>; 1088 }; 1089 1090 cmd-pins { 1091 pins = "sdc1_cmd"; 1092 bias-pull-up; 1093 drive-strength = <10>; 1094 }; 1095 1096 data-pins { 1097 pins = "sdc1_data"; 1098 bias-pull-up; 1099 drive-strength = <10>; 1100 }; 1101 }; 1102 1103 sdc1_sleep: sdc1-sleep-state { 1104 clk-pins { 1105 pins = "sdc1_clk"; 1106 bias-disable; 1107 drive-strength = <2>; 1108 }; 1109 1110 cmd-pins { 1111 pins = "sdc1_cmd"; 1112 bias-pull-up; 1113 drive-strength = <2>; 1114 }; 1115 1116 data-pins { 1117 pins = "sdc1_data"; 1118 bias-pull-up; 1119 drive-strength = <2>; 1120 }; 1121 }; 1122 1123 sdc2_default: sdc2-default-state { 1124 clk-pins { 1125 pins = "sdc2_clk"; 1126 bias-disable; 1127 drive-strength = <16>; 1128 }; 1129 1130 cmd-pins { 1131 pins = "sdc2_cmd"; 1132 bias-pull-up; 1133 drive-strength = <10>; 1134 }; 1135 1136 data-pins { 1137 pins = "sdc2_data"; 1138 bias-pull-up; 1139 drive-strength = <10>; 1140 }; 1141 }; 1142 1143 sdc2_sleep: sdc2-sleep-state { 1144 clk-pins { 1145 pins = "sdc2_clk"; 1146 bias-disable; 1147 drive-strength = <2>; 1148 }; 1149 1150 cmd-pins { 1151 pins = "sdc2_cmd"; 1152 bias-pull-up; 1153 drive-strength = <2>; 1154 }; 1155 1156 data-pins { 1157 pins = "sdc2_data"; 1158 bias-pull-up; 1159 drive-strength = <2>; 1160 }; 1161 }; 1162 1163 wcss_wlan_default: wcss-wlan-default-state { 1164 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; 1165 function = "wcss_wlan"; 1166 drive-strength = <6>; 1167 bias-pull-up; 1168 }; 1169 }; 1170 1171 gcc: clock-controller@1800000 { 1172 compatible = "qcom,gcc-msm8939"; 1173 reg = <0x01800000 0x80000>; 1174 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1175 <&sleep_clk>, 1176 <&mdss_dsi0_phy 1>, 1177 <&mdss_dsi0_phy 0>, 1178 <0>, 1179 <0>, 1180 <0>; 1181 clock-names = "xo", 1182 "sleep_clk", 1183 "dsi0pll", 1184 "dsi0pllbyte", 1185 "ext_mclk", 1186 "ext_pri_i2s", 1187 "ext_sec_i2s"; 1188 #clock-cells = <1>; 1189 #reset-cells = <1>; 1190 #power-domain-cells = <1>; 1191 }; 1192 1193 tcsr_mutex: hwlock@1905000 { 1194 compatible = "qcom,tcsr-mutex"; 1195 reg = <0x01905000 0x20000>; 1196 #hwlock-cells = <1>; 1197 }; 1198 1199 tcsr: syscon@1937000 { 1200 compatible = "qcom,tcsr-msm8916", "syscon"; 1201 reg = <0x01937000 0x30000>; 1202 }; 1203 1204 mdss: display-subsystem@1a00000 { 1205 compatible = "qcom,mdss"; 1206 reg = <0x01a00000 0x1000>, 1207 <0x01ac8000 0x3000>; 1208 reg-names = "mdss_phys", "vbif_phys"; 1209 1210 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1211 interrupt-controller; 1212 1213 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1214 <&gcc GCC_MDSS_AXI_CLK>, 1215 <&gcc GCC_MDSS_VSYNC_CLK>; 1216 clock-names = "iface", 1217 "bus", 1218 "vsync"; 1219 1220 power-domains = <&gcc MDSS_GDSC>; 1221 1222 #address-cells = <1>; 1223 #size-cells = <1>; 1224 #interrupt-cells = <1>; 1225 ranges; 1226 1227 status = "disabled"; 1228 1229 mdss_mdp: display-controller@1a01000 { 1230 compatible = "qcom,mdp5"; 1231 reg = <0x01a01000 0x89000>; 1232 reg-names = "mdp_phys"; 1233 1234 interrupt-parent = <&mdss>; 1235 interrupts = <0>; 1236 1237 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1238 <&gcc GCC_MDSS_AXI_CLK>, 1239 <&gcc GCC_MDSS_MDP_CLK>, 1240 <&gcc GCC_MDSS_VSYNC_CLK>; 1241 clock-names = "iface", 1242 "bus", 1243 "core", 1244 "vsync"; 1245 1246 iommus = <&apps_iommu 4>; 1247 1248 interconnects = <&snoc_mm MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 1249 <&snoc_mm MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>; 1250 interconnect-names = "mdp0-mem", "mdp1-mem"; 1251 1252 ports { 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 1256 port@0 { 1257 reg = <0>; 1258 mdss_mdp_intf1_out: endpoint { 1259 remote-endpoint = <&mdss_dsi0_in>; 1260 }; 1261 }; 1262 1263 port@1 { 1264 reg = <1>; 1265 mdss_mdp_intf2_out: endpoint { 1266 remote-endpoint = <&mdss_dsi1_in>; 1267 }; 1268 }; 1269 }; 1270 }; 1271 1272 mdss_dsi0: dsi@1a98000 { 1273 compatible = "qcom,msm8916-dsi-ctrl", 1274 "qcom,mdss-dsi-ctrl"; 1275 reg = <0x01a98000 0x25c>; 1276 reg-names = "dsi_ctrl"; 1277 1278 interrupt-parent = <&mdss>; 1279 interrupts = <4>; 1280 1281 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1282 <&gcc GCC_MDSS_AHB_CLK>, 1283 <&gcc GCC_MDSS_AXI_CLK>, 1284 <&gcc GCC_MDSS_BYTE0_CLK>, 1285 <&gcc GCC_MDSS_PCLK0_CLK>, 1286 <&gcc GCC_MDSS_ESC0_CLK>; 1287 clock-names = "mdp_core", 1288 "iface", 1289 "bus", 1290 "byte", 1291 "pixel", 1292 "core"; 1293 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1294 <&gcc PCLK0_CLK_SRC>; 1295 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1296 <&mdss_dsi0_phy 1>; 1297 1298 phys = <&mdss_dsi0_phy>; 1299 status = "disabled"; 1300 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 1304 ports { 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 1308 port@0 { 1309 reg = <0>; 1310 mdss_dsi0_in: endpoint { 1311 remote-endpoint = <&mdss_mdp_intf1_out>; 1312 }; 1313 }; 1314 1315 port@1 { 1316 reg = <1>; 1317 mdss_dsi0_out: endpoint { 1318 }; 1319 }; 1320 }; 1321 }; 1322 1323 mdss_dsi0_phy: phy@1a98300 { 1324 compatible = "qcom,dsi-phy-28nm-lp"; 1325 reg = <0x01a98300 0xd4>, 1326 <0x01a98500 0x280>, 1327 <0x01a98780 0x30>; 1328 reg-names = "dsi_pll", 1329 "dsi_phy", 1330 "dsi_phy_regulator"; 1331 1332 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1333 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1334 clock-names = "iface", "ref"; 1335 1336 #clock-cells = <1>; 1337 #phy-cells = <0>; 1338 status = "disabled"; 1339 }; 1340 1341 mdss_dsi1: dsi@1aa0000 { 1342 compatible = "qcom,msm8916-dsi-ctrl", 1343 "qcom,mdss-dsi-ctrl"; 1344 reg = <0x01aa0000 0x25c>; 1345 reg-names = "dsi_ctrl"; 1346 1347 interrupt-parent = <&mdss>; 1348 interrupts = <5>; 1349 1350 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1351 <&gcc GCC_MDSS_AHB_CLK>, 1352 <&gcc GCC_MDSS_AXI_CLK>, 1353 <&gcc GCC_MDSS_BYTE1_CLK>, 1354 <&gcc GCC_MDSS_PCLK1_CLK>, 1355 <&gcc GCC_MDSS_ESC1_CLK>; 1356 clock-names = "mdp_core", 1357 "iface", 1358 "bus", 1359 "byte", 1360 "pixel", 1361 "core"; 1362 assigned-clocks = <&gcc BYTE1_CLK_SRC>, 1363 <&gcc PCLK1_CLK_SRC>; 1364 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1365 <&mdss_dsi0_phy 1>; 1366 phys = <&mdss_dsi1_phy>; 1367 status = "disabled"; 1368 1369 ports { 1370 #address-cells = <1>; 1371 #size-cells = <0>; 1372 1373 port@0 { 1374 reg = <0>; 1375 mdss_dsi1_in: endpoint { 1376 remote-endpoint = <&mdss_mdp_intf2_out>; 1377 }; 1378 }; 1379 1380 port@1 { 1381 reg = <1>; 1382 mdss_dsi1_out: endpoint { 1383 }; 1384 }; 1385 }; 1386 }; 1387 1388 mdss_dsi1_phy: phy@1aa0300 { 1389 compatible = "qcom,dsi-phy-28nm-lp"; 1390 reg = <0x01aa0300 0xd4>, 1391 <0x01aa0500 0x280>, 1392 <0x01aa0780 0x30>; 1393 reg-names = "dsi_pll", 1394 "dsi_phy", 1395 "dsi_phy_regulator"; 1396 1397 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1398 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1399 clock-names = "iface", "ref"; 1400 1401 #clock-cells = <1>; 1402 #phy-cells = <0>; 1403 status = "disabled"; 1404 }; 1405 }; 1406 1407 gpu: gpu@1c00000 { 1408 compatible = "qcom,adreno-405.0", "qcom,adreno"; 1409 reg = <0x01c00000 0x10000>; 1410 reg-names = "kgsl_3d0_reg_memory"; 1411 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1412 interrupt-names = "kgsl_3d0_irq"; 1413 clock-names = "core", 1414 "iface", 1415 "mem", 1416 "mem_iface", 1417 "alt_mem_iface", 1418 "gfx3d", 1419 "rbbmtimer"; 1420 clocks = <&gcc GCC_OXILI_GFX3D_CLK>, 1421 <&gcc GCC_OXILI_AHB_CLK>, 1422 <&gcc GCC_OXILI_GMEM_CLK>, 1423 <&gcc GCC_BIMC_GFX_CLK>, 1424 <&gcc GCC_BIMC_GPU_CLK>, 1425 <&gcc GFX3D_CLK_SRC>, 1426 <&gcc GCC_OXILI_TIMER_CLK>; 1427 power-domains = <&gcc OXILI_GDSC>; 1428 operating-points-v2 = <&opp_table>; 1429 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 1430 status = "disabled"; 1431 1432 opp_table: opp-table { 1433 compatible = "operating-points-v2"; 1434 1435 opp-550000000 { 1436 opp-hz = /bits/ 64 <550000000>; 1437 }; 1438 1439 opp-465000000 { 1440 opp-hz = /bits/ 64 <465000000>; 1441 }; 1442 1443 opp-400000000 { 1444 opp-hz = /bits/ 64 <400000000>; 1445 }; 1446 1447 opp-220000000 { 1448 opp-hz = /bits/ 64 <220000000>; 1449 }; 1450 1451 opp-19200000 { 1452 opp-hz = /bits/ 64 <19200000>; 1453 }; 1454 }; 1455 }; 1456 1457 apps_iommu: iommu@1ef0000 { 1458 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1459 reg = <0x01ef0000 0x3000>; 1460 ranges = <0 0x01e20000 0x20000>; 1461 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1462 <&gcc GCC_APSS_TCU_CLK>; 1463 clock-names = "iface", "bus"; 1464 #address-cells = <1>; 1465 #size-cells = <1>; 1466 #iommu-cells = <1>; 1467 qcom,iommu-secure-id = <17>; 1468 1469 /* mdp_0: */ 1470 iommu-ctx@4000 { 1471 compatible = "qcom,msm-iommu-v1-ns"; 1472 reg = <0x4000 0x1000>; 1473 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1474 }; 1475 1476 /* venus_ns: */ 1477 iommu-ctx@5000 { 1478 compatible = "qcom,msm-iommu-v1-sec"; 1479 reg = <0x5000 0x1000>; 1480 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1481 }; 1482 }; 1483 1484 gpu_iommu: iommu@1f08000 { 1485 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1486 ranges = <0 0x1f08000 0x10000>; 1487 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1488 <&gcc GCC_GFX_TCU_CLK>, 1489 <&gcc GCC_GFX_TBU_CLK>; 1490 clock-names = "iface", "bus", "tbu"; 1491 #address-cells = <1>; 1492 #size-cells = <1>; 1493 #iommu-cells = <1>; 1494 qcom,iommu-secure-id = <18>; 1495 1496 /* gfx3d_user: */ 1497 iommu-ctx@1000 { 1498 compatible = "qcom,msm-iommu-v1-ns"; 1499 reg = <0x1000 0x1000>; 1500 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1501 }; 1502 1503 /* gfx3d_priv: */ 1504 iommu-ctx@2000 { 1505 compatible = "qcom,msm-iommu-v1-ns"; 1506 reg = <0x2000 0x1000>; 1507 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1508 }; 1509 }; 1510 1511 spmi_bus: spmi@200f000 { 1512 compatible = "qcom,spmi-pmic-arb"; 1513 reg = <0x0200f000 0x001000>, 1514 <0x02400000 0x400000>, 1515 <0x02c00000 0x400000>, 1516 <0x03800000 0x200000>, 1517 <0x0200a000 0x002100>; 1518 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1519 interrupt-names = "periph_irq"; 1520 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1521 qcom,ee = <0>; 1522 qcom,channel = <0>; 1523 #address-cells = <2>; 1524 #size-cells = <0>; 1525 interrupt-controller; 1526 #interrupt-cells = <4>; 1527 }; 1528 1529 bam_dmux_dma: dma-controller@4044000 { 1530 compatible = "qcom,bam-v1.7.0"; 1531 reg = <0x04044000 0x19000>; 1532 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1533 #dma-cells = <1>; 1534 qcom,ee = <0>; 1535 1536 num-channels = <6>; 1537 qcom,num-ees = <1>; 1538 qcom,powered-remotely; 1539 1540 status = "disabled"; 1541 }; 1542 1543 mpss: remoteproc@4080000 { 1544 compatible = "qcom,msm8916-mss-pil"; 1545 reg = <0x04080000 0x100>, <0x04020000 0x040>; 1546 reg-names = "qdsp6", "rmb"; 1547 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1548 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1549 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1550 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1551 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1552 interrupt-names = "wdog", 1553 "fatal", 1554 "ready", 1555 "handover", 1556 "stop-ack"; 1557 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1558 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1559 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1560 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1561 clock-names = "iface", 1562 "bus", 1563 "mem", 1564 "xo"; 1565 power-domains = <&rpmpd MSM8939_VDDMDCX>, 1566 <&rpmpd MSM8939_VDDMX>; 1567 power-domain-names = "cx", "mx"; 1568 qcom,smem-states = <&hexagon_smp2p_out 0>; 1569 qcom,smem-state-names = "stop"; 1570 resets = <&scm 0>; 1571 reset-names = "mss_restart"; 1572 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1573 status = "disabled"; 1574 1575 bam_dmux: bam-dmux { 1576 compatible = "qcom,bam-dmux"; 1577 1578 interrupt-parent = <&hexagon_smsm>; 1579 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1580 interrupt-names = "pc", "pc-ack"; 1581 1582 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1583 qcom,smem-state-names = "pc", "pc-ack"; 1584 1585 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1586 dma-names = "tx", "rx"; 1587 1588 status = "disabled"; 1589 }; 1590 1591 mba { 1592 memory-region = <&mba_mem>; 1593 }; 1594 1595 mpss { 1596 memory-region = <&mpss_mem>; 1597 }; 1598 1599 smd-edge { 1600 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1601 1602 qcom,smd-edge = <0>; 1603 mboxes = <&apcs1_mbox 12>; 1604 qcom,remote-pid = <1>; 1605 1606 label = "hexagon"; 1607 1608 apr: apr { 1609 compatible = "qcom,apr-v2"; 1610 qcom,smd-channels = "apr_audio_svc"; 1611 qcom,domain = <APR_DOMAIN_ADSP>; 1612 #address-cells = <1>; 1613 #size-cells = <0>; 1614 status = "disabled"; 1615 1616 q6core: service@3 { 1617 compatible = "qcom,q6core"; 1618 reg = <APR_SVC_ADSP_CORE>; 1619 }; 1620 1621 q6afe: service@4 { 1622 compatible = "qcom,q6afe"; 1623 reg = <APR_SVC_AFE>; 1624 1625 q6afedai: dais { 1626 compatible = "qcom,q6afe-dais"; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 #sound-dai-cells = <1>; 1630 }; 1631 }; 1632 1633 q6asm: service@7 { 1634 compatible = "qcom,q6asm"; 1635 reg = <APR_SVC_ASM>; 1636 1637 q6asmdai: dais { 1638 compatible = "qcom,q6asm-dais"; 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 #sound-dai-cells = <1>; 1642 }; 1643 }; 1644 1645 q6adm: service@8 { 1646 compatible = "qcom,q6adm"; 1647 reg = <APR_SVC_ADM>; 1648 1649 q6routing: routing { 1650 compatible = "qcom,q6adm-routing"; 1651 #sound-dai-cells = <0>; 1652 }; 1653 }; 1654 }; 1655 }; 1656 }; 1657 1658 sound: sound@7702000 { 1659 compatible = "qcom,apq8016-sbc-sndcard"; 1660 reg = <0x07702000 0x4>, 1661 <0x07702004 0x4>; 1662 reg-names = "mic-iomux", "spkr-iomux"; 1663 status = "disabled"; 1664 }; 1665 1666 lpass: audio-controller@7708000 { 1667 compatible = "qcom,apq8016-lpass-cpu"; 1668 reg = <0x07708000 0x10000>; 1669 reg-names = "lpass-lpaif"; 1670 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1671 interrupt-names = "lpass-irq-lpaif"; 1672 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1673 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1674 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1675 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 1676 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, 1677 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 1678 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; 1679 clock-names = "ahbix-clk", 1680 "mi2s-bit-clk0", 1681 "mi2s-bit-clk1", 1682 "mi2s-bit-clk2", 1683 "mi2s-bit-clk3", 1684 "pcnoc-mport-clk", 1685 "pcnoc-sway-clk"; 1686 #sound-dai-cells = <1>; 1687 #address-cells = <1>; 1688 #size-cells = <0>; 1689 status = "disabled"; 1690 }; 1691 1692 lpass_codec: audio-codec@771c000 { 1693 compatible = "qcom,msm8916-wcd-digital-codec"; 1694 reg = <0x0771c000 0x400>; 1695 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1696 <&gcc GCC_CODEC_DIGCODEC_CLK>; 1697 clock-names = "ahbix-clk", "mclk"; 1698 #sound-dai-cells = <1>; 1699 status = "disabled"; 1700 }; 1701 1702 sdhc_1: mmc@7824900 { 1703 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1704 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 1705 reg-names = "hc", "core"; 1706 1707 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1709 interrupt-names = "hc_irq", "pwr_irq"; 1710 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1711 <&gcc GCC_SDCC1_APPS_CLK>, 1712 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1713 clock-names = "iface", "core", "xo"; 1714 resets = <&gcc GCC_SDCC1_BCR>; 1715 pinctrl-0 = <&sdc1_default>; 1716 pinctrl-1 = <&sdc1_sleep>; 1717 pinctrl-names = "default", "sleep"; 1718 mmc-ddr-1_8v; 1719 bus-width = <8>; 1720 non-removable; 1721 status = "disabled"; 1722 }; 1723 1724 sdhc_2: mmc@7864900 { 1725 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1726 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 1727 reg-names = "hc", "core"; 1728 1729 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1731 interrupt-names = "hc_irq", "pwr_irq"; 1732 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1733 <&gcc GCC_SDCC2_APPS_CLK>, 1734 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1735 clock-names = "iface", "core", "xo"; 1736 resets = <&gcc GCC_SDCC2_BCR>; 1737 pinctrl-0 = <&sdc2_default>; 1738 pinctrl-1 = <&sdc2_sleep>; 1739 pinctrl-names = "default", "sleep"; 1740 bus-width = <4>; 1741 status = "disabled"; 1742 }; 1743 1744 blsp_dma: dma-controller@7884000 { 1745 compatible = "qcom,bam-v1.7.0"; 1746 reg = <0x07884000 0x23000>; 1747 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1748 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1749 clock-names = "bam_clk"; 1750 #dma-cells = <1>; 1751 qcom,ee = <0>; 1752 qcom,controlled-remotely; 1753 }; 1754 1755 blsp_uart1: serial@78af000 { 1756 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1757 reg = <0x078af000 0x200>; 1758 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1759 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1760 clock-names = "core", "iface"; 1761 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 1762 dma-names = "tx", "rx"; 1763 pinctrl-0 = <&blsp_uart1_default>; 1764 pinctrl-1 = <&blsp_uart1_sleep>; 1765 pinctrl-names = "default", "sleep"; 1766 status = "disabled"; 1767 }; 1768 1769 blsp_uart2: serial@78b0000 { 1770 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1771 reg = <0x078b0000 0x200>; 1772 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1773 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1774 clock-names = "core", "iface"; 1775 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 1776 dma-names = "tx", "rx"; 1777 pinctrl-0 = <&blsp_uart2_default>; 1778 pinctrl-1 = <&blsp_uart2_sleep>; 1779 pinctrl-names = "default", "sleep"; 1780 status = "disabled"; 1781 }; 1782 1783 blsp_i2c1: i2c@78b5000 { 1784 compatible = "qcom,i2c-qup-v2.2.1"; 1785 reg = <0x078b5000 0x500>; 1786 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1787 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1788 <&gcc GCC_BLSP1_AHB_CLK>; 1789 clock-names = "core", "iface"; 1790 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 1791 dma-names = "tx", "rx"; 1792 pinctrl-0 = <&blsp_i2c1_default>; 1793 pinctrl-1 = <&blsp_i2c1_sleep>; 1794 pinctrl-names = "default", "sleep"; 1795 #address-cells = <1>; 1796 #size-cells = <0>; 1797 status = "disabled"; 1798 }; 1799 1800 blsp_spi1: spi@78b5000 { 1801 compatible = "qcom,spi-qup-v2.2.1"; 1802 reg = <0x078b5000 0x500>; 1803 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1804 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1805 <&gcc GCC_BLSP1_AHB_CLK>; 1806 clock-names = "core", "iface"; 1807 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 1808 dma-names = "tx", "rx"; 1809 pinctrl-0 = <&blsp_spi1_default>; 1810 pinctrl-1 = <&blsp_spi1_sleep>; 1811 pinctrl-names = "default", "sleep"; 1812 #address-cells = <1>; 1813 #size-cells = <0>; 1814 status = "disabled"; 1815 }; 1816 1817 blsp_i2c2: i2c@78b6000 { 1818 compatible = "qcom,i2c-qup-v2.2.1"; 1819 reg = <0x078b6000 0x500>; 1820 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1821 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1822 <&gcc GCC_BLSP1_AHB_CLK>; 1823 clock-names = "core", "iface"; 1824 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 1825 dma-names = "tx", "rx"; 1826 pinctrl-0 = <&blsp_i2c2_default>; 1827 pinctrl-1 = <&blsp_i2c2_sleep>; 1828 pinctrl-names = "default", "sleep"; 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 status = "disabled"; 1832 }; 1833 1834 blsp_spi2: spi@78b6000 { 1835 compatible = "qcom,spi-qup-v2.2.1"; 1836 reg = <0x078b6000 0x500>; 1837 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1838 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 1839 <&gcc GCC_BLSP1_AHB_CLK>; 1840 clock-names = "core", "iface"; 1841 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 1842 dma-names = "tx", "rx"; 1843 pinctrl-0 = <&blsp_spi2_default>; 1844 pinctrl-1 = <&blsp_spi2_sleep>; 1845 pinctrl-names = "default", "sleep"; 1846 #address-cells = <1>; 1847 #size-cells = <0>; 1848 status = "disabled"; 1849 }; 1850 1851 blsp_i2c3: i2c@78b7000 { 1852 compatible = "qcom,i2c-qup-v2.2.1"; 1853 reg = <0x078b7000 0x500>; 1854 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1855 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1856 <&gcc GCC_BLSP1_AHB_CLK>; 1857 clock-names = "core", "iface"; 1858 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 1859 dma-names = "tx", "rx"; 1860 pinctrl-0 = <&blsp_i2c3_default>; 1861 pinctrl-1 = <&blsp_i2c3_sleep>; 1862 pinctrl-names = "default", "sleep"; 1863 #address-cells = <1>; 1864 #size-cells = <0>; 1865 status = "disabled"; 1866 }; 1867 1868 blsp_spi3: spi@78b7000 { 1869 compatible = "qcom,spi-qup-v2.2.1"; 1870 reg = <0x078b7000 0x500>; 1871 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1872 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1873 <&gcc GCC_BLSP1_AHB_CLK>; 1874 clock-names = "core", "iface"; 1875 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 1876 dma-names = "tx", "rx"; 1877 pinctrl-0 = <&blsp_spi3_default>; 1878 pinctrl-1 = <&blsp_spi3_sleep>; 1879 pinctrl-names = "default", "sleep"; 1880 #address-cells = <1>; 1881 #size-cells = <0>; 1882 status = "disabled"; 1883 }; 1884 1885 blsp_i2c4: i2c@78b8000 { 1886 compatible = "qcom,i2c-qup-v2.2.1"; 1887 reg = <0x078b8000 0x500>; 1888 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1889 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1890 <&gcc GCC_BLSP1_AHB_CLK>; 1891 clock-names = "core", "iface"; 1892 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 1893 dma-names = "tx", "rx"; 1894 pinctrl-0 = <&blsp_i2c4_default>; 1895 pinctrl-1 = <&blsp_i2c4_sleep>; 1896 pinctrl-names = "default", "sleep"; 1897 #address-cells = <1>; 1898 #size-cells = <0>; 1899 status = "disabled"; 1900 }; 1901 1902 blsp_spi4: spi@78b8000 { 1903 compatible = "qcom,spi-qup-v2.2.1"; 1904 reg = <0x078b8000 0x500>; 1905 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1906 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 1907 <&gcc GCC_BLSP1_AHB_CLK>; 1908 clock-names = "core", "iface"; 1909 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 1910 dma-names = "tx", "rx"; 1911 pinctrl-0 = <&blsp_spi4_default>; 1912 pinctrl-1 = <&blsp_spi4_sleep>; 1913 pinctrl-names = "default", "sleep"; 1914 #address-cells = <1>; 1915 #size-cells = <0>; 1916 status = "disabled"; 1917 }; 1918 1919 blsp_i2c5: i2c@78b9000 { 1920 compatible = "qcom,i2c-qup-v2.2.1"; 1921 reg = <0x078b9000 0x500>; 1922 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1923 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 1924 <&gcc GCC_BLSP1_AHB_CLK>; 1925 clock-names = "core", "iface"; 1926 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 1927 dma-names = "tx", "rx"; 1928 pinctrl-0 = <&blsp_i2c5_default>; 1929 pinctrl-1 = <&blsp_i2c5_sleep>; 1930 pinctrl-names = "default", "sleep"; 1931 #address-cells = <1>; 1932 #size-cells = <0>; 1933 status = "disabled"; 1934 }; 1935 1936 blsp_spi5: spi@78b9000 { 1937 compatible = "qcom,spi-qup-v2.2.1"; 1938 reg = <0x078b9000 0x500>; 1939 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1940 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 1941 <&gcc GCC_BLSP1_AHB_CLK>; 1942 clock-names = "core", "iface"; 1943 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 1944 dma-names = "tx", "rx"; 1945 pinctrl-0 = <&blsp_spi5_default>; 1946 pinctrl-1 = <&blsp_spi5_sleep>; 1947 pinctrl-names = "default", "sleep"; 1948 #address-cells = <1>; 1949 #size-cells = <0>; 1950 status = "disabled"; 1951 }; 1952 1953 blsp_i2c6: i2c@78ba000 { 1954 compatible = "qcom,i2c-qup-v2.2.1"; 1955 reg = <0x078ba000 0x500>; 1956 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1957 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 1958 <&gcc GCC_BLSP1_AHB_CLK>; 1959 clock-names = "core", "iface"; 1960 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 1961 dma-names = "tx", "rx"; 1962 pinctrl-0 = <&blsp_i2c6_default>; 1963 pinctrl-1 = <&blsp_i2c6_sleep>; 1964 pinctrl-names = "default", "sleep"; 1965 #address-cells = <1>; 1966 #size-cells = <0>; 1967 status = "disabled"; 1968 }; 1969 1970 blsp_spi6: spi@78ba000 { 1971 compatible = "qcom,spi-qup-v2.2.1"; 1972 reg = <0x078ba000 0x500>; 1973 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1974 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 1975 <&gcc GCC_BLSP1_AHB_CLK>; 1976 clock-names = "core", "iface"; 1977 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 1978 dma-names = "tx", "rx"; 1979 pinctrl-0 = <&blsp_spi6_default>; 1980 pinctrl-1 = <&blsp_spi6_sleep>; 1981 pinctrl-names = "default", "sleep"; 1982 #address-cells = <1>; 1983 #size-cells = <0>; 1984 status = "disabled"; 1985 }; 1986 1987 usb: usb@78d9000 { 1988 compatible = "qcom,ci-hdrc"; 1989 reg = <0x078d9000 0x200>, 1990 <0x078d9200 0x200>; 1991 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1993 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 1994 <&gcc GCC_USB_HS_SYSTEM_CLK>; 1995 clock-names = "iface", "core"; 1996 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 1997 assigned-clock-rates = <80000000>; 1998 resets = <&gcc GCC_USB_HS_BCR>; 1999 reset-names = "core"; 2000 #reset-cells = <1>; 2001 phy_type = "ulpi"; 2002 dr_mode = "otg"; 2003 adp-disable; 2004 hnp-disable; 2005 srp-disable; 2006 ahb-burst-config = <0>; 2007 phy-names = "usb-phy"; 2008 phys = <&usb_hs_phy>; 2009 status = "disabled"; 2010 2011 ulpi { 2012 usb_hs_phy: phy { 2013 compatible = "qcom,usb-hs-phy-msm8916", 2014 "qcom,usb-hs-phy"; 2015 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2016 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 2017 clock-names = "ref", "sleep"; 2018 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 2019 reset-names = "phy", "por"; 2020 #phy-cells = <0>; 2021 qcom,init-seq = /bits/ 8 <0x0 0x44>, 2022 <0x1 0x6b>, 2023 <0x2 0x24>, 2024 <0x3 0x13>; 2025 }; 2026 }; 2027 }; 2028 2029 wcnss: remoteproc@a204000 { 2030 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 2031 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 2032 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2033 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2034 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2035 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2036 interrupt-names = "wdog", 2037 "fatal", 2038 "ready", 2039 "handover", 2040 "stop-ack"; 2041 reg = <0x0a204000 0x2000>, 2042 <0x0a202000 0x1000>, 2043 <0x0a21b000 0x3000>; 2044 reg-names = "ccu", "dxe", "pmu"; 2045 2046 memory-region = <&wcnss_mem>; 2047 2048 power-domains = <&rpmpd MSM8939_VDDCX>, 2049 <&rpmpd MSM8939_VDDMX>; 2050 power-domain-names = "cx", "mx"; 2051 2052 qcom,smem-states = <&wcnss_smp2p_out 0>; 2053 qcom,smem-state-names = "stop"; 2054 2055 pinctrl-names = "default"; 2056 pinctrl-0 = <&wcss_wlan_default>; 2057 2058 status = "disabled"; 2059 2060 wcnss_iris: iris { 2061 /* Separate chip, compatible is board-specific */ 2062 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 2063 clock-names = "xo"; 2064 }; 2065 2066 smd-edge { 2067 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 2068 qcom,ipc = <&apcs1_mbox 8 17>; 2069 qcom,smd-edge = <6>; 2070 qcom,remote-pid = <4>; 2071 2072 label = "pronto"; 2073 2074 wcnss { 2075 compatible = "qcom,wcnss"; 2076 qcom,smd-channels = "WCNSS_CTRL"; 2077 2078 qcom,mmio = <&wcnss>; 2079 2080 wcnss_bt: bluetooth { 2081 compatible = "qcom,wcnss-bt"; 2082 }; 2083 2084 wcnss_wifi: wifi { 2085 compatible = "qcom,wcnss-wlan"; 2086 2087 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2088 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2089 interrupt-names = "tx", "rx"; 2090 2091 qcom,smem-states = <&apps_smsm 10>, 2092 <&apps_smsm 9>; 2093 qcom,smem-state-names = "tx-enable", 2094 "tx-rings-empty"; 2095 }; 2096 }; 2097 }; 2098 }; 2099 2100 intc: interrupt-controller@b000000 { 2101 compatible = "qcom,msm-qgic2"; 2102 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, 2103 <0x0b001000 0x1000>, <0x0b004000 0x2000>; 2104 interrupt-controller; 2105 #interrupt-cells = <3>; 2106 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2107 }; 2108 2109 apcs1_mbox: mailbox@b011000 { 2110 compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; 2111 reg = <0x0b011000 0x1000>; 2112 clocks = <&a53pll_c1>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 2113 clock-names = "pll", "aux", "ref"; 2114 #clock-cells = <0>; 2115 assigned-clocks = <&apcs2>; 2116 assigned-clock-rates = <297600000>; 2117 #mbox-cells = <1>; 2118 }; 2119 2120 a53pll_c1: clock@b016000 { 2121 compatible = "qcom,msm8939-a53pll"; 2122 reg = <0x0b016000 0x40>; 2123 #clock-cells = <0>; 2124 }; 2125 2126 acc0: clock-controller@b088000 { 2127 compatible = "qcom,kpss-acc-v2"; 2128 reg = <0x0b088000 0x1000>; 2129 }; 2130 2131 saw0: power-manager@b089000 { 2132 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2133 reg = <0x0b089000 0x1000>; 2134 }; 2135 2136 acc1: clock-controller@b098000 { 2137 compatible = "qcom,kpss-acc-v2"; 2138 reg = <0x0b098000 0x1000>; 2139 }; 2140 2141 saw1: power-manager@b099000 { 2142 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2143 reg = <0x0b099000 0x1000>; 2144 }; 2145 2146 acc2: clock-controller@b0a8000 { 2147 compatible = "qcom,kpss-acc-v2"; 2148 reg = <0x0b0a8000 0x1000>; 2149 }; 2150 2151 saw2: power-manager@b0a9000 { 2152 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2153 reg = <0x0b0a9000 0x1000>; 2154 }; 2155 2156 acc3: clock-controller@b0b8000 { 2157 compatible = "qcom,kpss-acc-v2"; 2158 reg = <0x0b0b8000 0x1000>; 2159 }; 2160 2161 saw3: power-manager@b0b9000 { 2162 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2163 reg = <0x0b0b9000 0x1000>; 2164 }; 2165 2166 apcs0_mbox: mailbox@b111000 { 2167 compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; 2168 reg = <0x0b111000 0x1000>; 2169 clocks = <&a53pll_c0>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 2170 clock-names = "pll", "aux", "ref"; 2171 #clock-cells = <0>; 2172 #mbox-cells = <1>; 2173 }; 2174 2175 a53pll_c0: clock@b116000 { 2176 compatible = "qcom,msm8939-a53pll"; 2177 reg = <0x0b116000 0x40>; 2178 #clock-cells = <0>; 2179 }; 2180 2181 timer@b120000 { 2182 compatible = "arm,armv7-timer-mem"; 2183 reg = <0x0b120000 0x1000>; 2184 #address-cells = <1>; 2185 #size-cells = <1>; 2186 ranges; 2187 /* Necessary because firmware does not configure this correctly */ 2188 clock-frequency = <19200000>; 2189 2190 frame@b121000 { 2191 reg = <0x0b121000 0x1000>, 2192 <0x0b122000 0x1000>; 2193 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2194 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2195 frame-number = <0>; 2196 }; 2197 2198 frame@b123000 { 2199 reg = <0x0b123000 0x1000>; 2200 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2201 frame-number = <1>; 2202 status = "disabled"; 2203 }; 2204 2205 frame@b124000 { 2206 reg = <0x0b124000 0x1000>; 2207 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2208 frame-number = <2>; 2209 status = "disabled"; 2210 }; 2211 2212 frame@b125000 { 2213 reg = <0x0b125000 0x1000>; 2214 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2215 frame-number = <3>; 2216 status = "disabled"; 2217 }; 2218 2219 frame@b126000 { 2220 reg = <0x0b126000 0x1000>; 2221 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2222 frame-number = <4>; 2223 status = "disabled"; 2224 }; 2225 2226 frame@b127000 { 2227 reg = <0x0b127000 0x1000>; 2228 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2229 frame-number = <5>; 2230 status = "disabled"; 2231 }; 2232 2233 frame@b128000 { 2234 reg = <0x0b128000 0x1000>; 2235 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2236 frame-number = <6>; 2237 status = "disabled"; 2238 }; 2239 }; 2240 2241 acc4: clock-controller@b188000 { 2242 compatible = "qcom,kpss-acc-v2"; 2243 reg = <0x0b188000 0x1000>; 2244 }; 2245 2246 saw4: power-manager@b189000 { 2247 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2248 reg = <0x0b189000 0x1000>; 2249 }; 2250 2251 acc5: clock-controller@b198000 { 2252 compatible = "qcom,kpss-acc-v2"; 2253 reg = <0x0b198000 0x1000>; 2254 }; 2255 2256 saw5: power-manager@b199000 { 2257 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2258 reg = <0x0b199000 0x1000>; 2259 }; 2260 2261 acc6: clock-controller@b1a8000 { 2262 compatible = "qcom,kpss-acc-v2"; 2263 reg = <0x0b1a8000 0x1000>; 2264 }; 2265 2266 saw6: power-manager@b1a9000 { 2267 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2268 reg = <0x0b1a9000 0x1000>; 2269 }; 2270 2271 acc7: clock-controller@b1b8000 { 2272 compatible = "qcom,kpss-acc-v2"; 2273 reg = <0x0b1b8000 0x1000>; 2274 }; 2275 2276 saw7: power-manager@b1b9000 { 2277 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2278 reg = <0x0b1b9000 0x1000>; 2279 }; 2280 2281 a53pll_cci: clock@b1d0000 { 2282 compatible = "qcom,msm8939-a53pll"; 2283 reg = <0x0b1d0000 0x40>; 2284 #clock-cells = <0>; 2285 }; 2286 2287 apcs2: mailbox@b1d1000 { 2288 compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; 2289 reg = <0x0b1d1000 0x1000>; 2290 clocks = <&a53pll_cci>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 2291 clock-names = "pll", "aux", "ref"; 2292 #clock-cells = <0>; 2293 #mbox-cells = <1>; 2294 }; 2295 }; 2296 2297 thermal_zones: thermal-zones { 2298 cpu0-thermal { 2299 polling-delay-passive = <250>; 2300 polling-delay = <1000>; 2301 2302 thermal-sensors = <&tsens 5>; 2303 2304 trips { 2305 cpu0_alert: trip0 { 2306 temperature = <75000>; 2307 hysteresis = <2000>; 2308 type = "passive"; 2309 }; 2310 2311 cpu0_crit: trip1 { 2312 temperature = <115000>; 2313 hysteresis = <0>; 2314 type = "critical"; 2315 }; 2316 }; 2317 2318 cooling-maps { 2319 map0 { 2320 trip = <&cpu0_alert>; 2321 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2322 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2323 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2324 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2325 }; 2326 }; 2327 }; 2328 2329 cpu1-thermal { 2330 polling-delay-passive = <250>; 2331 polling-delay = <1000>; 2332 2333 thermal-sensors = <&tsens 6>; 2334 2335 trips { 2336 cpu1_alert: trip0 { 2337 temperature = <75000>; 2338 hysteresis = <2000>; 2339 type = "passive"; 2340 }; 2341 2342 cpu1_crit: trip1 { 2343 temperature = <110000>; 2344 hysteresis = <2000>; 2345 type = "critical"; 2346 }; 2347 }; 2348 2349 cooling-maps { 2350 map0 { 2351 trip = <&cpu1_alert>; 2352 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2353 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2354 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2355 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2356 }; 2357 }; 2358 }; 2359 2360 cpu2-thermal { 2361 polling-delay-passive = <250>; 2362 polling-delay = <1000>; 2363 2364 thermal-sensors = <&tsens 7>; 2365 2366 trips { 2367 cpu2_alert: trip0 { 2368 temperature = <75000>; 2369 hysteresis = <2000>; 2370 type = "passive"; 2371 }; 2372 2373 cpu2_crit: trip1 { 2374 temperature = <110000>; 2375 hysteresis = <2000>; 2376 type = "critical"; 2377 }; 2378 }; 2379 2380 cooling-maps { 2381 map0 { 2382 trip = <&cpu2_alert>; 2383 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2384 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2385 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2386 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2387 }; 2388 }; 2389 }; 2390 2391 cpu3-thermal { 2392 polling-delay-passive = <250>; 2393 polling-delay = <1000>; 2394 2395 thermal-sensors = <&tsens 8>; 2396 2397 trips { 2398 cpu3_alert: trip0 { 2399 temperature = <75000>; 2400 hysteresis = <2000>; 2401 type = "passive"; 2402 }; 2403 2404 cpu3_crit: trip1 { 2405 temperature = <110000>; 2406 hysteresis = <2000>; 2407 type = "critical"; 2408 }; 2409 }; 2410 2411 cooling-maps { 2412 map0 { 2413 trip = <&cpu3_alert>; 2414 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2415 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2416 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2417 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2418 }; 2419 }; 2420 }; 2421 2422 cpu4567-thermal { 2423 polling-delay-passive = <250>; 2424 polling-delay = <1000>; 2425 2426 thermal-sensors = <&tsens 9>; 2427 2428 trips { 2429 cpu4567_alert: trip0 { 2430 temperature = <75000>; 2431 hysteresis = <2000>; 2432 type = "passive"; 2433 }; 2434 2435 cpu4567_crit: trip1 { 2436 temperature = <110000>; 2437 hysteresis = <2000>; 2438 type = "critical"; 2439 }; 2440 }; 2441 2442 cooling-maps { 2443 map0 { 2444 trip = <&cpu4567_alert>; 2445 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2446 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2447 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2448 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2449 }; 2450 }; 2451 }; 2452 2453 gpu-thermal { 2454 polling-delay-passive = <250>; 2455 polling-delay = <1000>; 2456 2457 thermal-sensors = <&tsens 3>; 2458 2459 trips { 2460 gpu_alert0: trip-point0 { 2461 temperature = <75000>; 2462 hysteresis = <2000>; 2463 type = "passive"; 2464 }; 2465 2466 gpu_crit: gpu_crit { 2467 temperature = <95000>; 2468 hysteresis = <2000>; 2469 type = "critical"; 2470 }; 2471 }; 2472 }; 2473 2474 modem1-thermal { 2475 polling-delay-passive = <250>; 2476 polling-delay = <1000>; 2477 2478 thermal-sensors = <&tsens 0>; 2479 2480 trips { 2481 modem1_alert0: trip-point0 { 2482 temperature = <85000>; 2483 hysteresis = <2000>; 2484 type = "hot"; 2485 }; 2486 }; 2487 }; 2488 2489 modem2-thermal { 2490 polling-delay-passive = <250>; 2491 polling-delay = <1000>; 2492 2493 thermal-sensors = <&tsens 2>; 2494 2495 trips { 2496 modem2_alert0: trip-point0 { 2497 temperature = <85000>; 2498 hysteresis = <2000>; 2499 type = "hot"; 2500 }; 2501 }; 2502 }; 2503 2504 camera-thermal { 2505 polling-delay-passive = <250>; 2506 polling-delay = <1000>; 2507 2508 thermal-sensors = <&tsens 1>; 2509 2510 trips { 2511 cam_alert0: trip-point0 { 2512 temperature = <75000>; 2513 hysteresis = <2000>; 2514 type = "hot"; 2515 }; 2516 }; 2517 }; 2518 }; 2519 2520 timer { 2521 compatible = "arm,armv8-timer"; 2522 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2523 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2524 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2525 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2526 }; 2527}; 2528