1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
6 * Copyright (c) 2012 Luiz Otavio O Souza.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 */
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/rman.h>
39 #include <sys/lock.h>
40 #include <sys/mutex.h>
41 #include <sys/gpio.h>
42 #include <sys/proc.h>
43
44 #include <machine/bus.h>
45 #include <machine/resource.h>
46 #include <machine/intr.h>
47
48 #include <dev/gpio/gpiobusvar.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
51 #include <dev/fdt/fdt_pinctrl.h>
52
53 #include <arm/allwinner/aw_machdep.h>
54 #include <arm/allwinner/allwinner_pinctrl.h>
55 #include <dev/clk/clk.h>
56 #include <dev/hwreset/hwreset.h>
57 #include <dev/regulator/regulator.h>
58
59 #if defined(__aarch64__)
60 #include "opt_soc.h"
61 #endif
62
63 #include "pic_if.h"
64 #include "gpio_if.h"
65
66 #define AW_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
67 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN);
68
69 #define AW_GPIO_INTR_CAPS (GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | \
70 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH)
71
72 #define AW_GPIO_NONE 0
73 #define AW_GPIO_PULLUP 1
74 #define AW_GPIO_PULLDOWN 2
75
76 #define AW_GPIO_INPUT 0
77 #define AW_GPIO_OUTPUT 1
78
79 #define AW_GPIO_DRV_MASK 0x3
80 #define AW_GPIO_PUD_MASK 0x3
81
82 #define AW_PINCTRL 1
83 #define AW_R_PINCTRL 2
84
85 struct aw_gpio_conf {
86 struct allwinner_padconf *padconf;
87 const char *banks;
88 };
89
90 /* Defined in aw_padconf.c */
91 #ifdef SOC_ALLWINNER_A10
92 extern struct allwinner_padconf a10_padconf;
93 struct aw_gpio_conf a10_gpio_conf = {
94 .padconf = &a10_padconf,
95 .banks = "abcdefghi",
96 };
97 #endif
98
99 /* Defined in a13_padconf.c */
100 #ifdef SOC_ALLWINNER_A13
101 extern struct allwinner_padconf a13_padconf;
102 struct aw_gpio_conf a13_gpio_conf = {
103 .padconf = &a13_padconf,
104 .banks = "bcdefg",
105 };
106 #endif
107
108 /* Defined in a20_padconf.c */
109 #ifdef SOC_ALLWINNER_A20
110 extern struct allwinner_padconf a20_padconf;
111 struct aw_gpio_conf a20_gpio_conf = {
112 .padconf = &a20_padconf,
113 .banks = "abcdefghi",
114 };
115 #endif
116
117 /* Defined in a31_padconf.c */
118 #ifdef SOC_ALLWINNER_A31
119 extern struct allwinner_padconf a31_padconf;
120 struct aw_gpio_conf a31_gpio_conf = {
121 .padconf = &a31_padconf,
122 .banks = "abcdefgh",
123 };
124 #endif
125
126 /* Defined in a31s_padconf.c */
127 #ifdef SOC_ALLWINNER_A31S
128 extern struct allwinner_padconf a31s_padconf;
129 struct aw_gpio_conf a31s_gpio_conf = {
130 .padconf = &a31s_padconf,
131 .banks = "abcdefgh",
132 };
133 #endif
134
135 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S)
136 extern struct allwinner_padconf a31_r_padconf;
137 struct aw_gpio_conf a31_r_gpio_conf = {
138 .padconf = &a31_r_padconf,
139 .banks = "lm",
140 };
141 #endif
142
143 /* Defined in a33_padconf.c */
144 #ifdef SOC_ALLWINNER_A33
145 extern struct allwinner_padconf a33_padconf;
146 struct aw_gpio_conf a33_gpio_conf = {
147 .padconf = &a33_padconf,
148 .banks = "bcdefgh",
149 };
150 #endif
151
152 /* Defined in h3_padconf.c */
153 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
154 extern struct allwinner_padconf h3_padconf;
155 extern struct allwinner_padconf h3_r_padconf;
156 struct aw_gpio_conf h3_gpio_conf = {
157 .padconf = &h3_padconf,
158 .banks = "acdefg",
159 };
160 struct aw_gpio_conf h3_r_gpio_conf = {
161 .padconf = &h3_r_padconf,
162 .banks = "l",
163 };
164 #endif
165
166 /* Defined in a83t_padconf.c */
167 #ifdef SOC_ALLWINNER_A83T
168 extern struct allwinner_padconf a83t_padconf;
169 extern struct allwinner_padconf a83t_r_padconf;
170 struct aw_gpio_conf a83t_gpio_conf = {
171 .padconf = &a83t_padconf,
172 .banks = "bcdefgh"
173 };
174 struct aw_gpio_conf a83t_r_gpio_conf = {
175 .padconf = &a83t_r_padconf,
176 .banks = "l",
177 };
178 #endif
179
180 /* Defined in a64_padconf.c */
181 #ifdef SOC_ALLWINNER_A64
182 extern struct allwinner_padconf a64_padconf;
183 extern struct allwinner_padconf a64_r_padconf;
184 struct aw_gpio_conf a64_gpio_conf = {
185 .padconf = &a64_padconf,
186 .banks = "bcdefgh",
187 };
188 struct aw_gpio_conf a64_r_gpio_conf = {
189 .padconf = &a64_r_padconf,
190 .banks = "l",
191 };
192 #endif
193
194 /* Defined in h6_padconf.c */
195 #ifdef SOC_ALLWINNER_H6
196 extern struct allwinner_padconf h6_padconf;
197 extern struct allwinner_padconf h6_r_padconf;
198 struct aw_gpio_conf h6_gpio_conf = {
199 .padconf = &h6_padconf,
200 .banks = "cdfgh",
201 };
202 struct aw_gpio_conf h6_r_gpio_conf = {
203 .padconf = &h6_r_padconf,
204 .banks = "lm",
205 };
206 #endif
207
208 static struct ofw_compat_data compat_data[] = {
209 #ifdef SOC_ALLWINNER_A10
210 {"allwinner,sun4i-a10-pinctrl", (uintptr_t)&a10_gpio_conf},
211 #endif
212 #ifdef SOC_ALLWINNER_A13
213 {"allwinner,sun5i-a13-pinctrl", (uintptr_t)&a13_gpio_conf},
214 #endif
215 #ifdef SOC_ALLWINNER_A20
216 {"allwinner,sun7i-a20-pinctrl", (uintptr_t)&a20_gpio_conf},
217 #endif
218 #ifdef SOC_ALLWINNER_A31
219 {"allwinner,sun6i-a31-pinctrl", (uintptr_t)&a31_gpio_conf},
220 #endif
221 #ifdef SOC_ALLWINNER_A31S
222 {"allwinner,sun6i-a31s-pinctrl", (uintptr_t)&a31s_gpio_conf},
223 #endif
224 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S)
225 {"allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&a31_r_gpio_conf},
226 #endif
227 #ifdef SOC_ALLWINNER_A33
228 {"allwinner,sun6i-a33-pinctrl", (uintptr_t)&a33_gpio_conf},
229 #endif
230 #ifdef SOC_ALLWINNER_A83T
231 {"allwinner,sun8i-a83t-pinctrl", (uintptr_t)&a83t_gpio_conf},
232 {"allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&a83t_r_gpio_conf},
233 #endif
234 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
235 {"allwinner,sun8i-h3-pinctrl", (uintptr_t)&h3_gpio_conf},
236 {"allwinner,sun50i-h5-pinctrl", (uintptr_t)&h3_gpio_conf},
237 {"allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&h3_r_gpio_conf},
238 #endif
239 #ifdef SOC_ALLWINNER_A64
240 {"allwinner,sun50i-a64-pinctrl", (uintptr_t)&a64_gpio_conf},
241 {"allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&a64_r_gpio_conf},
242 #endif
243 #ifdef SOC_ALLWINNER_H6
244 {"allwinner,sun50i-h6-pinctrl", (uintptr_t)&h6_gpio_conf},
245 {"allwinner,sun50i-h6-r-pinctrl", (uintptr_t)&h6_r_gpio_conf},
246 #endif
247 {NULL, 0}
248 };
249
250 struct clk_list {
251 TAILQ_ENTRY(clk_list) next;
252 clk_t clk;
253 };
254
255 struct gpio_irqsrc {
256 struct intr_irqsrc isrc;
257 u_int irq;
258 uint32_t mode;
259 uint32_t pin;
260 uint32_t bank;
261 uint32_t intnum;
262 uint32_t intfunc;
263 uint32_t oldfunc;
264 bool enabled;
265 };
266
267 #define AW_GPIO_MEMRES 0
268 #define AW_GPIO_IRQRES 1
269 #define AW_GPIO_RESSZ 2
270
271 struct aw_gpio_softc {
272 device_t sc_dev;
273 device_t sc_busdev;
274 struct resource * sc_res[AW_GPIO_RESSZ];
275 struct mtx sc_mtx;
276 struct resource * sc_mem_res;
277 struct resource * sc_irq_res;
278 void * sc_intrhand;
279 struct aw_gpio_conf *conf;
280 TAILQ_HEAD(, clk_list) clk_list;
281
282 struct gpio_irqsrc *gpio_pic_irqsrc;
283 int nirqs;
284 };
285
286 static struct resource_spec aw_gpio_res_spec[] = {
287 { SYS_RES_MEMORY, 0, RF_ACTIVE },
288 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
289 { -1, 0, 0 }
290 };
291
292 #define AW_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
293 #define AW_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
294 #define AW_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
295
296 #define AW_GPIO_GP_CFG(_bank, _idx) 0x00 + ((_bank) * 0x24) + ((_idx) << 2)
297 #define AW_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24)
298 #define AW_GPIO_GP_DRV(_bank, _idx) 0x14 + ((_bank) * 0x24) + ((_idx) << 2)
299 #define AW_GPIO_GP_PUL(_bank, _idx) 0x1c + ((_bank) * 0x24) + ((_idx) << 2)
300
301 #define AW_GPIO_GP_INT_BASE(_bank) (0x200 + 0x20 * _bank)
302
303 #define AW_GPIO_GP_INT_CFG(_bank, _pin) (AW_GPIO_GP_INT_BASE(_bank) + (0x4 * ((_pin) / 8)))
304 #define AW_GPIO_GP_INT_CTL(_bank) (AW_GPIO_GP_INT_BASE(_bank) + 0x10)
305 #define AW_GPIO_GP_INT_STA(_bank) (AW_GPIO_GP_INT_BASE(_bank) + 0x14)
306 #define AW_GPIO_GP_INT_DEB(_bank) (AW_GPIO_GP_INT_BASE(_bank) + 0x18)
307
308 #define AW_GPIO_INT_EDGE_POSITIVE 0x0
309 #define AW_GPIO_INT_EDGE_NEGATIVE 0x1
310 #define AW_GPIO_INT_LEVEL_HIGH 0x2
311 #define AW_GPIO_INT_LEVEL_LOW 0x3
312 #define AW_GPIO_INT_EDGE_BOTH 0x4
313
314 static char *aw_gpio_parse_function(phandle_t node);
315 static const char **aw_gpio_parse_pins(phandle_t node, int *pins_nb);
316 static uint32_t aw_gpio_parse_bias(phandle_t node);
317 static int aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive);
318
319 static int aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value);
320 static int aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
321 static int aw_gpio_pin_get_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int *value);
322 static int aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int value);
323
324 static void aw_gpio_intr(void *arg);
325 static void aw_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc);
326 static void aw_gpio_pic_disable_intr_locked(struct aw_gpio_softc *sc, struct intr_irqsrc *isrc);
327 static void aw_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc);
328 static int aw_gpio_register_isrcs(struct aw_gpio_softc *sc);
329
330 #define AW_GPIO_WRITE(_sc, _off, _val) \
331 bus_write_4((_sc)->sc_res[AW_GPIO_MEMRES], _off, _val)
332 #define AW_GPIO_READ(_sc, _off) \
333 bus_read_4((_sc)->sc_res[AW_GPIO_MEMRES], _off)
334
335 static uint32_t
aw_gpio_get_function(struct aw_gpio_softc * sc,uint32_t pin)336 aw_gpio_get_function(struct aw_gpio_softc *sc, uint32_t pin)
337 {
338 uint32_t bank, func, offset;
339
340 /* Must be called with lock held. */
341 AW_GPIO_LOCK_ASSERT(sc);
342
343 if (pin > sc->conf->padconf->npins)
344 return (0);
345 bank = sc->conf->padconf->pins[pin].port;
346 pin = sc->conf->padconf->pins[pin].pin;
347 offset = ((pin & 0x07) << 2);
348
349 func = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(bank, pin >> 3));
350
351 return ((func >> offset) & 0x7);
352 }
353
354 static int
aw_gpio_set_function(struct aw_gpio_softc * sc,uint32_t pin,uint32_t f)355 aw_gpio_set_function(struct aw_gpio_softc *sc, uint32_t pin, uint32_t f)
356 {
357 uint32_t bank, data, offset;
358
359 /* Check if the function exists in the padconf data */
360 if (sc->conf->padconf->pins[pin].functions[f] == NULL)
361 return (EINVAL);
362
363 /* Must be called with lock held. */
364 AW_GPIO_LOCK_ASSERT(sc);
365
366 bank = sc->conf->padconf->pins[pin].port;
367 pin = sc->conf->padconf->pins[pin].pin;
368 offset = ((pin & 0x07) << 2);
369
370 data = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(bank, pin >> 3));
371 data &= ~(7 << offset);
372 data |= (f << offset);
373 AW_GPIO_WRITE(sc, AW_GPIO_GP_CFG(bank, pin >> 3), data);
374
375 return (0);
376 }
377
378 static uint32_t
aw_gpio_get_pud(struct aw_gpio_softc * sc,uint32_t pin)379 aw_gpio_get_pud(struct aw_gpio_softc *sc, uint32_t pin)
380 {
381 uint32_t bank, offset, val;
382
383 /* Must be called with lock held. */
384 AW_GPIO_LOCK_ASSERT(sc);
385
386 bank = sc->conf->padconf->pins[pin].port;
387 pin = sc->conf->padconf->pins[pin].pin;
388 offset = ((pin & 0x0f) << 1);
389
390 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(bank, pin >> 4));
391
392 return ((val >> offset) & AW_GPIO_PUD_MASK);
393 }
394
395 static void
aw_gpio_set_pud(struct aw_gpio_softc * sc,uint32_t pin,uint32_t state)396 aw_gpio_set_pud(struct aw_gpio_softc *sc, uint32_t pin, uint32_t state)
397 {
398 uint32_t bank, offset, val;
399
400 if (aw_gpio_get_pud(sc, pin) == state)
401 return;
402
403 /* Must be called with lock held. */
404 AW_GPIO_LOCK_ASSERT(sc);
405
406 bank = sc->conf->padconf->pins[pin].port;
407 pin = sc->conf->padconf->pins[pin].pin;
408 offset = ((pin & 0x0f) << 1);
409
410 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(bank, pin >> 4));
411 val &= ~(AW_GPIO_PUD_MASK << offset);
412 val |= (state << offset);
413 AW_GPIO_WRITE(sc, AW_GPIO_GP_PUL(bank, pin >> 4), val);
414 }
415
416 static uint32_t
aw_gpio_get_drv(struct aw_gpio_softc * sc,uint32_t pin)417 aw_gpio_get_drv(struct aw_gpio_softc *sc, uint32_t pin)
418 {
419 uint32_t bank, offset, val;
420
421 /* Must be called with lock held. */
422 AW_GPIO_LOCK_ASSERT(sc);
423
424 bank = sc->conf->padconf->pins[pin].port;
425 pin = sc->conf->padconf->pins[pin].pin;
426 offset = ((pin & 0x0f) << 1);
427
428 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(bank, pin >> 4));
429
430 return ((val >> offset) & AW_GPIO_DRV_MASK);
431 }
432
433 static void
aw_gpio_set_drv(struct aw_gpio_softc * sc,uint32_t pin,uint32_t drive)434 aw_gpio_set_drv(struct aw_gpio_softc *sc, uint32_t pin, uint32_t drive)
435 {
436 uint32_t bank, offset, val;
437
438 if (aw_gpio_get_drv(sc, pin) == drive)
439 return;
440
441 /* Must be called with lock held. */
442 AW_GPIO_LOCK_ASSERT(sc);
443
444 bank = sc->conf->padconf->pins[pin].port;
445 pin = sc->conf->padconf->pins[pin].pin;
446 offset = ((pin & 0x0f) << 1);
447
448 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(bank, pin >> 4));
449 val &= ~(AW_GPIO_DRV_MASK << offset);
450 val |= (drive << offset);
451 AW_GPIO_WRITE(sc, AW_GPIO_GP_DRV(bank, pin >> 4), val);
452 }
453
454 static int
aw_gpio_pin_configure(struct aw_gpio_softc * sc,uint32_t pin,uint32_t flags)455 aw_gpio_pin_configure(struct aw_gpio_softc *sc, uint32_t pin, uint32_t flags)
456 {
457 u_int val;
458 int err = 0;
459
460 /* Must be called with lock held. */
461 AW_GPIO_LOCK_ASSERT(sc);
462
463 if (pin > sc->conf->padconf->npins)
464 return (EINVAL);
465
466 /* Manage input/output. */
467 if (flags & GPIO_PIN_INPUT) {
468 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT);
469 } else if ((flags & GPIO_PIN_OUTPUT) &&
470 aw_gpio_get_function(sc, pin) != AW_GPIO_OUTPUT) {
471 if (flags & GPIO_PIN_PRESET_LOW) {
472 aw_gpio_pin_set_locked(sc, pin, 0);
473 } else if (flags & GPIO_PIN_PRESET_HIGH) {
474 aw_gpio_pin_set_locked(sc, pin, 1);
475 } else {
476 /* Read the pin and preset output to current state. */
477 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT);
478 if (err == 0) {
479 aw_gpio_pin_get_locked(sc, pin, &val);
480 aw_gpio_pin_set_locked(sc, pin, val);
481 }
482 }
483 if (err == 0)
484 err = aw_gpio_set_function(sc, pin, AW_GPIO_OUTPUT);
485 }
486
487 if (err)
488 return (err);
489
490 /* Manage Pull-up/pull-down. */
491 if (flags & GPIO_PIN_PULLUP)
492 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLUP);
493 else if (flags & GPIO_PIN_PULLDOWN)
494 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLDOWN);
495 else
496 aw_gpio_set_pud(sc, pin, AW_GPIO_NONE);
497
498 return (0);
499 }
500
501 static device_t
aw_gpio_get_bus(device_t dev)502 aw_gpio_get_bus(device_t dev)
503 {
504 struct aw_gpio_softc *sc;
505
506 sc = device_get_softc(dev);
507
508 return (sc->sc_busdev);
509 }
510
511 static int
aw_gpio_pin_max(device_t dev,int * maxpin)512 aw_gpio_pin_max(device_t dev, int *maxpin)
513 {
514 struct aw_gpio_softc *sc;
515
516 sc = device_get_softc(dev);
517
518 *maxpin = sc->conf->padconf->npins - 1;
519 return (0);
520 }
521
522 static int
aw_gpio_pin_getcaps(device_t dev,uint32_t pin,uint32_t * caps)523 aw_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
524 {
525 struct aw_gpio_softc *sc;
526
527 sc = device_get_softc(dev);
528 if (pin >= sc->conf->padconf->npins)
529 return (EINVAL);
530
531 *caps = AW_GPIO_DEFAULT_CAPS;
532 if (sc->conf->padconf->pins[pin].eint_func != 0)
533 *caps |= AW_GPIO_INTR_CAPS;
534
535 return (0);
536 }
537
538 static int
aw_gpio_pin_getflags(device_t dev,uint32_t pin,uint32_t * flags)539 aw_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
540 {
541 struct aw_gpio_softc *sc;
542 uint32_t func;
543 uint32_t pud;
544
545 sc = device_get_softc(dev);
546 if (pin >= sc->conf->padconf->npins)
547 return (EINVAL);
548
549 AW_GPIO_LOCK(sc);
550 func = aw_gpio_get_function(sc, pin);
551 switch (func) {
552 case AW_GPIO_INPUT:
553 *flags = GPIO_PIN_INPUT;
554 break;
555 case AW_GPIO_OUTPUT:
556 *flags = GPIO_PIN_OUTPUT;
557 break;
558 default:
559 *flags = 0;
560 break;
561 }
562
563 pud = aw_gpio_get_pud(sc, pin);
564 switch (pud) {
565 case AW_GPIO_PULLDOWN:
566 *flags |= GPIO_PIN_PULLDOWN;
567 break;
568 case AW_GPIO_PULLUP:
569 *flags |= GPIO_PIN_PULLUP;
570 break;
571 default:
572 break;
573 }
574
575 AW_GPIO_UNLOCK(sc);
576
577 return (0);
578 }
579
580 static int
aw_gpio_pin_getname(device_t dev,uint32_t pin,char * name)581 aw_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
582 {
583 struct aw_gpio_softc *sc;
584
585 sc = device_get_softc(dev);
586 if (pin >= sc->conf->padconf->npins)
587 return (EINVAL);
588
589 snprintf(name, GPIOMAXNAME - 1, "%s",
590 sc->conf->padconf->pins[pin].name);
591 name[GPIOMAXNAME - 1] = '\0';
592
593 return (0);
594 }
595
596 static int
aw_gpio_pin_setflags(device_t dev,uint32_t pin,uint32_t flags)597 aw_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
598 {
599 struct aw_gpio_softc *sc;
600 int err;
601
602 sc = device_get_softc(dev);
603 if (pin > sc->conf->padconf->npins)
604 return (EINVAL);
605
606 AW_GPIO_LOCK(sc);
607 err = aw_gpio_pin_configure(sc, pin, flags);
608 AW_GPIO_UNLOCK(sc);
609
610 return (err);
611 }
612
613 static int
aw_gpio_pin_set_locked(struct aw_gpio_softc * sc,uint32_t pin,unsigned int value)614 aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin,
615 unsigned int value)
616 {
617 uint32_t bank, data;
618
619 AW_GPIO_LOCK_ASSERT(sc);
620
621 if (pin > sc->conf->padconf->npins)
622 return (EINVAL);
623
624 bank = sc->conf->padconf->pins[pin].port;
625 pin = sc->conf->padconf->pins[pin].pin;
626
627 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
628 if (value)
629 data |= (1 << pin);
630 else
631 data &= ~(1 << pin);
632 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), data);
633
634 return (0);
635 }
636
637 static int
aw_gpio_pin_set(device_t dev,uint32_t pin,unsigned int value)638 aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
639 {
640 struct aw_gpio_softc *sc;
641 int ret;
642
643 sc = device_get_softc(dev);
644
645 AW_GPIO_LOCK(sc);
646 ret = aw_gpio_pin_set_locked(sc, pin, value);
647 AW_GPIO_UNLOCK(sc);
648
649 return (ret);
650 }
651
652 static int
aw_gpio_pin_get_locked(struct aw_gpio_softc * sc,uint32_t pin,unsigned int * val)653 aw_gpio_pin_get_locked(struct aw_gpio_softc *sc,uint32_t pin,
654 unsigned int *val)
655 {
656 uint32_t bank, reg_data;
657 int32_t func;
658 int err;
659
660 AW_GPIO_LOCK_ASSERT(sc);
661
662 if (pin > sc->conf->padconf->npins)
663 return (EINVAL);
664
665 func = aw_gpio_get_function(sc, pin);
666 if (func == sc->conf->padconf->pins[pin].eint_func) { /* "pl_eintX */
667 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT);
668 if (err != 0)
669 return (err);
670 }
671
672 bank = sc->conf->padconf->pins[pin].port;
673 pin = sc->conf->padconf->pins[pin].pin;
674
675 reg_data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
676 *val = (reg_data & (1 << pin)) ? 1 : 0;
677
678 if (func == sc->conf->padconf->pins[pin].eint_func)
679 (void)aw_gpio_set_function(sc, pin, func);
680
681 return (0);
682 }
683
684 static char *
aw_gpio_parse_function(phandle_t node)685 aw_gpio_parse_function(phandle_t node)
686 {
687 char *function;
688
689 if (OF_getprop_alloc(node, "function",
690 (void **)&function) != -1)
691 return (function);
692 if (OF_getprop_alloc(node, "allwinner,function",
693 (void **)&function) != -1)
694 return (function);
695
696 return (NULL);
697 }
698
699 static const char **
aw_gpio_parse_pins(phandle_t node,int * pins_nb)700 aw_gpio_parse_pins(phandle_t node, int *pins_nb)
701 {
702 const char **pinlist;
703
704 *pins_nb = ofw_bus_string_list_to_array(node, "pins", &pinlist);
705 if (*pins_nb > 0)
706 return (pinlist);
707
708 *pins_nb = ofw_bus_string_list_to_array(node, "allwinner,pins",
709 &pinlist);
710 if (*pins_nb > 0)
711 return (pinlist);
712
713 return (NULL);
714 }
715
716 static uint32_t
aw_gpio_parse_bias(phandle_t node)717 aw_gpio_parse_bias(phandle_t node)
718 {
719 uint32_t bias;
720
721 if (OF_getencprop(node, "pull", &bias, sizeof(bias)) != -1)
722 return (bias);
723 if (OF_getencprop(node, "allwinner,pull", &bias, sizeof(bias)) != -1)
724 return (bias);
725 if (OF_hasprop(node, "bias-disable"))
726 return (AW_GPIO_NONE);
727 if (OF_hasprop(node, "bias-pull-up"))
728 return (AW_GPIO_PULLUP);
729 if (OF_hasprop(node, "bias-pull-down"))
730 return (AW_GPIO_PULLDOWN);
731
732 return (AW_GPIO_NONE);
733 }
734
735 static int
aw_gpio_parse_drive_strength(phandle_t node,uint32_t * drive)736 aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive)
737 {
738 uint32_t drive_str;
739
740 if (OF_getencprop(node, "drive", drive, sizeof(*drive)) != -1)
741 return (0);
742 if (OF_getencprop(node, "allwinner,drive", drive, sizeof(*drive)) != -1)
743 return (0);
744 if (OF_getencprop(node, "drive-strength", &drive_str,
745 sizeof(drive_str)) != -1) {
746 *drive = (drive_str / 10) - 1;
747 return (0);
748 }
749
750 return (1);
751 }
752
753 static int
aw_gpio_pin_get(device_t dev,uint32_t pin,unsigned int * val)754 aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
755 {
756 struct aw_gpio_softc *sc;
757 int ret;
758
759 sc = device_get_softc(dev);
760
761 AW_GPIO_LOCK(sc);
762 ret = aw_gpio_pin_get_locked(sc, pin, val);
763 AW_GPIO_UNLOCK(sc);
764
765 return (ret);
766 }
767
768 static int
aw_gpio_pin_toggle(device_t dev,uint32_t pin)769 aw_gpio_pin_toggle(device_t dev, uint32_t pin)
770 {
771 struct aw_gpio_softc *sc;
772 uint32_t bank, data;
773
774 sc = device_get_softc(dev);
775 if (pin > sc->conf->padconf->npins)
776 return (EINVAL);
777
778 bank = sc->conf->padconf->pins[pin].port;
779 pin = sc->conf->padconf->pins[pin].pin;
780
781 AW_GPIO_LOCK(sc);
782 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
783 if (data & (1 << pin))
784 data &= ~(1 << pin);
785 else
786 data |= (1 << pin);
787 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), data);
788 AW_GPIO_UNLOCK(sc);
789
790 return (0);
791 }
792
793 static int
aw_gpio_pin_access_32(device_t dev,uint32_t first_pin,uint32_t clear_pins,uint32_t change_pins,uint32_t * orig_pins)794 aw_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
795 uint32_t change_pins, uint32_t *orig_pins)
796 {
797 struct aw_gpio_softc *sc;
798 uint32_t bank, data, pin;
799
800 sc = device_get_softc(dev);
801 if (first_pin > sc->conf->padconf->npins)
802 return (EINVAL);
803
804 /*
805 * We require that first_pin refers to the first pin in a bank, because
806 * this API is not about convenience, it's for making a set of pins
807 * change simultaneously (required) with reasonably high performance
808 * (desired); we need to do a read-modify-write on a single register.
809 */
810 bank = sc->conf->padconf->pins[first_pin].port;
811 pin = sc->conf->padconf->pins[first_pin].pin;
812 if (pin != 0)
813 return (EINVAL);
814
815 AW_GPIO_LOCK(sc);
816 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
817 if ((clear_pins | change_pins) != 0)
818 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank),
819 (data & ~clear_pins) ^ change_pins);
820 AW_GPIO_UNLOCK(sc);
821
822 if (orig_pins != NULL)
823 *orig_pins = data;
824
825 return (0);
826 }
827
828 static int
aw_gpio_pin_config_32(device_t dev,uint32_t first_pin,uint32_t num_pins,uint32_t * pin_flags)829 aw_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
830 uint32_t *pin_flags)
831 {
832 struct aw_gpio_softc *sc;
833 uint32_t pin;
834 int err;
835
836 sc = device_get_softc(dev);
837 if (first_pin > sc->conf->padconf->npins)
838 return (EINVAL);
839
840 if (sc->conf->padconf->pins[first_pin].pin != 0)
841 return (EINVAL);
842
843 /*
844 * The configuration for a bank of pins is scattered among several
845 * registers; we cannot g'tee to simultaneously change the state of all
846 * the pins in the flags array. So just loop through the array
847 * configuring each pin for now. If there was a strong need, it might
848 * be possible to support some limited simultaneous config, such as
849 * adjacent groups of 8 pins that line up the same as the config regs.
850 */
851 for (err = 0, pin = first_pin; err == 0 && pin < num_pins; ++pin) {
852 if (pin_flags[pin] & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT))
853 err = aw_gpio_pin_configure(sc, pin, pin_flags[pin]);
854 }
855
856 return (err);
857 }
858
859 static int
aw_gpio_map_gpios(device_t bus,phandle_t dev,phandle_t gparent,int gcells,pcell_t * gpios,uint32_t * pin,uint32_t * flags)860 aw_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
861 pcell_t *gpios, uint32_t *pin, uint32_t *flags)
862 {
863 struct aw_gpio_softc *sc;
864 int i;
865
866 sc = device_get_softc(bus);
867
868 /* The GPIO pins are mapped as: <gpio-phandle bank pin flags>. */
869 for (i = 0; i < sc->conf->padconf->npins; i++)
870 if (sc->conf->padconf->pins[i].port == gpios[0] &&
871 sc->conf->padconf->pins[i].pin == gpios[1]) {
872 *pin = i;
873 break;
874 }
875 *flags = gpios[gcells - 1];
876
877 return (0);
878 }
879
880 static int
aw_find_pinnum_by_name(struct aw_gpio_softc * sc,const char * pinname)881 aw_find_pinnum_by_name(struct aw_gpio_softc *sc, const char *pinname)
882 {
883 int i;
884
885 for (i = 0; i < sc->conf->padconf->npins; i++)
886 if (!strcmp(pinname, sc->conf->padconf->pins[i].name))
887 return i;
888
889 return (-1);
890 }
891
892 static int
aw_find_pin_func(struct aw_gpio_softc * sc,int pin,const char * func)893 aw_find_pin_func(struct aw_gpio_softc *sc, int pin, const char *func)
894 {
895 int i;
896
897 for (i = 0; i < AW_MAX_FUNC_BY_PIN; i++)
898 if (sc->conf->padconf->pins[pin].functions[i] &&
899 !strcmp(func, sc->conf->padconf->pins[pin].functions[i]))
900 return (i);
901
902 return (-1);
903 }
904
905 static int
aw_fdt_configure_pins(device_t dev,phandle_t cfgxref)906 aw_fdt_configure_pins(device_t dev, phandle_t cfgxref)
907 {
908 struct aw_gpio_softc *sc;
909 phandle_t node;
910 const char **pinlist = NULL;
911 char *pin_function = NULL;
912 uint32_t pin_drive, pin_pull;
913 int pins_nb, pin_num, pin_func, i, ret;
914 bool set_drive;
915
916 sc = device_get_softc(dev);
917 node = OF_node_from_xref(cfgxref);
918 ret = 0;
919 set_drive = false;
920
921 /* Getting all prop for configuring pins */
922 pinlist = aw_gpio_parse_pins(node, &pins_nb);
923 if (pinlist == NULL)
924 return (ENOENT);
925
926 pin_function = aw_gpio_parse_function(node);
927 if (pin_function == NULL) {
928 ret = ENOENT;
929 goto out;
930 }
931
932 if (aw_gpio_parse_drive_strength(node, &pin_drive) == 0)
933 set_drive = true;
934
935 pin_pull = aw_gpio_parse_bias(node);
936
937 /* Configure each pin to the correct function, drive and pull */
938 for (i = 0; i < pins_nb; i++) {
939 pin_num = aw_find_pinnum_by_name(sc, pinlist[i]);
940 if (pin_num == -1) {
941 ret = ENOENT;
942 goto out;
943 }
944 pin_func = aw_find_pin_func(sc, pin_num, pin_function);
945 if (pin_func == -1) {
946 ret = ENOENT;
947 goto out;
948 }
949
950 AW_GPIO_LOCK(sc);
951
952 if (aw_gpio_get_function(sc, pin_num) != pin_func)
953 aw_gpio_set_function(sc, pin_num, pin_func);
954 if (set_drive)
955 aw_gpio_set_drv(sc, pin_num, pin_drive);
956 if (pin_pull != AW_GPIO_NONE)
957 aw_gpio_set_pud(sc, pin_num, pin_pull);
958
959 AW_GPIO_UNLOCK(sc);
960 }
961
962 out:
963 OF_prop_free(pinlist);
964 OF_prop_free(pin_function);
965 return (ret);
966 }
967
968 static void
aw_gpio_enable_bank_supply(void * arg)969 aw_gpio_enable_bank_supply(void *arg)
970 {
971 struct aw_gpio_softc *sc = arg;
972 regulator_t vcc_supply;
973 char bank_reg_name[16];
974 int i, nbanks;
975
976 nbanks = strlen(sc->conf->banks);
977 for (i = 0; i < nbanks; i++) {
978 snprintf(bank_reg_name, sizeof(bank_reg_name), "vcc-p%c-supply",
979 sc->conf->banks[i]);
980
981 if (regulator_get_by_ofw_property(sc->sc_dev, 0, bank_reg_name, &vcc_supply) == 0) {
982 if (bootverbose)
983 device_printf(sc->sc_dev,
984 "Enabling regulator for gpio bank %c\n",
985 sc->conf->banks[i]);
986 if (regulator_enable(vcc_supply) != 0) {
987 device_printf(sc->sc_dev,
988 "Cannot enable regulator for bank %c\n",
989 sc->conf->banks[i]);
990 }
991 }
992 }
993 }
994
995 static int
aw_gpio_probe(device_t dev)996 aw_gpio_probe(device_t dev)
997 {
998
999 if (!ofw_bus_status_okay(dev))
1000 return (ENXIO);
1001
1002 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
1003 return (ENXIO);
1004
1005 device_set_desc(dev, "Allwinner GPIO/Pinmux controller");
1006 return (BUS_PROBE_DEFAULT);
1007 }
1008
1009 static int
aw_gpio_attach(device_t dev)1010 aw_gpio_attach(device_t dev)
1011 {
1012 int error;
1013 phandle_t gpio;
1014 struct aw_gpio_softc *sc;
1015 struct clk_list *clkp, *clkp_tmp;
1016 clk_t clk;
1017 hwreset_t rst = NULL;
1018 int off, err, clkret;
1019
1020 sc = device_get_softc(dev);
1021 sc->sc_dev = dev;
1022
1023 mtx_init(&sc->sc_mtx, "aw gpio", "gpio", MTX_SPIN);
1024
1025 if (bus_alloc_resources(dev, aw_gpio_res_spec, sc->sc_res) != 0) {
1026 device_printf(dev, "cannot allocate device resources\n");
1027 return (ENXIO);
1028 }
1029
1030 if (bus_setup_intr(dev, sc->sc_res[AW_GPIO_IRQRES],
1031 INTR_TYPE_CLK | INTR_MPSAFE, NULL, aw_gpio_intr, sc,
1032 &sc->sc_intrhand)) {
1033 device_printf(dev, "cannot setup interrupt handler\n");
1034 goto fail;
1035 }
1036
1037 /* Find our node. */
1038 gpio = ofw_bus_get_node(sc->sc_dev);
1039 if (!OF_hasprop(gpio, "gpio-controller"))
1040 /* Node is not a GPIO controller. */
1041 goto fail;
1042
1043 /* Use the right pin data for the current SoC */
1044 sc->conf = (struct aw_gpio_conf *)ofw_bus_search_compatible(dev,
1045 compat_data)->ocd_data;
1046
1047 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) {
1048 error = hwreset_deassert(rst);
1049 if (error != 0) {
1050 device_printf(dev, "cannot de-assert reset\n");
1051 goto fail;
1052 }
1053 }
1054
1055 TAILQ_INIT(&sc->clk_list);
1056 for (off = 0, clkret = 0; clkret == 0; off++) {
1057 clkret = clk_get_by_ofw_index(dev, 0, off, &clk);
1058 if (clkret != 0)
1059 break;
1060 err = clk_enable(clk);
1061 if (err != 0) {
1062 device_printf(dev, "Could not enable clock %s\n",
1063 clk_get_name(clk));
1064 goto fail;
1065 }
1066 clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO);
1067 clkp->clk = clk;
1068 TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next);
1069 }
1070 if (clkret != 0 && clkret != ENOENT) {
1071 device_printf(dev, "Could not find clock at offset %d (%d)\n",
1072 off, clkret);
1073 goto fail;
1074 }
1075
1076 aw_gpio_register_isrcs(sc);
1077 intr_pic_register(dev, OF_xref_from_node(ofw_bus_get_node(dev)));
1078
1079 sc->sc_busdev = gpiobus_attach_bus(dev);
1080 if (sc->sc_busdev == NULL)
1081 goto fail;
1082
1083 /*
1084 * Register as a pinctrl device
1085 */
1086 fdt_pinctrl_register(dev, "pins");
1087 fdt_pinctrl_configure_tree(dev);
1088 fdt_pinctrl_register(dev, "allwinner,pins");
1089 fdt_pinctrl_configure_tree(dev);
1090
1091 config_intrhook_oneshot(aw_gpio_enable_bank_supply, sc);
1092
1093 return (0);
1094
1095 fail:
1096 if (sc->sc_irq_res)
1097 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
1098 if (sc->sc_mem_res)
1099 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
1100 mtx_destroy(&sc->sc_mtx);
1101
1102 /* Disable clock */
1103 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) {
1104 err = clk_disable(clkp->clk);
1105 if (err != 0)
1106 device_printf(dev, "Could not disable clock %s\n",
1107 clk_get_name(clkp->clk));
1108 err = clk_release(clkp->clk);
1109 if (err != 0)
1110 device_printf(dev, "Could not release clock %s\n",
1111 clk_get_name(clkp->clk));
1112 TAILQ_REMOVE(&sc->clk_list, clkp, next);
1113 free(clkp, M_DEVBUF);
1114 }
1115
1116 /* Assert resets */
1117 if (rst) {
1118 hwreset_assert(rst);
1119 hwreset_release(rst);
1120 }
1121
1122 return (ENXIO);
1123 }
1124
1125 static int
aw_gpio_detach(device_t dev)1126 aw_gpio_detach(device_t dev)
1127 {
1128
1129 return (EBUSY);
1130 }
1131
1132 static void
aw_gpio_intr(void * arg)1133 aw_gpio_intr(void *arg)
1134 {
1135 struct aw_gpio_softc *sc;
1136 struct intr_irqsrc *isrc;
1137 uint32_t reg;
1138 int irq;
1139
1140 sc = (struct aw_gpio_softc *)arg;
1141
1142 AW_GPIO_LOCK(sc);
1143 for (irq = 0; irq < sc->nirqs; irq++) {
1144 if (!sc->gpio_pic_irqsrc[irq].enabled)
1145 continue;
1146
1147 reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_STA(sc->gpio_pic_irqsrc[irq].bank));
1148 if (!(reg & (1 << sc->gpio_pic_irqsrc[irq].intnum)))
1149 continue;
1150
1151 isrc = &sc->gpio_pic_irqsrc[irq].isrc;
1152 if (intr_isrc_dispatch(isrc, curthread->td_intr_frame) != 0) {
1153 aw_gpio_pic_disable_intr_locked(sc, isrc);
1154 aw_gpio_pic_post_filter(sc->sc_dev, isrc);
1155 device_printf(sc->sc_dev, "Stray irq %u disabled\n", irq);
1156 }
1157 }
1158 AW_GPIO_UNLOCK(sc);
1159 }
1160
1161 /*
1162 * Interrupts support
1163 */
1164
1165 static int
aw_gpio_register_isrcs(struct aw_gpio_softc * sc)1166 aw_gpio_register_isrcs(struct aw_gpio_softc *sc)
1167 {
1168 const char *name;
1169 int nirqs;
1170 int pin;
1171 int err;
1172
1173 name = device_get_nameunit(sc->sc_dev);
1174
1175 for (nirqs = 0, pin = 0; pin < sc->conf->padconf->npins; pin++) {
1176 if (sc->conf->padconf->pins[pin].eint_func == 0)
1177 continue;
1178
1179 nirqs++;
1180 }
1181
1182 sc->gpio_pic_irqsrc = malloc(sizeof(*sc->gpio_pic_irqsrc) * nirqs,
1183 M_DEVBUF, M_WAITOK | M_ZERO);
1184 for (nirqs = 0, pin = 0; pin < sc->conf->padconf->npins; pin++) {
1185 if (sc->conf->padconf->pins[pin].eint_func == 0)
1186 continue;
1187
1188 sc->gpio_pic_irqsrc[nirqs].pin = pin;
1189 sc->gpio_pic_irqsrc[nirqs].bank = sc->conf->padconf->pins[pin].eint_bank;
1190 sc->gpio_pic_irqsrc[nirqs].intnum = sc->conf->padconf->pins[pin].eint_num;
1191 sc->gpio_pic_irqsrc[nirqs].intfunc = sc->conf->padconf->pins[pin].eint_func;
1192 sc->gpio_pic_irqsrc[nirqs].irq = nirqs;
1193 sc->gpio_pic_irqsrc[nirqs].mode = GPIO_INTR_CONFORM;
1194
1195 err = intr_isrc_register(&sc->gpio_pic_irqsrc[nirqs].isrc,
1196 sc->sc_dev, 0, "%s,%s", name,
1197 sc->conf->padconf->pins[pin].functions[sc->conf->padconf->pins[pin].eint_func]);
1198 if (err) {
1199 device_printf(sc->sc_dev, "intr_isrs_register failed for irq %d\n", nirqs);
1200 }
1201
1202 nirqs++;
1203 }
1204
1205 sc->nirqs = nirqs;
1206
1207 return (0);
1208 }
1209
1210 static void
aw_gpio_pic_disable_intr_locked(struct aw_gpio_softc * sc,struct intr_irqsrc * isrc)1211 aw_gpio_pic_disable_intr_locked(struct aw_gpio_softc *sc, struct intr_irqsrc *isrc)
1212 {
1213 u_int irq;
1214 uint32_t reg;
1215
1216 AW_GPIO_LOCK_ASSERT(sc);
1217 irq = ((struct gpio_irqsrc *)isrc)->irq;
1218 reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank));
1219 reg &= ~(1 << sc->gpio_pic_irqsrc[irq].intnum);
1220 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank), reg);
1221
1222 sc->gpio_pic_irqsrc[irq].enabled = false;
1223 }
1224
1225 static void
aw_gpio_pic_disable_intr(device_t dev,struct intr_irqsrc * isrc)1226 aw_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
1227 {
1228 struct aw_gpio_softc *sc;
1229
1230 sc = device_get_softc(dev);
1231
1232 AW_GPIO_LOCK(sc);
1233 aw_gpio_pic_disable_intr_locked(sc, isrc);
1234 AW_GPIO_UNLOCK(sc);
1235 }
1236
1237 static void
aw_gpio_pic_enable_intr(device_t dev,struct intr_irqsrc * isrc)1238 aw_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
1239 {
1240 struct aw_gpio_softc *sc;
1241 u_int irq;
1242 uint32_t reg;
1243
1244 sc = device_get_softc(dev);
1245 irq = ((struct gpio_irqsrc *)isrc)->irq;
1246 AW_GPIO_LOCK(sc);
1247 reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank));
1248 reg |= 1 << sc->gpio_pic_irqsrc[irq].intnum;
1249 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank), reg);
1250 AW_GPIO_UNLOCK(sc);
1251
1252 sc->gpio_pic_irqsrc[irq].enabled = true;
1253 }
1254
1255 static int
aw_gpio_pic_map_gpio(struct aw_gpio_softc * sc,struct intr_map_data_gpio * dag,u_int * irqp,u_int * mode)1256 aw_gpio_pic_map_gpio(struct aw_gpio_softc *sc, struct intr_map_data_gpio *dag,
1257 u_int *irqp, u_int *mode)
1258 {
1259 u_int irq;
1260 int pin;
1261
1262 irq = dag->gpio_pin_num;
1263
1264 for (pin = 0; pin < sc->nirqs; pin++)
1265 if (sc->gpio_pic_irqsrc[pin].pin == irq)
1266 break;
1267 if (pin == sc->nirqs) {
1268 device_printf(sc->sc_dev, "Invalid interrupt number %u\n", irq);
1269 return (EINVAL);
1270 }
1271
1272 switch (dag->gpio_intr_mode) {
1273 case GPIO_INTR_LEVEL_LOW:
1274 case GPIO_INTR_LEVEL_HIGH:
1275 case GPIO_INTR_EDGE_RISING:
1276 case GPIO_INTR_EDGE_FALLING:
1277 case GPIO_INTR_EDGE_BOTH:
1278 break;
1279 default:
1280 device_printf(sc->sc_dev, "Unsupported interrupt mode 0x%8x\n",
1281 dag->gpio_intr_mode);
1282 return (EINVAL);
1283 }
1284
1285 *irqp = pin;
1286 if (mode != NULL)
1287 *mode = dag->gpio_intr_mode;
1288
1289 return (0);
1290 }
1291
1292 static int
aw_gpio_pic_map_intr(device_t dev,struct intr_map_data * data,struct intr_irqsrc ** isrcp)1293 aw_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
1294 struct intr_irqsrc **isrcp)
1295 {
1296 struct aw_gpio_softc *sc;
1297 u_int irq;
1298 int err;
1299
1300 sc = device_get_softc(dev);
1301 switch (data->type) {
1302 case INTR_MAP_DATA_GPIO:
1303 err = aw_gpio_pic_map_gpio(sc,
1304 (struct intr_map_data_gpio *)data,
1305 &irq, NULL);
1306 break;
1307 default:
1308 return (ENOTSUP);
1309 };
1310
1311 if (err == 0)
1312 *isrcp = &sc->gpio_pic_irqsrc[irq].isrc;
1313 return (0);
1314 }
1315
1316 static int
aw_gpio_pic_setup_intr(device_t dev,struct intr_irqsrc * isrc,struct resource * res,struct intr_map_data * data)1317 aw_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
1318 struct resource *res, struct intr_map_data *data)
1319 {
1320 struct aw_gpio_softc *sc;
1321 uint32_t irqcfg;
1322 uint32_t pinidx, reg;
1323 u_int irq, mode;
1324 int err;
1325
1326 sc = device_get_softc(dev);
1327
1328 err = 0;
1329 switch (data->type) {
1330 case INTR_MAP_DATA_GPIO:
1331 err = aw_gpio_pic_map_gpio(sc,
1332 (struct intr_map_data_gpio *)data,
1333 &irq, &mode);
1334 if (err != 0)
1335 return (err);
1336 break;
1337 default:
1338 return (ENOTSUP);
1339 };
1340
1341 pinidx = (sc->gpio_pic_irqsrc[irq].intnum % 8) * 4;
1342
1343 AW_GPIO_LOCK(sc);
1344 switch (mode) {
1345 case GPIO_INTR_LEVEL_LOW:
1346 irqcfg = AW_GPIO_INT_LEVEL_LOW << pinidx;
1347 break;
1348 case GPIO_INTR_LEVEL_HIGH:
1349 irqcfg = AW_GPIO_INT_LEVEL_HIGH << pinidx;
1350 break;
1351 case GPIO_INTR_EDGE_RISING:
1352 irqcfg = AW_GPIO_INT_EDGE_POSITIVE << pinidx;
1353 break;
1354 case GPIO_INTR_EDGE_FALLING:
1355 irqcfg = AW_GPIO_INT_EDGE_NEGATIVE << pinidx;
1356 break;
1357 case GPIO_INTR_EDGE_BOTH:
1358 irqcfg = AW_GPIO_INT_EDGE_BOTH << pinidx;
1359 break;
1360 }
1361
1362 /* Switch the pin to interrupt mode */
1363 sc->gpio_pic_irqsrc[irq].oldfunc = aw_gpio_get_function(sc,
1364 sc->gpio_pic_irqsrc[irq].pin);
1365 aw_gpio_set_function(sc, sc->gpio_pic_irqsrc[irq].pin,
1366 sc->gpio_pic_irqsrc[irq].intfunc);
1367
1368 /* Write interrupt mode */
1369 reg = AW_GPIO_READ(sc,
1370 AW_GPIO_GP_INT_CFG(sc->gpio_pic_irqsrc[irq].bank,
1371 sc->gpio_pic_irqsrc[irq].intnum));
1372 reg &= ~(0xF << pinidx);
1373 reg |= irqcfg;
1374 AW_GPIO_WRITE(sc,
1375 AW_GPIO_GP_INT_CFG(sc->gpio_pic_irqsrc[irq].bank,
1376 sc->gpio_pic_irqsrc[irq].intnum),
1377 reg);
1378
1379 AW_GPIO_UNLOCK(sc);
1380
1381 return (0);
1382 }
1383
1384 static int
aw_gpio_pic_teardown_intr(device_t dev,struct intr_irqsrc * isrc,struct resource * res,struct intr_map_data * data)1385 aw_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
1386 struct resource *res, struct intr_map_data *data)
1387 {
1388 struct aw_gpio_softc *sc;
1389 struct gpio_irqsrc *gi;
1390
1391 sc = device_get_softc(dev);
1392 gi = (struct gpio_irqsrc *)isrc;
1393
1394 /* Switch back the pin to it's original function */
1395 AW_GPIO_LOCK(sc);
1396 aw_gpio_set_function(sc, gi->pin, gi->oldfunc);
1397 AW_GPIO_UNLOCK(sc);
1398
1399 return (0);
1400 }
1401
1402 static void
aw_gpio_pic_post_filter(device_t dev,struct intr_irqsrc * isrc)1403 aw_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
1404 {
1405 struct aw_gpio_softc *sc;
1406 struct gpio_irqsrc *gi;
1407
1408 sc = device_get_softc(dev);
1409 gi = (struct gpio_irqsrc *)isrc;
1410
1411 arm_irq_memory_barrier(0);
1412 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_STA(gi->bank), 1 << gi->intnum);
1413 }
1414
1415 static void
aw_gpio_pic_post_ithread(device_t dev,struct intr_irqsrc * isrc)1416 aw_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
1417 {
1418 struct aw_gpio_softc *sc;
1419 struct gpio_irqsrc *gi;
1420
1421 sc = device_get_softc(dev);
1422 gi = (struct gpio_irqsrc *)isrc;
1423
1424 arm_irq_memory_barrier(0);
1425 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_STA(gi->bank), 1 << gi->intnum);
1426 aw_gpio_pic_enable_intr(dev, isrc);
1427 }
1428
1429 static void
aw_gpio_pic_pre_ithread(device_t dev,struct intr_irqsrc * isrc)1430 aw_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
1431 {
1432 struct aw_gpio_softc *sc;
1433
1434 sc = device_get_softc(dev);
1435 aw_gpio_pic_disable_intr_locked(sc, isrc);
1436 }
1437
1438 /*
1439 * OFWBUS Interface
1440 */
1441 static phandle_t
aw_gpio_get_node(device_t dev,device_t bus)1442 aw_gpio_get_node(device_t dev, device_t bus)
1443 {
1444
1445 /* We only have one child, the GPIO bus, which needs our own node. */
1446 return (ofw_bus_get_node(dev));
1447 }
1448
1449 static device_method_t aw_gpio_methods[] = {
1450 /* Device interface */
1451 DEVMETHOD(device_probe, aw_gpio_probe),
1452 DEVMETHOD(device_attach, aw_gpio_attach),
1453 DEVMETHOD(device_detach, aw_gpio_detach),
1454
1455 /* Interrupt controller interface */
1456 DEVMETHOD(pic_disable_intr, aw_gpio_pic_disable_intr),
1457 DEVMETHOD(pic_enable_intr, aw_gpio_pic_enable_intr),
1458 DEVMETHOD(pic_map_intr, aw_gpio_pic_map_intr),
1459 DEVMETHOD(pic_setup_intr, aw_gpio_pic_setup_intr),
1460 DEVMETHOD(pic_teardown_intr, aw_gpio_pic_teardown_intr),
1461 DEVMETHOD(pic_post_filter, aw_gpio_pic_post_filter),
1462 DEVMETHOD(pic_post_ithread, aw_gpio_pic_post_ithread),
1463 DEVMETHOD(pic_pre_ithread, aw_gpio_pic_pre_ithread),
1464
1465 /* GPIO protocol */
1466 DEVMETHOD(gpio_get_bus, aw_gpio_get_bus),
1467 DEVMETHOD(gpio_pin_max, aw_gpio_pin_max),
1468 DEVMETHOD(gpio_pin_getname, aw_gpio_pin_getname),
1469 DEVMETHOD(gpio_pin_getflags, aw_gpio_pin_getflags),
1470 DEVMETHOD(gpio_pin_getcaps, aw_gpio_pin_getcaps),
1471 DEVMETHOD(gpio_pin_setflags, aw_gpio_pin_setflags),
1472 DEVMETHOD(gpio_pin_get, aw_gpio_pin_get),
1473 DEVMETHOD(gpio_pin_set, aw_gpio_pin_set),
1474 DEVMETHOD(gpio_pin_toggle, aw_gpio_pin_toggle),
1475 DEVMETHOD(gpio_pin_access_32, aw_gpio_pin_access_32),
1476 DEVMETHOD(gpio_pin_config_32, aw_gpio_pin_config_32),
1477 DEVMETHOD(gpio_map_gpios, aw_gpio_map_gpios),
1478
1479 /* ofw_bus interface */
1480 DEVMETHOD(ofw_bus_get_node, aw_gpio_get_node),
1481
1482 /* fdt_pinctrl interface */
1483 DEVMETHOD(fdt_pinctrl_configure,aw_fdt_configure_pins),
1484
1485 DEVMETHOD_END
1486 };
1487
1488 static driver_t aw_gpio_driver = {
1489 "gpio",
1490 aw_gpio_methods,
1491 sizeof(struct aw_gpio_softc),
1492 };
1493
1494 EARLY_DRIVER_MODULE(aw_gpio, simplebus, aw_gpio_driver, 0, 0,
1495 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
1496