1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/soc/tegra/pmc.c 4 * 5 * Copyright (c) 2010 Google, Inc 6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: 9 * Colin Cross <ccross@google.com> 10 */ 11 12 #define pr_fmt(fmt) "tegra-pmc: " fmt 13 14 #include <linux/arm-smccc.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/clkdev.h> 18 #include <linux/clk/clk-conf.h> 19 #include <linux/clk/tegra.h> 20 #include <linux/debugfs.h> 21 #include <linux/delay.h> 22 #include <linux/device.h> 23 #include <linux/err.h> 24 #include <linux/export.h> 25 #include <linux/init.h> 26 #include <linux/interrupt.h> 27 #include <linux/io.h> 28 #include <linux/iopoll.h> 29 #include <linux/irqdomain.h> 30 #include <linux/irq.h> 31 #include <linux/irq_work.h> 32 #include <linux/kernel.h> 33 #include <linux/of_address.h> 34 #include <linux/of_clk.h> 35 #include <linux/of.h> 36 #include <linux/of_irq.h> 37 #include <linux/of_platform.h> 38 #include <linux/pinctrl/pinconf-generic.h> 39 #include <linux/pinctrl/pinconf.h> 40 #include <linux/pinctrl/pinctrl.h> 41 #include <linux/platform_device.h> 42 #include <linux/pm_domain.h> 43 #include <linux/pm_opp.h> 44 #include <linux/power_supply.h> 45 #include <linux/reboot.h> 46 #include <linux/regmap.h> 47 #include <linux/reset.h> 48 #include <linux/seq_file.h> 49 #include <linux/slab.h> 50 #include <linux/spinlock.h> 51 #include <linux/string_choices.h> 52 #include <linux/syscore_ops.h> 53 54 #include <soc/tegra/common.h> 55 #include <soc/tegra/fuse.h> 56 #include <soc/tegra/pmc.h> 57 58 #include <dt-bindings/interrupt-controller/arm-gic.h> 59 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 60 #include <dt-bindings/gpio/tegra186-gpio.h> 61 #include <dt-bindings/gpio/tegra194-gpio.h> 62 #include <dt-bindings/gpio/tegra234-gpio.h> 63 #include <dt-bindings/gpio/nvidia,tegra264-gpio.h> 64 #include <dt-bindings/soc/tegra-pmc.h> 65 66 #define PMC_CNTRL 0x0 67 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 68 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 69 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 70 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 71 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 72 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 73 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8) 74 #define PMC_CNTRL_BLINK_EN 7 75 #define PMC_CNTRL_MAIN_RST BIT(4) 76 77 #define PMC_WAKE_MASK 0x0c 78 #define PMC_WAKE_LEVEL 0x10 79 #define PMC_WAKE_STATUS 0x14 80 #define PMC_SW_WAKE_STATUS 0x18 81 #define PMC_DPD_PADS_ORIDE 0x1c 82 #define PMC_DPD_PADS_ORIDE_BLINK 20 83 84 #define DPD_SAMPLE 0x020 85 #define DPD_SAMPLE_ENABLE BIT(0) 86 #define DPD_SAMPLE_DISABLE (0 << 0) 87 88 #define PWRGATE_TOGGLE 0x30 89 #define PWRGATE_TOGGLE_START BIT(8) 90 91 #define REMOVE_CLAMPING 0x34 92 93 #define PWRGATE_STATUS 0x38 94 95 #define PMC_BLINK_TIMER 0x40 96 #define PMC_IMPL_E_33V_PWR 0x40 97 98 #define PMC_PWR_DET 0x48 99 100 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 101 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 102 #define PMC_SCRATCH0_MODE_RCM BIT(1) 103 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 104 PMC_SCRATCH0_MODE_BOOTLOADER | \ 105 PMC_SCRATCH0_MODE_RCM) 106 107 #define PMC_CPUPWRGOOD_TIMER 0xc8 108 #define PMC_CPUPWROFF_TIMER 0xcc 109 #define PMC_COREPWRGOOD_TIMER 0x3c 110 #define PMC_COREPWROFF_TIMER 0xe0 111 112 #define PMC_PWR_DET_VALUE 0xe4 113 114 #define PMC_USB_DEBOUNCE_DEL 0xec 115 #define PMC_USB_AO 0xf0 116 117 #define PMC_SCRATCH37 0x130 118 #define PMC_SCRATCH41 0x140 119 120 #define PMC_WAKE2_MASK 0x160 121 #define PMC_WAKE2_LEVEL 0x164 122 #define PMC_WAKE2_STATUS 0x168 123 #define PMC_SW_WAKE2_STATUS 0x16c 124 125 #define PMC_CLK_OUT_CNTRL 0x1a8 126 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0) 127 #define PMC_SENSOR_CTRL 0x1b0 128 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 129 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 130 131 #define PMC_RST_STATUS_POR 0 132 #define PMC_RST_STATUS_WATCHDOG 1 133 #define PMC_RST_STATUS_SENSOR 2 134 #define PMC_RST_STATUS_SW_MAIN 3 135 #define PMC_RST_STATUS_LP0 4 136 #define PMC_RST_STATUS_AOTAG 5 137 138 #define IO_DPD_REQ 0x1b8 139 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 140 #define IO_DPD_REQ_CODE_OFF (1U << 30) 141 #define IO_DPD_REQ_CODE_ON (2U << 30) 142 #define IO_DPD_REQ_CODE_MASK (3U << 30) 143 144 #define IO_DPD_STATUS 0x1bc 145 #define IO_DPD2_REQ 0x1c0 146 #define IO_DPD2_STATUS 0x1c4 147 #define SEL_DPD_TIM 0x1c8 148 149 #define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec 150 #define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0 151 152 #define PMC_UTMIP_TERM_PAD_CFG 0x1f8 153 #define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc 154 #define PMC_UTMIP_UHSIC_FAKE 0x218 155 156 #define PMC_SCRATCH54 0x258 157 #define PMC_SCRATCH54_DATA_SHIFT 8 158 #define PMC_SCRATCH54_ADDR_SHIFT 0 159 160 #define PMC_SCRATCH55 0x25c 161 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 162 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 163 #define PMC_SCRATCH55_PINMUX_SHIFT 24 164 #define PMC_SCRATCH55_16BITOP BIT(15) 165 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 166 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 167 168 #define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c 169 170 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270 171 #define PMC_UTMIP_MASTER_CONFIG 0x274 172 #define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c 173 #define PMC_UTMIP_MASTER2_CONFIG 0x29c 174 175 #define GPU_RG_CNTRL 0x2d4 176 177 #define PMC_UTMIP_PAD_CFG0 0x4c0 178 #define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0 179 #define PMC_UTMIP_SLEEPWALK_P3 0x4e0 180 /* Tegra186 and later */ 181 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) 182 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) 183 #define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN (1 << 1) 184 #define WAKE_AOWAKE_MASK_W(_pmc, x) \ 185 ((_pmc)->soc->regs->aowake_mask_w + ((x) << 2)) 186 #define WAKE_AOWAKE_STATUS_W(_pmc, x) \ 187 ((_pmc)->soc->regs->aowake_status_w + ((x) << 2)) 188 #define WAKE_AOWAKE_STATUS_R(_pmc, x) \ 189 ((_pmc)->soc->regs->aowake_status_r + ((x) << 2)) 190 #define WAKE_AOWAKE_TIER2_ROUTING(_pmc, x) \ 191 ((_pmc)->soc->regs->aowake_tier2_routing + ((x) << 2)) 192 #define WAKE_AOWAKE_SW_STATUS(_pmc, x) \ 193 ((_pmc)->soc->regs->aowake_sw_status + ((x) << 2)) 194 195 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 196 197 #define SW_WAKE_ID 83 /* wake83 */ 198 199 /* for secure PMC */ 200 #define TEGRA_SMC_PMC 0xc2fffe00 201 #define TEGRA_SMC_PMC_READ 0xaa 202 #define TEGRA_SMC_PMC_WRITE 0xbb 203 204 /* Tegra264 and later */ 205 #define PMC_IMPL_SDMMC1_HV_PADCTL_0 0x41004 206 207 struct pmc_clk { 208 struct clk_hw hw; 209 struct tegra_pmc *pmc; 210 unsigned long offs; 211 u32 mux_shift; 212 u32 force_en_shift; 213 }; 214 215 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw) 216 217 struct pmc_clk_gate { 218 struct clk_hw hw; 219 struct tegra_pmc *pmc; 220 unsigned long offs; 221 u32 shift; 222 }; 223 224 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw) 225 226 struct pmc_clk_init_data { 227 char *name; 228 const char *const *parents; 229 int num_parents; 230 int clk_id; 231 u8 mux_shift; 232 u8 force_en_shift; 233 }; 234 235 static const char * const clk_out1_parents[] = { "osc", "osc_div2", 236 "osc_div4", "extern1", 237 }; 238 239 static const char * const clk_out2_parents[] = { "osc", "osc_div2", 240 "osc_div4", "extern2", 241 }; 242 243 static const char * const clk_out3_parents[] = { "osc", "osc_div2", 244 "osc_div4", "extern3", 245 }; 246 247 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = { 248 { 249 .name = "pmc_clk_out_1", 250 .parents = clk_out1_parents, 251 .num_parents = ARRAY_SIZE(clk_out1_parents), 252 .clk_id = TEGRA_PMC_CLK_OUT_1, 253 .mux_shift = 6, 254 .force_en_shift = 2, 255 }, 256 { 257 .name = "pmc_clk_out_2", 258 .parents = clk_out2_parents, 259 .num_parents = ARRAY_SIZE(clk_out2_parents), 260 .clk_id = TEGRA_PMC_CLK_OUT_2, 261 .mux_shift = 14, 262 .force_en_shift = 10, 263 }, 264 { 265 .name = "pmc_clk_out_3", 266 .parents = clk_out3_parents, 267 .num_parents = ARRAY_SIZE(clk_out3_parents), 268 .clk_id = TEGRA_PMC_CLK_OUT_3, 269 .mux_shift = 22, 270 .force_en_shift = 18, 271 }, 272 }; 273 274 struct tegra_pmc_core_pd { 275 struct generic_pm_domain genpd; 276 struct tegra_pmc *pmc; 277 }; 278 279 static inline struct tegra_pmc_core_pd * 280 to_core_pd(struct generic_pm_domain *genpd) 281 { 282 return container_of(genpd, struct tegra_pmc_core_pd, genpd); 283 } 284 285 struct tegra_powergate { 286 struct generic_pm_domain genpd; 287 struct tegra_pmc *pmc; 288 unsigned int id; 289 struct clk **clks; 290 unsigned int num_clks; 291 unsigned long *clk_rates; 292 struct reset_control *reset; 293 }; 294 295 struct tegra_io_pad_soc { 296 enum tegra_io_pad id; 297 unsigned int dpd; 298 unsigned int request; 299 unsigned int status; 300 const char *name; 301 }; 302 303 struct tegra_io_pad_vctrl { 304 enum tegra_io_pad id; 305 unsigned int offset; 306 unsigned int ena_3v3; 307 unsigned int ena_1v8; 308 }; 309 310 struct tegra_pmc_regs { 311 unsigned int scratch0; 312 unsigned int rst_status; 313 unsigned int rst_source_shift; 314 unsigned int rst_source_mask; 315 unsigned int rst_level_shift; 316 unsigned int rst_level_mask; 317 unsigned int aowake_mask_w; 318 unsigned int aowake_status_w; 319 unsigned int aowake_status_r; 320 unsigned int aowake_tier2_routing; 321 unsigned int aowake_sw_status_w; 322 unsigned int aowake_sw_status; 323 unsigned int aowake_latch_sw; 324 unsigned int aowake_ctrl; 325 }; 326 327 struct tegra_wake_event { 328 const char *name; 329 unsigned int id; 330 unsigned int irq; 331 struct { 332 unsigned int instance; 333 unsigned int pin; 334 } gpio; 335 }; 336 337 #define TEGRA_WAKE_SIMPLE(_name, _id) \ 338 { \ 339 .name = _name, \ 340 .id = _id, \ 341 .irq = 0, \ 342 .gpio = { \ 343 .instance = UINT_MAX, \ 344 .pin = UINT_MAX, \ 345 }, \ 346 } 347 348 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \ 349 { \ 350 .name = _name, \ 351 .id = _id, \ 352 .irq = _irq, \ 353 .gpio = { \ 354 .instance = UINT_MAX, \ 355 .pin = UINT_MAX, \ 356 }, \ 357 } 358 359 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \ 360 { \ 361 .name = _name, \ 362 .id = _id, \ 363 .irq = 0, \ 364 .gpio = { \ 365 .instance = _instance, \ 366 .pin = _pin, \ 367 }, \ 368 } 369 370 struct tegra_pmc_soc { 371 unsigned int num_powergates; 372 const char *const *powergates; 373 unsigned int num_cpu_powergates; 374 const u8 *cpu_powergates; 375 376 bool has_tsense_reset; 377 bool has_gpu_clamps; 378 bool needs_mbist_war; 379 bool has_io_pad_wren; 380 bool maybe_tz_only; 381 382 const struct tegra_io_pad_soc *io_pads; 383 unsigned int num_io_pads; 384 const struct tegra_io_pad_vctrl *io_pad_vctrls; 385 unsigned int num_io_pad_vctrls; 386 387 const struct pinctrl_pin_desc *pin_descs; 388 unsigned int num_pin_descs; 389 390 const struct tegra_pmc_regs *regs; 391 void (*init)(struct tegra_pmc *pmc); 392 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 393 struct device_node *np, 394 bool invert); 395 void (*set_wake_filters)(struct tegra_pmc *pmc); 396 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 397 int (*irq_set_type)(struct irq_data *data, unsigned int type); 398 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id, 399 bool new_state); 400 401 const char * const *reset_sources; 402 unsigned int num_reset_sources; 403 const char * const *reset_levels; 404 unsigned int num_reset_levels; 405 406 /* 407 * These describe events that can wake the system from sleep (i.e. 408 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2) 409 * are dealt with in the LIC. 410 */ 411 const struct tegra_wake_event *wake_events; 412 unsigned int num_wake_events; 413 unsigned int max_wake_events; 414 unsigned int max_wake_vectors; 415 416 const struct pmc_clk_init_data *pmc_clks_data; 417 unsigned int num_pmc_clks; 418 bool has_blink_output; 419 bool has_usb_sleepwalk; 420 bool supports_core_domain; 421 bool has_single_mmio_aperture; 422 }; 423 424 /** 425 * struct tegra_pmc - NVIDIA Tegra PMC 426 * @dev: pointer to PMC device structure 427 * @base: pointer to I/O remapped register region 428 * @wake: pointer to I/O remapped region for WAKE registers 429 * @aotag: pointer to I/O remapped region for AOTAG registers 430 * @scratch: pointer to I/O remapped region for scratch registers 431 * @clk: pointer to pclk clock 432 * @soc: pointer to SoC data structure 433 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone 434 * @rate: currently configured rate of pclk 435 * @suspend_mode: lowest suspend mode available 436 * @cpu_good_time: CPU power good time (in microseconds) 437 * @cpu_off_time: CPU power off time (in microsecends) 438 * @core_osc_time: core power good OSC time (in microseconds) 439 * @core_pmu_time: core power good PMU time (in microseconds) 440 * @core_off_time: core power off time (in microseconds) 441 * @corereq_high: core power request is active-high 442 * @sysclkreq_high: system clock request is active-high 443 * @combined_req: combined power request for CPU & core 444 * @cpu_pwr_good_en: CPU power good signal is enabled 445 * @lp0_vec_phys: physical base address of the LP0 warm boot code 446 * @lp0_vec_size: size of the LP0 warm boot code 447 * @powergates_available: Bitmap of available power gates 448 * @powergates_lock: mutex for power gate register access 449 * @pctl_dev: pin controller exposed by the PMC 450 * @domain: IRQ domain provided by the PMC 451 * @irq: chip implementation for the IRQ domain 452 * @clk_nb: pclk clock changes handler 453 * @core_domain_state_synced: flag marking the core domain's state as synced 454 * @wake_type_level_map: Bitmap indicating level type for non-dual edge wakes 455 * @wake_type_dual_edge_map: Bitmap indicating if a wake is dual-edge or not 456 * @wake_sw_status_map: Bitmap to hold raw status of wakes without mask 457 * @wake_cntrl_level_map: Bitmap to hold wake levels to be programmed in 458 * cntrl register associated with each wake during system suspend. 459 * @reboot_notifier: PMC reboot notifier handler 460 * @syscore: syscore suspend/resume callbacks 461 * @wake_work: IRQ work handler for processing wake-up events. 462 * @wake_status: Status of wake-up events. 463 */ 464 struct tegra_pmc { 465 struct device *dev; 466 void __iomem *base; 467 void __iomem *wake; 468 void __iomem *aotag; 469 void __iomem *scratch; 470 struct clk *clk; 471 472 const struct tegra_pmc_soc *soc; 473 bool tz_only; 474 475 unsigned long rate; 476 477 enum tegra_suspend_mode suspend_mode; 478 u32 cpu_good_time; 479 u32 cpu_off_time; 480 u32 core_osc_time; 481 u32 core_pmu_time; 482 u32 core_off_time; 483 bool corereq_high; 484 bool sysclkreq_high; 485 bool combined_req; 486 bool cpu_pwr_good_en; 487 u32 lp0_vec_phys; 488 u32 lp0_vec_size; 489 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 490 491 struct mutex powergates_lock; 492 493 struct pinctrl_dev *pctl_dev; 494 495 struct irq_domain *domain; 496 struct irq_chip irq; 497 498 struct notifier_block clk_nb; 499 500 bool core_domain_state_synced; 501 502 unsigned long *wake_type_level_map; 503 unsigned long *wake_type_dual_edge_map; 504 unsigned long *wake_sw_status_map; 505 unsigned long *wake_cntrl_level_map; 506 507 struct notifier_block reboot_notifier; 508 struct syscore syscore; 509 510 /* Pending wake IRQ processing */ 511 struct irq_work wake_work; 512 u32 *wake_status; 513 }; 514 515 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 516 .base = NULL, 517 .suspend_mode = TEGRA_SUSPEND_NOT_READY, 518 }; 519 520 static inline struct tegra_powergate * 521 to_powergate(struct generic_pm_domain *domain) 522 { 523 return container_of(domain, struct tegra_powergate, genpd); 524 } 525 526 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) 527 { 528 struct arm_smccc_res res; 529 530 if (pmc->tz_only) { 531 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, 532 0, 0, 0, &res); 533 if (res.a0) { 534 if (pmc->dev) 535 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 536 __func__, res.a0); 537 else 538 pr_warn("%s(): SMC failed: %lu\n", __func__, 539 res.a0); 540 } 541 542 return res.a1; 543 } 544 545 return readl(pmc->base + offset); 546 } 547 548 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, 549 unsigned long offset) 550 { 551 struct arm_smccc_res res; 552 553 if (pmc->tz_only) { 554 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, 555 value, 0, 0, 0, 0, &res); 556 if (res.a0) { 557 if (pmc->dev) 558 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 559 __func__, res.a0); 560 else 561 pr_warn("%s(): SMC failed: %lu\n", __func__, 562 res.a0); 563 } 564 } else { 565 writel(value, pmc->base + offset); 566 } 567 } 568 569 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) 570 { 571 if (pmc->tz_only) 572 return tegra_pmc_readl(pmc, offset); 573 574 return readl(pmc->scratch + offset); 575 } 576 577 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, 578 unsigned long offset) 579 { 580 if (pmc->tz_only) 581 tegra_pmc_writel(pmc, value, offset); 582 else 583 writel(value, pmc->scratch + offset); 584 } 585 586 static inline bool tegra_powergate_state(struct tegra_pmc *pmc, int id) 587 { 588 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 589 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; 590 else 591 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; 592 } 593 594 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) 595 { 596 return (pmc->soc && pmc->soc->powergates[id]); 597 } 598 599 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) 600 { 601 return test_bit(id, pmc->powergates_available); 602 } 603 604 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 605 { 606 unsigned int i; 607 608 if (!pmc || !pmc->soc || !name) 609 return -EINVAL; 610 611 for (i = 0; i < pmc->soc->num_powergates; i++) { 612 if (!tegra_powergate_is_valid(pmc, i)) 613 continue; 614 615 if (!strcmp(name, pmc->soc->powergates[i])) 616 return i; 617 } 618 619 return -ENODEV; 620 } 621 622 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id, 623 bool new_state) 624 { 625 unsigned int retries = 100; 626 bool status; 627 int ret; 628 629 /* 630 * As per TRM documentation, the toggle command will be dropped by PMC 631 * if there is contention with a HW-initiated toggling (i.e. CPU core 632 * power-gated), the command should be retried in that case. 633 */ 634 do { 635 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 636 637 /* wait for PMC to execute the command */ 638 ret = read_poll_timeout(tegra_powergate_state, status, 639 status == new_state, 1, 10, false, 640 pmc, id); 641 } while (ret == -ETIMEDOUT && retries--); 642 643 return ret; 644 } 645 646 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc) 647 { 648 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START); 649 } 650 651 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id, 652 bool new_state) 653 { 654 bool status; 655 int err; 656 657 /* wait while PMC power gating is contended */ 658 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 659 status == true, 1, 100); 660 if (err) 661 return err; 662 663 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 664 665 /* wait for PMC to accept the command */ 666 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 667 status == true, 1, 100); 668 if (err) 669 return err; 670 671 /* wait for PMC to execute the command */ 672 err = read_poll_timeout(tegra_powergate_state, status, 673 status == new_state, 10, 100000, false, 674 pmc, id); 675 if (err) 676 return err; 677 678 return 0; 679 } 680 681 /** 682 * tegra_powergate_set() - set the state of a partition 683 * @pmc: power management controller 684 * @id: partition ID 685 * @new_state: new state of the partition 686 */ 687 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, 688 bool new_state) 689 { 690 int err; 691 692 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 693 return -EINVAL; 694 695 mutex_lock(&pmc->powergates_lock); 696 697 if (tegra_powergate_state(pmc, id) == new_state) { 698 mutex_unlock(&pmc->powergates_lock); 699 return 0; 700 } 701 702 err = pmc->soc->powergate_set(pmc, id, new_state); 703 704 mutex_unlock(&pmc->powergates_lock); 705 706 return err; 707 } 708 709 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, 710 unsigned int id) 711 { 712 u32 mask; 713 714 mutex_lock(&pmc->powergates_lock); 715 716 /* 717 * On Tegra124 and later, the clamps for the GPU are controlled by a 718 * separate register (with different semantics). 719 */ 720 if (id == TEGRA_POWERGATE_3D) { 721 if (pmc->soc->has_gpu_clamps) { 722 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); 723 goto out; 724 } 725 } 726 727 /* 728 * Tegra 2 has a bug where PCIE and VDE clamping masks are 729 * swapped relatively to the partition ids 730 */ 731 if (id == TEGRA_POWERGATE_VDEC) 732 mask = (1 << TEGRA_POWERGATE_PCIE); 733 else if (id == TEGRA_POWERGATE_PCIE) 734 mask = (1 << TEGRA_POWERGATE_VDEC); 735 else 736 mask = (1 << id); 737 738 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); 739 740 out: 741 mutex_unlock(&pmc->powergates_lock); 742 743 return 0; 744 } 745 746 static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg) 747 { 748 unsigned long safe_rate = 100 * 1000 * 1000; 749 unsigned int i; 750 int err; 751 752 for (i = 0; i < pg->num_clks; i++) { 753 pg->clk_rates[i] = clk_get_rate(pg->clks[i]); 754 755 if (!pg->clk_rates[i]) { 756 err = -EINVAL; 757 goto out; 758 } 759 760 if (pg->clk_rates[i] <= safe_rate) 761 continue; 762 763 /* 764 * We don't know whether voltage state is okay for the 765 * current clock rate, hence it's better to temporally 766 * switch clock to a safe rate which is suitable for 767 * all voltages, before enabling the clock. 768 */ 769 err = clk_set_rate(pg->clks[i], safe_rate); 770 if (err) 771 goto out; 772 } 773 774 return 0; 775 776 out: 777 while (i--) 778 clk_set_rate(pg->clks[i], pg->clk_rates[i]); 779 780 return err; 781 } 782 783 static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg) 784 { 785 unsigned int i; 786 int err; 787 788 for (i = 0; i < pg->num_clks; i++) { 789 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]); 790 if (err) 791 return err; 792 } 793 794 return 0; 795 } 796 797 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 798 { 799 unsigned int i; 800 801 for (i = 0; i < pg->num_clks; i++) 802 clk_disable_unprepare(pg->clks[i]); 803 } 804 805 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 806 { 807 unsigned int i; 808 int err; 809 810 for (i = 0; i < pg->num_clks; i++) { 811 err = clk_prepare_enable(pg->clks[i]); 812 if (err) 813 goto out; 814 } 815 816 return 0; 817 818 out: 819 while (i--) 820 clk_disable_unprepare(pg->clks[i]); 821 822 return err; 823 } 824 825 static int tegra_powergate_power_up(struct tegra_powergate *pg, 826 bool disable_clocks) 827 { 828 int err; 829 830 err = reset_control_assert(pg->reset); 831 if (err) 832 return err; 833 834 usleep_range(10, 20); 835 836 err = tegra_powergate_set(pg->pmc, pg->id, true); 837 if (err < 0) 838 return err; 839 840 usleep_range(10, 20); 841 842 err = tegra_powergate_prepare_clocks(pg); 843 if (err) 844 goto powergate_off; 845 846 err = tegra_powergate_enable_clocks(pg); 847 if (err) 848 goto unprepare_clks; 849 850 usleep_range(10, 20); 851 852 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); 853 if (err) 854 goto disable_clks; 855 856 usleep_range(10, 20); 857 858 err = reset_control_deassert(pg->reset); 859 if (err) 860 goto disable_clks; 861 862 usleep_range(10, 20); 863 864 if (pg->pmc->soc->needs_mbist_war) 865 err = tegra210_clk_handle_mbist_war(pg->id); 866 if (err) 867 goto disable_clks; 868 869 if (disable_clocks) 870 tegra_powergate_disable_clocks(pg); 871 872 err = tegra_powergate_unprepare_clocks(pg); 873 if (err) 874 return err; 875 876 return 0; 877 878 disable_clks: 879 tegra_powergate_disable_clocks(pg); 880 usleep_range(10, 20); 881 882 unprepare_clks: 883 tegra_powergate_unprepare_clocks(pg); 884 885 powergate_off: 886 tegra_powergate_set(pg->pmc, pg->id, false); 887 888 return err; 889 } 890 891 static int tegra_powergate_power_down(struct tegra_powergate *pg) 892 { 893 int err; 894 895 err = tegra_powergate_prepare_clocks(pg); 896 if (err) 897 return err; 898 899 err = tegra_powergate_enable_clocks(pg); 900 if (err) 901 goto unprepare_clks; 902 903 usleep_range(10, 20); 904 905 err = reset_control_assert(pg->reset); 906 if (err) 907 goto disable_clks; 908 909 usleep_range(10, 20); 910 911 tegra_powergate_disable_clocks(pg); 912 913 usleep_range(10, 20); 914 915 err = tegra_powergate_set(pg->pmc, pg->id, false); 916 if (err) 917 goto assert_resets; 918 919 err = tegra_powergate_unprepare_clocks(pg); 920 if (err) 921 return err; 922 923 return 0; 924 925 assert_resets: 926 tegra_powergate_enable_clocks(pg); 927 usleep_range(10, 20); 928 reset_control_deassert(pg->reset); 929 usleep_range(10, 20); 930 931 disable_clks: 932 tegra_powergate_disable_clocks(pg); 933 934 unprepare_clks: 935 tegra_powergate_unprepare_clocks(pg); 936 937 return err; 938 } 939 940 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 941 { 942 struct tegra_powergate *pg = to_powergate(domain); 943 struct device *dev = pg->pmc->dev; 944 int err; 945 946 err = tegra_powergate_power_up(pg, true); 947 if (err) { 948 dev_err(dev, "failed to turn on PM domain %s: %d\n", 949 pg->genpd.name, err); 950 goto out; 951 } 952 953 reset_control_release(pg->reset); 954 955 out: 956 return err; 957 } 958 959 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 960 { 961 struct tegra_powergate *pg = to_powergate(domain); 962 struct device *dev = pg->pmc->dev; 963 int err; 964 965 err = reset_control_acquire(pg->reset); 966 if (err < 0) { 967 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n", 968 pg->genpd.name, err); 969 return err; 970 } 971 972 err = tegra_powergate_power_down(pg); 973 if (err) { 974 dev_err(dev, "failed to turn off PM domain %s: %d\n", 975 pg->genpd.name, err); 976 reset_control_release(pg->reset); 977 } 978 979 return err; 980 } 981 982 static void tegra_pmc_put_device(void *data) 983 { 984 struct tegra_pmc *pmc = data; 985 986 put_device(pmc->dev); 987 } 988 989 static const struct of_device_id tegra_pmc_match[]; 990 991 static struct tegra_pmc *tegra_pmc_get(struct device *dev) 992 { 993 struct platform_device *pdev; 994 struct device_node *np; 995 struct tegra_pmc *pmc; 996 997 np = of_parse_phandle(dev->of_node, "nvidia,pmc", 0); 998 if (!np) { 999 struct device_node *parent = of_node_get(dev->of_node); 1000 1001 while ((parent = of_get_next_parent(parent)) != NULL) { 1002 np = of_find_matching_node(parent, tegra_pmc_match); 1003 if (np) 1004 break; 1005 } 1006 1007 of_node_put(parent); 1008 1009 if (!np) 1010 return ERR_PTR(-ENODEV); 1011 } 1012 1013 pdev = of_find_device_by_node(np); 1014 of_node_put(np); 1015 1016 if (!pdev) 1017 return ERR_PTR(-ENODEV); 1018 1019 pmc = platform_get_drvdata(pdev); 1020 if (!pmc) { 1021 put_device(&pdev->dev); 1022 return ERR_PTR(-EPROBE_DEFER); 1023 } 1024 1025 return pmc; 1026 } 1027 1028 /** 1029 * devm_tegra_pmc_get() - find the PMC for a given device 1030 * @dev: device for which to find the PMC 1031 * 1032 * Returns a pointer to the PMC on success or an ERR_PTR()-encoded error code 1033 * otherwise. 1034 */ 1035 struct tegra_pmc *devm_tegra_pmc_get(struct device *dev) 1036 { 1037 struct tegra_pmc *pmc; 1038 int err; 1039 1040 pmc = tegra_pmc_get(dev); 1041 if (IS_ERR(pmc)) 1042 return pmc; 1043 1044 err = devm_add_action_or_reset(dev, tegra_pmc_put_device, pmc); 1045 if (err < 0) 1046 return ERR_PTR(err); 1047 1048 return pmc; 1049 } 1050 EXPORT_SYMBOL(devm_tegra_pmc_get); 1051 1052 /** 1053 * tegra_pmc_powergate_power_on() - power on partition 1054 * @pmc: power management controller 1055 * @id: partition ID 1056 */ 1057 int tegra_pmc_powergate_power_on(struct tegra_pmc *pmc, unsigned int id) 1058 { 1059 if (!tegra_powergate_is_available(pmc, id)) 1060 return -EINVAL; 1061 1062 return tegra_powergate_set(pmc, id, true); 1063 } 1064 EXPORT_SYMBOL(tegra_pmc_powergate_power_on); 1065 1066 /** 1067 * tegra_powergate_power_on() - power on partition 1068 * @id: partition ID 1069 */ 1070 int tegra_powergate_power_on(unsigned int id) 1071 { 1072 return tegra_pmc_powergate_power_on(pmc, id); 1073 } 1074 EXPORT_SYMBOL(tegra_powergate_power_on); 1075 1076 /** 1077 * tegra_pmc_powergate_power_off() - power off partition 1078 * @pmc: power management controller 1079 * @id: partition ID 1080 */ 1081 int tegra_pmc_powergate_power_off(struct tegra_pmc *pmc, unsigned int id) 1082 { 1083 if (!tegra_powergate_is_available(pmc, id)) 1084 return -EINVAL; 1085 1086 return tegra_powergate_set(pmc, id, false); 1087 } 1088 EXPORT_SYMBOL(tegra_pmc_powergate_power_off); 1089 1090 /** 1091 * tegra_powergate_power_off() - power off partition 1092 * @id: partition ID 1093 */ 1094 int tegra_powergate_power_off(unsigned int id) 1095 { 1096 return tegra_pmc_powergate_power_off(pmc, id); 1097 } 1098 EXPORT_SYMBOL(tegra_powergate_power_off); 1099 1100 /** 1101 * tegra_powergate_is_powered() - check if partition is powered 1102 * @pmc: power management controller 1103 * @id: partition ID 1104 */ 1105 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) 1106 { 1107 if (!tegra_powergate_is_valid(pmc, id)) 1108 return -EINVAL; 1109 1110 return tegra_powergate_state(pmc, id); 1111 } 1112 1113 /** 1114 * tegra_pmc_powergate_remove_clamping() - remove power clamps for partition 1115 * @pmc: power management controller 1116 * @id: partition ID 1117 */ 1118 int tegra_pmc_powergate_remove_clamping(struct tegra_pmc *pmc, unsigned int id) 1119 { 1120 if (!tegra_powergate_is_available(pmc, id)) 1121 return -EINVAL; 1122 1123 return __tegra_powergate_remove_clamping(pmc, id); 1124 } 1125 EXPORT_SYMBOL(tegra_pmc_powergate_remove_clamping); 1126 1127 /** 1128 * tegra_powergate_remove_clamping() - remove power clamps for partition 1129 * @id: partition ID 1130 */ 1131 int tegra_powergate_remove_clamping(unsigned int id) 1132 { 1133 return tegra_pmc_powergate_remove_clamping(pmc, id); 1134 } 1135 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 1136 1137 /** 1138 * tegra_pmc_powergate_sequence_power_up() - power up partition 1139 * @pmc: power management controller 1140 * @id: partition ID 1141 * @clk: clock for partition 1142 * @rst: reset for partition 1143 * 1144 * Must be called with clk disabled, and returns with clk enabled. 1145 */ 1146 int tegra_pmc_powergate_sequence_power_up(struct tegra_pmc *pmc, 1147 unsigned int id, struct clk *clk, 1148 struct reset_control *rst) 1149 { 1150 struct tegra_powergate *pg; 1151 int err; 1152 1153 if (!tegra_powergate_is_available(pmc, id)) 1154 return -EINVAL; 1155 1156 pg = kzalloc_obj(*pg); 1157 if (!pg) 1158 return -ENOMEM; 1159 1160 pg->clk_rates = kzalloc_obj(*pg->clk_rates); 1161 if (!pg->clk_rates) { 1162 kfree(pg->clks); 1163 return -ENOMEM; 1164 } 1165 1166 pg->id = id; 1167 pg->clks = &clk; 1168 pg->num_clks = 1; 1169 pg->reset = rst; 1170 pg->pmc = pmc; 1171 1172 err = tegra_powergate_power_up(pg, false); 1173 if (err) 1174 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, 1175 err); 1176 1177 kfree(pg->clk_rates); 1178 kfree(pg); 1179 1180 return err; 1181 } 1182 EXPORT_SYMBOL(tegra_pmc_powergate_sequence_power_up); 1183 1184 /** 1185 * tegra_powergate_sequence_power_up() - power up partition 1186 * @id: partition ID 1187 * @clk: clock for partition 1188 * @rst: reset for partition 1189 * 1190 * Must be called with clk disabled, and returns with clk enabled. 1191 */ 1192 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 1193 struct reset_control *rst) 1194 { 1195 return tegra_pmc_powergate_sequence_power_up(pmc, id, clk, rst); 1196 } 1197 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 1198 1199 /** 1200 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 1201 * @pmc: power management controller 1202 * @cpuid: CPU partition ID 1203 * 1204 * Returns the partition ID corresponding to the CPU partition ID or a 1205 * negative error code on failure. 1206 */ 1207 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, 1208 unsigned int cpuid) 1209 { 1210 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 1211 return pmc->soc->cpu_powergates[cpuid]; 1212 1213 return -EINVAL; 1214 } 1215 1216 /** 1217 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 1218 * @cpuid: CPU partition ID 1219 */ 1220 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 1221 { 1222 int id; 1223 1224 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1225 if (id < 0) 1226 return false; 1227 1228 return tegra_powergate_is_powered(pmc, id); 1229 } 1230 1231 /** 1232 * tegra_pmc_cpu_power_on() - power on CPU partition 1233 * @cpuid: CPU partition ID 1234 */ 1235 int tegra_pmc_cpu_power_on(unsigned int cpuid) 1236 { 1237 int id; 1238 1239 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1240 if (id < 0) 1241 return id; 1242 1243 return tegra_powergate_set(pmc, id, true); 1244 } 1245 1246 /** 1247 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 1248 * @cpuid: CPU partition ID 1249 */ 1250 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 1251 { 1252 int id; 1253 1254 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1255 if (id < 0) 1256 return id; 1257 1258 return tegra_powergate_remove_clamping(id); 1259 } 1260 1261 static void tegra_pmc_program_reboot_reason(struct tegra_pmc *pmc, 1262 const char *cmd) 1263 { 1264 u32 value; 1265 1266 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); 1267 value &= ~PMC_SCRATCH0_MODE_MASK; 1268 1269 if (cmd) { 1270 if (strcmp(cmd, "recovery") == 0) 1271 value |= PMC_SCRATCH0_MODE_RECOVERY; 1272 1273 if (strcmp(cmd, "bootloader") == 0) 1274 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 1275 1276 if (strcmp(cmd, "forced-recovery") == 0) 1277 value |= PMC_SCRATCH0_MODE_RCM; 1278 } 1279 1280 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); 1281 } 1282 1283 static int tegra_pmc_reboot_notify(struct notifier_block *this, 1284 unsigned long action, void *data) 1285 { 1286 struct tegra_pmc *pmc = container_of(this, struct tegra_pmc, 1287 reboot_notifier); 1288 if (action == SYS_RESTART) 1289 tegra_pmc_program_reboot_reason(pmc, data); 1290 1291 return NOTIFY_DONE; 1292 } 1293 1294 static void tegra_pmc_restart(struct tegra_pmc *pmc) 1295 { 1296 u32 value; 1297 1298 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 1299 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1300 value |= PMC_CNTRL_MAIN_RST; 1301 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1302 } 1303 1304 static int tegra_pmc_restart_handler(struct sys_off_data *data) 1305 { 1306 struct tegra_pmc *pmc = data->cb_data; 1307 1308 tegra_pmc_restart(pmc); 1309 1310 return NOTIFY_DONE; 1311 } 1312 1313 static int tegra_pmc_power_off_handler(struct sys_off_data *data) 1314 { 1315 struct tegra_pmc *pmc = data->cb_data; 1316 1317 /* 1318 * Reboot Nexus 7 into special bootloader mode if USB cable is 1319 * connected in order to display battery status and power off. 1320 */ 1321 if (of_machine_is_compatible("asus,grouper") && 1322 power_supply_is_system_supplied()) { 1323 const u32 go_to_charger_mode = 0xa5a55a5a; 1324 1325 tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37); 1326 tegra_pmc_restart(pmc); 1327 } 1328 1329 return NOTIFY_DONE; 1330 } 1331 1332 static int powergate_show(struct seq_file *s, void *data) 1333 { 1334 struct tegra_pmc *pmc = data; 1335 unsigned int i; 1336 int status; 1337 1338 seq_printf(s, " powergate powered\n"); 1339 seq_printf(s, "------------------\n"); 1340 1341 for (i = 0; i < pmc->soc->num_powergates; i++) { 1342 status = tegra_powergate_is_powered(pmc, i); 1343 if (status < 0) 1344 continue; 1345 1346 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 1347 str_yes_no(status)); 1348 } 1349 1350 return 0; 1351 } 1352 1353 DEFINE_SHOW_ATTRIBUTE(powergate); 1354 1355 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 1356 struct device_node *np) 1357 { 1358 struct clk *clk; 1359 unsigned int i, count; 1360 int err; 1361 1362 count = of_clk_get_parent_count(np); 1363 if (count == 0) 1364 return -ENODEV; 1365 1366 pg->clks = kzalloc_objs(clk, count); 1367 if (!pg->clks) 1368 return -ENOMEM; 1369 1370 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL); 1371 if (!pg->clk_rates) { 1372 kfree(pg->clks); 1373 return -ENOMEM; 1374 } 1375 1376 for (i = 0; i < count; i++) { 1377 pg->clks[i] = of_clk_get(np, i); 1378 if (IS_ERR(pg->clks[i])) { 1379 err = PTR_ERR(pg->clks[i]); 1380 goto err; 1381 } 1382 } 1383 1384 pg->num_clks = count; 1385 1386 return 0; 1387 1388 err: 1389 while (i--) 1390 clk_put(pg->clks[i]); 1391 1392 kfree(pg->clk_rates); 1393 kfree(pg->clks); 1394 1395 return err; 1396 } 1397 1398 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 1399 struct device_node *np) 1400 { 1401 struct device *dev = pg->pmc->dev; 1402 int err; 1403 1404 pg->reset = of_reset_control_array_get_exclusive_released(np); 1405 if (IS_ERR(pg->reset)) { 1406 err = PTR_ERR(pg->reset); 1407 dev_err(dev, "failed to get device resets: %d\n", err); 1408 return err; 1409 } 1410 1411 err = reset_control_acquire(pg->reset); 1412 if (err < 0) { 1413 pr_err("failed to acquire resets: %d\n", err); 1414 reset_control_put(pg->reset); 1415 } 1416 1417 return err; 1418 } 1419 1420 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 1421 { 1422 struct device *dev = pmc->dev; 1423 struct tegra_powergate *pg; 1424 int id, err = 0; 1425 bool off; 1426 1427 pg = kzalloc_obj(*pg); 1428 if (!pg) 1429 return -ENOMEM; 1430 1431 id = tegra_powergate_lookup(pmc, np->name); 1432 if (id < 0) { 1433 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id); 1434 err = -ENODEV; 1435 goto free_mem; 1436 } 1437 1438 /* 1439 * Clear the bit for this powergate so it cannot be managed 1440 * directly via the legacy APIs for controlling powergates. 1441 */ 1442 clear_bit(id, pmc->powergates_available); 1443 1444 pg->id = id; 1445 pg->genpd.name = np->name; 1446 pg->genpd.flags = GENPD_FLAG_NO_SYNC_STATE; 1447 pg->genpd.power_off = tegra_genpd_power_off; 1448 pg->genpd.power_on = tegra_genpd_power_on; 1449 pg->pmc = pmc; 1450 1451 off = !tegra_powergate_is_powered(pmc, pg->id); 1452 1453 err = tegra_powergate_of_get_clks(pg, np); 1454 if (err < 0) { 1455 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err); 1456 goto set_available; 1457 } 1458 1459 err = tegra_powergate_of_get_resets(pg, np); 1460 if (err < 0) { 1461 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err); 1462 goto remove_clks; 1463 } 1464 1465 /* 1466 * If the power-domain is off, then ensure the resets are asserted. 1467 * If the power-domain is on, then power down to ensure that when is 1468 * it turned on the power-domain, clocks and resets are all in the 1469 * expected state. 1470 */ 1471 if (off) { 1472 err = reset_control_assert(pg->reset); 1473 if (err) { 1474 pr_err("failed to assert resets: %d\n", err); 1475 goto remove_resets; 1476 } 1477 } else { 1478 err = tegra_powergate_power_down(pg); 1479 if (err) { 1480 dev_err(dev, "failed to turn off PM domain %s: %d\n", 1481 pg->genpd.name, err); 1482 goto remove_resets; 1483 } 1484 } 1485 1486 /* 1487 * If PM_GENERIC_DOMAINS is not enabled, power-on 1488 * the domain and skip the genpd registration. 1489 */ 1490 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 1491 WARN_ON(tegra_powergate_power_up(pg, true)); 1492 goto remove_resets; 1493 } 1494 1495 err = pm_genpd_init(&pg->genpd, NULL, true); 1496 if (err < 0) { 1497 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np, 1498 err); 1499 goto remove_resets; 1500 } 1501 1502 err = of_genpd_add_provider_simple(np, &pg->genpd); 1503 if (err < 0) { 1504 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n", 1505 np, err); 1506 goto remove_genpd; 1507 } 1508 1509 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); 1510 1511 return 0; 1512 1513 remove_genpd: 1514 pm_genpd_remove(&pg->genpd); 1515 1516 remove_resets: 1517 reset_control_put(pg->reset); 1518 1519 remove_clks: 1520 while (pg->num_clks--) 1521 clk_put(pg->clks[pg->num_clks]); 1522 1523 kfree(pg->clks); 1524 1525 set_available: 1526 set_bit(id, pmc->powergates_available); 1527 1528 free_mem: 1529 kfree(pg); 1530 1531 return err; 1532 } 1533 1534 bool tegra_pmc_core_domain_state_synced(void) 1535 { 1536 return pmc->core_domain_state_synced; 1537 } 1538 1539 static int 1540 tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd, 1541 unsigned int level) 1542 { 1543 struct tegra_pmc_core_pd *pd = to_core_pd(genpd); 1544 struct tegra_pmc *pmc = pd->pmc; 1545 struct dev_pm_opp *opp; 1546 int err; 1547 1548 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); 1549 if (IS_ERR(opp)) { 1550 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", 1551 level, opp); 1552 return PTR_ERR(opp); 1553 } 1554 1555 mutex_lock(&pmc->powergates_lock); 1556 err = dev_pm_opp_set_opp(pmc->dev, opp); 1557 mutex_unlock(&pmc->powergates_lock); 1558 1559 dev_pm_opp_put(opp); 1560 1561 if (err) { 1562 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", 1563 level, err); 1564 return err; 1565 } 1566 1567 return 0; 1568 } 1569 1570 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) 1571 { 1572 const char *rname[] = { "core", NULL}; 1573 struct tegra_pmc_core_pd *pd; 1574 int err; 1575 1576 pd = devm_kzalloc(pmc->dev, sizeof(*pd), GFP_KERNEL); 1577 if (!pd) 1578 return -ENOMEM; 1579 1580 pd->genpd.name = "core"; 1581 pd->genpd.flags = GENPD_FLAG_NO_SYNC_STATE; 1582 pd->genpd.set_performance_state = tegra_pmc_core_pd_set_performance_state; 1583 pd->pmc = pmc; 1584 1585 err = devm_pm_opp_set_regulators(pmc->dev, rname); 1586 if (err) 1587 return dev_err_probe(pmc->dev, err, 1588 "failed to set core OPP regulator\n"); 1589 1590 err = pm_genpd_init(&pd->genpd, NULL, false); 1591 if (err) { 1592 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); 1593 return err; 1594 } 1595 1596 err = of_genpd_add_provider_simple(np, &pd->genpd); 1597 if (err) { 1598 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); 1599 goto remove_genpd; 1600 } 1601 1602 return 0; 1603 1604 remove_genpd: 1605 pm_genpd_remove(&pd->genpd); 1606 1607 return err; 1608 } 1609 1610 static int tegra_powergate_init(struct tegra_pmc *pmc, 1611 struct device_node *parent) 1612 { 1613 struct of_phandle_args child_args, parent_args; 1614 struct device_node *np; 1615 int err = 0; 1616 1617 /* 1618 * Core power domain is the parent of powergate domains, hence it 1619 * should be registered first. 1620 */ 1621 np = of_get_child_by_name(parent, "core-domain"); 1622 if (np) { 1623 err = tegra_pmc_core_pd_add(pmc, np); 1624 of_node_put(np); 1625 if (err) 1626 return err; 1627 } 1628 1629 np = of_get_child_by_name(parent, "powergates"); 1630 if (!np) 1631 return 0; 1632 1633 for_each_child_of_node_scoped(np, child) { 1634 err = tegra_powergate_add(pmc, child); 1635 if (err < 0) 1636 break; 1637 1638 if (of_parse_phandle_with_args(child, "power-domains", 1639 "#power-domain-cells", 1640 0, &parent_args)) 1641 continue; 1642 1643 child_args.np = child; 1644 child_args.args_count = 0; 1645 1646 err = of_genpd_add_subdomain(&parent_args, &child_args); 1647 of_node_put(parent_args.np); 1648 if (err) 1649 break; 1650 } 1651 1652 of_node_put(np); 1653 1654 return err; 1655 } 1656 1657 static void tegra_powergate_remove(struct generic_pm_domain *genpd) 1658 { 1659 struct tegra_powergate *pg = to_powergate(genpd); 1660 1661 reset_control_put(pg->reset); 1662 1663 while (pg->num_clks--) 1664 clk_put(pg->clks[pg->num_clks]); 1665 1666 kfree(pg->clks); 1667 1668 set_bit(pg->id, pg->pmc->powergates_available); 1669 1670 kfree(pg); 1671 } 1672 1673 static void tegra_powergate_remove_all(struct device_node *parent) 1674 { 1675 struct generic_pm_domain *genpd; 1676 struct device_node *np, *child; 1677 1678 np = of_get_child_by_name(parent, "powergates"); 1679 if (!np) 1680 return; 1681 1682 for_each_child_of_node(np, child) { 1683 of_genpd_del_provider(child); 1684 1685 genpd = of_genpd_remove_last(child); 1686 if (IS_ERR(genpd)) 1687 continue; 1688 1689 tegra_powergate_remove(genpd); 1690 } 1691 1692 of_node_put(np); 1693 1694 np = of_get_child_by_name(parent, "core-domain"); 1695 if (np) { 1696 of_genpd_del_provider(np); 1697 of_genpd_remove_last(np); 1698 } 1699 } 1700 1701 static const struct tegra_io_pad_soc * 1702 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 1703 { 1704 unsigned int i; 1705 1706 for (i = 0; i < pmc->soc->num_io_pads; i++) 1707 if (pmc->soc->io_pads[i].id == id) 1708 return &pmc->soc->io_pads[i]; 1709 1710 return NULL; 1711 } 1712 1713 static const struct tegra_io_pad_vctrl * 1714 tegra_io_pad_vctrl_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 1715 { 1716 unsigned int i; 1717 1718 for (i = 0; i < pmc->soc->num_io_pad_vctrls; i++) 1719 if (pmc->soc->io_pad_vctrls[i].id == id) 1720 return &pmc->soc->io_pad_vctrls[i]; 1721 1722 return NULL; 1723 } 1724 1725 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, 1726 const struct tegra_io_pad_soc *pad, 1727 unsigned long *request, 1728 unsigned long *status, 1729 u32 *mask) 1730 { 1731 unsigned long rate, value; 1732 1733 if (pad->dpd == UINT_MAX) 1734 return -EINVAL; 1735 1736 *request = pad->request; 1737 *status = pad->status; 1738 *mask = BIT(pad->dpd); 1739 1740 if (pmc->clk) { 1741 rate = pmc->rate; 1742 if (!rate) { 1743 dev_err(pmc->dev, "failed to get clock rate\n"); 1744 return -ENODEV; 1745 } 1746 1747 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); 1748 1749 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 1750 value = DIV_ROUND_UP(1000000000, rate); 1751 value = DIV_ROUND_UP(200, value); 1752 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); 1753 } 1754 1755 return 0; 1756 } 1757 1758 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, 1759 u32 mask, u32 val, unsigned long timeout) 1760 { 1761 u32 value; 1762 1763 timeout = jiffies + msecs_to_jiffies(timeout); 1764 1765 while (time_after(timeout, jiffies)) { 1766 value = tegra_pmc_readl(pmc, offset); 1767 if ((value & mask) == val) 1768 return 0; 1769 1770 usleep_range(250, 1000); 1771 } 1772 1773 return -ETIMEDOUT; 1774 } 1775 1776 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) 1777 { 1778 if (pmc->clk) 1779 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1780 } 1781 1782 /** 1783 * tegra_pmc_io_pad_power_enable() - enable power to I/O pad 1784 * @pmc: power management controller 1785 * @id: Tegra I/O pad ID for which to enable power 1786 * 1787 * Returns: 0 on success or a negative error code on failure. 1788 */ 1789 int tegra_pmc_io_pad_power_enable(struct tegra_pmc *pmc, enum tegra_io_pad id) 1790 { 1791 const struct tegra_io_pad_soc *pad; 1792 unsigned long request, status; 1793 u32 mask; 1794 int err; 1795 1796 pad = tegra_io_pad_find(pmc, id); 1797 if (!pad) { 1798 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1799 return -ENOENT; 1800 } 1801 1802 mutex_lock(&pmc->powergates_lock); 1803 1804 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); 1805 if (err < 0) { 1806 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1807 goto unlock; 1808 } 1809 1810 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); 1811 1812 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); 1813 if (err < 0) { 1814 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); 1815 goto unlock; 1816 } 1817 1818 tegra_io_pad_unprepare(pmc); 1819 1820 unlock: 1821 mutex_unlock(&pmc->powergates_lock); 1822 return err; 1823 } 1824 EXPORT_SYMBOL(tegra_pmc_io_pad_power_enable); 1825 1826 /** 1827 * tegra_io_pad_power_enable() - enable power to I/O pad 1828 * @id: Tegra I/O pad ID for which to enable power 1829 * 1830 * Returns: 0 on success or a negative error code on failure. 1831 */ 1832 int tegra_io_pad_power_enable(enum tegra_io_pad id) 1833 { 1834 return tegra_pmc_io_pad_power_enable(pmc, id); 1835 } 1836 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1837 1838 /** 1839 * tegra_pmc_io_pad_power_disable() - disable power to I/O pad 1840 * @pmc: power management controller 1841 * @id: Tegra I/O pad ID for which to disable power 1842 * 1843 * Returns: 0 on success or a negative error code on failure. 1844 */ 1845 int tegra_pmc_io_pad_power_disable(struct tegra_pmc *pmc, enum tegra_io_pad id) 1846 { 1847 const struct tegra_io_pad_soc *pad; 1848 unsigned long request, status; 1849 u32 mask; 1850 int err; 1851 1852 pad = tegra_io_pad_find(pmc, id); 1853 if (!pad) { 1854 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1855 return -ENOENT; 1856 } 1857 1858 mutex_lock(&pmc->powergates_lock); 1859 1860 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); 1861 if (err < 0) { 1862 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1863 goto unlock; 1864 } 1865 1866 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); 1867 1868 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); 1869 if (err < 0) { 1870 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); 1871 goto unlock; 1872 } 1873 1874 tegra_io_pad_unprepare(pmc); 1875 1876 unlock: 1877 mutex_unlock(&pmc->powergates_lock); 1878 return err; 1879 } 1880 EXPORT_SYMBOL(tegra_pmc_io_pad_power_disable); 1881 1882 /** 1883 * tegra_io_pad_power_disable() - disable power to I/O pad 1884 * @id: Tegra I/O pad ID for which to disable power 1885 * 1886 * Returns: 0 on success or a negative error code on failure. 1887 */ 1888 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1889 { 1890 return tegra_pmc_io_pad_power_disable(pmc, id); 1891 } 1892 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1893 1894 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) 1895 { 1896 const struct tegra_io_pad_soc *pad; 1897 unsigned long status; 1898 u32 mask, value; 1899 1900 pad = tegra_io_pad_find(pmc, id); 1901 if (!pad) { 1902 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1903 return -ENOENT; 1904 } 1905 1906 if (pad->dpd == UINT_MAX) 1907 return -EINVAL; 1908 1909 status = pad->status; 1910 mask = BIT(pad->dpd); 1911 1912 value = tegra_pmc_readl(pmc, status); 1913 1914 return !(value & mask); 1915 } 1916 1917 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, 1918 int voltage) 1919 { 1920 const struct tegra_io_pad_vctrl *pad; 1921 u32 value; 1922 1923 pad = tegra_io_pad_vctrl_find(pmc, id); 1924 if (!pad) 1925 return -ENOENT; 1926 1927 mutex_lock(&pmc->powergates_lock); 1928 1929 if (pmc->soc->has_io_pad_wren) { 1930 /* write-enable PMC_PWR_DET_VALUE[pad->ena_3v3] */ 1931 value = tegra_pmc_readl(pmc, PMC_PWR_DET); 1932 value |= BIT(pad->ena_3v3); 1933 tegra_pmc_writel(pmc, value, PMC_PWR_DET); 1934 } 1935 1936 value = tegra_pmc_readl(pmc, pad->offset); 1937 1938 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) { 1939 value &= ~BIT(pad->ena_3v3); 1940 1941 if (pad->ena_1v8) 1942 value |= pad->ena_1v8; 1943 } else { 1944 value |= BIT(pad->ena_3v3); 1945 1946 if (pad->ena_1v8) 1947 value &= ~pad->ena_1v8; 1948 } 1949 1950 tegra_pmc_writel(pmc, value, pad->offset); 1951 1952 mutex_unlock(&pmc->powergates_lock); 1953 1954 usleep_range(100, 250); 1955 1956 return 0; 1957 } 1958 1959 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) 1960 { 1961 const struct tegra_io_pad_vctrl *pad; 1962 u32 value; 1963 1964 pad = tegra_io_pad_vctrl_find(pmc, id); 1965 if (!pad) 1966 return -ENOENT; 1967 1968 value = tegra_pmc_readl(pmc, pad->offset); 1969 1970 if ((value & BIT(pad->ena_3v3)) == 0) 1971 return TEGRA_IO_PAD_VOLTAGE_1V8; 1972 1973 return TEGRA_IO_PAD_VOLTAGE_3V3; 1974 } 1975 1976 #ifdef CONFIG_PM_SLEEP 1977 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1978 { 1979 return pmc->suspend_mode; 1980 } 1981 1982 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1983 { 1984 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1985 return; 1986 1987 pmc->suspend_mode = mode; 1988 } 1989 1990 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1991 { 1992 unsigned long long rate = 0; 1993 u64 ticks; 1994 u32 value; 1995 1996 switch (mode) { 1997 case TEGRA_SUSPEND_LP1: 1998 rate = 32768; 1999 break; 2000 2001 case TEGRA_SUSPEND_LP2: 2002 rate = pmc->rate; 2003 break; 2004 2005 default: 2006 break; 2007 } 2008 2009 if (WARN_ON_ONCE(rate == 0)) 2010 rate = 100000000; 2011 2012 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 2013 do_div(ticks, USEC_PER_SEC); 2014 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); 2015 2016 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 2017 do_div(ticks, USEC_PER_SEC); 2018 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); 2019 2020 value = tegra_pmc_readl(pmc, PMC_CNTRL); 2021 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 2022 value |= PMC_CNTRL_CPU_PWRREQ_OE; 2023 tegra_pmc_writel(pmc, value, PMC_CNTRL); 2024 } 2025 #endif 2026 2027 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 2028 { 2029 u32 value, values[2]; 2030 2031 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 2032 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 2033 } else { 2034 switch (value) { 2035 case 0: 2036 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 2037 break; 2038 2039 case 1: 2040 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 2041 break; 2042 2043 case 2: 2044 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 2045 break; 2046 2047 default: 2048 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 2049 break; 2050 } 2051 } 2052 2053 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 2054 2055 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 2056 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 2057 2058 pmc->cpu_good_time = value; 2059 2060 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 2061 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 2062 2063 pmc->cpu_off_time = value; 2064 2065 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 2066 values, ARRAY_SIZE(values))) 2067 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 2068 2069 pmc->core_osc_time = values[0]; 2070 pmc->core_pmu_time = values[1]; 2071 2072 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 2073 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 2074 2075 pmc->core_off_time = value; 2076 2077 pmc->corereq_high = of_property_read_bool(np, 2078 "nvidia,core-power-req-active-high"); 2079 2080 pmc->sysclkreq_high = of_property_read_bool(np, 2081 "nvidia,sys-clock-req-active-high"); 2082 2083 pmc->combined_req = of_property_read_bool(np, 2084 "nvidia,combined-power-req"); 2085 2086 pmc->cpu_pwr_good_en = of_property_read_bool(np, 2087 "nvidia,cpu-pwr-good-en"); 2088 2089 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 2090 ARRAY_SIZE(values))) 2091 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 2092 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 2093 2094 pmc->lp0_vec_phys = values[0]; 2095 pmc->lp0_vec_size = values[1]; 2096 2097 return 0; 2098 } 2099 2100 /* translate sc7 wake sources back into IRQs to catch edge triggered wakeups */ 2101 static void tegra186_pmc_wake_handler(struct irq_work *work) 2102 { 2103 struct tegra_pmc *pmc = container_of(work, struct tegra_pmc, wake_work); 2104 unsigned int i, wake; 2105 2106 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 2107 unsigned long status = pmc->wake_status[i]; 2108 2109 for_each_set_bit(wake, &status, 32) { 2110 irq_hw_number_t hwirq = wake + (i * 32); 2111 struct irq_desc *desc; 2112 unsigned int irq; 2113 2114 irq = irq_find_mapping(pmc->domain, hwirq); 2115 if (!irq) { 2116 dev_warn(pmc->dev, 2117 "No IRQ found for WAKE#%lu!\n", 2118 hwirq); 2119 continue; 2120 } 2121 2122 dev_dbg(pmc->dev, 2123 "Resume caused by WAKE#%lu mapped to IRQ#%u\n", 2124 hwirq, irq); 2125 2126 desc = irq_to_desc(irq); 2127 if (!desc) { 2128 dev_warn(pmc->dev, 2129 "No descriptor found for IRQ#%u\n", 2130 irq); 2131 continue; 2132 } 2133 2134 if (!desc->action || !desc->action->name) 2135 continue; 2136 2137 generic_handle_irq(irq); 2138 } 2139 2140 pmc->wake_status[i] = 0; 2141 } 2142 } 2143 2144 static int tegra_pmc_init(struct tegra_pmc *pmc) 2145 { 2146 if (pmc->soc->max_wake_events > 0) { 2147 pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 2148 if (!pmc->wake_type_level_map) 2149 return -ENOMEM; 2150 2151 pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 2152 if (!pmc->wake_type_dual_edge_map) 2153 return -ENOMEM; 2154 2155 pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 2156 if (!pmc->wake_sw_status_map) 2157 return -ENOMEM; 2158 2159 pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 2160 if (!pmc->wake_cntrl_level_map) 2161 return -ENOMEM; 2162 2163 pmc->wake_status = kcalloc(pmc->soc->max_wake_vectors, sizeof(u32), GFP_KERNEL); 2164 if (!pmc->wake_status) 2165 return -ENOMEM; 2166 2167 /* 2168 * Initialize IRQ work for processing wake IRQs. Must use 2169 * HARD_IRQ variant to run in hard IRQ context on PREEMPT_RT 2170 * because we call generic_handle_irq() which requires hard 2171 * IRQ context. 2172 */ 2173 pmc->wake_work = IRQ_WORK_INIT_HARD(tegra186_pmc_wake_handler); 2174 } 2175 2176 if (pmc->soc->init) 2177 pmc->soc->init(pmc); 2178 2179 return 0; 2180 } 2181 2182 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 2183 { 2184 static const char disabled[] = "emergency thermal reset disabled"; 2185 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 2186 struct device *dev = pmc->dev; 2187 struct device_node *np; 2188 u32 value, checksum; 2189 2190 if (!pmc->soc->has_tsense_reset) 2191 return; 2192 2193 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); 2194 if (!np) { 2195 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 2196 return; 2197 } 2198 2199 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 2200 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 2201 goto out; 2202 } 2203 2204 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 2205 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 2206 goto out; 2207 } 2208 2209 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 2210 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 2211 goto out; 2212 } 2213 2214 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 2215 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 2216 goto out; 2217 } 2218 2219 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 2220 pinmux = 0; 2221 2222 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 2223 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 2224 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 2225 2226 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 2227 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 2228 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); 2229 2230 value = PMC_SCRATCH55_RESET_TEGRA; 2231 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 2232 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 2233 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 2234 2235 /* 2236 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 2237 * contain the checksum and are currently zero, so they are not added. 2238 */ 2239 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 2240 + ((value >> 24) & 0xff); 2241 checksum &= 0xff; 2242 checksum = 0x100 - checksum; 2243 2244 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 2245 2246 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); 2247 2248 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 2249 value |= PMC_SENSOR_CTRL_ENABLE_RST; 2250 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 2251 2252 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 2253 2254 out: 2255 of_node_put(np); 2256 } 2257 2258 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) 2259 { 2260 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2261 2262 return pmc->soc->num_io_pads; 2263 } 2264 2265 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl, 2266 unsigned int group) 2267 { 2268 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); 2269 2270 return pmc->soc->io_pads[group].name; 2271 } 2272 2273 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, 2274 unsigned int group, 2275 const unsigned int **pins, 2276 unsigned int *num_pins) 2277 { 2278 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2279 2280 *pins = &pmc->soc->io_pads[group].id; 2281 *num_pins = 1; 2282 2283 return 0; 2284 } 2285 2286 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { 2287 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, 2288 .get_group_name = tegra_io_pad_pinctrl_get_group_name, 2289 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, 2290 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 2291 .dt_free_map = pinconf_generic_dt_free_map, 2292 }; 2293 2294 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, 2295 unsigned int pin, unsigned long *config) 2296 { 2297 enum pin_config_param param = pinconf_to_config_param(*config); 2298 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2299 const struct tegra_io_pad_soc *pad; 2300 int ret; 2301 u32 arg; 2302 2303 pad = tegra_io_pad_find(pmc, pin); 2304 if (!pad) 2305 return -EINVAL; 2306 2307 switch (param) { 2308 case PIN_CONFIG_POWER_SOURCE: 2309 ret = tegra_io_pad_get_voltage(pmc, pad->id); 2310 if (ret < 0) 2311 return ret; 2312 2313 arg = ret; 2314 break; 2315 2316 case PIN_CONFIG_MODE_LOW_POWER: 2317 ret = tegra_io_pad_is_powered(pmc, pad->id); 2318 if (ret < 0) 2319 return ret; 2320 2321 arg = !ret; 2322 break; 2323 2324 default: 2325 return -EINVAL; 2326 } 2327 2328 *config = pinconf_to_config_packed(param, arg); 2329 2330 return 0; 2331 } 2332 2333 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, 2334 unsigned int pin, unsigned long *configs, 2335 unsigned int num_configs) 2336 { 2337 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2338 const struct tegra_io_pad_soc *pad; 2339 enum pin_config_param param; 2340 unsigned int i; 2341 int err; 2342 u32 arg; 2343 2344 pad = tegra_io_pad_find(pmc, pin); 2345 if (!pad) 2346 return -EINVAL; 2347 2348 for (i = 0; i < num_configs; ++i) { 2349 param = pinconf_to_config_param(configs[i]); 2350 arg = pinconf_to_config_argument(configs[i]); 2351 2352 switch (param) { 2353 case PIN_CONFIG_MODE_LOW_POWER: 2354 if (arg) 2355 err = tegra_pmc_io_pad_power_disable(pmc, pad->id); 2356 else 2357 err = tegra_pmc_io_pad_power_enable(pmc, pad->id); 2358 if (err) 2359 return err; 2360 break; 2361 case PIN_CONFIG_POWER_SOURCE: 2362 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && 2363 arg != TEGRA_IO_PAD_VOLTAGE_3V3) 2364 return -EINVAL; 2365 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); 2366 if (err) 2367 return err; 2368 break; 2369 default: 2370 return -EINVAL; 2371 } 2372 } 2373 2374 return 0; 2375 } 2376 2377 static const struct pinconf_ops tegra_io_pad_pinconf_ops = { 2378 .pin_config_get = tegra_io_pad_pinconf_get, 2379 .pin_config_set = tegra_io_pad_pinconf_set, 2380 .is_generic = true, 2381 }; 2382 2383 static struct pinctrl_desc tegra_pmc_pctl_desc = { 2384 .pctlops = &tegra_io_pad_pinctrl_ops, 2385 .confops = &tegra_io_pad_pinconf_ops, 2386 }; 2387 2388 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) 2389 { 2390 int err; 2391 2392 if (!pmc->soc->num_pin_descs) 2393 return 0; 2394 2395 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); 2396 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; 2397 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; 2398 2399 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, 2400 pmc); 2401 if (IS_ERR(pmc->pctl_dev)) { 2402 err = PTR_ERR(pmc->pctl_dev); 2403 dev_err(pmc->dev, "failed to register pin controller: %d\n", 2404 err); 2405 return err; 2406 } 2407 2408 return 0; 2409 } 2410 2411 static ssize_t reset_reason_show(struct device *dev, 2412 struct device_attribute *attr, char *buf) 2413 { 2414 struct tegra_pmc *pmc = dev_get_drvdata(dev); 2415 u32 value; 2416 2417 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2418 value &= pmc->soc->regs->rst_source_mask; 2419 value >>= pmc->soc->regs->rst_source_shift; 2420 2421 if (WARN_ON(value >= pmc->soc->num_reset_sources)) 2422 return sprintf(buf, "%s\n", "UNKNOWN"); 2423 2424 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); 2425 } 2426 2427 static DEVICE_ATTR_RO(reset_reason); 2428 2429 static ssize_t reset_level_show(struct device *dev, 2430 struct device_attribute *attr, char *buf) 2431 { 2432 struct tegra_pmc *pmc = dev_get_drvdata(dev); 2433 u32 value; 2434 2435 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2436 value &= pmc->soc->regs->rst_level_mask; 2437 value >>= pmc->soc->regs->rst_level_shift; 2438 2439 if (WARN_ON(value >= pmc->soc->num_reset_levels)) 2440 return sprintf(buf, "%s\n", "UNKNOWN"); 2441 2442 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); 2443 } 2444 2445 static DEVICE_ATTR_RO(reset_level); 2446 2447 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) 2448 { 2449 struct device *dev = pmc->dev; 2450 int err = 0; 2451 2452 if (pmc->soc->reset_sources) { 2453 err = device_create_file(dev, &dev_attr_reset_reason); 2454 if (err < 0) 2455 dev_warn(dev, 2456 "failed to create attr \"reset_reason\": %d\n", 2457 err); 2458 } 2459 2460 if (pmc->soc->reset_levels) { 2461 err = device_create_file(dev, &dev_attr_reset_level); 2462 if (err < 0) 2463 dev_warn(dev, 2464 "failed to create attr \"reset_level\": %d\n", 2465 err); 2466 } 2467 } 2468 2469 static int tegra_pmc_irq_translate(struct irq_domain *domain, 2470 struct irq_fwspec *fwspec, 2471 unsigned long *hwirq, 2472 unsigned int *type) 2473 { 2474 if (WARN_ON(fwspec->param_count < 2)) 2475 return -EINVAL; 2476 2477 *hwirq = fwspec->param[0]; 2478 *type = fwspec->param[1]; 2479 2480 return 0; 2481 } 2482 2483 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, 2484 unsigned int num_irqs, void *data) 2485 { 2486 struct tegra_pmc *pmc = domain->host_data; 2487 const struct tegra_pmc_soc *soc = pmc->soc; 2488 struct irq_fwspec *fwspec = data; 2489 unsigned int i; 2490 int err = 0; 2491 2492 if (WARN_ON(num_irqs > 1)) 2493 return -EINVAL; 2494 2495 for (i = 0; i < soc->num_wake_events; i++) { 2496 const struct tegra_wake_event *event = &soc->wake_events[i]; 2497 2498 /* IRQ and simple wake events */ 2499 if (fwspec->param_count == 2) { 2500 struct irq_fwspec spec; 2501 2502 if (event->id != fwspec->param[0]) 2503 continue; 2504 2505 err = irq_domain_set_hwirq_and_chip(domain, virq, 2506 event->id, 2507 &pmc->irq, pmc); 2508 if (err < 0) 2509 break; 2510 2511 /* simple hierarchies stop at the PMC level */ 2512 if (event->irq == 0) { 2513 err = irq_domain_disconnect_hierarchy(domain->parent, virq); 2514 break; 2515 } 2516 2517 spec.fwnode = &pmc->dev->of_node->fwnode; 2518 spec.param_count = 3; 2519 spec.param[0] = GIC_SPI; 2520 spec.param[1] = event->irq; 2521 spec.param[2] = fwspec->param[1]; 2522 2523 err = irq_domain_alloc_irqs_parent(domain, virq, 2524 num_irqs, &spec); 2525 2526 break; 2527 } 2528 2529 /* GPIO wake events */ 2530 if (fwspec->param_count == 3) { 2531 if (event->gpio.instance != fwspec->param[0] || 2532 event->gpio.pin != fwspec->param[1]) 2533 continue; 2534 2535 err = irq_domain_set_hwirq_and_chip(domain, virq, 2536 event->id, 2537 &pmc->irq, pmc); 2538 2539 /* GPIO hierarchies stop at the PMC level */ 2540 if (!err && domain->parent) 2541 err = irq_domain_disconnect_hierarchy(domain->parent, 2542 virq); 2543 break; 2544 } 2545 } 2546 2547 /* If there is no wake-up event, there is no PMC mapping */ 2548 if (i == soc->num_wake_events) 2549 err = irq_domain_disconnect_hierarchy(domain, virq); 2550 2551 return err; 2552 } 2553 2554 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { 2555 .translate = tegra_pmc_irq_translate, 2556 .alloc = tegra_pmc_irq_alloc, 2557 }; 2558 2559 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2560 { 2561 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2562 unsigned int offset, bit; 2563 u32 value; 2564 2565 offset = data->hwirq / 32; 2566 bit = data->hwirq % 32; 2567 2568 /* clear wake status */ 2569 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); 2570 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); 2571 2572 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); 2573 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); 2574 2575 /* enable PMC wake */ 2576 if (data->hwirq >= 32) 2577 offset = PMC_WAKE2_MASK; 2578 else 2579 offset = PMC_WAKE_MASK; 2580 2581 value = tegra_pmc_readl(pmc, offset); 2582 2583 if (on) 2584 value |= BIT(bit); 2585 else 2586 value &= ~BIT(bit); 2587 2588 tegra_pmc_writel(pmc, value, offset); 2589 2590 return 0; 2591 } 2592 2593 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2594 { 2595 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2596 unsigned int offset, bit; 2597 u32 value; 2598 2599 offset = data->hwirq / 32; 2600 bit = data->hwirq % 32; 2601 2602 if (data->hwirq >= 32) 2603 offset = PMC_WAKE2_LEVEL; 2604 else 2605 offset = PMC_WAKE_LEVEL; 2606 2607 value = tegra_pmc_readl(pmc, offset); 2608 2609 switch (type) { 2610 case IRQ_TYPE_EDGE_RISING: 2611 case IRQ_TYPE_LEVEL_HIGH: 2612 value |= BIT(bit); 2613 break; 2614 2615 case IRQ_TYPE_EDGE_FALLING: 2616 case IRQ_TYPE_LEVEL_LOW: 2617 value &= ~BIT(bit); 2618 break; 2619 2620 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2621 value ^= BIT(bit); 2622 break; 2623 2624 default: 2625 return -EINVAL; 2626 } 2627 2628 tegra_pmc_writel(pmc, value, offset); 2629 2630 return 0; 2631 } 2632 2633 static void tegra186_pmc_set_wake_filters(struct tegra_pmc *pmc) 2634 { 2635 u32 value; 2636 2637 /* SW Wake (wake83) needs SR_CAPTURE filter to be enabled */ 2638 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); 2639 value |= WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN; 2640 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); 2641 dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value); 2642 } 2643 2644 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2645 { 2646 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2647 unsigned int offset, bit; 2648 u32 value; 2649 2650 offset = data->hwirq / 32; 2651 bit = data->hwirq % 32; 2652 2653 /* clear wake status */ 2654 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(pmc, data->hwirq)); 2655 2656 /* route wake to tier 2 */ 2657 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(pmc, offset)); 2658 2659 if (!on) 2660 value &= ~(1 << bit); 2661 else 2662 value |= 1 << bit; 2663 2664 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(pmc, offset)); 2665 2666 /* enable wakeup event */ 2667 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(pmc, data->hwirq)); 2668 2669 return 0; 2670 } 2671 2672 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2673 { 2674 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2675 u32 value; 2676 2677 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2678 2679 switch (type) { 2680 case IRQ_TYPE_EDGE_RISING: 2681 case IRQ_TYPE_LEVEL_HIGH: 2682 value |= WAKE_AOWAKE_CNTRL_LEVEL; 2683 set_bit(data->hwirq, pmc->wake_type_level_map); 2684 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2685 break; 2686 2687 case IRQ_TYPE_EDGE_FALLING: 2688 case IRQ_TYPE_LEVEL_LOW: 2689 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 2690 clear_bit(data->hwirq, pmc->wake_type_level_map); 2691 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2692 break; 2693 2694 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2695 value ^= WAKE_AOWAKE_CNTRL_LEVEL; 2696 clear_bit(data->hwirq, pmc->wake_type_level_map); 2697 set_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2698 break; 2699 2700 default: 2701 return -EINVAL; 2702 } 2703 2704 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2705 2706 return 0; 2707 } 2708 2709 static void tegra_irq_mask_parent(struct irq_data *data) 2710 { 2711 if (data->parent_data) 2712 irq_chip_mask_parent(data); 2713 } 2714 2715 static void tegra_irq_unmask_parent(struct irq_data *data) 2716 { 2717 if (data->parent_data) 2718 irq_chip_unmask_parent(data); 2719 } 2720 2721 static void tegra_irq_eoi_parent(struct irq_data *data) 2722 { 2723 if (data->parent_data) 2724 irq_chip_eoi_parent(data); 2725 } 2726 2727 static int tegra_irq_set_affinity_parent(struct irq_data *data, 2728 const struct cpumask *dest, 2729 bool force) 2730 { 2731 if (data->parent_data) 2732 return irq_chip_set_affinity_parent(data, dest, force); 2733 2734 return -EINVAL; 2735 } 2736 2737 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) 2738 { 2739 struct irq_domain *parent = NULL; 2740 struct device_node *np; 2741 2742 np = of_irq_find_parent(pmc->dev->of_node); 2743 if (np) { 2744 parent = irq_find_host(np); 2745 of_node_put(np); 2746 } 2747 2748 if (!parent) 2749 return 0; 2750 2751 pmc->irq.name = dev_name(pmc->dev); 2752 pmc->irq.irq_mask = tegra_irq_mask_parent; 2753 pmc->irq.irq_unmask = tegra_irq_unmask_parent; 2754 pmc->irq.irq_eoi = tegra_irq_eoi_parent; 2755 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; 2756 pmc->irq.irq_set_type = pmc->soc->irq_set_type; 2757 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; 2758 2759 pmc->domain = irq_domain_create_hierarchy(parent, 0, 96, dev_fwnode(pmc->dev), 2760 &tegra_pmc_irq_domain_ops, pmc); 2761 if (!pmc->domain) { 2762 dev_err(pmc->dev, "failed to allocate domain\n"); 2763 return -ENOMEM; 2764 } 2765 2766 return 0; 2767 } 2768 2769 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb, 2770 unsigned long action, void *ptr) 2771 { 2772 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb); 2773 struct clk_notifier_data *data = ptr; 2774 2775 switch (action) { 2776 case PRE_RATE_CHANGE: 2777 mutex_lock(&pmc->powergates_lock); 2778 break; 2779 2780 case POST_RATE_CHANGE: 2781 pmc->rate = data->new_rate; 2782 fallthrough; 2783 2784 case ABORT_RATE_CHANGE: 2785 mutex_unlock(&pmc->powergates_lock); 2786 break; 2787 2788 default: 2789 WARN_ON_ONCE(1); 2790 return notifier_from_errno(-EINVAL); 2791 } 2792 2793 return NOTIFY_OK; 2794 } 2795 2796 static void pmc_clk_fence_udelay(struct tegra_pmc *pmc, u32 offset) 2797 { 2798 tegra_pmc_readl(pmc, offset); 2799 /* pmc clk propagation delay 2 us */ 2800 udelay(2); 2801 } 2802 2803 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw) 2804 { 2805 struct pmc_clk *clk = to_pmc_clk(hw); 2806 u32 val; 2807 2808 val = tegra_pmc_readl(clk->pmc, clk->offs) >> clk->mux_shift; 2809 val &= PMC_CLK_OUT_MUX_MASK; 2810 2811 return val; 2812 } 2813 2814 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index) 2815 { 2816 struct pmc_clk *clk = to_pmc_clk(hw); 2817 u32 val; 2818 2819 val = tegra_pmc_readl(clk->pmc, clk->offs); 2820 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); 2821 val |= index << clk->mux_shift; 2822 tegra_pmc_writel(clk->pmc, val, clk->offs); 2823 pmc_clk_fence_udelay(clk->pmc, clk->offs); 2824 2825 return 0; 2826 } 2827 2828 static int pmc_clk_is_enabled(struct clk_hw *hw) 2829 { 2830 struct pmc_clk *clk = to_pmc_clk(hw); 2831 u32 val; 2832 2833 val = tegra_pmc_readl(clk->pmc, clk->offs) & BIT(clk->force_en_shift); 2834 2835 return val ? 1 : 0; 2836 } 2837 2838 static void pmc_clk_set_state(struct tegra_pmc *pmc, unsigned long offs, 2839 u32 shift, int state) 2840 { 2841 u32 val; 2842 2843 val = tegra_pmc_readl(pmc, offs); 2844 val = state ? (val | BIT(shift)) : (val & ~BIT(shift)); 2845 tegra_pmc_writel(pmc, val, offs); 2846 pmc_clk_fence_udelay(pmc, offs); 2847 } 2848 2849 static int pmc_clk_enable(struct clk_hw *hw) 2850 { 2851 struct pmc_clk *clk = to_pmc_clk(hw); 2852 2853 pmc_clk_set_state(clk->pmc, clk->offs, clk->force_en_shift, 1); 2854 2855 return 0; 2856 } 2857 2858 static void pmc_clk_disable(struct clk_hw *hw) 2859 { 2860 struct pmc_clk *clk = to_pmc_clk(hw); 2861 2862 pmc_clk_set_state(clk->pmc, clk->offs, clk->force_en_shift, 0); 2863 } 2864 2865 static const struct clk_ops pmc_clk_ops = { 2866 .get_parent = pmc_clk_mux_get_parent, 2867 .set_parent = pmc_clk_mux_set_parent, 2868 .determine_rate = __clk_mux_determine_rate, 2869 .is_enabled = pmc_clk_is_enabled, 2870 .enable = pmc_clk_enable, 2871 .disable = pmc_clk_disable, 2872 }; 2873 2874 static struct clk * 2875 tegra_pmc_clk_out_register(struct tegra_pmc *pmc, 2876 const struct pmc_clk_init_data *data, 2877 unsigned long offset) 2878 { 2879 struct clk_init_data init; 2880 struct pmc_clk *pmc_clk; 2881 2882 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); 2883 if (!pmc_clk) 2884 return ERR_PTR(-ENOMEM); 2885 2886 init.name = data->name; 2887 init.ops = &pmc_clk_ops; 2888 init.parent_names = data->parents; 2889 init.num_parents = data->num_parents; 2890 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT | 2891 CLK_SET_PARENT_GATE; 2892 2893 pmc_clk->hw.init = &init; 2894 pmc_clk->pmc = pmc; 2895 pmc_clk->offs = offset; 2896 pmc_clk->mux_shift = data->mux_shift; 2897 pmc_clk->force_en_shift = data->force_en_shift; 2898 2899 return clk_register(NULL, &pmc_clk->hw); 2900 } 2901 2902 static int pmc_clk_gate_is_enabled(struct clk_hw *hw) 2903 { 2904 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2905 u32 value = tegra_pmc_readl(gate->pmc, gate->offs); 2906 2907 return value & BIT(gate->shift) ? 1 : 0; 2908 } 2909 2910 static int pmc_clk_gate_enable(struct clk_hw *hw) 2911 { 2912 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2913 2914 pmc_clk_set_state(gate->pmc, gate->offs, gate->shift, 1); 2915 2916 return 0; 2917 } 2918 2919 static void pmc_clk_gate_disable(struct clk_hw *hw) 2920 { 2921 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2922 2923 pmc_clk_set_state(gate->pmc, gate->offs, gate->shift, 0); 2924 } 2925 2926 static const struct clk_ops pmc_clk_gate_ops = { 2927 .is_enabled = pmc_clk_gate_is_enabled, 2928 .enable = pmc_clk_gate_enable, 2929 .disable = pmc_clk_gate_disable, 2930 }; 2931 2932 static struct clk * 2933 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, 2934 const char *parent_name, unsigned long offset, 2935 u32 shift) 2936 { 2937 struct clk_init_data init; 2938 struct pmc_clk_gate *gate; 2939 2940 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); 2941 if (!gate) 2942 return ERR_PTR(-ENOMEM); 2943 2944 init.name = name; 2945 init.ops = &pmc_clk_gate_ops; 2946 init.parent_names = &parent_name; 2947 init.num_parents = 1; 2948 init.flags = 0; 2949 2950 gate->hw.init = &init; 2951 gate->pmc = pmc; 2952 gate->offs = offset; 2953 gate->shift = shift; 2954 2955 return clk_register(NULL, &gate->hw); 2956 } 2957 2958 static void tegra_pmc_clock_register(struct tegra_pmc *pmc, 2959 struct device_node *np) 2960 { 2961 struct clk *clk; 2962 struct clk_onecell_data *clk_data; 2963 unsigned int num_clks; 2964 int i, err; 2965 2966 num_clks = pmc->soc->num_pmc_clks; 2967 if (pmc->soc->has_blink_output) 2968 num_clks += 1; 2969 2970 if (!num_clks) 2971 return; 2972 2973 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); 2974 if (!clk_data) 2975 return; 2976 2977 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, 2978 sizeof(*clk_data->clks), GFP_KERNEL); 2979 if (!clk_data->clks) 2980 return; 2981 2982 clk_data->clk_num = TEGRA_PMC_CLK_MAX; 2983 2984 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++) 2985 clk_data->clks[i] = ERR_PTR(-ENOENT); 2986 2987 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { 2988 const struct pmc_clk_init_data *data; 2989 2990 data = pmc->soc->pmc_clks_data + i; 2991 2992 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); 2993 if (IS_ERR(clk)) { 2994 dev_warn(pmc->dev, "unable to register clock %s: %d\n", 2995 data->name, PTR_ERR_OR_ZERO(clk)); 2996 return; 2997 } 2998 2999 err = clk_register_clkdev(clk, data->name, NULL); 3000 if (err) { 3001 dev_warn(pmc->dev, 3002 "unable to register %s clock lookup: %d\n", 3003 data->name, err); 3004 return; 3005 } 3006 3007 clk_data->clks[data->clk_id] = clk; 3008 } 3009 3010 if (pmc->soc->has_blink_output) { 3011 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); 3012 clk = tegra_pmc_clk_gate_register(pmc, 3013 "pmc_blink_override", 3014 "clk_32k", 3015 PMC_DPD_PADS_ORIDE, 3016 PMC_DPD_PADS_ORIDE_BLINK); 3017 if (IS_ERR(clk)) { 3018 dev_warn(pmc->dev, 3019 "unable to register pmc_blink_override: %d\n", 3020 PTR_ERR_OR_ZERO(clk)); 3021 return; 3022 } 3023 3024 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", 3025 "pmc_blink_override", 3026 PMC_CNTRL, 3027 PMC_CNTRL_BLINK_EN); 3028 if (IS_ERR(clk)) { 3029 dev_warn(pmc->dev, 3030 "unable to register pmc_blink: %d\n", 3031 PTR_ERR_OR_ZERO(clk)); 3032 return; 3033 } 3034 3035 err = clk_register_clkdev(clk, "pmc_blink", NULL); 3036 if (err) { 3037 dev_warn(pmc->dev, 3038 "unable to register pmc_blink lookup: %d\n", 3039 err); 3040 return; 3041 } 3042 3043 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; 3044 } 3045 3046 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); 3047 if (err) 3048 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", 3049 err); 3050 } 3051 3052 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = { 3053 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO), 3054 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE), 3055 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE), 3056 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP), 3057 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG), 3058 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG), 3059 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1), 3060 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3), 3061 }; 3062 3063 static const struct regmap_access_table pmc_usb_sleepwalk_table = { 3064 .yes_ranges = pmc_usb_sleepwalk_ranges, 3065 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges), 3066 }; 3067 3068 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value) 3069 { 3070 struct tegra_pmc *pmc = context; 3071 3072 *value = tegra_pmc_readl(pmc, offset); 3073 return 0; 3074 } 3075 3076 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value) 3077 { 3078 struct tegra_pmc *pmc = context; 3079 3080 tegra_pmc_writel(pmc, value, offset); 3081 return 0; 3082 } 3083 3084 static const struct regmap_config usb_sleepwalk_regmap_config = { 3085 .name = "usb_sleepwalk", 3086 .reg_bits = 32, 3087 .val_bits = 32, 3088 .reg_stride = 4, 3089 .fast_io = true, 3090 .rd_table = &pmc_usb_sleepwalk_table, 3091 .wr_table = &pmc_usb_sleepwalk_table, 3092 .reg_read = tegra_pmc_regmap_readl, 3093 .reg_write = tegra_pmc_regmap_writel, 3094 }; 3095 3096 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc) 3097 { 3098 struct regmap *regmap; 3099 int err; 3100 3101 if (pmc->soc->has_usb_sleepwalk) { 3102 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); 3103 if (IS_ERR(regmap)) { 3104 err = PTR_ERR(regmap); 3105 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); 3106 return err; 3107 } 3108 } 3109 3110 return 0; 3111 } 3112 3113 static void tegra_pmc_reset_suspend_mode(void *data) 3114 { 3115 struct tegra_pmc *pmc = data; 3116 3117 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; 3118 } 3119 3120 static int tegra_pmc_probe(struct platform_device *pdev) 3121 { 3122 void __iomem *base; 3123 struct resource *res; 3124 int err; 3125 3126 /* 3127 * Early initialisation should have configured an initial 3128 * register mapping and setup the soc data pointer. If these 3129 * are not valid then something went badly wrong! 3130 */ 3131 if (WARN_ON(!pmc->base || !pmc->soc)) 3132 return -ENODEV; 3133 3134 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 3135 if (err < 0) 3136 return err; 3137 3138 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode, 3139 pmc); 3140 if (err) 3141 return err; 3142 3143 /* take over the memory region from the early initialization */ 3144 base = devm_platform_ioremap_resource(pdev, 0); 3145 if (IS_ERR(base)) 3146 return PTR_ERR(base); 3147 3148 if (pmc->soc->has_single_mmio_aperture) { 3149 pmc->wake = base; 3150 pmc->aotag = base; 3151 pmc->scratch = base; 3152 } else { 3153 pmc->wake = devm_platform_ioremap_resource_byname(pdev, "wake"); 3154 if (IS_ERR(pmc->wake)) 3155 return PTR_ERR(pmc->wake); 3156 3157 /* "aotag" is an optional aperture */ 3158 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 3159 "aotag"); 3160 if (res) { 3161 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 3162 if (IS_ERR(pmc->aotag)) 3163 return PTR_ERR(pmc->aotag); 3164 } else { 3165 pmc->aotag = NULL; 3166 } 3167 3168 /* "scratch" is an optional aperture */ 3169 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 3170 "scratch"); 3171 if (res) { 3172 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 3173 if (IS_ERR(pmc->scratch)) 3174 return PTR_ERR(pmc->scratch); 3175 } else { 3176 pmc->scratch = NULL; 3177 } 3178 } 3179 3180 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk"); 3181 if (IS_ERR(pmc->clk)) 3182 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk), 3183 "failed to get pclk\n"); 3184 3185 /* 3186 * PMC should be last resort for restarting since it soft-resets 3187 * CPU without resetting everything else. 3188 */ 3189 if (pmc->scratch) { 3190 pmc->reboot_notifier.notifier_call = tegra_pmc_reboot_notify; 3191 3192 err = devm_register_reboot_notifier(&pdev->dev, 3193 &pmc->reboot_notifier); 3194 if (err) { 3195 dev_err(&pdev->dev, 3196 "unable to register reboot notifier, %d\n", 3197 err); 3198 return err; 3199 } 3200 } 3201 3202 err = devm_register_sys_off_handler(&pdev->dev, 3203 SYS_OFF_MODE_RESTART, 3204 SYS_OFF_PRIO_LOW, 3205 tegra_pmc_restart_handler, 3206 pmc); 3207 if (err) { 3208 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", 3209 err); 3210 return err; 3211 } 3212 3213 /* 3214 * PMC should be primary power-off method if it soft-resets CPU, 3215 * asking bootloader to shutdown hardware. 3216 */ 3217 err = devm_register_sys_off_handler(&pdev->dev, 3218 SYS_OFF_MODE_POWER_OFF, 3219 SYS_OFF_PRIO_FIRMWARE, 3220 tegra_pmc_power_off_handler, 3221 pmc); 3222 if (err) { 3223 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", 3224 err); 3225 return err; 3226 } 3227 3228 /* 3229 * PCLK clock rate can't be retrieved using CLK API because it 3230 * causes lockup if CPU enters LP2 idle state from some other 3231 * CLK notifier, hence we're caching the rate's value locally. 3232 */ 3233 if (pmc->clk) { 3234 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; 3235 err = devm_clk_notifier_register(&pdev->dev, pmc->clk, 3236 &pmc->clk_nb); 3237 if (err) { 3238 dev_err(&pdev->dev, 3239 "failed to register clk notifier\n"); 3240 return err; 3241 } 3242 3243 pmc->rate = clk_get_rate(pmc->clk); 3244 } 3245 3246 pmc->dev = &pdev->dev; 3247 3248 err = tegra_pmc_init(pmc); 3249 if (err < 0) { 3250 dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err); 3251 return err; 3252 } 3253 3254 tegra_pmc_init_tsense_reset(pmc); 3255 3256 tegra_pmc_reset_sysfs_init(pmc); 3257 3258 err = tegra_pmc_pinctrl_init(pmc); 3259 if (err) 3260 goto cleanup_sysfs; 3261 3262 err = tegra_pmc_regmap_init(pmc); 3263 if (err < 0) 3264 goto cleanup_sysfs; 3265 3266 err = tegra_powergate_init(pmc, pdev->dev.of_node); 3267 if (err < 0) 3268 goto cleanup_powergates; 3269 3270 err = tegra_pmc_irq_init(pmc); 3271 if (err < 0) 3272 goto cleanup_powergates; 3273 3274 mutex_lock(&pmc->powergates_lock); 3275 iounmap(pmc->base); 3276 pmc->base = base; 3277 mutex_unlock(&pmc->powergates_lock); 3278 3279 tegra_pmc_clock_register(pmc, pdev->dev.of_node); 3280 platform_set_drvdata(pdev, pmc); 3281 tegra_pm_init_suspend(); 3282 3283 /* Some wakes require specific filter configuration */ 3284 if (pmc->soc->set_wake_filters) 3285 pmc->soc->set_wake_filters(pmc); 3286 3287 debugfs_create_file("powergate", 0444, NULL, pmc, &powergate_fops); 3288 3289 return 0; 3290 3291 cleanup_powergates: 3292 tegra_powergate_remove_all(pdev->dev.of_node); 3293 cleanup_sysfs: 3294 device_remove_file(&pdev->dev, &dev_attr_reset_reason); 3295 device_remove_file(&pdev->dev, &dev_attr_reset_level); 3296 3297 return err; 3298 } 3299 3300 /* 3301 * Ensures that sufficient time is passed for a register write to 3302 * serialize into the 32KHz domain. 3303 */ 3304 static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset) 3305 { 3306 writel(value, pmc->wake + offset); 3307 udelay(130); 3308 } 3309 3310 static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level) 3311 { 3312 unsigned int offset = WAKE_AOWAKE_CNTRL(wake); 3313 u32 value; 3314 3315 value = readl(pmc->wake + offset); 3316 if (level) 3317 value |= WAKE_AOWAKE_CNTRL_LEVEL; 3318 else 3319 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 3320 3321 writel(value, pmc->wake + offset); 3322 } 3323 3324 static void wke_write_wake_levels(struct tegra_pmc *pmc) 3325 { 3326 unsigned int i; 3327 3328 for (i = 0; i < pmc->soc->max_wake_events; i++) 3329 wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map)); 3330 } 3331 3332 static void wke_clear_sw_wake_status(struct tegra_pmc *pmc) 3333 { 3334 wke_32kwritel(pmc, 1, pmc->soc->regs->aowake_sw_status_w); 3335 } 3336 3337 static void wke_read_sw_wake_status(struct tegra_pmc *pmc) 3338 { 3339 unsigned long status; 3340 unsigned int wake, i; 3341 3342 for (i = 0; i < pmc->soc->max_wake_events; i++) 3343 wke_write_wake_level(pmc, i, 0); 3344 3345 wke_clear_sw_wake_status(pmc); 3346 3347 wke_32kwritel(pmc, 1, pmc->soc->regs->aowake_latch_sw); 3348 3349 /* 3350 * WAKE_AOWAKE_SW_STATUS is edge triggered, so in order to 3351 * obtain the current status of the input wake signals, change 3352 * the polarity of the wake level from 0->1 while latching to force 3353 * a positive edge if the sampled signal is '1'. 3354 */ 3355 for (i = 0; i < pmc->soc->max_wake_events; i++) 3356 wke_write_wake_level(pmc, i, 1); 3357 3358 /* 3359 * Wait for the update to be synced into the 32kHz domain, 3360 * and let enough time lapse, so that the wake signals have time to 3361 * be sampled. 3362 */ 3363 udelay(300); 3364 3365 wke_32kwritel(pmc, 0, pmc->soc->regs->aowake_latch_sw); 3366 3367 bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events); 3368 3369 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3370 status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(pmc, i)); 3371 3372 for_each_set_bit(wake, &status, 32) 3373 set_bit(wake + (i * 32), pmc->wake_sw_status_map); 3374 } 3375 } 3376 3377 static void wke_clear_wake_status(struct tegra_pmc *pmc) 3378 { 3379 unsigned long status; 3380 unsigned int i, wake; 3381 u32 mask; 3382 3383 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3384 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(pmc, i)); 3385 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(pmc, i)) & mask; 3386 3387 for_each_set_bit(wake, &status, 32) 3388 wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W(pmc, 3389 (i * 32) + wake)); 3390 } 3391 } 3392 3393 static void tegra186_pmc_wake_syscore_resume(void *data) 3394 { 3395 struct tegra_pmc *pmc = data; 3396 unsigned int i; 3397 u32 mask; 3398 3399 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3400 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(pmc, i)); 3401 pmc->wake_status[i] = readl(pmc->wake + 3402 WAKE_AOWAKE_STATUS_R(pmc, i)) & mask; 3403 } 3404 3405 /* Schedule IRQ work to process wake IRQs (if any) */ 3406 irq_work_queue(&pmc->wake_work); 3407 } 3408 3409 static int tegra186_pmc_wake_syscore_suspend(void *data) 3410 { 3411 struct tegra_pmc *pmc = data; 3412 unsigned int i; 3413 3414 /* Check if there are unhandled wake IRQs */ 3415 for (i = 0; i < pmc->soc->max_wake_vectors; i++) 3416 if (pmc->wake_status[i]) 3417 dev_warn(pmc->dev, 3418 "Unhandled wake IRQs pending vector[%u]: 0x%x\n", 3419 i, pmc->wake_status[i]); 3420 3421 wke_read_sw_wake_status(pmc); 3422 3423 /* flip the wakeup trigger for dual-edge triggered pads 3424 * which are currently asserting as wakeups 3425 */ 3426 bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map, 3427 pmc->wake_sw_status_map, pmc->soc->max_wake_events); 3428 bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map, 3429 pmc->wake_type_level_map, pmc->soc->max_wake_events); 3430 3431 /* Clear PMC Wake Status registers while going to suspend */ 3432 wke_clear_wake_status(pmc); 3433 wke_write_wake_levels(pmc); 3434 3435 return 0; 3436 } 3437 3438 static const struct syscore_ops tegra186_pmc_wake_syscore_ops = { 3439 .suspend = tegra186_pmc_wake_syscore_suspend, 3440 .resume = tegra186_pmc_wake_syscore_resume, 3441 }; 3442 3443 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 3444 static int tegra_pmc_suspend(struct device *dev) 3445 { 3446 struct tegra_pmc *pmc = dev_get_drvdata(dev); 3447 3448 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); 3449 3450 return 0; 3451 } 3452 3453 static int tegra_pmc_resume(struct device *dev) 3454 { 3455 struct tegra_pmc *pmc = dev_get_drvdata(dev); 3456 3457 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); 3458 3459 return 0; 3460 } 3461 3462 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 3463 3464 #endif 3465 3466 static const char * const tegra20_powergates[] = { 3467 [TEGRA_POWERGATE_CPU] = "cpu", 3468 [TEGRA_POWERGATE_3D] = "td", 3469 [TEGRA_POWERGATE_VENC] = "venc", 3470 [TEGRA_POWERGATE_VDEC] = "vdec", 3471 [TEGRA_POWERGATE_PCIE] = "pcie", 3472 [TEGRA_POWERGATE_L2] = "l2", 3473 [TEGRA_POWERGATE_MPE] = "mpe", 3474 }; 3475 3476 static const struct tegra_pmc_regs tegra20_pmc_regs = { 3477 .scratch0 = 0x50, 3478 .rst_status = 0x1b4, 3479 .rst_source_shift = 0x0, 3480 .rst_source_mask = 0x7, 3481 .rst_level_shift = 0x0, 3482 .rst_level_mask = 0x0, 3483 }; 3484 3485 static void tegra20_pmc_init(struct tegra_pmc *pmc) 3486 { 3487 u32 value, osc, pmu, off; 3488 3489 /* Always enable CPU power request */ 3490 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3491 value |= PMC_CNTRL_CPU_PWRREQ_OE; 3492 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3493 3494 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3495 3496 if (pmc->sysclkreq_high) 3497 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 3498 else 3499 value |= PMC_CNTRL_SYSCLK_POLARITY; 3500 3501 if (pmc->corereq_high) 3502 value &= ~PMC_CNTRL_PWRREQ_POLARITY; 3503 else 3504 value |= PMC_CNTRL_PWRREQ_POLARITY; 3505 3506 /* configure the output polarity while the request is tristated */ 3507 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3508 3509 /* now enable the request */ 3510 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3511 value |= PMC_CNTRL_SYSCLK_OE; 3512 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3513 3514 /* program core timings which are applicable only for suspend state */ 3515 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { 3516 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); 3517 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); 3518 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); 3519 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), 3520 PMC_COREPWRGOOD_TIMER); 3521 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); 3522 } 3523 } 3524 3525 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3526 struct device_node *np, 3527 bool invert) 3528 { 3529 u32 value; 3530 3531 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3532 3533 if (invert) 3534 value |= PMC_CNTRL_INTR_POLARITY; 3535 else 3536 value &= ~PMC_CNTRL_INTR_POLARITY; 3537 3538 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3539 } 3540 3541 static const struct tegra_pmc_soc tegra20_pmc_soc = { 3542 .supports_core_domain = true, 3543 .num_powergates = ARRAY_SIZE(tegra20_powergates), 3544 .powergates = tegra20_powergates, 3545 .num_cpu_powergates = 0, 3546 .cpu_powergates = NULL, 3547 .has_tsense_reset = false, 3548 .has_gpu_clamps = false, 3549 .needs_mbist_war = false, 3550 .has_io_pad_wren = true, 3551 .maybe_tz_only = false, 3552 .num_io_pads = 0, 3553 .io_pads = NULL, 3554 .num_pin_descs = 0, 3555 .pin_descs = NULL, 3556 .regs = &tegra20_pmc_regs, 3557 .init = tegra20_pmc_init, 3558 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3559 .powergate_set = tegra20_powergate_set, 3560 .reset_sources = NULL, 3561 .num_reset_sources = 0, 3562 .reset_levels = NULL, 3563 .num_reset_levels = 0, 3564 .pmc_clks_data = NULL, 3565 .num_pmc_clks = 0, 3566 .has_blink_output = true, 3567 .has_usb_sleepwalk = true, 3568 .has_single_mmio_aperture = true, 3569 }; 3570 3571 static const char * const tegra30_powergates[] = { 3572 [TEGRA_POWERGATE_CPU] = "cpu0", 3573 [TEGRA_POWERGATE_3D] = "td", 3574 [TEGRA_POWERGATE_VENC] = "venc", 3575 [TEGRA_POWERGATE_VDEC] = "vdec", 3576 [TEGRA_POWERGATE_PCIE] = "pcie", 3577 [TEGRA_POWERGATE_L2] = "l2", 3578 [TEGRA_POWERGATE_MPE] = "mpe", 3579 [TEGRA_POWERGATE_HEG] = "heg", 3580 [TEGRA_POWERGATE_SATA] = "sata", 3581 [TEGRA_POWERGATE_CPU1] = "cpu1", 3582 [TEGRA_POWERGATE_CPU2] = "cpu2", 3583 [TEGRA_POWERGATE_CPU3] = "cpu3", 3584 [TEGRA_POWERGATE_CELP] = "celp", 3585 [TEGRA_POWERGATE_3D1] = "td2", 3586 }; 3587 3588 static const u8 tegra30_cpu_powergates[] = { 3589 TEGRA_POWERGATE_CPU, 3590 TEGRA_POWERGATE_CPU1, 3591 TEGRA_POWERGATE_CPU2, 3592 TEGRA_POWERGATE_CPU3, 3593 }; 3594 3595 static const char * const tegra30_reset_sources[] = { 3596 "POWER_ON_RESET", 3597 "WATCHDOG", 3598 "SENSOR", 3599 "SW_MAIN", 3600 "LP0" 3601 }; 3602 3603 static const struct tegra_pmc_soc tegra30_pmc_soc = { 3604 .supports_core_domain = true, 3605 .num_powergates = ARRAY_SIZE(tegra30_powergates), 3606 .powergates = tegra30_powergates, 3607 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 3608 .cpu_powergates = tegra30_cpu_powergates, 3609 .has_tsense_reset = true, 3610 .has_gpu_clamps = false, 3611 .needs_mbist_war = false, 3612 .has_io_pad_wren = true, 3613 .maybe_tz_only = false, 3614 .num_io_pads = 0, 3615 .io_pads = NULL, 3616 .num_pin_descs = 0, 3617 .pin_descs = NULL, 3618 .regs = &tegra20_pmc_regs, 3619 .init = tegra20_pmc_init, 3620 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3621 .powergate_set = tegra20_powergate_set, 3622 .reset_sources = tegra30_reset_sources, 3623 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3624 .reset_levels = NULL, 3625 .num_reset_levels = 0, 3626 .pmc_clks_data = tegra_pmc_clks_data, 3627 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3628 .has_blink_output = true, 3629 .has_usb_sleepwalk = true, 3630 .has_single_mmio_aperture = true, 3631 }; 3632 3633 static const char * const tegra114_powergates[] = { 3634 [TEGRA_POWERGATE_CPU] = "crail", 3635 [TEGRA_POWERGATE_3D] = "td", 3636 [TEGRA_POWERGATE_VENC] = "venc", 3637 [TEGRA_POWERGATE_VDEC] = "vdec", 3638 [TEGRA_POWERGATE_MPE] = "mpe", 3639 [TEGRA_POWERGATE_HEG] = "heg", 3640 [TEGRA_POWERGATE_CPU1] = "cpu1", 3641 [TEGRA_POWERGATE_CPU2] = "cpu2", 3642 [TEGRA_POWERGATE_CPU3] = "cpu3", 3643 [TEGRA_POWERGATE_CELP] = "celp", 3644 [TEGRA_POWERGATE_CPU0] = "cpu0", 3645 [TEGRA_POWERGATE_C0NC] = "c0nc", 3646 [TEGRA_POWERGATE_C1NC] = "c1nc", 3647 [TEGRA_POWERGATE_DIS] = "dis", 3648 [TEGRA_POWERGATE_DISB] = "disb", 3649 [TEGRA_POWERGATE_XUSBA] = "xusba", 3650 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3651 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3652 }; 3653 3654 static const u8 tegra114_cpu_powergates[] = { 3655 TEGRA_POWERGATE_CPU0, 3656 TEGRA_POWERGATE_CPU1, 3657 TEGRA_POWERGATE_CPU2, 3658 TEGRA_POWERGATE_CPU3, 3659 }; 3660 3661 static const struct tegra_pmc_soc tegra114_pmc_soc = { 3662 .supports_core_domain = true, 3663 .num_powergates = ARRAY_SIZE(tegra114_powergates), 3664 .powergates = tegra114_powergates, 3665 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 3666 .cpu_powergates = tegra114_cpu_powergates, 3667 .has_tsense_reset = true, 3668 .has_gpu_clamps = false, 3669 .needs_mbist_war = false, 3670 .has_io_pad_wren = true, 3671 .maybe_tz_only = false, 3672 .num_io_pads = 0, 3673 .io_pads = NULL, 3674 .num_pin_descs = 0, 3675 .pin_descs = NULL, 3676 .regs = &tegra20_pmc_regs, 3677 .init = tegra20_pmc_init, 3678 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3679 .powergate_set = tegra114_powergate_set, 3680 .reset_sources = tegra30_reset_sources, 3681 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3682 .reset_levels = NULL, 3683 .num_reset_levels = 0, 3684 .pmc_clks_data = tegra_pmc_clks_data, 3685 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3686 .has_blink_output = true, 3687 .has_usb_sleepwalk = true, 3688 .has_single_mmio_aperture = true, 3689 }; 3690 3691 static const char * const tegra124_powergates[] = { 3692 [TEGRA_POWERGATE_CPU] = "crail", 3693 [TEGRA_POWERGATE_3D] = "3d", 3694 [TEGRA_POWERGATE_VENC] = "venc", 3695 [TEGRA_POWERGATE_PCIE] = "pcie", 3696 [TEGRA_POWERGATE_VDEC] = "vdec", 3697 [TEGRA_POWERGATE_MPE] = "mpe", 3698 [TEGRA_POWERGATE_HEG] = "heg", 3699 [TEGRA_POWERGATE_SATA] = "sata", 3700 [TEGRA_POWERGATE_CPU1] = "cpu1", 3701 [TEGRA_POWERGATE_CPU2] = "cpu2", 3702 [TEGRA_POWERGATE_CPU3] = "cpu3", 3703 [TEGRA_POWERGATE_CELP] = "celp", 3704 [TEGRA_POWERGATE_CPU0] = "cpu0", 3705 [TEGRA_POWERGATE_C0NC] = "c0nc", 3706 [TEGRA_POWERGATE_C1NC] = "c1nc", 3707 [TEGRA_POWERGATE_SOR] = "sor", 3708 [TEGRA_POWERGATE_DIS] = "dis", 3709 [TEGRA_POWERGATE_DISB] = "disb", 3710 [TEGRA_POWERGATE_XUSBA] = "xusba", 3711 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3712 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3713 [TEGRA_POWERGATE_VIC] = "vic", 3714 [TEGRA_POWERGATE_IRAM] = "iram", 3715 }; 3716 3717 static const u8 tegra124_cpu_powergates[] = { 3718 TEGRA_POWERGATE_CPU0, 3719 TEGRA_POWERGATE_CPU1, 3720 TEGRA_POWERGATE_CPU2, 3721 TEGRA_POWERGATE_CPU3, 3722 }; 3723 3724 #define TEGRA_IO_PAD(_id, _dpd, _request, _status, _name) \ 3725 ((struct tegra_io_pad_soc) { \ 3726 .id = (_id), \ 3727 .dpd = (_dpd), \ 3728 .request = (_request), \ 3729 .status = (_status), \ 3730 .name = (_name), \ 3731 }) 3732 3733 #define TEGRA_IO_PAD_VCTRL(_id, _offset, _ena_3v3) \ 3734 ((struct tegra_io_pad_vctrl) { \ 3735 .id = (_id), \ 3736 .offset = (_offset), \ 3737 .ena_3v3 = (_ena_3v3), \ 3738 .ena_1v8 = 0, \ 3739 }) 3740 3741 #define TEGRA_IO_PIN_DESC(_id, _name) \ 3742 ((struct pinctrl_pin_desc) { \ 3743 .number = (_id), \ 3744 .name = (_name), \ 3745 }) 3746 3747 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 3748 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, "audio"), 3749 TEGRA_IO_PAD(TEGRA_IO_PAD_BB, 15, 0x1b8, 0x1bc, "bb"), 3750 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, "cam"), 3751 TEGRA_IO_PAD(TEGRA_IO_PAD_COMP, 22, 0x1b8, 0x1bc, "comp"), 3752 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, "csia"), 3753 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, "csib"), 3754 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, "csie"), 3755 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, "dsi"), 3756 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, "dsib"), 3757 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, "dsic"), 3758 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, "dsid"), 3759 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, "hdmi"), 3760 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, "hsic"), 3761 TEGRA_IO_PAD(TEGRA_IO_PAD_HV, 6, 0x1c0, 0x1c4, "hv"), 3762 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, "lvds"), 3763 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, "mipi-bias"), 3764 TEGRA_IO_PAD(TEGRA_IO_PAD_NAND, 13, 0x1b8, 0x1bc, "nand"), 3765 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, "pex-bias"), 3766 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, "pex-clk1"), 3767 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, "pex-clk2"), 3768 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, "pex-cntrl"), 3769 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, "sdmmc1"), 3770 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, "sdmmc3"), 3771 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 3, 0x1c0, 0x1c4, "sdmmc4"), 3772 TEGRA_IO_PAD(TEGRA_IO_PAD_SYS_DDC, 26, 0x1c0, 0x1c4, "sys_ddc"), 3773 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, "uart"), 3774 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, "usb0"), 3775 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, "usb1"), 3776 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, "usb2"), 3777 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, "usb_bias"), 3778 }; 3779 3780 static const struct pinctrl_pin_desc tegra124_pin_descs[] = { 3781 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3782 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_BB, "bb"), 3783 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3784 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_COMP, "comp"), 3785 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3786 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3787 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3788 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3789 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3790 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3791 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3792 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"), 3793 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3794 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HV, "hv"), 3795 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"), 3796 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3797 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_NAND, "nand"), 3798 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"), 3799 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3800 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3801 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3802 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), 3803 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"), 3804 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 3805 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SYS_DDC, "sys_ddc"), 3806 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3807 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3808 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3809 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3810 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb_bias"), 3811 }; 3812 3813 static const struct tegra_pmc_soc tegra124_pmc_soc = { 3814 .supports_core_domain = false, 3815 .num_powergates = ARRAY_SIZE(tegra124_powergates), 3816 .powergates = tegra124_powergates, 3817 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 3818 .cpu_powergates = tegra124_cpu_powergates, 3819 .has_tsense_reset = true, 3820 .has_gpu_clamps = true, 3821 .needs_mbist_war = false, 3822 .has_io_pad_wren = true, 3823 .maybe_tz_only = false, 3824 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 3825 .io_pads = tegra124_io_pads, 3826 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), 3827 .pin_descs = tegra124_pin_descs, 3828 .regs = &tegra20_pmc_regs, 3829 .init = tegra20_pmc_init, 3830 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3831 .powergate_set = tegra114_powergate_set, 3832 .reset_sources = tegra30_reset_sources, 3833 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3834 .reset_levels = NULL, 3835 .num_reset_levels = 0, 3836 .pmc_clks_data = tegra_pmc_clks_data, 3837 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3838 .has_blink_output = true, 3839 .has_usb_sleepwalk = true, 3840 .has_single_mmio_aperture = true, 3841 }; 3842 3843 static const char * const tegra210_powergates[] = { 3844 [TEGRA_POWERGATE_CPU] = "crail", 3845 [TEGRA_POWERGATE_3D] = "3d", 3846 [TEGRA_POWERGATE_VENC] = "venc", 3847 [TEGRA_POWERGATE_PCIE] = "pcie", 3848 [TEGRA_POWERGATE_MPE] = "mpe", 3849 [TEGRA_POWERGATE_SATA] = "sata", 3850 [TEGRA_POWERGATE_CPU1] = "cpu1", 3851 [TEGRA_POWERGATE_CPU2] = "cpu2", 3852 [TEGRA_POWERGATE_CPU3] = "cpu3", 3853 [TEGRA_POWERGATE_CPU0] = "cpu0", 3854 [TEGRA_POWERGATE_C0NC] = "c0nc", 3855 [TEGRA_POWERGATE_SOR] = "sor", 3856 [TEGRA_POWERGATE_DIS] = "dis", 3857 [TEGRA_POWERGATE_DISB] = "disb", 3858 [TEGRA_POWERGATE_XUSBA] = "xusba", 3859 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3860 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3861 [TEGRA_POWERGATE_VIC] = "vic", 3862 [TEGRA_POWERGATE_IRAM] = "iram", 3863 [TEGRA_POWERGATE_NVDEC] = "nvdec", 3864 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 3865 [TEGRA_POWERGATE_AUD] = "aud", 3866 [TEGRA_POWERGATE_DFD] = "dfd", 3867 [TEGRA_POWERGATE_VE2] = "ve2", 3868 }; 3869 3870 static const u8 tegra210_cpu_powergates[] = { 3871 TEGRA_POWERGATE_CPU0, 3872 TEGRA_POWERGATE_CPU1, 3873 TEGRA_POWERGATE_CPU2, 3874 TEGRA_POWERGATE_CPU3, 3875 }; 3876 3877 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 3878 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, "audio"), 3879 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, "audio-hv"), 3880 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, "cam"), 3881 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, "csia"), 3882 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, "csib"), 3883 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 10, 0x1c0, 0x1c4, "csic"), 3884 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 11, 0x1c0, 0x1c4, "csid"), 3885 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, "csie"), 3886 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 13, 0x1c0, 0x1c4, "csif"), 3887 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x1b8, 0x1bc, "dbg"), 3888 TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, "debug-nonao"), 3889 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC, 18, 0x1c0, 0x1c4, "dmic"), 3890 TEGRA_IO_PAD(TEGRA_IO_PAD_DP, 19, 0x1c0, 0x1c4, "dp"), 3891 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, "dsi"), 3892 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, "dsib"), 3893 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, "dsic"), 3894 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, "dsid"), 3895 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC, 3, 0x1c0, 0x1c4, "emmc"), 3896 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC2, 5, 0x1c0, 0x1c4, "emmc2"), 3897 TEGRA_IO_PAD(TEGRA_IO_PAD_GPIO, 27, 0x1b8, 0x1bc, "gpio"), 3898 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, "hdmi"), 3899 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, "hsic"), 3900 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, "lvds"), 3901 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, "mipi-bias"), 3902 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, "pex-bias"), 3903 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, "pex-clk1"), 3904 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, "pex-clk2"), 3905 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, "pex-cntrl"), 3906 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, "sdmmc1"), 3907 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, "sdmmc3"), 3908 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 14, 0x1c0, 0x1c4, "spi"), 3909 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, "spi-hv"), 3910 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, "uart"), 3911 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, "usb0"), 3912 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, "usb1"), 3913 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, "usb2"), 3914 TEGRA_IO_PAD(TEGRA_IO_PAD_USB3, 18, 0x1b8, 0x1bc, "usb3"), 3915 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, "usb-bias"), 3916 }; 3917 3918 static const struct tegra_io_pad_vctrl tegra210_io_pad_vctrls[] = { 3919 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO, PMC_PWR_DET_VALUE, 5), 3920 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO_HV, PMC_PWR_DET_VALUE, 18), 3921 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_CAM, PMC_PWR_DET_VALUE, 10), 3922 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_DBG, PMC_PWR_DET_VALUE, 19), 3923 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_DMIC, PMC_PWR_DET_VALUE, 20), 3924 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_GPIO, PMC_PWR_DET_VALUE, 21), 3925 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_PEX_CNTRL, PMC_PWR_DET_VALUE, 11), 3926 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1, PMC_PWR_DET_VALUE, 12), 3927 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC3, PMC_PWR_DET_VALUE, 13), 3928 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SPI, PMC_PWR_DET_VALUE, 22), 3929 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SPI_HV, PMC_PWR_DET_VALUE, 23), 3930 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_UART, PMC_PWR_DET_VALUE, 2), 3931 }; 3932 static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 3933 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3934 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 3935 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3936 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3937 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3938 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 3939 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 3940 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3941 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 3942 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 3943 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"), 3944 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC, "dmic"), 3945 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DP, "dp"), 3946 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3947 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3948 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3949 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3950 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC, "emmc"), 3951 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC2, "emmc2"), 3952 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GPIO, "gpio"), 3953 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"), 3954 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3955 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"), 3956 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3957 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"), 3958 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3959 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3960 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3961 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), 3962 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"), 3963 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 3964 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"), 3965 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3966 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3967 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3968 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3969 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB3, "usb3"), 3970 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"), 3971 }; 3972 3973 static const char * const tegra210_reset_sources[] = { 3974 "POWER_ON_RESET", 3975 "WATCHDOG", 3976 "SENSOR", 3977 "SW_MAIN", 3978 "LP0", 3979 "AOTAG" 3980 }; 3981 3982 static const struct tegra_wake_event tegra210_wake_events[] = { 3983 TEGRA_WAKE_IRQ("rtc", 16, 2), 3984 TEGRA_WAKE_IRQ("pmu", 51, 86), 3985 }; 3986 3987 static const struct tegra_pmc_soc tegra210_pmc_soc = { 3988 .supports_core_domain = false, 3989 .num_powergates = ARRAY_SIZE(tegra210_powergates), 3990 .powergates = tegra210_powergates, 3991 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 3992 .cpu_powergates = tegra210_cpu_powergates, 3993 .has_tsense_reset = true, 3994 .has_gpu_clamps = true, 3995 .needs_mbist_war = true, 3996 .has_io_pad_wren = true, 3997 .maybe_tz_only = true, 3998 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 3999 .io_pads = tegra210_io_pads, 4000 .num_io_pad_vctrls = ARRAY_SIZE(tegra210_io_pad_vctrls), 4001 .io_pad_vctrls = tegra210_io_pad_vctrls, 4002 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 4003 .pin_descs = tegra210_pin_descs, 4004 .regs = &tegra20_pmc_regs, 4005 .init = tegra20_pmc_init, 4006 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 4007 .powergate_set = tegra114_powergate_set, 4008 .irq_set_wake = tegra210_pmc_irq_set_wake, 4009 .irq_set_type = tegra210_pmc_irq_set_type, 4010 .reset_sources = tegra210_reset_sources, 4011 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), 4012 .reset_levels = NULL, 4013 .num_reset_levels = 0, 4014 .num_wake_events = ARRAY_SIZE(tegra210_wake_events), 4015 .wake_events = tegra210_wake_events, 4016 .pmc_clks_data = tegra_pmc_clks_data, 4017 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 4018 .has_blink_output = true, 4019 .has_usb_sleepwalk = true, 4020 .has_single_mmio_aperture = true, 4021 }; 4022 4023 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 4024 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, "csia"), 4025 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, "csib"), 4026 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x74, 0x78, "dsi"), 4027 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, "mipi-bias"), 4028 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, "pex-clk-bias"), 4029 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, "pex-clk3"), 4030 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, "pex-clk2"), 4031 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, "pex-clk1"), 4032 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x74, 0x78, "usb0"), 4033 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x74, 0x78, "usb1"), 4034 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x74, 0x78, "usb2"), 4035 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, "usb-bias"), 4036 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, "uart"), 4037 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, "audio"), 4038 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x74, 0x78, "hsic"), 4039 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, "dbg"), 4040 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, "hdmi-dp0"), 4041 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, "hdmi-dp1"), 4042 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, "pex-cntrl"), 4043 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, "sdmmc2-hv"), 4044 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, "sdmmc4"), 4045 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, "cam"), 4046 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 8, 0x7c, 0x80, "dsib"), 4047 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 9, 0x7c, 0x80, "dsic"), 4048 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 10, 0x7c, 0x80, "dsid"), 4049 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, "csic"), 4050 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, "csid"), 4051 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, "csie"), 4052 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, "csif"), 4053 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, "spi"), 4054 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, "ufs"), 4055 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, "dmic-hv"), 4056 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, "edp"), 4057 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, "sdmmc1-hv"), 4058 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, "sdmmc3-hv"), 4059 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, "conn"), 4060 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, "audio-hv"), 4061 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, "ao-hv"), 4062 }; 4063 4064 static const struct tegra_io_pad_vctrl tegra186_io_pad_vctrls[] = { 4065 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC2_HV, PMC_IMPL_E_33V_PWR, 5), 4066 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_DMIC_HV, PMC_IMPL_E_33V_PWR, 2), 4067 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1_HV, PMC_IMPL_E_33V_PWR, 4), 4068 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC3_HV, PMC_IMPL_E_33V_PWR, 6), 4069 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO_HV, PMC_IMPL_E_33V_PWR, 1), 4070 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AO_HV, PMC_IMPL_E_33V_PWR, 0), 4071 }; 4072 4073 static const struct pinctrl_pin_desc tegra186_pin_descs[] = { 4074 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 4075 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 4076 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 4077 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 4078 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"), 4079 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"), 4080 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 4081 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 4082 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 4083 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 4084 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 4085 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"), 4086 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 4087 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 4088 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 4089 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 4090 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4091 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"), 4092 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 4093 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC2_HV, "sdmmc2-hv"), 4094 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 4095 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 4096 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 4097 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 4098 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 4099 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4100 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4101 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4102 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4103 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 4104 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4105 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC_HV, "dmic-hv"), 4106 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4107 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4108 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4109 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"), 4110 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4111 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4112 }; 4113 4114 static const struct tegra_pmc_regs tegra186_pmc_regs = { 4115 .scratch0 = 0x2000, 4116 .rst_status = 0x70, 4117 .rst_source_shift = 0x2, 4118 .rst_source_mask = 0x3c, 4119 .rst_level_shift = 0x0, 4120 .rst_level_mask = 0x3, 4121 .aowake_mask_w = 0x180, 4122 .aowake_status_w = 0x30c, 4123 .aowake_status_r = 0x48c, 4124 .aowake_tier2_routing = 0x4cc, 4125 .aowake_sw_status_w = 0x49c, 4126 .aowake_sw_status = 0x4a0, 4127 .aowake_latch_sw = 0x498, 4128 .aowake_ctrl = 0x4f4, 4129 }; 4130 4131 static void tegra186_pmc_init(struct tegra_pmc *pmc) 4132 { 4133 pmc->syscore.ops = &tegra186_pmc_wake_syscore_ops; 4134 pmc->syscore.data = pmc; 4135 register_syscore(&pmc->syscore); 4136 } 4137 4138 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 4139 struct device_node *np, 4140 bool invert) 4141 { 4142 struct resource regs; 4143 void __iomem *wake; 4144 u32 value; 4145 int index; 4146 4147 index = of_property_match_string(np, "reg-names", "wake"); 4148 if (index < 0) { 4149 dev_err(pmc->dev, "failed to find PMC wake registers\n"); 4150 return; 4151 } 4152 4153 of_address_to_resource(np, index, ®s); 4154 4155 wake = ioremap(regs.start, resource_size(®s)); 4156 if (!wake) { 4157 dev_err(pmc->dev, "failed to map PMC wake registers\n"); 4158 return; 4159 } 4160 4161 value = readl(wake + pmc->soc->regs->aowake_ctrl); 4162 4163 if (invert) 4164 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 4165 else 4166 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 4167 4168 writel(value, wake + pmc->soc->regs->aowake_ctrl); 4169 4170 iounmap(wake); 4171 } 4172 4173 static const char * const tegra186_reset_sources[] = { 4174 "SYS_RESET", 4175 "AOWDT", 4176 "MCCPLEXWDT", 4177 "BPMPWDT", 4178 "SCEWDT", 4179 "SPEWDT", 4180 "APEWDT", 4181 "BCCPLEXWDT", 4182 "SENSOR", 4183 "AOTAG", 4184 "VFSENSOR", 4185 "SWREST", 4186 "SC7", 4187 "HSM", 4188 "CORESIGHT" 4189 }; 4190 4191 static const char * const tegra186_reset_levels[] = { 4192 "L0", "L1", "L2", "WARM" 4193 }; 4194 4195 static const struct tegra_wake_event tegra186_wake_events[] = { 4196 TEGRA_WAKE_IRQ("pmu", 24, 209), 4197 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)), 4198 TEGRA_WAKE_IRQ("rtc", 73, 10), 4199 }; 4200 4201 static const struct tegra_pmc_soc tegra186_pmc_soc = { 4202 .supports_core_domain = false, 4203 .num_powergates = 0, 4204 .powergates = NULL, 4205 .num_cpu_powergates = 0, 4206 .cpu_powergates = NULL, 4207 .has_tsense_reset = false, 4208 .has_gpu_clamps = false, 4209 .needs_mbist_war = false, 4210 .has_io_pad_wren = false, 4211 .maybe_tz_only = false, 4212 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 4213 .io_pads = tegra186_io_pads, 4214 .num_io_pad_vctrls = ARRAY_SIZE(tegra186_io_pad_vctrls), 4215 .io_pad_vctrls = tegra186_io_pad_vctrls, 4216 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), 4217 .pin_descs = tegra186_pin_descs, 4218 .regs = &tegra186_pmc_regs, 4219 .init = tegra186_pmc_init, 4220 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4221 .set_wake_filters = tegra186_pmc_set_wake_filters, 4222 .irq_set_wake = tegra186_pmc_irq_set_wake, 4223 .irq_set_type = tegra186_pmc_irq_set_type, 4224 .reset_sources = tegra186_reset_sources, 4225 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), 4226 .reset_levels = tegra186_reset_levels, 4227 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4228 .num_wake_events = ARRAY_SIZE(tegra186_wake_events), 4229 .wake_events = tegra186_wake_events, 4230 .max_wake_events = 96, 4231 .max_wake_vectors = 3, 4232 .pmc_clks_data = NULL, 4233 .num_pmc_clks = 0, 4234 .has_blink_output = false, 4235 .has_usb_sleepwalk = false, 4236 .has_single_mmio_aperture = false, 4237 }; 4238 4239 static const struct tegra_io_pad_soc tegra194_io_pads[] = { 4240 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, "csia"), 4241 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, "csib"), 4242 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, "mipi-bias"), 4243 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, "pex-clk-bias"), 4244 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, "pex-clk3"), 4245 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, "pex-clk2"), 4246 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, "pex-clk1"), 4247 TEGRA_IO_PAD(TEGRA_IO_PAD_EQOS, 8, 0x74, 0x78, "eqos"), 4248 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, "pex-clk-2-bias"), 4249 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, "pex-clk-2"), 4250 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP3, 11, 0x74, 0x78, "dap3"), 4251 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP5, 12, 0x74, 0x78, "dap5"), 4252 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, "uart"), 4253 TEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, "pwr-ctl"), 4254 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, "soc-gpio53"), 4255 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, "audio"), 4256 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, "gp-pwm2"), 4257 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, "gp-pwm3"), 4258 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, "soc-gpio12"), 4259 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, "soc-gpio13"), 4260 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, "soc-gpio10"), 4261 TEGRA_IO_PAD(TEGRA_IO_PAD_UART4, 23, 0x74, 0x78, "uart4"), 4262 TEGRA_IO_PAD(TEGRA_IO_PAD_UART5, 24, 0x74, 0x78, "uart5"), 4263 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, "dbg"), 4264 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, "hdmi-dp3"), 4265 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, "hdmi-dp2"), 4266 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, "hdmi-dp0"), 4267 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, "hdmi-dp1"), 4268 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, "pex-cntrl"), 4269 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, "pex-ctl2"), 4270 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, "pex-l0-rst"), 4271 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, "pex-l1-rst"), 4272 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, "sdmmc4"), 4273 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, "pex-l5-rst"), 4274 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, "cam"), 4275 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, "csic"), 4276 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, "csid"), 4277 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, "csie"), 4278 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, "csif"), 4279 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, "spi"), 4280 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, "ufs"), 4281 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 18, 0x7c, 0x80, "csig"), 4282 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 19, 0x7c, 0x80, "csih"), 4283 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, "edp"), 4284 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, "sdmmc1-hv"), 4285 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, "sdmmc3-hv"), 4286 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, "conn"), 4287 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, "audio-hv"), 4288 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, "ao-hv"), 4289 }; 4290 4291 static const struct tegra_io_pad_vctrl tegra194_io_pad_vctrls[] = { 4292 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1_HV, PMC_IMPL_E_33V_PWR, 4), 4293 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC3_HV, PMC_IMPL_E_33V_PWR, 6), 4294 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO_HV, PMC_IMPL_E_33V_PWR, 1), 4295 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AO_HV, PMC_IMPL_E_33V_PWR, 0), 4296 }; 4297 4298 static const struct pinctrl_pin_desc tegra194_pin_descs[] = { 4299 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 4300 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 4301 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 4302 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"), 4303 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"), 4304 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 4305 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 4306 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EQOS, "eqos"), 4307 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2_BIAS, "pex-clk-2-bias"), 4308 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2, "pex-clk-2"), 4309 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP3, "dap3"), 4310 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP5, "dap5"), 4311 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 4312 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PWR_CTL, "pwr-ctl"), 4313 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO53, "soc-gpio53"), 4314 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 4315 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM2, "gp-pwm2"), 4316 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM3, "gp-pwm3"), 4317 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO12, "soc-gpio12"), 4318 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO13, "soc-gpio13"), 4319 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO10, "soc-gpio10"), 4320 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART4, "uart4"), 4321 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART5, "uart5"), 4322 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 4323 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP3, "hdmi-dp3"), 4324 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP2, "hdmi-dp2"), 4325 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4326 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"), 4327 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 4328 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"), 4329 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L0_RST, "pex-l0-rst"), 4330 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L1_RST, "pex-l1-rst"), 4331 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 4332 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L5_RST, "pex-l5-rst"), 4333 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 4334 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4335 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4336 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4337 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4338 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 4339 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4340 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), 4341 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), 4342 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4343 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4344 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4345 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"), 4346 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4347 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4348 }; 4349 4350 static const struct tegra_pmc_regs tegra194_pmc_regs = { 4351 .scratch0 = 0x2000, 4352 .rst_status = 0x70, 4353 .rst_source_shift = 0x2, 4354 .rst_source_mask = 0x7c, 4355 .rst_level_shift = 0x0, 4356 .rst_level_mask = 0x3, 4357 .aowake_mask_w = 0x180, 4358 .aowake_status_w = 0x30c, 4359 .aowake_status_r = 0x48c, 4360 .aowake_tier2_routing = 0x4cc, 4361 .aowake_sw_status_w = 0x49c, 4362 .aowake_sw_status = 0x4a0, 4363 .aowake_latch_sw = 0x498, 4364 .aowake_ctrl = 0x4f4, 4365 }; 4366 4367 static const char * const tegra194_reset_sources[] = { 4368 "SYS_RESET_N", 4369 "AOWDT", 4370 "BCCPLEXWDT", 4371 "BPMPWDT", 4372 "SCEWDT", 4373 "SPEWDT", 4374 "APEWDT", 4375 "LCCPLEXWDT", 4376 "SENSOR", 4377 "AOTAG", 4378 "VFSENSOR", 4379 "MAINSWRST", 4380 "SC7", 4381 "HSM", 4382 "CSITE", 4383 "RCEWDT", 4384 "PVA0WDT", 4385 "PVA1WDT", 4386 "L1A_ASYNC", 4387 "BPMPBOOT", 4388 "FUSECRC", 4389 }; 4390 4391 static const struct tegra_wake_event tegra194_wake_events[] = { 4392 TEGRA_WAKE_GPIO("eqos", 20, 0, TEGRA194_MAIN_GPIO(G, 4)), 4393 TEGRA_WAKE_IRQ("pmu", 24, 209), 4394 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)), 4395 TEGRA_WAKE_IRQ("rtc", 73, 10), 4396 TEGRA_WAKE_SIMPLE("usb3-port-0", 76), 4397 TEGRA_WAKE_SIMPLE("usb3-port-1", 77), 4398 TEGRA_WAKE_SIMPLE("usb3-port-2-3", 78), 4399 TEGRA_WAKE_SIMPLE("usb2-port-0", 79), 4400 TEGRA_WAKE_SIMPLE("usb2-port-1", 80), 4401 TEGRA_WAKE_SIMPLE("usb2-port-2", 81), 4402 TEGRA_WAKE_SIMPLE("usb2-port-3", 82), 4403 }; 4404 4405 static const struct tegra_pmc_soc tegra194_pmc_soc = { 4406 .supports_core_domain = false, 4407 .num_powergates = 0, 4408 .powergates = NULL, 4409 .num_cpu_powergates = 0, 4410 .cpu_powergates = NULL, 4411 .has_tsense_reset = false, 4412 .has_gpu_clamps = false, 4413 .needs_mbist_war = false, 4414 .has_io_pad_wren = false, 4415 .maybe_tz_only = false, 4416 .num_io_pads = ARRAY_SIZE(tegra194_io_pads), 4417 .io_pads = tegra194_io_pads, 4418 .num_io_pad_vctrls = ARRAY_SIZE(tegra194_io_pad_vctrls), 4419 .io_pad_vctrls = tegra194_io_pad_vctrls, 4420 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs), 4421 .pin_descs = tegra194_pin_descs, 4422 .regs = &tegra194_pmc_regs, 4423 .init = tegra186_pmc_init, 4424 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4425 .set_wake_filters = tegra186_pmc_set_wake_filters, 4426 .irq_set_wake = tegra186_pmc_irq_set_wake, 4427 .irq_set_type = tegra186_pmc_irq_set_type, 4428 .reset_sources = tegra194_reset_sources, 4429 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources), 4430 .reset_levels = tegra186_reset_levels, 4431 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4432 .num_wake_events = ARRAY_SIZE(tegra194_wake_events), 4433 .wake_events = tegra194_wake_events, 4434 .max_wake_events = 96, 4435 .max_wake_vectors = 3, 4436 .pmc_clks_data = NULL, 4437 .num_pmc_clks = 0, 4438 .has_blink_output = false, 4439 .has_usb_sleepwalk = false, 4440 .has_single_mmio_aperture = false, 4441 }; 4442 4443 static const struct tegra_io_pad_soc tegra234_io_pads[] = { 4444 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0xe0c0, 0xe0c4, "csia"), 4445 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0xe0c0, 0xe0c4, "csib"), 4446 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, "hdmi-dp0"), 4447 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0xe0c0, 0xe0c4, "csic"), 4448 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0xe0c0, 0xe0c4, "csid"), 4449 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0xe0c0, 0xe0c4, "csie"), 4450 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0xe0c0, 0xe0c4, "csif"), 4451 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe064, 0xe068, "ufs"), 4452 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 1, 0xe05c, 0xe060, "edp"), 4453 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, "sdmmc1-hv"), 4454 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, "sdmmc3-hv"), 4455 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, "audio-hv"), 4456 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, "ao-hv"), 4457 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0xe0c0, 0xe0c4, "csig"), 4458 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0xe0c0, 0xe0c4, "csih"), 4459 }; 4460 4461 static const struct tegra_io_pad_vctrl tegra234_io_pad_vctrls[] = { 4462 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1_HV, PMC_IMPL_E_33V_PWR, 4), 4463 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC3_HV, PMC_IMPL_E_33V_PWR, 6), 4464 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO_HV, PMC_IMPL_E_33V_PWR, 1), 4465 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AO_HV, PMC_IMPL_E_33V_PWR, 0), 4466 }; 4467 4468 static const struct pinctrl_pin_desc tegra234_pin_descs[] = { 4469 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 4470 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 4471 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4472 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4473 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4474 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4475 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4476 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4477 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4478 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4479 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4480 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4481 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4482 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), 4483 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), 4484 }; 4485 4486 static const struct tegra_pmc_regs tegra234_pmc_regs = { 4487 .scratch0 = 0x2000, 4488 .rst_status = 0x70, 4489 .rst_source_shift = 0x2, 4490 .rst_source_mask = 0xfc, 4491 .rst_level_shift = 0x0, 4492 .rst_level_mask = 0x3, 4493 .aowake_mask_w = 0x180, 4494 .aowake_status_w = 0x30c, 4495 .aowake_status_r = 0x48c, 4496 .aowake_tier2_routing = 0x4cc, 4497 .aowake_sw_status_w = 0x49c, 4498 .aowake_sw_status = 0x4a0, 4499 .aowake_latch_sw = 0x498, 4500 .aowake_ctrl = 0x4f4, 4501 }; 4502 4503 static const char * const tegra234_reset_sources[] = { 4504 "SYS_RESET_N", /* 0x0 */ 4505 "AOWDT", 4506 "BCCPLEXWDT", 4507 "BPMPWDT", 4508 "SCEWDT", 4509 "SPEWDT", 4510 "APEWDT", 4511 "LCCPLEXWDT", 4512 "SENSOR", /* 0x8 */ 4513 NULL, 4514 NULL, 4515 "MAINSWRST", 4516 "SC7", 4517 "HSM", 4518 NULL, 4519 "RCEWDT", 4520 NULL, /* 0x10 */ 4521 NULL, 4522 NULL, 4523 "BPMPBOOT", 4524 "FUSECRC", 4525 "DCEWDT", 4526 "PSCWDT", 4527 "PSC", 4528 "CSITE_SW", /* 0x18 */ 4529 "POD", 4530 "SCPM", 4531 "VREFRO_POWERBAD", 4532 "VMON", 4533 "FMON", 4534 "FSI_R5WDT", 4535 "FSI_THERM", 4536 "FSI_R52C0WDT", /* 0x20 */ 4537 "FSI_R52C1WDT", 4538 "FSI_R52C2WDT", 4539 "FSI_R52C3WDT", 4540 "FSI_FMON", 4541 "FSI_VMON", /* 0x25 */ 4542 }; 4543 4544 static const struct tegra_wake_event tegra234_wake_events[] = { 4545 TEGRA_WAKE_GPIO("sd-wake", 8, 0, TEGRA234_MAIN_GPIO(G, 7)), 4546 TEGRA_WAKE_GPIO("eqos", 20, 0, TEGRA234_MAIN_GPIO(G, 4)), 4547 TEGRA_WAKE_IRQ("pmu", 24, 209), 4548 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), 4549 TEGRA_WAKE_GPIO("mgbe", 56, 0, TEGRA234_MAIN_GPIO(Y, 3)), 4550 TEGRA_WAKE_IRQ("rtc", 73, 10), 4551 TEGRA_WAKE_IRQ("usb3-port-0", 76, 167), 4552 TEGRA_WAKE_IRQ("usb3-port-1", 77, 167), 4553 TEGRA_WAKE_IRQ("usb3-port-2-3", 78, 167), 4554 TEGRA_WAKE_IRQ("usb2-port-0", 79, 167), 4555 TEGRA_WAKE_IRQ("usb2-port-1", 80, 167), 4556 TEGRA_WAKE_IRQ("usb2-port-2", 81, 167), 4557 TEGRA_WAKE_IRQ("usb2-port-3", 82, 167), 4558 TEGRA_WAKE_IRQ("sw-wake", SW_WAKE_ID, 179), 4559 }; 4560 4561 static const struct tegra_pmc_soc tegra234_pmc_soc = { 4562 .supports_core_domain = false, 4563 .num_powergates = 0, 4564 .powergates = NULL, 4565 .num_cpu_powergates = 0, 4566 .cpu_powergates = NULL, 4567 .has_tsense_reset = false, 4568 .has_gpu_clamps = false, 4569 .needs_mbist_war = false, 4570 .has_io_pad_wren = false, 4571 .maybe_tz_only = false, 4572 .num_io_pads = ARRAY_SIZE(tegra234_io_pads), 4573 .io_pads = tegra234_io_pads, 4574 .num_io_pad_vctrls = ARRAY_SIZE(tegra234_io_pad_vctrls), 4575 .io_pad_vctrls = tegra234_io_pad_vctrls, 4576 .num_pin_descs = ARRAY_SIZE(tegra234_pin_descs), 4577 .pin_descs = tegra234_pin_descs, 4578 .regs = &tegra234_pmc_regs, 4579 .init = tegra186_pmc_init, 4580 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4581 .set_wake_filters = tegra186_pmc_set_wake_filters, 4582 .irq_set_wake = tegra186_pmc_irq_set_wake, 4583 .irq_set_type = tegra186_pmc_irq_set_type, 4584 .reset_sources = tegra234_reset_sources, 4585 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources), 4586 .reset_levels = tegra186_reset_levels, 4587 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4588 .num_wake_events = ARRAY_SIZE(tegra234_wake_events), 4589 .wake_events = tegra234_wake_events, 4590 .max_wake_events = 96, 4591 .max_wake_vectors = 3, 4592 .pmc_clks_data = NULL, 4593 .num_pmc_clks = 0, 4594 .has_blink_output = false, 4595 .has_single_mmio_aperture = false, 4596 }; 4597 4598 #define TEGRA264_IO_PAD_VCTRL(_id, _offset, _ena_3v3, _ena_1v8) \ 4599 ((struct tegra_io_pad_vctrl) { \ 4600 .id = (_id), \ 4601 .offset = (_offset), \ 4602 .ena_3v3 = (_ena_3v3), \ 4603 .ena_1v8 = (_ena_1v8), \ 4604 }) 4605 4606 static const struct tegra_io_pad_soc tegra264_io_pads[] = { 4607 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x41020, 0x41024, "csia"), 4608 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x41020, 0x41024, "csib"), 4609 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0x41050, 0x41054, "hdmi-dp0"), 4610 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0x41020, 0x41024, "csic"), 4611 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0x41020, 0x41024, "csid"), 4612 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0x41020, 0x41024, "csie"), 4613 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0x41020, 0x41024, "csif"), 4614 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 4, 0x41040, 0x41044, "ufs0"), 4615 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 0, 0x41028, 0x4102c, "edp"), 4616 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 0, 0x41090, 0x41094, "sdmmc1"), 4617 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, UINT_MAX, UINT_MAX, UINT_MAX, "sdmmc1-hv"), 4618 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0x41020, 0x41024, "csig"), 4619 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0x41020, 0x41024, "csih"), 4620 }; 4621 4622 static const struct tegra_io_pad_vctrl tegra264_io_pad_vctrls[] = { 4623 TEGRA264_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1_HV, PMC_IMPL_SDMMC1_HV_PADCTL_0, 0, 0x6), 4624 }; 4625 4626 static const struct pinctrl_pin_desc tegra264_pin_descs[] = { 4627 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 4628 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 4629 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4630 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4631 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4632 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4633 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4634 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs0"), 4635 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4636 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), 4637 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4638 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), 4639 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), 4640 }; 4641 4642 static const struct tegra_pmc_regs tegra264_pmc_regs = { 4643 .scratch0 = 0x684, 4644 .rst_status = 0x4, 4645 .rst_source_shift = 0x2, 4646 .rst_source_mask = 0x1fc, 4647 .rst_level_shift = 0x0, 4648 .rst_level_mask = 0x3, 4649 .aowake_mask_w = 0x200, 4650 .aowake_status_w = 0x410, 4651 .aowake_status_r = 0x610, 4652 .aowake_tier2_routing = 0x660, 4653 .aowake_sw_status_w = 0x624, 4654 .aowake_sw_status = 0x628, 4655 .aowake_latch_sw = 0x620, 4656 .aowake_ctrl = 0x68c, 4657 }; 4658 4659 static const char * const tegra264_reset_sources[] = { 4660 "SYS_RESET_N", /* 0x0 */ 4661 "CSDC_RTC_XTAL", 4662 "VREFRO_POWER_BAD", 4663 "SCPM_SOC_XTAL", 4664 "SCPM_RTC_XTAL", 4665 "FMON_32K", 4666 "FMON_OSC", 4667 "POD_RTC", 4668 "POD_IO", /* 0x8 */ 4669 "POD_PLUS_IO_SPLL", 4670 "POD_PLUS_SOC", 4671 "VMON_PLUS_UV", 4672 "VMON_PLUS_OV", 4673 "FUSECRC_FAULT", 4674 "OSC_FAULT", 4675 "BPMP_BOOT_FAULT", 4676 "SCPM_BPMP_CORE_CLK", /* 0x10 */ 4677 "SCPM_PSC_SE_CLK", 4678 "VMON_SOC_MIN", 4679 "VMON_SOC_MAX", 4680 "VMON_MSS_MIN", 4681 "VMON_MSS_MAX", 4682 "POD_PLUS_IO_VMON", 4683 "NVJTAG_SEL_MONITOR", 4684 "NV_THERM_FAULT", /* 0x18 */ 4685 "FSI_THERM_FAULT", 4686 "PSC_SW", 4687 "SCPM_OESP_SE_CLK", 4688 "SCPM_SB_SE_CLK", 4689 "POD_CPU", 4690 "POD_GPU", 4691 "DCLS_GPU", 4692 "POD_MSS", /* 0x20 */ 4693 "FMON_FSI", 4694 "POD_FSI", 4695 "VMON_FSI_MIN", 4696 "VMON_FSI_MAX", 4697 "VMON_CPU0_MIN", 4698 "VMON_CPU0_MAX", 4699 "BPMP_FMON", 4700 "AO_WDT_POR", /* 0x28 */ 4701 "BPMP_WDT_POR", 4702 "AO_TKE_WDT_POR", 4703 "RCE0_WDT_POR", 4704 "RCE1_WDT_POR", 4705 "DCE_WDT_POR", 4706 "FSI_R5_WDT_POR", 4707 "FSI_R52_0_WDT_POR", 4708 "FSI_R52_1_WDT_POR", /* 0x30 */ 4709 "FSI_R52_2_WDT_POR", 4710 "FSI_R52_3_WDT_POR", 4711 "TOP_0_WDT_POR", 4712 "TOP_1_WDT_POR", 4713 "TOP_2_WDT_POR", 4714 "APE_C0_WDT_POR", 4715 "APE_C1_WDT_POR", 4716 "GPU_TKE_WDT_POR", /* 0x38 */ 4717 "PSC_WDT_POR", 4718 "OESP_WDT_POR", 4719 "SB_WDT_POR", 4720 "SW_MAIN", 4721 "L0L1_RST_OUT_N", 4722 "FSI_HSM", 4723 "CSITE_SW", 4724 "AO_WDT_DBG", /* 0x40 */ 4725 "BPMP_WDT_DBG", 4726 "AO_TKE_WDT_DBG", 4727 "RCE0_WDT_DBG", 4728 "RCE1_WDT_DBG", 4729 "DCE_WDT_DBG", 4730 "FSI_R5_WDT_DBG", 4731 "FSI_R52_0_WDT_DBG", 4732 "FSI_R52_1_WDT_DBG", /* 0x48 */ 4733 "FSI_R52_2_WDT_DBG", 4734 "FSI_R52_3_WDT_DBG", 4735 "TOP_0_WDT_DBG", 4736 "TOP_1_WDT_DBG", 4737 "TOP_2_WDT_DBG", 4738 "APE_C0_WDT_DBG", 4739 "APE_C1_WDT_DBG", 4740 "PSC_WDT_DBG", /* 0x50 */ 4741 "OESP_WDT_DBG", 4742 "SB_WDT_DBG", 4743 "TSC_0_WDT_DBG", 4744 "TSC_1_WDT_DBG", 4745 "L2_RST_OUT_N", 4746 "SC7" 4747 }; 4748 4749 static const struct tegra_wake_event tegra264_wake_events[] = { 4750 TEGRA_WAKE_IRQ("pmu", 0, 727), 4751 TEGRA_WAKE_GPIO("power", 5, 1, TEGRA264_AON_GPIO(AA, 5)), 4752 TEGRA_WAKE_IRQ("rtc", 65, 548), 4753 TEGRA_WAKE_IRQ("usb3-port-0", 79, 965), 4754 TEGRA_WAKE_IRQ("usb3-port-1", 80, 965), 4755 TEGRA_WAKE_IRQ("usb3-port-3", 82, 965), 4756 TEGRA_WAKE_IRQ("usb2-port-0", 83, 965), 4757 TEGRA_WAKE_IRQ("usb2-port-1", 84, 965), 4758 TEGRA_WAKE_IRQ("usb2-port-2", 85, 965), 4759 TEGRA_WAKE_IRQ("usb2-port-3", 86, 965), 4760 }; 4761 4762 static const struct tegra_pmc_soc tegra264_pmc_soc = { 4763 .has_io_pad_wren = false, 4764 .num_io_pads = ARRAY_SIZE(tegra264_io_pads), 4765 .io_pads = tegra264_io_pads, 4766 .num_io_pad_vctrls = ARRAY_SIZE(tegra264_io_pad_vctrls), 4767 .io_pad_vctrls = tegra264_io_pad_vctrls, 4768 .num_pin_descs = ARRAY_SIZE(tegra264_pin_descs), 4769 .pin_descs = tegra264_pin_descs, 4770 .regs = &tegra264_pmc_regs, 4771 .init = tegra186_pmc_init, 4772 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4773 .set_wake_filters = tegra186_pmc_set_wake_filters, 4774 .irq_set_wake = tegra186_pmc_irq_set_wake, 4775 .irq_set_type = tegra186_pmc_irq_set_type, 4776 .reset_sources = tegra264_reset_sources, 4777 .num_reset_sources = ARRAY_SIZE(tegra264_reset_sources), 4778 .reset_levels = tegra186_reset_levels, 4779 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4780 .wake_events = tegra264_wake_events, 4781 .num_wake_events = ARRAY_SIZE(tegra264_wake_events), 4782 .max_wake_events = 128, 4783 .max_wake_vectors = 4, 4784 }; 4785 4786 static const struct of_device_id tegra_pmc_match[] = { 4787 { .compatible = "nvidia,tegra264-pmc", .data = &tegra264_pmc_soc }, 4788 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc }, 4789 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, 4790 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 4791 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 4792 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 4793 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 4794 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 4795 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 4796 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 4797 { } 4798 }; 4799 4800 static void tegra_pmc_sync_state(struct device *dev) 4801 { 4802 struct device_node *np, *child; 4803 int err; 4804 4805 np = of_get_child_by_name(dev->of_node, "powergates"); 4806 if (!np) 4807 return; 4808 4809 for_each_child_of_node(np, child) 4810 of_genpd_sync_state(child); 4811 4812 of_node_put(np); 4813 4814 np = of_get_child_by_name(dev->of_node, "core-domain"); 4815 if (!np) 4816 return; 4817 4818 of_genpd_sync_state(np); 4819 of_node_put(np); 4820 4821 /* 4822 * Newer device-trees have power domains, but we need to prepare all 4823 * device drivers with runtime PM and OPP support first, otherwise 4824 * state syncing is unsafe. 4825 */ 4826 if (!pmc->soc->supports_core_domain) 4827 return; 4828 4829 /* 4830 * Older device-trees don't have core PD, and thus, there are 4831 * no dependencies that will block the state syncing. We shouldn't 4832 * mark the domain as synced in this case. 4833 */ 4834 pmc->core_domain_state_synced = true; 4835 4836 /* this is a no-op if core regulator isn't used */ 4837 mutex_lock(&pmc->powergates_lock); 4838 err = dev_pm_opp_sync_regulators(dev); 4839 mutex_unlock(&pmc->powergates_lock); 4840 4841 if (err) 4842 dev_err(dev, "failed to sync regulators: %d\n", err); 4843 } 4844 4845 static struct platform_driver tegra_pmc_driver = { 4846 .driver = { 4847 .name = "tegra-pmc", 4848 .suppress_bind_attrs = true, 4849 .of_match_table = tegra_pmc_match, 4850 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 4851 .pm = &tegra_pmc_pm_ops, 4852 #endif 4853 .sync_state = tegra_pmc_sync_state, 4854 }, 4855 .probe = tegra_pmc_probe, 4856 }; 4857 builtin_platform_driver(tegra_pmc_driver); 4858 4859 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) 4860 { 4861 u32 value, saved; 4862 4863 saved = readl(pmc->base + pmc->soc->regs->scratch0); 4864 value = saved ^ 0xffffffff; 4865 4866 if (value == 0xffffffff) 4867 value = 0xdeadbeef; 4868 4869 /* write pattern and read it back */ 4870 writel(value, pmc->base + pmc->soc->regs->scratch0); 4871 value = readl(pmc->base + pmc->soc->regs->scratch0); 4872 4873 /* if we read all-zeroes, access is restricted to TZ only */ 4874 if (value == 0) { 4875 pr_info("access to PMC is restricted to TZ\n"); 4876 return true; 4877 } 4878 4879 /* restore original value */ 4880 writel(saved, pmc->base + pmc->soc->regs->scratch0); 4881 4882 return false; 4883 } 4884 4885 /* 4886 * Early initialization to allow access to registers in the very early boot 4887 * process. 4888 */ 4889 static int __init tegra_pmc_early_init(void) 4890 { 4891 const struct of_device_id *match; 4892 struct device_node *np; 4893 struct resource regs; 4894 unsigned int i; 4895 bool invert; 4896 4897 mutex_init(&pmc->powergates_lock); 4898 4899 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 4900 if (!np) { 4901 /* 4902 * Fall back to legacy initialization for 32-bit ARM only. All 4903 * 64-bit ARM device tree files for Tegra are required to have 4904 * a PMC node. 4905 * 4906 * This is for backwards-compatibility with old device trees 4907 * that didn't contain a PMC node. Note that in this case the 4908 * SoC data can't be matched and therefore powergating is 4909 * disabled. 4910 */ 4911 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 4912 pr_warn("DT node not found, powergating disabled\n"); 4913 4914 regs.start = 0x7000e400; 4915 regs.end = 0x7000e7ff; 4916 regs.flags = IORESOURCE_MEM; 4917 4918 pr_warn("Using memory region %pR\n", ®s); 4919 } else { 4920 /* 4921 * At this point we're not running on Tegra, so play 4922 * nice with multi-platform kernels. 4923 */ 4924 return 0; 4925 } 4926 } else { 4927 /* 4928 * Extract information from the device tree if we've found a 4929 * matching node. 4930 */ 4931 if (of_address_to_resource(np, 0, ®s) < 0) { 4932 pr_err("failed to get PMC registers\n"); 4933 of_node_put(np); 4934 return -ENXIO; 4935 } 4936 } 4937 4938 pmc->base = ioremap(regs.start, resource_size(®s)); 4939 if (!pmc->base) { 4940 pr_err("failed to map PMC registers\n"); 4941 of_node_put(np); 4942 return -ENXIO; 4943 } 4944 4945 if (of_device_is_available(np)) { 4946 pmc->soc = match->data; 4947 4948 if (pmc->soc->maybe_tz_only) 4949 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); 4950 4951 /* Create a bitmap of the available and valid partitions */ 4952 for (i = 0; i < pmc->soc->num_powergates; i++) 4953 if (pmc->soc->powergates[i]) 4954 set_bit(i, pmc->powergates_available); 4955 4956 /* 4957 * Invert the interrupt polarity if a PMC device tree node 4958 * exists and contains the nvidia,invert-interrupt property. 4959 */ 4960 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 4961 4962 pmc->soc->setup_irq_polarity(pmc, np, invert); 4963 4964 of_node_put(np); 4965 } 4966 4967 return 0; 4968 } 4969 early_initcall(tegra_pmc_early_init); 4970