/linux/drivers/clk/sprd/ |
H A D | gate.h | 31 #define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument 47 #define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \ argument 54 #define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \ argument 60 #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ argument 66 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument 72 #define SPRD_PLL_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ argument 81 #define SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct, _name, _parent, _reg, \ argument 90 #define SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, \ argument 97 #define SPRD_SC_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument 104 #define SPRD_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument [all …]
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H A D | composite.h | 21 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ argument 35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument 41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument 46 #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \ argument 54 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \ argument 60 #define SPRD_COMP_CLK_DATA_TABLE_OFFSET(_struct, _name, _parent, _reg, \ argument 69 #define SPRD_COMP_CLK_DATA_OFFSET(_struct, _name, _parent, _reg, \ argument
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H A D | mux.h | 40 _reg, _shift, _width, _flags, _fn) \ argument 52 _reg, _shift, _width, _flags) \ argument 57 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \ argument 63 _reg, _shift, _width, _flags) \ argument 68 #define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \ argument
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H A D | div.h | 40 #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _offset, \ argument 52 #define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \ argument 57 #define SPRD_DIV_CLK_FW_NAME(_struct, _name, _parent, _reg, \ argument 62 #define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \ argument
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H A D | pll.h | 64 #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument 85 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ argument 92 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ argument 99 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ argument 105 #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \ argument 112 #define SPRD_PLL_HW(_struct, _name, _parent, _reg, _regs_num, _itable, \ argument
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/linux/drivers/clk/meson/ |
H A D | axg-audio.c | 26 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ argument 40 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \ argument 56 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ argument 72 #define AUD_PCLK_GATE(_name, _reg, _bit) { \ argument 85 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ argument 108 #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ argument 136 #define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \ argument 153 #define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \ argument 188 #define AUD_MST_MUX(_name, _reg, _flag) \ argument 191 #define AUD_MST_DIV(_name, _reg, _flag) \ argument [all …]
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H A D | c3-peripherals.c | 167 #define C3_CLK_GATE(_name, _reg, _bit, _fw_name, _ops, _flags) \ argument 184 #define C3_SYS_GATE(_name, _reg, _bit, _flags) \ argument 188 #define C3_SYS_GATE_RO(_name, _reg, _bit) \ argument 293 #define C3_AXI_GATE(_name, _reg, _bit, _flags) \ argument 532 #define AML_PWM_CLK_MUX(_name, _reg, _shift) { \ argument 546 #define AML_PWM_CLK_DIV(_name, _reg, _shift) { \ argument 561 #define AML_PWM_CLK_GATE(_name, _reg, _bit) { \ argument
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H A D | clk-regmap.h | 117 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument 132 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument 135 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument
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/linux/drivers/clk/sophgo/ |
H A D | clk-cv18xx-pll.h | 50 #define PLL_GET_PRE_DIV_SEL(_reg) \ argument 52 #define PLL_GET_POST_DIV_SEL(_reg) \ argument 54 #define PLL_GET_SEL_MODE(_reg) \ argument 56 #define PLL_GET_DIV_SEL(_reg) \ argument 58 #define PLL_GET_ICTRL(_reg) \ argument 61 #define PLL_SET_PRE_DIV_SEL(_reg, _val) \ argument 63 #define PLL_SET_POST_DIV_SEL(_reg, _val) \ argument 65 #define PLL_SET_SEL_MODE(_reg, _val) \ argument 67 #define PLL_SET_DIV_SEL(_reg, _val) \ argument 69 #define PLL_SET_ICTRL(_reg, _val) \ argument
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H A D | clk-cv18xx-common.h | 45 #define CV1800_CLK_BIT(_reg, _shift) \ argument 51 #define CV1800_CLK_REG(_reg, _shift, _width, _initval, _flags) \ argument 60 #define cv1800_clk_regfield_genmask(_reg) \ argument 62 #define cv1800_clk_regfield_get(_val, _reg) \ argument 64 #define cv1800_clk_regfield_set(_val, _new, _reg) \ argument 68 #define _CV1800_SET_FIELD(_reg, _val, _field) \ argument
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/linux/drivers/clk/sunxi-ng/ |
H A D | ccu_gate.h | 19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument 31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument 43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument 59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument 71 #define SUNXI_CCU_GATE_HWS_WITH_PREDIV(_struct, _name, _parent, _reg, \ argument 86 #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \ argument 99 #define SUNXI_CCU_GATE_DATA_WITH_PREDIV(_struct, _name, _parent, _reg, \ argument
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H A D | ccu_div.h | 87 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument 104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument 111 #define SUNXI_CCU_DIV_TABLE_HW(_struct, _name, _parent, _reg, \ argument 129 _reg, \ argument 148 _reg, \ argument 166 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument 176 _reg, _mshift, _mwidth, \ argument 185 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument 195 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ argument 210 #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ argument [all …]
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H A D | ccu_mp.h | 34 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument 55 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument 74 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument 85 #define SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument 104 #define SUNXI_CCU_MP_DATA_WITH_MUX(_struct, _name, _parents, _reg, \ argument 115 #define SUNXI_CCU_MP_HW_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument 152 #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
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H A D | ccu_mux.h | 50 _reg, _shift, _width, _gate, \ argument 66 _table, _reg, _shift, \ argument 74 _reg, _shift, _width, _gate, \ argument 80 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument 86 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument 91 #define SUNXI_CCU_MUX_DATA_WITH_GATE(_struct, _name, _parents, _reg, \ argument 105 #define SUNXI_CCU_MUX_DATA(_struct, _name, _parents, _reg, \ argument 110 #define SUNXI_CCU_MUX_HW_WITH_GATE(_struct, _name, _parents, _reg, \ argument
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H A D | ccu_nm.h | 38 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ argument 61 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ argument 86 _reg, _min_rate, \ argument 112 _parent, _reg, \ argument 142 _parent, _reg, \ argument 162 _parent, _reg, \ argument 182 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
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/linux/drivers/regulator/ |
H A D | mc13xxx.h | 55 #define MC13xxx_DEFINE(prefix, _name, _node, _reg, _vsel_reg, _voltages, _ops) \ argument 73 #define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument 88 #define MC13xxx_GPO_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument 103 #define MC13xxx_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages, ops) \ argument 105 #define MC13xxx_DEFINE_REGU(_name, _node, _reg, _vsel_reg, _voltages, ops) \ argument
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/linux/arch/mips/include/asm/mach-pic32/ |
H A D | pic32.h | 14 #define PIC32_CLR(_reg) ((_reg) + 0x04) argument 15 #define PIC32_SET(_reg) ((_reg) + 0x08) argument 16 #define PIC32_INV(_reg) ((_reg) + 0x0C) argument
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/linux/drivers/clk/pistachio/ |
H A D | clk.h | 19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument 39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument 59 #define DIV(_id, _name, _pname, _reg, _width) \ argument 69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument 119 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument 130 #define PLL_FIXED(_id, _name, _pname, _type, _reg) \ argument
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/linux/drivers/clk/actions/ |
H A D | owl-gate.h | 27 #define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ argument 34 #define OWL_GATE(_struct, _name, _parent, _reg, \ argument 47 #define OWL_GATE_NO_PARENT(_struct, _name, _reg, \ argument
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H A D | owl-pll.h | 41 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ argument 55 #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ argument 70 #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \ argument 84 #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
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/linux/drivers/net/ethernet/mediatek/ |
H A D | mtk_wed_debugfs.c | 28 #define DUMP_REG(_reg, ...) { #_reg, MTK_##_reg, __VA_ARGS__ } argument 29 #define DUMP_REG_MASK(_reg, _mask) \ argument 37 #define DUMP_WED(_reg) DUMP_REG(_reg, DUMP_TYPE_WED) argument 38 #define DUMP_WED_MASK(_reg, _mask) DUMP_REG_MASK(_reg, _mask) argument 41 #define DUMP_WDMA(_reg) DUMP_REG(_reg, DUMP_TYPE_WDMA) argument
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/linux/drivers/reset/sti/ |
H A D | reset-stih407.c | 57 #define STIH407_SRST_CORE(_reg, _bit) \ argument 60 #define STIH407_SRST_SBC(_reg, _bit) \ argument 63 #define STIH407_SRST_LPM(_reg, _bit) \ argument
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/linux/drivers/clk/mediatek/ |
H A D | clk-mt8167-apmixedsys.c | 22 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument 42 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument 77 #define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \ argument
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H A D | clk-mtk.h | 112 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument 132 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument 141 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument 145 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument 149 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ argument 196 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
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/linux/drivers/net/ethernet/amd/xgbe/ |
H A D | xgbe-common.h | 1502 #define XGMAC_IOREAD(_pdata, _reg) \ argument 1505 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ argument 1510 #define XGMAC_IOWRITE(_pdata, _reg, _val) \ argument 1513 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ argument 1526 #define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \ argument 1530 #define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \ argument 1535 #define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \ argument 1539 #define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \ argument 1552 #define XGMAC_DMA_IOREAD(_channel, _reg) \ argument 1555 #define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \ argument [all …]
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