1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: QPLib resource manager (header) 37 */ 38 39 #ifndef __BNXT_QPLIB_RES_H__ 40 #define __BNXT_QPLIB_RES_H__ 41 42 #include "bnxt_ulp.h" 43 44 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero; 45 46 #define CHIP_NUM_57508 0x1750 47 #define CHIP_NUM_57504 0x1751 48 #define CHIP_NUM_57502 0x1752 49 #define CHIP_NUM_58818 0xd818 50 #define CHIP_NUM_57608 0x1760 51 52 #define BNXT_RE_MAX_QPC_COUNT (64 * 1024) 53 #define BNXT_RE_MAX_MRW_COUNT (64 * 1024) 54 #define BNXT_RE_MAX_SRQC_COUNT (64 * 1024) 55 #define BNXT_RE_MAX_CQ_COUNT (64 * 1024) 56 #define BNXT_RE_MAX_MRW_COUNT_64K (64 * 1024) 57 #define BNXT_RE_MAX_MRW_COUNT_256K (256 * 1024) 58 59 #define BNXT_QPLIB_DBR_VALID (0x1UL << 26) 60 #define BNXT_QPLIB_DBR_EPOCH_SHIFT 24 61 #define BNXT_QPLIB_DBR_TOGGLE_SHIFT 25 62 63 struct bnxt_qplib_drv_modes { 64 u8 wqe_mode; 65 bool db_push; 66 bool dbr_pacing; 67 u32 toggle_bits; 68 }; 69 70 enum bnxt_re_toggle_modes { 71 BNXT_QPLIB_CQ_TOGGLE_BIT = 0x1, 72 BNXT_QPLIB_SRQ_TOGGLE_BIT = 0x2, 73 }; 74 75 struct bnxt_qplib_chip_ctx { 76 u16 chip_num; 77 u8 chip_rev; 78 u8 chip_metal; 79 u16 hw_stats_size; 80 u16 hwrm_cmd_max_timeout; 81 struct bnxt_qplib_drv_modes modes; 82 u64 hwrm_intf_ver; 83 u32 dbr_stat_db_fifo; 84 }; 85 86 struct bnxt_qplib_db_pacing_data { 87 u32 do_pacing; 88 u32 pacing_th; 89 u32 alarm_th; 90 u32 fifo_max_depth; 91 u32 fifo_room_mask; 92 u32 fifo_room_shift; 93 u32 grc_reg_offset; 94 u32 dev_err_state; 95 }; 96 97 #define BNXT_QPLIB_DBR_PF_DB_OFFSET 0x10000 98 #define BNXT_QPLIB_DBR_VF_DB_OFFSET 0x4000 99 100 #define PTR_CNT_PER_PG (PAGE_SIZE / sizeof(void *)) 101 #define PTR_MAX_IDX_PER_PG (PTR_CNT_PER_PG - 1) 102 #define PTR_PG(x) (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG) 103 #define PTR_IDX(x) ((x) & PTR_MAX_IDX_PER_PG) 104 105 #define HWQ_CMP(idx, hwq) ((idx) & ((hwq)->max_elements - 1)) 106 107 #define HWQ_FREE_SLOTS(hwq) (hwq->max_elements - \ 108 ((HWQ_CMP(hwq->prod, hwq)\ 109 - HWQ_CMP(hwq->cons, hwq))\ 110 & (hwq->max_elements - 1))) 111 enum bnxt_qplib_hwq_type { 112 HWQ_TYPE_CTX, 113 HWQ_TYPE_QUEUE, 114 HWQ_TYPE_L2_CMPL, 115 HWQ_TYPE_MR 116 }; 117 118 #define MAX_PBL_LVL_0_PGS 1 119 #define MAX_PBL_LVL_1_PGS 512 120 #define MAX_PBL_LVL_1_PGS_SHIFT 9 121 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2 256 122 #define MAX_PBL_LVL_2_PGS (256 * 512) 123 #define MAX_PDL_LVL_SHIFT 9 124 125 enum bnxt_qplib_pbl_lvl { 126 PBL_LVL_0, 127 PBL_LVL_1, 128 PBL_LVL_2, 129 PBL_LVL_MAX 130 }; 131 132 #define ROCE_PG_SIZE_4K (4 * 1024) 133 #define ROCE_PG_SIZE_8K (8 * 1024) 134 #define ROCE_PG_SIZE_64K (64 * 1024) 135 #define ROCE_PG_SIZE_2M (2 * 1024 * 1024) 136 #define ROCE_PG_SIZE_8M (8 * 1024 * 1024) 137 #define ROCE_PG_SIZE_1G (1024 * 1024 * 1024) 138 139 enum bnxt_qplib_hwrm_pg_size { 140 BNXT_QPLIB_HWRM_PG_SIZE_4K = 0, 141 BNXT_QPLIB_HWRM_PG_SIZE_8K = 1, 142 BNXT_QPLIB_HWRM_PG_SIZE_64K = 2, 143 BNXT_QPLIB_HWRM_PG_SIZE_2M = 3, 144 BNXT_QPLIB_HWRM_PG_SIZE_8M = 4, 145 BNXT_QPLIB_HWRM_PG_SIZE_1G = 5, 146 }; 147 148 struct bnxt_qplib_reg_desc { 149 u8 bar_id; 150 resource_size_t bar_base; 151 unsigned long offset; 152 void __iomem *bar_reg; 153 size_t len; 154 }; 155 156 struct bnxt_qplib_pbl { 157 u32 pg_count; 158 u32 pg_size; 159 void **pg_arr; 160 dma_addr_t *pg_map_arr; 161 }; 162 163 struct bnxt_qplib_sg_info { 164 struct ib_umem *umem; 165 u32 npages; 166 u32 pgshft; 167 u32 pgsize; 168 bool nopte; 169 }; 170 171 struct bnxt_qplib_hwq_attr { 172 struct bnxt_qplib_res *res; 173 struct bnxt_qplib_sg_info *sginfo; 174 enum bnxt_qplib_hwq_type type; 175 u32 depth; 176 u32 stride; 177 u32 aux_stride; 178 u32 aux_depth; 179 }; 180 181 struct bnxt_qplib_hwq { 182 struct pci_dev *pdev; 183 /* lock to protect qplib_hwq */ 184 spinlock_t lock; 185 struct bnxt_qplib_pbl pbl[PBL_LVL_MAX + 1]; 186 enum bnxt_qplib_pbl_lvl level; /* 0, 1, or 2 */ 187 /* ptr for easy access to the PBL entries */ 188 void **pbl_ptr; 189 /* ptr for easy access to the dma_addr */ 190 dma_addr_t *pbl_dma_ptr; 191 u32 max_elements; 192 u32 depth; 193 u16 element_size; /* Size of each entry */ 194 u16 qe_ppg; /* queue entry per page */ 195 196 u32 prod; /* raw */ 197 u32 cons; /* raw */ 198 u8 cp_bit; 199 u8 is_user; 200 u64 *pad_pg; 201 u32 pad_stride; 202 u32 pad_pgofft; 203 }; 204 205 struct bnxt_qplib_db_info { 206 void __iomem *db; 207 void __iomem *priv_db; 208 struct bnxt_qplib_hwq *hwq; 209 u32 xid; 210 u32 max_slot; 211 u32 flags; 212 u8 toggle; 213 }; 214 215 enum bnxt_qplib_db_info_flags_mask { 216 BNXT_QPLIB_FLAG_EPOCH_CONS_SHIFT = 0x0UL, 217 BNXT_QPLIB_FLAG_EPOCH_PROD_SHIFT = 0x1UL, 218 BNXT_QPLIB_FLAG_EPOCH_CONS_MASK = 0x1UL, 219 BNXT_QPLIB_FLAG_EPOCH_PROD_MASK = 0x2UL, 220 }; 221 222 enum bnxt_qplib_db_epoch_flag_shift { 223 BNXT_QPLIB_DB_EPOCH_CONS_SHIFT = BNXT_QPLIB_DBR_EPOCH_SHIFT, 224 BNXT_QPLIB_DB_EPOCH_PROD_SHIFT = (BNXT_QPLIB_DBR_EPOCH_SHIFT - 1), 225 }; 226 227 /* Tables */ 228 struct bnxt_qplib_pd_tbl { 229 unsigned long *tbl; 230 u32 max; 231 }; 232 233 struct bnxt_qplib_sgid_tbl { 234 struct bnxt_qplib_gid_info *tbl; 235 u16 *hw_id; 236 u16 max; 237 u16 active; 238 void *ctx; 239 u8 *vlan; 240 }; 241 242 enum { 243 BNXT_QPLIB_DPI_TYPE_KERNEL = 0, 244 BNXT_QPLIB_DPI_TYPE_UC = 1, 245 BNXT_QPLIB_DPI_TYPE_WC = 2 246 }; 247 248 struct bnxt_qplib_dpi { 249 u32 dpi; 250 u32 bit; 251 void __iomem *dbr; 252 u64 umdbr; 253 u8 type; 254 }; 255 256 struct bnxt_qplib_dpi_tbl { 257 void **app_tbl; 258 unsigned long *tbl; 259 u16 max; 260 struct bnxt_qplib_reg_desc ucreg; /* Hold entire DB bar. */ 261 struct bnxt_qplib_reg_desc wcreg; 262 void __iomem *priv_db; 263 }; 264 265 struct bnxt_qplib_stats { 266 dma_addr_t dma_map; 267 void *dma; 268 u32 size; 269 u32 fw_id; 270 }; 271 272 struct bnxt_qplib_vf_res { 273 u32 max_qp_per_vf; 274 u32 max_mrw_per_vf; 275 u32 max_srq_per_vf; 276 u32 max_cq_per_vf; 277 u32 max_gid_per_vf; 278 }; 279 280 #define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE 448 281 #define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE 64 282 #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE 64 283 #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE 128 284 285 #define MAX_TQM_ALLOC_REQ 48 286 #define MAX_TQM_ALLOC_BLK_SIZE 8 287 struct bnxt_qplib_tqm_ctx { 288 struct bnxt_qplib_hwq pde; 289 u8 pde_level; /* Original level */ 290 struct bnxt_qplib_hwq qtbl[MAX_TQM_ALLOC_REQ]; 291 u8 qcount[MAX_TQM_ALLOC_REQ]; 292 }; 293 294 struct bnxt_qplib_ctx { 295 u32 qpc_count; 296 struct bnxt_qplib_hwq qpc_tbl; 297 u32 mrw_count; 298 struct bnxt_qplib_hwq mrw_tbl; 299 u32 srqc_count; 300 struct bnxt_qplib_hwq srqc_tbl; 301 u32 cq_count; 302 struct bnxt_qplib_hwq cq_tbl; 303 struct bnxt_qplib_hwq tim_tbl; 304 struct bnxt_qplib_tqm_ctx tqm_ctx; 305 struct bnxt_qplib_stats stats; 306 struct bnxt_qplib_vf_res vf_res; 307 }; 308 309 struct bnxt_qplib_res { 310 struct pci_dev *pdev; 311 struct bnxt_qplib_chip_ctx *cctx; 312 struct bnxt_qplib_dev_attr *dattr; 313 struct net_device *netdev; 314 struct bnxt_en_dev *en_dev; 315 struct bnxt_qplib_rcfw *rcfw; 316 struct bnxt_qplib_pd_tbl pd_tbl; 317 /* To protect the pd table bit map */ 318 struct mutex pd_tbl_lock; 319 struct bnxt_qplib_sgid_tbl sgid_tbl; 320 struct bnxt_qplib_dpi_tbl dpi_tbl; 321 /* To protect the dpi table bit map */ 322 struct mutex dpi_tbl_lock; 323 bool prio; 324 bool is_vf; 325 struct bnxt_qplib_db_pacing_data *pacing_data; 326 }; 327 328 static inline bool bnxt_qplib_is_chip_gen_p7(struct bnxt_qplib_chip_ctx *cctx) 329 { 330 return (cctx->chip_num == CHIP_NUM_58818 || 331 cctx->chip_num == CHIP_NUM_57608); 332 } 333 334 static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx) 335 { 336 return (cctx->chip_num == CHIP_NUM_57508 || 337 cctx->chip_num == CHIP_NUM_57504 || 338 cctx->chip_num == CHIP_NUM_57502); 339 } 340 341 static inline bool bnxt_qplib_is_chip_gen_p5_p7(struct bnxt_qplib_chip_ctx *cctx) 342 { 343 return bnxt_qplib_is_chip_gen_p5(cctx) || bnxt_qplib_is_chip_gen_p7(cctx); 344 } 345 346 static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res) 347 { 348 return bnxt_qplib_is_chip_gen_p5_p7(res->cctx) ? 349 HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL; 350 } 351 352 static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx) 353 { 354 return bnxt_qplib_is_chip_gen_p5_p7(cctx) ? 355 RING_ALLOC_REQ_RING_TYPE_NQ : 356 RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL; 357 } 358 359 static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq) 360 { 361 u8 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K; 362 struct bnxt_qplib_pbl *pbl; 363 364 pbl = &hwq->pbl[PBL_LVL_0]; 365 switch (pbl->pg_size) { 366 case ROCE_PG_SIZE_4K: 367 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K; 368 break; 369 case ROCE_PG_SIZE_8K: 370 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8K; 371 break; 372 case ROCE_PG_SIZE_64K: 373 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_64K; 374 break; 375 case ROCE_PG_SIZE_2M: 376 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_2M; 377 break; 378 case ROCE_PG_SIZE_8M: 379 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8M; 380 break; 381 case ROCE_PG_SIZE_1G: 382 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_1G; 383 break; 384 default: 385 break; 386 } 387 388 return pg_size; 389 } 390 391 static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq, 392 u32 indx, u64 *pg) 393 { 394 u32 pg_num, pg_idx; 395 396 pg_num = (indx / hwq->qe_ppg); 397 pg_idx = (indx % hwq->qe_ppg); 398 if (pg) 399 *pg = (u64)&hwq->pbl_ptr[pg_num]; 400 return (void *)(hwq->pbl_ptr[pg_num] + hwq->element_size * pg_idx); 401 } 402 403 static inline void *bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq *hwq, u32 idx) 404 { 405 idx += hwq->prod; 406 if (idx >= hwq->depth) 407 idx -= hwq->depth; 408 return bnxt_qplib_get_qe(hwq, idx, NULL); 409 } 410 411 #define to_bnxt_qplib(ptr, type, member) \ 412 container_of(ptr, type, member) 413 414 struct bnxt_qplib_pd; 415 struct bnxt_qplib_dev_attr; 416 417 void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res, 418 struct bnxt_qplib_hwq *hwq); 419 int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq, 420 struct bnxt_qplib_hwq_attr *hwq_attr); 421 int bnxt_qplib_alloc_pd(struct bnxt_qplib_res *res, 422 struct bnxt_qplib_pd *pd); 423 int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res, 424 struct bnxt_qplib_pd_tbl *pd_tbl, 425 struct bnxt_qplib_pd *pd); 426 int bnxt_qplib_alloc_dpi(struct bnxt_qplib_res *res, 427 struct bnxt_qplib_dpi *dpi, 428 void *app, u8 type); 429 int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res, 430 struct bnxt_qplib_dpi *dpi); 431 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res); 432 int bnxt_qplib_init_res(struct bnxt_qplib_res *res); 433 void bnxt_qplib_free_res(struct bnxt_qplib_res *res); 434 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct net_device *netdev); 435 void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res, 436 struct bnxt_qplib_ctx *ctx); 437 int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res, 438 struct bnxt_qplib_ctx *ctx, 439 bool virt_fn, bool is_p5); 440 int bnxt_qplib_map_db_bar(struct bnxt_qplib_res *res); 441 void bnxt_qplib_unmap_db_bar(struct bnxt_qplib_res *res); 442 443 int bnxt_qplib_determine_atomics(struct pci_dev *dev); 444 445 static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_db_info *dbinfo, 446 struct bnxt_qplib_hwq *hwq, u32 cnt) 447 { 448 /* move prod and update toggle/epoch if wrap around */ 449 hwq->prod += cnt; 450 if (hwq->prod >= hwq->depth) { 451 hwq->prod %= hwq->depth; 452 dbinfo->flags ^= 1UL << BNXT_QPLIB_FLAG_EPOCH_PROD_SHIFT; 453 } 454 } 455 456 static inline void bnxt_qplib_hwq_incr_cons(u32 max_elements, u32 *cons, u32 cnt, 457 u32 *dbinfo_flags) 458 { 459 /* move cons and update toggle/epoch if wrap around */ 460 *cons += cnt; 461 if (*cons >= max_elements) { 462 *cons %= max_elements; 463 *dbinfo_flags ^= 1UL << BNXT_QPLIB_FLAG_EPOCH_CONS_SHIFT; 464 } 465 } 466 467 static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info, 468 bool arm) 469 { 470 u32 key = 0; 471 472 key |= info->hwq->cons | (CMPL_DOORBELL_IDX_VALID | 473 (CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK)); 474 if (!arm) 475 key |= CMPL_DOORBELL_MASK; 476 writel(key, info->db); 477 } 478 479 #define BNXT_QPLIB_INIT_DBHDR(xid, type, indx, toggle) \ 480 (((u64)(((xid) & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | \ 481 (type) | BNXT_QPLIB_DBR_VALID) << 32) | (indx) | \ 482 (((u32)(toggle)) << (BNXT_QPLIB_DBR_TOGGLE_SHIFT))) 483 484 static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info, 485 u32 type) 486 { 487 u64 key = 0; 488 u32 indx; 489 u8 toggle = 0; 490 491 if (type == DBC_DBC_TYPE_CQ_ARMALL || 492 type == DBC_DBC_TYPE_CQ_ARMSE) 493 toggle = info->toggle; 494 495 indx = (info->hwq->cons & DBC_DBC_INDEX_MASK) | 496 ((info->flags & BNXT_QPLIB_FLAG_EPOCH_CONS_MASK) << 497 BNXT_QPLIB_DB_EPOCH_CONS_SHIFT); 498 499 key = BNXT_QPLIB_INIT_DBHDR(info->xid, type, indx, toggle); 500 writeq(key, info->db); 501 } 502 503 static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info, 504 u32 type) 505 { 506 u64 key = 0; 507 u32 indx; 508 509 indx = (((info->hwq->prod / info->max_slot) & DBC_DBC_INDEX_MASK) | 510 ((info->flags & BNXT_QPLIB_FLAG_EPOCH_PROD_MASK) << 511 BNXT_QPLIB_DB_EPOCH_PROD_SHIFT)); 512 key = BNXT_QPLIB_INIT_DBHDR(info->xid, type, indx, 0); 513 writeq(key, info->db); 514 } 515 516 static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info, 517 u32 type) 518 { 519 u64 key = 0; 520 u8 toggle = 0; 521 522 if (type == DBC_DBC_TYPE_CQ_ARMENA || type == DBC_DBC_TYPE_SRQ_ARMENA) 523 toggle = info->toggle; 524 /* Index always at 0 */ 525 key = BNXT_QPLIB_INIT_DBHDR(info->xid, type, 0, toggle); 526 writeq(key, info->priv_db); 527 } 528 529 static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info, 530 u32 th) 531 { 532 u64 key = 0; 533 534 key = BNXT_QPLIB_INIT_DBHDR(info->xid, DBC_DBC_TYPE_SRQ_ARM, th, info->toggle); 535 writeq(key, info->priv_db); 536 } 537 538 static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info, 539 struct bnxt_qplib_chip_ctx *cctx, 540 bool arm) 541 { 542 u32 type; 543 544 type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ; 545 if (bnxt_qplib_is_chip_gen_p5_p7(cctx)) 546 bnxt_qplib_ring_db(info, type); 547 else 548 bnxt_qplib_ring_db32(info, arm); 549 } 550 551 static inline bool _is_ext_stats_supported(u16 dev_cap_flags) 552 { 553 return dev_cap_flags & 554 CREQ_QUERY_FUNC_RESP_SB_EXT_STATS; 555 } 556 557 static inline int bnxt_ext_stats_supported(struct bnxt_qplib_chip_ctx *ctx, 558 u16 flags, bool virtfn) 559 { 560 /* ext stats supported if cap flag is set AND is a PF OR a Thor2 VF */ 561 return (_is_ext_stats_supported(flags) && 562 ((virtfn && bnxt_qplib_is_chip_gen_p7(ctx)) || (!virtfn))); 563 } 564 565 static inline bool _is_hw_retx_supported(u16 dev_cap_flags) 566 { 567 return dev_cap_flags & 568 (CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED | 569 CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED); 570 } 571 572 #define BNXT_RE_HW_RETX(a) _is_hw_retx_supported((a)) 573 574 static inline bool _is_host_msn_table(u16 dev_cap_ext_flags2) 575 { 576 return (dev_cap_ext_flags2 & CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_MASK) == 577 CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_MSN_TABLE; 578 } 579 580 static inline u8 bnxt_qplib_dbr_pacing_en(struct bnxt_qplib_chip_ctx *cctx) 581 { 582 return cctx->modes.dbr_pacing; 583 } 584 585 static inline bool _is_alloc_mr_unified(u16 dev_cap_flags) 586 { 587 return dev_cap_flags & CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC; 588 } 589 590 static inline bool _is_relaxed_ordering_supported(u16 dev_cap_ext_flags2) 591 { 592 return dev_cap_ext_flags2 & CREQ_QUERY_FUNC_RESP_SB_MEMORY_REGION_RO_SUPPORTED; 593 } 594 595 static inline bool _is_optimize_modify_qp_supported(u16 dev_cap_ext_flags2) 596 { 597 return dev_cap_ext_flags2 & CREQ_QUERY_FUNC_RESP_SB_OPTIMIZE_MODIFY_QP_SUPPORTED; 598 } 599 600 static inline bool _is_min_rnr_in_rtr_rts_mandatory(u16 dev_cap_ext_flags2) 601 { 602 return !!(dev_cap_ext_flags2 & CREQ_QUERY_FUNC_RESP_SB_MIN_RNR_RTR_RTS_OPT_SUPPORTED); 603 } 604 605 static inline bool _is_cq_coalescing_supported(u16 dev_cap_ext_flags2) 606 { 607 return dev_cap_ext_flags2 & CREQ_QUERY_FUNC_RESP_SB_CQ_COALESCING_SUPPORTED; 608 } 609 610 static inline bool _is_max_srq_ext_supported(u16 dev_cap_ext_flags_2) 611 { 612 return !!(dev_cap_ext_flags_2 & CREQ_QUERY_FUNC_RESP_SB_MAX_SRQ_EXTENDED); 613 } 614 615 #endif /* __BNXT_QPLIB_RES_H__ */ 616