1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 *
26 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
27 */
28
29 /*
30 * Portions Copyright 2009 Advanced Micro Devices, Inc.
31 */
32
33 /*
34 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
35 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
36 * Copyright 2019 Joyent, Inc.
37 * Copyright 2025 Oxide Computer Company
38 */
39
40 /*
41 * Support functions that interpret CPUID and similar information.
42 * These should not be used from anywhere other than cpuid.c and
43 * cmi_hw.c - as such we will not list them in any header file
44 * such as x86_archext.h.
45 *
46 * In cpuid.c we process CPUID information for each cpu_t instance
47 * we're presented with, and stash this raw information and material
48 * derived from it in per-cpu_t structures.
49 *
50 * If we are virtualized then the CPUID information derived from CPUID
51 * instructions executed in the guest is based on whatever the hypervisor
52 * wanted to make things look like, and the cpu_t are not necessarily in 1:1
53 * or fixed correspondence with real processor execution resources. In cmi_hw.c
54 * we are interested in the native properties of a processor - for fault
55 * management (and potentially other, such as power management) purposes;
56 * it will tunnel through to real hardware information, and use the
57 * functionality provided in this file to process it.
58 */
59
60 #include <sys/types.h>
61 #include <sys/systm.h>
62 #include <sys/bitmap.h>
63 #include <sys/x86_archext.h>
64 #include <sys/pci_cfgspace.h>
65 #include <sys/sysmacros.h>
66 #ifdef __xpv
67 #include <sys/hypervisor.h>
68 #endif
69
70 /*
71 * AMD socket types.
72 * First index defines a processor family; see notes inline. The second index
73 * selects the socket type by either (model & 0x3) for family 0fh or the CPUID
74 * pkg bits (Fn8000_0001_EBX[31:28]) for later families.
75 */
76 static uint32_t amd_skts[][16] = {
77 /*
78 * Family 0xf revisions B through E
79 */
80 #define A_SKTS_0 0
81 {
82 [0] = X86_SOCKET_754,
83 [1] = X86_SOCKET_940,
84 [2] = X86_SOCKET_754,
85 [3] = X86_SOCKET_939,
86 },
87 /*
88 * Family 0xf revisions F and G
89 */
90 #define A_SKTS_1 1
91 {
92 [0] = X86_SOCKET_S1g1,
93 [1] = X86_SOCKET_F1207,
94 [3] = X86_SOCKET_AM2
95 },
96 /*
97 * Family 0x10
98 */
99 #define A_SKTS_2 2
100 {
101 [0] = X86_SOCKET_F1207,
102 [1] = X86_SOCKET_AM2R2,
103 [2] = X86_SOCKET_S1g3,
104 [3] = X86_SOCKET_G34,
105 [4] = X86_SOCKET_ASB2,
106 [5] = X86_SOCKET_C32
107 },
108
109 /*
110 * Family 0x11
111 */
112 #define A_SKTS_3 3
113 {
114 [2] = X86_SOCKET_S1g2
115 },
116
117 /*
118 * Family 0x12
119 */
120 #define A_SKTS_4 4
121 {
122 [1] = X86_SOCKET_FS1,
123 [2] = X86_SOCKET_FM1
124 },
125
126 /*
127 * Family 0x14
128 */
129 #define A_SKTS_5 5
130 {
131 [0] = X86_SOCKET_FT1
132 },
133
134 /*
135 * Family 0x15 models 00 - 0f
136 */
137 #define A_SKTS_6 6
138 {
139 [1] = X86_SOCKET_AM3R2,
140 [3] = X86_SOCKET_G34,
141 [5] = X86_SOCKET_C32
142 },
143
144 /*
145 * Family 0x15 models 10 - 1f
146 */
147 #define A_SKTS_7 7
148 {
149 [0] = X86_SOCKET_FP2,
150 [1] = X86_SOCKET_FS1R2,
151 [2] = X86_SOCKET_FM2
152 },
153
154 /*
155 * Family 0x15 models 30-3f
156 */
157 #define A_SKTS_8 8
158 {
159 [0] = X86_SOCKET_FP3,
160 [1] = X86_SOCKET_FM2R2
161 },
162
163 /*
164 * Family 0x15 models 60-6f
165 */
166 #define A_SKTS_9 9
167 {
168 [0] = X86_SOCKET_FP4,
169 [2] = X86_SOCKET_AM4,
170 [3] = X86_SOCKET_FM2R2
171 },
172
173 /*
174 * Family 0x15 models 70-7f
175 */
176 #define A_SKTS_10 10
177 {
178 [0] = X86_SOCKET_FP4,
179 [2] = X86_SOCKET_AM4,
180 [4] = X86_SOCKET_FT4
181 },
182
183 /*
184 * Family 0x16 models 00-0f
185 */
186 #define A_SKTS_11 11
187 {
188 [0] = X86_SOCKET_FT3,
189 [1] = X86_SOCKET_FS1B
190 },
191
192 /*
193 * Family 0x16 models 30-3f
194 */
195 #define A_SKTS_12 12
196 {
197 [0] = X86_SOCKET_FT3B,
198 [3] = X86_SOCKET_FP4
199 },
200
201 /*
202 * Family 0x17 models 00-0f (Zen 1 - Naples, Ryzen)
203 */
204 #define A_SKTS_NAPLES 13
205 {
206 [2] = X86_SOCKET_AM4,
207 [4] = X86_SOCKET_SP3,
208 [7] = X86_SOCKET_SP3R2
209 },
210
211 /*
212 * Family 0x17 models 10-2f (Zen 1 - APU: Raven Ridge)
213 * (Zen 1 - APU: Banded Kestrel)
214 * (Zen 1 - APU: Dali)
215 */
216 #define A_SKTS_RAVEN 14
217 {
218 [0] = X86_SOCKET_FP5,
219 [2] = X86_SOCKET_AM4
220 },
221
222 /*
223 * Family 0x17 models 30-3f (Zen 2 - Rome)
224 */
225 #define A_SKTS_ROME 15
226 {
227 [4] = X86_SOCKET_SP3,
228 [7] = X86_SOCKET_SP3R2
229 },
230
231 /*
232 * Family 0x17 models 60-6f (Zen 2 - Renoir)
233 */
234 #define A_SKTS_RENOIR 16
235 {
236 [0] = X86_SOCKET_FP6,
237 [2] = X86_SOCKET_AM4
238 },
239
240 /*
241 * Family 0x17 models 70-7f (Zen 2 - Matisse)
242 */
243 #define A_SKTS_MATISSE 17
244 {
245 [2] = X86_SOCKET_AM4,
246 },
247
248 /*
249 * Family 0x18 models 00-0f (Dhyana)
250 */
251 #define A_SKTS_DHYANA 18
252 {
253 [4] = X86_SOCKET_SL1,
254 [6] = X86_SOCKET_DM1,
255 [7] = X86_SOCKET_SL1R2
256 },
257
258 /*
259 * Family 0x19 models 00-0f (Zen 3 - Milan)
260 */
261 #define A_SKTS_MILAN 19
262 {
263 [4] = X86_SOCKET_SP3,
264 [7] = X86_SOCKET_STRX4
265 },
266
267 /*
268 * Family 0x19 models 20-2f (Zen 3 - Vermeer)
269 */
270 #define A_SKTS_VERMEER 20
271 {
272 [2] = X86_SOCKET_AM4,
273 },
274
275 /*
276 * Family 0x19 models 50-5f (Zen 3 - Cezanne)
277 */
278 #define A_SKTS_CEZANNE 21
279 {
280 [0] = X86_SOCKET_FP6,
281 [2] = X86_SOCKET_AM4
282 },
283
284 /*
285 * Family 0x19 models 10-1f (Zen 4 - Genoa)
286 */
287 #define A_SKTS_GENOA 22
288 {
289 [4] = X86_SOCKET_SP5,
290 [8] = X86_SOCKET_TR5
291 },
292
293 /*
294 * Family 0x19 models 40-4f (Zen 3 - Rembrandt)
295 */
296 #define A_SKTS_REMBRANDT 23
297 {
298 [0] = X86_SOCKET_AM5,
299 [1] = X86_SOCKET_FP7,
300 [2] = X86_SOCKET_FP7R2
301 },
302
303 /*
304 * Family 0x19 models 60-6f (Zen 4 - Raphael)
305 */
306 #define A_SKTS_RAPHAEL 24
307 {
308 [0] = X86_SOCKET_AM5,
309 [1] = X86_SOCKET_FL1
310 },
311
312 /*
313 * The always-unknown socket group, used for undocumented parts. It
314 * need not be last; the position is arbitrary. The default initializer
315 * for this is zero which is x86 socket unknown.
316 */
317 #define A_SKTS_UNKNOWN 25
318 {
319 },
320 /*
321 * Family 0x17 models 90-97 (Zen 2 - Van Gogh)
322 */
323 #define A_SKTS_VANGOGH 26
324 {
325 [3] = X86_SOCKET_FF3
326 },
327 /*
328 * Family 0x17 models a0-af (Zen 2 - Mendocino)
329 */
330 #define A_SKTS_MENDOCINO 27
331 {
332 [1] = X86_SOCKET_FT6
333 },
334
335 /*
336 * Family 0x19 models 70-7f (Zen 4 - Phoenix)
337 */
338 #define A_SKTS_PHOENIX 28
339 {
340 [0] = X86_SOCKET_AM5,
341 [1] = X86_SOCKET_FP8,
342 [4] = X86_SOCKET_FP7,
343 [5] = X86_SOCKET_FP7R2,
344 },
345
346 /*
347 * Family 0x19 models a0-af (Zen 4c - Bergamo/Siena)
348 */
349 #define A_SKTS_BERGAMO 29
350 {
351 [4] = X86_SOCKET_SP5,
352 [8] = X86_SOCKET_SP6
353 },
354 /*
355 * Family 0x1a models 00-1f (Zen 5[c] - Turin)
356 */
357 #define A_SKTS_TURIN 30
358 {
359 [4] = X86_SOCKET_SP5,
360 },
361
362 /*
363 * Family 0x1a models 20-2f (Zen 5 - Strix)
364 * Family 0x1a models 60-6f (Zen 5 - Krackan)
365 */
366 #define A_SKTS_STRIX 31
367 {
368 [0] = X86_SOCKET_AM5,
369 [1] = X86_SOCKET_FP8
370 },
371
372 /*
373 * Family 0x1a models 40-4f (Zen 5 - Granite Ridge)
374 */
375 #define A_SKTS_GRANITE_RIDGE 32
376 {
377 [0] = X86_SOCKET_AM5,
378 [1] = X86_SOCKET_FL1
379 },
380
381 /*
382 * Family 0x1a models 70-77 (Zen 5 - Strix Halo)
383 */
384 #define A_SKTS_STRIX_HALO 33
385 {
386 [1] = X86_SOCKET_FP11
387 }
388 };
389
390 struct amd_sktmap_s {
391 uint32_t skt_code;
392 char sktstr[16];
393 };
394 static struct amd_sktmap_s amd_sktmap_strs[] = {
395 { X86_SOCKET_754, "754" },
396 { X86_SOCKET_939, "939" },
397 { X86_SOCKET_940, "940" },
398 { X86_SOCKET_S1g1, "S1g1" },
399 { X86_SOCKET_AM2, "AM2" },
400 { X86_SOCKET_F1207, "F(1207)" },
401 { X86_SOCKET_S1g2, "S1g2" },
402 { X86_SOCKET_S1g3, "S1g3" },
403 { X86_SOCKET_AM, "AM" },
404 { X86_SOCKET_AM2R2, "AM2r2" },
405 { X86_SOCKET_AM3, "AM3" },
406 { X86_SOCKET_G34, "G34" },
407 { X86_SOCKET_ASB2, "ASB2" },
408 { X86_SOCKET_C32, "C32" },
409 { X86_SOCKET_S1g4, "S1g4" },
410 { X86_SOCKET_FT1, "FT1" },
411 { X86_SOCKET_FM1, "FM1" },
412 { X86_SOCKET_FS1, "FS1" },
413 { X86_SOCKET_AM3R2, "AM3r2" },
414 { X86_SOCKET_FP2, "FP2" },
415 { X86_SOCKET_FS1R2, "FS1r2" },
416 { X86_SOCKET_FM2, "FM2" },
417 { X86_SOCKET_FP3, "FP3" },
418 { X86_SOCKET_FM2R2, "FM2r2" },
419 { X86_SOCKET_FP4, "FP4" },
420 { X86_SOCKET_AM4, "AM4" },
421 { X86_SOCKET_FT3, "FT3" },
422 { X86_SOCKET_FT4, "FT4" },
423 { X86_SOCKET_FS1B, "FS1b" },
424 { X86_SOCKET_FT3B, "FT3b" },
425 { X86_SOCKET_SP3, "SP3" },
426 { X86_SOCKET_SP3R2, "SP3r2" },
427 { X86_SOCKET_FP5, "FP5" },
428 { X86_SOCKET_FP6, "FP6" },
429 { X86_SOCKET_STRX4, "sTRX4" },
430 { X86_SOCKET_SL1, "SL1" },
431 { X86_SOCKET_SL1R2, "SL1R2" },
432 { X86_SOCKET_DM1, "DM1" },
433 { X86_SOCKET_SP5, "SP5" },
434 { X86_SOCKET_AM5, "AM5" },
435 { X86_SOCKET_FP7, "FP7" },
436 { X86_SOCKET_FP7R2, "FP7r2" },
437 { X86_SOCKET_FF3, "FF3" },
438 { X86_SOCKET_FT6, "FT6" },
439 { X86_SOCKET_FP8, "FP8" },
440 { X86_SOCKET_FL1, "FL1" },
441 { X86_SOCKET_SP6, "SP6" },
442 { X86_SOCKET_TR5, "TR5" },
443 { X86_SOCKET_FP11, "FP11" },
444 { X86_SOCKET_UNKNOWN, "Unknown" } /* Must be last! */
445 };
446
447 /* Keep the array above in sync with the definitions in x86_archext.h. */
448 CTASSERT(ARRAY_SIZE(amd_sktmap_strs) == X86_NUM_SOCKETS + 1);
449
450 /*
451 * Table for mapping AMD family/model/stepping ranges onto three derived items:
452 *
453 * * The "chiprev" and associated string, which is generally the AMD silicon
454 * revision along with a symbolic representation of the marketing (not cpuid)
455 * family. In line with the overall cpuid usage, we refer to this as a
456 * processor family.
457 * * The uarch, which is analogous to the chiprev and provides the
458 * microarchitecture/core generation and silicon revision. Note that this is
459 * distinct from the package-level silicon/product revision and is often common
460 * to multiple product lines offered at a given time.
461 * * The socket map selector, used to translate this collection of products'
462 * last 4 model bits (for family 0xf only) or Fn8000_0001_EBX[30:28] into a
463 * socket ID.
464 *
465 * The first member of this array that matches a given family, extended model
466 * plus model range, and stepping range will be considered a match. This allows
467 * us to end each cpuid family and/or processor family with a catchall that
468 * while less specific than we might like still allows us to provide a fair
469 * amount of detail to both other kernel consumers and userland.
470 */
471 static const struct amd_rev_mapent {
472 uint_t rm_family;
473 uint_t rm_modello;
474 uint_t rm_modelhi;
475 uint_t rm_steplo;
476 uint_t rm_stephi;
477 x86_chiprev_t rm_chiprev;
478 const char *rm_chiprevstr;
479 x86_uarchrev_t rm_uarchrev;
480 uint_t rm_sktidx;
481 } amd_revmap[] = {
482 /*
483 * =============== AuthenticAMD Family 0xf ===============
484 */
485
486 /*
487 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1.
488 */
489 { 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_LEGACY_F_REV_B, "B",
490 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 },
491 { 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_LEGACY_F_REV_B, "B",
492 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 },
493 /*
494 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8
495 */
496 { 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_LEGACY_F_REV_C0, "C0",
497 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 },
498 /*
499 * Rev CG is the rest of extended model 0x0 - i.e., everything
500 * but the rev B and C0 combinations covered above.
501 */
502 { 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_CG, "CG",
503 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 },
504 /*
505 * Rev D has extended model 0x1.
506 */
507 { 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_D, "D",
508 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 },
509 /*
510 * Rev E has extended model 0x2.
511 * Extended model 0x3 is unused but available to grow into.
512 */
513 { 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_E, "E",
514 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 },
515 /*
516 * Rev F has extended models 0x4 and 0x5.
517 */
518 { 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_F, "F",
519 X86_UARCHREV_AMD_LEGACY, A_SKTS_1 },
520 /*
521 * Rev G has extended model 0x6.
522 */
523 { 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_G, "G",
524 X86_UARCHREV_AMD_LEGACY, A_SKTS_1 },
525
526 /*
527 * =============== AuthenticAMD Family 0x10 ===============
528 */
529
530 /*
531 * Rev A has model 0 and stepping 0/1/2 for DR-{A0,A1,A2}.
532 * Give all of model 0 stepping range to rev A.
533 */
534 { 0x10, 0x00, 0x00, 0x0, 0x2, X86_CHIPREV_AMD_LEGACY_10_REV_A, "A",
535 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 },
536
537 /*
538 * Rev B has model 2 and steppings 0/1/0xa/2 for DR-{B0,B1,BA,B2}.
539 * Give all of model 2 stepping range to rev B.
540 */
541 { 0x10, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_10_REV_B, "B",
542 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 },
543
544 /*
545 * Rev C has models 4-6 (depending on L3 cache configuration)
546 * Give all of models 4-6 stepping range 0-2 to rev C2.
547 */
548 { 0x10, 0x4, 0x6, 0x0, 0x2, X86_CHIPREV_AMD_LEGACY_10_REV_C2, "C2",
549 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 },
550
551 /*
552 * Rev C has models 4-6 (depending on L3 cache configuration)
553 * Give all of models 4-6 stepping range >= 3 to rev C3.
554 */
555 { 0x10, 0x4, 0x6, 0x3, 0xf, X86_CHIPREV_AMD_LEGACY_10_REV_C3, "C3",
556 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 },
557
558 /*
559 * Rev D has models 8 and 9
560 * Give all of model 8 and 9 stepping 0 to rev D0.
561 */
562 { 0x10, 0x8, 0x9, 0x0, 0x0, X86_CHIPREV_AMD_LEGACY_10_REV_D0, "D0",
563 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 },
564
565 /*
566 * Rev D has models 8 and 9
567 * Give all of model 8 and 9 stepping range >= 1 to rev D1.
568 */
569 { 0x10, 0x8, 0x9, 0x1, 0xf, X86_CHIPREV_AMD_LEGACY_10_REV_D1, "D1",
570 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 },
571
572 /*
573 * Rev E has models A and stepping 0
574 * Give all of model A stepping range to rev E.
575 */
576 { 0x10, 0xA, 0xA, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_10_REV_E, "E",
577 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 },
578
579 { 0x10, 0x0, 0xff, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_10_UNKNOWN, "??",
580 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 },
581
582 /*
583 * =============== AuthenticAMD Family 0x11 ===============
584 */
585 { 0x11, 0x03, 0x03, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_11_REV_B, "B",
586 X86_UARCHREV_AMD_LEGACY, A_SKTS_3 },
587 { 0x11, 0x00, 0xff, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_11_UNKNOWN, "??",
588 X86_UARCHREV_AMD_LEGACY, A_SKTS_3 },
589
590 /*
591 * =============== AuthenticAMD Family 0x12 ===============
592 */
593 { 0x12, 0x01, 0x01, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_12_REV_B, "B",
594 X86_UARCHREV_AMD_LEGACY, A_SKTS_4 },
595 { 0x12, 0x00, 0x00, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_12_UNKNOWN, "??",
596 X86_UARCHREV_AMD_LEGACY, A_SKTS_4 },
597
598 /*
599 * =============== AuthenticAMD Family 0x14 ===============
600 */
601 { 0x14, 0x01, 0x01, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_14_REV_B, "B",
602 X86_UARCHREV_AMD_LEGACY, A_SKTS_5 },
603 { 0x14, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_14_REV_C, "C",
604 X86_UARCHREV_AMD_LEGACY, A_SKTS_5 },
605 { 0x14, 0x00, 0xff, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_14_UNKNOWN, "??",
606 X86_UARCHREV_AMD_LEGACY, A_SKTS_5 },
607
608 /*
609 * =============== AuthenticAMD Family 0x15 ===============
610 */
611 { 0x15, 0x01, 0x01, 0x2, 0x2, X86_CHIPREV_AMD_OROCHI_REV_B2, "OR-B2",
612 X86_UARCHREV_AMD_LEGACY, A_SKTS_6 },
613 { 0x15, 0x02, 0x02, 0x0, 0x0, X86_CHIPREV_AMD_OROCHI_REV_C0, "OR-C0",
614 X86_UARCHREV_AMD_LEGACY, A_SKTS_6 },
615 { 0x15, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_OROCHI_UNKNOWN, "OR-??",
616 X86_UARCHREV_AMD_LEGACY, A_SKTS_6 },
617
618 { 0x15, 0x10, 0x10, 0x1, 0x1, X86_CHIPREV_AMD_TRINITY_REV_A1, "TN-A1",
619 X86_UARCHREV_AMD_LEGACY, A_SKTS_7 },
620 { 0x15, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_TRINITY_UNKNOWN, "TN-??",
621 X86_UARCHREV_AMD_LEGACY, A_SKTS_7 },
622
623 { 0x15, 0x30, 0x30, 0x1, 0x1, X86_CHIPREV_AMD_KAVERI_REV_A1, "KV-A1",
624 X86_UARCHREV_AMD_LEGACY, A_SKTS_8 },
625 { 0x15, 0x30, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_KAVERI_UNKNOWN, "KV-??",
626 X86_UARCHREV_AMD_LEGACY, A_SKTS_8 },
627
628 /*
629 * The Carrizo rev guide mentions A0 as having an ID of "00600F00h" but
630 * this appears to be a typo as elsewhere it's given as "00660F00h". We
631 * assume the latter is correct.
632 */
633 { 0x15, 0x60, 0x60, 0x0, 0x0, X86_CHIPREV_AMD_CARRIZO_REV_A0, "CZ-A0",
634 X86_UARCHREV_AMD_LEGACY, A_SKTS_9 },
635 { 0x15, 0x60, 0x60, 0x1, 0x1, X86_CHIPREV_AMD_CARRIZO_REV_A1, "CZ-A1",
636 X86_UARCHREV_AMD_LEGACY, A_SKTS_9 },
637 /*
638 * CZ-DDR4 and BR-A1 are indistinguishable via cpuid; the rev guide
639 * indicates that they should be distinguished by the contents of the
640 * OSVW MSR, but this register is just a software scratch space which
641 * means the actual method of distinguishing the two is not documented
642 * and on PCs will be done by a BIOS. In the extremely unlikely event
643 * it becomes necessary to distinguish these, an OSVW-driven fixup can
644 * be added.
645 */
646 { 0x15, 0x65, 0x65, 0x1, 0x1, X86_CHIPREV_AMD_CARRIZO_REV_DDR4,
647 "CZ-DDR4", X86_UARCHREV_AMD_LEGACY, A_SKTS_9 },
648 { 0x15, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_CARRIZO_UNKNOWN, "CZ-??",
649 X86_UARCHREV_AMD_LEGACY, A_SKTS_9 },
650
651 { 0x15, 0x70, 0x70, 0x0, 0x0, X86_CHIPREV_AMD_STONEY_RIDGE_REV_A0,
652 "ST-A0", X86_UARCHREV_AMD_LEGACY, A_SKTS_10 },
653 { 0x15, 0x70, 0x7f, 0x0, 0xf, X86_CHIPREV_AMD_STONEY_RIDGE_UNKNOWN,
654 "ST-??", X86_UARCHREV_AMD_LEGACY, A_SKTS_10 },
655
656 /*
657 * =============== AuthenticAMD Family 0x16 ===============
658 */
659 { 0x16, 0x00, 0x00, 0x1, 0x1, X86_CHIPREV_AMD_KABINI_A1, "KB-A1",
660 X86_UARCHREV_AMD_LEGACY, A_SKTS_11 },
661 { 0x16, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_KABINI_UNKNOWN, "KB-??",
662 X86_UARCHREV_AMD_LEGACY, A_SKTS_11 },
663
664 { 0x16, 0x30, 0x30, 0x1, 0x1, X86_CHIPREV_AMD_MULLINS_A1, "ML-A1",
665 X86_UARCHREV_AMD_LEGACY, A_SKTS_12 },
666 { 0x16, 0x30, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_MULLINS_UNKNOWN, "ML-??",
667 X86_UARCHREV_AMD_LEGACY, A_SKTS_12 },
668
669 /*
670 * =============== AuthenticAMD Family 0x17 ===============
671 */
672 /* Naples == Zeppelin == ZP */
673 { 0x17, 0x00, 0x00, 0x0, 0x0, X86_CHIPREV_AMD_NAPLES_A0, "ZP-A0",
674 X86_UARCHREV_AMD_ZEN1, A_SKTS_NAPLES },
675 { 0x17, 0x01, 0x01, 0x1, 0x1, X86_CHIPREV_AMD_NAPLES_B1, "ZP-B1",
676 X86_UARCHREV_AMD_ZEN1, A_SKTS_NAPLES },
677 { 0x17, 0x01, 0x01, 0x2, 0x2, X86_CHIPREV_AMD_NAPLES_B2, "ZP-B2",
678 X86_UARCHREV_AMD_ZEN1, A_SKTS_NAPLES },
679 { 0x17, 0x00, 0x07, 0x0, 0xf, X86_CHIPREV_AMD_NAPLES_UNKNOWN, "ZP-??",
680 X86_UARCHREV_AMD_ZEN1, A_SKTS_NAPLES },
681 { 0x17, 0x08, 0x08, 0x2, 0x2, X86_CHIPREV_AMD_PINNACLE_RIDGE_B2,
682 "PiR-B2", X86_UARCHREV_AMD_ZENPLUS, A_SKTS_NAPLES },
683 { 0x17, 0x08, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_PINNACLE_RIDGE_UNKNOWN,
684 "PiR-??", X86_UARCHREV_AMD_ZENPLUS, A_SKTS_NAPLES },
685
686 { 0x17, 0x11, 0x11, 0x0, 0x0, X86_CHIPREV_AMD_RAVEN_RIDGE_B0,
687 "RV-B0", X86_UARCHREV_AMD_ZEN1, A_SKTS_RAVEN },
688 { 0x17, 0x11, 0x11, 0x1, 0x1, X86_CHIPREV_AMD_RAVEN_RIDGE_B1,
689 "RV-B1", X86_UARCHREV_AMD_ZEN1, A_SKTS_RAVEN },
690 { 0x17, 0x10, 0x17, 0x0, 0xf, X86_CHIPREV_AMD_RAVEN_RIDGE_UNKNOWN,
691 "RV-??", X86_UARCHREV_AMD_ZEN1, A_SKTS_RAVEN },
692 { 0x17, 0x18, 0x18, 0x1, 0x1, X86_CHIPREV_AMD_PICASSO_B1, "PCO-B1",
693 X86_UARCHREV_AMD_ZENPLUS, A_SKTS_RAVEN },
694 { 0x17, 0x18, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_PICASSO_UNKNOWN, "PCO-??",
695 X86_UARCHREV_AMD_ZENPLUS, A_SKTS_RAVEN },
696
697 { 0x17, 0x20, 0x20, 0x1, 0x1, X86_CHIPREV_AMD_DALI_A1, "RV2X-A1",
698 X86_UARCHREV_AMD_ZEN1, A_SKTS_RAVEN },
699 { 0x17, 0x20, 0x2f, 0x0, 0xf, X86_CHIPREV_AMD_DALI_UNKNOWN, "RV2X-??",
700 X86_UARCHREV_AMD_ZEN1, A_SKTS_RAVEN },
701
702 /* Rome == Starship == SSP */
703 { 0x17, 0x30, 0x30, 0x0, 0x0, X86_CHIPREV_AMD_ROME_A0, "SSP-A0",
704 X86_UARCHREV_AMD_ZEN2_A0, A_SKTS_ROME },
705 { 0x17, 0x31, 0x31, 0x0, 0x0, X86_CHIPREV_AMD_ROME_B0, "SSP-B0",
706 X86_UARCHREV_AMD_ZEN2_B0, A_SKTS_ROME },
707 { 0x17, 0x30, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_ROME_UNKNOWN, "SSP-??",
708 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_ROME },
709
710 { 0x17, 0x60, 0x60, 0x1, 0x1, X86_CHIPREV_AMD_RENOIR_A1, "RN-A1",
711 X86_UARCHREV_AMD_ZEN2_B0, A_SKTS_RENOIR },
712 { 0x17, 0x60, 0x67, 0x0, 0xf, X86_CHIPREV_AMD_RENOIR_UNKNOWN, "RN-??",
713 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_RENOIR },
714 { 0x17, 0x68, 0x68, 0x1, 0x1, X86_CHIPREV_AMD_RENOIR_LCN_A1, "LCN-A1",
715 X86_UARCHREV_AMD_ZEN2_B0, A_SKTS_RENOIR },
716 { 0x17, 0x68, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_RENOIR_UNKNOWN, "LCN-??",
717 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_RENOIR },
718
719 { 0x17, 0x71, 0x71, 0x0, 0x0, X86_CHIPREV_AMD_MATISSE_B0, "MTS-B0",
720 X86_UARCHREV_AMD_ZEN2_B0, A_SKTS_MATISSE },
721 { 0x17, 0x70, 0x7f, 0x0, 0xf, X86_CHIPREV_AMD_MATISSE_UNKNOWN, "MTS-??",
722 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_MATISSE },
723
724 { 0x17, 0x90, 0x97, 0x0, 0xf, X86_CHIPREV_AMD_VAN_GOGH_UNKNOWN, "??",
725 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_VANGOGH },
726 { 0x17, 0x98, 0x9f, 0x0, 0xf, X86_CHIPREV_AMD_VAN_GOGH_UNKNOWN, "??",
727 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_UNKNOWN },
728
729 { 0x17, 0xa0, 0xaf, 0x0, 0xf, X86_CHIPREV_AMD_MENDOCINO_UNKNOWN, "??",
730 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_MENDOCINO },
731
732 /*
733 * =============== HygonGenuine Family 0x18 ===============
734 */
735 { 0x18, 0x00, 0x00, 0x1, 0x1, X86_CHIPREV_HYGON_DHYANA_A1, "DN_A1",
736 X86_UARCHREV_AMD_ZEN1, A_SKTS_DHYANA },
737 { 0x18, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_HYGON_DHYANA_UNKNOWN, "DN_??",
738 X86_UARCHREV_AMD_ZEN1, A_SKTS_DHYANA },
739
740 /*
741 * =============== AuthenticAMD Family 0x19 ===============
742 */
743 /* Milan == Genesis == GN */
744 { 0x19, 0x00, 0x00, 0x0, 0x0, X86_CHIPREV_AMD_MILAN_A0, "GN-A0",
745 X86_UARCHREV_AMD_ZEN3_A0, A_SKTS_MILAN },
746 { 0x19, 0x01, 0x01, 0x0, 0x0, X86_CHIPREV_AMD_MILAN_B0, "GN-B0",
747 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_MILAN },
748 { 0x19, 0x01, 0x01, 0x1, 0x1, X86_CHIPREV_AMD_MILAN_B1, "GN-B1",
749 X86_UARCHREV_AMD_ZEN3_B1, A_SKTS_MILAN },
750 /* Marketed as Milan-X but still GN */
751 { 0x19, 0x01, 0x01, 0x2, 0x2, X86_CHIPREV_AMD_MILAN_B2, "GN-B2",
752 X86_UARCHREV_AMD_ZEN3_B2, A_SKTS_MILAN },
753 { 0x19, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_MILAN_UNKNOWN, "GN-??",
754 X86_UARCHREV_AMD_ZEN3_UNKNOWN, A_SKTS_MILAN },
755
756 /* Genoa == Stones == RS */
757 { 0x19, 0x10, 0x10, 0x0, 0x0, X86_CHIPREV_AMD_GENOA_A0, "RS-A0",
758 X86_UARCHREV_AMD_ZEN4_A0, A_SKTS_GENOA },
759 /* RS-A0 & RS-A1 both map to Zen 4 uarch A0 */
760 { 0x19, 0x10, 0x10, 0x1, 0x1, X86_CHIPREV_AMD_GENOA_A1, "RS-A1",
761 X86_UARCHREV_AMD_ZEN4_A0, A_SKTS_GENOA },
762 { 0x19, 0x11, 0x11, 0x0, 0x0, X86_CHIPREV_AMD_GENOA_B0, "RS-B0",
763 X86_UARCHREV_AMD_ZEN4_B0, A_SKTS_GENOA },
764 { 0x19, 0x11, 0x11, 0x1, 0x1, X86_CHIPREV_AMD_GENOA_B1, "RS-B1",
765 X86_UARCHREV_AMD_ZEN4_B1, A_SKTS_GENOA },
766 { 0x19, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_GENOA_UNKNOWN, "RS-??",
767 X86_UARCHREV_AMD_ZEN4_UNKNOWN, A_SKTS_GENOA },
768
769 { 0x19, 0x20, 0x20, 0x0, 0x0, X86_CHIPREV_AMD_VERMEER_A0, "VMR-A0",
770 X86_UARCHREV_AMD_ZEN3_A0, A_SKTS_VERMEER },
771 { 0x19, 0x21, 0x21, 0x0, 0x0, X86_CHIPREV_AMD_VERMEER_B0, "VMR-B0",
772 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_VERMEER },
773 { 0x19, 0x21, 0x21, 0x2, 0x2, X86_CHIPREV_AMD_VERMEER_B2, "VMR-B2",
774 X86_UARCHREV_AMD_ZEN3_B2, A_SKTS_VERMEER },
775 { 0x19, 0x20, 0x2f, 0x0, 0xf, X86_CHIPREV_AMD_VERMEER_UNKNOWN, "VMR-??",
776 X86_UARCHREV_AMD_ZEN3_UNKNOWN, A_SKTS_VERMEER },
777
778 /* Rev guide is missing AM5 information, including A0 and B0 */
779 { 0x19, 0x40, 0x40, 0x0, 0x0, X86_CHIPREV_AMD_REMBRANDT_A0, "RMB-A0",
780 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_REMBRANDT },
781 { 0x19, 0x44, 0x44, 0x0, 0x0, X86_CHIPREV_AMD_REMBRANDT_B0, "RMB-B0",
782 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_REMBRANDT },
783 { 0x19, 0x44, 0x44, 0x1, 0x1, X86_CHIPREV_AMD_REMBRANDT_B1, "RMB-B1",
784 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_REMBRANDT },
785 { 0x19, 0x40, 0x4f, 0x0, 0xf, X86_CHIPREV_AMD_REMBRANDT_UNKNOWN,
786 "RMB-??", X86_UARCHREV_AMD_ZEN3_UNKNOWN, A_SKTS_REMBRANDT },
787
788 /* Cezanne */
789 { 0x19, 0x50, 0x50, 0x0, 0x0, X86_CHIPREV_AMD_CEZANNE_A0, "CZN-A0",
790 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_CEZANNE },
791 { 0x19, 0x50, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_CEZANNE_UNKNOWN, "CZN-??",
792 X86_UARCHREV_AMD_ZEN3_UNKNOWN, A_SKTS_CEZANNE },
793
794 /* Raphael */
795 { 0x19, 0x61, 0x61, 0x2, 0x2, X86_CHIPREV_AMD_RAPHAEL_B2, "RPL-B2",
796 X86_UARCHREV_AMD_ZEN4_B2, A_SKTS_RAPHAEL },
797 { 0x19, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_RAPHAEL_UNKNOWN, "RPL-??",
798 X86_UARCHREV_AMD_ZEN4_UNKNOWN, A_SKTS_RAPHAEL },
799
800 /* Phoenix */
801 { 0x19, 0x74, 0x74, 0x1, 0x1, X86_CHIPREV_AMD_PHOENIX_A1, "PHX-A1",
802 X86_UARCHREV_AMD_ZEN4_A1, A_SKTS_PHOENIX },
803 { 0x19, 0x70, 0x7f, 0x0, 0xf, X86_CHIPREV_AMD_PHOENIX_UNKNOWN, "PHX-??",
804 X86_UARCHREV_AMD_ZEN4_UNKNOWN, A_SKTS_PHOENIX },
805
806 /* Bergamo / Siena */
807 { 0x19, 0xa0, 0xaf, 0x0, 0x0, X86_CHIPREV_AMD_BERGAMO_A0, "RSDN-A0",
808 X86_UARCHREV_AMD_ZEN4_A0, A_SKTS_BERGAMO },
809 { 0x19, 0xa0, 0xaf, 0x1, 0x1, X86_CHIPREV_AMD_BERGAMO_A1, "RSDN-A1",
810 X86_UARCHREV_AMD_ZEN4_A1, A_SKTS_BERGAMO },
811 { 0x19, 0xa0, 0xaf, 0x2, 0x2, X86_CHIPREV_AMD_BERGAMO_A2, "RSDN-A2",
812 X86_UARCHREV_AMD_ZEN4_A2, A_SKTS_BERGAMO },
813 { 0x19, 0xa0, 0xaf, 0x0, 0xf, X86_CHIPREV_AMD_BERGAMO_UNKNOWN, "???",
814 X86_UARCHREV_AMD_ZEN4_UNKNOWN, A_SKTS_BERGAMO },
815
816 /*
817 * =============== AuthenticAMD Family 0x1a ===============
818 */
819 /* Turin */
820 { 0x1a, 0x00, 0x00, 0x0, 0x0, X86_CHIPREV_AMD_TURIN_A0, "BRH-A0",
821 X86_UARCHREV_AMD_ZEN5_A0, A_SKTS_TURIN },
822 /* BRH-A0 & BRH-B0 both map to Zen 5 uarch A0 */
823 { 0x1a, 0x01, 0x01, 0x0, 0x0, X86_CHIPREV_AMD_TURIN_B0, "BRH-B0",
824 X86_UARCHREV_AMD_ZEN5_A0, A_SKTS_TURIN },
825 /* BRH-B1 maps to Zen 5 uarch B0 */
826 { 0x1a, 0x01, 0x01, 0x1, 0x1, X86_CHIPREV_AMD_TURIN_B1, "BRH-B1",
827 X86_UARCHREV_AMD_ZEN5_B0, A_SKTS_TURIN },
828 { 0x1a, 0x02, 0x02, 0x0, 0x0, X86_CHIPREV_AMD_TURIN_C0, "BRH-C0",
829 X86_UARCHREV_AMD_ZEN5_C0, A_SKTS_TURIN },
830 { 0x1a, 0x02, 0x02, 0x1, 0x1, X86_CHIPREV_AMD_TURIN_C1, "BRH-C1",
831 X86_UARCHREV_AMD_ZEN5_C1, A_SKTS_TURIN },
832 { 0x1a, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_TURIN_UNKNOWN, "BRH-???",
833 X86_UARCHREV_AMD_ZEN5_UNKNOWN, A_SKTS_TURIN },
834 { 0x1a, 0x10, 0x10, 0x0, 0x0, X86_CHIPREV_AMD_DENSE_TURIN_A0,
835 "BRHD-A0", X86_UARCHREV_AMD_ZEN5_A0, A_SKTS_TURIN },
836 { 0x1a, 0x11, 0x11, 0x0, 0x0, X86_CHIPREV_AMD_DENSE_TURIN_B0,
837 "BRHD-B0", X86_UARCHREV_AMD_ZEN5_B0, A_SKTS_TURIN },
838 /* BRHD-B0 & BRHD-B1 both map to Zen 5 uarch B0 */
839 { 0x1a, 0x11, 0x11, 0x1, 0x1, X86_CHIPREV_AMD_DENSE_TURIN_B1,
840 "BRHD-B1", X86_UARCHREV_AMD_ZEN5_B0, A_SKTS_TURIN },
841 { 0x1a, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_DENSE_TURIN_UNKNOWN,
842 "BRHD-???", X86_UARCHREV_AMD_ZEN5_UNKNOWN, A_SKTS_TURIN },
843
844 /* Strix and Krackan */
845 { 0x1a, 0x24, 0x24, 0x0, 0x0, X86_CHIPREV_AMD_STRIX_B0,
846 "STX-B0", X86_UARCHREV_AMD_ZEN5_B0, A_SKTS_STRIX },
847 { 0x1a, 0x20, 0x2f, 0x0, 0xf, X86_CHIPREV_AMD_STRIX_UNKNOWN,
848 "STX-???", X86_UARCHREV_AMD_ZEN5_UNKNOWN, A_SKTS_STRIX },
849 { 0x1a, 0x60, 0x60, 0x0, 0x0, X86_CHIPREV_AMD_KRACKAN_A0,
850 "KRK-A0", X86_UARCHREV_AMD_ZEN5_A0, A_SKTS_STRIX },
851 { 0x1a, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_KRACKAN_UNKNOWN,
852 "KRK-???", X86_UARCHREV_AMD_ZEN5_UNKNOWN, A_SKTS_STRIX },
853
854 /* Granite Ridge */
855 { 0x1a, 0x44, 0x44, 0x0, 0x0, X86_CHIPREV_AMD_GRANITE_RIDGE_B0,
856 "GNR-B0", X86_UARCHREV_AMD_ZEN5_B0, A_SKTS_GRANITE_RIDGE },
857 { 0x1a, 0x40, 0x4f, 0x0, 0xf, X86_CHIPREV_AMD_GRANITE_RIDGE_UNKNOWN,
858 "GNR-???", X86_UARCHREV_AMD_ZEN5_UNKNOWN, A_SKTS_GRANITE_RIDGE },
859
860 { 0x1a, 0x70, 0x70, 0x0, 0x0, X86_CHIPREV_AMD_STRIX_HALO_A0,
861 "STXH-A0", X86_UARCHREV_AMD_ZEN5_A0, A_SKTS_STRIX_HALO },
862 { 0x1a, 0x70, 0x77, 0x0, 0xf, X86_CHIPREV_AMD_STRIX_HALO_UNKNOWN,
863 "STXH-???", X86_UARCHREV_AMD_ZEN5_UNKNOWN, A_SKTS_STRIX_HALO }
864 };
865
866 /*
867 * AMD keeps the socket type in CPUID Fn8000_0001_EBX, bits 31:28.
868 */
869 static uint32_t
synth_amd_skt_cpuid(uint_t family,uint_t sktid)870 synth_amd_skt_cpuid(uint_t family, uint_t sktid)
871 {
872 struct cpuid_regs cp;
873 uint_t idx;
874
875 cp.cp_eax = 0x80000001;
876 (void) __cpuid_insn(&cp);
877
878 /* PkgType bits */
879 idx = BITX(cp.cp_ebx, 31, 28);
880
881 if (family == 0x10) {
882 uint32_t val;
883
884 val = pci_getl_func(0, 24, 2, 0x94);
885 if (BITX(val, 8, 8)) {
886 if (amd_skts[sktid][idx] == X86_SOCKET_AM2R2) {
887 return (X86_SOCKET_AM3);
888 } else if (amd_skts[sktid][idx] == X86_SOCKET_S1g3) {
889 return (X86_SOCKET_S1g4);
890 }
891 }
892 }
893
894 return (amd_skts[sktid][idx]);
895 }
896
897 static void
synth_amd_info(uint_t family,uint_t model,uint_t step,uint32_t * skt_p,x86_chiprev_t * chiprev_p,const char ** chiprevstr_p,x86_uarchrev_t * uarchrev_p)898 synth_amd_info(uint_t family, uint_t model, uint_t step,
899 uint32_t *skt_p, x86_chiprev_t *chiprev_p, const char **chiprevstr_p,
900 x86_uarchrev_t *uarchrev_p)
901 {
902 const struct amd_rev_mapent *rmp;
903 int found = 0;
904 int i;
905
906 if (family < 0xf)
907 return;
908
909 for (i = 0, rmp = amd_revmap; i < ARRAY_SIZE(amd_revmap); i++, rmp++) {
910 if (family == rmp->rm_family &&
911 model >= rmp->rm_modello && model <= rmp->rm_modelhi &&
912 step >= rmp->rm_steplo && step <= rmp->rm_stephi) {
913 found = 1;
914 break;
915 }
916 }
917
918 if (found) {
919 if (chiprev_p != NULL)
920 *chiprev_p = rmp->rm_chiprev;
921 if (chiprevstr_p != NULL)
922 *chiprevstr_p = rmp->rm_chiprevstr;
923 if (uarchrev_p != NULL)
924 *uarchrev_p = rmp->rm_uarchrev;
925 }
926
927 if (skt_p != NULL) {
928 int platform;
929
930 #ifdef __xpv
931 /* PV guest */
932 if (!is_controldom()) {
933 *skt_p = X86_SOCKET_UNKNOWN;
934 return;
935 }
936 #endif
937 platform = get_hwenv();
938
939 if ((platform & HW_VIRTUAL) != 0) {
940 *skt_p = X86_SOCKET_UNKNOWN;
941 return;
942 }
943
944 if (!found)
945 return;
946
947 if (family == 0xf) {
948 *skt_p = amd_skts[rmp->rm_sktidx][model & 0x3];
949 } else {
950 *skt_p = synth_amd_skt_cpuid(family, rmp->rm_sktidx);
951 }
952 }
953 }
954
955 uint32_t
_cpuid_skt(uint_t vendor,uint_t family,uint_t model,uint_t step)956 _cpuid_skt(uint_t vendor, uint_t family, uint_t model, uint_t step)
957 {
958 uint32_t skt = X86_SOCKET_UNKNOWN;
959
960 switch (vendor) {
961 case X86_VENDOR_AMD:
962 case X86_VENDOR_HYGON:
963 synth_amd_info(family, model, step, &skt, NULL, NULL, NULL);
964 break;
965
966 default:
967 break;
968
969 }
970
971 return (skt);
972 }
973
974 const char *
_cpuid_sktstr(uint_t vendor,uint_t family,uint_t model,uint_t step)975 _cpuid_sktstr(uint_t vendor, uint_t family, uint_t model, uint_t step)
976 {
977 const char *sktstr = "Unknown";
978 struct amd_sktmap_s *sktmapp;
979 uint32_t skt = X86_SOCKET_UNKNOWN;
980
981 switch (vendor) {
982 case X86_VENDOR_AMD:
983 case X86_VENDOR_HYGON:
984 synth_amd_info(family, model, step, &skt, NULL, NULL, NULL);
985
986 sktmapp = amd_sktmap_strs;
987 while (sktmapp->skt_code != X86_SOCKET_UNKNOWN) {
988 if (sktmapp->skt_code == skt)
989 break;
990 sktmapp++;
991 }
992 sktstr = sktmapp->sktstr;
993 break;
994
995 default:
996 break;
997
998 }
999
1000 return (sktstr);
1001 }
1002
1003 x86_chiprev_t
_cpuid_chiprev(uint_t vendor,uint_t family,uint_t model,uint_t step)1004 _cpuid_chiprev(uint_t vendor, uint_t family, uint_t model, uint_t step)
1005 {
1006 x86_chiprev_t chiprev = X86_CHIPREV_UNKNOWN;
1007
1008 switch (vendor) {
1009 case X86_VENDOR_AMD:
1010 case X86_VENDOR_HYGON:
1011 synth_amd_info(family, model, step, NULL, &chiprev, NULL, NULL);
1012 break;
1013
1014 default:
1015 break;
1016
1017 }
1018
1019 return (chiprev);
1020 }
1021
1022 x86_uarchrev_t
_cpuid_uarchrev(uint_t vendor,uint_t family,uint_t model,uint_t step)1023 _cpuid_uarchrev(uint_t vendor, uint_t family, uint_t model, uint_t step)
1024 {
1025 x86_uarchrev_t uarchrev = X86_UARCHREV_UNKNOWN;
1026
1027 switch (vendor) {
1028 case X86_VENDOR_AMD:
1029 case X86_VENDOR_HYGON:
1030 synth_amd_info(family, model, step, NULL, NULL, NULL,
1031 &uarchrev);
1032 break;
1033
1034 default:
1035 break;
1036
1037 }
1038
1039 return (uarchrev);
1040 }
1041
1042 const char *
_cpuid_chiprevstr(uint_t vendor,uint_t family,uint_t model,uint_t step)1043 _cpuid_chiprevstr(uint_t vendor, uint_t family, uint_t model, uint_t step)
1044 {
1045 const char *revstr = "Unknown";
1046
1047 switch (vendor) {
1048 case X86_VENDOR_AMD:
1049 case X86_VENDOR_HYGON:
1050 synth_amd_info(family, model, step, NULL, NULL, &revstr, NULL);
1051 break;
1052
1053 default:
1054 break;
1055
1056 }
1057
1058 return (revstr);
1059
1060 }
1061
1062 /*
1063 * Map the vendor string to a type code
1064 */
1065 uint_t
_cpuid_vendorstr_to_vendorcode(char * vendorstr)1066 _cpuid_vendorstr_to_vendorcode(char *vendorstr)
1067 {
1068 if (strcmp(vendorstr, X86_VENDORSTR_Intel) == 0)
1069 return (X86_VENDOR_Intel);
1070 else if (strcmp(vendorstr, X86_VENDORSTR_AMD) == 0)
1071 return (X86_VENDOR_AMD);
1072 else if (strcmp(vendorstr, X86_VENDORSTR_HYGON) == 0)
1073 return (X86_VENDOR_HYGON);
1074 else if (strcmp(vendorstr, X86_VENDORSTR_TM) == 0)
1075 return (X86_VENDOR_TM);
1076 else if (strcmp(vendorstr, X86_VENDORSTR_CYRIX) == 0)
1077 return (X86_VENDOR_Cyrix);
1078 else if (strcmp(vendorstr, X86_VENDORSTR_UMC) == 0)
1079 return (X86_VENDOR_UMC);
1080 else if (strcmp(vendorstr, X86_VENDORSTR_NexGen) == 0)
1081 return (X86_VENDOR_NexGen);
1082 else if (strcmp(vendorstr, X86_VENDORSTR_Centaur) == 0)
1083 return (X86_VENDOR_Centaur);
1084 else if (strcmp(vendorstr, X86_VENDORSTR_Rise) == 0)
1085 return (X86_VENDOR_Rise);
1086 else if (strcmp(vendorstr, X86_VENDORSTR_SiS) == 0)
1087 return (X86_VENDOR_SiS);
1088 else if (strcmp(vendorstr, X86_VENDORSTR_NSC) == 0)
1089 return (X86_VENDOR_NSC);
1090 else
1091 return (X86_VENDOR_IntelClone);
1092 }
1093