Searched defs:__base (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/clocksource/ |
| H A D | timer-nxp-stm.c | 25 #define STM_CR(__base) (__base) argument
32 #define STM_CNT(__base) ((__base) + 0x04) argument
34 #define STM_CCR0(__base) ((__base) + 0x10) argument
35 #define STM_CCR1(__base) ((__base) + 0x20) argument
36 #define STM_CCR2(__base) ((__base) + 0x30) argument
37 #define STM_CCR3(__base) ((__base) + 0x40) argument
41 #define STM_CIR0(__base) ((__base) + 0x14) argument
42 #define STM_CIR1(__base) ((__base) + 0x24) argument
43 #define STM_CIR2(__base) ((__base) + 0x34) argument
44 #define STM_CIR3(__base) ((__base) + 0x44) argument
[all …]
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| H A D | timer-nxp-pit.c | 21 #define PITMCR(__base) (__base) argument
26 #define PITLDVAL(__base) (__base) argument
27 #define PITTCTRL(__base) ((__base) + 0x08) argument
30 #define PITCVAL(__base) ((__base) + 0x04) argument
35 #define PITTFLG(__base) ((__base) + 0x0c) argument
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| /linux/drivers/watchdog/ |
| H A D | s32g_wdt.c | 20 #define S32G_SWT_CR(__base) ((__base) + 0x00) /* Control Register offset */ argument
26 #define S32G_SWT_TO(__base) ((__base) + 0x08) /* Timeout Register offset */ argument
28 #define S32G_SWT_SR(__base) ((__base) + 0x10) /* Service Register offset */ argument
32 #define S32G_SWT_CO(__base) ((__base) + 0x14) /* Counter output register */ argument
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| /linux/include/net/netfilter/ |
| H A D | nf_tables_offload.h | 79 #define NFT_OFFLOAD_MATCH_FLAGS(__key, __base, __field, __len, __reg, __flags) \ argument
88 #define NFT_OFFLOAD_MATCH(__key, __base, __field, __len, __reg) \ argument
91 #define NFT_OFFLOAD_MATCH_EXACT(__key, __base, __field, __len, __reg) \ argument
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| /linux/drivers/gpu/drm/vmwgfx/ |
| H A D | ttm_object.h | 285 #define ttm_base_object_kfree(__object, __base)\ argument
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| /linux/drivers/net/wireless/ralink/rt2x00/ |
| H A D | rt2x00queue.c | 1113 #define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \ in rt2x00queue_alloc_entries() argument
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