xref: /linux/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef __DPU_RM_H__
7 #define __DPU_RM_H__
8 
9 #include <linux/list.h>
10 
11 #include "msm_kms.h"
12 #include "dpu_hw_top.h"
13 
14 struct dpu_global_state;
15 
16 /**
17  * struct dpu_rm - DPU dynamic hardware resource manager
18  * @pingpong_blks: array of pingpong hardware resources
19  * @mixer_blks: array of layer mixer hardware resources
20  * @ctl_blks: array of ctl hardware resources
21  * @hw_intf: array of intf hardware resources
22  * @hw_wb: array of wb hardware resources
23  * @hw_cwb: array of cwb hardware resources
24  * @dspp_blks: array of dspp hardware resources
25  * @hw_sspp: array of sspp hardware resources
26  * @cdm_blk: cdm hardware resource
27  */
28 struct dpu_rm {
29 	struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
30 	struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];
31 	struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];
32 	struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0];
33 	struct dpu_hw_wb *hw_wb[WB_MAX - WB_0];
34 	struct dpu_hw_blk *cwb_blks[CWB_MAX - CWB_0];
35 	struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
36 	struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
37 	struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
38 	struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
39 	struct dpu_hw_blk *cdm_blk;
40 };
41 
42 struct dpu_rm_sspp_requirements {
43 	bool yuv;
44 	bool scale;
45 	bool rot90;
46 };
47 
48 /**
49  * struct msm_display_topology - defines a display topology pipeline
50  * @num_lm:       number of layer mixers used
51  * @num_intf:     number of interfaces the panel is mounted on
52  * @num_dspp:     number of dspp blocks used
53  * @num_dsc:      number of Display Stream Compression (DSC) blocks used
54  * @needs_cdm:    indicates whether cdm block is needed for this display topology
55  */
56 struct msm_display_topology {
57 	u32 num_lm;
58 	u32 num_intf;
59 	u32 num_dspp;
60 	u32 num_dsc;
61 	bool needs_cdm;
62 };
63 
64 int dpu_rm_init(struct drm_device *dev,
65 		struct dpu_rm *rm,
66 		const struct dpu_mdss_cfg *cat,
67 		const struct msm_mdss_data *mdss_data,
68 		void __iomem *mmio);
69 
70 int dpu_rm_reserve(struct dpu_rm *rm,
71 		struct dpu_global_state *global_state,
72 		struct drm_encoder *drm_enc,
73 		struct drm_crtc_state *crtc_state,
74 		struct msm_display_topology *topology);
75 
76 void dpu_rm_release(struct dpu_global_state *global_state,
77 		struct drm_encoder *enc);
78 
79 struct dpu_hw_sspp *dpu_rm_reserve_sspp(struct dpu_rm *rm,
80 					struct dpu_global_state *global_state,
81 					struct drm_crtc *crtc,
82 					struct dpu_rm_sspp_requirements *reqs);
83 
84 void dpu_rm_release_all_sspp(struct dpu_global_state *global_state,
85 			     struct drm_crtc *crtc);
86 
87 int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
88 	struct dpu_global_state *global_state, uint32_t enc_id,
89 	enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size);
90 
91 void dpu_rm_print_state(struct drm_printer *p,
92 			const struct dpu_global_state *global_state);
93 
94 /**
95  * dpu_rm_get_intf - Return a struct dpu_hw_intf instance given it's index.
96  * @rm: DPU Resource Manager handle
97  * @intf_idx: INTF's index
98  */
dpu_rm_get_intf(struct dpu_rm * rm,enum dpu_intf intf_idx)99 static inline struct dpu_hw_intf *dpu_rm_get_intf(struct dpu_rm *rm, enum dpu_intf intf_idx)
100 {
101 	return rm->hw_intf[intf_idx - INTF_0];
102 }
103 
104 /**
105  * dpu_rm_get_wb - Return a struct dpu_hw_wb instance given it's index.
106  * @rm: DPU Resource Manager handle
107  * @wb_idx: WB index
108  */
dpu_rm_get_wb(struct dpu_rm * rm,enum dpu_wb wb_idx)109 static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_idx)
110 {
111 	return rm->hw_wb[wb_idx - WB_0];
112 }
113 
114 /**
115  * dpu_rm_get_sspp - Return a struct dpu_hw_sspp instance given it's index.
116  * @rm: DPU Resource Manager handle
117  * @sspp_idx: SSPP index
118  */
dpu_rm_get_sspp(struct dpu_rm * rm,enum dpu_sspp sspp_idx)119 static inline struct dpu_hw_sspp *dpu_rm_get_sspp(struct dpu_rm *rm, enum dpu_sspp sspp_idx)
120 {
121 	return rm->hw_sspp[sspp_idx - SSPP_NONE];
122 }
123 
124 #endif /* __DPU_RM_H__ */
125 
126