1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 * 25 * Copyright 2020 OmniOS Community Edition (OmniOSce) Association. 26 * 27 */ 28 29 #ifndef _SYS_PCI_CFGACC_X86_H 30 #define _SYS_PCI_CFGACC_X86_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* AMD's northbridges vendor-id and device-ids */ 37 #define AMD_NTBRDIGE_VID 0x1022 /* AMD vendor-id */ 38 #define AMD_HT_NTBRIDGE_DID 0x1100 /* HT Configuration */ 39 #define AMD_AM_NTBRIDGE_DID 0x1101 /* Address Map */ 40 #define AMD_DC_NTBRIDGE_DID 0x1102 /* DRAM Controller */ 41 #define AMD_MC_NTBRIDGE_DID 0x1103 /* Misc Controller */ 42 #define AMD_K10_NTBRIDGE_DID_0 0x1200 43 #define AMD_K10_NTBRIDGE_DID_1 0x1201 44 #define AMD_K10_NTBRIDGE_DID_2 0x1202 45 #define AMD_K10_NTBRIDGE_DID_3 0x1203 46 #define AMD_K10_NTBRIDGE_DID_4 0x1204 47 48 /* AMD's 8132 chipset vendor-id and device-ids */ 49 #define AMD_8132_BRIDGE_DID 0x7458 /* 8132 PCI-X bridge */ 50 #define AMD_8132_IOAPIC_DID 0x7459 /* 8132 IO APIC */ 51 52 /* 53 * Check if the given device is an AMD northbridge 54 */ 55 #define IS_BAD_AMD_NTBRIDGE(vid, did) \ 56 (((vid) == AMD_NTBRDIGE_VID) && \ 57 (((did) == AMD_HT_NTBRIDGE_DID) || \ 58 ((did) == AMD_AM_NTBRIDGE_DID) || \ 59 ((did) == AMD_DC_NTBRIDGE_DID) || \ 60 ((did) == AMD_MC_NTBRIDGE_DID))) 61 62 #define IS_K10_AMD_NTBRIDGE(vid, did) \ 63 (((vid) == AMD_NTBRDIGE_VID) && \ 64 (((did) == AMD_K10_NTBRIDGE_DID_0) || \ 65 ((did) == AMD_K10_NTBRIDGE_DID_1) || \ 66 ((did) == AMD_K10_NTBRIDGE_DID_2) || \ 67 ((did) == AMD_K10_NTBRIDGE_DID_3) || \ 68 ((did) == AMD_K10_NTBRIDGE_DID_4))) 69 70 #define IS_AMD_8132_CHIP(vid, did) \ 71 (((vid) == AMD_NTBRDIGE_VID) && \ 72 (((did) == AMD_8132_BRIDGE_DID) || \ 73 ((did) == AMD_8132_IOAPIC_DID))) 74 75 #define MSR_AMD_NB_MMIO_CFG_BADDR 0xc0010058 76 #define AMD_MMIO_CFG_BADDR_ADDR_MASK 0xFFFFFFF00000ULL 77 #define AMD_MMIO_CFG_BADDR_ENA_MASK 0x000000000001ULL 78 #define AMD_MMIO_CFG_BADDR_ENA_ON 0x000000000001ULL 79 #define AMD_MMIO_CFG_BADDR_ENA_OFF 0x000000000000ULL 80 81 #ifdef __cplusplus 82 } 83 #endif 84 85 #endif /* _SYS_PCI_CFGACC_X86_H */ 86