1 /*- 2 * Copyright (c) 2015-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31 #ifndef _SYS_EF10_IMPL_H 32 #define _SYS_EF10_IMPL_H 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /* Number of hardware PIO buffers (for compile-time resource dimensions) */ 39 #define EF10_MAX_PIOBUF_NBUFS (16) 40 41 #if EFSYS_OPT_HUNTINGTON 42 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS) 43 # error "EF10_MAX_PIOBUF_NBUFS too small" 44 # endif 45 #endif /* EFSYS_OPT_HUNTINGTON */ 46 #if EFSYS_OPT_MEDFORD 47 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS) 48 # error "EF10_MAX_PIOBUF_NBUFS too small" 49 # endif 50 #endif /* EFSYS_OPT_MEDFORD */ 51 #if EFSYS_OPT_MEDFORD2 52 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS) 53 # error "EF10_MAX_PIOBUF_NBUFS too small" 54 # endif 55 #endif /* EFSYS_OPT_MEDFORD2 */ 56 57 /* 58 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could 59 * possibly be increased, or the write size reported by newer firmware used 60 * instead. 61 */ 62 #define EF10_NVRAM_CHUNK 0x80 63 64 /* 65 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned 66 * to an 8 descriptor boundary. 67 */ 68 #define EF10_RX_WPTR_ALIGN 8 69 70 /* 71 * Max byte offset into the packet the TCP header must start for the hardware 72 * to be able to parse the packet correctly. 73 */ 74 #define EF10_TCP_HEADER_OFFSET_LIMIT 208 75 76 /* Invalid RSS context handle */ 77 #define EF10_RSS_CONTEXT_INVALID (0xffffffff) 78 79 /* EV */ 80 81 __checkReturn efx_rc_t 82 ef10_ev_init( 83 __in efx_nic_t *enp); 84 85 void 86 ef10_ev_fini( 87 __in efx_nic_t *enp); 88 89 __checkReturn efx_rc_t 90 ef10_ev_qcreate( 91 __in efx_nic_t *enp, 92 __in unsigned int index, 93 __in efsys_mem_t *esmp, 94 __in size_t ndescs, 95 __in uint32_t id, 96 __in uint32_t us, 97 __in uint32_t flags, 98 __in efx_evq_t *eep); 99 100 void 101 ef10_ev_qdestroy( 102 __in efx_evq_t *eep); 103 104 __checkReturn efx_rc_t 105 ef10_ev_qprime( 106 __in efx_evq_t *eep, 107 __in unsigned int count); 108 109 void 110 ef10_ev_qpost( 111 __in efx_evq_t *eep, 112 __in uint16_t data); 113 114 __checkReturn efx_rc_t 115 ef10_ev_qmoderate( 116 __in efx_evq_t *eep, 117 __in unsigned int us); 118 119 #if EFSYS_OPT_QSTATS 120 void 121 ef10_ev_qstats_update( 122 __in efx_evq_t *eep, 123 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 124 #endif /* EFSYS_OPT_QSTATS */ 125 126 void 127 ef10_ev_rxlabel_init( 128 __in efx_evq_t *eep, 129 __in efx_rxq_t *erp, 130 __in unsigned int label, 131 __in efx_rxq_type_t type); 132 133 void 134 ef10_ev_rxlabel_fini( 135 __in efx_evq_t *eep, 136 __in unsigned int label); 137 138 /* INTR */ 139 140 __checkReturn efx_rc_t 141 ef10_intr_init( 142 __in efx_nic_t *enp, 143 __in efx_intr_type_t type, 144 __in efsys_mem_t *esmp); 145 146 void 147 ef10_intr_enable( 148 __in efx_nic_t *enp); 149 150 void 151 ef10_intr_disable( 152 __in efx_nic_t *enp); 153 154 void 155 ef10_intr_disable_unlocked( 156 __in efx_nic_t *enp); 157 158 __checkReturn efx_rc_t 159 ef10_intr_trigger( 160 __in efx_nic_t *enp, 161 __in unsigned int level); 162 163 void 164 ef10_intr_status_line( 165 __in efx_nic_t *enp, 166 __out boolean_t *fatalp, 167 __out uint32_t *qmaskp); 168 169 void 170 ef10_intr_status_message( 171 __in efx_nic_t *enp, 172 __in unsigned int message, 173 __out boolean_t *fatalp); 174 175 void 176 ef10_intr_fatal( 177 __in efx_nic_t *enp); 178 void 179 ef10_intr_fini( 180 __in efx_nic_t *enp); 181 182 /* NIC */ 183 184 extern __checkReturn efx_rc_t 185 ef10_nic_probe( 186 __in efx_nic_t *enp); 187 188 extern __checkReturn efx_rc_t 189 ef10_nic_set_drv_limits( 190 __inout efx_nic_t *enp, 191 __in efx_drv_limits_t *edlp); 192 193 extern __checkReturn efx_rc_t 194 ef10_nic_get_vi_pool( 195 __in efx_nic_t *enp, 196 __out uint32_t *vi_countp); 197 198 extern __checkReturn efx_rc_t 199 ef10_nic_get_bar_region( 200 __in efx_nic_t *enp, 201 __in efx_nic_region_t region, 202 __out uint32_t *offsetp, 203 __out size_t *sizep); 204 205 extern __checkReturn efx_rc_t 206 ef10_nic_reset( 207 __in efx_nic_t *enp); 208 209 extern __checkReturn efx_rc_t 210 ef10_nic_init( 211 __in efx_nic_t *enp); 212 213 extern __checkReturn boolean_t 214 ef10_nic_hw_unavailable( 215 __in efx_nic_t *enp); 216 217 extern void 218 ef10_nic_set_hw_unavailable( 219 __in efx_nic_t *enp); 220 221 #if EFSYS_OPT_DIAG 222 223 extern __checkReturn efx_rc_t 224 ef10_nic_register_test( 225 __in efx_nic_t *enp); 226 227 #endif /* EFSYS_OPT_DIAG */ 228 229 extern void 230 ef10_nic_fini( 231 __in efx_nic_t *enp); 232 233 extern void 234 ef10_nic_unprobe( 235 __in efx_nic_t *enp); 236 237 /* MAC */ 238 239 extern __checkReturn efx_rc_t 240 ef10_mac_poll( 241 __in efx_nic_t *enp, 242 __out efx_link_mode_t *link_modep); 243 244 extern __checkReturn efx_rc_t 245 ef10_mac_up( 246 __in efx_nic_t *enp, 247 __out boolean_t *mac_upp); 248 249 extern __checkReturn efx_rc_t 250 ef10_mac_addr_set( 251 __in efx_nic_t *enp); 252 253 extern __checkReturn efx_rc_t 254 ef10_mac_pdu_set( 255 __in efx_nic_t *enp); 256 257 extern __checkReturn efx_rc_t 258 ef10_mac_pdu_get( 259 __in efx_nic_t *enp, 260 __out size_t *pdu); 261 262 extern __checkReturn efx_rc_t 263 ef10_mac_reconfigure( 264 __in efx_nic_t *enp); 265 266 extern __checkReturn efx_rc_t 267 ef10_mac_multicast_list_set( 268 __in efx_nic_t *enp); 269 270 extern __checkReturn efx_rc_t 271 ef10_mac_filter_default_rxq_set( 272 __in efx_nic_t *enp, 273 __in efx_rxq_t *erp, 274 __in boolean_t using_rss); 275 276 extern void 277 ef10_mac_filter_default_rxq_clear( 278 __in efx_nic_t *enp); 279 280 #if EFSYS_OPT_LOOPBACK 281 282 extern __checkReturn efx_rc_t 283 ef10_mac_loopback_set( 284 __in efx_nic_t *enp, 285 __in efx_link_mode_t link_mode, 286 __in efx_loopback_type_t loopback_type); 287 288 #endif /* EFSYS_OPT_LOOPBACK */ 289 290 #if EFSYS_OPT_MAC_STATS 291 292 extern __checkReturn efx_rc_t 293 ef10_mac_stats_get_mask( 294 __in efx_nic_t *enp, 295 __inout_bcount(mask_size) uint32_t *maskp, 296 __in size_t mask_size); 297 298 extern __checkReturn efx_rc_t 299 ef10_mac_stats_update( 300 __in efx_nic_t *enp, 301 __in efsys_mem_t *esmp, 302 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 303 __inout_opt uint32_t *generationp); 304 305 #endif /* EFSYS_OPT_MAC_STATS */ 306 307 /* MCDI */ 308 309 #if EFSYS_OPT_MCDI 310 311 extern __checkReturn efx_rc_t 312 ef10_mcdi_init( 313 __in efx_nic_t *enp, 314 __in const efx_mcdi_transport_t *mtp); 315 316 extern void 317 ef10_mcdi_fini( 318 __in efx_nic_t *enp); 319 320 extern void 321 ef10_mcdi_send_request( 322 __in efx_nic_t *enp, 323 __in_bcount(hdr_len) void *hdrp, 324 __in size_t hdr_len, 325 __in_bcount(sdu_len) void *sdup, 326 __in size_t sdu_len); 327 328 extern __checkReturn boolean_t 329 ef10_mcdi_poll_response( 330 __in efx_nic_t *enp); 331 332 extern void 333 ef10_mcdi_read_response( 334 __in efx_nic_t *enp, 335 __out_bcount(length) void *bufferp, 336 __in size_t offset, 337 __in size_t length); 338 339 extern efx_rc_t 340 ef10_mcdi_poll_reboot( 341 __in efx_nic_t *enp); 342 343 extern __checkReturn efx_rc_t 344 ef10_mcdi_feature_supported( 345 __in efx_nic_t *enp, 346 __in efx_mcdi_feature_id_t id, 347 __out boolean_t *supportedp); 348 349 extern void 350 ef10_mcdi_get_timeout( 351 __in efx_nic_t *enp, 352 __in efx_mcdi_req_t *emrp, 353 __out uint32_t *timeoutp); 354 355 #endif /* EFSYS_OPT_MCDI */ 356 357 /* NVRAM */ 358 359 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 360 361 extern __checkReturn efx_rc_t 362 ef10_nvram_buf_read_tlv( 363 __in efx_nic_t *enp, 364 __in_bcount(max_seg_size) caddr_t seg_data, 365 __in size_t max_seg_size, 366 __in uint32_t tag, 367 __deref_out_bcount_opt(*sizep) caddr_t *datap, 368 __out size_t *sizep); 369 370 extern __checkReturn efx_rc_t 371 ef10_nvram_buf_write_tlv( 372 __inout_bcount(partn_size) caddr_t partn_data, 373 __in size_t partn_size, 374 __in uint32_t tag, 375 __in_bcount(tag_size) caddr_t tag_data, 376 __in size_t tag_size, 377 __out size_t *total_lengthp); 378 379 extern __checkReturn efx_rc_t 380 ef10_nvram_partn_read_tlv( 381 __in efx_nic_t *enp, 382 __in uint32_t partn, 383 __in uint32_t tag, 384 __deref_out_bcount_opt(*sizep) caddr_t *datap, 385 __out size_t *sizep); 386 387 extern __checkReturn efx_rc_t 388 ef10_nvram_partn_write_tlv( 389 __in efx_nic_t *enp, 390 __in uint32_t partn, 391 __in uint32_t tag, 392 __in_bcount(size) caddr_t data, 393 __in size_t size); 394 395 extern __checkReturn efx_rc_t 396 ef10_nvram_partn_write_segment_tlv( 397 __in efx_nic_t *enp, 398 __in uint32_t partn, 399 __in uint32_t tag, 400 __in_bcount(size) caddr_t data, 401 __in size_t size, 402 __in boolean_t all_segments); 403 404 extern __checkReturn efx_rc_t 405 ef10_nvram_partn_lock( 406 __in efx_nic_t *enp, 407 __in uint32_t partn); 408 409 extern __checkReturn efx_rc_t 410 ef10_nvram_partn_unlock( 411 __in efx_nic_t *enp, 412 __in uint32_t partn, 413 __out_opt uint32_t *resultp); 414 415 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 416 417 #if EFSYS_OPT_NVRAM 418 419 #if EFSYS_OPT_DIAG 420 421 extern __checkReturn efx_rc_t 422 ef10_nvram_test( 423 __in efx_nic_t *enp); 424 425 #endif /* EFSYS_OPT_DIAG */ 426 427 extern __checkReturn efx_rc_t 428 ef10_nvram_type_to_partn( 429 __in efx_nic_t *enp, 430 __in efx_nvram_type_t type, 431 __out uint32_t *partnp); 432 433 extern __checkReturn efx_rc_t 434 ef10_nvram_partn_size( 435 __in efx_nic_t *enp, 436 __in uint32_t partn, 437 __out size_t *sizep); 438 439 extern __checkReturn efx_rc_t 440 ef10_nvram_partn_rw_start( 441 __in efx_nic_t *enp, 442 __in uint32_t partn, 443 __out size_t *chunk_sizep); 444 445 extern __checkReturn efx_rc_t 446 ef10_nvram_partn_read_mode( 447 __in efx_nic_t *enp, 448 __in uint32_t partn, 449 __in unsigned int offset, 450 __out_bcount(size) caddr_t data, 451 __in size_t size, 452 __in uint32_t mode); 453 454 extern __checkReturn efx_rc_t 455 ef10_nvram_partn_read( 456 __in efx_nic_t *enp, 457 __in uint32_t partn, 458 __in unsigned int offset, 459 __in_bcount(size) caddr_t data, 460 __in size_t size); 461 462 extern __checkReturn efx_rc_t 463 ef10_nvram_partn_read_backup( 464 __in efx_nic_t *enp, 465 __in uint32_t partn, 466 __in unsigned int offset, 467 __out_bcount(size) caddr_t data, 468 __in size_t size); 469 470 extern __checkReturn efx_rc_t 471 ef10_nvram_partn_erase( 472 __in efx_nic_t *enp, 473 __in uint32_t partn, 474 __in unsigned int offset, 475 __in size_t size); 476 477 extern __checkReturn efx_rc_t 478 ef10_nvram_partn_write( 479 __in efx_nic_t *enp, 480 __in uint32_t partn, 481 __in unsigned int offset, 482 __out_bcount(size) caddr_t data, 483 __in size_t size); 484 485 extern __checkReturn efx_rc_t 486 ef10_nvram_partn_rw_finish( 487 __in efx_nic_t *enp, 488 __in uint32_t partn, 489 __out_opt uint32_t *verify_resultp); 490 491 extern __checkReturn efx_rc_t 492 ef10_nvram_partn_get_version( 493 __in efx_nic_t *enp, 494 __in uint32_t partn, 495 __out uint32_t *subtypep, 496 __out_ecount(4) uint16_t version[4]); 497 498 extern __checkReturn efx_rc_t 499 ef10_nvram_partn_set_version( 500 __in efx_nic_t *enp, 501 __in uint32_t partn, 502 __in_ecount(4) uint16_t version[4]); 503 504 extern __checkReturn efx_rc_t 505 ef10_nvram_buffer_validate( 506 __in uint32_t partn, 507 __in_bcount(buffer_size) 508 caddr_t bufferp, 509 __in size_t buffer_size); 510 511 extern void 512 ef10_nvram_buffer_init( 513 __out_bcount(buffer_size) 514 caddr_t bufferp, 515 __in size_t buffer_size); 516 517 extern __checkReturn efx_rc_t 518 ef10_nvram_buffer_create( 519 __in uint32_t partn_type, 520 __out_bcount(buffer_size) 521 caddr_t bufferp, 522 __in size_t buffer_size); 523 524 extern __checkReturn efx_rc_t 525 ef10_nvram_buffer_find_item_start( 526 __in_bcount(buffer_size) 527 caddr_t bufferp, 528 __in size_t buffer_size, 529 __out uint32_t *startp); 530 531 extern __checkReturn efx_rc_t 532 ef10_nvram_buffer_find_end( 533 __in_bcount(buffer_size) 534 caddr_t bufferp, 535 __in size_t buffer_size, 536 __in uint32_t offset, 537 __out uint32_t *endp); 538 539 extern __checkReturn __success(return != B_FALSE) boolean_t 540 ef10_nvram_buffer_find_item( 541 __in_bcount(buffer_size) 542 caddr_t bufferp, 543 __in size_t buffer_size, 544 __in uint32_t offset, 545 __out uint32_t *startp, 546 __out uint32_t *lengthp); 547 548 extern __checkReturn efx_rc_t 549 ef10_nvram_buffer_peek_item( 550 __in_bcount(buffer_size) 551 caddr_t bufferp, 552 __in size_t buffer_size, 553 __in uint32_t offset, 554 __out uint32_t *tagp, 555 __out uint32_t *lengthp, 556 __out uint32_t *value_offsetp); 557 558 extern __checkReturn efx_rc_t 559 ef10_nvram_buffer_get_item( 560 __in_bcount(buffer_size) 561 caddr_t bufferp, 562 __in size_t buffer_size, 563 __in uint32_t offset, 564 __in uint32_t length, 565 __out uint32_t *tagp, 566 __out_bcount_part(value_max_size, *lengthp) 567 caddr_t valuep, 568 __in size_t value_max_size, 569 __out uint32_t *lengthp); 570 571 extern __checkReturn efx_rc_t 572 ef10_nvram_buffer_insert_item( 573 __in_bcount(buffer_size) 574 caddr_t bufferp, 575 __in size_t buffer_size, 576 __in uint32_t offset, 577 __in uint32_t tag, 578 __in_bcount(length) caddr_t valuep, 579 __in uint32_t length, 580 __out uint32_t *lengthp); 581 582 extern __checkReturn efx_rc_t 583 ef10_nvram_buffer_modify_item( 584 __in_bcount(buffer_size) 585 caddr_t bufferp, 586 __in size_t buffer_size, 587 __in uint32_t offset, 588 __in uint32_t tag, 589 __in_bcount(length) caddr_t valuep, 590 __in uint32_t length, 591 __out uint32_t *lengthp); 592 593 extern __checkReturn efx_rc_t 594 ef10_nvram_buffer_delete_item( 595 __in_bcount(buffer_size) 596 caddr_t bufferp, 597 __in size_t buffer_size, 598 __in uint32_t offset, 599 __in uint32_t length, 600 __in uint32_t end); 601 602 extern __checkReturn efx_rc_t 603 ef10_nvram_buffer_finish( 604 __in_bcount(buffer_size) 605 caddr_t bufferp, 606 __in size_t buffer_size); 607 608 #endif /* EFSYS_OPT_NVRAM */ 609 610 /* PHY */ 611 612 typedef struct ef10_link_state_s { 613 efx_phy_link_state_t epls; 614 #if EFSYS_OPT_LOOPBACK 615 efx_loopback_type_t els_loopback; 616 #endif 617 boolean_t els_mac_up; 618 } ef10_link_state_t; 619 620 extern void 621 ef10_phy_link_ev( 622 __in efx_nic_t *enp, 623 __in efx_qword_t *eqp, 624 __out efx_link_mode_t *link_modep); 625 626 extern __checkReturn efx_rc_t 627 ef10_phy_get_link( 628 __in efx_nic_t *enp, 629 __out ef10_link_state_t *elsp); 630 631 extern __checkReturn efx_rc_t 632 ef10_phy_power( 633 __in efx_nic_t *enp, 634 __in boolean_t on); 635 636 extern __checkReturn efx_rc_t 637 ef10_phy_reconfigure( 638 __in efx_nic_t *enp); 639 640 extern __checkReturn efx_rc_t 641 ef10_phy_verify( 642 __in efx_nic_t *enp); 643 644 extern __checkReturn efx_rc_t 645 ef10_phy_oui_get( 646 __in efx_nic_t *enp, 647 __out uint32_t *ouip); 648 649 extern __checkReturn efx_rc_t 650 ef10_phy_link_state_get( 651 __in efx_nic_t *enp, 652 __out efx_phy_link_state_t *eplsp); 653 654 #if EFSYS_OPT_PHY_STATS 655 656 extern __checkReturn efx_rc_t 657 ef10_phy_stats_update( 658 __in efx_nic_t *enp, 659 __in efsys_mem_t *esmp, 660 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 661 662 #endif /* EFSYS_OPT_PHY_STATS */ 663 664 #if EFSYS_OPT_BIST 665 666 extern __checkReturn efx_rc_t 667 ef10_bist_enable_offline( 668 __in efx_nic_t *enp); 669 670 extern __checkReturn efx_rc_t 671 ef10_bist_start( 672 __in efx_nic_t *enp, 673 __in efx_bist_type_t type); 674 675 extern __checkReturn efx_rc_t 676 ef10_bist_poll( 677 __in efx_nic_t *enp, 678 __in efx_bist_type_t type, 679 __out efx_bist_result_t *resultp, 680 __out_opt __drv_when(count > 0, __notnull) 681 uint32_t *value_maskp, 682 __out_ecount_opt(count) __drv_when(count > 0, __notnull) 683 unsigned long *valuesp, 684 __in size_t count); 685 686 extern void 687 ef10_bist_stop( 688 __in efx_nic_t *enp, 689 __in efx_bist_type_t type); 690 691 #endif /* EFSYS_OPT_BIST */ 692 693 /* TX */ 694 695 extern __checkReturn efx_rc_t 696 ef10_tx_init( 697 __in efx_nic_t *enp); 698 699 extern void 700 ef10_tx_fini( 701 __in efx_nic_t *enp); 702 703 extern __checkReturn efx_rc_t 704 ef10_tx_qcreate( 705 __in efx_nic_t *enp, 706 __in unsigned int index, 707 __in unsigned int label, 708 __in efsys_mem_t *esmp, 709 __in size_t ndescs, 710 __in uint32_t id, 711 __in uint16_t flags, 712 __in efx_evq_t *eep, 713 __in efx_txq_t *etp, 714 __out unsigned int *addedp); 715 716 extern void 717 ef10_tx_qdestroy( 718 __in efx_txq_t *etp); 719 720 extern __checkReturn efx_rc_t 721 ef10_tx_qpost( 722 __in efx_txq_t *etp, 723 __in_ecount(ndescs) efx_buffer_t *ebp, 724 __in unsigned int ndescs, 725 __in unsigned int completed, 726 __inout unsigned int *addedp); 727 728 extern void 729 ef10_tx_qpush( 730 __in efx_txq_t *etp, 731 __in unsigned int added, 732 __in unsigned int pushed); 733 734 #if EFSYS_OPT_RX_PACKED_STREAM 735 extern void 736 ef10_rx_qpush_ps_credits( 737 __in efx_rxq_t *erp); 738 739 extern __checkReturn uint8_t * 740 ef10_rx_qps_packet_info( 741 __in efx_rxq_t *erp, 742 __in uint8_t *buffer, 743 __in uint32_t buffer_length, 744 __in uint32_t current_offset, 745 __out uint16_t *lengthp, 746 __out uint32_t *next_offsetp, 747 __out uint32_t *timestamp); 748 #endif 749 750 extern __checkReturn efx_rc_t 751 ef10_tx_qpace( 752 __in efx_txq_t *etp, 753 __in unsigned int ns); 754 755 extern __checkReturn efx_rc_t 756 ef10_tx_qflush( 757 __in efx_txq_t *etp); 758 759 extern void 760 ef10_tx_qenable( 761 __in efx_txq_t *etp); 762 763 extern __checkReturn efx_rc_t 764 ef10_tx_qpio_enable( 765 __in efx_txq_t *etp); 766 767 extern void 768 ef10_tx_qpio_disable( 769 __in efx_txq_t *etp); 770 771 extern __checkReturn efx_rc_t 772 ef10_tx_qpio_write( 773 __in efx_txq_t *etp, 774 __in_ecount(buf_length) uint8_t *buffer, 775 __in size_t buf_length, 776 __in size_t pio_buf_offset); 777 778 extern __checkReturn efx_rc_t 779 ef10_tx_qpio_post( 780 __in efx_txq_t *etp, 781 __in size_t pkt_length, 782 __in unsigned int completed, 783 __inout unsigned int *addedp); 784 785 extern __checkReturn efx_rc_t 786 ef10_tx_qdesc_post( 787 __in efx_txq_t *etp, 788 __in_ecount(n) efx_desc_t *ed, 789 __in unsigned int n, 790 __in unsigned int completed, 791 __inout unsigned int *addedp); 792 793 extern void 794 ef10_tx_qdesc_dma_create( 795 __in efx_txq_t *etp, 796 __in efsys_dma_addr_t addr, 797 __in size_t size, 798 __in boolean_t eop, 799 __out efx_desc_t *edp); 800 801 extern void 802 ef10_tx_qdesc_tso_create( 803 __in efx_txq_t *etp, 804 __in uint16_t ipv4_id, 805 __in uint32_t tcp_seq, 806 __in uint8_t tcp_flags, 807 __out efx_desc_t *edp); 808 809 extern void 810 ef10_tx_qdesc_tso2_create( 811 __in efx_txq_t *etp, 812 __in uint16_t ipv4_id, 813 __in uint16_t outer_ipv4_id, 814 __in uint32_t tcp_seq, 815 __in uint16_t tcp_mss, 816 __out_ecount(count) efx_desc_t *edp, 817 __in int count); 818 819 extern void 820 ef10_tx_qdesc_vlantci_create( 821 __in efx_txq_t *etp, 822 __in uint16_t vlan_tci, 823 __out efx_desc_t *edp); 824 825 extern void 826 ef10_tx_qdesc_checksum_create( 827 __in efx_txq_t *etp, 828 __in uint16_t flags, 829 __out efx_desc_t *edp); 830 831 #if EFSYS_OPT_QSTATS 832 833 extern void 834 ef10_tx_qstats_update( 835 __in efx_txq_t *etp, 836 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 837 838 #endif /* EFSYS_OPT_QSTATS */ 839 840 typedef uint32_t efx_piobuf_handle_t; 841 842 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1) 843 844 extern __checkReturn efx_rc_t 845 ef10_nic_pio_alloc( 846 __inout efx_nic_t *enp, 847 __out uint32_t *bufnump, 848 __out efx_piobuf_handle_t *handlep, 849 __out uint32_t *blknump, 850 __out uint32_t *offsetp, 851 __out size_t *sizep); 852 853 extern __checkReturn efx_rc_t 854 ef10_nic_pio_free( 855 __inout efx_nic_t *enp, 856 __in uint32_t bufnum, 857 __in uint32_t blknum); 858 859 extern __checkReturn efx_rc_t 860 ef10_nic_pio_link( 861 __inout efx_nic_t *enp, 862 __in uint32_t vi_index, 863 __in efx_piobuf_handle_t handle); 864 865 extern __checkReturn efx_rc_t 866 ef10_nic_pio_unlink( 867 __inout efx_nic_t *enp, 868 __in uint32_t vi_index); 869 870 /* VPD */ 871 872 #if EFSYS_OPT_VPD 873 874 extern __checkReturn efx_rc_t 875 ef10_vpd_init( 876 __in efx_nic_t *enp); 877 878 extern __checkReturn efx_rc_t 879 ef10_vpd_size( 880 __in efx_nic_t *enp, 881 __out size_t *sizep); 882 883 extern __checkReturn efx_rc_t 884 ef10_vpd_read( 885 __in efx_nic_t *enp, 886 __out_bcount(size) caddr_t data, 887 __in size_t size); 888 889 extern __checkReturn efx_rc_t 890 ef10_vpd_verify( 891 __in efx_nic_t *enp, 892 __in_bcount(size) caddr_t data, 893 __in size_t size); 894 895 extern __checkReturn efx_rc_t 896 ef10_vpd_reinit( 897 __in efx_nic_t *enp, 898 __in_bcount(size) caddr_t data, 899 __in size_t size); 900 901 extern __checkReturn efx_rc_t 902 ef10_vpd_get( 903 __in efx_nic_t *enp, 904 __in_bcount(size) caddr_t data, 905 __in size_t size, 906 __inout efx_vpd_value_t *evvp); 907 908 extern __checkReturn efx_rc_t 909 ef10_vpd_set( 910 __in efx_nic_t *enp, 911 __in_bcount(size) caddr_t data, 912 __in size_t size, 913 __in efx_vpd_value_t *evvp); 914 915 extern __checkReturn efx_rc_t 916 ef10_vpd_next( 917 __in efx_nic_t *enp, 918 __in_bcount(size) caddr_t data, 919 __in size_t size, 920 __out efx_vpd_value_t *evvp, 921 __inout unsigned int *contp); 922 923 extern __checkReturn efx_rc_t 924 ef10_vpd_write( 925 __in efx_nic_t *enp, 926 __in_bcount(size) caddr_t data, 927 __in size_t size); 928 929 extern void 930 ef10_vpd_fini( 931 __in efx_nic_t *enp); 932 933 #endif /* EFSYS_OPT_VPD */ 934 935 /* RX */ 936 937 extern __checkReturn efx_rc_t 938 ef10_rx_init( 939 __in efx_nic_t *enp); 940 941 #if EFSYS_OPT_RX_SCATTER 942 extern __checkReturn efx_rc_t 943 ef10_rx_scatter_enable( 944 __in efx_nic_t *enp, 945 __in unsigned int buf_size); 946 #endif /* EFSYS_OPT_RX_SCATTER */ 947 948 #if EFSYS_OPT_RX_SCALE 949 950 extern __checkReturn efx_rc_t 951 ef10_rx_scale_context_alloc( 952 __in efx_nic_t *enp, 953 __in efx_rx_scale_context_type_t type, 954 __in uint32_t num_queues, 955 __out uint32_t *rss_contextp); 956 957 extern __checkReturn efx_rc_t 958 ef10_rx_scale_context_free( 959 __in efx_nic_t *enp, 960 __in uint32_t rss_context); 961 962 extern __checkReturn efx_rc_t 963 ef10_rx_scale_mode_set( 964 __in efx_nic_t *enp, 965 __in uint32_t rss_context, 966 __in efx_rx_hash_alg_t alg, 967 __in efx_rx_hash_type_t type, 968 __in boolean_t insert); 969 970 extern __checkReturn efx_rc_t 971 ef10_rx_scale_key_set( 972 __in efx_nic_t *enp, 973 __in uint32_t rss_context, 974 __in_ecount(n) uint8_t *key, 975 __in size_t n); 976 977 extern __checkReturn efx_rc_t 978 ef10_rx_scale_tbl_set( 979 __in efx_nic_t *enp, 980 __in uint32_t rss_context, 981 __in_ecount(n) unsigned int *table, 982 __in size_t n); 983 984 extern __checkReturn uint32_t 985 ef10_rx_prefix_hash( 986 __in efx_nic_t *enp, 987 __in efx_rx_hash_alg_t func, 988 __in uint8_t *buffer); 989 990 #endif /* EFSYS_OPT_RX_SCALE */ 991 992 extern __checkReturn efx_rc_t 993 ef10_rx_prefix_pktlen( 994 __in efx_nic_t *enp, 995 __in uint8_t *buffer, 996 __out uint16_t *lengthp); 997 998 extern void 999 ef10_rx_qpost( 1000 __in efx_rxq_t *erp, 1001 __in_ecount(ndescs) efsys_dma_addr_t *addrp, 1002 __in size_t size, 1003 __in unsigned int ndescs, 1004 __in unsigned int completed, 1005 __in unsigned int added); 1006 1007 extern void 1008 ef10_rx_qpush( 1009 __in efx_rxq_t *erp, 1010 __in unsigned int added, 1011 __inout unsigned int *pushedp); 1012 1013 extern __checkReturn efx_rc_t 1014 ef10_rx_qflush( 1015 __in efx_rxq_t *erp); 1016 1017 extern void 1018 ef10_rx_qenable( 1019 __in efx_rxq_t *erp); 1020 1021 union efx_rxq_type_data_u; 1022 1023 extern __checkReturn efx_rc_t 1024 ef10_rx_qcreate( 1025 __in efx_nic_t *enp, 1026 __in unsigned int index, 1027 __in unsigned int label, 1028 __in efx_rxq_type_t type, 1029 __in_opt const union efx_rxq_type_data_u *type_data, 1030 __in efsys_mem_t *esmp, 1031 __in size_t ndescs, 1032 __in uint32_t id, 1033 __in unsigned int flags, 1034 __in efx_evq_t *eep, 1035 __in efx_rxq_t *erp); 1036 1037 extern void 1038 ef10_rx_qdestroy( 1039 __in efx_rxq_t *erp); 1040 1041 extern void 1042 ef10_rx_fini( 1043 __in efx_nic_t *enp); 1044 1045 #if EFSYS_OPT_FILTER 1046 1047 typedef struct ef10_filter_handle_s { 1048 uint32_t efh_lo; 1049 uint32_t efh_hi; 1050 } ef10_filter_handle_t; 1051 1052 typedef struct ef10_filter_entry_s { 1053 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */ 1054 ef10_filter_handle_t efe_handle; 1055 } ef10_filter_entry_t; 1056 1057 /* 1058 * BUSY flag indicates that an update is in progress. 1059 * AUTO_OLD flag is used to mark and sweep MAC packet filters. 1060 */ 1061 #define EFX_EF10_FILTER_FLAG_BUSY 1U 1062 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U 1063 #define EFX_EF10_FILTER_FLAGS 3U 1064 1065 /* 1066 * Size of the hash table used by the driver. Doesn't need to be the 1067 * same size as the hardware's table. 1068 */ 1069 #define EFX_EF10_FILTER_TBL_ROWS 8192 1070 1071 /* Only need to allow for one directed and one unknown unicast filter */ 1072 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2 1073 1074 /* Allow for the broadcast address to be added to the multicast list */ 1075 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1) 1076 1077 /* 1078 * For encapsulated packets, there is one filter each for each combination of 1079 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or 1080 * multicast inner frames. 1081 */ 1082 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12 1083 1084 typedef struct ef10_filter_table_s { 1085 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS]; 1086 efx_rxq_t *eft_default_rxq; 1087 boolean_t eft_using_rss; 1088 uint32_t eft_unicst_filter_indexes[ 1089 EFX_EF10_FILTER_UNICAST_FILTERS_MAX]; 1090 uint32_t eft_unicst_filter_count; 1091 uint32_t eft_mulcst_filter_indexes[ 1092 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX]; 1093 uint32_t eft_mulcst_filter_count; 1094 boolean_t eft_using_all_mulcst; 1095 uint32_t eft_encap_filter_indexes[ 1096 EFX_EF10_FILTER_ENCAP_FILTERS_MAX]; 1097 uint32_t eft_encap_filter_count; 1098 } ef10_filter_table_t; 1099 1100 __checkReturn efx_rc_t 1101 ef10_filter_init( 1102 __in efx_nic_t *enp); 1103 1104 void 1105 ef10_filter_fini( 1106 __in efx_nic_t *enp); 1107 1108 __checkReturn efx_rc_t 1109 ef10_filter_restore( 1110 __in efx_nic_t *enp); 1111 1112 __checkReturn efx_rc_t 1113 ef10_filter_add( 1114 __in efx_nic_t *enp, 1115 __inout efx_filter_spec_t *spec, 1116 __in boolean_t may_replace); 1117 1118 __checkReturn efx_rc_t 1119 ef10_filter_delete( 1120 __in efx_nic_t *enp, 1121 __inout efx_filter_spec_t *spec); 1122 1123 extern __checkReturn efx_rc_t 1124 ef10_filter_supported_filters( 1125 __in efx_nic_t *enp, 1126 __out_ecount(buffer_length) uint32_t *buffer, 1127 __in size_t buffer_length, 1128 __out size_t *list_lengthp); 1129 1130 extern __checkReturn efx_rc_t 1131 ef10_filter_reconfigure( 1132 __in efx_nic_t *enp, 1133 __in_ecount(6) uint8_t const *mac_addr, 1134 __in boolean_t all_unicst, 1135 __in boolean_t mulcst, 1136 __in boolean_t all_mulcst, 1137 __in boolean_t brdcst, 1138 __in_ecount(6*count) uint8_t const *addrs, 1139 __in uint32_t count); 1140 1141 extern void 1142 ef10_filter_get_default_rxq( 1143 __in efx_nic_t *enp, 1144 __out efx_rxq_t **erpp, 1145 __out boolean_t *using_rss); 1146 1147 extern void 1148 ef10_filter_default_rxq_set( 1149 __in efx_nic_t *enp, 1150 __in efx_rxq_t *erp, 1151 __in boolean_t using_rss); 1152 1153 extern void 1154 ef10_filter_default_rxq_clear( 1155 __in efx_nic_t *enp); 1156 1157 #endif /* EFSYS_OPT_FILTER */ 1158 1159 extern __checkReturn efx_rc_t 1160 efx_mcdi_get_function_info( 1161 __in efx_nic_t *enp, 1162 __out uint32_t *pfp, 1163 __out_opt uint32_t *vfp); 1164 1165 extern __checkReturn efx_rc_t 1166 efx_mcdi_privilege_mask( 1167 __in efx_nic_t *enp, 1168 __in uint32_t pf, 1169 __in uint32_t vf, 1170 __out uint32_t *maskp); 1171 1172 extern __checkReturn efx_rc_t 1173 efx_mcdi_get_port_assignment( 1174 __in efx_nic_t *enp, 1175 __out uint32_t *portp); 1176 1177 extern __checkReturn efx_rc_t 1178 efx_mcdi_get_port_modes( 1179 __in efx_nic_t *enp, 1180 __out uint32_t *modesp, 1181 __out_opt uint32_t *current_modep, 1182 __out_opt uint32_t *default_modep); 1183 1184 extern __checkReturn efx_rc_t 1185 ef10_nic_get_port_mode_bandwidth( 1186 __in efx_nic_t *enp, 1187 __out uint32_t *bandwidth_mbpsp); 1188 1189 extern __checkReturn efx_rc_t 1190 efx_mcdi_get_mac_address_pf( 1191 __in efx_nic_t *enp, 1192 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1193 1194 extern __checkReturn efx_rc_t 1195 efx_mcdi_get_mac_address_vf( 1196 __in efx_nic_t *enp, 1197 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1198 1199 extern __checkReturn efx_rc_t 1200 efx_mcdi_get_clock( 1201 __in efx_nic_t *enp, 1202 __out uint32_t *sys_freqp, 1203 __out uint32_t *dpcpu_freqp); 1204 1205 extern __checkReturn efx_rc_t 1206 efx_mcdi_get_rxdp_config( 1207 __in efx_nic_t *enp, 1208 __out uint32_t *end_paddingp); 1209 1210 extern __checkReturn efx_rc_t 1211 efx_mcdi_get_vector_cfg( 1212 __in efx_nic_t *enp, 1213 __out_opt uint32_t *vec_basep, 1214 __out_opt uint32_t *pf_nvecp, 1215 __out_opt uint32_t *vf_nvecp); 1216 1217 extern __checkReturn efx_rc_t 1218 ef10_get_privilege_mask( 1219 __in efx_nic_t *enp, 1220 __out uint32_t *maskp); 1221 1222 #if EFSYS_OPT_FW_SUBVARIANT_AWARE 1223 1224 extern __checkReturn efx_rc_t 1225 efx_mcdi_get_nic_global( 1226 __in efx_nic_t *enp, 1227 __in uint32_t key, 1228 __out uint32_t *valuep); 1229 1230 extern __checkReturn efx_rc_t 1231 efx_mcdi_set_nic_global( 1232 __in efx_nic_t *enp, 1233 __in uint32_t key, 1234 __in uint32_t value); 1235 1236 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ 1237 1238 #if EFSYS_OPT_RX_PACKED_STREAM 1239 1240 /* Data space per credit in packed stream mode */ 1241 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16) 1242 1243 /* 1244 * Received packets are always aligned at this boundary. Also there always 1245 * exists a gap of this size between packets. 1246 * (see SF-112241-TC, 4.5) 1247 */ 1248 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64 1249 1250 /* 1251 * Size of a pseudo-header prepended to received packets 1252 * in packed stream mode 1253 */ 1254 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8 1255 1256 /* Minimum space for packet in packed stream mode */ 1257 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \ 1258 EFX_P2ROUNDUP(size_t, \ 1259 EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \ 1260 EFX_MAC_PDU_MIN + \ 1261 EFX_RX_PACKED_STREAM_ALIGNMENT, \ 1262 EFX_RX_PACKED_STREAM_ALIGNMENT) 1263 1264 /* Maximum number of credits */ 1265 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127 1266 1267 #endif /* EFSYS_OPT_RX_PACKED_STREAM */ 1268 1269 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 1270 1271 /* 1272 * Maximum DMA length and buffer stride alignment. 1273 * (see SF-119419-TC, 3.2) 1274 */ 1275 #define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64 1276 1277 #endif 1278 1279 #ifdef __cplusplus 1280 } 1281 #endif 1282 1283 #endif /* _SYS_EF10_IMPL_H */ 1284