xref: /illumos-gate/usr/src/uts/common/sys/1394/adapters/hci1394_csr.h (revision 2d6eb4a5e0a47d30189497241345dc5466bb68ab)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright (c) 1999-2000 by Sun Microsystems, Inc.
24  * All rights reserved.
25  */
26 
27 #ifndef _SYS_1394_ADAPTERS_HCI1394_CSR_H
28 #define	_SYS_1394_ADAPTERS_HCI1394_CSR_H
29 
30 /*
31  * hci1394_csr.h
32  *    This file contains the code for the CSR registers handled by the HAL in
33  *    SW.  The HW implemented CSR registers are in hci1394_ohci.c
34  *
35  *   For more information on CSR registers, see
36  *	IEEE 1212
37  *	IEEE 1394-1995
38  *		section 8.3.2
39  *	IEEE P1394A Draft 3.0
40  *		sections 10.32,10.33
41  *
42  * NOTE: A read/write to a CSR SW based register will first go to the Services
43  *    Layer which will do some filtering and then come through the s1394if.
44  */
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49 
50 #include <sys/ddi.h>
51 #include <sys/modctl.h>
52 #include <sys/sunddi.h>
53 
54 #include <sys/1394/adapters/hci1394_def.h>
55 
56 
57 /*
58  * The 1394 bus sends out cycle start packets periodically.  The time in
59  * between these packets is commonly referred to as a bus cycle.  The 1394
60  * cycle start packets come every 125uS. split_timeout is represented in 1394
61  * bus cycles (e.g. to have ATREQ ACK_PENDED timeout after 100mS, you would set
62  * split_timeout to 800).
63  *
64  * The CSR register interface has the split timeout broken into two registers,
65  * split_timeout_hi and split_timeout_lo.  The least significant 3 bits of
66  * split_timeout_hi contain the # of seconds and the most significant 13 bits
67  * of split_timeout_lo contain the fraction of a seconds in 125uS increments.
68  * There is a further constraint that the value in split_timeout_lo must be >=
69  * 800 && <= 7999 (>=100mS && < 1S). (don't forget that this value is in the
70  * most significant 13 bits, i.e. 800 << 19)  We will threshold the writes into
71  * these registers to make sure they always have legal values (i.e. if
72  * [8000 << 19] is written to split_timeout_lo, we will write [7999 << 19].
73  *
74  * The split timeout CSR registers have some inherent problems. There is a race
75  * condition when updating the split timeout value since you cannot atomically
76  * write to both the hi and lo registers.  This should not be a serious problem
77  * since we should never get close to having a split timeout of 1S or greater.
78  */
79 
80 
81 /* CSR Register Address Offsets (1394-1995 8.3.2.2) */
82 #define	CSR_STATE_CLEAR			0x000
83 #define	CSR_STATE_SET			0x004
84 #define	CSR_NODE_IDS			0x008
85 #define	CSR_RESET_START			0x00C
86 #define	CSR_SPLIT_TIMEOUT_HI		0x018
87 #define	CSR_SPLIT_TIMEOUT_LO		0x01C
88 #define	CSR_CYCLE_TIME			0x200
89 #define	CSR_BUS_TIME			0x204
90 #define	CSR_BUSY_TIMEOUT		0x210
91 #define	CSR_BUS_MANAGER_ID		0x21C
92 #define	CSR_BANDWIDTH_AVAILABLE		0x220
93 #define	CSR_CHANNELS_AVAILABLE_HI	0x224
94 #define	CSR_CHANNELS_AVAILABLE_LO	0x228
95 
96 
97 typedef struct hci1394_csr_s {
98 	/* SW registers */
99 	uint32_t csr_state;
100 	uint32_t csr_split_timeout_lo;
101 	uint32_t csr_split_timeout_hi;
102 
103 	/* split timeout that we are observing */
104 	uint_t csr_split_timeout;
105 
106 	/* were we root last bus reset */
107 	boolean_t csr_was_root;
108 
109 	/* our node capabilities */
110 	uint32_t csr_capabilities;
111 
112 	/* copies of OpenHCI handle and pointer to general driver info */
113 	hci1394_ohci_handle_t csr_ohci;
114 	hci1394_drvinfo_t *csr_drvinfo;
115 
116 	kmutex_t csr_mutex;
117 } hci1394_csr_t;
118 
119 /* handle passed back from init() and used for rest of functions */
120 typedef	struct hci1394_csr_s	*hci1394_csr_handle_t;
121 
122 
123 void hci1394_csr_init(hci1394_drvinfo_t *drvinfo, hci1394_ohci_handle_t ohci,
124     hci1394_csr_handle_t *csr_handle);
125 void hci1394_csr_fini(hci1394_csr_handle_t *csr_handle);
126 void hci1394_csr_resume(hci1394_csr_handle_t csr_handle);
127 
128 void hci1394_csr_node_capabilities(hci1394_csr_handle_t csr_handle,
129     uint32_t *capabilities);
130 
131 void hci1394_csr_state_get(hci1394_csr_handle_t csr_handle, uint32_t *state);
132 void hci1394_csr_state_bset(hci1394_csr_handle_t csr_handle, uint32_t state);
133 void hci1394_csr_state_bclr(hci1394_csr_handle_t csr_handle, uint32_t state);
134 
135 void hci1394_csr_split_timeout_hi_get(hci1394_csr_handle_t csr_handle,
136     uint32_t *split_timeout_hi);
137 void hci1394_csr_split_timeout_lo_get(hci1394_csr_handle_t csr_handle,
138     uint32_t *split_timeout_lo);
139 void hci1394_csr_split_timeout_hi_set(hci1394_csr_handle_t csr_handle,
140     uint32_t split_timeout_hi);
141 void hci1394_csr_split_timeout_lo_set(hci1394_csr_handle_t csr_handle,
142     uint32_t split_timeout_lo);
143 uint_t hci1394_csr_split_timeout_get(hci1394_csr_handle_t csr_handle);
144 
145 void hci1394_csr_bus_reset(hci1394_csr_handle_t csr_handle);
146 
147 
148 #ifdef __cplusplus
149 }
150 #endif
151 
152 #endif	/* _SYS_1394_ADAPTERS_HCI1394_CSR_H */
153