1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2024 Oxide Computer Company 14 */ 15 16 #ifndef _SPD_COMMON_H 17 #define _SPD_COMMON_H 18 19 /* 20 * This contains common definitions that are shared across all SPD revisions. 21 * This header will also pull in the various version specific pieces of 22 * information. 23 */ 24 25 #include <sys/bitext.h> 26 #include <libjedec.h> 27 28 #include "spd_ddr3.h" 29 #include "spd_ddr4.h" 30 #include "spd_ddr5.h" 31 #include "spd_lp4.h" 32 #include "spd_lp5.h" 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /* 39 * This enumeration covers the DRAM Device Type key byte and is consistent 40 * across all SPD revisions. This must be used first when identifying devices. 41 */ 42 43 /* 44 * This is the common byte that is used across all the different SPD types to 45 * determine the type of DRAM present. Its values are covered in the 46 * 'spd_dram_type_t' enumeration found in libjedec.h. 47 */ 48 #define SPD_DRAM_TYPE 0x002 49 50 /* 51 * Common definitions for taking apart a JEDEC manufacturer ID. The first byte 52 * is always a continuation code with a parity while the second byte is the 53 * specific entry for that continuation code. The continuation code and the id 54 * within a group tie into the common libjedec vendor decoding table. 55 */ 56 #define SPD_MFG_ID0_PAR(r) bitx8(r, 7, 7) 57 #define SPD_MFG_ID0_CONT(r) bitx8(r, 6, 0) 58 59 /* 60 * DDR4 and DDR5 have a DRAM stepping revision. This is the sentinel that 61 * indicates that there is no value. 62 */ 63 #define SPD_DRAM_STEP_NOINFO 0xff 64 65 #ifdef __cplusplus 66 } 67 #endif 68 69 #endif /* _SPD_COMMON_H */ 70