xref: /titanic_41/usr/src/uts/common/io/ixgbe/ixgbe_phy.h (revision 69b5a878d62fdee1b12e78371ce6cc8abddcad15)
1 /******************************************************************************
2 
3   Copyright (c) 2001-2012, Intel Corporation
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32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #ifndef _IXGBE_PHY_H_
36 #define _IXGBE_PHY_H_
37 
38 #include "ixgbe_type.h"
39 #define IXGBE_I2C_EEPROM_DEV_ADDR    0xA0
40 
41 /* EEPROM byte offsets */
42 #define IXGBE_SFF_IDENTIFIER		0x0
43 #define IXGBE_SFF_IDENTIFIER_SFP	0x3
44 #define IXGBE_SFF_VENDOR_OUI_BYTE0	0x25
45 #define IXGBE_SFF_VENDOR_OUI_BYTE1	0x26
46 #define IXGBE_SFF_VENDOR_OUI_BYTE2	0x27
47 #define IXGBE_SFF_1GBE_COMP_CODES	0x6
48 #define IXGBE_SFF_10GBE_COMP_CODES	0x3
49 #define IXGBE_SFF_CABLE_TECHNOLOGY	0x8
50 #define IXGBE_SFF_CABLE_SPEC_COMP	0x3C
51 
52 /* Bitmasks */
53 #define IXGBE_SFF_DA_PASSIVE_CABLE	0x4
54 #define IXGBE_SFF_DA_ACTIVE_CABLE	0x8
55 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING	0x4
56 #define IXGBE_SFF_1GBASESX_CAPABLE	0x1
57 #define IXGBE_SFF_1GBASELX_CAPABLE	0x2
58 #define IXGBE_SFF_1GBASET_CAPABLE	0x8
59 #define IXGBE_SFF_10GBASESR_CAPABLE	0x10
60 #define IXGBE_SFF_10GBASELR_CAPABLE	0x20
61 #define IXGBE_I2C_EEPROM_READ_MASK	0x100
62 #define IXGBE_I2C_EEPROM_STATUS_MASK	0x3
63 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION	0x0
64 #define IXGBE_I2C_EEPROM_STATUS_PASS	0x1
65 #define IXGBE_I2C_EEPROM_STATUS_FAIL	0x2
66 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS	0x3
67 
68 /* Flow control defines */
69 #define IXGBE_TAF_SYM_PAUSE		0x400
70 #define IXGBE_TAF_ASM_PAUSE		0x800
71 
72 /* Bit-shift macros */
73 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT	24
74 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT	16
75 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT	8
76 
77 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
78 #define IXGBE_SFF_VENDOR_OUI_TYCO	0x00407600
79 #define IXGBE_SFF_VENDOR_OUI_FTL	0x00906500
80 #define IXGBE_SFF_VENDOR_OUI_AVAGO	0x00176A00
81 #define IXGBE_SFF_VENDOR_OUI_INTEL	0x001B2100
82 
83 /* I2C SDA and SCL timing parameters for standard mode */
84 #define IXGBE_I2C_T_HD_STA	4
85 #define IXGBE_I2C_T_LOW		5
86 #define IXGBE_I2C_T_HIGH	4
87 #define IXGBE_I2C_T_SU_STA	5
88 #define IXGBE_I2C_T_HD_DATA	5
89 #define IXGBE_I2C_T_SU_DATA	1
90 #define IXGBE_I2C_T_RISE	1
91 #define IXGBE_I2C_T_FALL	1
92 #define IXGBE_I2C_T_SU_STO	4
93 #define IXGBE_I2C_T_BUF		5
94 
95 #define IXGBE_TN_LASI_STATUS_REG	0x9005
96 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM	0x0008
97 
98 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
99 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
100 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
101 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
102 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
103 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
104 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
105 			       u32 device_type, u16 *phy_data);
106 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
107 				u32 device_type, u16 phy_data);
108 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
109 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
110 				       ixgbe_link_speed speed,
111 				       bool autoneg,
112 				       bool autoneg_wait_to_complete);
113 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
114 					       ixgbe_link_speed *speed,
115 					       bool *autoneg);
116 
117 /* PHY specific */
118 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
119 			     ixgbe_link_speed *speed,
120 			     bool *link_up);
121 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
122 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
123 				       u16 *firmware_version);
124 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
125 					   u16 *firmware_version);
126 
127 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
128 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
129 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
130 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
131 					u16 *list_offset,
132 					u16 *data_offset);
133 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
134 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
135 				u8 dev_addr, u8 *data);
136 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
137 				 u8 dev_addr, u8 data);
138 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
139 				  u8 *eeprom_data);
140 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
141 				   u8 eeprom_data);
142 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
143 #endif /* _IXGBE_PHY_H_ */
144