xref: /illumos-gate/usr/src/uts/common/io/usbgem/usbgem_mii.h (revision 6716431ba7de213d5c318e58dc24c8a36da9b068)
1 /*
2  *  gem_mii.h: mii header for gem
3  *
4  * Copyright (c) 2002-2007 Masayuki Murayama.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright notice,
10  *    this list of conditions and the following disclaimer.
11  *
12  * 2. Redistributions in binary form must reproduce the above copyright notice,
13  *    this list of conditions and the following disclaimer in the documentation
14  *    and/or other materials provided with the distribution.
15  *
16  * 3. Neither the name of the author nor the names of its contributors may be
17  *    used to endorse or promote products derived from this software without
18  *    specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24  * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
26  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
27  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
28  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
29  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
30  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31  * DAMAGE.
32  */
33 
34 /*
35  * gem_mii.h : MII registers
36  */
37 #ifndef _GEM_MII_H_
38 #define	_GEM_MII_H_
39 
40 #ifdef GEM_CONFIG_GLDv3
41 #include <sys/miiregs.h>
42 #else
43 #define	MII_CONTROL 		0
44 #define	MII_STATUS 		1
45 #define	MII_PHYIDH		2
46 #define	MII_PHYIDL		3
47 #define	MII_AN_ADVERT		4
48 #define	MII_AN_LPABLE		5
49 #define	MII_AN_EXPANSION	6
50 #define	MII_AN_NXTPGXMIT	7
51 #endif /* GEM_CONFIG_GLDv3 */
52 
53 #define	MII_AN_LPANXT		8
54 #define	MII_MS_CONTROL		9
55 #define	MII_MS_STATUS		10
56 #define	MII_XSTATUS		15
57 
58 /* for 1000BaseT support */
59 #define	MII_1000TC		MII_MS_CONTROL
60 #define	MII_1000TS		MII_MS_STATUS
61 #ifndef GEM_CONFIG_GLDv3
62 #define	MII_CONTROL_RESET	0x8000
63 #define	MII_CONTROL_LOOPBACK	0x4000
64 #define	MII_CONTROL_100MB	0x2000
65 #define	MII_CONTROL_ANE		0x1000
66 #define	MII_CONTROL_PWRDN	0x0800
67 #define	MII_CONTROL_ISOLATE	0x0400
68 #define	MII_CONTROL_RSAN	0x0200
69 #define	MII_CONTROL_FDUPLEX	0x0100
70 #define	MII_CONTROL_COLTST	0x0080
71 #endif /* !GEM_CONFIG_GLDv3 */
72 #define	MII_CONTROL_SPEED	0x2040
73 
74 #define	MII_CONTROL_10MB	0x0000
75 #define	MII_CONTROL_1000MB	0x0040
76 
77 #define	MII_CONTROL_BITS	\
78 	"\020"	\
79 	"\020RESET"	\
80 	"\017LOOPBACK"	\
81 	"\016100MB"	\
82 	"\015ANE"	\
83 	"\014PWRDN"	\
84 	"\013ISOLATE"	\
85 	"\012RSAN"	\
86 	"\011FDUPLEX"	\
87 	"\010COLTST"	\
88 	"\0071000M"
89 #ifndef GEM_CONFIG_GLDv3
90 #define	MII_STATUS_100_BASE_T4		0x8000
91 #define	MII_STATUS_100_BASEX_FD		0x4000
92 #define	MII_STATUS_100_BASEX		0x2000
93 #define	MII_STATUS_10_FD		0x1000
94 #define	MII_STATUS_10			0x0800
95 #define	MII_STATUS_MFPRMBLSUPR		0x0040
96 #define	MII_STATUS_ANDONE		0x0020
97 #define	MII_STATUS_REMFAULT		0x0010
98 #define	MII_STATUS_CANAUTONEG		0x0008
99 #define	MII_STATUS_LINKUP		0x0004
100 #define	MII_STATUS_JABBERING		0x0002
101 #define	MII_STATUS_EXTENDED		0x0001
102 #endif /* !GEM_CONFIG_GLDv3 */
103 #define	MII_STATUS_XSTATUS		0x0100
104 #define	MII_STATUS_100_BASE_T2_FD	0x0400
105 #define	MII_STATUS_100_BASE_T2		0x0200
106 
107 #define	MII_STATUS_ABILITY_TECH	\
108 	(MII_STATUS_100_BASE_T4	|	\
109 	MII_STATUS_100_BASEX_FD |	\
110 	MII_STATUS_100_BASEX |	\
111 	MII_STATUS_10 |	\
112 	MII_STATUS_10_FD)
113 
114 
115 #define	MII_STATUS_BITS	\
116 	"\020"	\
117 	"\020100_BASE_T4"	\
118 	"\017100_BASEX_FD"	\
119 	"\016100_BASEX"	\
120 	"\01510_BASE_FD"	\
121 	"\01410_BASE"	\
122 	"\013100_BASE_T2_FD"	\
123 	"\012100_BASE_T2"	\
124 	"\011XSTATUS"	\
125 	"\007MFPRMBLSUPR"	\
126 	"\006ANDONE"	\
127 	"\005REMFAULT"	\
128 	"\004CANAUTONEG"	\
129 	"\003LINKUP"	\
130 	"\002JABBERING"	\
131 	"\001EXTENDED"
132 #ifndef GEM_CONFIG_GLDv3
133 #define	MII_AN_ADVERT_NP		0x8000
134 #define	MII_AN_ADVERT_REMFAULT		0x2000
135 #define	MII_AN_ADVERT_SELECTOR		0x001f
136 #endif /* !GEM_CONFIG_GLDv3 */
137 
138 #define	MII_ABILITY_ASM_DIR		0x0800	/* for annex 28B */
139 #ifndef	MII_ABILITY_PAUSE
140 #define	MII_ABILITY_PAUSE		0x0400	/* for IEEE 802.3x */
141 #endif
142 #ifndef GEM_CONFIG_GLDv3
143 #define	MII_ABILITY_100BASE_T4		0x0200
144 #define	MII_ABILITY_100BASE_TX_FD	0x0100
145 #define	MII_ABILITY_100BASE_TX		0x0080
146 #define	MII_ABILITY_10BASE_T_FD		0x0040
147 #define	MII_ABILITY_10BASE_T		0x0020
148 #endif /* !GEM_CONFIG_GLDv3 */
149 
150 #define	MII_AN_LPABLE_NP	0x8000
151 
152 #define	MII_ABILITY_TECH	\
153 	(MII_ABILITY_100BASE_T4	|	\
154 	MII_ABILITY_100BASE_TX_FD |	\
155 	MII_ABILITY_100BASE_TX |	\
156 	MII_ABILITY_10BASE_T |	\
157 	MII_ABILITY_10BASE_T_FD)
158 
159 #define	MII_ABILITY_ALL	\
160 	(MII_AN_ADVERT_REMFAULT |	\
161 	MII_ABILITY_ASM_DIR |	\
162 	MII_ABILITY_PAUSE |	\
163 	MII_ABILITY_TECH)
164 
165 
166 #define	MII_ABILITY_BITS	\
167 	"\020"	\
168 	"\016REMFAULT"	\
169 	"\014ASM_DIR"	\
170 	"\013PAUSE"	\
171 	"\012100BASE_T4"	\
172 	"\011100BASE_TX_FD"	\
173 	"\010100BASE_TX"	\
174 	"\00710BASE_T_FD"	\
175 	"\00610BASE_T"
176 #ifndef GEM_CONFIG_GLDv3
177 #define	MII_AN_EXP_PARFAULT	0x0010
178 #define	MII_AN_EXP_LPCANNXTP	0x0008
179 #define	MII_AN_EXP_CANNXTPP	0x0004
180 #define	MII_AN_EXP_PAGERCVD 	0x0002
181 #define	MII_AN_EXP_LPCANAN 	0x0001
182 #endif /* !GEM_CONFIG_GLDv3 */
183 
184 #define	MII_AN_EXP_BITS	\
185 	"\020"	\
186 	"\005PARFAULT"	\
187 	"\004LPCANNXTP"	\
188 	"\003CANNXTPP"	\
189 	"\002PAGERCVD"	\
190 	"\001LPCANAN"
191 
192 #define	MII_1000TC_TESTMODE	0xe000
193 #define	MII_1000TC_CFG_EN	0x1000
194 #define	MII_1000TC_CFG_VAL	0x0800
195 #define	MII_1000TC_PORTTYPE	0x0400
196 #define	MII_1000TC_ADV_FULL	0x0200
197 #define	MII_1000TC_ADV_HALF	0x0100
198 
199 #define	MII_1000TC_BITS	\
200 	"\020"	\
201 	"\015CFG_EN"	\
202 	"\014CFG_VAL"	\
203 	"\013PORTTYPE"	\
204 	"\012FULL"	\
205 	"\011HALF"
206 
207 #define	MII_1000TS_CFG_FAULT	0x8000
208 #define	MII_1000TS_CFG_MASTER	0x4000
209 #define	MII_1000TS_LOCALRXOK	0x2000
210 #define	MII_1000TS_REMOTERXOK	0x1000
211 #define	MII_1000TS_LP_FULL	0x0800
212 #define	MII_1000TS_LP_HALF	0x0400
213 
214 #define	MII_1000TS_BITS	\
215 	"\020"	\
216 	"\020CFG_FAULT"	\
217 	"\017CFG_MASTER"	\
218 	"\014CFG_LOCALRXOK"	\
219 	"\013CFG_REMOTERXOK"	\
220 	"\012LP_FULL"	\
221 	"\011LP_HALF"
222 
223 #define	MII_XSTATUS_1000BASEX_FD	0x8000
224 #define	MII_XSTATUS_1000BASEX		0x4000
225 #define	MII_XSTATUS_1000BASET_FD	0x2000
226 #define	MII_XSTATUS_1000BASET		0x1000
227 
228 #define	MII_XSTATUS_BITS	\
229 	"\020"	\
230 	"\0201000BASEX_FD"	\
231 	"\0171000BASEX"		\
232 	"\0161000BASET_FD"	\
233 	"\0151000BASET"
234 
235 #define	MII_READ_CMD(p, r)	\
236 	((6<<(18+5+5)) | ((p)<<(18+5)) | ((r)<<18))
237 
238 #define	MII_WRITE_CMD(p, r, v)	\
239 	((5<<(18+5+5)) | ((p)<<(18+5)) | ((r)<<18) | (2 << 16) | (v))
240 
241 #endif /* _GEM_MII_H_ */
242