| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FixupSetCC.cpp | 123 Register ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
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| H A D | X86FrameLowering.cpp | 956 ZeroReg = InProlog ? X86::RCX : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
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| H A D | MipsAsmPrinter.cpp | 141 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch() local
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| H A D | MipsSEISelDAGToDAG.cpp | 85 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4430 unsigned Opcode, unsigned ZeroReg, in copyGPRRegTuple()
5924 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine()
5957 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL()
6100 unsigned Pattern) { in getMaddPatterns()
7049 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
7111 unsigned SubOpc, ZeroReg; in genAlternativeCodeSequence() local
7159 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
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| H A D | AArch64ExpandPseudoInsts.cpp | 237 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP()
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| H A D | AArch64FastISel.cpp | 384 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt() local
4939 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectSDiv() local
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| H A D | AArch64ISelDAGToDAG.cpp | 3785 unsigned ZeroReg; in tryShiftAmountMod() local
3805 unsigned ZeroReg; in tryShiftAmountMod() local
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| H A D | AArch64ISelLowering.cpp | 21863 unsigned ZeroReg; in replaceZeroVectorStore() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 934 SDValue ZeroReg = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8); in LowerINLINEASM() local
1915 Register ZeroReg = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift() local
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| H A D | AVRExpandPseudoInsts.cpp | 459 Register ZeroReg = MI.getOperand(2).getReg(); in expand() local
1494 Register ZeroReg = MI.getOperand(3).getReg(); in expandROLBRd() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | GIMatchTableExecutorImpl.h | 1088 uint16_t ZeroReg = readU16(); in executeMatchTable() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 552 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp() local
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| H A D | ARMFastISel.cpp | 1476 unsigned ZeroReg = fastMaterializeConstant(Zero); in SelectCmp() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 1636 Register ZeroReg = in legalizeIntrinsic() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVInstructionSelector.cpp | 1663 Register ZeroReg = buildZerosVal(ResType, I); in selectSelect() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 2782 unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg(); in loadImmediate() local
4259 unsigned ZeroReg; in expandDivRem() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2098 MCRegister ZeroReg; in onlyFoldImmediate() local
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| H A D | PPCISelDAGToDAG.cpp | 6310 SDValue ZeroReg = in Select() local
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| H A D | PPCISelLowering.cpp | 12242 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitPartwordAtomicBinary() local
13295 Register ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitInstrWithCustomInserter() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 8816 Register ZeroReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformLoopRegion() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 2292 Register ZeroReg; in applyCombineUnmergeZExtToZExt() local
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