1 //===--- AMDHSAKernelDescriptor.h -----------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "AMDGPUMCKernelDescriptor.h"
10 #include "AMDGPUMCTargetDesc.h"
11 #include "Utils/AMDGPUBaseInfo.h"
12 #include "llvm/MC/MCContext.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCSubtargetInfo.h"
15 #include "llvm/TargetParser/TargetParser.h"
16
17 using namespace llvm;
18 using namespace llvm::AMDGPU;
19
20 MCKernelDescriptor
getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo * STI,MCContext & Ctx)21 MCKernelDescriptor::getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI,
22 MCContext &Ctx) {
23 IsaVersion Version = getIsaVersion(STI->getCPU());
24
25 MCKernelDescriptor KD;
26 const MCExpr *ZeroMCExpr = MCConstantExpr::create(0, Ctx);
27 const MCExpr *OneMCExpr = MCConstantExpr::create(1, Ctx);
28
29 KD.group_segment_fixed_size = ZeroMCExpr;
30 KD.private_segment_fixed_size = ZeroMCExpr;
31 KD.compute_pgm_rsrc1 = ZeroMCExpr;
32 KD.compute_pgm_rsrc2 = ZeroMCExpr;
33 KD.compute_pgm_rsrc3 = ZeroMCExpr;
34 KD.kernarg_size = ZeroMCExpr;
35 KD.kernel_code_properties = ZeroMCExpr;
36 KD.kernarg_preload = ZeroMCExpr;
37
38 MCKernelDescriptor::bits_set(
39 KD.compute_pgm_rsrc1,
40 MCConstantExpr::create(amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE, Ctx),
41 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64_SHIFT,
42 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64, Ctx);
43 if (Version.Major < 12) {
44 MCKernelDescriptor::bits_set(
45 KD.compute_pgm_rsrc1, OneMCExpr,
46 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP_SHIFT,
47 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP, Ctx);
48 MCKernelDescriptor::bits_set(
49 KD.compute_pgm_rsrc1, OneMCExpr,
50 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE_SHIFT,
51 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE, Ctx);
52 }
53 MCKernelDescriptor::bits_set(
54 KD.compute_pgm_rsrc2, OneMCExpr,
55 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT,
56 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, Ctx);
57 if (Version.Major >= 10) {
58 if (STI->getFeatureBits().test(FeatureWavefrontSize32))
59 MCKernelDescriptor::bits_set(
60 KD.kernel_code_properties, OneMCExpr,
61 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_SHIFT,
62 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, Ctx);
63 if (!STI->getFeatureBits().test(FeatureCuMode))
64 MCKernelDescriptor::bits_set(
65 KD.compute_pgm_rsrc1, OneMCExpr,
66 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE_SHIFT,
67 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE, Ctx);
68
69 MCKernelDescriptor::bits_set(
70 KD.compute_pgm_rsrc1, OneMCExpr,
71 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED_SHIFT,
72 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED, Ctx);
73 }
74 if (AMDGPU::isGFX90A(*STI) && STI->getFeatureBits().test(FeatureTgSplit))
75 MCKernelDescriptor::bits_set(
76 KD.compute_pgm_rsrc3, OneMCExpr,
77 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT,
78 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, Ctx);
79 return KD;
80 }
81
bits_set(const MCExpr * & Dst,const MCExpr * Value,uint32_t Shift,uint32_t Mask,MCContext & Ctx)82 void MCKernelDescriptor::bits_set(const MCExpr *&Dst, const MCExpr *Value,
83 uint32_t Shift, uint32_t Mask,
84 MCContext &Ctx) {
85 auto Sft = MCConstantExpr::create(Shift, Ctx);
86 auto Msk = MCConstantExpr::create(Mask, Ctx);
87 Dst = MCBinaryExpr::createAnd(Dst, MCUnaryExpr::createNot(Msk, Ctx), Ctx);
88 Dst = MCBinaryExpr::createOr(Dst, MCBinaryExpr::createShl(Value, Sft, Ctx),
89 Ctx);
90 }
91
bits_get(const MCExpr * Src,uint32_t Shift,uint32_t Mask,MCContext & Ctx)92 const MCExpr *MCKernelDescriptor::bits_get(const MCExpr *Src, uint32_t Shift,
93 uint32_t Mask, MCContext &Ctx) {
94 auto Sft = MCConstantExpr::create(Shift, Ctx);
95 auto Msk = MCConstantExpr::create(Mask, Ctx);
96 return MCBinaryExpr::createLShr(MCBinaryExpr::createAnd(Src, Msk, Ctx), Sft,
97 Ctx);
98 }
99