xref: /linux/drivers/tty/serial/zs.c (revision a23e1966932464e1c5226cb9ac4ce1d5fc10ba22)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * zs.c: Serial port driver for IOASIC DECstations.
4  *
5  * Derived from drivers/sbus/char/sunserial.c by Paul Mackerras.
6  * Derived from drivers/macintosh/macserial.c by Harald Koerfgen.
7  *
8  * DECstation changes
9  * Copyright (C) 1998-2000 Harald Koerfgen
10  * Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007  Maciej W. Rozycki
11  *
12  * For the rest of the code the original Copyright applies:
13  * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
14  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
15  *
16  *
17  * Note: for IOASIC systems the wiring is as follows:
18  *
19  * mouse/keyboard:
20  * DIN-7 MJ-4  signal        SCC
21  * 2     1     TxD       <-  A.TxD
22  * 3     4     RxD       ->  A.RxD
23  *
24  * EIA-232/EIA-423:
25  * DB-25 MMJ-6 signal        SCC
26  * 2     2     TxD       <-  B.TxD
27  * 3     5     RxD       ->  B.RxD
28  * 4           RTS       <- ~A.RTS
29  * 5           CTS       -> ~B.CTS
30  * 6     6     DSR       -> ~A.SYNC
31  * 8           CD        -> ~B.DCD
32  * 12          DSRS(DCE) -> ~A.CTS  (*)
33  * 15          TxC       ->  B.TxC
34  * 17          RxC       ->  B.RxC
35  * 20    1     DTR       <- ~A.DTR
36  * 22          RI        -> ~A.DCD
37  * 23          DSRS(DTE) <- ~B.RTS
38  *
39  * (*) EIA-232 defines the signal at this pin to be SCD, while DSRS(DCE)
40  *     is shared with DSRS(DTE) at pin 23.
41  *
42  * As you can immediately notice the wiring of the RTS, DTR and DSR signals
43  * is a bit odd.  This makes the handling of port B unnecessarily
44  * complicated and prevents the use of some automatic modes of operation.
45  */
46 
47 #include <linux/bug.h>
48 #include <linux/console.h>
49 #include <linux/delay.h>
50 #include <linux/errno.h>
51 #include <linux/init.h>
52 #include <linux/interrupt.h>
53 #include <linux/io.h>
54 #include <linux/ioport.h>
55 #include <linux/irqflags.h>
56 #include <linux/kernel.h>
57 #include <linux/module.h>
58 #include <linux/major.h>
59 #include <linux/serial.h>
60 #include <linux/serial_core.h>
61 #include <linux/spinlock.h>
62 #include <linux/sysrq.h>
63 #include <linux/tty.h>
64 #include <linux/tty_flip.h>
65 #include <linux/types.h>
66 
67 #include <linux/atomic.h>
68 
69 #include <asm/dec/interrupts.h>
70 #include <asm/dec/ioasic_addrs.h>
71 #include <asm/dec/system.h>
72 
73 #include "zs.h"
74 
75 
76 MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>");
77 MODULE_DESCRIPTION("DECstation Z85C30 serial driver");
78 MODULE_LICENSE("GPL");
79 
80 
81 static char zs_name[] __initdata = "DECstation Z85C30 serial driver version ";
82 static char zs_version[] __initdata = "0.10";
83 
84 /*
85  * It would be nice to dynamically allocate everything that
86  * depends on ZS_NUM_SCCS, so we could support any number of
87  * Z85C30s, but for now...
88  */
89 #define ZS_NUM_SCCS	2		/* Max # of ZS chips supported.  */
90 #define ZS_NUM_CHAN	2		/* 2 channels per chip.  */
91 #define ZS_CHAN_A	0		/* Index of the channel A.  */
92 #define ZS_CHAN_B	1		/* Index of the channel B.  */
93 #define ZS_CHAN_IO_SIZE 8		/* IOMEM space size.  */
94 #define ZS_CHAN_IO_STRIDE 4		/* Register alignment.  */
95 #define ZS_CHAN_IO_OFFSET 1		/* The SCC resides on the high byte
96 					   of the 16-bit IOBUS.  */
97 #define ZS_CLOCK        7372800 	/* Z85C30 PCLK input clock rate.  */
98 
99 #define to_zport(uport) container_of(uport, struct zs_port, port)
100 
101 struct zs_parms {
102 	resource_size_t scc[ZS_NUM_SCCS];
103 	int irq[ZS_NUM_SCCS];
104 };
105 
106 static struct zs_scc zs_sccs[ZS_NUM_SCCS];
107 
108 static u8 zs_init_regs[ZS_NUM_REGS] __initdata = {
109 	0,				/* write 0 */
110 	PAR_SPEC,			/* write 1 */
111 	0,				/* write 2 */
112 	0,				/* write 3 */
113 	X16CLK | SB1,			/* write 4 */
114 	0,				/* write 5 */
115 	0, 0, 0,			/* write 6, 7, 8 */
116 	MIE | DLC | NV,			/* write 9 */
117 	NRZ,				/* write 10 */
118 	TCBR | RCBR,			/* write 11 */
119 	0, 0,				/* BRG time constant, write 12 + 13 */
120 	BRSRC | BRENABL,		/* write 14 */
121 	0,				/* write 15 */
122 };
123 
124 /*
125  * Debugging.
126  */
127 #undef ZS_DEBUG_REGS
128 
129 
130 /*
131  * Reading and writing Z85C30 registers.
132  */
133 static void recovery_delay(void)
134 {
135 	udelay(2);
136 }
137 
138 static u8 read_zsreg(struct zs_port *zport, int reg)
139 {
140 	void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;
141 	u8 retval;
142 
143 	if (reg != 0) {
144 		writeb(reg & 0xf, control);
145 		fast_iob();
146 		recovery_delay();
147 	}
148 	retval = readb(control);
149 	recovery_delay();
150 	return retval;
151 }
152 
153 static void write_zsreg(struct zs_port *zport, int reg, u8 value)
154 {
155 	void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;
156 
157 	if (reg != 0) {
158 		writeb(reg & 0xf, control);
159 		fast_iob(); recovery_delay();
160 	}
161 	writeb(value, control);
162 	fast_iob();
163 	recovery_delay();
164 	return;
165 }
166 
167 static u8 read_zsdata(struct zs_port *zport)
168 {
169 	void __iomem *data = zport->port.membase +
170 			     ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;
171 	u8 retval;
172 
173 	retval = readb(data);
174 	recovery_delay();
175 	return retval;
176 }
177 
178 static void write_zsdata(struct zs_port *zport, u8 value)
179 {
180 	void __iomem *data = zport->port.membase +
181 			     ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;
182 
183 	writeb(value, data);
184 	fast_iob();
185 	recovery_delay();
186 	return;
187 }
188 
189 #ifdef ZS_DEBUG_REGS
190 void zs_dump(void)
191 {
192 	struct zs_port *zport;
193 	int i, j;
194 
195 	for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {
196 		zport = &zs_sccs[i / ZS_NUM_CHAN].zport[i % ZS_NUM_CHAN];
197 
198 		if (!zport->scc)
199 			continue;
200 
201 		for (j = 0; j < 16; j++)
202 			printk("W%-2d = 0x%02x\t", j, zport->regs[j]);
203 		printk("\n");
204 		for (j = 0; j < 16; j++)
205 			printk("R%-2d = 0x%02x\t", j, read_zsreg(zport, j));
206 		printk("\n\n");
207 	}
208 }
209 #endif
210 
211 
212 static void zs_spin_lock_cond_irq(spinlock_t *lock, int irq)
213 {
214 	if (irq)
215 		spin_lock_irq(lock);
216 	else
217 		spin_lock(lock);
218 }
219 
220 static void zs_spin_unlock_cond_irq(spinlock_t *lock, int irq)
221 {
222 	if (irq)
223 		spin_unlock_irq(lock);
224 	else
225 		spin_unlock(lock);
226 }
227 
228 static int zs_receive_drain(struct zs_port *zport)
229 {
230 	int loops = 10000;
231 
232 	while ((read_zsreg(zport, R0) & Rx_CH_AV) && --loops)
233 		read_zsdata(zport);
234 	return loops;
235 }
236 
237 static int zs_transmit_drain(struct zs_port *zport, int irq)
238 {
239 	struct zs_scc *scc = zport->scc;
240 	int loops = 10000;
241 
242 	while (!(read_zsreg(zport, R0) & Tx_BUF_EMP) && --loops) {
243 		zs_spin_unlock_cond_irq(&scc->zlock, irq);
244 		udelay(2);
245 		zs_spin_lock_cond_irq(&scc->zlock, irq);
246 	}
247 	return loops;
248 }
249 
250 static int zs_line_drain(struct zs_port *zport, int irq)
251 {
252 	struct zs_scc *scc = zport->scc;
253 	int loops = 10000;
254 
255 	while (!(read_zsreg(zport, R1) & ALL_SNT) && --loops) {
256 		zs_spin_unlock_cond_irq(&scc->zlock, irq);
257 		udelay(2);
258 		zs_spin_lock_cond_irq(&scc->zlock, irq);
259 	}
260 	return loops;
261 }
262 
263 
264 static void load_zsregs(struct zs_port *zport, u8 *regs, int irq)
265 {
266 	/* Let the current transmission finish.  */
267 	zs_line_drain(zport, irq);
268 	/* Load 'em up.  */
269 	write_zsreg(zport, R3, regs[3] & ~RxENABLE);
270 	write_zsreg(zport, R5, regs[5] & ~TxENAB);
271 	write_zsreg(zport, R4, regs[4]);
272 	write_zsreg(zport, R9, regs[9]);
273 	write_zsreg(zport, R1, regs[1]);
274 	write_zsreg(zport, R2, regs[2]);
275 	write_zsreg(zport, R10, regs[10]);
276 	write_zsreg(zport, R14, regs[14] & ~BRENABL);
277 	write_zsreg(zport, R11, regs[11]);
278 	write_zsreg(zport, R12, regs[12]);
279 	write_zsreg(zport, R13, regs[13]);
280 	write_zsreg(zport, R14, regs[14]);
281 	write_zsreg(zport, R15, regs[15]);
282 	if (regs[3] & RxENABLE)
283 		write_zsreg(zport, R3, regs[3]);
284 	if (regs[5] & TxENAB)
285 		write_zsreg(zport, R5, regs[5]);
286 	return;
287 }
288 
289 
290 /*
291  * Status handling routines.
292  */
293 
294 /*
295  * zs_tx_empty() -- get the transmitter empty status
296  *
297  * Purpose: Let user call ioctl() to get info when the UART physically
298  * 	    is emptied.  On bus types like RS485, the transmitter must
299  * 	    release the bus after transmitting.  This must be done when
300  * 	    the transmit shift register is empty, not be done when the
301  * 	    transmit holding register is empty.  This functionality
302  * 	    allows an RS485 driver to be written in user space.
303  */
304 static unsigned int zs_tx_empty(struct uart_port *uport)
305 {
306 	struct zs_port *zport = to_zport(uport);
307 	struct zs_scc *scc = zport->scc;
308 	unsigned long flags;
309 	u8 status;
310 
311 	spin_lock_irqsave(&scc->zlock, flags);
312 	status = read_zsreg(zport, R1);
313 	spin_unlock_irqrestore(&scc->zlock, flags);
314 
315 	return status & ALL_SNT ? TIOCSER_TEMT : 0;
316 }
317 
318 static unsigned int zs_raw_get_ab_mctrl(struct zs_port *zport_a,
319 					struct zs_port *zport_b)
320 {
321 	u8 status_a, status_b;
322 	unsigned int mctrl;
323 
324 	status_a = read_zsreg(zport_a, R0);
325 	status_b = read_zsreg(zport_b, R0);
326 
327 	mctrl = ((status_b & CTS) ? TIOCM_CTS : 0) |
328 		((status_b & DCD) ? TIOCM_CAR : 0) |
329 		((status_a & DCD) ? TIOCM_RNG : 0) |
330 		((status_a & SYNC_HUNT) ? TIOCM_DSR : 0);
331 
332 	return mctrl;
333 }
334 
335 static unsigned int zs_raw_get_mctrl(struct zs_port *zport)
336 {
337 	struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];
338 
339 	return zport != zport_a ? zs_raw_get_ab_mctrl(zport_a, zport) : 0;
340 }
341 
342 static unsigned int zs_raw_xor_mctrl(struct zs_port *zport)
343 {
344 	struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];
345 	unsigned int mmask, mctrl, delta;
346 	u8 mask_a, mask_b;
347 
348 	if (zport == zport_a)
349 		return 0;
350 
351 	mask_a = zport_a->regs[15];
352 	mask_b = zport->regs[15];
353 
354 	mmask = ((mask_b & CTSIE) ? TIOCM_CTS : 0) |
355 		((mask_b & DCDIE) ? TIOCM_CAR : 0) |
356 		((mask_a & DCDIE) ? TIOCM_RNG : 0) |
357 		((mask_a & SYNCIE) ? TIOCM_DSR : 0);
358 
359 	mctrl = zport->mctrl;
360 	if (mmask) {
361 		mctrl &= ~mmask;
362 		mctrl |= zs_raw_get_ab_mctrl(zport_a, zport) & mmask;
363 	}
364 
365 	delta = mctrl ^ zport->mctrl;
366 	if (delta)
367 		zport->mctrl = mctrl;
368 
369 	return delta;
370 }
371 
372 static unsigned int zs_get_mctrl(struct uart_port *uport)
373 {
374 	struct zs_port *zport = to_zport(uport);
375 	struct zs_scc *scc = zport->scc;
376 	unsigned int mctrl;
377 
378 	spin_lock(&scc->zlock);
379 	mctrl = zs_raw_get_mctrl(zport);
380 	spin_unlock(&scc->zlock);
381 
382 	return mctrl;
383 }
384 
385 static void zs_set_mctrl(struct uart_port *uport, unsigned int mctrl)
386 {
387 	struct zs_port *zport = to_zport(uport);
388 	struct zs_scc *scc = zport->scc;
389 	struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
390 	u8 oldloop, newloop;
391 
392 	spin_lock(&scc->zlock);
393 	if (zport != zport_a) {
394 		if (mctrl & TIOCM_DTR)
395 			zport_a->regs[5] |= DTR;
396 		else
397 			zport_a->regs[5] &= ~DTR;
398 		if (mctrl & TIOCM_RTS)
399 			zport_a->regs[5] |= RTS;
400 		else
401 			zport_a->regs[5] &= ~RTS;
402 		write_zsreg(zport_a, R5, zport_a->regs[5]);
403 	}
404 
405 	/* Rarely modified, so don't poke at hardware unless necessary. */
406 	oldloop = zport->regs[14];
407 	newloop = oldloop;
408 	if (mctrl & TIOCM_LOOP)
409 		newloop |= LOOPBAK;
410 	else
411 		newloop &= ~LOOPBAK;
412 	if (newloop != oldloop) {
413 		zport->regs[14] = newloop;
414 		write_zsreg(zport, R14, zport->regs[14]);
415 	}
416 	spin_unlock(&scc->zlock);
417 }
418 
419 static void zs_raw_stop_tx(struct zs_port *zport)
420 {
421 	write_zsreg(zport, R0, RES_Tx_P);
422 	zport->tx_stopped = 1;
423 }
424 
425 static void zs_stop_tx(struct uart_port *uport)
426 {
427 	struct zs_port *zport = to_zport(uport);
428 	struct zs_scc *scc = zport->scc;
429 
430 	spin_lock(&scc->zlock);
431 	zs_raw_stop_tx(zport);
432 	spin_unlock(&scc->zlock);
433 }
434 
435 static void zs_raw_transmit_chars(struct zs_port *);
436 
437 static void zs_start_tx(struct uart_port *uport)
438 {
439 	struct zs_port *zport = to_zport(uport);
440 	struct zs_scc *scc = zport->scc;
441 
442 	spin_lock(&scc->zlock);
443 	if (zport->tx_stopped) {
444 		zs_transmit_drain(zport, 0);
445 		zport->tx_stopped = 0;
446 		zs_raw_transmit_chars(zport);
447 	}
448 	spin_unlock(&scc->zlock);
449 }
450 
451 static void zs_stop_rx(struct uart_port *uport)
452 {
453 	struct zs_port *zport = to_zport(uport);
454 	struct zs_scc *scc = zport->scc;
455 	struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
456 
457 	spin_lock(&scc->zlock);
458 	zport->regs[15] &= ~BRKIE;
459 	zport->regs[1] &= ~(RxINT_MASK | TxINT_ENAB);
460 	zport->regs[1] |= RxINT_DISAB;
461 
462 	if (zport != zport_a) {
463 		/* A-side DCD tracks RI and SYNC tracks DSR.  */
464 		zport_a->regs[15] &= ~(DCDIE | SYNCIE);
465 		write_zsreg(zport_a, R15, zport_a->regs[15]);
466 		if (!(zport_a->regs[15] & BRKIE)) {
467 			zport_a->regs[1] &= ~EXT_INT_ENAB;
468 			write_zsreg(zport_a, R1, zport_a->regs[1]);
469 		}
470 
471 		/* This-side DCD tracks DCD and CTS tracks CTS.  */
472 		zport->regs[15] &= ~(DCDIE | CTSIE);
473 		zport->regs[1] &= ~EXT_INT_ENAB;
474 	} else {
475 		/* DCD tracks RI and SYNC tracks DSR for the B side.  */
476 		if (!(zport->regs[15] & (DCDIE | SYNCIE)))
477 			zport->regs[1] &= ~EXT_INT_ENAB;
478 	}
479 
480 	write_zsreg(zport, R15, zport->regs[15]);
481 	write_zsreg(zport, R1, zport->regs[1]);
482 	spin_unlock(&scc->zlock);
483 }
484 
485 static void zs_enable_ms(struct uart_port *uport)
486 {
487 	struct zs_port *zport = to_zport(uport);
488 	struct zs_scc *scc = zport->scc;
489 	struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
490 
491 	if (zport == zport_a)
492 		return;
493 
494 	spin_lock(&scc->zlock);
495 
496 	/* Clear Ext interrupts if not being handled already.  */
497 	if (!(zport_a->regs[1] & EXT_INT_ENAB))
498 		write_zsreg(zport_a, R0, RES_EXT_INT);
499 
500 	/* A-side DCD tracks RI and SYNC tracks DSR.  */
501 	zport_a->regs[1] |= EXT_INT_ENAB;
502 	zport_a->regs[15] |= DCDIE | SYNCIE;
503 
504 	/* This-side DCD tracks DCD and CTS tracks CTS.  */
505 	zport->regs[15] |= DCDIE | CTSIE;
506 
507 	zs_raw_xor_mctrl(zport);
508 
509 	write_zsreg(zport_a, R1, zport_a->regs[1]);
510 	write_zsreg(zport_a, R15, zport_a->regs[15]);
511 	write_zsreg(zport, R15, zport->regs[15]);
512 	spin_unlock(&scc->zlock);
513 }
514 
515 static void zs_break_ctl(struct uart_port *uport, int break_state)
516 {
517 	struct zs_port *zport = to_zport(uport);
518 	struct zs_scc *scc = zport->scc;
519 	unsigned long flags;
520 
521 	spin_lock_irqsave(&scc->zlock, flags);
522 	if (break_state == -1)
523 		zport->regs[5] |= SND_BRK;
524 	else
525 		zport->regs[5] &= ~SND_BRK;
526 	write_zsreg(zport, R5, zport->regs[5]);
527 	spin_unlock_irqrestore(&scc->zlock, flags);
528 }
529 
530 
531 /*
532  * Interrupt handling routines.
533  */
534 #define Rx_BRK 0x0100			/* BREAK event software flag.  */
535 #define Rx_SYS 0x0200			/* SysRq event software flag.  */
536 
537 static void zs_receive_chars(struct zs_port *zport)
538 {
539 	struct uart_port *uport = &zport->port;
540 	struct zs_scc *scc = zport->scc;
541 	struct uart_icount *icount;
542 	unsigned int avail, status;
543 	int count;
544 	u8 ch, flag;
545 
546 	for (count = 16; count; count--) {
547 		spin_lock(&scc->zlock);
548 		avail = read_zsreg(zport, R0) & Rx_CH_AV;
549 		spin_unlock(&scc->zlock);
550 		if (!avail)
551 			break;
552 
553 		spin_lock(&scc->zlock);
554 		status = read_zsreg(zport, R1) & (Rx_OVR | FRM_ERR | PAR_ERR);
555 		ch = read_zsdata(zport);
556 		spin_unlock(&scc->zlock);
557 
558 		flag = TTY_NORMAL;
559 
560 		icount = &uport->icount;
561 		icount->rx++;
562 
563 		/* Handle the null char got when BREAK is removed.  */
564 		if (!ch)
565 			status |= zport->tty_break;
566 		if (unlikely(status &
567 			     (Rx_OVR | FRM_ERR | PAR_ERR | Rx_SYS | Rx_BRK))) {
568 			zport->tty_break = 0;
569 
570 			/* Reset the error indication.  */
571 			if (status & (Rx_OVR | FRM_ERR | PAR_ERR)) {
572 				spin_lock(&scc->zlock);
573 				write_zsreg(zport, R0, ERR_RES);
574 				spin_unlock(&scc->zlock);
575 			}
576 
577 			if (status & (Rx_SYS | Rx_BRK)) {
578 				icount->brk++;
579 				/* SysRq discards the null char.  */
580 				if (status & Rx_SYS)
581 					continue;
582 			} else if (status & FRM_ERR)
583 				icount->frame++;
584 			else if (status & PAR_ERR)
585 				icount->parity++;
586 			if (status & Rx_OVR)
587 				icount->overrun++;
588 
589 			status &= uport->read_status_mask;
590 			if (status & Rx_BRK)
591 				flag = TTY_BREAK;
592 			else if (status & FRM_ERR)
593 				flag = TTY_FRAME;
594 			else if (status & PAR_ERR)
595 				flag = TTY_PARITY;
596 		}
597 
598 		if (uart_handle_sysrq_char(uport, ch))
599 			continue;
600 
601 		uart_insert_char(uport, status, Rx_OVR, ch, flag);
602 	}
603 
604 	tty_flip_buffer_push(&uport->state->port);
605 }
606 
607 static void zs_raw_transmit_chars(struct zs_port *zport)
608 {
609 	struct circ_buf *xmit = &zport->port.state->xmit;
610 
611 	/* XON/XOFF chars.  */
612 	if (zport->port.x_char) {
613 		write_zsdata(zport, zport->port.x_char);
614 		zport->port.icount.tx++;
615 		zport->port.x_char = 0;
616 		return;
617 	}
618 
619 	/* If nothing to do or stopped or hardware stopped.  */
620 	if (uart_circ_empty(xmit) || uart_tx_stopped(&zport->port)) {
621 		zs_raw_stop_tx(zport);
622 		return;
623 	}
624 
625 	/* Send char.  */
626 	write_zsdata(zport, xmit->buf[xmit->tail]);
627 	uart_xmit_advance(&zport->port, 1);
628 
629 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
630 		uart_write_wakeup(&zport->port);
631 
632 	/* Are we are done?  */
633 	if (uart_circ_empty(xmit))
634 		zs_raw_stop_tx(zport);
635 }
636 
637 static void zs_transmit_chars(struct zs_port *zport)
638 {
639 	struct zs_scc *scc = zport->scc;
640 
641 	spin_lock(&scc->zlock);
642 	zs_raw_transmit_chars(zport);
643 	spin_unlock(&scc->zlock);
644 }
645 
646 static void zs_status_handle(struct zs_port *zport, struct zs_port *zport_a)
647 {
648 	struct uart_port *uport = &zport->port;
649 	struct zs_scc *scc = zport->scc;
650 	unsigned int delta;
651 	u8 status, brk;
652 
653 	spin_lock(&scc->zlock);
654 
655 	/* Get status from Read Register 0.  */
656 	status = read_zsreg(zport, R0);
657 
658 	if (zport->regs[15] & BRKIE) {
659 		brk = status & BRK_ABRT;
660 		if (brk && !zport->brk) {
661 			spin_unlock(&scc->zlock);
662 			if (uart_handle_break(uport))
663 				zport->tty_break = Rx_SYS;
664 			else
665 				zport->tty_break = Rx_BRK;
666 			spin_lock(&scc->zlock);
667 		}
668 		zport->brk = brk;
669 	}
670 
671 	if (zport != zport_a) {
672 		delta = zs_raw_xor_mctrl(zport);
673 		spin_unlock(&scc->zlock);
674 
675 		if (delta & TIOCM_CTS)
676 			uart_handle_cts_change(uport,
677 					       zport->mctrl & TIOCM_CTS);
678 		if (delta & TIOCM_CAR)
679 			uart_handle_dcd_change(uport,
680 					       zport->mctrl & TIOCM_CAR);
681 		if (delta & TIOCM_RNG)
682 			uport->icount.dsr++;
683 		if (delta & TIOCM_DSR)
684 			uport->icount.rng++;
685 
686 		if (delta)
687 			wake_up_interruptible(&uport->state->port.delta_msr_wait);
688 
689 		spin_lock(&scc->zlock);
690 	}
691 
692 	/* Clear the status condition...  */
693 	write_zsreg(zport, R0, RES_EXT_INT);
694 
695 	spin_unlock(&scc->zlock);
696 }
697 
698 /*
699  * This is the Z85C30 driver's generic interrupt routine.
700  */
701 static irqreturn_t zs_interrupt(int irq, void *dev_id)
702 {
703 	struct zs_scc *scc = dev_id;
704 	struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
705 	struct zs_port *zport_b = &scc->zport[ZS_CHAN_B];
706 	irqreturn_t status = IRQ_NONE;
707 	u8 zs_intreg;
708 	int count;
709 
710 	/*
711 	 * NOTE: The read register 3, which holds the irq status,
712 	 *       does so for both channels on each chip.  Although
713 	 *       the status value itself must be read from the A
714 	 *       channel and is only valid when read from channel A.
715 	 *       Yes... broken hardware...
716 	 */
717 	for (count = 16; count; count--) {
718 		spin_lock(&scc->zlock);
719 		zs_intreg = read_zsreg(zport_a, R3);
720 		spin_unlock(&scc->zlock);
721 		if (!zs_intreg)
722 			break;
723 
724 		/*
725 		 * We do not like losing characters, so we prioritise
726 		 * interrupt sources a little bit differently than
727 		 * the SCC would, was it allowed to.
728 		 */
729 		if (zs_intreg & CHBRxIP)
730 			zs_receive_chars(zport_b);
731 		if (zs_intreg & CHARxIP)
732 			zs_receive_chars(zport_a);
733 		if (zs_intreg & CHBEXT)
734 			zs_status_handle(zport_b, zport_a);
735 		if (zs_intreg & CHAEXT)
736 			zs_status_handle(zport_a, zport_a);
737 		if (zs_intreg & CHBTxIP)
738 			zs_transmit_chars(zport_b);
739 		if (zs_intreg & CHATxIP)
740 			zs_transmit_chars(zport_a);
741 
742 		status = IRQ_HANDLED;
743 	}
744 
745 	return status;
746 }
747 
748 
749 /*
750  * Finally, routines used to initialize the serial port.
751  */
752 static int zs_startup(struct uart_port *uport)
753 {
754 	struct zs_port *zport = to_zport(uport);
755 	struct zs_scc *scc = zport->scc;
756 	unsigned long flags;
757 	int irq_guard;
758 	int ret;
759 
760 	irq_guard = atomic_add_return(1, &scc->irq_guard);
761 	if (irq_guard == 1) {
762 		ret = request_irq(zport->port.irq, zs_interrupt,
763 				  IRQF_SHARED, "scc", scc);
764 		if (ret) {
765 			atomic_add(-1, &scc->irq_guard);
766 			printk(KERN_ERR "zs: can't get irq %d\n",
767 			       zport->port.irq);
768 			return ret;
769 		}
770 	}
771 
772 	spin_lock_irqsave(&scc->zlock, flags);
773 
774 	/* Clear the receive FIFO.  */
775 	zs_receive_drain(zport);
776 
777 	/* Clear the interrupt registers.  */
778 	write_zsreg(zport, R0, ERR_RES);
779 	write_zsreg(zport, R0, RES_Tx_P);
780 	/* But Ext only if not being handled already.  */
781 	if (!(zport->regs[1] & EXT_INT_ENAB))
782 		write_zsreg(zport, R0, RES_EXT_INT);
783 
784 	/* Finally, enable sequencing and interrupts.  */
785 	zport->regs[1] &= ~RxINT_MASK;
786 	zport->regs[1] |= RxINT_ALL | TxINT_ENAB | EXT_INT_ENAB;
787 	zport->regs[3] |= RxENABLE;
788 	zport->regs[15] |= BRKIE;
789 	write_zsreg(zport, R1, zport->regs[1]);
790 	write_zsreg(zport, R3, zport->regs[3]);
791 	write_zsreg(zport, R5, zport->regs[5]);
792 	write_zsreg(zport, R15, zport->regs[15]);
793 
794 	/* Record the current state of RR0.  */
795 	zport->mctrl = zs_raw_get_mctrl(zport);
796 	zport->brk = read_zsreg(zport, R0) & BRK_ABRT;
797 
798 	zport->tx_stopped = 1;
799 
800 	spin_unlock_irqrestore(&scc->zlock, flags);
801 
802 	return 0;
803 }
804 
805 static void zs_shutdown(struct uart_port *uport)
806 {
807 	struct zs_port *zport = to_zport(uport);
808 	struct zs_scc *scc = zport->scc;
809 	unsigned long flags;
810 	int irq_guard;
811 
812 	spin_lock_irqsave(&scc->zlock, flags);
813 
814 	zport->regs[3] &= ~RxENABLE;
815 	write_zsreg(zport, R5, zport->regs[5]);
816 	write_zsreg(zport, R3, zport->regs[3]);
817 
818 	spin_unlock_irqrestore(&scc->zlock, flags);
819 
820 	irq_guard = atomic_add_return(-1, &scc->irq_guard);
821 	if (!irq_guard)
822 		free_irq(zport->port.irq, scc);
823 }
824 
825 
826 static void zs_reset(struct zs_port *zport)
827 {
828 	struct zs_scc *scc = zport->scc;
829 	int irq;
830 	unsigned long flags;
831 
832 	spin_lock_irqsave(&scc->zlock, flags);
833 	irq = !irqs_disabled_flags(flags);
834 	if (!scc->initialised) {
835 		/* Reset the pointer first, just in case...  */
836 		read_zsreg(zport, R0);
837 		/* And let the current transmission finish.  */
838 		zs_line_drain(zport, irq);
839 		write_zsreg(zport, R9, FHWRES);
840 		udelay(10);
841 		write_zsreg(zport, R9, 0);
842 		scc->initialised = 1;
843 	}
844 	load_zsregs(zport, zport->regs, irq);
845 	spin_unlock_irqrestore(&scc->zlock, flags);
846 }
847 
848 static void zs_set_termios(struct uart_port *uport, struct ktermios *termios,
849 			   const struct ktermios *old_termios)
850 {
851 	struct zs_port *zport = to_zport(uport);
852 	struct zs_scc *scc = zport->scc;
853 	struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
854 	int irq;
855 	unsigned int baud, brg;
856 	unsigned long flags;
857 
858 	spin_lock_irqsave(&scc->zlock, flags);
859 	irq = !irqs_disabled_flags(flags);
860 
861 	/* Byte size.  */
862 	zport->regs[3] &= ~RxNBITS_MASK;
863 	zport->regs[5] &= ~TxNBITS_MASK;
864 	switch (termios->c_cflag & CSIZE) {
865 	case CS5:
866 		zport->regs[3] |= Rx5;
867 		zport->regs[5] |= Tx5;
868 		break;
869 	case CS6:
870 		zport->regs[3] |= Rx6;
871 		zport->regs[5] |= Tx6;
872 		break;
873 	case CS7:
874 		zport->regs[3] |= Rx7;
875 		zport->regs[5] |= Tx7;
876 		break;
877 	case CS8:
878 	default:
879 		zport->regs[3] |= Rx8;
880 		zport->regs[5] |= Tx8;
881 		break;
882 	}
883 
884 	/* Parity and stop bits.  */
885 	zport->regs[4] &= ~(XCLK_MASK | SB_MASK | PAR_ENA | PAR_EVEN);
886 	if (termios->c_cflag & CSTOPB)
887 		zport->regs[4] |= SB2;
888 	else
889 		zport->regs[4] |= SB1;
890 	if (termios->c_cflag & PARENB)
891 		zport->regs[4] |= PAR_ENA;
892 	if (!(termios->c_cflag & PARODD))
893 		zport->regs[4] |= PAR_EVEN;
894 	switch (zport->clk_mode) {
895 	case 64:
896 		zport->regs[4] |= X64CLK;
897 		break;
898 	case 32:
899 		zport->regs[4] |= X32CLK;
900 		break;
901 	case 16:
902 		zport->regs[4] |= X16CLK;
903 		break;
904 	case 1:
905 		zport->regs[4] |= X1CLK;
906 		break;
907 	default:
908 		BUG();
909 	}
910 
911 	baud = uart_get_baud_rate(uport, termios, old_termios, 0,
912 				  uport->uartclk / zport->clk_mode / 4);
913 
914 	brg = ZS_BPS_TO_BRG(baud, uport->uartclk / zport->clk_mode);
915 	zport->regs[12] = brg & 0xff;
916 	zport->regs[13] = (brg >> 8) & 0xff;
917 
918 	uart_update_timeout(uport, termios->c_cflag, baud);
919 
920 	uport->read_status_mask = Rx_OVR;
921 	if (termios->c_iflag & INPCK)
922 		uport->read_status_mask |= FRM_ERR | PAR_ERR;
923 	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
924 		uport->read_status_mask |= Rx_BRK;
925 
926 	uport->ignore_status_mask = 0;
927 	if (termios->c_iflag & IGNPAR)
928 		uport->ignore_status_mask |= FRM_ERR | PAR_ERR;
929 	if (termios->c_iflag & IGNBRK) {
930 		uport->ignore_status_mask |= Rx_BRK;
931 		if (termios->c_iflag & IGNPAR)
932 			uport->ignore_status_mask |= Rx_OVR;
933 	}
934 
935 	if (termios->c_cflag & CREAD)
936 		zport->regs[3] |= RxENABLE;
937 	else
938 		zport->regs[3] &= ~RxENABLE;
939 
940 	if (zport != zport_a) {
941 		if (!(termios->c_cflag & CLOCAL)) {
942 			zport->regs[15] |= DCDIE;
943 		} else
944 			zport->regs[15] &= ~DCDIE;
945 		if (termios->c_cflag & CRTSCTS) {
946 			zport->regs[15] |= CTSIE;
947 		} else
948 			zport->regs[15] &= ~CTSIE;
949 		zs_raw_xor_mctrl(zport);
950 	}
951 
952 	/* Load up the new values.  */
953 	load_zsregs(zport, zport->regs, irq);
954 
955 	spin_unlock_irqrestore(&scc->zlock, flags);
956 }
957 
958 /*
959  * Hack alert!
960  * Required solely so that the initial PROM-based console
961  * works undisturbed in parallel with this one.
962  */
963 static void zs_pm(struct uart_port *uport, unsigned int state,
964 		  unsigned int oldstate)
965 {
966 	struct zs_port *zport = to_zport(uport);
967 
968 	if (state < 3)
969 		zport->regs[5] |= TxENAB;
970 	else
971 		zport->regs[5] &= ~TxENAB;
972 	write_zsreg(zport, R5, zport->regs[5]);
973 }
974 
975 
976 static const char *zs_type(struct uart_port *uport)
977 {
978 	return "Z85C30 SCC";
979 }
980 
981 static void zs_release_port(struct uart_port *uport)
982 {
983 	iounmap(uport->membase);
984 	uport->membase = NULL;
985 	release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
986 }
987 
988 static int zs_map_port(struct uart_port *uport)
989 {
990 	if (!uport->membase)
991 		uport->membase = ioremap(uport->mapbase,
992 						 ZS_CHAN_IO_SIZE);
993 	if (!uport->membase) {
994 		printk(KERN_ERR "zs: Cannot map MMIO\n");
995 		return -ENOMEM;
996 	}
997 	return 0;
998 }
999 
1000 static int zs_request_port(struct uart_port *uport)
1001 {
1002 	int ret;
1003 
1004 	if (!request_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE, "scc")) {
1005 		printk(KERN_ERR "zs: Unable to reserve MMIO resource\n");
1006 		return -EBUSY;
1007 	}
1008 	ret = zs_map_port(uport);
1009 	if (ret) {
1010 		release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
1011 		return ret;
1012 	}
1013 	return 0;
1014 }
1015 
1016 static void zs_config_port(struct uart_port *uport, int flags)
1017 {
1018 	struct zs_port *zport = to_zport(uport);
1019 
1020 	if (flags & UART_CONFIG_TYPE) {
1021 		if (zs_request_port(uport))
1022 			return;
1023 
1024 		uport->type = PORT_ZS;
1025 
1026 		zs_reset(zport);
1027 	}
1028 }
1029 
1030 static int zs_verify_port(struct uart_port *uport, struct serial_struct *ser)
1031 {
1032 	struct zs_port *zport = to_zport(uport);
1033 	int ret = 0;
1034 
1035 	if (ser->type != PORT_UNKNOWN && ser->type != PORT_ZS)
1036 		ret = -EINVAL;
1037 	if (ser->irq != uport->irq)
1038 		ret = -EINVAL;
1039 	if (ser->baud_base != uport->uartclk / zport->clk_mode / 4)
1040 		ret = -EINVAL;
1041 	return ret;
1042 }
1043 
1044 
1045 static const struct uart_ops zs_ops = {
1046 	.tx_empty	= zs_tx_empty,
1047 	.set_mctrl	= zs_set_mctrl,
1048 	.get_mctrl	= zs_get_mctrl,
1049 	.stop_tx	= zs_stop_tx,
1050 	.start_tx	= zs_start_tx,
1051 	.stop_rx	= zs_stop_rx,
1052 	.enable_ms	= zs_enable_ms,
1053 	.break_ctl	= zs_break_ctl,
1054 	.startup	= zs_startup,
1055 	.shutdown	= zs_shutdown,
1056 	.set_termios	= zs_set_termios,
1057 	.pm		= zs_pm,
1058 	.type		= zs_type,
1059 	.release_port	= zs_release_port,
1060 	.request_port	= zs_request_port,
1061 	.config_port	= zs_config_port,
1062 	.verify_port	= zs_verify_port,
1063 };
1064 
1065 /*
1066  * Initialize Z85C30 port structures.
1067  */
1068 static int __init zs_probe_sccs(void)
1069 {
1070 	static int probed;
1071 	struct zs_parms zs_parms;
1072 	int chip, side, irq;
1073 	int n_chips = 0;
1074 	int i;
1075 
1076 	if (probed)
1077 		return 0;
1078 
1079 	irq = dec_interrupt[DEC_IRQ_SCC0];
1080 	if (irq >= 0) {
1081 		zs_parms.scc[n_chips] = IOASIC_SCC0;
1082 		zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC0];
1083 		n_chips++;
1084 	}
1085 	irq = dec_interrupt[DEC_IRQ_SCC1];
1086 	if (irq >= 0) {
1087 		zs_parms.scc[n_chips] = IOASIC_SCC1;
1088 		zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC1];
1089 		n_chips++;
1090 	}
1091 	if (!n_chips)
1092 		return -ENXIO;
1093 
1094 	probed = 1;
1095 
1096 	for (chip = 0; chip < n_chips; chip++) {
1097 		spin_lock_init(&zs_sccs[chip].zlock);
1098 		for (side = 0; side < ZS_NUM_CHAN; side++) {
1099 			struct zs_port *zport = &zs_sccs[chip].zport[side];
1100 			struct uart_port *uport = &zport->port;
1101 
1102 			zport->scc	= &zs_sccs[chip];
1103 			zport->clk_mode	= 16;
1104 
1105 			uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_ZS_CONSOLE);
1106 			uport->irq	= zs_parms.irq[chip];
1107 			uport->uartclk	= ZS_CLOCK;
1108 			uport->fifosize	= 1;
1109 			uport->iotype	= UPIO_MEM;
1110 			uport->flags	= UPF_BOOT_AUTOCONF;
1111 			uport->ops	= &zs_ops;
1112 			uport->line	= chip * ZS_NUM_CHAN + side;
1113 			uport->mapbase	= dec_kn_slot_base +
1114 					  zs_parms.scc[chip] +
1115 					  (side ^ ZS_CHAN_B) * ZS_CHAN_IO_SIZE;
1116 
1117 			for (i = 0; i < ZS_NUM_REGS; i++)
1118 				zport->regs[i] = zs_init_regs[i];
1119 		}
1120 	}
1121 
1122 	return 0;
1123 }
1124 
1125 
1126 #ifdef CONFIG_SERIAL_ZS_CONSOLE
1127 static void zs_console_putchar(struct uart_port *uport, unsigned char ch)
1128 {
1129 	struct zs_port *zport = to_zport(uport);
1130 	struct zs_scc *scc = zport->scc;
1131 	int irq;
1132 	unsigned long flags;
1133 
1134 	spin_lock_irqsave(&scc->zlock, flags);
1135 	irq = !irqs_disabled_flags(flags);
1136 	if (zs_transmit_drain(zport, irq))
1137 		write_zsdata(zport, ch);
1138 	spin_unlock_irqrestore(&scc->zlock, flags);
1139 }
1140 
1141 /*
1142  * Print a string to the serial port trying not to disturb
1143  * any possible real use of the port...
1144  */
1145 static void zs_console_write(struct console *co, const char *s,
1146 			     unsigned int count)
1147 {
1148 	int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;
1149 	struct zs_port *zport = &zs_sccs[chip].zport[side];
1150 	struct zs_scc *scc = zport->scc;
1151 	unsigned long flags;
1152 	u8 txint, txenb;
1153 	int irq;
1154 
1155 	/* Disable transmit interrupts and enable the transmitter. */
1156 	spin_lock_irqsave(&scc->zlock, flags);
1157 	txint = zport->regs[1];
1158 	txenb = zport->regs[5];
1159 	if (txint & TxINT_ENAB) {
1160 		zport->regs[1] = txint & ~TxINT_ENAB;
1161 		write_zsreg(zport, R1, zport->regs[1]);
1162 	}
1163 	if (!(txenb & TxENAB)) {
1164 		zport->regs[5] = txenb | TxENAB;
1165 		write_zsreg(zport, R5, zport->regs[5]);
1166 	}
1167 	spin_unlock_irqrestore(&scc->zlock, flags);
1168 
1169 	uart_console_write(&zport->port, s, count, zs_console_putchar);
1170 
1171 	/* Restore transmit interrupts and the transmitter enable. */
1172 	spin_lock_irqsave(&scc->zlock, flags);
1173 	irq = !irqs_disabled_flags(flags);
1174 	zs_line_drain(zport, irq);
1175 	if (!(txenb & TxENAB)) {
1176 		zport->regs[5] &= ~TxENAB;
1177 		write_zsreg(zport, R5, zport->regs[5]);
1178 	}
1179 	if (txint & TxINT_ENAB) {
1180 		zport->regs[1] |= TxINT_ENAB;
1181 		write_zsreg(zport, R1, zport->regs[1]);
1182 
1183 		/* Resume any transmission as the TxIP bit won't be set.  */
1184 		if (!zport->tx_stopped)
1185 			zs_raw_transmit_chars(zport);
1186 	}
1187 	spin_unlock_irqrestore(&scc->zlock, flags);
1188 }
1189 
1190 /*
1191  * Setup serial console baud/bits/parity.  We do two things here:
1192  * - construct a cflag setting for the first uart_open()
1193  * - initialise the serial port
1194  * Return non-zero if we didn't find a serial port.
1195  */
1196 static int __init zs_console_setup(struct console *co, char *options)
1197 {
1198 	int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;
1199 	struct zs_port *zport = &zs_sccs[chip].zport[side];
1200 	struct uart_port *uport = &zport->port;
1201 	int baud = 9600;
1202 	int bits = 8;
1203 	int parity = 'n';
1204 	int flow = 'n';
1205 	int ret;
1206 
1207 	ret = zs_map_port(uport);
1208 	if (ret)
1209 		return ret;
1210 
1211 	zs_reset(zport);
1212 	zs_pm(uport, 0, -1);
1213 
1214 	if (options)
1215 		uart_parse_options(options, &baud, &parity, &bits, &flow);
1216 	return uart_set_options(uport, co, baud, parity, bits, flow);
1217 }
1218 
1219 static struct uart_driver zs_reg;
1220 static struct console zs_console = {
1221 	.name	= "ttyS",
1222 	.write	= zs_console_write,
1223 	.device	= uart_console_device,
1224 	.setup	= zs_console_setup,
1225 	.flags	= CON_PRINTBUFFER,
1226 	.index	= -1,
1227 	.data	= &zs_reg,
1228 };
1229 
1230 /*
1231  *	Register console.
1232  */
1233 static int __init zs_serial_console_init(void)
1234 {
1235 	int ret;
1236 
1237 	ret = zs_probe_sccs();
1238 	if (ret)
1239 		return ret;
1240 	register_console(&zs_console);
1241 
1242 	return 0;
1243 }
1244 
1245 console_initcall(zs_serial_console_init);
1246 
1247 #define SERIAL_ZS_CONSOLE	&zs_console
1248 #else
1249 #define SERIAL_ZS_CONSOLE	NULL
1250 #endif /* CONFIG_SERIAL_ZS_CONSOLE */
1251 
1252 static struct uart_driver zs_reg = {
1253 	.owner			= THIS_MODULE,
1254 	.driver_name		= "serial",
1255 	.dev_name		= "ttyS",
1256 	.major			= TTY_MAJOR,
1257 	.minor			= 64,
1258 	.nr			= ZS_NUM_SCCS * ZS_NUM_CHAN,
1259 	.cons			= SERIAL_ZS_CONSOLE,
1260 };
1261 
1262 /* zs_init inits the driver. */
1263 static int __init zs_init(void)
1264 {
1265 	int i, ret;
1266 
1267 	pr_info("%s%s\n", zs_name, zs_version);
1268 
1269 	/* Find out how many Z85C30 SCCs we have.  */
1270 	ret = zs_probe_sccs();
1271 	if (ret)
1272 		return ret;
1273 
1274 	ret = uart_register_driver(&zs_reg);
1275 	if (ret)
1276 		return ret;
1277 
1278 	for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {
1279 		struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];
1280 		struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];
1281 		struct uart_port *uport = &zport->port;
1282 
1283 		if (zport->scc)
1284 			uart_add_one_port(&zs_reg, uport);
1285 	}
1286 
1287 	return 0;
1288 }
1289 
1290 static void __exit zs_exit(void)
1291 {
1292 	int i;
1293 
1294 	for (i = ZS_NUM_SCCS * ZS_NUM_CHAN - 1; i >= 0; i--) {
1295 		struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];
1296 		struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];
1297 		struct uart_port *uport = &zport->port;
1298 
1299 		if (zport->scc)
1300 			uart_remove_one_port(&zs_reg, uport);
1301 	}
1302 
1303 	uart_unregister_driver(&zs_reg);
1304 }
1305 
1306 module_init(zs_init);
1307 module_exit(zs_exit);
1308