1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 #ifndef _PKEYS_X86_H
4 #define _PKEYS_X86_H
5
6 #ifdef __i386__
7
8 #define REG_IP_IDX REG_EIP
9 #define si_pkey_offset 0x14
10
11 #else
12
13 #define REG_IP_IDX REG_RIP
14 #define si_pkey_offset 0x20
15
16 #endif
17
18 #define MCONTEXT_IP(mc) mc.gregs[REG_IP_IDX]
19 #define MCONTEXT_TRAPNO(mc) mc.gregs[REG_TRAPNO]
20 #define MCONTEXT_FPREGS
21
22 #ifndef PKEY_DISABLE_ACCESS
23 # define PKEY_DISABLE_ACCESS 0x1
24 #endif
25
26 #ifndef PKEY_DISABLE_WRITE
27 # define PKEY_DISABLE_WRITE 0x2
28 #endif
29
30 #define NR_PKEYS 16
31 #define NR_RESERVED_PKEYS 2 /* pkey-0 and exec-only-pkey */
32 #define PKEY_BITS_PER_PKEY 2
33 #define HPAGE_SIZE (1UL<<21)
34 #define PAGE_SIZE 4096
35 #define MB (1<<20)
36
37 #define PKEY_REG_ALLOW_NONE 0x55555555
38
__page_o_noops(void)39 static inline void __page_o_noops(void)
40 {
41 /* 8-bytes of instruction * 512 bytes = 1 page */
42 asm(".rept 512 ; nopl 0x7eeeeeee(%eax) ; .endr");
43 }
44
__read_pkey_reg(void)45 static inline u64 __read_pkey_reg(void)
46 {
47 unsigned int eax, edx;
48 unsigned int ecx = 0;
49 unsigned pkey_reg;
50
51 asm volatile(".byte 0x0f,0x01,0xee\n\t"
52 : "=a" (eax), "=d" (edx)
53 : "c" (ecx));
54 pkey_reg = eax;
55 return pkey_reg;
56 }
57
__write_pkey_reg(u64 pkey_reg)58 static inline void __write_pkey_reg(u64 pkey_reg)
59 {
60 unsigned int eax = pkey_reg;
61 unsigned int ecx = 0;
62 unsigned int edx = 0;
63
64 dprintf4("%s() changing %016llx to %016llx\n", __func__,
65 __read_pkey_reg(), pkey_reg);
66 asm volatile(".byte 0x0f,0x01,0xef\n\t"
67 : : "a" (eax), "c" (ecx), "d" (edx));
68 assert(pkey_reg == __read_pkey_reg());
69 }
70
71 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx) */
72 #define X86_FEATURE_PKU (1<<3) /* Protection Keys for Userspace */
73 #define X86_FEATURE_OSPKE (1<<4) /* OS Protection Keys Enable */
74
cpu_has_pkeys(void)75 static inline int cpu_has_pkeys(void)
76 {
77 unsigned int eax;
78 unsigned int ebx;
79 unsigned int ecx;
80 unsigned int edx;
81
82 __cpuid_count(0x7, 0x0, eax, ebx, ecx, edx);
83
84 if (!(ecx & X86_FEATURE_PKU)) {
85 dprintf2("cpu does not have PKU\n");
86 return 0;
87 }
88 if (!(ecx & X86_FEATURE_OSPKE)) {
89 dprintf2("cpu does not have OSPKE\n");
90 return 0;
91 }
92 return 1;
93 }
94
cpu_max_xsave_size(void)95 static inline int cpu_max_xsave_size(void)
96 {
97 unsigned long XSTATE_CPUID = 0xd;
98 unsigned int eax;
99 unsigned int ebx;
100 unsigned int ecx;
101 unsigned int edx;
102
103 __cpuid_count(XSTATE_CPUID, 0, eax, ebx, ecx, edx);
104 return ecx;
105 }
106
pkey_bit_position(int pkey)107 static inline u32 pkey_bit_position(int pkey)
108 {
109 return pkey * PKEY_BITS_PER_PKEY;
110 }
111
112 #define XSTATE_PKEY_BIT (9)
113 #define XSTATE_PKEY 0x200
114 #define XSTATE_BV_OFFSET 512
115
pkey_reg_xstate_offset(void)116 int pkey_reg_xstate_offset(void)
117 {
118 unsigned int eax;
119 unsigned int ebx;
120 unsigned int ecx;
121 unsigned int edx;
122 int xstate_offset;
123 int xstate_size = 0;
124 unsigned long XSTATE_CPUID = 0xd;
125 int leaf;
126
127 /* assume that XSTATE_PKEY is set in XCR0 */
128 leaf = XSTATE_PKEY_BIT;
129 {
130 __cpuid_count(XSTATE_CPUID, leaf, eax, ebx, ecx, edx);
131
132 if (leaf == XSTATE_PKEY_BIT) {
133 xstate_offset = ebx;
134 xstate_size = eax;
135 }
136 }
137
138 if (xstate_size == 0) {
139 printf("could not find size/offset of PKEY in xsave state\n");
140 return 0;
141 }
142
143 return xstate_offset;
144 }
145
get_arch_reserved_keys(void)146 static inline int get_arch_reserved_keys(void)
147 {
148 return NR_RESERVED_PKEYS;
149 }
150
expect_fault_on_read_execonly_key(void * p1,int pkey)151 void expect_fault_on_read_execonly_key(void *p1, int pkey)
152 {
153 int ptr_contents;
154
155 ptr_contents = read_ptr(p1);
156 dprintf2("ptr (%p) contents@%d: %x\n", p1, __LINE__, ptr_contents);
157 expected_pkey_fault(pkey);
158 }
159
malloc_pkey_with_mprotect_subpage(long size,int prot,u16 pkey)160 void *malloc_pkey_with_mprotect_subpage(long size, int prot, u16 pkey)
161 {
162 return PTR_ERR_ENOTSUP;
163 }
164
165 #endif /* _PKEYS_X86_H */
166