1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc. 4 * Copyright (c) 2014, Synopsys, Inc. 5 * All rights reserved 6 */ 7 8 #ifndef __XGBE_COMMON_H__ 9 #define __XGBE_COMMON_H__ 10 11 /* DMA register offsets */ 12 #define DMA_MR 0x3000 13 #define DMA_SBMR 0x3004 14 #define DMA_ISR 0x3008 15 #define DMA_AXIARCR 0x3010 16 #define DMA_AXIAWCR 0x3018 17 #define DMA_AXIAWARCR 0x301c 18 #define DMA_DSR0 0x3020 19 #define DMA_DSR1 0x3024 20 #define DMA_TXEDMACR 0x3040 21 #define DMA_RXEDMACR 0x3044 22 23 /* DMA register entry bit positions and sizes */ 24 #define DMA_ISR_MACIS_INDEX 17 25 #define DMA_ISR_MACIS_WIDTH 1 26 #define DMA_ISR_MTLIS_INDEX 16 27 #define DMA_ISR_MTLIS_WIDTH 1 28 #define DMA_MR_INTM_INDEX 12 29 #define DMA_MR_INTM_WIDTH 2 30 #define DMA_MR_SWR_INDEX 0 31 #define DMA_MR_SWR_WIDTH 1 32 #define DMA_RXEDMACR_RDPS_INDEX 0 33 #define DMA_RXEDMACR_RDPS_WIDTH 3 34 #define DMA_SBMR_AAL_INDEX 12 35 #define DMA_SBMR_AAL_WIDTH 1 36 #define DMA_SBMR_EAME_INDEX 11 37 #define DMA_SBMR_EAME_WIDTH 1 38 #define DMA_SBMR_BLEN_INDEX 1 39 #define DMA_SBMR_BLEN_WIDTH 7 40 #define DMA_SBMR_RD_OSR_LMT_INDEX 16 41 #define DMA_SBMR_RD_OSR_LMT_WIDTH 6 42 #define DMA_SBMR_UNDEF_INDEX 0 43 #define DMA_SBMR_UNDEF_WIDTH 1 44 #define DMA_SBMR_WR_OSR_LMT_INDEX 24 45 #define DMA_SBMR_WR_OSR_LMT_WIDTH 6 46 #define DMA_TXEDMACR_TDPS_INDEX 0 47 #define DMA_TXEDMACR_TDPS_WIDTH 3 48 49 /* DMA register values */ 50 #define DMA_SBMR_BLEN_256 256 51 #define DMA_SBMR_BLEN_128 128 52 #define DMA_SBMR_BLEN_64 64 53 #define DMA_SBMR_BLEN_32 32 54 #define DMA_SBMR_BLEN_16 16 55 #define DMA_SBMR_BLEN_8 8 56 #define DMA_SBMR_BLEN_4 4 57 #define DMA_DSR_RPS_WIDTH 4 58 #define DMA_DSR_TPS_WIDTH 4 59 #define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH) 60 #define DMA_DSR0_RPS_START 8 61 #define DMA_DSR0_TPS_START 12 62 #define DMA_DSRX_FIRST_QUEUE 3 63 #define DMA_DSRX_INC 4 64 #define DMA_DSRX_QPR 4 65 #define DMA_DSRX_RPS_START 0 66 #define DMA_DSRX_TPS_START 4 67 #define DMA_TPS_STOPPED 0x00 68 #define DMA_TPS_SUSPENDED 0x06 69 70 /* DMA channel register offsets 71 * Multiple channels can be active. The first channel has registers 72 * that begin at 0x3100. Each subsequent channel has registers that 73 * are accessed using an offset of 0x80 from the previous channel. 74 */ 75 #define DMA_CH_BASE 0x3100 76 #define DMA_CH_INC 0x80 77 78 #define DMA_CH_CR 0x00 79 #define DMA_CH_TCR 0x04 80 #define DMA_CH_RCR 0x08 81 #define DMA_CH_TDLR_HI 0x10 82 #define DMA_CH_TDLR_LO 0x14 83 #define DMA_CH_RDLR_HI 0x18 84 #define DMA_CH_RDLR_LO 0x1c 85 #define DMA_CH_TDTR_LO 0x24 86 #define DMA_CH_RDTR_LO 0x2c 87 #define DMA_CH_TDRLR 0x30 88 #define DMA_CH_RDRLR 0x34 89 #define DMA_CH_IER 0x38 90 #define DMA_CH_RIWT 0x3c 91 #define DMA_CH_CATDR_LO 0x44 92 #define DMA_CH_CARDR_LO 0x4c 93 #define DMA_CH_CATBR_HI 0x50 94 #define DMA_CH_CATBR_LO 0x54 95 #define DMA_CH_CARBR_HI 0x58 96 #define DMA_CH_CARBR_LO 0x5c 97 #define DMA_CH_SR 0x60 98 99 /* DMA channel register entry bit positions and sizes */ 100 #define DMA_CH_CR_PBLX8_INDEX 16 101 #define DMA_CH_CR_PBLX8_WIDTH 1 102 #define DMA_CH_CR_SPH_INDEX 24 103 #define DMA_CH_CR_SPH_WIDTH 1 104 #define DMA_CH_IER_AIE20_INDEX 15 105 #define DMA_CH_IER_AIE20_WIDTH 1 106 #define DMA_CH_IER_AIE_INDEX 14 107 #define DMA_CH_IER_AIE_WIDTH 1 108 #define DMA_CH_IER_FBEE_INDEX 12 109 #define DMA_CH_IER_FBEE_WIDTH 1 110 #define DMA_CH_IER_NIE20_INDEX 16 111 #define DMA_CH_IER_NIE20_WIDTH 1 112 #define DMA_CH_IER_NIE_INDEX 15 113 #define DMA_CH_IER_NIE_WIDTH 1 114 #define DMA_CH_IER_RBUE_INDEX 7 115 #define DMA_CH_IER_RBUE_WIDTH 1 116 #define DMA_CH_IER_RIE_INDEX 6 117 #define DMA_CH_IER_RIE_WIDTH 1 118 #define DMA_CH_IER_RSE_INDEX 8 119 #define DMA_CH_IER_RSE_WIDTH 1 120 #define DMA_CH_IER_TBUE_INDEX 2 121 #define DMA_CH_IER_TBUE_WIDTH 1 122 #define DMA_CH_IER_TIE_INDEX 0 123 #define DMA_CH_IER_TIE_WIDTH 1 124 #define DMA_CH_IER_TXSE_INDEX 1 125 #define DMA_CH_IER_TXSE_WIDTH 1 126 #define DMA_CH_RCR_PBL_INDEX 16 127 #define DMA_CH_RCR_PBL_WIDTH 6 128 #define DMA_CH_RCR_RBSZ_INDEX 1 129 #define DMA_CH_RCR_RBSZ_WIDTH 14 130 #define DMA_CH_RCR_SR_INDEX 0 131 #define DMA_CH_RCR_SR_WIDTH 1 132 #define DMA_CH_RIWT_RWT_INDEX 0 133 #define DMA_CH_RIWT_RWT_WIDTH 8 134 #define DMA_CH_SR_FBE_INDEX 12 135 #define DMA_CH_SR_FBE_WIDTH 1 136 #define DMA_CH_SR_RBU_INDEX 7 137 #define DMA_CH_SR_RBU_WIDTH 1 138 #define DMA_CH_SR_RI_INDEX 6 139 #define DMA_CH_SR_RI_WIDTH 1 140 #define DMA_CH_SR_RPS_INDEX 8 141 #define DMA_CH_SR_RPS_WIDTH 1 142 #define DMA_CH_SR_TBU_INDEX 2 143 #define DMA_CH_SR_TBU_WIDTH 1 144 #define DMA_CH_SR_TI_INDEX 0 145 #define DMA_CH_SR_TI_WIDTH 1 146 #define DMA_CH_SR_TPS_INDEX 1 147 #define DMA_CH_SR_TPS_WIDTH 1 148 #define DMA_CH_TCR_OSP_INDEX 4 149 #define DMA_CH_TCR_OSP_WIDTH 1 150 #define DMA_CH_TCR_PBL_INDEX 16 151 #define DMA_CH_TCR_PBL_WIDTH 6 152 #define DMA_CH_TCR_ST_INDEX 0 153 #define DMA_CH_TCR_ST_WIDTH 1 154 #define DMA_CH_TCR_TSE_INDEX 12 155 #define DMA_CH_TCR_TSE_WIDTH 1 156 157 /* DMA channel register values */ 158 #define DMA_OSP_DISABLE 0x00 159 #define DMA_OSP_ENABLE 0x01 160 #define DMA_PBL_1 1 161 #define DMA_PBL_2 2 162 #define DMA_PBL_4 4 163 #define DMA_PBL_8 8 164 #define DMA_PBL_16 16 165 #define DMA_PBL_32 32 166 #define DMA_PBL_64 64 /* 8 x 8 */ 167 #define DMA_PBL_128 128 /* 8 x 16 */ 168 #define DMA_PBL_256 256 /* 8 x 32 */ 169 #define DMA_PBL_X8_DISABLE 0x00 170 #define DMA_PBL_X8_ENABLE 0x01 171 172 /* MAC register offsets */ 173 #define MAC_TCR 0x0000 174 #define MAC_RCR 0x0004 175 #define MAC_PFR 0x0008 176 #define MAC_WTR 0x000c 177 #define MAC_HTR0 0x0010 178 #define MAC_VLANTR 0x0050 179 #define MAC_VLANHTR 0x0058 180 #define MAC_VLANIR 0x0060 181 #define MAC_IVLANIR 0x0064 182 #define MAC_RETMR 0x006c 183 #define MAC_Q0TFCR 0x0070 184 #define MAC_RFCR 0x0090 185 #define MAC_RQC0R 0x00a0 186 #define MAC_RQC1R 0x00a4 187 #define MAC_RQC2R 0x00a8 188 #define MAC_RQC3R 0x00ac 189 #define MAC_ISR 0x00b0 190 #define MAC_IER 0x00b4 191 #define MAC_RTSR 0x00b8 192 #define MAC_PMTCSR 0x00c0 193 #define MAC_RWKPFR 0x00c4 194 #define MAC_LPICSR 0x00d0 195 #define MAC_LPITCR 0x00d4 196 #define MAC_TIR 0x00e0 197 #define MAC_VR 0x0110 198 #define MAC_DR 0x0114 199 #define MAC_HWF0R 0x011c 200 #define MAC_HWF1R 0x0120 201 #define MAC_HWF2R 0x0124 202 #define MAC_MDIOSCAR 0x0200 203 #define MAC_MDIOSCCDR 0x0204 204 #define MAC_MDIOISR 0x0214 205 #define MAC_MDIOIER 0x0218 206 #define MAC_MDIOCL22R 0x0220 207 #define MAC_GPIOCR 0x0278 208 #define MAC_GPIOSR 0x027c 209 #define MAC_MACA0HR 0x0300 210 #define MAC_MACA0LR 0x0304 211 #define MAC_MACA1HR 0x0308 212 #define MAC_MACA1LR 0x030c 213 #define MAC_RSSCR 0x0c80 214 #define MAC_RSSAR 0x0c88 215 #define MAC_RSSDR 0x0c8c 216 #define MAC_TSCR 0x0d00 217 #define MAC_SSIR 0x0d04 218 #define MAC_STSR 0x0d08 219 #define MAC_STNR 0x0d0c 220 #define MAC_STSUR 0x0d10 221 #define MAC_STNUR 0x0d14 222 #define MAC_TSAR 0x0d18 223 #define MAC_TSSR 0x0d20 224 #define MAC_TXSNR 0x0d30 225 #define MAC_TXSSR 0x0d34 226 227 #define MAC_QTFCR_INC 4 228 #define MAC_MACA_INC 4 229 #define MAC_HTR_INC 4 230 231 #define MAC_RQC2_INC 4 232 #define MAC_RQC2_Q_PER_REG 4 233 234 /* MAC register entry bit positions and sizes */ 235 #define MAC_HWF0R_ADDMACADRSEL_INDEX 18 236 #define MAC_HWF0R_ADDMACADRSEL_WIDTH 5 237 #define MAC_HWF0R_ARPOFFSEL_INDEX 9 238 #define MAC_HWF0R_ARPOFFSEL_WIDTH 1 239 #define MAC_HWF0R_EEESEL_INDEX 13 240 #define MAC_HWF0R_EEESEL_WIDTH 1 241 #define MAC_HWF0R_GMIISEL_INDEX 1 242 #define MAC_HWF0R_GMIISEL_WIDTH 1 243 #define MAC_HWF0R_MGKSEL_INDEX 7 244 #define MAC_HWF0R_MGKSEL_WIDTH 1 245 #define MAC_HWF0R_MMCSEL_INDEX 8 246 #define MAC_HWF0R_MMCSEL_WIDTH 1 247 #define MAC_HWF0R_RWKSEL_INDEX 6 248 #define MAC_HWF0R_RWKSEL_WIDTH 1 249 #define MAC_HWF0R_RXCOESEL_INDEX 16 250 #define MAC_HWF0R_RXCOESEL_WIDTH 1 251 #define MAC_HWF0R_SAVLANINS_INDEX 27 252 #define MAC_HWF0R_SAVLANINS_WIDTH 1 253 #define MAC_HWF0R_SMASEL_INDEX 5 254 #define MAC_HWF0R_SMASEL_WIDTH 1 255 #define MAC_HWF0R_TSSEL_INDEX 12 256 #define MAC_HWF0R_TSSEL_WIDTH 1 257 #define MAC_HWF0R_TSSTSSEL_INDEX 25 258 #define MAC_HWF0R_TSSTSSEL_WIDTH 2 259 #define MAC_HWF0R_TXCOESEL_INDEX 14 260 #define MAC_HWF0R_TXCOESEL_WIDTH 1 261 #define MAC_HWF0R_VLHASH_INDEX 4 262 #define MAC_HWF0R_VLHASH_WIDTH 1 263 #define MAC_HWF0R_VXN_INDEX 29 264 #define MAC_HWF0R_VXN_WIDTH 1 265 #define MAC_HWF1R_ADDR64_INDEX 14 266 #define MAC_HWF1R_ADDR64_WIDTH 2 267 #define MAC_HWF1R_ADVTHWORD_INDEX 13 268 #define MAC_HWF1R_ADVTHWORD_WIDTH 1 269 #define MAC_HWF1R_DBGMEMA_INDEX 19 270 #define MAC_HWF1R_DBGMEMA_WIDTH 1 271 #define MAC_HWF1R_DCBEN_INDEX 16 272 #define MAC_HWF1R_DCBEN_WIDTH 1 273 #define MAC_HWF1R_HASHTBLSZ_INDEX 24 274 #define MAC_HWF1R_HASHTBLSZ_WIDTH 3 275 #define MAC_HWF1R_L3L4FNUM_INDEX 27 276 #define MAC_HWF1R_L3L4FNUM_WIDTH 4 277 #define MAC_HWF1R_NUMTC_INDEX 21 278 #define MAC_HWF1R_NUMTC_WIDTH 3 279 #define MAC_HWF1R_RSSEN_INDEX 20 280 #define MAC_HWF1R_RSSEN_WIDTH 1 281 #define MAC_HWF1R_RXFIFOSIZE_INDEX 0 282 #define MAC_HWF1R_RXFIFOSIZE_WIDTH 5 283 #define MAC_HWF1R_SPHEN_INDEX 17 284 #define MAC_HWF1R_SPHEN_WIDTH 1 285 #define MAC_HWF1R_TSOEN_INDEX 18 286 #define MAC_HWF1R_TSOEN_WIDTH 1 287 #define MAC_HWF1R_TXFIFOSIZE_INDEX 6 288 #define MAC_HWF1R_TXFIFOSIZE_WIDTH 5 289 #define MAC_HWF2R_AUXSNAPNUM_INDEX 28 290 #define MAC_HWF2R_AUXSNAPNUM_WIDTH 3 291 #define MAC_HWF2R_PPSOUTNUM_INDEX 24 292 #define MAC_HWF2R_PPSOUTNUM_WIDTH 3 293 #define MAC_HWF2R_RXCHCNT_INDEX 12 294 #define MAC_HWF2R_RXCHCNT_WIDTH 4 295 #define MAC_HWF2R_RXQCNT_INDEX 0 296 #define MAC_HWF2R_RXQCNT_WIDTH 4 297 #define MAC_HWF2R_TXCHCNT_INDEX 18 298 #define MAC_HWF2R_TXCHCNT_WIDTH 4 299 #define MAC_HWF2R_TXQCNT_INDEX 6 300 #define MAC_HWF2R_TXQCNT_WIDTH 4 301 #define MAC_IER_TSIE_INDEX 12 302 #define MAC_IER_TSIE_WIDTH 1 303 #define MAC_ISR_MMCRXIS_INDEX 9 304 #define MAC_ISR_MMCRXIS_WIDTH 1 305 #define MAC_ISR_MMCTXIS_INDEX 10 306 #define MAC_ISR_MMCTXIS_WIDTH 1 307 #define MAC_ISR_PMTIS_INDEX 4 308 #define MAC_ISR_PMTIS_WIDTH 1 309 #define MAC_ISR_SMI_INDEX 1 310 #define MAC_ISR_SMI_WIDTH 1 311 #define MAC_ISR_TSIS_INDEX 12 312 #define MAC_ISR_TSIS_WIDTH 1 313 #define MAC_MACA1HR_AE_INDEX 31 314 #define MAC_MACA1HR_AE_WIDTH 1 315 #define MAC_MDIOIER_SNGLCOMPIE_INDEX 12 316 #define MAC_MDIOIER_SNGLCOMPIE_WIDTH 1 317 #define MAC_MDIOISR_SNGLCOMPINT_INDEX 12 318 #define MAC_MDIOISR_SNGLCOMPINT_WIDTH 1 319 #define MAC_MDIOSCAR_DA_INDEX 21 320 #define MAC_MDIOSCAR_DA_WIDTH 5 321 #define MAC_MDIOSCAR_PA_INDEX 16 322 #define MAC_MDIOSCAR_PA_WIDTH 5 323 #define MAC_MDIOSCAR_RA_INDEX 0 324 #define MAC_MDIOSCAR_RA_WIDTH 16 325 #define MAC_MDIOSCCDR_BUSY_INDEX 22 326 #define MAC_MDIOSCCDR_BUSY_WIDTH 1 327 #define MAC_MDIOSCCDR_CMD_INDEX 16 328 #define MAC_MDIOSCCDR_CMD_WIDTH 2 329 #define MAC_MDIOSCCDR_CR_INDEX 19 330 #define MAC_MDIOSCCDR_CR_WIDTH 3 331 #define MAC_MDIOSCCDR_DATA_INDEX 0 332 #define MAC_MDIOSCCDR_DATA_WIDTH 16 333 #define MAC_MDIOSCCDR_SADDR_INDEX 18 334 #define MAC_MDIOSCCDR_SADDR_WIDTH 1 335 #define MAC_PFR_HMC_INDEX 2 336 #define MAC_PFR_HMC_WIDTH 1 337 #define MAC_PFR_HPF_INDEX 10 338 #define MAC_PFR_HPF_WIDTH 1 339 #define MAC_PFR_HUC_INDEX 1 340 #define MAC_PFR_HUC_WIDTH 1 341 #define MAC_PFR_PM_INDEX 4 342 #define MAC_PFR_PM_WIDTH 1 343 #define MAC_PFR_PR_INDEX 0 344 #define MAC_PFR_PR_WIDTH 1 345 #define MAC_PFR_VTFE_INDEX 16 346 #define MAC_PFR_VTFE_WIDTH 1 347 #define MAC_PFR_VUCC_INDEX 22 348 #define MAC_PFR_VUCC_WIDTH 1 349 #define MAC_PMTCSR_MGKPKTEN_INDEX 1 350 #define MAC_PMTCSR_MGKPKTEN_WIDTH 1 351 #define MAC_PMTCSR_PWRDWN_INDEX 0 352 #define MAC_PMTCSR_PWRDWN_WIDTH 1 353 #define MAC_PMTCSR_RWKFILTRST_INDEX 31 354 #define MAC_PMTCSR_RWKFILTRST_WIDTH 1 355 #define MAC_PMTCSR_RWKPKTEN_INDEX 2 356 #define MAC_PMTCSR_RWKPKTEN_WIDTH 1 357 #define MAC_Q0TFCR_PT_INDEX 16 358 #define MAC_Q0TFCR_PT_WIDTH 16 359 #define MAC_Q0TFCR_TFE_INDEX 1 360 #define MAC_Q0TFCR_TFE_WIDTH 1 361 #define MAC_RCR_ACS_INDEX 1 362 #define MAC_RCR_ACS_WIDTH 1 363 #define MAC_RCR_CST_INDEX 2 364 #define MAC_RCR_CST_WIDTH 1 365 #define MAC_RCR_DCRCC_INDEX 3 366 #define MAC_RCR_DCRCC_WIDTH 1 367 #define MAC_RCR_HDSMS_INDEX 12 368 #define MAC_RCR_HDSMS_WIDTH 3 369 #define MAC_RCR_IPC_INDEX 9 370 #define MAC_RCR_IPC_WIDTH 1 371 #define MAC_RCR_JE_INDEX 8 372 #define MAC_RCR_JE_WIDTH 1 373 #define MAC_RCR_LM_INDEX 10 374 #define MAC_RCR_LM_WIDTH 1 375 #define MAC_RCR_RE_INDEX 0 376 #define MAC_RCR_RE_WIDTH 1 377 #define MAC_RFCR_PFCE_INDEX 8 378 #define MAC_RFCR_PFCE_WIDTH 1 379 #define MAC_RFCR_RFE_INDEX 0 380 #define MAC_RFCR_RFE_WIDTH 1 381 #define MAC_RFCR_UP_INDEX 1 382 #define MAC_RFCR_UP_WIDTH 1 383 #define MAC_RQC0R_RXQ0EN_INDEX 0 384 #define MAC_RQC0R_RXQ0EN_WIDTH 2 385 #define MAC_RSSAR_ADDRT_INDEX 2 386 #define MAC_RSSAR_ADDRT_WIDTH 1 387 #define MAC_RSSAR_CT_INDEX 1 388 #define MAC_RSSAR_CT_WIDTH 1 389 #define MAC_RSSAR_OB_INDEX 0 390 #define MAC_RSSAR_OB_WIDTH 1 391 #define MAC_RSSAR_RSSIA_INDEX 8 392 #define MAC_RSSAR_RSSIA_WIDTH 8 393 #define MAC_RSSCR_IP2TE_INDEX 1 394 #define MAC_RSSCR_IP2TE_WIDTH 1 395 #define MAC_RSSCR_RSSE_INDEX 0 396 #define MAC_RSSCR_RSSE_WIDTH 1 397 #define MAC_RSSCR_TCP4TE_INDEX 2 398 #define MAC_RSSCR_TCP4TE_WIDTH 1 399 #define MAC_RSSCR_UDP4TE_INDEX 3 400 #define MAC_RSSCR_UDP4TE_WIDTH 1 401 #define MAC_RSSDR_DMCH_INDEX 0 402 #define MAC_RSSDR_DMCH_WIDTH 4 403 #define MAC_SSIR_SNSINC_INDEX 8 404 #define MAC_SSIR_SNSINC_WIDTH 8 405 #define MAC_SSIR_SSINC_INDEX 16 406 #define MAC_SSIR_SSINC_WIDTH 8 407 #define MAC_TCR_SS_INDEX 29 408 #define MAC_TCR_SS_WIDTH 2 409 #define MAC_TCR_TE_INDEX 0 410 #define MAC_TCR_TE_WIDTH 1 411 #define MAC_TCR_VNE_INDEX 24 412 #define MAC_TCR_VNE_WIDTH 1 413 #define MAC_TCR_VNM_INDEX 25 414 #define MAC_TCR_VNM_WIDTH 1 415 #define MAC_TIR_TNID_INDEX 0 416 #define MAC_TIR_TNID_WIDTH 16 417 #define MAC_TSCR_AV8021ASMEN_INDEX 28 418 #define MAC_TSCR_AV8021ASMEN_WIDTH 1 419 #define MAC_TSCR_SNAPTYPSEL_INDEX 16 420 #define MAC_TSCR_SNAPTYPSEL_WIDTH 2 421 #define MAC_TSCR_TSADDREG_INDEX 5 422 #define MAC_TSCR_TSADDREG_WIDTH 1 423 #define MAC_TSCR_TSCFUPDT_INDEX 1 424 #define MAC_TSCR_TSCFUPDT_WIDTH 1 425 #define MAC_TSCR_TSCTRLSSR_INDEX 9 426 #define MAC_TSCR_TSCTRLSSR_WIDTH 1 427 #define MAC_TSCR_TSENA_INDEX 0 428 #define MAC_TSCR_TSENA_WIDTH 1 429 #define MAC_TSCR_TSENALL_INDEX 8 430 #define MAC_TSCR_TSENALL_WIDTH 1 431 #define MAC_TSCR_TSEVNTENA_INDEX 14 432 #define MAC_TSCR_TSEVNTENA_WIDTH 1 433 #define MAC_TSCR_TSINIT_INDEX 2 434 #define MAC_TSCR_TSINIT_WIDTH 1 435 #define MAC_TSCR_TSIPENA_INDEX 11 436 #define MAC_TSCR_TSIPENA_WIDTH 1 437 #define MAC_TSCR_TSIPV4ENA_INDEX 13 438 #define MAC_TSCR_TSIPV4ENA_WIDTH 1 439 #define MAC_TSCR_TSIPV6ENA_INDEX 12 440 #define MAC_TSCR_TSIPV6ENA_WIDTH 1 441 #define MAC_TSCR_TSMSTRENA_INDEX 15 442 #define MAC_TSCR_TSMSTRENA_WIDTH 1 443 #define MAC_TSCR_TSVER2ENA_INDEX 10 444 #define MAC_TSCR_TSVER2ENA_WIDTH 1 445 #define MAC_TSCR_TXTSSTSM_INDEX 24 446 #define MAC_TSCR_TXTSSTSM_WIDTH 1 447 #define MAC_TSSR_TXTSC_INDEX 15 448 #define MAC_TSSR_TXTSC_WIDTH 1 449 #define MAC_TXSNR_TXTSSTSMIS_INDEX 31 450 #define MAC_TXSNR_TXTSSTSMIS_WIDTH 1 451 #define MAC_VLANHTR_VLHT_INDEX 0 452 #define MAC_VLANHTR_VLHT_WIDTH 16 453 #define MAC_VLANIR_VLTI_INDEX 20 454 #define MAC_VLANIR_VLTI_WIDTH 1 455 #define MAC_VLANIR_CSVL_INDEX 19 456 #define MAC_VLANIR_CSVL_WIDTH 1 457 #define MAC_VLANTR_DOVLTC_INDEX 20 458 #define MAC_VLANTR_DOVLTC_WIDTH 1 459 #define MAC_VLANTR_ERSVLM_INDEX 19 460 #define MAC_VLANTR_ERSVLM_WIDTH 1 461 #define MAC_VLANTR_ESVL_INDEX 18 462 #define MAC_VLANTR_ESVL_WIDTH 1 463 #define MAC_VLANTR_ETV_INDEX 16 464 #define MAC_VLANTR_ETV_WIDTH 1 465 #define MAC_VLANTR_EVLS_INDEX 21 466 #define MAC_VLANTR_EVLS_WIDTH 2 467 #define MAC_VLANTR_EVLRXS_INDEX 24 468 #define MAC_VLANTR_EVLRXS_WIDTH 1 469 #define MAC_VLANTR_VL_INDEX 0 470 #define MAC_VLANTR_VL_WIDTH 16 471 #define MAC_VLANTR_VTHM_INDEX 25 472 #define MAC_VLANTR_VTHM_WIDTH 1 473 #define MAC_VLANTR_VTIM_INDEX 17 474 #define MAC_VLANTR_VTIM_WIDTH 1 475 #define MAC_VR_DEVID_INDEX 8 476 #define MAC_VR_DEVID_WIDTH 8 477 #define MAC_VR_SNPSVER_INDEX 0 478 #define MAC_VR_SNPSVER_WIDTH 8 479 #define MAC_VR_USERVER_INDEX 16 480 #define MAC_VR_USERVER_WIDTH 8 481 482 /* MMC register offsets */ 483 #define MMC_CR 0x0800 484 #define MMC_RISR 0x0804 485 #define MMC_TISR 0x0808 486 #define MMC_RIER 0x080c 487 #define MMC_TIER 0x0810 488 #define MMC_TXOCTETCOUNT_GB_LO 0x0814 489 #define MMC_TXOCTETCOUNT_GB_HI 0x0818 490 #define MMC_TXFRAMECOUNT_GB_LO 0x081c 491 #define MMC_TXFRAMECOUNT_GB_HI 0x0820 492 #define MMC_TXBROADCASTFRAMES_G_LO 0x0824 493 #define MMC_TXBROADCASTFRAMES_G_HI 0x0828 494 #define MMC_TXMULTICASTFRAMES_G_LO 0x082c 495 #define MMC_TXMULTICASTFRAMES_G_HI 0x0830 496 #define MMC_TX64OCTETS_GB_LO 0x0834 497 #define MMC_TX64OCTETS_GB_HI 0x0838 498 #define MMC_TX65TO127OCTETS_GB_LO 0x083c 499 #define MMC_TX65TO127OCTETS_GB_HI 0x0840 500 #define MMC_TX128TO255OCTETS_GB_LO 0x0844 501 #define MMC_TX128TO255OCTETS_GB_HI 0x0848 502 #define MMC_TX256TO511OCTETS_GB_LO 0x084c 503 #define MMC_TX256TO511OCTETS_GB_HI 0x0850 504 #define MMC_TX512TO1023OCTETS_GB_LO 0x0854 505 #define MMC_TX512TO1023OCTETS_GB_HI 0x0858 506 #define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c 507 #define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860 508 #define MMC_TXUNICASTFRAMES_GB_LO 0x0864 509 #define MMC_TXUNICASTFRAMES_GB_HI 0x0868 510 #define MMC_TXMULTICASTFRAMES_GB_LO 0x086c 511 #define MMC_TXMULTICASTFRAMES_GB_HI 0x0870 512 #define MMC_TXBROADCASTFRAMES_GB_LO 0x0874 513 #define MMC_TXBROADCASTFRAMES_GB_HI 0x0878 514 #define MMC_TXUNDERFLOWERROR_LO 0x087c 515 #define MMC_TXUNDERFLOWERROR_HI 0x0880 516 #define MMC_TXOCTETCOUNT_G_LO 0x0884 517 #define MMC_TXOCTETCOUNT_G_HI 0x0888 518 #define MMC_TXFRAMECOUNT_G_LO 0x088c 519 #define MMC_TXFRAMECOUNT_G_HI 0x0890 520 #define MMC_TXPAUSEFRAMES_LO 0x0894 521 #define MMC_TXPAUSEFRAMES_HI 0x0898 522 #define MMC_TXVLANFRAMES_G_LO 0x089c 523 #define MMC_TXVLANFRAMES_G_HI 0x08a0 524 #define MMC_RXFRAMECOUNT_GB_LO 0x0900 525 #define MMC_RXFRAMECOUNT_GB_HI 0x0904 526 #define MMC_RXOCTETCOUNT_GB_LO 0x0908 527 #define MMC_RXOCTETCOUNT_GB_HI 0x090c 528 #define MMC_RXOCTETCOUNT_G_LO 0x0910 529 #define MMC_RXOCTETCOUNT_G_HI 0x0914 530 #define MMC_RXBROADCASTFRAMES_G_LO 0x0918 531 #define MMC_RXBROADCASTFRAMES_G_HI 0x091c 532 #define MMC_RXMULTICASTFRAMES_G_LO 0x0920 533 #define MMC_RXMULTICASTFRAMES_G_HI 0x0924 534 #define MMC_RXCRCERROR_LO 0x0928 535 #define MMC_RXCRCERROR_HI 0x092c 536 #define MMC_RXRUNTERROR 0x0930 537 #define MMC_RXJABBERERROR 0x0934 538 #define MMC_RXUNDERSIZE_G 0x0938 539 #define MMC_RXOVERSIZE_G 0x093c 540 #define MMC_RX64OCTETS_GB_LO 0x0940 541 #define MMC_RX64OCTETS_GB_HI 0x0944 542 #define MMC_RX65TO127OCTETS_GB_LO 0x0948 543 #define MMC_RX65TO127OCTETS_GB_HI 0x094c 544 #define MMC_RX128TO255OCTETS_GB_LO 0x0950 545 #define MMC_RX128TO255OCTETS_GB_HI 0x0954 546 #define MMC_RX256TO511OCTETS_GB_LO 0x0958 547 #define MMC_RX256TO511OCTETS_GB_HI 0x095c 548 #define MMC_RX512TO1023OCTETS_GB_LO 0x0960 549 #define MMC_RX512TO1023OCTETS_GB_HI 0x0964 550 #define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968 551 #define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c 552 #define MMC_RXUNICASTFRAMES_G_LO 0x0970 553 #define MMC_RXUNICASTFRAMES_G_HI 0x0974 554 #define MMC_RXLENGTHERROR_LO 0x0978 555 #define MMC_RXLENGTHERROR_HI 0x097c 556 #define MMC_RXOUTOFRANGETYPE_LO 0x0980 557 #define MMC_RXOUTOFRANGETYPE_HI 0x0984 558 #define MMC_RXPAUSEFRAMES_LO 0x0988 559 #define MMC_RXPAUSEFRAMES_HI 0x098c 560 #define MMC_RXFIFOOVERFLOW_LO 0x0990 561 #define MMC_RXFIFOOVERFLOW_HI 0x0994 562 #define MMC_RXVLANFRAMES_GB_LO 0x0998 563 #define MMC_RXVLANFRAMES_GB_HI 0x099c 564 #define MMC_RXWATCHDOGERROR 0x09a0 565 566 /* MMC register entry bit positions and sizes */ 567 #define MMC_CR_CR_INDEX 0 568 #define MMC_CR_CR_WIDTH 1 569 #define MMC_CR_CSR_INDEX 1 570 #define MMC_CR_CSR_WIDTH 1 571 #define MMC_CR_ROR_INDEX 2 572 #define MMC_CR_ROR_WIDTH 1 573 #define MMC_CR_MCF_INDEX 3 574 #define MMC_CR_MCF_WIDTH 1 575 #define MMC_CR_MCT_INDEX 4 576 #define MMC_CR_MCT_WIDTH 2 577 #define MMC_RIER_ALL_INTERRUPTS_INDEX 0 578 #define MMC_RIER_ALL_INTERRUPTS_WIDTH 23 579 #define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0 580 #define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1 581 #define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1 582 #define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1 583 #define MMC_RISR_RXOCTETCOUNT_G_INDEX 2 584 #define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1 585 #define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3 586 #define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1 587 #define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4 588 #define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1 589 #define MMC_RISR_RXCRCERROR_INDEX 5 590 #define MMC_RISR_RXCRCERROR_WIDTH 1 591 #define MMC_RISR_RXRUNTERROR_INDEX 6 592 #define MMC_RISR_RXRUNTERROR_WIDTH 1 593 #define MMC_RISR_RXJABBERERROR_INDEX 7 594 #define MMC_RISR_RXJABBERERROR_WIDTH 1 595 #define MMC_RISR_RXUNDERSIZE_G_INDEX 8 596 #define MMC_RISR_RXUNDERSIZE_G_WIDTH 1 597 #define MMC_RISR_RXOVERSIZE_G_INDEX 9 598 #define MMC_RISR_RXOVERSIZE_G_WIDTH 1 599 #define MMC_RISR_RX64OCTETS_GB_INDEX 10 600 #define MMC_RISR_RX64OCTETS_GB_WIDTH 1 601 #define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11 602 #define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1 603 #define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12 604 #define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1 605 #define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13 606 #define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1 607 #define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14 608 #define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1 609 #define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15 610 #define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1 611 #define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16 612 #define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1 613 #define MMC_RISR_RXLENGTHERROR_INDEX 17 614 #define MMC_RISR_RXLENGTHERROR_WIDTH 1 615 #define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18 616 #define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1 617 #define MMC_RISR_RXPAUSEFRAMES_INDEX 19 618 #define MMC_RISR_RXPAUSEFRAMES_WIDTH 1 619 #define MMC_RISR_RXFIFOOVERFLOW_INDEX 20 620 #define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1 621 #define MMC_RISR_RXVLANFRAMES_GB_INDEX 21 622 #define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1 623 #define MMC_RISR_RXWATCHDOGERROR_INDEX 22 624 #define MMC_RISR_RXWATCHDOGERROR_WIDTH 1 625 #define MMC_TIER_ALL_INTERRUPTS_INDEX 0 626 #define MMC_TIER_ALL_INTERRUPTS_WIDTH 18 627 #define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0 628 #define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1 629 #define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1 630 #define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1 631 #define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2 632 #define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1 633 #define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3 634 #define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1 635 #define MMC_TISR_TX64OCTETS_GB_INDEX 4 636 #define MMC_TISR_TX64OCTETS_GB_WIDTH 1 637 #define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5 638 #define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1 639 #define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6 640 #define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1 641 #define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7 642 #define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1 643 #define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8 644 #define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1 645 #define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9 646 #define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1 647 #define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10 648 #define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1 649 #define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11 650 #define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1 651 #define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12 652 #define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1 653 #define MMC_TISR_TXUNDERFLOWERROR_INDEX 13 654 #define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1 655 #define MMC_TISR_TXOCTETCOUNT_G_INDEX 14 656 #define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1 657 #define MMC_TISR_TXFRAMECOUNT_G_INDEX 15 658 #define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1 659 #define MMC_TISR_TXPAUSEFRAMES_INDEX 16 660 #define MMC_TISR_TXPAUSEFRAMES_WIDTH 1 661 #define MMC_TISR_TXVLANFRAMES_G_INDEX 17 662 #define MMC_TISR_TXVLANFRAMES_G_WIDTH 1 663 664 /* MTL register offsets */ 665 #define MTL_OMR 0x1000 666 #define MTL_FDCR 0x1008 667 #define MTL_FDSR 0x100c 668 #define MTL_FDDR 0x1010 669 #define MTL_ISR 0x1020 670 #define MTL_RQDCM0R 0x1030 671 #define MTL_TCPM0R 0x1040 672 #define MTL_TCPM1R 0x1044 673 674 #define MTL_RQDCM_INC 4 675 #define MTL_RQDCM_Q_PER_REG 4 676 #define MTL_TCPM_INC 4 677 #define MTL_TCPM_TC_PER_REG 4 678 679 /* MTL register entry bit positions and sizes */ 680 #define MTL_OMR_ETSALG_INDEX 5 681 #define MTL_OMR_ETSALG_WIDTH 2 682 #define MTL_OMR_RAA_INDEX 2 683 #define MTL_OMR_RAA_WIDTH 1 684 685 /* MTL queue register offsets 686 * Multiple queues can be active. The first queue has registers 687 * that begin at 0x1100. Each subsequent queue has registers that 688 * are accessed using an offset of 0x80 from the previous queue. 689 */ 690 #define MTL_Q_BASE 0x1100 691 #define MTL_Q_INC 0x80 692 693 #define MTL_Q_TQOMR 0x00 694 #define MTL_Q_TQUR 0x04 695 #define MTL_Q_TQDR 0x08 696 #define MTL_Q_RQOMR 0x40 697 #define MTL_Q_RQMPOCR 0x44 698 #define MTL_Q_RQDR 0x48 699 #define MTL_Q_RQFCR 0x50 700 #define MTL_Q_IER 0x70 701 #define MTL_Q_ISR 0x74 702 703 /* MTL queue register entry bit positions and sizes */ 704 #define MTL_Q_RQDR_PRXQ_INDEX 16 705 #define MTL_Q_RQDR_PRXQ_WIDTH 14 706 #define MTL_Q_RQDR_RXQSTS_INDEX 4 707 #define MTL_Q_RQDR_RXQSTS_WIDTH 2 708 #define MTL_Q_RQFCR_RFA_INDEX 1 709 #define MTL_Q_RQFCR_RFA_WIDTH 6 710 #define MTL_Q_RQFCR_RFD_INDEX 17 711 #define MTL_Q_RQFCR_RFD_WIDTH 6 712 #define MTL_Q_RQOMR_EHFC_INDEX 7 713 #define MTL_Q_RQOMR_EHFC_WIDTH 1 714 #define MTL_Q_RQOMR_RQS_INDEX 16 715 #define MTL_Q_RQOMR_RQS_WIDTH 9 716 #define MTL_Q_RQOMR_RSF_INDEX 5 717 #define MTL_Q_RQOMR_RSF_WIDTH 1 718 #define MTL_Q_RQOMR_RTC_INDEX 0 719 #define MTL_Q_RQOMR_RTC_WIDTH 2 720 #define MTL_Q_TQDR_TRCSTS_INDEX 1 721 #define MTL_Q_TQDR_TRCSTS_WIDTH 2 722 #define MTL_Q_TQDR_TXQSTS_INDEX 4 723 #define MTL_Q_TQDR_TXQSTS_WIDTH 1 724 #define MTL_Q_TQOMR_FTQ_INDEX 0 725 #define MTL_Q_TQOMR_FTQ_WIDTH 1 726 #define MTL_Q_TQOMR_Q2TCMAP_INDEX 8 727 #define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3 728 #define MTL_Q_TQOMR_TQS_INDEX 16 729 #define MTL_Q_TQOMR_TQS_WIDTH 10 730 #define MTL_Q_TQOMR_TSF_INDEX 1 731 #define MTL_Q_TQOMR_TSF_WIDTH 1 732 #define MTL_Q_TQOMR_TTC_INDEX 4 733 #define MTL_Q_TQOMR_TTC_WIDTH 3 734 #define MTL_Q_TQOMR_TXQEN_INDEX 2 735 #define MTL_Q_TQOMR_TXQEN_WIDTH 2 736 737 /* MTL queue register value */ 738 #define MTL_RSF_DISABLE 0x00 739 #define MTL_RSF_ENABLE 0x01 740 #define MTL_TSF_DISABLE 0x00 741 #define MTL_TSF_ENABLE 0x01 742 743 #define MTL_RX_THRESHOLD_64 0x00 744 #define MTL_RX_THRESHOLD_96 0x02 745 #define MTL_RX_THRESHOLD_128 0x03 746 #define MTL_TX_THRESHOLD_32 0x01 747 #define MTL_TX_THRESHOLD_64 0x00 748 #define MTL_TX_THRESHOLD_96 0x02 749 #define MTL_TX_THRESHOLD_128 0x03 750 #define MTL_TX_THRESHOLD_192 0x04 751 #define MTL_TX_THRESHOLD_256 0x05 752 #define MTL_TX_THRESHOLD_384 0x06 753 #define MTL_TX_THRESHOLD_512 0x07 754 755 #define MTL_ETSALG_WRR 0x00 756 #define MTL_ETSALG_WFQ 0x01 757 #define MTL_ETSALG_DWRR 0x02 758 #define MTL_RAA_SP 0x00 759 #define MTL_RAA_WSP 0x01 760 761 #define MTL_Q_DISABLED 0x00 762 #define MTL_Q_ENABLED 0x02 763 764 /* MTL traffic class register offsets 765 * Multiple traffic classes can be active. The first class has registers 766 * that begin at 0x1100. Each subsequent queue has registers that 767 * are accessed using an offset of 0x80 from the previous queue. 768 */ 769 #define MTL_TC_BASE MTL_Q_BASE 770 #define MTL_TC_INC MTL_Q_INC 771 772 #define MTL_TC_ETSCR 0x10 773 #define MTL_TC_ETSSR 0x14 774 #define MTL_TC_QWR 0x18 775 776 /* MTL traffic class register entry bit positions and sizes */ 777 #define MTL_TC_ETSCR_TSA_INDEX 0 778 #define MTL_TC_ETSCR_TSA_WIDTH 2 779 #define MTL_TC_QWR_QW_INDEX 0 780 #define MTL_TC_QWR_QW_WIDTH 21 781 782 /* MTL traffic class register value */ 783 #define MTL_TSA_SP 0x00 784 #define MTL_TSA_ETS 0x02 785 786 /* PCS register offsets */ 787 #define PCS_V1_WINDOW_SELECT 0x03fc 788 #define PCS_V2_WINDOW_DEF 0x9060 789 #define PCS_V2_WINDOW_SELECT 0x9064 790 #define PCS_V2_RV_WINDOW_DEF 0x1060 791 #define PCS_V2_RV_WINDOW_SELECT 0x1064 792 #define PCS_V2_YC_WINDOW_DEF 0x18060 793 #define PCS_V2_YC_WINDOW_SELECT 0x18064 794 #define PCS_V3_RN_WINDOW_DEF 0xf8078 795 #define PCS_V3_RN_WINDOW_SELECT 0xf807c 796 797 #define PCS_RN_SMN_BASE_ADDR 0x11e00000 798 #define PCS_RN_PORT_ADDR_SIZE 0x100000 799 800 /* PCS register entry bit positions and sizes */ 801 #define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6 802 #define PCS_V2_WINDOW_DEF_OFFSET_WIDTH 14 803 #define PCS_V2_WINDOW_DEF_SIZE_INDEX 2 804 #define PCS_V2_WINDOW_DEF_SIZE_WIDTH 4 805 806 /* SerDes integration register offsets */ 807 #define SIR0_KR_RT_1 0x002c 808 #define SIR0_STATUS 0x0040 809 #define SIR1_SPEED 0x0000 810 811 /* SerDes integration register entry bit positions and sizes */ 812 #define SIR0_KR_RT_1_RESET_INDEX 11 813 #define SIR0_KR_RT_1_RESET_WIDTH 1 814 #define SIR0_STATUS_RX_READY_INDEX 0 815 #define SIR0_STATUS_RX_READY_WIDTH 1 816 #define SIR0_STATUS_TX_READY_INDEX 8 817 #define SIR0_STATUS_TX_READY_WIDTH 1 818 #define SIR1_SPEED_CDR_RATE_INDEX 12 819 #define SIR1_SPEED_CDR_RATE_WIDTH 4 820 #define SIR1_SPEED_DATARATE_INDEX 4 821 #define SIR1_SPEED_DATARATE_WIDTH 2 822 #define SIR1_SPEED_PLLSEL_INDEX 3 823 #define SIR1_SPEED_PLLSEL_WIDTH 1 824 #define SIR1_SPEED_RATECHANGE_INDEX 6 825 #define SIR1_SPEED_RATECHANGE_WIDTH 1 826 #define SIR1_SPEED_TXAMP_INDEX 8 827 #define SIR1_SPEED_TXAMP_WIDTH 4 828 #define SIR1_SPEED_WORDMODE_INDEX 0 829 #define SIR1_SPEED_WORDMODE_WIDTH 3 830 831 /* SerDes RxTx register offsets */ 832 #define RXTX_REG6 0x0018 833 #define RXTX_REG20 0x0050 834 #define RXTX_REG22 0x0058 835 #define RXTX_REG114 0x01c8 836 #define RXTX_REG129 0x0204 837 838 /* SerDes RxTx register entry bit positions and sizes */ 839 #define RXTX_REG6_RESETB_RXD_INDEX 8 840 #define RXTX_REG6_RESETB_RXD_WIDTH 1 841 #define RXTX_REG20_BLWC_ENA_INDEX 2 842 #define RXTX_REG20_BLWC_ENA_WIDTH 1 843 #define RXTX_REG114_PQ_REG_INDEX 9 844 #define RXTX_REG114_PQ_REG_WIDTH 7 845 #define RXTX_REG129_RXDFE_CONFIG_INDEX 14 846 #define RXTX_REG129_RXDFE_CONFIG_WIDTH 2 847 848 /* MAC Control register offsets */ 849 #define XP_PROP_0 0x0000 850 #define XP_PROP_1 0x0004 851 #define XP_PROP_2 0x0008 852 #define XP_PROP_3 0x000c 853 #define XP_PROP_4 0x0010 854 #define XP_PROP_5 0x0014 855 #define XP_MAC_ADDR_LO 0x0020 856 #define XP_MAC_ADDR_HI 0x0024 857 #define XP_ECC_ISR 0x0030 858 #define XP_ECC_IER 0x0034 859 #define XP_ECC_CNT0 0x003c 860 #define XP_ECC_CNT1 0x0040 861 #define XP_DRIVER_INT_REQ 0x0060 862 #define XP_DRIVER_INT_RO 0x0064 863 #define XP_DRIVER_SCRATCH_0 0x0068 864 #define XP_DRIVER_SCRATCH_1 0x006c 865 #define XP_INT_REISSUE_EN 0x0074 866 #define XP_INT_EN 0x0078 867 #define XP_I2C_MUTEX 0x0080 868 #define XP_MDIO_MUTEX 0x0084 869 870 /* MAC Control register entry bit positions and sizes */ 871 #define XP_DRIVER_INT_REQ_REQUEST_INDEX 0 872 #define XP_DRIVER_INT_REQ_REQUEST_WIDTH 1 873 #define XP_DRIVER_INT_RO_STATUS_INDEX 0 874 #define XP_DRIVER_INT_RO_STATUS_WIDTH 1 875 #define XP_DRIVER_SCRATCH_0_COMMAND_INDEX 0 876 #define XP_DRIVER_SCRATCH_0_COMMAND_WIDTH 8 877 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_INDEX 8 878 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_WIDTH 8 879 #define XP_ECC_CNT0_RX_DED_INDEX 24 880 #define XP_ECC_CNT0_RX_DED_WIDTH 8 881 #define XP_ECC_CNT0_RX_SEC_INDEX 16 882 #define XP_ECC_CNT0_RX_SEC_WIDTH 8 883 #define XP_ECC_CNT0_TX_DED_INDEX 8 884 #define XP_ECC_CNT0_TX_DED_WIDTH 8 885 #define XP_ECC_CNT0_TX_SEC_INDEX 0 886 #define XP_ECC_CNT0_TX_SEC_WIDTH 8 887 #define XP_ECC_CNT1_DESC_DED_INDEX 8 888 #define XP_ECC_CNT1_DESC_DED_WIDTH 8 889 #define XP_ECC_CNT1_DESC_SEC_INDEX 0 890 #define XP_ECC_CNT1_DESC_SEC_WIDTH 8 891 #define XP_ECC_IER_DESC_DED_INDEX 5 892 #define XP_ECC_IER_DESC_DED_WIDTH 1 893 #define XP_ECC_IER_DESC_SEC_INDEX 4 894 #define XP_ECC_IER_DESC_SEC_WIDTH 1 895 #define XP_ECC_IER_RX_DED_INDEX 3 896 #define XP_ECC_IER_RX_DED_WIDTH 1 897 #define XP_ECC_IER_RX_SEC_INDEX 2 898 #define XP_ECC_IER_RX_SEC_WIDTH 1 899 #define XP_ECC_IER_TX_DED_INDEX 1 900 #define XP_ECC_IER_TX_DED_WIDTH 1 901 #define XP_ECC_IER_TX_SEC_INDEX 0 902 #define XP_ECC_IER_TX_SEC_WIDTH 1 903 #define XP_ECC_ISR_DESC_DED_INDEX 5 904 #define XP_ECC_ISR_DESC_DED_WIDTH 1 905 #define XP_ECC_ISR_DESC_SEC_INDEX 4 906 #define XP_ECC_ISR_DESC_SEC_WIDTH 1 907 #define XP_ECC_ISR_RX_DED_INDEX 3 908 #define XP_ECC_ISR_RX_DED_WIDTH 1 909 #define XP_ECC_ISR_RX_SEC_INDEX 2 910 #define XP_ECC_ISR_RX_SEC_WIDTH 1 911 #define XP_ECC_ISR_TX_DED_INDEX 1 912 #define XP_ECC_ISR_TX_DED_WIDTH 1 913 #define XP_ECC_ISR_TX_SEC_INDEX 0 914 #define XP_ECC_ISR_TX_SEC_WIDTH 1 915 #define XP_I2C_MUTEX_BUSY_INDEX 31 916 #define XP_I2C_MUTEX_BUSY_WIDTH 1 917 #define XP_I2C_MUTEX_ID_INDEX 29 918 #define XP_I2C_MUTEX_ID_WIDTH 2 919 #define XP_I2C_MUTEX_ACTIVE_INDEX 0 920 #define XP_I2C_MUTEX_ACTIVE_WIDTH 1 921 #define XP_MAC_ADDR_HI_VALID_INDEX 31 922 #define XP_MAC_ADDR_HI_VALID_WIDTH 1 923 #define XP_PROP_0_CONN_TYPE_INDEX 28 924 #define XP_PROP_0_CONN_TYPE_WIDTH 3 925 #define XP_PROP_0_MDIO_ADDR_INDEX 16 926 #define XP_PROP_0_MDIO_ADDR_WIDTH 5 927 #define XP_PROP_0_PORT_ID_INDEX 0 928 #define XP_PROP_0_PORT_ID_WIDTH 8 929 #define XP_PROP_0_PORT_MODE_INDEX 8 930 #define XP_PROP_0_PORT_MODE_WIDTH 4 931 #define XP_PROP_0_PORT_SPEEDS_INDEX 22 932 #define XP_PROP_0_PORT_SPEEDS_WIDTH 5 933 #define XP_PROP_1_MAX_RX_DMA_INDEX 24 934 #define XP_PROP_1_MAX_RX_DMA_WIDTH 5 935 #define XP_PROP_1_MAX_RX_QUEUES_INDEX 8 936 #define XP_PROP_1_MAX_RX_QUEUES_WIDTH 5 937 #define XP_PROP_1_MAX_TX_DMA_INDEX 16 938 #define XP_PROP_1_MAX_TX_DMA_WIDTH 5 939 #define XP_PROP_1_MAX_TX_QUEUES_INDEX 0 940 #define XP_PROP_1_MAX_TX_QUEUES_WIDTH 5 941 #define XP_PROP_2_RX_FIFO_SIZE_INDEX 16 942 #define XP_PROP_2_RX_FIFO_SIZE_WIDTH 16 943 #define XP_PROP_2_TX_FIFO_SIZE_INDEX 0 944 #define XP_PROP_2_TX_FIFO_SIZE_WIDTH 16 945 #define XP_PROP_3_GPIO_MASK_INDEX 28 946 #define XP_PROP_3_GPIO_MASK_WIDTH 4 947 #define XP_PROP_3_GPIO_MOD_ABS_INDEX 20 948 #define XP_PROP_3_GPIO_MOD_ABS_WIDTH 4 949 #define XP_PROP_3_GPIO_RATE_SELECT_INDEX 16 950 #define XP_PROP_3_GPIO_RATE_SELECT_WIDTH 4 951 #define XP_PROP_3_GPIO_RX_LOS_INDEX 24 952 #define XP_PROP_3_GPIO_RX_LOS_WIDTH 4 953 #define XP_PROP_3_GPIO_TX_FAULT_INDEX 12 954 #define XP_PROP_3_GPIO_TX_FAULT_WIDTH 4 955 #define XP_PROP_3_GPIO_ADDR_INDEX 8 956 #define XP_PROP_3_GPIO_ADDR_WIDTH 3 957 #define XP_PROP_3_MDIO_RESET_INDEX 0 958 #define XP_PROP_3_MDIO_RESET_WIDTH 2 959 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_INDEX 8 960 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_WIDTH 3 961 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_INDEX 12 962 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_WIDTH 4 963 #define XP_PROP_3_MDIO_RESET_INT_GPIO_INDEX 4 964 #define XP_PROP_3_MDIO_RESET_INT_GPIO_WIDTH 2 965 #define XP_PROP_4_MUX_ADDR_HI_INDEX 8 966 #define XP_PROP_4_MUX_ADDR_HI_WIDTH 5 967 #define XP_PROP_4_MUX_ADDR_LO_INDEX 0 968 #define XP_PROP_4_MUX_ADDR_LO_WIDTH 3 969 #define XP_PROP_4_MUX_CHAN_INDEX 4 970 #define XP_PROP_4_MUX_CHAN_WIDTH 3 971 #define XP_PROP_4_REDRV_ADDR_INDEX 16 972 #define XP_PROP_4_REDRV_ADDR_WIDTH 7 973 #define XP_PROP_4_REDRV_IF_INDEX 23 974 #define XP_PROP_4_REDRV_IF_WIDTH 1 975 #define XP_PROP_4_REDRV_LANE_INDEX 24 976 #define XP_PROP_4_REDRV_LANE_WIDTH 3 977 #define XP_PROP_4_REDRV_MODEL_INDEX 28 978 #define XP_PROP_4_REDRV_MODEL_WIDTH 3 979 #define XP_PROP_4_REDRV_PRESENT_INDEX 31 980 #define XP_PROP_4_REDRV_PRESENT_WIDTH 1 981 982 /* I2C Control register offsets */ 983 #define IC_CON 0x0000 984 #define IC_TAR 0x0004 985 #define IC_DATA_CMD 0x0010 986 #define IC_INTR_STAT 0x002c 987 #define IC_INTR_MASK 0x0030 988 #define IC_RAW_INTR_STAT 0x0034 989 #define IC_CLR_INTR 0x0040 990 #define IC_CLR_TX_ABRT 0x0054 991 #define IC_CLR_STOP_DET 0x0060 992 #define IC_ENABLE 0x006c 993 #define IC_TXFLR 0x0074 994 #define IC_RXFLR 0x0078 995 #define IC_TX_ABRT_SOURCE 0x0080 996 #define IC_ENABLE_STATUS 0x009c 997 #define IC_COMP_PARAM_1 0x00f4 998 999 /* I2C Control register entry bit positions and sizes */ 1000 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX 2 1001 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH 2 1002 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX 8 1003 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH 8 1004 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX 16 1005 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH 8 1006 #define IC_CON_MASTER_MODE_INDEX 0 1007 #define IC_CON_MASTER_MODE_WIDTH 1 1008 #define IC_CON_RESTART_EN_INDEX 5 1009 #define IC_CON_RESTART_EN_WIDTH 1 1010 #define IC_CON_RX_FIFO_FULL_HOLD_INDEX 9 1011 #define IC_CON_RX_FIFO_FULL_HOLD_WIDTH 1 1012 #define IC_CON_SLAVE_DISABLE_INDEX 6 1013 #define IC_CON_SLAVE_DISABLE_WIDTH 1 1014 #define IC_CON_SPEED_INDEX 1 1015 #define IC_CON_SPEED_WIDTH 2 1016 #define IC_DATA_CMD_CMD_INDEX 8 1017 #define IC_DATA_CMD_CMD_WIDTH 1 1018 #define IC_DATA_CMD_STOP_INDEX 9 1019 #define IC_DATA_CMD_STOP_WIDTH 1 1020 #define IC_ENABLE_ABORT_INDEX 1 1021 #define IC_ENABLE_ABORT_WIDTH 1 1022 #define IC_ENABLE_EN_INDEX 0 1023 #define IC_ENABLE_EN_WIDTH 1 1024 #define IC_ENABLE_STATUS_EN_INDEX 0 1025 #define IC_ENABLE_STATUS_EN_WIDTH 1 1026 #define IC_INTR_MASK_TX_EMPTY_INDEX 4 1027 #define IC_INTR_MASK_TX_EMPTY_WIDTH 1 1028 #define IC_RAW_INTR_STAT_RX_FULL_INDEX 2 1029 #define IC_RAW_INTR_STAT_RX_FULL_WIDTH 1 1030 #define IC_RAW_INTR_STAT_STOP_DET_INDEX 9 1031 #define IC_RAW_INTR_STAT_STOP_DET_WIDTH 1 1032 #define IC_RAW_INTR_STAT_TX_ABRT_INDEX 6 1033 #define IC_RAW_INTR_STAT_TX_ABRT_WIDTH 1 1034 #define IC_RAW_INTR_STAT_TX_EMPTY_INDEX 4 1035 #define IC_RAW_INTR_STAT_TX_EMPTY_WIDTH 1 1036 1037 /* I2C Control register value */ 1038 #define IC_TX_ABRT_7B_ADDR_NOACK 0x0001 1039 #define IC_TX_ABRT_ARB_LOST 0x1000 1040 1041 /* Descriptor/Packet entry bit positions and sizes */ 1042 #define RX_PACKET_ERRORS_CRC_INDEX 2 1043 #define RX_PACKET_ERRORS_CRC_WIDTH 1 1044 #define RX_PACKET_ERRORS_FRAME_INDEX 3 1045 #define RX_PACKET_ERRORS_FRAME_WIDTH 1 1046 #define RX_PACKET_ERRORS_LENGTH_INDEX 0 1047 #define RX_PACKET_ERRORS_LENGTH_WIDTH 1 1048 #define RX_PACKET_ERRORS_OVERRUN_INDEX 1 1049 #define RX_PACKET_ERRORS_OVERRUN_WIDTH 1 1050 1051 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0 1052 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1 1053 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1 1054 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1 1055 #define RX_PACKET_ATTRIBUTES_LAST_INDEX 2 1056 #define RX_PACKET_ATTRIBUTES_LAST_WIDTH 1 1057 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3 1058 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1 1059 #define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4 1060 #define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1 1061 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5 1062 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1 1063 #define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 6 1064 #define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1 1065 #define RX_PACKET_ATTRIBUTES_FIRST_INDEX 7 1066 #define RX_PACKET_ATTRIBUTES_FIRST_WIDTH 1 1067 #define RX_PACKET_ATTRIBUTES_TNP_INDEX 8 1068 #define RX_PACKET_ATTRIBUTES_TNP_WIDTH 1 1069 #define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_INDEX 9 1070 #define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_WIDTH 1 1071 1072 #define RX_NORMAL_DESC0_OVT_INDEX 0 1073 #define RX_NORMAL_DESC0_OVT_WIDTH 16 1074 #define RX_NORMAL_DESC2_HL_INDEX 0 1075 #define RX_NORMAL_DESC2_HL_WIDTH 10 1076 #define RX_NORMAL_DESC2_TNP_INDEX 11 1077 #define RX_NORMAL_DESC2_TNP_WIDTH 1 1078 #define RX_NORMAL_DESC3_CDA_INDEX 27 1079 #define RX_NORMAL_DESC3_CDA_WIDTH 1 1080 #define RX_NORMAL_DESC3_CTXT_INDEX 30 1081 #define RX_NORMAL_DESC3_CTXT_WIDTH 1 1082 #define RX_NORMAL_DESC3_ES_INDEX 15 1083 #define RX_NORMAL_DESC3_ES_WIDTH 1 1084 #define RX_NORMAL_DESC3_ETLT_INDEX 16 1085 #define RX_NORMAL_DESC3_ETLT_WIDTH 4 1086 #define RX_NORMAL_DESC3_FD_INDEX 29 1087 #define RX_NORMAL_DESC3_FD_WIDTH 1 1088 #define RX_NORMAL_DESC3_INTE_INDEX 30 1089 #define RX_NORMAL_DESC3_INTE_WIDTH 1 1090 #define RX_NORMAL_DESC3_L34T_INDEX 20 1091 #define RX_NORMAL_DESC3_L34T_WIDTH 4 1092 #define RX_NORMAL_DESC3_LD_INDEX 28 1093 #define RX_NORMAL_DESC3_LD_WIDTH 1 1094 #define RX_NORMAL_DESC3_OWN_INDEX 31 1095 #define RX_NORMAL_DESC3_OWN_WIDTH 1 1096 #define RX_NORMAL_DESC3_PL_INDEX 0 1097 #define RX_NORMAL_DESC3_PL_WIDTH 14 1098 #define RX_NORMAL_DESC3_RSV_INDEX 26 1099 #define RX_NORMAL_DESC3_RSV_WIDTH 1 1100 1101 #define RX_DESC3_L34T_IPV4_TCP 1 1102 #define RX_DESC3_L34T_IPV4_UDP 2 1103 #define RX_DESC3_L34T_IPV4_ICMP 3 1104 #define RX_DESC3_L34T_IPV4_UNKNOWN 7 1105 #define RX_DESC3_L34T_IPV6_TCP 9 1106 #define RX_DESC3_L34T_IPV6_UDP 10 1107 #define RX_DESC3_L34T_IPV6_ICMP 11 1108 #define RX_DESC3_L34T_IPV6_UNKNOWN 15 1109 1110 #define RX_CONTEXT_DESC3_TSA_INDEX 4 1111 #define RX_CONTEXT_DESC3_TSA_WIDTH 1 1112 #define RX_CONTEXT_DESC3_TSD_INDEX 6 1113 #define RX_CONTEXT_DESC3_TSD_WIDTH 1 1114 1115 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0 1116 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1 1117 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1 1118 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1 1119 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2 1120 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1 1121 #define TX_PACKET_ATTRIBUTES_PTP_INDEX 3 1122 #define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1 1123 #define TX_PACKET_ATTRIBUTES_VXLAN_INDEX 4 1124 #define TX_PACKET_ATTRIBUTES_VXLAN_WIDTH 1 1125 1126 #define TX_CONTEXT_DESC2_MSS_INDEX 0 1127 #define TX_CONTEXT_DESC2_MSS_WIDTH 15 1128 #define TX_CONTEXT_DESC3_CTXT_INDEX 30 1129 #define TX_CONTEXT_DESC3_CTXT_WIDTH 1 1130 #define TX_CONTEXT_DESC3_TCMSSV_INDEX 26 1131 #define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1 1132 #define TX_CONTEXT_DESC3_VLTV_INDEX 16 1133 #define TX_CONTEXT_DESC3_VLTV_WIDTH 1 1134 #define TX_CONTEXT_DESC3_VT_INDEX 0 1135 #define TX_CONTEXT_DESC3_VT_WIDTH 16 1136 1137 #define TX_NORMAL_DESC2_HL_B1L_INDEX 0 1138 #define TX_NORMAL_DESC2_HL_B1L_WIDTH 14 1139 #define TX_NORMAL_DESC2_IC_INDEX 31 1140 #define TX_NORMAL_DESC2_IC_WIDTH 1 1141 #define TX_NORMAL_DESC2_TTSE_INDEX 30 1142 #define TX_NORMAL_DESC2_TTSE_WIDTH 1 1143 #define TX_NORMAL_DESC2_VTIR_INDEX 14 1144 #define TX_NORMAL_DESC2_VTIR_WIDTH 2 1145 #define TX_NORMAL_DESC3_CIC_INDEX 16 1146 #define TX_NORMAL_DESC3_CIC_WIDTH 2 1147 #define TX_NORMAL_DESC3_CPC_INDEX 26 1148 #define TX_NORMAL_DESC3_CPC_WIDTH 2 1149 #define TX_NORMAL_DESC3_CTXT_INDEX 30 1150 #define TX_NORMAL_DESC3_CTXT_WIDTH 1 1151 #define TX_NORMAL_DESC3_FD_INDEX 29 1152 #define TX_NORMAL_DESC3_FD_WIDTH 1 1153 #define TX_NORMAL_DESC3_FL_INDEX 0 1154 #define TX_NORMAL_DESC3_FL_WIDTH 15 1155 #define TX_NORMAL_DESC3_LD_INDEX 28 1156 #define TX_NORMAL_DESC3_LD_WIDTH 1 1157 #define TX_NORMAL_DESC3_OWN_INDEX 31 1158 #define TX_NORMAL_DESC3_OWN_WIDTH 1 1159 #define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19 1160 #define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4 1161 #define TX_NORMAL_DESC3_TCPPL_INDEX 0 1162 #define TX_NORMAL_DESC3_TCPPL_WIDTH 18 1163 #define TX_NORMAL_DESC3_TSE_INDEX 18 1164 #define TX_NORMAL_DESC3_TSE_WIDTH 1 1165 #define TX_NORMAL_DESC3_VNP_INDEX 23 1166 #define TX_NORMAL_DESC3_VNP_WIDTH 3 1167 1168 #define TX_NORMAL_DESC2_VLAN_INSERT 0x2 1169 #define TX_NORMAL_DESC3_VXLAN_PACKET 0x3 1170 1171 /* MDIO undefined or vendor specific registers */ 1172 #ifndef MDIO_PMA_10GBR_PMD_CTRL 1173 #define MDIO_PMA_10GBR_PMD_CTRL 0x0096 1174 #endif 1175 1176 #ifndef MDIO_PMA_10GBR_FECCTRL 1177 #define MDIO_PMA_10GBR_FECCTRL 0x00ab 1178 #endif 1179 1180 #ifndef MDIO_PMA_RX_CTRL1 1181 #define MDIO_PMA_RX_CTRL1 0x8051 1182 #endif 1183 1184 #ifndef MDIO_PMA_RX_LSTS 1185 #define MDIO_PMA_RX_LSTS 0x018020 1186 #endif 1187 1188 #ifndef MDIO_PMA_RX_EQ_CTRL4 1189 #define MDIO_PMA_RX_EQ_CTRL4 0x0001805C 1190 #endif 1191 1192 #ifndef MDIO_PMA_MP_MISC_STS 1193 #define MDIO_PMA_MP_MISC_STS 0x0078 1194 #endif 1195 1196 #ifndef MDIO_PMA_PHY_RX_EQ_CEU 1197 #define MDIO_PMA_PHY_RX_EQ_CEU 0x1800E 1198 #endif 1199 1200 #ifndef MDIO_PCS_DIG_CTRL 1201 #define MDIO_PCS_DIG_CTRL 0x8000 1202 #endif 1203 1204 #ifndef MDIO_PCS_DIGITAL_STAT 1205 #define MDIO_PCS_DIGITAL_STAT 0x8010 1206 #endif 1207 1208 #ifndef MDIO_AN_XNP 1209 #define MDIO_AN_XNP 0x0016 1210 #endif 1211 1212 #ifndef MDIO_AN_LPX 1213 #define MDIO_AN_LPX 0x0019 1214 #endif 1215 1216 #ifndef MDIO_AN_COMP_STAT 1217 #define MDIO_AN_COMP_STAT 0x0030 1218 #endif 1219 1220 #ifndef MDIO_AN_INTMASK 1221 #define MDIO_AN_INTMASK 0x8001 1222 #endif 1223 1224 #ifndef MDIO_AN_INT 1225 #define MDIO_AN_INT 0x8002 1226 #endif 1227 1228 #ifndef MDIO_VEND2_AN_ADVERTISE 1229 #define MDIO_VEND2_AN_ADVERTISE 0x0004 1230 #endif 1231 1232 #ifndef MDIO_VEND2_AN_LP_ABILITY 1233 #define MDIO_VEND2_AN_LP_ABILITY 0x0005 1234 #endif 1235 1236 #ifndef MDIO_VEND2_AN_CTRL 1237 #define MDIO_VEND2_AN_CTRL 0x8001 1238 #endif 1239 1240 #ifndef MDIO_VEND2_AN_STAT 1241 #define MDIO_VEND2_AN_STAT 0x8002 1242 #endif 1243 1244 #ifndef MDIO_VEND2_PMA_CDR_CONTROL 1245 #define MDIO_VEND2_PMA_CDR_CONTROL 0x8056 1246 #endif 1247 1248 #ifndef MDIO_VEND2_PMA_MISC_CTRL0 1249 #define MDIO_VEND2_PMA_MISC_CTRL0 0x8090 1250 #endif 1251 1252 #ifndef MDIO_CTRL1_SPEED1G 1253 #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100) 1254 #endif 1255 1256 #ifndef MDIO_VEND2_CTRL1_AN_ENABLE 1257 #define MDIO_VEND2_CTRL1_AN_ENABLE BIT(12) 1258 #endif 1259 1260 #ifndef MDIO_VEND2_CTRL1_AN_RESTART 1261 #define MDIO_VEND2_CTRL1_AN_RESTART BIT(9) 1262 #endif 1263 1264 #ifndef MDIO_VEND2_CTRL1_SS6 1265 #define MDIO_VEND2_CTRL1_SS6 BIT(6) 1266 #endif 1267 1268 #ifndef MDIO_VEND2_CTRL1_SS13 1269 #define MDIO_VEND2_CTRL1_SS13 BIT(13) 1270 #endif 1271 1272 #define XGBE_VEND2_MAC_AUTO_SW BIT(9) 1273 1274 /* MDIO mask values */ 1275 #define XGBE_AN_CL73_INT_CMPLT BIT(0) 1276 #define XGBE_AN_CL73_INC_LINK BIT(1) 1277 #define XGBE_AN_CL73_PG_RCV BIT(2) 1278 #define XGBE_AN_CL73_INT_MASK 0x07 1279 1280 #define XGBE_XNP_MCF_NULL_MESSAGE 0x001 1281 #define XGBE_XNP_ACK_PROCESSED BIT(12) 1282 #define XGBE_XNP_MP_FORMATTED BIT(13) 1283 #define XGBE_XNP_NP_EXCHANGE BIT(15) 1284 1285 #define XGBE_KR_TRAINING_START BIT(0) 1286 #define XGBE_KR_TRAINING_ENABLE BIT(1) 1287 1288 #define XGBE_PCS_CL37_BP BIT(12) 1289 #define XGBE_PCS_PSEQ_STATE_MASK 0x1c 1290 #define XGBE_PCS_PSEQ_STATE_POWER_GOOD 0x10 1291 1292 #define XGBE_AN_CL37_INT_CMPLT BIT(0) 1293 #define XGBE_AN_CL37_INT_MASK 0x01 1294 1295 #define XGBE_AN_CL37_HD_MASK 0x40 1296 #define XGBE_AN_CL37_FD_MASK 0x20 1297 1298 #define XGBE_AN_CL37_PCS_MODE_MASK 0x06 1299 #define XGBE_AN_CL37_PCS_MODE_BASEX 0x00 1300 #define XGBE_AN_CL37_PCS_MODE_SGMII 0x04 1301 #define XGBE_AN_CL37_TX_CONFIG_MASK 0x08 1302 #define XGBE_AN_CL37_MII_CTRL_8BIT 0x0100 1303 1304 #define XGBE_PMA_CDR_TRACK_EN_MASK 0x01 1305 #define XGBE_PMA_CDR_TRACK_EN_OFF 0x00 1306 #define XGBE_PMA_CDR_TRACK_EN_ON 0x01 1307 1308 #define XGBE_PMA_RX_RST_0_MASK BIT(4) 1309 #define XGBE_PMA_RX_RST_0_RESET_ON 0x10 1310 #define XGBE_PMA_RX_RST_0_RESET_OFF 0x00 1311 1312 #define XGBE_PMA_RX_SIG_DET_0_MASK BIT(4) 1313 #define XGBE_PMA_RX_SIG_DET_0_ENABLE BIT(4) 1314 #define XGBE_PMA_RX_SIG_DET_0_DISABLE 0x0000 1315 1316 #define XGBE_PMA_RX_VALID_0_MASK BIT(12) 1317 #define XGBE_PMA_RX_VALID_0_ENABLE BIT(12) 1318 #define XGBE_PMA_RX_VALID_0_DISABLE 0x0000 1319 1320 #define XGBE_PMA_RX_AD_REQ_MASK BIT(12) 1321 #define XGBE_PMA_RX_AD_REQ_ENABLE BIT(12) 1322 #define XGBE_PMA_RX_AD_REQ_DISABLE 0x0000 1323 1324 #define XGBE_PMA_RX_ADPT_ACK_MASK BIT(12) 1325 #define XGBE_PMA_RX_ADPT_ACK BIT(12) 1326 1327 #define XGBE_PMA_CFF_UPDTM1_VLD BIT(8) 1328 #define XGBE_PMA_CFF_UPDT0_VLD BIT(9) 1329 #define XGBE_PMA_CFF_UPDT1_VLD BIT(10) 1330 #define XGBE_PMA_CFF_UPDT_MASK (XGBE_PMA_CFF_UPDTM1_VLD |\ 1331 XGBE_PMA_CFF_UPDT0_VLD | \ 1332 XGBE_PMA_CFF_UPDT1_VLD) 1333 1334 #define XGBE_PMA_PLL_CTRL_MASK BIT(15) 1335 #define XGBE_PMA_PLL_CTRL_ENABLE BIT(15) 1336 #define XGBE_PMA_PLL_CTRL_DISABLE 0x0000 1337 1338 /* Bit setting and getting macros 1339 * The get macro will extract the current bit field value from within 1340 * the variable 1341 * 1342 * The set macro will clear the current bit field value within the 1343 * variable and then set the bit field of the variable to the 1344 * specified value 1345 */ 1346 #define GET_BITS(_var, _index, _width) \ 1347 (((_var) >> (_index)) & ((0x1 << (_width)) - 1)) 1348 1349 #define SET_BITS(_var, _index, _width, _val) \ 1350 do { \ 1351 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \ 1352 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \ 1353 } while (0) 1354 1355 #define GET_BITS_LE(_var, _index, _width) \ 1356 ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1)) 1357 1358 #define SET_BITS_LE(_var, _index, _width, _val) \ 1359 do { \ 1360 (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \ 1361 (_var) |= cpu_to_le32((((_val) & \ 1362 ((0x1 << (_width)) - 1)) << (_index))); \ 1363 } while (0) 1364 1365 /* Bit setting and getting macros based on register fields 1366 * The get macro uses the bit field definitions formed using the input 1367 * names to extract the current bit field value from within the 1368 * variable 1369 * 1370 * The set macro uses the bit field definitions formed using the input 1371 * names to set the bit field of the variable to the specified value 1372 */ 1373 #define XGMAC_GET_BITS(_var, _prefix, _field) \ 1374 GET_BITS((_var), \ 1375 _prefix##_##_field##_INDEX, \ 1376 _prefix##_##_field##_WIDTH) 1377 1378 #define XGMAC_SET_BITS(_var, _prefix, _field, _val) \ 1379 SET_BITS((_var), \ 1380 _prefix##_##_field##_INDEX, \ 1381 _prefix##_##_field##_WIDTH, (_val)) 1382 1383 #define XGMAC_GET_BITS_LE(_var, _prefix, _field) \ 1384 GET_BITS_LE((_var), \ 1385 _prefix##_##_field##_INDEX, \ 1386 _prefix##_##_field##_WIDTH) 1387 1388 #define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \ 1389 SET_BITS_LE((_var), \ 1390 _prefix##_##_field##_INDEX, \ 1391 _prefix##_##_field##_WIDTH, (_val)) 1392 1393 /* Macros for reading or writing registers 1394 * The ioread macros will get bit fields or full values using the 1395 * register definitions formed using the input names 1396 * 1397 * The iowrite macros will set bit fields or full values using the 1398 * register definitions formed using the input names 1399 */ 1400 #define XGMAC_IOREAD(_pdata, _reg) \ 1401 ioread32((_pdata)->xgmac_regs + _reg) 1402 1403 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ 1404 GET_BITS(XGMAC_IOREAD((_pdata), _reg), \ 1405 _reg##_##_field##_INDEX, \ 1406 _reg##_##_field##_WIDTH) 1407 1408 #define XGMAC_IOWRITE(_pdata, _reg, _val) \ 1409 iowrite32((_val), (_pdata)->xgmac_regs + _reg) 1410 1411 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1412 do { \ 1413 u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \ 1414 SET_BITS(reg_val, \ 1415 _reg##_##_field##_INDEX, \ 1416 _reg##_##_field##_WIDTH, (_val)); \ 1417 XGMAC_IOWRITE((_pdata), _reg, reg_val); \ 1418 } while (0) 1419 1420 /* Macros for reading or writing MTL queue or traffic class registers 1421 * Similar to the standard read and write macros except that the 1422 * base register value is calculated by the queue or traffic class number 1423 */ 1424 #define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \ 1425 ioread32((_pdata)->xgmac_regs + \ 1426 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg) 1427 1428 #define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \ 1429 GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg), \ 1430 _reg##_##_field##_INDEX, \ 1431 _reg##_##_field##_WIDTH) 1432 1433 #define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \ 1434 iowrite32((_val), (_pdata)->xgmac_regs + \ 1435 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg) 1436 1437 #define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \ 1438 do { \ 1439 u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \ 1440 SET_BITS(reg_val, \ 1441 _reg##_##_field##_INDEX, \ 1442 _reg##_##_field##_WIDTH, (_val)); \ 1443 XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \ 1444 } while (0) 1445 1446 /* Macros for reading or writing DMA channel registers 1447 * Similar to the standard read and write macros except that the 1448 * base register value is obtained from the ring 1449 */ 1450 #define XGMAC_DMA_IOREAD(_channel, _reg) \ 1451 ioread32((_channel)->dma_regs + _reg) 1452 1453 #define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \ 1454 GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg), \ 1455 _reg##_##_field##_INDEX, \ 1456 _reg##_##_field##_WIDTH) 1457 1458 #define XGMAC_DMA_IOWRITE(_channel, _reg, _val) \ 1459 iowrite32((_val), (_channel)->dma_regs + _reg) 1460 1461 #define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \ 1462 do { \ 1463 u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \ 1464 SET_BITS(reg_val, \ 1465 _reg##_##_field##_INDEX, \ 1466 _reg##_##_field##_WIDTH, (_val)); \ 1467 XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \ 1468 } while (0) 1469 1470 /* Macros for building, reading or writing register values or bits 1471 * within the register values of XPCS registers. 1472 */ 1473 #define XPCS_GET_BITS(_var, _prefix, _field) \ 1474 GET_BITS((_var), \ 1475 _prefix##_##_field##_INDEX, \ 1476 _prefix##_##_field##_WIDTH) 1477 1478 #define XPCS_SET_BITS(_var, _prefix, _field, _val) \ 1479 SET_BITS((_var), \ 1480 _prefix##_##_field##_INDEX, \ 1481 _prefix##_##_field##_WIDTH, (_val)) 1482 1483 #define XPCS32_IOWRITE(_pdata, _off, _val) \ 1484 iowrite32(_val, (_pdata)->xpcs_regs + (_off)) 1485 1486 #define XPCS32_IOREAD(_pdata, _off) \ 1487 ioread32((_pdata)->xpcs_regs + (_off)) 1488 1489 #define XPCS16_IOWRITE(_pdata, _off, _val) \ 1490 iowrite16(_val, (_pdata)->xpcs_regs + (_off)) 1491 1492 #define XPCS16_IOREAD(_pdata, _off) \ 1493 ioread16((_pdata)->xpcs_regs + (_off)) 1494 1495 /* Macros for building, reading or writing register values or bits 1496 * within the register values of SerDes integration registers. 1497 */ 1498 #define XSIR_GET_BITS(_var, _prefix, _field) \ 1499 GET_BITS((_var), \ 1500 _prefix##_##_field##_INDEX, \ 1501 _prefix##_##_field##_WIDTH) 1502 1503 #define XSIR_SET_BITS(_var, _prefix, _field, _val) \ 1504 SET_BITS((_var), \ 1505 _prefix##_##_field##_INDEX, \ 1506 _prefix##_##_field##_WIDTH, (_val)) 1507 1508 #define XSIR0_IOREAD(_pdata, _reg) \ 1509 ioread16((_pdata)->sir0_regs + _reg) 1510 1511 #define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \ 1512 GET_BITS(XSIR0_IOREAD((_pdata), _reg), \ 1513 _reg##_##_field##_INDEX, \ 1514 _reg##_##_field##_WIDTH) 1515 1516 #define XSIR0_IOWRITE(_pdata, _reg, _val) \ 1517 iowrite16((_val), (_pdata)->sir0_regs + _reg) 1518 1519 #define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1520 do { \ 1521 u16 reg_val = XSIR0_IOREAD((_pdata), _reg); \ 1522 SET_BITS(reg_val, \ 1523 _reg##_##_field##_INDEX, \ 1524 _reg##_##_field##_WIDTH, (_val)); \ 1525 XSIR0_IOWRITE((_pdata), _reg, reg_val); \ 1526 } while (0) 1527 1528 #define XSIR1_IOREAD(_pdata, _reg) \ 1529 ioread16((_pdata)->sir1_regs + _reg) 1530 1531 #define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \ 1532 GET_BITS(XSIR1_IOREAD((_pdata), _reg), \ 1533 _reg##_##_field##_INDEX, \ 1534 _reg##_##_field##_WIDTH) 1535 1536 #define XSIR1_IOWRITE(_pdata, _reg, _val) \ 1537 iowrite16((_val), (_pdata)->sir1_regs + _reg) 1538 1539 #define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1540 do { \ 1541 u16 reg_val = XSIR1_IOREAD((_pdata), _reg); \ 1542 SET_BITS(reg_val, \ 1543 _reg##_##_field##_INDEX, \ 1544 _reg##_##_field##_WIDTH, (_val)); \ 1545 XSIR1_IOWRITE((_pdata), _reg, reg_val); \ 1546 } while (0) 1547 1548 /* Macros for building, reading or writing register values or bits 1549 * within the register values of SerDes RxTx registers. 1550 */ 1551 #define XRXTX_IOREAD(_pdata, _reg) \ 1552 ioread16((_pdata)->rxtx_regs + _reg) 1553 1554 #define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \ 1555 GET_BITS(XRXTX_IOREAD((_pdata), _reg), \ 1556 _reg##_##_field##_INDEX, \ 1557 _reg##_##_field##_WIDTH) 1558 1559 #define XRXTX_IOWRITE(_pdata, _reg, _val) \ 1560 iowrite16((_val), (_pdata)->rxtx_regs + _reg) 1561 1562 #define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1563 do { \ 1564 u16 reg_val = XRXTX_IOREAD((_pdata), _reg); \ 1565 SET_BITS(reg_val, \ 1566 _reg##_##_field##_INDEX, \ 1567 _reg##_##_field##_WIDTH, (_val)); \ 1568 XRXTX_IOWRITE((_pdata), _reg, reg_val); \ 1569 } while (0) 1570 1571 /* Macros for building, reading or writing register values or bits 1572 * within the register values of MAC Control registers. 1573 */ 1574 #define XP_GET_BITS(_var, _prefix, _field) \ 1575 GET_BITS((_var), \ 1576 _prefix##_##_field##_INDEX, \ 1577 _prefix##_##_field##_WIDTH) 1578 1579 #define XP_SET_BITS(_var, _prefix, _field, _val) \ 1580 SET_BITS((_var), \ 1581 _prefix##_##_field##_INDEX, \ 1582 _prefix##_##_field##_WIDTH, (_val)) 1583 1584 #define XP_IOREAD(_pdata, _reg) \ 1585 ioread32((_pdata)->xprop_regs + (_reg)) 1586 1587 #define XP_IOREAD_BITS(_pdata, _reg, _field) \ 1588 GET_BITS(XP_IOREAD((_pdata), (_reg)), \ 1589 _reg##_##_field##_INDEX, \ 1590 _reg##_##_field##_WIDTH) 1591 1592 #define XP_IOWRITE(_pdata, _reg, _val) \ 1593 iowrite32((_val), (_pdata)->xprop_regs + (_reg)) 1594 1595 #define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1596 do { \ 1597 u32 reg_val = XP_IOREAD((_pdata), (_reg)); \ 1598 SET_BITS(reg_val, \ 1599 _reg##_##_field##_INDEX, \ 1600 _reg##_##_field##_WIDTH, (_val)); \ 1601 XP_IOWRITE((_pdata), (_reg), reg_val); \ 1602 } while (0) 1603 1604 /* Macros for building, reading or writing register values or bits 1605 * within the register values of I2C Control registers. 1606 */ 1607 #define XI2C_GET_BITS(_var, _prefix, _field) \ 1608 GET_BITS((_var), \ 1609 _prefix##_##_field##_INDEX, \ 1610 _prefix##_##_field##_WIDTH) 1611 1612 #define XI2C_SET_BITS(_var, _prefix, _field, _val) \ 1613 SET_BITS((_var), \ 1614 _prefix##_##_field##_INDEX, \ 1615 _prefix##_##_field##_WIDTH, (_val)) 1616 1617 #define XI2C_IOREAD(_pdata, _reg) \ 1618 ioread32((_pdata)->xi2c_regs + (_reg)) 1619 1620 #define XI2C_IOREAD_BITS(_pdata, _reg, _field) \ 1621 GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \ 1622 _reg##_##_field##_INDEX, \ 1623 _reg##_##_field##_WIDTH) 1624 1625 #define XI2C_IOWRITE(_pdata, _reg, _val) \ 1626 iowrite32((_val), (_pdata)->xi2c_regs + (_reg)) 1627 1628 #define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1629 do { \ 1630 u32 reg_val = XI2C_IOREAD((_pdata), (_reg)); \ 1631 SET_BITS(reg_val, \ 1632 _reg##_##_field##_INDEX, \ 1633 _reg##_##_field##_WIDTH, (_val)); \ 1634 XI2C_IOWRITE((_pdata), (_reg), reg_val); \ 1635 } while (0) 1636 1637 /* Macros for building, reading or writing register values or bits 1638 * using MDIO. 1639 */ 1640 1641 #define XGBE_ADDR_C45 BIT(30) 1642 1643 #define XMDIO_READ(_pdata, _mmd, _reg) \ 1644 ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \ 1645 XGBE_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff))) 1646 1647 #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \ 1648 (XMDIO_READ((_pdata), _mmd, _reg) & _mask) 1649 1650 #define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \ 1651 ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \ 1652 XGBE_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val))) 1653 1654 #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \ 1655 do { \ 1656 u32 mmd_val = XMDIO_READ((_pdata), _mmd, _reg); \ 1657 mmd_val &= ~_mask; \ 1658 mmd_val |= (_val); \ 1659 XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val); \ 1660 } while (0) 1661 1662 #endif 1663