1 /*-
2 * Data structures and definitions for CAM Control Blocks (CCBs).
3 *
4 * SPDX-License-Identifier: BSD-2-Clause
5 *
6 * Copyright (c) 1997, 1998 Justin T. Gibbs.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification, immediately at the beginning of the file.
15 * 2. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 #ifndef _CAM_CAM_CCB_H
32 #define _CAM_CAM_CCB_H 1
33
34 #include <sys/queue.h>
35 #include <sys/time.h>
36 #include <sys/limits.h>
37 #ifndef _KERNEL
38 #include <sys/callout.h>
39 #endif
40 #include <cam/cam_debug.h>
41 #include <cam/scsi/scsi_all.h>
42 #include <cam/ata/ata_all.h>
43 #include <cam/nvme/nvme_all.h>
44 #include <cam/mmc/mmc_all.h>
45
46 /* General allocation length definitions for CCB structures */
47 #define IOCDBLEN CAM_MAX_CDBLEN /* Space for CDB bytes/pointer */
48 #define VUHBALEN 14 /* Vendor Unique HBA length */
49 #define SIM_IDLEN 16 /* ASCII string len for SIM ID */
50 #define HBA_IDLEN 16 /* ASCII string len for HBA ID */
51 #define DEV_IDLEN 16 /* ASCII string len for device names */
52 #define CCB_PERIPH_PRIV_SIZE 2 /* size of peripheral private area */
53 #define CCB_SIM_PRIV_SIZE 2 /* size of sim private area */
54
55 /* Struct definitions for CAM control blocks */
56
57 /* Common CCB header */
58
59 /* CCB memory allocation flags */
60 typedef enum {
61 CAM_CCB_FROM_UMA = 0x00000001,/* CCB from a periph UMA zone */
62 } ccb_alloc_flags;
63
64 /* CAM CCB flags */
65 typedef enum {
66 CAM_CDB_POINTER = 0x00000001,/* The CDB field is a pointer */
67 CAM_unused1 = 0x00000002,
68 CAM_unused2 = 0x00000004,
69 CAM_NEGOTIATE = 0x00000008,/*
70 * Perform transport negotiation
71 * with this command.
72 */
73 CAM_DATA_ISPHYS = 0x00000010,/* Data type with physical addrs */
74 CAM_DIS_AUTOSENSE = 0x00000020,/* Disable autosense feature */
75 CAM_DIR_BOTH = 0x00000000,/* Data direction (00:IN/OUT) */
76 CAM_DIR_IN = 0x00000040,/* Data direction (01:DATA IN) */
77 CAM_DIR_OUT = 0x00000080,/* Data direction (10:DATA OUT) */
78 CAM_DIR_NONE = 0x000000C0,/* Data direction (11:no data) */
79 CAM_DIR_MASK = 0x000000C0,/* Data direction Mask */
80 CAM_DATA_VADDR = 0x00000000,/* Data type (000:Virtual) */
81 CAM_DATA_PADDR = 0x00000010,/* Data type (001:Physical) */
82 CAM_DATA_SG = 0x00040000,/* Data type (010:sglist) */
83 CAM_DATA_SG_PADDR = 0x00040010,/* Data type (011:sglist phys) */
84 CAM_DATA_BIO = 0x00200000,/* Data type (100:bio) */
85 CAM_DATA_MASK = 0x00240010,/* Data type mask */
86 CAM_unused3 = 0x00000100,
87 CAM_unused4 = 0x00000200,
88 CAM_DEV_QFRZDIS = 0x00000400,/* Disable DEV Q freezing */
89 CAM_DEV_QFREEZE = 0x00000800,/* Freeze DEV Q on execution */
90 CAM_HIGH_POWER = 0x00001000,/* Command takes a lot of power */
91 CAM_SENSE_PTR = 0x00002000,/* Sense data is a pointer */
92 CAM_SENSE_PHYS = 0x00004000,/* Sense pointer is physical addr*/
93 CAM_TAG_ACTION_VALID = 0x00008000,/* Use the tag action in this ccb*/
94 CAM_PASS_ERR_RECOVER = 0x00010000,/* Pass driver does err. recovery*/
95 CAM_DIS_DISCONNECT = 0x00020000,/* Disable disconnect */
96 CAM_unused5 = 0x00080000,
97 CAM_unused6 = 0x00100000,
98 CAM_CDB_PHYS = 0x00400000,/* CDB poiner is physical */
99 CAM_unused7 = 0x00800000,
100
101 /* Phase cognizant mode flags */
102 CAM_unused8 = 0x01000000,
103 CAM_unused9 = 0x02000000,
104 CAM_unused10 = 0x04000000,
105 CAM_unused11 = 0x08000000,
106 CAM_unused12 = 0x10000000,
107 CAM_unused13 = 0x20000000,
108 CAM_unused14 = 0x40000000,
109
110 /* Host target Mode flags */
111 CAM_SEND_SENSE = 0x08000000,/* Send sense data with status */
112 CAM_unused15 = 0x10000000,
113 CAM_unused16 = 0x20000000,
114 CAM_SEND_STATUS = 0x40000000,/* Send status after data phase */
115
116 CAM_UNLOCKED = 0x80000000 /* Call callback without lock. */
117 } ccb_flags;
118
119 typedef enum {
120 CAM_USER_DATA_ADDR = 0x00000002,/* Userspace data pointers */
121 CAM_SG_FORMAT_IOVEC = 0x00000004,/* iovec instead of busdma S/G*/
122 CAM_UNMAPPED_BUF = 0x00000008 /* use unmapped I/O */
123 } ccb_xflags;
124
125 /* XPT Opcodes for xpt_action */
126 typedef enum {
127 /* Function code flags are bits greater than 0xff */
128 XPT_FC_QUEUED = 0x100,
129 /* Non-immediate function code */
130 XPT_FC_USER_CCB = 0x200,
131 XPT_FC_XPT_ONLY = 0x400,
132 /* Only for the transport layer device */
133 XPT_FC_DEV_QUEUED = 0x800 | XPT_FC_QUEUED,
134 /* Passes through the device queues */
135 /* Common function commands: 0x00->0x0F */
136 XPT_NOOP = 0x00,
137 /* Execute Nothing */
138 XPT_SCSI_IO = 0x01 | XPT_FC_DEV_QUEUED,
139 /* Execute the requested I/O operation */
140 XPT_GDEV_TYPE = 0x02,
141 /* Get type information for specified device */
142 XPT_GDEVLIST = 0x03,
143 /* Get a list of peripheral devices */
144 XPT_PATH_INQ = 0x04,
145 /* Path routing inquiry */
146 XPT_REL_SIMQ = 0x05,
147 /* Release a frozen device queue */
148 XPT_SASYNC_CB = 0x06,
149 /* Set Asynchronous Callback Parameters */
150 XPT_SDEV_TYPE = 0x07,
151 /* Set device type information */
152 XPT_SCAN_BUS = 0x08 | XPT_FC_QUEUED | XPT_FC_USER_CCB
153 | XPT_FC_XPT_ONLY,
154 /* (Re)Scan the SCSI Bus */
155 XPT_DEV_MATCH = 0x09 | XPT_FC_XPT_ONLY,
156 /* Get EDT entries matching the given pattern */
157 XPT_DEBUG = 0x0a,
158 /* Turn on debugging for a bus, target or lun */
159 XPT_PATH_STATS = 0x0b,
160 /* Path statistics (error counts, etc.) */
161 XPT_GDEV_STATS = 0x0c,
162 /* Device statistics (error counts, etc.) */
163 XPT_DEV_ADVINFO = 0x0e,
164 /* Get/Set Device advanced information */
165 XPT_ASYNC = 0x0f | XPT_FC_QUEUED | XPT_FC_USER_CCB
166 | XPT_FC_XPT_ONLY,
167 /* Asynchronous event */
168 /* SCSI Control Functions: 0x10->0x1F */
169 XPT_ABORT = 0x10,
170 /* Abort the specified CCB */
171 XPT_RESET_BUS = 0x11 | XPT_FC_XPT_ONLY,
172 /* Reset the specified SCSI bus */
173 XPT_RESET_DEV = 0x12 | XPT_FC_DEV_QUEUED,
174 /* Bus Device Reset the specified SCSI device */
175 XPT_TERM_IO = 0x13,
176 /* Terminate the I/O process */
177 XPT_SCAN_LUN = 0x14 | XPT_FC_QUEUED | XPT_FC_USER_CCB
178 | XPT_FC_XPT_ONLY,
179 /* Scan Logical Unit */
180 XPT_GET_TRAN_SETTINGS = 0x15,
181 /*
182 * Get default/user transfer settings
183 * for the target
184 */
185 XPT_SET_TRAN_SETTINGS = 0x16,
186 /*
187 * Set transfer rate/width
188 * negotiation settings
189 */
190 XPT_CALC_GEOMETRY = 0x17,
191 /*
192 * Calculate the geometry parameters for
193 * a device give the sector size and
194 * volume size.
195 */
196 XPT_ATA_IO = 0x18 | XPT_FC_DEV_QUEUED,
197 /* Execute the requested ATA I/O operation */
198
199 XPT_GET_SIM_KNOB_OLD = 0x18, /* Compat only */
200
201 XPT_SET_SIM_KNOB = 0x19,
202 /*
203 * Set SIM specific knob values.
204 */
205
206 XPT_GET_SIM_KNOB = 0x1a,
207 /*
208 * Get SIM specific knob values.
209 */
210
211 XPT_SMP_IO = 0x1b | XPT_FC_DEV_QUEUED,
212 /* Serial Management Protocol */
213
214 XPT_NVME_IO = 0x1c | XPT_FC_DEV_QUEUED,
215 /* Execute the requested NVMe I/O operation */
216
217 XPT_MMC_IO = 0x1d | XPT_FC_DEV_QUEUED,
218 /* Placeholder for MMC / SD / SDIO I/O stuff */
219
220 XPT_SCAN_TGT = 0x1e | XPT_FC_QUEUED | XPT_FC_USER_CCB
221 | XPT_FC_XPT_ONLY,
222 /* Scan Target */
223
224 XPT_NVME_ADMIN = 0x1f | XPT_FC_DEV_QUEUED,
225 /* Execute the requested NVMe Admin operation */
226
227 /* HBA engine commands 0x20->0x2F */
228 XPT_ENG_INQ = 0x20 | XPT_FC_XPT_ONLY,
229 /* HBA engine feature inquiry */
230 XPT_ENG_EXEC = 0x21 | XPT_FC_DEV_QUEUED,
231 /* HBA execute engine request */
232
233 /* Target mode commands: 0x30->0x3F */
234 XPT_EN_LUN = 0x30,
235 /* Enable LUN as a target */
236 XPT_TARGET_IO = 0x31 | XPT_FC_DEV_QUEUED,
237 /* Execute target I/O request */
238 XPT_ACCEPT_TARGET_IO = 0x32 | XPT_FC_QUEUED | XPT_FC_USER_CCB,
239 /* Accept Host Target Mode CDB */
240 XPT_CONT_TARGET_IO = 0x33 | XPT_FC_DEV_QUEUED,
241 /* Continue Host Target I/O Connection */
242 XPT_IMMED_NOTIFY = 0x34 | XPT_FC_QUEUED | XPT_FC_USER_CCB,
243 /* Notify Host Target driver of event (obsolete) */
244 XPT_NOTIFY_ACK = 0x35,
245 /* Acknowledgement of event (obsolete) */
246 XPT_IMMEDIATE_NOTIFY = 0x36 | XPT_FC_QUEUED | XPT_FC_USER_CCB,
247 /* Notify Host Target driver of event */
248 XPT_NOTIFY_ACKNOWLEDGE = 0x37 | XPT_FC_QUEUED | XPT_FC_USER_CCB,
249 /* Acknowledgement of event */
250 XPT_REPROBE_LUN = 0x38 | XPT_FC_QUEUED | XPT_FC_USER_CCB,
251 /* Query device capacity and notify GEOM */
252
253 XPT_MMC_SET_TRAN_SETTINGS = 0x40 | XPT_FC_DEV_QUEUED,
254 XPT_MMC_GET_TRAN_SETTINGS = 0x41 | XPT_FC_DEV_QUEUED,
255
256 /* Vendor Unique codes: 0x80->0x8F */
257 XPT_VUNIQUE = 0x80
258 } xpt_opcode;
259
260 #define XPT_FC_GROUP_MASK 0xF0
261 #define XPT_FC_GROUP(op) ((op) & XPT_FC_GROUP_MASK)
262 #define XPT_FC_GROUP_COMMON 0x00
263 #define XPT_FC_GROUP_SCSI_CONTROL 0x10
264 #define XPT_FC_GROUP_HBA_ENGINE 0x20
265 #define XPT_FC_GROUP_TMODE 0x30
266 #define XPT_FC_GROUP_VENDOR_UNIQUE 0x80
267
268 #define XPT_FC_IS_DEV_QUEUED(ccb) \
269 (((ccb)->ccb_h.func_code & XPT_FC_DEV_QUEUED) == XPT_FC_DEV_QUEUED)
270 #define XPT_FC_IS_QUEUED(ccb) \
271 (((ccb)->ccb_h.func_code & XPT_FC_QUEUED) != 0)
272
273 typedef enum {
274 PROTO_UNKNOWN,
275 PROTO_UNSPECIFIED,
276 PROTO_SCSI, /* Small Computer System Interface */
277 PROTO_ATA, /* AT Attachment */
278 PROTO_ATAPI, /* AT Attachment Packetized Interface */
279 PROTO_SATAPM, /* SATA Port Multiplier */
280 PROTO_SEMB, /* SATA Enclosure Management Bridge */
281 PROTO_NVME, /* NVME */
282 PROTO_MMCSD, /* MMC, SD, SDIO */
283 } cam_proto;
284
285 typedef enum {
286 XPORT_UNKNOWN,
287 XPORT_UNSPECIFIED,
288 XPORT_SPI, /* SCSI Parallel Interface */
289 XPORT_FC, /* Fiber Channel */
290 XPORT_SSA, /* Serial Storage Architecture */
291 XPORT_USB, /* Universal Serial Bus */
292 XPORT_PPB, /* Parallel Port Bus */
293 XPORT_ATA, /* AT Attachment */
294 XPORT_SAS, /* Serial Attached SCSI */
295 XPORT_SATA, /* Serial AT Attachment */
296 XPORT_ISCSI, /* iSCSI */
297 XPORT_SRP, /* SCSI RDMA Protocol */
298 XPORT_NVME, /* NVMe over PCIe */
299 XPORT_MMCSD, /* MMC, SD, SDIO card */
300 XPORT_NVMF, /* NVMe over Fabrics */
301 XPORT_UFSHCI, /* Universal Flash Storage Host Interface */
302 } cam_xport;
303
304 #define XPORT_IS_NVME(t) ((t) == XPORT_NVME || (t) == XPORT_NVMF)
305 #define XPORT_IS_ATA(t) ((t) == XPORT_ATA || (t) == XPORT_SATA)
306 #define XPORT_IS_SCSI(t) ((t) != XPORT_UNKNOWN && \
307 (t) != XPORT_UNSPECIFIED && \
308 !XPORT_IS_ATA(t) && !XPORT_IS_NVME(t))
309 #define XPORT_DEVSTAT_TYPE(t) (XPORT_IS_ATA(t) ? DEVSTAT_TYPE_IF_IDE : \
310 XPORT_IS_SCSI(t) ? DEVSTAT_TYPE_IF_SCSI : \
311 XPORT_IS_NVME(t) ? DEVSTAT_TYPE_IF_NVME : \
312 DEVSTAT_TYPE_IF_OTHER)
313
314 #define PROTO_VERSION_UNKNOWN (UINT_MAX - 1)
315 #define PROTO_VERSION_UNSPECIFIED UINT_MAX
316 #define XPORT_VERSION_UNKNOWN (UINT_MAX - 1)
317 #define XPORT_VERSION_UNSPECIFIED UINT_MAX
318
319 typedef union {
320 LIST_ENTRY(ccb_hdr) le;
321 SLIST_ENTRY(ccb_hdr) sle;
322 TAILQ_ENTRY(ccb_hdr) tqe;
323 STAILQ_ENTRY(ccb_hdr) stqe;
324 } camq_entry;
325
326 typedef union {
327 void *ptr;
328 u_long field;
329 uint8_t bytes[sizeof(uintptr_t)];
330 } ccb_priv_entry;
331
332 typedef union {
333 ccb_priv_entry entries[CCB_PERIPH_PRIV_SIZE];
334 uint8_t bytes[CCB_PERIPH_PRIV_SIZE * sizeof(ccb_priv_entry)];
335 } ccb_ppriv_area;
336
337 typedef union {
338 ccb_priv_entry entries[CCB_SIM_PRIV_SIZE];
339 uint8_t bytes[CCB_SIM_PRIV_SIZE * sizeof(ccb_priv_entry)];
340 } ccb_spriv_area;
341
342 typedef struct {
343 struct timeval *etime;
344 uintptr_t sim_data;
345 uintptr_t periph_data;
346 } ccb_qos_area;
347
348 struct ccb_hdr {
349 cam_pinfo pinfo; /* Info for priority scheduling */
350 camq_entry xpt_links; /* For chaining in the XPT layer */
351 camq_entry sim_links; /* For chaining in the SIM layer */
352 camq_entry periph_links; /* For chaining in the type driver */
353 #if BYTE_ORDER == LITTLE_ENDIAN
354 uint16_t retry_count;
355 uint16_t alloc_flags; /* ccb_alloc_flags */
356 #else
357 uint16_t alloc_flags; /* ccb_alloc_flags */
358 uint16_t retry_count;
359 #endif
360 void (*cbfcnp)(struct cam_periph *, union ccb *);
361 /* Callback on completion function */
362 xpt_opcode func_code; /* XPT function code */
363 uint32_t status; /* Status returned by CAM subsystem */
364 struct cam_path *path; /* Compiled path for this ccb */
365 path_id_t path_id; /* Path ID for the request */
366 target_id_t target_id; /* Target device ID */
367 lun_id_t target_lun; /* Target LUN number */
368 uint32_t flags; /* ccb_flags */
369 uint32_t xflags; /* Extended flags */
370 ccb_ppriv_area periph_priv;
371 ccb_spriv_area sim_priv;
372 ccb_qos_area qos;
373 uint32_t timeout; /* Hard timeout value in mseconds */
374 struct timeval softtimeout; /* Soft timeout value in sec + usec */
375 };
376
377 /* Get Device Information CCB */
378 struct ccb_getdev {
379 struct ccb_hdr ccb_h;
380 cam_proto protocol;
381 struct scsi_inquiry_data inq_data;
382 struct ata_params ident_data;
383 uint8_t serial_num[252];
384 uint8_t inq_flags;
385 uint8_t serial_num_len;
386 void *padding[2];
387 };
388
389 /* Device Statistics CCB */
390 struct ccb_getdevstats {
391 struct ccb_hdr ccb_h;
392 int dev_openings; /* Space left for more work on device*/
393 int dev_active; /* Transactions running on the device */
394 int allocated; /* CCBs allocated for the device */
395 int queued; /* CCBs queued to be sent to the device */
396 int held; /*
397 * CCBs held by peripheral drivers
398 * for this device
399 */
400 int maxtags; /*
401 * Boundary conditions for number of
402 * tagged operations
403 */
404 int mintags;
405 struct timeval last_reset; /* Time of last bus reset/loop init */
406 };
407
408 typedef enum {
409 CAM_GDEVLIST_LAST_DEVICE,
410 CAM_GDEVLIST_LIST_CHANGED,
411 CAM_GDEVLIST_MORE_DEVS,
412 CAM_GDEVLIST_ERROR
413 } ccb_getdevlist_status_e;
414
415 struct ccb_getdevlist {
416 struct ccb_hdr ccb_h;
417 char periph_name[DEV_IDLEN];
418 uint32_t unit_number;
419 unsigned int generation;
420 uint32_t index;
421 ccb_getdevlist_status_e status;
422 };
423
424 typedef enum {
425 PERIPH_MATCH_ANY = 0x000,
426 PERIPH_MATCH_PATH = 0x001,
427 PERIPH_MATCH_TARGET = 0x002,
428 PERIPH_MATCH_LUN = 0x004,
429 PERIPH_MATCH_NAME = 0x008,
430 PERIPH_MATCH_UNIT = 0x010,
431 } periph_pattern_flags;
432
433 struct periph_match_pattern {
434 char periph_name[DEV_IDLEN];
435 uint32_t unit_number;
436 path_id_t path_id;
437 target_id_t target_id;
438 lun_id_t target_lun;
439 periph_pattern_flags flags;
440 };
441
442 typedef enum {
443 DEV_MATCH_ANY = 0x000,
444 DEV_MATCH_PATH = 0x001,
445 DEV_MATCH_TARGET = 0x002,
446 DEV_MATCH_LUN = 0x004,
447 DEV_MATCH_INQUIRY = 0x008,
448 DEV_MATCH_DEVID = 0x010,
449 } dev_pattern_flags;
450
451 struct device_id_match_pattern {
452 uint8_t id_len;
453 uint8_t id[256];
454 };
455
456 struct device_match_pattern {
457 path_id_t path_id;
458 target_id_t target_id;
459 lun_id_t target_lun;
460 dev_pattern_flags flags;
461 union {
462 struct scsi_static_inquiry_pattern inq_pat;
463 struct device_id_match_pattern devid_pat;
464 } data;
465 };
466
467 typedef enum {
468 BUS_MATCH_ANY = 0x000,
469 BUS_MATCH_PATH = 0x001,
470 BUS_MATCH_NAME = 0x002,
471 BUS_MATCH_UNIT = 0x004,
472 BUS_MATCH_BUS_ID = 0x008,
473 } bus_pattern_flags;
474
475 struct bus_match_pattern {
476 path_id_t path_id;
477 char dev_name[DEV_IDLEN];
478 uint32_t unit_number;
479 uint32_t bus_id;
480 bus_pattern_flags flags;
481 };
482
483 union match_pattern {
484 struct periph_match_pattern periph_pattern;
485 struct device_match_pattern device_pattern;
486 struct bus_match_pattern bus_pattern;
487 };
488
489 typedef enum {
490 DEV_MATCH_PERIPH,
491 DEV_MATCH_DEVICE,
492 DEV_MATCH_BUS
493 } dev_match_type;
494
495 struct dev_match_pattern {
496 dev_match_type type;
497 union match_pattern pattern;
498 };
499
500 struct periph_match_result {
501 char periph_name[DEV_IDLEN];
502 uint32_t unit_number;
503 path_id_t path_id;
504 target_id_t target_id;
505 lun_id_t target_lun;
506 };
507
508 typedef enum {
509 DEV_RESULT_NOFLAG = 0x00,
510 DEV_RESULT_UNCONFIGURED = 0x01
511 } dev_result_flags;
512
513 struct device_match_result {
514 path_id_t path_id;
515 target_id_t target_id;
516 lun_id_t target_lun;
517 cam_proto protocol;
518 struct scsi_inquiry_data inq_data;
519 struct ata_params ident_data;
520 dev_result_flags flags;
521 };
522
523 struct bus_match_result {
524 path_id_t path_id;
525 char dev_name[DEV_IDLEN];
526 uint32_t unit_number;
527 uint32_t bus_id;
528 };
529
530 union match_result {
531 struct periph_match_result periph_result;
532 struct device_match_result device_result;
533 struct bus_match_result bus_result;
534 };
535
536 struct dev_match_result {
537 dev_match_type type;
538 union match_result result;
539 };
540
541 typedef enum {
542 CAM_DEV_MATCH_LAST,
543 CAM_DEV_MATCH_MORE,
544 CAM_DEV_MATCH_LIST_CHANGED,
545 CAM_DEV_MATCH_SIZE_ERROR,
546 CAM_DEV_MATCH_ERROR
547 } ccb_dev_match_status;
548
549 typedef enum {
550 CAM_DEV_POS_NONE = 0x000,
551 CAM_DEV_POS_BUS = 0x001,
552 CAM_DEV_POS_TARGET = 0x002,
553 CAM_DEV_POS_DEVICE = 0x004,
554 CAM_DEV_POS_PERIPH = 0x008,
555 CAM_DEV_POS_PDPTR = 0x010,
556 CAM_DEV_POS_TYPEMASK = 0xf00,
557 CAM_DEV_POS_EDT = 0x100,
558 CAM_DEV_POS_PDRV = 0x200
559 } dev_pos_type;
560
561 struct ccb_dm_cookie {
562 void *bus;
563 void *target;
564 void *device;
565 void *periph;
566 void *pdrv;
567 };
568
569 struct ccb_dev_position {
570 u_int generations[4];
571 #define CAM_BUS_GENERATION 0x00
572 #define CAM_TARGET_GENERATION 0x01
573 #define CAM_DEV_GENERATION 0x02
574 #define CAM_PERIPH_GENERATION 0x03
575 dev_pos_type position_type;
576 struct ccb_dm_cookie cookie;
577 };
578
579 struct ccb_dev_match {
580 struct ccb_hdr ccb_h;
581 ccb_dev_match_status status;
582 uint32_t num_patterns;
583 uint32_t pattern_buf_len;
584 struct dev_match_pattern *patterns;
585 uint32_t num_matches;
586 uint32_t match_buf_len;
587 struct dev_match_result *matches;
588 struct ccb_dev_position pos;
589 };
590
591 /*
592 * Definitions for the path inquiry CCB fields.
593 */
594 #define CAM_VERSION 0x1a /* Hex value for current version */
595
596 typedef enum {
597 PI_MDP_ABLE = 0x80, /* Supports MDP message */
598 PI_WIDE_32 = 0x40, /* Supports 32 bit wide SCSI */
599 PI_WIDE_16 = 0x20, /* Supports 16 bit wide SCSI */
600 PI_SDTR_ABLE = 0x10, /* Supports SDTR message */
601 PI_LINKED_CDB = 0x08, /* Supports linked CDBs */
602 PI_SATAPM = 0x04, /* Supports SATA PM */
603 PI_TAG_ABLE = 0x02, /* Supports tag queue messages */
604 PI_SOFT_RST = 0x01 /* Supports soft reset alternative */
605 } pi_inqflag;
606
607 typedef enum {
608 PIT_PROCESSOR = 0x80, /* Target mode processor mode */
609 PIT_PHASE = 0x40, /* Target mode phase cog. mode */
610 PIT_DISCONNECT = 0x20, /* Disconnects supported in target mode */
611 PIT_TERM_IO = 0x10, /* Terminate I/O message supported in TM */
612 PIT_GRP_6 = 0x08, /* Group 6 commands supported */
613 PIT_GRP_7 = 0x04 /* Group 7 commands supported */
614 } pi_tmflag;
615
616 typedef enum {
617 PIM_ATA_EXT = 0x200,/* ATA requests can understand ata_ext requests */
618 PIM_EXTLUNS = 0x100,/* 64bit extended LUNs supported */
619 PIM_SCANHILO = 0x80, /* Bus scans from high ID to low ID */
620 PIM_NOREMOVE = 0x40, /* Removeable devices not included in scan */
621 PIM_NOINITIATOR = 0x20, /* Initiator role not supported. */
622 PIM_NOBUSRESET = 0x10, /* User has disabled initial BUS RESET */
623 PIM_NO_6_BYTE = 0x08, /* Do not send 6-byte commands */
624 PIM_SEQSCAN = 0x04, /* Do bus scans sequentially, not in parallel */
625 PIM_UNMAPPED = 0x02,
626 PIM_NOSCAN = 0x01 /* SIM does its own scanning */
627 } pi_miscflag;
628
629 /* Path Inquiry CCB */
630 struct ccb_pathinq_settings_spi {
631 uint8_t ppr_options;
632 };
633
634 struct ccb_pathinq_settings_fc {
635 uint64_t wwnn; /* world wide node name */
636 uint64_t wwpn; /* world wide port name */
637 uint32_t port; /* 24 bit port id, if known */
638 uint32_t bitrate; /* Mbps */
639 };
640
641 struct ccb_pathinq_settings_sas {
642 uint32_t bitrate; /* Mbps */
643 };
644
645 #define NVME_DEV_NAME_LEN 52
646 struct ccb_pathinq_settings_nvme {
647 uint32_t nsid; /* Namespace ID for this path */
648 uint32_t domain;
649 uint8_t bus;
650 uint8_t slot;
651 uint8_t function;
652 uint8_t extra;
653 char dev_name[NVME_DEV_NAME_LEN]; /* nvme controller dev name for this device */
654 };
655 _Static_assert(sizeof(struct ccb_pathinq_settings_nvme) == 64,
656 "ccb_pathinq_settings_nvme too big");
657
658 struct ccb_pathinq_settings_nvmf {
659 uint32_t nsid; /* Namespace ID for this path */
660 uint8_t trtype;
661 char dev_name[NVME_DEV_NAME_LEN]; /* nvme controller dev name for this device */
662 };
663
664 #define PATHINQ_SETTINGS_SIZE 128
665
666 struct ccb_pathinq {
667 struct ccb_hdr ccb_h;
668 uint8_t version_num; /* Version number for the SIM/HBA */
669 uint8_t hba_inquiry; /* Mimic of INQ byte 7 for the HBA */
670 uint16_t target_sprt; /* Flags for target mode support */
671 uint32_t hba_misc; /* Misc HBA features */
672 uint16_t hba_eng_cnt; /* HBA engine count */
673 /* Vendor Unique capabilities */
674 uint8_t vuhba_flags[VUHBALEN];
675 uint32_t max_target; /* Maximum supported Target */
676 uint32_t max_lun; /* Maximum supported Lun */
677 uint32_t async_flags; /* Installed Async handlers */
678 path_id_t hpath_id; /* Highest Path ID in the subsystem */
679 target_id_t initiator_id; /* ID of the HBA on the SCSI bus */
680 char sim_vid[SIM_IDLEN]; /* Vendor ID of the SIM */
681 char hba_vid[HBA_IDLEN]; /* Vendor ID of the HBA */
682 char dev_name[DEV_IDLEN];/* Device name for SIM */
683 uint32_t unit_number; /* Unit number for SIM */
684 uint32_t bus_id; /* Bus ID for SIM */
685 uint32_t base_transfer_speed;/* Base bus speed in KB/sec */
686 cam_proto protocol;
687 u_int protocol_version;
688 cam_xport transport;
689 u_int transport_version;
690 union {
691 struct ccb_pathinq_settings_spi spi;
692 struct ccb_pathinq_settings_fc fc;
693 struct ccb_pathinq_settings_sas sas;
694 struct ccb_pathinq_settings_nvme nvme;
695 struct ccb_pathinq_settings_nvmf nvmf;
696 char ccb_pathinq_settings_opaque[PATHINQ_SETTINGS_SIZE];
697 } xport_specific;
698 u_int maxio; /* Max supported I/O size, in bytes. */
699 uint16_t hba_vendor; /* HBA vendor ID */
700 uint16_t hba_device; /* HBA device ID */
701 uint16_t hba_subvendor; /* HBA subvendor ID */
702 uint16_t hba_subdevice; /* HBA subdevice ID */
703 };
704
705 /* Path Statistics CCB */
706 struct ccb_pathstats {
707 struct ccb_hdr ccb_h;
708 struct timeval last_reset; /* Time of last bus reset/loop init */
709 };
710
711 typedef enum {
712 SMP_FLAG_NONE = 0x00,
713 SMP_FLAG_REQ_SG = 0x01,
714 SMP_FLAG_RSP_SG = 0x02
715 } ccb_smp_pass_flags;
716
717 /*
718 * Serial Management Protocol CCB
719 * XXX Currently the semantics for this CCB are that it is executed either
720 * by the addressed device, or that device's parent (i.e. an expander for
721 * any device on an expander) if the addressed device doesn't support SMP.
722 * Later, once we have the ability to probe SMP-only devices and put them
723 * in CAM's topology, the CCB will only be executed by the addressed device
724 * if possible.
725 */
726 struct ccb_smpio {
727 struct ccb_hdr ccb_h;
728 uint8_t *smp_request;
729 int smp_request_len;
730 uint16_t smp_request_sglist_cnt;
731 uint8_t *smp_response;
732 int smp_response_len;
733 uint16_t smp_response_sglist_cnt;
734 ccb_smp_pass_flags flags;
735 };
736
737 typedef union {
738 uint8_t *sense_ptr; /*
739 * Pointer to storage
740 * for sense information
741 */
742 /* Storage Area for sense information */
743 struct scsi_sense_data sense_buf;
744 } sense_t;
745
746 typedef union {
747 uint8_t *cdb_ptr; /* Pointer to the CDB bytes to send */
748 /* Area for the CDB send */
749 uint8_t cdb_bytes[IOCDBLEN];
750 } cdb_t;
751
752 /*
753 * SCSI I/O Request CCB used for the XPT_SCSI_IO and XPT_CONT_TARGET_IO
754 * function codes.
755 */
756 struct ccb_scsiio {
757 struct ccb_hdr ccb_h;
758 union ccb *next_ccb; /* Ptr for next CCB for action */
759 uint8_t *req_map; /* Ptr to mapping info */
760 uint8_t *data_ptr; /* Ptr to the data buf/SG list */
761 uint32_t dxfer_len; /* Data transfer length */
762 /* Autosense storage */
763 struct scsi_sense_data sense_data;
764 uint8_t sense_len; /* Number of bytes to autosense */
765 uint8_t cdb_len; /* Number of bytes for the CDB */
766 uint16_t sglist_cnt; /* Number of SG list entries */
767 uint8_t scsi_status; /* Returned SCSI status */
768 uint8_t sense_resid; /* Autosense resid length: 2's comp */
769 uint32_t resid; /* Transfer residual length: 2's comp */
770 cdb_t cdb_io; /* Union for CDB bytes/pointer */
771 uint8_t *msg_ptr; /* Pointer to the message buffer */
772 uint16_t msg_len; /* Number of bytes for the Message */
773 uint8_t tag_action; /* What to do for tag queueing */
774 /*
775 * The tag action should be either the define below (to send a
776 * non-tagged transaction) or one of the defined scsi tag messages
777 * from scsi_message.h.
778 */
779 #define CAM_TAG_ACTION_NONE 0x00
780 uint8_t priority; /* Command priority for SIMPLE tag */
781 u_int tag_id; /* tag id from initator (target mode) */
782 u_int init_id; /* initiator id of who selected */
783 #if defined(BUF_TRACKING) || defined(FULL_BUF_TRACKING)
784 struct bio *bio; /* Associated bio */
785 #endif
786 };
787
788 static __inline uint8_t *
scsiio_cdb_ptr(struct ccb_scsiio * ccb)789 scsiio_cdb_ptr(struct ccb_scsiio *ccb)
790 {
791 return ((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
792 ccb->cdb_io.cdb_ptr : ccb->cdb_io.cdb_bytes);
793 }
794
795 /*
796 * ATA I/O Request CCB used for the XPT_ATA_IO function code.
797 */
798 struct ccb_ataio {
799 struct ccb_hdr ccb_h;
800 union ccb *next_ccb; /* Ptr for next CCB for action */
801 struct ata_cmd cmd; /* ATA command register set */
802 struct ata_res res; /* ATA result register set */
803 uint8_t *data_ptr; /* Ptr to the data buf/SG list */
804 uint32_t dxfer_len; /* Data transfer length */
805 uint32_t resid; /* Transfer residual length: 2's comp */
806 uint8_t ata_flags; /* Flags for the rest of the buffer */
807 #define ATA_FLAG_AUX 0x1
808 #define ATA_FLAG_ICC 0x2
809 uint8_t icc; /* Isochronous Command Completion */
810 uint32_t aux;
811 uint32_t unused;
812 };
813
814 /*
815 * MMC I/O Request CCB used for the XPT_MMC_IO function code.
816 */
817 struct ccb_mmcio {
818 struct ccb_hdr ccb_h;
819 union ccb *next_ccb; /* Ptr for next CCB for action */
820 struct mmc_command cmd;
821 struct mmc_command stop;
822 };
823
824 struct ccb_accept_tio {
825 struct ccb_hdr ccb_h;
826 cdb_t cdb_io; /* Union for CDB bytes/pointer */
827 uint8_t cdb_len; /* Number of bytes for the CDB */
828 uint8_t tag_action; /* What to do for tag queueing */
829 uint8_t sense_len; /* Number of bytes of Sense Data */
830 uint8_t priority; /* Command priority for SIMPLE tag */
831 u_int tag_id; /* tag id from initator (target mode) */
832 u_int init_id; /* initiator id of who selected */
833 struct scsi_sense_data sense_data;
834 };
835
836 static __inline uint8_t *
atio_cdb_ptr(struct ccb_accept_tio * ccb)837 atio_cdb_ptr(struct ccb_accept_tio *ccb)
838 {
839 return ((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
840 ccb->cdb_io.cdb_ptr : ccb->cdb_io.cdb_bytes);
841 }
842
843 /* Release SIM Queue */
844 struct ccb_relsim {
845 struct ccb_hdr ccb_h;
846 uint32_t release_flags;
847 #define RELSIM_ADJUST_OPENINGS 0x01
848 #define RELSIM_RELEASE_AFTER_TIMEOUT 0x02
849 #define RELSIM_RELEASE_AFTER_CMDCMPLT 0x04
850 #define RELSIM_RELEASE_AFTER_QEMPTY 0x08
851 uint32_t openings;
852 uint32_t release_timeout; /* Abstract argument. */
853 uint32_t qfrozen_cnt;
854 };
855
856 /*
857 * NVMe I/O Request CCB used for the XPT_NVME_IO and XPT_NVME_ADMIN function codes.
858 */
859 struct ccb_nvmeio {
860 struct ccb_hdr ccb_h;
861 union ccb *next_ccb; /* Ptr for next CCB for action */
862 struct nvme_command cmd; /* NVME command, per NVME standard */
863 struct nvme_completion cpl; /* NVME completion, per NVME standard */
864 uint8_t *data_ptr; /* Ptr to the data buf/SG list */
865 uint32_t dxfer_len; /* Data transfer length */
866 uint16_t sglist_cnt; /* Number of SG list entries */
867 uint16_t unused; /* padding for removed uint32_t */
868 };
869
870 /*
871 * Definitions for the asynchronous callback CCB fields.
872 */
873 typedef enum {
874 AC_UNIT_ATTENTION = 0x4000,/* Device reported UNIT ATTENTION */
875 AC_ADVINFO_CHANGED = 0x2000,/* Advance info might have changes */
876 AC_CONTRACT = 0x1000,/* A contractual callback */
877 AC_GETDEV_CHANGED = 0x800,/* Getdev info might have changed */
878 AC_INQ_CHANGED = 0x400,/* Inquiry info might have changed */
879 AC_TRANSFER_NEG = 0x200,/* New transfer settings in effect */
880 AC_LOST_DEVICE = 0x100,/* A device went away */
881 AC_FOUND_DEVICE = 0x080,/* A new device was found */
882 AC_PATH_DEREGISTERED = 0x040,/* A path has de-registered */
883 AC_PATH_REGISTERED = 0x020,/* A new path has been registered */
884 AC_SENT_BDR = 0x010,/* A BDR message was sent to target */
885 AC_SCSI_AEN = 0x008,/* A SCSI AEN has been received */
886 AC_UNSOL_RESEL = 0x002,/* Unsolicited reselection occurred */
887 AC_BUS_RESET = 0x001 /* A SCSI bus reset occurred */
888 } ac_code;
889
890 typedef void ac_callback_t (void *softc, uint32_t code,
891 struct cam_path *path, void *args);
892
893 /*
894 * Generic Asynchronous callbacks.
895 *
896 * Generic arguments passed bac which are then interpreted between a per-system
897 * contract number.
898 */
899 #define AC_CONTRACT_DATA_MAX (128 - sizeof (uint64_t))
900 struct ac_contract {
901 uint64_t contract_number;
902 uint8_t contract_data[AC_CONTRACT_DATA_MAX];
903 };
904
905 #define AC_CONTRACT_DEV_CHG 1
906 struct ac_device_changed {
907 uint64_t wwpn;
908 uint32_t port;
909 target_id_t target;
910 uint8_t arrived;
911 };
912
913 /* Set Asynchronous Callback CCB */
914 struct ccb_setasync {
915 struct ccb_hdr ccb_h;
916 uint32_t event_enable; /* Async Event enables */
917 ac_callback_t *callback;
918 void *callback_arg;
919 };
920
921 /* Set Device Type CCB */
922 struct ccb_setdev {
923 struct ccb_hdr ccb_h;
924 uint8_t dev_type; /* Value for dev type field in EDT */
925 };
926
927 /* SCSI Control Functions */
928
929 /* Abort XPT request CCB */
930 struct ccb_abort {
931 struct ccb_hdr ccb_h;
932 union ccb *abort_ccb; /* Pointer to CCB to abort */
933 };
934
935 /* Reset SCSI Bus CCB */
936 struct ccb_resetbus {
937 struct ccb_hdr ccb_h;
938 };
939
940 /* Reset SCSI Device CCB */
941 struct ccb_resetdev {
942 struct ccb_hdr ccb_h;
943 };
944
945 /* Terminate I/O Process Request CCB */
946 struct ccb_termio {
947 struct ccb_hdr ccb_h;
948 union ccb *termio_ccb; /* Pointer to CCB to terminate */
949 };
950
951 typedef enum {
952 CTS_TYPE_CURRENT_SETTINGS,
953 CTS_TYPE_USER_SETTINGS
954 } cts_type;
955
956 struct ccb_trans_settings_scsi
957 {
958 u_int valid; /* Which fields to honor */
959 #define CTS_SCSI_VALID_TQ 0x01
960 u_int flags;
961 #define CTS_SCSI_FLAGS_TAG_ENB 0x01
962 };
963
964 struct ccb_trans_settings_ata
965 {
966 u_int valid; /* Which fields to honor */
967 #define CTS_ATA_VALID_TQ 0x01
968 u_int flags;
969 #define CTS_ATA_FLAGS_TAG_ENB 0x01
970 };
971
972 struct ccb_trans_settings_spi
973 {
974 u_int valid; /* Which fields to honor */
975 #define CTS_SPI_VALID_SYNC_RATE 0x01
976 #define CTS_SPI_VALID_SYNC_OFFSET 0x02
977 #define CTS_SPI_VALID_BUS_WIDTH 0x04
978 #define CTS_SPI_VALID_DISC 0x08
979 #define CTS_SPI_VALID_PPR_OPTIONS 0x10
980 u_int flags;
981 #define CTS_SPI_FLAGS_DISC_ENB 0x01
982 u_int sync_period;
983 u_int sync_offset;
984 u_int bus_width;
985 u_int ppr_options;
986 };
987
988 struct ccb_trans_settings_fc {
989 u_int valid; /* Which fields to honor */
990 #define CTS_FC_VALID_WWNN 0x8000
991 #define CTS_FC_VALID_WWPN 0x4000
992 #define CTS_FC_VALID_PORT 0x2000
993 #define CTS_FC_VALID_SPEED 0x1000
994 uint64_t wwnn; /* world wide node name */
995 uint64_t wwpn; /* world wide port name */
996 uint32_t port; /* 24 bit port id, if known */
997 uint32_t bitrate; /* Mbps */
998 };
999
1000 struct ccb_trans_settings_sas {
1001 u_int valid; /* Which fields to honor */
1002 #define CTS_SAS_VALID_SPEED 0x1000
1003 uint32_t bitrate; /* Mbps */
1004 };
1005
1006 struct ccb_trans_settings_pata {
1007 u_int valid; /* Which fields to honor */
1008 #define CTS_ATA_VALID_MODE 0x01
1009 #define CTS_ATA_VALID_BYTECOUNT 0x02
1010 #define CTS_ATA_VALID_ATAPI 0x20
1011 #define CTS_ATA_VALID_CAPS 0x40
1012 int mode; /* Mode */
1013 u_int bytecount; /* Length of PIO transaction */
1014 u_int atapi; /* Length of ATAPI CDB */
1015 u_int caps; /* Device and host SATA caps. */
1016 #define CTS_ATA_CAPS_H 0x0000ffff
1017 #define CTS_ATA_CAPS_H_DMA48 0x00000001 /* 48-bit DMA */
1018 #define CTS_ATA_CAPS_D 0xffff0000
1019 };
1020
1021 struct ccb_trans_settings_sata {
1022 u_int valid; /* Which fields to honor */
1023 #define CTS_SATA_VALID_MODE 0x01
1024 #define CTS_SATA_VALID_BYTECOUNT 0x02
1025 #define CTS_SATA_VALID_REVISION 0x04
1026 #define CTS_SATA_VALID_PM 0x08
1027 #define CTS_SATA_VALID_TAGS 0x10
1028 #define CTS_SATA_VALID_ATAPI 0x20
1029 #define CTS_SATA_VALID_CAPS 0x40
1030 int mode; /* Legacy PATA mode */
1031 u_int bytecount; /* Length of PIO transaction */
1032 int revision; /* SATA revision */
1033 u_int pm_present; /* PM is present (XPT->SIM) */
1034 u_int tags; /* Number of allowed tags */
1035 u_int atapi; /* Length of ATAPI CDB */
1036 u_int caps; /* Device and host SATA caps. */
1037 #define CTS_SATA_CAPS_H 0x0000ffff
1038 #define CTS_SATA_CAPS_H_PMREQ 0x00000001
1039 #define CTS_SATA_CAPS_H_APST 0x00000002
1040 #define CTS_SATA_CAPS_H_DMAAA 0x00000010 /* Auto-activation */
1041 #define CTS_SATA_CAPS_H_AN 0x00000020 /* Async. notification */
1042 #define CTS_SATA_CAPS_D 0xffff0000
1043 #define CTS_SATA_CAPS_D_PMREQ 0x00010000
1044 #define CTS_SATA_CAPS_D_APST 0x00020000
1045 };
1046
1047 struct ccb_trans_settings_nvme
1048 {
1049 u_int valid; /* Which fields to honor */
1050 #define CTS_NVME_VALID_SPEC 0x01
1051 #define CTS_NVME_VALID_CAPS 0x02
1052 #define CTS_NVME_VALID_LINK 0x04
1053 uint32_t spec; /* NVMe spec implemented -- same as vs register */
1054 uint32_t max_xfer; /* Max transfer size (0 -> unlimited */
1055 uint32_t caps;
1056 uint8_t lanes; /* Number of PCIe lanes */
1057 uint8_t speed; /* PCIe generation for each lane */
1058 uint8_t max_lanes; /* Number of PCIe lanes */
1059 uint8_t max_speed; /* PCIe generation for each lane */
1060 };
1061
1062 struct ccb_trans_settings_nvmf
1063 {
1064 u_int valid; /* Which fields to honor */
1065 #define CTS_NVMF_VALID_TRTYPE 0x01
1066 uint8_t trtype;
1067 };
1068
1069 struct ccb_trans_settings_ufshci
1070 {
1071 u_int valid; /* Which fields to honor */
1072 /*
1073 * Ensure the validity of the information for the Unipro link
1074 * (GEAR, SPEED, LANE)
1075 */
1076 #define CTS_UFSHCI_VALID_LINK 0x01
1077 uint32_t speed;
1078 uint8_t hs_gear; /* High Speed Gear (G1, G2, G3...) */
1079 uint8_t tx_lanes;
1080 uint8_t rx_lanes;
1081 uint8_t max_hs_gear; /* Maximum HS Gear */
1082 uint8_t max_tx_lanes;
1083 uint8_t max_rx_lanes;
1084 };
1085
1086
1087 #include <cam/mmc/mmc_bus.h>
1088 struct ccb_trans_settings_mmc {
1089 struct mmc_ios ios;
1090 #define MMC_CLK (1 << 1)
1091 #define MMC_VDD (1 << 2)
1092 #define MMC_CS (1 << 3)
1093 #define MMC_BW (1 << 4)
1094 #define MMC_PM (1 << 5)
1095 #define MMC_BT (1 << 6)
1096 #define MMC_BM (1 << 7)
1097 #define MMC_VCCQ (1 << 8)
1098 uint32_t ios_valid;
1099 /* The folowing is used only for GET_TRAN_SETTINGS */
1100 uint32_t host_ocr;
1101 int host_f_min;
1102 int host_f_max;
1103 /* Copied from sys/dev/mmc/bridge.h */
1104 #define MMC_CAP_4_BIT_DATA (1 << 0) /* Can do 4-bit data transfers */
1105 #define MMC_CAP_8_BIT_DATA (1 << 1) /* Can do 8-bit data transfers */
1106 #define MMC_CAP_HSPEED (1 << 2) /* Can do High Speed transfers */
1107 #define MMC_CAP_BOOT_NOACC (1 << 4) /* Cannot access boot partitions */
1108 #define MMC_CAP_WAIT_WHILE_BUSY (1 << 5) /* Host waits for busy responses */
1109 #define MMC_CAP_UHS_SDR12 (1 << 6) /* Can do UHS SDR12 */
1110 #define MMC_CAP_UHS_SDR25 (1 << 7) /* Can do UHS SDR25 */
1111 #define MMC_CAP_UHS_SDR50 (1 << 8) /* Can do UHS SDR50 */
1112 #define MMC_CAP_UHS_SDR104 (1 << 9) /* Can do UHS SDR104 */
1113 #define MMC_CAP_UHS_DDR50 (1 << 10) /* Can do UHS DDR50 */
1114 #define MMC_CAP_MMC_DDR52_120 (1 << 11) /* Can do eMMC DDR52 at 1.2 V */
1115 #define MMC_CAP_MMC_DDR52_180 (1 << 12) /* Can do eMMC DDR52 at 1.8 V */
1116 #define MMC_CAP_MMC_DDR52 (MMC_CAP_MMC_DDR52_120 | MMC_CAP_MMC_DDR52_180)
1117 #define MMC_CAP_MMC_HS200_120 (1 << 13) /* Can do eMMC HS200 at 1.2 V */
1118 #define MMC_CAP_MMC_HS200_180 (1 << 14) /* Can do eMMC HS200 at 1.8 V */
1119 #define MMC_CAP_MMC_HS200 (MMC_CAP_MMC_HS200_120| MMC_CAP_MMC_HS200_180)
1120 #define MMC_CAP_MMC_HS400_120 (1 << 15) /* Can do eMMC HS400 at 1.2 V */
1121 #define MMC_CAP_MMC_HS400_180 (1 << 16) /* Can do eMMC HS400 at 1.8 V */
1122 #define MMC_CAP_MMC_HS400 (MMC_CAP_MMC_HS400_120 | MMC_CAP_MMC_HS400_180)
1123 #define MMC_CAP_MMC_HSX00_120 (MMC_CAP_MMC_HS200_120 | MMC_CAP_MMC_HS400_120)
1124 #define MMC_CAP_MMC_ENH_STROBE (1 << 17) /* Can do eMMC Enhanced Strobe */
1125 #define MMC_CAP_SIGNALING_120 (1 << 18) /* Can do signaling at 1.2 V */
1126 #define MMC_CAP_SIGNALING_180 (1 << 19) /* Can do signaling at 1.8 V */
1127 #define MMC_CAP_SIGNALING_330 (1 << 20) /* Can do signaling at 3.3 V */
1128 #define MMC_CAP_DRIVER_TYPE_A (1 << 21) /* Can do Driver Type A */
1129 #define MMC_CAP_DRIVER_TYPE_C (1 << 22) /* Can do Driver Type C */
1130 #define MMC_CAP_DRIVER_TYPE_D (1 << 23) /* Can do Driver Type D */
1131
1132 uint32_t host_caps;
1133 uint32_t host_max_data;
1134 };
1135
1136 /* Get/Set transfer rate/width/disconnection/tag queueing settings */
1137 struct ccb_trans_settings {
1138 struct ccb_hdr ccb_h;
1139 cts_type type; /* Current or User settings */
1140 cam_proto protocol;
1141 u_int protocol_version;
1142 cam_xport transport;
1143 u_int transport_version;
1144 union {
1145 u_int valid; /* Which fields to honor */
1146 struct ccb_trans_settings_ata ata;
1147 struct ccb_trans_settings_scsi scsi;
1148 struct ccb_trans_settings_nvme nvme;
1149 struct ccb_trans_settings_mmc mmc;
1150 } proto_specific;
1151 union {
1152 u_int valid; /* Which fields to honor */
1153 struct ccb_trans_settings_spi spi;
1154 struct ccb_trans_settings_fc fc;
1155 struct ccb_trans_settings_sas sas;
1156 struct ccb_trans_settings_pata ata;
1157 struct ccb_trans_settings_sata sata;
1158 struct ccb_trans_settings_nvme nvme;
1159 struct ccb_trans_settings_nvmf nvmf;
1160 struct ccb_trans_settings_ufshci ufshci;
1161 } xport_specific;
1162 };
1163
1164 /*
1165 * Calculate the geometry parameters for a device
1166 * give the block size and volume size in blocks.
1167 */
1168 struct ccb_calc_geometry {
1169 struct ccb_hdr ccb_h;
1170 uint32_t block_size;
1171 uint64_t volume_size;
1172 uint32_t cylinders;
1173 uint8_t heads;
1174 uint8_t secs_per_track;
1175 };
1176
1177 /*
1178 * Set or get SIM (and transport) specific knobs
1179 */
1180
1181 #define KNOB_VALID_ADDRESS 0x1
1182 #define KNOB_VALID_ROLE 0x2
1183
1184 #define KNOB_ROLE_NONE 0x0
1185 #define KNOB_ROLE_INITIATOR 0x1
1186 #define KNOB_ROLE_TARGET 0x2
1187 #define KNOB_ROLE_BOTH 0x3
1188
1189 struct ccb_sim_knob_settings_spi {
1190 u_int valid;
1191 u_int initiator_id;
1192 u_int role;
1193 };
1194
1195 struct ccb_sim_knob_settings_fc {
1196 u_int valid;
1197 uint64_t wwnn; /* world wide node name */
1198 uint64_t wwpn; /* world wide port name */
1199 u_int role;
1200 };
1201
1202 struct ccb_sim_knob_settings_sas {
1203 u_int valid;
1204 uint64_t wwnn; /* world wide node name */
1205 u_int role;
1206 };
1207 #define KNOB_SETTINGS_SIZE 128
1208
1209 struct ccb_sim_knob {
1210 struct ccb_hdr ccb_h;
1211 union {
1212 u_int valid; /* Which fields to honor */
1213 struct ccb_sim_knob_settings_spi spi;
1214 struct ccb_sim_knob_settings_fc fc;
1215 struct ccb_sim_knob_settings_sas sas;
1216 char pad[KNOB_SETTINGS_SIZE];
1217 } xport_specific;
1218 };
1219
1220 /*
1221 * Rescan the given bus, or bus/target/lun
1222 */
1223 struct ccb_rescan {
1224 struct ccb_hdr ccb_h;
1225 cam_flags flags;
1226 };
1227
1228 /*
1229 * Turn on debugging for the given bus, bus/target, or bus/target/lun.
1230 */
1231 struct ccb_debug {
1232 struct ccb_hdr ccb_h;
1233 cam_debug_flags flags;
1234 };
1235
1236 /* Target mode structures. */
1237
1238 struct ccb_en_lun {
1239 struct ccb_hdr ccb_h;
1240 uint16_t grp6_len; /* Group 6 VU CDB length */
1241 uint16_t grp7_len; /* Group 7 VU CDB length */
1242 uint8_t enable;
1243 };
1244
1245 /* old, barely used immediate notify, binary compatibility */
1246 struct ccb_immed_notify {
1247 struct ccb_hdr ccb_h;
1248 struct scsi_sense_data sense_data;
1249 uint8_t sense_len; /* Number of bytes in sense buffer */
1250 uint8_t initiator_id; /* Id of initiator that selected */
1251 uint8_t message_args[7]; /* Message Arguments */
1252 };
1253
1254 struct ccb_notify_ack {
1255 struct ccb_hdr ccb_h;
1256 uint16_t seq_id; /* Sequence identifier */
1257 uint8_t event; /* Event flags */
1258 };
1259
1260 struct ccb_immediate_notify {
1261 struct ccb_hdr ccb_h;
1262 u_int tag_id; /* Tag for immediate notify */
1263 u_int seq_id; /* Tag for target of notify */
1264 u_int initiator_id; /* Initiator Identifier */
1265 u_int arg; /* Function specific */
1266 };
1267
1268 struct ccb_notify_acknowledge {
1269 struct ccb_hdr ccb_h;
1270 u_int tag_id; /* Tag for immediate notify */
1271 u_int seq_id; /* Tar for target of notify */
1272 u_int initiator_id; /* Initiator Identifier */
1273 u_int arg; /* Response information */
1274 /*
1275 * Lower byte of arg is one of RESPONSE CODE values defined below
1276 * (subset of response codes from SPL-4 and FCP-4 specifications),
1277 * upper 3 bytes is code-specific ADDITIONAL RESPONSE INFORMATION.
1278 */
1279 #define CAM_RSP_TMF_COMPLETE 0x00
1280 #define CAM_RSP_TMF_REJECTED 0x04
1281 #define CAM_RSP_TMF_FAILED 0x05
1282 #define CAM_RSP_TMF_SUCCEEDED 0x08
1283 #define CAM_RSP_TMF_INCORRECT_LUN 0x09
1284 };
1285
1286 /* HBA engine structures. */
1287
1288 typedef enum {
1289 EIT_BUFFER, /* Engine type: buffer memory */
1290 EIT_LOSSLESS, /* Engine type: lossless compression */
1291 EIT_LOSSY, /* Engine type: lossy compression */
1292 EIT_ENCRYPT /* Engine type: encryption */
1293 } ei_type;
1294
1295 typedef enum {
1296 EAD_VUNIQUE, /* Engine algorithm ID: vendor unique */
1297 EAD_LZ1V1, /* Engine algorithm ID: LZ1 var.1 */
1298 EAD_LZ2V1, /* Engine algorithm ID: LZ2 var.1 */
1299 EAD_LZ2V2 /* Engine algorithm ID: LZ2 var.2 */
1300 } ei_algo;
1301
1302 struct ccb_eng_inq {
1303 struct ccb_hdr ccb_h;
1304 uint16_t eng_num; /* The engine number for this inquiry */
1305 ei_type eng_type; /* Returned engine type */
1306 ei_algo eng_algo; /* Returned engine algorithm type */
1307 uint32_t eng_memeory; /* Returned engine memory size */
1308 };
1309
1310 struct ccb_eng_exec { /* This structure must match SCSIIO size */
1311 struct ccb_hdr ccb_h;
1312 uint8_t *pdrv_ptr; /* Ptr used by the peripheral driver */
1313 uint8_t *req_map; /* Ptr for mapping info on the req. */
1314 uint8_t *data_ptr; /* Pointer to the data buf/SG list */
1315 uint32_t dxfer_len; /* Data transfer length */
1316 uint8_t *engdata_ptr; /* Pointer to the engine buffer data */
1317 uint16_t sglist_cnt; /* Num of scatter gather list entries */
1318 uint32_t dmax_len; /* Destination data maximum length */
1319 uint32_t dest_len; /* Destination data length */
1320 int32_t src_resid; /* Source residual length: 2's comp */
1321 uint32_t timeout; /* Timeout value */
1322 uint16_t eng_num; /* Engine number for this request */
1323 uint16_t vu_flags; /* Vendor Unique flags */
1324 };
1325
1326 /*
1327 * Definitions for the timeout field in the SCSI I/O CCB.
1328 */
1329 #define CAM_TIME_DEFAULT 0x00000000 /* Use SIM default value */
1330 #define CAM_TIME_INFINITY 0xFFFFFFFF /* Infinite timeout */
1331
1332 #define CAM_SUCCESS 0 /* For signaling general success */
1333
1334 #define XPT_CCB_INVALID -1 /* for signaling a bad CCB to free */
1335
1336 /*
1337 * CCB for working with advanced device information. This operates in a fashion
1338 * similar to XPT_GDEV_TYPE. Specify the target in ccb_h, the buffer
1339 * type requested, and provide a buffer size/buffer to write to. If the
1340 * buffer is too small, provsiz will be larger than bufsiz.
1341 */
1342 struct ccb_dev_advinfo {
1343 struct ccb_hdr ccb_h;
1344 uint32_t flags;
1345 #define CDAI_FLAG_NONE 0x0 /* No flags set */
1346 #define CDAI_FLAG_STORE 0x1 /* If set, action becomes store */
1347 uint32_t buftype; /* IN: Type of data being requested */
1348 /* NB: buftype is interpreted on a per-transport basis */
1349 #define CDAI_TYPE_SCSI_DEVID 1
1350 #define CDAI_TYPE_SERIAL_NUM 2
1351 #define CDAI_TYPE_PHYS_PATH 3
1352 #define CDAI_TYPE_RCAPLONG 4
1353 #define CDAI_TYPE_EXT_INQ 5
1354 #define CDAI_TYPE_NVME_CNTRL 6 /* NVMe Identify Controller data */
1355 #define CDAI_TYPE_NVME_NS 7 /* NVMe Identify Namespace data */
1356 #define CDAI_TYPE_MMC_PARAMS 8 /* MMC/SD ident */
1357 off_t bufsiz; /* IN: Size of external buffer */
1358 #define CAM_SCSI_DEVID_MAXLEN 65536 /* length in buffer is an uint16_t */
1359 off_t provsiz; /* OUT: Size required/used */
1360 uint8_t *buf; /* IN/OUT: Buffer for requested data */
1361 };
1362
1363 /*
1364 * CCB for sending async events
1365 */
1366 struct ccb_async {
1367 struct ccb_hdr ccb_h;
1368 uint32_t async_code;
1369 off_t async_arg_size;
1370 void *async_arg_ptr;
1371 };
1372
1373 /*
1374 * Union of all CCB types for kernel space allocation. This union should
1375 * never be used for manipulating CCBs - its only use is for the allocation
1376 * and deallocation of raw CCB space and is the return type of xpt_ccb_alloc
1377 * and the argument to xpt_ccb_free.
1378 */
1379 union ccb {
1380 struct ccb_hdr ccb_h; /* For convenience */
1381 struct ccb_scsiio csio;
1382 struct ccb_getdev cgd;
1383 struct ccb_getdevlist cgdl;
1384 struct ccb_pathinq cpi;
1385 struct ccb_relsim crs;
1386 struct ccb_setasync csa;
1387 struct ccb_setdev csd;
1388 struct ccb_pathstats cpis;
1389 struct ccb_getdevstats cgds;
1390 struct ccb_dev_match cdm;
1391 struct ccb_trans_settings cts;
1392 struct ccb_calc_geometry ccg;
1393 struct ccb_sim_knob knob;
1394 struct ccb_abort cab;
1395 struct ccb_resetbus crb;
1396 struct ccb_resetdev crd;
1397 struct ccb_termio tio;
1398 struct ccb_accept_tio atio;
1399 struct ccb_scsiio ctio;
1400 struct ccb_en_lun cel;
1401 struct ccb_immed_notify cin;
1402 struct ccb_notify_ack cna;
1403 struct ccb_immediate_notify cin1;
1404 struct ccb_notify_acknowledge cna2;
1405 struct ccb_eng_inq cei;
1406 struct ccb_eng_exec cee;
1407 struct ccb_smpio smpio;
1408 struct ccb_rescan crcn;
1409 struct ccb_debug cdbg;
1410 struct ccb_ataio ataio;
1411 struct ccb_dev_advinfo cdai;
1412 struct ccb_async casync;
1413 struct ccb_nvmeio nvmeio;
1414 struct ccb_mmcio mmcio;
1415 };
1416
1417 #define CCB_CLEAR_ALL_EXCEPT_HDR(ccbp) \
1418 bzero((char *)(ccbp) + sizeof((ccbp)->ccb_h), \
1419 sizeof(*(ccbp)) - sizeof((ccbp)->ccb_h))
1420
1421 __BEGIN_DECLS
1422 static __inline void
cam_fill_csio(struct ccb_scsiio * csio,uint32_t retries,void (* cbfcnp)(struct cam_periph *,union ccb *),uint32_t flags,uint8_t tag_action,uint8_t * data_ptr,uint32_t dxfer_len,uint8_t sense_len,uint8_t cdb_len,uint32_t timeout)1423 cam_fill_csio(struct ccb_scsiio *csio, uint32_t retries,
1424 void (*cbfcnp)(struct cam_periph *, union ccb *),
1425 uint32_t flags, uint8_t tag_action,
1426 uint8_t *data_ptr, uint32_t dxfer_len,
1427 uint8_t sense_len, uint8_t cdb_len,
1428 uint32_t timeout)
1429 {
1430 csio->ccb_h.func_code = XPT_SCSI_IO;
1431 csio->ccb_h.flags = flags;
1432 csio->ccb_h.xflags = 0;
1433 csio->ccb_h.retry_count = retries;
1434 csio->ccb_h.cbfcnp = cbfcnp;
1435 csio->ccb_h.timeout = timeout;
1436 csio->data_ptr = data_ptr;
1437 csio->dxfer_len = dxfer_len;
1438 csio->sense_len = sense_len;
1439 csio->cdb_len = cdb_len;
1440 csio->tag_action = tag_action;
1441 csio->priority = 0;
1442 #if defined(BUF_TRACKING) || defined(FULL_BUF_TRACKING)
1443 csio->bio = NULL;
1444 #endif
1445 }
1446
1447 static __inline void
cam_fill_ctio(struct ccb_scsiio * csio,uint32_t retries,void (* cbfcnp)(struct cam_periph *,union ccb *),uint32_t flags,u_int tag_action,u_int tag_id,u_int init_id,u_int scsi_status,uint8_t * data_ptr,uint32_t dxfer_len,uint32_t timeout)1448 cam_fill_ctio(struct ccb_scsiio *csio, uint32_t retries,
1449 void (*cbfcnp)(struct cam_periph *, union ccb *),
1450 uint32_t flags, u_int tag_action, u_int tag_id,
1451 u_int init_id, u_int scsi_status, uint8_t *data_ptr,
1452 uint32_t dxfer_len, uint32_t timeout)
1453 {
1454 csio->ccb_h.func_code = XPT_CONT_TARGET_IO;
1455 csio->ccb_h.flags = flags;
1456 csio->ccb_h.xflags = 0;
1457 csio->ccb_h.retry_count = retries;
1458 csio->ccb_h.cbfcnp = cbfcnp;
1459 csio->ccb_h.timeout = timeout;
1460 csio->data_ptr = data_ptr;
1461 csio->dxfer_len = dxfer_len;
1462 csio->scsi_status = scsi_status;
1463 csio->tag_action = tag_action;
1464 csio->priority = 0;
1465 csio->tag_id = tag_id;
1466 csio->init_id = init_id;
1467 }
1468
1469 static __inline void
cam_fill_ataio(struct ccb_ataio * ataio,uint32_t retries,void (* cbfcnp)(struct cam_periph *,union ccb *),uint32_t flags,u_int tag_action __unused,uint8_t * data_ptr,uint32_t dxfer_len,uint32_t timeout)1470 cam_fill_ataio(struct ccb_ataio *ataio, uint32_t retries,
1471 void (*cbfcnp)(struct cam_periph *, union ccb *),
1472 uint32_t flags, u_int tag_action __unused,
1473 uint8_t *data_ptr, uint32_t dxfer_len,
1474 uint32_t timeout)
1475 {
1476 ataio->ccb_h.func_code = XPT_ATA_IO;
1477 ataio->ccb_h.flags = flags;
1478 ataio->ccb_h.retry_count = retries;
1479 ataio->ccb_h.cbfcnp = cbfcnp;
1480 ataio->ccb_h.timeout = timeout;
1481 ataio->data_ptr = data_ptr;
1482 ataio->dxfer_len = dxfer_len;
1483 ataio->ata_flags = 0;
1484 }
1485
1486 static __inline void
cam_fill_smpio(struct ccb_smpio * smpio,uint32_t retries,void (* cbfcnp)(struct cam_periph *,union ccb *),uint32_t flags,uint8_t * smp_request,int smp_request_len,uint8_t * smp_response,int smp_response_len,uint32_t timeout)1487 cam_fill_smpio(struct ccb_smpio *smpio, uint32_t retries,
1488 void (*cbfcnp)(struct cam_periph *, union ccb *), uint32_t flags,
1489 uint8_t *smp_request, int smp_request_len,
1490 uint8_t *smp_response, int smp_response_len,
1491 uint32_t timeout)
1492 {
1493 #ifdef _KERNEL
1494 KASSERT((flags & CAM_DIR_MASK) == CAM_DIR_BOTH,
1495 ("direction != CAM_DIR_BOTH"));
1496 KASSERT((smp_request != NULL) && (smp_response != NULL),
1497 ("need valid request and response buffers"));
1498 KASSERT((smp_request_len != 0) && (smp_response_len != 0),
1499 ("need non-zero request and response lengths"));
1500 #endif /*_KERNEL*/
1501 smpio->ccb_h.func_code = XPT_SMP_IO;
1502 smpio->ccb_h.flags = flags;
1503 smpio->ccb_h.retry_count = retries;
1504 smpio->ccb_h.cbfcnp = cbfcnp;
1505 smpio->ccb_h.timeout = timeout;
1506 smpio->smp_request = smp_request;
1507 smpio->smp_request_len = smp_request_len;
1508 smpio->smp_response = smp_response;
1509 smpio->smp_response_len = smp_response_len;
1510 }
1511
1512 static __inline void
cam_fill_mmcio(struct ccb_mmcio * mmcio,uint32_t retries,void (* cbfcnp)(struct cam_periph *,union ccb *),uint32_t flags,uint32_t mmc_opcode,uint32_t mmc_arg,uint32_t mmc_flags,struct mmc_data * mmc_d,uint32_t timeout)1513 cam_fill_mmcio(struct ccb_mmcio *mmcio, uint32_t retries,
1514 void (*cbfcnp)(struct cam_periph *, union ccb *), uint32_t flags,
1515 uint32_t mmc_opcode, uint32_t mmc_arg, uint32_t mmc_flags,
1516 struct mmc_data *mmc_d,
1517 uint32_t timeout)
1518 {
1519 mmcio->ccb_h.func_code = XPT_MMC_IO;
1520 mmcio->ccb_h.flags = flags;
1521 mmcio->ccb_h.retry_count = retries;
1522 mmcio->ccb_h.cbfcnp = cbfcnp;
1523 mmcio->ccb_h.timeout = timeout;
1524 mmcio->cmd.opcode = mmc_opcode;
1525 mmcio->cmd.arg = mmc_arg;
1526 mmcio->cmd.flags = mmc_flags;
1527 mmcio->cmd.error = 0;
1528 mmcio->stop.opcode = 0;
1529 mmcio->stop.arg = 0;
1530 mmcio->stop.flags = 0;
1531 if (mmc_d != NULL) {
1532 mmcio->cmd.data = mmc_d;
1533 } else
1534 mmcio->cmd.data = NULL;
1535 mmcio->cmd.resp[0] = 0;
1536 mmcio->cmd.resp[1] = 0;
1537 mmcio->cmd.resp[2] = 0;
1538 mmcio->cmd.resp[3] = 0;
1539 }
1540
1541 static __inline void
cam_set_ccbstatus(union ccb * ccb,cam_status status)1542 cam_set_ccbstatus(union ccb *ccb, cam_status status)
1543 {
1544 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1545 ccb->ccb_h.status |= status;
1546 }
1547
1548 static __inline cam_status
cam_ccb_status(union ccb * ccb)1549 cam_ccb_status(union ccb *ccb)
1550 {
1551 return ((cam_status)(ccb->ccb_h.status & CAM_STATUS_MASK));
1552 }
1553
1554 static inline bool
cam_ccb_success(union ccb * ccb)1555 cam_ccb_success(union ccb *ccb)
1556 {
1557 return (cam_ccb_status(ccb) == CAM_REQ_CMP);
1558 }
1559
1560 void cam_calc_geometry(struct ccb_calc_geometry *ccg, int extended);
1561
1562 static __inline void
cam_fill_nvmeio(struct ccb_nvmeio * nvmeio,uint32_t retries,void (* cbfcnp)(struct cam_periph *,union ccb *),uint32_t flags,uint8_t * data_ptr,uint32_t dxfer_len,uint32_t timeout)1563 cam_fill_nvmeio(struct ccb_nvmeio *nvmeio, uint32_t retries,
1564 void (*cbfcnp)(struct cam_periph *, union ccb *),
1565 uint32_t flags, uint8_t *data_ptr, uint32_t dxfer_len,
1566 uint32_t timeout)
1567 {
1568 nvmeio->ccb_h.func_code = XPT_NVME_IO;
1569 nvmeio->ccb_h.flags = flags;
1570 nvmeio->ccb_h.retry_count = retries;
1571 nvmeio->ccb_h.cbfcnp = cbfcnp;
1572 nvmeio->ccb_h.timeout = timeout;
1573 nvmeio->data_ptr = data_ptr;
1574 nvmeio->dxfer_len = dxfer_len;
1575 }
1576
1577 static __inline void
cam_fill_nvmeadmin(struct ccb_nvmeio * nvmeio,uint32_t retries,void (* cbfcnp)(struct cam_periph *,union ccb *),uint32_t flags,uint8_t * data_ptr,uint32_t dxfer_len,uint32_t timeout)1578 cam_fill_nvmeadmin(struct ccb_nvmeio *nvmeio, uint32_t retries,
1579 void (*cbfcnp)(struct cam_periph *, union ccb *),
1580 uint32_t flags, uint8_t *data_ptr, uint32_t dxfer_len,
1581 uint32_t timeout)
1582 {
1583 nvmeio->ccb_h.func_code = XPT_NVME_ADMIN;
1584 nvmeio->ccb_h.flags = flags;
1585 nvmeio->ccb_h.retry_count = retries;
1586 nvmeio->ccb_h.cbfcnp = cbfcnp;
1587 nvmeio->ccb_h.timeout = timeout;
1588 nvmeio->data_ptr = data_ptr;
1589 nvmeio->dxfer_len = dxfer_len;
1590 }
1591 __END_DECLS
1592
1593 #endif /* _CAM_CAM_CCB_H */
1594