1 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause 4 * 5 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _XHCIREG_H_ 30 #define _XHCIREG_H_ 31 32 /* XHCI PCI config registers */ 33 #define PCI_XHCI_CBMEM 0x10 /* configuration base MEM */ 34 #define PCI_XHCI_USBREV 0x60 /* RO USB protocol revision */ 35 #define PCI_USB_REV_3_0 0x30 /* USB 3.0 */ 36 #define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */ 37 38 #define PCI_XHCI_INTEL_XUSB2PR 0xD0 /* Intel USB2 Port Routing */ 39 #define PCI_XHCI_INTEL_USB2PRM 0xD4 /* Intel USB2 Port Routing Mask */ 40 #define PCI_XHCI_INTEL_USB3_PSSEN 0xD8 /* Intel USB3 Port SuperSpeed Enable */ 41 #define PCI_XHCI_INTEL_USB3PRM 0xDC /* Intel USB3 Port Routing Mask */ 42 43 /* XHCI capability registers */ 44 #define XHCI_CAPLENGTH 0x00 /* RO capability */ 45 #define XHCI_RESERVED 0x01 /* Reserved */ 46 #define XHCI_HCIVERSION 0x02 /* RO Interface version number */ 47 #define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */ 48 #define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */ 49 #define XHCI_HCSPARAMS1 0x04 /* RO structural parameters 1 */ 50 #define XHCI_HCS1_DEVSLOT_MAX(x)((x) & 0xFF) 51 #define XHCI_HCS1_IRQ_MAX(x) (((x) >> 8) & 0x3FF) 52 #define XHCI_HCS1_N_PORTS(x) (((x) >> 24) & 0xFF) 53 #define XHCI_HCSPARAMS2 0x08 /* RO structural parameters 2 */ 54 #define XHCI_HCS2_IST(x) ((x) & 0xF) 55 #define XHCI_HCS2_ERST_MAX(x) (((x) >> 4) & 0xF) 56 #define XHCI_HCS2_SPR(x) (((x) >> 26) & 0x1) 57 #define XHCI_HCS2_SPB_MAX(x) ((((x) >> 16) & 0x3E0) | (((x) >> 27) & 0x1F)) 58 #define XHCI_HCSPARAMS3 0x0C /* RO structural parameters 3 */ 59 #define XHCI_HCS3_U1_DEL(x) ((x) & 0xFF) 60 #define XHCI_HCS3_U2_DEL(x) (((x) >> 16) & 0xFFFF) 61 #define XHCI_HCCPARAMS1 0x10 /* RO capability parameters */ 62 #define XHCI_HCS0_AC64(x) ((x) & 0x1) /* 64-bit capable */ 63 #define XHCI_HCS0_BNC(x) (((x) >> 1) & 0x1) /* BW negotiation */ 64 #define XHCI_HCS0_CSZ(x) (((x) >> 2) & 0x1) /* context size */ 65 #define XHCI_HCS0_PPC(x) (((x) >> 3) & 0x1) /* port power control */ 66 #define XHCI_HCS0_PIND(x) (((x) >> 4) & 0x1) /* port indicators */ 67 #define XHCI_HCS0_LHRC(x) (((x) >> 5) & 0x1) /* light HC reset */ 68 #define XHCI_HCS0_LTC(x) (((x) >> 6) & 0x1) /* latency tolerance msg */ 69 #define XHCI_HCS0_NSS(x) (((x) >> 7) & 0x1) /* no secondary sid */ 70 #define XHCI_HCS0_PSA_SZ_MAX(x) (((x) >> 12) & 0xF) /* max pri. stream array size */ 71 #define XHCI_HCS0_XECP(x) (((x) >> 16) & 0xFFFF) /* extended capabilities pointer */ 72 #define XHCI_DBOFF 0x14 /* RO doorbell offset */ 73 #define XHCI_RTSOFF 0x18 /* RO runtime register space offset */ 74 75 /* XHCI operational registers. Offset given by XHCI_CAPLENGTH register */ 76 #define XHCI_USBCMD 0x00 /* XHCI command */ 77 #define XHCI_CMD_RS 0x00000001 /* RW Run/Stop */ 78 #define XHCI_CMD_HCRST 0x00000002 /* RW Host Controller Reset */ 79 #define XHCI_CMD_INTE 0x00000004 /* RW Interrupter Enable */ 80 #define XHCI_CMD_HSEE 0x00000008 /* RW Host System Error Enable */ 81 #define XHCI_CMD_LHCRST 0x00000080 /* RO/RW Light Host Controller Reset */ 82 #define XHCI_CMD_CSS 0x00000100 /* RW Controller Save State */ 83 #define XHCI_CMD_CRS 0x00000200 /* RW Controller Restore State */ 84 #define XHCI_CMD_EWE 0x00000400 /* RW Enable Wrap Event */ 85 #define XHCI_CMD_EU3S 0x00000800 /* RW Enable U3 MFINDEX Stop */ 86 #define XHCI_USBSTS 0x04 /* XHCI status */ 87 #define XHCI_STS_HCH 0x00000001 /* RO - Host Controller Halted */ 88 #define XHCI_STS_HSE 0x00000004 /* RW - Host System Error */ 89 #define XHCI_STS_EINT 0x00000008 /* RW - Event Interrupt */ 90 #define XHCI_STS_PCD 0x00000010 /* RW - Port Change Detect */ 91 #define XHCI_STS_SSS 0x00000100 /* RO - Save State Status */ 92 #define XHCI_STS_RSS 0x00000200 /* RO - Restore State Status */ 93 #define XHCI_STS_SRE 0x00000400 /* RW - Save/Restore Error */ 94 #define XHCI_STS_CNR 0x00000800 /* RO - Controller Not Ready */ 95 #define XHCI_STS_HCE 0x00001000 /* RO - Host Controller Error */ 96 #define XHCI_PAGESIZE 0x08 /* XHCI page size mask */ 97 #define XHCI_PAGESIZE_4K 0x00000001 /* 4K Page Size */ 98 #define XHCI_PAGESIZE_8K 0x00000002 /* 8K Page Size */ 99 #define XHCI_PAGESIZE_16K 0x00000004 /* 16K Page Size */ 100 #define XHCI_PAGESIZE_32K 0x00000008 /* 32K Page Size */ 101 #define XHCI_PAGESIZE_64K 0x00000010 /* 64K Page Size */ 102 #define XHCI_DNCTRL 0x14 /* XHCI device notification control */ 103 #define XHCI_DNCTRL_MASK(n) (1U << (n)) 104 #define XHCI_CRCR_LO 0x18 /* XHCI command ring control */ 105 #define XHCI_CRCR_LO_RCS 0x00000001 /* RW - consumer cycle state */ 106 #define XHCI_CRCR_LO_CS 0x00000002 /* RW - command stop */ 107 #define XHCI_CRCR_LO_CA 0x00000004 /* RW - command abort */ 108 #define XHCI_CRCR_LO_CRR 0x00000008 /* RW - command ring running */ 109 #define XHCI_CRCR_LO_MASK 0x0000000F 110 #define XHCI_CRCR_HI 0x1C /* XHCI command ring control */ 111 #define XHCI_DCBAAP_LO 0x30 /* XHCI dev context BA pointer */ 112 #define XHCI_DCBAAP_HI 0x34 /* XHCI dev context BA pointer */ 113 #define XHCI_CONFIG 0x38 114 #define XHCI_CONFIG_SLOTS_MASK 0x000000FF /* RW - number of device slots enabled */ 115 116 /* XHCI port status registers */ 117 #define XHCI_PORTSC(n) (0x3F0 + (0x10 * (n))) /* XHCI port status */ 118 #define XHCI_PS_CCS 0x00000001 /* RO - current connect status */ 119 #define XHCI_PS_PED 0x00000002 /* RW - port enabled / disabled */ 120 #define XHCI_PS_OCA 0x00000008 /* RO - over current active */ 121 #define XHCI_PS_PR 0x00000010 /* RW - port reset */ 122 #define XHCI_PS_PLS_GET(x) (((x) >> 5) & 0xF) /* RW - port link state */ 123 #define XHCI_PS_PLS_SET(x) (((x) & 0xF) << 5) /* RW - port link state */ 124 #define XHCI_PS_PP 0x00000200 /* RW - port power */ 125 #define XHCI_PS_SPEED_GET(x) (((x) >> 10) & 0xF) /* RO - port speed */ 126 #define XHCI_PS_SPEED_FULL 0x1 /* Full Speed USB */ 127 #define XHCI_PS_SPEED_LOW 0x2 /* Low Speed USB */ 128 #define XHCI_PS_SPEED_HIGH 0x3 /* High Speed USB */ 129 #define XHCI_PS_SPEED_SS 0x4 /* Super Speed USB */ 130 #define XHCI_PS_PIC_GET(x) (((x) >> 14) & 0x3) /* RW - port indicator */ 131 #define XHCI_PS_PIC_SET(x) (((x) & 0x3) << 14) /* RW - port indicator */ 132 #define XHCI_PS_LWS 0x00010000 /* RW - port link state write strobe */ 133 #define XHCI_PS_CSC 0x00020000 /* RW - connect status change */ 134 #define XHCI_PS_PEC 0x00040000 /* RW - port enable/disable change */ 135 #define XHCI_PS_WRC 0x00080000 /* RW - warm port reset change */ 136 #define XHCI_PS_OCC 0x00100000 /* RW - over-current change */ 137 #define XHCI_PS_PRC 0x00200000 /* RW - port reset change */ 138 #define XHCI_PS_PLC 0x00400000 /* RW - port link state change */ 139 #define XHCI_PS_CEC 0x00800000 /* RW - config error change */ 140 #define XHCI_PS_CAS 0x01000000 /* RO - cold attach status */ 141 #define XHCI_PS_WCE 0x02000000 /* RW - wake on connect enable */ 142 #define XHCI_PS_WDE 0x04000000 /* RW - wake on disconnect enable */ 143 #define XHCI_PS_WOE 0x08000000 /* RW - wake on over-current enable */ 144 #define XHCI_PS_DR 0x40000000 /* RO - device removable */ 145 #define XHCI_PS_WPR 0x80000000U /* RW - warm port reset */ 146 #define XHCI_PS_CLEAR 0x80FF01FFU /* command bits */ 147 148 #define XHCI_PORTPMSC(n) (0x3F4 + (0x10 * (n))) /* XHCI status and control */ 149 #define XHCI_PM3_U1TO_GET(x) (((x) >> 0) & 0xFF) /* RW - U1 timeout */ 150 #define XHCI_PM3_U1TO_SET(x) (((x) & 0xFF) << 0) /* RW - U1 timeout */ 151 #define XHCI_PM3_U2TO_GET(x) (((x) >> 8) & 0xFF) /* RW - U2 timeout */ 152 #define XHCI_PM3_U2TO_SET(x) (((x) & 0xFF) << 8) /* RW - U2 timeout */ 153 #define XHCI_PM3_FLA 0x00010000 /* RW - Force Link PM Accept */ 154 #define XHCI_PM2_L1S_GET(x) (((x) >> 0) & 0x7) /* RO - L1 status */ 155 #define XHCI_PM2_RWE 0x00000008 /* RW - remote wakup enable */ 156 #define XHCI_PM2_HIRD_GET(x) (((x) >> 4) & 0xF) /* RW - host initiated resume duration */ 157 #define XHCI_PM2_HIRD_SET(x) (((x) & 0xF) << 4) /* RW - host initiated resume duration */ 158 #define XHCI_PM2_L1SLOT_GET(x) (((x) >> 8) & 0xFF) /* RW - L1 device slot */ 159 #define XHCI_PM2_L1SLOT_SET(x) (((x) & 0xFF) << 8) /* RW - L1 device slot */ 160 #define XHCI_PM2_HLE 0x00010000 /* RW - hardware LPM enable */ 161 #define XHCI_PORTLI(n) (0x3F8 + (0x10 * (n))) /* XHCI port link info */ 162 #define XHCI_PLI3_ERR_GET(x) (((x) >> 0) & 0xFFFF) /* RO - port link errors */ 163 #define XHCI_PORTRSV(n) (0x3FC + (0x10 * (n))) /* XHCI port reserved */ 164 165 /* XHCI runtime registers. Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers */ 166 #define XHCI_MFINDEX 0x0000 /* RO - microframe index */ 167 #define XHCI_MFINDEX_GET(x) ((x) & 0x3FFF) 168 #define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) /* XHCI interrupt management */ 169 #define XHCI_IMAN_INTR_PEND 0x00000001 /* RW - interrupt pending */ 170 #define XHCI_IMAN_INTR_ENA 0x00000002 /* RW - interrupt enable */ 171 #define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) /* XHCI interrupt moderation */ 172 #define XHCI_IMOD_IVAL_GET(x) (((x) >> 0) & 0xFFFF) /* 250ns unit */ 173 #define XHCI_IMOD_IVAL_SET(x) (((x) & 0xFFFF) << 0) /* 250ns unit */ 174 #define XHCI_IMOD_ICNT_GET(x) (((x) >> 16) & 0xFFFF) /* 250ns unit */ 175 #define XHCI_IMOD_ICNT_SET(x) (((x) & 0xFFFF) << 16) /* 250ns unit */ 176 #define XHCI_IMOD_DEFAULT 0x000001F4U /* 8000 IRQs/second */ 177 #define XHCI_IMOD_DEFAULT_LP 0x000003F8U /* 4000 IRQs/second - LynxPoint */ 178 #define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) /* XHCI event ring segment table size */ 179 #define XHCI_ERSTS_GET(x) ((x) & 0xFFFF) 180 #define XHCI_ERSTS_SET(x) ((x) & 0xFFFF) 181 #define XHCI_ERSTBA_LO(n) (0x0030 + (0x20 * (n))) /* XHCI event ring segment table BA */ 182 #define XHCI_ERSTBA_HI(n) (0x0034 + (0x20 * (n))) /* XHCI event ring segment table BA */ 183 #define XHCI_ERDP_LO(n) (0x0038 + (0x20 * (n))) /* XHCI event ring dequeue pointer */ 184 #define XHCI_ERDP_LO_SINDEX(x) ((x) & 0x7) /* RO - dequeue segment index */ 185 #define XHCI_ERDP_LO_BUSY 0x00000008 /* RW - event handler busy */ 186 #define XHCI_ERDP_HI(n) (0x003C + (0x20 * (n))) /* XHCI event ring dequeue pointer */ 187 188 /* XHCI doorbell registers. Offset given by XHCI_CAPLENGTH + XHCI_DBOFF registers */ 189 #define XHCI_DOORBELL(n) (0x0000 + (4 * (n))) 190 #define XHCI_DB_TARGET_GET(x) ((x) & 0xFF) /* RW - doorbell target */ 191 #define XHCI_DB_TARGET_SET(x) ((x) & 0xFF) /* RW - doorbell target */ 192 #define XHCI_DB_SID_GET(x) (((x) >> 16) & 0xFFFF) /* RW - doorbell stream ID */ 193 #define XHCI_DB_SID_SET(x) (((x) & 0xFFFF) << 16) /* RW - doorbell stream ID */ 194 195 /* XHCI legacy support */ 196 #define XHCI_XECP_ID(x) ((x) & 0xFF) 197 #define XHCI_XECP_NEXT(x) (((x) >> 8) & 0xFF) 198 #define XHCI_XECP_BIOS_SEM 0x0002 199 #define XHCI_XECP_OS_SEM 0x0003 200 201 /* XHCI capability ID's */ 202 #define XHCI_ID_USB_LEGACY 0x0001 203 #define XHCI_ID_PROTOCOLS 0x0002 204 #define XHCI_ID_POWER_MGMT 0x0003 205 #define XHCI_ID_VIRTUALIZATION 0x0004 206 #define XHCI_ID_MSG_IRQ 0x0005 207 #define XHCI_ID_USB_LOCAL_MEM 0x0006 208 /* values 7-9 are reserved */ 209 #define XHCI_ID_USB_DEBUG 0x000a 210 /* values 11-16 are reserved */ 211 #define XHCI_ID_EXT_MSI 0x0011 212 #define XHCI_ID_USB3_TUN 0x0012 213 214 /* 215 * XHCI Debug Capability 216 * From Section 7.6 of xHCI April 2023 Revision 1.2b. 217 */ 218 #define XHCI_DCID 0x0000 219 220 #define XHCI_DCDB 0x0004 /* Doorbell */ 221 #define XHCI_DCDB_OUT 0x00000000 222 #define XHCI_DCDB_IN 0x00000100 223 #define XHCI_DCDB_INVAL 0x0000FE00 224 225 #define XHCI_DCERSTSZ 0x0008 /* Event Ring Segment Table size */ 226 #define XHCI_DCERSTBA_LO 0x0010 227 #define XHCI_DCERSTBA_HI 0x0014 228 #define XHCI_DCERDP_LO 0x0018 229 #define XHCI_DCERDP_HI 0x001C 230 231 #define XHCI_DCCTRL 0x0020 /* Debug Control */ 232 #define XHCI_DCCTRL_DCR 0x00000001 233 #define XHCI_DCCTRL_DCR_GET(x) (((x) ) & 0x01) 234 #define XHCI_DCCTRL_LSE 0x00000002 235 #define XHCI_DCCTRL_LSE_GET(x) (((x) >> 1) & 0x01) 236 #define XHCI_DCCTRL_HOT 0x00000004 237 #define XHCI_DCCTRL_HOT_GET(x) (((x) >> 2) & 0x01) 238 #define XHCI_DCCTRL_HIT 0x00000008 239 #define XHCI_DCCTRL_HIT_GET(x) (((x) >> 3) & 0x01) 240 #define XHCI_DCCTRL_DRC 0x00000010 241 #define XHCI_DCCTRL_DRC_GET(x) (((x) >> 4) & 0x01) 242 #define XHCI_DCCTRL_MBS_GET(x) (((x) >> 16) & 0xFF) 243 #define XHCI_DCCTRL_ADDR_GET(x) (((x) >> 24) & 0x7F) 244 #define XHCI_DCCTRL_DCE 0x80000000 245 #define XHCI_DCCTRL_DCE_GET(x) (((x) >> 31) & 0x01) 246 247 #define XHCI_DCST 0x0024 /* Status */ 248 #define XHCI_DCST_ER 0x00000001 249 #define XHCI_DCST_ER_GET(x) (((x) ) & 0x01) 250 #define XHCI_DCST_SBR 0x00000002 251 #define XHCI_DCST_SBR_GET(x) (((x) >> 1) & 0x01) 252 #define XHCI_DCST_PORT_GET(x) (((x) >> 24) & 0xFF) 253 254 #define XHCI_DCPORTSC 0x0028 /* Port Control */ 255 #define XHCI_DCPORTSC_CCS 0x00000001 256 #define XHCI_DCPORTSC_CCS_GET(x) (((x) ) & 0x01) 257 #define XHCI_DCPORTSC_PED 0x00000002 258 #define XHCI_DCPORTSC_PED_GET(x) (((x) >> 1) & 0x01) 259 #define XHCI_DCPORTSC_PR 0x00000010 260 #define XHCI_DCPORTSC_PR_GET(x) (((x) >> 4) & 0x01) 261 #define XHCI_DCPORTSC_PLS_GET(x) (((x) >> 5) & 0x0F) 262 #define XHCI_DCPORTSC_PLS_U0 0x00 263 #define XHCI_DCPORTSC_PLS_U1 0x01 264 #define XHCI_DCPORTSC_PLS_U2 0x02 265 #define XHCI_DCPORTSC_PLS_U3 0x03 266 #define XHCI_DCPORTSC_PLS_DISABLED 0x04 267 #define XHCI_DCPORTSC_PLS_RXDETECTED 0x05 268 #define XHCI_DCPORTSC_PLS_INACTIVE 0x06 269 #define XHCI_DCPORTSC_PLS_POLLING 0x07 270 #define XHCI_DCPORTSC_PLS_RECOVERY 0x08 271 #define XHCI_DCPORTSC_PLS_HOTRESET 0x09 272 #define XHCI_DCPORTSC_SPEED_GET(x) (((x) >> 10) & 0x0F) 273 #define XHCI_DCPORTSC_CSC 0x00020000 274 #define XHCI_DCPORTSC_CSC_GET(x) (((x) >> 17) & 0x01) 275 #define XHCI_DCPORTSC_PRC 0x00200000 276 #define XHCI_DCPORTSC_PRC_GET(x) (((x) >> 21) & 0x01) 277 #define XHCI_DCPORTSC_PLC 0x00400000 278 #define XHCI_DCPORTSC_PLC_GET(x) (((x) >> 22) & 0x01) 279 #define XHCI_DCPORTSC_CEC 0x00800000 280 #define XHCI_DCPORTSC_CEC_GET(x) (((x) >> 23) & 0x01) 281 #define XHCI_DCCP_LO 0x0030 /* Context Pointer */ 282 #define XHCI_DCCP_HI 0x0034 283 #define XHCI_DCDDI1 0x0038 /* Device Descriptor Info */ 284 #define XHCI_DCDDI2 0x003C /* Device Descriptor Info */ 285 286 /* DbC CIC offset in uint32 */ 287 #define XHCI_DCDBCIC_STR0DESC_LO 0x0000 288 #define XHCI_DCDBCIC_STR0DESC_HI 0x0001 289 #define XHCI_DCDBCIC_MANUDESC_LO 0x0002 290 #define XHCI_DCDBCIC_MANUDESC_HI 0x0003 291 #define XHCI_DCDBCIC_PRODDESC_LO 0x0004 292 #define XHCI_DCDBCIC_PRODDESC_HI 0x0005 293 #define XHCI_DCDBCIC_SERIALDESC_LO 0x0006 294 #define XHCI_DCDBCIC_SERIALDESC_HI 0x0007 295 #define XHCI_DCDBCIC_DESCLEN 0x0008 296 #define XHCI_DCDBCIC_STR0DESC_LEN_GET(x) (((x) >> 0) & 0xff) 297 #define XHCI_DCDBCIC_STR0DESC_LEN_SET(x) (((x) & 0xff) << 0) 298 #define XHCI_DCDBCIC_MANUDESC_LEN_GET(x) (((x) >> 8) & 0xff) 299 #define XHCI_DCDBCIC_MANUDESC_LEN_SET(x) (((x) & 0xff) << 8) 300 #define XHCI_DCDBCIC_PRODDESC_LEN_GET(x) (((x) >> 16) & 0xff) 301 #define XHCI_DCDBCIC_PRODDESC_LEN_SET(x) (((x) & 0xff) << 16) 302 #define XHCI_DCDBCIC_SERIALDESC_LEN_GET(x) (((x) >> 24) & 0xff) 303 #define XHCI_DCDBCIC_SERIALDESC_LEN_SET(x) (((x) & 0xff) << 24) 304 305 #define XHCI_DCSTATUS(ctrl, portsc) \ 306 (XHCI_DCCTRL_DCE_GET(ctrl) << 4 | \ 307 XHCI_DCPORTSC_CCS_GET(portsc) << 3 | \ 308 XHCI_DCPORTSC_PED_GET(portsc) << 2 | \ 309 XHCI_DCPORTSC_PR_GET(portsc) << 1 | \ 310 XHCI_DCCTRL_DCR_GET(ctrl)) 311 #define XHCI_DCPORTSC_ACK_MASK \ 312 (XHCI_DCPORTSC_PED | \ 313 XHCI_DCPORTSC_CSC | XHCI_DCPORTSC_PRC | \ 314 XHCI_DCPORTSC_PLC | XHCI_DCPORTSC_CEC) 315 316 #define XHCI_DCPORT_ST_OFF 0x00 317 #define XHCI_DCPORT_ST_DISCONNECTED 0x10 /* DCE only */ 318 #define XHCI_DCPORT_ST_DISCONNECTED_RUNNING 0x11 /* XXX: DCE + DCR */ 319 #define XHCI_DCPORT_ST_DISABLED 0x18 /* DCE + CCS */ 320 #define XHCI_DCPORT_ST_RESETTING 0x1a /* DCE + CCS + PR */ 321 #define XHCI_DCPORT_ST_ENABLED 0x1c /* DCE + CCS + PED */ 322 #define XHCI_DCPORT_ST_CONFIGURED 0x1d /* DCE + CCS + PED + DCR */ 323 324 #define XHCI_DC_MAXPACKETLEN 1024 325 /* 326 * While Sec 7.6.3.2 describes Endpoint IDs should be 0 or 1, 327 * Intel chips use Device Context Index (Sec 4.5.1) instead. 328 */ 329 #define XHCI_DC_EPID_OUT 0 330 #define XHCI_DC_EPID_IN 1 331 #define XHCI_DC_EPID_OUT_INTEL 2 332 #define XHCI_DC_EPID_IN_INTEL 3 333 #define XHCI_DC_SLOT 1 334 335 /* XHCI register R/W wrappers */ 336 #define XREAD1(sc, what, a) \ 337 bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 338 (a) + (sc)->sc_##what##_off) 339 #define XREAD2(sc, what, a) \ 340 bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 341 (a) + (sc)->sc_##what##_off) 342 #define XREAD4(sc, what, a) \ 343 bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 344 (a) + (sc)->sc_##what##_off) 345 #define XWRITE1(sc, what, a, x) \ 346 bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 347 (a) + (sc)->sc_##what##_off, (x)) 348 #define XWRITE2(sc, what, a, x) \ 349 bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 350 (a) + (sc)->sc_##what##_off, (x)) 351 #define XWRITE4(sc, what, a, x) \ 352 bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 353 (a) + (sc)->sc_##what##_off, (x)) 354 355 #endif /* _XHCIREG_H_ */ 356