xref: /titanic_41/usr/src/uts/common/io/xge/hal/include/xgehal-ring.h (revision 7eced415e5dd557aef2d78483b5a7785f0e13670)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  *
21  * Copyright (c) 2002-2006 Neterion, Inc.
22  */
23 
24 #ifndef XGE_HAL_RING_H
25 #define XGE_HAL_RING_H
26 
27 #include "xgehal-channel.h"
28 #include "xgehal-config.h"
29 #include "xgehal-mm.h"
30 
31 __EXTERN_BEGIN_DECLS
32 
33 /* HW ring configuration */
34 #define XGE_HAL_RING_RXDBLOCK_SIZE	0x1000
35 
36 #define XGE_HAL_RXD_T_CODE_OK		0x0
37 #define XGE_HAL_RXD_T_CODE_PARITY	0x1
38 #define XGE_HAL_RXD_T_CODE_ABORT	0x2
39 #define XGE_HAL_RXD_T_CODE_PARITY_ABORT	0x3
40 #define XGE_HAL_RXD_T_CODE_RDA_FAILURE	0x4
41 #define XGE_HAL_RXD_T_CODE_UNKNOWN_PROTO 0x5
42 #define XGE_HAL_RXD_T_CODE_BAD_FCS	0x6
43 #define XGE_HAL_RXD_T_CODE_BUFF_SIZE	0x7
44 #define XGE_HAL_RXD_T_CODE_BAD_ECC	0x8
45 #define XGE_HAL_RXD_T_CODE_UNUSED_C	0xC
46 #define XGE_HAL_RXD_T_CODE_UNKNOWN	0xF
47 
48 #define XGE_HAL_RING_USE_MTU		-1
49 
50 /* control_1 and control_2 formatting - same for all buffer modes */
51 #define XGE_HAL_RXD_GET_L3_CKSUM(control_1) ((u16)(control_1>>16) & 0xFFFF)
52 #define XGE_HAL_RXD_GET_L4_CKSUM(control_1) ((u16)(control_1 & 0xFFFF))
53 
54 #define XGE_HAL_RXD_MASK_VLAN_TAG		vBIT(0xFFFF,48,16)
55 #define XGE_HAL_RXD_SET_VLAN_TAG(control_2, val) control_2 |= (u16)val
56 #define XGE_HAL_RXD_GET_VLAN_TAG(control_2)	((u16)(control_2 & 0xFFFF))
57 
58 #define XGE_HAL_RXD_POSTED_4_XFRAME		BIT(7)  /* control_1 */
59 #define XGE_HAL_RXD_NOT_COMPLETED               BIT(0)  /* control_2 */
60 #define XGE_HAL_RXD_T_CODE		(BIT(12)|BIT(13)|BIT(14)|BIT(15))
61 #define XGE_HAL_RXD_GET_T_CODE(control_1)	\
62 				((control_1 & XGE_HAL_RXD_T_CODE)>>48)
63 #define XGE_HAL_RXD_SET_T_CODE(control_1, val) \
64 				(control_1 |= (((u64)val & 0xF) << 48))
65 
66 #define XGE_HAL_RXD_MASK_FRAME_TYPE		vBIT(0x3,25,2)
67 #define XGE_HAL_RXD_MASK_FRAME_PROTO		vBIT(0xFFFF,24,8)
68 #define XGE_HAL_RXD_GET_FRAME_TYPE(control_1)	\
69 		(u8)(0x3 & ((control_1 & XGE_HAL_RXD_MASK_FRAME_TYPE) >> 37))
70 #define XGE_HAL_RXD_GET_FRAME_PROTO(control_1)	\
71 			(u8)((control_1 & XGE_HAL_RXD_MASK_FRAME_PROTO) >> 32)
72 #define XGE_HAL_RXD_FRAME_PROTO_VLAN_TAGGED	BIT(24)
73 #define XGE_HAL_RXD_FRAME_PROTO_IPV4		BIT(27)
74 #define XGE_HAL_RXD_FRAME_PROTO_IPV6		BIT(28)
75 #define XGE_HAL_RXD_FRAME_PROTO_IP_FRAGMENTED	BIT(29)
76 #define XGE_HAL_RXD_FRAME_PROTO_TCP		BIT(30)
77 #define XGE_HAL_RXD_FRAME_PROTO_UDP		BIT(31)
78 #define XGE_HAL_RXD_FRAME_TCP_OR_UDP (XGE_HAL_RXD_FRAME_PROTO_TCP | \
79 				XGE_HAL_RXD_FRAME_PROTO_UDP)
80 
81 /**
82  * enum xge_hal_frame_type_e - Ethernet frame format.
83  * @XGE_HAL_FRAME_TYPE_DIX: DIX (Ethernet II) format.
84  * @XGE_HAL_FRAME_TYPE_LLC: LLC format.
85  * @XGE_HAL_FRAME_TYPE_SNAP: SNAP format.
86  * @XGE_HAL_FRAME_TYPE_IPX: IPX format.
87  *
88  * Ethernet frame format.
89  */
90 typedef enum xge_hal_frame_type_e {
91 	XGE_HAL_FRAME_TYPE_DIX			= 0x0,
92 	XGE_HAL_FRAME_TYPE_LLC			= 0x1,
93 	XGE_HAL_FRAME_TYPE_SNAP			= 0x2,
94 	XGE_HAL_FRAME_TYPE_IPX			= 0x3,
95 } xge_hal_frame_type_e;
96 
97 /**
98  * enum xge_hal_frame_proto_e - Higher-layer ethernet protocols.
99  * @XGE_HAL_FRAME_PROTO_VLAN_TAGGED: VLAN.
100  * @XGE_HAL_FRAME_PROTO_IPV4: IPv4.
101  * @XGE_HAL_FRAME_PROTO_IPV6: IPv6.
102  * @XGE_HAL_FRAME_PROTO_IP_FRAGMENTED: IP fragmented.
103  * @XGE_HAL_FRAME_PROTO_TCP: TCP.
104  * @XGE_HAL_FRAME_PROTO_UDP: UDP.
105  * @XGE_HAL_FRAME_PROTO_TCP_OR_UDP: TCP or UDP.
106  *
107  * Higher layer ethernet protocols and options.
108  */
109 typedef enum xge_hal_frame_proto_e {
110 	XGE_HAL_FRAME_PROTO_VLAN_TAGGED		= 0x80,
111 	XGE_HAL_FRAME_PROTO_IPV4		= 0x10,
112 	XGE_HAL_FRAME_PROTO_IPV6		= 0x08,
113 	XGE_HAL_FRAME_PROTO_IP_FRAGMENTED	= 0x04,
114 	XGE_HAL_FRAME_PROTO_TCP			= 0x02,
115 	XGE_HAL_FRAME_PROTO_UDP			= 0x01,
116 	XGE_HAL_FRAME_PROTO_TCP_OR_UDP		= (XGE_HAL_FRAME_PROTO_TCP | \
117 						   XGE_HAL_FRAME_PROTO_UDP)
118 } xge_hal_frame_proto_e;
119 
120 /*
121  * xge_hal_ring_rxd_1_t
122  */
123 typedef struct {
124 	u64 host_control;
125 	u64 control_1;
126 	u64 control_2;
127 #define XGE_HAL_RXD_1_MASK_BUFFER0_SIZE		vBIT(0xFFFF,0,16)
128 #define XGE_HAL_RXD_1_SET_BUFFER0_SIZE(val)	vBIT(val,0,16)
129 #define XGE_HAL_RXD_1_GET_BUFFER0_SIZE(Control_2) \
130 			(int)((Control_2 & vBIT(0xFFFF,0,16))>>48)
131 #define XGE_HAL_RXD_1_GET_RTH_VALUE(Control_2) \
132 			(u32)((Control_2 & vBIT(0xFFFFFFFF,16,32))>>16)
133 	u64 buffer0_ptr;
134 } xge_hal_ring_rxd_1_t;
135 
136 /*
137  * xge_hal_ring_rxd_3_t
138  */
139 typedef struct {
140 	u64 host_control;
141 	u64 control_1;
142 
143 	u64 control_2;
144 #define XGE_HAL_RXD_3_MASK_BUFFER0_SIZE		vBIT(0xFF,8,8)
145 #define XGE_HAL_RXD_3_SET_BUFFER0_SIZE(val)	vBIT(val,8,8)
146 #define XGE_HAL_RXD_3_MASK_BUFFER1_SIZE		vBIT(0xFFFF,16,16)
147 #define XGE_HAL_RXD_3_SET_BUFFER1_SIZE(val)	vBIT(val,16,16)
148 #define XGE_HAL_RXD_3_MASK_BUFFER2_SIZE		vBIT(0xFFFF,32,16)
149 #define XGE_HAL_RXD_3_SET_BUFFER2_SIZE(val)	vBIT(val,32,16)
150 
151 
152 #define XGE_HAL_RXD_3_GET_BUFFER0_SIZE(Control_2) \
153 				(int)((Control_2 & vBIT(0xFF,8,8))>>48)
154 #define XGE_HAL_RXD_3_GET_BUFFER1_SIZE(Control_2) \
155 				(int)((Control_2 & vBIT(0xFFFF,16,16))>>32)
156 #define XGE_HAL_RXD_3_GET_BUFFER2_SIZE(Control_2) \
157 				(int)((Control_2 & vBIT(0xFFFF,32,16))>>16)
158 
159 	u64 buffer0_ptr;
160 	u64 buffer1_ptr;
161 	u64 buffer2_ptr;
162 } xge_hal_ring_rxd_3_t;
163 
164 /*
165  * xge_hal_ring_rxd_5_t
166  */
167 typedef struct {
168 #ifdef XGE_OS_HOST_BIG_ENDIAN
169 	u32 host_control;
170 	u32 control_3;
171 #else
172 	u32 control_3;
173 	u32 host_control;
174 #endif
175 
176 
177 #define XGE_HAL_RXD_5_MASK_BUFFER3_SIZE		vBIT(0xFFFF,32,16)
178 #define XGE_HAL_RXD_5_SET_BUFFER3_SIZE(val)	vBIT(val,32,16)
179 #define XGE_HAL_RXD_5_MASK_BUFFER4_SIZE		vBIT(0xFFFF,48,16)
180 #define XGE_HAL_RXD_5_SET_BUFFER4_SIZE(val)	vBIT(val,48,16)
181 
182 #define XGE_HAL_RXD_5_GET_BUFFER3_SIZE(Control_3) \
183 				(int)((Control_3 & vBIT(0xFFFF,32,16))>>16)
184 #define XGE_HAL_RXD_5_GET_BUFFER4_SIZE(Control_3) \
185 				(int)((Control_3 & vBIT(0xFFFF,48,16)))
186 
187 	u64 control_1;
188 	u64 control_2;
189 
190 #define XGE_HAL_RXD_5_MASK_BUFFER0_SIZE		vBIT(0xFFFF,0,16)
191 #define XGE_HAL_RXD_5_SET_BUFFER0_SIZE(val)	vBIT(val,0,16)
192 #define XGE_HAL_RXD_5_MASK_BUFFER1_SIZE		vBIT(0xFFFF,16,16)
193 #define XGE_HAL_RXD_5_SET_BUFFER1_SIZE(val)	vBIT(val,16,16)
194 #define XGE_HAL_RXD_5_MASK_BUFFER2_SIZE		vBIT(0xFFFF,32,16)
195 #define XGE_HAL_RXD_5_SET_BUFFER2_SIZE(val)	vBIT(val,32,16)
196 
197 
198 #define XGE_HAL_RXD_5_GET_BUFFER0_SIZE(Control_2) \
199 			(int)((Control_2 & vBIT(0xFFFF,0,16))>>48)
200 #define XGE_HAL_RXD_5_GET_BUFFER1_SIZE(Control_2) \
201 			(int)((Control_2 & vBIT(0xFFFF,16,16))>>32)
202 #define XGE_HAL_RXD_5_GET_BUFFER2_SIZE(Control_2) \
203 			(int)((Control_2 & vBIT(0xFFFF,32,16))>>16)
204 	u64 buffer0_ptr;
205 	u64 buffer1_ptr;
206 	u64 buffer2_ptr;
207 	u64 buffer3_ptr;
208 	u64 buffer4_ptr;
209 } xge_hal_ring_rxd_5_t;
210 
211 #define XGE_HAL_RXD_GET_RTH_SPDM_HIT(Control_1) \
212 		(u8)((Control_1 & BIT(18))>>45)
213 #define XGE_HAL_RXD_GET_RTH_IT_HIT(Control_1) \
214 		(u8)((Control_1 & BIT(19))>>44)
215 #define XGE_HAL_RXD_GET_RTH_HASH_TYPE(Control_1) \
216 		(u8)((Control_1 & vBIT(0xF,20,4))>>40)
217 
218 #define XGE_HAL_RXD_HASH_TYPE_NONE				0x0
219 #define XGE_HAL_RXD_HASH_TYPE_TCP_IPV4			0x1
220 #define XGE_HAL_RXD_HASH_TYPE_UDP_IPV4			0x2
221 #define XGE_HAL_RXD_HASH_TYPE_IPV4				0x3
222 #define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6			0x4
223 #define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6			0x5
224 #define XGE_HAL_RXD_HASH_TYPE_IPV6				0x6
225 #define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6_EX		0x7
226 #define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6_EX		0x8
227 #define XGE_HAL_RXD_HASH_TYPE_IPV6_EX			0x9
228 
229 typedef u8 xge_hal_ring_block_t[XGE_HAL_RING_RXDBLOCK_SIZE];
230 
231 #define XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET	0xFF8
232 #define XGE_HAL_RING_MEMBLOCK_IDX_OFFSET	0xFF0
233 
234 #define XGE_HAL_RING_RXD_SIZEOF(n) \
235 	(n==1 ? sizeof(xge_hal_ring_rxd_1_t) : \
236 		(n==3 ? sizeof(xge_hal_ring_rxd_3_t) : \
237 			sizeof(xge_hal_ring_rxd_5_t)))
238 
239 #define XGE_HAL_RING_RXDS_PER_BLOCK(n) \
240 	(n==1 ? 127 : (n==3 ? 85 : 63))
241 
242 /**
243  * struct xge_hal_ring_rxd_priv_t - Receive descriptor HAL-private data.
244  * @dma_addr: DMA (mapped) address of _this_ descriptor.
245  * @dma_handle: DMA handle used to map the descriptor onto device.
246  * @dma_offset: Descriptor's offset in the memory block. HAL allocates
247  *              descriptors in memory blocks of
248  *              %XGE_HAL_RING_RXDBLOCK_SIZE
249  *              bytes. Each memblock is contiguous DMA-able memory. Each
250  *              memblock contains 1 or more 4KB RxD blocks visible to the
251  *              Xframe hardware.
252  * @dma_object: DMA address and handle of the memory block that contains
253  *              the descriptor. This member is used only in the "checked"
254  *              version of the HAL (to enforce certain assertions);
255  *              otherwise it gets compiled out.
256  * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
257  *
258  * Per-receive decsriptor HAL-private data. HAL uses the space to keep DMA
259  * information associated with the descriptor. Note that ULD can ask HAL
260  * to allocate additional per-descriptor space for its own (ULD-specific)
261  * purposes.
262  */
263 typedef struct xge_hal_ring_rxd_priv_t {
264 	dma_addr_t		dma_addr;
265 	pci_dma_h		dma_handle;
266 	ptrdiff_t		dma_offset;
267 #ifdef XGE_DEBUG_ASSERT
268 	xge_hal_mempool_dma_t	*dma_object;
269 #endif
270 #ifdef XGE_OS_MEMORY_CHECK
271 	int			allocated;
272 #endif
273 } xge_hal_ring_rxd_priv_t;
274 
275 /**
276  * struct xge_hal_ring_t - Ring channel.
277  * @channel: Channel "base" of this ring, the common part of all HAL
278  *           channels.
279  * @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode,
280  *          as per Xframe User Guide.
281  * @indicate_max_pkts: Maximum number of packets processed within a single
282  *          interrupt. Can be used to limit the time spent inside hw
283  *          interrupt.
284  * @config: Ring configuration, part of device configuration
285  *          (see xge_hal_device_config_t{}).
286  * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per Xframe spec,
287  *            1-buffer mode descriptor is 32 byte long, etc.
288  * @rxd_priv_size: Per RxD size reserved (by HAL) for ULD to keep per-descriptor
289  *                 data (e.g., DMA handle for Solaris)
290  * @rxds_per_block: Number of descriptors per hardware-defined RxD
291  *                  block. Depends on the (1-,3-,5-) buffer mode.
292  * @mempool: Memory pool, the pool from which descriptors get allocated.
293  *           (See xge_hal_mm.h).
294  * @rxdblock_priv_size: Reserved at the end of each RxD block. HAL internal
295  *                      usage. Not to confuse with @rxd_priv_size.
296  * @reserved_rxds_arr: Array of RxD pointers. At any point in time each
297  *                     entry in this array is available for allocation
298  *                     (via xge_hal_ring_dtr_reserve()) and posting.
299  * @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR.
300  *            Used in conjunction with @indicate_max_pkts.
301  * Ring channel.
302  *
303  * Note: The structure is cache line aligned to better utilize
304  *       CPU cache performance.
305  */
306 typedef struct xge_hal_ring_t {
307 	xge_hal_channel_t		channel;
308 	int				buffer_mode;
309 	int				indicate_max_pkts;
310 	xge_hal_ring_config_t		*config;
311 	int				rxd_size;
312 	int				rxd_priv_size;
313 	int				rxds_per_block;
314 	xge_hal_mempool_t		*mempool;
315 	int				rxdblock_priv_size;
316 	void				**reserved_rxds_arr;
317 	int				cmpl_cnt;
318 } __xge_os_attr_cacheline_aligned xge_hal_ring_t;
319 
320 /**
321  * struct xge_hal_dtr_info_t - Extended information associated with a
322  * completed ring descriptor.
323  * @l3_cksum: Result of IP checksum check (by Xframe hardware).
324  *            This field containing XGE_HAL_L3_CKSUM_OK would mean that
325  *            the checksum is correct, otherwise - the datagram is
326  *            corrupted.
327  * @l4_cksum: Result of TCP/UDP checksum check (by Xframe hardware).
328  *            This field containing XGE_HAL_L4_CKSUM_OK would mean that
329  *            the checksum is correct. Otherwise - the packet is
330  *            corrupted.
331  * @frame: See xge_hal_frame_type_e{}.
332  * @proto:    Reporting bits for various higher-layer protocols, including (but
333  *	      note restricted to) TCP and UDP. See xge_hal_frame_proto_e{}.
334  * @vlan:     VLAN tag extracted from the received frame.
335  * @rth_value: Receive Traffic Hashing(RTH) hash value. Produced by Xframe II
336  *             hardware if RTH is enabled.
337  * @rth_it_hit: Set, If RTH hash value calculated by the Xframe II hardware
338  *             has a matching entry in the Indirection table.
339  * @rth_spdm_hit: Set, If RTH hash value calculated by the Xframe II hardware
340  *             has a matching entry in the Socket Pair Direct Match table.
341  * @rth_hash_type: RTH hash code of the function used to calculate the hash.
342  * @reserved_pad: Unused byte.
343  */
344 typedef struct xge_hal_dtr_info_t {
345 	int	l3_cksum;
346 	int	l4_cksum;
347 	int	frame; /* zero or more of xge_hal_frame_type_e flags */
348 	int	proto; /* zero or more of xge_hal_frame_proto_e flags */
349 	int	vlan;
350 	u32	rth_value;
351 	u8	rth_it_hit;
352 	u8	rth_spdm_hit;
353 	u8	rth_hash_type;
354 	u8	reserved_pad;
355 } xge_hal_dtr_info_t;
356 
357 /* ========================== RING PRIVATE API ============================ */
358 
359 xge_hal_status_e __hal_ring_open(xge_hal_channel_h channelh,
360 			xge_hal_channel_attr_t	*attr);
361 
362 void __hal_ring_close(xge_hal_channel_h channelh);
363 
364 void __hal_ring_hw_initialize(xge_hal_device_h devh);
365 
366 void __hal_ring_mtu_set(xge_hal_device_h devh, int new_mtu);
367 
368 void __hal_ring_prc_enable(xge_hal_channel_h channelh);
369 
370 void __hal_ring_prc_disable(xge_hal_channel_h channelh);
371 
372 xge_hal_status_e __hal_ring_initial_replenish(xge_hal_channel_t *channel,
373 					      xge_hal_channel_reopen_e reopen);
374 
375 #if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_RING)
376 #define __HAL_STATIC_RING
377 #define __HAL_INLINE_RING
378 
379 __HAL_STATIC_RING __HAL_INLINE_RING int
380 __hal_ring_block_memblock_idx(xge_hal_ring_block_t *block);
381 
382 __HAL_STATIC_RING __HAL_INLINE_RING void
383 __hal_ring_block_memblock_idx_set(xge_hal_ring_block_t*block, int memblock_idx);
384 
385 __HAL_STATIC_RING __HAL_INLINE_RING dma_addr_t
386 __hal_ring_block_next_pointer(xge_hal_ring_block_t *block);
387 
388 __HAL_STATIC_RING __HAL_INLINE_RING void
389 __hal_ring_block_next_pointer_set(xge_hal_ring_block_t*block,
390 			dma_addr_t dma_next);
391 
392 __HAL_STATIC_RING __HAL_INLINE_RING xge_hal_ring_rxd_priv_t*
393 __hal_ring_rxd_priv(xge_hal_ring_t *ring, xge_hal_dtr_h dtrh);
394 
395 /* =========================== RING PUBLIC API ============================ */
396 
397 __HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e
398 xge_hal_ring_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh);
399 
400 __HAL_STATIC_RING __HAL_INLINE_RING void*
401 xge_hal_ring_dtr_private(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
402 
403 __HAL_STATIC_RING __HAL_INLINE_RING void
404 xge_hal_ring_dtr_1b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointer, int	size);
405 
406 __HAL_STATIC_RING __HAL_INLINE_RING void
407 xge_hal_ring_dtr_info_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
408 			xge_hal_dtr_info_t *ext_info);
409 
410 __HAL_STATIC_RING __HAL_INLINE_RING void
411 xge_hal_ring_dtr_1b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
412 			dma_addr_t *dma_pointer, int *pkt_length);
413 
414 __HAL_STATIC_RING __HAL_INLINE_RING void
415 xge_hal_ring_dtr_3b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[],
416 			int sizes[]);
417 
418 __HAL_STATIC_RING __HAL_INLINE_RING void
419 xge_hal_ring_dtr_3b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
420 			dma_addr_t dma_pointers[], int sizes[]);
421 
422 __HAL_STATIC_RING __HAL_INLINE_RING void
423 xge_hal_ring_dtr_5b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[],
424 			int sizes[]);
425 
426 __HAL_STATIC_RING __HAL_INLINE_RING void
427 xge_hal_ring_dtr_5b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
428 			dma_addr_t dma_pointer[], int sizes[]);
429 
430 __HAL_STATIC_RING __HAL_INLINE_RING void
431 xge_hal_ring_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
432 
433 __HAL_STATIC_RING __HAL_INLINE_RING void
434 xge_hal_ring_dtr_pre_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
435 
436 __HAL_STATIC_RING __HAL_INLINE_RING void
437 xge_hal_ring_dtr_post_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
438 
439 __HAL_STATIC_RING __HAL_INLINE_RING void
440 xge_hal_ring_dtr_post_post_wmb(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
441 
442 __HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e
443 xge_hal_ring_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh,
444 			u8 *t_code);
445 
446 __HAL_STATIC_RING __HAL_INLINE_RING void
447 xge_hal_ring_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
448 
449 __HAL_STATIC_RING __HAL_INLINE_RING	xge_hal_status_e
450 xge_hal_ring_is_next_dtr_completed(xge_hal_channel_h channelh);
451 
452 #else /* XGE_FASTPATH_EXTERN */
453 #define __HAL_STATIC_RING static
454 #define __HAL_INLINE_RING inline
455 #include "xgehal-ring-fp.c"
456 #endif /* XGE_FASTPATH_INLINE */
457 
458 __EXTERN_END_DECLS
459 
460 #endif /* XGE_HAL_RING_H */
461