xref: /titanic_41/usr/src/uts/common/io/xge/hal/include/xgehal-types.h (revision 7eced415e5dd557aef2d78483b5a7785f0e13670)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  *
21  * Copyright (c) 2002-2006 Neterion, Inc.
22  */
23 
24 #ifndef XGE_HAL_TYPES_H
25 #define XGE_HAL_TYPES_H
26 
27 #include "xge-os-pal.h"
28 
29 __EXTERN_BEGIN_DECLS
30 
31 /*
32  * BIT(loc) - set bit at offset
33  */
34 #define BIT(loc)		(0x8000000000000000ULL >> (loc))
35 
36 /*
37  * vBIT(val, loc, sz) - set bits at offset
38  */
39 #define vBIT(val, loc, sz)	(((u64)(val)) << (64-(loc)-(sz)))
40 #define vBIT32(val, loc, sz)	(((u32)(val)) << (32-(loc)-(sz)))
41 
42 /*
43  * bVALx(bits, loc) - Get the value of x bits at location
44  */
45 #define bVAL1(bits, loc)	((((u64)bits) >> (64-(loc+1))) & 0x1)
46 #define bVAL2(bits, loc)	((((u64)bits) >> (64-(loc+2))) & 0x3)
47 #define bVAL3(bits, loc)	((((u64)bits) >> (64-(loc+3))) & 0x7)
48 #define bVAL4(bits, loc)	((((u64)bits) >> (64-(loc+4))) & 0xF)
49 #define bVAL5(bits, loc)	((((u64)bits) >> (64-(loc+5))) & 0x1F)
50 #define bVAL6(bits, loc)	((((u64)bits) >> (64-(loc+6))) & 0x3F)
51 #define bVAL7(bits, loc)	((((u64)bits) >> (64-(loc+7))) & 0x7F)
52 #define bVAL8(bits, loc)	((((u64)bits) >> (64-(loc+8))) & 0xFF)
53 #define bVAL12(bits, loc)	((((u64)bits) >> (64-(loc+12))) & 0xFFF)
54 #define bVAL14(bits, loc)	((((u64)bits) >> (64-(loc+14))) & 0x3FFF)
55 #define bVAL16(bits, loc)	((((u64)bits) >> (64-(loc+16))) & 0xFFFF)
56 #define bVAL20(bits, loc)	((((u64)bits) >> (64-(loc+20))) & 0xFFFFF)
57 #define bVAL22(bits, loc)	((((u64)bits) >> (64-(loc+22))) & 0x3FFFFF)
58 #define bVAL24(bits, loc)	((((u64)bits) >> (64-(loc+24))) & 0xFFFFFF)
59 #define bVAL28(bits, loc)	((((u64)bits) >> (64-(loc+28))) & 0xFFFFFFF)
60 #define bVAL32(bits, loc)	((((u64)bits) >> (64-(loc+32))) & 0xFFFFFFFF)
61 #define bVAL36(bits, loc)	((((u64)bits) >> (64-(loc+36))) & 0xFFFFFFFFF)
62 #define bVAL40(bits, loc)	((((u64)bits) >> (64-(loc+40))) & 0xFFFFFFFFFF)
63 #define bVAL44(bits, loc)	((((u64)bits) >> (64-(loc+44))) & 0xFFFFFFFFFFF)
64 #define bVAL48(bits, loc)	((((u64)bits) >> (64-(loc+48))) & 0xFFFFFFFFFFFF)
65 #define bVAL52(bits, loc)	((((u64)bits) >> (64-(loc+52))) & 0xFFFFFFFFFFFFF)
66 #define bVAL56(bits, loc)	((((u64)bits) >> (64-(loc+56))) & 0xFFFFFFFFFFFFFF)
67 #define bVAL60(bits, loc)	((((u64)bits) >> (64-(loc+60))) & 0xFFFFFFFFFFFFFFF)
68 
69 #define XGE_HAL_BASE_INF		100
70 #define XGE_HAL_BASE_ERR		200
71 #define XGE_HAL_BASE_BADCFG	        300
72 
73 #define XGE_HAL_ALL_FOXES   0xFFFFFFFFFFFFFFFFULL
74 
75 /**
76  * enum xge_hal_status_e - HAL return codes.
77  * @XGE_HAL_OK: Success.
78  * @XGE_HAL_FAIL: Failure.
79  * @XGE_HAL_COMPLETIONS_REMAIN: There are more completions on a channel.
80  *      (specific to polling mode completion processing).
81  * @XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS: No more completed
82  * descriptors. See xge_hal_fifo_dtr_next_completed().
83  * @XGE_HAL_INF_OUT_OF_DESCRIPTORS: Out of descriptors. Channel
84  * descriptors
85  *           are reserved (via xge_hal_fifo_dtr_reserve(),
86  *           xge_hal_fifo_dtr_reserve())
87  *           and not yet freed (via xge_hal_fifo_dtr_free(),
88  *           xge_hal_ring_dtr_free()).
89  * @XGE_HAL_INF_CHANNEL_IS_NOT_READY: Channel is not ready for
90  * operation.
91  * @XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING: Indicates that host needs to
92  * poll until PIO is executed.
93  * @XGE_HAL_INF_STATS_IS_NOT_READY: Cannot retrieve statistics because
94  * HAL and/or device is not yet initialized.
95  * @XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS: No descriptors left to
96  * reserve. Internal use only.
97  * @XGE_HAL_INF_IRQ_POLLING_CONTINUE: Returned by the ULD channel
98  * callback when instructed to exit descriptor processing loop
99  * prematurely. Typical usage: polling mode of processing completed
100  * descriptors.
101  *           Upon getting LRO_ISED, ll driver shall
102  *           1) initialise lro struct with mbuf if sg_num == 1.
103  *           2) else it will update m_data_ptr_of_mbuf to tcp pointer and
104  *           append the new mbuf to the tail of mbuf chain in lro struct.
105  *
106  * @XGE_HAL_INF_LRO_BEGIN: Returned by ULD LRO module, when new LRO is
107  * being initiated.
108  * @XGE_HAL_INF_LRO_CONT: Returned by ULD LRO module, when new frame
109  * is appended at the end of existing LRO.
110  * @XGE_HAL_INF_LRO_UNCAPABLE: Returned by ULD LRO module, when new
111  * frame is not LRO capable.
112  * @XGE_HAL_INF_LRO_END_1: Returned by ULD LRO module, when new frame
113  * triggers LRO flush.
114  * @XGE_HAL_INF_LRO_END_2: Returned by ULD LRO module, when new
115  * frame triggers LRO flush. Lro frame should be flushed first then
116  * new frame should be flushed next.
117  * @XGE_HAL_INF_LRO_END_3: Returned by ULD LRO module, when new
118  * frame triggers close of current LRO session and opening of new LRO session
119  * with the frame.
120  * @XGE_HAL_INF_LRO_SESSIONS_XCDED: Returned by ULD LRO module, when no
121  * more LRO sessions can be added.
122  * @XGE_HAL_INF_NOT_ENOUGH_HW_CQES: TBD
123  * @XGE_HAL_ERR_DRIVER_NOT_INITIALIZED: HAL is not initialized.
124  * @XGE_HAL_ERR_OUT_OF_MEMORY: Out of memory (example, when and
125  * allocating descriptors).
126  * @XGE_HAL_ERR_CHANNEL_NOT_FOUND: xge_hal_channel_open will return this
127  * error if corresponding channel is not configured.
128  * @XGE_HAL_ERR_WRONG_IRQ: Returned by HAL's ISR when the latter is
129  * invoked not because of the Xframe-generated interrupt.
130  * @XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES: Returned when user tries to
131  * configure more than XGE_HAL_MAX_MAC_ADDRESSES  mac addresses.
132  * @XGE_HAL_ERR_BAD_DEVICE_ID: Unknown device PCI ID.
133  * @XGE_HAL_ERR_OUT_ALIGNED_FRAGS: Too many unaligned fragments
134  * in a scatter-gather list.
135  * @XGE_HAL_ERR_DEVICE_NOT_INITIALIZED: Device is not initialized.
136  * Typically means wrong sequence of API calls.
137  * @XGE_HAL_ERR_SWAPPER_CTRL: Error during device initialization: failed
138  * to set Xframe byte swapper in accordnace with the host
139  * endian-ness.
140  * @XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT: Failed to restore the device to
141  * a "quiescent" state.
142  * @XGE_HAL_ERR_INVALID_MTU_SIZE: Returned when MTU size specified by
143  * caller is not in the (64, 9600) range.
144  * @XGE_HAL_ERR_OUT_OF_MAPPING: Failed to map DMA-able memory.
145  * @XGE_HAL_ERR_BAD_SUBSYSTEM_ID: Bad PCI subsystem ID. (Currently we
146  * check for zero/non-zero only.)
147  * @XGE_HAL_ERR_INVALID_BAR_ID: Invalid BAR ID. Xframe supports two Base
148  * Address Register Spaces: BAR0 (id=0) and BAR1 (id=1).
149  * @XGE_HAL_ERR_INVALID_OFFSET: Invalid offset. Example, attempt to read
150  * register value (with offset) outside of the BAR0 space.
151  * @XGE_HAL_ERR_INVALID_DEVICE: Invalid device. The HAL device handle
152  * (passed by ULD) is invalid.
153  * @XGE_HAL_ERR_OUT_OF_SPACE: Out-of-provided-buffer-space. Returned by
154  * management "get" routines when the retrieved information does
155  * not fit into the provided buffer.
156  * @XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE: Invalid bit size.
157  * @XGE_HAL_ERR_VERSION_CONFLICT: Upper-layer driver and HAL (versions)
158  * are not compatible.
159  * @XGE_HAL_ERR_INVALID_MAC_ADDRESS: Invalid MAC address.
160  * @XGE_HAL_ERR_SPDM_NOT_ENABLED: SPDM support is not enabled.
161  * @XGE_HAL_ERR_SPDM_TABLE_FULL: SPDM table is full.
162  * @XGE_HAL_ERR_SPDM_INVALID_ENTRY: Invalid SPDM entry.
163  * @XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND: Unable to locate the entry in the
164  * SPDM table.
165  * @XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT: Local SPDM table is not in
166  * synch ith the actual one.
167  * @XGE_HAL_ERR_INVALID_PCI_INFO: Invalid or unrecognized PCI frequency,
168  * and or width, and or mode (Xframe-II only, see UG on PCI_INFO register).
169  * @XGE_HAL_ERR_CRITICAL: Critical error. Returned by HAL APIs
170  * (including xge_hal_device_handle_tcode()) on: ECC, parity, SERR.
171  * Also returned when PIO read does not go through ("all-foxes")
172  * because of "slot-freeze".
173  * @XGE_HAL_ERR_RESET_FAILED: Failed to soft-reset the device.
174  * Returned by xge_hal_device_reset(). One circumstance when it could
175  * happen: slot freeze by the system (see @XGE_HAL_ERR_CRITICAL).
176  * @XGE_HAL_ERR_TOO_MANY: This error is returned if there were laready
177  * maximum number of sessions or queues allocated
178  * @XGE_HAL_ERR_PKT_DROP: TBD
179  * @XGE_HAL_BADCFG_TX_URANGE_A: Invalid Tx link utilization range A. See
180  * the structure xge_hal_tti_config_t{} for valid values.
181  * @XGE_HAL_BADCFG_TX_UFC_A: Invalid frame count for Tx link utilization
182  * range A. See the structure xge_hal_tti_config_t{} for valid values.
183  * @XGE_HAL_BADCFG_TX_URANGE_B: Invalid Tx link utilization range B. See
184  * the structure xge_hal_tti_config_t{} for valid values.
185  * @XGE_HAL_BADCFG_TX_UFC_B: Invalid frame count for Tx link utilization
186  * range B. See the strucuture  xge_hal_tti_config_t{} for valid values.
187  * @XGE_HAL_BADCFG_TX_URANGE_C: Invalid Tx link utilization range C. See
188  * the structure  xge_hal_tti_config_t{} for valid values.
189  * @XGE_HAL_BADCFG_TX_UFC_C: Invalid frame count for Tx link utilization
190  * range C. See the structure xge_hal_tti_config_t{} for valid values.
191  * @XGE_HAL_BADCFG_TX_UFC_D: Invalid frame count for Tx link utilization
192  * range D. See the structure  xge_hal_tti_config_t{} for valid values.
193  * @XGE_HAL_BADCFG_TX_TIMER_VAL: Invalid Tx timer value. See the
194  * structure xge_hal_tti_config_t{} for valid values.
195  * @XGE_HAL_BADCFG_TX_TIMER_CI_EN: Invalid Tx timer continuous interrupt
196  * enable. See the structure xge_hal_tti_config_t{} for valid values.
197  * @XGE_HAL_BADCFG_RX_URANGE_A: Invalid Rx link utilization range A. See
198  * the structure xge_hal_rti_config_t{} for valid values.
199  * @XGE_HAL_BADCFG_RX_UFC_A: Invalid frame count for Rx link utilization
200  * range A. See the structure xge_hal_rti_config_t{} for valid values.
201  * @XGE_HAL_BADCFG_RX_URANGE_B: Invalid Rx link utilization range B. See
202  * the structure xge_hal_rti_config_t{} for valid values.
203  * @XGE_HAL_BADCFG_RX_UFC_B: Invalid frame count for Rx link utilization
204  * range B. See the structure xge_hal_rti_config_t{} for valid values.
205  * @XGE_HAL_BADCFG_RX_URANGE_C: Invalid Rx link utilization range C. See
206  * the structure xge_hal_rti_config_t{} for valid values.
207  * @XGE_HAL_BADCFG_RX_UFC_C: Invalid frame count for Rx link utilization
208  * range C. See the structure xge_hal_rti_config_t{} for valid values.
209  * @XGE_HAL_BADCFG_RX_UFC_D: Invalid frame count for Rx link utilization
210  * range D. See the structure xge_hal_rti_config_t{} for valid values.
211  * @XGE_HAL_BADCFG_RX_TIMER_VAL:  Invalid Rx timer value. See the
212  * structure xge_hal_rti_config_t{} for valid values.
213  * @XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH: Invalid initial fifo queue
214  * length. See the structure xge_hal_fifo_queue_t for valid values.
215  * @XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH: Invalid fifo queue max length.
216  * See the structure xge_hal_fifo_queue_t for valid values.
217  * @XGE_HAL_BADCFG_FIFO_QUEUE_INTR: Invalid fifo queue interrupt mode.
218  * See the structure xge_hal_fifo_queue_t for valid values.
219  * @XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS: Invalid Initial number of
220  * RxD blocks for the ring. See the structure xge_hal_ring_queue_t for
221  * valid values.
222  * @XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS: Invalid maximum number of RxD
223  * blocks for the ring. See the structure xge_hal_ring_queue_t for
224  * valid values.
225  * @XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE: Invalid ring buffer mode. See
226  * the structure xge_hal_ring_queue_t for valid values.
227  * @XGE_HAL_BADCFG_RING_QUEUE_SIZE: Invalid ring queue size. See the
228  * structure xge_hal_ring_queue_t for valid values.
229  * @XGE_HAL_BADCFG_BACKOFF_INTERVAL_US: Invalid backoff timer interval
230  * for the ring. See the structure xge_hal_ring_queue_t for valid values.
231  * @XGE_HAL_BADCFG_MAX_FRM_LEN: Invalid ring max frame length. See the
232  * structure xge_hal_ring_queue_t for valid values.
233  * @XGE_HAL_BADCFG_RING_PRIORITY: Invalid ring priority. See the
234  * structure xge_hal_ring_queue_t for valid values.
235  * @XGE_HAL_BADCFG_TMAC_UTIL_PERIOD: Invalid tmac util period. See the
236  * structure xge_hal_mac_config_t{} for valid values.
237  * @XGE_HAL_BADCFG_RMAC_UTIL_PERIOD: Invalid rmac util period. See the
238  * structure xge_hal_mac_config_t{} for valid values.
239  * @XGE_HAL_BADCFG_RMAC_BCAST_EN: Invalid rmac brodcast enable. See the
240  * structure xge_hal_mac_config_t{} for valid values.
241  * @XGE_HAL_BADCFG_RMAC_HIGH_PTIME: Invalid rmac pause time. See the
242  * structure xge_hal_mac_config_t{} for valid values.
243  * @XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3: Invalid threshold for pause
244  * frame generation for queues 0 through 3. See the structure
245  * xge_hal_mac_config_t{} for valid values.
246  * @XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7:Invalid threshold for pause
247  * frame generation for queues 4 through 7. See the structure
248  * xge_hal_mac_config_t{} for valid values.
249  * @XGE_HAL_BADCFG_FIFO_FRAGS: Invalid fifo max fragments length. See
250  * the structure xge_hal_fifo_config_t{} for valid values.
251  * @XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD: Invalid fifo reserve
252  * threshold. See the structure xge_hal_fifo_config_t{} for valid values.
253  * @XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE: Invalid fifo descriptors memblock
254  * size. See the structure xge_hal_fifo_config_t{} for valid values.
255  * @XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE: Invalid ring descriptors memblock
256  * size. See the structure xge_hal_ring_config_t{} for valid values.
257  * @XGE_HAL_BADCFG_MAX_MTU: Invalid max mtu for the device. See the
258  * structure xge_hal_device_config_t{} for valid values.
259  * @XGE_HAL_BADCFG_ISR_POLLING_CNT: Invalid isr polling count. See the
260  * structure xge_hal_device_config_t{} for valid values.
261  * @XGE_HAL_BADCFG_LATENCY_TIMER: Invalid Latency timer. See the
262  * structure xge_hal_device_config_t{} for valid values.
263  * @XGE_HAL_BADCFG_MAX_SPLITS_TRANS: Invalid maximum  number of pci-x
264  * split transactions. See the structure xge_hal_device_config_t{} for valid
265  * values.
266  * @XGE_HAL_BADCFG_MMRB_COUNT: Invalid mmrb count.  See the structure
267  * xge_hal_device_config_t{} for valid values.
268  * @XGE_HAL_BADCFG_SHARED_SPLITS: Invalid number of outstanding split
269  * transactions that is shared by Tx and Rx requests. See the structure
270  * xge_hal_device_config_t{} for valid values.
271  * @XGE_HAL_BADCFG_STATS_REFRESH_TIME: Invalid time interval for
272  * automatic statistics transfer to the host. See the structure
273  * xge_hal_device_config_t{} for valid values.
274  * @XGE_HAL_BADCFG_PCI_FREQ_MHERZ:  Invalid pci clock frequency. See the
275  * structure xge_hal_device_config_t{} for valid values.
276  * @XGE_HAL_BADCFG_PCI_MODE: Invalid pci mode. See the structure
277  * xge_hal_device_config_t{} for valid values.
278  * @XGE_HAL_BADCFG_INTR_MODE: Invalid interrupt mode. See the structure
279  * xge_hal_device_config_t{} for valid values.
280  * @XGE_HAL_BADCFG_SCHED_TIMER_US: Invalid scheduled timer interval to
281  * generate interrupt. See the structure  xge_hal_device_config_t{}
282  * for valid values.
283  * @XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT: Invalid scheduled timer one
284  * shot. See the structure xge_hal_device_config_t{} for valid values.
285  * @XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL: Invalid driver queue initial
286  * size. See the structure xge_hal_driver_config_t{} for valid values.
287  * @XGE_HAL_BADCFG_QUEUE_SIZE_MAX: Invalid driver queue max size.  See
288  * the structure xge_hal_driver_config_t{} for valid values.
289  * @XGE_HAL_BADCFG_RING_RTH_EN: Invalid value of RTH-enable. See
290  * the structure xge_hal_ring_queue_t for valid values.
291  * @XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS: Invalid value configured for
292  * indicate_max_pkts variable.
293  * @XGE_HAL_BADCFG_TX_TIMER_AC_EN: Invalid value for Tx timer
294  * auto-cancel. See xge_hal_tti_config_t{}.
295  * @XGE_HAL_BADCFG_RX_TIMER_AC_EN: Invalid value for Rx timer
296  * auto-cancel. See xge_hal_rti_config_t{}.
297  * @XGE_HAL_BADCFG_RXUFCA_INTR_THRES: TODO
298  * @XGE_HAL_BADCFG_RXUFCA_LO_LIM: TODO
299  * @XGE_HAL_BADCFG_RXUFCA_HI_LIM: TODO
300  * @XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD: TODO
301  * @XGE_HAL_BADCFG_TRACEBUF_SIZE: Bad configuration: the size of the circular
302  * (in memory) trace buffer either too large or too small. See the
303  * the corresponding header file or README for the acceptable range.
304  * @XGE_HAL_BADCFG_LINK_VALID_CNT: Bad configuration: the link-valid
305  * counter cannot have the specified value. Note that the link-valid
306  * counting is done only at device-open time, to determine with the
307  * specified certainty that the link is up. See the
308  * the corresponding header file or README for the acceptable range.
309  * See also @XGE_HAL_BADCFG_LINK_RETRY_CNT.
310  * @XGE_HAL_BADCFG_LINK_RETRY_CNT: Bad configuration: the specified
311  * link-up retry count is out of the valid range. Note that the link-up
312  * retry counting is done only at device-open time.
313  * See also xge_hal_device_config_t{}.
314  * @XGE_HAL_BADCFG_LINK_STABILITY_PERIOD: Invalid link stability period.
315  * @XGE_HAL_BADCFG_DEVICE_POLL_MILLIS: Invalid device poll interval.
316  * @XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN: TBD
317  * @XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN: TBD
318  * @XGE_HAL_BADCFG_MEDIA: TBD
319  * @XGE_HAL_BADCFG_NO_ISR_EVENTS: TBD
320  * See the structure xge_hal_device_config_t{} for valid values.
321  * @XGE_HAL_EOF_TRACE_BUF: End of the circular (in memory) trace buffer.
322  * Returned by xge_hal_mgmt_trace_read(), when user tries to read the trace
323  * past the buffer limits. Used to enable user to load the trace in two
324  * or more reads.
325  * @XGE_HAL_BADCFG_RING_RTS_MAC_EN: Invalid value of RTS_MAC_EN enable. See
326  * the structure xge_hal_ring_queue_t for valid values.
327  * @XGE_HAL_BADCFG_LRO_SG_SIZE : Invalid value of LRO scatter gatter size.
328  * See the structure xge_hal_device_config_t for valid values.
329  * @XGE_HAL_BADCFG_LRO_FRM_LEN : Invalid value of LRO frame length.
330  * See the structure xge_hal_device_config_t for valid values.
331  * @XGE_HAL_BADCFG_WQE_NUM_ODS: TBD
332  * @XGE_HAL_BADCFG_BIMODAL_INTR: Invalid value to configure bimodal interrupts
333  * Enumerates status and error codes returned by HAL public
334  * API functions.
335  * @XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US: TBD
336  * @XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US: TBD
337  * @XGE_HAL_BADCFG_BIMODAL_XENA_NOT_ALLOWED: TBD
338  * @XGE_HAL_BADCFG_RTS_QOS_EN: TBD
339  * @XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR: TBD
340  * @XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR: TBD
341  * @XGE_HAL_BADCFG_RTS_PORT_EN: TBD
342  * @XGE_HAL_BADCFG_RING_RTS_PORT_EN: TBD
343  *
344  */
345 typedef enum xge_hal_status_e {
346 	XGE_HAL_OK				= 0,
347 	XGE_HAL_FAIL				= 1,
348 	XGE_HAL_COMPLETIONS_REMAIN		= 2,
349 
350 	XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS = XGE_HAL_BASE_INF + 1,
351 	XGE_HAL_INF_OUT_OF_DESCRIPTORS		= XGE_HAL_BASE_INF + 2,
352 	XGE_HAL_INF_CHANNEL_IS_NOT_READY	= XGE_HAL_BASE_INF + 3,
353 	XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING	= XGE_HAL_BASE_INF + 4,
354 	XGE_HAL_INF_STATS_IS_NOT_READY		= XGE_HAL_BASE_INF + 5,
355 	XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS	= XGE_HAL_BASE_INF + 6,
356 	XGE_HAL_INF_IRQ_POLLING_CONTINUE	= XGE_HAL_BASE_INF + 7,
357 	XGE_HAL_INF_LRO_BEGIN			= XGE_HAL_BASE_INF + 8,
358 	XGE_HAL_INF_LRO_CONT			= XGE_HAL_BASE_INF + 9,
359 	XGE_HAL_INF_LRO_UNCAPABLE		= XGE_HAL_BASE_INF + 10,
360 	XGE_HAL_INF_LRO_END_1			= XGE_HAL_BASE_INF + 11,
361 	XGE_HAL_INF_LRO_END_2			= XGE_HAL_BASE_INF + 12,
362 	XGE_HAL_INF_LRO_END_3			= XGE_HAL_BASE_INF + 13,
363 	XGE_HAL_INF_LRO_SESSIONS_XCDED		= XGE_HAL_BASE_INF + 14,
364 	XGE_HAL_INF_NOT_ENOUGH_HW_CQES		= XGE_HAL_BASE_INF + 15,
365 	XGE_HAL_ERR_DRIVER_NOT_INITIALIZED	= XGE_HAL_BASE_ERR + 1,
366 	XGE_HAL_ERR_OUT_OF_MEMORY		= XGE_HAL_BASE_ERR + 4,
367 	XGE_HAL_ERR_CHANNEL_NOT_FOUND		= XGE_HAL_BASE_ERR + 5,
368 	XGE_HAL_ERR_WRONG_IRQ			= XGE_HAL_BASE_ERR + 6,
369 	XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES	= XGE_HAL_BASE_ERR + 7,
370 	XGE_HAL_ERR_SWAPPER_CTRL		= XGE_HAL_BASE_ERR + 8,
371 	XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT	= XGE_HAL_BASE_ERR + 9,
372 	XGE_HAL_ERR_INVALID_MTU_SIZE		= XGE_HAL_BASE_ERR + 10,
373 	XGE_HAL_ERR_OUT_OF_MAPPING		= XGE_HAL_BASE_ERR + 11,
374 	XGE_HAL_ERR_BAD_SUBSYSTEM_ID		= XGE_HAL_BASE_ERR + 12,
375 	XGE_HAL_ERR_INVALID_BAR_ID		= XGE_HAL_BASE_ERR + 13,
376 	XGE_HAL_ERR_INVALID_OFFSET		= XGE_HAL_BASE_ERR + 14,
377 	XGE_HAL_ERR_INVALID_DEVICE		= XGE_HAL_BASE_ERR + 15,
378 	XGE_HAL_ERR_OUT_OF_SPACE		= XGE_HAL_BASE_ERR + 16,
379 	XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE	= XGE_HAL_BASE_ERR + 17,
380 	XGE_HAL_ERR_VERSION_CONFLICT		= XGE_HAL_BASE_ERR + 18,
381 	XGE_HAL_ERR_INVALID_MAC_ADDRESS		= XGE_HAL_BASE_ERR + 19,
382 	XGE_HAL_ERR_BAD_DEVICE_ID		= XGE_HAL_BASE_ERR + 20,
383         XGE_HAL_ERR_OUT_ALIGNED_FRAGS           = XGE_HAL_BASE_ERR + 21,
384 	XGE_HAL_ERR_DEVICE_NOT_INITIALIZED	= XGE_HAL_BASE_ERR + 22,
385 	XGE_HAL_ERR_SPDM_NOT_ENABLED		= XGE_HAL_BASE_ERR + 23,
386 	XGE_HAL_ERR_SPDM_TABLE_FULL		= XGE_HAL_BASE_ERR + 24,
387 	XGE_HAL_ERR_SPDM_INVALID_ENTRY		= XGE_HAL_BASE_ERR + 25,
388 	XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND	= XGE_HAL_BASE_ERR + 26,
389 	XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT= XGE_HAL_BASE_ERR + 27,
390 	XGE_HAL_ERR_INVALID_PCI_INFO		= XGE_HAL_BASE_ERR + 28,
391 	XGE_HAL_ERR_CRITICAL		        = XGE_HAL_BASE_ERR + 29,
392 	XGE_HAL_ERR_RESET_FAILED		= XGE_HAL_BASE_ERR + 30,
393 	XGE_HAL_ERR_TOO_MANY			= XGE_HAL_BASE_ERR + 32,
394 	XGE_HAL_ERR_PKT_DROP		        = XGE_HAL_BASE_ERR + 33,
395 
396 	XGE_HAL_BADCFG_TX_URANGE_A		= XGE_HAL_BASE_BADCFG + 1,
397 	XGE_HAL_BADCFG_TX_UFC_A			= XGE_HAL_BASE_BADCFG + 2,
398 	XGE_HAL_BADCFG_TX_URANGE_B		= XGE_HAL_BASE_BADCFG + 3,
399 	XGE_HAL_BADCFG_TX_UFC_B			= XGE_HAL_BASE_BADCFG + 4,
400 	XGE_HAL_BADCFG_TX_URANGE_C		= XGE_HAL_BASE_BADCFG + 5,
401 	XGE_HAL_BADCFG_TX_UFC_C			= XGE_HAL_BASE_BADCFG + 6,
402 	XGE_HAL_BADCFG_TX_UFC_D			= XGE_HAL_BASE_BADCFG + 8,
403 	XGE_HAL_BADCFG_TX_TIMER_VAL		= XGE_HAL_BASE_BADCFG + 9,
404 	XGE_HAL_BADCFG_TX_TIMER_CI_EN		= XGE_HAL_BASE_BADCFG + 10,
405 	XGE_HAL_BADCFG_RX_URANGE_A		= XGE_HAL_BASE_BADCFG + 11,
406 	XGE_HAL_BADCFG_RX_UFC_A			= XGE_HAL_BASE_BADCFG + 12,
407 	XGE_HAL_BADCFG_RX_URANGE_B		= XGE_HAL_BASE_BADCFG + 13,
408 	XGE_HAL_BADCFG_RX_UFC_B			= XGE_HAL_BASE_BADCFG + 14,
409 	XGE_HAL_BADCFG_RX_URANGE_C		= XGE_HAL_BASE_BADCFG + 15,
410 	XGE_HAL_BADCFG_RX_UFC_C			= XGE_HAL_BASE_BADCFG + 16,
411 	XGE_HAL_BADCFG_RX_UFC_D			= XGE_HAL_BASE_BADCFG + 17,
412 	XGE_HAL_BADCFG_RX_TIMER_VAL		= XGE_HAL_BASE_BADCFG + 18,
413 	XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH= XGE_HAL_BASE_BADCFG +	19,
414 	XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH    = XGE_HAL_BASE_BADCFG + 20,
415 	XGE_HAL_BADCFG_FIFO_QUEUE_INTR		= XGE_HAL_BASE_BADCFG + 21,
416 	XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS=XGE_HAL_BASE_BADCFG +	22,
417 	XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS	= XGE_HAL_BASE_BADCFG +	23,
418 	XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE	= XGE_HAL_BASE_BADCFG +	24,
419 	XGE_HAL_BADCFG_RING_QUEUE_SIZE		= XGE_HAL_BASE_BADCFG + 25,
420 	XGE_HAL_BADCFG_BACKOFF_INTERVAL_US	= XGE_HAL_BASE_BADCFG + 26,
421 	XGE_HAL_BADCFG_MAX_FRM_LEN		= XGE_HAL_BASE_BADCFG + 27,
422 	XGE_HAL_BADCFG_RING_PRIORITY		= XGE_HAL_BASE_BADCFG + 28,
423 	XGE_HAL_BADCFG_TMAC_UTIL_PERIOD		= XGE_HAL_BASE_BADCFG + 29,
424 	XGE_HAL_BADCFG_RMAC_UTIL_PERIOD		= XGE_HAL_BASE_BADCFG + 30,
425 	XGE_HAL_BADCFG_RMAC_BCAST_EN		= XGE_HAL_BASE_BADCFG + 31,
426 	XGE_HAL_BADCFG_RMAC_HIGH_PTIME		= XGE_HAL_BASE_BADCFG + 32,
427 	XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3	= XGE_HAL_BASE_BADCFG +33,
428 	XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7	= XGE_HAL_BASE_BADCFG +	34,
429 	XGE_HAL_BADCFG_FIFO_FRAGS		= XGE_HAL_BASE_BADCFG + 35,
430 	XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD	= XGE_HAL_BASE_BADCFG +	37,
431 	XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE	= XGE_HAL_BASE_BADCFG + 38,
432 	XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE	= XGE_HAL_BASE_BADCFG +	39,
433 	XGE_HAL_BADCFG_MAX_MTU			= XGE_HAL_BASE_BADCFG + 40,
434 	XGE_HAL_BADCFG_ISR_POLLING_CNT		= XGE_HAL_BASE_BADCFG + 41,
435 	XGE_HAL_BADCFG_LATENCY_TIMER		= XGE_HAL_BASE_BADCFG + 42,
436 	XGE_HAL_BADCFG_MAX_SPLITS_TRANS		= XGE_HAL_BASE_BADCFG + 43,
437 	XGE_HAL_BADCFG_MMRB_COUNT		= XGE_HAL_BASE_BADCFG + 44,
438 	XGE_HAL_BADCFG_SHARED_SPLITS		= XGE_HAL_BASE_BADCFG + 45,
439 	XGE_HAL_BADCFG_STATS_REFRESH_TIME	= XGE_HAL_BASE_BADCFG +	46,
440 	XGE_HAL_BADCFG_PCI_FREQ_MHERZ		= XGE_HAL_BASE_BADCFG + 47,
441 	XGE_HAL_BADCFG_PCI_MODE			= XGE_HAL_BASE_BADCFG + 48,
442 	XGE_HAL_BADCFG_INTR_MODE		= XGE_HAL_BASE_BADCFG + 49,
443 	XGE_HAL_BADCFG_SCHED_TIMER_US		= XGE_HAL_BASE_BADCFG + 50,
444 	XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT	= XGE_HAL_BASE_BADCFG + 51,
445 	XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL	= XGE_HAL_BASE_BADCFG + 52,
446 	XGE_HAL_BADCFG_QUEUE_SIZE_MAX		= XGE_HAL_BASE_BADCFG + 53,
447 	XGE_HAL_BADCFG_RING_RTH_EN		= XGE_HAL_BASE_BADCFG + 54,
448 	XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS	= XGE_HAL_BASE_BADCFG + 55,
449 	XGE_HAL_BADCFG_TX_TIMER_AC_EN		= XGE_HAL_BASE_BADCFG +	56,
450 	XGE_HAL_BADCFG_RX_TIMER_AC_EN		= XGE_HAL_BASE_BADCFG +	57,
451 	XGE_HAL_BADCFG_RXUFCA_INTR_THRES	= XGE_HAL_BASE_BADCFG + 58,
452 	XGE_HAL_BADCFG_RXUFCA_LO_LIM		= XGE_HAL_BASE_BADCFG + 59,
453 	XGE_HAL_BADCFG_RXUFCA_HI_LIM		= XGE_HAL_BASE_BADCFG + 60,
454 	XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD	= XGE_HAL_BASE_BADCFG + 61,
455 	XGE_HAL_BADCFG_TRACEBUF_SIZE		= XGE_HAL_BASE_BADCFG + 62,
456 	XGE_HAL_BADCFG_LINK_VALID_CNT		= XGE_HAL_BASE_BADCFG + 63,
457 	XGE_HAL_BADCFG_LINK_RETRY_CNT		= XGE_HAL_BASE_BADCFG + 64,
458 	XGE_HAL_BADCFG_LINK_STABILITY_PERIOD	= XGE_HAL_BASE_BADCFG + 65,
459 	XGE_HAL_BADCFG_DEVICE_POLL_MILLIS       = XGE_HAL_BASE_BADCFG + 66,
460 	XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN	= XGE_HAL_BASE_BADCFG + 67,
461 	XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN	= XGE_HAL_BASE_BADCFG + 68,
462 	XGE_HAL_BADCFG_MEDIA			= XGE_HAL_BASE_BADCFG + 69,
463 	XGE_HAL_BADCFG_NO_ISR_EVENTS		= XGE_HAL_BASE_BADCFG + 70,
464 	XGE_HAL_BADCFG_RING_RTS_MAC_EN		= XGE_HAL_BASE_BADCFG + 71,
465 	XGE_HAL_BADCFG_LRO_SG_SIZE		= XGE_HAL_BASE_BADCFG + 72,
466 	XGE_HAL_BADCFG_LRO_FRM_LEN		= XGE_HAL_BASE_BADCFG + 73,
467 	XGE_HAL_BADCFG_WQE_NUM_ODS		= XGE_HAL_BASE_BADCFG + 74,
468 	XGE_HAL_BADCFG_BIMODAL_INTR		= XGE_HAL_BASE_BADCFG + 75,
469 	XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US	= XGE_HAL_BASE_BADCFG + 76,
470 	XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US	= XGE_HAL_BASE_BADCFG + 77,
471 	XGE_HAL_BADCFG_BIMODAL_XENA_NOT_ALLOWED	= XGE_HAL_BASE_BADCFG + 78,
472 	XGE_HAL_BADCFG_RTS_QOS_EN		= XGE_HAL_BASE_BADCFG + 79,
473 	XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR	= XGE_HAL_BASE_BADCFG + 80,
474 	XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR	= XGE_HAL_BASE_BADCFG + 81,
475 	XGE_HAL_BADCFG_RTS_PORT_EN		= XGE_HAL_BASE_BADCFG + 82,
476 	XGE_HAL_BADCFG_RING_RTS_PORT_EN		= XGE_HAL_BASE_BADCFG + 83,
477 	XGE_HAL_BADCFG_TRACEBUF_TIMESTAMP	= XGE_HAL_BASE_BADCFG + 84,
478 	XGE_HAL_EOF_TRACE_BUF			= -1
479 } xge_hal_status_e;
480 
481 #define XGE_HAL_ETH_ALEN				6
482 typedef u8 macaddr_t[XGE_HAL_ETH_ALEN];
483 
484 #define XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE		0x100
485 
486 /* frames sizes */
487 #define XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE		14
488 #define XGE_HAL_HEADER_802_2_SIZE			3
489 #define XGE_HAL_HEADER_SNAP_SIZE			5
490 #define XGE_HAL_HEADER_VLAN_SIZE			4
491 #define XGE_HAL_MAC_HEADER_MAX_SIZE \
492 			(XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE + \
493 			 XGE_HAL_HEADER_802_2_SIZE + \
494 			 XGE_HAL_HEADER_SNAP_SIZE)
495 
496 #define XGE_HAL_TCPIP_HEADER_MAX_SIZE			(64 + 64)
497 
498 /* 32bit alignments */
499 #define XGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN		2
500 #define XGE_HAL_HEADER_802_2_SNAP_ALIGN			2
501 #define XGE_HAL_HEADER_802_2_ALIGN			3
502 #define XGE_HAL_HEADER_SNAP_ALIGN			1
503 
504 #define XGE_HAL_L3_CKSUM_OK				0xFFFF
505 #define XGE_HAL_L4_CKSUM_OK				0xFFFF
506 #define XGE_HAL_MIN_MTU					46
507 #define XGE_HAL_MAX_MTU					9600
508 #define XGE_HAL_DEFAULT_MTU				1500
509 
510 #define XGE_HAL_SEGEMENT_OFFLOAD_MAX_SIZE	81920
511 
512 #define XGE_HAL_PCISIZE_XENA			26 /* multiples of dword */
513 #define XGE_HAL_PCISIZE_HERC			64 /* multiples of dword */
514 
515 #define XGE_HAL_MAX_MSIX_MESSAGES	64
516 #define XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR XGE_HAL_MAX_MSIX_MESSAGES * 2
517 /*  Highest level interrupt blocks */
518 #define XGE_HAL_TX_PIC_INTR     (0x0001<<0)
519 #define XGE_HAL_TX_DMA_INTR     (0x0001<<1)
520 #define XGE_HAL_TX_MAC_INTR     (0x0001<<2)
521 #define XGE_HAL_TX_XGXS_INTR    (0x0001<<3)
522 #define XGE_HAL_TX_TRAFFIC_INTR (0x0001<<4)
523 #define XGE_HAL_RX_PIC_INTR     (0x0001<<5)
524 #define XGE_HAL_RX_DMA_INTR     (0x0001<<6)
525 #define XGE_HAL_RX_MAC_INTR     (0x0001<<7)
526 #define XGE_HAL_RX_XGXS_INTR    (0x0001<<8)
527 #define XGE_HAL_RX_TRAFFIC_INTR (0x0001<<9)
528 #define XGE_HAL_MC_INTR         (0x0001<<10)
529 #define XGE_HAL_SCHED_INTR      (0x0001<<11)
530 #define XGE_HAL_ALL_INTRS       (XGE_HAL_TX_PIC_INTR   | \
531                                XGE_HAL_TX_DMA_INTR     | \
532                                XGE_HAL_TX_MAC_INTR     | \
533                                XGE_HAL_TX_XGXS_INTR    | \
534                                XGE_HAL_TX_TRAFFIC_INTR | \
535                                XGE_HAL_RX_PIC_INTR     | \
536                                XGE_HAL_RX_DMA_INTR     | \
537                                XGE_HAL_RX_MAC_INTR     | \
538                                XGE_HAL_RX_XGXS_INTR    | \
539                                XGE_HAL_RX_TRAFFIC_INTR | \
540                                XGE_HAL_MC_INTR	       | \
541 			       XGE_HAL_SCHED_INTR)
542 #define XGE_HAL_GEN_MASK_INTR    (0x0001<<12)
543 
544 /* Interrupt masks for the general interrupt mask register */
545 #define XGE_HAL_ALL_INTRS_DIS   0xFFFFFFFFFFFFFFFFULL
546 
547 #define XGE_HAL_TXPIC_INT_M     BIT(0)
548 #define XGE_HAL_TXDMA_INT_M     BIT(1)
549 #define XGE_HAL_TXMAC_INT_M     BIT(2)
550 #define XGE_HAL_TXXGXS_INT_M    BIT(3)
551 #define XGE_HAL_TXTRAFFIC_INT_M BIT(8)
552 #define XGE_HAL_PIC_RX_INT_M    BIT(32)
553 #define XGE_HAL_RXDMA_INT_M     BIT(33)
554 #define XGE_HAL_RXMAC_INT_M     BIT(34)
555 #define XGE_HAL_MC_INT_M        BIT(35)
556 #define XGE_HAL_RXXGXS_INT_M    BIT(36)
557 #define XGE_HAL_RXTRAFFIC_INT_M BIT(40)
558 
559 /* MSI level Interrupts */
560 #define XGE_HAL_MAX_MSIX_VECTORS	(16)
561 
562 typedef struct xge_hal_ipv4 {
563 	u32 addr;
564 }xge_hal_ipv4;
565 
566 typedef struct xge_hal_ipv6 {
567 	u64 addr[2];
568 }xge_hal_ipv6;
569 
570 typedef union xge_hal_ipaddr_t {
571 	xge_hal_ipv4 ipv4;
572 	xge_hal_ipv6 ipv6;
573 }xge_hal_ipaddr_t;
574 
575 /* DMA level Interrupts */
576 #define XGE_HAL_TXDMA_PFC_INT_M	BIT(0)
577 
578 /*  PFC block interrupts */
579 #define XGE_HAL_PFC_MISC_ERR_1	BIT(0)   /* Interrupt to indicate FIFO
580 full */
581 
582 /* basic handles */
583 typedef void* xge_hal_device_h;
584 typedef void* xge_hal_dtr_h;
585 typedef void* xge_hal_channel_h;
586 
587 /*
588  * I2C device id. Used in I2C control register for accessing EEPROM device
589  * memory.
590  */
591 #define XGE_DEV_ID		5
592 
593 typedef enum xge_hal_xpak_alarm_type_e {
594 	XGE_HAL_XPAK_ALARM_EXCESS_TEMP = 1,
595 	XGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT = 2,
596 	XGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT = 3,
597 } xge_hal_xpak_alarm_type_e;
598 
599 
600 __EXTERN_END_DECLS
601 
602 #endif /* XGE_HAL_TYPES_H */
603