xref: /linux/drivers/video/fbdev/cyber2000fb.c (revision 06d07429858317ded2db7986113a9e0129cd599b)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  linux/drivers/video/cyber2000fb.c
4  *
5  *  Copyright (C) 1998-2002 Russell King
6  *
7  *  MIPS and 50xx clock support
8  *  Copyright (C) 2001 Bradley D. LaRonde <brad@ltc.com>
9  *
10  *  32 bit support, text color and panning fixes for modes != 8 bit
11  *  Copyright (C) 2002 Denis Oliver Kropp <dok@directfb.org>
12  *
13  * Integraphics CyberPro 2000, 2010 and 5000 frame buffer device
14  *
15  * Based on cyberfb.c.
16  *
17  * Note that we now use the new fbcon fix, var and cmap scheme.  We do
18  * still have to check which console is the currently displayed one
19  * however, especially for the colourmap stuff.
20  *
21  * We also use the new hotplug PCI subsystem.  I'm not sure if there
22  * are any such cards, but I'm erring on the side of caution.  We don't
23  * want to go pop just because someone does have one.
24  *
25  * Note that this doesn't work fully in the case of multiple CyberPro
26  * cards with grabbers.  We currently can only attach to the first
27  * CyberPro card found.
28  *
29  * When we're in truecolour mode, we power down the LUT RAM as a power
30  * saving feature.  Also, when we enter any of the powersaving modes
31  * (except soft blanking) we power down the RAMDACs.  This saves about
32  * 1W, which is roughly 8% of the power consumption of a NetWinder
33  * (which, incidentally, is about the same saving as a 2.5in hard disk
34  * entering standby mode.)
35  */
36 #include <linux/aperture.h>
37 #include <linux/module.h>
38 #include <linux/kernel.h>
39 #include <linux/errno.h>
40 #include <linux/string.h>
41 #include <linux/mm.h>
42 #include <linux/slab.h>
43 #include <linux/delay.h>
44 #include <linux/fb.h>
45 #include <linux/pci.h>
46 #include <linux/init.h>
47 #include <linux/io.h>
48 #include <linux/i2c.h>
49 #include <linux/i2c-algo-bit.h>
50 
51 #ifdef __arm__
52 #include <asm/mach-types.h>
53 #endif
54 
55 #include "cyber2000fb.h"
56 
57 struct cfb_info {
58 	struct fb_info		fb;
59 	struct display_switch	*dispsw;
60 	unsigned char		__iomem *region;
61 	unsigned char		__iomem *regs;
62 	u_int			id;
63 	u_int			irq;
64 	int			func_use_count;
65 	u_long			ref_ps;
66 
67 	/*
68 	 * Clock divisors
69 	 */
70 	u_int			divisors[4];
71 
72 	struct {
73 		u8 red, green, blue;
74 	} palette[NR_PALETTE];
75 
76 	u_char			mem_ctl1;
77 	u_char			mem_ctl2;
78 	u_char			mclk_mult;
79 	u_char			mclk_div;
80 	/*
81 	 * RAMDAC control register is both of these or'ed together
82 	 */
83 	u_char			ramdac_ctrl;
84 	u_char			ramdac_powerdown;
85 
86 	u32			pseudo_palette[16];
87 
88 	spinlock_t		reg_b0_lock;
89 
90 #ifdef CONFIG_FB_CYBER2000_DDC
91 	bool			ddc_registered;
92 	struct i2c_adapter	ddc_adapter;
93 	struct i2c_algo_bit_data	ddc_algo;
94 #endif
95 
96 #ifdef CONFIG_FB_CYBER2000_I2C
97 	struct i2c_adapter	i2c_adapter;
98 	struct i2c_algo_bit_data i2c_algo;
99 #endif
100 };
101 
102 static char *default_font = "Acorn8x8";
103 module_param(default_font, charp, 0);
104 MODULE_PARM_DESC(default_font, "Default font name");
105 
106 /*
107  * Our access methods.
108  */
109 #define cyber2000fb_writel(val, reg, cfb)	writel(val, (cfb)->regs + (reg))
110 #define cyber2000fb_writew(val, reg, cfb)	writew(val, (cfb)->regs + (reg))
111 #define cyber2000fb_writeb(val, reg, cfb)	writeb(val, (cfb)->regs + (reg))
112 
113 #define cyber2000fb_readb(reg, cfb)		readb((cfb)->regs + (reg))
114 
115 static inline void
cyber2000_crtcw(unsigned int reg,unsigned int val,struct cfb_info * cfb)116 cyber2000_crtcw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
117 {
118 	cyber2000fb_writew((reg & 255) | val << 8, 0x3d4, cfb);
119 }
120 
121 static inline void
cyber2000_grphw(unsigned int reg,unsigned int val,struct cfb_info * cfb)122 cyber2000_grphw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
123 {
124 	cyber2000fb_writew((reg & 255) | val << 8, 0x3ce, cfb);
125 }
126 
127 static inline unsigned int
cyber2000_grphr(unsigned int reg,struct cfb_info * cfb)128 cyber2000_grphr(unsigned int reg, struct cfb_info *cfb)
129 {
130 	cyber2000fb_writeb(reg, 0x3ce, cfb);
131 	return cyber2000fb_readb(0x3cf, cfb);
132 }
133 
134 static inline void
cyber2000_attrw(unsigned int reg,unsigned int val,struct cfb_info * cfb)135 cyber2000_attrw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
136 {
137 	cyber2000fb_readb(0x3da, cfb);
138 	cyber2000fb_writeb(reg, 0x3c0, cfb);
139 	cyber2000fb_readb(0x3c1, cfb);
140 	cyber2000fb_writeb(val, 0x3c0, cfb);
141 }
142 
143 static inline void
cyber2000_seqw(unsigned int reg,unsigned int val,struct cfb_info * cfb)144 cyber2000_seqw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
145 {
146 	cyber2000fb_writew((reg & 255) | val << 8, 0x3c4, cfb);
147 }
148 
149 /* -------------------- Hardware specific routines ------------------------- */
150 
151 /*
152  * Hardware Cyber2000 Acceleration
153  */
154 static void
cyber2000fb_fillrect(struct fb_info * info,const struct fb_fillrect * rect)155 cyber2000fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
156 {
157 	struct cfb_info *cfb = container_of(info, struct cfb_info, fb);
158 	unsigned long dst, col;
159 
160 	if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
161 		cfb_fillrect(info, rect);
162 		return;
163 	}
164 
165 	cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
166 	cyber2000fb_writew(rect->width - 1, CO_REG_PIXWIDTH, cfb);
167 	cyber2000fb_writew(rect->height - 1, CO_REG_PIXHEIGHT, cfb);
168 
169 	col = rect->color;
170 	if (cfb->fb.var.bits_per_pixel > 8)
171 		col = ((u32 *)cfb->fb.pseudo_palette)[col];
172 	cyber2000fb_writel(col, CO_REG_FGCOLOUR, cfb);
173 
174 	dst = rect->dx + rect->dy * cfb->fb.var.xres_virtual;
175 	if (cfb->fb.var.bits_per_pixel == 24) {
176 		cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb);
177 		dst *= 3;
178 	}
179 
180 	cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb);
181 	cyber2000fb_writeb(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb);
182 	cyber2000fb_writew(CO_CMD_L_PATTERN_FGCOL, CO_REG_CMD_L, cfb);
183 	cyber2000fb_writew(CO_CMD_H_BLITTER, CO_REG_CMD_H, cfb);
184 }
185 
186 static void
cyber2000fb_copyarea(struct fb_info * info,const struct fb_copyarea * region)187 cyber2000fb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
188 {
189 	struct cfb_info *cfb = container_of(info, struct cfb_info, fb);
190 	unsigned int cmd = CO_CMD_L_PATTERN_FGCOL;
191 	unsigned long src, dst;
192 
193 	if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
194 		cfb_copyarea(info, region);
195 		return;
196 	}
197 
198 	cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
199 	cyber2000fb_writew(region->width - 1, CO_REG_PIXWIDTH, cfb);
200 	cyber2000fb_writew(region->height - 1, CO_REG_PIXHEIGHT, cfb);
201 
202 	src = region->sx + region->sy * cfb->fb.var.xres_virtual;
203 	dst = region->dx + region->dy * cfb->fb.var.xres_virtual;
204 
205 	if (region->sx < region->dx) {
206 		src += region->width - 1;
207 		dst += region->width - 1;
208 		cmd |= CO_CMD_L_INC_LEFT;
209 	}
210 
211 	if (region->sy < region->dy) {
212 		src += (region->height - 1) * cfb->fb.var.xres_virtual;
213 		dst += (region->height - 1) * cfb->fb.var.xres_virtual;
214 		cmd |= CO_CMD_L_INC_UP;
215 	}
216 
217 	if (cfb->fb.var.bits_per_pixel == 24) {
218 		cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb);
219 		src *= 3;
220 		dst *= 3;
221 	}
222 	cyber2000fb_writel(src, CO_REG_SRC1_PTR, cfb);
223 	cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb);
224 	cyber2000fb_writew(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb);
225 	cyber2000fb_writew(cmd, CO_REG_CMD_L, cfb);
226 	cyber2000fb_writew(CO_CMD_H_FGSRCMAP | CO_CMD_H_BLITTER,
227 			   CO_REG_CMD_H, cfb);
228 }
229 
cyber2000fb_sync(struct fb_info * info)230 static int cyber2000fb_sync(struct fb_info *info)
231 {
232 	struct cfb_info *cfb = container_of(info, struct cfb_info, fb);
233 	int count = 100000;
234 
235 	if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT))
236 		return 0;
237 
238 	while (cyber2000fb_readb(CO_REG_CONTROL, cfb) & CO_CTRL_BUSY) {
239 		if (!count--) {
240 			debug_printf("accel_wait timed out\n");
241 			cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
242 			break;
243 		}
244 		udelay(1);
245 	}
246 	return 0;
247 }
248 
249 /*
250  * ===========================================================================
251  */
252 
convert_bitfield(u_int val,struct fb_bitfield * bf)253 static inline u32 convert_bitfield(u_int val, struct fb_bitfield *bf)
254 {
255 	u_int mask = (1 << bf->length) - 1;
256 
257 	return (val >> (16 - bf->length) & mask) << bf->offset;
258 }
259 
260 /*
261  *    Set a single color register. Return != 0 for invalid regno.
262  */
263 static int
cyber2000fb_setcolreg(u_int regno,u_int red,u_int green,u_int blue,u_int transp,struct fb_info * info)264 cyber2000fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
265 		      u_int transp, struct fb_info *info)
266 {
267 	struct cfb_info *cfb = container_of(info, struct cfb_info, fb);
268 	struct fb_var_screeninfo *var = &cfb->fb.var;
269 	u32 pseudo_val;
270 	int ret = 1;
271 
272 	switch (cfb->fb.fix.visual) {
273 	default:
274 		return 1;
275 
276 	/*
277 	 * Pseudocolour:
278 	 *	   8     8
279 	 * pixel --/--+--/-->  red lut  --> red dac
280 	 *	      |  8
281 	 *	      +--/--> green lut --> green dac
282 	 *	      |  8
283 	 *	      +--/-->  blue lut --> blue dac
284 	 */
285 	case FB_VISUAL_PSEUDOCOLOR:
286 		if (regno >= NR_PALETTE)
287 			return 1;
288 
289 		red >>= 8;
290 		green >>= 8;
291 		blue >>= 8;
292 
293 		cfb->palette[regno].red = red;
294 		cfb->palette[regno].green = green;
295 		cfb->palette[regno].blue = blue;
296 
297 		cyber2000fb_writeb(regno, 0x3c8, cfb);
298 		cyber2000fb_writeb(red, 0x3c9, cfb);
299 		cyber2000fb_writeb(green, 0x3c9, cfb);
300 		cyber2000fb_writeb(blue, 0x3c9, cfb);
301 		return 0;
302 
303 	/*
304 	 * Direct colour:
305 	 *	   n     rl
306 	 * pixel --/--+--/-->  red lut  --> red dac
307 	 *	      |  gl
308 	 *	      +--/--> green lut --> green dac
309 	 *	      |  bl
310 	 *	      +--/-->  blue lut --> blue dac
311 	 * n = bpp, rl = red length, gl = green length, bl = blue length
312 	 */
313 	case FB_VISUAL_DIRECTCOLOR:
314 		red >>= 8;
315 		green >>= 8;
316 		blue >>= 8;
317 
318 		if (var->green.length == 6 && regno < 64) {
319 			cfb->palette[regno << 2].green = green;
320 
321 			/*
322 			 * The 6 bits of the green component are applied
323 			 * to the high 6 bits of the LUT.
324 			 */
325 			cyber2000fb_writeb(regno << 2, 0x3c8, cfb);
326 			cyber2000fb_writeb(cfb->palette[regno >> 1].red,
327 					   0x3c9, cfb);
328 			cyber2000fb_writeb(green, 0x3c9, cfb);
329 			cyber2000fb_writeb(cfb->palette[regno >> 1].blue,
330 					   0x3c9, cfb);
331 
332 			green = cfb->palette[regno << 3].green;
333 
334 			ret = 0;
335 		}
336 
337 		if (var->green.length >= 5 && regno < 32) {
338 			cfb->palette[regno << 3].red = red;
339 			cfb->palette[regno << 3].green = green;
340 			cfb->palette[regno << 3].blue = blue;
341 
342 			/*
343 			 * The 5 bits of each colour component are
344 			 * applied to the high 5 bits of the LUT.
345 			 */
346 			cyber2000fb_writeb(regno << 3, 0x3c8, cfb);
347 			cyber2000fb_writeb(red, 0x3c9, cfb);
348 			cyber2000fb_writeb(green, 0x3c9, cfb);
349 			cyber2000fb_writeb(blue, 0x3c9, cfb);
350 			ret = 0;
351 		}
352 
353 		if (var->green.length == 4 && regno < 16) {
354 			cfb->palette[regno << 4].red = red;
355 			cfb->palette[regno << 4].green = green;
356 			cfb->palette[regno << 4].blue = blue;
357 
358 			/*
359 			 * The 5 bits of each colour component are
360 			 * applied to the high 5 bits of the LUT.
361 			 */
362 			cyber2000fb_writeb(regno << 4, 0x3c8, cfb);
363 			cyber2000fb_writeb(red, 0x3c9, cfb);
364 			cyber2000fb_writeb(green, 0x3c9, cfb);
365 			cyber2000fb_writeb(blue, 0x3c9, cfb);
366 			ret = 0;
367 		}
368 
369 		/*
370 		 * Since this is only used for the first 16 colours, we
371 		 * don't have to care about overflowing for regno >= 32
372 		 */
373 		pseudo_val = regno << var->red.offset |
374 			     regno << var->green.offset |
375 			     regno << var->blue.offset;
376 		break;
377 
378 	/*
379 	 * True colour:
380 	 *	   n     rl
381 	 * pixel --/--+--/--> red dac
382 	 *	      |  gl
383 	 *	      +--/--> green dac
384 	 *	      |  bl
385 	 *	      +--/--> blue dac
386 	 * n = bpp, rl = red length, gl = green length, bl = blue length
387 	 */
388 	case FB_VISUAL_TRUECOLOR:
389 		pseudo_val = convert_bitfield(transp ^ 0xffff, &var->transp);
390 		pseudo_val |= convert_bitfield(red, &var->red);
391 		pseudo_val |= convert_bitfield(green, &var->green);
392 		pseudo_val |= convert_bitfield(blue, &var->blue);
393 		ret = 0;
394 		break;
395 	}
396 
397 	/*
398 	 * Now set our pseudo palette for the CFB16/24/32 drivers.
399 	 */
400 	if (regno < 16)
401 		((u32 *)cfb->fb.pseudo_palette)[regno] = pseudo_val;
402 
403 	return ret;
404 }
405 
406 struct par_info {
407 	/*
408 	 * Hardware
409 	 */
410 	u_char	clock_mult;
411 	u_char	clock_div;
412 	u_char	extseqmisc;
413 	u_char	co_pixfmt;
414 	u_char	crtc_ofl;
415 	u_char	crtc[19];
416 	u_int	width;
417 	u_int	pitch;
418 	u_int	fetch;
419 
420 	/*
421 	 * Other
422 	 */
423 	u_char	ramdac;
424 };
425 
426 static const u_char crtc_idx[] = {
427 	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
428 	0x08, 0x09,
429 	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18
430 };
431 
cyber2000fb_write_ramdac_ctrl(struct cfb_info * cfb)432 static void cyber2000fb_write_ramdac_ctrl(struct cfb_info *cfb)
433 {
434 	unsigned int i;
435 	unsigned int val = cfb->ramdac_ctrl | cfb->ramdac_powerdown;
436 
437 	cyber2000fb_writeb(0x56, 0x3ce, cfb);
438 	i = cyber2000fb_readb(0x3cf, cfb);
439 	cyber2000fb_writeb(i | 4, 0x3cf, cfb);
440 	cyber2000fb_writeb(val, 0x3c6, cfb);
441 	cyber2000fb_writeb(i, 0x3cf, cfb);
442 	/* prevent card lock-up observed on x86 with CyberPro 2000 */
443 	cyber2000fb_readb(0x3cf, cfb);
444 }
445 
cyber2000fb_set_timing(struct cfb_info * cfb,struct par_info * hw)446 static void cyber2000fb_set_timing(struct cfb_info *cfb, struct par_info *hw)
447 {
448 	u_int i;
449 
450 	/*
451 	 * Blank palette
452 	 */
453 	for (i = 0; i < NR_PALETTE; i++) {
454 		cyber2000fb_writeb(i, 0x3c8, cfb);
455 		cyber2000fb_writeb(0, 0x3c9, cfb);
456 		cyber2000fb_writeb(0, 0x3c9, cfb);
457 		cyber2000fb_writeb(0, 0x3c9, cfb);
458 	}
459 
460 	cyber2000fb_writeb(0xef, 0x3c2, cfb);
461 	cyber2000_crtcw(0x11, 0x0b, cfb);
462 	cyber2000_attrw(0x11, 0x00, cfb);
463 
464 	cyber2000_seqw(0x00, 0x01, cfb);
465 	cyber2000_seqw(0x01, 0x01, cfb);
466 	cyber2000_seqw(0x02, 0x0f, cfb);
467 	cyber2000_seqw(0x03, 0x00, cfb);
468 	cyber2000_seqw(0x04, 0x0e, cfb);
469 	cyber2000_seqw(0x00, 0x03, cfb);
470 
471 	for (i = 0; i < sizeof(crtc_idx); i++)
472 		cyber2000_crtcw(crtc_idx[i], hw->crtc[i], cfb);
473 
474 	for (i = 0x0a; i < 0x10; i++)
475 		cyber2000_crtcw(i, 0, cfb);
476 
477 	cyber2000_grphw(EXT_CRT_VRTOFL, hw->crtc_ofl, cfb);
478 	cyber2000_grphw(0x00, 0x00, cfb);
479 	cyber2000_grphw(0x01, 0x00, cfb);
480 	cyber2000_grphw(0x02, 0x00, cfb);
481 	cyber2000_grphw(0x03, 0x00, cfb);
482 	cyber2000_grphw(0x04, 0x00, cfb);
483 	cyber2000_grphw(0x05, 0x60, cfb);
484 	cyber2000_grphw(0x06, 0x05, cfb);
485 	cyber2000_grphw(0x07, 0x0f, cfb);
486 	cyber2000_grphw(0x08, 0xff, cfb);
487 
488 	/* Attribute controller registers */
489 	for (i = 0; i < 16; i++)
490 		cyber2000_attrw(i, i, cfb);
491 
492 	cyber2000_attrw(0x10, 0x01, cfb);
493 	cyber2000_attrw(0x11, 0x00, cfb);
494 	cyber2000_attrw(0x12, 0x0f, cfb);
495 	cyber2000_attrw(0x13, 0x00, cfb);
496 	cyber2000_attrw(0x14, 0x00, cfb);
497 
498 	/* PLL registers */
499 	spin_lock(&cfb->reg_b0_lock);
500 	cyber2000_grphw(EXT_DCLK_MULT, hw->clock_mult, cfb);
501 	cyber2000_grphw(EXT_DCLK_DIV, hw->clock_div, cfb);
502 	cyber2000_grphw(EXT_MCLK_MULT, cfb->mclk_mult, cfb);
503 	cyber2000_grphw(EXT_MCLK_DIV, cfb->mclk_div, cfb);
504 	cyber2000_grphw(0x90, 0x01, cfb);
505 	cyber2000_grphw(0xb9, 0x80, cfb);
506 	cyber2000_grphw(0xb9, 0x00, cfb);
507 	spin_unlock(&cfb->reg_b0_lock);
508 
509 	cfb->ramdac_ctrl = hw->ramdac;
510 	cyber2000fb_write_ramdac_ctrl(cfb);
511 
512 	cyber2000fb_writeb(0x20, 0x3c0, cfb);
513 	cyber2000fb_writeb(0xff, 0x3c6, cfb);
514 
515 	cyber2000_grphw(0x14, hw->fetch, cfb);
516 	cyber2000_grphw(0x15, ((hw->fetch >> 8) & 0x03) |
517 			      ((hw->pitch >> 4) & 0x30), cfb);
518 	cyber2000_grphw(EXT_SEQ_MISC, hw->extseqmisc, cfb);
519 
520 	/*
521 	 * Set up accelerator registers
522 	 */
523 	cyber2000fb_writew(hw->width, CO_REG_SRC_WIDTH, cfb);
524 	cyber2000fb_writew(hw->width, CO_REG_DEST_WIDTH, cfb);
525 	cyber2000fb_writeb(hw->co_pixfmt, CO_REG_PIXFMT, cfb);
526 }
527 
528 static inline int
cyber2000fb_update_start(struct cfb_info * cfb,struct fb_var_screeninfo * var)529 cyber2000fb_update_start(struct cfb_info *cfb, struct fb_var_screeninfo *var)
530 {
531 	u_int base = var->yoffset * var->xres_virtual + var->xoffset;
532 
533 	base *= var->bits_per_pixel;
534 
535 	/*
536 	 * Convert to bytes and shift two extra bits because DAC
537 	 * can only start on 4 byte aligned data.
538 	 */
539 	base >>= 5;
540 
541 	if (base >= 1 << 20)
542 		return -EINVAL;
543 
544 	cyber2000_grphw(0x10, base >> 16 | 0x10, cfb);
545 	cyber2000_crtcw(0x0c, base >> 8, cfb);
546 	cyber2000_crtcw(0x0d, base, cfb);
547 
548 	return 0;
549 }
550 
551 static int
cyber2000fb_decode_crtc(struct par_info * hw,struct cfb_info * cfb,struct fb_var_screeninfo * var)552 cyber2000fb_decode_crtc(struct par_info *hw, struct cfb_info *cfb,
553 			struct fb_var_screeninfo *var)
554 {
555 	u_int Htotal, Hblankend, Hsyncend;
556 	u_int Vtotal, Vdispend, Vblankstart, Vblankend, Vsyncstart, Vsyncend;
557 #define ENCODE_BIT(v, b1, m, b2) ((((v) >> (b1)) & (m)) << (b2))
558 
559 	hw->crtc[13] = hw->pitch;
560 	hw->crtc[17] = 0xe3;
561 	hw->crtc[14] = 0;
562 	hw->crtc[8]  = 0;
563 
564 	Htotal     = var->xres + var->right_margin +
565 		     var->hsync_len + var->left_margin;
566 
567 	if (Htotal > 2080)
568 		return -EINVAL;
569 
570 	hw->crtc[0] = (Htotal >> 3) - 5;
571 	hw->crtc[1] = (var->xres >> 3) - 1;
572 	hw->crtc[2] = var->xres >> 3;
573 	hw->crtc[4] = (var->xres + var->right_margin) >> 3;
574 
575 	Hblankend   = (Htotal - 4 * 8) >> 3;
576 
577 	hw->crtc[3] = ENCODE_BIT(Hblankend,  0, 0x1f,  0) |
578 		      ENCODE_BIT(1,          0, 0x01,  7);
579 
580 	Hsyncend    = (var->xres + var->right_margin + var->hsync_len) >> 3;
581 
582 	hw->crtc[5] = ENCODE_BIT(Hsyncend,   0, 0x1f,  0) |
583 		      ENCODE_BIT(Hblankend,  5, 0x01,  7);
584 
585 	Vdispend    = var->yres - 1;
586 	Vsyncstart  = var->yres + var->lower_margin;
587 	Vsyncend    = var->yres + var->lower_margin + var->vsync_len;
588 	Vtotal      = var->yres + var->lower_margin + var->vsync_len +
589 		      var->upper_margin - 2;
590 
591 	if (Vtotal > 2047)
592 		return -EINVAL;
593 
594 	Vblankstart = var->yres + 6;
595 	Vblankend   = Vtotal - 10;
596 
597 	hw->crtc[6]  = Vtotal;
598 	hw->crtc[7]  = ENCODE_BIT(Vtotal,     8, 0x01,  0) |
599 			ENCODE_BIT(Vdispend,   8, 0x01,  1) |
600 			ENCODE_BIT(Vsyncstart, 8, 0x01,  2) |
601 			ENCODE_BIT(Vblankstart, 8, 0x01,  3) |
602 			ENCODE_BIT(1,          0, 0x01,  4) |
603 			ENCODE_BIT(Vtotal,     9, 0x01,  5) |
604 			ENCODE_BIT(Vdispend,   9, 0x01,  6) |
605 			ENCODE_BIT(Vsyncstart, 9, 0x01,  7);
606 	hw->crtc[9]  = ENCODE_BIT(0,          0, 0x1f,  0) |
607 			ENCODE_BIT(Vblankstart, 9, 0x01,  5) |
608 			ENCODE_BIT(1,          0, 0x01,  6);
609 	hw->crtc[10] = Vsyncstart;
610 	hw->crtc[11] = ENCODE_BIT(Vsyncend,   0, 0x0f,  0) |
611 		       ENCODE_BIT(1,          0, 0x01,  7);
612 	hw->crtc[12] = Vdispend;
613 	hw->crtc[15] = Vblankstart;
614 	hw->crtc[16] = Vblankend;
615 	hw->crtc[18] = 0xff;
616 
617 	/*
618 	 * overflow - graphics reg 0x11
619 	 * 0=VTOTAL:10 1=VDEND:10 2=VRSTART:10 3=VBSTART:10
620 	 * 4=LINECOMP:10 5-IVIDEO 6=FIXCNT
621 	 */
622 	hw->crtc_ofl =
623 		ENCODE_BIT(Vtotal, 10, 0x01, 0) |
624 		ENCODE_BIT(Vdispend, 10, 0x01, 1) |
625 		ENCODE_BIT(Vsyncstart, 10, 0x01, 2) |
626 		ENCODE_BIT(Vblankstart, 10, 0x01, 3) |
627 		EXT_CRT_VRTOFL_LINECOMP10;
628 
629 	/* woody: set the interlaced bit... */
630 	/* FIXME: what about doublescan? */
631 	if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
632 		hw->crtc_ofl |= EXT_CRT_VRTOFL_INTERLACE;
633 
634 	return 0;
635 }
636 
637 /*
638  * The following was discovered by a good monitor, bit twiddling, theorising
639  * and but mostly luck.  Strangely, it looks like everyone elses' PLL!
640  *
641  * Clock registers:
642  *   fclock = fpll / div2
643  *   fpll   = fref * mult / div1
644  * where:
645  *   fref = 14.318MHz (69842ps)
646  *   mult = reg0xb0.7:0
647  *   div1 = (reg0xb1.5:0 + 1)
648  *   div2 =  2^(reg0xb1.7:6)
649  *   fpll should be between 115 and 260 MHz
650  *  (8696ps and 3846ps)
651  */
652 static int
cyber2000fb_decode_clock(struct par_info * hw,struct cfb_info * cfb,struct fb_var_screeninfo * var)653 cyber2000fb_decode_clock(struct par_info *hw, struct cfb_info *cfb,
654 			 struct fb_var_screeninfo *var)
655 {
656 	u_long pll_ps = var->pixclock;
657 	const u_long ref_ps = cfb->ref_ps;
658 	u_int div2, t_div1, best_div1, best_mult;
659 	int best_diff;
660 	int vco;
661 
662 	/*
663 	 * Step 1:
664 	 *   find div2 such that 115MHz < fpll < 260MHz
665 	 *   and 0 <= div2 < 4
666 	 */
667 	for (div2 = 0; div2 < 4; div2++) {
668 		u_long new_pll;
669 
670 		new_pll = pll_ps / cfb->divisors[div2];
671 		if (8696 > new_pll && new_pll > 3846) {
672 			pll_ps = new_pll;
673 			break;
674 		}
675 	}
676 
677 	if (div2 == 4)
678 		return -EINVAL;
679 
680 	/*
681 	 * Step 2:
682 	 *  Given pll_ps and ref_ps, find:
683 	 *    pll_ps * 0.995 < pll_ps_calc < pll_ps * 1.005
684 	 *  where { 1 < best_div1 < 32, 1 < best_mult < 256 }
685 	 *    pll_ps_calc = best_div1 / (ref_ps * best_mult)
686 	 */
687 	best_diff = 0x7fffffff;
688 	best_mult = 2;
689 	best_div1 = 32;
690 	for (t_div1 = 2; t_div1 < 32; t_div1 += 1) {
691 		u_int rr, t_mult, t_pll_ps;
692 		int diff;
693 
694 		/*
695 		 * Find the multiplier for this divisor
696 		 */
697 		rr = ref_ps * t_div1;
698 		t_mult = (rr + pll_ps / 2) / pll_ps;
699 
700 		/*
701 		 * Is the multiplier within the correct range?
702 		 */
703 		if (t_mult > 256 || t_mult < 2)
704 			continue;
705 
706 		/*
707 		 * Calculate the actual clock period from this multiplier
708 		 * and divisor, and estimate the error.
709 		 */
710 		t_pll_ps = (rr + t_mult / 2) / t_mult;
711 		diff = pll_ps - t_pll_ps;
712 		if (diff < 0)
713 			diff = -diff;
714 
715 		if (diff < best_diff) {
716 			best_diff = diff;
717 			best_mult = t_mult;
718 			best_div1 = t_div1;
719 		}
720 
721 		/*
722 		 * If we hit an exact value, there is no point in continuing.
723 		 */
724 		if (diff == 0)
725 			break;
726 	}
727 
728 	/*
729 	 * Step 3:
730 	 *  combine values
731 	 */
732 	hw->clock_mult = best_mult - 1;
733 	hw->clock_div  = div2 << 6 | (best_div1 - 1);
734 
735 	vco = ref_ps * best_div1 / best_mult;
736 	if ((ref_ps == 40690) && (vco < 5556))
737 		/* Set VFSEL when VCO > 180MHz (5.556 ps). */
738 		hw->clock_div |= EXT_DCLK_DIV_VFSEL;
739 
740 	return 0;
741 }
742 
743 /*
744  *    Set the User Defined Part of the Display
745  */
746 static int
cyber2000fb_check_var(struct fb_var_screeninfo * var,struct fb_info * info)747 cyber2000fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
748 {
749 	struct cfb_info *cfb = container_of(info, struct cfb_info, fb);
750 	struct par_info hw;
751 	unsigned int mem;
752 	int err;
753 
754 	var->transp.msb_right	= 0;
755 	var->red.msb_right	= 0;
756 	var->green.msb_right	= 0;
757 	var->blue.msb_right	= 0;
758 	var->transp.offset	= 0;
759 	var->transp.length	= 0;
760 
761 	switch (var->bits_per_pixel) {
762 	case 8:	/* PSEUDOCOLOUR, 256 */
763 		var->red.offset		= 0;
764 		var->red.length		= 8;
765 		var->green.offset	= 0;
766 		var->green.length	= 8;
767 		var->blue.offset	= 0;
768 		var->blue.length	= 8;
769 		break;
770 
771 	case 16:/* DIRECTCOLOUR, 64k or 32k */
772 		switch (var->green.length) {
773 		case 6: /* RGB565, 64k */
774 			var->red.offset		= 11;
775 			var->red.length		= 5;
776 			var->green.offset	= 5;
777 			var->green.length	= 6;
778 			var->blue.offset	= 0;
779 			var->blue.length	= 5;
780 			break;
781 
782 		default:
783 		case 5: /* RGB555, 32k */
784 			var->red.offset		= 10;
785 			var->red.length		= 5;
786 			var->green.offset	= 5;
787 			var->green.length	= 5;
788 			var->blue.offset	= 0;
789 			var->blue.length	= 5;
790 			break;
791 
792 		case 4: /* RGB444, 4k + transparency? */
793 			var->transp.offset	= 12;
794 			var->transp.length	= 4;
795 			var->red.offset		= 8;
796 			var->red.length		= 4;
797 			var->green.offset	= 4;
798 			var->green.length	= 4;
799 			var->blue.offset	= 0;
800 			var->blue.length	= 4;
801 			break;
802 		}
803 		break;
804 
805 	case 24:/* TRUECOLOUR, 16m */
806 		var->red.offset		= 16;
807 		var->red.length		= 8;
808 		var->green.offset	= 8;
809 		var->green.length	= 8;
810 		var->blue.offset	= 0;
811 		var->blue.length	= 8;
812 		break;
813 
814 	case 32:/* TRUECOLOUR, 16m */
815 		var->transp.offset	= 24;
816 		var->transp.length	= 8;
817 		var->red.offset		= 16;
818 		var->red.length		= 8;
819 		var->green.offset	= 8;
820 		var->green.length	= 8;
821 		var->blue.offset	= 0;
822 		var->blue.length	= 8;
823 		break;
824 
825 	default:
826 		return -EINVAL;
827 	}
828 
829 	mem = var->xres_virtual * var->yres_virtual * (var->bits_per_pixel / 8);
830 	if (mem > cfb->fb.fix.smem_len)
831 		var->yres_virtual = cfb->fb.fix.smem_len * 8 /
832 				    (var->bits_per_pixel * var->xres_virtual);
833 
834 	if (var->yres > var->yres_virtual)
835 		var->yres = var->yres_virtual;
836 	if (var->xres > var->xres_virtual)
837 		var->xres = var->xres_virtual;
838 
839 	err = cyber2000fb_decode_clock(&hw, cfb, var);
840 	if (err)
841 		return err;
842 
843 	err = cyber2000fb_decode_crtc(&hw, cfb, var);
844 	if (err)
845 		return err;
846 
847 	return 0;
848 }
849 
cyber2000fb_set_par(struct fb_info * info)850 static int cyber2000fb_set_par(struct fb_info *info)
851 {
852 	struct cfb_info *cfb = container_of(info, struct cfb_info, fb);
853 	struct fb_var_screeninfo *var = &cfb->fb.var;
854 	struct par_info hw;
855 	unsigned int mem;
856 
857 	hw.width = var->xres_virtual;
858 	hw.ramdac = RAMDAC_VREFEN | RAMDAC_DAC8BIT;
859 
860 	switch (var->bits_per_pixel) {
861 	case 8:
862 		hw.co_pixfmt		= CO_PIXFMT_8BPP;
863 		hw.pitch		= hw.width >> 3;
864 		hw.extseqmisc		= EXT_SEQ_MISC_8;
865 		break;
866 
867 	case 16:
868 		hw.co_pixfmt		= CO_PIXFMT_16BPP;
869 		hw.pitch		= hw.width >> 2;
870 
871 		switch (var->green.length) {
872 		case 6: /* RGB565, 64k */
873 			hw.extseqmisc	= EXT_SEQ_MISC_16_RGB565;
874 			break;
875 		case 5: /* RGB555, 32k */
876 			hw.extseqmisc	= EXT_SEQ_MISC_16_RGB555;
877 			break;
878 		case 4: /* RGB444, 4k + transparency? */
879 			hw.extseqmisc	= EXT_SEQ_MISC_16_RGB444;
880 			break;
881 		default:
882 			BUG();
883 		}
884 		break;
885 
886 	case 24:/* TRUECOLOUR, 16m */
887 		hw.co_pixfmt		= CO_PIXFMT_24BPP;
888 		hw.width		*= 3;
889 		hw.pitch		= hw.width >> 3;
890 		hw.ramdac		|= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
891 		hw.extseqmisc		= EXT_SEQ_MISC_24_RGB888;
892 		break;
893 
894 	case 32:/* TRUECOLOUR, 16m */
895 		hw.co_pixfmt		= CO_PIXFMT_32BPP;
896 		hw.pitch		= hw.width >> 1;
897 		hw.ramdac		|= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
898 		hw.extseqmisc		= EXT_SEQ_MISC_32;
899 		break;
900 
901 	default:
902 		BUG();
903 	}
904 
905 	/*
906 	 * Sigh, this is absolutely disgusting, but caused by
907 	 * the way the fbcon developers want to separate out
908 	 * the "checking" and the "setting" of the video mode.
909 	 *
910 	 * If the mode is not suitable for the hardware here,
911 	 * we can't prevent it being set by returning an error.
912 	 *
913 	 * In theory, since NetWinders contain just one VGA card,
914 	 * we should never end up hitting this problem.
915 	 */
916 	BUG_ON(cyber2000fb_decode_clock(&hw, cfb, var) != 0);
917 	BUG_ON(cyber2000fb_decode_crtc(&hw, cfb, var) != 0);
918 
919 	hw.width -= 1;
920 	hw.fetch = hw.pitch;
921 	if (!(cfb->mem_ctl2 & MEM_CTL2_64BIT))
922 		hw.fetch <<= 1;
923 	hw.fetch += 1;
924 
925 	cfb->fb.fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
926 
927 	/*
928 	 * Same here - if the size of the video mode exceeds the
929 	 * available RAM, we can't prevent this mode being set.
930 	 *
931 	 * In theory, since NetWinders contain just one VGA card,
932 	 * we should never end up hitting this problem.
933 	 */
934 	mem = cfb->fb.fix.line_length * var->yres_virtual;
935 	BUG_ON(mem > cfb->fb.fix.smem_len);
936 
937 	/*
938 	 * 8bpp displays are always pseudo colour.  16bpp and above
939 	 * are direct colour or true colour, depending on whether
940 	 * the RAMDAC palettes are bypassed.  (Direct colour has
941 	 * palettes, true colour does not.)
942 	 */
943 	if (var->bits_per_pixel == 8)
944 		cfb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
945 	else if (hw.ramdac & RAMDAC_BYPASS)
946 		cfb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
947 	else
948 		cfb->fb.fix.visual = FB_VISUAL_DIRECTCOLOR;
949 
950 	cyber2000fb_set_timing(cfb, &hw);
951 	cyber2000fb_update_start(cfb, var);
952 
953 	return 0;
954 }
955 
956 /*
957  *    Pan or Wrap the Display
958  */
959 static int
cyber2000fb_pan_display(struct fb_var_screeninfo * var,struct fb_info * info)960 cyber2000fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
961 {
962 	struct cfb_info *cfb = container_of(info, struct cfb_info, fb);
963 
964 	if (cyber2000fb_update_start(cfb, var))
965 		return -EINVAL;
966 
967 	cfb->fb.var.xoffset = var->xoffset;
968 	cfb->fb.var.yoffset = var->yoffset;
969 
970 	if (var->vmode & FB_VMODE_YWRAP) {
971 		cfb->fb.var.vmode |= FB_VMODE_YWRAP;
972 	} else {
973 		cfb->fb.var.vmode &= ~FB_VMODE_YWRAP;
974 	}
975 
976 	return 0;
977 }
978 
979 /*
980  *    (Un)Blank the display.
981  *
982  *  Blank the screen if blank_mode != 0, else unblank. If
983  *  blank == NULL then the caller blanks by setting the CLUT
984  *  (Color Look Up Table) to all black. Return 0 if blanking
985  *  succeeded, != 0 if un-/blanking failed due to e.g. a
986  *  video mode which doesn't support it. Implements VESA
987  *  suspend and powerdown modes on hardware that supports
988  *  disabling hsync/vsync:
989  *    blank_mode == 2: suspend vsync
990  *    blank_mode == 3: suspend hsync
991  *    blank_mode == 4: powerdown
992  *
993  *  wms...Enable VESA DMPS compatible powerdown mode
994  *  run "setterm -powersave powerdown" to take advantage
995  */
cyber2000fb_blank(int blank,struct fb_info * info)996 static int cyber2000fb_blank(int blank, struct fb_info *info)
997 {
998 	struct cfb_info *cfb = container_of(info, struct cfb_info, fb);
999 	unsigned int sync = 0;
1000 	int i;
1001 
1002 	switch (blank) {
1003 	case FB_BLANK_POWERDOWN:	/* powerdown - both sync lines down */
1004 		sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_0;
1005 		break;
1006 	case FB_BLANK_HSYNC_SUSPEND:	/* hsync off */
1007 		sync = EXT_SYNC_CTL_VS_NORMAL | EXT_SYNC_CTL_HS_0;
1008 		break;
1009 	case FB_BLANK_VSYNC_SUSPEND:	/* vsync off */
1010 		sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_NORMAL;
1011 		break;
1012 	case FB_BLANK_NORMAL:		/* soft blank */
1013 	default:			/* unblank */
1014 		break;
1015 	}
1016 
1017 	cyber2000_grphw(EXT_SYNC_CTL, sync, cfb);
1018 
1019 	if (blank <= 1) {
1020 		/* turn on ramdacs */
1021 		cfb->ramdac_powerdown &= ~(RAMDAC_DACPWRDN | RAMDAC_BYPASS |
1022 					   RAMDAC_RAMPWRDN);
1023 		cyber2000fb_write_ramdac_ctrl(cfb);
1024 	}
1025 
1026 	/*
1027 	 * Soft blank/unblank the display.
1028 	 */
1029 	if (blank) {	/* soft blank */
1030 		for (i = 0; i < NR_PALETTE; i++) {
1031 			cyber2000fb_writeb(i, 0x3c8, cfb);
1032 			cyber2000fb_writeb(0, 0x3c9, cfb);
1033 			cyber2000fb_writeb(0, 0x3c9, cfb);
1034 			cyber2000fb_writeb(0, 0x3c9, cfb);
1035 		}
1036 	} else {	/* unblank */
1037 		for (i = 0; i < NR_PALETTE; i++) {
1038 			cyber2000fb_writeb(i, 0x3c8, cfb);
1039 			cyber2000fb_writeb(cfb->palette[i].red, 0x3c9, cfb);
1040 			cyber2000fb_writeb(cfb->palette[i].green, 0x3c9, cfb);
1041 			cyber2000fb_writeb(cfb->palette[i].blue, 0x3c9, cfb);
1042 		}
1043 	}
1044 
1045 	if (blank >= 2) {
1046 		/* turn off ramdacs */
1047 		cfb->ramdac_powerdown |= RAMDAC_DACPWRDN | RAMDAC_BYPASS |
1048 					 RAMDAC_RAMPWRDN;
1049 		cyber2000fb_write_ramdac_ctrl(cfb);
1050 	}
1051 
1052 	return 0;
1053 }
1054 
1055 static const struct fb_ops cyber2000fb_ops = {
1056 	.owner		= THIS_MODULE,
1057 	__FB_DEFAULT_IOMEM_OPS_RDWR,
1058 	.fb_check_var	= cyber2000fb_check_var,
1059 	.fb_set_par	= cyber2000fb_set_par,
1060 	.fb_setcolreg	= cyber2000fb_setcolreg,
1061 	.fb_blank	= cyber2000fb_blank,
1062 	.fb_pan_display	= cyber2000fb_pan_display,
1063 	.fb_fillrect	= cyber2000fb_fillrect,
1064 	.fb_copyarea	= cyber2000fb_copyarea,
1065 	.fb_imageblit	= cfb_imageblit,
1066 	.fb_sync	= cyber2000fb_sync,
1067 	__FB_DEFAULT_IOMEM_OPS_MMAP,
1068 };
1069 
1070 /*
1071  * This is the only "static" reference to the internal data structures
1072  * of this driver.  It is here solely at the moment to support the other
1073  * CyberPro modules external to this driver.
1074  */
1075 static struct cfb_info *int_cfb_info;
1076 
1077 /*
1078  * Enable access to the extended registers
1079  */
cyber2000fb_enable_extregs(struct cfb_info * cfb)1080 void cyber2000fb_enable_extregs(struct cfb_info *cfb)
1081 {
1082 	cfb->func_use_count += 1;
1083 
1084 	if (cfb->func_use_count == 1) {
1085 		int old;
1086 
1087 		old = cyber2000_grphr(EXT_FUNC_CTL, cfb);
1088 		old |= EXT_FUNC_CTL_EXTREGENBL;
1089 		cyber2000_grphw(EXT_FUNC_CTL, old, cfb);
1090 	}
1091 }
1092 EXPORT_SYMBOL(cyber2000fb_enable_extregs);
1093 
1094 /*
1095  * Disable access to the extended registers
1096  */
cyber2000fb_disable_extregs(struct cfb_info * cfb)1097 void cyber2000fb_disable_extregs(struct cfb_info *cfb)
1098 {
1099 	if (cfb->func_use_count == 1) {
1100 		int old;
1101 
1102 		old = cyber2000_grphr(EXT_FUNC_CTL, cfb);
1103 		old &= ~EXT_FUNC_CTL_EXTREGENBL;
1104 		cyber2000_grphw(EXT_FUNC_CTL, old, cfb);
1105 	}
1106 
1107 	if (cfb->func_use_count == 0)
1108 		printk(KERN_ERR "disable_extregs: count = 0\n");
1109 	else
1110 		cfb->func_use_count -= 1;
1111 }
1112 EXPORT_SYMBOL(cyber2000fb_disable_extregs);
1113 
1114 /*
1115  * Attach a capture/tv driver to the core CyberX0X0 driver.
1116  */
cyber2000fb_attach(struct cyberpro_info * info,int idx)1117 int cyber2000fb_attach(struct cyberpro_info *info, int idx)
1118 {
1119 	if (int_cfb_info != NULL) {
1120 		info->dev	      = int_cfb_info->fb.device;
1121 #ifdef CONFIG_FB_CYBER2000_I2C
1122 		info->i2c	      = &int_cfb_info->i2c_adapter;
1123 #else
1124 		info->i2c	      = NULL;
1125 #endif
1126 		info->regs	      = int_cfb_info->regs;
1127 		info->irq             = int_cfb_info->irq;
1128 		info->fb	      = int_cfb_info->fb.screen_base;
1129 		info->fb_size	      = int_cfb_info->fb.fix.smem_len;
1130 		info->info	      = int_cfb_info;
1131 
1132 		strscpy(info->dev_name, int_cfb_info->fb.fix.id,
1133 			sizeof(info->dev_name));
1134 	}
1135 
1136 	return int_cfb_info != NULL;
1137 }
1138 EXPORT_SYMBOL(cyber2000fb_attach);
1139 
1140 /*
1141  * Detach a capture/tv driver from the core CyberX0X0 driver.
1142  */
cyber2000fb_detach(int idx)1143 void cyber2000fb_detach(int idx)
1144 {
1145 }
1146 EXPORT_SYMBOL(cyber2000fb_detach);
1147 
1148 #ifdef CONFIG_FB_CYBER2000_DDC
1149 
1150 #define DDC_REG		0xb0
1151 #define DDC_SCL_OUT	(1 << 0)
1152 #define DDC_SDA_OUT	(1 << 4)
1153 #define DDC_SCL_IN	(1 << 2)
1154 #define DDC_SDA_IN	(1 << 6)
1155 
cyber2000fb_enable_ddc(struct cfb_info * cfb)1156 static void cyber2000fb_enable_ddc(struct cfb_info *cfb)
1157 	__acquires(&cfb->reg_b0_lock)
1158 {
1159 	spin_lock(&cfb->reg_b0_lock);
1160 	cyber2000fb_writew(0x1bf, 0x3ce, cfb);
1161 }
1162 
cyber2000fb_disable_ddc(struct cfb_info * cfb)1163 static void cyber2000fb_disable_ddc(struct cfb_info *cfb)
1164 	__releases(&cfb->reg_b0_lock)
1165 {
1166 	cyber2000fb_writew(0x0bf, 0x3ce, cfb);
1167 	spin_unlock(&cfb->reg_b0_lock);
1168 }
1169 
1170 
cyber2000fb_ddc_setscl(void * data,int val)1171 static void cyber2000fb_ddc_setscl(void *data, int val)
1172 {
1173 	struct cfb_info *cfb = data;
1174 	unsigned char reg;
1175 
1176 	cyber2000fb_enable_ddc(cfb);
1177 	reg = cyber2000_grphr(DDC_REG, cfb);
1178 	if (!val)	/* bit is inverted */
1179 		reg |= DDC_SCL_OUT;
1180 	else
1181 		reg &= ~DDC_SCL_OUT;
1182 	cyber2000_grphw(DDC_REG, reg, cfb);
1183 	cyber2000fb_disable_ddc(cfb);
1184 }
1185 
cyber2000fb_ddc_setsda(void * data,int val)1186 static void cyber2000fb_ddc_setsda(void *data, int val)
1187 {
1188 	struct cfb_info *cfb = data;
1189 	unsigned char reg;
1190 
1191 	cyber2000fb_enable_ddc(cfb);
1192 	reg = cyber2000_grphr(DDC_REG, cfb);
1193 	if (!val)	/* bit is inverted */
1194 		reg |= DDC_SDA_OUT;
1195 	else
1196 		reg &= ~DDC_SDA_OUT;
1197 	cyber2000_grphw(DDC_REG, reg, cfb);
1198 	cyber2000fb_disable_ddc(cfb);
1199 }
1200 
cyber2000fb_ddc_getscl(void * data)1201 static int cyber2000fb_ddc_getscl(void *data)
1202 {
1203 	struct cfb_info *cfb = data;
1204 	int retval;
1205 
1206 	cyber2000fb_enable_ddc(cfb);
1207 	retval = !!(cyber2000_grphr(DDC_REG, cfb) & DDC_SCL_IN);
1208 	cyber2000fb_disable_ddc(cfb);
1209 
1210 	return retval;
1211 }
1212 
cyber2000fb_ddc_getsda(void * data)1213 static int cyber2000fb_ddc_getsda(void *data)
1214 {
1215 	struct cfb_info *cfb = data;
1216 	int retval;
1217 
1218 	cyber2000fb_enable_ddc(cfb);
1219 	retval = !!(cyber2000_grphr(DDC_REG, cfb) & DDC_SDA_IN);
1220 	cyber2000fb_disable_ddc(cfb);
1221 
1222 	return retval;
1223 }
1224 
cyber2000fb_setup_ddc_bus(struct cfb_info * cfb)1225 static int cyber2000fb_setup_ddc_bus(struct cfb_info *cfb)
1226 {
1227 	strscpy(cfb->ddc_adapter.name, cfb->fb.fix.id,
1228 		sizeof(cfb->ddc_adapter.name));
1229 	cfb->ddc_adapter.owner		= THIS_MODULE;
1230 	cfb->ddc_adapter.algo_data	= &cfb->ddc_algo;
1231 	cfb->ddc_adapter.dev.parent	= cfb->fb.device;
1232 	cfb->ddc_algo.setsda		= cyber2000fb_ddc_setsda;
1233 	cfb->ddc_algo.setscl		= cyber2000fb_ddc_setscl;
1234 	cfb->ddc_algo.getsda		= cyber2000fb_ddc_getsda;
1235 	cfb->ddc_algo.getscl		= cyber2000fb_ddc_getscl;
1236 	cfb->ddc_algo.udelay		= 10;
1237 	cfb->ddc_algo.timeout		= 20;
1238 	cfb->ddc_algo.data		= cfb;
1239 
1240 	i2c_set_adapdata(&cfb->ddc_adapter, cfb);
1241 
1242 	return i2c_bit_add_bus(&cfb->ddc_adapter);
1243 }
1244 #endif /* CONFIG_FB_CYBER2000_DDC */
1245 
1246 #ifdef CONFIG_FB_CYBER2000_I2C
cyber2000fb_i2c_setsda(void * data,int state)1247 static void cyber2000fb_i2c_setsda(void *data, int state)
1248 {
1249 	struct cfb_info *cfb = data;
1250 	unsigned int latch2;
1251 
1252 	spin_lock(&cfb->reg_b0_lock);
1253 	latch2 = cyber2000_grphr(EXT_LATCH2, cfb);
1254 	latch2 &= EXT_LATCH2_I2C_CLKEN;
1255 	if (state)
1256 		latch2 |= EXT_LATCH2_I2C_DATEN;
1257 	cyber2000_grphw(EXT_LATCH2, latch2, cfb);
1258 	spin_unlock(&cfb->reg_b0_lock);
1259 }
1260 
cyber2000fb_i2c_setscl(void * data,int state)1261 static void cyber2000fb_i2c_setscl(void *data, int state)
1262 {
1263 	struct cfb_info *cfb = data;
1264 	unsigned int latch2;
1265 
1266 	spin_lock(&cfb->reg_b0_lock);
1267 	latch2 = cyber2000_grphr(EXT_LATCH2, cfb);
1268 	latch2 &= EXT_LATCH2_I2C_DATEN;
1269 	if (state)
1270 		latch2 |= EXT_LATCH2_I2C_CLKEN;
1271 	cyber2000_grphw(EXT_LATCH2, latch2, cfb);
1272 	spin_unlock(&cfb->reg_b0_lock);
1273 }
1274 
cyber2000fb_i2c_getsda(void * data)1275 static int cyber2000fb_i2c_getsda(void *data)
1276 {
1277 	struct cfb_info *cfb = data;
1278 	int ret;
1279 
1280 	spin_lock(&cfb->reg_b0_lock);
1281 	ret = !!(cyber2000_grphr(EXT_LATCH2, cfb) & EXT_LATCH2_I2C_DAT);
1282 	spin_unlock(&cfb->reg_b0_lock);
1283 
1284 	return ret;
1285 }
1286 
cyber2000fb_i2c_getscl(void * data)1287 static int cyber2000fb_i2c_getscl(void *data)
1288 {
1289 	struct cfb_info *cfb = data;
1290 	int ret;
1291 
1292 	spin_lock(&cfb->reg_b0_lock);
1293 	ret = !!(cyber2000_grphr(EXT_LATCH2, cfb) & EXT_LATCH2_I2C_CLK);
1294 	spin_unlock(&cfb->reg_b0_lock);
1295 
1296 	return ret;
1297 }
1298 
cyber2000fb_i2c_register(struct cfb_info * cfb)1299 static int cyber2000fb_i2c_register(struct cfb_info *cfb)
1300 {
1301 	strscpy(cfb->i2c_adapter.name, cfb->fb.fix.id,
1302 		sizeof(cfb->i2c_adapter.name));
1303 	cfb->i2c_adapter.owner = THIS_MODULE;
1304 	cfb->i2c_adapter.algo_data = &cfb->i2c_algo;
1305 	cfb->i2c_adapter.dev.parent = cfb->fb.device;
1306 	cfb->i2c_algo.setsda = cyber2000fb_i2c_setsda;
1307 	cfb->i2c_algo.setscl = cyber2000fb_i2c_setscl;
1308 	cfb->i2c_algo.getsda = cyber2000fb_i2c_getsda;
1309 	cfb->i2c_algo.getscl = cyber2000fb_i2c_getscl;
1310 	cfb->i2c_algo.udelay = 5;
1311 	cfb->i2c_algo.timeout = msecs_to_jiffies(100);
1312 	cfb->i2c_algo.data = cfb;
1313 
1314 	return i2c_bit_add_bus(&cfb->i2c_adapter);
1315 }
1316 
cyber2000fb_i2c_unregister(struct cfb_info * cfb)1317 static void cyber2000fb_i2c_unregister(struct cfb_info *cfb)
1318 {
1319 	i2c_del_adapter(&cfb->i2c_adapter);
1320 }
1321 #else
1322 #define cyber2000fb_i2c_register(cfb)	(0)
1323 #define cyber2000fb_i2c_unregister(cfb)	do { } while (0)
1324 #endif
1325 
1326 /*
1327  * These parameters give
1328  * 640x480, hsync 31.5kHz, vsync 60Hz
1329  */
1330 static const struct fb_videomode cyber2000fb_default_mode = {
1331 	.refresh	= 60,
1332 	.xres		= 640,
1333 	.yres		= 480,
1334 	.pixclock	= 39722,
1335 	.left_margin	= 56,
1336 	.right_margin	= 16,
1337 	.upper_margin	= 34,
1338 	.lower_margin	= 9,
1339 	.hsync_len	= 88,
1340 	.vsync_len	= 2,
1341 	.sync		= FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1342 	.vmode		= FB_VMODE_NONINTERLACED
1343 };
1344 
1345 static char igs_regs[] = {
1346 	EXT_CRT_IRQ,		0,
1347 	EXT_CRT_TEST,		0,
1348 	EXT_SYNC_CTL,		0,
1349 	EXT_SEG_WRITE_PTR,	0,
1350 	EXT_SEG_READ_PTR,	0,
1351 	EXT_BIU_MISC,		EXT_BIU_MISC_LIN_ENABLE |
1352 				EXT_BIU_MISC_COP_ENABLE |
1353 				EXT_BIU_MISC_COP_BFC,
1354 	EXT_FUNC_CTL,		0,
1355 	CURS_H_START,		0,
1356 	CURS_H_START + 1,	0,
1357 	CURS_H_PRESET,		0,
1358 	CURS_V_START,		0,
1359 	CURS_V_START + 1,	0,
1360 	CURS_V_PRESET,		0,
1361 	CURS_CTL,		0,
1362 	EXT_ATTRIB_CTL,		EXT_ATTRIB_CTL_EXT,
1363 	EXT_OVERSCAN_RED,	0,
1364 	EXT_OVERSCAN_GREEN,	0,
1365 	EXT_OVERSCAN_BLUE,	0,
1366 
1367 	/* some of these are questionable when we have a BIOS */
1368 	EXT_MEM_CTL0,		EXT_MEM_CTL0_7CLK |
1369 				EXT_MEM_CTL0_RAS_1 |
1370 				EXT_MEM_CTL0_MULTCAS,
1371 	EXT_HIDDEN_CTL1,	0x30,
1372 	EXT_FIFO_CTL,		0x0b,
1373 	EXT_FIFO_CTL + 1,	0x17,
1374 	0x76,			0x00,
1375 	EXT_HIDDEN_CTL4,	0xc8
1376 };
1377 
1378 /*
1379  * Initialise the CyberPro hardware.  On the CyberPro5XXXX,
1380  * ensure that we're using the correct PLL (5XXX's may be
1381  * programmed to use an additional set of PLLs.)
1382  */
cyberpro_init_hw(struct cfb_info * cfb)1383 static void cyberpro_init_hw(struct cfb_info *cfb)
1384 {
1385 	int i;
1386 
1387 	for (i = 0; i < sizeof(igs_regs); i += 2)
1388 		cyber2000_grphw(igs_regs[i], igs_regs[i + 1], cfb);
1389 
1390 	if (cfb->id == ID_CYBERPRO_5000) {
1391 		unsigned char val;
1392 		cyber2000fb_writeb(0xba, 0x3ce, cfb);
1393 		val = cyber2000fb_readb(0x3cf, cfb) & 0x80;
1394 		cyber2000fb_writeb(val, 0x3cf, cfb);
1395 	}
1396 }
1397 
cyberpro_alloc_fb_info(unsigned int id,char * name)1398 static struct cfb_info *cyberpro_alloc_fb_info(unsigned int id, char *name)
1399 {
1400 	struct cfb_info *cfb;
1401 
1402 	cfb = kzalloc(sizeof(struct cfb_info), GFP_KERNEL);
1403 	if (!cfb)
1404 		return NULL;
1405 
1406 
1407 	cfb->id			= id;
1408 
1409 	if (id == ID_CYBERPRO_5000)
1410 		cfb->ref_ps	= 40690; /* 24.576 MHz */
1411 	else
1412 		cfb->ref_ps	= 69842; /* 14.31818 MHz (69841?) */
1413 
1414 	cfb->divisors[0]	= 1;
1415 	cfb->divisors[1]	= 2;
1416 	cfb->divisors[2]	= 4;
1417 
1418 	if (id == ID_CYBERPRO_2000)
1419 		cfb->divisors[3] = 8;
1420 	else
1421 		cfb->divisors[3] = 6;
1422 
1423 	strcpy(cfb->fb.fix.id, name);
1424 
1425 	cfb->fb.fix.type	= FB_TYPE_PACKED_PIXELS;
1426 	cfb->fb.fix.type_aux	= 0;
1427 	cfb->fb.fix.xpanstep	= 0;
1428 	cfb->fb.fix.ypanstep	= 1;
1429 	cfb->fb.fix.ywrapstep	= 0;
1430 
1431 	switch (id) {
1432 	case ID_IGA_1682:
1433 		cfb->fb.fix.accel = 0;
1434 		break;
1435 
1436 	case ID_CYBERPRO_2000:
1437 		cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2000;
1438 		break;
1439 
1440 	case ID_CYBERPRO_2010:
1441 		cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2010;
1442 		break;
1443 
1444 	case ID_CYBERPRO_5000:
1445 		cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER5000;
1446 		break;
1447 	}
1448 
1449 	cfb->fb.var.nonstd	= 0;
1450 	cfb->fb.var.activate	= FB_ACTIVATE_NOW;
1451 	cfb->fb.var.height	= -1;
1452 	cfb->fb.var.width	= -1;
1453 	cfb->fb.var.accel_flags	= FB_ACCELF_TEXT;
1454 
1455 	cfb->fb.fbops		= &cyber2000fb_ops;
1456 	cfb->fb.flags		= FBINFO_HWACCEL_YPAN;
1457 	cfb->fb.pseudo_palette	= cfb->pseudo_palette;
1458 
1459 	spin_lock_init(&cfb->reg_b0_lock);
1460 
1461 	fb_alloc_cmap(&cfb->fb.cmap, NR_PALETTE, 0);
1462 
1463 	return cfb;
1464 }
1465 
cyberpro_free_fb_info(struct cfb_info * cfb)1466 static void cyberpro_free_fb_info(struct cfb_info *cfb)
1467 {
1468 	if (cfb) {
1469 		/*
1470 		 * Free the colourmap
1471 		 */
1472 		fb_alloc_cmap(&cfb->fb.cmap, 0, 0);
1473 
1474 		kfree(cfb);
1475 	}
1476 }
1477 
1478 /*
1479  * Parse Cyber2000fb options.  Usage:
1480  *  video=cyber2000:font:fontname
1481  */
1482 #ifndef MODULE
cyber2000fb_setup(char * options)1483 static int cyber2000fb_setup(char *options)
1484 {
1485 	char *opt;
1486 
1487 	if (!options || !*options)
1488 		return 0;
1489 
1490 	while ((opt = strsep(&options, ",")) != NULL) {
1491 		if (!*opt)
1492 			continue;
1493 
1494 		if (strncmp(opt, "font:", 5) == 0) {
1495 			static char default_font_storage[40];
1496 
1497 			strscpy(default_font_storage, opt + 5,
1498 				sizeof(default_font_storage));
1499 			default_font = default_font_storage;
1500 			continue;
1501 		}
1502 
1503 		printk(KERN_ERR "CyberPro20x0: unknown parameter: %s\n", opt);
1504 	}
1505 	return 0;
1506 }
1507 #endif  /*  MODULE  */
1508 
1509 /*
1510  * The CyberPro chips can be placed on many different bus types.
1511  * This probe function is common to all bus types.  The bus-specific
1512  * probe function is expected to have:
1513  *  - enabled access to the linear memory region
1514  *  - memory mapped access to the registers
1515  *  - initialised mem_ctl1 and mem_ctl2 appropriately.
1516  */
cyberpro_common_probe(struct cfb_info * cfb)1517 static int cyberpro_common_probe(struct cfb_info *cfb)
1518 {
1519 	u_long smem_size;
1520 	u_int h_sync, v_sync;
1521 	int err;
1522 
1523 	cyberpro_init_hw(cfb);
1524 
1525 	/*
1526 	 * Get the video RAM size and width from the VGA register.
1527 	 * This should have been already initialised by the BIOS,
1528 	 * but if it's garbage, claim default 1MB VRAM (woody)
1529 	 */
1530 	cfb->mem_ctl1 = cyber2000_grphr(EXT_MEM_CTL1, cfb);
1531 	cfb->mem_ctl2 = cyber2000_grphr(EXT_MEM_CTL2, cfb);
1532 
1533 	/*
1534 	 * Determine the size of the memory.
1535 	 */
1536 	switch (cfb->mem_ctl2 & MEM_CTL2_SIZE_MASK) {
1537 	case MEM_CTL2_SIZE_4MB:
1538 		smem_size = 0x00400000;
1539 		break;
1540 	case MEM_CTL2_SIZE_2MB:
1541 		smem_size = 0x00200000;
1542 		break;
1543 	case MEM_CTL2_SIZE_1MB:
1544 		smem_size = 0x00100000;
1545 		break;
1546 	default:
1547 		smem_size = 0x00100000;
1548 		break;
1549 	}
1550 
1551 	cfb->fb.fix.smem_len   = smem_size;
1552 	cfb->fb.fix.mmio_len   = MMIO_SIZE;
1553 	cfb->fb.screen_base    = cfb->region;
1554 
1555 #ifdef CONFIG_FB_CYBER2000_DDC
1556 	if (cyber2000fb_setup_ddc_bus(cfb) == 0)
1557 		cfb->ddc_registered = true;
1558 #endif
1559 
1560 	err = -EINVAL;
1561 	if (!fb_find_mode(&cfb->fb.var, &cfb->fb, NULL, NULL, 0,
1562 			  &cyber2000fb_default_mode, 8)) {
1563 		printk(KERN_ERR "%s: no valid mode found\n", cfb->fb.fix.id);
1564 		goto failed;
1565 	}
1566 
1567 	cfb->fb.var.yres_virtual = cfb->fb.fix.smem_len * 8 /
1568 			(cfb->fb.var.bits_per_pixel * cfb->fb.var.xres_virtual);
1569 
1570 	if (cfb->fb.var.yres_virtual < cfb->fb.var.yres)
1571 		cfb->fb.var.yres_virtual = cfb->fb.var.yres;
1572 
1573 /*	fb_set_var(&cfb->fb.var, -1, &cfb->fb); */
1574 
1575 	/*
1576 	 * Calculate the hsync and vsync frequencies.  Note that
1577 	 * we split the 1e12 constant up so that we can preserve
1578 	 * the precision and fit the results into 32-bit registers.
1579 	 *  (1953125000 * 512 = 1e12)
1580 	 */
1581 	h_sync = 1953125000 / cfb->fb.var.pixclock;
1582 	h_sync = h_sync * 512 / (cfb->fb.var.xres + cfb->fb.var.left_margin +
1583 		 cfb->fb.var.right_margin + cfb->fb.var.hsync_len);
1584 	v_sync = h_sync / (cfb->fb.var.yres + cfb->fb.var.upper_margin +
1585 		 cfb->fb.var.lower_margin + cfb->fb.var.vsync_len);
1586 
1587 	printk(KERN_INFO "%s: %dKiB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
1588 		cfb->fb.fix.id, cfb->fb.fix.smem_len >> 10,
1589 		cfb->fb.var.xres, cfb->fb.var.yres,
1590 		h_sync / 1000, h_sync % 1000, v_sync);
1591 
1592 	err = cyber2000fb_i2c_register(cfb);
1593 	if (err)
1594 		goto failed;
1595 
1596 	err = register_framebuffer(&cfb->fb);
1597 	if (err)
1598 		cyber2000fb_i2c_unregister(cfb);
1599 
1600 failed:
1601 #ifdef CONFIG_FB_CYBER2000_DDC
1602 	if (err && cfb->ddc_registered)
1603 		i2c_del_adapter(&cfb->ddc_adapter);
1604 #endif
1605 	return err;
1606 }
1607 
cyberpro_common_remove(struct cfb_info * cfb)1608 static void cyberpro_common_remove(struct cfb_info *cfb)
1609 {
1610 	unregister_framebuffer(&cfb->fb);
1611 #ifdef CONFIG_FB_CYBER2000_DDC
1612 	if (cfb->ddc_registered)
1613 		i2c_del_adapter(&cfb->ddc_adapter);
1614 #endif
1615 	cyber2000fb_i2c_unregister(cfb);
1616 }
1617 
cyberpro_common_resume(struct cfb_info * cfb)1618 static void cyberpro_common_resume(struct cfb_info *cfb)
1619 {
1620 	cyberpro_init_hw(cfb);
1621 
1622 	/*
1623 	 * Reprogram the MEM_CTL1 and MEM_CTL2 registers
1624 	 */
1625 	cyber2000_grphw(EXT_MEM_CTL1, cfb->mem_ctl1, cfb);
1626 	cyber2000_grphw(EXT_MEM_CTL2, cfb->mem_ctl2, cfb);
1627 
1628 	/*
1629 	 * Restore the old video mode and the palette.
1630 	 * We also need to tell fbcon to redraw the console.
1631 	 */
1632 	cyber2000fb_set_par(&cfb->fb);
1633 }
1634 
1635 /*
1636  * We need to wake up the CyberPro, and make sure its in linear memory
1637  * mode.  Unfortunately, this is specific to the platform and card that
1638  * we are running on.
1639  *
1640  * On x86 and ARM, should we be initialising the CyberPro first via the
1641  * IO registers, and then the MMIO registers to catch all cases?  Can we
1642  * end up in the situation where the chip is in MMIO mode, but not awake
1643  * on an x86 system?
1644  */
cyberpro_pci_enable_mmio(struct cfb_info * cfb)1645 static int cyberpro_pci_enable_mmio(struct cfb_info *cfb)
1646 {
1647 	unsigned char val;
1648 
1649 #if defined(__sparc_v9__)
1650 #error "You lose, consult DaveM."
1651 #elif defined(__sparc__)
1652 	/*
1653 	 * SPARC does not have an "outb" instruction, so we generate
1654 	 * I/O cycles storing into a reserved memory space at
1655 	 * physical address 0x3000000
1656 	 */
1657 	unsigned char __iomem *iop;
1658 
1659 	iop = ioremap(0x3000000, 0x5000);
1660 	if (iop == NULL) {
1661 		printk(KERN_ERR "iga5000: cannot map I/O\n");
1662 		return -ENOMEM;
1663 	}
1664 
1665 	writeb(0x18, iop + 0x46e8);
1666 	writeb(0x01, iop + 0x102);
1667 	writeb(0x08, iop + 0x46e8);
1668 	writeb(EXT_BIU_MISC, iop + 0x3ce);
1669 	writeb(EXT_BIU_MISC_LIN_ENABLE, iop + 0x3cf);
1670 
1671 	iounmap(iop);
1672 #else
1673 	/*
1674 	 * Most other machine types are "normal", so
1675 	 * we use the standard IO-based wakeup.
1676 	 */
1677 	outb(0x18, 0x46e8);
1678 	outb(0x01, 0x102);
1679 	outb(0x08, 0x46e8);
1680 	outb(EXT_BIU_MISC, 0x3ce);
1681 	outb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf);
1682 #endif
1683 
1684 	/*
1685 	 * Allow the CyberPro to accept PCI burst accesses
1686 	 */
1687 	if (cfb->id == ID_CYBERPRO_2010) {
1688 		printk(KERN_INFO "%s: NOT enabling PCI bursts\n",
1689 		       cfb->fb.fix.id);
1690 	} else {
1691 		val = cyber2000_grphr(EXT_BUS_CTL, cfb);
1692 		if (!(val & EXT_BUS_CTL_PCIBURST_WRITE)) {
1693 			printk(KERN_INFO "%s: enabling PCI bursts\n",
1694 				cfb->fb.fix.id);
1695 
1696 			val |= EXT_BUS_CTL_PCIBURST_WRITE;
1697 
1698 			if (cfb->id == ID_CYBERPRO_5000)
1699 				val |= EXT_BUS_CTL_PCIBURST_READ;
1700 
1701 			cyber2000_grphw(EXT_BUS_CTL, val, cfb);
1702 		}
1703 	}
1704 
1705 	return 0;
1706 }
1707 
cyberpro_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)1708 static int cyberpro_pci_probe(struct pci_dev *dev,
1709 			      const struct pci_device_id *id)
1710 {
1711 	struct cfb_info *cfb;
1712 	char name[16];
1713 	int err;
1714 
1715 	sprintf(name, "CyberPro%4X", id->device);
1716 
1717 	err = aperture_remove_conflicting_pci_devices(dev, name);
1718 	if (err)
1719 		return err;
1720 
1721 	err = pci_enable_device(dev);
1722 	if (err)
1723 		return err;
1724 
1725 	err = -ENOMEM;
1726 	cfb = cyberpro_alloc_fb_info(id->driver_data, name);
1727 	if (!cfb)
1728 		goto failed_release;
1729 
1730 	err = pci_request_regions(dev, cfb->fb.fix.id);
1731 	if (err)
1732 		goto failed_regions;
1733 
1734 	cfb->irq = dev->irq;
1735 	cfb->region = pci_ioremap_bar(dev, 0);
1736 	if (!cfb->region) {
1737 		err = -ENOMEM;
1738 		goto failed_ioremap;
1739 	}
1740 
1741 	cfb->regs = cfb->region + MMIO_OFFSET;
1742 	cfb->fb.device = &dev->dev;
1743 	cfb->fb.fix.mmio_start = pci_resource_start(dev, 0) + MMIO_OFFSET;
1744 	cfb->fb.fix.smem_start = pci_resource_start(dev, 0);
1745 
1746 	/*
1747 	 * Bring up the hardware.  This is expected to enable access
1748 	 * to the linear memory region, and allow access to the memory
1749 	 * mapped registers.  Also, mem_ctl1 and mem_ctl2 must be
1750 	 * initialised.
1751 	 */
1752 	err = cyberpro_pci_enable_mmio(cfb);
1753 	if (err)
1754 		goto failed;
1755 
1756 	/*
1757 	 * Use MCLK from BIOS. FIXME: what about hotplug?
1758 	 */
1759 	cfb->mclk_mult = cyber2000_grphr(EXT_MCLK_MULT, cfb);
1760 	cfb->mclk_div  = cyber2000_grphr(EXT_MCLK_DIV, cfb);
1761 
1762 #ifdef __arm__
1763 	/*
1764 	 * MCLK on the NetWinder and the Shark is fixed at 75MHz
1765 	 */
1766 	if (machine_is_netwinder()) {
1767 		cfb->mclk_mult = 0xdb;
1768 		cfb->mclk_div  = 0x54;
1769 	}
1770 #endif
1771 
1772 	err = cyberpro_common_probe(cfb);
1773 	if (err)
1774 		goto failed;
1775 
1776 	/*
1777 	 * Our driver data
1778 	 */
1779 	pci_set_drvdata(dev, cfb);
1780 	if (int_cfb_info == NULL)
1781 		int_cfb_info = cfb;
1782 
1783 	return 0;
1784 
1785 failed:
1786 	iounmap(cfb->region);
1787 failed_ioremap:
1788 	pci_release_regions(dev);
1789 failed_regions:
1790 	cyberpro_free_fb_info(cfb);
1791 failed_release:
1792 	pci_disable_device(dev);
1793 	return err;
1794 }
1795 
cyberpro_pci_remove(struct pci_dev * dev)1796 static void cyberpro_pci_remove(struct pci_dev *dev)
1797 {
1798 	struct cfb_info *cfb = pci_get_drvdata(dev);
1799 
1800 	if (cfb) {
1801 		cyberpro_common_remove(cfb);
1802 		iounmap(cfb->region);
1803 		cyberpro_free_fb_info(cfb);
1804 
1805 		if (cfb == int_cfb_info)
1806 			int_cfb_info = NULL;
1807 
1808 		pci_release_regions(dev);
1809 		pci_disable_device(dev);
1810 	}
1811 }
1812 
cyberpro_pci_suspend(struct device * dev)1813 static int __maybe_unused cyberpro_pci_suspend(struct device *dev)
1814 {
1815 	return 0;
1816 }
1817 
1818 /*
1819  * Re-initialise the CyberPro hardware
1820  */
cyberpro_pci_resume(struct device * dev)1821 static int __maybe_unused cyberpro_pci_resume(struct device *dev)
1822 {
1823 	struct cfb_info *cfb = dev_get_drvdata(dev);
1824 
1825 	if (cfb) {
1826 		cyberpro_pci_enable_mmio(cfb);
1827 		cyberpro_common_resume(cfb);
1828 	}
1829 
1830 	return 0;
1831 }
1832 
1833 static struct pci_device_id cyberpro_pci_table[] = {
1834 /*	Not yet
1835  *	{ PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_1682,
1836  *		PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_IGA_1682 },
1837  */
1838 	{ PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2000,
1839 		PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2000 },
1840 	{ PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2010,
1841 		PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2010 },
1842 	{ PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_5000,
1843 		PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_5000 },
1844 	{ 0, }
1845 };
1846 
1847 MODULE_DEVICE_TABLE(pci, cyberpro_pci_table);
1848 
1849 static SIMPLE_DEV_PM_OPS(cyberpro_pci_pm_ops,
1850 			 cyberpro_pci_suspend,
1851 			 cyberpro_pci_resume);
1852 
1853 static struct pci_driver cyberpro_driver = {
1854 	.name		= "CyberPro",
1855 	.probe		= cyberpro_pci_probe,
1856 	.remove		= cyberpro_pci_remove,
1857 	.driver.pm	= &cyberpro_pci_pm_ops,
1858 	.id_table	= cyberpro_pci_table
1859 };
1860 
1861 /*
1862  * I don't think we can use the "module_init" stuff here because
1863  * the fbcon stuff may not be initialised yet.  Hence the #ifdef
1864  * around module_init.
1865  *
1866  * Tony: "module_init" is now required
1867  */
cyber2000fb_init(void)1868 static int __init cyber2000fb_init(void)
1869 {
1870 	int ret = -1, err;
1871 
1872 #ifndef MODULE
1873 	char *option = NULL;
1874 #endif
1875 
1876 	if (fb_modesetting_disabled("CyberPro"))
1877 		return -ENODEV;
1878 
1879 #ifndef MODULE
1880 	if (fb_get_options("cyber2000fb", &option))
1881 		return -ENODEV;
1882 	cyber2000fb_setup(option);
1883 #endif
1884 
1885 	err = pci_register_driver(&cyberpro_driver);
1886 	if (!err)
1887 		ret = 0;
1888 
1889 	return ret ? err : 0;
1890 }
1891 module_init(cyber2000fb_init);
1892 
cyberpro_exit(void)1893 static void __exit cyberpro_exit(void)
1894 {
1895 	pci_unregister_driver(&cyberpro_driver);
1896 }
1897 module_exit(cyberpro_exit);
1898 
1899 MODULE_AUTHOR("Russell King");
1900 MODULE_DESCRIPTION("CyberPro 2000, 2010 and 5000 framebuffer driver");
1901 MODULE_LICENSE("GPL");
1902