xref: /illumos-gate/usr/src/uts/common/io/chxge/com/mv88e1xxx.h (revision 2d6eb4a5e0a47d30189497241345dc5466bb68ab)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (C) 2003-2005 Chelsio Communications.  All rights reserved.
24  */
25 
26 #ifndef CHELSIO_MV8E1XXX_H
27 #define CHELSIO_MV8E1XXX_H
28 
29 #ifndef BMCR_SPEED1000
30 # define BMCR_SPEED1000 0x40
31 #endif
32 
33 #ifndef ADVERTISE_PAUSE
34 # define ADVERTISE_PAUSE 0x400
35 #endif
36 #ifndef ADVERTISE_PAUSE_ASYM
37 # define ADVERTISE_PAUSE_ASYM 0x800
38 #endif
39 
40 /* Gigabit MII registers */
41 #define MII_GBCR 9       /* 1000Base-T control register */
42 #define MII_GBSR 10      /* 1000Base-T status register */
43 
44 /* 1000Base-T control register fields */
45 #define GBCR_ADV_1000HALF         0x100
46 #define GBCR_ADV_1000FULL         0x200
47 #define GBCR_PREFER_MASTER        0x400
48 #define GBCR_MANUAL_AS_MASTER     0x800
49 #define GBCR_MANUAL_CONFIG_ENABLE 0x1000
50 
51 /* 1000Base-T status register fields */
52 #define GBSR_LP_1000HALF  0x400
53 #define GBSR_LP_1000FULL  0x800
54 #define GBSR_REMOTE_OK    0x1000
55 #define GBSR_LOCAL_OK     0x2000
56 #define GBSR_LOCAL_MASTER 0x4000
57 #define GBSR_MASTER_FAULT 0x8000
58 
59 /* Marvell PHY interrupt status bits. */
60 #define MV88E1XXX_INTR_JABBER          0x0001
61 #define MV88E1XXX_INTR_POLARITY_CHNG   0x0002
62 #define MV88E1XXX_INTR_ENG_DETECT_CHNG 0x0010
63 #define MV88E1XXX_INTR_DOWNSHIFT       0x0020
64 #define MV88E1XXX_INTR_MDI_XOVER_CHNG  0x0040
65 #define MV88E1XXX_INTR_FIFO_OVER_UNDER 0x0080
66 #define MV88E1XXX_INTR_FALSE_CARRIER   0x0100
67 #define MV88E1XXX_INTR_SYMBOL_ERROR    0x0200
68 #define MV88E1XXX_INTR_LINK_CHNG       0x0400
69 #define MV88E1XXX_INTR_AUTONEG_DONE    0x0800
70 #define MV88E1XXX_INTR_PAGE_RECV       0x1000
71 #define MV88E1XXX_INTR_DUPLEX_CHNG     0x2000
72 #define MV88E1XXX_INTR_SPEED_CHNG      0x4000
73 #define MV88E1XXX_INTR_AUTONEG_ERR     0x8000
74 
75 /* Marvell PHY specific registers. */
76 #define MV88E1XXX_SPECIFIC_CNTRL_REGISTER               16
77 #define MV88E1XXX_SPECIFIC_STATUS_REGISTER              17
78 #define MV88E1XXX_INTERRUPT_ENABLE_REGISTER             18
79 #define MV88E1XXX_INTERRUPT_STATUS_REGISTER             19
80 #define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER       20
81 #define MV88E1XXX_RECV_ERR_CNTR_REGISTER                21
82 #define MV88E1XXX_RES_REGISTER                          22
83 #define MV88E1XXX_GLOBAL_STATUS_REGISTER                23
84 #define MV88E1XXX_LED_CONTROL_REGISTER                  24
85 #define MV88E1XXX_MANUAL_LED_OVERRIDE_REGISTER          25
86 #define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_2_REGISTER     26
87 #define MV88E1XXX_EXT_PHY_SPECIFIC_STATUS_REGISTER      27
88 #define MV88E1XXX_VIRTUAL_CABLE_TESTER_REGISTER         28
89 #define MV88E1XXX_EXTENDED_ADDR_REGISTER                29
90 #define MV88E1XXX_EXTENDED_REGISTER                     30
91 
92 /* PHY specific control register fields */
93 #define S_PSCR_MDI_XOVER_MODE    5
94 #define M_PSCR_MDI_XOVER_MODE    0x3
95 #define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE)
96 #define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE)
97 
98 /* Extended PHY specific control register fields */
99 #define S_DOWNSHIFT_ENABLE 8
100 #define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE)
101 
102 #define S_DOWNSHIFT_CNT    9
103 #define M_DOWNSHIFT_CNT    0x7
104 #define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT)
105 #define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT)
106 
107 /* PHY specific status register fields */
108 #define S_PSSR_JABBER 0
109 #define V_PSSR_JABBER (1 << S_PSSR_JABBER)
110 
111 #define S_PSSR_POLARITY 1
112 #define V_PSSR_POLARITY (1 << S_PSSR_POLARITY)
113 
114 #define S_PSSR_RX_PAUSE 2
115 #define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE)
116 
117 #define S_PSSR_TX_PAUSE 3
118 #define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE)
119 
120 #define S_PSSR_ENERGY_DETECT 4
121 #define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT)
122 
123 #define S_PSSR_DOWNSHIFT_STATUS 5
124 #define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS)
125 
126 #define S_PSSR_MDI 6
127 #define V_PSSR_MDI (1 << S_PSSR_MDI)
128 
129 #define S_PSSR_CABLE_LEN    7
130 #define M_PSSR_CABLE_LEN    0x7
131 #define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN)
132 #define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN)
133 
134 #define S_PSSR_LINK 10
135 #define V_PSSR_LINK (1 << S_PSSR_LINK)
136 
137 #define S_PSSR_STATUS_RESOLVED 11
138 #define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED)
139 
140 #define S_PSSR_PAGE_RECEIVED 12
141 #define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED)
142 
143 #define S_PSSR_DUPLEX 13
144 #define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX)
145 
146 #define S_PSSR_SPEED    14
147 #define M_PSSR_SPEED    0x3
148 #define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED)
149 #define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED)
150 
151 #endif
152