1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011, 2016, 2025 Chelsio Communications. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef T4_MSG_H 30 #define T4_MSG_H 31 32 enum cpl_opcodes { 33 CPL_PASS_OPEN_REQ = 0x1, 34 CPL_PASS_ACCEPT_RPL = 0x2, 35 CPL_ACT_OPEN_REQ = 0x3, 36 CPL_SET_TCB = 0x4, 37 CPL_SET_TCB_FIELD = 0x5, 38 CPL_GET_TCB = 0x6, 39 CPL_CLOSE_CON_REQ = 0x8, 40 CPL_CLOSE_LISTSRV_REQ = 0x9, 41 CPL_ABORT_REQ = 0xA, 42 CPL_ABORT_RPL = 0xB, 43 CPL_TX_DATA = 0xC, 44 CPL_RX_DATA_ACK = 0xD, 45 CPL_TX_PKT = 0xE, 46 CPL_RTE_DELETE_REQ = 0xF, 47 CPL_RTE_WRITE_REQ = 0x10, 48 CPL_RTE_READ_REQ = 0x11, 49 CPL_L2T_WRITE_REQ = 0x12, 50 CPL_L2T_READ_REQ = 0x13, 51 CPL_SMT_WRITE_REQ = 0x14, 52 CPL_SMT_READ_REQ = 0x15, 53 CPL_TAG_WRITE_REQ = 0x16, 54 CPL_BARRIER = 0x18, 55 CPL_TID_RELEASE = 0x1A, 56 CPL_TAG_READ_REQ = 0x1B, 57 CPL_SRQ_TABLE_REQ = 0x1C, 58 CPL_TX_PKT_FSO = 0x1E, 59 CPL_TX_DATA_ISO = 0x1F, 60 61 CPL_CLOSE_LISTSRV_RPL = 0x20, 62 CPL_ERROR = 0x21, 63 CPL_GET_TCB_RPL = 0x22, 64 CPL_L2T_WRITE_RPL = 0x23, 65 CPL_PASS_OPEN_RPL = 0x24, 66 CPL_ACT_OPEN_RPL = 0x25, 67 CPL_PEER_CLOSE = 0x26, 68 CPL_RTE_DELETE_RPL = 0x27, 69 CPL_RTE_WRITE_RPL = 0x28, 70 CPL_ROCE_FW_NOTIFY = 0x28, 71 CPL_RX_URG_PKT = 0x29, 72 CPL_TAG_WRITE_RPL = 0x2A, 73 CPL_RDMA_ASYNC_EVENT = 0x2A, 74 CPL_ABORT_REQ_RSS = 0x2B, 75 CPL_RX_URG_NOTIFY = 0x2C, 76 CPL_ABORT_RPL_RSS = 0x2D, 77 CPL_SMT_WRITE_RPL = 0x2E, 78 CPL_TX_DATA_ACK = 0x2F, 79 CPL_RDMA_INV_REQ = 0x2F, 80 81 CPL_RX_PHYS_ADDR = 0x30, 82 CPL_PCMD_READ_RPL = 0x31, 83 CPL_CLOSE_CON_RPL = 0x32, 84 CPL_ISCSI_HDR = 0x33, 85 CPL_L2T_READ_RPL = 0x34, 86 CPL_RDMA_CQE = 0x35, 87 CPL_RDMA_CQE_READ_RSP = 0x36, 88 CPL_RDMA_CQE_ERR = 0x37, 89 CPL_RTE_READ_RPL = 0x38, 90 CPL_RX_DATA = 0x39, 91 CPL_SET_TCB_RPL = 0x3A, 92 CPL_RX_PKT = 0x3B, 93 CPL_TAG_READ_RPL = 0x3C, 94 CPL_HIT_NOTIFY = 0x3D, 95 CPL_PKT_NOTIFY = 0x3E, 96 CPL_RX_DDP_COMPLETE = 0x3F, 97 98 CPL_ACT_ESTABLISH = 0x40, 99 CPL_PASS_ESTABLISH = 0x41, 100 CPL_RX_DATA_DDP = 0x42, 101 CPL_SMT_READ_RPL = 0x43, 102 CPL_PASS_ACCEPT_REQ = 0x44, 103 CPL_RX_ISCSI_CMP = 0x45, 104 CPL_RX_FCOE_DDP = 0x46, 105 CPL_FCOE_HDR = 0x47, 106 CPL_T5_TRACE_PKT = 0x48, 107 CPL_RX_ISCSI_DDP = 0x49, 108 CPL_RX_FCOE_DIF = 0x4A, 109 CPL_RX_DATA_DIF = 0x4B, 110 CPL_ERR_NOTIFY = 0x4D, 111 CPL_RX_TLS_CMP = 0x4E, 112 CPL_T6_TX_DATA_ACK = 0x4F, 113 114 CPL_RDMA_READ_REQ = 0x60, 115 CPL_RX_ISCSI_DIF = 0x60, 116 CPL_RDMA_CQE_EXT = 0x61, 117 CPL_RDMA_CQE_FW_EXT = 0x62, 118 CPL_RDMA_CQE_ERR_EXT = 0x63, 119 CPL_TX_DATA_ACK_XT = 0x64, 120 CPL_ROCE_CQE = 0x68, 121 CPL_ROCE_CQE_FW = 0x69, 122 CPL_ROCE_CQE_ERR = 0x6A, 123 124 CPL_SACK_REQ = 0x70, 125 126 CPL_SET_LE_REQ = 0x80, 127 CPL_PASS_OPEN_REQ6 = 0x81, 128 CPL_ACT_OPEN_REQ6 = 0x83, 129 CPL_TX_TLS_PDU = 0x88, 130 CPL_TX_TLS_SFO = 0x89, 131 CPL_TX_SEC_PDU = 0x8A, 132 CPL_TX_TLS_ACK = 0x8B, 133 CPL_RCB_UPD = 0x8C, 134 135 CPL_SGE_FLR_FLUSH = 0xA0, 136 CPL_RDMA_TERMINATE = 0xA2, 137 CPL_RDMA_WRITE = 0xA4, 138 CPL_SGE_EGR_UPDATE = 0xA5, 139 CPL_SET_LE_RPL = 0xA6, 140 CPL_FW2_MSG = 0xA7, 141 CPL_FW2_PLD = 0xA8, 142 CPL_T5_RDMA_READ_REQ = 0xA9, 143 CPL_RDMA_ATOMIC_REQ = 0xAA, 144 CPL_RDMA_ATOMIC_RPL = 0xAB, 145 CPL_RDMA_IMM_DATA = 0xAC, 146 CPL_RDMA_IMM_DATA_SE = 0xAD, 147 CPL_RX_MPS_PKT = 0xAF, 148 149 CPL_TRACE_PKT = 0xB0, 150 CPL_RX2TX_DATA = 0xB1, 151 CPL_TLS_DATA = 0xB1, 152 CPL_ISCSI_DATA = 0xB2, 153 CPL_FCOE_DATA = 0xB3, 154 CPL_NVMT_DATA = 0xB4, 155 CPL_NVMT_CMP = 0xB5, 156 CPL_NVMT_CMP_IMM = 0xB6, 157 CPL_NVMT_CMP_SRQ = 0xB7, 158 CPL_ROCE_ACK_NAK_REQ = 0xBC, 159 CPL_ROCE_ACK_NAK = 0xBD, 160 161 CPL_FW4_MSG = 0xC0, 162 CPL_FW4_PLD = 0xC1, 163 CPL_RDMA_CQE_SRQ = 0xC2, 164 CPL_ACCELERATOR_ACK = 0xC4, 165 CPL_FW4_ACK = 0xC3, 166 CPL_RX_PKT_IPSEC = 0xC6, 167 CPL_SRQ_TABLE_RPL = 0xCC, 168 CPL_TX_DATA_REQ = 0xCF, 169 170 CPL_RX_PHYS_DSGL = 0xD0, 171 172 CPL_FW6_MSG = 0xE0, 173 CPL_FW6_PLD = 0xE1, 174 CPL_ACCELERATOR_HDR = 0xE8, 175 CPL_TX_TNL_LSO = 0xEC, 176 CPL_TX_PKT_LSO = 0xED, 177 CPL_TX_PKT_XT = 0xEE, 178 179 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 180 }; 181 182 enum CPL_error { 183 CPL_ERR_NONE = 0, 184 CPL_ERR_TCAM_PARITY = 1, 185 CPL_ERR_TCAM_MISS = 2, 186 CPL_ERR_TCAM_FULL = 3, 187 CPL_ERR_BAD_LENGTH = 15, 188 CPL_ERR_BAD_ROUTE = 18, 189 CPL_ERR_CONN_RESET = 20, 190 CPL_ERR_CONN_EXIST_SYNRECV = 21, 191 CPL_ERR_CONN_EXIST = 22, 192 CPL_ERR_ARP_MISS = 23, 193 CPL_ERR_BAD_SYN = 24, 194 CPL_ERR_CONN_TIMEDOUT = 30, 195 CPL_ERR_XMIT_TIMEDOUT = 31, 196 CPL_ERR_PERSIST_TIMEDOUT = 32, 197 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 198 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 199 CPL_ERR_RTX_NEG_ADVICE = 35, 200 CPL_ERR_PERSIST_NEG_ADVICE = 36, 201 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 202 CPL_ERR_WAIT_ARP_RPL = 41, 203 CPL_ERR_ABORT_FAILED = 42, 204 CPL_ERR_IWARP_FLM = 50, 205 CPL_CONTAINS_READ_RPL = 60, 206 CPL_CONTAINS_WRITE_RPL = 61, 207 }; 208 209 /* 210 * Some of the error codes above implicitly indicate that there is no TID 211 * allocated with the result of an ACT_OPEN. We use this predicate to make 212 * that explicit. 213 */ 214 static inline int act_open_has_tid(int status) 215 { 216 return (status != CPL_ERR_TCAM_PARITY && 217 status != CPL_ERR_TCAM_MISS && 218 status != CPL_ERR_TCAM_FULL && 219 status != CPL_ERR_CONN_EXIST_SYNRECV && 220 status != CPL_ERR_CONN_EXIST); 221 } 222 223 /* 224 * Convert an ACT_OPEN_RPL status to an errno. 225 */ 226 static inline int 227 act_open_rpl_status_to_errno(int status) 228 { 229 230 switch (status) { 231 case CPL_ERR_CONN_RESET: 232 return (ECONNREFUSED); 233 case CPL_ERR_ARP_MISS: 234 return (EHOSTUNREACH); 235 case CPL_ERR_CONN_TIMEDOUT: 236 return (ETIMEDOUT); 237 case CPL_ERR_TCAM_FULL: 238 return (EAGAIN); 239 case CPL_ERR_CONN_EXIST: 240 return (EAGAIN); 241 default: 242 return (EIO); 243 } 244 } 245 246 247 enum { 248 CPL_CONN_POLICY_AUTO = 0, 249 CPL_CONN_POLICY_ASK = 1, 250 CPL_CONN_POLICY_FILTER = 2, 251 CPL_CONN_POLICY_DENY = 3 252 }; 253 254 enum { 255 ULP_MODE_NONE = 0, 256 ULP_MODE_ISCSI = 2, 257 ULP_MODE_RDMA = 4, 258 ULP_MODE_TCPDDP = 5, 259 ULP_MODE_FCOE = 6, 260 ULP_MODE_TLS = 8, 261 ULP_MODE_RDMA_V2 = 10, 262 ULP_MODE_NVMET = 11, 263 }; 264 265 enum { 266 ULP_CRC_HEADER = 1 << 0, 267 ULP_CRC_DATA = 1 << 1 268 }; 269 270 enum { 271 CPL_PASS_OPEN_ACCEPT, 272 CPL_PASS_OPEN_REJECT, 273 CPL_PASS_OPEN_ACCEPT_TNL 274 }; 275 276 enum { 277 CPL_ABORT_SEND_RST = 0, 278 CPL_ABORT_NO_RST, 279 }; 280 281 enum { /* TX_PKT_XT checksum types */ 282 TX_CSUM_TCP = 0, 283 TX_CSUM_UDP = 1, 284 TX_CSUM_CRC16 = 4, 285 TX_CSUM_CRC32 = 5, 286 TX_CSUM_CRC32C = 6, 287 TX_CSUM_FCOE = 7, 288 TX_CSUM_TCPIP = 8, 289 TX_CSUM_UDPIP = 9, 290 TX_CSUM_TCPIP6 = 10, 291 TX_CSUM_UDPIP6 = 11, 292 TX_CSUM_IP = 12, 293 }; 294 295 enum { /* packet type in CPL_RX_PKT */ 296 PKTYPE_XACT_UCAST = 0, 297 PKTYPE_HASH_UCAST = 1, 298 PKTYPE_XACT_MCAST = 2, 299 PKTYPE_HASH_MCAST = 3, 300 PKTYPE_PROMISC = 4, 301 PKTYPE_HPROMISC = 5, 302 PKTYPE_BCAST = 6 303 }; 304 305 enum { /* DMAC type in CPL_RX_PKT */ 306 DATYPE_UCAST, 307 DATYPE_MCAST, 308 DATYPE_BCAST 309 }; 310 311 enum { /* TCP congestion control algorithms */ 312 CONG_ALG_RENO, 313 CONG_ALG_TAHOE, 314 CONG_ALG_NEWRENO, 315 CONG_ALG_HIGHSPEED 316 }; 317 318 enum { /* RSS hash type */ 319 RSS_HASH_NONE = 0, /* no hash computed */ 320 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 321 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 322 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 323 }; 324 325 enum { /* LE commands */ 326 LE_CMD_READ = 0x4, 327 LE_CMD_WRITE = 0xb 328 }; 329 330 enum { /* LE request size */ 331 LE_SZ_NONE = 0, 332 LE_SZ_33 = 1, 333 LE_SZ_66 = 2, 334 LE_SZ_132 = 3, 335 LE_SZ_264 = 4, 336 LE_SZ_528 = 5 337 }; 338 339 union opcode_tid { 340 __be32 opcode_tid; 341 __u8 opcode; 342 }; 343 344 #define S_CPL_OPCODE 24 345 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 346 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 347 #define G_TID(x) ((x) & 0xFFFFFF) 348 349 /* tid is assumed to be 24-bits */ 350 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 351 352 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 353 354 /* extract the TID from a CPL command */ 355 #define GET_TID(cmd) (G_TID(be32toh(OPCODE_TID(cmd)))) 356 #define GET_OPCODE(cmd) ((cmd)->ot.opcode) 357 358 359 /* 360 * Note that this driver splits the 14b opaque atid into an 11b atid and a 3b 361 * cookie that is used to demux replies for shared CPLs. 362 */ 363 /* partitioning of TID fields that also carry a queue id */ 364 #define S_TID_TID 0 365 #define M_TID_TID 0x7ff 366 #define V_TID_TID(x) ((x) << S_TID_TID) 367 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 368 369 #define S_TID_COOKIE 11 370 #define M_TID_COOKIE 0x7 371 #define V_TID_COOKIE(x) ((x) << S_TID_COOKIE) 372 #define G_TID_COOKIE(x) (((x) >> S_TID_COOKIE) & M_TID_COOKIE) 373 374 #define S_TID_QID 14 375 #define M_TID_QID 0x3ff 376 #define V_TID_QID(x) ((x) << S_TID_QID) 377 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 378 379 union opcode_info { 380 __be64 opcode_info; 381 __u8 opcode; 382 }; 383 384 struct tcp_options { 385 __be16 mss; 386 __u8 wsf; 387 #if defined(__LITTLE_ENDIAN_BITFIELD) 388 __u8 :4; 389 __u8 unknown:1; 390 __u8 ecn:1; 391 __u8 sack:1; 392 __u8 tstamp:1; 393 #else 394 __u8 tstamp:1; 395 __u8 sack:1; 396 __u8 ecn:1; 397 __u8 unknown:1; 398 __u8 :4; 399 #endif 400 }; 401 402 struct rss_header { 403 __u8 opcode; 404 #if defined(__LITTLE_ENDIAN_BITFIELD) 405 __u8 channel:2; 406 __u8 filter_hit:1; 407 __u8 filter_tid:1; 408 __u8 hash_type:2; 409 __u8 ipv6:1; 410 __u8 send2fw:1; 411 #else 412 __u8 send2fw:1; 413 __u8 ipv6:1; 414 __u8 hash_type:2; 415 __u8 filter_tid:1; 416 __u8 filter_hit:1; 417 __u8 channel:2; 418 #endif 419 __be16 qid; 420 __be32 hash_val; 421 }; 422 423 #define S_HASHTYPE 20 424 #define M_HASHTYPE 0x3 425 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 426 427 #define S_QNUM 0 428 #define M_QNUM 0xFFFF 429 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 430 431 #if defined(RSS_HDR_VLD) || defined(CHELSIO_FW) 432 # define RSS_HDR struct rss_header rss_hdr; 433 #else 434 # define RSS_HDR 435 #endif 436 437 #ifndef CHELSIO_FW 438 struct work_request_hdr { 439 __be32 wr_hi; 440 __be32 wr_mid; 441 __be64 wr_lo; 442 }; 443 444 /* wr_mid fields */ 445 #define S_WR_LEN16 0 446 #define M_WR_LEN16 0xFF 447 #define V_WR_LEN16(x) ((x) << S_WR_LEN16) 448 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 449 450 /* wr_hi fields */ 451 #define S_WR_OP 24 452 #define M_WR_OP 0xFF 453 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 454 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 455 456 # define WR_HDR struct work_request_hdr wr 457 # define WR_HDR_SIZE sizeof(struct work_request_hdr) 458 #else 459 # define WR_HDR 460 # define WR_HDR_SIZE 0 461 #endif 462 463 /* option 0 fields */ 464 #define S_ACCEPT_MODE 0 465 #define M_ACCEPT_MODE 0x3 466 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 467 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 468 469 #define S_TX_CHAN 2 470 #define M_TX_CHAN 0x3 471 #define V_TX_CHAN(x) ((x) << S_TX_CHAN) 472 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 473 474 #define S_NO_CONG 4 475 #define V_NO_CONG(x) ((x) << S_NO_CONG) 476 #define F_NO_CONG V_NO_CONG(1U) 477 478 #define S_DELACK 5 479 #define V_DELACK(x) ((x) << S_DELACK) 480 #define F_DELACK V_DELACK(1U) 481 482 #define S_INJECT_TIMER 6 483 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 484 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 485 486 #define S_NON_OFFLOAD 7 487 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 488 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 489 490 #define S_ULP_MODE 8 491 #define M_ULP_MODE 0xF 492 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 493 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 494 495 #define S_RCV_BUFSIZ 12 496 #define M_RCV_BUFSIZ 0x3FFU 497 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 498 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 499 500 #define S_DSCP 22 501 #define M_DSCP 0x3F 502 #define V_DSCP(x) ((x) << S_DSCP) 503 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 504 505 #define S_SMAC_SEL 28 506 #define M_SMAC_SEL 0xFF 507 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 508 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 509 510 #define S_L2T_IDX 36 511 #define M_L2T_IDX 0xFFF 512 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 513 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 514 515 #define S_TCAM_BYPASS 48 516 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 517 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 518 519 #define S_NAGLE 49 520 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 521 #define F_NAGLE V_NAGLE(1ULL) 522 523 #define S_WND_SCALE 50 524 #define M_WND_SCALE 0xF 525 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 526 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 527 528 #define S_KEEP_ALIVE 54 529 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 530 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 531 532 #define S_MAX_RT 55 533 #define M_MAX_RT 0xF 534 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 535 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 536 537 #define S_MAX_RT_OVERRIDE 59 538 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 539 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 540 541 #define S_MSS_IDX 60 542 #define M_MSS_IDX 0xF 543 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 544 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 545 546 /* option 1 fields */ 547 #define S_SYN_RSS_ENABLE 0 548 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 549 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 550 551 #define S_SYN_RSS_USE_HASH 1 552 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 553 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 554 555 #define S_SYN_RSS_QUEUE 2 556 #define M_SYN_RSS_QUEUE 0x3FF 557 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 558 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 559 560 #define S_LISTEN_INTF 12 561 #define M_LISTEN_INTF 0xFF 562 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 563 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 564 565 #define S_LISTEN_FILTER 20 566 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 567 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 568 569 #define S_SYN_DEFENSE 21 570 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 571 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 572 573 #define S_CONN_POLICY 22 574 #define M_CONN_POLICY 0x3 575 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 576 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 577 578 #define S_T5_FILT_INFO 24 579 #define M_T5_FILT_INFO 0xffffffffffULL 580 #define V_T5_FILT_INFO(x) ((x) << S_T5_FILT_INFO) 581 #define G_T5_FILT_INFO(x) (((x) >> S_T5_FILT_INFO) & M_T5_FILT_INFO) 582 583 #define S_FILT_INFO 28 584 #define M_FILT_INFO 0xfffffffffULL 585 #define V_FILT_INFO(x) ((x) << S_FILT_INFO) 586 #define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO) 587 588 /* option 2 fields */ 589 #define S_RSS_QUEUE 0 590 #define M_RSS_QUEUE 0x3FF 591 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 592 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 593 594 #define S_RSS_QUEUE_VALID 10 595 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 596 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 597 598 #define S_RX_COALESCE_VALID 11 599 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 600 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 601 602 #define S_RX_COALESCE 12 603 #define M_RX_COALESCE 0x3 604 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 605 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 606 607 #define S_CONG_CNTRL 14 608 #define M_CONG_CNTRL 0x3 609 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 610 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 611 612 #define S_PACE 16 613 #define M_PACE 0x3 614 #define V_PACE(x) ((x) << S_PACE) 615 #define G_PACE(x) (((x) >> S_PACE) & M_PACE) 616 617 #define S_CONG_CNTRL_VALID 18 618 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 619 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 620 621 #define S_T5_ISS 18 622 #define V_T5_ISS(x) ((x) << S_T5_ISS) 623 #define F_T5_ISS V_T5_ISS(1U) 624 625 #define S_PACE_VALID 19 626 #define V_PACE_VALID(x) ((x) << S_PACE_VALID) 627 #define F_PACE_VALID V_PACE_VALID(1U) 628 629 #define S_RX_FC_DISABLE 20 630 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 631 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 632 633 #define S_RX_FC_DDP 21 634 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 635 #define F_RX_FC_DDP V_RX_FC_DDP(1U) 636 637 #define S_RX_FC_VALID 22 638 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 639 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 640 641 #define S_TX_QUEUE 23 642 #define M_TX_QUEUE 0x7 643 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 644 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 645 646 #define S_RX_CHANNEL 26 647 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 648 #define F_RX_CHANNEL V_RX_CHANNEL(1U) 649 650 #define S_CCTRL_ECN 27 651 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 652 #define F_CCTRL_ECN V_CCTRL_ECN(1U) 653 654 #define S_WND_SCALE_EN 28 655 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 656 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 657 658 #define S_TSTAMPS_EN 29 659 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 660 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 661 662 #define S_SACK_EN 30 663 #define V_SACK_EN(x) ((x) << S_SACK_EN) 664 #define F_SACK_EN V_SACK_EN(1U) 665 666 #define S_T5_OPT_2_VALID 31 667 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID) 668 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U) 669 670 struct cpl_pass_open_req { 671 WR_HDR; 672 union opcode_tid ot; 673 __be16 local_port; 674 __be16 peer_port; 675 __be32 local_ip; 676 __be32 peer_ip; 677 __be64 opt0; 678 __be64 opt1; 679 }; 680 681 struct cpl_pass_open_req6 { 682 WR_HDR; 683 union opcode_tid ot; 684 __be16 local_port; 685 __be16 peer_port; 686 __be64 local_ip_hi; 687 __be64 local_ip_lo; 688 __be64 peer_ip_hi; 689 __be64 peer_ip_lo; 690 __be64 opt0; 691 __be64 opt1; 692 }; 693 694 struct cpl_pass_open_rpl { 695 RSS_HDR 696 union opcode_tid ot; 697 __u8 rsvd[3]; 698 __u8 status; 699 }; 700 701 struct cpl_pass_establish { 702 RSS_HDR 703 union opcode_tid ot; 704 __be32 rsvd; 705 __be32 tos_stid; 706 __be16 mac_idx; 707 __be16 tcp_opt; 708 __be32 snd_isn; 709 __be32 rcv_isn; 710 }; 711 712 /* cpl_pass_establish.tos_stid fields */ 713 #define S_PASS_OPEN_TID 0 714 #define M_PASS_OPEN_TID 0xFFFFFF 715 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 716 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 717 718 #define S_PASS_OPEN_TOS 24 719 #define M_PASS_OPEN_TOS 0xFF 720 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 721 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 722 723 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 724 #define S_TCPOPT_WSCALE_OK 5 725 #define M_TCPOPT_WSCALE_OK 0x1 726 #define V_TCPOPT_WSCALE_OK(x) ((x) << S_TCPOPT_WSCALE_OK) 727 #define G_TCPOPT_WSCALE_OK(x) (((x) >> S_TCPOPT_WSCALE_OK) & M_TCPOPT_WSCALE_OK) 728 729 #define S_TCPOPT_SACK 6 730 #define M_TCPOPT_SACK 0x1 731 #define V_TCPOPT_SACK(x) ((x) << S_TCPOPT_SACK) 732 #define G_TCPOPT_SACK(x) (((x) >> S_TCPOPT_SACK) & M_TCPOPT_SACK) 733 734 #define S_TCPOPT_TSTAMP 7 735 #define M_TCPOPT_TSTAMP 0x1 736 #define V_TCPOPT_TSTAMP(x) ((x) << S_TCPOPT_TSTAMP) 737 #define G_TCPOPT_TSTAMP(x) (((x) >> S_TCPOPT_TSTAMP) & M_TCPOPT_TSTAMP) 738 739 #define S_TCPOPT_SND_WSCALE 8 740 #define M_TCPOPT_SND_WSCALE 0xF 741 #define V_TCPOPT_SND_WSCALE(x) ((x) << S_TCPOPT_SND_WSCALE) 742 #define G_TCPOPT_SND_WSCALE(x) (((x) >> S_TCPOPT_SND_WSCALE) & M_TCPOPT_SND_WSCALE) 743 744 #define S_TCPOPT_MSS 12 745 #define M_TCPOPT_MSS 0xF 746 #define V_TCPOPT_MSS(x) ((x) << S_TCPOPT_MSS) 747 #define G_TCPOPT_MSS(x) (((x) >> S_TCPOPT_MSS) & M_TCPOPT_MSS) 748 749 struct cpl_pass_accept_req { 750 RSS_HDR 751 union opcode_tid ot; 752 __be16 ipsecen_outiphdrlen; 753 __be16 len; 754 __be32 hdr_len; 755 __be16 vlan; 756 __be16 l2info; 757 __be32 tos_stid; 758 struct tcp_options tcpopt; 759 }; 760 761 /* cpl_pass_accept_req.hdr_len fields */ 762 #define S_SYN_RX_CHAN 0 763 #define M_SYN_RX_CHAN 0xF 764 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 765 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 766 767 #define S_TCP_HDR_LEN 10 768 #define M_TCP_HDR_LEN 0x3F 769 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 770 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 771 772 #define S_T6_TCP_HDR_LEN 8 773 #define V_T6_TCP_HDR_LEN(x) ((x) << S_T6_TCP_HDR_LEN) 774 #define G_T6_TCP_HDR_LEN(x) (((x) >> S_T6_TCP_HDR_LEN) & M_TCP_HDR_LEN) 775 776 #define S_IP_HDR_LEN 16 777 #define M_IP_HDR_LEN 0x3FF 778 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 779 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 780 781 #define S_T6_IP_HDR_LEN 14 782 #define V_T6_IP_HDR_LEN(x) ((x) << S_T6_IP_HDR_LEN) 783 #define G_T6_IP_HDR_LEN(x) (((x) >> S_T6_IP_HDR_LEN) & M_IP_HDR_LEN) 784 785 #define S_ETH_HDR_LEN 26 786 #define M_ETH_HDR_LEN 0x3F 787 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 788 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 789 790 #define S_T6_ETH_HDR_LEN 24 791 #define M_T6_ETH_HDR_LEN 0xFF 792 #define V_T6_ETH_HDR_LEN(x) ((x) << S_T6_ETH_HDR_LEN) 793 #define G_T6_ETH_HDR_LEN(x) (((x) >> S_T6_ETH_HDR_LEN) & M_T6_ETH_HDR_LEN) 794 795 /* cpl_pass_accept_req.l2info fields */ 796 #define S_SYN_MAC_IDX 0 797 #define M_SYN_MAC_IDX 0x1FF 798 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 799 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 800 801 #define S_SYN_XACT_MATCH 9 802 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 803 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 804 805 #define S_SYN_INTF 12 806 #define M_SYN_INTF 0xF 807 #define V_SYN_INTF(x) ((x) << S_SYN_INTF) 808 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 809 810 struct cpl_t7_pass_accept_req { 811 RSS_HDR 812 union opcode_tid ot; 813 __be16 ipsecen_to_outiphdrlen; 814 __be16 length; 815 __be32 ethhdrlen_to_rxchannel; 816 __be16 vlantag; 817 __be16 interface_to_mac_ix; 818 __be32 tos_ptid; 819 __be16 tcpmss; 820 __u8 tcpwsc; 821 __u8 tcptmstp_to_tcpunkn; 822 }; 823 824 #define S_CPL_T7_PASS_ACCEPT_REQ_IPSECEN 12 825 #define M_CPL_T7_PASS_ACCEPT_REQ_IPSECEN 0x1 826 #define V_CPL_T7_PASS_ACCEPT_REQ_IPSECEN(x) \ 827 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_IPSECEN) 828 #define G_CPL_T7_PASS_ACCEPT_REQ_IPSECEN(x) \ 829 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_IPSECEN) & \ 830 M_CPL_T7_PASS_ACCEPT_REQ_IPSECEN) 831 #define F_CPL_PASS_T7_ACCEPT_REQ_IPSECEN \ 832 V_CPL_T7_PASS_ACCEPT_REQ_IPSECEN(1U) 833 834 #define S_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE 10 835 #define M_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE 0x3 836 #define V_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE(x) \ 837 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE) 838 #define G_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE(x) \ 839 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE) & \ 840 M_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE) 841 842 #define S_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN 0 843 #define M_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN 0x3ff 844 #define V_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN(x) \ 845 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN) 846 #define G_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN(x) \ 847 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN) & \ 848 M_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN) 849 850 #define S_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN 24 851 #define M_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN 0xff 852 #define V_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN(x) \ 853 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN) 854 #define G_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN(x) \ 855 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN) & \ 856 M_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN) 857 858 #define S_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN 14 859 #define M_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN 0x3ff 860 #define V_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN(x) \ 861 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN) 862 #define G_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN(x) \ 863 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN) & \ 864 M_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN) 865 866 #define S_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN 8 867 #define M_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN 0x3f 868 #define V_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN(x) \ 869 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN) 870 #define G_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN(x) \ 871 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN) & \ 872 M_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN) 873 874 #define S_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL 0 875 #define M_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL 0xf 876 #define V_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL(x) \ 877 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL) 878 #define G_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL(x) \ 879 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL) & \ 880 M_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL) 881 882 #define S_CPL_T7_PASS_ACCEPT_REQ_INTERFACE 12 883 #define M_CPL_T7_PASS_ACCEPT_REQ_INTERFACE 0xf 884 #define V_CPL_T7_PASS_ACCEPT_REQ_INTERFACE(x) \ 885 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_INTERFACE) 886 #define G_CPL_T7_PASS_ACCEPT_REQ_INTERFACE(x) \ 887 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_INTERFACE) & \ 888 M_CPL_T7_PASS_ACCEPT_REQ_INTERFACE) 889 890 #define S_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH 9 891 #define M_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH 0x1 892 #define V_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH(x) \ 893 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH) 894 #define G_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH(x) \ 895 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH) & \ 896 M_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH) 897 #define F_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH \ 898 V_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH(1U) 899 900 #define S_CPL_T7_PASS_ACCEPT_REQ_MAC_IX 0 901 #define M_CPL_T7_PASS_ACCEPT_REQ_MAC_IX 0x1ff 902 #define V_CPL_T7_PASS_ACCEPT_REQ_MAC_IX(x) \ 903 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_MAC_IX) 904 #define G_CPL_T7_PASS_ACCEPT_REQ_MAC_IX(x) \ 905 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_MAC_IX) & M_CPL_T7_PASS_ACCEPT_REQ_MAC_IX) 906 907 #define S_CPL_T7_PASS_ACCEPT_REQ_TOS 24 908 #define M_CPL_T7_PASS_ACCEPT_REQ_TOS 0xff 909 #define V_CPL_T7_PASS_ACCEPT_REQ_TOS(x) ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TOS) 910 #define G_CPL_T7_PASS_ACCEPT_REQ_TOS(x) \ 911 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TOS) & M_CPL_T7_PASS_ACCEPT_REQ_TOS) 912 913 #define S_CPL_T7_PASS_ACCEPT_REQ_PTID 0 914 #define M_CPL_T7_PASS_ACCEPT_REQ_PTID 0xffffff 915 #define V_CPL_T7_PASS_ACCEPT_REQ_PTID(x) \ 916 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_PTID) 917 #define G_CPL_T7_PASS_ACCEPT_REQ_PTID(x) \ 918 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_PTID) & M_CPL_T7_PASS_ACCEPT_REQ_PTID) 919 920 #define S_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP 7 921 #define M_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP 0x1 922 #define V_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP(x) \ 923 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP) 924 #define G_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP(x) \ 925 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP) & \ 926 M_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP) 927 #define F_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP \ 928 V_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP(1U) 929 930 #define S_CPL_T7_PASS_ACCEPT_REQ_TCPSACK 6 931 #define M_CPL_T7_PASS_ACCEPT_REQ_TCPSACK 0x1 932 #define V_CPL_T7_PASS_ACCEPT_REQ_TCPSACK(x) \ 933 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPSACK) 934 #define G_CPL_T7_PASS_ACCEPT_REQ_TCPSACK(x) \ 935 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPSACK) & \ 936 M_CPL_T7_PASS_ACCEPT_REQ_TCPSACK) 937 #define F_CPL_T7_PASS_ACCEPT_REQ_TCPSACK \ 938 V_CPL_T7_PASS_ACCEPT_REQ_TCPSACK(1U) 939 940 #define S_CPL_T7_PASS_ACCEPT_REQ_TCPECN 5 941 #define M_CPL_T7_PASS_ACCEPT_REQ_TCPECN 0x1 942 #define V_CPL_T7_PASS_ACCEPT_REQ_TCPECN(x) \ 943 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPECN) 944 #define G_CPL_T7_PASS_ACCEPT_REQ_TCPECN(x) \ 945 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPECN) & M_CPL_T7_PASS_ACCEPT_REQ_TCPECN) 946 #define F_CPL_T7_PASS_ACCEPT_REQ_TCPECN \ 947 V_CPL_T7_PASS_ACCEPT_REQ_TCPECN(1U) 948 949 #define S_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN 4 950 #define M_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN 0x1 951 #define V_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN(x) \ 952 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN) 953 #define G_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN(x) \ 954 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN) & \ 955 M_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN) 956 #define F_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN \ 957 V_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN(1U) 958 959 struct cpl_pass_accept_rpl { 960 WR_HDR; 961 union opcode_tid ot; 962 __be32 opt2; 963 __be64 opt0; 964 }; 965 966 struct cpl_t5_pass_accept_rpl { 967 WR_HDR; 968 union opcode_tid ot; 969 __be32 opt2; 970 __be64 opt0; 971 __be32 iss; 972 union { 973 __be32 rsvd; /* T5 */ 974 __be32 opt3; /* T6 */ 975 } u; 976 }; 977 978 struct cpl_act_open_req { 979 WR_HDR; 980 union opcode_tid ot; 981 __be16 local_port; 982 __be16 peer_port; 983 __be32 local_ip; 984 __be32 peer_ip; 985 __be64 opt0; 986 __be32 params; 987 __be32 opt2; 988 }; 989 990 #define S_FILTER_TUPLE 24 991 #define M_FILTER_TUPLE 0xFFFFFFFFFF 992 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) 993 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) 994 995 struct cpl_t5_act_open_req { 996 WR_HDR; 997 union opcode_tid ot; 998 __be16 local_port; 999 __be16 peer_port; 1000 __be32 local_ip; 1001 __be32 peer_ip; 1002 __be64 opt0; 1003 __be32 iss; 1004 __be32 opt2; 1005 __be64 params; 1006 }; 1007 1008 struct cpl_t6_act_open_req { 1009 WR_HDR; 1010 union opcode_tid ot; 1011 __be16 local_port; 1012 __be16 peer_port; 1013 __be32 local_ip; 1014 __be32 peer_ip; 1015 __be64 opt0; 1016 __be32 iss; 1017 __be32 opt2; 1018 __be64 params; 1019 __be32 rsvd2; 1020 __be32 opt3; 1021 }; 1022 1023 /* cpl_{t5,t6}_act_open_req.params field */ 1024 #define S_AOPEN_FCOEMASK 0 1025 #define V_AOPEN_FCOEMASK(x) ((x) << S_AOPEN_FCOEMASK) 1026 #define F_AOPEN_FCOEMASK V_AOPEN_FCOEMASK(1U) 1027 1028 struct cpl_t7_act_open_req { 1029 WR_HDR; 1030 union opcode_tid ot; 1031 __be16 local_port; 1032 __be16 peer_port; 1033 __be32 local_ip; 1034 __be32 peer_ip; 1035 __be64 opt0; 1036 __be32 iss; 1037 __be32 opt2; 1038 __be64 params; 1039 __be32 rsvd2; 1040 __be32 opt3; 1041 }; 1042 1043 #define S_T7_FILTER_TUPLE 1 1044 #define M_T7_FILTER_TUPLE 0x7FFFFFFFFFFFFFFFULL 1045 #define V_T7_FILTER_TUPLE(x) ((x) << S_T7_FILTER_TUPLE) 1046 #define G_T7_FILTER_TUPLE(x) (((x) >> S_T7_FILTER_TUPLE) & M_T7_FILTER_TUPLE) 1047 1048 struct cpl_act_open_req6 { 1049 WR_HDR; 1050 union opcode_tid ot; 1051 __be16 local_port; 1052 __be16 peer_port; 1053 __be64 local_ip_hi; 1054 __be64 local_ip_lo; 1055 __be64 peer_ip_hi; 1056 __be64 peer_ip_lo; 1057 __be64 opt0; 1058 __be32 params; 1059 __be32 opt2; 1060 }; 1061 1062 struct cpl_t5_act_open_req6 { 1063 WR_HDR; 1064 union opcode_tid ot; 1065 __be16 local_port; 1066 __be16 peer_port; 1067 __be64 local_ip_hi; 1068 __be64 local_ip_lo; 1069 __be64 peer_ip_hi; 1070 __be64 peer_ip_lo; 1071 __be64 opt0; 1072 __be32 iss; 1073 __be32 opt2; 1074 __be64 params; 1075 }; 1076 1077 struct cpl_t6_act_open_req6 { 1078 WR_HDR; 1079 union opcode_tid ot; 1080 __be16 local_port; 1081 __be16 peer_port; 1082 __be64 local_ip_hi; 1083 __be64 local_ip_lo; 1084 __be64 peer_ip_hi; 1085 __be64 peer_ip_lo; 1086 __be64 opt0; 1087 __be32 iss; 1088 __be32 opt2; 1089 __be64 params; 1090 __be32 rsvd2; 1091 __be32 opt3; 1092 }; 1093 1094 struct cpl_t7_act_open_req6 { 1095 WR_HDR; 1096 union opcode_tid ot; 1097 __be16 local_port; 1098 __be16 peer_port; 1099 __be64 local_ip_hi; 1100 __be64 local_ip_lo; 1101 __be64 peer_ip_hi; 1102 __be64 peer_ip_lo; 1103 __be64 opt0; 1104 __be32 iss; 1105 __be32 opt2; 1106 __be64 params; 1107 __be32 rsvd2; 1108 __be32 opt3; 1109 }; 1110 1111 struct cpl_act_open_rpl { 1112 RSS_HDR 1113 union opcode_tid ot; 1114 __be32 atid_status; 1115 }; 1116 1117 /* cpl_act_open_rpl.atid_status fields */ 1118 #define S_AOPEN_STATUS 0 1119 #define M_AOPEN_STATUS 0xFF 1120 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 1121 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 1122 1123 #define S_AOPEN_ATID 8 1124 #define M_AOPEN_ATID 0xFFFFFF 1125 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 1126 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 1127 1128 struct cpl_act_establish { 1129 RSS_HDR 1130 union opcode_tid ot; 1131 __be32 rsvd; 1132 __be32 tos_atid; 1133 __be16 mac_idx; 1134 __be16 tcp_opt; 1135 __be32 snd_isn; 1136 __be32 rcv_isn; 1137 }; 1138 1139 struct cpl_get_tcb { 1140 WR_HDR; 1141 union opcode_tid ot; 1142 __be16 reply_ctrl; 1143 __be16 cookie; 1144 }; 1145 1146 /* cpl_get_tcb.reply_ctrl fields */ 1147 #define S_QUEUENO 0 1148 #define M_QUEUENO 0x3FF 1149 #define V_QUEUENO(x) ((x) << S_QUEUENO) 1150 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 1151 1152 #define S_T7_QUEUENO 0 1153 #define M_T7_QUEUENO 0xFFF 1154 #define V_T7_QUEUENO(x) ((x) << S_T7_QUEUENO) 1155 #define G_T7_QUEUENO(x) (((x) >> S_T7_QUEUENO) & M_T7_QUEUENO) 1156 1157 #define S_REPLY_CHAN 14 1158 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 1159 #define F_REPLY_CHAN V_REPLY_CHAN(1U) 1160 1161 #define S_T7_REPLY_CHAN 12 1162 #define M_T7_REPLY_CHAN 0x7 1163 #define V_T7_REPLY_CHAN(x) ((x) << S_T7_REPLY_CHAN) 1164 #define G_T7_REPLY_CHAN(x) (((x) >> S_T7_REPLY_CHAN) & M_T7_REPLY_CHAN) 1165 1166 #define S_NO_REPLY 15 1167 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 1168 #define F_NO_REPLY V_NO_REPLY(1U) 1169 1170 struct cpl_get_tcb_rpl { 1171 RSS_HDR 1172 union opcode_tid ot; 1173 __u8 cookie; 1174 __u8 status; 1175 __be16 len; 1176 }; 1177 1178 struct cpl_set_tcb { 1179 WR_HDR; 1180 union opcode_tid ot; 1181 __be16 reply_ctrl; 1182 __be16 cookie; 1183 }; 1184 1185 struct cpl_set_tcb_field { 1186 WR_HDR; 1187 union opcode_tid ot; 1188 __be16 reply_ctrl; 1189 __be16 word_cookie; 1190 __be64 mask; 1191 __be64 val; 1192 }; 1193 1194 struct cpl_set_tcb_field_core { 1195 union opcode_tid ot; 1196 __be16 reply_ctrl; 1197 __be16 word_cookie; 1198 __be64 mask; 1199 __be64 val; 1200 }; 1201 1202 /* cpl_set_tcb_field.word_cookie fields */ 1203 #define S_WORD 0 1204 #define M_WORD 0x1F 1205 #define V_WORD(x) ((x) << S_WORD) 1206 #define G_WORD(x) (((x) >> S_WORD) & M_WORD) 1207 1208 #define S_COOKIE 5 1209 #define M_COOKIE 0x7 1210 #define V_COOKIE(x) ((x) << S_COOKIE) 1211 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 1212 1213 struct cpl_set_tcb_rpl { 1214 RSS_HDR 1215 union opcode_tid ot; 1216 __be16 rsvd; 1217 __u8 cookie; 1218 __u8 status; 1219 __be64 oldval; 1220 }; 1221 1222 struct cpl_close_con_req { 1223 WR_HDR; 1224 union opcode_tid ot; 1225 __be32 rsvd; 1226 }; 1227 1228 struct cpl_close_con_rpl { 1229 RSS_HDR 1230 union opcode_tid ot; 1231 __u8 rsvd[3]; 1232 __u8 status; 1233 __be32 snd_nxt; 1234 __be32 rcv_nxt; 1235 }; 1236 1237 struct cpl_close_listsvr_req { 1238 WR_HDR; 1239 union opcode_tid ot; 1240 __be16 reply_ctrl; 1241 __be16 rsvd; 1242 }; 1243 1244 /* additional cpl_close_listsvr_req.reply_ctrl field */ 1245 #define S_LISTSVR_IPV6 14 1246 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 1247 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 1248 1249 struct cpl_t7_close_listsvr_req { 1250 WR_HDR; 1251 union opcode_tid ot; 1252 __be16 noreply_to_queue; 1253 __be16 r2; 1254 }; 1255 1256 #define S_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY 15 1257 #define M_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY 0x1 1258 #define V_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY(x) \ 1259 ((x) << S_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY) 1260 #define G_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY(x) \ 1261 (((x) >> S_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY) & \ 1262 M_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY) 1263 #define F_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY \ 1264 V_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY(1U) 1265 1266 #define S_CPL_T7_CLOSE_LISTSVR_REQ_IPV6 14 1267 #define M_CPL_T7_CLOSE_LISTSVR_REQ_IPV6 0x1 1268 #define V_CPL_T7_CLOSE_LISTSVR_REQ_IPV6(x) \ 1269 ((x) << S_CPL_T7_CLOSE_LISTSVR_REQ_IPV6) 1270 #define G_CPL_T7_CLOSE_LISTSVR_REQ_IPV6(x) \ 1271 (((x) >> S_CPL_T7_CLOSE_LISTSVR_REQ_IPV6) & M_CPL_T7_CLOSE_LISTSVR_REQ_IPV6) 1272 #define F_CPL_T7_CLOSE_LISTSVR_REQ_IPV6 \ 1273 V_CPL_T7_CLOSE_LISTSVR_REQ_IPV6(1U) 1274 1275 #define S_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE 0 1276 #define M_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE 0xfff 1277 #define V_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE(x) \ 1278 ((x) << S_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE) 1279 #define G_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE(x) \ 1280 (((x) >> S_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE) & \ 1281 M_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE) 1282 1283 struct cpl_close_listsvr_rpl { 1284 RSS_HDR 1285 union opcode_tid ot; 1286 __u8 rsvd[3]; 1287 __u8 status; 1288 }; 1289 1290 struct cpl_abort_req_rss { 1291 RSS_HDR 1292 union opcode_tid ot; 1293 __u8 rsvd[3]; 1294 __u8 status; 1295 }; 1296 1297 struct cpl_abort_req_rss6 { 1298 RSS_HDR 1299 union opcode_tid ot; 1300 __u32 srqidx_status; 1301 }; 1302 1303 #define S_ABORT_RSS_STATUS 0 1304 #define M_ABORT_RSS_STATUS 0xff 1305 #define V_ABORT_RSS_STATUS(x) ((x) << S_ABORT_RSS_STATUS) 1306 #define G_ABORT_RSS_STATUS(x) (((x) >> S_ABORT_RSS_STATUS) & M_ABORT_RSS_STATUS) 1307 1308 #define S_ABORT_RSS_SRQIDX 8 1309 #define M_ABORT_RSS_SRQIDX 0xffffff 1310 #define V_ABORT_RSS_SRQIDX(x) ((x) << S_ABORT_RSS_SRQIDX) 1311 #define G_ABORT_RSS_SRQIDX(x) (((x) >> S_ABORT_RSS_SRQIDX) & M_ABORT_RSS_SRQIDX) 1312 1313 1314 /* cpl_abort_req status command code in case of T6, 1315 * bit[0] specifies whether to send RST (0) to remote peer or suppress it (1) 1316 * bit[1] indicates ABORT_REQ was sent after a CLOSE_CON_REQ 1317 * bit[2] specifies whether to disable the mmgr (1) or not (0) 1318 */ 1319 struct cpl_abort_req { 1320 WR_HDR; 1321 union opcode_tid ot; 1322 __be32 rsvd0; 1323 __u8 rsvd1; 1324 __u8 cmd; 1325 __u8 rsvd2[6]; 1326 }; 1327 1328 struct cpl_abort_req_core { 1329 union opcode_tid ot; 1330 __be32 rsvd0; 1331 __u8 rsvd1; 1332 __u8 cmd; 1333 __u8 rsvd2[6]; 1334 }; 1335 1336 struct cpl_abort_rpl_rss { 1337 RSS_HDR 1338 union opcode_tid ot; 1339 __u8 rsvd[3]; 1340 __u8 status; 1341 }; 1342 1343 struct cpl_abort_rpl_rss6 { 1344 RSS_HDR 1345 union opcode_tid ot; 1346 __u32 srqidx_status; 1347 }; 1348 1349 struct cpl_abort_rpl { 1350 WR_HDR; 1351 union opcode_tid ot; 1352 __be32 rsvd0; 1353 __u8 rsvd1; 1354 __u8 cmd; 1355 __u8 rsvd2[6]; 1356 }; 1357 1358 struct cpl_abort_rpl_core { 1359 union opcode_tid ot; 1360 __be32 rsvd0; 1361 __u8 rsvd1; 1362 __u8 cmd; 1363 __u8 rsvd2[6]; 1364 }; 1365 1366 struct cpl_peer_close { 1367 RSS_HDR 1368 union opcode_tid ot; 1369 __be32 rcv_nxt; 1370 }; 1371 1372 struct cpl_tid_release { 1373 WR_HDR; 1374 union opcode_tid ot; 1375 __be32 rsvd; 1376 }; 1377 1378 struct tx_data_wr { 1379 __be32 wr_hi; 1380 __be32 wr_lo; 1381 __be32 len; 1382 __be32 flags; 1383 __be32 sndseq; 1384 __be32 param; 1385 }; 1386 1387 /* tx_data_wr.flags fields */ 1388 #define S_TX_ACK_PAGES 21 1389 #define M_TX_ACK_PAGES 0x7 1390 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 1391 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 1392 1393 /* tx_data_wr.param fields */ 1394 #define S_TX_PORT 0 1395 #define M_TX_PORT 0x7 1396 #define V_TX_PORT(x) ((x) << S_TX_PORT) 1397 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 1398 1399 #define S_TX_MSS 4 1400 #define M_TX_MSS 0xF 1401 #define V_TX_MSS(x) ((x) << S_TX_MSS) 1402 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 1403 1404 #define S_TX_QOS 8 1405 #define M_TX_QOS 0xFF 1406 #define V_TX_QOS(x) ((x) << S_TX_QOS) 1407 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 1408 1409 #define S_TX_SNDBUF 16 1410 #define M_TX_SNDBUF 0xFFFF 1411 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 1412 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 1413 1414 struct cpl_tx_data { 1415 union opcode_tid ot; 1416 __be32 len; 1417 __be32 rsvd; 1418 __be32 flags; 1419 }; 1420 1421 /* cpl_tx_data.len fields */ 1422 #define S_TX_DATA_MSS 16 1423 #define M_TX_DATA_MSS 0xFFFF 1424 #define V_TX_DATA_MSS(x) ((x) << S_TX_DATA_MSS) 1425 #define G_TX_DATA_MSS(x) (((x) >> S_TX_DATA_MSS) & M_TX_DATA_MSS) 1426 1427 #define S_TX_LENGTH 0 1428 #define M_TX_LENGTH 0xFFFF 1429 #define V_TX_LENGTH(x) ((x) << S_TX_LENGTH) 1430 #define G_TX_LENGTH(x) (((x) >> S_TX_LENGTH) & M_TX_LENGTH) 1431 1432 /* cpl_tx_data.flags fields */ 1433 #define S_TX_PROXY 5 1434 #define V_TX_PROXY(x) ((x) << S_TX_PROXY) 1435 #define F_TX_PROXY V_TX_PROXY(1U) 1436 1437 #define S_TX_ULP_SUBMODE 6 1438 #define M_TX_ULP_SUBMODE 0xF 1439 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 1440 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 1441 1442 #define S_TX_ULP_MODE 10 1443 #define M_TX_ULP_MODE 0x7 1444 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 1445 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 1446 1447 #define S_TX_FORCE 13 1448 #define V_TX_FORCE(x) ((x) << S_TX_FORCE) 1449 #define F_TX_FORCE V_TX_FORCE(1U) 1450 1451 #define S_TX_SHOVE 14 1452 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 1453 #define F_TX_SHOVE V_TX_SHOVE(1U) 1454 1455 #define S_TX_MORE 15 1456 #define V_TX_MORE(x) ((x) << S_TX_MORE) 1457 #define F_TX_MORE V_TX_MORE(1U) 1458 1459 #define S_TX_URG 16 1460 #define V_TX_URG(x) ((x) << S_TX_URG) 1461 #define F_TX_URG V_TX_URG(1U) 1462 1463 #define S_TX_FLUSH 17 1464 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 1465 #define F_TX_FLUSH V_TX_FLUSH(1U) 1466 1467 #define S_TX_SAVE 18 1468 #define V_TX_SAVE(x) ((x) << S_TX_SAVE) 1469 #define F_TX_SAVE V_TX_SAVE(1U) 1470 1471 #define S_TX_TNL 19 1472 #define V_TX_TNL(x) ((x) << S_TX_TNL) 1473 #define F_TX_TNL V_TX_TNL(1U) 1474 1475 #define S_T6_TX_FORCE 20 1476 #define V_T6_TX_FORCE(x) ((x) << S_T6_TX_FORCE) 1477 #define F_T6_TX_FORCE V_T6_TX_FORCE(1U) 1478 1479 #define S_TX_BYPASS 21 1480 #define V_TX_BYPASS(x) ((x) << S_TX_BYPASS) 1481 #define F_TX_BYPASS V_TX_BYPASS(1U) 1482 1483 #define S_TX_PUSH 22 1484 #define V_TX_PUSH(x) ((x) << S_TX_PUSH) 1485 #define F_TX_PUSH V_TX_PUSH(1U) 1486 1487 /* additional tx_data_wr.flags fields */ 1488 #define S_TX_CPU_IDX 0 1489 #define M_TX_CPU_IDX 0x3F 1490 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 1491 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 1492 1493 #define S_TX_CLOSE 17 1494 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 1495 #define F_TX_CLOSE V_TX_CLOSE(1U) 1496 1497 #define S_TX_INIT 18 1498 #define V_TX_INIT(x) ((x) << S_TX_INIT) 1499 #define F_TX_INIT V_TX_INIT(1U) 1500 1501 #define S_TX_IMM_ACK 19 1502 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 1503 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 1504 1505 #define S_TX_IMM_DMA 20 1506 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 1507 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 1508 1509 struct cpl_tx_data_ack { 1510 RSS_HDR 1511 union opcode_tid ot; 1512 __be32 snd_una; 1513 }; 1514 1515 struct cpl_tx_data_ack_xt { 1516 RSS_HDR 1517 union opcode_tid ot; 1518 __be32 snd_una; 1519 __be32 snd_end; 1520 __be32 snd_nxt; 1521 __be32 snd_adv; 1522 __be16 rttvar; 1523 __be16 srtt; 1524 __be32 extinfoh[2]; 1525 __be32 extinfol[2]; 1526 }; 1527 1528 struct cpl_tx_data_req { 1529 RSS_HDR 1530 union opcode_tid ot; 1531 __be32 snd_una; 1532 __be32 snd_end; 1533 __be32 snd_nxt; 1534 __be32 snd_adv; 1535 __be16 rttvar; 1536 __be16 srtt; 1537 }; 1538 1539 #define S_CPL_TX_DATA_REQ_TID 0 1540 #define M_CPL_TX_DATA_REQ_TID 0xffffff 1541 #define V_CPL_TX_DATA_REQ_TID(x) ((x) << S_CPL_TX_DATA_REQ_TID) 1542 #define G_CPL_TX_DATA_REQ_TID(x) \ 1543 (((x) >> S_CPL_TX_DATA_REQ_TID) & M_CPL_TX_DATA_REQ_TID) 1544 1545 struct cpl_sack_req { 1546 RSS_HDR 1547 union opcode_tid ot; 1548 __be32 snd_una; 1549 __be32 snd_end; 1550 __be32 snd_nxt; 1551 __be32 snd_adv; 1552 __be16 rttvar; 1553 __be16 srtt; 1554 __be32 block1[2]; 1555 __be32 block2[2]; 1556 __be32 block3[2]; 1557 }; 1558 1559 struct cpl_sge_flr_flush { 1560 RSS_HDR 1561 union opcode_tid ot; 1562 __be32 cookievalue_cookiesel; 1563 }; 1564 1565 #define S_CPL_SGE_FLR_FLUSH_COOKIEVALUE 4 1566 #define M_CPL_SGE_FLR_FLUSH_COOKIEVALUE 0x3ff 1567 #define V_CPL_SGE_FLR_FLUSH_COOKIEVALUE(x) \ 1568 ((x) << S_CPL_SGE_FLR_FLUSH_COOKIEVALUE) 1569 #define G_CPL_SGE_FLR_FLUSH_COOKIEVALUE(x) \ 1570 (((x) >> S_CPL_SGE_FLR_FLUSH_COOKIEVALUE) & \ 1571 M_CPL_SGE_FLR_FLUSH_COOKIEVALUE) 1572 1573 #define S_CPL_SGE_FLR_FLUSH_COOKIESEL 0 1574 #define M_CPL_SGE_FLR_FLUSH_COOKIESEL 0xf 1575 #define V_CPL_SGE_FLR_FLUSH_COOKIESEL(x) \ 1576 ((x) << S_CPL_SGE_FLR_FLUSH_COOKIESEL) 1577 #define G_CPL_SGE_FLR_FLUSH_COOKIESEL(x) \ 1578 (((x) >> S_CPL_SGE_FLR_FLUSH_COOKIESEL) & M_CPL_SGE_FLR_FLUSH_COOKIESEL) 1579 1580 struct cpl_wr_ack { /* XXX */ 1581 RSS_HDR 1582 union opcode_tid ot; 1583 __be16 credits; 1584 __be16 rsvd; 1585 __be32 snd_nxt; 1586 __be32 snd_una; 1587 }; 1588 1589 struct cpl_tx_pkt_core { 1590 __be32 ctrl0; 1591 __be16 pack; 1592 __be16 len; 1593 __be64 ctrl1; 1594 }; 1595 1596 struct cpl_tx_pkt { 1597 WR_HDR; 1598 struct cpl_tx_pkt_core c; 1599 }; 1600 1601 /* cpl_tx_pkt_core.ctrl0 fields */ 1602 #define S_TXPKT_VF 0 1603 #define M_TXPKT_VF 0xFF 1604 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 1605 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 1606 1607 #define S_TXPKT_PF 8 1608 #define M_TXPKT_PF 0x7 1609 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 1610 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 1611 1612 #define S_TXPKT_VF_VLD 11 1613 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 1614 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 1615 1616 #define S_TXPKT_OVLAN_IDX 12 1617 #define M_TXPKT_OVLAN_IDX 0xF 1618 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 1619 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1620 1621 #define S_TXPKT_T5_OVLAN_IDX 12 1622 #define M_TXPKT_T5_OVLAN_IDX 0x7 1623 #define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX) 1624 #define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \ 1625 M_TXPKT_T5_OVLAN_IDX) 1626 1627 #define S_TXPKT_INTF 16 1628 #define M_TXPKT_INTF 0xF 1629 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1630 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1631 1632 #define S_TXPKT_SPECIAL_STAT 20 1633 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1634 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1635 1636 #define S_TXPKT_T5_FCS_DIS 21 1637 #define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS) 1638 #define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U) 1639 1640 #define S_TXPKT_INS_OVLAN 21 1641 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1642 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1643 1644 #define S_TXPKT_T5_INS_OVLAN 15 1645 #define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN) 1646 #define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U) 1647 1648 #define S_TXPKT_STAT_DIS 22 1649 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1650 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1651 1652 #define S_TXPKT_LOOPBACK 23 1653 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1654 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1655 1656 #define S_TXPKT_TSTAMP 23 1657 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) 1658 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) 1659 1660 #define S_TXPKT_OPCODE 24 1661 #define M_TXPKT_OPCODE 0xFF 1662 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1663 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1664 1665 /* cpl_tx_pkt_core.ctrl1 fields */ 1666 #define S_TXPKT_SA_IDX 0 1667 #define M_TXPKT_SA_IDX 0xFFF 1668 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1669 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1670 1671 #define S_TXPKT_CSUM_END 12 1672 #define M_TXPKT_CSUM_END 0xFF 1673 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1674 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1675 1676 #define S_TXPKT_CSUM_START 20 1677 #define M_TXPKT_CSUM_START 0x3FF 1678 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1679 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1680 1681 #define S_TXPKT_IPHDR_LEN 20 1682 #define M_TXPKT_IPHDR_LEN 0x3FFF 1683 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1684 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1685 1686 #define M_T6_TXPKT_IPHDR_LEN 0xFFF 1687 #define G_T6_TXPKT_IPHDR_LEN(x) \ 1688 (((x) >> S_TXPKT_IPHDR_LEN) & M_T6_TXPKT_IPHDR_LEN) 1689 1690 #define S_TXPKT_CSUM_LOC 30 1691 #define M_TXPKT_CSUM_LOC 0x3FF 1692 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1693 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1694 1695 #define S_TXPKT_ETHHDR_LEN 34 1696 #define M_TXPKT_ETHHDR_LEN 0x3F 1697 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1698 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1699 1700 #define S_T6_TXPKT_ETHHDR_LEN 32 1701 #define M_T6_TXPKT_ETHHDR_LEN 0xFF 1702 #define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN) 1703 #define G_T6_TXPKT_ETHHDR_LEN(x) \ 1704 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN) 1705 1706 #define S_TXPKT_CSUM_TYPE 40 1707 #define M_TXPKT_CSUM_TYPE 0xF 1708 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1709 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1710 1711 #define S_TXPKT_VLAN 44 1712 #define M_TXPKT_VLAN 0xFFFF 1713 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1714 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1715 1716 #define S_TXPKT_VLAN_VLD 60 1717 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1718 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1719 1720 #define S_TXPKT_IPSEC 61 1721 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1722 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1723 1724 #define S_TXPKT_IPCSUM_DIS 62 1725 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1726 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1727 1728 #define S_TXPKT_L4CSUM_DIS 63 1729 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1730 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1731 1732 struct cpl_tx_pkt_xt { 1733 WR_HDR; 1734 __be32 ctrl0; 1735 __be16 pack; 1736 __be16 len; 1737 __be32 ctrl1; 1738 __be32 ctrl2; 1739 }; 1740 1741 /* cpl_tx_pkt_xt.core.ctrl0 fields */ 1742 #define S_CPL_TX_PKT_XT_OPCODE 24 1743 #define M_CPL_TX_PKT_XT_OPCODE 0xff 1744 #define V_CPL_TX_PKT_XT_OPCODE(x) ((x) << S_CPL_TX_PKT_XT_OPCODE) 1745 #define G_CPL_TX_PKT_XT_OPCODE(x) \ 1746 (((x) >> S_CPL_TX_PKT_XT_OPCODE) & M_CPL_TX_PKT_XT_OPCODE) 1747 1748 #define S_CPL_TX_PKT_XT_TIMESTAMP 23 1749 #define M_CPL_TX_PKT_XT_TIMESTAMP 0x1 1750 #define V_CPL_TX_PKT_XT_TIMESTAMP(x) ((x) << S_CPL_TX_PKT_XT_TIMESTAMP) 1751 #define G_CPL_TX_PKT_XT_TIMESTAMP(x) \ 1752 (((x) >> S_CPL_TX_PKT_XT_TIMESTAMP) & M_CPL_TX_PKT_XT_TIMESTAMP) 1753 #define F_CPL_TX_PKT_XT_TIMESTAMP V_CPL_TX_PKT_XT_TIMESTAMP(1U) 1754 1755 #define S_CPL_TX_PKT_XT_STATDISABLE 22 1756 #define M_CPL_TX_PKT_XT_STATDISABLE 0x1 1757 #define V_CPL_TX_PKT_XT_STATDISABLE(x) ((x) << S_CPL_TX_PKT_XT_STATDISABLE) 1758 #define G_CPL_TX_PKT_XT_STATDISABLE(x) \ 1759 (((x) >> S_CPL_TX_PKT_XT_STATDISABLE) & M_CPL_TX_PKT_XT_STATDISABLE) 1760 #define F_CPL_TX_PKT_XT_STATDISABLE V_CPL_TX_PKT_XT_STATDISABLE(1U) 1761 1762 #define S_CPL_TX_PKT_XT_FCSDIS 21 1763 #define M_CPL_TX_PKT_XT_FCSDIS 0x1 1764 #define V_CPL_TX_PKT_XT_FCSDIS(x) ((x) << S_CPL_TX_PKT_XT_FCSDIS) 1765 #define G_CPL_TX_PKT_XT_FCSDIS(x) \ 1766 (((x) >> S_CPL_TX_PKT_XT_FCSDIS) & M_CPL_TX_PKT_XT_FCSDIS) 1767 #define F_CPL_TX_PKT_XT_FCSDIS V_CPL_TX_PKT_XT_FCSDIS(1U) 1768 1769 #define S_CPL_TX_PKT_XT_STATSPECIAL 20 1770 #define M_CPL_TX_PKT_XT_STATSPECIAL 0x1 1771 #define V_CPL_TX_PKT_XT_STATSPECIAL(x) ((x) << S_CPL_TX_PKT_XT_STATSPECIAL) 1772 #define G_CPL_TX_PKT_XT_STATSPECIAL(x) \ 1773 (((x) >> S_CPL_TX_PKT_XT_STATSPECIAL) & M_CPL_TX_PKT_XT_STATSPECIAL) 1774 #define F_CPL_TX_PKT_XT_STATSPECIAL V_CPL_TX_PKT_XT_STATSPECIAL(1U) 1775 1776 #define S_CPL_TX_PKT_XT_INTERFACE 16 1777 #define M_CPL_TX_PKT_XT_INTERFACE 0xf 1778 #define V_CPL_TX_PKT_XT_INTERFACE(x) ((x) << S_CPL_TX_PKT_XT_INTERFACE) 1779 #define G_CPL_TX_PKT_XT_INTERFACE(x) \ 1780 (((x) >> S_CPL_TX_PKT_XT_INTERFACE) & M_CPL_TX_PKT_XT_INTERFACE) 1781 1782 #define S_CPL_TX_PKT_XT_OVLAN 15 1783 #define M_CPL_TX_PKT_XT_OVLAN 0x1 1784 #define V_CPL_TX_PKT_XT_OVLAN(x) ((x) << S_CPL_TX_PKT_XT_OVLAN) 1785 #define G_CPL_TX_PKT_XT_OVLAN(x) \ 1786 (((x) >> S_CPL_TX_PKT_XT_OVLAN) & M_CPL_TX_PKT_XT_OVLAN) 1787 #define F_CPL_TX_PKT_XT_OVLAN V_CPL_TX_PKT_XT_OVLAN(1U) 1788 1789 #define S_CPL_TX_PKT_XT_OVLANIDX 12 1790 #define M_CPL_TX_PKT_XT_OVLANIDX 0x7 1791 #define V_CPL_TX_PKT_XT_OVLANIDX(x) ((x) << S_CPL_TX_PKT_XT_OVLANIDX) 1792 #define G_CPL_TX_PKT_XT_OVLANIDX(x) \ 1793 (((x) >> S_CPL_TX_PKT_XT_OVLANIDX) & M_CPL_TX_PKT_XT_OVLANIDX) 1794 1795 #define S_CPL_TX_PKT_XT_VFVALID 11 1796 #define M_CPL_TX_PKT_XT_VFVALID 0x1 1797 #define V_CPL_TX_PKT_XT_VFVALID(x) ((x) << S_CPL_TX_PKT_XT_VFVALID) 1798 #define G_CPL_TX_PKT_XT_VFVALID(x) \ 1799 (((x) >> S_CPL_TX_PKT_XT_VFVALID) & M_CPL_TX_PKT_XT_VFVALID) 1800 #define F_CPL_TX_PKT_XT_VFVALID V_CPL_TX_PKT_XT_VFVALID(1U) 1801 1802 #define S_CPL_TX_PKT_XT_PF 8 1803 #define M_CPL_TX_PKT_XT_PF 0x7 1804 #define V_CPL_TX_PKT_XT_PF(x) ((x) << S_CPL_TX_PKT_XT_PF) 1805 #define G_CPL_TX_PKT_XT_PF(x) \ 1806 (((x) >> S_CPL_TX_PKT_XT_PF) & M_CPL_TX_PKT_XT_PF) 1807 1808 #define S_CPL_TX_PKT_XT_VF 0 1809 #define M_CPL_TX_PKT_XT_VF 0xff 1810 #define V_CPL_TX_PKT_XT_VF(x) ((x) << S_CPL_TX_PKT_XT_VF) 1811 #define G_CPL_TX_PKT_XT_VF(x) \ 1812 (((x) >> S_CPL_TX_PKT_XT_VF) & M_CPL_TX_PKT_XT_VF) 1813 1814 /* cpl_tx_pkt_xt.core.ctrl1 fields */ 1815 #define S_CPL_TX_PKT_XT_L4CHKDISABLE 31 1816 #define M_CPL_TX_PKT_XT_L4CHKDISABLE 0x1 1817 #define V_CPL_TX_PKT_XT_L4CHKDISABLE(x) ((x) << S_CPL_TX_PKT_XT_L4CHKDISABLE) 1818 #define G_CPL_TX_PKT_XT_L4CHKDISABLE(x) \ 1819 (((x) >> S_CPL_TX_PKT_XT_L4CHKDISABLE) & M_CPL_TX_PKT_XT_L4CHKDISABLE) 1820 #define F_CPL_TX_PKT_XT_L4CHKDISABLE V_CPL_TX_PKT_XT_L4CHKDISABLE(1U) 1821 1822 #define S_CPL_TX_PKT_XT_L3CHKDISABLE 30 1823 #define M_CPL_TX_PKT_XT_L3CHKDISABLE 0x1 1824 #define V_CPL_TX_PKT_XT_L3CHKDISABLE(x) ((x) << S_CPL_TX_PKT_XT_L3CHKDISABLE) 1825 #define G_CPL_TX_PKT_XT_L3CHKDISABLE(x) \ 1826 (((x) >> S_CPL_TX_PKT_XT_L3CHKDISABLE) & M_CPL_TX_PKT_XT_L3CHKDISABLE) 1827 #define F_CPL_TX_PKT_XT_L3CHKDISABLE V_CPL_TX_PKT_XT_L3CHKDISABLE(1U) 1828 1829 #define S_CPL_TX_PKT_XT_OUTL4CHKEN 29 1830 #define M_CPL_TX_PKT_XT_OUTL4CHKEN 0x1 1831 #define V_CPL_TX_PKT_XT_OUTL4CHKEN(x) ((x) << S_CPL_TX_PKT_XT_OUTL4CHKEN) 1832 #define G_CPL_TX_PKT_XT_OUTL4CHKEN(x) \ 1833 (((x) >> S_CPL_TX_PKT_XT_OUTL4CHKEN) & M_CPL_TX_PKT_XT_OUTL4CHKEN) 1834 #define F_CPL_TX_PKT_XT_OUTL4CHKEN V_CPL_TX_PKT_XT_OUTL4CHKEN(1U) 1835 1836 #define S_CPL_TX_PKT_XT_IVLAN 28 1837 #define M_CPL_TX_PKT_XT_IVLAN 0x1 1838 #define V_CPL_TX_PKT_XT_IVLAN(x) ((x) << S_CPL_TX_PKT_XT_IVLAN) 1839 #define G_CPL_TX_PKT_XT_IVLAN(x) \ 1840 (((x) >> S_CPL_TX_PKT_XT_IVLAN) & M_CPL_TX_PKT_XT_IVLAN) 1841 #define F_CPL_TX_PKT_XT_IVLAN V_CPL_TX_PKT_XT_IVLAN(1U) 1842 1843 #define S_CPL_TX_PKT_XT_IVLANTAG 12 1844 #define M_CPL_TX_PKT_XT_IVLANTAG 0xffff 1845 #define V_CPL_TX_PKT_XT_IVLANTAG(x) ((x) << S_CPL_TX_PKT_XT_IVLANTAG) 1846 #define G_CPL_TX_PKT_XT_IVLANTAG(x) \ 1847 (((x) >> S_CPL_TX_PKT_XT_IVLANTAG) & M_CPL_TX_PKT_XT_IVLANTAG) 1848 1849 #define S_CPL_TX_PKT_XT_CHKTYPE 8 1850 #define M_CPL_TX_PKT_XT_CHKTYPE 0xf 1851 #define V_CPL_TX_PKT_XT_CHKTYPE(x) ((x) << S_CPL_TX_PKT_XT_CHKTYPE) 1852 #define G_CPL_TX_PKT_XT_CHKTYPE(x) \ 1853 (((x) >> S_CPL_TX_PKT_XT_CHKTYPE) & M_CPL_TX_PKT_XT_CHKTYPE) 1854 1855 #define S_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI 0 1856 #define M_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI 0xff 1857 #define V_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI(x) \ 1858 ((x) << S_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI) 1859 #define G_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI(x) \ 1860 (((x) >> S_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI) & \ 1861 M_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI) 1862 1863 #define S_CPL_TX_PKT_XT_ETHHDRLEN 0 1864 #define M_CPL_TX_PKT_XT_ETHHDRLEN 0xff 1865 #define V_CPL_TX_PKT_XT_ETHHDRLEN(x) ((x) << S_CPL_TX_PKT_XT_ETHHDRLEN) 1866 #define G_CPL_TX_PKT_XT_ETHHDRLEN(x) \ 1867 (((x) >> S_CPL_TX_PKT_XT_ETHHDRLEN) & M_CPL_TX_PKT_XT_ETHHDRLEN) 1868 1869 #define S_CPL_TX_PKT_XT_ROCECHKINSMODE 6 1870 #define M_CPL_TX_PKT_XT_ROCECHKINSMODE 0x3 1871 #define V_CPL_TX_PKT_XT_ROCECHKINSMODE(x) \ 1872 ((x) << S_CPL_TX_PKT_XT_ROCECHKINSMODE) 1873 #define G_CPL_TX_PKT_XT_ROCECHKINSMODE(x) \ 1874 (((x) >> S_CPL_TX_PKT_XT_ROCECHKINSMODE) & M_CPL_TX_PKT_XT_ROCECHKINSMODE) 1875 1876 #define S_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI 0 1877 #define M_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI 0x3f 1878 #define V_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI(x) \ 1879 ((x) << S_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI) 1880 #define G_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI(x) \ 1881 (((x) >> S_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI) & \ 1882 M_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI) 1883 1884 #define S_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO 30 1885 #define M_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO 0x3 1886 #define V_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO(x) \ 1887 ((x) << S_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO) 1888 #define G_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO(x) \ 1889 (((x) >> S_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO) & \ 1890 M_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO) 1891 1892 /* cpl_tx_pkt_xt.core.ctrl2 fields */ 1893 #define S_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO 30 1894 #define M_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO 0x3 1895 #define V_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO(x) \ 1896 ((x) << S_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO) 1897 #define G_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO(x) \ 1898 (((x) >> S_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO) & \ 1899 M_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO) 1900 1901 #define S_CPL_TX_PKT_XT_CHKSTARTOFFSET 20 1902 #define M_CPL_TX_PKT_XT_CHKSTARTOFFSET 0x3ff 1903 #define V_CPL_TX_PKT_XT_CHKSTARTOFFSET(x) \ 1904 ((x) << S_CPL_TX_PKT_XT_CHKSTARTOFFSET) 1905 #define G_CPL_TX_PKT_XT_CHKSTARTOFFSET(x) \ 1906 (((x) >> S_CPL_TX_PKT_XT_CHKSTARTOFFSET) & M_CPL_TX_PKT_XT_CHKSTARTOFFSET) 1907 1908 #define S_CPL_TX_PKT_XT_IPHDRLEN 20 1909 #define M_CPL_TX_PKT_XT_IPHDRLEN 0xfff 1910 #define V_CPL_TX_PKT_XT_IPHDRLEN(x) ((x) << S_CPL_TX_PKT_XT_IPHDRLEN) 1911 #define G_CPL_TX_PKT_XT_IPHDRLEN(x) \ 1912 (((x) >> S_CPL_TX_PKT_XT_IPHDRLEN) & M_CPL_TX_PKT_XT_IPHDRLEN) 1913 1914 #define S_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET 20 1915 #define M_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET 0x3ff 1916 #define V_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET(x) \ 1917 ((x) << S_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET) 1918 #define G_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET(x) \ 1919 (((x) >> S_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET) & \ 1920 M_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET) 1921 1922 #define S_CPL_TX_PKT_XT_CHKSTOPOFFSET 12 1923 #define M_CPL_TX_PKT_XT_CHKSTOPOFFSET 0xff 1924 #define V_CPL_TX_PKT_XT_CHKSTOPOFFSET(x) \ 1925 ((x) << S_CPL_TX_PKT_XT_CHKSTOPOFFSET) 1926 #define G_CPL_TX_PKT_XT_CHKSTOPOFFSET(x) \ 1927 (((x) >> S_CPL_TX_PKT_XT_CHKSTOPOFFSET) & M_CPL_TX_PKT_XT_CHKSTOPOFFSET) 1928 1929 #define S_CPL_TX_PKT_XT_IPSECIDX 0 1930 #define M_CPL_TX_PKT_XT_IPSECIDX 0xfff 1931 #define V_CPL_TX_PKT_XT_IPSECIDX(x) ((x) << S_CPL_TX_PKT_XT_IPSECIDX) 1932 #define G_CPL_TX_PKT_XT_IPSECIDX(x) \ 1933 (((x) >> S_CPL_TX_PKT_XT_IPSECIDX) & M_CPL_TX_PKT_XT_IPSECIDX) 1934 1935 #define S_CPL_TX_TNL_LSO_BTH_OPCODE 24 1936 #define M_CPL_TX_TNL_LSO_BTH_OPCODE 0xff 1937 #define V_CPL_TX_TNL_LSO_BTH_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_BTH_OPCODE) 1938 #define G_CPL_TX_TNL_LSO_BTH_OPCODE(x) \ 1939 (((x) >> S_CPL_TX_TNL_LSO_BTH_OPCODE) & \ 1940 M_CPL_TX_TNL_LSO_BTH_OPCODE) 1941 1942 #define S_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN 0 1943 #define M_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN 0xffffff 1944 #define V_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN(x) \ 1945 ((x) << S_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN) 1946 #define G_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN(x) \ 1947 (((x) >> S_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN) & \ 1948 M_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN) 1949 1950 #define S_CPL_TX_TNL_LSO_MSS_TVER 8 1951 #define M_CPL_TX_TNL_LSO_MSS_TVER 0xf 1952 #define V_CPL_TX_TNL_LSO_MSS_TVER(x) ((x) << S_CPL_TX_TNL_LSO_MSS_TVER) 1953 #define G_CPL_TX_TNL_LSO_MSS_TVER(x) \ 1954 (((x) >> S_CPL_TX_TNL_LSO_MSS_TVER) & M_CPL_TX_TNL_LSO_MSS_TVER) 1955 1956 #define S_CPL_TX_TNL_LSO_MSS_M 7 1957 #define M_CPL_TX_TNL_LSO_MSS_M 0x1 1958 #define V_CPL_TX_TNL_LSO_MSS_M(x) ((x) << S_CPL_TX_TNL_LSO_MSS_M) 1959 #define G_CPL_TX_TNL_LSO_MSS_M(x) \ 1960 (((x) >> S_CPL_TX_TNL_LSO_MSS_M) & M_CPL_TX_TNL_LSO_MSS_M) 1961 1962 #define S_CPL_TX_TNL_LSO_MSS_PMTU 4 1963 #define M_CPL_TX_TNL_LSO_MSS_PMTU 0x7 1964 #define V_CPL_TX_TNL_LSO_MSS_PMTU(x) ((x) << S_CPL_TX_TNL_LSO_MSS_PMTU) 1965 #define G_CPL_TX_TNL_LSO_MSS_PMTU(x) \ 1966 (((x) >> S_CPL_TX_TNL_LSO_MSS_PMTU) & M_CPL_TX_TNL_LSO_MSS_PMTU) 1967 1968 #define S_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR 3 1969 #define M_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR 0x1 1970 #define V_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR(x) \ 1971 ((x) << S_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR) 1972 #define G_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR(x) \ 1973 (((x) >> S_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR) & M_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR) 1974 1975 #define S_CPL_TX_TNL_LSO_MSS_ACKREQ 1 1976 #define M_CPL_TX_TNL_LSO_MSS_ACKREQ 0x3 1977 #define V_CPL_TX_TNL_LSO_MSS_ACKREQ(x) ((x) << S_CPL_TX_TNL_LSO_MSS_ACKREQ) 1978 #define G_CPL_TX_TNL_LSO_MSS_ACKREQ(x) \ 1979 (((x) >> S_CPL_TX_TNL_LSO_MSS_ACKREQ) & M_CPL_TX_TNL_LSO_MSS_ACKREQ) 1980 1981 #define S_CPL_TX_TNL_LSO_MSS_SE 0 1982 #define M_CPL_TX_TNL_LSO_MSS_SE 0x1 1983 #define V_CPL_TX_TNL_LSO_MSS_SE(x) ((x) << S_CPL_TX_TNL_LSO_MSS_SE) 1984 #define G_CPL_TX_TNL_LSO_MSS_SE(x) \ 1985 (((x) >> S_CPL_TX_TNL_LSO_MSS_SE) & M_CPL_TX_TNL_LSO_MSS_SE) 1986 1987 struct cpl_tx_pkt_lso_core { 1988 __be32 lso_ctrl; 1989 __be16 ipid_ofst; 1990 __be16 mss; 1991 __be32 seqno_offset; 1992 __be32 len; 1993 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1994 }; 1995 1996 struct cpl_tx_pkt_lso { 1997 WR_HDR; 1998 struct cpl_tx_pkt_lso_core c; 1999 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 2000 }; 2001 2002 struct cpl_tx_pkt_ufo_core { 2003 __be16 ethlen; 2004 __be16 iplen; 2005 __be16 udplen; 2006 __be16 mss; 2007 __be32 len; 2008 __be32 r1; 2009 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 2010 }; 2011 2012 struct cpl_tx_pkt_ufo { 2013 WR_HDR; 2014 struct cpl_tx_pkt_ufo_core c; 2015 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 2016 }; 2017 2018 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 2019 #define S_LSO_TCPHDR_LEN 0 2020 #define M_LSO_TCPHDR_LEN 0xF 2021 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 2022 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 2023 2024 #define S_LSO_IPHDR_LEN 4 2025 #define M_LSO_IPHDR_LEN 0xFFF 2026 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 2027 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 2028 2029 #define S_LSO_ETHHDR_LEN 16 2030 #define M_LSO_ETHHDR_LEN 0xF 2031 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 2032 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 2033 2034 #define S_LSO_IPV6 20 2035 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 2036 #define F_LSO_IPV6 V_LSO_IPV6(1U) 2037 2038 #define S_LSO_OFLD_ENCAP 21 2039 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 2040 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 2041 2042 #define S_LSO_LAST_SLICE 22 2043 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 2044 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 2045 2046 #define S_LSO_FIRST_SLICE 23 2047 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 2048 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 2049 2050 #define S_LSO_OPCODE 24 2051 #define M_LSO_OPCODE 0xFF 2052 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 2053 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 2054 2055 #define S_LSO_T5_XFER_SIZE 0 2056 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF 2057 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE) 2058 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE) 2059 2060 /* cpl_tx_pkt_lso_core.mss fields */ 2061 #define S_LSO_MSS 0 2062 #define M_LSO_MSS 0x3FFF 2063 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 2064 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 2065 2066 #define S_LSO_IPID_SPLIT 15 2067 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 2068 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 2069 2070 struct cpl_tx_pkt_fso { 2071 WR_HDR; 2072 __be32 fso_ctrl; 2073 __be16 seqcnt_ofst; 2074 __be16 mtu; 2075 __be32 param_offset; 2076 __be32 len; 2077 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ 2078 }; 2079 2080 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 2081 #define S_FSO_XCHG_CLASS 21 2082 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) 2083 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) 2084 2085 #define S_FSO_INITIATOR 20 2086 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) 2087 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U) 2088 2089 #define S_FSO_FCHDR_LEN 12 2090 #define M_FSO_FCHDR_LEN 0xF 2091 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) 2092 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) 2093 2094 struct cpl_iscsi_hdr_no_rss { 2095 union opcode_tid ot; 2096 __be16 pdu_len_ddp; 2097 __be16 len; 2098 __be32 seq; 2099 __be16 urg; 2100 __u8 rsvd; 2101 __u8 status; 2102 }; 2103 2104 struct cpl_tx_data_iso { 2105 __be32 op_to_scsi; 2106 __u8 reserved1; 2107 __u8 ahs_len; 2108 __be16 mpdu; 2109 __be32 burst_size; 2110 __be32 len; 2111 __be32 reserved2_seglen_offset; 2112 __be32 datasn_offset; 2113 __be32 buffer_offset; 2114 __be32 reserved3; 2115 2116 /* encapsulated CPL_TX_DATA follows here */ 2117 }; 2118 2119 /* cpl_tx_data_iso.op_to_scsi fields */ 2120 #define S_CPL_TX_DATA_ISO_OP 24 2121 #define M_CPL_TX_DATA_ISO_OP 0xff 2122 #define V_CPL_TX_DATA_ISO_OP(x) ((x) << S_CPL_TX_DATA_ISO_OP) 2123 #define G_CPL_TX_DATA_ISO_OP(x) \ 2124 (((x) >> S_CPL_TX_DATA_ISO_OP) & M_CPL_TX_DATA_ISO_OP) 2125 2126 #define S_CPL_TX_DATA_ISO_FIRST 23 2127 #define M_CPL_TX_DATA_ISO_FIRST 0x1 2128 #define V_CPL_TX_DATA_ISO_FIRST(x) ((x) << S_CPL_TX_DATA_ISO_FIRST) 2129 #define G_CPL_TX_DATA_ISO_FIRST(x) \ 2130 (((x) >> S_CPL_TX_DATA_ISO_FIRST) & M_CPL_TX_DATA_ISO_FIRST) 2131 #define F_CPL_TX_DATA_ISO_FIRST V_CPL_TX_DATA_ISO_FIRST(1U) 2132 2133 #define S_CPL_TX_DATA_ISO_LAST 22 2134 #define M_CPL_TX_DATA_ISO_LAST 0x1 2135 #define V_CPL_TX_DATA_ISO_LAST(x) ((x) << S_CPL_TX_DATA_ISO_LAST) 2136 #define G_CPL_TX_DATA_ISO_LAST(x) \ 2137 (((x) >> S_CPL_TX_DATA_ISO_LAST) & M_CPL_TX_DATA_ISO_LAST) 2138 #define F_CPL_TX_DATA_ISO_LAST V_CPL_TX_DATA_ISO_LAST(1U) 2139 2140 #define S_CPL_TX_DATA_ISO_CPLHDRLEN 21 2141 #define M_CPL_TX_DATA_ISO_CPLHDRLEN 0x1 2142 #define V_CPL_TX_DATA_ISO_CPLHDRLEN(x) ((x) << S_CPL_TX_DATA_ISO_CPLHDRLEN) 2143 #define G_CPL_TX_DATA_ISO_CPLHDRLEN(x) \ 2144 (((x) >> S_CPL_TX_DATA_ISO_CPLHDRLEN) & M_CPL_TX_DATA_ISO_CPLHDRLEN) 2145 #define F_CPL_TX_DATA_ISO_CPLHDRLEN V_CPL_TX_DATA_ISO_CPLHDRLEN(1U) 2146 2147 #define S_CPL_TX_DATA_ISO_HDRCRC 20 2148 #define M_CPL_TX_DATA_ISO_HDRCRC 0x1 2149 #define V_CPL_TX_DATA_ISO_HDRCRC(x) ((x) << S_CPL_TX_DATA_ISO_HDRCRC) 2150 #define G_CPL_TX_DATA_ISO_HDRCRC(x) \ 2151 (((x) >> S_CPL_TX_DATA_ISO_HDRCRC) & M_CPL_TX_DATA_ISO_HDRCRC) 2152 #define F_CPL_TX_DATA_ISO_HDRCRC V_CPL_TX_DATA_ISO_HDRCRC(1U) 2153 2154 #define S_CPL_TX_DATA_ISO_PLDCRC 19 2155 #define M_CPL_TX_DATA_ISO_PLDCRC 0x1 2156 #define V_CPL_TX_DATA_ISO_PLDCRC(x) ((x) << S_CPL_TX_DATA_ISO_PLDCRC) 2157 #define G_CPL_TX_DATA_ISO_PLDCRC(x) \ 2158 (((x) >> S_CPL_TX_DATA_ISO_PLDCRC) & M_CPL_TX_DATA_ISO_PLDCRC) 2159 #define F_CPL_TX_DATA_ISO_PLDCRC V_CPL_TX_DATA_ISO_PLDCRC(1U) 2160 2161 #define S_CPL_TX_DATA_ISO_IMMEDIATE 18 2162 #define M_CPL_TX_DATA_ISO_IMMEDIATE 0x1 2163 #define V_CPL_TX_DATA_ISO_IMMEDIATE(x) ((x) << S_CPL_TX_DATA_ISO_IMMEDIATE) 2164 #define G_CPL_TX_DATA_ISO_IMMEDIATE(x) \ 2165 (((x) >> S_CPL_TX_DATA_ISO_IMMEDIATE) & M_CPL_TX_DATA_ISO_IMMEDIATE) 2166 #define F_CPL_TX_DATA_ISO_IMMEDIATE V_CPL_TX_DATA_ISO_IMMEDIATE(1U) 2167 2168 #define S_CPL_TX_DATA_ISO_SCSI 16 2169 #define M_CPL_TX_DATA_ISO_SCSI 0x3 2170 #define V_CPL_TX_DATA_ISO_SCSI(x) ((x) << S_CPL_TX_DATA_ISO_SCSI) 2171 #define G_CPL_TX_DATA_ISO_SCSI(x) \ 2172 (((x) >> S_CPL_TX_DATA_ISO_SCSI) & M_CPL_TX_DATA_ISO_SCSI) 2173 2174 /* cpl_tx_data_iso.reserved2_seglen_offset fields */ 2175 #define S_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0 2176 #define M_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0xffffff 2177 #define V_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 2178 ((x) << S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 2179 #define G_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 2180 (((x) >> S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) & \ 2181 M_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 2182 2183 struct cpl_t7_tx_data_iso { 2184 __be32 op_to_scsi; 2185 __u8 nvme_tcp_pkd; 2186 __u8 ahs; 2187 __be16 mpdu; 2188 __be32 burst; 2189 __be32 size; 2190 __be32 num_pi_bytes_seglen_offset; 2191 __be32 datasn_offset; 2192 __be32 buffer_offset; 2193 __be32 reserved3; 2194 }; 2195 2196 #define S_CPL_T7_TX_DATA_ISO_OPCODE 24 2197 #define M_CPL_T7_TX_DATA_ISO_OPCODE 0xff 2198 #define V_CPL_T7_TX_DATA_ISO_OPCODE(x) ((x) << S_CPL_T7_TX_DATA_ISO_OPCODE) 2199 #define G_CPL_T7_TX_DATA_ISO_OPCODE(x) \ 2200 (((x) >> S_CPL_T7_TX_DATA_ISO_OPCODE) & M_CPL_T7_TX_DATA_ISO_OPCODE) 2201 2202 #define S_CPL_T7_TX_DATA_ISO_FIRST 23 2203 #define M_CPL_T7_TX_DATA_ISO_FIRST 0x1 2204 #define V_CPL_T7_TX_DATA_ISO_FIRST(x) ((x) << S_CPL_T7_TX_DATA_ISO_FIRST) 2205 #define G_CPL_T7_TX_DATA_ISO_FIRST(x) \ 2206 (((x) >> S_CPL_T7_TX_DATA_ISO_FIRST) & M_CPL_T7_TX_DATA_ISO_FIRST) 2207 #define F_CPL_T7_TX_DATA_ISO_FIRST V_CPL_T7_TX_DATA_ISO_FIRST(1U) 2208 2209 #define S_CPL_T7_TX_DATA_ISO_LAST 22 2210 #define M_CPL_T7_TX_DATA_ISO_LAST 0x1 2211 #define V_CPL_T7_TX_DATA_ISO_LAST(x) ((x) << S_CPL_T7_TX_DATA_ISO_LAST) 2212 #define G_CPL_T7_TX_DATA_ISO_LAST(x) \ 2213 (((x) >> S_CPL_T7_TX_DATA_ISO_LAST) & M_CPL_T7_TX_DATA_ISO_LAST) 2214 #define F_CPL_T7_TX_DATA_ISO_LAST V_CPL_T7_TX_DATA_ISO_LAST(1U) 2215 2216 #define S_CPL_T7_TX_DATA_ISO_CPLHDRLEN 21 2217 #define M_CPL_T7_TX_DATA_ISO_CPLHDRLEN 0x1 2218 #define V_CPL_T7_TX_DATA_ISO_CPLHDRLEN(x) \ 2219 ((x) << S_CPL_T7_TX_DATA_ISO_CPLHDRLEN) 2220 #define G_CPL_T7_TX_DATA_ISO_CPLHDRLEN(x) \ 2221 (((x) >> S_CPL_T7_TX_DATA_ISO_CPLHDRLEN) & M_CPL_T7_TX_DATA_ISO_CPLHDRLEN) 2222 #define F_CPL_T7_TX_DATA_ISO_CPLHDRLEN V_CPL_T7_TX_DATA_ISO_CPLHDRLEN(1U) 2223 2224 #define S_CPL_T7_TX_DATA_ISO_HDRCRC 20 2225 #define M_CPL_T7_TX_DATA_ISO_HDRCRC 0x1 2226 #define V_CPL_T7_TX_DATA_ISO_HDRCRC(x) ((x) << S_CPL_T7_TX_DATA_ISO_HDRCRC) 2227 #define G_CPL_T7_TX_DATA_ISO_HDRCRC(x) \ 2228 (((x) >> S_CPL_T7_TX_DATA_ISO_HDRCRC) & M_CPL_T7_TX_DATA_ISO_HDRCRC) 2229 #define F_CPL_T7_TX_DATA_ISO_HDRCRC V_CPL_T7_TX_DATA_ISO_HDRCRC(1U) 2230 2231 #define S_CPL_T7_TX_DATA_ISO_PLDCRC 19 2232 #define M_CPL_T7_TX_DATA_ISO_PLDCRC 0x1 2233 #define V_CPL_T7_TX_DATA_ISO_PLDCRC(x) ((x) << S_CPL_T7_TX_DATA_ISO_PLDCRC) 2234 #define G_CPL_T7_TX_DATA_ISO_PLDCRC(x) \ 2235 (((x) >> S_CPL_T7_TX_DATA_ISO_PLDCRC) & M_CPL_T7_TX_DATA_ISO_PLDCRC) 2236 #define F_CPL_T7_TX_DATA_ISO_PLDCRC V_CPL_T7_TX_DATA_ISO_PLDCRC(1U) 2237 2238 #define S_CPL_T7_TX_DATA_ISO_IMMEDIATE 18 2239 #define M_CPL_T7_TX_DATA_ISO_IMMEDIATE 0x1 2240 #define V_CPL_T7_TX_DATA_ISO_IMMEDIATE(x) \ 2241 ((x) << S_CPL_T7_TX_DATA_ISO_IMMEDIATE) 2242 #define G_CPL_T7_TX_DATA_ISO_IMMEDIATE(x) \ 2243 (((x) >> S_CPL_T7_TX_DATA_ISO_IMMEDIATE) & M_CPL_T7_TX_DATA_ISO_IMMEDIATE) 2244 #define F_CPL_T7_TX_DATA_ISO_IMMEDIATE \ 2245 V_CPL_T7_TX_DATA_ISO_IMMEDIATE(1U) 2246 2247 #define S_CPL_T7_TX_DATA_ISO_SCSI 16 2248 #define M_CPL_T7_TX_DATA_ISO_SCSI 0x3 2249 #define V_CPL_T7_TX_DATA_ISO_SCSI(x) ((x) << S_CPL_T7_TX_DATA_ISO_SCSI) 2250 #define G_CPL_T7_TX_DATA_ISO_SCSI(x) \ 2251 (((x) >> S_CPL_T7_TX_DATA_ISO_SCSI) & M_CPL_T7_TX_DATA_ISO_SCSI) 2252 2253 #define S_CPL_T7_TX_DATA_ISO_NVME_TCP 0 2254 #define M_CPL_T7_TX_DATA_ISO_NVME_TCP 0x1 2255 #define V_CPL_T7_TX_DATA_ISO_NVME_TCP(x) \ 2256 ((x) << S_CPL_T7_TX_DATA_ISO_NVME_TCP) 2257 #define G_CPL_T7_TX_DATA_ISO_NVME_TCP(x) \ 2258 (((x) >> S_CPL_T7_TX_DATA_ISO_NVME_TCP) & M_CPL_T7_TX_DATA_ISO_NVME_TCP) 2259 #define F_CPL_T7_TX_DATA_ISO_NVME_TCP \ 2260 V_CPL_T7_TX_DATA_ISO_NVME_TCP(1U) 2261 2262 #define S_CPL_T7_TX_DATA_ISO_NUMPIBYTES 24 2263 #define M_CPL_T7_TX_DATA_ISO_NUMPIBYTES 0xff 2264 #define V_CPL_T7_TX_DATA_ISO_NUMPIBYTES(x) \ 2265 ((x) << S_CPL_T7_TX_DATA_ISO_NUMPIBYTES) 2266 #define G_CPL_T7_TX_DATA_ISO_NUMPIBYTES(x) \ 2267 (((x) >> S_CPL_T7_TX_DATA_ISO_NUMPIBYTES) & M_CPL_T7_TX_DATA_ISO_NUMPIBYTES) 2268 2269 #define S_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET 0 2270 #define M_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET 0xffffff 2271 #define V_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET(x) \ 2272 ((x) << S_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET) 2273 #define G_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET(x) \ 2274 (((x) >> S_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET) & \ 2275 M_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET) 2276 2277 struct cpl_iscsi_hdr { 2278 RSS_HDR 2279 union opcode_tid ot; 2280 __be16 pdu_len_ddp; 2281 __be16 len; 2282 __be32 seq; 2283 __be16 urg; 2284 __u8 rsvd; 2285 __u8 status; 2286 }; 2287 2288 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 2289 #define S_ISCSI_PDU_LEN 0 2290 #define M_ISCSI_PDU_LEN 0x7FFF 2291 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 2292 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 2293 2294 #define S_ISCSI_DDP 15 2295 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 2296 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 2297 2298 struct cpl_iscsi_data { 2299 RSS_HDR 2300 union opcode_tid ot; 2301 __u8 rsvd0[2]; 2302 __be16 len; 2303 __be32 seq; 2304 __be16 urg; 2305 __u8 rsvd1; 2306 __u8 status; 2307 }; 2308 2309 struct cpl_rx_data { 2310 RSS_HDR 2311 union opcode_tid ot; 2312 __be16 rsvd; 2313 __be16 len; 2314 __be32 seq; 2315 __be16 urg; 2316 #if defined(__LITTLE_ENDIAN_BITFIELD) 2317 __u8 dack_mode:2; 2318 __u8 psh:1; 2319 __u8 heartbeat:1; 2320 __u8 ddp_off:1; 2321 __u8 :3; 2322 #else 2323 __u8 :3; 2324 __u8 ddp_off:1; 2325 __u8 heartbeat:1; 2326 __u8 psh:1; 2327 __u8 dack_mode:2; 2328 #endif 2329 __u8 status; 2330 }; 2331 2332 struct cpl_fcoe_hdr { 2333 RSS_HDR 2334 union opcode_tid ot; 2335 __be16 oxid; 2336 __be16 len; 2337 __be32 rctl_fctl; 2338 __u8 cs_ctl; 2339 __u8 df_ctl; 2340 __u8 sof; 2341 __u8 eof; 2342 __be16 seq_cnt; 2343 __u8 seq_id; 2344 __u8 type; 2345 __be32 param; 2346 }; 2347 2348 /* cpl_fcoe_hdr.rctl_fctl fields */ 2349 #define S_FCOE_FCHDR_RCTL 24 2350 #define M_FCOE_FCHDR_RCTL 0xff 2351 #define V_FCOE_FCHDR_RCTL(x) ((x) << S_FCOE_FCHDR_RCTL) 2352 #define G_FCOE_FCHDR_RCTL(x) \ 2353 (((x) >> S_FCOE_FCHDR_RCTL) & M_FCOE_FCHDR_RCTL) 2354 2355 #define S_FCOE_FCHDR_FCTL 0 2356 #define M_FCOE_FCHDR_FCTL 0xffffff 2357 #define V_FCOE_FCHDR_FCTL(x) ((x) << S_FCOE_FCHDR_FCTL) 2358 #define G_FCOE_FCHDR_FCTL(x) \ 2359 (((x) >> S_FCOE_FCHDR_FCTL) & M_FCOE_FCHDR_FCTL) 2360 2361 struct cpl_fcoe_data { 2362 RSS_HDR 2363 union opcode_tid ot; 2364 __u8 rsvd0[2]; 2365 __be16 len; 2366 __be32 seq; 2367 __u8 rsvd1[3]; 2368 __u8 status; 2369 }; 2370 2371 struct cpl_rx_urg_notify { 2372 RSS_HDR 2373 union opcode_tid ot; 2374 __be32 seq; 2375 }; 2376 2377 struct cpl_rx_urg_pkt { 2378 RSS_HDR 2379 union opcode_tid ot; 2380 __be16 rsvd; 2381 __be16 len; 2382 }; 2383 2384 struct cpl_rx_data_ack { 2385 WR_HDR; 2386 union opcode_tid ot; 2387 __be32 credit_dack; 2388 }; 2389 2390 struct cpl_rx_data_ack_core { 2391 union opcode_tid ot; 2392 __be32 credit_dack; 2393 }; 2394 2395 /* cpl_rx_data_ack.ack_seq fields */ 2396 #define S_RX_CREDITS 0 2397 #define M_RX_CREDITS 0x3FFFFFF 2398 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 2399 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 2400 2401 #define S_RX_MODULATE_TX 26 2402 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 2403 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 2404 2405 #define S_RX_MODULATE_RX 27 2406 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 2407 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 2408 2409 #define S_RX_FORCE_ACK 28 2410 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 2411 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 2412 2413 #define S_RX_DACK_MODE 29 2414 #define M_RX_DACK_MODE 0x3 2415 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 2416 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 2417 2418 #define S_RX_DACK_CHANGE 31 2419 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 2420 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 2421 2422 struct cpl_rx_ddp_complete { 2423 RSS_HDR 2424 union opcode_tid ot; 2425 __be32 ddp_report; 2426 __be32 rcv_nxt; 2427 __be32 rsvd; 2428 }; 2429 2430 struct cpl_rx_data_ddp { 2431 RSS_HDR 2432 union opcode_tid ot; 2433 __be16 urg; 2434 __be16 len; 2435 __be32 seq; 2436 union { 2437 __be32 nxt_seq; 2438 __be32 ddp_report; 2439 } u; 2440 __be32 ulp_crc; 2441 __be32 ddpvld; 2442 }; 2443 2444 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 2445 2446 struct cpl_rx_fcoe_ddp { 2447 RSS_HDR 2448 union opcode_tid ot; 2449 __be16 rsvd; 2450 __be16 len; 2451 __be32 seq; 2452 __be32 ddp_report; 2453 __be32 ulp_crc; 2454 __be32 ddpvld; 2455 }; 2456 2457 struct cpl_rx_data_dif { 2458 RSS_HDR 2459 union opcode_tid ot; 2460 __be16 ddp_len; 2461 __be16 msg_len; 2462 __be32 seq; 2463 union { 2464 __be32 nxt_seq; 2465 __be32 ddp_report; 2466 } u; 2467 __be32 err_vec; 2468 __be32 ddpvld; 2469 }; 2470 2471 struct cpl_rx_iscsi_dif { 2472 RSS_HDR 2473 union opcode_tid ot; 2474 __be16 ddp_len; 2475 __be16 msg_len; 2476 __be32 seq; 2477 union { 2478 __be32 nxt_seq; 2479 __be32 ddp_report; 2480 } u; 2481 __be32 ulp_crc; 2482 __be32 ddpvld; 2483 __u8 rsvd0[8]; 2484 __be32 err_vec; 2485 __u8 rsvd1[4]; 2486 }; 2487 2488 struct cpl_rx_iscsi_cmp { 2489 RSS_HDR 2490 union opcode_tid ot; 2491 __be16 pdu_len_ddp; 2492 __be16 len; 2493 __be32 seq; 2494 __be16 urg; 2495 __u8 rsvd; 2496 __u8 status; 2497 __be32 ulp_crc; 2498 __be32 ddpvld; 2499 }; 2500 2501 struct cpl_rx_fcoe_dif { 2502 RSS_HDR 2503 union opcode_tid ot; 2504 __be16 ddp_len; 2505 __be16 msg_len; 2506 __be32 seq; 2507 __be32 ddp_report; 2508 __be32 err_vec; 2509 __be32 ddpvld; 2510 }; 2511 2512 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ 2513 #define S_DDP_VALID 15 2514 #define M_DDP_VALID 0x1FFFF 2515 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 2516 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 2517 2518 #define S_DDP_PPOD_MISMATCH 15 2519 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 2520 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 2521 2522 #define S_DDP_PDU 16 2523 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 2524 #define F_DDP_PDU V_DDP_PDU(1U) 2525 2526 #define S_DDP_LLIMIT_ERR 17 2527 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 2528 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 2529 2530 #define S_DDP_PPOD_PARITY_ERR 18 2531 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 2532 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 2533 2534 #define S_DDP_PADDING_ERR 19 2535 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 2536 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 2537 2538 #define S_DDP_HDRCRC_ERR 20 2539 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 2540 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 2541 2542 #define S_DDP_DATACRC_ERR 21 2543 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 2544 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 2545 2546 #define S_DDP_INVALID_TAG 22 2547 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 2548 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 2549 2550 #define S_DDP_ULIMIT_ERR 23 2551 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 2552 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 2553 2554 #define S_DDP_OFFSET_ERR 24 2555 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 2556 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 2557 2558 #define S_DDP_COLOR_ERR 25 2559 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 2560 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 2561 2562 #define S_DDP_TID_MISMATCH 26 2563 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 2564 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 2565 2566 #define S_DDP_INVALID_PPOD 27 2567 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 2568 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 2569 2570 #define S_DDP_ULP_MODE 28 2571 #define M_DDP_ULP_MODE 0xF 2572 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 2573 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 2574 2575 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ 2576 #define S_DDP_OFFSET 0 2577 #define M_DDP_OFFSET 0xFFFFFF 2578 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 2579 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 2580 2581 #define S_DDP_DACK_MODE 24 2582 #define M_DDP_DACK_MODE 0x3 2583 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 2584 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 2585 2586 #define S_DDP_BUF_IDX 26 2587 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 2588 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 2589 2590 #define S_DDP_URG 27 2591 #define V_DDP_URG(x) ((x) << S_DDP_URG) 2592 #define F_DDP_URG V_DDP_URG(1U) 2593 2594 #define S_DDP_PSH 28 2595 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 2596 #define F_DDP_PSH V_DDP_PSH(1U) 2597 2598 #define S_DDP_BUF_COMPLETE 29 2599 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 2600 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 2601 2602 #define S_DDP_BUF_TIMED_OUT 30 2603 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 2604 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 2605 2606 #define S_DDP_INV 31 2607 #define V_DDP_INV(x) ((x) << S_DDP_INV) 2608 #define F_DDP_INV V_DDP_INV(1U) 2609 2610 struct cpl_rx_pkt { 2611 RSS_HDR 2612 __u8 opcode; 2613 #if defined(__LITTLE_ENDIAN_BITFIELD) 2614 __u8 iff:4; 2615 __u8 csum_calc:1; 2616 __u8 ipmi_pkt:1; 2617 __u8 vlan_ex:1; 2618 __u8 ip_frag:1; 2619 #else 2620 __u8 ip_frag:1; 2621 __u8 vlan_ex:1; 2622 __u8 ipmi_pkt:1; 2623 __u8 csum_calc:1; 2624 __u8 iff:4; 2625 #endif 2626 __be16 csum; 2627 __be16 vlan; 2628 __be16 len; 2629 __be32 l2info; 2630 __be16 hdr_len; 2631 __be16 err_vec; 2632 }; 2633 2634 /* rx_pkt.l2info fields */ 2635 #define S_RX_ETHHDR_LEN 0 2636 #define M_RX_ETHHDR_LEN 0x1F 2637 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 2638 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 2639 2640 #define S_RX_T5_ETHHDR_LEN 0 2641 #define M_RX_T5_ETHHDR_LEN 0x3F 2642 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 2643 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 2644 2645 #define M_RX_T6_ETHHDR_LEN 0xFF 2646 #define G_RX_T6_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_T6_ETHHDR_LEN) 2647 2648 #define S_RX_PKTYPE 5 2649 #define M_RX_PKTYPE 0x7 2650 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 2651 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 2652 2653 #define S_RX_T5_DATYPE 6 2654 #define M_RX_T5_DATYPE 0x3 2655 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) 2656 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) 2657 2658 #define S_RX_MACIDX 8 2659 #define M_RX_MACIDX 0x1FF 2660 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 2661 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 2662 2663 #define S_RX_T5_PKTYPE 17 2664 #define M_RX_T5_PKTYPE 0x7 2665 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) 2666 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) 2667 2668 #define S_RX_DATYPE 18 2669 #define M_RX_DATYPE 0x3 2670 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 2671 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 2672 2673 #define S_RXF_PSH 20 2674 #define V_RXF_PSH(x) ((x) << S_RXF_PSH) 2675 #define F_RXF_PSH V_RXF_PSH(1U) 2676 2677 #define S_RXF_SYN 21 2678 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 2679 #define F_RXF_SYN V_RXF_SYN(1U) 2680 2681 #define S_RXF_UDP 22 2682 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 2683 #define F_RXF_UDP V_RXF_UDP(1U) 2684 2685 #define S_RXF_TCP 23 2686 #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 2687 #define F_RXF_TCP V_RXF_TCP(1U) 2688 2689 #define S_RXF_IP 24 2690 #define V_RXF_IP(x) ((x) << S_RXF_IP) 2691 #define F_RXF_IP V_RXF_IP(1U) 2692 2693 #define S_RXF_IP6 25 2694 #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 2695 #define F_RXF_IP6 V_RXF_IP6(1U) 2696 2697 #define S_RXF_SYN_COOKIE 26 2698 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 2699 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 2700 2701 #define S_RXF_FCOE 26 2702 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 2703 #define F_RXF_FCOE V_RXF_FCOE(1U) 2704 2705 #define S_RXF_LRO 27 2706 #define V_RXF_LRO(x) ((x) << S_RXF_LRO) 2707 #define F_RXF_LRO V_RXF_LRO(1U) 2708 2709 #define S_RX_CHAN 28 2710 #define M_RX_CHAN 0xF 2711 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 2712 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 2713 2714 /* rx_pkt.hdr_len fields */ 2715 #define S_RX_TCPHDR_LEN 0 2716 #define M_RX_TCPHDR_LEN 0x3F 2717 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 2718 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 2719 2720 #define S_RX_IPHDR_LEN 6 2721 #define M_RX_IPHDR_LEN 0x3FF 2722 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 2723 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 2724 2725 /* rx_pkt.err_vec fields */ 2726 #define S_RXERR_OR 0 2727 #define V_RXERR_OR(x) ((x) << S_RXERR_OR) 2728 #define F_RXERR_OR V_RXERR_OR(1U) 2729 2730 #define S_RXERR_MAC 1 2731 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 2732 #define F_RXERR_MAC V_RXERR_MAC(1U) 2733 2734 #define S_RXERR_IPVERS 2 2735 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 2736 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 2737 2738 #define S_RXERR_FRAG 3 2739 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 2740 #define F_RXERR_FRAG V_RXERR_FRAG(1U) 2741 2742 #define S_RXERR_ATTACK 4 2743 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 2744 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 2745 2746 #define S_RXERR_ETHHDR_LEN 5 2747 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 2748 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 2749 2750 #define S_RXERR_IPHDR_LEN 6 2751 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 2752 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 2753 2754 #define S_RXERR_TCPHDR_LEN 7 2755 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 2756 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 2757 2758 #define S_RXERR_PKT_LEN 8 2759 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 2760 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 2761 2762 #define S_RXERR_TCP_OPT 9 2763 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 2764 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 2765 2766 #define S_RXERR_IPCSUM 12 2767 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 2768 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 2769 2770 #define S_RXERR_CSUM 13 2771 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 2772 #define F_RXERR_CSUM V_RXERR_CSUM(1U) 2773 2774 #define S_RXERR_PING 14 2775 #define V_RXERR_PING(x) ((x) << S_RXERR_PING) 2776 #define F_RXERR_PING V_RXERR_PING(1U) 2777 2778 /* In T6, rx_pkt.err_vec indicates 2779 * RxError Error vector (16b) or 2780 * Encapsulating header length (8b), 2781 * Outer encapsulation type (2b) and 2782 * compressed error vector (6b) if CRxPktEnc is 2783 * enabled in TP_OUT_CONFIG 2784 */ 2785 2786 #define S_T6_COMPR_RXERR_VEC 0 2787 #define M_T6_COMPR_RXERR_VEC 0x3F 2788 #define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC) 2789 #define G_T6_COMPR_RXERR_VEC(x) \ 2790 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC) 2791 2792 #define S_T6_COMPR_RXERR_MAC 0 2793 #define V_T6_COMPR_RXERR_MAC(x) ((x) << S_T6_COMPR_RXERR_MAC) 2794 #define F_T6_COMPR_RXERR_MAC V_T6_COMPR_RXERR_MAC(1U) 2795 2796 /* Logical OR of RX_ERROR_PKT_LEN, RX_ERROR_TCP_HDR_LEN 2797 * RX_ERROR_IP_HDR_LEN, RX_ERROR_ETH_HDR_LEN 2798 */ 2799 #define S_T6_COMPR_RXERR_LEN 1 2800 #define V_T6_COMPR_RXERR_LEN(x) ((x) << S_T6_COMPR_RXERR_LEN) 2801 #define F_T6_COMPR_RXERR_LEN V_COMPR_T6_RXERR_LEN(1U) 2802 2803 #define S_T6_COMPR_RXERR_TCP_OPT 2 2804 #define V_T6_COMPR_RXERR_TCP_OPT(x) ((x) << S_T6_COMPR_RXERR_TCP_OPT) 2805 #define F_T6_COMPR_RXERR_TCP_OPT V_T6_COMPR_RXERR_TCP_OPT(1U) 2806 2807 #define S_T6_COMPR_RXERR_IPV6_EXT 3 2808 #define V_T6_COMPR_RXERR_IPV6_EXT(x) ((x) << S_T6_COMPR_RXERR_IPV6_EXT) 2809 #define F_T6_COMPR_RXERR_IPV6_EXT V_T6_COMPR_RXERR_IPV6_EXT(1U) 2810 2811 /* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */ 2812 #define S_T6_COMPR_RXERR_SUM 4 2813 #define V_T6_COMPR_RXERR_SUM(x) ((x) << S_T6_COMPR_RXERR_SUM) 2814 #define F_T6_COMPR_RXERR_SUM V_T6_COMPR_RXERR_SUM(1U) 2815 2816 /* Logical OR of RX_ERROR_FPMA, RX_ERROR_PING_DROP, 2817 * RX_ERROR_ATTACK, RX_ERROR_FRAG,RX_ERROR_IPVERSION 2818 */ 2819 #define S_T6_COMPR_RXERR_MISC 5 2820 #define V_T6_COMPR_RXERR_MISC(x) ((x) << S_T6_COMPR_RXERR_MISC) 2821 #define F_T6_COMPR_RXERR_MISC V_T6_COMPR_RXERR_MISC(1U) 2822 2823 #define S_T6_RX_TNL_TYPE 6 2824 #define M_T6_RX_TNL_TYPE 0x3 2825 #define V_T6_RX_TNL_TYPE(x) ((x) << S_T6_RX_TNL_TYPE) 2826 #define G_T6_RX_TNL_TYPE(x) (((x) >> S_T6_RX_TNL_TYPE) & M_T6_RX_TNL_TYPE) 2827 2828 #define RX_PKT_TNL_TYPE_NVGRE 1 2829 #define RX_PKT_TNL_TYPE_VXLAN 2 2830 #define RX_PKT_TNL_TYPE_GENEVE 3 2831 2832 #define S_T6_RX_TNLHDR_LEN 8 2833 #define M_T6_RX_TNLHDR_LEN 0xFF 2834 #define V_T6_RX_TNLHDR_LEN(x) ((x) << S_T6_RX_TNLHDR_LEN) 2835 #define G_T6_RX_TNLHDR_LEN(x) (((x) >> S_T6_RX_TNLHDR_LEN) & M_T6_RX_TNLHDR_LEN) 2836 2837 struct cpl_trace_pkt { 2838 RSS_HDR 2839 __u8 opcode; 2840 __u8 intf; 2841 #if defined(__LITTLE_ENDIAN_BITFIELD) 2842 __u8 runt:4; 2843 __u8 filter_hit:4; 2844 __u8 :6; 2845 __u8 err:1; 2846 __u8 trunc:1; 2847 #else 2848 __u8 filter_hit:4; 2849 __u8 runt:4; 2850 __u8 trunc:1; 2851 __u8 err:1; 2852 __u8 :6; 2853 #endif 2854 __be16 rsvd; 2855 __be16 len; 2856 __be64 tstamp; 2857 }; 2858 2859 struct cpl_t5_trace_pkt { 2860 RSS_HDR 2861 __u8 opcode; 2862 __u8 intf; 2863 #if defined(__LITTLE_ENDIAN_BITFIELD) 2864 __u8 runt:4; 2865 __u8 filter_hit:4; 2866 __u8 :6; 2867 __u8 err:1; 2868 __u8 trunc:1; 2869 #else 2870 __u8 filter_hit:4; 2871 __u8 runt:4; 2872 __u8 trunc:1; 2873 __u8 err:1; 2874 __u8 :6; 2875 #endif 2876 __be16 rsvd; 2877 __be16 len; 2878 __be64 tstamp; 2879 __be64 rsvd1; 2880 }; 2881 2882 struct cpl_rte_delete_req { 2883 WR_HDR; 2884 union opcode_tid ot; 2885 __be32 params; 2886 }; 2887 2888 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 2889 #define S_RTE_REQ_LUT_IX 8 2890 #define M_RTE_REQ_LUT_IX 0x7FF 2891 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 2892 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 2893 2894 #define S_RTE_REQ_LUT_BASE 19 2895 #define M_RTE_REQ_LUT_BASE 0x7FF 2896 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 2897 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 2898 2899 #define S_RTE_READ_REQ_SELECT 31 2900 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 2901 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 2902 2903 struct cpl_rte_delete_rpl { 2904 RSS_HDR 2905 union opcode_tid ot; 2906 __u8 status; 2907 __u8 rsvd[3]; 2908 }; 2909 2910 struct cpl_rte_write_req { 2911 WR_HDR; 2912 union opcode_tid ot; 2913 __u32 write_sel; 2914 __be32 lut_params; 2915 __be32 l2t_idx; 2916 __be32 netmask; 2917 __be32 faddr; 2918 }; 2919 2920 /* cpl_rte_write_req.write_sel fields */ 2921 #define S_RTE_WR_L2TIDX 31 2922 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 2923 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 2924 2925 #define S_RTE_WR_FADDR 30 2926 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 2927 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 2928 2929 /* cpl_rte_write_req.lut_params fields */ 2930 #define S_RTE_WR_LUT_IX 10 2931 #define M_RTE_WR_LUT_IX 0x7FF 2932 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 2933 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 2934 2935 #define S_RTE_WR_LUT_BASE 21 2936 #define M_RTE_WR_LUT_BASE 0x7FF 2937 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 2938 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 2939 2940 struct cpl_rte_write_rpl { 2941 RSS_HDR 2942 union opcode_tid ot; 2943 __u8 status; 2944 __u8 rsvd[3]; 2945 }; 2946 2947 struct cpl_rte_read_req { 2948 WR_HDR; 2949 union opcode_tid ot; 2950 __be32 params; 2951 }; 2952 2953 struct cpl_rte_read_rpl { 2954 RSS_HDR 2955 union opcode_tid ot; 2956 __u8 status; 2957 __u8 rsvd; 2958 __be16 l2t_idx; 2959 #if defined(__LITTLE_ENDIAN_BITFIELD) 2960 __u32 :30; 2961 __u32 select:1; 2962 #else 2963 __u32 select:1; 2964 __u32 :30; 2965 #endif 2966 __be32 addr; 2967 }; 2968 2969 struct cpl_l2t_write_req { 2970 WR_HDR; 2971 union opcode_tid ot; 2972 __be16 params; 2973 __be16 l2t_idx; 2974 __be16 vlan; 2975 __u8 dst_mac[6]; 2976 }; 2977 2978 /* cpl_l2t_write_req.params fields */ 2979 #define S_L2T_W_INFO 2 2980 #define M_L2T_W_INFO 0x3F 2981 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 2982 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 2983 2984 #define S_L2T_W_PORT 8 2985 #define M_L2T_W_PORT 0x3 2986 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 2987 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 2988 2989 #define S_L2T_W_LPBK 10 2990 #define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK) 2991 #define F_L2T_W_PKBK V_L2T_W_LPBK(1U) 2992 2993 #define S_L2T_W_ARPMISS 11 2994 #define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS) 2995 #define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U) 2996 2997 #define S_L2T_W_NOREPLY 15 2998 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 2999 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 3000 3001 3002 /* cpl_l2t_write_req.vlan fields */ 3003 #define S_L2T_VLANTAG 0 3004 #define M_L2T_VLANTAG 0xFFF 3005 #define V_L2T_VLANTAG(x) ((x) << S_L2T_VLANTAG) 3006 #define G_L2T_VLANTAG(x) (((x) >> S_L2T_VLANTAG) & M_L2T_VLANTAG) 3007 3008 #define S_L2T_VLANPRIO 13 3009 #define M_L2T_VLANPRIO 0x7 3010 #define V_L2T_VLANPRIO(x) ((x) << S_L2T_VLANPRIO) 3011 #define G_L2T_VLANPRIO(x) (((x) >> S_L2T_VLANPRIO) & M_L2T_VLANPRIO) 3012 3013 #define CPL_L2T_VLAN_NONE 0xfff 3014 3015 struct cpl_l2t_write_rpl { 3016 RSS_HDR 3017 union opcode_tid ot; 3018 __u8 status; 3019 __u8 rsvd[3]; 3020 }; 3021 3022 struct cpl_l2t_read_req { 3023 WR_HDR; 3024 union opcode_tid ot; 3025 __be32 l2t_idx; 3026 }; 3027 3028 struct cpl_l2t_read_rpl { 3029 RSS_HDR 3030 union opcode_tid ot; 3031 __u8 status; 3032 #if defined(__LITTLE_ENDIAN_BITFIELD) 3033 __u8 :4; 3034 __u8 iff:4; 3035 #else 3036 __u8 iff:4; 3037 __u8 :4; 3038 #endif 3039 __be16 vlan; 3040 __be16 info; 3041 __u8 dst_mac[6]; 3042 }; 3043 3044 struct cpl_srq_table_req { 3045 WR_HDR; 3046 union opcode_tid ot; 3047 __u8 status; 3048 __u8 rsvd[2]; 3049 __u8 idx; 3050 __be64 rsvd_pdid; 3051 __be32 qlen_qbase; 3052 __be16 cur_msn; 3053 __be16 max_msn; 3054 }; 3055 3056 struct cpl_srq_table_rpl { 3057 RSS_HDR 3058 union opcode_tid ot; 3059 __u8 status; 3060 __u8 rsvd[2]; 3061 __u8 idx; 3062 __be64 rsvd_pdid; 3063 __be32 qlen_qbase; 3064 __be16 cur_msn; 3065 __be16 max_msn; 3066 }; 3067 3068 /* cpl_srq_table_{req,rpl}.params fields */ 3069 #define S_SRQT_QLEN 28 3070 #define M_SRQT_QLEN 0xF 3071 #define V_SRQT_QLEN(x) ((x) << S_SRQT_QLEN) 3072 #define G_SRQT_QLEN(x) (((x) >> S_SRQT_QLEN) & M_SRQT_QLEN) 3073 3074 #define S_SRQT_QBASE 0 3075 #define M_SRQT_QBASE 0x3FFFFFF 3076 #define V_SRQT_QBASE(x) ((x) << S_SRQT_QBASE) 3077 #define G_SRQT_QBASE(x) (((x) >> S_SRQT_QBASE) & M_SRQT_QBASE) 3078 3079 #define S_SRQT_PDID 0 3080 #define M_SRQT_PDID 0xFF 3081 #define V_SRQT_PDID(x) ((x) << S_SRQT_PDID) 3082 #define G_SRQT_PDID(x) (((x) >> S_SRQT_PDID) & M_SRQT_PDID) 3083 3084 #define S_SRQT_IDX 0 3085 #define M_SRQT_IDX 0xF 3086 #define V_SRQT_IDX(x) ((x) << S_SRQT_IDX) 3087 #define G_SRQT_IDX(x) (((x) >> S_SRQT_IDX) & M_SRQT_IDX) 3088 3089 struct cpl_t7_srq_table_req { 3090 WR_HDR; 3091 union opcode_tid ot; 3092 __be32 noreply_to_index; 3093 __be16 srqlimit_pkd; 3094 __be16 cqid; 3095 __be16 xdid; 3096 __be16 pdid; 3097 __be32 quelen_quebase; 3098 __be32 curmsn_maxmsn; 3099 }; 3100 3101 #define S_CPL_T7_SRQ_TABLE_REQ_NOREPLY 31 3102 #define M_CPL_T7_SRQ_TABLE_REQ_NOREPLY 0x1 3103 #define V_CPL_T7_SRQ_TABLE_REQ_NOREPLY(x) \ 3104 ((x) << S_CPL_T7_SRQ_TABLE_REQ_NOREPLY) 3105 #define G_CPL_T7_SRQ_TABLE_REQ_NOREPLY(x) \ 3106 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_NOREPLY) & M_CPL_T7_SRQ_TABLE_REQ_NOREPLY) 3107 #define F_CPL_T7_SRQ_TABLE_REQ_NOREPLY \ 3108 V_CPL_T7_SRQ_TABLE_REQ_NOREPLY(1U) 3109 3110 #define S_CPL_T7_SRQ_TABLE_REQ_WRITE 30 3111 #define M_CPL_T7_SRQ_TABLE_REQ_WRITE 0x1 3112 #define V_CPL_T7_SRQ_TABLE_REQ_WRITE(x) ((x) << S_CPL_T7_SRQ_TABLE_REQ_WRITE) 3113 #define G_CPL_T7_SRQ_TABLE_REQ_WRITE(x) \ 3114 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_WRITE) & M_CPL_T7_SRQ_TABLE_REQ_WRITE) 3115 #define F_CPL_T7_SRQ_TABLE_REQ_WRITE V_CPL_T7_SRQ_TABLE_REQ_WRITE(1U) 3116 3117 #define S_CPL_T7_SRQ_TABLE_REQ_INCR 28 3118 #define M_CPL_T7_SRQ_TABLE_REQ_INCR 0x3 3119 #define V_CPL_T7_SRQ_TABLE_REQ_INCR(x) ((x) << S_CPL_T7_SRQ_TABLE_REQ_INCR) 3120 #define G_CPL_T7_SRQ_TABLE_REQ_INCR(x) \ 3121 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_INCR) & M_CPL_T7_SRQ_TABLE_REQ_INCR) 3122 3123 #define S_CPL_T7_SRQ_TABLE_REQ_OVER 24 3124 #define M_CPL_T7_SRQ_TABLE_REQ_OVER 0xf 3125 #define V_CPL_T7_SRQ_TABLE_REQ_OVER(x) ((x) << S_CPL_T7_SRQ_TABLE_REQ_OVER) 3126 #define G_CPL_T7_SRQ_TABLE_REQ_OVER(x) \ 3127 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_OVER) & M_CPL_T7_SRQ_TABLE_REQ_OVER) 3128 3129 #define S_CPL_T7_SRQ_TABLE_REQ_LIMITUPD 23 3130 #define M_CPL_T7_SRQ_TABLE_REQ_LIMITUPD 0x1 3131 #define V_CPL_T7_SRQ_TABLE_REQ_LIMITUPD(x) \ 3132 ((x) << S_CPL_T7_SRQ_TABLE_REQ_LIMITUPD) 3133 #define G_CPL_T7_SRQ_TABLE_REQ_LIMITUPD(x) \ 3134 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_LIMITUPD) & M_CPL_T7_SRQ_TABLE_REQ_LIMITUPD) 3135 #define F_CPL_T7_SRQ_TABLE_REQ_LIMITUPD V_CPL_T7_SRQ_TABLE_REQ_LIMITUPD(1U) 3136 3137 #define S_CPL_T7_SRQ_TABLE_REQ_INDEX 0 3138 #define M_CPL_T7_SRQ_TABLE_REQ_INDEX 0x3ff 3139 #define V_CPL_T7_SRQ_TABLE_REQ_INDEX(x) ((x) << S_CPL_T7_SRQ_TABLE_REQ_INDEX) 3140 #define G_CPL_T7_SRQ_TABLE_REQ_INDEX(x) \ 3141 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_INDEX) & M_CPL_T7_SRQ_TABLE_REQ_INDEX) 3142 3143 #define S_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT 0 3144 #define M_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT 0x3f 3145 #define V_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT(x) \ 3146 ((x) << S_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT) 3147 #define G_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT(x) \ 3148 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT) & M_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT) 3149 3150 #define S_CPL_T7_SRQ_TABLE_REQ_QUELEN 28 3151 #define M_CPL_T7_SRQ_TABLE_REQ_QUELEN 0xf 3152 #define V_CPL_T7_SRQ_TABLE_REQ_QUELEN(x) \ 3153 ((x) << S_CPL_T7_SRQ_TABLE_REQ_QUELEN) 3154 #define G_CPL_T7_SRQ_TABLE_REQ_QUELEN(x) \ 3155 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_QUELEN) & M_CPL_T7_SRQ_TABLE_REQ_QUELEN) 3156 3157 #define S_CPL_T7_SRQ_TABLE_REQ_QUEBASE 0 3158 #define M_CPL_T7_SRQ_TABLE_REQ_QUEBASE 0x3ffffff 3159 #define V_CPL_T7_SRQ_TABLE_REQ_QUEBASE(x) \ 3160 ((x) << S_CPL_T7_SRQ_TABLE_REQ_QUEBASE) 3161 #define G_CPL_T7_SRQ_TABLE_REQ_QUEBASE(x) \ 3162 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_QUEBASE) & M_CPL_T7_SRQ_TABLE_REQ_QUEBASE) 3163 3164 #define S_CPL_T7_SRQ_TABLE_REQ_CURMSN 16 3165 #define M_CPL_T7_SRQ_TABLE_REQ_CURMSN 0xffff 3166 #define V_CPL_T7_SRQ_TABLE_REQ_CURMSN(x) \ 3167 ((x) << S_CPL_T7_SRQ_TABLE_REQ_CURMSN) 3168 #define G_CPL_T7_SRQ_TABLE_REQ_CURMSN(x) \ 3169 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_CURMSN) & M_CPL_T7_SRQ_TABLE_REQ_CURMSN) 3170 3171 #define S_CPL_T7_SRQ_TABLE_REQ_MAXMSN 0 3172 #define M_CPL_T7_SRQ_TABLE_REQ_MAXMSN 0xffff 3173 #define V_CPL_T7_SRQ_TABLE_REQ_MAXMSN(x) \ 3174 ((x) << S_CPL_T7_SRQ_TABLE_REQ_MAXMSN) 3175 #define G_CPL_T7_SRQ_TABLE_REQ_MAXMSN(x) \ 3176 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_MAXMSN) & M_CPL_T7_SRQ_TABLE_REQ_MAXMSN) 3177 3178 struct cpl_t7_srq_table_rpl { 3179 RSS_HDR 3180 union opcode_tid ot; 3181 __be32 status_index; 3182 __be16 srqlimit_pkd; 3183 __be16 cqid; 3184 __be16 xdid; 3185 __be16 pdid; 3186 __be32 quelen_quebase; 3187 __be32 curmsn_maxmsn; 3188 }; 3189 3190 #define S_CPL_T7_SRQ_TABLE_RPL_STATUS 24 3191 #define M_CPL_T7_SRQ_TABLE_RPL_STATUS 0xff 3192 #define V_CPL_T7_SRQ_TABLE_RPL_STATUS(x) \ 3193 ((x) << S_CPL_T7_SRQ_TABLE_RPL_STATUS) 3194 #define G_CPL_T7_SRQ_TABLE_RPL_STATUS(x) \ 3195 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_STATUS) & M_CPL_T7_SRQ_TABLE_RPL_STATUS) 3196 3197 #define S_CPL_T7_SRQ_TABLE_RPL_INDEX 0 3198 #define M_CPL_T7_SRQ_TABLE_RPL_INDEX 0x3ff 3199 #define V_CPL_T7_SRQ_TABLE_RPL_INDEX(x) ((x) << S_CPL_T7_SRQ_TABLE_RPL_INDEX) 3200 #define G_CPL_T7_SRQ_TABLE_RPL_INDEX(x) \ 3201 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_INDEX) & M_CPL_T7_SRQ_TABLE_RPL_INDEX) 3202 3203 #define S_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT 0 3204 #define M_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT 0x3f 3205 #define V_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT(x) \ 3206 ((x) << S_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT) 3207 #define G_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT(x) \ 3208 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT) & M_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT) 3209 3210 #define S_CPL_T7_SRQ_TABLE_RPL_QUELEN 28 3211 #define M_CPL_T7_SRQ_TABLE_RPL_QUELEN 0xf 3212 #define V_CPL_T7_SRQ_TABLE_RPL_QUELEN(x) \ 3213 ((x) << S_CPL_T7_SRQ_TABLE_RPL_QUELEN) 3214 #define G_CPL_T7_SRQ_TABLE_RPL_QUELEN(x) \ 3215 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_QUELEN) & M_CPL_T7_SRQ_TABLE_RPL_QUELEN) 3216 3217 #define S_CPL_T7_SRQ_TABLE_RPL_QUEBASE 0 3218 #define M_CPL_T7_SRQ_TABLE_RPL_QUEBASE 0x3ffffff 3219 #define V_CPL_T7_SRQ_TABLE_RPL_QUEBASE(x) \ 3220 ((x) << S_CPL_T7_SRQ_TABLE_RPL_QUEBASE) 3221 #define G_CPL_T7_SRQ_TABLE_RPL_QUEBASE(x) \ 3222 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_QUEBASE) & M_CPL_T7_SRQ_TABLE_RPL_QUEBASE) 3223 3224 #define S_CPL_T7_SRQ_TABLE_RPL_CURMSN 16 3225 #define M_CPL_T7_SRQ_TABLE_RPL_CURMSN 0xffff 3226 #define V_CPL_T7_SRQ_TABLE_RPL_CURMSN(x) \ 3227 ((x) << S_CPL_T7_SRQ_TABLE_RPL_CURMSN) 3228 #define G_CPL_T7_SRQ_TABLE_RPL_CURMSN(x) \ 3229 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_CURMSN) & M_CPL_T7_SRQ_TABLE_RPL_CURMSN) 3230 3231 #define S_CPL_T7_SRQ_TABLE_RPL_MAXMSN 0 3232 #define M_CPL_T7_SRQ_TABLE_RPL_MAXMSN 0xffff 3233 #define V_CPL_T7_SRQ_TABLE_RPL_MAXMSN(x) \ 3234 ((x) << S_CPL_T7_SRQ_TABLE_RPL_MAXMSN) 3235 #define G_CPL_T7_SRQ_TABLE_RPL_MAXMSN(x) \ 3236 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_MAXMSN) & M_CPL_T7_SRQ_TABLE_RPL_MAXMSN) 3237 3238 struct cpl_rdma_async_event { 3239 RSS_HDR 3240 union opcode_tid ot; 3241 __be32 EventInfo; 3242 }; 3243 3244 #define S_CPL_RDMA_ASYNC_EVENT_EVENTTYPE 16 3245 #define M_CPL_RDMA_ASYNC_EVENT_EVENTTYPE 0xf 3246 #define V_CPL_RDMA_ASYNC_EVENT_EVENTTYPE(x) \ 3247 ((x) << S_CPL_RDMA_ASYNC_EVENT_EVENTTYPE) 3248 #define G_CPL_RDMA_ASYNC_EVENT_EVENTTYPE(x) \ 3249 (((x) >> S_CPL_RDMA_ASYNC_EVENT_EVENTTYPE) & \ 3250 M_CPL_RDMA_ASYNC_EVENT_EVENTTYPE) 3251 3252 #define S_CPL_RDMA_ASYNC_EVENT_INDEX 0 3253 #define M_CPL_RDMA_ASYNC_EVENT_INDEX 0xffff 3254 #define V_CPL_RDMA_ASYNC_EVENT_INDEX(x) ((x) << S_CPL_RDMA_ASYNC_EVENT_INDEX) 3255 #define G_CPL_RDMA_ASYNC_EVENT_INDEX(x) \ 3256 (((x) >> S_CPL_RDMA_ASYNC_EVENT_INDEX) & M_CPL_RDMA_ASYNC_EVENT_INDEX) 3257 3258 struct cpl_smt_write_req { 3259 WR_HDR; 3260 union opcode_tid ot; 3261 __be32 params; 3262 __be16 pfvf1; 3263 __u8 src_mac1[6]; 3264 __be16 pfvf0; 3265 __u8 src_mac0[6]; 3266 }; 3267 3268 struct cpl_t6_smt_write_req { 3269 WR_HDR; 3270 union opcode_tid ot; 3271 __be32 params; 3272 __be64 tag; 3273 __be16 pfvf0; 3274 __u8 src_mac0[6]; 3275 __be32 local_ip; 3276 __be32 rsvd; 3277 }; 3278 3279 struct cpl_smt_write_rpl { 3280 RSS_HDR 3281 union opcode_tid ot; 3282 __u8 status; 3283 __u8 rsvd[3]; 3284 }; 3285 3286 struct cpl_smt_read_req { 3287 WR_HDR; 3288 union opcode_tid ot; 3289 __be32 params; 3290 }; 3291 3292 struct cpl_smt_read_rpl { 3293 RSS_HDR 3294 union opcode_tid ot; 3295 __u8 status; 3296 __u8 ovlan_idx; 3297 __be16 rsvd; 3298 __be16 pfvf1; 3299 __u8 src_mac1[6]; 3300 __be16 pfvf0; 3301 __u8 src_mac0[6]; 3302 }; 3303 3304 /* cpl_smt_{read,write}_req.params fields */ 3305 #define S_SMTW_OVLAN_IDX 16 3306 #define M_SMTW_OVLAN_IDX 0xF 3307 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 3308 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 3309 3310 #define S_SMTW_IDX 20 3311 #define M_SMTW_IDX 0x7F 3312 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 3313 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 3314 3315 #define M_T6_SMTW_IDX 0xFF 3316 #define G_T6_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_T6_SMTW_IDX) 3317 3318 #define S_SMTW_NORPL 31 3319 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 3320 #define F_SMTW_NORPL V_SMTW_NORPL(1U) 3321 3322 /* cpl_smt_{read,write}_req.pfvf? fields */ 3323 #define S_SMTW_VF 0 3324 #define M_SMTW_VF 0xFF 3325 #define V_SMTW_VF(x) ((x) << S_SMTW_VF) 3326 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 3327 3328 #define S_SMTW_PF 8 3329 #define M_SMTW_PF 0x7 3330 #define V_SMTW_PF(x) ((x) << S_SMTW_PF) 3331 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 3332 3333 #define S_SMTW_VF_VLD 11 3334 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 3335 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 3336 3337 struct cpl_t7_smt_write_req { 3338 WR_HDR; 3339 union opcode_tid ot; 3340 __be32 noreply_to_mtu; 3341 union smt_write_req { 3342 struct smt_write_req_pfvf { 3343 __be64 tagvalue; 3344 __be32 pfvf_smac_hi; 3345 __be32 smac_lo; 3346 __be64 tagext; 3347 } pfvf; 3348 struct smt_write_req_ipv4 { 3349 __be32 srcipv4; 3350 __be32 destipv4; 3351 } ipv4; 3352 struct smt_write_req_ipv6 { 3353 __be64 ipv6ms; 3354 __be64 ipv6ls; 3355 } ipv6; 3356 } u; 3357 }; 3358 3359 #define S_CPL_T7_SMT_WRITE_REQ_NOREPLY 31 3360 #define M_CPL_T7_SMT_WRITE_REQ_NOREPLY 0x1 3361 #define V_CPL_T7_SMT_WRITE_REQ_NOREPLY(x) \ 3362 ((x) << S_CPL_T7_SMT_WRITE_REQ_NOREPLY) 3363 #define G_CPL_T7_SMT_WRITE_REQ_NOREPLY(x) \ 3364 (((x) >> S_CPL_T7_SMT_WRITE_REQ_NOREPLY) & M_CPL_T7_SMT_WRITE_REQ_NOREPLY) 3365 #define F_CPL_T7_SMT_WRITE_REQ_NOREPLY \ 3366 V_CPL_T7_SMT_WRITE_REQ_NOREPLY(1U) 3367 3368 #define S_CPL_T7_SMT_WRITE_REQ_TAGINSERT 30 3369 #define M_CPL_T7_SMT_WRITE_REQ_TAGINSERT 0x1 3370 #define V_CPL_T7_SMT_WRITE_REQ_TAGINSERT(x) \ 3371 ((x) << S_CPL_T7_SMT_WRITE_REQ_TAGINSERT) 3372 #define G_CPL_T7_SMT_WRITE_REQ_TAGINSERT(x) \ 3373 (((x) >> S_CPL_T7_SMT_WRITE_REQ_TAGINSERT) & \ 3374 M_CPL_T7_SMT_WRITE_REQ_TAGINSERT) 3375 #define F_CPL_T7_SMT_WRITE_REQ_TAGINSERT \ 3376 V_CPL_T7_SMT_WRITE_REQ_TAGINSERT(1U) 3377 3378 #define S_CPL_T7_SMT_WRITE_REQ_TAGTYPE 28 3379 #define M_CPL_T7_SMT_WRITE_REQ_TAGTYPE 0x3 3380 #define V_CPL_T7_SMT_WRITE_REQ_TAGTYPE(x) \ 3381 ((x) << S_CPL_T7_SMT_WRITE_REQ_TAGTYPE) 3382 #define G_CPL_T7_SMT_WRITE_REQ_TAGTYPE(x) \ 3383 (((x) >> S_CPL_T7_SMT_WRITE_REQ_TAGTYPE) & M_CPL_T7_SMT_WRITE_REQ_TAGTYPE) 3384 3385 #define S_CPL_T7_SMT_WRITE_REQ_INDEX 20 3386 #define M_CPL_T7_SMT_WRITE_REQ_INDEX 0xff 3387 #define V_CPL_T7_SMT_WRITE_REQ_INDEX(x) ((x) << S_CPL_T7_SMT_WRITE_REQ_INDEX) 3388 #define G_CPL_T7_SMT_WRITE_REQ_INDEX(x) \ 3389 (((x) >> S_CPL_T7_SMT_WRITE_REQ_INDEX) & M_CPL_T7_SMT_WRITE_REQ_INDEX) 3390 3391 #define S_CPL_T7_SMT_WRITE_REQ_OVLAN 16 3392 #define M_CPL_T7_SMT_WRITE_REQ_OVLAN 0xf 3393 #define V_CPL_T7_SMT_WRITE_REQ_OVLAN(x) ((x) << S_CPL_T7_SMT_WRITE_REQ_OVLAN) 3394 #define G_CPL_T7_SMT_WRITE_REQ_OVLAN(x) \ 3395 (((x) >> S_CPL_T7_SMT_WRITE_REQ_OVLAN) & M_CPL_T7_SMT_WRITE_REQ_OVLAN) 3396 3397 #define S_CPL_T7_SMT_WRITE_REQ_IPSEC 14 3398 #define M_CPL_T7_SMT_WRITE_REQ_IPSEC 0x1 3399 #define V_CPL_T7_SMT_WRITE_REQ_IPSEC(x) ((x) << S_CPL_T7_SMT_WRITE_REQ_IPSEC) 3400 #define G_CPL_T7_SMT_WRITE_REQ_IPSEC(x) \ 3401 (((x) >> S_CPL_T7_SMT_WRITE_REQ_IPSEC) & M_CPL_T7_SMT_WRITE_REQ_IPSEC) 3402 #define F_CPL_T7_SMT_WRITE_REQ_IPSEC V_CPL_T7_SMT_WRITE_REQ_IPSEC(1U) 3403 3404 #define S_CPL_T7_SMT_WRITE_REQ_MTU 0 3405 #define M_CPL_T7_SMT_WRITE_REQ_MTU 0x3fff 3406 #define V_CPL_T7_SMT_WRITE_REQ_MTU(x) ((x) << S_CPL_T7_SMT_WRITE_REQ_MTU) 3407 #define G_CPL_T7_SMT_WRITE_REQ_MTU(x) \ 3408 (((x) >> S_CPL_T7_SMT_WRITE_REQ_MTU) & M_CPL_T7_SMT_WRITE_REQ_MTU) 3409 3410 #define S_CPL_T7_SMT_WRITE_REQ_PFVF 16 3411 #define M_CPL_T7_SMT_WRITE_REQ_PFVF 0xfff 3412 #define V_CPL_T7_SMT_WRITE_REQ_PFVF(x) ((x) << S_CPL_T7_SMT_WRITE_REQ_PFVF) 3413 #define G_CPL_T7_SMT_WRITE_REQ_PFVF(x) \ 3414 (((x) >> S_CPL_T7_SMT_WRITE_REQ_PFVF) & M_CPL_T7_SMT_WRITE_REQ_PFVF) 3415 3416 #define S_CPL_T7_SMT_WRITE_REQ_SMAC_HI 0 3417 #define M_CPL_T7_SMT_WRITE_REQ_SMAC_HI 0xffff 3418 #define V_CPL_T7_SMT_WRITE_REQ_SMAC_HI(x) \ 3419 ((x) << S_CPL_T7_SMT_WRITE_REQ_SMAC_HI) 3420 #define G_CPL_T7_SMT_WRITE_REQ_SMAC_HI(x) \ 3421 (((x) >> S_CPL_T7_SMT_WRITE_REQ_SMAC_HI) & M_CPL_T7_SMT_WRITE_REQ_SMAC_HI) 3422 3423 struct cpl_t7_smt_read_req { 3424 WR_HDR; 3425 union opcode_tid ot; 3426 __be32 index_to_ipsecidx; 3427 }; 3428 3429 #define S_CPL_T7_SMT_READ_REQ_INDEX 20 3430 #define M_CPL_T7_SMT_READ_REQ_INDEX 0xff 3431 #define V_CPL_T7_SMT_READ_REQ_INDEX(x) ((x) << S_CPL_T7_SMT_READ_REQ_INDEX) 3432 #define G_CPL_T7_SMT_READ_REQ_INDEX(x) \ 3433 (((x) >> S_CPL_SMT_READ_REQ_INDEX) & M_CPL_T7_SMT_READ_REQ_INDEX) 3434 3435 #define S_CPL_T7_SMT_READ_REQ_IPSEC 14 3436 #define M_CPL_T7_SMT_READ_REQ_IPSEC 0x1 3437 #define V_CPL_T7_SMT_READ_REQ_IPSEC(x) ((x) << S_CPL_T7_SMT_READ_REQ_IPSEC) 3438 #define G_CPL_T7_SMT_READ_REQ_IPSEC(x) \ 3439 (((x) >> S_CPL_T7_SMT_READ_REQ_IPSEC) & M_CPL_T7_SMT_READ_REQ_IPSEC) 3440 #define F_CPL_T7_SMT_READ_REQ_IPSEC V_CPL_T7_SMT_READ_REQ_IPSEC(1U) 3441 3442 #define S_CPL_T7_SMT_READ_REQ_IPSECIDX 0 3443 #define M_CPL_T7_SMT_READ_REQ_IPSECIDX 0x1fff 3444 #define V_CPL_T7_SMT_READ_REQ_IPSECIDX(x) \ 3445 ((x) << S_CPL_T7_SMT_READ_REQ_IPSECIDX) 3446 #define G_CPL_T7_SMT_READ_REQ_IPSECIDX(x) \ 3447 (((x) >> S_CPL_T7_SMT_READ_REQ_IPSECIDX) & M_CPL_T7_SMT_READ_REQ_IPSECIDX) 3448 3449 struct cpl_tag_write_req { 3450 WR_HDR; 3451 union opcode_tid ot; 3452 __be32 params; 3453 __be64 tag_val; 3454 }; 3455 3456 struct cpl_tag_write_rpl { 3457 RSS_HDR 3458 union opcode_tid ot; 3459 __u8 status; 3460 __u8 rsvd[2]; 3461 __u8 idx; 3462 }; 3463 3464 struct cpl_tag_read_req { 3465 WR_HDR; 3466 union opcode_tid ot; 3467 __be32 params; 3468 }; 3469 3470 struct cpl_tag_read_rpl { 3471 RSS_HDR 3472 union opcode_tid ot; 3473 __u8 status; 3474 #if defined(__LITTLE_ENDIAN_BITFIELD) 3475 __u8 :4; 3476 __u8 tag_len:1; 3477 __u8 :2; 3478 __u8 ins_enable:1; 3479 #else 3480 __u8 ins_enable:1; 3481 __u8 :2; 3482 __u8 tag_len:1; 3483 __u8 :4; 3484 #endif 3485 __u8 rsvd; 3486 __u8 tag_idx; 3487 __be64 tag_val; 3488 }; 3489 3490 /* cpl_tag{read,write}_req.params fields */ 3491 #define S_TAGW_IDX 0 3492 #define M_TAGW_IDX 0x7F 3493 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) 3494 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) 3495 3496 #define S_TAGW_LEN 20 3497 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) 3498 #define F_TAGW_LEN V_TAGW_LEN(1U) 3499 3500 #define S_TAGW_INS_ENABLE 23 3501 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) 3502 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) 3503 3504 #define S_TAGW_NORPL 31 3505 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) 3506 #define F_TAGW_NORPL V_TAGW_NORPL(1U) 3507 3508 struct cpl_barrier { 3509 WR_HDR; 3510 __u8 opcode; 3511 __u8 chan_map; 3512 __be16 rsvd0; 3513 __be32 rsvd1; 3514 }; 3515 3516 /* cpl_barrier.chan_map fields */ 3517 #define S_CHAN_MAP 4 3518 #define M_CHAN_MAP 0xF 3519 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 3520 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 3521 3522 struct cpl_error { 3523 RSS_HDR 3524 union opcode_tid ot; 3525 __be32 error; 3526 }; 3527 3528 struct cpl_hit_notify { 3529 RSS_HDR 3530 union opcode_tid ot; 3531 __be32 rsvd; 3532 __be32 info; 3533 __be32 reason; 3534 }; 3535 3536 struct cpl_pkt_notify { 3537 RSS_HDR 3538 union opcode_tid ot; 3539 __be16 rsvd; 3540 __be16 len; 3541 __be32 info; 3542 __be32 reason; 3543 }; 3544 3545 /* cpl_{hit,pkt}_notify.info fields */ 3546 #define S_NTFY_MAC_IDX 0 3547 #define M_NTFY_MAC_IDX 0x1FF 3548 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 3549 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 3550 3551 #define S_NTFY_INTF 10 3552 #define M_NTFY_INTF 0xF 3553 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 3554 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 3555 3556 #define S_NTFY_TCPHDR_LEN 14 3557 #define M_NTFY_TCPHDR_LEN 0xF 3558 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 3559 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 3560 3561 #define S_NTFY_IPHDR_LEN 18 3562 #define M_NTFY_IPHDR_LEN 0x1FF 3563 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 3564 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 3565 3566 #define S_NTFY_ETHHDR_LEN 27 3567 #define M_NTFY_ETHHDR_LEN 0x1F 3568 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 3569 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 3570 3571 #define S_NTFY_T5_IPHDR_LEN 18 3572 #define M_NTFY_T5_IPHDR_LEN 0xFF 3573 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) 3574 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) 3575 3576 #define S_NTFY_T5_ETHHDR_LEN 26 3577 #define M_NTFY_T5_ETHHDR_LEN 0x3F 3578 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) 3579 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) 3580 3581 struct cpl_t7_pkt_notify { 3582 RSS_HDR 3583 union opcode_tid ot; 3584 __be16 r1; 3585 __be16 length; 3586 __be32 ethhdrlen_to_macindex; 3587 __be32 lineinfo; 3588 }; 3589 3590 #define S_CPL_T7_PKT_NOTIFY_ETHHDRLEN 24 3591 #define M_CPL_T7_PKT_NOTIFY_ETHHDRLEN 0xff 3592 #define V_CPL_T7_PKT_NOTIFY_ETHHDRLEN(x) \ 3593 ((x) << S_CPL_T7_PKT_NOTIFY_ETHHDRLEN) 3594 #define G_CPL_T7_PKT_NOTIFY_ETHHDRLEN(x) \ 3595 (((x) >> S_CPL_T7_PKT_NOTIFY_ETHHDRLEN) & M_CPL_T7_PKT_NOTIFY_ETHHDRLEN) 3596 3597 #define S_CPL_T7_PKT_NOTIFY_IPHDRLEN 18 3598 #define M_CPL_T7_PKT_NOTIFY_IPHDRLEN 0x3f 3599 #define V_CPL_T7_PKT_NOTIFY_IPHDRLEN(x) ((x) << S_CPL_T7_PKT_NOTIFY_IPHDRLEN) 3600 #define G_CPL_T7_PKT_NOTIFY_IPHDRLEN(x) \ 3601 (((x) >> S_CPL_T7_PKT_NOTIFY_IPHDRLEN) & M_CPL_T7_PKT_NOTIFY_IPHDRLEN) 3602 3603 #define S_CPL_T7_PKT_NOTIFY_TCPHDRLEN 14 3604 #define M_CPL_T7_PKT_NOTIFY_TCPHDRLEN 0xf 3605 #define V_CPL_T7_PKT_NOTIFY_TCPHDRLEN(x) \ 3606 ((x) << S_CPL_T7_PKT_NOTIFY_TCPHDRLEN) 3607 #define G_CPL_T7_PKT_NOTIFY_TCPHDRLEN(x) \ 3608 (((x) >> S_CPL_T7_PKT_NOTIFY_TCPHDRLEN) & M_CPL_T7_PKT_NOTIFY_TCPHDRLEN) 3609 3610 #define S_CPL_T7_PKT_NOTIFY_INTERFACE 10 3611 #define M_CPL_T7_PKT_NOTIFY_INTERFACE 0xf 3612 #define V_CPL_T7_PKT_NOTIFY_INTERFACE(x) \ 3613 ((x) << S_CPL_T7_PKT_NOTIFY_INTERFACE) 3614 #define G_CPL_T7_PKT_NOTIFY_INTERFACE(x) \ 3615 (((x) >> S_CPL_T7_PKT_NOTIFY_INTERFACE) & M_CPL_T7_PKT_NOTIFY_INTERFACE) 3616 3617 #define S_CPL_T7_PKT_NOTIFY_MACINDEX 0 3618 #define M_CPL_T7_PKT_NOTIFY_MACINDEX 0x1ff 3619 #define V_CPL_T7_PKT_NOTIFY_MACINDEX(x) ((x) << S_CPL_T7_PKT_NOTIFY_MACINDEX) 3620 #define G_CPL_T7_PKT_NOTIFY_MACINDEX(x) \ 3621 (((x) >> S_CPL_T7_PKT_NOTIFY_MACINDEX) & M_CPL_T7_PKT_NOTIFY_MACINDEX) 3622 3623 struct cpl_rdma_cqe { 3624 WR_HDR; 3625 union opcode_tid ot; 3626 __be32 tid_flitcnt; 3627 __be32 qpid_to_wr_type; 3628 __be32 length; 3629 __be32 tag; 3630 __be32 msn; 3631 }; 3632 3633 #define S_CPL_RDMA_CQE_RSSCTRL 16 3634 #define M_CPL_RDMA_CQE_RSSCTRL 0xff 3635 #define V_CPL_RDMA_CQE_RSSCTRL(x) ((x) << S_CPL_RDMA_CQE_RSSCTRL) 3636 #define G_CPL_RDMA_CQE_RSSCTRL(x) \ 3637 (((x) >> S_CPL_RDMA_CQE_RSSCTRL) & M_CPL_RDMA_CQE_RSSCTRL) 3638 3639 #define S_CPL_RDMA_CQE_CQID 0 3640 #define M_CPL_RDMA_CQE_CQID 0xffff 3641 #define V_CPL_RDMA_CQE_CQID(x) ((x) << S_CPL_RDMA_CQE_CQID) 3642 #define G_CPL_RDMA_CQE_CQID(x) \ 3643 (((x) >> S_CPL_RDMA_CQE_CQID) & M_CPL_RDMA_CQE_CQID) 3644 3645 #define S_CPL_RDMA_CQE_TID 8 3646 #define M_CPL_RDMA_CQE_TID 0xfffff 3647 #define V_CPL_RDMA_CQE_TID(x) ((x) << S_CPL_RDMA_CQE_TID) 3648 #define G_CPL_RDMA_CQE_TID(x) \ 3649 (((x) >> S_CPL_RDMA_CQE_TID) & M_CPL_RDMA_CQE_TID) 3650 3651 #define S_CPL_RDMA_CQE_FLITCNT 0 3652 #define M_CPL_RDMA_CQE_FLITCNT 0xff 3653 #define V_CPL_RDMA_CQE_FLITCNT(x) ((x) << S_CPL_RDMA_CQE_FLITCNT) 3654 #define G_CPL_RDMA_CQE_FLITCNT(x) \ 3655 (((x) >> S_CPL_RDMA_CQE_FLITCNT) & M_CPL_RDMA_CQE_FLITCNT) 3656 3657 #define S_CPL_RDMA_CQE_QPID 12 3658 #define M_CPL_RDMA_CQE_QPID 0xfffff 3659 #define V_CPL_RDMA_CQE_QPID(x) ((x) << S_CPL_RDMA_CQE_QPID) 3660 #define G_CPL_RDMA_CQE_QPID(x) \ 3661 (((x) >> S_CPL_RDMA_CQE_QPID) & M_CPL_RDMA_CQE_QPID) 3662 3663 #define S_CPL_RDMA_CQE_GENERATION_BIT 10 3664 #define M_CPL_RDMA_CQE_GENERATION_BIT 0x1 3665 #define V_CPL_RDMA_CQE_GENERATION_BIT(x) \ 3666 ((x) << S_CPL_RDMA_CQE_GENERATION_BIT) 3667 #define G_CPL_RDMA_CQE_GENERATION_BIT(x) \ 3668 (((x) >> S_CPL_RDMA_CQE_GENERATION_BIT) & M_CPL_RDMA_CQE_GENERATION_BIT) 3669 #define F_CPL_RDMA_CQE_GENERATION_BIT V_CPL_RDMA_CQE_GENERATION_BIT(1U) 3670 3671 #define S_CPL_RDMA_CQE_STATUS 5 3672 #define M_CPL_RDMA_CQE_STATUS 0x1f 3673 #define V_CPL_RDMA_CQE_STATUS(x) ((x) << S_CPL_RDMA_CQE_STATUS) 3674 #define G_CPL_RDMA_CQE_STATUS(x) \ 3675 (((x) >> S_CPL_RDMA_CQE_STATUS) & M_CPL_RDMA_CQE_STATUS) 3676 3677 #define S_CPL_RDMA_CQE_CQE_TYPE 4 3678 #define M_CPL_RDMA_CQE_CQE_TYPE 0x1 3679 #define V_CPL_RDMA_CQE_CQE_TYPE(x) ((x) << S_CPL_RDMA_CQE_CQE_TYPE) 3680 #define G_CPL_RDMA_CQE_CQE_TYPE(x) \ 3681 (((x) >> S_CPL_RDMA_CQE_CQE_TYPE) & M_CPL_RDMA_CQE_CQE_TYPE) 3682 #define F_CPL_RDMA_CQE_CQE_TYPE V_CPL_RDMA_CQE_CQE_TYPE(1U) 3683 3684 #define S_CPL_RDMA_CQE_WR_TYPE 0 3685 #define M_CPL_RDMA_CQE_WR_TYPE 0xf 3686 #define V_CPL_RDMA_CQE_WR_TYPE(x) ((x) << S_CPL_RDMA_CQE_WR_TYPE) 3687 #define G_CPL_RDMA_CQE_WR_TYPE(x) \ 3688 (((x) >> S_CPL_RDMA_CQE_WR_TYPE) & M_CPL_RDMA_CQE_WR_TYPE) 3689 3690 struct cpl_rdma_cqe_srq { 3691 WR_HDR; 3692 union opcode_tid ot; 3693 __be32 tid_flitcnt; 3694 __be32 qpid_to_wr_type; 3695 __be32 length; 3696 __be32 tag; 3697 __be32 msn; 3698 __be32 r3; 3699 __be32 rqe; 3700 }; 3701 3702 #define S_CPL_RDMA_CQE_SRQ_OPCODE 24 3703 #define M_CPL_RDMA_CQE_SRQ_OPCODE 0xff 3704 #define V_CPL_RDMA_CQE_SRQ_OPCODE(x) ((x) << S_CPL_RDMA_CQE_SRQ_OPCODE) 3705 #define G_CPL_RDMA_CQE_SRQ_OPCODE(x) \ 3706 (((x) >> S_CPL_RDMA_CQE_SRQ_OPCODE) & M_CPL_RDMA_CQE_SRQ_OPCODE) 3707 3708 #define S_CPL_RDMA_CQE_SRQ_RSSCTRL 16 3709 #define M_CPL_RDMA_CQE_SRQ_RSSCTRL 0xff 3710 #define V_CPL_RDMA_CQE_SRQ_RSSCTRL(x) ((x) << S_CPL_RDMA_CQE_SRQ_RSSCTRL) 3711 #define G_CPL_RDMA_CQE_SRQ_RSSCTRL(x) \ 3712 (((x) >> S_CPL_RDMA_CQE_SRQ_RSSCTRL) & M_CPL_RDMA_CQE_SRQ_RSSCTRL) 3713 3714 #define S_CPL_RDMA_CQE_SRQ_CQID 0 3715 #define M_CPL_RDMA_CQE_SRQ_CQID 0xffff 3716 #define V_CPL_RDMA_CQE_SRQ_CQID(x) ((x) << S_CPL_RDMA_CQE_SRQ_CQID) 3717 #define G_CPL_RDMA_CQE_SRQ_CQID(x) \ 3718 (((x) >> S_CPL_RDMA_CQE_SRQ_CQID) & M_CPL_RDMA_CQE_SRQ_CQID) 3719 3720 #define S_CPL_RDMA_CQE_SRQ_TID 8 3721 #define M_CPL_RDMA_CQE_SRQ_TID 0xfffff 3722 #define V_CPL_RDMA_CQE_SRQ_TID(x) ((x) << S_CPL_RDMA_CQE_SRQ_TID) 3723 #define G_CPL_RDMA_CQE_SRQ_TID(x) \ 3724 (((x) >> S_CPL_RDMA_CQE_SRQ_TID) & M_CPL_RDMA_CQE_SRQ_TID) 3725 3726 #define S_CPL_RDMA_CQE_SRQ_FLITCNT 0 3727 #define M_CPL_RDMA_CQE_SRQ_FLITCNT 0xff 3728 #define V_CPL_RDMA_CQE_SRQ_FLITCNT(x) ((x) << S_CPL_RDMA_CQE_SRQ_FLITCNT) 3729 #define G_CPL_RDMA_CQE_SRQ_FLITCNT(x) \ 3730 (((x) >> S_CPL_RDMA_CQE_SRQ_FLITCNT) & M_CPL_RDMA_CQE_SRQ_FLITCNT) 3731 3732 #define S_CPL_RDMA_CQE_SRQ_QPID 12 3733 #define M_CPL_RDMA_CQE_SRQ_QPID 0xfffff 3734 #define V_CPL_RDMA_CQE_SRQ_QPID(x) ((x) << S_CPL_RDMA_CQE_SRQ_QPID) 3735 #define G_CPL_RDMA_CQE_SRQ_QPID(x) \ 3736 (((x) >> S_CPL_RDMA_CQE_SRQ_QPID) & M_CPL_RDMA_CQE_SRQ_QPID) 3737 3738 #define S_CPL_RDMA_CQE_SRQ_GENERATION_BIT 10 3739 #define M_CPL_RDMA_CQE_SRQ_GENERATION_BIT 0x1 3740 #define V_CPL_RDMA_CQE_SRQ_GENERATION_BIT(x) \ 3741 ((x) << S_CPL_RDMA_CQE_SRQ_GENERATION_BIT) 3742 #define G_CPL_RDMA_CQE_SRQ_GENERATION_BIT(x) \ 3743 (((x) >> S_CPL_RDMA_CQE_SRQ_GENERATION_BIT) & \ 3744 M_CPL_RDMA_CQE_SRQ_GENERATION_BIT) 3745 #define F_CPL_RDMA_CQE_SRQ_GENERATION_BIT \ 3746 V_CPL_RDMA_CQE_SRQ_GENERATION_BIT(1U) 3747 3748 #define S_CPL_RDMA_CQE_SRQ_STATUS 5 3749 #define M_CPL_RDMA_CQE_SRQ_STATUS 0x1f 3750 #define V_CPL_RDMA_CQE_SRQ_STATUS(x) ((x) << S_CPL_RDMA_CQE_SRQ_STATUS) 3751 #define G_CPL_RDMA_CQE_SRQ_STATUS(x) \ 3752 (((x) >> S_CPL_RDMA_CQE_SRQ_STATUS) & M_CPL_RDMA_CQE_SRQ_STATUS) 3753 3754 #define S_CPL_RDMA_CQE_SRQ_CQE_TYPE 4 3755 #define M_CPL_RDMA_CQE_SRQ_CQE_TYPE 0x1 3756 #define V_CPL_RDMA_CQE_SRQ_CQE_TYPE(x) ((x) << S_CPL_RDMA_CQE_SRQ_CQE_TYPE) 3757 #define G_CPL_RDMA_CQE_SRQ_CQE_TYPE(x) \ 3758 (((x) >> S_CPL_RDMA_CQE_SRQ_CQE_TYPE) & M_CPL_RDMA_CQE_SRQ_CQE_TYPE) 3759 #define F_CPL_RDMA_CQE_SRQ_CQE_TYPE V_CPL_RDMA_CQE_SRQ_CQE_TYPE(1U) 3760 3761 #define S_CPL_RDMA_CQE_SRQ_WR_TYPE 0 3762 #define M_CPL_RDMA_CQE_SRQ_WR_TYPE 0xf 3763 #define V_CPL_RDMA_CQE_SRQ_WR_TYPE(x) ((x) << S_CPL_RDMA_CQE_SRQ_WR_TYPE) 3764 #define G_CPL_RDMA_CQE_SRQ_WR_TYPE(x) \ 3765 (((x) >> S_CPL_RDMA_CQE_SRQ_WR_TYPE) & M_CPL_RDMA_CQE_SRQ_WR_TYPE) 3766 3767 struct cpl_rdma_cqe_read_rsp { 3768 WR_HDR; 3769 union opcode_tid ot; 3770 __be32 tid_flitcnt; 3771 __be32 qpid_to_wr_type; 3772 __be32 length; 3773 __be32 tag; 3774 __be32 msn; 3775 }; 3776 3777 #define S_CPL_RDMA_CQE_READ_RSP_RSSCTRL 16 3778 #define M_CPL_RDMA_CQE_READ_RSP_RSSCTRL 0xff 3779 #define V_CPL_RDMA_CQE_READ_RSP_RSSCTRL(x) \ 3780 ((x) << S_CPL_RDMA_CQE_READ_RSP_RSSCTRL) 3781 #define G_CPL_RDMA_CQE_READ_RSP_RSSCTRL(x) \ 3782 (((x) >> S_CPL_RDMA_CQE_READ_RSP_RSSCTRL) & \ 3783 M_CPL_RDMA_CQE_READ_RSP_RSSCTRL) 3784 3785 #define S_CPL_RDMA_CQE_READ_RSP_CQID 0 3786 #define M_CPL_RDMA_CQE_READ_RSP_CQID 0xffff 3787 #define V_CPL_RDMA_CQE_READ_RSP_CQID(x) ((x) << S_CPL_RDMA_CQE_READ_RSP_CQID) 3788 #define G_CPL_RDMA_CQE_READ_RSP_CQID(x) \ 3789 (((x) >> S_CPL_RDMA_CQE_READ_RSP_CQID) & M_CPL_RDMA_CQE_READ_RSP_CQID) 3790 3791 #define S_CPL_RDMA_CQE_READ_RSP_TID 8 3792 #define M_CPL_RDMA_CQE_READ_RSP_TID 0xfffff 3793 #define V_CPL_RDMA_CQE_READ_RSP_TID(x) ((x) << S_CPL_RDMA_CQE_READ_RSP_TID) 3794 #define G_CPL_RDMA_CQE_READ_RSP_TID(x) \ 3795 (((x) >> S_CPL_RDMA_CQE_READ_RSP_TID) & M_CPL_RDMA_CQE_READ_RSP_TID) 3796 3797 #define S_CPL_RDMA_CQE_READ_RSP_FLITCNT 0 3798 #define M_CPL_RDMA_CQE_READ_RSP_FLITCNT 0xff 3799 #define V_CPL_RDMA_CQE_READ_RSP_FLITCNT(x) \ 3800 ((x) << S_CPL_RDMA_CQE_READ_RSP_FLITCNT) 3801 #define G_CPL_RDMA_CQE_READ_RSP_FLITCNT(x) \ 3802 (((x) >> S_CPL_RDMA_CQE_READ_RSP_FLITCNT) & \ 3803 M_CPL_RDMA_CQE_READ_RSP_FLITCNT) 3804 3805 #define S_CPL_RDMA_CQE_READ_RSP_QPID 12 3806 #define M_CPL_RDMA_CQE_READ_RSP_QPID 0xfffff 3807 #define V_CPL_RDMA_CQE_READ_RSP_QPID(x) ((x) << S_CPL_RDMA_CQE_READ_RSP_QPID) 3808 #define G_CPL_RDMA_CQE_READ_RSP_QPID(x) \ 3809 (((x) >> S_CPL_RDMA_CQE_READ_RSP_QPID) & M_CPL_RDMA_CQE_READ_RSP_QPID) 3810 3811 #define S_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT 10 3812 #define M_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT 0x1 3813 #define V_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT(x) \ 3814 ((x) << S_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT) 3815 #define G_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT(x) \ 3816 (((x) >> S_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT) & \ 3817 M_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT) 3818 #define F_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT \ 3819 V_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT(1U) 3820 3821 #define S_CPL_RDMA_CQE_READ_RSP_STATUS 5 3822 #define M_CPL_RDMA_CQE_READ_RSP_STATUS 0x1f 3823 #define V_CPL_RDMA_CQE_READ_RSP_STATUS(x) \ 3824 ((x) << S_CPL_RDMA_CQE_READ_RSP_STATUS) 3825 #define G_CPL_RDMA_CQE_READ_RSP_STATUS(x) \ 3826 (((x) >> S_CPL_RDMA_CQE_READ_RSP_STATUS) & M_CPL_RDMA_CQE_READ_RSP_STATUS) 3827 3828 #define S_CPL_RDMA_CQE_READ_RSP_CQE_TYPE 4 3829 #define M_CPL_RDMA_CQE_READ_RSP_CQE_TYPE 0x1 3830 #define V_CPL_RDMA_CQE_READ_RSP_CQE_TYPE(x) \ 3831 ((x) << S_CPL_RDMA_CQE_READ_RSP_CQE_TYPE) 3832 #define G_CPL_RDMA_CQE_READ_RSP_CQE_TYPE(x) \ 3833 (((x) >> S_CPL_RDMA_CQE_READ_RSP_CQE_TYPE) & \ 3834 M_CPL_RDMA_CQE_READ_RSP_CQE_TYPE) 3835 #define F_CPL_RDMA_CQE_READ_RSP_CQE_TYPE V_CPL_RDMA_CQE_READ_RSP_CQE_TYPE(1U) 3836 3837 #define S_CPL_RDMA_CQE_READ_RSP_WR_TYPE 0 3838 #define M_CPL_RDMA_CQE_READ_RSP_WR_TYPE 0xf 3839 #define V_CPL_RDMA_CQE_READ_RSP_WR_TYPE(x) \ 3840 ((x) << S_CPL_RDMA_CQE_READ_RSP_WR_TYPE) 3841 #define G_CPL_RDMA_CQE_READ_RSP_WR_TYPE(x) \ 3842 (((x) >> S_CPL_RDMA_CQE_READ_RSP_WR_TYPE) & \ 3843 M_CPL_RDMA_CQE_READ_RSP_WR_TYPE) 3844 3845 struct cpl_rdma_cqe_err { 3846 WR_HDR; 3847 union opcode_tid ot; 3848 __be32 tid_flitcnt; 3849 __be32 qpid_to_wr_type; 3850 __be32 length; 3851 __be32 tag; 3852 __be32 msn; 3853 }; 3854 3855 #define S_CPL_RDMA_CQE_ERR_RSSCTRL 16 3856 #define M_CPL_RDMA_CQE_ERR_RSSCTRL 0xff 3857 #define V_CPL_RDMA_CQE_ERR_RSSCTRL(x) ((x) << S_CPL_RDMA_CQE_ERR_RSSCTRL) 3858 #define G_CPL_RDMA_CQE_ERR_RSSCTRL(x) \ 3859 (((x) >> S_CPL_RDMA_CQE_ERR_RSSCTRL) & M_CPL_RDMA_CQE_ERR_RSSCTRL) 3860 3861 #define S_CPL_RDMA_CQE_ERR_CQID 0 3862 #define M_CPL_RDMA_CQE_ERR_CQID 0xffff 3863 #define V_CPL_RDMA_CQE_ERR_CQID(x) ((x) << S_CPL_RDMA_CQE_ERR_CQID) 3864 #define G_CPL_RDMA_CQE_ERR_CQID(x) \ 3865 (((x) >> S_CPL_RDMA_CQE_ERR_CQID) & M_CPL_RDMA_CQE_ERR_CQID) 3866 3867 #define S_CPL_RDMA_CQE_ERR_TID 8 3868 #define M_CPL_RDMA_CQE_ERR_TID 0xfffff 3869 #define V_CPL_RDMA_CQE_ERR_TID(x) ((x) << S_CPL_RDMA_CQE_ERR_TID) 3870 #define G_CPL_RDMA_CQE_ERR_TID(x) \ 3871 (((x) >> S_CPL_RDMA_CQE_ERR_TID) & M_CPL_RDMA_CQE_ERR_TID) 3872 3873 #define S_CPL_RDMA_CQE_ERR_FLITCNT 0 3874 #define M_CPL_RDMA_CQE_ERR_FLITCNT 0xff 3875 #define V_CPL_RDMA_CQE_ERR_FLITCNT(x) ((x) << S_CPL_RDMA_CQE_ERR_FLITCNT) 3876 #define G_CPL_RDMA_CQE_ERR_FLITCNT(x) \ 3877 (((x) >> S_CPL_RDMA_CQE_ERR_FLITCNT) & M_CPL_RDMA_CQE_ERR_FLITCNT) 3878 3879 #define S_CPL_RDMA_CQE_ERR_QPID 12 3880 #define M_CPL_RDMA_CQE_ERR_QPID 0xfffff 3881 #define V_CPL_RDMA_CQE_ERR_QPID(x) ((x) << S_CPL_RDMA_CQE_ERR_QPID) 3882 #define G_CPL_RDMA_CQE_ERR_QPID(x) \ 3883 (((x) >> S_CPL_RDMA_CQE_ERR_QPID) & M_CPL_RDMA_CQE_ERR_QPID) 3884 3885 #define S_CPL_RDMA_CQE_ERR_GENERATION_BIT 10 3886 #define M_CPL_RDMA_CQE_ERR_GENERATION_BIT 0x1 3887 #define V_CPL_RDMA_CQE_ERR_GENERATION_BIT(x) \ 3888 ((x) << S_CPL_RDMA_CQE_ERR_GENERATION_BIT) 3889 #define G_CPL_RDMA_CQE_ERR_GENERATION_BIT(x) \ 3890 (((x) >> S_CPL_RDMA_CQE_ERR_GENERATION_BIT) & \ 3891 M_CPL_RDMA_CQE_ERR_GENERATION_BIT) 3892 #define F_CPL_RDMA_CQE_ERR_GENERATION_BIT \ 3893 V_CPL_RDMA_CQE_ERR_GENERATION_BIT(1U) 3894 3895 #define S_CPL_RDMA_CQE_ERR_STATUS 5 3896 #define M_CPL_RDMA_CQE_ERR_STATUS 0x1f 3897 #define V_CPL_RDMA_CQE_ERR_STATUS(x) ((x) << S_CPL_RDMA_CQE_ERR_STATUS) 3898 #define G_CPL_RDMA_CQE_ERR_STATUS(x) \ 3899 (((x) >> S_CPL_RDMA_CQE_ERR_STATUS) & M_CPL_RDMA_CQE_ERR_STATUS) 3900 3901 #define S_CPL_RDMA_CQE_ERR_CQE_TYPE 4 3902 #define M_CPL_RDMA_CQE_ERR_CQE_TYPE 0x1 3903 #define V_CPL_RDMA_CQE_ERR_CQE_TYPE(x) ((x) << S_CPL_RDMA_CQE_ERR_CQE_TYPE) 3904 #define G_CPL_RDMA_CQE_ERR_CQE_TYPE(x) \ 3905 (((x) >> S_CPL_RDMA_CQE_ERR_CQE_TYPE) & M_CPL_RDMA_CQE_ERR_CQE_TYPE) 3906 #define F_CPL_RDMA_CQE_ERR_CQE_TYPE V_CPL_RDMA_CQE_ERR_CQE_TYPE(1U) 3907 3908 #define S_CPL_RDMA_CQE_ERR_WR_TYPE 0 3909 #define M_CPL_RDMA_CQE_ERR_WR_TYPE 0xf 3910 #define V_CPL_RDMA_CQE_ERR_WR_TYPE(x) ((x) << S_CPL_RDMA_CQE_ERR_WR_TYPE) 3911 #define G_CPL_RDMA_CQE_ERR_WR_TYPE(x) \ 3912 (((x) >> S_CPL_RDMA_CQE_ERR_WR_TYPE) & M_CPL_RDMA_CQE_ERR_WR_TYPE) 3913 3914 struct cpl_rdma_read_req { 3915 WR_HDR; 3916 union opcode_tid ot; 3917 __be16 srq_pkd; 3918 __be16 length; 3919 }; 3920 3921 #define S_CPL_RDMA_READ_REQ_SRQ 0 3922 #define M_CPL_RDMA_READ_REQ_SRQ 0xfff 3923 #define V_CPL_RDMA_READ_REQ_SRQ(x) ((x) << S_CPL_RDMA_READ_REQ_SRQ) 3924 #define G_CPL_RDMA_READ_REQ_SRQ(x) \ 3925 (((x) >> S_CPL_RDMA_READ_REQ_SRQ) & M_CPL_RDMA_READ_REQ_SRQ) 3926 3927 struct cpl_rdma_terminate { 3928 RSS_HDR 3929 union opcode_tid ot; 3930 __be16 rsvd; 3931 __be16 len; 3932 }; 3933 3934 struct cpl_rdma_atomic_req { 3935 RSS_HDR 3936 union opcode_tid ot; 3937 __be16 opcode_srq; 3938 __be16 length; 3939 }; 3940 3941 #define S_CPL_RDMA_ATOMIC_REQ_OPCODE 12 3942 #define M_CPL_RDMA_ATOMIC_REQ_OPCODE 0xf 3943 #define V_CPL_RDMA_ATOMIC_REQ_OPCODE(x) ((x) << S_CPL_RDMA_ATOMIC_REQ_OPCODE) 3944 #define G_CPL_RDMA_ATOMIC_REQ_OPCODE(x) \ 3945 (((x) >> S_CPL_RDMA_ATOMIC_REQ_OPCODE) & M_CPL_RDMA_ATOMIC_REQ_OPCODE) 3946 3947 #define S_CPL_RDMA_ATOMIC_REQ_SRQ 0 3948 #define M_CPL_RDMA_ATOMIC_REQ_SRQ 0xfff 3949 #define V_CPL_RDMA_ATOMIC_REQ_SRQ(x) ((x) << S_CPL_RDMA_ATOMIC_REQ_SRQ) 3950 #define G_CPL_RDMA_ATOMIC_REQ_SRQ(x) \ 3951 (((x) >> S_CPL_RDMA_ATOMIC_REQ_SRQ) & M_CPL_RDMA_ATOMIC_REQ_SRQ) 3952 3953 struct cpl_rdma_atomic_rpl { 3954 RSS_HDR 3955 union opcode_tid ot; 3956 __be16 opcode_srq; 3957 __be16 length; 3958 }; 3959 3960 #define S_CPL_RDMA_ATOMIC_RPL_OPCODE 12 3961 #define M_CPL_RDMA_ATOMIC_RPL_OPCODE 0xf 3962 #define V_CPL_RDMA_ATOMIC_RPL_OPCODE(x) ((x) << S_CPL_RDMA_ATOMIC_RPL_OPCODE) 3963 #define G_CPL_RDMA_ATOMIC_RPL_OPCODE(x) \ 3964 (((x) >> S_CPL_RDMA_ATOMIC_RPL_OPCODE) & M_CPL_RDMA_ATOMIC_RPL_OPCODE) 3965 3966 #define S_CPL_RDMA_ATOMIC_RPL_SRQ 0 3967 #define M_CPL_RDMA_ATOMIC_RPL_SRQ 0xfff 3968 #define V_CPL_RDMA_ATOMIC_RPL_SRQ(x) ((x) << S_CPL_RDMA_ATOMIC_RPL_SRQ) 3969 #define G_CPL_RDMA_ATOMIC_RPL_SRQ(x) \ 3970 (((x) >> S_CPL_RDMA_ATOMIC_RPL_SRQ) & M_CPL_RDMA_ATOMIC_RPL_SRQ) 3971 3972 struct cpl_rdma_imm_data { 3973 RSS_HDR 3974 union opcode_tid ot; 3975 __be16 r; 3976 __be16 Length; 3977 }; 3978 3979 struct cpl_rdma_imm_data_se { 3980 RSS_HDR 3981 union opcode_tid ot; 3982 __be16 r; 3983 __be16 Length; 3984 }; 3985 3986 struct cpl_rdma_inv_req { 3987 WR_HDR; 3988 union opcode_tid ot; 3989 __be32 stag; 3990 __be32 cqid_pdid_hi; 3991 __be32 pdid_lo_qpid; 3992 }; 3993 3994 #define S_CPL_RDMA_INV_REQ_CQID 8 3995 #define M_CPL_RDMA_INV_REQ_CQID 0xfffff 3996 #define V_CPL_RDMA_INV_REQ_CQID(x) ((x) << S_CPL_RDMA_INV_REQ_CQID) 3997 #define G_CPL_RDMA_INV_REQ_CQID(x) \ 3998 (((x) >> S_CPL_RDMA_INV_REQ_CQID) & M_CPL_RDMA_INV_REQ_CQID) 3999 4000 #define S_CPL_RDMA_INV_REQ_PDID_HI 0 4001 #define M_CPL_RDMA_INV_REQ_PDID_HI 0xff 4002 #define V_CPL_RDMA_INV_REQ_PDID_HI(x) ((x) << S_CPL_RDMA_INV_REQ_PDID_HI) 4003 #define G_CPL_RDMA_INV_REQ_PDID_HI(x) \ 4004 (((x) >> S_CPL_RDMA_INV_REQ_PDID_HI) & M_CPL_RDMA_INV_REQ_PDID_HI) 4005 4006 #define S_CPL_RDMA_INV_REQ_PDID_LO 20 4007 #define M_CPL_RDMA_INV_REQ_PDID_LO 0xfff 4008 #define V_CPL_RDMA_INV_REQ_PDID_LO(x) ((x) << S_CPL_RDMA_INV_REQ_PDID_LO) 4009 #define G_CPL_RDMA_INV_REQ_PDID_LO(x) \ 4010 (((x) >> S_CPL_RDMA_INV_REQ_PDID_LO) & M_CPL_RDMA_INV_REQ_PDID_LO) 4011 4012 #define S_CPL_RDMA_INV_REQ_QPID 0 4013 #define M_CPL_RDMA_INV_REQ_QPID 0xfffff 4014 #define V_CPL_RDMA_INV_REQ_QPID(x) ((x) << S_CPL_RDMA_INV_REQ_QPID) 4015 #define G_CPL_RDMA_INV_REQ_QPID(x) \ 4016 (((x) >> S_CPL_RDMA_INV_REQ_QPID) & M_CPL_RDMA_INV_REQ_QPID) 4017 4018 struct cpl_rdma_cqe_ext { 4019 WR_HDR; 4020 union opcode_tid ot; 4021 __be32 tid_flitcnt; 4022 __be32 qpid_to_wr_type; 4023 __be32 length; 4024 __be32 tag; 4025 __be32 msn; 4026 __be32 se_to_srq; 4027 __be32 rqe; 4028 __be32 extinfoms[2]; 4029 __be32 extinfols[2]; 4030 }; 4031 4032 #define S_CPL_RDMA_CQE_EXT_RSSCTRL 16 4033 #define M_CPL_RDMA_CQE_EXT_RSSCTRL 0xff 4034 #define V_CPL_RDMA_CQE_EXT_RSSCTRL(x) ((x) << S_CPL_RDMA_CQE_EXT_RSSCTRL) 4035 #define G_CPL_RDMA_CQE_EXT_RSSCTRL(x) \ 4036 (((x) >> S_CPL_RDMA_CQE_EXT_RSSCTRL) & M_CPL_RDMA_CQE_EXT_RSSCTRL) 4037 4038 #define S_CPL_RDMA_CQE_EXT_CQID 0 4039 #define M_CPL_RDMA_CQE_EXT_CQID 0xffff 4040 #define V_CPL_RDMA_CQE_EXT_CQID(x) ((x) << S_CPL_RDMA_CQE_EXT_CQID) 4041 #define G_CPL_RDMA_CQE_EXT_CQID(x) \ 4042 (((x) >> S_CPL_RDMA_CQE_EXT_CQID) & M_CPL_RDMA_CQE_EXT_CQID) 4043 4044 #define S_CPL_RDMA_CQE_EXT_TID 8 4045 #define M_CPL_RDMA_CQE_EXT_TID 0xfffff 4046 #define V_CPL_RDMA_CQE_EXT_TID(x) ((x) << S_CPL_RDMA_CQE_EXT_TID) 4047 #define G_CPL_RDMA_CQE_EXT_TID(x) \ 4048 (((x) >> S_CPL_RDMA_CQE_EXT_TID) & M_CPL_RDMA_CQE_EXT_TID) 4049 4050 #define S_CPL_RDMA_CQE_EXT_FLITCNT 0 4051 #define M_CPL_RDMA_CQE_EXT_FLITCNT 0xff 4052 #define V_CPL_RDMA_CQE_EXT_FLITCNT(x) ((x) << S_CPL_RDMA_CQE_EXT_FLITCNT) 4053 #define G_CPL_RDMA_CQE_EXT_FLITCNT(x) \ 4054 (((x) >> S_CPL_RDMA_CQE_EXT_FLITCNT) & M_CPL_RDMA_CQE_EXT_FLITCNT) 4055 4056 #define S_CPL_RDMA_CQE_EXT_QPID 12 4057 #define M_CPL_RDMA_CQE_EXT_QPID 0xfffff 4058 #define V_CPL_RDMA_CQE_EXT_QPID(x) ((x) << S_CPL_RDMA_CQE_EXT_QPID) 4059 #define G_CPL_RDMA_CQE_EXT_QPID(x) \ 4060 (((x) >> S_CPL_RDMA_CQE_EXT_QPID) & M_CPL_RDMA_CQE_EXT_QPID) 4061 4062 #define S_CPL_RDMA_CQE_EXT_EXTMODE 11 4063 #define M_CPL_RDMA_CQE_EXT_EXTMODE 0x1 4064 #define V_CPL_RDMA_CQE_EXT_EXTMODE(x) ((x) << S_CPL_RDMA_CQE_EXT_EXTMODE) 4065 #define G_CPL_RDMA_CQE_EXT_EXTMODE(x) \ 4066 (((x) >> S_CPL_RDMA_CQE_EXT_EXTMODE) & M_CPL_RDMA_CQE_EXT_EXTMODE) 4067 #define F_CPL_RDMA_CQE_EXT_EXTMODE V_CPL_RDMA_CQE_EXT_EXTMODE(1U) 4068 4069 #define S_CPL_RDMA_CQE_EXT_GENERATION_BIT 10 4070 #define M_CPL_RDMA_CQE_EXT_GENERATION_BIT 0x1 4071 #define V_CPL_RDMA_CQE_EXT_GENERATION_BIT(x) \ 4072 ((x) << S_CPL_RDMA_CQE_EXT_GENERATION_BIT) 4073 #define G_CPL_RDMA_CQE_EXT_GENERATION_BIT(x) \ 4074 (((x) >> S_CPL_RDMA_CQE_EXT_GENERATION_BIT) & \ 4075 M_CPL_RDMA_CQE_EXT_GENERATION_BIT) 4076 #define F_CPL_RDMA_CQE_EXT_GENERATION_BIT \ 4077 V_CPL_RDMA_CQE_EXT_GENERATION_BIT(1U) 4078 4079 #define S_CPL_RDMA_CQE_EXT_STATUS 5 4080 #define M_CPL_RDMA_CQE_EXT_STATUS 0x1f 4081 #define V_CPL_RDMA_CQE_EXT_STATUS(x) ((x) << S_CPL_RDMA_CQE_EXT_STATUS) 4082 #define G_CPL_RDMA_CQE_EXT_STATUS(x) \ 4083 (((x) >> S_CPL_RDMA_CQE_EXT_STATUS) & M_CPL_RDMA_CQE_EXT_STATUS) 4084 4085 #define S_CPL_RDMA_CQE_EXT_CQE_TYPE 4 4086 #define M_CPL_RDMA_CQE_EXT_CQE_TYPE 0x1 4087 #define V_CPL_RDMA_CQE_EXT_CQE_TYPE(x) ((x) << S_CPL_RDMA_CQE_EXT_CQE_TYPE) 4088 #define G_CPL_RDMA_CQE_EXT_CQE_TYPE(x) \ 4089 (((x) >> S_CPL_RDMA_CQE_EXT_CQE_TYPE) & M_CPL_RDMA_CQE_EXT_CQE_TYPE) 4090 #define F_CPL_RDMA_CQE_EXT_CQE_TYPE V_CPL_RDMA_CQE_EXT_CQE_TYPE(1U) 4091 4092 #define S_CPL_RDMA_CQE_EXT_WR_TYPE 0 4093 #define M_CPL_RDMA_CQE_EXT_WR_TYPE 0xf 4094 #define V_CPL_RDMA_CQE_EXT_WR_TYPE(x) ((x) << S_CPL_RDMA_CQE_EXT_WR_TYPE) 4095 #define G_CPL_RDMA_CQE_EXT_WR_TYPE(x) \ 4096 (((x) >> S_CPL_RDMA_CQE_EXT_WR_TYPE) & M_CPL_RDMA_CQE_EXT_WR_TYPE) 4097 4098 #define S_CPL_RDMA_CQE_EXT_SE 31 4099 #define M_CPL_RDMA_CQE_EXT_SE 0x1 4100 #define V_CPL_RDMA_CQE_EXT_SE(x) ((x) << S_CPL_RDMA_CQE_EXT_SE) 4101 #define G_CPL_RDMA_CQE_EXT_SE(x) \ 4102 (((x) >> S_CPL_RDMA_CQE_EXT_SE) & M_CPL_RDMA_CQE_EXT_SE) 4103 #define F_CPL_RDMA_CQE_EXT_SE V_CPL_RDMA_CQE_EXT_SE(1U) 4104 4105 #define S_CPL_RDMA_CQE_EXT_WR_TYPE_EXT 24 4106 #define M_CPL_RDMA_CQE_EXT_WR_TYPE_EXT 0x7f 4107 #define V_CPL_RDMA_CQE_EXT_WR_TYPE_EXT(x) \ 4108 ((x) << S_CPL_RDMA_CQE_EXT_WR_TYPE_EXT) 4109 #define G_CPL_RDMA_CQE_EXT_WR_TYPE_EXT(x) \ 4110 (((x) >> S_CPL_RDMA_CQE_EXT_WR_TYPE_EXT) & M_CPL_RDMA_CQE_EXT_WR_TYPE_EXT) 4111 4112 #define S_CPL_RDMA_CQE_EXT_SRQ 0 4113 #define M_CPL_RDMA_CQE_EXT_SRQ 0xfff 4114 #define V_CPL_RDMA_CQE_EXT_SRQ(x) ((x) << S_CPL_RDMA_CQE_EXT_SRQ) 4115 #define G_CPL_RDMA_CQE_EXT_SRQ(x) \ 4116 (((x) >> S_CPL_RDMA_CQE_EXT_SRQ) & M_CPL_RDMA_CQE_EXT_SRQ) 4117 4118 struct cpl_rdma_cqe_fw_ext { 4119 WR_HDR; 4120 union opcode_tid ot; 4121 __be32 tid_flitcnt; 4122 __be32 qpid_to_wr_type; 4123 __be32 length; 4124 __be32 tag; 4125 __be32 msn; 4126 __be32 se_to_srq; 4127 __be32 rqe; 4128 __be32 extinfoms[2]; 4129 __be32 extinfols[2]; 4130 }; 4131 4132 #define S_CPL_RDMA_CQE_FW_EXT_RSSCTRL 16 4133 #define M_CPL_RDMA_CQE_FW_EXT_RSSCTRL 0xff 4134 #define V_CPL_RDMA_CQE_FW_EXT_RSSCTRL(x) \ 4135 ((x) << S_CPL_RDMA_CQE_FW_EXT_RSSCTRL) 4136 #define G_CPL_RDMA_CQE_FW_EXT_RSSCTRL(x) \ 4137 (((x) >> S_CPL_RDMA_CQE_FW_EXT_RSSCTRL) & M_CPL_RDMA_CQE_FW_EXT_RSSCTRL) 4138 4139 #define S_CPL_RDMA_CQE_FW_EXT_CQID 0 4140 #define M_CPL_RDMA_CQE_FW_EXT_CQID 0xffff 4141 #define V_CPL_RDMA_CQE_FW_EXT_CQID(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_CQID) 4142 #define G_CPL_RDMA_CQE_FW_EXT_CQID(x) \ 4143 (((x) >> S_CPL_RDMA_CQE_FW_EXT_CQID) & M_CPL_RDMA_CQE_FW_EXT_CQID) 4144 4145 #define S_CPL_RDMA_CQE_FW_EXT_TID 8 4146 #define M_CPL_RDMA_CQE_FW_EXT_TID 0xfffff 4147 #define V_CPL_RDMA_CQE_FW_EXT_TID(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_TID) 4148 #define G_CPL_RDMA_CQE_FW_EXT_TID(x) \ 4149 (((x) >> S_CPL_RDMA_CQE_FW_EXT_TID) & M_CPL_RDMA_CQE_FW_EXT_TID) 4150 4151 #define S_CPL_RDMA_CQE_FW_EXT_FLITCNT 0 4152 #define M_CPL_RDMA_CQE_FW_EXT_FLITCNT 0xff 4153 #define V_CPL_RDMA_CQE_FW_EXT_FLITCNT(x) \ 4154 ((x) << S_CPL_RDMA_CQE_FW_EXT_FLITCNT) 4155 #define G_CPL_RDMA_CQE_FW_EXT_FLITCNT(x) \ 4156 (((x) >> S_CPL_RDMA_CQE_FW_EXT_FLITCNT) & M_CPL_RDMA_CQE_FW_EXT_FLITCNT) 4157 4158 #define S_CPL_RDMA_CQE_FW_EXT_QPID 12 4159 #define M_CPL_RDMA_CQE_FW_EXT_QPID 0xfffff 4160 #define V_CPL_RDMA_CQE_FW_EXT_QPID(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_QPID) 4161 #define G_CPL_RDMA_CQE_FW_EXT_QPID(x) \ 4162 (((x) >> S_CPL_RDMA_CQE_FW_EXT_QPID) & M_CPL_RDMA_CQE_FW_EXT_QPID) 4163 4164 #define S_CPL_RDMA_CQE_FW_EXT_EXTMODE 11 4165 #define M_CPL_RDMA_CQE_FW_EXT_EXTMODE 0x1 4166 #define V_CPL_RDMA_CQE_FW_EXT_EXTMODE(x) \ 4167 ((x) << S_CPL_RDMA_CQE_FW_EXT_EXTMODE) 4168 #define G_CPL_RDMA_CQE_FW_EXT_EXTMODE(x) \ 4169 (((x) >> S_CPL_RDMA_CQE_FW_EXT_EXTMODE) & M_CPL_RDMA_CQE_FW_EXT_EXTMODE) 4170 #define F_CPL_RDMA_CQE_FW_EXT_EXTMODE V_CPL_RDMA_CQE_FW_EXT_EXTMODE(1U) 4171 4172 #define S_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT 10 4173 #define M_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT 0x1 4174 #define V_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT(x) \ 4175 ((x) << S_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT) 4176 #define G_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT(x) \ 4177 (((x) >> S_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT) & \ 4178 M_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT) 4179 #define F_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT \ 4180 V_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT(1U) 4181 4182 #define S_CPL_RDMA_CQE_FW_EXT_STATUS 5 4183 #define M_CPL_RDMA_CQE_FW_EXT_STATUS 0x1f 4184 #define V_CPL_RDMA_CQE_FW_EXT_STATUS(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_STATUS) 4185 #define G_CPL_RDMA_CQE_FW_EXT_STATUS(x) \ 4186 (((x) >> S_CPL_RDMA_CQE_FW_EXT_STATUS) & M_CPL_RDMA_CQE_FW_EXT_STATUS) 4187 4188 #define S_CPL_RDMA_CQE_FW_EXT_CQE_TYPE 4 4189 #define M_CPL_RDMA_CQE_FW_EXT_CQE_TYPE 0x1 4190 #define V_CPL_RDMA_CQE_FW_EXT_CQE_TYPE(x) \ 4191 ((x) << S_CPL_RDMA_CQE_FW_EXT_CQE_TYPE) 4192 #define G_CPL_RDMA_CQE_FW_EXT_CQE_TYPE(x) \ 4193 (((x) >> S_CPL_RDMA_CQE_FW_EXT_CQE_TYPE) & M_CPL_RDMA_CQE_FW_EXT_CQE_TYPE) 4194 #define F_CPL_RDMA_CQE_FW_EXT_CQE_TYPE V_CPL_RDMA_CQE_FW_EXT_CQE_TYPE(1U) 4195 4196 #define S_CPL_RDMA_CQE_FW_EXT_WR_TYPE 0 4197 #define M_CPL_RDMA_CQE_FW_EXT_WR_TYPE 0xf 4198 #define V_CPL_RDMA_CQE_FW_EXT_WR_TYPE(x) \ 4199 ((x) << S_CPL_RDMA_CQE_FW_EXT_WR_TYPE) 4200 #define G_CPL_RDMA_CQE_FW_EXT_WR_TYPE(x) \ 4201 (((x) >> S_CPL_RDMA_CQE_FW_EXT_WR_TYPE) & M_CPL_RDMA_CQE_FW_EXT_WR_TYPE) 4202 4203 #define S_CPL_RDMA_CQE_FW_EXT_SE 31 4204 #define M_CPL_RDMA_CQE_FW_EXT_SE 0x1 4205 #define V_CPL_RDMA_CQE_FW_EXT_SE(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_SE) 4206 #define G_CPL_RDMA_CQE_FW_EXT_SE(x) \ 4207 (((x) >> S_CPL_RDMA_CQE_FW_EXT_SE) & M_CPL_RDMA_CQE_FW_EXT_SE) 4208 #define F_CPL_RDMA_CQE_FW_EXT_SE V_CPL_RDMA_CQE_FW_EXT_SE(1U) 4209 4210 #define S_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT 24 4211 #define M_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT 0x7f 4212 #define V_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT(x) \ 4213 ((x) << S_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT) 4214 #define G_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT(x) \ 4215 (((x) >> S_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT) & \ 4216 M_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT) 4217 4218 #define S_CPL_RDMA_CQE_FW_EXT_SRQ 0 4219 #define M_CPL_RDMA_CQE_FW_EXT_SRQ 0xfff 4220 #define V_CPL_RDMA_CQE_FW_EXT_SRQ(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_SRQ) 4221 #define G_CPL_RDMA_CQE_FW_EXT_SRQ(x) \ 4222 (((x) >> S_CPL_RDMA_CQE_FW_EXT_SRQ) & M_CPL_RDMA_CQE_FW_EXT_SRQ) 4223 4224 struct cpl_rdma_cqe_err_ext { 4225 WR_HDR; 4226 union opcode_tid ot; 4227 __be32 tid_flitcnt; 4228 __be32 qpid_to_wr_type; 4229 __be32 length; 4230 __be32 tag; 4231 __be32 msn; 4232 __be32 se_to_srq; 4233 __be32 rqe; 4234 __be32 extinfoms[2]; 4235 __be32 extinfols[2]; 4236 }; 4237 4238 #define S_CPL_RDMA_CQE_ERR_EXT_RSSCTRL 16 4239 #define M_CPL_RDMA_CQE_ERR_EXT_RSSCTRL 0xff 4240 #define V_CPL_RDMA_CQE_ERR_EXT_RSSCTRL(x) \ 4241 ((x) << S_CPL_RDMA_CQE_ERR_EXT_RSSCTRL) 4242 #define G_CPL_RDMA_CQE_ERR_EXT_RSSCTRL(x) \ 4243 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_RSSCTRL) & M_CPL_RDMA_CQE_ERR_EXT_RSSCTRL) 4244 4245 #define S_CPL_RDMA_CQE_ERR_EXT_CQID 0 4246 #define M_CPL_RDMA_CQE_ERR_EXT_CQID 0xffff 4247 #define V_CPL_RDMA_CQE_ERR_EXT_CQID(x) ((x) << S_CPL_RDMA_CQE_ERR_EXT_CQID) 4248 #define G_CPL_RDMA_CQE_ERR_EXT_CQID(x) \ 4249 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_CQID) & M_CPL_RDMA_CQE_ERR_EXT_CQID) 4250 4251 #define S_CPL_RDMA_CQE_ERR_EXT_TID 8 4252 #define M_CPL_RDMA_CQE_ERR_EXT_TID 0xfffff 4253 #define V_CPL_RDMA_CQE_ERR_EXT_TID(x) ((x) << S_CPL_RDMA_CQE_ERR_EXT_TID) 4254 #define G_CPL_RDMA_CQE_ERR_EXT_TID(x) \ 4255 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_TID) & M_CPL_RDMA_CQE_ERR_EXT_TID) 4256 4257 #define S_CPL_RDMA_CQE_ERR_EXT_FLITCNT 0 4258 #define M_CPL_RDMA_CQE_ERR_EXT_FLITCNT 0xff 4259 #define V_CPL_RDMA_CQE_ERR_EXT_FLITCNT(x) \ 4260 ((x) << S_CPL_RDMA_CQE_ERR_EXT_FLITCNT) 4261 #define G_CPL_RDMA_CQE_ERR_EXT_FLITCNT(x) \ 4262 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_FLITCNT) & M_CPL_RDMA_CQE_ERR_EXT_FLITCNT) 4263 4264 #define S_CPL_RDMA_CQE_ERR_EXT_QPID 12 4265 #define M_CPL_RDMA_CQE_ERR_EXT_QPID 0xfffff 4266 #define V_CPL_RDMA_CQE_ERR_EXT_QPID(x) ((x) << S_CPL_RDMA_CQE_ERR_EXT_QPID) 4267 #define G_CPL_RDMA_CQE_ERR_EXT_QPID(x) \ 4268 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_QPID) & M_CPL_RDMA_CQE_ERR_EXT_QPID) 4269 4270 #define S_CPL_RDMA_CQE_ERR_EXT_EXTMODE 11 4271 #define M_CPL_RDMA_CQE_ERR_EXT_EXTMODE 0x1 4272 #define V_CPL_RDMA_CQE_ERR_EXT_EXTMODE(x) \ 4273 ((x) << S_CPL_RDMA_CQE_ERR_EXT_EXTMODE) 4274 #define G_CPL_RDMA_CQE_ERR_EXT_EXTMODE(x) \ 4275 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_EXTMODE) & M_CPL_RDMA_CQE_ERR_EXT_EXTMODE) 4276 #define F_CPL_RDMA_CQE_ERR_EXT_EXTMODE V_CPL_RDMA_CQE_ERR_EXT_EXTMODE(1U) 4277 4278 #define S_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT 10 4279 #define M_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT 0x1 4280 #define V_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT(x) \ 4281 ((x) << S_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT) 4282 #define G_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT(x) \ 4283 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT) & \ 4284 M_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT) 4285 #define F_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT \ 4286 V_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT(1U) 4287 4288 #define S_CPL_RDMA_CQE_ERR_EXT_STATUS 5 4289 #define M_CPL_RDMA_CQE_ERR_EXT_STATUS 0x1f 4290 #define V_CPL_RDMA_CQE_ERR_EXT_STATUS(x) \ 4291 ((x) << S_CPL_RDMA_CQE_ERR_EXT_STATUS) 4292 #define G_CPL_RDMA_CQE_ERR_EXT_STATUS(x) \ 4293 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_STATUS) & M_CPL_RDMA_CQE_ERR_EXT_STATUS) 4294 4295 #define S_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE 4 4296 #define M_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE 0x1 4297 #define V_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE(x) \ 4298 ((x) << S_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE) 4299 #define G_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE(x) \ 4300 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE) & \ 4301 M_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE) 4302 #define F_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE V_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE(1U) 4303 4304 #define S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE 0 4305 #define M_CPL_RDMA_CQE_ERR_EXT_WR_TYPE 0xf 4306 #define V_CPL_RDMA_CQE_ERR_EXT_WR_TYPE(x) \ 4307 ((x) << S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE) 4308 #define G_CPL_RDMA_CQE_ERR_EXT_WR_TYPE(x) \ 4309 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE) & M_CPL_RDMA_CQE_ERR_EXT_WR_TYPE) 4310 4311 #define S_CPL_RDMA_CQE_ERR_EXT_SE 31 4312 #define M_CPL_RDMA_CQE_ERR_EXT_SE 0x1 4313 #define V_CPL_RDMA_CQE_ERR_EXT_SE(x) ((x) << S_CPL_RDMA_CQE_ERR_EXT_SE) 4314 #define G_CPL_RDMA_CQE_ERR_EXT_SE(x) \ 4315 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_SE) & M_CPL_RDMA_CQE_ERR_EXT_SE) 4316 #define F_CPL_RDMA_CQE_ERR_EXT_SE V_CPL_RDMA_CQE_ERR_EXT_SE(1U) 4317 4318 #define S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT 24 4319 #define M_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT 0x7f 4320 #define V_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT(x) \ 4321 ((x) << S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT) 4322 #define G_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT(x) \ 4323 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT) & \ 4324 M_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT) 4325 4326 #define S_CPL_RDMA_CQE_ERR_EXT_SRQ 0 4327 #define M_CPL_RDMA_CQE_ERR_EXT_SRQ 0xfff 4328 #define V_CPL_RDMA_CQE_ERR_EXT_SRQ(x) ((x) << S_CPL_RDMA_CQE_ERR_EXT_SRQ) 4329 #define G_CPL_RDMA_CQE_ERR_EXT_SRQ(x) \ 4330 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_SRQ) & M_CPL_RDMA_CQE_ERR_EXT_SRQ) 4331 4332 struct cpl_set_le_req { 4333 WR_HDR; 4334 union opcode_tid ot; 4335 __be16 reply_ctrl; 4336 __be16 params; 4337 __be64 mask_hi; 4338 __be64 mask_lo; 4339 __be64 val_hi; 4340 __be64 val_lo; 4341 }; 4342 4343 /* cpl_set_le_req.reply_ctrl additional fields */ 4344 #define S_LE_REQ_RXCHANNEL 14 4345 #define M_LE_REQ_RXCHANNEL 0x1 4346 #define V_LE_REQ_RXCHANNEL(x) ((x) << S_LE_REQ_RXCHANNEL) 4347 #define G_LE_REQ_RXCHANNEL(x) \ 4348 (((x) >> S_LE_REQ_RXCHANNEL) & M_LE_REQ_RXCHANNEL) 4349 #define F_LE_REQ_RXCHANNEL V_LE_REQ_RXCHANNEL(1U) 4350 4351 #define S_LE_REQ_IP6 13 4352 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 4353 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 4354 4355 /* cpl_set_le_req.params fields */ 4356 #define S_LE_CHAN 0 4357 #define M_LE_CHAN 0x3 4358 #define V_LE_CHAN(x) ((x) << S_LE_CHAN) 4359 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 4360 4361 #define S_LE_OFFSET 5 4362 #define M_LE_OFFSET 0x7 4363 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 4364 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 4365 4366 #define S_LE_MORE 8 4367 #define V_LE_MORE(x) ((x) << S_LE_MORE) 4368 #define F_LE_MORE V_LE_MORE(1U) 4369 4370 #define S_LE_REQSIZE 9 4371 #define M_LE_REQSIZE 0x7 4372 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 4373 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 4374 4375 #define S_LE_REQCMD 12 4376 #define M_LE_REQCMD 0xF 4377 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 4378 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 4379 4380 struct cpl_t7_set_le_req { 4381 WR_HDR; 4382 union opcode_tid ot; 4383 __be32 noreply_to_channel; 4384 __be32 mask1[2]; 4385 __be32 mask0[2]; 4386 __be32 value1[2]; 4387 __be32 value0[2]; 4388 }; 4389 4390 #define S_CPL_T7_SET_LE_REQ_INDEX 0 4391 #define M_CPL_T7_SET_LE_REQ_INDEX 0xffffff 4392 #define V_CPL_T7_SET_LE_REQ_INDEX(x) ((x) << S_CPL_T7_SET_LE_REQ_INDEX) 4393 #define G_CPL_T7_SET_LE_REQ_INDEX(x) \ 4394 (((x) >> S_CPL_T7_SET_LE_REQ_INDEX) & M_CPL_T7_SET_LE_REQ_INDEX) 4395 4396 #define S_CPL_T7_SET_LE_REQ_NOREPLY 31 4397 #define M_CPL_T7_SET_LE_REQ_NOREPLY 0x1 4398 #define V_CPL_T7_SET_LE_REQ_NOREPLY(x) ((x) << S_CPL_T7_SET_LE_REQ_NOREPLY) 4399 #define G_CPL_T7_SET_LE_REQ_NOREPLY(x) \ 4400 (((x) >> S_CPL_T7_SET_LE_REQ_NOREPLY) & M_CPL_T7_SET_LE_REQ_NOREPLY) 4401 #define F_CPL_T7_SET_LE_REQ_NOREPLY V_CPL_T7_SET_LE_REQ_NOREPLY(1U) 4402 4403 #define S_CPL_T7_SET_LE_REQ_RXCHANNEL 28 4404 #define M_CPL_T7_SET_LE_REQ_RXCHANNEL 0x7 4405 #define V_CPL_T7_SET_LE_REQ_RXCHANNEL(x) \ 4406 ((x) << S_CPL_T7_SET_LE_REQ_RXCHANNEL) 4407 #define G_CPL_T7_SET_LE_REQ_RXCHANNEL(x) \ 4408 (((x) >> S_CPL_T7_SET_LE_REQ_RXCHANNEL) & M_CPL_T7_SET_LE_REQ_RXCHANNEL) 4409 4410 #define S_CPL_T7_SET_LE_REQ_QUEUE 16 4411 #define M_CPL_T7_SET_LE_REQ_QUEUE 0xfff 4412 #define V_CPL_T7_SET_LE_REQ_QUEUE(x) ((x) << S_CPL_T7_SET_LE_REQ_QUEUE) 4413 #define G_CPL_T7_SET_LE_REQ_QUEUE(x) \ 4414 (((x) >> S_CPL_T7_SET_LE_REQ_QUEUE) & M_CPL_T7_SET_LE_REQ_QUEUE) 4415 4416 #define S_CPL_T7_SET_LE_REQ_REQCMD 12 4417 #define M_CPL_T7_SET_LE_REQ_REQCMD 0xf 4418 #define V_CPL_T7_SET_LE_REQ_REQCMD(x) ((x) << S_CPL_T7_SET_LE_REQ_REQCMD) 4419 #define G_CPL_T7_SET_LE_REQ_REQCMD(x) \ 4420 (((x) >> S_CPL_T7_SET_LE_REQ_REQCMD) & M_CPL_T7_SET_LE_REQ_REQCMD) 4421 4422 #define S_CPL_T7_SET_LE_REQ_REQSIZE 9 4423 #define M_CPL_T7_SET_LE_REQ_REQSIZE 0x7 4424 #define V_CPL_T7_SET_LE_REQ_REQSIZE(x) ((x) << S_CPL_T7_SET_LE_REQ_REQSIZE) 4425 #define G_CPL_T7_SET_LE_REQ_REQSIZE(x) \ 4426 (((x) >> S_CPL_T7_SET_LE_REQ_REQSIZE) & M_CPL_T7_SET_LE_REQ_REQSIZE) 4427 4428 #define S_CPL_T7_SET_LE_REQ_MORE 8 4429 #define M_CPL_T7_SET_LE_REQ_MORE 0x1 4430 #define V_CPL_T7_SET_LE_REQ_MORE(x) ((x) << S_CPL_T7_SET_LE_REQ_MORE) 4431 #define G_CPL_T7_SET_LE_REQ_MORE(x) \ 4432 (((x) >> S_CPL_T7_SET_LE_REQ_MORE) & M_CPL_T7_SET_LE_REQ_MORE) 4433 #define F_CPL_T7_SET_LE_REQ_MORE V_CPL_T7_SET_LE_REQ_MORE(1U) 4434 4435 #define S_CPL_T7_SET_LE_REQ_OFFSET 5 4436 #define M_CPL_T7_SET_LE_REQ_OFFSET 0x7 4437 #define V_CPL_T7_SET_LE_REQ_OFFSET(x) ((x) << S_CPL_T7_SET_LE_REQ_OFFSET) 4438 #define G_CPL_T7_SET_LE_REQ_OFFSET(x) \ 4439 (((x) >> S_CPL_T7_SET_LE_REQ_OFFSET) & M_CPL_T7_SET_LE_REQ_OFFSET) 4440 4441 #define S_CPL_T7_SET_LE_REQ_REQTYPE 4 4442 #define M_CPL_T7_SET_LE_REQ_REQTYPE 0x1 4443 #define V_CPL_T7_SET_LE_REQ_REQTYPE(x) ((x) << S_CPL_T7_SET_LE_REQ_REQTYPE) 4444 #define G_CPL_T7_SET_LE_REQ_REQTYPE(x) \ 4445 (((x) >> S_CPL_T7_SET_LE_REQ_REQTYPE) & M_CPL_T7_SET_LE_REQ_REQTYPE) 4446 #define F_CPL_T7_SET_LE_REQ_REQTYPE V_CPL_T7_SET_LE_REQ_REQTYPE(1U) 4447 4448 #define S_CPL_T7_SET_LE_REQ_CHANNEL 0 4449 #define M_CPL_T7_SET_LE_REQ_CHANNEL 0x3 4450 #define V_CPL_T7_SET_LE_REQ_CHANNEL(x) ((x) << S_CPL_T7_SET_LE_REQ_CHANNEL) 4451 #define G_CPL_T7_SET_LE_REQ_CHANNEL(x) \ 4452 (((x) >> S_CPL_T7_SET_LE_REQ_CHANNEL) & M_CPL_T7_SET_LE_REQ_CHANNEL) 4453 4454 struct cpl_set_le_rpl { 4455 RSS_HDR 4456 union opcode_tid ot; 4457 __u8 chan; 4458 __u8 info; 4459 __be16 len; 4460 }; 4461 4462 /* cpl_set_le_rpl.info fields */ 4463 #define S_LE_RSPCMD 0 4464 #define M_LE_RSPCMD 0xF 4465 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 4466 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 4467 4468 #define S_LE_RSPSIZE 4 4469 #define M_LE_RSPSIZE 0x7 4470 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 4471 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 4472 4473 #define S_LE_RSPTYPE 7 4474 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 4475 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 4476 4477 struct cpl_sge_egr_update { 4478 RSS_HDR 4479 __be32 opcode_qid; 4480 __be16 cidx; 4481 __be16 pidx; 4482 }; 4483 4484 /* cpl_sge_egr_update.ot fields */ 4485 #define S_AUTOEQU 22 4486 #define M_AUTOEQU 0x1 4487 #define V_AUTOEQU(x) ((x) << S_AUTOEQU) 4488 #define G_AUTOEQU(x) (((x) >> S_AUTOEQU) & M_AUTOEQU) 4489 4490 #define S_EGR_QID 0 4491 #define M_EGR_QID 0x1FFFF 4492 #define V_EGR_QID(x) ((x) << S_EGR_QID) 4493 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 4494 4495 /* cpl_fw*.type values */ 4496 enum { 4497 FW_TYPE_CMD_RPL = 0, 4498 FW_TYPE_WR_RPL = 1, 4499 FW_TYPE_CQE = 2, 4500 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 4501 FW_TYPE_RSSCPL = 4, 4502 FW_TYPE_WRERR_RPL = 5, 4503 FW_TYPE_PI_ERR = 6, 4504 FW_TYPE_TLS_KEY = 7, 4505 FW_TYPE_IPSEC_SA = 8, 4506 }; 4507 4508 struct cpl_fw2_pld { 4509 RSS_HDR 4510 u8 opcode; 4511 u8 rsvd[5]; 4512 __be16 len; 4513 }; 4514 4515 struct cpl_fw4_pld { 4516 RSS_HDR 4517 u8 opcode; 4518 u8 rsvd0[3]; 4519 u8 type; 4520 u8 rsvd1; 4521 __be16 len; 4522 __be64 data; 4523 __be64 rsvd2; 4524 }; 4525 4526 struct cpl_fw6_pld { 4527 RSS_HDR 4528 u8 opcode; 4529 u8 rsvd[5]; 4530 __be16 len; 4531 __be64 data[4]; 4532 }; 4533 4534 struct cpl_fw2_msg { 4535 RSS_HDR 4536 union opcode_info oi; 4537 }; 4538 4539 struct cpl_fw4_msg { 4540 RSS_HDR 4541 u8 opcode; 4542 u8 type; 4543 __be16 rsvd0; 4544 __be32 rsvd1; 4545 __be64 data[2]; 4546 }; 4547 4548 struct cpl_fw4_ack { 4549 RSS_HDR 4550 union opcode_tid ot; 4551 u8 credits; 4552 u8 rsvd0[2]; 4553 u8 flags; 4554 __be32 snd_nxt; 4555 __be32 snd_una; 4556 __be64 rsvd1; 4557 }; 4558 4559 enum { 4560 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 4561 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 4562 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 4563 }; 4564 4565 #define S_CPL_FW4_ACK_OPCODE 24 4566 #define M_CPL_FW4_ACK_OPCODE 0xff 4567 #define V_CPL_FW4_ACK_OPCODE(x) ((x) << S_CPL_FW4_ACK_OPCODE) 4568 #define G_CPL_FW4_ACK_OPCODE(x) \ 4569 (((x) >> S_CPL_FW4_ACK_OPCODE) & M_CPL_FW4_ACK_OPCODE) 4570 4571 #define S_CPL_FW4_ACK_FLOWID 0 4572 #define M_CPL_FW4_ACK_FLOWID 0xffffff 4573 #define V_CPL_FW4_ACK_FLOWID(x) ((x) << S_CPL_FW4_ACK_FLOWID) 4574 #define G_CPL_FW4_ACK_FLOWID(x) \ 4575 (((x) >> S_CPL_FW4_ACK_FLOWID) & M_CPL_FW4_ACK_FLOWID) 4576 4577 #define S_CPL_FW4_ACK_CR 24 4578 #define M_CPL_FW4_ACK_CR 0xff 4579 #define V_CPL_FW4_ACK_CR(x) ((x) << S_CPL_FW4_ACK_CR) 4580 #define G_CPL_FW4_ACK_CR(x) (((x) >> S_CPL_FW4_ACK_CR) & M_CPL_FW4_ACK_CR) 4581 4582 #define S_CPL_FW4_ACK_SEQVAL 0 4583 #define M_CPL_FW4_ACK_SEQVAL 0x1 4584 #define V_CPL_FW4_ACK_SEQVAL(x) ((x) << S_CPL_FW4_ACK_SEQVAL) 4585 #define G_CPL_FW4_ACK_SEQVAL(x) \ 4586 (((x) >> S_CPL_FW4_ACK_SEQVAL) & M_CPL_FW4_ACK_SEQVAL) 4587 #define F_CPL_FW4_ACK_SEQVAL V_CPL_FW4_ACK_SEQVAL(1U) 4588 4589 struct cpl_fw6_msg { 4590 RSS_HDR 4591 u8 opcode; 4592 u8 type; 4593 __be16 rsvd0; 4594 __be32 rsvd1; 4595 __be64 data[4]; 4596 }; 4597 4598 /* cpl_fw6_msg.type values */ 4599 enum { 4600 FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL, 4601 FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL, 4602 FW6_TYPE_CQE = FW_TYPE_CQE, 4603 FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL, 4604 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 4605 FW6_TYPE_WRERR_RPL = FW_TYPE_WRERR_RPL, 4606 FW6_TYPE_PI_ERR = FW_TYPE_PI_ERR, 4607 FW6_TYPE_TLS_KEY = FW_TYPE_TLS_KEY, 4608 FW6_TYPE_IPSEC_SA = FW_TYPE_IPSEC_SA, 4609 NUM_FW6_TYPES 4610 }; 4611 4612 struct cpl_fw6_msg_ofld_connection_wr_rpl { 4613 __u64 cookie; 4614 __be32 tid; /* or atid in case of active failure */ 4615 __u8 t_state; 4616 __u8 retval; 4617 __u8 rsvd[2]; 4618 }; 4619 4620 /* ULP_TX opcodes */ 4621 enum { 4622 ULP_TX_MEM_READ = 2, 4623 ULP_TX_MEM_WRITE = 3, 4624 ULP_TX_PKT = 4 4625 }; 4626 4627 enum { 4628 ULP_TX_SC_NOOP = 0x80, 4629 ULP_TX_SC_IMM = 0x81, 4630 ULP_TX_SC_DSGL = 0x82, 4631 ULP_TX_SC_ISGL = 0x83, 4632 ULP_TX_SC_PICTRL = 0x84, 4633 ULP_TX_SC_MEMRD = 0x86 4634 }; 4635 4636 #define S_ULPTX_CMD 24 4637 #define M_ULPTX_CMD 0xFF 4638 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 4639 4640 #define S_ULPTX_LEN16 0 4641 #define M_ULPTX_LEN16 0xFF 4642 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 4643 4644 #define S_ULP_TX_SC_MORE 23 4645 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 4646 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 4647 4648 struct ulptx_sge_pair { 4649 __be32 len[2]; 4650 __be64 addr[2]; 4651 }; 4652 4653 struct ulptx_sgl { 4654 __be32 cmd_nsge; 4655 __be32 len0; 4656 __be64 addr0; 4657 #if !(defined C99_NOT_SUPPORTED) 4658 struct ulptx_sge_pair sge[]; 4659 #endif 4660 }; 4661 4662 struct ulptx_isge { 4663 __be32 stag; 4664 __be32 len; 4665 __be64 target_ofst; 4666 }; 4667 4668 struct ulptx_isgl { 4669 __be32 cmd_nisge; 4670 __be32 rsvd; 4671 #if !(defined C99_NOT_SUPPORTED) 4672 struct ulptx_isge sge[]; 4673 #endif 4674 }; 4675 4676 struct ulptx_idata { 4677 __be32 cmd_more; 4678 __be32 len; 4679 }; 4680 4681 #define S_ULPTX_NSGE 0 4682 #define M_ULPTX_NSGE 0xFFFF 4683 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 4684 #define G_ULPTX_NSGE(x) (((x) >> S_ULPTX_NSGE) & M_ULPTX_NSGE) 4685 4686 struct ulptx_sc_memrd { 4687 __be32 cmd_to_len; 4688 __be32 addr; 4689 }; 4690 4691 struct ulp_mem_io { 4692 WR_HDR; 4693 __be32 cmd; 4694 __be32 len16; /* command length */ 4695 __be32 dlen; /* data length in 32-byte units */ 4696 __be32 lock_addr; 4697 }; 4698 4699 /* additional ulp_mem_io.cmd fields */ 4700 #define S_ULP_MEMIO_ORDER 23 4701 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 4702 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 4703 4704 #define S_T5_ULP_MEMIO_IMM 23 4705 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) 4706 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) 4707 4708 #define S_T5_ULP_MEMIO_ORDER 22 4709 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) 4710 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) 4711 4712 #define S_T5_ULP_MEMIO_FID 4 4713 #define M_T5_ULP_MEMIO_FID 0x7ff 4714 #define V_T5_ULP_MEMIO_FID(x) ((x) << S_T5_ULP_MEMIO_FID) 4715 4716 /* ulp_mem_io.lock_addr fields */ 4717 #define S_ULP_MEMIO_ADDR 0 4718 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 4719 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 4720 4721 #define S_ULP_MEMIO_LOCK 31 4722 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 4723 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 4724 4725 /* ulp_mem_io.dlen fields */ 4726 #define S_ULP_MEMIO_DATA_LEN 0 4727 #define M_ULP_MEMIO_DATA_LEN 0x1F 4728 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 4729 4730 #define S_T7_ULP_MEMIO_DATA_LEN 0 4731 #define M_T7_ULP_MEMIO_DATA_LEN 0x7FF 4732 #define V_T7_ULP_MEMIO_DATA_LEN(x) ((x) << S_T7_ULP_MEMIO_DATA_LEN) 4733 4734 /* ULP_TXPKT field values */ 4735 enum { 4736 ULP_TXPKT_DEST_TP = 0, 4737 ULP_TXPKT_DEST_SGE, 4738 ULP_TXPKT_DEST_UP, 4739 ULP_TXPKT_DEST_DEVNULL, 4740 }; 4741 4742 struct ulp_txpkt { 4743 __be32 cmd_dest; 4744 __be32 len; 4745 }; 4746 4747 /* ulp_txpkt.cmd_dest fields */ 4748 #define S_ULP_TXPKT_DATAMODIFY 23 4749 #define M_ULP_TXPKT_DATAMODIFY 0x1 4750 #define V_ULP_TXPKT_DATAMODIFY(x) ((x) << S_ULP_TXPKT_DATAMODIFY) 4751 #define G_ULP_TXPKT_DATAMODIFY(x) \ 4752 (((x) >> S_ULP_TXPKT_DATAMODIFY) & M_ULP_TXPKT_DATAMODIFY_) 4753 #define F_ULP_TXPKT_DATAMODIFY V_ULP_TXPKT_DATAMODIFY(1U) 4754 4755 #define S_ULP_TXPKT_CHANNELID 22 4756 #define M_ULP_TXPKT_CHANNELID 0x1 4757 #define V_ULP_TXPKT_CHANNELID(x) ((x) << S_ULP_TXPKT_CHANNELID) 4758 #define G_ULP_TXPKT_CHANNELID(x) \ 4759 (((x) >> S_ULP_TXPKT_CHANNELID) & M_ULP_TXPKT_CHANNELID) 4760 #define F_ULP_TXPKT_CHANNELID V_ULP_TXPKT_CHANNELID(1U) 4761 4762 #define S_T7_ULP_TXPKT_CHANNELID 22 4763 #define M_T7_ULP_TXPKT_CHANNELID 0x3 4764 #define V_T7_ULP_TXPKT_CHANNELID(x) ((x) << S_T7_ULP_TXPKT_CHANNELID) 4765 #define G_T7_ULP_TXPKT_CHANNELID(x) \ 4766 (((x) >> S_T7_ULP_TXPKT_CHANNELID) & M_T7_ULP_TXPKT_CHANNELID) 4767 #define F_T7_ULP_TXPKT_CHANNELID V_T7_ULP_TXPKT_CHANNELID(1U) 4768 4769 /* ulp_txpkt.cmd_dest fields */ 4770 #define S_ULP_TXPKT_DEST 16 4771 #define M_ULP_TXPKT_DEST 0x3 4772 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 4773 4774 #define S_ULP_TXPKT_CMDMORE 15 4775 #define M_ULP_TXPKT_CMDMORE 0x1 4776 #define V_ULP_TXPKT_CMDMORE(x) ((x) << S_ULP_TXPKT_CMDMORE) 4777 #define G_ULP_TXPKT_CMDMORE(x) \ 4778 (((x) >> S_ULP_TXPKT_CMDMORE) & M_ULP_TXPKT_CMDMORE) 4779 #define F_ULP_TXPKT_CMDMORE V_ULP_TXPKT_CMDMORE(1U) 4780 4781 #define S_ULP_TXPKT_FID 4 4782 #define M_ULP_TXPKT_FID 0x7ff 4783 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 4784 4785 #define S_ULP_TXPKT_RO 3 4786 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 4787 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 4788 4789 enum cpl_tx_tnl_lso_type { 4790 TX_TNL_TYPE_OPAQUE, 4791 TX_TNL_TYPE_NVGRE, 4792 TX_TNL_TYPE_VXLAN, 4793 TX_TNL_TYPE_GENEVE, 4794 TX_TNL_TYPE_IPSEC, 4795 }; 4796 4797 struct cpl_tx_tnl_lso { 4798 __be32 op_to_IpIdSplitOut; 4799 __be16 IpIdOffsetOut; 4800 __be16 UdpLenSetOut_to_TnlHdrLen; 4801 __be32 ipsecen_to_rocev2; 4802 __be32 roce_eth; 4803 __be32 Flow_to_TcpHdrLen; 4804 __be16 IpIdOffset; 4805 __be16 IpIdSplit_to_Mss; 4806 __be32 TCPSeqOffset; 4807 __be32 EthLenOffset_Size; 4808 /* encapsulated CPL (TX_PKT_XT) follows here */ 4809 }; 4810 4811 #define S_CPL_TX_TNL_LSO_OPCODE 24 4812 #define M_CPL_TX_TNL_LSO_OPCODE 0xff 4813 #define V_CPL_TX_TNL_LSO_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_OPCODE) 4814 #define G_CPL_TX_TNL_LSO_OPCODE(x) \ 4815 (((x) >> S_CPL_TX_TNL_LSO_OPCODE) & M_CPL_TX_TNL_LSO_OPCODE) 4816 4817 #define S_CPL_TX_TNL_LSO_FIRST 23 4818 #define M_CPL_TX_TNL_LSO_FIRST 0x1 4819 #define V_CPL_TX_TNL_LSO_FIRST(x) ((x) << S_CPL_TX_TNL_LSO_FIRST) 4820 #define G_CPL_TX_TNL_LSO_FIRST(x) \ 4821 (((x) >> S_CPL_TX_TNL_LSO_FIRST) & M_CPL_TX_TNL_LSO_FIRST) 4822 #define F_CPL_TX_TNL_LSO_FIRST V_CPL_TX_TNL_LSO_FIRST(1U) 4823 4824 #define S_CPL_TX_TNL_LSO_LAST 22 4825 #define M_CPL_TX_TNL_LSO_LAST 0x1 4826 #define V_CPL_TX_TNL_LSO_LAST(x) ((x) << S_CPL_TX_TNL_LSO_LAST) 4827 #define G_CPL_TX_TNL_LSO_LAST(x) \ 4828 (((x) >> S_CPL_TX_TNL_LSO_LAST) & M_CPL_TX_TNL_LSO_LAST) 4829 #define F_CPL_TX_TNL_LSO_LAST V_CPL_TX_TNL_LSO_LAST(1U) 4830 4831 #define S_CPL_TX_TNL_LSO_ETHHDRLENXOUT 21 4832 #define M_CPL_TX_TNL_LSO_ETHHDRLENXOUT 0x1 4833 #define V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 4834 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 4835 #define G_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 4836 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 4837 #define F_CPL_TX_TNL_LSO_ETHHDRLENXOUT V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(1U) 4838 4839 #define S_CPL_TX_TNL_LSO_IPV6OUT 20 4840 #define M_CPL_TX_TNL_LSO_IPV6OUT 0x1 4841 #define V_CPL_TX_TNL_LSO_IPV6OUT(x) ((x) << S_CPL_TX_TNL_LSO_IPV6OUT) 4842 #define G_CPL_TX_TNL_LSO_IPV6OUT(x) \ 4843 (((x) >> S_CPL_TX_TNL_LSO_IPV6OUT) & M_CPL_TX_TNL_LSO_IPV6OUT) 4844 #define F_CPL_TX_TNL_LSO_IPV6OUT V_CPL_TX_TNL_LSO_IPV6OUT(1U) 4845 4846 #define S_CPL_TX_TNL_LSO_ETHHDRLENOUT 16 4847 #define M_CPL_TX_TNL_LSO_ETHHDRLENOUT 0xf 4848 #define V_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 4849 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENOUT) 4850 #define G_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 4851 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENOUT) 4852 4853 #define S_CPL_TX_TNL_LSO_IPHDRLENOUT 4 4854 #define M_CPL_TX_TNL_LSO_IPHDRLENOUT 0xfff 4855 #define V_CPL_TX_TNL_LSO_IPHDRLENOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLENOUT) 4856 #define G_CPL_TX_TNL_LSO_IPHDRLENOUT(x) \ 4857 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLENOUT) & M_CPL_TX_TNL_LSO_IPHDRLENOUT) 4858 4859 #define S_CPL_TX_TNL_LSO_IPHDRCHKOUT 3 4860 #define M_CPL_TX_TNL_LSO_IPHDRCHKOUT 0x1 4861 #define V_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRCHKOUT) 4862 #define G_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) \ 4863 (((x) >> S_CPL_TX_TNL_LSO_IPHDRCHKOUT) & M_CPL_TX_TNL_LSO_IPHDRCHKOUT) 4864 #define F_CPL_TX_TNL_LSO_IPHDRCHKOUT V_CPL_TX_TNL_LSO_IPHDRCHKOUT(1U) 4865 4866 #define S_CPL_TX_TNL_LSO_IPLENSETOUT 2 4867 #define M_CPL_TX_TNL_LSO_IPLENSETOUT 0x1 4868 #define V_CPL_TX_TNL_LSO_IPLENSETOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPLENSETOUT) 4869 #define G_CPL_TX_TNL_LSO_IPLENSETOUT(x) \ 4870 (((x) >> S_CPL_TX_TNL_LSO_IPLENSETOUT) & M_CPL_TX_TNL_LSO_IPLENSETOUT) 4871 #define F_CPL_TX_TNL_LSO_IPLENSETOUT V_CPL_TX_TNL_LSO_IPLENSETOUT(1U) 4872 4873 #define S_CPL_TX_TNL_LSO_IPIDINCOUT 1 4874 #define M_CPL_TX_TNL_LSO_IPIDINCOUT 0x1 4875 #define V_CPL_TX_TNL_LSO_IPIDINCOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDINCOUT) 4876 #define G_CPL_TX_TNL_LSO_IPIDINCOUT(x) \ 4877 (((x) >> S_CPL_TX_TNL_LSO_IPIDINCOUT) & M_CPL_TX_TNL_LSO_IPIDINCOUT) 4878 #define F_CPL_TX_TNL_LSO_IPIDINCOUT V_CPL_TX_TNL_LSO_IPIDINCOUT(1U) 4879 4880 #define S_CPL_TX_TNL_LSO_IPIDSPLITOUT 0 4881 #define M_CPL_TX_TNL_LSO_IPIDSPLITOUT 0x1 4882 #define V_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 4883 ((x) << S_CPL_TX_TNL_LSO_IPIDSPLITOUT) 4884 #define G_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 4885 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLITOUT) & M_CPL_TX_TNL_LSO_IPIDSPLITOUT) 4886 #define F_CPL_TX_TNL_LSO_IPIDSPLITOUT V_CPL_TX_TNL_LSO_IPIDSPLITOUT(1U) 4887 4888 #define S_CPL_TX_TNL_LSO_UDPLENSETOUT 15 4889 #define M_CPL_TX_TNL_LSO_UDPLENSETOUT 0x1 4890 #define V_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 4891 ((x) << S_CPL_TX_TNL_LSO_UDPLENSETOUT) 4892 #define G_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 4893 (((x) >> S_CPL_TX_TNL_LSO_UDPLENSETOUT) & M_CPL_TX_TNL_LSO_UDPLENSETOUT) 4894 #define F_CPL_TX_TNL_LSO_UDPLENSETOUT V_CPL_TX_TNL_LSO_UDPLENSETOUT(1U) 4895 4896 #define S_CPL_TX_TNL_LSO_UDPCHKCLROUT 14 4897 #define M_CPL_TX_TNL_LSO_UDPCHKCLROUT 0x1 4898 #define V_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 4899 ((x) << S_CPL_TX_TNL_LSO_UDPCHKCLROUT) 4900 #define G_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 4901 (((x) >> S_CPL_TX_TNL_LSO_UDPCHKCLROUT) & M_CPL_TX_TNL_LSO_UDPCHKCLROUT) 4902 #define F_CPL_TX_TNL_LSO_UDPCHKCLROUT V_CPL_TX_TNL_LSO_UDPCHKCLROUT(1U) 4903 4904 #define S_CPL_TX_TNL_LSO_TNLTYPE 12 4905 #define M_CPL_TX_TNL_LSO_TNLTYPE 0x3 4906 #define V_CPL_TX_TNL_LSO_TNLTYPE(x) ((x) << S_CPL_TX_TNL_LSO_TNLTYPE) 4907 #define G_CPL_TX_TNL_LSO_TNLTYPE(x) \ 4908 (((x) >> S_CPL_TX_TNL_LSO_TNLTYPE) & M_CPL_TX_TNL_LSO_TNLTYPE) 4909 4910 #define S_CPL_TX_TNL_LSO_TNLHDRLEN 0 4911 #define M_CPL_TX_TNL_LSO_TNLHDRLEN 0xfff 4912 #define V_CPL_TX_TNL_LSO_TNLHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TNLHDRLEN) 4913 #define G_CPL_TX_TNL_LSO_TNLHDRLEN(x) \ 4914 (((x) >> S_CPL_TX_TNL_LSO_TNLHDRLEN) & M_CPL_TX_TNL_LSO_TNLHDRLEN) 4915 4916 #define S_CPL_TX_TNL_LSO_IPSECEN 31 4917 #define M_CPL_TX_TNL_LSO_IPSECEN 0x1 4918 #define V_CPL_TX_TNL_LSO_IPSECEN(x) ((x) << S_CPL_TX_TNL_LSO_IPSECEN) 4919 #define G_CPL_TX_TNL_LSO_IPSECEN(x) \ 4920 (((x) >> S_CPL_TX_TNL_LSO_IPSECEN) & M_CPL_TX_TNL_LSO_IPSECEN) 4921 #define F_CPL_TX_TNL_LSO_IPSECEN V_CPL_TX_TNL_LSO_IPSECEN(1U) 4922 4923 #define S_CPL_TX_TNL_LSO_ENCAPDIS 30 4924 #define M_CPL_TX_TNL_LSO_ENCAPDIS 0x1 4925 #define V_CPL_TX_TNL_LSO_ENCAPDIS(x) ((x) << S_CPL_TX_TNL_LSO_ENCAPDIS) 4926 #define G_CPL_TX_TNL_LSO_ENCAPDIS(x) \ 4927 (((x) >> S_CPL_TX_TNL_LSO_ENCAPDIS) & M_CPL_TX_TNL_LSO_ENCAPDIS) 4928 #define F_CPL_TX_TNL_LSO_ENCAPDIS V_CPL_TX_TNL_LSO_ENCAPDIS(1U) 4929 4930 #define S_CPL_TX_TNL_LSO_IPSECMODE 29 4931 #define M_CPL_TX_TNL_LSO_IPSECMODE 0x1 4932 #define V_CPL_TX_TNL_LSO_IPSECMODE(x) ((x) << S_CPL_TX_TNL_LSO_IPSECMODE) 4933 #define G_CPL_TX_TNL_LSO_IPSECMODE(x) \ 4934 (((x) >> S_CPL_TX_TNL_LSO_IPSECMODE) & M_CPL_TX_TNL_LSO_IPSECMODE) 4935 #define F_CPL_TX_TNL_LSO_IPSECMODE V_CPL_TX_TNL_LSO_IPSECMODE(1U) 4936 4937 #define S_CPL_TX_TNL_LSO_IPSECTNLIPV6 28 4938 #define M_CPL_TX_TNL_LSO_IPSECTNLIPV6 0x1 4939 #define V_CPL_TX_TNL_LSO_IPSECTNLIPV6(x) \ 4940 ((x) << S_CPL_TX_TNL_LSO_IPSECTNLIPV6) 4941 #define G_CPL_TX_TNL_LSO_IPSECTNLIPV6(x) \ 4942 (((x) >> S_CPL_TX_TNL_LSO_IPSECTNLIPV6) & M_CPL_TX_TNL_LSO_IPSECTNLIPV6) 4943 #define F_CPL_TX_TNL_LSO_IPSECTNLIPV6 V_CPL_TX_TNL_LSO_IPSECTNLIPV6(1U) 4944 4945 #define S_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN 20 4946 #define M_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN 0xff 4947 #define V_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN(x) \ 4948 ((x) << S_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN) 4949 #define G_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN(x) \ 4950 (((x) >> S_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN) & \ 4951 M_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN) 4952 4953 #define S_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT 19 4954 #define M_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT 0x1 4955 #define V_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT(x) \ 4956 ((x) << S_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT) 4957 #define G_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT(x) \ 4958 (((x) >> S_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT) & \ 4959 M_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT) 4960 #define F_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT \ 4961 V_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT(1U) 4962 4963 #define S_CPL_TX_TNL_LSO_ROCEV2 18 4964 #define M_CPL_TX_TNL_LSO_ROCEV2 0x1 4965 #define V_CPL_TX_TNL_LSO_ROCEV2(x) ((x) << S_CPL_TX_TNL_LSO_ROCEV2) 4966 #define G_CPL_TX_TNL_LSO_ROCEV2(x) \ 4967 (((x) >> S_CPL_TX_TNL_LSO_ROCEV2) & M_CPL_TX_TNL_LSO_ROCEV2) 4968 #define F_CPL_TX_TNL_LSO_ROCEV2 V_CPL_TX_TNL_LSO_ROCEV2(1U) 4969 4970 #define S_CPL_TX_TNL_LSO_UDPCHKUPDOUT 17 4971 #define M_CPL_TX_TNL_LSO_UDPCHKUPDOUT 0x1 4972 #define V_CPL_TX_TNL_LSO_UDPCHKUPDOUT(x) \ 4973 ((x) << S_CPL_TX_TNL_LSO_UDPCHKUPDOUT) 4974 #define G_CPL_TX_TNL_LSO_UDPCHKUPDOUT(x) \ 4975 (((x) >> S_CPL_TX_TNL_LSO_UDPCHKUPDOUT) & M_CPL_TX_TNL_LSO_UDPCHKUPDOUT) 4976 #define F_CPL_TX_TNL_LSO_UDPCHKUPDOUT V_CPL_TX_TNL_LSO_UDPCHKUPDOUT(1U) 4977 4978 #define S_CPL_TX_TNL_LSO_FLOW 21 4979 #define M_CPL_TX_TNL_LSO_FLOW 0x1 4980 #define V_CPL_TX_TNL_LSO_FLOW(x) ((x) << S_CPL_TX_TNL_LSO_FLOW) 4981 #define G_CPL_TX_TNL_LSO_FLOW(x) \ 4982 (((x) >> S_CPL_TX_TNL_LSO_FLOW) & M_CPL_TX_TNL_LSO_FLOW) 4983 #define F_CPL_TX_TNL_LSO_FLOW V_CPL_TX_TNL_LSO_FLOW(1U) 4984 4985 #define S_CPL_TX_TNL_LSO_IPV6 20 4986 #define M_CPL_TX_TNL_LSO_IPV6 0x1 4987 #define V_CPL_TX_TNL_LSO_IPV6(x) ((x) << S_CPL_TX_TNL_LSO_IPV6) 4988 #define G_CPL_TX_TNL_LSO_IPV6(x) \ 4989 (((x) >> S_CPL_TX_TNL_LSO_IPV6) & M_CPL_TX_TNL_LSO_IPV6) 4990 #define F_CPL_TX_TNL_LSO_IPV6 V_CPL_TX_TNL_LSO_IPV6(1U) 4991 4992 #define S_CPL_TX_TNL_LSO_ETHHDRLEN 16 4993 #define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf 4994 #define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN) 4995 #define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \ 4996 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN) 4997 4998 #define S_CPL_TX_TNL_LSO_IPHDRLEN 4 4999 #define M_CPL_TX_TNL_LSO_IPHDRLEN 0xfff 5000 #define V_CPL_TX_TNL_LSO_IPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLEN) 5001 #define G_CPL_TX_TNL_LSO_IPHDRLEN(x) \ 5002 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLEN) & M_CPL_TX_TNL_LSO_IPHDRLEN) 5003 5004 #define S_CPL_TX_TNL_LSO_TCPHDRLEN 0 5005 #define M_CPL_TX_TNL_LSO_TCPHDRLEN 0xf 5006 #define V_CPL_TX_TNL_LSO_TCPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TCPHDRLEN) 5007 #define G_CPL_TX_TNL_LSO_TCPHDRLEN(x) \ 5008 (((x) >> S_CPL_TX_TNL_LSO_TCPHDRLEN) & M_CPL_TX_TNL_LSO_TCPHDRLEN) 5009 5010 #define S_CPL_TX_TNL_LSO_IPIDSPLIT 15 5011 #define M_CPL_TX_TNL_LSO_IPIDSPLIT 0x1 5012 #define V_CPL_TX_TNL_LSO_IPIDSPLIT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDSPLIT) 5013 #define G_CPL_TX_TNL_LSO_IPIDSPLIT(x) \ 5014 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLIT) & M_CPL_TX_TNL_LSO_IPIDSPLIT) 5015 #define F_CPL_TX_TNL_LSO_IPIDSPLIT V_CPL_TX_TNL_LSO_IPIDSPLIT(1U) 5016 5017 #define S_CPL_TX_TNL_LSO_ETHHDRLENX 14 5018 #define M_CPL_TX_TNL_LSO_ETHHDRLENX 0x1 5019 #define V_CPL_TX_TNL_LSO_ETHHDRLENX(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENX) 5020 #define G_CPL_TX_TNL_LSO_ETHHDRLENX(x) \ 5021 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENX) & M_CPL_TX_TNL_LSO_ETHHDRLENX) 5022 #define F_CPL_TX_TNL_LSO_ETHHDRLENX V_CPL_TX_TNL_LSO_ETHHDRLENX(1U) 5023 5024 #define S_CPL_TX_TNL_LSO_MSS 0 5025 #define M_CPL_TX_TNL_LSO_MSS 0x3fff 5026 #define V_CPL_TX_TNL_LSO_MSS(x) ((x) << S_CPL_TX_TNL_LSO_MSS) 5027 #define G_CPL_TX_TNL_LSO_MSS(x) \ 5028 (((x) >> S_CPL_TX_TNL_LSO_MSS) & M_CPL_TX_TNL_LSO_MSS) 5029 5030 #define S_CPL_TX_TNL_LSO_ETHLENOFFSET 28 5031 #define M_CPL_TX_TNL_LSO_ETHLENOFFSET 0xf 5032 #define V_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 5033 ((x) << S_CPL_TX_TNL_LSO_ETHLENOFFSET) 5034 #define G_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 5035 (((x) >> S_CPL_TX_TNL_LSO_ETHLENOFFSET) & M_CPL_TX_TNL_LSO_ETHLENOFFSET) 5036 5037 #define S_CPL_TX_TNL_LSO_SIZE 0 5038 #define M_CPL_TX_TNL_LSO_SIZE 0xfffffff 5039 #define V_CPL_TX_TNL_LSO_SIZE(x) ((x) << S_CPL_TX_TNL_LSO_SIZE) 5040 #define G_CPL_TX_TNL_LSO_SIZE(x) \ 5041 (((x) >> S_CPL_TX_TNL_LSO_SIZE) & M_CPL_TX_TNL_LSO_SIZE) 5042 5043 struct cpl_rx_mps_pkt { 5044 __be32 op_to_r1_hi; 5045 __be32 r1_lo_length; 5046 }; 5047 5048 #define S_CPL_RX_MPS_PKT_OP 24 5049 #define M_CPL_RX_MPS_PKT_OP 0xff 5050 #define V_CPL_RX_MPS_PKT_OP(x) ((x) << S_CPL_RX_MPS_PKT_OP) 5051 #define G_CPL_RX_MPS_PKT_OP(x) \ 5052 (((x) >> S_CPL_RX_MPS_PKT_OP) & M_CPL_RX_MPS_PKT_OP) 5053 5054 #define S_CPL_RX_MPS_PKT_TYPE 20 5055 #define M_CPL_RX_MPS_PKT_TYPE 0xf 5056 #define V_CPL_RX_MPS_PKT_TYPE(x) ((x) << S_CPL_RX_MPS_PKT_TYPE) 5057 #define G_CPL_RX_MPS_PKT_TYPE(x) \ 5058 (((x) >> S_CPL_RX_MPS_PKT_TYPE) & M_CPL_RX_MPS_PKT_TYPE) 5059 5060 #define S_CPL_RX_MPS_PKT_LENGTH 0 5061 #define M_CPL_RX_MPS_PKT_LENGTH 0xffff 5062 #define V_CPL_RX_MPS_PKT_LENGTH(x) ((x) << S_CPL_RX_MPS_PKT_LENGTH) 5063 #define G_CPL_RX_MPS_PKT_LENGTH(x) \ 5064 (((x) >> S_CPL_RX_MPS_PKT_LENGTH) & M_CPL_RX_MPS_PKT_LENGTH) 5065 5066 /* 5067 * Values for CPL_RX_MPS_PKT_TYPE, a bit-wise orthogonal field. 5068 */ 5069 #define X_CPL_RX_MPS_PKT_TYPE_PAUSE (1 << 0) 5070 #define X_CPL_RX_MPS_PKT_TYPE_PPP (1 << 1) 5071 #define X_CPL_RX_MPS_PKT_TYPE_QFC (1 << 2) 5072 #define X_CPL_RX_MPS_PKT_TYPE_PTP (1 << 3) 5073 5074 struct cpl_t7_rx_mps_pkt { 5075 RSS_HDR 5076 union opcode_tid ot; 5077 __be32 length_pkd; 5078 }; 5079 5080 #define S_CPL_T7_RX_MPS_PKT_TYPE 20 5081 #define M_CPL_T7_RX_MPS_PKT_TYPE 0xf 5082 #define V_CPL_T7_RX_MPS_PKT_TYPE(x) ((x) << S_CPL_T7_RX_MPS_PKT_TYPE) 5083 #define G_CPL_T7_RX_MPS_PKT_TYPE(x) \ 5084 (((x) >> S_CPL_T7_RX_MPS_PKT_TYPE) & M_CPL_T7_RX_MPS_PKT_TYPE) 5085 5086 #define S_CPL_T7_RX_MPS_PKT_INTERFACE 16 5087 #define M_CPL_T7_RX_MPS_PKT_INTERFACE 0xf 5088 #define V_CPL_T7_RX_MPS_PKT_INTERFACE(x) \ 5089 ((x) << S_CPL_T7_RX_MPS_PKT_INTERFACE) 5090 #define G_CPL_T7_RX_MPS_PKT_INTERFACE(x) \ 5091 (((x) >> S_CPL_T7_RX_MPS_PKT_INTERFACE) & M_CPL_T7_RX_MPS_PKT_INTERFACE) 5092 5093 #define S_CPL_T7_RX_MPS_PKT_TRUNCATED 7 5094 #define M_CPL_T7_RX_MPS_PKT_TRUNCATED 0x1 5095 #define V_CPL_T7_RX_MPS_PKT_TRUNCATED(x) \ 5096 ((x) << S_CPL_T7_RX_MPS_PKT_TRUNCATED) 5097 #define G_CPL_T7_RX_MPS_PKT_TRUNCATED(x) \ 5098 (((x) >> S_CPL_T7_RX_MPS_PKT_TRUNCATED) & M_CPL_T7_RX_MPS_PKT_TRUNCATED) 5099 #define F_CPL_T7_RX_MPS_PKT_TRUNCATED V_CPL_T7_RX_MPS_PKT_TRUNCATED(1U) 5100 5101 #define S_CPL_T7_RX_MPS_PKT_PKTERR 6 5102 #define M_CPL_T7_RX_MPS_PKT_PKTERR 0x1 5103 #define V_CPL_T7_RX_MPS_PKT_PKTERR(x) ((x) << S_CPL_T7_RX_MPS_PKT_PKTERR) 5104 #define G_CPL_T7_RX_MPS_PKT_PKTERR(x) \ 5105 (((x) >> S_CPL_T7_RX_MPS_PKT_PKTERR) & M_CPL_T7_RX_MPS_PKT_PKTERR) 5106 #define F_CPL_T7_RX_MPS_PKT_PKTERR V_CPL_T7_RX_MPS_PKT_PKTERR(1U) 5107 5108 #define S_CPL_T7_RX_MPS_PKT_LENGTH 0 5109 #define M_CPL_T7_RX_MPS_PKT_LENGTH 0xffff 5110 #define V_CPL_T7_RX_MPS_PKT_LENGTH(x) ((x) << S_CPL_T7_RX_MPS_PKT_LENGTH) 5111 #define G_CPL_T7_RX_MPS_PKT_LENGTH(x) \ 5112 (((x) >> S_CPL_T7_RX_MPS_PKT_LENGTH) & M_CPL_T7_RX_MPS_PKT_LENGTH) 5113 5114 struct cpl_tx_tls_pdu { 5115 WR_HDR; 5116 union opcode_tid ot; 5117 __be32 pldlen_pkd; 5118 __be32 customtype_customprotover; 5119 __be32 r2_lo; 5120 __be32 scmd0[2]; 5121 __be32 scmd1[2]; 5122 }; 5123 5124 #define S_CPL_TX_TLS_PDU_DATATYPE 20 5125 #define M_CPL_TX_TLS_PDU_DATATYPE 0xf 5126 #define V_CPL_TX_TLS_PDU_DATATYPE(x) ((x) << S_CPL_TX_TLS_PDU_DATATYPE) 5127 #define G_CPL_TX_TLS_PDU_DATATYPE(x) \ 5128 (((x) >> S_CPL_TX_TLS_PDU_DATATYPE) & M_CPL_TX_TLS_PDU_DATATYPE) 5129 5130 #define S_CPL_TX_TLS_PDU_CPLLEN 16 5131 #define M_CPL_TX_TLS_PDU_CPLLEN 0xf 5132 #define V_CPL_TX_TLS_PDU_CPLLEN(x) ((x) << S_CPL_TX_TLS_PDU_CPLLEN) 5133 #define G_CPL_TX_TLS_PDU_CPLLEN(x) \ 5134 (((x) >> S_CPL_TX_TLS_PDU_CPLLEN) & M_CPL_TX_TLS_PDU_CPLLEN) 5135 5136 #define S_CPL_TX_TLS_PDU_PLDLEN 0 5137 #define M_CPL_TX_TLS_PDU_PLDLEN 0xfffff 5138 #define V_CPL_TX_TLS_PDU_PLDLEN(x) ((x) << S_CPL_TX_TLS_PDU_PLDLEN) 5139 #define G_CPL_TX_TLS_PDU_PLDLEN(x) \ 5140 (((x) >> S_CPL_TX_TLS_PDU_PLDLEN) & M_CPL_TX_TLS_PDU_PLDLEN) 5141 5142 #define S_CPL_TX_TLS_PDU_CUSTOMTYPE 24 5143 #define M_CPL_TX_TLS_PDU_CUSTOMTYPE 0xff 5144 #define V_CPL_TX_TLS_PDU_CUSTOMTYPE(x) ((x) << S_CPL_TX_TLS_PDU_CUSTOMTYPE) 5145 #define G_CPL_TX_TLS_PDU_CUSTOMTYPE(x) \ 5146 (((x) >> S_CPL_TX_TLS_PDU_CUSTOMTYPE) & M_CPL_TX_TLS_PDU_CUSTOMTYPE) 5147 5148 #define S_CPL_TX_TLS_PDU_CUSTOMPROTOVER 8 5149 #define M_CPL_TX_TLS_PDU_CUSTOMPROTOVER 0xffff 5150 #define V_CPL_TX_TLS_PDU_CUSTOMPROTOVER(x) \ 5151 ((x) << S_CPL_TX_TLS_PDU_CUSTOMPROTOVER) 5152 #define G_CPL_TX_TLS_PDU_CUSTOMPROTOVER(x) \ 5153 (((x) >> S_CPL_TX_TLS_PDU_CUSTOMPROTOVER) & \ 5154 M_CPL_TX_TLS_PDU_CUSTOMPROTOVER) 5155 5156 struct cpl_tx_tls_sfo { 5157 __be32 op_to_seg_len; 5158 __be32 pld_len; 5159 __be32 type_protover; 5160 __be32 r1_lo; 5161 __be32 seqno_numivs; 5162 __be32 ivgen_hdrlen; 5163 __be64 scmd1; 5164 }; 5165 5166 /* cpl_tx_tls_sfo macros */ 5167 #define S_CPL_TX_TLS_SFO_OPCODE 24 5168 #define M_CPL_TX_TLS_SFO_OPCODE 0xff 5169 #define V_CPL_TX_TLS_SFO_OPCODE(x) ((x) << S_CPL_TX_TLS_SFO_OPCODE) 5170 #define G_CPL_TX_TLS_SFO_OPCODE(x) \ 5171 (((x) >> S_CPL_TX_TLS_SFO_OPCODE) & M_CPL_TX_TLS_SFO_OPCODE) 5172 5173 #define S_CPL_TX_TLS_SFO_DATA_TYPE 20 5174 #define M_CPL_TX_TLS_SFO_DATA_TYPE 0xf 5175 #define V_CPL_TX_TLS_SFO_DATA_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_DATA_TYPE) 5176 #define G_CPL_TX_TLS_SFO_DATA_TYPE(x) \ 5177 (((x) >> S_CPL_TX_TLS_SFO_DATA_TYPE) & M_CPL_TX_TLS_SFO_DATA_TYPE) 5178 5179 #define S_CPL_TX_TLS_SFO_CPL_LEN 16 5180 #define M_CPL_TX_TLS_SFO_CPL_LEN 0xf 5181 #define V_CPL_TX_TLS_SFO_CPL_LEN(x) ((x) << S_CPL_TX_TLS_SFO_CPL_LEN) 5182 #define G_CPL_TX_TLS_SFO_CPL_LEN(x) \ 5183 (((x) >> S_CPL_TX_TLS_SFO_CPL_LEN) & M_CPL_TX_TLS_SFO_CPL_LEN) 5184 5185 #define S_CPL_TX_TLS_SFO_SEG_LEN 0 5186 #define M_CPL_TX_TLS_SFO_SEG_LEN 0xffff 5187 #define V_CPL_TX_TLS_SFO_SEG_LEN(x) ((x) << S_CPL_TX_TLS_SFO_SEG_LEN) 5188 #define G_CPL_TX_TLS_SFO_SEG_LEN(x) \ 5189 (((x) >> S_CPL_TX_TLS_SFO_SEG_LEN) & M_CPL_TX_TLS_SFO_SEG_LEN) 5190 5191 #define S_CPL_TX_TLS_SFO_PLDLEN 0 5192 #define M_CPL_TX_TLS_SFO_PLDLEN 0xfffff 5193 #define V_CPL_TX_TLS_SFO_PLDLEN(x) ((x) << S_CPL_TX_TLS_SFO_PLDLEN) 5194 #define G_CPL_TX_TLS_SFO_PLDLEN(x) \ 5195 (((x) >> S_CPL_TX_TLS_SFO_PLDLEN) & M_CPL_TX_TLS_SFO_PLDLEN) 5196 5197 #define S_CPL_TX_TLS_SFO_TYPE 24 5198 #define M_CPL_TX_TLS_SFO_TYPE 0xff 5199 #define V_CPL_TX_TLS_SFO_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_TYPE) 5200 #define G_CPL_TX_TLS_SFO_TYPE(x) \ 5201 (((x) >> S_CPL_TX_TLS_SFO_TYPE) & M_CPL_TX_TLS_SFO_TYPE) 5202 5203 #define S_CPL_TX_TLS_SFO_PROTOVER 8 5204 #define M_CPL_TX_TLS_SFO_PROTOVER 0xffff 5205 #define V_CPL_TX_TLS_SFO_PROTOVER(x) ((x) << S_CPL_TX_TLS_SFO_PROTOVER) 5206 #define G_CPL_TX_TLS_SFO_PROTOVER(x) \ 5207 (((x) >> S_CPL_TX_TLS_SFO_PROTOVER) & M_CPL_TX_TLS_SFO_PROTOVER) 5208 5209 struct cpl_tls_data { 5210 RSS_HDR 5211 union opcode_tid ot; 5212 __be32 length_pkd; 5213 __be32 seq; 5214 __be32 r1; 5215 }; 5216 5217 #define S_CPL_TLS_DATA_OPCODE 24 5218 #define M_CPL_TLS_DATA_OPCODE 0xff 5219 #define V_CPL_TLS_DATA_OPCODE(x) ((x) << S_CPL_TLS_DATA_OPCODE) 5220 #define G_CPL_TLS_DATA_OPCODE(x) \ 5221 (((x) >> S_CPL_TLS_DATA_OPCODE) & M_CPL_TLS_DATA_OPCODE) 5222 5223 #define S_CPL_TLS_DATA_TID 0 5224 #define M_CPL_TLS_DATA_TID 0xffffff 5225 #define V_CPL_TLS_DATA_TID(x) ((x) << S_CPL_TLS_DATA_TID) 5226 #define G_CPL_TLS_DATA_TID(x) \ 5227 (((x) >> S_CPL_TLS_DATA_TID) & M_CPL_TLS_DATA_TID) 5228 5229 #define S_CPL_TLS_DATA_LENGTH 0 5230 #define M_CPL_TLS_DATA_LENGTH 0xffff 5231 #define V_CPL_TLS_DATA_LENGTH(x) ((x) << S_CPL_TLS_DATA_LENGTH) 5232 #define G_CPL_TLS_DATA_LENGTH(x) \ 5233 (((x) >> S_CPL_TLS_DATA_LENGTH) & M_CPL_TLS_DATA_LENGTH) 5234 5235 struct cpl_rx_tls_cmp { 5236 RSS_HDR 5237 union opcode_tid ot; 5238 __be32 pdulength_length; 5239 __be32 seq; 5240 __be32 ddp_report; 5241 __be32 r; 5242 __be32 ddp_valid; 5243 }; 5244 5245 #define S_CPL_RX_TLS_CMP_OPCODE 24 5246 #define M_CPL_RX_TLS_CMP_OPCODE 0xff 5247 #define V_CPL_RX_TLS_CMP_OPCODE(x) ((x) << S_CPL_RX_TLS_CMP_OPCODE) 5248 #define G_CPL_RX_TLS_CMP_OPCODE(x) \ 5249 (((x) >> S_CPL_RX_TLS_CMP_OPCODE) & M_CPL_RX_TLS_CMP_OPCODE) 5250 5251 #define S_CPL_RX_TLS_CMP_TID 0 5252 #define M_CPL_RX_TLS_CMP_TID 0xffffff 5253 #define V_CPL_RX_TLS_CMP_TID(x) ((x) << S_CPL_RX_TLS_CMP_TID) 5254 #define G_CPL_RX_TLS_CMP_TID(x) \ 5255 (((x) >> S_CPL_RX_TLS_CMP_TID) & M_CPL_RX_TLS_CMP_TID) 5256 5257 #define S_CPL_RX_TLS_CMP_PDULENGTH 16 5258 #define M_CPL_RX_TLS_CMP_PDULENGTH 0xffff 5259 #define V_CPL_RX_TLS_CMP_PDULENGTH(x) ((x) << S_CPL_RX_TLS_CMP_PDULENGTH) 5260 #define G_CPL_RX_TLS_CMP_PDULENGTH(x) \ 5261 (((x) >> S_CPL_RX_TLS_CMP_PDULENGTH) & M_CPL_RX_TLS_CMP_PDULENGTH) 5262 5263 #define S_CPL_RX_TLS_CMP_LENGTH 0 5264 #define M_CPL_RX_TLS_CMP_LENGTH 0xffff 5265 #define V_CPL_RX_TLS_CMP_LENGTH(x) ((x) << S_CPL_RX_TLS_CMP_LENGTH) 5266 #define G_CPL_RX_TLS_CMP_LENGTH(x) \ 5267 (((x) >> S_CPL_RX_TLS_CMP_LENGTH) & M_CPL_RX_TLS_CMP_LENGTH) 5268 5269 #define S_SCMD_SEQ_NO_CTRL 29 5270 #define M_SCMD_SEQ_NO_CTRL 0x3 5271 #define V_SCMD_SEQ_NO_CTRL(x) ((x) << S_SCMD_SEQ_NO_CTRL) 5272 #define G_SCMD_SEQ_NO_CTRL(x) \ 5273 (((x) >> S_SCMD_SEQ_NO_CTRL) & M_SCMD_SEQ_NO_CTRL) 5274 5275 /* StsFieldPrsnt- Status field at the end of the TLS PDU */ 5276 #define S_SCMD_STATUS_PRESENT 28 5277 #define M_SCMD_STATUS_PRESENT 0x1 5278 #define V_SCMD_STATUS_PRESENT(x) ((x) << S_SCMD_STATUS_PRESENT) 5279 #define G_SCMD_STATUS_PRESENT(x) \ 5280 (((x) >> S_SCMD_STATUS_PRESENT) & M_SCMD_STATUS_PRESENT) 5281 #define F_SCMD_STATUS_PRESENT V_SCMD_STATUS_PRESENT(1U) 5282 5283 /* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic, 5284 * 3-15: Reserved. */ 5285 #define S_SCMD_PROTO_VERSION 24 5286 #define M_SCMD_PROTO_VERSION 0xf 5287 #define V_SCMD_PROTO_VERSION(x) ((x) << S_SCMD_PROTO_VERSION) 5288 #define G_SCMD_PROTO_VERSION(x) \ 5289 (((x) >> S_SCMD_PROTO_VERSION) & M_SCMD_PROTO_VERSION) 5290 5291 /* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */ 5292 #define S_SCMD_ENC_DEC_CTRL 23 5293 #define M_SCMD_ENC_DEC_CTRL 0x1 5294 #define V_SCMD_ENC_DEC_CTRL(x) ((x) << S_SCMD_ENC_DEC_CTRL) 5295 #define G_SCMD_ENC_DEC_CTRL(x) \ 5296 (((x) >> S_SCMD_ENC_DEC_CTRL) & M_SCMD_ENC_DEC_CTRL) 5297 #define F_SCMD_ENC_DEC_CTRL V_SCMD_ENC_DEC_CTRL(1U) 5298 5299 /* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */ 5300 #define S_SCMD_CIPH_AUTH_SEQ_CTRL 22 5301 #define M_SCMD_CIPH_AUTH_SEQ_CTRL 0x1 5302 #define V_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 5303 ((x) << S_SCMD_CIPH_AUTH_SEQ_CTRL) 5304 #define G_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 5305 (((x) >> S_SCMD_CIPH_AUTH_SEQ_CTRL) & M_SCMD_CIPH_AUTH_SEQ_CTRL) 5306 #define F_SCMD_CIPH_AUTH_SEQ_CTRL V_SCMD_CIPH_AUTH_SEQ_CTRL(1U) 5307 5308 /* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR, 5309 * 4:Generic-AES, 5-15: Reserved. */ 5310 #define S_SCMD_CIPH_MODE 18 5311 #define M_SCMD_CIPH_MODE 0xf 5312 #define V_SCMD_CIPH_MODE(x) ((x) << S_SCMD_CIPH_MODE) 5313 #define G_SCMD_CIPH_MODE(x) \ 5314 (((x) >> S_SCMD_CIPH_MODE) & M_SCMD_CIPH_MODE) 5315 5316 /* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256 5317 * 4-15: Reserved */ 5318 #define S_SCMD_AUTH_MODE 14 5319 #define M_SCMD_AUTH_MODE 0xf 5320 #define V_SCMD_AUTH_MODE(x) ((x) << S_SCMD_AUTH_MODE) 5321 #define G_SCMD_AUTH_MODE(x) \ 5322 (((x) >> S_SCMD_AUTH_MODE) & M_SCMD_AUTH_MODE) 5323 5324 /* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation 5325 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved 5326 */ 5327 #define S_SCMD_HMAC_CTRL 11 5328 #define M_SCMD_HMAC_CTRL 0x7 5329 #define V_SCMD_HMAC_CTRL(x) ((x) << S_SCMD_HMAC_CTRL) 5330 #define G_SCMD_HMAC_CTRL(x) \ 5331 (((x) >> S_SCMD_HMAC_CTRL) & M_SCMD_HMAC_CTRL) 5332 5333 /* IvSize - IV size in units of 2 bytes */ 5334 #define S_SCMD_IV_SIZE 7 5335 #define M_SCMD_IV_SIZE 0xf 5336 #define V_SCMD_IV_SIZE(x) ((x) << S_SCMD_IV_SIZE) 5337 #define G_SCMD_IV_SIZE(x) \ 5338 (((x) >> S_SCMD_IV_SIZE) & M_SCMD_IV_SIZE) 5339 5340 /* NumIVs - Number of IVs */ 5341 #define S_SCMD_NUM_IVS 0 5342 #define M_SCMD_NUM_IVS 0x7f 5343 #define V_SCMD_NUM_IVS(x) ((x) << S_SCMD_NUM_IVS) 5344 #define G_SCMD_NUM_IVS(x) \ 5345 (((x) >> S_SCMD_NUM_IVS) & M_SCMD_NUM_IVS) 5346 5347 /* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber 5348 * (below) are used as Cid (connection id for debug status), these 5349 * bits are padded to zero for forming the 64 bit 5350 * sequence number for TLS 5351 */ 5352 #define S_SCMD_ENB_DBGID 31 5353 #define M_SCMD_ENB_DBGID 0x1 5354 #define V_SCMD_ENB_DBGID(x) ((x) << S_SCMD_ENB_DBGID) 5355 #define G_SCMD_ENB_DBGID(x) \ 5356 (((x) >> S_SCMD_ENB_DBGID) & M_SCMD_ENB_DBGID) 5357 5358 /* IV generation in SW. */ 5359 #define S_SCMD_IV_GEN_CTRL 30 5360 #define M_SCMD_IV_GEN_CTRL 0x1 5361 #define V_SCMD_IV_GEN_CTRL(x) ((x) << S_SCMD_IV_GEN_CTRL) 5362 #define G_SCMD_IV_GEN_CTRL(x) \ 5363 (((x) >> S_SCMD_IV_GEN_CTRL) & M_SCMD_IV_GEN_CTRL) 5364 #define F_SCMD_IV_GEN_CTRL V_SCMD_IV_GEN_CTRL(1U) 5365 5366 /* More frags */ 5367 #define S_SCMD_MORE_FRAGS 20 5368 #define M_SCMD_MORE_FRAGS 0x1 5369 #define V_SCMD_MORE_FRAGS(x) ((x) << S_SCMD_MORE_FRAGS) 5370 #define G_SCMD_MORE_FRAGS(x) (((x) >> S_SCMD_MORE_FRAGS) & M_SCMD_MORE_FRAGS) 5371 5372 /*last frag */ 5373 #define S_SCMD_LAST_FRAG 19 5374 #define M_SCMD_LAST_FRAG 0x1 5375 #define V_SCMD_LAST_FRAG(x) ((x) << S_SCMD_LAST_FRAG) 5376 #define G_SCMD_LAST_FRAG(x) (((x) >> S_SCMD_LAST_FRAG) & M_SCMD_LAST_FRAG) 5377 5378 /* TlsCompPdu */ 5379 #define S_SCMD_TLS_COMPPDU 18 5380 #define M_SCMD_TLS_COMPPDU 0x1 5381 #define V_SCMD_TLS_COMPPDU(x) ((x) << S_SCMD_TLS_COMPPDU) 5382 #define G_SCMD_TLS_COMPPDU(x) (((x) >> S_SCMD_TLS_COMPPDU) & M_SCMD_TLS_COMPPDU) 5383 5384 /* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/ 5385 #define S_SCMD_KEY_CTX_INLINE 17 5386 #define M_SCMD_KEY_CTX_INLINE 0x1 5387 #define V_SCMD_KEY_CTX_INLINE(x) ((x) << S_SCMD_KEY_CTX_INLINE) 5388 #define G_SCMD_KEY_CTX_INLINE(x) \ 5389 (((x) >> S_SCMD_KEY_CTX_INLINE) & M_SCMD_KEY_CTX_INLINE) 5390 #define F_SCMD_KEY_CTX_INLINE V_SCMD_KEY_CTX_INLINE(1U) 5391 5392 /* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */ 5393 #define S_SCMD_TLS_FRAG_ENABLE 16 5394 #define M_SCMD_TLS_FRAG_ENABLE 0x1 5395 #define V_SCMD_TLS_FRAG_ENABLE(x) ((x) << S_SCMD_TLS_FRAG_ENABLE) 5396 #define G_SCMD_TLS_FRAG_ENABLE(x) \ 5397 (((x) >> S_SCMD_TLS_FRAG_ENABLE) & M_SCMD_TLS_FRAG_ENABLE) 5398 #define F_SCMD_TLS_FRAG_ENABLE V_SCMD_TLS_FRAG_ENABLE(1U) 5399 5400 /* MacOnly - Only send the MAC and discard PDU. This is valid for hash only 5401 * modes, in this case TLS_TX will drop the PDU and only 5402 * send back the MAC bytes. */ 5403 #define S_SCMD_MAC_ONLY 15 5404 #define M_SCMD_MAC_ONLY 0x1 5405 #define V_SCMD_MAC_ONLY(x) ((x) << S_SCMD_MAC_ONLY) 5406 #define G_SCMD_MAC_ONLY(x) \ 5407 (((x) >> S_SCMD_MAC_ONLY) & M_SCMD_MAC_ONLY) 5408 #define F_SCMD_MAC_ONLY V_SCMD_MAC_ONLY(1U) 5409 5410 /* AadIVDrop - Drop the AAD and IV fields. Useful in protocols 5411 * which have complex AAD and IV formations Eg:AES-CCM 5412 */ 5413 #define S_SCMD_AADIVDROP 14 5414 #define M_SCMD_AADIVDROP 0x1 5415 #define V_SCMD_AADIVDROP(x) ((x) << S_SCMD_AADIVDROP) 5416 #define G_SCMD_AADIVDROP(x) \ 5417 (((x) >> S_SCMD_AADIVDROP) & M_SCMD_AADIVDROP) 5418 #define F_SCMD_AADIVDROP V_SCMD_AADIVDROP(1U) 5419 5420 /* HdrLength - Length of all headers excluding TLS header 5421 * present before start of crypto PDU/payload. */ 5422 #define S_SCMD_HDR_LEN 0 5423 #define M_SCMD_HDR_LEN 0x3fff 5424 #define V_SCMD_HDR_LEN(x) ((x) << S_SCMD_HDR_LEN) 5425 #define G_SCMD_HDR_LEN(x) \ 5426 (((x) >> S_SCMD_HDR_LEN) & M_SCMD_HDR_LEN) 5427 5428 struct cpl_rx_pkt_ipsec { 5429 RSS_HDR 5430 union opcode_tid ot; 5431 __be16 vlan; 5432 __be16 length; 5433 __be32 rxchannel_to_ethhdrlen; 5434 __be32 iphdrlen_to_rxerror; 5435 __be64 timestamp; 5436 }; 5437 5438 #define S_CPL_RX_PKT_IPSEC_OPCODE 24 5439 #define M_CPL_RX_PKT_IPSEC_OPCODE 0xff 5440 #define V_CPL_RX_PKT_IPSEC_OPCODE(x) ((x) << S_CPL_RX_PKT_IPSEC_OPCODE) 5441 #define G_CPL_RX_PKT_IPSEC_OPCODE(x) \ 5442 (((x) >> S_CPL_RX_PKT_IPSEC_OPCODE) & M_CPL_RX_PKT_IPSEC_OPCODE) 5443 5444 #define S_CPL_RX_PKT_IPSEC_IPFRAG 23 5445 #define M_CPL_RX_PKT_IPSEC_IPFRAG 0x1 5446 #define V_CPL_RX_PKT_IPSEC_IPFRAG(x) ((x) << S_CPL_RX_PKT_IPSEC_IPFRAG) 5447 #define G_CPL_RX_PKT_IPSEC_IPFRAG(x) \ 5448 (((x) >> S_CPL_RX_PKT_IPSEC_IPFRAG) & M_CPL_RX_PKT_IPSEC_IPFRAG) 5449 #define F_CPL_RX_PKT_IPSEC_IPFRAG V_CPL_RX_PKT_IPSEC_IPFRAG(1U) 5450 5451 #define S_CPL_RX_PKT_IPSEC_VLAN_EX 22 5452 #define M_CPL_RX_PKT_IPSEC_VLAN_EX 0x1 5453 #define V_CPL_RX_PKT_IPSEC_VLAN_EX(x) ((x) << S_CPL_RX_PKT_IPSEC_VLAN_EX) 5454 #define G_CPL_RX_PKT_IPSEC_VLAN_EX(x) \ 5455 (((x) >> S_CPL_RX_PKT_IPSEC_VLAN_EX) & M_CPL_RX_PKT_IPSEC_VLAN_EX) 5456 #define F_CPL_RX_PKT_IPSEC_VLAN_EX V_CPL_RX_PKT_IPSEC_VLAN_EX(1U) 5457 5458 #define S_CPL_RX_PKT_IPSEC_IPMI 21 5459 #define M_CPL_RX_PKT_IPSEC_IPMI 0x1 5460 #define V_CPL_RX_PKT_IPSEC_IPMI(x) ((x) << S_CPL_RX_PKT_IPSEC_IPMI) 5461 #define G_CPL_RX_PKT_IPSEC_IPMI(x) \ 5462 (((x) >> S_CPL_RX_PKT_IPSEC_IPMI) & M_CPL_RX_PKT_IPSEC_IPMI) 5463 #define F_CPL_RX_PKT_IPSEC_IPMI V_CPL_RX_PKT_IPSEC_IPMI(1U) 5464 5465 #define S_CPL_RX_PKT_IPSEC_INTERFACE 16 5466 #define M_CPL_RX_PKT_IPSEC_INTERFACE 0xf 5467 #define V_CPL_RX_PKT_IPSEC_INTERFACE(x) ((x) << S_CPL_RX_PKT_IPSEC_INTERFACE) 5468 #define G_CPL_RX_PKT_IPSEC_INTERFACE(x) \ 5469 (((x) >> S_CPL_RX_PKT_IPSEC_INTERFACE) & M_CPL_RX_PKT_IPSEC_INTERFACE) 5470 5471 #define S_CPL_RX_PKT_IPSEC_IPSECEXTERR 12 5472 #define M_CPL_RX_PKT_IPSEC_IPSECEXTERR 0xf 5473 #define V_CPL_RX_PKT_IPSEC_IPSECEXTERR(x) \ 5474 ((x) << S_CPL_RX_PKT_IPSEC_IPSECEXTERR) 5475 #define G_CPL_RX_PKT_IPSEC_IPSECEXTERR(x) \ 5476 (((x) >> S_CPL_RX_PKT_IPSEC_IPSECEXTERR) & M_CPL_RX_PKT_IPSEC_IPSECEXTERR) 5477 5478 #define S_CPL_RX_PKT_IPSEC_IPSECTYPE 10 5479 #define M_CPL_RX_PKT_IPSEC_IPSECTYPE 0x3 5480 #define V_CPL_RX_PKT_IPSEC_IPSECTYPE(x) ((x) << S_CPL_RX_PKT_IPSEC_IPSECTYPE) 5481 #define G_CPL_RX_PKT_IPSEC_IPSECTYPE(x) \ 5482 (((x) >> S_CPL_RX_PKT_IPSEC_IPSECTYPE) & M_CPL_RX_PKT_IPSEC_IPSECTYPE) 5483 5484 #define S_CPL_RX_PKT_IPSEC_OUTIPHDRLEN 0 5485 #define M_CPL_RX_PKT_IPSEC_OUTIPHDRLEN 0x3ff 5486 #define V_CPL_RX_PKT_IPSEC_OUTIPHDRLEN(x) \ 5487 ((x) << S_CPL_RX_PKT_IPSEC_OUTIPHDRLEN) 5488 #define G_CPL_RX_PKT_IPSEC_OUTIPHDRLEN(x) \ 5489 (((x) >> S_CPL_RX_PKT_IPSEC_OUTIPHDRLEN) & M_CPL_RX_PKT_IPSEC_OUTIPHDRLEN) 5490 5491 #define S_CPL_RX_PKT_IPSEC_RXCHANNEL 28 5492 #define M_CPL_RX_PKT_IPSEC_RXCHANNEL 0xf 5493 #define V_CPL_RX_PKT_IPSEC_RXCHANNEL(x) ((x) << S_CPL_RX_PKT_IPSEC_RXCHANNEL) 5494 #define G_CPL_RX_PKT_IPSEC_RXCHANNEL(x) \ 5495 (((x) >> S_CPL_RX_PKT_IPSEC_RXCHANNEL) & M_CPL_RX_PKT_IPSEC_RXCHANNEL) 5496 5497 #define S_CPL_RX_PKT_IPSEC_FLAGS 20 5498 #define M_CPL_RX_PKT_IPSEC_FLAGS 0xff 5499 #define V_CPL_RX_PKT_IPSEC_FLAGS(x) ((x) << S_CPL_RX_PKT_IPSEC_FLAGS) 5500 #define G_CPL_RX_PKT_IPSEC_FLAGS(x) \ 5501 (((x) >> S_CPL_RX_PKT_IPSEC_FLAGS) & M_CPL_RX_PKT_IPSEC_FLAGS) 5502 5503 #define S_CPL_RX_PKT_IPSEC_MACMATCHTYPE 17 5504 #define M_CPL_RX_PKT_IPSEC_MACMATCHTYPE 0x7 5505 #define V_CPL_RX_PKT_IPSEC_MACMATCHTYPE(x) \ 5506 ((x) << S_CPL_RX_PKT_IPSEC_MACMATCHTYPE) 5507 #define G_CPL_RX_PKT_IPSEC_MACMATCHTYPE(x) \ 5508 (((x) >> S_CPL_RX_PKT_IPSEC_MACMATCHTYPE) & \ 5509 M_CPL_RX_PKT_IPSEC_MACMATCHTYPE) 5510 5511 #define S_CPL_RX_PKT_IPSEC_MACINDEX 8 5512 #define M_CPL_RX_PKT_IPSEC_MACINDEX 0x1ff 5513 #define V_CPL_RX_PKT_IPSEC_MACINDEX(x) ((x) << S_CPL_RX_PKT_IPSEC_MACINDEX) 5514 #define G_CPL_RX_PKT_IPSEC_MACINDEX(x) \ 5515 (((x) >> S_CPL_RX_PKT_IPSEC_MACINDEX) & M_CPL_RX_PKT_IPSEC_MACINDEX) 5516 5517 #define S_CPL_RX_PKT_IPSEC_ETHHDRLEN 0 5518 #define M_CPL_RX_PKT_IPSEC_ETHHDRLEN 0xff 5519 #define V_CPL_RX_PKT_IPSEC_ETHHDRLEN(x) ((x) << S_CPL_RX_PKT_IPSEC_ETHHDRLEN) 5520 #define G_CPL_RX_PKT_IPSEC_ETHHDRLEN(x) \ 5521 (((x) >> S_CPL_RX_PKT_IPSEC_ETHHDRLEN) & M_CPL_RX_PKT_IPSEC_ETHHDRLEN) 5522 5523 #define S_CPL_RX_PKT_IPSEC_IPHDRLEN 22 5524 #define M_CPL_RX_PKT_IPSEC_IPHDRLEN 0x3ff 5525 #define V_CPL_RX_PKT_IPSEC_IPHDRLEN(x) ((x) << S_CPL_RX_PKT_IPSEC_IPHDRLEN) 5526 #define G_CPL_RX_PKT_IPSEC_IPHDRLEN(x) \ 5527 (((x) >> S_CPL_RX_PKT_IPSEC_IPHDRLEN) & M_CPL_RX_PKT_IPSEC_IPHDRLEN) 5528 5529 #define S_CPL_RX_PKT_IPSEC_TCPHDRLEN 16 5530 #define M_CPL_RX_PKT_IPSEC_TCPHDRLEN 0x3f 5531 #define V_CPL_RX_PKT_IPSEC_TCPHDRLEN(x) ((x) << S_CPL_RX_PKT_IPSEC_TCPHDRLEN) 5532 #define G_CPL_RX_PKT_IPSEC_TCPHDRLEN(x) \ 5533 (((x) >> S_CPL_RX_PKT_IPSEC_TCPHDRLEN) & M_CPL_RX_PKT_IPSEC_TCPHDRLEN) 5534 5535 #define S_CPL_RX_PKT_IPSEC_RXERROR 0 5536 #define M_CPL_RX_PKT_IPSEC_RXERROR 0xffff 5537 #define V_CPL_RX_PKT_IPSEC_RXERROR(x) ((x) << S_CPL_RX_PKT_IPSEC_RXERROR) 5538 #define G_CPL_RX_PKT_IPSEC_RXERROR(x) \ 5539 (((x) >> S_CPL_RX_PKT_IPSEC_RXERROR) & M_CPL_RX_PKT_IPSEC_RXERROR) 5540 5541 struct cpl_tx_sec_pdu { 5542 __be32 op_ivinsrtofst; 5543 __be32 pldlen; 5544 __be32 aadstart_cipherstop_hi; 5545 __be32 cipherstop_lo_authinsert; 5546 __be32 seqno_numivs; 5547 __be32 ivgen_hdrlen; 5548 __be64 scmd1; 5549 }; 5550 5551 #define S_CPL_TX_SEC_PDU_OPCODE 24 5552 #define M_CPL_TX_SEC_PDU_OPCODE 0xff 5553 #define V_CPL_TX_SEC_PDU_OPCODE(x) ((x) << S_CPL_TX_SEC_PDU_OPCODE) 5554 #define G_CPL_TX_SEC_PDU_OPCODE(x) \ 5555 (((x) >> S_CPL_TX_SEC_PDU_OPCODE) & M_CPL_TX_SEC_PDU_OPCODE) 5556 5557 /* RX Channel Id */ 5558 #define S_CPL_TX_SEC_PDU_RXCHID 22 5559 #define M_CPL_TX_SEC_PDU_RXCHID 0x1 5560 #define V_CPL_TX_SEC_PDU_RXCHID(x) ((x) << S_CPL_TX_SEC_PDU_RXCHID) 5561 #define G_CPL_TX_SEC_PDU_RXCHID(x) \ 5562 (((x) >> S_CPL_TX_SEC_PDU_RXCHID) & M_CPL_TX_SEC_PDU_RXCHID) 5563 #define F_CPL_TX_SEC_PDU_RXCHID V_CPL_TX_SEC_PDU_RXCHID(1U) 5564 5565 #define S_T7_CPL_TX_SEC_PDU_RXCHID 22 5566 #define M_T7_CPL_TX_SEC_PDU_RXCHID 0x3 5567 #define V_T7_CPL_TX_SEC_PDU_RXCHID(x) ((x) << S_T7_CPL_TX_SEC_PDU_RXCHID) 5568 #define G_T7_CPL_TX_SEC_PDU_RXCHID(x) \ 5569 (((x) >> S_T7_CPL_TX_SEC_PDU_RXCHID) & M_T7_CPL_TX_SEC_PDU_RXCHID) 5570 #define F_T7_CPL_TX_SEC_PDU_RXCHID V_T7_CPL_TX_SEC_PDU_RXCHID(1U) 5571 5572 /* Ack Follows */ 5573 #define S_CPL_TX_SEC_PDU_ACKFOLLOWS 21 5574 #define M_CPL_TX_SEC_PDU_ACKFOLLOWS 0x1 5575 #define V_CPL_TX_SEC_PDU_ACKFOLLOWS(x) ((x) << S_CPL_TX_SEC_PDU_ACKFOLLOWS) 5576 #define G_CPL_TX_SEC_PDU_ACKFOLLOWS(x) \ 5577 (((x) >> S_CPL_TX_SEC_PDU_ACKFOLLOWS) & M_CPL_TX_SEC_PDU_ACKFOLLOWS) 5578 #define F_CPL_TX_SEC_PDU_ACKFOLLOWS V_CPL_TX_SEC_PDU_ACKFOLLOWS(1U) 5579 5580 /* Loopback bit in cpl_tx_sec_pdu */ 5581 #define S_CPL_TX_SEC_PDU_ULPTXLPBK 20 5582 #define M_CPL_TX_SEC_PDU_ULPTXLPBK 0x1 5583 #define V_CPL_TX_SEC_PDU_ULPTXLPBK(x) ((x) << S_CPL_TX_SEC_PDU_ULPTXLPBK) 5584 #define G_CPL_TX_SEC_PDU_ULPTXLPBK(x) \ 5585 (((x) >> S_CPL_TX_SEC_PDU_ULPTXLPBK) & M_CPL_TX_SEC_PDU_ULPTXLPBK) 5586 #define F_CPL_TX_SEC_PDU_ULPTXLPBK V_CPL_TX_SEC_PDU_ULPTXLPBK(1U) 5587 5588 /* Length of cpl header encapsulated */ 5589 #define S_CPL_TX_SEC_PDU_CPLLEN 16 5590 #define M_CPL_TX_SEC_PDU_CPLLEN 0xf 5591 #define V_CPL_TX_SEC_PDU_CPLLEN(x) ((x) << S_CPL_TX_SEC_PDU_CPLLEN) 5592 #define G_CPL_TX_SEC_PDU_CPLLEN(x) \ 5593 (((x) >> S_CPL_TX_SEC_PDU_CPLLEN) & M_CPL_TX_SEC_PDU_CPLLEN) 5594 5595 #define S_CPL_TX_SEC_PDU_ACKNEXT 15 5596 #define M_CPL_TX_SEC_PDU_ACKNEXT 0x1 5597 #define V_CPL_TX_SEC_PDU_ACKNEXT(x) ((x) << S_CPL_TX_SEC_PDU_ACKNEXT) 5598 #define G_CPL_TX_SEC_PDU_ACKNEXT(x) \ 5599 (((x) >> S_CPL_TX_SEC_PDU_ACKNEXT) & M_CPL_TX_SEC_PDU_ACKNEXT) 5600 #define F_CPL_TX_SEC_PDU_ACKNEXT V_CPL_TX_SEC_PDU_ACKNEXT(1U) 5601 5602 /* PlaceHolder */ 5603 #define S_CPL_TX_SEC_PDU_PLACEHOLDER 10 5604 #define M_CPL_TX_SEC_PDU_PLACEHOLDER 0x1 5605 #define V_CPL_TX_SEC_PDU_PLACEHOLDER(x) ((x) << S_CPL_TX_SEC_PDU_PLACEHOLDER) 5606 #define G_CPL_TX_SEC_PDU_PLACEHOLDER(x) \ 5607 (((x) >> S_CPL_TX_SEC_PDU_PLACEHOLDER) & \ 5608 M_CPL_TX_SEC_PDU_PLACEHOLDER) 5609 5610 /* IvInsrtOffset: Insertion location for IV */ 5611 #define S_CPL_TX_SEC_PDU_IVINSRTOFST 0 5612 #define M_CPL_TX_SEC_PDU_IVINSRTOFST 0x3ff 5613 #define V_CPL_TX_SEC_PDU_IVINSRTOFST(x) ((x) << S_CPL_TX_SEC_PDU_IVINSRTOFST) 5614 #define G_CPL_TX_SEC_PDU_IVINSRTOFST(x) \ 5615 (((x) >> S_CPL_TX_SEC_PDU_IVINSRTOFST) & \ 5616 M_CPL_TX_SEC_PDU_IVINSRTOFST) 5617 5618 #define S_CPL_TX_SEC_PDU_PLDLEN 0 5619 #define M_CPL_TX_SEC_PDU_PLDLEN 0xfffff 5620 #define V_CPL_TX_SEC_PDU_PLDLEN(x) ((x) << S_CPL_TX_SEC_PDU_PLDLEN) 5621 #define G_CPL_TX_SEC_PDU_PLDLEN(x) \ 5622 (((x) >> S_CPL_TX_SEC_PDU_PLDLEN) & M_CPL_TX_SEC_PDU_PLDLEN) 5623 5624 /* AadStartOffset: Offset in bytes for AAD start from 5625 * the first byte following 5626 * the pkt headers (0-255 5627 * bytes) */ 5628 #define S_CPL_TX_SEC_PDU_AADSTART 24 5629 #define M_CPL_TX_SEC_PDU_AADSTART 0xff 5630 #define V_CPL_TX_SEC_PDU_AADSTART(x) ((x) << S_CPL_TX_SEC_PDU_AADSTART) 5631 #define G_CPL_TX_SEC_PDU_AADSTART(x) \ 5632 (((x) >> S_CPL_TX_SEC_PDU_AADSTART) & \ 5633 M_CPL_TX_SEC_PDU_AADSTART) 5634 5635 /* AadStopOffset: offset in bytes for AAD stop/end from the first byte following 5636 * the pkt headers (0-511 bytes) */ 5637 #define S_CPL_TX_SEC_PDU_AADSTOP 15 5638 #define M_CPL_TX_SEC_PDU_AADSTOP 0x1ff 5639 #define V_CPL_TX_SEC_PDU_AADSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AADSTOP) 5640 #define G_CPL_TX_SEC_PDU_AADSTOP(x) \ 5641 (((x) >> S_CPL_TX_SEC_PDU_AADSTOP) & M_CPL_TX_SEC_PDU_AADSTOP) 5642 5643 /* CipherStartOffset: offset in bytes for encryption/decryption start from the 5644 * first byte following the pkt headers (0-1023 5645 * bytes) */ 5646 #define S_CPL_TX_SEC_PDU_CIPHERSTART 5 5647 #define M_CPL_TX_SEC_PDU_CIPHERSTART 0x3ff 5648 #define V_CPL_TX_SEC_PDU_CIPHERSTART(x) ((x) << S_CPL_TX_SEC_PDU_CIPHERSTART) 5649 #define G_CPL_TX_SEC_PDU_CIPHERSTART(x) \ 5650 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTART) & \ 5651 M_CPL_TX_SEC_PDU_CIPHERSTART) 5652 5653 /* CipherStopOffset: offset in bytes for encryption/decryption end 5654 * from end of the payload of this command (0-511 bytes) */ 5655 #define S_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0 5656 #define M_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0x1f 5657 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 5658 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 5659 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 5660 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) & \ 5661 M_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 5662 5663 #define S_CPL_TX_SEC_PDU_CIPHERSTOP_LO 28 5664 #define M_CPL_TX_SEC_PDU_CIPHERSTOP_LO 0xf 5665 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 5666 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 5667 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 5668 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) & \ 5669 M_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 5670 5671 /* AuthStartOffset: offset in bytes for authentication start from 5672 * the first byte following the pkt headers (0-1023) 5673 * */ 5674 #define S_CPL_TX_SEC_PDU_AUTHSTART 18 5675 #define M_CPL_TX_SEC_PDU_AUTHSTART 0x3ff 5676 #define V_CPL_TX_SEC_PDU_AUTHSTART(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTART) 5677 #define G_CPL_TX_SEC_PDU_AUTHSTART(x) \ 5678 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTART) & \ 5679 M_CPL_TX_SEC_PDU_AUTHSTART) 5680 5681 /* AuthStopOffset: offset in bytes for authentication 5682 * end from end of the payload of this command (0-511 Bytes) */ 5683 #define S_CPL_TX_SEC_PDU_AUTHSTOP 9 5684 #define M_CPL_TX_SEC_PDU_AUTHSTOP 0x1ff 5685 #define V_CPL_TX_SEC_PDU_AUTHSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTOP) 5686 #define G_CPL_TX_SEC_PDU_AUTHSTOP(x) \ 5687 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTOP) & \ 5688 M_CPL_TX_SEC_PDU_AUTHSTOP) 5689 5690 /* AuthInsrtOffset: offset in bytes for authentication insertion 5691 * from end of the payload of this command (0-511 bytes) */ 5692 #define S_CPL_TX_SEC_PDU_AUTHINSERT 0 5693 #define M_CPL_TX_SEC_PDU_AUTHINSERT 0x1ff 5694 #define V_CPL_TX_SEC_PDU_AUTHINSERT(x) ((x) << S_CPL_TX_SEC_PDU_AUTHINSERT) 5695 #define G_CPL_TX_SEC_PDU_AUTHINSERT(x) \ 5696 (((x) >> S_CPL_TX_SEC_PDU_AUTHINSERT) & \ 5697 M_CPL_TX_SEC_PDU_AUTHINSERT) 5698 5699 struct cpl_rx_phys_dsgl { 5700 __be32 op_to_tid; 5701 __be32 pcirlxorder_to_noofsgentr; 5702 struct rss_header rss_hdr_int; 5703 }; 5704 5705 #define S_CPL_RX_PHYS_DSGL_OPCODE 24 5706 #define M_CPL_RX_PHYS_DSGL_OPCODE 0xff 5707 #define V_CPL_RX_PHYS_DSGL_OPCODE(x) ((x) << S_CPL_RX_PHYS_DSGL_OPCODE) 5708 #define G_CPL_RX_PHYS_DSGL_OPCODE(x) \ 5709 (((x) >> S_CPL_RX_PHYS_DSGL_OPCODE) & M_CPL_RX_PHYS_DSGL_OPCODE) 5710 5711 #define S_CPL_RX_PHYS_DSGL_ISRDMA 23 5712 #define M_CPL_RX_PHYS_DSGL_ISRDMA 0x1 5713 #define V_CPL_RX_PHYS_DSGL_ISRDMA(x) ((x) << S_CPL_RX_PHYS_DSGL_ISRDMA) 5714 #define G_CPL_RX_PHYS_DSGL_ISRDMA(x) \ 5715 (((x) >> S_CPL_RX_PHYS_DSGL_ISRDMA) & M_CPL_RX_PHYS_DSGL_ISRDMA) 5716 #define F_CPL_RX_PHYS_DSGL_ISRDMA V_CPL_RX_PHYS_DSGL_ISRDMA(1U) 5717 5718 #define S_CPL_RX_PHYS_DSGL_RSVD1 20 5719 #define M_CPL_RX_PHYS_DSGL_RSVD1 0x7 5720 #define V_CPL_RX_PHYS_DSGL_RSVD1(x) ((x) << S_CPL_RX_PHYS_DSGL_RSVD1) 5721 #define G_CPL_RX_PHYS_DSGL_RSVD1(x) \ 5722 (((x) >> S_CPL_RX_PHYS_DSGL_RSVD1) & M_CPL_RX_PHYS_DSGL_RSVD1) 5723 5724 #define S_CPL_RX_PHYS_DSGL_PCIRLXORDER 31 5725 #define M_CPL_RX_PHYS_DSGL_PCIRLXORDER 0x1 5726 #define V_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 5727 ((x) << S_CPL_RX_PHYS_DSGL_PCIRLXORDER) 5728 #define G_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 5729 (((x) >> S_CPL_RX_PHYS_DSGL_PCIRLXORDER) & \ 5730 M_CPL_RX_PHYS_DSGL_PCIRLXORDER) 5731 #define F_CPL_RX_PHYS_DSGL_PCIRLXORDER V_CPL_RX_PHYS_DSGL_PCIRLXORDER(1U) 5732 5733 #define S_CPL_RX_PHYS_DSGL_PCINOSNOOP 30 5734 #define M_CPL_RX_PHYS_DSGL_PCINOSNOOP 0x1 5735 #define V_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 5736 ((x) << S_CPL_RX_PHYS_DSGL_PCINOSNOOP) 5737 #define G_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 5738 (((x) >> S_CPL_RX_PHYS_DSGL_PCINOSNOOP) & \ 5739 M_CPL_RX_PHYS_DSGL_PCINOSNOOP) 5740 #define F_CPL_RX_PHYS_DSGL_PCINOSNOOP V_CPL_RX_PHYS_DSGL_PCINOSNOOP(1U) 5741 5742 #define S_CPL_RX_PHYS_DSGL_PCITPHNTENB 29 5743 #define M_CPL_RX_PHYS_DSGL_PCITPHNTENB 0x1 5744 #define V_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 5745 ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNTENB) 5746 #define G_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 5747 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNTENB) & \ 5748 M_CPL_RX_PHYS_DSGL_PCITPHNTENB) 5749 #define F_CPL_RX_PHYS_DSGL_PCITPHNTENB V_CPL_RX_PHYS_DSGL_PCITPHNTENB(1U) 5750 5751 #define S_CPL_RX_PHYS_DSGL_PCITPHNT 27 5752 #define M_CPL_RX_PHYS_DSGL_PCITPHNT 0x3 5753 #define V_CPL_RX_PHYS_DSGL_PCITPHNT(x) ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNT) 5754 #define G_CPL_RX_PHYS_DSGL_PCITPHNT(x) \ 5755 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNT) & \ 5756 M_CPL_RX_PHYS_DSGL_PCITPHNT) 5757 5758 #define S_CPL_RX_PHYS_DSGL_DCAID 16 5759 #define M_CPL_RX_PHYS_DSGL_DCAID 0x7ff 5760 #define V_CPL_RX_PHYS_DSGL_DCAID(x) ((x) << S_CPL_RX_PHYS_DSGL_DCAID) 5761 #define G_CPL_RX_PHYS_DSGL_DCAID(x) \ 5762 (((x) >> S_CPL_RX_PHYS_DSGL_DCAID) & \ 5763 M_CPL_RX_PHYS_DSGL_DCAID) 5764 5765 #define S_CPL_RX_PHYS_DSGL_NOOFSGENTR 0 5766 #define M_CPL_RX_PHYS_DSGL_NOOFSGENTR 0xffff 5767 #define V_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 5768 ((x) << S_CPL_RX_PHYS_DSGL_NOOFSGENTR) 5769 #define G_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 5770 (((x) >> S_CPL_RX_PHYS_DSGL_NOOFSGENTR) & \ 5771 M_CPL_RX_PHYS_DSGL_NOOFSGENTR) 5772 5773 struct cpl_t7_rx_phys_dsgl { 5774 RSS_HDR 5775 union opcode_tid ot; 5776 __be32 PhysAddrFields_lo_to_NumSGE; 5777 __be32 RSSCopy[2]; 5778 }; 5779 5780 #define S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI 0 5781 #define M_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI 0xffffff 5782 #define V_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI(x) \ 5783 ((x) << S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI) 5784 #define G_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI(x) \ 5785 (((x) >> S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI) & \ 5786 M_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI) 5787 5788 #define S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO 16 5789 #define M_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO 0xffff 5790 #define V_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO(x) \ 5791 ((x) << S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO) 5792 #define G_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO(x) \ 5793 (((x) >> S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO) & \ 5794 M_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO) 5795 5796 #define S_CPL_T7_RX_PHYS_DSGL_NUMSGEERR 11 5797 #define M_CPL_T7_RX_PHYS_DSGL_NUMSGEERR 0x1 5798 #define V_CPL_T7_RX_PHYS_DSGL_NUMSGEERR(x) \ 5799 ((x) << S_CPL_T7_RX_PHYS_DSGL_NUMSGEERR) 5800 #define G_CPL_T7_RX_PHYS_DSGL_NUMSGEERR(x) \ 5801 (((x) >> S_CPL_T7_RX_PHYS_DSGL_NUMSGEERR) & M_CPL_T7_RX_PHYS_DSGL_NUMSGEERR) 5802 #define F_CPL_T7_RX_PHYS_DSGL_NUMSGEERR V_CPL_T7_RX_PHYS_DSGL_NUMSGEERR(1U) 5803 5804 #define S_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE 10 5805 #define M_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE 0x1 5806 #define V_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE(x) \ 5807 ((x) << S_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE) 5808 #define G_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE(x) \ 5809 (((x) >> S_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE) & \ 5810 M_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE) 5811 #define F_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE \ 5812 V_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE(1U) 5813 5814 #define S_CPL_T7_RX_PHYS_DSGL_SPLITMODE 9 5815 #define M_CPL_T7_RX_PHYS_DSGL_SPLITMODE 0x1 5816 #define V_CPL_T7_RX_PHYS_DSGL_SPLITMODE(x) \ 5817 ((x) << S_CPL_T7_RX_PHYS_DSGL_SPLITMODE) 5818 #define G_CPL_T7_RX_PHYS_DSGL_SPLITMODE(x) \ 5819 (((x) >> S_CPL_T7_RX_PHYS_DSGL_SPLITMODE) & M_CPL_T7_RX_PHYS_DSGL_SPLITMODE) 5820 #define F_CPL_T7_RX_PHYS_DSGL_SPLITMODE \ 5821 V_CPL_T7_RX_PHYS_DSGL_SPLITMODE(1U) 5822 5823 #define S_CPL_T7_RX_PHYS_DSGL_NUMSGE 0 5824 #define M_CPL_T7_RX_PHYS_DSGL_NUMSGE 0x1ff 5825 #define V_CPL_T7_RX_PHYS_DSGL_NUMSGE(x) ((x) << S_CPL_T7_RX_PHYS_DSGL_NUMSGE) 5826 #define G_CPL_T7_RX_PHYS_DSGL_NUMSGE(x) \ 5827 (((x) >> S_CPL_T7_RX_PHYS_DSGL_NUMSGE) & M_CPL_T7_RX_PHYS_DSGL_NUMSGE) 5828 5829 /* CPL_TX_TLS_ACK */ 5830 struct cpl_tx_tls_ack { 5831 __be32 op_to_Rsvd2; 5832 __be32 PldLen; 5833 __be64 Rsvd3; 5834 }; 5835 5836 #define S_CPL_TX_TLS_ACK_OPCODE 24 5837 #define M_CPL_TX_TLS_ACK_OPCODE 0xff 5838 #define V_CPL_TX_TLS_ACK_OPCODE(x) ((x) << S_CPL_TX_TLS_ACK_OPCODE) 5839 #define G_CPL_TX_TLS_ACK_OPCODE(x) \ 5840 (((x) >> S_CPL_TX_TLS_ACK_OPCODE) & M_CPL_TX_TLS_ACK_OPCODE) 5841 5842 #define S_T7_CPL_TX_TLS_ACK_RXCHID 22 5843 #define M_T7_CPL_TX_TLS_ACK_RXCHID 0x3 5844 #define V_T7_CPL_TX_TLS_ACK_RXCHID(x) ((x) << S_T7_CPL_TX_TLS_ACK_RXCHID) 5845 #define G_T7_CPL_TX_TLS_ACK_RXCHID(x) \ 5846 (((x) >> S_T7_CPL_TX_TLS_ACK_RXCHID) & M_T7_CPL_TX_TLS_ACK_RXCHID) 5847 5848 #define S_CPL_TX_TLS_ACK_RXCHID 22 5849 #define M_CPL_TX_TLS_ACK_RXCHID 0x1 5850 #define V_CPL_TX_TLS_ACK_RXCHID(x) ((x) << S_CPL_TX_TLS_ACK_RXCHID) 5851 #define G_CPL_TX_TLS_ACK_RXCHID(x) \ 5852 (((x) >> S_CPL_TX_TLS_ACK_RXCHID) & M_CPL_TX_TLS_ACK_RXCHID) 5853 #define F_CPL_TX_TLS_ACK_RXCHID V_CPL_TX_TLS_ACK_RXCHID(1U) 5854 5855 #define S_CPL_TX_TLS_ACK_FWMSG 21 5856 #define M_CPL_TX_TLS_ACK_FWMSG 0x1 5857 #define V_CPL_TX_TLS_ACK_FWMSG(x) ((x) << S_CPL_TX_TLS_ACK_FWMSG) 5858 #define G_CPL_TX_TLS_ACK_FWMSG(x) \ 5859 (((x) >> S_CPL_TX_TLS_ACK_FWMSG) & M_CPL_TX_TLS_ACK_FWMSG) 5860 #define F_CPL_TX_TLS_ACK_FWMSG V_CPL_TX_TLS_ACK_FWMSG(1U) 5861 5862 #define S_CPL_TX_TLS_ACK_ULPTXLPBK 20 5863 #define M_CPL_TX_TLS_ACK_ULPTXLPBK 0x1 5864 #define V_CPL_TX_TLS_ACK_ULPTXLPBK(x) ((x) << S_CPL_TX_TLS_ACK_ULPTXLPBK) 5865 #define G_CPL_TX_TLS_ACK_ULPTXLPBK(x) \ 5866 (((x) >> S_CPL_TX_TLS_ACK_ULPTXLPBK) & M_CPL_TX_TLS_ACK_ULPTXLPBK) 5867 #define F_CPL_TX_TLS_ACK_ULPTXLPBK V_CPL_TX_TLS_ACK_ULPTXLPBK(1U) 5868 5869 #define S_CPL_TX_TLS_ACK_CPLLEN 16 5870 #define M_CPL_TX_TLS_ACK_CPLLEN 0xf 5871 #define V_CPL_TX_TLS_ACK_CPLLEN(x) ((x) << S_CPL_TX_TLS_ACK_CPLLEN) 5872 #define G_CPL_TX_TLS_ACK_CPLLEN(x) \ 5873 (((x) >> S_CPL_TX_TLS_ACK_CPLLEN) & M_CPL_TX_TLS_ACK_CPLLEN) 5874 5875 #define S_CPL_TX_TLS_ACK_COMPLONERR 15 5876 #define M_CPL_TX_TLS_ACK_COMPLONERR 0x1 5877 #define V_CPL_TX_TLS_ACK_COMPLONERR(x) ((x) << S_CPL_TX_TLS_ACK_COMPLONERR) 5878 #define G_CPL_TX_TLS_ACK_COMPLONERR(x) \ 5879 (((x) >> S_CPL_TX_TLS_ACK_COMPLONERR) & M_CPL_TX_TLS_ACK_COMPLONERR) 5880 #define F_CPL_TX_TLS_ACK_COMPLONERR V_CPL_TX_TLS_ACK_COMPLONERR(1U) 5881 5882 #define S_CPL_TX_TLS_ACK_LCB 14 5883 #define M_CPL_TX_TLS_ACK_LCB 0x1 5884 #define V_CPL_TX_TLS_ACK_LCB(x) ((x) << S_CPL_TX_TLS_ACK_LCB) 5885 #define G_CPL_TX_TLS_ACK_LCB(x) \ 5886 (((x) >> S_CPL_TX_TLS_ACK_LCB) & M_CPL_TX_TLS_ACK_LCB) 5887 #define F_CPL_TX_TLS_ACK_LCB V_CPL_TX_TLS_ACK_LCB(1U) 5888 5889 #define S_CPL_TX_TLS_ACK_PHASH 13 5890 #define M_CPL_TX_TLS_ACK_PHASH 0x1 5891 #define V_CPL_TX_TLS_ACK_PHASH(x) ((x) << S_CPL_TX_TLS_ACK_PHASH) 5892 #define G_CPL_TX_TLS_ACK_PHASH(x) \ 5893 (((x) >> S_CPL_TX_TLS_ACK_PHASH) & M_CPL_TX_TLS_ACK_PHASH) 5894 #define F_CPL_TX_TLS_ACK_PHASH V_CPL_TX_TLS_ACK_PHASH(1U) 5895 5896 #define S_CPL_TX_TLS_ACK_RSVD2 0 5897 #define M_CPL_TX_TLS_ACK_RSVD2 0x1fff 5898 #define V_CPL_TX_TLS_ACK_RSVD2(x) ((x) << S_CPL_TX_TLS_ACK_RSVD2) 5899 #define G_CPL_TX_TLS_ACK_RSVD2(x) \ 5900 (((x) >> S_CPL_TX_TLS_ACK_RSVD2) & M_CPL_TX_TLS_ACK_RSVD2) 5901 5902 #define S_CPL_TX_TLS_ACK_PLDLEN 0 5903 #define M_CPL_TX_TLS_ACK_PLDLEN 0xfffff 5904 #define V_CPL_TX_TLS_ACK_PLDLEN(x) ((x) << S_CPL_TX_TLS_ACK_PLDLEN) 5905 #define G_CPL_TX_TLS_ACK_PLDLEN(x) \ 5906 (((x) >> S_CPL_TX_TLS_ACK_PLDLEN) & M_CPL_TX_TLS_ACK_PLDLEN) 5907 5908 struct cpl_rcb_upd { 5909 __be32 op_to_tid; 5910 __be32 opcode_psn; 5911 __u8 nodata_to_cnprepclr; 5912 __u8 r0; 5913 __be16 wrptr; 5914 __be32 length; 5915 }; 5916 5917 #define S_CPL_RCB_UPD_OPCODE 24 5918 #define M_CPL_RCB_UPD_OPCODE 0xff 5919 #define V_CPL_RCB_UPD_OPCODE(x) ((x) << S_CPL_RCB_UPD_OPCODE) 5920 #define G_CPL_RCB_UPD_OPCODE(x) \ 5921 (((x) >> S_CPL_RCB_UPD_OPCODE) & M_CPL_RCB_UPD_OPCODE) 5922 5923 #define S_CPL_RCB_UPD_TID 0 5924 #define M_CPL_RCB_UPD_TID 0xffffff 5925 #define V_CPL_RCB_UPD_TID(x) ((x) << S_CPL_RCB_UPD_TID) 5926 #define G_CPL_RCB_UPD_TID(x) \ 5927 (((x) >> S_CPL_RCB_UPD_TID) & M_CPL_RCB_UPD_TID) 5928 5929 #define S_CPL_RCB_UPD_OPCODE 24 5930 #define M_CPL_RCB_UPD_OPCODE 0xff 5931 #define V_CPL_RCB_UPD_OPCODE(x) ((x) << S_CPL_RCB_UPD_OPCODE) 5932 #define G_CPL_RCB_UPD_OPCODE(x) \ 5933 (((x) >> S_CPL_RCB_UPD_OPCODE) & M_CPL_RCB_UPD_OPCODE) 5934 5935 #define S_CPL_RCB_UPD_PSN 0 5936 #define M_CPL_RCB_UPD_PSN 0xffffff 5937 #define V_CPL_RCB_UPD_PSN(x) ((x) << S_CPL_RCB_UPD_PSN) 5938 #define G_CPL_RCB_UPD_PSN(x) \ 5939 (((x) >> S_CPL_RCB_UPD_PSN) & M_CPL_RCB_UPD_PSN) 5940 5941 #define S_CPL_RCB_UPD_NODATA 7 5942 #define M_CPL_RCB_UPD_NODATA 0x1 5943 #define V_CPL_RCB_UPD_NODATA(x) ((x) << S_CPL_RCB_UPD_NODATA) 5944 #define G_CPL_RCB_UPD_NODATA(x) \ 5945 (((x) >> S_CPL_RCB_UPD_NODATA) & M_CPL_RCB_UPD_NODATA) 5946 #define F_CPL_RCB_UPD_NODATA V_CPL_RCB_UPD_NODATA(1U) 5947 5948 #define S_CPL_RCB_UPD_RTTSTAMP 6 5949 #define M_CPL_RCB_UPD_RTTSTAMP 0x1 5950 #define V_CPL_RCB_UPD_RTTSTAMP(x) ((x) << S_CPL_RCB_UPD_RTTSTAMP) 5951 #define G_CPL_RCB_UPD_RTTSTAMP(x) \ 5952 (((x) >> S_CPL_RCB_UPD_RTTSTAMP) & M_CPL_RCB_UPD_RTTSTAMP) 5953 #define F_CPL_RCB_UPD_RTTSTAMP V_CPL_RCB_UPD_RTTSTAMP(1U) 5954 5955 #define S_CPL_RCB_UPD_ECNREPCLR 5 5956 #define M_CPL_RCB_UPD_ECNREPCLR 0x1 5957 #define V_CPL_RCB_UPD_ECNREPCLR(x) ((x) << S_CPL_RCB_UPD_ECNREPCLR) 5958 #define G_CPL_RCB_UPD_ECNREPCLR(x) \ 5959 (((x) >> S_CPL_RCB_UPD_ECNREPCLR) & M_CPL_RCB_UPD_ECNREPCLR) 5960 #define F_CPL_RCB_UPD_ECNREPCLR V_CPL_RCB_UPD_ECNREPCLR(1U) 5961 5962 #define S_CPL_RCB_UPD_NAKSEQCLR 4 5963 #define M_CPL_RCB_UPD_NAKSEQCLR 0x1 5964 #define V_CPL_RCB_UPD_NAKSEQCLR(x) ((x) << S_CPL_RCB_UPD_NAKSEQCLR) 5965 #define G_CPL_RCB_UPD_NAKSEQCLR(x) \ 5966 (((x) >> S_CPL_RCB_UPD_NAKSEQCLR) & M_CPL_RCB_UPD_NAKSEQCLR) 5967 #define F_CPL_RCB_UPD_NAKSEQCLR V_CPL_RCB_UPD_NAKSEQCLR(1U) 5968 5969 #define S_CPL_RCB_UPD_QPERRSET 3 5970 #define M_CPL_RCB_UPD_QPERRSET 0x1 5971 #define V_CPL_RCB_UPD_QPERRSET(x) ((x) << S_CPL_RCB_UPD_QPERRSET) 5972 #define G_CPL_RCB_UPD_QPERRSET(x) \ 5973 (((x) >> S_CPL_RCB_UPD_QPERRSET) & M_CPL_RCB_UPD_QPERRSET) 5974 #define F_CPL_RCB_UPD_QPERRSET V_CPL_RCB_UPD_QPERRSET(1U) 5975 5976 #define S_CPL_RCB_UPD_RRQUPDEN 2 5977 #define M_CPL_RCB_UPD_RRQUPDEN 0x1 5978 #define V_CPL_RCB_UPD_RRQUPDEN(x) ((x) << S_CPL_RCB_UPD_RRQUPDEN) 5979 #define G_CPL_RCB_UPD_RRQUPDEN(x) \ 5980 (((x) >> S_CPL_RCB_UPD_RRQUPDEN) & M_CPL_RCB_UPD_RRQUPDEN) 5981 #define F_CPL_RCB_UPD_RRQUPDEN V_CPL_RCB_UPD_RRQUPDEN(1U) 5982 5983 #define S_CPL_RCB_UPD_RQUPDEN 1 5984 #define M_CPL_RCB_UPD_RQUPDEN 0x1 5985 #define V_CPL_RCB_UPD_RQUPDEN(x) ((x) << S_CPL_RCB_UPD_RQUPDEN) 5986 #define G_CPL_RCB_UPD_RQUPDEN(x) \ 5987 (((x) >> S_CPL_RCB_UPD_RQUPDEN) & M_CPL_RCB_UPD_RQUPDEN) 5988 #define F_CPL_RCB_UPD_RQUPDEN V_CPL_RCB_UPD_RQUPDEN(1U) 5989 5990 #define S_CPL_RCB_UPD_CNPREPCLR 0 5991 #define M_CPL_RCB_UPD_CNPREPCLR 0x1 5992 #define V_CPL_RCB_UPD_CNPREPCLR(x) ((x) << S_CPL_RCB_UPD_CNPREPCLR) 5993 #define G_CPL_RCB_UPD_CNPREPCLR(x) \ 5994 (((x) >> S_CPL_RCB_UPD_CNPREPCLR) & M_CPL_RCB_UPD_CNPREPCLR) 5995 #define F_CPL_RCB_UPD_CNPREPCLR V_CPL_RCB_UPD_CNPREPCLR(1U) 5996 5997 #define S_CPL_RCB_UPD_RSPNAKSEQCLR 7 5998 #define M_CPL_RCB_UPD_RSPNAKSEQCLR 0x1 5999 #define V_CPL_RCB_UPD_RSPNAKSEQCLR(x) ((x) << S_CPL_RCB_UPD_RSPNAKSEQCLR) 6000 #define G_CPL_RCB_UPD_RSPNAKSEQCLR(x) \ 6001 (((x) >> S_CPL_RCB_UPD_RSPNAKSEQCLR) & M_CPL_RCB_UPD_RSPNAKSEQCLR) 6002 #define F_CPL_RCB_UPD_RSPNAKSEQCLR V_CPL_RCB_UPD_RSPNAKSEQCLR(1U) 6003 6004 struct cpl_roce_fw_notify { 6005 RSS_HDR 6006 union opcode_tid ot; 6007 __be32 type_pkd; 6008 }; 6009 6010 #define S_CPL_ROCE_FW_NOTIFY_OPCODE 24 6011 #define M_CPL_ROCE_FW_NOTIFY_OPCODE 0xff 6012 #define V_CPL_ROCE_FW_NOTIFY_OPCODE(x) ((x) << S_CPL_ROCE_FW_NOTIFY_OPCODE) 6013 #define G_CPL_ROCE_FW_NOTIFY_OPCODE(x) \ 6014 (((x) >> S_CPL_ROCE_FW_NOTIFY_OPCODE) & M_CPL_ROCE_FW_NOTIFY_OPCODE) 6015 6016 #define S_CPL_ROCE_FW_NOTIFY_TID 0 6017 #define M_CPL_ROCE_FW_NOTIFY_TID 0xffffff 6018 #define V_CPL_ROCE_FW_NOTIFY_TID(x) ((x) << S_CPL_ROCE_FW_NOTIFY_TID) 6019 #define G_CPL_ROCE_FW_NOTIFY_TID(x) \ 6020 (((x) >> S_CPL_ROCE_FW_NOTIFY_TID) & M_CPL_ROCE_FW_NOTIFY_TID) 6021 6022 #define S_CPL_ROCE_FW_NOTIFY_TYPE 28 6023 #define M_CPL_ROCE_FW_NOTIFY_TYPE 0xf 6024 #define V_CPL_ROCE_FW_NOTIFY_TYPE(x) ((x) << S_CPL_ROCE_FW_NOTIFY_TYPE) 6025 #define G_CPL_ROCE_FW_NOTIFY_TYPE(x) \ 6026 (((x) >> S_CPL_ROCE_FW_NOTIFY_TYPE) & M_CPL_ROCE_FW_NOTIFY_TYPE) 6027 6028 struct cpl_roce_ack_nak_req { 6029 RSS_HDR 6030 union opcode_tid ot; 6031 __be16 type_to_opcode; 6032 __be16 length; 6033 __be32 psn_msn_hi; 6034 __be32 msn_lo_pkd; 6035 }; 6036 6037 #define S_CPL_ROCE_ACK_NAK_REQ_OPCODE 24 6038 #define M_CPL_ROCE_ACK_NAK_REQ_OPCODE 0xff 6039 #define V_CPL_ROCE_ACK_NAK_REQ_OPCODE(x) \ 6040 ((x) << S_CPL_ROCE_ACK_NAK_REQ_OPCODE) 6041 #define G_CPL_ROCE_ACK_NAK_REQ_OPCODE(x) \ 6042 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_OPCODE) & M_CPL_ROCE_ACK_NAK_REQ_OPCODE) 6043 6044 #define S_CPL_ROCE_ACK_NAK_REQ_TID 0 6045 #define M_CPL_ROCE_ACK_NAK_REQ_TID 0xffffff 6046 #define V_CPL_ROCE_ACK_NAK_REQ_TID(x) ((x) << S_CPL_ROCE_ACK_NAK_REQ_TID) 6047 #define G_CPL_ROCE_ACK_NAK_REQ_TID(x) \ 6048 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_TID) & M_CPL_ROCE_ACK_NAK_REQ_TID) 6049 6050 #define S_CPL_ROCE_ACK_NAK_REQ_TYPE 12 6051 #define M_CPL_ROCE_ACK_NAK_REQ_TYPE 0xf 6052 #define V_CPL_ROCE_ACK_NAK_REQ_TYPE(x) ((x) << S_CPL_ROCE_ACK_NAK_REQ_TYPE) 6053 #define G_CPL_ROCE_ACK_NAK_REQ_TYPE(x) \ 6054 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_TYPE) & M_CPL_ROCE_ACK_NAK_REQ_TYPE) 6055 6056 #define S_CPL_ROCE_ACK_NAK_REQ_STATUS 8 6057 #define M_CPL_ROCE_ACK_NAK_REQ_STATUS 0xf 6058 #define V_CPL_ROCE_ACK_NAK_REQ_STATUS(x) \ 6059 ((x) << S_CPL_ROCE_ACK_NAK_REQ_STATUS) 6060 #define G_CPL_ROCE_ACK_NAK_REQ_STATUS(x) \ 6061 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_STATUS) & M_CPL_ROCE_ACK_NAK_REQ_STATUS) 6062 6063 #define S_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE 0 6064 #define M_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE 0xff 6065 #define V_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE(x) \ 6066 ((x) << S_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE) 6067 #define G_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE(x) \ 6068 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE) & M_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE) 6069 6070 #define S_CPL_ROCE_ACK_NAK_REQ_PSN 8 6071 #define M_CPL_ROCE_ACK_NAK_REQ_PSN 0xffffff 6072 #define V_CPL_ROCE_ACK_NAK_REQ_PSN(x) ((x) << S_CPL_ROCE_ACK_NAK_REQ_PSN) 6073 #define G_CPL_ROCE_ACK_NAK_REQ_PSN(x) \ 6074 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_PSN) & M_CPL_ROCE_ACK_NAK_REQ_PSN) 6075 6076 #define S_CPL_ROCE_ACK_NAK_REQ_MSN_HI 0 6077 #define M_CPL_ROCE_ACK_NAK_REQ_MSN_HI 0xff 6078 #define V_CPL_ROCE_ACK_NAK_REQ_MSN_HI(x) \ 6079 ((x) << S_CPL_ROCE_ACK_NAK_REQ_MSN_HI) 6080 #define G_CPL_ROCE_ACK_NAK_REQ_MSN_HI(x) \ 6081 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_MSN_HI) & M_CPL_ROCE_ACK_NAK_REQ_MSN_HI) 6082 6083 #define S_CPL_ROCE_ACK_NAK_REQ_MSN_LO 16 6084 #define M_CPL_ROCE_ACK_NAK_REQ_MSN_LO 0xffff 6085 #define V_CPL_ROCE_ACK_NAK_REQ_MSN_LO(x) \ 6086 ((x) << S_CPL_ROCE_ACK_NAK_REQ_MSN_LO) 6087 #define G_CPL_ROCE_ACK_NAK_REQ_MSN_LO(x) \ 6088 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_MSN_LO) & M_CPL_ROCE_ACK_NAK_REQ_MSN_LO) 6089 6090 struct cpl_roce_ack_nak { 6091 RSS_HDR 6092 union opcode_tid ot; 6093 __be16 type_to_opcode; 6094 __be16 length; 6095 __be32 psn_rtt_hi; 6096 __be32 rtt_lo_to_rttbad; 6097 }; 6098 6099 #define S_CPL_ROCE_ACK_NAK_OPCODE 24 6100 #define M_CPL_ROCE_ACK_NAK_OPCODE 0xff 6101 #define V_CPL_ROCE_ACK_NAK_OPCODE(x) ((x) << S_CPL_ROCE_ACK_NAK_OPCODE) 6102 #define G_CPL_ROCE_ACK_NAK_OPCODE(x) \ 6103 (((x) >> S_CPL_ROCE_ACK_NAK_OPCODE) & M_CPL_ROCE_ACK_NAK_OPCODE) 6104 6105 #define S_CPL_ROCE_ACK_NAK_TID 0 6106 #define M_CPL_ROCE_ACK_NAK_TID 0xffffff 6107 #define V_CPL_ROCE_ACK_NAK_TID(x) ((x) << S_CPL_ROCE_ACK_NAK_TID) 6108 #define G_CPL_ROCE_ACK_NAK_TID(x) \ 6109 (((x) >> S_CPL_ROCE_ACK_NAK_TID) & M_CPL_ROCE_ACK_NAK_TID) 6110 6111 #define S_CPL_ROCE_ACK_NAK_TYPE 12 6112 #define M_CPL_ROCE_ACK_NAK_TYPE 0xf 6113 #define V_CPL_ROCE_ACK_NAK_TYPE(x) ((x) << S_CPL_ROCE_ACK_NAK_TYPE) 6114 #define G_CPL_ROCE_ACK_NAK_TYPE(x) \ 6115 (((x) >> S_CPL_ROCE_ACK_NAK_TYPE) & M_CPL_ROCE_ACK_NAK_TYPE) 6116 6117 #define S_CPL_ROCE_ACK_NAK_STATUS 8 6118 #define M_CPL_ROCE_ACK_NAK_STATUS 0xf 6119 #define V_CPL_ROCE_ACK_NAK_STATUS(x) ((x) << S_CPL_ROCE_ACK_NAK_STATUS) 6120 #define G_CPL_ROCE_ACK_NAK_STATUS(x) \ 6121 (((x) >> S_CPL_ROCE_ACK_NAK_STATUS) & M_CPL_ROCE_ACK_NAK_STATUS) 6122 6123 #define S_CPL_ROCE_ACK_NAK_WIRE_OPCODE 0 6124 #define M_CPL_ROCE_ACK_NAK_WIRE_OPCODE 0xff 6125 #define V_CPL_ROCE_ACK_NAK_WIRE_OPCODE(x) ((x) << S_CPL_ROCE_ACK_NAK_WIRE_OPCODE) 6126 #define G_CPL_ROCE_ACK_NAK_WIRE_OPCODE(x) \ 6127 (((x) >> S_CPL_ROCE_ACK_NAK_WIRE_OPCODE) & M_CPL_ROCE_ACK_NAK_WIRE_OPCODE) 6128 6129 #define S_CPL_ROCE_ACK_NAK_PSN 8 6130 #define M_CPL_ROCE_ACK_NAK_PSN 0xffffff 6131 #define V_CPL_ROCE_ACK_NAK_PSN(x) ((x) << S_CPL_ROCE_ACK_NAK_PSN) 6132 #define G_CPL_ROCE_ACK_NAK_PSN(x) \ 6133 (((x) >> S_CPL_ROCE_ACK_NAK_PSN) & M_CPL_ROCE_ACK_NAK_PSN) 6134 6135 #define S_CPL_ROCE_ACK_NAK_RTT_HI 0 6136 #define M_CPL_ROCE_ACK_NAK_RTT_HI 0xff 6137 #define V_CPL_ROCE_ACK_NAK_RTT_HI(x) ((x) << S_CPL_ROCE_ACK_NAK_RTT_HI) 6138 #define G_CPL_ROCE_ACK_NAK_RTT_HI(x) \ 6139 (((x) >> S_CPL_ROCE_ACK_NAK_RTT_HI) & M_CPL_ROCE_ACK_NAK_RTT_HI) 6140 6141 #define S_CPL_ROCE_ACK_NAK_RTT_LO 24 6142 #define M_CPL_ROCE_ACK_NAK_RTT_LO 0xff 6143 #define V_CPL_ROCE_ACK_NAK_RTT_LO(x) ((x) << S_CPL_ROCE_ACK_NAK_RTT_LO) 6144 #define G_CPL_ROCE_ACK_NAK_RTT_LO(x) \ 6145 (((x) >> S_CPL_ROCE_ACK_NAK_RTT_LO) & M_CPL_ROCE_ACK_NAK_RTT_LO) 6146 6147 #define S_CPL_ROCE_ACK_NAK_RTTVALID 23 6148 #define M_CPL_ROCE_ACK_NAK_RTTVALID 0x1 6149 #define V_CPL_ROCE_ACK_NAK_RTTVALID(x) ((x) << S_CPL_ROCE_ACK_NAK_RTTVALID) 6150 #define G_CPL_ROCE_ACK_NAK_RTTVALID(x) \ 6151 (((x) >> S_CPL_ROCE_ACK_NAK_RTTVALID) & M_CPL_ROCE_ACK_NAK_RTTVALID) 6152 #define F_CPL_ROCE_ACK_NAK_RTTVALID V_CPL_ROCE_ACK_NAK_RTTVALID(1U) 6153 6154 #define S_CPL_ROCE_ACK_NAK_RTTBAD 22 6155 #define M_CPL_ROCE_ACK_NAK_RTTBAD 0x1 6156 #define V_CPL_ROCE_ACK_NAK_RTTBAD(x) ((x) << S_CPL_ROCE_ACK_NAK_RTTBAD) 6157 #define G_CPL_ROCE_ACK_NAK_RTTBAD(x) \ 6158 (((x) >> S_CPL_ROCE_ACK_NAK_RTTBAD) & M_CPL_ROCE_ACK_NAK_RTTBAD) 6159 #define F_CPL_ROCE_ACK_NAK_RTTBAD V_CPL_ROCE_ACK_NAK_RTTBAD(1U) 6160 6161 struct cpl_roce_cqe { 6162 __be16 op_rssctrl; 6163 __be16 cqid; 6164 __be32 tid_flitcnt; 6165 __be32 qpid_to_wr_type; 6166 __be32 length; 6167 __be32 tag; 6168 __be32 msn; 6169 __be32 se_to_srq; 6170 __be32 rqe; 6171 __be32 extinfoms[2]; 6172 __be32 extinfols[2]; 6173 }; 6174 6175 #define S_CPL_ROCE_CQE_OPCODE 8 6176 #define M_CPL_ROCE_CQE_OPCODE 0xff 6177 #define V_CPL_ROCE_CQE_OPCODE(x) ((x) << S_CPL_ROCE_CQE_OPCODE) 6178 #define G_CPL_ROCE_CQE_OPCODE(x) \ 6179 (((x) >> S_CPL_ROCE_CQE_OPCODE) & M_CPL_ROCE_CQE_OPCODE) 6180 6181 #define S_CPL_ROCE_CQE_RSSCTRL 0 6182 #define M_CPL_ROCE_CQE_RSSCTRL 0xff 6183 #define V_CPL_ROCE_CQE_RSSCTRL(x) ((x) << S_CPL_ROCE_CQE_RSSCTRL) 6184 #define G_CPL_ROCE_CQE_RSSCTRL(x) \ 6185 (((x) >> S_CPL_ROCE_CQE_RSSCTRL) & M_CPL_ROCE_CQE_RSSCTRL) 6186 6187 #define S_CPL_ROCE_CQE_TID 8 6188 #define M_CPL_ROCE_CQE_TID 0xfffff 6189 #define V_CPL_ROCE_CQE_TID(x) ((x) << S_CPL_ROCE_CQE_TID) 6190 #define G_CPL_ROCE_CQE_TID(x) \ 6191 (((x) >> S_CPL_ROCE_CQE_TID) & M_CPL_ROCE_CQE_TID) 6192 6193 #define S_CPL_ROCE_CQE_FLITCNT 0 6194 #define M_CPL_ROCE_CQE_FLITCNT 0xff 6195 #define V_CPL_ROCE_CQE_FLITCNT(x) ((x) << S_CPL_ROCE_CQE_FLITCNT) 6196 #define G_CPL_ROCE_CQE_FLITCNT(x) \ 6197 (((x) >> S_CPL_ROCE_CQE_FLITCNT) & M_CPL_ROCE_CQE_FLITCNT) 6198 6199 #define S_CPL_ROCE_CQE_QPID 12 6200 #define M_CPL_ROCE_CQE_QPID 0xfffff 6201 #define V_CPL_ROCE_CQE_QPID(x) ((x) << S_CPL_ROCE_CQE_QPID) 6202 #define G_CPL_ROCE_CQE_QPID(x) \ 6203 (((x) >> S_CPL_ROCE_CQE_QPID) & M_CPL_ROCE_CQE_QPID) 6204 6205 #define S_CPL_ROCE_CQE_EXTMODE 11 6206 #define M_CPL_ROCE_CQE_EXTMODE 0x1 6207 #define V_CPL_ROCE_CQE_EXTMODE(x) ((x) << S_CPL_ROCE_CQE_EXTMODE) 6208 #define G_CPL_ROCE_CQE_EXTMODE(x) \ 6209 (((x) >> S_CPL_ROCE_CQE_EXTMODE) & M_CPL_ROCE_CQE_EXTMODE) 6210 #define F_CPL_ROCE_CQE_EXTMODE V_CPL_ROCE_CQE_EXTMODE(1U) 6211 6212 #define S_CPL_ROCE_CQE_GENERATION_BIT 10 6213 #define M_CPL_ROCE_CQE_GENERATION_BIT 0x1 6214 #define V_CPL_ROCE_CQE_GENERATION_BIT(x) \ 6215 ((x) << S_CPL_ROCE_CQE_GENERATION_BIT) 6216 #define G_CPL_ROCE_CQE_GENERATION_BIT(x) \ 6217 (((x) >> S_CPL_ROCE_CQE_GENERATION_BIT) & M_CPL_ROCE_CQE_GENERATION_BIT) 6218 #define F_CPL_ROCE_CQE_GENERATION_BIT V_CPL_ROCE_CQE_GENERATION_BIT(1U) 6219 6220 #define S_CPL_ROCE_CQE_STATUS 5 6221 #define M_CPL_ROCE_CQE_STATUS 0x1f 6222 #define V_CPL_ROCE_CQE_STATUS(x) ((x) << S_CPL_ROCE_CQE_STATUS) 6223 #define G_CPL_ROCE_CQE_STATUS(x) \ 6224 (((x) >> S_CPL_ROCE_CQE_STATUS) & M_CPL_ROCE_CQE_STATUS) 6225 6226 #define S_CPL_ROCE_CQE_CQE_TYPE 4 6227 #define M_CPL_ROCE_CQE_CQE_TYPE 0x1 6228 #define V_CPL_ROCE_CQE_CQE_TYPE(x) ((x) << S_CPL_ROCE_CQE_CQE_TYPE) 6229 #define G_CPL_ROCE_CQE_CQE_TYPE(x) \ 6230 (((x) >> S_CPL_ROCE_CQE_CQE_TYPE) & M_CPL_ROCE_CQE_CQE_TYPE) 6231 #define F_CPL_ROCE_CQE_CQE_TYPE V_CPL_ROCE_CQE_CQE_TYPE(1U) 6232 6233 #define S_CPL_ROCE_CQE_WR_TYPE 0 6234 #define M_CPL_ROCE_CQE_WR_TYPE 0xf 6235 #define V_CPL_ROCE_CQE_WR_TYPE(x) ((x) << S_CPL_ROCE_CQE_WR_TYPE) 6236 #define G_CPL_ROCE_CQE_WR_TYPE(x) \ 6237 (((x) >> S_CPL_ROCE_CQE_WR_TYPE) & M_CPL_ROCE_CQE_WR_TYPE) 6238 6239 #define S_CPL_ROCE_CQE_SE 31 6240 #define M_CPL_ROCE_CQE_SE 0x1 6241 #define V_CPL_ROCE_CQE_SE(x) ((x) << S_CPL_ROCE_CQE_SE) 6242 #define G_CPL_ROCE_CQE_SE(x) \ 6243 (((x) >> S_CPL_ROCE_CQE_SE) & M_CPL_ROCE_CQE_SE) 6244 #define F_CPL_ROCE_CQE_SE V_CPL_ROCE_CQE_SE(1U) 6245 6246 #define S_CPL_ROCE_CQE_WR_TYPE_EXT 24 6247 #define M_CPL_ROCE_CQE_WR_TYPE_EXT 0x7f 6248 #define V_CPL_ROCE_CQE_WR_TYPE_EXT(x) ((x) << S_CPL_ROCE_CQE_WR_TYPE_EXT) 6249 #define G_CPL_ROCE_CQE_WR_TYPE_EXT(x) \ 6250 (((x) >> S_CPL_ROCE_CQE_WR_TYPE_EXT) & M_CPL_ROCE_CQE_WR_TYPE_EXT) 6251 6252 #define S_CPL_ROCE_CQE_SRQ 0 6253 #define M_CPL_ROCE_CQE_SRQ 0xfff 6254 #define V_CPL_ROCE_CQE_SRQ(x) ((x) << S_CPL_ROCE_CQE_SRQ) 6255 #define G_CPL_ROCE_CQE_SRQ(x) \ 6256 (((x) >> S_CPL_ROCE_CQE_SRQ) & M_CPL_ROCE_CQE_SRQ) 6257 6258 struct cpl_roce_cqe_fw { 6259 __be32 op_to_cqid; 6260 __be32 tid_flitcnt; 6261 __be32 qpid_to_wr_type; 6262 __be32 length; 6263 __be32 tag; 6264 __be32 msn; 6265 __be32 se_to_srq; 6266 __be32 rqe; 6267 __be32 extinfoms[2]; 6268 __be32 extinfols[2]; 6269 }; 6270 6271 #define S_CPL_ROCE_CQE_FW_OPCODE 24 6272 #define M_CPL_ROCE_CQE_FW_OPCODE 0xff 6273 #define V_CPL_ROCE_CQE_FW_OPCODE(x) ((x) << S_CPL_ROCE_CQE_FW_OPCODE) 6274 #define G_CPL_ROCE_CQE_FW_OPCODE(x) \ 6275 (((x) >> S_CPL_ROCE_CQE_FW_OPCODE) & M_CPL_ROCE_CQE_FW_OPCODE) 6276 6277 #define S_CPL_ROCE_CQE_FW_RSSCTRL 16 6278 #define M_CPL_ROCE_CQE_FW_RSSCTRL 0xff 6279 #define V_CPL_ROCE_CQE_FW_RSSCTRL(x) ((x) << S_CPL_ROCE_CQE_FW_RSSCTRL) 6280 #define G_CPL_ROCE_CQE_FW_RSSCTRL(x) \ 6281 (((x) >> S_CPL_ROCE_CQE_FW_RSSCTRL) & M_CPL_ROCE_CQE_FW_RSSCTRL) 6282 6283 #define S_CPL_ROCE_CQE_FW_CQID 0 6284 #define M_CPL_ROCE_CQE_FW_CQID 0xffff 6285 #define V_CPL_ROCE_CQE_FW_CQID(x) ((x) << S_CPL_ROCE_CQE_FW_CQID) 6286 #define G_CPL_ROCE_CQE_FW_CQID(x) \ 6287 (((x) >> S_CPL_ROCE_CQE_FW_CQID) & M_CPL_ROCE_CQE_FW_CQID) 6288 6289 #define S_CPL_ROCE_CQE_FW_TID 8 6290 #define M_CPL_ROCE_CQE_FW_TID 0xfffff 6291 #define V_CPL_ROCE_CQE_FW_TID(x) ((x) << S_CPL_ROCE_CQE_FW_TID) 6292 #define G_CPL_ROCE_CQE_FW_TID(x) \ 6293 (((x) >> S_CPL_ROCE_CQE_FW_TID) & M_CPL_ROCE_CQE_FW_TID) 6294 6295 #define S_CPL_ROCE_CQE_FW_FLITCNT 0 6296 #define M_CPL_ROCE_CQE_FW_FLITCNT 0xff 6297 #define V_CPL_ROCE_CQE_FW_FLITCNT(x) ((x) << S_CPL_ROCE_CQE_FW_FLITCNT) 6298 #define G_CPL_ROCE_CQE_FW_FLITCNT(x) \ 6299 (((x) >> S_CPL_ROCE_CQE_FW_FLITCNT) & M_CPL_ROCE_CQE_FW_FLITCNT) 6300 6301 #define S_CPL_ROCE_CQE_FW_QPID 12 6302 #define M_CPL_ROCE_CQE_FW_QPID 0xfffff 6303 #define V_CPL_ROCE_CQE_FW_QPID(x) ((x) << S_CPL_ROCE_CQE_FW_QPID) 6304 #define G_CPL_ROCE_CQE_FW_QPID(x) \ 6305 (((x) >> S_CPL_ROCE_CQE_FW_QPID) & M_CPL_ROCE_CQE_FW_QPID) 6306 6307 #define S_CPL_ROCE_CQE_FW_EXTMODE 11 6308 #define M_CPL_ROCE_CQE_FW_EXTMODE 0x1 6309 #define V_CPL_ROCE_CQE_FW_EXTMODE(x) ((x) << S_CPL_ROCE_CQE_FW_EXTMODE) 6310 #define G_CPL_ROCE_CQE_FW_EXTMODE(x) \ 6311 (((x) >> S_CPL_ROCE_CQE_FW_EXTMODE) & M_CPL_ROCE_CQE_FW_EXTMODE) 6312 #define F_CPL_ROCE_CQE_FW_EXTMODE V_CPL_ROCE_CQE_FW_EXTMODE(1U) 6313 6314 #define S_CPL_ROCE_CQE_FW_GENERATION_BIT 10 6315 #define M_CPL_ROCE_CQE_FW_GENERATION_BIT 0x1 6316 #define V_CPL_ROCE_CQE_FW_GENERATION_BIT(x) \ 6317 ((x) << S_CPL_ROCE_CQE_FW_GENERATION_BIT) 6318 #define G_CPL_ROCE_CQE_FW_GENERATION_BIT(x) \ 6319 (((x) >> S_CPL_ROCE_CQE_FW_GENERATION_BIT) & \ 6320 M_CPL_ROCE_CQE_FW_GENERATION_BIT) 6321 #define F_CPL_ROCE_CQE_FW_GENERATION_BIT V_CPL_ROCE_CQE_FW_GENERATION_BIT(1U) 6322 6323 #define S_CPL_ROCE_CQE_FW_STATUS 5 6324 #define M_CPL_ROCE_CQE_FW_STATUS 0x1f 6325 #define V_CPL_ROCE_CQE_FW_STATUS(x) ((x) << S_CPL_ROCE_CQE_FW_STATUS) 6326 #define G_CPL_ROCE_CQE_FW_STATUS(x) \ 6327 (((x) >> S_CPL_ROCE_CQE_FW_STATUS) & M_CPL_ROCE_CQE_FW_STATUS) 6328 6329 #define S_CPL_ROCE_CQE_FW_CQE_TYPE 4 6330 #define M_CPL_ROCE_CQE_FW_CQE_TYPE 0x1 6331 #define V_CPL_ROCE_CQE_FW_CQE_TYPE(x) ((x) << S_CPL_ROCE_CQE_FW_CQE_TYPE) 6332 #define G_CPL_ROCE_CQE_FW_CQE_TYPE(x) \ 6333 (((x) >> S_CPL_ROCE_CQE_FW_CQE_TYPE) & M_CPL_ROCE_CQE_FW_CQE_TYPE) 6334 #define F_CPL_ROCE_CQE_FW_CQE_TYPE V_CPL_ROCE_CQE_FW_CQE_TYPE(1U) 6335 6336 #define S_CPL_ROCE_CQE_FW_WR_TYPE 0 6337 #define M_CPL_ROCE_CQE_FW_WR_TYPE 0xf 6338 #define V_CPL_ROCE_CQE_FW_WR_TYPE(x) ((x) << S_CPL_ROCE_CQE_FW_WR_TYPE) 6339 #define G_CPL_ROCE_CQE_FW_WR_TYPE(x) \ 6340 (((x) >> S_CPL_ROCE_CQE_FW_WR_TYPE) & M_CPL_ROCE_CQE_FW_WR_TYPE) 6341 6342 #define S_CPL_ROCE_CQE_FW_SE 31 6343 #define M_CPL_ROCE_CQE_FW_SE 0x1 6344 #define V_CPL_ROCE_CQE_FW_SE(x) ((x) << S_CPL_ROCE_CQE_FW_SE) 6345 #define G_CPL_ROCE_CQE_FW_SE(x) \ 6346 (((x) >> S_CPL_ROCE_CQE_FW_SE) & M_CPL_ROCE_CQE_FW_SE) 6347 #define F_CPL_ROCE_CQE_FW_SE V_CPL_ROCE_CQE_FW_SE(1U) 6348 6349 #define S_CPL_ROCE_CQE_FW_WR_TYPE_EXT 24 6350 #define M_CPL_ROCE_CQE_FW_WR_TYPE_EXT 0x7f 6351 #define V_CPL_ROCE_CQE_FW_WR_TYPE_EXT(x) \ 6352 ((x) << S_CPL_ROCE_CQE_FW_WR_TYPE_EXT) 6353 #define G_CPL_ROCE_CQE_FW_WR_TYPE_EXT(x) \ 6354 (((x) >> S_CPL_ROCE_CQE_FW_WR_TYPE_EXT) & M_CPL_ROCE_CQE_FW_WR_TYPE_EXT) 6355 6356 #define S_CPL_ROCE_CQE_FW_SRQ 0 6357 #define M_CPL_ROCE_CQE_FW_SRQ 0xfff 6358 #define V_CPL_ROCE_CQE_FW_SRQ(x) ((x) << S_CPL_ROCE_CQE_FW_SRQ) 6359 #define G_CPL_ROCE_CQE_FW_SRQ(x) \ 6360 (((x) >> S_CPL_ROCE_CQE_FW_SRQ) & M_CPL_ROCE_CQE_FW_SRQ) 6361 6362 struct cpl_roce_cqe_err { 6363 __be32 op_to_CQID; 6364 __be32 Tid_FlitCnt; 6365 __be32 QPID_to_WR_type; 6366 __be32 Length; 6367 __be32 TAG; 6368 __be32 MSN; 6369 __be32 SE_to_SRQ; 6370 __be32 RQE; 6371 __be32 ExtInfoMS[2]; 6372 __be32 ExtInfoLS[2]; 6373 }; 6374 6375 #define S_CPL_ROCE_CQE_ERR_OPCODE 24 6376 #define M_CPL_ROCE_CQE_ERR_OPCODE 0xff 6377 #define V_CPL_ROCE_CQE_ERR_OPCODE(x) ((x) << S_CPL_ROCE_CQE_ERR_OPCODE) 6378 #define G_CPL_ROCE_CQE_ERR_OPCODE(x) \ 6379 (((x) >> S_CPL_ROCE_CQE_ERR_OPCODE) & M_CPL_ROCE_CQE_ERR_OPCODE) 6380 6381 #define S_CPL_ROCE_CQE_ERR_RSSCTRL 16 6382 #define M_CPL_ROCE_CQE_ERR_RSSCTRL 0xff 6383 #define V_CPL_ROCE_CQE_ERR_RSSCTRL(x) ((x) << S_CPL_ROCE_CQE_ERR_RSSCTRL) 6384 #define G_CPL_ROCE_CQE_ERR_RSSCTRL(x) \ 6385 (((x) >> S_CPL_ROCE_CQE_ERR_RSSCTRL) & M_CPL_ROCE_CQE_ERR_RSSCTRL) 6386 6387 #define S_CPL_ROCE_CQE_ERR_CQID 0 6388 #define M_CPL_ROCE_CQE_ERR_CQID 0xffff 6389 #define V_CPL_ROCE_CQE_ERR_CQID(x) ((x) << S_CPL_ROCE_CQE_ERR_CQID) 6390 #define G_CPL_ROCE_CQE_ERR_CQID(x) \ 6391 (((x) >> S_CPL_ROCE_CQE_ERR_CQID) & M_CPL_ROCE_CQE_ERR_CQID) 6392 6393 #define S_CPL_ROCE_CQE_ERR_TID 8 6394 #define M_CPL_ROCE_CQE_ERR_TID 0xfffff 6395 #define V_CPL_ROCE_CQE_ERR_TID(x) ((x) << S_CPL_ROCE_CQE_ERR_TID) 6396 #define G_CPL_ROCE_CQE_ERR_TID(x) \ 6397 (((x) >> S_CPL_ROCE_CQE_ERR_TID) & M_CPL_ROCE_CQE_ERR_TID) 6398 6399 #define S_CPL_ROCE_CQE_ERR_FLITCNT 0 6400 #define M_CPL_ROCE_CQE_ERR_FLITCNT 0xff 6401 #define V_CPL_ROCE_CQE_ERR_FLITCNT(x) ((x) << S_CPL_ROCE_CQE_ERR_FLITCNT) 6402 #define G_CPL_ROCE_CQE_ERR_FLITCNT(x) \ 6403 (((x) >> S_CPL_ROCE_CQE_ERR_FLITCNT) & M_CPL_ROCE_CQE_ERR_FLITCNT) 6404 6405 #define S_CPL_ROCE_CQE_ERR_QPID 12 6406 #define M_CPL_ROCE_CQE_ERR_QPID 0xfffff 6407 #define V_CPL_ROCE_CQE_ERR_QPID(x) ((x) << S_CPL_ROCE_CQE_ERR_QPID) 6408 #define G_CPL_ROCE_CQE_ERR_QPID(x) \ 6409 (((x) >> S_CPL_ROCE_CQE_ERR_QPID) & M_CPL_ROCE_CQE_ERR_QPID) 6410 6411 #define S_CPL_ROCE_CQE_ERR_EXTMODE 11 6412 #define M_CPL_ROCE_CQE_ERR_EXTMODE 0x1 6413 #define V_CPL_ROCE_CQE_ERR_EXTMODE(x) ((x) << S_CPL_ROCE_CQE_ERR_EXTMODE) 6414 #define G_CPL_ROCE_CQE_ERR_EXTMODE(x) \ 6415 (((x) >> S_CPL_ROCE_CQE_ERR_EXTMODE) & M_CPL_ROCE_CQE_ERR_EXTMODE) 6416 #define F_CPL_ROCE_CQE_ERR_EXTMODE V_CPL_ROCE_CQE_ERR_EXTMODE(1U) 6417 6418 #define S_CPL_ROCE_CQE_ERR_GENERATION_BIT 10 6419 #define M_CPL_ROCE_CQE_ERR_GENERATION_BIT 0x1 6420 #define V_CPL_ROCE_CQE_ERR_GENERATION_BIT(x) \ 6421 ((x) << S_CPL_ROCE_CQE_ERR_GENERATION_BIT) 6422 #define G_CPL_ROCE_CQE_ERR_GENERATION_BIT(x) \ 6423 (((x) >> S_CPL_ROCE_CQE_ERR_GENERATION_BIT) & \ 6424 M_CPL_ROCE_CQE_ERR_GENERATION_BIT) 6425 #define F_CPL_ROCE_CQE_ERR_GENERATION_BIT \ 6426 V_CPL_ROCE_CQE_ERR_GENERATION_BIT(1U) 6427 6428 #define S_CPL_ROCE_CQE_ERR_STATUS 5 6429 #define M_CPL_ROCE_CQE_ERR_STATUS 0x1f 6430 #define V_CPL_ROCE_CQE_ERR_STATUS(x) ((x) << S_CPL_ROCE_CQE_ERR_STATUS) 6431 #define G_CPL_ROCE_CQE_ERR_STATUS(x) \ 6432 (((x) >> S_CPL_ROCE_CQE_ERR_STATUS) & M_CPL_ROCE_CQE_ERR_STATUS) 6433 6434 #define S_CPL_ROCE_CQE_ERR_CQE_TYPE 4 6435 #define M_CPL_ROCE_CQE_ERR_CQE_TYPE 0x1 6436 #define V_CPL_ROCE_CQE_ERR_CQE_TYPE(x) ((x) << S_CPL_ROCE_CQE_ERR_CQE_TYPE) 6437 #define G_CPL_ROCE_CQE_ERR_CQE_TYPE(x) \ 6438 (((x) >> S_CPL_ROCE_CQE_ERR_CQE_TYPE) & M_CPL_ROCE_CQE_ERR_CQE_TYPE) 6439 #define F_CPL_ROCE_CQE_ERR_CQE_TYPE V_CPL_ROCE_CQE_ERR_CQE_TYPE(1U) 6440 6441 #define S_CPL_ROCE_CQE_ERR_WR_TYPE 0 6442 #define M_CPL_ROCE_CQE_ERR_WR_TYPE 0xf 6443 #define V_CPL_ROCE_CQE_ERR_WR_TYPE(x) ((x) << S_CPL_ROCE_CQE_ERR_WR_TYPE) 6444 #define G_CPL_ROCE_CQE_ERR_WR_TYPE(x) \ 6445 (((x) >> S_CPL_ROCE_CQE_ERR_WR_TYPE) & M_CPL_ROCE_CQE_ERR_WR_TYPE) 6446 6447 #define S_CPL_ROCE_CQE_ERR_SE 31 6448 #define M_CPL_ROCE_CQE_ERR_SE 0x1 6449 #define V_CPL_ROCE_CQE_ERR_SE(x) ((x) << S_CPL_ROCE_CQE_ERR_SE) 6450 #define G_CPL_ROCE_CQE_ERR_SE(x) \ 6451 (((x) >> S_CPL_ROCE_CQE_ERR_SE) & M_CPL_ROCE_CQE_ERR_SE) 6452 #define F_CPL_ROCE_CQE_ERR_SE V_CPL_ROCE_CQE_ERR_SE(1U) 6453 6454 #define S_CPL_ROCE_CQE_ERR_WR_TYPE_EXT 24 6455 #define M_CPL_ROCE_CQE_ERR_WR_TYPE_EXT 0x7f 6456 #define V_CPL_ROCE_CQE_ERR_WR_TYPE_EXT(x) \ 6457 ((x) << S_CPL_ROCE_CQE_ERR_WR_TYPE_EXT) 6458 #define G_CPL_ROCE_CQE_ERR_WR_TYPE_EXT(x) \ 6459 (((x) >> S_CPL_ROCE_CQE_ERR_WR_TYPE_EXT) & M_CPL_ROCE_CQE_ERR_WR_TYPE_EXT) 6460 6461 #define S_CPL_ROCE_CQE_ERR_SRQ 0 6462 #define M_CPL_ROCE_CQE_ERR_SRQ 0xfff 6463 #define V_CPL_ROCE_CQE_ERR_SRQ(x) ((x) << S_CPL_ROCE_CQE_ERR_SRQ) 6464 #define G_CPL_ROCE_CQE_ERR_SRQ(x) \ 6465 (((x) >> S_CPL_ROCE_CQE_ERR_SRQ) & M_CPL_ROCE_CQE_ERR_SRQ) 6466 6467 struct cpl_accelerator_hdr { 6468 __be16 op_accelerator_id; 6469 __be16 rxchid_payload_to_inner_cpl_length_ack; 6470 __be32 inner_cpl_length_payload_status_loc; 6471 }; 6472 6473 #define S_CPL_ACCELERATOR_HDR_OPCODE 8 6474 #define M_CPL_ACCELERATOR_HDR_OPCODE 0xff 6475 #define V_CPL_ACCELERATOR_HDR_OPCODE(x) ((x) << S_CPL_ACCELERATOR_HDR_OPCODE) 6476 #define G_CPL_ACCELERATOR_HDR_OPCODE(x) \ 6477 (((x) >> S_CPL_ACCELERATOR_HDR_OPCODE) & M_CPL_ACCELERATOR_HDR_OPCODE) 6478 6479 #define S_CPL_ACCELERATOR_HDR_ACCELERATOR_ID 0 6480 #define M_CPL_ACCELERATOR_HDR_ACCELERATOR_ID 0xff 6481 #define V_CPL_ACCELERATOR_HDR_ACCELERATOR_ID(x) \ 6482 ((x) << S_CPL_ACCELERATOR_HDR_ACCELERATOR_ID) 6483 #define G_CPL_ACCELERATOR_HDR_ACCELERATOR_ID(x) \ 6484 (((x) >> S_CPL_ACCELERATOR_HDR_ACCELERATOR_ID) & \ 6485 M_CPL_ACCELERATOR_HDR_ACCELERATOR_ID) 6486 6487 #define S_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD 14 6488 #define M_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD 0x3 6489 #define V_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD(x) \ 6490 ((x) << S_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD) 6491 #define G_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD(x) \ 6492 (((x) >> S_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD) & \ 6493 M_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD) 6494 6495 #define S_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD 12 6496 #define M_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD 0x3 6497 #define V_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD(x) \ 6498 ((x) << S_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD) 6499 #define G_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD(x) \ 6500 (((x) >> S_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD) & \ 6501 M_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD) 6502 6503 #define S_CPL_ACCELERATOR_HDR_RXCHID_ACK 10 6504 #define M_CPL_ACCELERATOR_HDR_RXCHID_ACK 0x3 6505 #define V_CPL_ACCELERATOR_HDR_RXCHID_ACK(x) \ 6506 ((x) << S_CPL_ACCELERATOR_HDR_RXCHID_ACK) 6507 #define G_CPL_ACCELERATOR_HDR_RXCHID_ACK(x) \ 6508 (((x) >> S_CPL_ACCELERATOR_HDR_RXCHID_ACK) & \ 6509 M_CPL_ACCELERATOR_HDR_RXCHID_ACK) 6510 6511 #define S_CPL_ACCELERATOR_HDR_DESTID_ACK 8 6512 #define M_CPL_ACCELERATOR_HDR_DESTID_ACK 0x3 6513 #define V_CPL_ACCELERATOR_HDR_DESTID_ACK(x) \ 6514 ((x) << S_CPL_ACCELERATOR_HDR_DESTID_ACK) 6515 #define G_CPL_ACCELERATOR_HDR_DESTID_ACK(x) \ 6516 (((x) >> S_CPL_ACCELERATOR_HDR_DESTID_ACK) & \ 6517 M_CPL_ACCELERATOR_HDR_DESTID_ACK) 6518 6519 #define S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK 0 6520 #define M_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK 0xff 6521 #define V_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK(x) \ 6522 ((x) << S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK) 6523 #define G_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK(x) \ 6524 (((x) >> S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK) & \ 6525 M_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK) 6526 6527 #define S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD 24 6528 #define M_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD 0xff 6529 #define V_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD(x) \ 6530 ((x) << S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD) 6531 #define G_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD(x) \ 6532 (((x) >> S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD) & \ 6533 M_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD) 6534 6535 #define S_CPL_ACCELERATOR_HDR_STATUS_LOC 22 6536 #define M_CPL_ACCELERATOR_HDR_STATUS_LOC 0x3 6537 #define V_CPL_ACCELERATOR_HDR_STATUS_LOC(x) \ 6538 ((x) << S_CPL_ACCELERATOR_HDR_STATUS_LOC) 6539 #define G_CPL_ACCELERATOR_HDR_STATUS_LOC(x) \ 6540 (((x) >> S_CPL_ACCELERATOR_HDR_STATUS_LOC) & \ 6541 M_CPL_ACCELERATOR_HDR_STATUS_LOC) 6542 6543 struct cpl_accelerator_ack { 6544 RSS_HDR 6545 __be16 op_accelerator_id; 6546 __be16 r0; 6547 __be32 status; 6548 __be64 r1; 6549 __be64 r2; 6550 }; 6551 6552 #define S_CPL_ACCELERATOR_ACK_OPCODE 8 6553 #define M_CPL_ACCELERATOR_ACK_OPCODE 0xff 6554 #define V_CPL_ACCELERATOR_ACK_OPCODE(x) ((x) << S_CPL_ACCELERATOR_ACK_OPCODE) 6555 #define G_CPL_ACCELERATOR_ACK_OPCODE(x) \ 6556 (((x) >> S_CPL_ACCELERATOR_ACK_OPCODE) & M_CPL_ACCELERATOR_ACK_OPCODE) 6557 6558 #define S_CPL_ACCELERATOR_ACK_ACCELERATOR_ID 0 6559 #define M_CPL_ACCELERATOR_ACK_ACCELERATOR_ID 0xff 6560 #define V_CPL_ACCELERATOR_ACK_ACCELERATOR_ID(x) \ 6561 ((x) << S_CPL_ACCELERATOR_ACK_ACCELERATOR_ID) 6562 #define G_CPL_ACCELERATOR_ACK_ACCELERATOR_ID(x) \ 6563 (((x) >> S_CPL_ACCELERATOR_ACK_ACCELERATOR_ID) & \ 6564 M_CPL_ACCELERATOR_ACK_ACCELERATOR_ID) 6565 6566 struct cpl_nvmt_data { 6567 RSS_HDR 6568 union opcode_tid ot; 6569 __be16 r0; 6570 __be16 length; 6571 __be32 seq; 6572 __be32 status_pkd; 6573 }; 6574 6575 #define S_CPL_NVMT_DATA_OPCODE 24 6576 #define M_CPL_NVMT_DATA_OPCODE 0xff 6577 #define V_CPL_NVMT_DATA_OPCODE(x) ((x) << S_CPL_NVMT_DATA_OPCODE) 6578 #define G_CPL_NVMT_DATA_OPCODE(x) \ 6579 (((x) >> S_CPL_NVMT_DATA_OPCODE) & M_CPL_NVMT_DATA_OPCODE) 6580 6581 #define S_CPL_NVMT_DATA_TID 0 6582 #define M_CPL_NVMT_DATA_TID 0xffffff 6583 #define V_CPL_NVMT_DATA_TID(x) ((x) << S_CPL_NVMT_DATA_TID) 6584 #define G_CPL_NVMT_DATA_TID(x) \ 6585 (((x) >> S_CPL_NVMT_DATA_TID) & M_CPL_NVMT_DATA_TID) 6586 6587 #define S_CPL_NVMT_DATA_STATUS 0 6588 #define M_CPL_NVMT_DATA_STATUS 0xff 6589 #define V_CPL_NVMT_DATA_STATUS(x) ((x) << S_CPL_NVMT_DATA_STATUS) 6590 #define G_CPL_NVMT_DATA_STATUS(x) \ 6591 (((x) >> S_CPL_NVMT_DATA_STATUS) & M_CPL_NVMT_DATA_STATUS) 6592 6593 struct cpl_nvmt_cmp { 6594 RSS_HDR 6595 union opcode_tid ot; 6596 __be16 crch; 6597 __be16 length; 6598 __be32 seq; 6599 __u8 t10status; 6600 __u8 status; 6601 __be16 crcl; 6602 }; 6603 6604 #define S_CPL_NVMT_CMP_OPCODE 24 6605 #define M_CPL_NVMT_CMP_OPCODE 0xff 6606 #define V_CPL_NVMT_CMP_OPCODE(x) ((x) << S_CPL_NVMT_CMP_OPCODE) 6607 #define G_CPL_NVMT_CMP_OPCODE(x) \ 6608 (((x) >> S_CPL_NVMT_CMP_OPCODE) & M_CPL_NVMT_CMP_OPCODE) 6609 6610 #define S_CPL_NVMT_CMP_TID 0 6611 #define M_CPL_NVMT_CMP_TID 0xffffff 6612 #define V_CPL_NVMT_CMP_TID(x) ((x) << S_CPL_NVMT_CMP_TID) 6613 #define G_CPL_NVMT_CMP_TID(x) \ 6614 (((x) >> S_CPL_NVMT_CMP_TID) & M_CPL_NVMT_CMP_TID) 6615 6616 struct cpl_nvmt_cmp_imm { 6617 __be32 op_to_cqid; 6618 __be32 generation_bit_to_oprqinc; 6619 __be32 seq; 6620 __be16 crch; 6621 __be16 length; 6622 __be16 crcl; 6623 __u8 t10status; 6624 __u8 status; 6625 __be32 r1; 6626 }; 6627 6628 #define S_CPL_NVMT_CMP_IMM_OPCODE 24 6629 #define M_CPL_NVMT_CMP_IMM_OPCODE 0xff 6630 #define V_CPL_NVMT_CMP_IMM_OPCODE(x) ((x) << S_CPL_NVMT_CMP_IMM_OPCODE) 6631 #define G_CPL_NVMT_CMP_IMM_OPCODE(x) \ 6632 (((x) >> S_CPL_NVMT_CMP_IMM_OPCODE) & M_CPL_NVMT_CMP_IMM_OPCODE) 6633 6634 #define S_CPL_NVMT_CMP_IMM_RSSCTRL 16 6635 #define M_CPL_NVMT_CMP_IMM_RSSCTRL 0xff 6636 #define V_CPL_NVMT_CMP_IMM_RSSCTRL(x) ((x) << S_CPL_NVMT_CMP_IMM_RSSCTRL) 6637 #define G_CPL_NVMT_CMP_IMM_RSSCTRL(x) \ 6638 (((x) >> S_CPL_NVMT_CMP_IMM_RSSCTRL) & M_CPL_NVMT_CMP_IMM_RSSCTRL) 6639 6640 #define S_CPL_NVMT_CMP_IMM_CQID 0 6641 #define M_CPL_NVMT_CMP_IMM_CQID 0xffff 6642 #define V_CPL_NVMT_CMP_IMM_CQID(x) ((x) << S_CPL_NVMT_CMP_IMM_CQID) 6643 #define G_CPL_NVMT_CMP_IMM_CQID(x) \ 6644 (((x) >> S_CPL_NVMT_CMP_IMM_CQID) & M_CPL_NVMT_CMP_IMM_CQID) 6645 6646 #define S_CPL_NVMT_CMP_IMM_GENERATION_BIT 31 6647 #define M_CPL_NVMT_CMP_IMM_GENERATION_BIT 0x1 6648 #define V_CPL_NVMT_CMP_IMM_GENERATION_BIT(x) \ 6649 ((x) << S_CPL_NVMT_CMP_IMM_GENERATION_BIT) 6650 #define G_CPL_NVMT_CMP_IMM_GENERATION_BIT(x) \ 6651 (((x) >> S_CPL_NVMT_CMP_IMM_GENERATION_BIT) & \ 6652 M_CPL_NVMT_CMP_IMM_GENERATION_BIT) 6653 #define F_CPL_NVMT_CMP_IMM_GENERATION_BIT \ 6654 V_CPL_NVMT_CMP_IMM_GENERATION_BIT(1U) 6655 6656 #define S_CPL_NVMT_CMP_IMM_TID 8 6657 #define M_CPL_NVMT_CMP_IMM_TID 0xfffff 6658 #define V_CPL_NVMT_CMP_IMM_TID(x) ((x) << S_CPL_NVMT_CMP_IMM_TID) 6659 #define G_CPL_NVMT_CMP_IMM_TID(x) \ 6660 (((x) >> S_CPL_NVMT_CMP_IMM_TID) & M_CPL_NVMT_CMP_IMM_TID) 6661 6662 #define S_CPL_NVMT_CMP_IMM_OPRQINC 0 6663 #define M_CPL_NVMT_CMP_IMM_OPRQINC 0xff 6664 #define V_CPL_NVMT_CMP_IMM_OPRQINC(x) ((x) << S_CPL_NVMT_CMP_IMM_OPRQINC) 6665 #define G_CPL_NVMT_CMP_IMM_OPRQINC(x) \ 6666 (((x) >> S_CPL_NVMT_CMP_IMM_OPRQINC) & M_CPL_NVMT_CMP_IMM_OPRQINC) 6667 6668 struct cpl_nvmt_cmp_srq { 6669 __be32 op_to_cqid; 6670 __be32 generation_bit_to_oprqinc; 6671 __be32 seq; 6672 __be16 crch; 6673 __be16 length; 6674 __be16 crcl; 6675 __u8 t10status; 6676 __u8 status; 6677 __be32 rqe; 6678 }; 6679 6680 #define S_CPL_NVMT_CMP_SRQ_OPCODE 24 6681 #define M_CPL_NVMT_CMP_SRQ_OPCODE 0xff 6682 #define V_CPL_NVMT_CMP_SRQ_OPCODE(x) ((x) << S_CPL_NVMT_CMP_SRQ_OPCODE) 6683 #define G_CPL_NVMT_CMP_SRQ_OPCODE(x) \ 6684 (((x) >> S_CPL_NVMT_CMP_SRQ_OPCODE) & M_CPL_NVMT_CMP_SRQ_OPCODE) 6685 6686 #define S_CPL_NVMT_CMP_SRQ_RSSCTRL 16 6687 #define M_CPL_NVMT_CMP_SRQ_RSSCTRL 0xff 6688 #define V_CPL_NVMT_CMP_SRQ_RSSCTRL(x) ((x) << S_CPL_NVMT_CMP_SRQ_RSSCTRL) 6689 #define G_CPL_NVMT_CMP_SRQ_RSSCTRL(x) \ 6690 (((x) >> S_CPL_NVMT_CMP_SRQ_RSSCTRL) & M_CPL_NVMT_CMP_SRQ_RSSCTRL) 6691 6692 #define S_CPL_NVMT_CMP_SRQ_CQID 0 6693 #define M_CPL_NVMT_CMP_SRQ_CQID 0xffff 6694 #define V_CPL_NVMT_CMP_SRQ_CQID(x) ((x) << S_CPL_NVMT_CMP_SRQ_CQID) 6695 #define G_CPL_NVMT_CMP_SRQ_CQID(x) \ 6696 (((x) >> S_CPL_NVMT_CMP_SRQ_CQID) & M_CPL_NVMT_CMP_SRQ_CQID) 6697 6698 #define S_CPL_NVMT_CMP_SRQ_GENERATION_BIT 31 6699 #define M_CPL_NVMT_CMP_SRQ_GENERATION_BIT 0x1 6700 #define V_CPL_NVMT_CMP_SRQ_GENERATION_BIT(x) \ 6701 ((x) << S_CPL_NVMT_CMP_SRQ_GENERATION_BIT) 6702 #define G_CPL_NVMT_CMP_SRQ_GENERATION_BIT(x) \ 6703 (((x) >> S_CPL_NVMT_CMP_SRQ_GENERATION_BIT) & \ 6704 M_CPL_NVMT_CMP_SRQ_GENERATION_BIT) 6705 #define F_CPL_NVMT_CMP_SRQ_GENERATION_BIT \ 6706 V_CPL_NVMT_CMP_SRQ_GENERATION_BIT(1U) 6707 6708 #define S_CPL_NVMT_CMP_SRQ_TID 8 6709 #define M_CPL_NVMT_CMP_SRQ_TID 0xfffff 6710 #define V_CPL_NVMT_CMP_SRQ_TID(x) ((x) << S_CPL_NVMT_CMP_SRQ_TID) 6711 #define G_CPL_NVMT_CMP_SRQ_TID(x) \ 6712 (((x) >> S_CPL_NVMT_CMP_SRQ_TID) & M_CPL_NVMT_CMP_SRQ_TID) 6713 6714 #define S_CPL_NVMT_CMP_SRQ_OPRQINC 0 6715 #define M_CPL_NVMT_CMP_SRQ_OPRQINC 0xff 6716 #define V_CPL_NVMT_CMP_SRQ_OPRQINC(x) ((x) << S_CPL_NVMT_CMP_SRQ_OPRQINC) 6717 #define G_CPL_NVMT_CMP_SRQ_OPRQINC(x) \ 6718 (((x) >> S_CPL_NVMT_CMP_SRQ_OPRQINC) & M_CPL_NVMT_CMP_SRQ_OPRQINC) 6719 6720 #endif /* T4_MSG_H */ 6721