xref: /freebsd/sys/dev/cxgbe/common/t4_regs.h (revision c7b2e390de43bb2b1a5918a23310ec5464ee3787)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2013, 2016, 2025 Chelsio Communications.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  */
28 
29 /* This file is automatically generated --- changes will be lost */
30 /* Generation Date : Thu Sep 11 05:25:56 PM IST 2025 */
31 /* Directory name: t4_reg.txt, Date: Not specified */
32 /* Directory name: t5_reg.txt, Changeset: 6945:54ba4ba7ee8b */
33 /* Directory name: t6_reg.txt, Changeset: 4277:9c165d0f4899 */
34 /* Directory name: t7_reg.txt, Changeset: 5945:1487219ecb20 */
35 
36 #define MYPF_BASE 0x1b000
37 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
38 
39 #define PF0_BASE 0x1e000
40 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
41 
42 #define PF1_BASE 0x1e400
43 #define PF1_REG(reg_addr) (PF1_BASE + (reg_addr))
44 
45 #define PF2_BASE 0x1e800
46 #define PF2_REG(reg_addr) (PF2_BASE + (reg_addr))
47 
48 #define PF3_BASE 0x1ec00
49 #define PF3_REG(reg_addr) (PF3_BASE + (reg_addr))
50 
51 #define PF4_BASE 0x1f000
52 #define PF4_REG(reg_addr) (PF4_BASE + (reg_addr))
53 
54 #define PF5_BASE 0x1f400
55 #define PF5_REG(reg_addr) (PF5_BASE + (reg_addr))
56 
57 #define PF6_BASE 0x1f800
58 #define PF6_REG(reg_addr) (PF6_BASE + (reg_addr))
59 
60 #define PF7_BASE 0x1fc00
61 #define PF7_REG(reg_addr) (PF7_BASE + (reg_addr))
62 
63 #define PF_STRIDE 0x400
64 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
65 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
66 
67 #define VF_SGE_BASE 0x0
68 #define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr))
69 
70 #define VF_MPS_BASE 0x100
71 #define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr))
72 
73 #define VF_PL_BASE 0x200
74 #define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr))
75 
76 #define VF_MBDATA_BASE 0x240
77 #define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr))
78 
79 #define VF_CIM_BASE 0x300
80 #define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr))
81 
82 #define MYPORT_BASE 0x1c000
83 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
84 
85 #define PORT0_BASE 0x20000
86 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
87 
88 #define PORT1_BASE 0x22000
89 #define PORT1_REG(reg_addr) (PORT1_BASE + (reg_addr))
90 
91 #define PORT2_BASE 0x24000
92 #define PORT2_REG(reg_addr) (PORT2_BASE + (reg_addr))
93 
94 #define PORT3_BASE 0x26000
95 #define PORT3_REG(reg_addr) (PORT3_BASE + (reg_addr))
96 
97 #define PORT_STRIDE 0x2000
98 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
99 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
100 
101 #define SGE_QUEUE_BASE_MAP_HIGH(idx) (A_SGE_QUEUE_BASE_MAP_HIGH + (idx) * 8)
102 #define NUM_SGE_QUEUE_BASE_MAP_HIGH_INSTANCES 136
103 
104 #define SGE_QUEUE_BASE_MAP_LOW(idx) (A_SGE_QUEUE_BASE_MAP_LOW + (idx) * 8)
105 #define NUM_SGE_QUEUE_BASE_MAP_LOW_INSTANCES 136
106 
107 #define PCIE_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
108 #define NUM_PCIE_DMA_INSTANCES 4
109 
110 #define PCIE_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
111 #define NUM_PCIE_CMD_INSTANCES 2
112 
113 #define PCIE_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
114 #define NUM_PCIE_HMA_INSTANCES 1
115 
116 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
117 #define NUM_PCIE_MEM_ACCESS_INSTANCES 8
118 
119 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
120 #define NUM_PCIE_MAILBOX_INSTANCES 1
121 
122 #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
123 #define NUM_PCIE_FW_INSTANCES 8
124 
125 #define PCIE_FUNC_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
126 #define NUM_PCIE_FUNC_INSTANCES 256
127 
128 #define PCIE_FID(idx) (A_PCIE_FID + (idx) * 4)
129 #define NUM_PCIE_FID_INSTANCES 2048
130 
131 #define PCIE_DMA_BUF_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
132 #define NUM_PCIE_DMA_BUF_INSTANCES 4
133 
134 #define MC_DDR3PHYDATX8_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)
135 #define NUM_MC_DDR3PHYDATX8_INSTANCES 9
136 
137 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
138 #define NUM_MC_BIST_STATUS_INSTANCES 18
139 
140 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
141 #define NUM_EDC_BIST_STATUS_INSTANCES 18
142 
143 #define CIM_PF_MAILBOX_DATA(idx) (A_CIM_PF_MAILBOX_DATA + (idx) * 4)
144 #define NUM_CIM_PF_MAILBOX_DATA_INSTANCES 16
145 
146 #define MPS_TRC_FILTER_MATCH_CTL_A(idx) (A_MPS_TRC_FILTER_MATCH_CTL_A + (idx) * 4)
147 #define NUM_MPS_TRC_FILTER_MATCH_CTL_A_INSTANCES 4
148 
149 #define MPS_TRC_FILTER_MATCH_CTL_B(idx) (A_MPS_TRC_FILTER_MATCH_CTL_B + (idx) * 4)
150 #define NUM_MPS_TRC_FILTER_MATCH_CTL_B_INSTANCES 4
151 
152 #define MPS_TRC_FILTER_RUNT_CTL(idx) (A_MPS_TRC_FILTER_RUNT_CTL + (idx) * 4)
153 #define NUM_MPS_TRC_FILTER_RUNT_CTL_INSTANCES 4
154 
155 #define MPS_TRC_FILTER_DROP(idx) (A_MPS_TRC_FILTER_DROP + (idx) * 4)
156 #define NUM_MPS_TRC_FILTER_DROP_INSTANCES 4
157 
158 #define MPS_TRC_FILTER0_MATCH(idx) (A_MPS_TRC_FILTER0_MATCH + (idx) * 4)
159 #define NUM_MPS_TRC_FILTER0_MATCH_INSTANCES 28
160 
161 #define MPS_TRC_FILTER0_DONT_CARE(idx) (A_MPS_TRC_FILTER0_DONT_CARE + (idx) * 4)
162 #define NUM_MPS_TRC_FILTER0_DONT_CARE_INSTANCES 28
163 
164 #define MPS_TRC_FILTER1_MATCH(idx) (A_MPS_TRC_FILTER1_MATCH + (idx) * 4)
165 #define NUM_MPS_TRC_FILTER1_MATCH_INSTANCES 28
166 
167 #define MPS_TRC_FILTER1_DONT_CARE(idx) (A_MPS_TRC_FILTER1_DONT_CARE + (idx) * 4)
168 #define NUM_MPS_TRC_FILTER1_DONT_CARE_INSTANCES 28
169 
170 #define MPS_TRC_FILTER2_MATCH(idx) (A_MPS_TRC_FILTER2_MATCH + (idx) * 4)
171 #define NUM_MPS_TRC_FILTER2_MATCH_INSTANCES 28
172 
173 #define MPS_TRC_FILTER2_DONT_CARE(idx) (A_MPS_TRC_FILTER2_DONT_CARE + (idx) * 4)
174 #define NUM_MPS_TRC_FILTER2_DONT_CARE_INSTANCES 28
175 
176 #define MPS_TRC_FILTER3_MATCH(idx) (A_MPS_TRC_FILTER3_MATCH + (idx) * 4)
177 #define NUM_MPS_TRC_FILTER3_MATCH_INSTANCES 28
178 
179 #define MPS_TRC_FILTER3_DONT_CARE(idx) (A_MPS_TRC_FILTER3_DONT_CARE + (idx) * 4)
180 #define NUM_MPS_TRC_FILTER3_DONT_CARE_INSTANCES 28
181 
182 #define MPS_PORT_CLS_HASH_SRAM(idx) (A_MPS_PORT_CLS_HASH_SRAM + (idx) * 4)
183 #define NUM_MPS_PORT_CLS_HASH_SRAM_INSTANCES 65
184 
185 #define MPS_CLS_VLAN_TABLE(idx) (A_MPS_CLS_VLAN_TABLE + (idx) * 4)
186 #define NUM_MPS_CLS_VLAN_TABLE_INSTANCES 9
187 
188 #define MPS_CLS_SRAM_L(idx) (A_MPS_CLS_SRAM_L + (idx) * 8)
189 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
190 
191 #define MPS_CLS_SRAM_H(idx) (A_MPS_CLS_SRAM_H + (idx) * 8)
192 #define NUM_MPS_CLS_SRAM_H_INSTANCES 336
193 
194 #define MPS_CLS_TCAM_Y_L(idx) (A_MPS_CLS_TCAM_Y_L + (idx) * 16)
195 #define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
196 
197 #define MPS_CLS_TCAM_Y_H(idx) (A_MPS_CLS_TCAM_Y_H + (idx) * 16)
198 #define NUM_MPS_CLS_TCAM_Y_H_INSTANCES 512
199 
200 #define MPS_CLS_TCAM_X_L(idx) (A_MPS_CLS_TCAM_X_L + (idx) * 16)
201 #define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
202 
203 #define MPS_CLS_TCAM_X_H(idx) (A_MPS_CLS_TCAM_X_H + (idx) * 16)
204 #define NUM_MPS_CLS_TCAM_X_H_INSTANCES 512
205 
206 #define PL_SEMAPHORE_LOCK(idx) (A_PL_SEMAPHORE_LOCK + (idx) * 4)
207 #define NUM_PL_SEMAPHORE_LOCK_INSTANCES 8
208 
209 #define PL_VF_SLICE_L(idx) (A_PL_VF_SLICE_L + (idx) * 8)
210 #define NUM_PL_VF_SLICE_L_INSTANCES 8
211 
212 #define PL_VF_SLICE_H(idx) (A_PL_VF_SLICE_H + (idx) * 8)
213 #define NUM_PL_VF_SLICE_H_INSTANCES 8
214 
215 #define PL_FLR_VF_STATUS(idx) (A_PL_FLR_VF_STATUS + (idx) * 4)
216 #define NUM_PL_FLR_VF_STATUS_INSTANCES 4
217 
218 #define PL_VFID_MAP(idx) (A_PL_VFID_MAP + (idx) * 4)
219 #define NUM_PL_VFID_MAP_INSTANCES 256
220 
221 #define LE_DB_MASK_IPV4(idx) (A_LE_DB_MASK_IPV4 + (idx) * 4)
222 #define NUM_LE_DB_MASK_IPV4_INSTANCES 17
223 
224 #define LE_DB_MASK_IPV6(idx) (A_LE_DB_MASK_IPV6 + (idx) * 4)
225 #define NUM_LE_DB_MASK_IPV6_INSTANCES 17
226 
227 #define LE_DB_DBGI_REQ_DATA(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
228 #define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17
229 
230 #define LE_DB_DBGI_REQ_MASK(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
231 #define NUM_LE_DB_DBGI_REQ_MASK_INSTANCES 17
232 
233 #define LE_DB_DBGI_RSP_DATA(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4)
234 #define NUM_LE_DB_DBGI_RSP_DATA_INSTANCES 17
235 
236 #define LE_DB_ACTIVE_MASK_IPV4(idx) (A_LE_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
237 #define NUM_LE_DB_ACTIVE_MASK_IPV4_INSTANCES 17
238 
239 #define LE_DB_ACTIVE_MASK_IPV6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
240 #define NUM_LE_DB_ACTIVE_MASK_IPV6_INSTANCES 17
241 
242 #define LE_HASH_MASK_GEN_IPV4(idx) (A_LE_HASH_MASK_GEN_IPV4 + (idx) * 4)
243 #define NUM_LE_HASH_MASK_GEN_IPV4_INSTANCES 4
244 
245 #define LE_HASH_MASK_GEN_IPV6(idx) (A_LE_HASH_MASK_GEN_IPV6 + (idx) * 4)
246 #define NUM_LE_HASH_MASK_GEN_IPV6_INSTANCES 12
247 
248 #define LE_HASH_MASK_CMP_IPV4(idx) (A_LE_HASH_MASK_CMP_IPV4 + (idx) * 4)
249 #define NUM_LE_HASH_MASK_CMP_IPV4_INSTANCES 4
250 
251 #define LE_HASH_MASK_CMP_IPV6(idx) (A_LE_HASH_MASK_CMP_IPV6 + (idx) * 4)
252 #define NUM_LE_HASH_MASK_CMP_IPV6_INSTANCES 12
253 
254 #define UP_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
255 #define NUM_UP_TSCH_CHANNEL_INSTANCES 4
256 
257 #define CIM_CTL_MAILBOX_VF_STATUS(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
258 #define NUM_CIM_CTL_MAILBOX_VF_STATUS_INSTANCES 4
259 
260 #define CIM_CTL_MAILBOX_VFN_CTL(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 16)
261 #define NUM_CIM_CTL_MAILBOX_VFN_CTL_INSTANCES 128
262 
263 #define CIM_CTL_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 288)
264 #define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4
265 
266 #define CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
267 #define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16
268 
269 #define T5_MYPORT_BASE 0x2c000
270 #define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr))
271 
272 #define T5_PORT0_BASE 0x30000
273 #define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr))
274 
275 #define T5_PORT1_BASE 0x34000
276 #define T5_PORT1_REG(reg_addr) (T5_PORT1_BASE + (reg_addr))
277 
278 #define T5_PORT2_BASE 0x38000
279 #define T5_PORT2_REG(reg_addr) (T5_PORT2_BASE + (reg_addr))
280 
281 #define T5_PORT3_BASE 0x3c000
282 #define T5_PORT3_REG(reg_addr) (T5_PORT3_BASE + (reg_addr))
283 
284 #define T5_PORT_STRIDE 0x4000
285 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
286 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
287 
288 #define PCIE_PF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
289 #define NUM_PCIE_PF_INT_INSTANCES 8
290 
291 #define PCIE_VF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
292 #define NUM_PCIE_VF_INT_INSTANCES 128
293 
294 #define PCIE_FID_VFID(idx) (A_PCIE_FID_VFID + (idx) * 4)
295 #define NUM_PCIE_FID_VFID_INSTANCES 2048
296 
297 #define PCIE_COOKIE_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
298 #define NUM_PCIE_COOKIE_INSTANCES 8
299 
300 #define PCIE_T5_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
301 #define NUM_PCIE_T5_DMA_INSTANCES 4
302 
303 #define PCIE_T5_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
304 #define NUM_PCIE_T5_CMD_INSTANCES 3
305 
306 #define PCIE_T5_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
307 #define NUM_PCIE_T5_HMA_INSTANCES 1
308 
309 #define PCIE_PHY_PRESET_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
310 #define NUM_PCIE_PHY_PRESET_INSTANCES 11
311 
312 #define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8)
313 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
314 
315 #define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8)
316 #define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512
317 
318 #define LE_T5_DB_MASK_IPV4(idx) (A_LE_T5_DB_MASK_IPV4 + (idx) * 4)
319 #define NUM_LE_T5_DB_MASK_IPV4_INSTANCES 5
320 
321 #define LE_T5_DB_ACTIVE_MASK_IPV4(idx) (A_LE_T5_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
322 #define NUM_LE_T5_DB_ACTIVE_MASK_IPV4_INSTANCES 5
323 
324 #define LE_HASH_MASK_GEN_IPV4T5(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
325 #define NUM_LE_HASH_MASK_GEN_IPV4T5_INSTANCES 5
326 
327 #define LE_HASH_MASK_GEN_IPV6T5(idx) (A_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
328 #define NUM_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 12
329 
330 #define LE_HASH_MASK_CMP_IPV4T5(idx) (A_LE_HASH_MASK_CMP_IPV4T5 + (idx) * 4)
331 #define NUM_LE_HASH_MASK_CMP_IPV4T5_INSTANCES 5
332 
333 #define LE_HASH_MASK_CMP_IPV6T5(idx) (A_LE_HASH_MASK_CMP_IPV6T5 + (idx) * 4)
334 #define NUM_LE_HASH_MASK_CMP_IPV6T5_INSTANCES 12
335 
336 #define LE_DB_SECOND_ACTIVE_MASK_IPV4(idx) (A_LE_DB_SECOND_ACTIVE_MASK_IPV4 + (idx) * 4)
337 #define NUM_LE_DB_SECOND_ACTIVE_MASK_IPV4_INSTANCES 5
338 
339 #define LE_DB_SECOND_GEN_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
340 #define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_INSTANCES 5
341 
342 #define LE_DB_SECOND_CMP_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 + (idx) * 4)
343 #define NUM_LE_DB_SECOND_CMP_HASH_MASK_IPV4_INSTANCES 5
344 
345 #define MC_ADR_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
346 #define NUM_MC_ADR_INSTANCES 2
347 
348 #define MC_DDRPHY_DP18_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
349 #define NUM_MC_DDRPHY_DP18_INSTANCES 5
350 
351 #define MC_CE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
352 #define NUM_MC_CE_ERR_DATA_INSTANCES 8
353 
354 #define MC_CE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
355 #define NUM_MC_CE_COR_DATA_INSTANCES 8
356 
357 #define MC_UE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
358 #define NUM_MC_UE_ERR_DATA_INSTANCES 8
359 
360 #define MC_UE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
361 #define NUM_MC_UE_COR_DATA_INSTANCES 8
362 
363 #define MC_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
364 #define NUM_MC_P_BIST_STATUS_INSTANCES 18
365 
366 #define EDC_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
367 #define NUM_EDC_H_BIST_STATUS_INSTANCES 18
368 
369 #define EDC_H_ECC_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
370 #define NUM_EDC_H_ECC_ERR_DATA_INSTANCES 16
371 
372 #define SGE_DEBUG1_DBP_THREAD(idx) (A_SGE_DEBUG1_DBP_THREAD + (idx) * 4)
373 #define NUM_SGE_DEBUG1_DBP_THREAD_INSTANCES 4
374 
375 #define SGE_DEBUG0_DBP_THREAD(idx) (A_SGE_DEBUG0_DBP_THREAD + (idx) * 4)
376 #define NUM_SGE_DEBUG0_DBP_THREAD_INSTANCES 5
377 
378 #define SGE_WC_EGRS_BAR2_OFF_PF(idx) (A_SGE_WC_EGRS_BAR2_OFF_PF + (idx) * 4)
379 #define NUM_SGE_WC_EGRS_BAR2_OFF_PF_INSTANCES 8
380 
381 #define SGE_WC_EGRS_BAR2_OFF_VF(idx) (A_SGE_WC_EGRS_BAR2_OFF_VF + (idx) * 4)
382 #define NUM_SGE_WC_EGRS_BAR2_OFF_VF_INSTANCES 8
383 
384 #define PCIE_T6_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
385 #define NUM_PCIE_T6_DMA_INSTANCES 2
386 
387 #define PCIE_T6_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
388 #define NUM_PCIE_T6_CMD_INSTANCES 1
389 
390 #define PCIE_VF_256_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
391 #define NUM_PCIE_VF_256_INT_INSTANCES 128
392 
393 #define MPS_CLS_REQUEST_TRACE_MAC_DA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_L + (idx) * 32)
394 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_L_INSTANCES 8
395 
396 #define MPS_CLS_REQUEST_TRACE_MAC_DA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_H + (idx) * 32)
397 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_H_INSTANCES 8
398 
399 #define MPS_CLS_REQUEST_TRACE_MAC_SA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_L + (idx) * 32)
400 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_L_INSTANCES 8
401 
402 #define MPS_CLS_REQUEST_TRACE_MAC_SA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_H + (idx) * 32)
403 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_H_INSTANCES 8
404 
405 #define MPS_CLS_REQUEST_TRACE_PORT_VLAN(idx) (A_MPS_CLS_REQUEST_TRACE_PORT_VLAN + (idx) * 32)
406 #define NUM_MPS_CLS_REQUEST_TRACE_PORT_VLAN_INSTANCES 8
407 
408 #define MPS_CLS_REQUEST_TRACE_ENCAP(idx) (A_MPS_CLS_REQUEST_TRACE_ENCAP + (idx) * 32)
409 #define NUM_MPS_CLS_REQUEST_TRACE_ENCAP_INSTANCES 8
410 
411 #define MPS_CLS_RESULT_TRACE(idx) (A_MPS_CLS_RESULT_TRACE + (idx) * 4)
412 #define NUM_MPS_CLS_RESULT_TRACE_INSTANCES 8
413 
414 #define MPS_CLS_DIPIPV4_ID_TABLE(idx) (A_MPS_CLS_DIPIPV4_ID_TABLE + (idx) * 8)
415 #define NUM_MPS_CLS_DIPIPV4_ID_TABLE_INSTANCES 4
416 
417 #define MPS_CLS_DIPIPV4_MASK_TABLE(idx) (A_MPS_CLS_DIPIPV4_MASK_TABLE + (idx) * 8)
418 #define NUM_MPS_CLS_DIPIPV4_MASK_TABLE_INSTANCES 4
419 
420 #define MPS_CLS_DIPIPV6ID_0_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_0_TABLE + (idx) * 32)
421 #define NUM_MPS_CLS_DIPIPV6ID_0_TABLE_INSTANCES 2
422 
423 #define MPS_CLS_DIPIPV6ID_1_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_1_TABLE + (idx) * 32)
424 #define NUM_MPS_CLS_DIPIPV6ID_1_TABLE_INSTANCES 2
425 
426 #define MPS_CLS_DIPIPV6ID_2_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_2_TABLE + (idx) * 32)
427 #define NUM_MPS_CLS_DIPIPV6ID_2_TABLE_INSTANCES 2
428 
429 #define MPS_CLS_DIPIPV6ID_3_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_3_TABLE + (idx) * 32)
430 #define NUM_MPS_CLS_DIPIPV6ID_3_TABLE_INSTANCES 2
431 
432 #define MPS_CLS_DIPIPV6MASK_0_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_0_TABLE + (idx) * 32)
433 #define NUM_MPS_CLS_DIPIPV6MASK_0_TABLE_INSTANCES 2
434 
435 #define MPS_CLS_DIPIPV6MASK_1_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_1_TABLE + (idx) * 32)
436 #define NUM_MPS_CLS_DIPIPV6MASK_1_TABLE_INSTANCES 2
437 
438 #define MPS_CLS_DIPIPV6MASK_2_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_2_TABLE + (idx) * 32)
439 #define NUM_MPS_CLS_DIPIPV6MASK_2_TABLE_INSTANCES 2
440 
441 #define MPS_CLS_DIPIPV6MASK_3_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_3_TABLE + (idx) * 32)
442 #define NUM_MPS_CLS_DIPIPV6MASK_3_TABLE_INSTANCES 2
443 
444 #define MPS_RX_HASH_LKP_TABLE(idx) (A_MPS_RX_HASH_LKP_TABLE + (idx) * 4)
445 #define NUM_MPS_RX_HASH_LKP_TABLE_INSTANCES 4
446 
447 #define LE_DB_DBG_MATCH_DATA_MASK(idx) (A_LE_DB_DBG_MATCH_DATA_MASK + (idx) * 4)
448 #define NUM_LE_DB_DBG_MATCH_DATA_MASK_INSTANCES 8
449 
450 #define LE_DB_DBG_MATCH_DATA(idx) (A_LE_DB_DBG_MATCH_DATA + (idx) * 4)
451 #define NUM_LE_DB_DBG_MATCH_DATA_INSTANCES 8
452 
453 #define LE_DB_DBGI_REQ_DATA_T6(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
454 #define NUM_LE_DB_DBGI_REQ_DATA_T6_INSTANCES 11
455 
456 #define LE_DB_DBGI_REQ_MASK_T6(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
457 #define NUM_LE_DB_DBGI_REQ_MASK_T6_INSTANCES 11
458 
459 #define LE_DB_ACTIVE_MASK_IPV6_T6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
460 #define NUM_LE_DB_ACTIVE_MASK_IPV6_T6_INSTANCES 8
461 
462 #define LE_HASH_MASK_GEN_IPV4T6(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
463 #define NUM_LE_HASH_MASK_GEN_IPV4T6_INSTANCES 8
464 
465 #define T6_LE_HASH_MASK_GEN_IPV6T5(idx) (A_T6_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
466 #define NUM_T6_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 8
467 
468 #define LE_DB_PSV_FILTER_MASK_TUP_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV4 + (idx) * 4)
469 #define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV4_INSTANCES 3
470 
471 #define LE_DB_PSV_FILTER_MASK_FLT_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV4 + (idx) * 4)
472 #define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV4_INSTANCES 2
473 
474 #define LE_DB_PSV_FILTER_MASK_TUP_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV6 + (idx) * 4)
475 #define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV6_INSTANCES 9
476 
477 #define LE_DB_PSV_FILTER_MASK_FLT_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV6 + (idx) * 4)
478 #define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV6_INSTANCES 2
479 
480 #define LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
481 #define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6_INSTANCES 8
482 
483 #define MC_DDRPHY_DP18_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
484 #define NUM_MC_DDRPHY_DP18_T6_INSTANCES 9
485 
486 #define MC_CE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
487 #define NUM_MC_CE_ERR_DATA_T6_INSTANCES 16
488 
489 #define MC_UE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
490 #define NUM_MC_UE_ERR_DATA_T6_INSTANCES 16
491 
492 #define CIM_CTL_MAILBOX_VF_STATUS_T6(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
493 #define NUM_CIM_CTL_MAILBOX_VF_STATUS_T6_INSTANCES 8
494 
495 #define CIM_CTL_MAILBOX_VFN_CTL_T6(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 4)
496 #define NUM_CIM_CTL_MAILBOX_VFN_CTL_T6_INSTANCES 256
497 
498 #define T7_MYPORT_BASE 0x2e000
499 #define T7_MYPORT_REG(reg_addr) (T7_MYPORT_BASE + (reg_addr))
500 
501 #define T7_PORT0_BASE 0x30000
502 #define T7_PORT0_REG(reg_addr) (T7_PORT0_BASE + (reg_addr))
503 
504 #define T7_PORT1_BASE 0x32000
505 #define T7_PORT1_REG(reg_addr) (T7_PORT1_BASE + (reg_addr))
506 
507 #define T7_PORT2_BASE 0x34000
508 #define T7_PORT2_REG(reg_addr) (T7_PORT2_BASE + (reg_addr))
509 
510 #define T7_PORT3_BASE 0x36000
511 #define T7_PORT3_REG(reg_addr) (T7_PORT3_BASE + (reg_addr))
512 
513 #define T7_PORT_STRIDE 0x2000
514 #define T7_PORT_BASE(idx) (T7_PORT0_BASE + (idx) * T7_PORT_STRIDE)
515 #define T7_PORT_REG(idx, reg) (T7_PORT_BASE(idx) + (reg))
516 
517 #define PCIE_MEM_ACCESS_T7_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
518 #define NUM_PCIE_MEM_ACCESS_T7_INSTANCES 16
519 
520 #define PCIE_T7_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
521 #define NUM_PCIE_T7_CMD_INSTANCES 1
522 
523 #define PCIE_T5_ARM_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
524 #define NUM_PCIE_T5_ARM_INSTANCES 1
525 
526 #define PCIE_JBOF_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
527 #define NUM_PCIE_JBOF_INSTANCES 16
528 
529 #define PCIE_EMUADRRMAP_REG(reg_addr, idx) ((reg_addr) + (idx) * 32)
530 #define NUM_PCIE_EMUADRRMAP_INSTANCES 3
531 
532 #define CIM_GFT_MASK(idx) (A_CIM_GFT_MASK + (idx) * 4)
533 #define NUM_CIM_GFT_MASK_INSTANCES 4
534 
535 #define T7_MPS_TRC_FILTER_MATCH_CTL_A(idx) (A_T7_MPS_TRC_FILTER_MATCH_CTL_A + (idx) * 4)
536 #define NUM_T7_MPS_TRC_FILTER_MATCH_CTL_A_INSTANCES 8
537 
538 #define T7_MPS_TRC_FILTER_MATCH_CTL_B(idx) (A_T7_MPS_TRC_FILTER_MATCH_CTL_B + (idx) * 4)
539 #define NUM_T7_MPS_TRC_FILTER_MATCH_CTL_B_INSTANCES 8
540 
541 #define T7_MPS_TRC_FILTER_RUNT_CTL(idx) (A_T7_MPS_TRC_FILTER_RUNT_CTL + (idx) * 4)
542 #define NUM_T7_MPS_TRC_FILTER_RUNT_CTL_INSTANCES 8
543 
544 #define T7_MPS_TRC_FILTER_DROP(idx) (A_T7_MPS_TRC_FILTER_DROP + (idx) * 4)
545 #define NUM_T7_MPS_TRC_FILTER_DROP_INSTANCES 8
546 
547 #define MPS_TRC_FILTER4_MATCH(idx) (A_MPS_TRC_FILTER4_MATCH + (idx) * 4)
548 #define NUM_MPS_TRC_FILTER4_MATCH_INSTANCES 28
549 
550 #define MPS_TRC_FILTER4_DONT_CARE(idx) (A_MPS_TRC_FILTER4_DONT_CARE + (idx) * 4)
551 #define NUM_MPS_TRC_FILTER4_DONT_CARE_INSTANCES 28
552 
553 #define MPS_TRC_FILTER5_MATCH(idx) (A_MPS_TRC_FILTER5_MATCH + (idx) * 4)
554 #define NUM_MPS_TRC_FILTER5_MATCH_INSTANCES 28
555 
556 #define MPS_TRC_FILTER5_DONT_CARE(idx) (A_MPS_TRC_FILTER5_DONT_CARE + (idx) * 4)
557 #define NUM_MPS_TRC_FILTER5_DONT_CARE_INSTANCES 28
558 
559 #define MPS_TRC_FILTER6_MATCH(idx) (A_MPS_TRC_FILTER6_MATCH + (idx) * 4)
560 #define NUM_MPS_TRC_FILTER6_MATCH_INSTANCES 28
561 
562 #define MPS_TRC_FILTER6_DONT_CARE(idx) (A_MPS_TRC_FILTER6_DONT_CARE + (idx) * 4)
563 #define NUM_MPS_TRC_FILTER6_DONT_CARE_INSTANCES 28
564 
565 #define MPS_TRC_FILTER7_MATCH(idx) (A_MPS_TRC_FILTER7_MATCH + (idx) * 4)
566 #define NUM_MPS_TRC_FILTER7_MATCH_INSTANCES 28
567 
568 #define MPS_TRC_FILTER7_DONT_CARE(idx) (A_MPS_TRC_FILTER7_DONT_CARE + (idx) * 4)
569 #define NUM_MPS_TRC_FILTER7_DONT_CARE_INSTANCES 28
570 
571 #define LE_DB_DBGI_REQ_DATA_T7(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
572 #define NUM_LE_DB_DBGI_REQ_DATA_T7_INSTANCES 13
573 
574 #define LE_DB_DBGI_REQ_MASK_T7(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
575 #define NUM_LE_DB_DBGI_REQ_MASK_T7_INSTANCES 13
576 
577 #define LE_DB_ACTIVE_MASK_IPV6_T7(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
578 #define NUM_LE_DB_ACTIVE_MASK_IPV6_T7_INSTANCES 8
579 
580 #define LE_HASH_MASK_GEN_IPV4T7(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
581 #define NUM_LE_HASH_MASK_GEN_IPV4T7_INSTANCES 8
582 
583 #define T7_LE_HASH_MASK_GEN_IPV6T5(idx) (A_T7_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
584 #define NUM_T7_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 8
585 
586 #define LE_DB_SECOND_GEN_HASH_MASK_IPV4_T7(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
587 #define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_T7_INSTANCES 8
588 
589 #define TLS_TX_CH_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)
590 #define NUM_TLS_TX_CH_INSTANCES 6
591 
592 #define TLS_TX_CH_IND_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)
593 #define NUM_TLS_TX_CH_IND_INSTANCES 6
594 
595 #define ARM_CPU_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
596 #define NUM_ARM_CPU_INSTANCES 4
597 
598 #define ARM_CCIM_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
599 #define NUM_ARM_CCIM_INSTANCES 4
600 
601 #define ARM_CCIS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
602 #define NUM_ARM_CCIS_INSTANCES 5
603 
604 #define ARM_CCI_EVNTBUS(idx) (A_ARM_CCI_EVNTBUS + (idx) * 4)
605 #define NUM_ARM_CCI_EVNTBUS_INSTANCES 5
606 
607 #define ARM_ARM_CFG1(idx) (A_ARM_ARM_CFG1 + (idx) * 4)
608 #define NUM_ARM_ARM_CFG1_INSTANCES 2
609 
610 #define ARM_ARM_CFG2(idx) (A_ARM_ARM_CFG2 + (idx) * 4)
611 #define NUM_ARM_ARM_CFG2_INSTANCES 2
612 
613 #define ARM_MSG_REG(reg_addr, idx) ((reg_addr) + (idx) * 48)
614 #define NUM_ARM_MSG_INSTANCES 4
615 
616 #define ARM_MSG_PCIE_MESSAGE2AXI_CFG4(idx) (A_ARM_MSG_PCIE_MESSAGE2AXI_CFG4 + (idx) * 4)
617 #define NUM_ARM_MSG_PCIE_MESSAGE2AXI_CFG4_INSTANCES 2
618 
619 #define MC_CE_ERR_DATA_T7_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
620 #define NUM_MC_CE_ERR_DATA_T7_INSTANCES 16
621 
622 #define MC_UE_ERR_DATA_T7_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
623 #define NUM_MC_UE_ERR_DATA_T7_INSTANCES 16
624 
625 #define MC_P_BIST_USER_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
626 #define NUM_MC_P_BIST_USER_INSTANCES 36
627 
628 #define HMA_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
629 #define NUM_HMA_H_BIST_STATUS_INSTANCES 18
630 
631 #define GCACHE_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
632 #define NUM_GCACHE_P_BIST_STATUS_INSTANCES 18
633 
634 #define CIM_CTL_MAILBOX_VF_STATUS_T7(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
635 #define NUM_CIM_CTL_MAILBOX_VF_STATUS_T7_INSTANCES 8
636 
637 #define CIM_CTL_MAILBOX_VFN_CTL_T7(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 4)
638 #define NUM_CIM_CTL_MAILBOX_VFN_CTL_T7_INSTANCES 256
639 
640 #define CIM_CTL_TID_MAP_EN(idx) (A_CIM_CTL_TID_MAP_EN + (idx) * 4)
641 #define NUM_CIM_CTL_TID_MAP_EN_INSTANCES 8
642 
643 #define CIM_CTL_TID_MAP_CORE(idx) (A_CIM_CTL_TID_MAP_CORE + (idx) * 4)
644 #define NUM_CIM_CTL_TID_MAP_CORE_INSTANCES 8
645 
646 #define CIM_CTL_CRYPTO_KEY_DATA(idx) (A_CIM_CTL_CRYPTO_KEY_DATA + (idx) * 4)
647 #define NUM_CIM_CTL_CRYPTO_KEY_DATA_INSTANCES 17
648 
649 #define CIM_CTL_FLOWID_OP_VALID(idx) (A_CIM_CTL_FLOWID_OP_VALID + (idx) * 4)
650 #define NUM_CIM_CTL_FLOWID_OP_VALID_INSTANCES 8
651 
652 #define CIM_CTL_SLV_REG(reg_addr, idx) ((reg_addr) + (idx) * 1024)
653 #define NUM_CIM_CTL_SLV_INSTANCES 7
654 
655 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
656 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
657 
658 #define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
659 #define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx)
660 
661 #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
662 #define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
663 
664 #define MC_T7_STRIDE (MC_T71_BASE_ADDR - MC_T70_BASE_ADDR)
665 #define MC_T7_REG(reg, idx) (reg + MC_T7_STRIDE * idx)
666 
667 /* registers for module SGE */
668 #define SGE_BASE_ADDR 0x1000
669 
670 #define A_SGE_PF_KDOORBELL 0x0
671 
672 #define S_QID    15
673 #define M_QID    0x1ffffU
674 #define V_QID(x) ((x) << S_QID)
675 #define G_QID(x) (((x) >> S_QID) & M_QID)
676 
677 #define S_DBPRIO    14
678 #define V_DBPRIO(x) ((x) << S_DBPRIO)
679 #define F_DBPRIO    V_DBPRIO(1U)
680 
681 #define S_PIDX    0
682 #define M_PIDX    0x3fffU
683 #define V_PIDX(x) ((x) << S_PIDX)
684 #define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX)
685 
686 #define A_SGE_VF_KDOORBELL 0x0
687 
688 #define S_DBTYPE    13
689 #define V_DBTYPE(x) ((x) << S_DBTYPE)
690 #define F_DBTYPE    V_DBTYPE(1U)
691 
692 #define S_PIDX_T5    0
693 #define M_PIDX_T5    0x1fffU
694 #define V_PIDX_T5(x) ((x) << S_PIDX_T5)
695 #define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
696 
697 #define S_SYNC_T6    14
698 #define V_SYNC_T6(x) ((x) << S_SYNC_T6)
699 #define F_SYNC_T6    V_SYNC_T6(1U)
700 
701 #define A_SGE_PF_GTS 0x4
702 
703 #define S_INGRESSQID    16
704 #define M_INGRESSQID    0xffffU
705 #define V_INGRESSQID(x) ((x) << S_INGRESSQID)
706 #define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID)
707 
708 #define S_TIMERREG    13
709 #define M_TIMERREG    0x7U
710 #define V_TIMERREG(x) ((x) << S_TIMERREG)
711 #define G_TIMERREG(x) (((x) >> S_TIMERREG) & M_TIMERREG)
712 
713 #define S_SEINTARM    12
714 #define V_SEINTARM(x) ((x) << S_SEINTARM)
715 #define F_SEINTARM    V_SEINTARM(1U)
716 
717 #define S_CIDXINC    0
718 #define M_CIDXINC    0xfffU
719 #define V_CIDXINC(x) ((x) << S_CIDXINC)
720 #define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC)
721 
722 #define A_SGE_VF_GTS 0x4
723 #define A_SGE_PF_KTIMESTAMP_LO 0x8
724 #define A_SGE_VF_KTIMESTAMP_LO 0x8
725 #define A_SGE_PF_KTIMESTAMP_HI 0xc
726 
727 #define S_TSTAMPVAL    0
728 #define M_TSTAMPVAL    0xfffffffU
729 #define V_TSTAMPVAL(x) ((x) << S_TSTAMPVAL)
730 #define G_TSTAMPVAL(x) (((x) >> S_TSTAMPVAL) & M_TSTAMPVAL)
731 
732 #define A_SGE_VF_KTIMESTAMP_HI 0xc
733 #define A_SGE_CONTROL 0x1008
734 
735 #define S_IGRALLCPLTOFL    31
736 #define V_IGRALLCPLTOFL(x) ((x) << S_IGRALLCPLTOFL)
737 #define F_IGRALLCPLTOFL    V_IGRALLCPLTOFL(1U)
738 
739 #define S_FLSPLITMIN    22
740 #define M_FLSPLITMIN    0x1ffU
741 #define V_FLSPLITMIN(x) ((x) << S_FLSPLITMIN)
742 #define G_FLSPLITMIN(x) (((x) >> S_FLSPLITMIN) & M_FLSPLITMIN)
743 
744 #define S_FLSPLITMODE    20
745 #define M_FLSPLITMODE    0x3U
746 #define V_FLSPLITMODE(x) ((x) << S_FLSPLITMODE)
747 #define G_FLSPLITMODE(x) (((x) >> S_FLSPLITMODE) & M_FLSPLITMODE)
748 
749 #define S_DCASYSTYPE    19
750 #define V_DCASYSTYPE(x) ((x) << S_DCASYSTYPE)
751 #define F_DCASYSTYPE    V_DCASYSTYPE(1U)
752 
753 #define S_RXPKTCPLMODE    18
754 #define V_RXPKTCPLMODE(x) ((x) << S_RXPKTCPLMODE)
755 #define F_RXPKTCPLMODE    V_RXPKTCPLMODE(1U)
756 
757 #define S_EGRSTATUSPAGESIZE    17
758 #define V_EGRSTATUSPAGESIZE(x) ((x) << S_EGRSTATUSPAGESIZE)
759 #define F_EGRSTATUSPAGESIZE    V_EGRSTATUSPAGESIZE(1U)
760 
761 #define S_INGHINTENABLE1    15
762 #define V_INGHINTENABLE1(x) ((x) << S_INGHINTENABLE1)
763 #define F_INGHINTENABLE1    V_INGHINTENABLE1(1U)
764 
765 #define S_INGHINTENABLE0    14
766 #define V_INGHINTENABLE0(x) ((x) << S_INGHINTENABLE0)
767 #define F_INGHINTENABLE0    V_INGHINTENABLE0(1U)
768 
769 #define S_INGINTCOMPAREIDX    13
770 #define V_INGINTCOMPAREIDX(x) ((x) << S_INGINTCOMPAREIDX)
771 #define F_INGINTCOMPAREIDX    V_INGINTCOMPAREIDX(1U)
772 
773 #define S_PKTSHIFT    10
774 #define M_PKTSHIFT    0x7U
775 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
776 #define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)
777 
778 #define S_INGPCIEBOUNDARY    7
779 #define M_INGPCIEBOUNDARY    0x7U
780 #define V_INGPCIEBOUNDARY(x) ((x) << S_INGPCIEBOUNDARY)
781 #define G_INGPCIEBOUNDARY(x) (((x) >> S_INGPCIEBOUNDARY) & M_INGPCIEBOUNDARY)
782 
783 #define S_INGPADBOUNDARY    4
784 #define M_INGPADBOUNDARY    0x7U
785 #define V_INGPADBOUNDARY(x) ((x) << S_INGPADBOUNDARY)
786 #define G_INGPADBOUNDARY(x) (((x) >> S_INGPADBOUNDARY) & M_INGPADBOUNDARY)
787 
788 #define S_EGRPCIEBOUNDARY    1
789 #define M_EGRPCIEBOUNDARY    0x7U
790 #define V_EGRPCIEBOUNDARY(x) ((x) << S_EGRPCIEBOUNDARY)
791 #define G_EGRPCIEBOUNDARY(x) (((x) >> S_EGRPCIEBOUNDARY) & M_EGRPCIEBOUNDARY)
792 
793 #define S_GLOBALENABLE    0
794 #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
795 #define F_GLOBALENABLE    V_GLOBALENABLE(1U)
796 
797 #define S_NUMOFFID    19
798 #define M_NUMOFFID    0x7U
799 #define V_NUMOFFID(x) ((x) << S_NUMOFFID)
800 #define G_NUMOFFID(x) (((x) >> S_NUMOFFID) & M_NUMOFFID)
801 
802 #define S_INGHINTENABLE2    16
803 #define V_INGHINTENABLE2(x) ((x) << S_INGHINTENABLE2)
804 #define F_INGHINTENABLE2    V_INGHINTENABLE2(1U)
805 
806 #define S_INGHINTENABLE3    3
807 #define V_INGHINTENABLE3(x) ((x) << S_INGHINTENABLE3)
808 #define F_INGHINTENABLE3    V_INGHINTENABLE3(1U)
809 
810 #define S_TF_MODE    1
811 #define M_TF_MODE    0x3U
812 #define V_TF_MODE(x) ((x) << S_TF_MODE)
813 #define G_TF_MODE(x) (((x) >> S_TF_MODE) & M_TF_MODE)
814 
815 #define A_SGE_HOST_PAGE_SIZE 0x100c
816 
817 #define S_HOSTPAGESIZEPF7    28
818 #define M_HOSTPAGESIZEPF7    0xfU
819 #define V_HOSTPAGESIZEPF7(x) ((x) << S_HOSTPAGESIZEPF7)
820 #define G_HOSTPAGESIZEPF7(x) (((x) >> S_HOSTPAGESIZEPF7) & M_HOSTPAGESIZEPF7)
821 
822 #define S_HOSTPAGESIZEPF6    24
823 #define M_HOSTPAGESIZEPF6    0xfU
824 #define V_HOSTPAGESIZEPF6(x) ((x) << S_HOSTPAGESIZEPF6)
825 #define G_HOSTPAGESIZEPF6(x) (((x) >> S_HOSTPAGESIZEPF6) & M_HOSTPAGESIZEPF6)
826 
827 #define S_HOSTPAGESIZEPF5    20
828 #define M_HOSTPAGESIZEPF5    0xfU
829 #define V_HOSTPAGESIZEPF5(x) ((x) << S_HOSTPAGESIZEPF5)
830 #define G_HOSTPAGESIZEPF5(x) (((x) >> S_HOSTPAGESIZEPF5) & M_HOSTPAGESIZEPF5)
831 
832 #define S_HOSTPAGESIZEPF4    16
833 #define M_HOSTPAGESIZEPF4    0xfU
834 #define V_HOSTPAGESIZEPF4(x) ((x) << S_HOSTPAGESIZEPF4)
835 #define G_HOSTPAGESIZEPF4(x) (((x) >> S_HOSTPAGESIZEPF4) & M_HOSTPAGESIZEPF4)
836 
837 #define S_HOSTPAGESIZEPF3    12
838 #define M_HOSTPAGESIZEPF3    0xfU
839 #define V_HOSTPAGESIZEPF3(x) ((x) << S_HOSTPAGESIZEPF3)
840 #define G_HOSTPAGESIZEPF3(x) (((x) >> S_HOSTPAGESIZEPF3) & M_HOSTPAGESIZEPF3)
841 
842 #define S_HOSTPAGESIZEPF2    8
843 #define M_HOSTPAGESIZEPF2    0xfU
844 #define V_HOSTPAGESIZEPF2(x) ((x) << S_HOSTPAGESIZEPF2)
845 #define G_HOSTPAGESIZEPF2(x) (((x) >> S_HOSTPAGESIZEPF2) & M_HOSTPAGESIZEPF2)
846 
847 #define S_HOSTPAGESIZEPF1    4
848 #define M_HOSTPAGESIZEPF1    0xfU
849 #define V_HOSTPAGESIZEPF1(x) ((x) << S_HOSTPAGESIZEPF1)
850 #define G_HOSTPAGESIZEPF1(x) (((x) >> S_HOSTPAGESIZEPF1) & M_HOSTPAGESIZEPF1)
851 
852 #define S_HOSTPAGESIZEPF0    0
853 #define M_HOSTPAGESIZEPF0    0xfU
854 #define V_HOSTPAGESIZEPF0(x) ((x) << S_HOSTPAGESIZEPF0)
855 #define G_HOSTPAGESIZEPF0(x) (((x) >> S_HOSTPAGESIZEPF0) & M_HOSTPAGESIZEPF0)
856 
857 #define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
858 
859 #define S_QUEUESPERPAGEPF7    28
860 #define M_QUEUESPERPAGEPF7    0xfU
861 #define V_QUEUESPERPAGEPF7(x) ((x) << S_QUEUESPERPAGEPF7)
862 #define G_QUEUESPERPAGEPF7(x) (((x) >> S_QUEUESPERPAGEPF7) & M_QUEUESPERPAGEPF7)
863 
864 #define S_QUEUESPERPAGEPF6    24
865 #define M_QUEUESPERPAGEPF6    0xfU
866 #define V_QUEUESPERPAGEPF6(x) ((x) << S_QUEUESPERPAGEPF6)
867 #define G_QUEUESPERPAGEPF6(x) (((x) >> S_QUEUESPERPAGEPF6) & M_QUEUESPERPAGEPF6)
868 
869 #define S_QUEUESPERPAGEPF5    20
870 #define M_QUEUESPERPAGEPF5    0xfU
871 #define V_QUEUESPERPAGEPF5(x) ((x) << S_QUEUESPERPAGEPF5)
872 #define G_QUEUESPERPAGEPF5(x) (((x) >> S_QUEUESPERPAGEPF5) & M_QUEUESPERPAGEPF5)
873 
874 #define S_QUEUESPERPAGEPF4    16
875 #define M_QUEUESPERPAGEPF4    0xfU
876 #define V_QUEUESPERPAGEPF4(x) ((x) << S_QUEUESPERPAGEPF4)
877 #define G_QUEUESPERPAGEPF4(x) (((x) >> S_QUEUESPERPAGEPF4) & M_QUEUESPERPAGEPF4)
878 
879 #define S_QUEUESPERPAGEPF3    12
880 #define M_QUEUESPERPAGEPF3    0xfU
881 #define V_QUEUESPERPAGEPF3(x) ((x) << S_QUEUESPERPAGEPF3)
882 #define G_QUEUESPERPAGEPF3(x) (((x) >> S_QUEUESPERPAGEPF3) & M_QUEUESPERPAGEPF3)
883 
884 #define S_QUEUESPERPAGEPF2    8
885 #define M_QUEUESPERPAGEPF2    0xfU
886 #define V_QUEUESPERPAGEPF2(x) ((x) << S_QUEUESPERPAGEPF2)
887 #define G_QUEUESPERPAGEPF2(x) (((x) >> S_QUEUESPERPAGEPF2) & M_QUEUESPERPAGEPF2)
888 
889 #define S_QUEUESPERPAGEPF1    4
890 #define M_QUEUESPERPAGEPF1    0xfU
891 #define V_QUEUESPERPAGEPF1(x) ((x) << S_QUEUESPERPAGEPF1)
892 #define G_QUEUESPERPAGEPF1(x) (((x) >> S_QUEUESPERPAGEPF1) & M_QUEUESPERPAGEPF1)
893 
894 #define S_QUEUESPERPAGEPF0    0
895 #define M_QUEUESPERPAGEPF0    0xfU
896 #define V_QUEUESPERPAGEPF0(x) ((x) << S_QUEUESPERPAGEPF0)
897 #define G_QUEUESPERPAGEPF0(x) (((x) >> S_QUEUESPERPAGEPF0) & M_QUEUESPERPAGEPF0)
898 
899 #define A_SGE_EGRESS_QUEUES_PER_PAGE_VF 0x1014
900 
901 #define S_QUEUESPERPAGEVFPF7    28
902 #define M_QUEUESPERPAGEVFPF7    0xfU
903 #define V_QUEUESPERPAGEVFPF7(x) ((x) << S_QUEUESPERPAGEVFPF7)
904 #define G_QUEUESPERPAGEVFPF7(x) (((x) >> S_QUEUESPERPAGEVFPF7) & M_QUEUESPERPAGEVFPF7)
905 
906 #define S_QUEUESPERPAGEVFPF6    24
907 #define M_QUEUESPERPAGEVFPF6    0xfU
908 #define V_QUEUESPERPAGEVFPF6(x) ((x) << S_QUEUESPERPAGEVFPF6)
909 #define G_QUEUESPERPAGEVFPF6(x) (((x) >> S_QUEUESPERPAGEVFPF6) & M_QUEUESPERPAGEVFPF6)
910 
911 #define S_QUEUESPERPAGEVFPF5    20
912 #define M_QUEUESPERPAGEVFPF5    0xfU
913 #define V_QUEUESPERPAGEVFPF5(x) ((x) << S_QUEUESPERPAGEVFPF5)
914 #define G_QUEUESPERPAGEVFPF5(x) (((x) >> S_QUEUESPERPAGEVFPF5) & M_QUEUESPERPAGEVFPF5)
915 
916 #define S_QUEUESPERPAGEVFPF4    16
917 #define M_QUEUESPERPAGEVFPF4    0xfU
918 #define V_QUEUESPERPAGEVFPF4(x) ((x) << S_QUEUESPERPAGEVFPF4)
919 #define G_QUEUESPERPAGEVFPF4(x) (((x) >> S_QUEUESPERPAGEVFPF4) & M_QUEUESPERPAGEVFPF4)
920 
921 #define S_QUEUESPERPAGEVFPF3    12
922 #define M_QUEUESPERPAGEVFPF3    0xfU
923 #define V_QUEUESPERPAGEVFPF3(x) ((x) << S_QUEUESPERPAGEVFPF3)
924 #define G_QUEUESPERPAGEVFPF3(x) (((x) >> S_QUEUESPERPAGEVFPF3) & M_QUEUESPERPAGEVFPF3)
925 
926 #define S_QUEUESPERPAGEVFPF2    8
927 #define M_QUEUESPERPAGEVFPF2    0xfU
928 #define V_QUEUESPERPAGEVFPF2(x) ((x) << S_QUEUESPERPAGEVFPF2)
929 #define G_QUEUESPERPAGEVFPF2(x) (((x) >> S_QUEUESPERPAGEVFPF2) & M_QUEUESPERPAGEVFPF2)
930 
931 #define S_QUEUESPERPAGEVFPF1    4
932 #define M_QUEUESPERPAGEVFPF1    0xfU
933 #define V_QUEUESPERPAGEVFPF1(x) ((x) << S_QUEUESPERPAGEVFPF1)
934 #define G_QUEUESPERPAGEVFPF1(x) (((x) >> S_QUEUESPERPAGEVFPF1) & M_QUEUESPERPAGEVFPF1)
935 
936 #define S_QUEUESPERPAGEVFPF0    0
937 #define M_QUEUESPERPAGEVFPF0    0xfU
938 #define V_QUEUESPERPAGEVFPF0(x) ((x) << S_QUEUESPERPAGEVFPF0)
939 #define G_QUEUESPERPAGEVFPF0(x) (((x) >> S_QUEUESPERPAGEVFPF0) & M_QUEUESPERPAGEVFPF0)
940 
941 #define A_SGE_USER_MODE_LIMITS 0x1018
942 
943 #define S_OPCODE_MIN    24
944 #define M_OPCODE_MIN    0xffU
945 #define V_OPCODE_MIN(x) ((x) << S_OPCODE_MIN)
946 #define G_OPCODE_MIN(x) (((x) >> S_OPCODE_MIN) & M_OPCODE_MIN)
947 
948 #define S_OPCODE_MAX    16
949 #define M_OPCODE_MAX    0xffU
950 #define V_OPCODE_MAX(x) ((x) << S_OPCODE_MAX)
951 #define G_OPCODE_MAX(x) (((x) >> S_OPCODE_MAX) & M_OPCODE_MAX)
952 
953 #define S_LENGTH_MIN    8
954 #define M_LENGTH_MIN    0xffU
955 #define V_LENGTH_MIN(x) ((x) << S_LENGTH_MIN)
956 #define G_LENGTH_MIN(x) (((x) >> S_LENGTH_MIN) & M_LENGTH_MIN)
957 
958 #define S_LENGTH_MAX    0
959 #define M_LENGTH_MAX    0xffU
960 #define V_LENGTH_MAX(x) ((x) << S_LENGTH_MAX)
961 #define G_LENGTH_MAX(x) (((x) >> S_LENGTH_MAX) & M_LENGTH_MAX)
962 
963 #define A_SGE_WR_ERROR 0x101c
964 
965 #define S_WR_ERROR_OPCODE    0
966 #define M_WR_ERROR_OPCODE    0xffU
967 #define V_WR_ERROR_OPCODE(x) ((x) << S_WR_ERROR_OPCODE)
968 #define G_WR_ERROR_OPCODE(x) (((x) >> S_WR_ERROR_OPCODE) & M_WR_ERROR_OPCODE)
969 
970 #define S_WR_SENDPATH_ERROR_OPCODE    16
971 #define M_WR_SENDPATH_ERROR_OPCODE    0xffU
972 #define V_WR_SENDPATH_ERROR_OPCODE(x) ((x) << S_WR_SENDPATH_ERROR_OPCODE)
973 #define G_WR_SENDPATH_ERROR_OPCODE(x) (((x) >> S_WR_SENDPATH_ERROR_OPCODE) & M_WR_SENDPATH_ERROR_OPCODE)
974 
975 #define S_WR_SENDPATH_OPCODE    8
976 #define M_WR_SENDPATH_OPCODE    0xffU
977 #define V_WR_SENDPATH_OPCODE(x) ((x) << S_WR_SENDPATH_OPCODE)
978 #define G_WR_SENDPATH_OPCODE(x) (((x) >> S_WR_SENDPATH_OPCODE) & M_WR_SENDPATH_OPCODE)
979 
980 #define A_SGE_PERR_INJECT 0x1020
981 
982 #define S_MEMSEL    1
983 #define M_MEMSEL    0x1fU
984 #define V_MEMSEL(x) ((x) << S_MEMSEL)
985 #define G_MEMSEL(x) (((x) >> S_MEMSEL) & M_MEMSEL)
986 
987 #define S_INJECTDATAERR    0
988 #define V_INJECTDATAERR(x) ((x) << S_INJECTDATAERR)
989 #define F_INJECTDATAERR    V_INJECTDATAERR(1U)
990 
991 #define A_SGE_INT_CAUSE1 0x1024
992 
993 #define S_PERR_FLM_CREDITFIFO    30
994 #define V_PERR_FLM_CREDITFIFO(x) ((x) << S_PERR_FLM_CREDITFIFO)
995 #define F_PERR_FLM_CREDITFIFO    V_PERR_FLM_CREDITFIFO(1U)
996 
997 #define S_PERR_IMSG_HINT_FIFO    29
998 #define V_PERR_IMSG_HINT_FIFO(x) ((x) << S_PERR_IMSG_HINT_FIFO)
999 #define F_PERR_IMSG_HINT_FIFO    V_PERR_IMSG_HINT_FIFO(1U)
1000 
1001 #define S_PERR_MC_PC    28
1002 #define V_PERR_MC_PC(x) ((x) << S_PERR_MC_PC)
1003 #define F_PERR_MC_PC    V_PERR_MC_PC(1U)
1004 
1005 #define S_PERR_MC_IGR_CTXT    27
1006 #define V_PERR_MC_IGR_CTXT(x) ((x) << S_PERR_MC_IGR_CTXT)
1007 #define F_PERR_MC_IGR_CTXT    V_PERR_MC_IGR_CTXT(1U)
1008 
1009 #define S_PERR_MC_EGR_CTXT    26
1010 #define V_PERR_MC_EGR_CTXT(x) ((x) << S_PERR_MC_EGR_CTXT)
1011 #define F_PERR_MC_EGR_CTXT    V_PERR_MC_EGR_CTXT(1U)
1012 
1013 #define S_PERR_MC_FLM    25
1014 #define V_PERR_MC_FLM(x) ((x) << S_PERR_MC_FLM)
1015 #define F_PERR_MC_FLM    V_PERR_MC_FLM(1U)
1016 
1017 #define S_PERR_PC_MCTAG    24
1018 #define V_PERR_PC_MCTAG(x) ((x) << S_PERR_PC_MCTAG)
1019 #define F_PERR_PC_MCTAG    V_PERR_PC_MCTAG(1U)
1020 
1021 #define S_PERR_PC_CHPI_RSP1    23
1022 #define V_PERR_PC_CHPI_RSP1(x) ((x) << S_PERR_PC_CHPI_RSP1)
1023 #define F_PERR_PC_CHPI_RSP1    V_PERR_PC_CHPI_RSP1(1U)
1024 
1025 #define S_PERR_PC_CHPI_RSP0    22
1026 #define V_PERR_PC_CHPI_RSP0(x) ((x) << S_PERR_PC_CHPI_RSP0)
1027 #define F_PERR_PC_CHPI_RSP0    V_PERR_PC_CHPI_RSP0(1U)
1028 
1029 #define S_PERR_DBP_PC_RSP_FIFO3    21
1030 #define V_PERR_DBP_PC_RSP_FIFO3(x) ((x) << S_PERR_DBP_PC_RSP_FIFO3)
1031 #define F_PERR_DBP_PC_RSP_FIFO3    V_PERR_DBP_PC_RSP_FIFO3(1U)
1032 
1033 #define S_PERR_DBP_PC_RSP_FIFO2    20
1034 #define V_PERR_DBP_PC_RSP_FIFO2(x) ((x) << S_PERR_DBP_PC_RSP_FIFO2)
1035 #define F_PERR_DBP_PC_RSP_FIFO2    V_PERR_DBP_PC_RSP_FIFO2(1U)
1036 
1037 #define S_PERR_DBP_PC_RSP_FIFO1    19
1038 #define V_PERR_DBP_PC_RSP_FIFO1(x) ((x) << S_PERR_DBP_PC_RSP_FIFO1)
1039 #define F_PERR_DBP_PC_RSP_FIFO1    V_PERR_DBP_PC_RSP_FIFO1(1U)
1040 
1041 #define S_PERR_DBP_PC_RSP_FIFO0    18
1042 #define V_PERR_DBP_PC_RSP_FIFO0(x) ((x) << S_PERR_DBP_PC_RSP_FIFO0)
1043 #define F_PERR_DBP_PC_RSP_FIFO0    V_PERR_DBP_PC_RSP_FIFO0(1U)
1044 
1045 #define S_PERR_DMARBT    17
1046 #define V_PERR_DMARBT(x) ((x) << S_PERR_DMARBT)
1047 #define F_PERR_DMARBT    V_PERR_DMARBT(1U)
1048 
1049 #define S_PERR_FLM_DBPFIFO    16
1050 #define V_PERR_FLM_DBPFIFO(x) ((x) << S_PERR_FLM_DBPFIFO)
1051 #define F_PERR_FLM_DBPFIFO    V_PERR_FLM_DBPFIFO(1U)
1052 
1053 #define S_PERR_FLM_MCREQ_FIFO    15
1054 #define V_PERR_FLM_MCREQ_FIFO(x) ((x) << S_PERR_FLM_MCREQ_FIFO)
1055 #define F_PERR_FLM_MCREQ_FIFO    V_PERR_FLM_MCREQ_FIFO(1U)
1056 
1057 #define S_PERR_FLM_HINTFIFO    14
1058 #define V_PERR_FLM_HINTFIFO(x) ((x) << S_PERR_FLM_HINTFIFO)
1059 #define F_PERR_FLM_HINTFIFO    V_PERR_FLM_HINTFIFO(1U)
1060 
1061 #define S_PERR_ALIGN_CTL_FIFO3    13
1062 #define V_PERR_ALIGN_CTL_FIFO3(x) ((x) << S_PERR_ALIGN_CTL_FIFO3)
1063 #define F_PERR_ALIGN_CTL_FIFO3    V_PERR_ALIGN_CTL_FIFO3(1U)
1064 
1065 #define S_PERR_ALIGN_CTL_FIFO2    12
1066 #define V_PERR_ALIGN_CTL_FIFO2(x) ((x) << S_PERR_ALIGN_CTL_FIFO2)
1067 #define F_PERR_ALIGN_CTL_FIFO2    V_PERR_ALIGN_CTL_FIFO2(1U)
1068 
1069 #define S_PERR_ALIGN_CTL_FIFO1    11
1070 #define V_PERR_ALIGN_CTL_FIFO1(x) ((x) << S_PERR_ALIGN_CTL_FIFO1)
1071 #define F_PERR_ALIGN_CTL_FIFO1    V_PERR_ALIGN_CTL_FIFO1(1U)
1072 
1073 #define S_PERR_ALIGN_CTL_FIFO0    10
1074 #define V_PERR_ALIGN_CTL_FIFO0(x) ((x) << S_PERR_ALIGN_CTL_FIFO0)
1075 #define F_PERR_ALIGN_CTL_FIFO0    V_PERR_ALIGN_CTL_FIFO0(1U)
1076 
1077 #define S_PERR_EDMA_FIFO3    9
1078 #define V_PERR_EDMA_FIFO3(x) ((x) << S_PERR_EDMA_FIFO3)
1079 #define F_PERR_EDMA_FIFO3    V_PERR_EDMA_FIFO3(1U)
1080 
1081 #define S_PERR_EDMA_FIFO2    8
1082 #define V_PERR_EDMA_FIFO2(x) ((x) << S_PERR_EDMA_FIFO2)
1083 #define F_PERR_EDMA_FIFO2    V_PERR_EDMA_FIFO2(1U)
1084 
1085 #define S_PERR_EDMA_FIFO1    7
1086 #define V_PERR_EDMA_FIFO1(x) ((x) << S_PERR_EDMA_FIFO1)
1087 #define F_PERR_EDMA_FIFO1    V_PERR_EDMA_FIFO1(1U)
1088 
1089 #define S_PERR_EDMA_FIFO0    6
1090 #define V_PERR_EDMA_FIFO0(x) ((x) << S_PERR_EDMA_FIFO0)
1091 #define F_PERR_EDMA_FIFO0    V_PERR_EDMA_FIFO0(1U)
1092 
1093 #define S_PERR_PD_FIFO3    5
1094 #define V_PERR_PD_FIFO3(x) ((x) << S_PERR_PD_FIFO3)
1095 #define F_PERR_PD_FIFO3    V_PERR_PD_FIFO3(1U)
1096 
1097 #define S_PERR_PD_FIFO2    4
1098 #define V_PERR_PD_FIFO2(x) ((x) << S_PERR_PD_FIFO2)
1099 #define F_PERR_PD_FIFO2    V_PERR_PD_FIFO2(1U)
1100 
1101 #define S_PERR_PD_FIFO1    3
1102 #define V_PERR_PD_FIFO1(x) ((x) << S_PERR_PD_FIFO1)
1103 #define F_PERR_PD_FIFO1    V_PERR_PD_FIFO1(1U)
1104 
1105 #define S_PERR_PD_FIFO0    2
1106 #define V_PERR_PD_FIFO0(x) ((x) << S_PERR_PD_FIFO0)
1107 #define F_PERR_PD_FIFO0    V_PERR_PD_FIFO0(1U)
1108 
1109 #define S_PERR_ING_CTXT_MIFRSP    1
1110 #define V_PERR_ING_CTXT_MIFRSP(x) ((x) << S_PERR_ING_CTXT_MIFRSP)
1111 #define F_PERR_ING_CTXT_MIFRSP    V_PERR_ING_CTXT_MIFRSP(1U)
1112 
1113 #define S_PERR_EGR_CTXT_MIFRSP    0
1114 #define V_PERR_EGR_CTXT_MIFRSP(x) ((x) << S_PERR_EGR_CTXT_MIFRSP)
1115 #define F_PERR_EGR_CTXT_MIFRSP    V_PERR_EGR_CTXT_MIFRSP(1U)
1116 
1117 #define S_PERR_PC_CHPI_RSP2    31
1118 #define V_PERR_PC_CHPI_RSP2(x) ((x) << S_PERR_PC_CHPI_RSP2)
1119 #define F_PERR_PC_CHPI_RSP2    V_PERR_PC_CHPI_RSP2(1U)
1120 
1121 #define S_PERR_PC_RSP    23
1122 #define V_PERR_PC_RSP(x) ((x) << S_PERR_PC_RSP)
1123 #define F_PERR_PC_RSP    V_PERR_PC_RSP(1U)
1124 
1125 #define S_PERR_PC_REQ    22
1126 #define V_PERR_PC_REQ(x) ((x) << S_PERR_PC_REQ)
1127 #define F_PERR_PC_REQ    V_PERR_PC_REQ(1U)
1128 
1129 #define S_PERR_HEADERSPLIT_FIFO3    28
1130 #define V_PERR_HEADERSPLIT_FIFO3(x) ((x) << S_PERR_HEADERSPLIT_FIFO3)
1131 #define F_PERR_HEADERSPLIT_FIFO3    V_PERR_HEADERSPLIT_FIFO3(1U)
1132 
1133 #define S_PERR_HEADERSPLIT_FIFO2    27
1134 #define V_PERR_HEADERSPLIT_FIFO2(x) ((x) << S_PERR_HEADERSPLIT_FIFO2)
1135 #define F_PERR_HEADERSPLIT_FIFO2    V_PERR_HEADERSPLIT_FIFO2(1U)
1136 
1137 #define S_PERR_PAYLOAD_FIFO3    26
1138 #define V_PERR_PAYLOAD_FIFO3(x) ((x) << S_PERR_PAYLOAD_FIFO3)
1139 #define F_PERR_PAYLOAD_FIFO3    V_PERR_PAYLOAD_FIFO3(1U)
1140 
1141 #define S_PERR_PAYLOAD_FIFO2    25
1142 #define V_PERR_PAYLOAD_FIFO2(x) ((x) << S_PERR_PAYLOAD_FIFO2)
1143 #define F_PERR_PAYLOAD_FIFO2    V_PERR_PAYLOAD_FIFO2(1U)
1144 
1145 #define A_SGE_INT_ENABLE1 0x1028
1146 #define A_SGE_PERR_ENABLE1 0x102c
1147 #define A_SGE_INT_CAUSE2 0x1030
1148 
1149 #define S_PERR_HINT_DELAY_FIFO1    30
1150 #define V_PERR_HINT_DELAY_FIFO1(x) ((x) << S_PERR_HINT_DELAY_FIFO1)
1151 #define F_PERR_HINT_DELAY_FIFO1    V_PERR_HINT_DELAY_FIFO1(1U)
1152 
1153 #define S_PERR_HINT_DELAY_FIFO0    29
1154 #define V_PERR_HINT_DELAY_FIFO0(x) ((x) << S_PERR_HINT_DELAY_FIFO0)
1155 #define F_PERR_HINT_DELAY_FIFO0    V_PERR_HINT_DELAY_FIFO0(1U)
1156 
1157 #define S_PERR_IMSG_PD_FIFO    28
1158 #define V_PERR_IMSG_PD_FIFO(x) ((x) << S_PERR_IMSG_PD_FIFO)
1159 #define F_PERR_IMSG_PD_FIFO    V_PERR_IMSG_PD_FIFO(1U)
1160 
1161 #define S_PERR_ULPTX_FIFO1    27
1162 #define V_PERR_ULPTX_FIFO1(x) ((x) << S_PERR_ULPTX_FIFO1)
1163 #define F_PERR_ULPTX_FIFO1    V_PERR_ULPTX_FIFO1(1U)
1164 
1165 #define S_PERR_ULPTX_FIFO0    26
1166 #define V_PERR_ULPTX_FIFO0(x) ((x) << S_PERR_ULPTX_FIFO0)
1167 #define F_PERR_ULPTX_FIFO0    V_PERR_ULPTX_FIFO0(1U)
1168 
1169 #define S_PERR_IDMA2IMSG_FIFO1    25
1170 #define V_PERR_IDMA2IMSG_FIFO1(x) ((x) << S_PERR_IDMA2IMSG_FIFO1)
1171 #define F_PERR_IDMA2IMSG_FIFO1    V_PERR_IDMA2IMSG_FIFO1(1U)
1172 
1173 #define S_PERR_IDMA2IMSG_FIFO0    24
1174 #define V_PERR_IDMA2IMSG_FIFO0(x) ((x) << S_PERR_IDMA2IMSG_FIFO0)
1175 #define F_PERR_IDMA2IMSG_FIFO0    V_PERR_IDMA2IMSG_FIFO0(1U)
1176 
1177 #define S_PERR_HEADERSPLIT_FIFO1    23
1178 #define V_PERR_HEADERSPLIT_FIFO1(x) ((x) << S_PERR_HEADERSPLIT_FIFO1)
1179 #define F_PERR_HEADERSPLIT_FIFO1    V_PERR_HEADERSPLIT_FIFO1(1U)
1180 
1181 #define S_PERR_HEADERSPLIT_FIFO0    22
1182 #define V_PERR_HEADERSPLIT_FIFO0(x) ((x) << S_PERR_HEADERSPLIT_FIFO0)
1183 #define F_PERR_HEADERSPLIT_FIFO0    V_PERR_HEADERSPLIT_FIFO0(1U)
1184 
1185 #define S_PERR_ESWITCH_FIFO3    21
1186 #define V_PERR_ESWITCH_FIFO3(x) ((x) << S_PERR_ESWITCH_FIFO3)
1187 #define F_PERR_ESWITCH_FIFO3    V_PERR_ESWITCH_FIFO3(1U)
1188 
1189 #define S_PERR_ESWITCH_FIFO2    20
1190 #define V_PERR_ESWITCH_FIFO2(x) ((x) << S_PERR_ESWITCH_FIFO2)
1191 #define F_PERR_ESWITCH_FIFO2    V_PERR_ESWITCH_FIFO2(1U)
1192 
1193 #define S_PERR_ESWITCH_FIFO1    19
1194 #define V_PERR_ESWITCH_FIFO1(x) ((x) << S_PERR_ESWITCH_FIFO1)
1195 #define F_PERR_ESWITCH_FIFO1    V_PERR_ESWITCH_FIFO1(1U)
1196 
1197 #define S_PERR_ESWITCH_FIFO0    18
1198 #define V_PERR_ESWITCH_FIFO0(x) ((x) << S_PERR_ESWITCH_FIFO0)
1199 #define F_PERR_ESWITCH_FIFO0    V_PERR_ESWITCH_FIFO0(1U)
1200 
1201 #define S_PERR_PC_DBP1    17
1202 #define V_PERR_PC_DBP1(x) ((x) << S_PERR_PC_DBP1)
1203 #define F_PERR_PC_DBP1    V_PERR_PC_DBP1(1U)
1204 
1205 #define S_PERR_PC_DBP0    16
1206 #define V_PERR_PC_DBP0(x) ((x) << S_PERR_PC_DBP0)
1207 #define F_PERR_PC_DBP0    V_PERR_PC_DBP0(1U)
1208 
1209 #define S_PERR_IMSG_OB_FIFO    15
1210 #define V_PERR_IMSG_OB_FIFO(x) ((x) << S_PERR_IMSG_OB_FIFO)
1211 #define F_PERR_IMSG_OB_FIFO    V_PERR_IMSG_OB_FIFO(1U)
1212 
1213 #define S_PERR_CONM_SRAM    14
1214 #define V_PERR_CONM_SRAM(x) ((x) << S_PERR_CONM_SRAM)
1215 #define F_PERR_CONM_SRAM    V_PERR_CONM_SRAM(1U)
1216 
1217 #define S_PERR_PC_MC_RSP    13
1218 #define V_PERR_PC_MC_RSP(x) ((x) << S_PERR_PC_MC_RSP)
1219 #define F_PERR_PC_MC_RSP    V_PERR_PC_MC_RSP(1U)
1220 
1221 #define S_PERR_ISW_IDMA0_FIFO    12
1222 #define V_PERR_ISW_IDMA0_FIFO(x) ((x) << S_PERR_ISW_IDMA0_FIFO)
1223 #define F_PERR_ISW_IDMA0_FIFO    V_PERR_ISW_IDMA0_FIFO(1U)
1224 
1225 #define S_PERR_ISW_IDMA1_FIFO    11
1226 #define V_PERR_ISW_IDMA1_FIFO(x) ((x) << S_PERR_ISW_IDMA1_FIFO)
1227 #define F_PERR_ISW_IDMA1_FIFO    V_PERR_ISW_IDMA1_FIFO(1U)
1228 
1229 #define S_PERR_ISW_DBP_FIFO    10
1230 #define V_PERR_ISW_DBP_FIFO(x) ((x) << S_PERR_ISW_DBP_FIFO)
1231 #define F_PERR_ISW_DBP_FIFO    V_PERR_ISW_DBP_FIFO(1U)
1232 
1233 #define S_PERR_ISW_GTS_FIFO    9
1234 #define V_PERR_ISW_GTS_FIFO(x) ((x) << S_PERR_ISW_GTS_FIFO)
1235 #define F_PERR_ISW_GTS_FIFO    V_PERR_ISW_GTS_FIFO(1U)
1236 
1237 #define S_PERR_ITP_EVR    8
1238 #define V_PERR_ITP_EVR(x) ((x) << S_PERR_ITP_EVR)
1239 #define F_PERR_ITP_EVR    V_PERR_ITP_EVR(1U)
1240 
1241 #define S_PERR_FLM_CNTXMEM    7
1242 #define V_PERR_FLM_CNTXMEM(x) ((x) << S_PERR_FLM_CNTXMEM)
1243 #define F_PERR_FLM_CNTXMEM    V_PERR_FLM_CNTXMEM(1U)
1244 
1245 #define S_PERR_FLM_L1CACHE    6
1246 #define V_PERR_FLM_L1CACHE(x) ((x) << S_PERR_FLM_L1CACHE)
1247 #define F_PERR_FLM_L1CACHE    V_PERR_FLM_L1CACHE(1U)
1248 
1249 #define S_PERR_DBP_HINT_FIFO    5
1250 #define V_PERR_DBP_HINT_FIFO(x) ((x) << S_PERR_DBP_HINT_FIFO)
1251 #define F_PERR_DBP_HINT_FIFO    V_PERR_DBP_HINT_FIFO(1U)
1252 
1253 #define S_PERR_DBP_HP_FIFO    4
1254 #define V_PERR_DBP_HP_FIFO(x) ((x) << S_PERR_DBP_HP_FIFO)
1255 #define F_PERR_DBP_HP_FIFO    V_PERR_DBP_HP_FIFO(1U)
1256 
1257 #define S_PERR_DBP_LP_FIFO    3
1258 #define V_PERR_DBP_LP_FIFO(x) ((x) << S_PERR_DBP_LP_FIFO)
1259 #define F_PERR_DBP_LP_FIFO    V_PERR_DBP_LP_FIFO(1U)
1260 
1261 #define S_PERR_ING_CTXT_CACHE    2
1262 #define V_PERR_ING_CTXT_CACHE(x) ((x) << S_PERR_ING_CTXT_CACHE)
1263 #define F_PERR_ING_CTXT_CACHE    V_PERR_ING_CTXT_CACHE(1U)
1264 
1265 #define S_PERR_EGR_CTXT_CACHE    1
1266 #define V_PERR_EGR_CTXT_CACHE(x) ((x) << S_PERR_EGR_CTXT_CACHE)
1267 #define F_PERR_EGR_CTXT_CACHE    V_PERR_EGR_CTXT_CACHE(1U)
1268 
1269 #define S_PERR_BASE_SIZE    0
1270 #define V_PERR_BASE_SIZE(x) ((x) << S_PERR_BASE_SIZE)
1271 #define F_PERR_BASE_SIZE    V_PERR_BASE_SIZE(1U)
1272 
1273 #define S_PERR_DBP_HINT_FL_FIFO    24
1274 #define V_PERR_DBP_HINT_FL_FIFO(x) ((x) << S_PERR_DBP_HINT_FL_FIFO)
1275 #define F_PERR_DBP_HINT_FL_FIFO    V_PERR_DBP_HINT_FL_FIFO(1U)
1276 
1277 #define S_PERR_EGR_DBP_TX_COAL    23
1278 #define V_PERR_EGR_DBP_TX_COAL(x) ((x) << S_PERR_EGR_DBP_TX_COAL)
1279 #define F_PERR_EGR_DBP_TX_COAL    V_PERR_EGR_DBP_TX_COAL(1U)
1280 
1281 #define S_PERR_DBP_FL_FIFO    22
1282 #define V_PERR_DBP_FL_FIFO(x) ((x) << S_PERR_DBP_FL_FIFO)
1283 #define F_PERR_DBP_FL_FIFO    V_PERR_DBP_FL_FIFO(1U)
1284 
1285 #define S_PERR_PC_DBP2    15
1286 #define V_PERR_PC_DBP2(x) ((x) << S_PERR_PC_DBP2)
1287 #define F_PERR_PC_DBP2    V_PERR_PC_DBP2(1U)
1288 
1289 #define S_DEQ_LL_PERR    21
1290 #define V_DEQ_LL_PERR(x) ((x) << S_DEQ_LL_PERR)
1291 #define F_DEQ_LL_PERR    V_DEQ_LL_PERR(1U)
1292 
1293 #define S_ENQ_PERR    20
1294 #define V_ENQ_PERR(x) ((x) << S_ENQ_PERR)
1295 #define F_ENQ_PERR    V_ENQ_PERR(1U)
1296 
1297 #define S_DEQ_OUT_PERR    19
1298 #define V_DEQ_OUT_PERR(x) ((x) << S_DEQ_OUT_PERR)
1299 #define F_DEQ_OUT_PERR    V_DEQ_OUT_PERR(1U)
1300 
1301 #define S_BUF_PERR    18
1302 #define V_BUF_PERR(x) ((x) << S_BUF_PERR)
1303 #define F_BUF_PERR    V_BUF_PERR(1U)
1304 
1305 #define S_PERR_DB_FIFO    3
1306 #define V_PERR_DB_FIFO(x) ((x) << S_PERR_DB_FIFO)
1307 #define F_PERR_DB_FIFO    V_PERR_DB_FIFO(1U)
1308 
1309 #define S_TF_FIFO_PERR    24
1310 #define V_TF_FIFO_PERR(x) ((x) << S_TF_FIFO_PERR)
1311 #define F_TF_FIFO_PERR    V_TF_FIFO_PERR(1U)
1312 
1313 #define S_PERR_ISW_IDMA3_FIFO    15
1314 #define V_PERR_ISW_IDMA3_FIFO(x) ((x) << S_PERR_ISW_IDMA3_FIFO)
1315 #define F_PERR_ISW_IDMA3_FIFO    V_PERR_ISW_IDMA3_FIFO(1U)
1316 
1317 #define S_PERR_ISW_IDMA2_FIFO    13
1318 #define V_PERR_ISW_IDMA2_FIFO(x) ((x) << S_PERR_ISW_IDMA2_FIFO)
1319 #define F_PERR_ISW_IDMA2_FIFO    V_PERR_ISW_IDMA2_FIFO(1U)
1320 
1321 #define S_SGE_IPP_FIFO_PERR    5
1322 #define V_SGE_IPP_FIFO_PERR(x) ((x) << S_SGE_IPP_FIFO_PERR)
1323 #define F_SGE_IPP_FIFO_PERR    V_SGE_IPP_FIFO_PERR(1U)
1324 
1325 #define A_SGE_INT_ENABLE2 0x1034
1326 #define A_SGE_PERR_ENABLE2 0x1038
1327 #define A_SGE_INT_CAUSE3 0x103c
1328 
1329 #define S_ERR_FLM_DBP    31
1330 #define V_ERR_FLM_DBP(x) ((x) << S_ERR_FLM_DBP)
1331 #define F_ERR_FLM_DBP    V_ERR_FLM_DBP(1U)
1332 
1333 #define S_ERR_FLM_IDMA1    30
1334 #define V_ERR_FLM_IDMA1(x) ((x) << S_ERR_FLM_IDMA1)
1335 #define F_ERR_FLM_IDMA1    V_ERR_FLM_IDMA1(1U)
1336 
1337 #define S_ERR_FLM_IDMA0    29
1338 #define V_ERR_FLM_IDMA0(x) ((x) << S_ERR_FLM_IDMA0)
1339 #define F_ERR_FLM_IDMA0    V_ERR_FLM_IDMA0(1U)
1340 
1341 #define S_ERR_FLM_HINT    28
1342 #define V_ERR_FLM_HINT(x) ((x) << S_ERR_FLM_HINT)
1343 #define F_ERR_FLM_HINT    V_ERR_FLM_HINT(1U)
1344 
1345 #define S_ERR_PCIE_ERROR3    27
1346 #define V_ERR_PCIE_ERROR3(x) ((x) << S_ERR_PCIE_ERROR3)
1347 #define F_ERR_PCIE_ERROR3    V_ERR_PCIE_ERROR3(1U)
1348 
1349 #define S_ERR_PCIE_ERROR2    26
1350 #define V_ERR_PCIE_ERROR2(x) ((x) << S_ERR_PCIE_ERROR2)
1351 #define F_ERR_PCIE_ERROR2    V_ERR_PCIE_ERROR2(1U)
1352 
1353 #define S_ERR_PCIE_ERROR1    25
1354 #define V_ERR_PCIE_ERROR1(x) ((x) << S_ERR_PCIE_ERROR1)
1355 #define F_ERR_PCIE_ERROR1    V_ERR_PCIE_ERROR1(1U)
1356 
1357 #define S_ERR_PCIE_ERROR0    24
1358 #define V_ERR_PCIE_ERROR0(x) ((x) << S_ERR_PCIE_ERROR0)
1359 #define F_ERR_PCIE_ERROR0    V_ERR_PCIE_ERROR0(1U)
1360 
1361 #define S_ERR_TIMER_ABOVE_MAX_QID    23
1362 #define V_ERR_TIMER_ABOVE_MAX_QID(x) ((x) << S_ERR_TIMER_ABOVE_MAX_QID)
1363 #define F_ERR_TIMER_ABOVE_MAX_QID    V_ERR_TIMER_ABOVE_MAX_QID(1U)
1364 
1365 #define S_ERR_CPL_EXCEED_IQE_SIZE    22
1366 #define V_ERR_CPL_EXCEED_IQE_SIZE(x) ((x) << S_ERR_CPL_EXCEED_IQE_SIZE)
1367 #define F_ERR_CPL_EXCEED_IQE_SIZE    V_ERR_CPL_EXCEED_IQE_SIZE(1U)
1368 
1369 #define S_ERR_INVALID_CIDX_INC    21
1370 #define V_ERR_INVALID_CIDX_INC(x) ((x) << S_ERR_INVALID_CIDX_INC)
1371 #define F_ERR_INVALID_CIDX_INC    V_ERR_INVALID_CIDX_INC(1U)
1372 
1373 #define S_ERR_ITP_TIME_PAUSED    20
1374 #define V_ERR_ITP_TIME_PAUSED(x) ((x) << S_ERR_ITP_TIME_PAUSED)
1375 #define F_ERR_ITP_TIME_PAUSED    V_ERR_ITP_TIME_PAUSED(1U)
1376 
1377 #define S_ERR_CPL_OPCODE_0    19
1378 #define V_ERR_CPL_OPCODE_0(x) ((x) << S_ERR_CPL_OPCODE_0)
1379 #define F_ERR_CPL_OPCODE_0    V_ERR_CPL_OPCODE_0(1U)
1380 
1381 #define S_ERR_DROPPED_DB    18
1382 #define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB)
1383 #define F_ERR_DROPPED_DB    V_ERR_DROPPED_DB(1U)
1384 
1385 #define S_ERR_DATA_CPL_ON_HIGH_QID1    17
1386 #define V_ERR_DATA_CPL_ON_HIGH_QID1(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID1)
1387 #define F_ERR_DATA_CPL_ON_HIGH_QID1    V_ERR_DATA_CPL_ON_HIGH_QID1(1U)
1388 
1389 #define S_ERR_DATA_CPL_ON_HIGH_QID0    16
1390 #define V_ERR_DATA_CPL_ON_HIGH_QID0(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID0)
1391 #define F_ERR_DATA_CPL_ON_HIGH_QID0    V_ERR_DATA_CPL_ON_HIGH_QID0(1U)
1392 
1393 #define S_ERR_BAD_DB_PIDX3    15
1394 #define V_ERR_BAD_DB_PIDX3(x) ((x) << S_ERR_BAD_DB_PIDX3)
1395 #define F_ERR_BAD_DB_PIDX3    V_ERR_BAD_DB_PIDX3(1U)
1396 
1397 #define S_ERR_BAD_DB_PIDX2    14
1398 #define V_ERR_BAD_DB_PIDX2(x) ((x) << S_ERR_BAD_DB_PIDX2)
1399 #define F_ERR_BAD_DB_PIDX2    V_ERR_BAD_DB_PIDX2(1U)
1400 
1401 #define S_ERR_BAD_DB_PIDX1    13
1402 #define V_ERR_BAD_DB_PIDX1(x) ((x) << S_ERR_BAD_DB_PIDX1)
1403 #define F_ERR_BAD_DB_PIDX1    V_ERR_BAD_DB_PIDX1(1U)
1404 
1405 #define S_ERR_BAD_DB_PIDX0    12
1406 #define V_ERR_BAD_DB_PIDX0(x) ((x) << S_ERR_BAD_DB_PIDX0)
1407 #define F_ERR_BAD_DB_PIDX0    V_ERR_BAD_DB_PIDX0(1U)
1408 
1409 #define S_ERR_ING_PCIE_CHAN    11
1410 #define V_ERR_ING_PCIE_CHAN(x) ((x) << S_ERR_ING_PCIE_CHAN)
1411 #define F_ERR_ING_PCIE_CHAN    V_ERR_ING_PCIE_CHAN(1U)
1412 
1413 #define S_ERR_ING_CTXT_PRIO    10
1414 #define V_ERR_ING_CTXT_PRIO(x) ((x) << S_ERR_ING_CTXT_PRIO)
1415 #define F_ERR_ING_CTXT_PRIO    V_ERR_ING_CTXT_PRIO(1U)
1416 
1417 #define S_ERR_EGR_CTXT_PRIO    9
1418 #define V_ERR_EGR_CTXT_PRIO(x) ((x) << S_ERR_EGR_CTXT_PRIO)
1419 #define F_ERR_EGR_CTXT_PRIO    V_ERR_EGR_CTXT_PRIO(1U)
1420 
1421 #define S_DBFIFO_HP_INT    8
1422 #define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT)
1423 #define F_DBFIFO_HP_INT    V_DBFIFO_HP_INT(1U)
1424 
1425 #define S_DBFIFO_LP_INT    7
1426 #define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT)
1427 #define F_DBFIFO_LP_INT    V_DBFIFO_LP_INT(1U)
1428 
1429 #define S_REG_ADDRESS_ERR    6
1430 #define V_REG_ADDRESS_ERR(x) ((x) << S_REG_ADDRESS_ERR)
1431 #define F_REG_ADDRESS_ERR    V_REG_ADDRESS_ERR(1U)
1432 
1433 #define S_INGRESS_SIZE_ERR    5
1434 #define V_INGRESS_SIZE_ERR(x) ((x) << S_INGRESS_SIZE_ERR)
1435 #define F_INGRESS_SIZE_ERR    V_INGRESS_SIZE_ERR(1U)
1436 
1437 #define S_EGRESS_SIZE_ERR    4
1438 #define V_EGRESS_SIZE_ERR(x) ((x) << S_EGRESS_SIZE_ERR)
1439 #define F_EGRESS_SIZE_ERR    V_EGRESS_SIZE_ERR(1U)
1440 
1441 #define S_ERR_INV_CTXT3    3
1442 #define V_ERR_INV_CTXT3(x) ((x) << S_ERR_INV_CTXT3)
1443 #define F_ERR_INV_CTXT3    V_ERR_INV_CTXT3(1U)
1444 
1445 #define S_ERR_INV_CTXT2    2
1446 #define V_ERR_INV_CTXT2(x) ((x) << S_ERR_INV_CTXT2)
1447 #define F_ERR_INV_CTXT2    V_ERR_INV_CTXT2(1U)
1448 
1449 #define S_ERR_INV_CTXT1    1
1450 #define V_ERR_INV_CTXT1(x) ((x) << S_ERR_INV_CTXT1)
1451 #define F_ERR_INV_CTXT1    V_ERR_INV_CTXT1(1U)
1452 
1453 #define S_ERR_INV_CTXT0    0
1454 #define V_ERR_INV_CTXT0(x) ((x) << S_ERR_INV_CTXT0)
1455 #define F_ERR_INV_CTXT0    V_ERR_INV_CTXT0(1U)
1456 
1457 #define S_DBP_TBUF_FULL    8
1458 #define V_DBP_TBUF_FULL(x) ((x) << S_DBP_TBUF_FULL)
1459 #define F_DBP_TBUF_FULL    V_DBP_TBUF_FULL(1U)
1460 
1461 #define S_FATAL_WRE_LEN    7
1462 #define V_FATAL_WRE_LEN(x) ((x) << S_FATAL_WRE_LEN)
1463 #define F_FATAL_WRE_LEN    V_FATAL_WRE_LEN(1U)
1464 
1465 #define A_SGE_INT_ENABLE3 0x1040
1466 #define A_SGE_FL_BUFFER_SIZE0 0x1044
1467 
1468 #define S_SIZE    4
1469 #define CXGBE_M_SIZE    0xfffffffU
1470 #define V_SIZE(x) ((x) << S_SIZE)
1471 #define G_SIZE(x) (((x) >> S_SIZE) & CXGBE_M_SIZE)
1472 
1473 #define S_T6_SIZE    4
1474 #define M_T6_SIZE    0xfffffU
1475 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1476 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1477 
1478 #define A_SGE_FL_BUFFER_SIZE1 0x1048
1479 #define A_SGE_FL_BUFFER_SIZE2 0x104c
1480 #define A_SGE_FL_BUFFER_SIZE3 0x1050
1481 #define A_SGE_FL_BUFFER_SIZE4 0x1054
1482 #define A_SGE_FL_BUFFER_SIZE5 0x1058
1483 #define A_SGE_FL_BUFFER_SIZE6 0x105c
1484 #define A_SGE_FL_BUFFER_SIZE7 0x1060
1485 #define A_SGE_FL_BUFFER_SIZE8 0x1064
1486 #define A_SGE_FL_BUFFER_SIZE9 0x1068
1487 #define A_SGE_FL_BUFFER_SIZE10 0x106c
1488 #define A_SGE_FL_BUFFER_SIZE11 0x1070
1489 #define A_SGE_FL_BUFFER_SIZE12 0x1074
1490 #define A_SGE_FL_BUFFER_SIZE13 0x1078
1491 #define A_SGE_FL_BUFFER_SIZE14 0x107c
1492 #define A_SGE_FL_BUFFER_SIZE15 0x1080
1493 #define A_SGE_DBQ_CTXT_BADDR 0x1084
1494 
1495 #define S_BASEADDR    3
1496 #define M_BASEADDR    0x1fffffffU
1497 #define V_BASEADDR(x) ((x) << S_BASEADDR)
1498 #define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR)
1499 
1500 #define A_SGE_IMSG_CTXT_BADDR 0x1088
1501 #define A_SGE_FLM_CACHE_BADDR 0x108c
1502 #define A_SGE_FLM_CFG 0x1090
1503 
1504 #define S_OPMODE    26
1505 #define M_OPMODE    0x3fU
1506 #define V_OPMODE(x) ((x) << S_OPMODE)
1507 #define G_OPMODE(x) (((x) >> S_OPMODE) & M_OPMODE)
1508 
1509 #define S_NOHDR    18
1510 #define V_NOHDR(x) ((x) << S_NOHDR)
1511 #define F_NOHDR    V_NOHDR(1U)
1512 
1513 #define S_CACHEPTRCNT    16
1514 #define M_CACHEPTRCNT    0x3U
1515 #define V_CACHEPTRCNT(x) ((x) << S_CACHEPTRCNT)
1516 #define G_CACHEPTRCNT(x) (((x) >> S_CACHEPTRCNT) & M_CACHEPTRCNT)
1517 
1518 #define S_EDRAMPTRCNT    14
1519 #define M_EDRAMPTRCNT    0x3U
1520 #define V_EDRAMPTRCNT(x) ((x) << S_EDRAMPTRCNT)
1521 #define G_EDRAMPTRCNT(x) (((x) >> S_EDRAMPTRCNT) & M_EDRAMPTRCNT)
1522 
1523 #define S_HDRSTARTFLQ    11
1524 #define M_HDRSTARTFLQ    0x7U
1525 #define V_HDRSTARTFLQ(x) ((x) << S_HDRSTARTFLQ)
1526 #define G_HDRSTARTFLQ(x) (((x) >> S_HDRSTARTFLQ) & M_HDRSTARTFLQ)
1527 
1528 #define S_FETCHTHRESH    6
1529 #define M_FETCHTHRESH    0x1fU
1530 #define V_FETCHTHRESH(x) ((x) << S_FETCHTHRESH)
1531 #define G_FETCHTHRESH(x) (((x) >> S_FETCHTHRESH) & M_FETCHTHRESH)
1532 
1533 #define S_CREDITCNT    4
1534 #define M_CREDITCNT    0x3U
1535 #define V_CREDITCNT(x) ((x) << S_CREDITCNT)
1536 #define G_CREDITCNT(x) (((x) >> S_CREDITCNT) & M_CREDITCNT)
1537 
1538 #define S_NOEDRAM    0
1539 #define V_NOEDRAM(x) ((x) << S_NOEDRAM)
1540 #define F_NOEDRAM    V_NOEDRAM(1U)
1541 
1542 #define S_CREDITCNTPACKING    2
1543 #define M_CREDITCNTPACKING    0x3U
1544 #define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING)
1545 #define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING)
1546 
1547 #define S_NULLPTR    20
1548 #define M_NULLPTR    0xfU
1549 #define V_NULLPTR(x) ((x) << S_NULLPTR)
1550 #define G_NULLPTR(x) (((x) >> S_NULLPTR) & M_NULLPTR)
1551 
1552 #define S_NULLPTREN    19
1553 #define V_NULLPTREN(x) ((x) << S_NULLPTREN)
1554 #define F_NULLPTREN    V_NULLPTREN(1U)
1555 
1556 #define S_HDRSTARTFLQ4K    1
1557 #define V_HDRSTARTFLQ4K(x) ((x) << S_HDRSTARTFLQ4K)
1558 #define F_HDRSTARTFLQ4K    V_HDRSTARTFLQ4K(1U)
1559 
1560 #define A_SGE_CONM_CTRL 0x1094
1561 
1562 #define S_EGRTHRESHOLD    8
1563 #define M_EGRTHRESHOLD    0x3fU
1564 #define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD)
1565 #define G_EGRTHRESHOLD(x) (((x) >> S_EGRTHRESHOLD) & M_EGRTHRESHOLD)
1566 
1567 #define S_INGTHRESHOLD    2
1568 #define M_INGTHRESHOLD    0x3fU
1569 #define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD)
1570 #define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD)
1571 
1572 #define S_MPS_ENABLE    1
1573 #define V_MPS_ENABLE(x) ((x) << S_MPS_ENABLE)
1574 #define F_MPS_ENABLE    V_MPS_ENABLE(1U)
1575 
1576 #define S_TP_ENABLE    0
1577 #define V_TP_ENABLE(x) ((x) << S_TP_ENABLE)
1578 #define F_TP_ENABLE    V_TP_ENABLE(1U)
1579 
1580 #define S_EGRTHRESHOLDPACKING    14
1581 #define M_EGRTHRESHOLDPACKING    0x3fU
1582 #define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING)
1583 #define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & M_EGRTHRESHOLDPACKING)
1584 
1585 #define S_T6_EGRTHRESHOLDPACKING    16
1586 #define M_T6_EGRTHRESHOLDPACKING    0xffU
1587 #define V_T6_EGRTHRESHOLDPACKING(x) ((x) << S_T6_EGRTHRESHOLDPACKING)
1588 #define G_T6_EGRTHRESHOLDPACKING(x) (((x) >> S_T6_EGRTHRESHOLDPACKING) & M_T6_EGRTHRESHOLDPACKING)
1589 
1590 #define S_T6_EGRTHRESHOLD    8
1591 #define M_T6_EGRTHRESHOLD    0xffU
1592 #define V_T6_EGRTHRESHOLD(x) ((x) << S_T6_EGRTHRESHOLD)
1593 #define G_T6_EGRTHRESHOLD(x) (((x) >> S_T6_EGRTHRESHOLD) & M_T6_EGRTHRESHOLD)
1594 
1595 #define A_SGE_TIMESTAMP_LO 0x1098
1596 #define A_SGE_TIMESTAMP_HI 0x109c
1597 
1598 #define S_TSOP    28
1599 #define M_TSOP    0x3U
1600 #define V_TSOP(x) ((x) << S_TSOP)
1601 #define G_TSOP(x) (((x) >> S_TSOP) & M_TSOP)
1602 
1603 #define S_TSVAL    0
1604 #define M_TSVAL    0xfffffffU
1605 #define V_TSVAL(x) ((x) << S_TSVAL)
1606 #define G_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL)
1607 
1608 #define A_SGE_INGRESS_RX_THRESHOLD 0x10a0
1609 
1610 #define S_THRESHOLD_0    24
1611 #define M_THRESHOLD_0    0x3fU
1612 #define V_THRESHOLD_0(x) ((x) << S_THRESHOLD_0)
1613 #define G_THRESHOLD_0(x) (((x) >> S_THRESHOLD_0) & M_THRESHOLD_0)
1614 
1615 #define S_THRESHOLD_1    16
1616 #define M_THRESHOLD_1    0x3fU
1617 #define V_THRESHOLD_1(x) ((x) << S_THRESHOLD_1)
1618 #define G_THRESHOLD_1(x) (((x) >> S_THRESHOLD_1) & M_THRESHOLD_1)
1619 
1620 #define S_THRESHOLD_2    8
1621 #define M_THRESHOLD_2    0x3fU
1622 #define V_THRESHOLD_2(x) ((x) << S_THRESHOLD_2)
1623 #define G_THRESHOLD_2(x) (((x) >> S_THRESHOLD_2) & M_THRESHOLD_2)
1624 
1625 #define S_THRESHOLD_3    0
1626 #define M_THRESHOLD_3    0x3fU
1627 #define V_THRESHOLD_3(x) ((x) << S_THRESHOLD_3)
1628 #define G_THRESHOLD_3(x) (((x) >> S_THRESHOLD_3) & M_THRESHOLD_3)
1629 
1630 #define A_SGE_DBFIFO_STATUS 0x10a4
1631 
1632 #define S_HP_INT_THRESH    28
1633 #define M_HP_INT_THRESH    0xfU
1634 #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
1635 #define G_HP_INT_THRESH(x) (((x) >> S_HP_INT_THRESH) & M_HP_INT_THRESH)
1636 
1637 #define S_HP_COUNT    16
1638 #define M_HP_COUNT    0x7ffU
1639 #define V_HP_COUNT(x) ((x) << S_HP_COUNT)
1640 #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
1641 
1642 #define S_LP_INT_THRESH    12
1643 #define M_LP_INT_THRESH    0xfU
1644 #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
1645 #define G_LP_INT_THRESH(x) (((x) >> S_LP_INT_THRESH) & M_LP_INT_THRESH)
1646 
1647 #define S_LP_COUNT    0
1648 #define M_LP_COUNT    0x7ffU
1649 #define V_LP_COUNT(x) ((x) << S_LP_COUNT)
1650 #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
1651 
1652 #define S_BAR2VALID    31
1653 #define V_BAR2VALID(x) ((x) << S_BAR2VALID)
1654 #define F_BAR2VALID    V_BAR2VALID(1U)
1655 
1656 #define S_BAR2FULL    30
1657 #define V_BAR2FULL(x) ((x) << S_BAR2FULL)
1658 #define F_BAR2FULL    V_BAR2FULL(1U)
1659 
1660 #define S_LP_INT_THRESH_T5    18
1661 #define M_LP_INT_THRESH_T5    0xfffU
1662 #define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
1663 #define G_LP_INT_THRESH_T5(x) (((x) >> S_LP_INT_THRESH_T5) & M_LP_INT_THRESH_T5)
1664 
1665 #define S_LP_COUNT_T5    0
1666 #define M_LP_COUNT_T5    0x3ffffU
1667 #define V_LP_COUNT_T5(x) ((x) << S_LP_COUNT_T5)
1668 #define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT_T5) & M_LP_COUNT_T5)
1669 
1670 #define S_VFIFO_CNT    15
1671 #define M_VFIFO_CNT    0x1ffffU
1672 #define V_VFIFO_CNT(x) ((x) << S_VFIFO_CNT)
1673 #define G_VFIFO_CNT(x) (((x) >> S_VFIFO_CNT) & M_VFIFO_CNT)
1674 
1675 #define S_COAL_CTL_FIFO_CNT    8
1676 #define M_COAL_CTL_FIFO_CNT    0x3fU
1677 #define V_COAL_CTL_FIFO_CNT(x) ((x) << S_COAL_CTL_FIFO_CNT)
1678 #define G_COAL_CTL_FIFO_CNT(x) (((x) >> S_COAL_CTL_FIFO_CNT) & M_COAL_CTL_FIFO_CNT)
1679 
1680 #define S_MERGE_FIFO_CNT    0
1681 #define M_MERGE_FIFO_CNT    0x3fU
1682 #define V_MERGE_FIFO_CNT(x) ((x) << S_MERGE_FIFO_CNT)
1683 #define G_MERGE_FIFO_CNT(x) (((x) >> S_MERGE_FIFO_CNT) & M_MERGE_FIFO_CNT)
1684 
1685 #define A_SGE_DOORBELL_CONTROL 0x10a8
1686 
1687 #define S_HINTDEPTHCTL    27
1688 #define M_HINTDEPTHCTL    0x1fU
1689 #define V_HINTDEPTHCTL(x) ((x) << S_HINTDEPTHCTL)
1690 #define G_HINTDEPTHCTL(x) (((x) >> S_HINTDEPTHCTL) & M_HINTDEPTHCTL)
1691 
1692 #define S_NOCOALESCE    26
1693 #define V_NOCOALESCE(x) ((x) << S_NOCOALESCE)
1694 #define F_NOCOALESCE    V_NOCOALESCE(1U)
1695 
1696 #define S_HP_WEIGHT    24
1697 #define M_HP_WEIGHT    0x3U
1698 #define V_HP_WEIGHT(x) ((x) << S_HP_WEIGHT)
1699 #define G_HP_WEIGHT(x) (((x) >> S_HP_WEIGHT) & M_HP_WEIGHT)
1700 
1701 #define S_HP_DISABLE    23
1702 #define V_HP_DISABLE(x) ((x) << S_HP_DISABLE)
1703 #define F_HP_DISABLE    V_HP_DISABLE(1U)
1704 
1705 #define S_FORCEUSERDBTOLP    22
1706 #define V_FORCEUSERDBTOLP(x) ((x) << S_FORCEUSERDBTOLP)
1707 #define F_FORCEUSERDBTOLP    V_FORCEUSERDBTOLP(1U)
1708 
1709 #define S_FORCEVFPF0DBTOLP    21
1710 #define V_FORCEVFPF0DBTOLP(x) ((x) << S_FORCEVFPF0DBTOLP)
1711 #define F_FORCEVFPF0DBTOLP    V_FORCEVFPF0DBTOLP(1U)
1712 
1713 #define S_FORCEVFPF1DBTOLP    20
1714 #define V_FORCEVFPF1DBTOLP(x) ((x) << S_FORCEVFPF1DBTOLP)
1715 #define F_FORCEVFPF1DBTOLP    V_FORCEVFPF1DBTOLP(1U)
1716 
1717 #define S_FORCEVFPF2DBTOLP    19
1718 #define V_FORCEVFPF2DBTOLP(x) ((x) << S_FORCEVFPF2DBTOLP)
1719 #define F_FORCEVFPF2DBTOLP    V_FORCEVFPF2DBTOLP(1U)
1720 
1721 #define S_FORCEVFPF3DBTOLP    18
1722 #define V_FORCEVFPF3DBTOLP(x) ((x) << S_FORCEVFPF3DBTOLP)
1723 #define F_FORCEVFPF3DBTOLP    V_FORCEVFPF3DBTOLP(1U)
1724 
1725 #define S_FORCEVFPF4DBTOLP    17
1726 #define V_FORCEVFPF4DBTOLP(x) ((x) << S_FORCEVFPF4DBTOLP)
1727 #define F_FORCEVFPF4DBTOLP    V_FORCEVFPF4DBTOLP(1U)
1728 
1729 #define S_FORCEVFPF5DBTOLP    16
1730 #define V_FORCEVFPF5DBTOLP(x) ((x) << S_FORCEVFPF5DBTOLP)
1731 #define F_FORCEVFPF5DBTOLP    V_FORCEVFPF5DBTOLP(1U)
1732 
1733 #define S_FORCEVFPF6DBTOLP    15
1734 #define V_FORCEVFPF6DBTOLP(x) ((x) << S_FORCEVFPF6DBTOLP)
1735 #define F_FORCEVFPF6DBTOLP    V_FORCEVFPF6DBTOLP(1U)
1736 
1737 #define S_FORCEVFPF7DBTOLP    14
1738 #define V_FORCEVFPF7DBTOLP(x) ((x) << S_FORCEVFPF7DBTOLP)
1739 #define F_FORCEVFPF7DBTOLP    V_FORCEVFPF7DBTOLP(1U)
1740 
1741 #define S_ENABLE_DROP    13
1742 #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
1743 #define F_ENABLE_DROP    V_ENABLE_DROP(1U)
1744 
1745 #define S_DROP_TIMEOUT    1
1746 #define M_DROP_TIMEOUT    0xfffU
1747 #define V_DROP_TIMEOUT(x) ((x) << S_DROP_TIMEOUT)
1748 #define G_DROP_TIMEOUT(x) (((x) >> S_DROP_TIMEOUT) & M_DROP_TIMEOUT)
1749 
1750 #define S_DROPPED_DB    0
1751 #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
1752 #define F_DROPPED_DB    V_DROPPED_DB(1U)
1753 
1754 #define S_T6_DROP_TIMEOUT    7
1755 #define M_T6_DROP_TIMEOUT    0x3fU
1756 #define V_T6_DROP_TIMEOUT(x) ((x) << S_T6_DROP_TIMEOUT)
1757 #define G_T6_DROP_TIMEOUT(x) (((x) >> S_T6_DROP_TIMEOUT) & M_T6_DROP_TIMEOUT)
1758 
1759 #define S_INVONDBSYNC    6
1760 #define V_INVONDBSYNC(x) ((x) << S_INVONDBSYNC)
1761 #define F_INVONDBSYNC    V_INVONDBSYNC(1U)
1762 
1763 #define S_INVONGTSSYNC    5
1764 #define V_INVONGTSSYNC(x) ((x) << S_INVONGTSSYNC)
1765 #define F_INVONGTSSYNC    V_INVONGTSSYNC(1U)
1766 
1767 #define S_DB_DBG_EN    4
1768 #define V_DB_DBG_EN(x) ((x) << S_DB_DBG_EN)
1769 #define F_DB_DBG_EN    V_DB_DBG_EN(1U)
1770 
1771 #define S_GTS_DBG_TIMER_REG    1
1772 #define M_GTS_DBG_TIMER_REG    0x7U
1773 #define V_GTS_DBG_TIMER_REG(x) ((x) << S_GTS_DBG_TIMER_REG)
1774 #define G_GTS_DBG_TIMER_REG(x) (((x) >> S_GTS_DBG_TIMER_REG) & M_GTS_DBG_TIMER_REG)
1775 
1776 #define S_GTS_DBG_EN    0
1777 #define V_GTS_DBG_EN(x) ((x) << S_GTS_DBG_EN)
1778 #define F_GTS_DBG_EN    V_GTS_DBG_EN(1U)
1779 
1780 #define A_SGE_DROPPED_DOORBELL 0x10ac
1781 #define A_SGE_DOORBELL_THROTTLE_CONTROL 0x10b0
1782 
1783 #define S_THROTTLE_COUNT    1
1784 #define M_THROTTLE_COUNT    0xfffU
1785 #define V_THROTTLE_COUNT(x) ((x) << S_THROTTLE_COUNT)
1786 #define G_THROTTLE_COUNT(x) (((x) >> S_THROTTLE_COUNT) & M_THROTTLE_COUNT)
1787 
1788 #define S_THROTTLE_ENABLE    0
1789 #define V_THROTTLE_ENABLE(x) ((x) << S_THROTTLE_ENABLE)
1790 #define F_THROTTLE_ENABLE    V_THROTTLE_ENABLE(1U)
1791 
1792 #define S_BAR2THROTTLECOUNT    16
1793 #define M_BAR2THROTTLECOUNT    0xffU
1794 #define V_BAR2THROTTLECOUNT(x) ((x) << S_BAR2THROTTLECOUNT)
1795 #define G_BAR2THROTTLECOUNT(x) (((x) >> S_BAR2THROTTLECOUNT) & M_BAR2THROTTLECOUNT)
1796 
1797 #define S_CLRCOALESCEDISABLE    15
1798 #define V_CLRCOALESCEDISABLE(x) ((x) << S_CLRCOALESCEDISABLE)
1799 #define F_CLRCOALESCEDISABLE    V_CLRCOALESCEDISABLE(1U)
1800 
1801 #define S_OPENBAR2GATEONCE    14
1802 #define V_OPENBAR2GATEONCE(x) ((x) << S_OPENBAR2GATEONCE)
1803 #define F_OPENBAR2GATEONCE    V_OPENBAR2GATEONCE(1U)
1804 
1805 #define S_FORCEOPENBAR2GATE    13
1806 #define V_FORCEOPENBAR2GATE(x) ((x) << S_FORCEOPENBAR2GATE)
1807 #define F_FORCEOPENBAR2GATE    V_FORCEOPENBAR2GATE(1U)
1808 
1809 #define A_SGE_ITP_CONTROL 0x10b4
1810 
1811 #define S_CRITICAL_TIME    10
1812 #define M_CRITICAL_TIME    0x7fffU
1813 #define V_CRITICAL_TIME(x) ((x) << S_CRITICAL_TIME)
1814 #define G_CRITICAL_TIME(x) (((x) >> S_CRITICAL_TIME) & M_CRITICAL_TIME)
1815 
1816 #define S_LL_EMPTY    4
1817 #define M_LL_EMPTY    0x3fU
1818 #define V_LL_EMPTY(x) ((x) << S_LL_EMPTY)
1819 #define G_LL_EMPTY(x) (((x) >> S_LL_EMPTY) & M_LL_EMPTY)
1820 
1821 #define S_LL_READ_WAIT_DISABLE    0
1822 #define V_LL_READ_WAIT_DISABLE(x) ((x) << S_LL_READ_WAIT_DISABLE)
1823 #define F_LL_READ_WAIT_DISABLE    V_LL_READ_WAIT_DISABLE(1U)
1824 
1825 #define S_TSCALE    28
1826 #define M_TSCALE    0xfU
1827 #define V_TSCALE(x) ((x) << S_TSCALE)
1828 #define G_TSCALE(x) (((x) >> S_TSCALE) & M_TSCALE)
1829 
1830 #define A_SGE_TIMER_VALUE_0_AND_1 0x10b8
1831 
1832 #define S_TIMERVALUE0    16
1833 #define M_TIMERVALUE0    0xffffU
1834 #define V_TIMERVALUE0(x) ((x) << S_TIMERVALUE0)
1835 #define G_TIMERVALUE0(x) (((x) >> S_TIMERVALUE0) & M_TIMERVALUE0)
1836 
1837 #define S_TIMERVALUE1    0
1838 #define M_TIMERVALUE1    0xffffU
1839 #define V_TIMERVALUE1(x) ((x) << S_TIMERVALUE1)
1840 #define G_TIMERVALUE1(x) (((x) >> S_TIMERVALUE1) & M_TIMERVALUE1)
1841 
1842 #define A_SGE_TIMER_VALUE_2_AND_3 0x10bc
1843 
1844 #define S_TIMERVALUE2    16
1845 #define M_TIMERVALUE2    0xffffU
1846 #define V_TIMERVALUE2(x) ((x) << S_TIMERVALUE2)
1847 #define G_TIMERVALUE2(x) (((x) >> S_TIMERVALUE2) & M_TIMERVALUE2)
1848 
1849 #define S_TIMERVALUE3    0
1850 #define M_TIMERVALUE3    0xffffU
1851 #define V_TIMERVALUE3(x) ((x) << S_TIMERVALUE3)
1852 #define G_TIMERVALUE3(x) (((x) >> S_TIMERVALUE3) & M_TIMERVALUE3)
1853 
1854 #define A_SGE_TIMER_VALUE_4_AND_5 0x10c0
1855 
1856 #define S_TIMERVALUE4    16
1857 #define M_TIMERVALUE4    0xffffU
1858 #define V_TIMERVALUE4(x) ((x) << S_TIMERVALUE4)
1859 #define G_TIMERVALUE4(x) (((x) >> S_TIMERVALUE4) & M_TIMERVALUE4)
1860 
1861 #define S_TIMERVALUE5    0
1862 #define M_TIMERVALUE5    0xffffU
1863 #define V_TIMERVALUE5(x) ((x) << S_TIMERVALUE5)
1864 #define G_TIMERVALUE5(x) (((x) >> S_TIMERVALUE5) & M_TIMERVALUE5)
1865 
1866 #define A_SGE_PD_RSP_CREDIT01 0x10c4
1867 
1868 #define S_RSPCREDITEN0    31
1869 #define V_RSPCREDITEN0(x) ((x) << S_RSPCREDITEN0)
1870 #define F_RSPCREDITEN0    V_RSPCREDITEN0(1U)
1871 
1872 #define S_MAXTAG0    24
1873 #define M_MAXTAG0    0x7fU
1874 #define V_MAXTAG0(x) ((x) << S_MAXTAG0)
1875 #define G_MAXTAG0(x) (((x) >> S_MAXTAG0) & M_MAXTAG0)
1876 
1877 #define S_MAXRSPCNT0    16
1878 #define M_MAXRSPCNT0    0xffU
1879 #define V_MAXRSPCNT0(x) ((x) << S_MAXRSPCNT0)
1880 #define G_MAXRSPCNT0(x) (((x) >> S_MAXRSPCNT0) & M_MAXRSPCNT0)
1881 
1882 #define S_RSPCREDITEN1    15
1883 #define V_RSPCREDITEN1(x) ((x) << S_RSPCREDITEN1)
1884 #define F_RSPCREDITEN1    V_RSPCREDITEN1(1U)
1885 
1886 #define S_MAXTAG1    8
1887 #define M_MAXTAG1    0x7fU
1888 #define V_MAXTAG1(x) ((x) << S_MAXTAG1)
1889 #define G_MAXTAG1(x) (((x) >> S_MAXTAG1) & M_MAXTAG1)
1890 
1891 #define S_MAXRSPCNT1    0
1892 #define M_MAXRSPCNT1    0xffU
1893 #define V_MAXRSPCNT1(x) ((x) << S_MAXRSPCNT1)
1894 #define G_MAXRSPCNT1(x) (((x) >> S_MAXRSPCNT1) & M_MAXRSPCNT1)
1895 
1896 #define A_SGE_GK_CONTROL 0x10c4
1897 
1898 #define S_EN_FLM_FIFTH    29
1899 #define V_EN_FLM_FIFTH(x) ((x) << S_EN_FLM_FIFTH)
1900 #define F_EN_FLM_FIFTH    V_EN_FLM_FIFTH(1U)
1901 
1902 #define S_FL_PROG_THRESH    20
1903 #define M_FL_PROG_THRESH    0x1ffU
1904 #define V_FL_PROG_THRESH(x) ((x) << S_FL_PROG_THRESH)
1905 #define G_FL_PROG_THRESH(x) (((x) >> S_FL_PROG_THRESH) & M_FL_PROG_THRESH)
1906 
1907 #define S_COAL_ALL_THREAD    19
1908 #define V_COAL_ALL_THREAD(x) ((x) << S_COAL_ALL_THREAD)
1909 #define F_COAL_ALL_THREAD    V_COAL_ALL_THREAD(1U)
1910 
1911 #define S_EN_PSHB    18
1912 #define V_EN_PSHB(x) ((x) << S_EN_PSHB)
1913 #define F_EN_PSHB    V_EN_PSHB(1U)
1914 
1915 #define S_EN_DB_FIFTH    17
1916 #define V_EN_DB_FIFTH(x) ((x) << S_EN_DB_FIFTH)
1917 #define F_EN_DB_FIFTH    V_EN_DB_FIFTH(1U)
1918 
1919 #define S_DB_PROG_THRESH    8
1920 #define M_DB_PROG_THRESH    0x1ffU
1921 #define V_DB_PROG_THRESH(x) ((x) << S_DB_PROG_THRESH)
1922 #define G_DB_PROG_THRESH(x) (((x) >> S_DB_PROG_THRESH) & M_DB_PROG_THRESH)
1923 
1924 #define S_100NS_TIMER    0
1925 #define M_100NS_TIMER    0xffU
1926 #define V_100NS_TIMER(x) ((x) << S_100NS_TIMER)
1927 #define G_100NS_TIMER(x) (((x) >> S_100NS_TIMER) & M_100NS_TIMER)
1928 
1929 #define A_SGE_PD_RSP_CREDIT23 0x10c8
1930 
1931 #define S_RSPCREDITEN2    31
1932 #define V_RSPCREDITEN2(x) ((x) << S_RSPCREDITEN2)
1933 #define F_RSPCREDITEN2    V_RSPCREDITEN2(1U)
1934 
1935 #define S_MAXTAG2    24
1936 #define M_MAXTAG2    0x7fU
1937 #define V_MAXTAG2(x) ((x) << S_MAXTAG2)
1938 #define G_MAXTAG2(x) (((x) >> S_MAXTAG2) & M_MAXTAG2)
1939 
1940 #define S_MAXRSPCNT2    16
1941 #define M_MAXRSPCNT2    0xffU
1942 #define V_MAXRSPCNT2(x) ((x) << S_MAXRSPCNT2)
1943 #define G_MAXRSPCNT2(x) (((x) >> S_MAXRSPCNT2) & M_MAXRSPCNT2)
1944 
1945 #define S_RSPCREDITEN3    15
1946 #define V_RSPCREDITEN3(x) ((x) << S_RSPCREDITEN3)
1947 #define F_RSPCREDITEN3    V_RSPCREDITEN3(1U)
1948 
1949 #define S_MAXTAG3    8
1950 #define M_MAXTAG3    0x7fU
1951 #define V_MAXTAG3(x) ((x) << S_MAXTAG3)
1952 #define G_MAXTAG3(x) (((x) >> S_MAXTAG3) & M_MAXTAG3)
1953 
1954 #define S_MAXRSPCNT3    0
1955 #define M_MAXRSPCNT3    0xffU
1956 #define V_MAXRSPCNT3(x) ((x) << S_MAXRSPCNT3)
1957 #define G_MAXRSPCNT3(x) (((x) >> S_MAXRSPCNT3) & M_MAXRSPCNT3)
1958 
1959 #define A_SGE_GK_CONTROL2 0x10c8
1960 
1961 #define S_DBQ_TIMER_TICK    16
1962 #define M_DBQ_TIMER_TICK    0xffffU
1963 #define V_DBQ_TIMER_TICK(x) ((x) << S_DBQ_TIMER_TICK)
1964 #define G_DBQ_TIMER_TICK(x) (((x) >> S_DBQ_TIMER_TICK) & M_DBQ_TIMER_TICK)
1965 
1966 #define S_FL_MERGE_CNT_THRESH    8
1967 #define M_FL_MERGE_CNT_THRESH    0xfU
1968 #define V_FL_MERGE_CNT_THRESH(x) ((x) << S_FL_MERGE_CNT_THRESH)
1969 #define G_FL_MERGE_CNT_THRESH(x) (((x) >> S_FL_MERGE_CNT_THRESH) & M_FL_MERGE_CNT_THRESH)
1970 
1971 #define S_MERGE_CNT_THRESH    0
1972 #define M_MERGE_CNT_THRESH    0x3fU
1973 #define V_MERGE_CNT_THRESH(x) ((x) << S_MERGE_CNT_THRESH)
1974 #define G_MERGE_CNT_THRESH(x) (((x) >> S_MERGE_CNT_THRESH) & M_MERGE_CNT_THRESH)
1975 
1976 #define A_SGE_DEBUG_INDEX 0x10cc
1977 #define A_SGE_DEBUG_DATA_HIGH 0x10d0
1978 #define A_SGE_DEBUG_DATA_LOW 0x10d4
1979 #define A_SGE_REVISION 0x10d8
1980 #define A_SGE_INT_CAUSE4 0x10dc
1981 
1982 #define S_ERR_BAD_UPFL_INC_CREDIT3    8
1983 #define V_ERR_BAD_UPFL_INC_CREDIT3(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT3)
1984 #define F_ERR_BAD_UPFL_INC_CREDIT3    V_ERR_BAD_UPFL_INC_CREDIT3(1U)
1985 
1986 #define S_ERR_BAD_UPFL_INC_CREDIT2    7
1987 #define V_ERR_BAD_UPFL_INC_CREDIT2(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT2)
1988 #define F_ERR_BAD_UPFL_INC_CREDIT2    V_ERR_BAD_UPFL_INC_CREDIT2(1U)
1989 
1990 #define S_ERR_BAD_UPFL_INC_CREDIT1    6
1991 #define V_ERR_BAD_UPFL_INC_CREDIT1(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT1)
1992 #define F_ERR_BAD_UPFL_INC_CREDIT1    V_ERR_BAD_UPFL_INC_CREDIT1(1U)
1993 
1994 #define S_ERR_BAD_UPFL_INC_CREDIT0    5
1995 #define V_ERR_BAD_UPFL_INC_CREDIT0(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT0)
1996 #define F_ERR_BAD_UPFL_INC_CREDIT0    V_ERR_BAD_UPFL_INC_CREDIT0(1U)
1997 
1998 #define S_ERR_PHYSADDR_LEN0_IDMA1    4
1999 #define V_ERR_PHYSADDR_LEN0_IDMA1(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA1)
2000 #define F_ERR_PHYSADDR_LEN0_IDMA1    V_ERR_PHYSADDR_LEN0_IDMA1(1U)
2001 
2002 #define S_ERR_PHYSADDR_LEN0_IDMA0    3
2003 #define V_ERR_PHYSADDR_LEN0_IDMA0(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA0)
2004 #define F_ERR_PHYSADDR_LEN0_IDMA0    V_ERR_PHYSADDR_LEN0_IDMA0(1U)
2005 
2006 #define S_ERR_FLM_INVALID_PKT_DROP1    2
2007 #define V_ERR_FLM_INVALID_PKT_DROP1(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP1)
2008 #define F_ERR_FLM_INVALID_PKT_DROP1    V_ERR_FLM_INVALID_PKT_DROP1(1U)
2009 
2010 #define S_ERR_FLM_INVALID_PKT_DROP0    1
2011 #define V_ERR_FLM_INVALID_PKT_DROP0(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP0)
2012 #define F_ERR_FLM_INVALID_PKT_DROP0    V_ERR_FLM_INVALID_PKT_DROP0(1U)
2013 
2014 #define S_ERR_UNEXPECTED_TIMER    0
2015 #define V_ERR_UNEXPECTED_TIMER(x) ((x) << S_ERR_UNEXPECTED_TIMER)
2016 #define F_ERR_UNEXPECTED_TIMER    V_ERR_UNEXPECTED_TIMER(1U)
2017 
2018 #define S_BAR2_EGRESS_LEN_OR_ADDR_ERR    29
2019 #define V_BAR2_EGRESS_LEN_OR_ADDR_ERR(x) ((x) << S_BAR2_EGRESS_LEN_OR_ADDR_ERR)
2020 #define F_BAR2_EGRESS_LEN_OR_ADDR_ERR    V_BAR2_EGRESS_LEN_OR_ADDR_ERR(1U)
2021 
2022 #define S_ERR_CPL_EXCEED_MAX_IQE_SIZE1    28
2023 #define V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE1)
2024 #define F_ERR_CPL_EXCEED_MAX_IQE_SIZE1    V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(1U)
2025 
2026 #define S_ERR_CPL_EXCEED_MAX_IQE_SIZE0    27
2027 #define V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE0)
2028 #define F_ERR_CPL_EXCEED_MAX_IQE_SIZE0    V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(1U)
2029 
2030 #define S_ERR_WR_LEN_TOO_LARGE3    26
2031 #define V_ERR_WR_LEN_TOO_LARGE3(x) ((x) << S_ERR_WR_LEN_TOO_LARGE3)
2032 #define F_ERR_WR_LEN_TOO_LARGE3    V_ERR_WR_LEN_TOO_LARGE3(1U)
2033 
2034 #define S_ERR_WR_LEN_TOO_LARGE2    25
2035 #define V_ERR_WR_LEN_TOO_LARGE2(x) ((x) << S_ERR_WR_LEN_TOO_LARGE2)
2036 #define F_ERR_WR_LEN_TOO_LARGE2    V_ERR_WR_LEN_TOO_LARGE2(1U)
2037 
2038 #define S_ERR_WR_LEN_TOO_LARGE1    24
2039 #define V_ERR_WR_LEN_TOO_LARGE1(x) ((x) << S_ERR_WR_LEN_TOO_LARGE1)
2040 #define F_ERR_WR_LEN_TOO_LARGE1    V_ERR_WR_LEN_TOO_LARGE1(1U)
2041 
2042 #define S_ERR_WR_LEN_TOO_LARGE0    23
2043 #define V_ERR_WR_LEN_TOO_LARGE0(x) ((x) << S_ERR_WR_LEN_TOO_LARGE0)
2044 #define F_ERR_WR_LEN_TOO_LARGE0    V_ERR_WR_LEN_TOO_LARGE0(1U)
2045 
2046 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL3    22
2047 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL3)
2048 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL3    V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(1U)
2049 
2050 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL2    21
2051 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL2)
2052 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL2    V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(1U)
2053 
2054 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL1    20
2055 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL1)
2056 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL1    V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(1U)
2057 
2058 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL0    19
2059 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL0)
2060 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL0    V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(1U)
2061 
2062 #define S_COAL_WITH_HP_DISABLE_ERR    18
2063 #define V_COAL_WITH_HP_DISABLE_ERR(x) ((x) << S_COAL_WITH_HP_DISABLE_ERR)
2064 #define F_COAL_WITH_HP_DISABLE_ERR    V_COAL_WITH_HP_DISABLE_ERR(1U)
2065 
2066 #define S_BAR2_EGRESS_COAL0_ERR    17
2067 #define V_BAR2_EGRESS_COAL0_ERR(x) ((x) << S_BAR2_EGRESS_COAL0_ERR)
2068 #define F_BAR2_EGRESS_COAL0_ERR    V_BAR2_EGRESS_COAL0_ERR(1U)
2069 
2070 #define S_BAR2_EGRESS_SIZE_ERR    16
2071 #define V_BAR2_EGRESS_SIZE_ERR(x) ((x) << S_BAR2_EGRESS_SIZE_ERR)
2072 #define F_BAR2_EGRESS_SIZE_ERR    V_BAR2_EGRESS_SIZE_ERR(1U)
2073 
2074 #define S_FLM_PC_RSP_ERR    15
2075 #define V_FLM_PC_RSP_ERR(x) ((x) << S_FLM_PC_RSP_ERR)
2076 #define F_FLM_PC_RSP_ERR    V_FLM_PC_RSP_ERR(1U)
2077 
2078 #define S_DBFIFO_HP_INT_LOW    14
2079 #define V_DBFIFO_HP_INT_LOW(x) ((x) << S_DBFIFO_HP_INT_LOW)
2080 #define F_DBFIFO_HP_INT_LOW    V_DBFIFO_HP_INT_LOW(1U)
2081 
2082 #define S_DBFIFO_LP_INT_LOW    13
2083 #define V_DBFIFO_LP_INT_LOW(x) ((x) << S_DBFIFO_LP_INT_LOW)
2084 #define F_DBFIFO_LP_INT_LOW    V_DBFIFO_LP_INT_LOW(1U)
2085 
2086 #define S_DBFIFO_FL_INT_LOW    12
2087 #define V_DBFIFO_FL_INT_LOW(x) ((x) << S_DBFIFO_FL_INT_LOW)
2088 #define F_DBFIFO_FL_INT_LOW    V_DBFIFO_FL_INT_LOW(1U)
2089 
2090 #define S_DBFIFO_FL_INT    11
2091 #define V_DBFIFO_FL_INT(x) ((x) << S_DBFIFO_FL_INT)
2092 #define F_DBFIFO_FL_INT    V_DBFIFO_FL_INT(1U)
2093 
2094 #define S_ERR_RX_CPL_PACKET_SIZE1    10
2095 #define V_ERR_RX_CPL_PACKET_SIZE1(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE1)
2096 #define F_ERR_RX_CPL_PACKET_SIZE1    V_ERR_RX_CPL_PACKET_SIZE1(1U)
2097 
2098 #define S_ERR_RX_CPL_PACKET_SIZE0    9
2099 #define V_ERR_RX_CPL_PACKET_SIZE0(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE0)
2100 #define F_ERR_RX_CPL_PACKET_SIZE0    V_ERR_RX_CPL_PACKET_SIZE0(1U)
2101 
2102 #define S_ERR_ISHIFT_UR1    31
2103 #define V_ERR_ISHIFT_UR1(x) ((x) << S_ERR_ISHIFT_UR1)
2104 #define F_ERR_ISHIFT_UR1    V_ERR_ISHIFT_UR1(1U)
2105 
2106 #define S_ERR_ISHIFT_UR0    30
2107 #define V_ERR_ISHIFT_UR0(x) ((x) << S_ERR_ISHIFT_UR0)
2108 #define F_ERR_ISHIFT_UR0    V_ERR_ISHIFT_UR0(1U)
2109 
2110 #define S_ERR_TH3_MAX_FETCH    14
2111 #define V_ERR_TH3_MAX_FETCH(x) ((x) << S_ERR_TH3_MAX_FETCH)
2112 #define F_ERR_TH3_MAX_FETCH    V_ERR_TH3_MAX_FETCH(1U)
2113 
2114 #define S_ERR_TH2_MAX_FETCH    13
2115 #define V_ERR_TH2_MAX_FETCH(x) ((x) << S_ERR_TH2_MAX_FETCH)
2116 #define F_ERR_TH2_MAX_FETCH    V_ERR_TH2_MAX_FETCH(1U)
2117 
2118 #define S_ERR_TH1_MAX_FETCH    12
2119 #define V_ERR_TH1_MAX_FETCH(x) ((x) << S_ERR_TH1_MAX_FETCH)
2120 #define F_ERR_TH1_MAX_FETCH    V_ERR_TH1_MAX_FETCH(1U)
2121 
2122 #define S_ERR_TH0_MAX_FETCH    11
2123 #define V_ERR_TH0_MAX_FETCH(x) ((x) << S_ERR_TH0_MAX_FETCH)
2124 #define F_ERR_TH0_MAX_FETCH    V_ERR_TH0_MAX_FETCH(1U)
2125 
2126 #define A_SGE_INT_ENABLE4 0x10e0
2127 #define A_SGE_STAT_TOTAL 0x10e4
2128 #define A_SGE_STAT_MATCH 0x10e8
2129 #define A_SGE_STAT_CFG 0x10ec
2130 
2131 #define S_ITPOPMODE    8
2132 #define V_ITPOPMODE(x) ((x) << S_ITPOPMODE)
2133 #define F_ITPOPMODE    V_ITPOPMODE(1U)
2134 
2135 #define S_EGRCTXTOPMODE    6
2136 #define M_EGRCTXTOPMODE    0x3U
2137 #define V_EGRCTXTOPMODE(x) ((x) << S_EGRCTXTOPMODE)
2138 #define G_EGRCTXTOPMODE(x) (((x) >> S_EGRCTXTOPMODE) & M_EGRCTXTOPMODE)
2139 
2140 #define S_INGCTXTOPMODE    4
2141 #define M_INGCTXTOPMODE    0x3U
2142 #define V_INGCTXTOPMODE(x) ((x) << S_INGCTXTOPMODE)
2143 #define G_INGCTXTOPMODE(x) (((x) >> S_INGCTXTOPMODE) & M_INGCTXTOPMODE)
2144 
2145 #define S_STATMODE    2
2146 #define M_STATMODE    0x3U
2147 #define V_STATMODE(x) ((x) << S_STATMODE)
2148 #define G_STATMODE(x) (((x) >> S_STATMODE) & M_STATMODE)
2149 
2150 #define S_STATSOURCE    0
2151 #define M_STATSOURCE    0x3U
2152 #define V_STATSOURCE(x) ((x) << S_STATSOURCE)
2153 #define G_STATSOURCE(x) (((x) >> S_STATSOURCE) & M_STATSOURCE)
2154 
2155 #define S_STATSOURCE_T5    9
2156 #define M_STATSOURCE_T5    0xfU
2157 #define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
2158 #define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5)
2159 
2160 #define S_T6_STATMODE    0
2161 #define M_T6_STATMODE    0xfU
2162 #define V_T6_STATMODE(x) ((x) << S_T6_STATMODE)
2163 #define G_T6_STATMODE(x) (((x) >> S_T6_STATMODE) & M_T6_STATMODE)
2164 
2165 #define A_SGE_HINT_CFG 0x10f0
2166 
2167 #define S_HINTSALLOWEDNOHDR    6
2168 #define M_HINTSALLOWEDNOHDR    0x3fU
2169 #define V_HINTSALLOWEDNOHDR(x) ((x) << S_HINTSALLOWEDNOHDR)
2170 #define G_HINTSALLOWEDNOHDR(x) (((x) >> S_HINTSALLOWEDNOHDR) & M_HINTSALLOWEDNOHDR)
2171 
2172 #define S_HINTSALLOWEDHDR    0
2173 #define M_HINTSALLOWEDHDR    0x3fU
2174 #define V_HINTSALLOWEDHDR(x) ((x) << S_HINTSALLOWEDHDR)
2175 #define G_HINTSALLOWEDHDR(x) (((x) >> S_HINTSALLOWEDHDR) & M_HINTSALLOWEDHDR)
2176 
2177 #define S_UPCUTOFFTHRESHLP    12
2178 #define M_UPCUTOFFTHRESHLP    0x7ffU
2179 #define V_UPCUTOFFTHRESHLP(x) ((x) << S_UPCUTOFFTHRESHLP)
2180 #define G_UPCUTOFFTHRESHLP(x) (((x) >> S_UPCUTOFFTHRESHLP) & M_UPCUTOFFTHRESHLP)
2181 
2182 #define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
2183 #define A_SGE_INGRESS_QUEUES_PER_PAGE_VF 0x10f8
2184 #define A_SGE_PD_WRR_CONFIG 0x10fc
2185 
2186 #define S_EDMA_WEIGHT    0
2187 #define M_EDMA_WEIGHT    0x3fU
2188 #define V_EDMA_WEIGHT(x) ((x) << S_EDMA_WEIGHT)
2189 #define G_EDMA_WEIGHT(x) (((x) >> S_EDMA_WEIGHT) & M_EDMA_WEIGHT)
2190 
2191 #define A_SGE_ERROR_STATS 0x1100
2192 
2193 #define S_UNCAPTURED_ERROR    18
2194 #define V_UNCAPTURED_ERROR(x) ((x) << S_UNCAPTURED_ERROR)
2195 #define F_UNCAPTURED_ERROR    V_UNCAPTURED_ERROR(1U)
2196 
2197 #define S_ERROR_QID_VALID    17
2198 #define V_ERROR_QID_VALID(x) ((x) << S_ERROR_QID_VALID)
2199 #define F_ERROR_QID_VALID    V_ERROR_QID_VALID(1U)
2200 
2201 #define S_ERROR_QID    0
2202 #define M_ERROR_QID    0x1ffffU
2203 #define V_ERROR_QID(x) ((x) << S_ERROR_QID)
2204 #define G_ERROR_QID(x) (((x) >> S_ERROR_QID) & M_ERROR_QID)
2205 
2206 #define S_CAUSE_REGISTER    24
2207 #define M_CAUSE_REGISTER    0x7U
2208 #define V_CAUSE_REGISTER(x) ((x) << S_CAUSE_REGISTER)
2209 #define G_CAUSE_REGISTER(x) (((x) >> S_CAUSE_REGISTER) & M_CAUSE_REGISTER)
2210 
2211 #define S_CAUSE_BIT    19
2212 #define M_CAUSE_BIT    0x1fU
2213 #define V_CAUSE_BIT(x) ((x) << S_CAUSE_BIT)
2214 #define G_CAUSE_BIT(x) (((x) >> S_CAUSE_BIT) & M_CAUSE_BIT)
2215 
2216 #define A_SGE_SHARED_TAG_CHAN_CFG 0x1104
2217 
2218 #define S_MINTAG3    24
2219 #define M_MINTAG3    0xffU
2220 #define V_MINTAG3(x) ((x) << S_MINTAG3)
2221 #define G_MINTAG3(x) (((x) >> S_MINTAG3) & M_MINTAG3)
2222 
2223 #define S_MINTAG2    16
2224 #define M_MINTAG2    0xffU
2225 #define V_MINTAG2(x) ((x) << S_MINTAG2)
2226 #define G_MINTAG2(x) (((x) >> S_MINTAG2) & M_MINTAG2)
2227 
2228 #define S_MINTAG1    8
2229 #define M_MINTAG1    0xffU
2230 #define V_MINTAG1(x) ((x) << S_MINTAG1)
2231 #define G_MINTAG1(x) (((x) >> S_MINTAG1) & M_MINTAG1)
2232 
2233 #define S_MINTAG0    0
2234 #define M_MINTAG0    0xffU
2235 #define V_MINTAG0(x) ((x) << S_MINTAG0)
2236 #define G_MINTAG0(x) (((x) >> S_MINTAG0) & M_MINTAG0)
2237 
2238 #define A_SGE_IDMA0_DROP_CNT 0x1104
2239 #define A_SGE_SHARED_TAG_POOL_CFG 0x1108
2240 
2241 #define S_TAGPOOLTOTAL    0
2242 #define M_TAGPOOLTOTAL    0xffU
2243 #define V_TAGPOOLTOTAL(x) ((x) << S_TAGPOOLTOTAL)
2244 #define G_TAGPOOLTOTAL(x) (((x) >> S_TAGPOOLTOTAL) & M_TAGPOOLTOTAL)
2245 
2246 #define A_SGE_IDMA1_DROP_CNT 0x1108
2247 #define A_SGE_INT_CAUSE5 0x110c
2248 
2249 #define S_ERR_T_RXCRC    31
2250 #define V_ERR_T_RXCRC(x) ((x) << S_ERR_T_RXCRC)
2251 #define F_ERR_T_RXCRC    V_ERR_T_RXCRC(1U)
2252 
2253 #define S_PERR_MC_RSPDATA    30
2254 #define V_PERR_MC_RSPDATA(x) ((x) << S_PERR_MC_RSPDATA)
2255 #define F_PERR_MC_RSPDATA    V_PERR_MC_RSPDATA(1U)
2256 
2257 #define S_PERR_PC_RSPDATA    29
2258 #define V_PERR_PC_RSPDATA(x) ((x) << S_PERR_PC_RSPDATA)
2259 #define F_PERR_PC_RSPDATA    V_PERR_PC_RSPDATA(1U)
2260 
2261 #define S_PERR_PD_RDRSPDATA    28
2262 #define V_PERR_PD_RDRSPDATA(x) ((x) << S_PERR_PD_RDRSPDATA)
2263 #define F_PERR_PD_RDRSPDATA    V_PERR_PD_RDRSPDATA(1U)
2264 
2265 #define S_PERR_U_RXDATA    27
2266 #define V_PERR_U_RXDATA(x) ((x) << S_PERR_U_RXDATA)
2267 #define F_PERR_U_RXDATA    V_PERR_U_RXDATA(1U)
2268 
2269 #define S_PERR_UD_RXDATA    26
2270 #define V_PERR_UD_RXDATA(x) ((x) << S_PERR_UD_RXDATA)
2271 #define F_PERR_UD_RXDATA    V_PERR_UD_RXDATA(1U)
2272 
2273 #define S_PERR_UP_DATA    25
2274 #define V_PERR_UP_DATA(x) ((x) << S_PERR_UP_DATA)
2275 #define F_PERR_UP_DATA    V_PERR_UP_DATA(1U)
2276 
2277 #define S_PERR_CIM2SGE_RXDATA    24
2278 #define V_PERR_CIM2SGE_RXDATA(x) ((x) << S_PERR_CIM2SGE_RXDATA)
2279 #define F_PERR_CIM2SGE_RXDATA    V_PERR_CIM2SGE_RXDATA(1U)
2280 
2281 #define S_PERR_HINT_DELAY_FIFO1_T5    23
2282 #define V_PERR_HINT_DELAY_FIFO1_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO1_T5)
2283 #define F_PERR_HINT_DELAY_FIFO1_T5    V_PERR_HINT_DELAY_FIFO1_T5(1U)
2284 
2285 #define S_PERR_HINT_DELAY_FIFO0_T5    22
2286 #define V_PERR_HINT_DELAY_FIFO0_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO0_T5)
2287 #define F_PERR_HINT_DELAY_FIFO0_T5    V_PERR_HINT_DELAY_FIFO0_T5(1U)
2288 
2289 #define S_PERR_IMSG_PD_FIFO_T5    21
2290 #define V_PERR_IMSG_PD_FIFO_T5(x) ((x) << S_PERR_IMSG_PD_FIFO_T5)
2291 #define F_PERR_IMSG_PD_FIFO_T5    V_PERR_IMSG_PD_FIFO_T5(1U)
2292 
2293 #define S_PERR_ULPTX_FIFO1_T5    20
2294 #define V_PERR_ULPTX_FIFO1_T5(x) ((x) << S_PERR_ULPTX_FIFO1_T5)
2295 #define F_PERR_ULPTX_FIFO1_T5    V_PERR_ULPTX_FIFO1_T5(1U)
2296 
2297 #define S_PERR_ULPTX_FIFO0_T5    19
2298 #define V_PERR_ULPTX_FIFO0_T5(x) ((x) << S_PERR_ULPTX_FIFO0_T5)
2299 #define F_PERR_ULPTX_FIFO0_T5    V_PERR_ULPTX_FIFO0_T5(1U)
2300 
2301 #define S_PERR_IDMA2IMSG_FIFO1_T5    18
2302 #define V_PERR_IDMA2IMSG_FIFO1_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO1_T5)
2303 #define F_PERR_IDMA2IMSG_FIFO1_T5    V_PERR_IDMA2IMSG_FIFO1_T5(1U)
2304 
2305 #define S_PERR_IDMA2IMSG_FIFO0_T5    17
2306 #define V_PERR_IDMA2IMSG_FIFO0_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO0_T5)
2307 #define F_PERR_IDMA2IMSG_FIFO0_T5    V_PERR_IDMA2IMSG_FIFO0_T5(1U)
2308 
2309 #define S_PERR_POINTER_DATA_FIFO0    16
2310 #define V_PERR_POINTER_DATA_FIFO0(x) ((x) << S_PERR_POINTER_DATA_FIFO0)
2311 #define F_PERR_POINTER_DATA_FIFO0    V_PERR_POINTER_DATA_FIFO0(1U)
2312 
2313 #define S_PERR_POINTER_DATA_FIFO1    15
2314 #define V_PERR_POINTER_DATA_FIFO1(x) ((x) << S_PERR_POINTER_DATA_FIFO1)
2315 #define F_PERR_POINTER_DATA_FIFO1    V_PERR_POINTER_DATA_FIFO1(1U)
2316 
2317 #define S_PERR_POINTER_HDR_FIFO0    14
2318 #define V_PERR_POINTER_HDR_FIFO0(x) ((x) << S_PERR_POINTER_HDR_FIFO0)
2319 #define F_PERR_POINTER_HDR_FIFO0    V_PERR_POINTER_HDR_FIFO0(1U)
2320 
2321 #define S_PERR_POINTER_HDR_FIFO1    13
2322 #define V_PERR_POINTER_HDR_FIFO1(x) ((x) << S_PERR_POINTER_HDR_FIFO1)
2323 #define F_PERR_POINTER_HDR_FIFO1    V_PERR_POINTER_HDR_FIFO1(1U)
2324 
2325 #define S_PERR_PAYLOAD_FIFO0    12
2326 #define V_PERR_PAYLOAD_FIFO0(x) ((x) << S_PERR_PAYLOAD_FIFO0)
2327 #define F_PERR_PAYLOAD_FIFO0    V_PERR_PAYLOAD_FIFO0(1U)
2328 
2329 #define S_PERR_PAYLOAD_FIFO1    11
2330 #define V_PERR_PAYLOAD_FIFO1(x) ((x) << S_PERR_PAYLOAD_FIFO1)
2331 #define F_PERR_PAYLOAD_FIFO1    V_PERR_PAYLOAD_FIFO1(1U)
2332 
2333 #define S_PERR_EDMA_INPUT_FIFO3    10
2334 #define V_PERR_EDMA_INPUT_FIFO3(x) ((x) << S_PERR_EDMA_INPUT_FIFO3)
2335 #define F_PERR_EDMA_INPUT_FIFO3    V_PERR_EDMA_INPUT_FIFO3(1U)
2336 
2337 #define S_PERR_EDMA_INPUT_FIFO2    9
2338 #define V_PERR_EDMA_INPUT_FIFO2(x) ((x) << S_PERR_EDMA_INPUT_FIFO2)
2339 #define F_PERR_EDMA_INPUT_FIFO2    V_PERR_EDMA_INPUT_FIFO2(1U)
2340 
2341 #define S_PERR_EDMA_INPUT_FIFO1    8
2342 #define V_PERR_EDMA_INPUT_FIFO1(x) ((x) << S_PERR_EDMA_INPUT_FIFO1)
2343 #define F_PERR_EDMA_INPUT_FIFO1    V_PERR_EDMA_INPUT_FIFO1(1U)
2344 
2345 #define S_PERR_EDMA_INPUT_FIFO0    7
2346 #define V_PERR_EDMA_INPUT_FIFO0(x) ((x) << S_PERR_EDMA_INPUT_FIFO0)
2347 #define F_PERR_EDMA_INPUT_FIFO0    V_PERR_EDMA_INPUT_FIFO0(1U)
2348 
2349 #define S_PERR_MGT_BAR2_FIFO    6
2350 #define V_PERR_MGT_BAR2_FIFO(x) ((x) << S_PERR_MGT_BAR2_FIFO)
2351 #define F_PERR_MGT_BAR2_FIFO    V_PERR_MGT_BAR2_FIFO(1U)
2352 
2353 #define S_PERR_HEADERSPLIT_FIFO1_T5    5
2354 #define V_PERR_HEADERSPLIT_FIFO1_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO1_T5)
2355 #define F_PERR_HEADERSPLIT_FIFO1_T5    V_PERR_HEADERSPLIT_FIFO1_T5(1U)
2356 
2357 #define S_PERR_HEADERSPLIT_FIFO0_T5    4
2358 #define V_PERR_HEADERSPLIT_FIFO0_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO0_T5)
2359 #define F_PERR_HEADERSPLIT_FIFO0_T5    V_PERR_HEADERSPLIT_FIFO0_T5(1U)
2360 
2361 #define S_PERR_CIM_FIFO1    3
2362 #define V_PERR_CIM_FIFO1(x) ((x) << S_PERR_CIM_FIFO1)
2363 #define F_PERR_CIM_FIFO1    V_PERR_CIM_FIFO1(1U)
2364 
2365 #define S_PERR_CIM_FIFO0    2
2366 #define V_PERR_CIM_FIFO0(x) ((x) << S_PERR_CIM_FIFO0)
2367 #define F_PERR_CIM_FIFO0    V_PERR_CIM_FIFO0(1U)
2368 
2369 #define S_PERR_IDMA_SWITCH_OUTPUT_FIFO1    1
2370 #define V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO1)
2371 #define F_PERR_IDMA_SWITCH_OUTPUT_FIFO1    V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(1U)
2372 
2373 #define S_PERR_IDMA_SWITCH_OUTPUT_FIFO0    0
2374 #define V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO0)
2375 #define F_PERR_IDMA_SWITCH_OUTPUT_FIFO0    V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(1U)
2376 
2377 #define S_PERR_POINTER_HDR_FIFO3    10
2378 #define V_PERR_POINTER_HDR_FIFO3(x) ((x) << S_PERR_POINTER_HDR_FIFO3)
2379 #define F_PERR_POINTER_HDR_FIFO3    V_PERR_POINTER_HDR_FIFO3(1U)
2380 
2381 #define S_PERR_POINTER_HDR_FIFO2    9
2382 #define V_PERR_POINTER_HDR_FIFO2(x) ((x) << S_PERR_POINTER_HDR_FIFO2)
2383 #define F_PERR_POINTER_HDR_FIFO2    V_PERR_POINTER_HDR_FIFO2(1U)
2384 
2385 #define S_PERR_POINTER_DATA_FIFO3    8
2386 #define V_PERR_POINTER_DATA_FIFO3(x) ((x) << S_PERR_POINTER_DATA_FIFO3)
2387 #define F_PERR_POINTER_DATA_FIFO3    V_PERR_POINTER_DATA_FIFO3(1U)
2388 
2389 #define S_PERR_POINTER_DATA_FIFO2    7
2390 #define V_PERR_POINTER_DATA_FIFO2(x) ((x) << S_PERR_POINTER_DATA_FIFO2)
2391 #define F_PERR_POINTER_DATA_FIFO2    V_PERR_POINTER_DATA_FIFO2(1U)
2392 
2393 #define S_PERR_IDMA2IMSG_FIFO3    3
2394 #define V_PERR_IDMA2IMSG_FIFO3(x) ((x) << S_PERR_IDMA2IMSG_FIFO3)
2395 #define F_PERR_IDMA2IMSG_FIFO3    V_PERR_IDMA2IMSG_FIFO3(1U)
2396 
2397 #define S_PERR_IDMA2IMSG_FIFO2    2
2398 #define V_PERR_IDMA2IMSG_FIFO2(x) ((x) << S_PERR_IDMA2IMSG_FIFO2)
2399 #define F_PERR_IDMA2IMSG_FIFO2    V_PERR_IDMA2IMSG_FIFO2(1U)
2400 
2401 #define S_PERR_HINT_DELAY_FIFO    0
2402 #define V_PERR_HINT_DELAY_FIFO(x) ((x) << S_PERR_HINT_DELAY_FIFO)
2403 #define F_PERR_HINT_DELAY_FIFO    V_PERR_HINT_DELAY_FIFO(1U)
2404 
2405 #define A_SGE_INT_ENABLE5 0x1110
2406 #define A_SGE_PERR_ENABLE5 0x1114
2407 #define A_SGE_DBFIFO_STATUS2 0x1118
2408 
2409 #define S_FL_INT_THRESH    24
2410 #define M_FL_INT_THRESH    0xfU
2411 #define V_FL_INT_THRESH(x) ((x) << S_FL_INT_THRESH)
2412 #define G_FL_INT_THRESH(x) (((x) >> S_FL_INT_THRESH) & M_FL_INT_THRESH)
2413 
2414 #define S_FL_COUNT    14
2415 #define M_FL_COUNT    0x3ffU
2416 #define V_FL_COUNT(x) ((x) << S_FL_COUNT)
2417 #define G_FL_COUNT(x) (((x) >> S_FL_COUNT) & M_FL_COUNT)
2418 
2419 #define S_HP_INT_THRESH_T5    10
2420 #define M_HP_INT_THRESH_T5    0xfU
2421 #define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
2422 #define G_HP_INT_THRESH_T5(x) (((x) >> S_HP_INT_THRESH_T5) & M_HP_INT_THRESH_T5)
2423 
2424 #define S_HP_COUNT_T5    0
2425 #define M_HP_COUNT_T5    0x3ffU
2426 #define V_HP_COUNT_T5(x) ((x) << S_HP_COUNT_T5)
2427 #define G_HP_COUNT_T5(x) (((x) >> S_HP_COUNT_T5) & M_HP_COUNT_T5)
2428 
2429 #define A_SGE_FETCH_BURST_MAX_0_AND_1 0x111c
2430 
2431 #define S_FETCHBURSTMAX0    16
2432 #define M_FETCHBURSTMAX0    0x3ffU
2433 #define V_FETCHBURSTMAX0(x) ((x) << S_FETCHBURSTMAX0)
2434 #define G_FETCHBURSTMAX0(x) (((x) >> S_FETCHBURSTMAX0) & M_FETCHBURSTMAX0)
2435 
2436 #define S_FETCHBURSTMAX1    0
2437 #define M_FETCHBURSTMAX1    0x3ffU
2438 #define V_FETCHBURSTMAX1(x) ((x) << S_FETCHBURSTMAX1)
2439 #define G_FETCHBURSTMAX1(x) (((x) >> S_FETCHBURSTMAX1) & M_FETCHBURSTMAX1)
2440 
2441 #define A_SGE_FETCH_BURST_MAX_2_AND_3 0x1120
2442 
2443 #define S_FETCHBURSTMAX2    16
2444 #define M_FETCHBURSTMAX2    0x3ffU
2445 #define V_FETCHBURSTMAX2(x) ((x) << S_FETCHBURSTMAX2)
2446 #define G_FETCHBURSTMAX2(x) (((x) >> S_FETCHBURSTMAX2) & M_FETCHBURSTMAX2)
2447 
2448 #define S_FETCHBURSTMAX3    0
2449 #define M_FETCHBURSTMAX3    0x3ffU
2450 #define V_FETCHBURSTMAX3(x) ((x) << S_FETCHBURSTMAX3)
2451 #define G_FETCHBURSTMAX3(x) (((x) >> S_FETCHBURSTMAX3) & M_FETCHBURSTMAX3)
2452 
2453 #define A_SGE_CONTROL2 0x1124
2454 
2455 #define S_UPFLCUTOFFDIS    21
2456 #define V_UPFLCUTOFFDIS(x) ((x) << S_UPFLCUTOFFDIS)
2457 #define F_UPFLCUTOFFDIS    V_UPFLCUTOFFDIS(1U)
2458 
2459 #define S_RXCPLSIZEAUTOCORRECT    20
2460 #define V_RXCPLSIZEAUTOCORRECT(x) ((x) << S_RXCPLSIZEAUTOCORRECT)
2461 #define F_RXCPLSIZEAUTOCORRECT    V_RXCPLSIZEAUTOCORRECT(1U)
2462 
2463 #define S_IDMAARBROUNDROBIN    19
2464 #define V_IDMAARBROUNDROBIN(x) ((x) << S_IDMAARBROUNDROBIN)
2465 #define F_IDMAARBROUNDROBIN    V_IDMAARBROUNDROBIN(1U)
2466 
2467 #define S_INGPACKBOUNDARY    16
2468 #define M_INGPACKBOUNDARY    0x7U
2469 #define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY)
2470 #define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY)
2471 
2472 #define S_CGEN_EGRESS_CONTEXT    15
2473 #define V_CGEN_EGRESS_CONTEXT(x) ((x) << S_CGEN_EGRESS_CONTEXT)
2474 #define F_CGEN_EGRESS_CONTEXT    V_CGEN_EGRESS_CONTEXT(1U)
2475 
2476 #define S_CGEN_INGRESS_CONTEXT    14
2477 #define V_CGEN_INGRESS_CONTEXT(x) ((x) << S_CGEN_INGRESS_CONTEXT)
2478 #define F_CGEN_INGRESS_CONTEXT    V_CGEN_INGRESS_CONTEXT(1U)
2479 
2480 #define S_CGEN_IDMA    13
2481 #define V_CGEN_IDMA(x) ((x) << S_CGEN_IDMA)
2482 #define F_CGEN_IDMA    V_CGEN_IDMA(1U)
2483 
2484 #define S_CGEN_DBP    12
2485 #define V_CGEN_DBP(x) ((x) << S_CGEN_DBP)
2486 #define F_CGEN_DBP    V_CGEN_DBP(1U)
2487 
2488 #define S_CGEN_EDMA    11
2489 #define V_CGEN_EDMA(x) ((x) << S_CGEN_EDMA)
2490 #define F_CGEN_EDMA    V_CGEN_EDMA(1U)
2491 
2492 #define S_VFIFO_ENABLE    10
2493 #define V_VFIFO_ENABLE(x) ((x) << S_VFIFO_ENABLE)
2494 #define F_VFIFO_ENABLE    V_VFIFO_ENABLE(1U)
2495 
2496 #define S_FLM_RESCHEDULE_MODE    9
2497 #define V_FLM_RESCHEDULE_MODE(x) ((x) << S_FLM_RESCHEDULE_MODE)
2498 #define F_FLM_RESCHEDULE_MODE    V_FLM_RESCHEDULE_MODE(1U)
2499 
2500 #define S_HINTDEPTHCTLFL    4
2501 #define M_HINTDEPTHCTLFL    0x1fU
2502 #define V_HINTDEPTHCTLFL(x) ((x) << S_HINTDEPTHCTLFL)
2503 #define G_HINTDEPTHCTLFL(x) (((x) >> S_HINTDEPTHCTLFL) & M_HINTDEPTHCTLFL)
2504 
2505 #define S_FORCE_ORDERING    3
2506 #define V_FORCE_ORDERING(x) ((x) << S_FORCE_ORDERING)
2507 #define F_FORCE_ORDERING    V_FORCE_ORDERING(1U)
2508 
2509 #define S_TX_COALESCE_SIZE    2
2510 #define V_TX_COALESCE_SIZE(x) ((x) << S_TX_COALESCE_SIZE)
2511 #define F_TX_COALESCE_SIZE    V_TX_COALESCE_SIZE(1U)
2512 
2513 #define S_COAL_STRICT_CIM_PRI    1
2514 #define V_COAL_STRICT_CIM_PRI(x) ((x) << S_COAL_STRICT_CIM_PRI)
2515 #define F_COAL_STRICT_CIM_PRI    V_COAL_STRICT_CIM_PRI(1U)
2516 
2517 #define S_TX_COALESCE_PRI    0
2518 #define V_TX_COALESCE_PRI(x) ((x) << S_TX_COALESCE_PRI)
2519 #define F_TX_COALESCE_PRI    V_TX_COALESCE_PRI(1U)
2520 
2521 #define S_HINT_SGE_SEL    31
2522 #define V_HINT_SGE_SEL(x) ((x) << S_HINT_SGE_SEL)
2523 #define F_HINT_SGE_SEL    V_HINT_SGE_SEL(1U)
2524 
2525 #define S_HINT_SEL    30
2526 #define V_HINT_SEL(x) ((x) << S_HINT_SEL)
2527 #define F_HINT_SEL    V_HINT_SEL(1U)
2528 
2529 #define S_HINT_DISABLE    29
2530 #define V_HINT_DISABLE(x) ((x) << S_HINT_DISABLE)
2531 #define F_HINT_DISABLE    V_HINT_DISABLE(1U)
2532 
2533 #define S_RXCPLMODE_ISCSI    28
2534 #define V_RXCPLMODE_ISCSI(x) ((x) << S_RXCPLMODE_ISCSI)
2535 #define F_RXCPLMODE_ISCSI    V_RXCPLMODE_ISCSI(1U)
2536 
2537 #define S_RXCPLMODE_NVMT    27
2538 #define V_RXCPLMODE_NVMT(x) ((x) << S_RXCPLMODE_NVMT)
2539 #define F_RXCPLMODE_NVMT    V_RXCPLMODE_NVMT(1U)
2540 
2541 #define S_WRE_REPLAY_INORDER    26
2542 #define V_WRE_REPLAY_INORDER(x) ((x) << S_WRE_REPLAY_INORDER)
2543 #define F_WRE_REPLAY_INORDER    V_WRE_REPLAY_INORDER(1U)
2544 
2545 #define S_ETH2XEN    25
2546 #define V_ETH2XEN(x) ((x) << S_ETH2XEN)
2547 #define F_ETH2XEN    V_ETH2XEN(1U)
2548 
2549 #define S_ARMDBENDDIS    24
2550 #define V_ARMDBENDDIS(x) ((x) << S_ARMDBENDDIS)
2551 #define F_ARMDBENDDIS    V_ARMDBENDDIS(1U)
2552 
2553 #define S_PACKPADT7    23
2554 #define V_PACKPADT7(x) ((x) << S_PACKPADT7)
2555 #define F_PACKPADT7    V_PACKPADT7(1U)
2556 
2557 #define S_WRE_UPFLCREDIT    22
2558 #define V_WRE_UPFLCREDIT(x) ((x) << S_WRE_UPFLCREDIT)
2559 #define F_WRE_UPFLCREDIT    V_WRE_UPFLCREDIT(1U)
2560 
2561 #define A_SGE_DEEP_SLEEP 0x1128
2562 
2563 #define S_IDMA1_SLEEP_STATUS    11
2564 #define V_IDMA1_SLEEP_STATUS(x) ((x) << S_IDMA1_SLEEP_STATUS)
2565 #define F_IDMA1_SLEEP_STATUS    V_IDMA1_SLEEP_STATUS(1U)
2566 
2567 #define S_IDMA0_SLEEP_STATUS    10
2568 #define V_IDMA0_SLEEP_STATUS(x) ((x) << S_IDMA0_SLEEP_STATUS)
2569 #define F_IDMA0_SLEEP_STATUS    V_IDMA0_SLEEP_STATUS(1U)
2570 
2571 #define S_IDMA1_SLEEP_REQ    9
2572 #define V_IDMA1_SLEEP_REQ(x) ((x) << S_IDMA1_SLEEP_REQ)
2573 #define F_IDMA1_SLEEP_REQ    V_IDMA1_SLEEP_REQ(1U)
2574 
2575 #define S_IDMA0_SLEEP_REQ    8
2576 #define V_IDMA0_SLEEP_REQ(x) ((x) << S_IDMA0_SLEEP_REQ)
2577 #define F_IDMA0_SLEEP_REQ    V_IDMA0_SLEEP_REQ(1U)
2578 
2579 #define S_EDMA3_SLEEP_STATUS    7
2580 #define V_EDMA3_SLEEP_STATUS(x) ((x) << S_EDMA3_SLEEP_STATUS)
2581 #define F_EDMA3_SLEEP_STATUS    V_EDMA3_SLEEP_STATUS(1U)
2582 
2583 #define S_EDMA2_SLEEP_STATUS    6
2584 #define V_EDMA2_SLEEP_STATUS(x) ((x) << S_EDMA2_SLEEP_STATUS)
2585 #define F_EDMA2_SLEEP_STATUS    V_EDMA2_SLEEP_STATUS(1U)
2586 
2587 #define S_EDMA1_SLEEP_STATUS    5
2588 #define V_EDMA1_SLEEP_STATUS(x) ((x) << S_EDMA1_SLEEP_STATUS)
2589 #define F_EDMA1_SLEEP_STATUS    V_EDMA1_SLEEP_STATUS(1U)
2590 
2591 #define S_EDMA0_SLEEP_STATUS    4
2592 #define V_EDMA0_SLEEP_STATUS(x) ((x) << S_EDMA0_SLEEP_STATUS)
2593 #define F_EDMA0_SLEEP_STATUS    V_EDMA0_SLEEP_STATUS(1U)
2594 
2595 #define S_EDMA3_SLEEP_REQ    3
2596 #define V_EDMA3_SLEEP_REQ(x) ((x) << S_EDMA3_SLEEP_REQ)
2597 #define F_EDMA3_SLEEP_REQ    V_EDMA3_SLEEP_REQ(1U)
2598 
2599 #define S_EDMA2_SLEEP_REQ    2
2600 #define V_EDMA2_SLEEP_REQ(x) ((x) << S_EDMA2_SLEEP_REQ)
2601 #define F_EDMA2_SLEEP_REQ    V_EDMA2_SLEEP_REQ(1U)
2602 
2603 #define S_EDMA1_SLEEP_REQ    1
2604 #define V_EDMA1_SLEEP_REQ(x) ((x) << S_EDMA1_SLEEP_REQ)
2605 #define F_EDMA1_SLEEP_REQ    V_EDMA1_SLEEP_REQ(1U)
2606 
2607 #define S_EDMA0_SLEEP_REQ    0
2608 #define V_EDMA0_SLEEP_REQ(x) ((x) << S_EDMA0_SLEEP_REQ)
2609 #define F_EDMA0_SLEEP_REQ    V_EDMA0_SLEEP_REQ(1U)
2610 
2611 #define A_SGE_INT_CAUSE6 0x1128
2612 
2613 #define S_ERR_DB_SYNC    21
2614 #define V_ERR_DB_SYNC(x) ((x) << S_ERR_DB_SYNC)
2615 #define F_ERR_DB_SYNC    V_ERR_DB_SYNC(1U)
2616 
2617 #define S_ERR_GTS_SYNC    20
2618 #define V_ERR_GTS_SYNC(x) ((x) << S_ERR_GTS_SYNC)
2619 #define F_ERR_GTS_SYNC    V_ERR_GTS_SYNC(1U)
2620 
2621 #define S_FATAL_LARGE_COAL    19
2622 #define V_FATAL_LARGE_COAL(x) ((x) << S_FATAL_LARGE_COAL)
2623 #define F_FATAL_LARGE_COAL    V_FATAL_LARGE_COAL(1U)
2624 
2625 #define S_PL_BAR2_FRM_ERR    18
2626 #define V_PL_BAR2_FRM_ERR(x) ((x) << S_PL_BAR2_FRM_ERR)
2627 #define F_PL_BAR2_FRM_ERR    V_PL_BAR2_FRM_ERR(1U)
2628 
2629 #define S_SILENT_DROP_TX_COAL    17
2630 #define V_SILENT_DROP_TX_COAL(x) ((x) << S_SILENT_DROP_TX_COAL)
2631 #define F_SILENT_DROP_TX_COAL    V_SILENT_DROP_TX_COAL(1U)
2632 
2633 #define S_ERR_INV_CTXT4    16
2634 #define V_ERR_INV_CTXT4(x) ((x) << S_ERR_INV_CTXT4)
2635 #define F_ERR_INV_CTXT4    V_ERR_INV_CTXT4(1U)
2636 
2637 #define S_ERR_BAD_DB_PIDX4    15
2638 #define V_ERR_BAD_DB_PIDX4(x) ((x) << S_ERR_BAD_DB_PIDX4)
2639 #define F_ERR_BAD_DB_PIDX4    V_ERR_BAD_DB_PIDX4(1U)
2640 
2641 #define S_ERR_BAD_UPFL_INC_CREDIT4    14
2642 #define V_ERR_BAD_UPFL_INC_CREDIT4(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT4)
2643 #define F_ERR_BAD_UPFL_INC_CREDIT4    V_ERR_BAD_UPFL_INC_CREDIT4(1U)
2644 
2645 #define S_FATAL_TAG_MISMATCH    13
2646 #define V_FATAL_TAG_MISMATCH(x) ((x) << S_FATAL_TAG_MISMATCH)
2647 #define F_FATAL_TAG_MISMATCH    V_FATAL_TAG_MISMATCH(1U)
2648 
2649 #define S_FATAL_ENQ_CTL_RDY    12
2650 #define V_FATAL_ENQ_CTL_RDY(x) ((x) << S_FATAL_ENQ_CTL_RDY)
2651 #define F_FATAL_ENQ_CTL_RDY    V_FATAL_ENQ_CTL_RDY(1U)
2652 
2653 #define S_ERR_PC_RSP_LEN3    11
2654 #define V_ERR_PC_RSP_LEN3(x) ((x) << S_ERR_PC_RSP_LEN3)
2655 #define F_ERR_PC_RSP_LEN3    V_ERR_PC_RSP_LEN3(1U)
2656 
2657 #define S_ERR_PC_RSP_LEN2    10
2658 #define V_ERR_PC_RSP_LEN2(x) ((x) << S_ERR_PC_RSP_LEN2)
2659 #define F_ERR_PC_RSP_LEN2    V_ERR_PC_RSP_LEN2(1U)
2660 
2661 #define S_ERR_PC_RSP_LEN1    9
2662 #define V_ERR_PC_RSP_LEN1(x) ((x) << S_ERR_PC_RSP_LEN1)
2663 #define F_ERR_PC_RSP_LEN1    V_ERR_PC_RSP_LEN1(1U)
2664 
2665 #define S_ERR_PC_RSP_LEN0    8
2666 #define V_ERR_PC_RSP_LEN0(x) ((x) << S_ERR_PC_RSP_LEN0)
2667 #define F_ERR_PC_RSP_LEN0    V_ERR_PC_RSP_LEN0(1U)
2668 
2669 #define S_FATAL_ENQ2LL_VLD    7
2670 #define V_FATAL_ENQ2LL_VLD(x) ((x) << S_FATAL_ENQ2LL_VLD)
2671 #define F_FATAL_ENQ2LL_VLD    V_FATAL_ENQ2LL_VLD(1U)
2672 
2673 #define S_FATAL_LL_EMPTY    6
2674 #define V_FATAL_LL_EMPTY(x) ((x) << S_FATAL_LL_EMPTY)
2675 #define F_FATAL_LL_EMPTY    V_FATAL_LL_EMPTY(1U)
2676 
2677 #define S_FATAL_OFF_WDENQ    5
2678 #define V_FATAL_OFF_WDENQ(x) ((x) << S_FATAL_OFF_WDENQ)
2679 #define F_FATAL_OFF_WDENQ    V_FATAL_OFF_WDENQ(1U)
2680 
2681 #define S_FATAL_DEQ_DRDY    3
2682 #define M_FATAL_DEQ_DRDY    0x3U
2683 #define V_FATAL_DEQ_DRDY(x) ((x) << S_FATAL_DEQ_DRDY)
2684 #define G_FATAL_DEQ_DRDY(x) (((x) >> S_FATAL_DEQ_DRDY) & M_FATAL_DEQ_DRDY)
2685 
2686 #define S_FATAL_OUTP_DRDY    1
2687 #define M_FATAL_OUTP_DRDY    0x3U
2688 #define V_FATAL_OUTP_DRDY(x) ((x) << S_FATAL_OUTP_DRDY)
2689 #define G_FATAL_OUTP_DRDY(x) (((x) >> S_FATAL_OUTP_DRDY) & M_FATAL_OUTP_DRDY)
2690 
2691 #define S_FATAL_DEQ    0
2692 #define V_FATAL_DEQ(x) ((x) << S_FATAL_DEQ)
2693 #define F_FATAL_DEQ    V_FATAL_DEQ(1U)
2694 
2695 #define S_FATAL_DEQ0_DRDY    29
2696 #define M_FATAL_DEQ0_DRDY    0x7U
2697 #define V_FATAL_DEQ0_DRDY(x) ((x) << S_FATAL_DEQ0_DRDY)
2698 #define G_FATAL_DEQ0_DRDY(x) (((x) >> S_FATAL_DEQ0_DRDY) & M_FATAL_DEQ0_DRDY)
2699 
2700 #define S_FATAL_OUT0_DRDY    26
2701 #define M_FATAL_OUT0_DRDY    0x7U
2702 #define V_FATAL_OUT0_DRDY(x) ((x) << S_FATAL_OUT0_DRDY)
2703 #define G_FATAL_OUT0_DRDY(x) (((x) >> S_FATAL_OUT0_DRDY) & M_FATAL_OUT0_DRDY)
2704 
2705 #define S_IMSG_DBG3_STUCK    25
2706 #define V_IMSG_DBG3_STUCK(x) ((x) << S_IMSG_DBG3_STUCK)
2707 #define F_IMSG_DBG3_STUCK    V_IMSG_DBG3_STUCK(1U)
2708 
2709 #define S_IMSG_DBG2_STUCK    24
2710 #define V_IMSG_DBG2_STUCK(x) ((x) << S_IMSG_DBG2_STUCK)
2711 #define F_IMSG_DBG2_STUCK    V_IMSG_DBG2_STUCK(1U)
2712 
2713 #define S_IMSG_DBG1_STUCK    23
2714 #define V_IMSG_DBG1_STUCK(x) ((x) << S_IMSG_DBG1_STUCK)
2715 #define F_IMSG_DBG1_STUCK    V_IMSG_DBG1_STUCK(1U)
2716 
2717 #define S_IMSG_DBG0_STUCK    22
2718 #define V_IMSG_DBG0_STUCK(x) ((x) << S_IMSG_DBG0_STUCK)
2719 #define F_IMSG_DBG0_STUCK    V_IMSG_DBG0_STUCK(1U)
2720 
2721 #define S_FATAL_DEQ1_DRDY    3
2722 #define M_FATAL_DEQ1_DRDY    0x3U
2723 #define V_FATAL_DEQ1_DRDY(x) ((x) << S_FATAL_DEQ1_DRDY)
2724 #define G_FATAL_DEQ1_DRDY(x) (((x) >> S_FATAL_DEQ1_DRDY) & M_FATAL_DEQ1_DRDY)
2725 
2726 #define S_FATAL_OUT1_DRDY    1
2727 #define M_FATAL_OUT1_DRDY    0x3U
2728 #define V_FATAL_OUT1_DRDY(x) ((x) << S_FATAL_OUT1_DRDY)
2729 #define G_FATAL_OUT1_DRDY(x) (((x) >> S_FATAL_OUT1_DRDY) & M_FATAL_OUT1_DRDY)
2730 
2731 #define A_SGE_DOORBELL_THROTTLE_THRESHOLD 0x112c
2732 
2733 #define S_THROTTLE_THRESHOLD_FL    16
2734 #define M_THROTTLE_THRESHOLD_FL    0xfU
2735 #define V_THROTTLE_THRESHOLD_FL(x) ((x) << S_THROTTLE_THRESHOLD_FL)
2736 #define G_THROTTLE_THRESHOLD_FL(x) (((x) >> S_THROTTLE_THRESHOLD_FL) & M_THROTTLE_THRESHOLD_FL)
2737 
2738 #define S_THROTTLE_THRESHOLD_HP    12
2739 #define M_THROTTLE_THRESHOLD_HP    0xfU
2740 #define V_THROTTLE_THRESHOLD_HP(x) ((x) << S_THROTTLE_THRESHOLD_HP)
2741 #define G_THROTTLE_THRESHOLD_HP(x) (((x) >> S_THROTTLE_THRESHOLD_HP) & M_THROTTLE_THRESHOLD_HP)
2742 
2743 #define S_THROTTLE_THRESHOLD_LP    0
2744 #define M_THROTTLE_THRESHOLD_LP    0xfffU
2745 #define V_THROTTLE_THRESHOLD_LP(x) ((x) << S_THROTTLE_THRESHOLD_LP)
2746 #define G_THROTTLE_THRESHOLD_LP(x) (((x) >> S_THROTTLE_THRESHOLD_LP) & M_THROTTLE_THRESHOLD_LP)
2747 
2748 #define A_SGE_INT_ENABLE6 0x112c
2749 #define A_SGE_DBP_FETCH_THRESHOLD 0x1130
2750 
2751 #define S_DBP_FETCH_THRESHOLD_FL    21
2752 #define M_DBP_FETCH_THRESHOLD_FL    0xfU
2753 #define V_DBP_FETCH_THRESHOLD_FL(x) ((x) << S_DBP_FETCH_THRESHOLD_FL)
2754 #define G_DBP_FETCH_THRESHOLD_FL(x) (((x) >> S_DBP_FETCH_THRESHOLD_FL) & M_DBP_FETCH_THRESHOLD_FL)
2755 
2756 #define S_DBP_FETCH_THRESHOLD_HP    17
2757 #define M_DBP_FETCH_THRESHOLD_HP    0xfU
2758 #define V_DBP_FETCH_THRESHOLD_HP(x) ((x) << S_DBP_FETCH_THRESHOLD_HP)
2759 #define G_DBP_FETCH_THRESHOLD_HP(x) (((x) >> S_DBP_FETCH_THRESHOLD_HP) & M_DBP_FETCH_THRESHOLD_HP)
2760 
2761 #define S_DBP_FETCH_THRESHOLD_LP    5
2762 #define M_DBP_FETCH_THRESHOLD_LP    0xfffU
2763 #define V_DBP_FETCH_THRESHOLD_LP(x) ((x) << S_DBP_FETCH_THRESHOLD_LP)
2764 #define G_DBP_FETCH_THRESHOLD_LP(x) (((x) >> S_DBP_FETCH_THRESHOLD_LP) & M_DBP_FETCH_THRESHOLD_LP)
2765 
2766 #define S_DBP_FETCH_THRESHOLD_MODE    4
2767 #define V_DBP_FETCH_THRESHOLD_MODE(x) ((x) << S_DBP_FETCH_THRESHOLD_MODE)
2768 #define F_DBP_FETCH_THRESHOLD_MODE    V_DBP_FETCH_THRESHOLD_MODE(1U)
2769 
2770 #define S_DBP_FETCH_THRESHOLD_EN3    3
2771 #define V_DBP_FETCH_THRESHOLD_EN3(x) ((x) << S_DBP_FETCH_THRESHOLD_EN3)
2772 #define F_DBP_FETCH_THRESHOLD_EN3    V_DBP_FETCH_THRESHOLD_EN3(1U)
2773 
2774 #define S_DBP_FETCH_THRESHOLD_EN2    2
2775 #define V_DBP_FETCH_THRESHOLD_EN2(x) ((x) << S_DBP_FETCH_THRESHOLD_EN2)
2776 #define F_DBP_FETCH_THRESHOLD_EN2    V_DBP_FETCH_THRESHOLD_EN2(1U)
2777 
2778 #define S_DBP_FETCH_THRESHOLD_EN1    1
2779 #define V_DBP_FETCH_THRESHOLD_EN1(x) ((x) << S_DBP_FETCH_THRESHOLD_EN1)
2780 #define F_DBP_FETCH_THRESHOLD_EN1    V_DBP_FETCH_THRESHOLD_EN1(1U)
2781 
2782 #define S_DBP_FETCH_THRESHOLD_EN0    0
2783 #define V_DBP_FETCH_THRESHOLD_EN0(x) ((x) << S_DBP_FETCH_THRESHOLD_EN0)
2784 #define F_DBP_FETCH_THRESHOLD_EN0    V_DBP_FETCH_THRESHOLD_EN0(1U)
2785 
2786 #define A_SGE_DBP_FETCH_THRESHOLD_QUEUE 0x1134
2787 
2788 #define S_DBP_FETCH_THRESHOLD_IQ1    16
2789 #define M_DBP_FETCH_THRESHOLD_IQ1    0xffffU
2790 #define V_DBP_FETCH_THRESHOLD_IQ1(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ1)
2791 #define G_DBP_FETCH_THRESHOLD_IQ1(x) (((x) >> S_DBP_FETCH_THRESHOLD_IQ1) & M_DBP_FETCH_THRESHOLD_IQ1)
2792 
2793 #define S_DBP_FETCH_THRESHOLD_IQ0    0
2794 #define M_DBP_FETCH_THRESHOLD_IQ0    0xffffU
2795 #define V_DBP_FETCH_THRESHOLD_IQ0(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ0)
2796 #define G_DBP_FETCH_THRESHOLD_IQ0(x) (((x) >> S_DBP_FETCH_THRESHOLD_IQ0) & M_DBP_FETCH_THRESHOLD_IQ0)
2797 
2798 #define A_SGE_DBVFIFO_BADDR 0x1138
2799 #define A_SGE_DBVFIFO_SIZE 0x113c
2800 
2801 #define S_DBVFIFO_SIZE    6
2802 #define M_DBVFIFO_SIZE    0xfffU
2803 #define V_DBVFIFO_SIZE(x) ((x) << S_DBVFIFO_SIZE)
2804 #define G_DBVFIFO_SIZE(x) (((x) >> S_DBVFIFO_SIZE) & M_DBVFIFO_SIZE)
2805 
2806 #define S_T6_DBVFIFO_SIZE    0
2807 #define M_T6_DBVFIFO_SIZE    0x1fffU
2808 #define V_T6_DBVFIFO_SIZE(x) ((x) << S_T6_DBVFIFO_SIZE)
2809 #define G_T6_DBVFIFO_SIZE(x) (((x) >> S_T6_DBVFIFO_SIZE) & M_T6_DBVFIFO_SIZE)
2810 
2811 #define A_SGE_DBFIFO_STATUS3 0x1140
2812 
2813 #define S_LP_PTRS_EQUAL    21
2814 #define V_LP_PTRS_EQUAL(x) ((x) << S_LP_PTRS_EQUAL)
2815 #define F_LP_PTRS_EQUAL    V_LP_PTRS_EQUAL(1U)
2816 
2817 #define S_LP_SNAPHOT    20
2818 #define V_LP_SNAPHOT(x) ((x) << S_LP_SNAPHOT)
2819 #define F_LP_SNAPHOT    V_LP_SNAPHOT(1U)
2820 
2821 #define S_FL_INT_THRESH_LOW    16
2822 #define M_FL_INT_THRESH_LOW    0xfU
2823 #define V_FL_INT_THRESH_LOW(x) ((x) << S_FL_INT_THRESH_LOW)
2824 #define G_FL_INT_THRESH_LOW(x) (((x) >> S_FL_INT_THRESH_LOW) & M_FL_INT_THRESH_LOW)
2825 
2826 #define S_HP_INT_THRESH_LOW    12
2827 #define M_HP_INT_THRESH_LOW    0xfU
2828 #define V_HP_INT_THRESH_LOW(x) ((x) << S_HP_INT_THRESH_LOW)
2829 #define G_HP_INT_THRESH_LOW(x) (((x) >> S_HP_INT_THRESH_LOW) & M_HP_INT_THRESH_LOW)
2830 
2831 #define S_LP_INT_THRESH_LOW    0
2832 #define M_LP_INT_THRESH_LOW    0xfffU
2833 #define V_LP_INT_THRESH_LOW(x) ((x) << S_LP_INT_THRESH_LOW)
2834 #define G_LP_INT_THRESH_LOW(x) (((x) >> S_LP_INT_THRESH_LOW) & M_LP_INT_THRESH_LOW)
2835 
2836 #define A_SGE_CHANGESET 0x1144
2837 #define A_SGE_PC_RSP_ERROR 0x1148
2838 #define A_SGE_TBUF_CONTROL 0x114c
2839 
2840 #define S_DBPTBUFRSV1    9
2841 #define M_DBPTBUFRSV1    0x1ffU
2842 #define V_DBPTBUFRSV1(x) ((x) << S_DBPTBUFRSV1)
2843 #define G_DBPTBUFRSV1(x) (((x) >> S_DBPTBUFRSV1) & M_DBPTBUFRSV1)
2844 
2845 #define S_DBPTBUFRSV0    0
2846 #define M_DBPTBUFRSV0    0x1ffU
2847 #define V_DBPTBUFRSV0(x) ((x) << S_DBPTBUFRSV0)
2848 #define G_DBPTBUFRSV0(x) (((x) >> S_DBPTBUFRSV0) & M_DBPTBUFRSV0)
2849 
2850 #define A_SGE_TBUF_CONTROL0 0x114c
2851 #define A_SGE_TBUF_CONTROL1 0x1150
2852 
2853 #define S_DBPTBUFRSV3    9
2854 #define M_DBPTBUFRSV3    0x1ffU
2855 #define V_DBPTBUFRSV3(x) ((x) << S_DBPTBUFRSV3)
2856 #define G_DBPTBUFRSV3(x) (((x) >> S_DBPTBUFRSV3) & M_DBPTBUFRSV3)
2857 
2858 #define S_DBPTBUFRSV2    0
2859 #define M_DBPTBUFRSV2    0x1ffU
2860 #define V_DBPTBUFRSV2(x) ((x) << S_DBPTBUFRSV2)
2861 #define G_DBPTBUFRSV2(x) (((x) >> S_DBPTBUFRSV2) & M_DBPTBUFRSV2)
2862 
2863 #define A_SGE_TBUF_CONTROL2 0x1154
2864 
2865 #define S_DBPTBUFRSV5    9
2866 #define M_DBPTBUFRSV5    0x1ffU
2867 #define V_DBPTBUFRSV5(x) ((x) << S_DBPTBUFRSV5)
2868 #define G_DBPTBUFRSV5(x) (((x) >> S_DBPTBUFRSV5) & M_DBPTBUFRSV5)
2869 
2870 #define S_DBPTBUFRSV4    0
2871 #define M_DBPTBUFRSV4    0x1ffU
2872 #define V_DBPTBUFRSV4(x) ((x) << S_DBPTBUFRSV4)
2873 #define G_DBPTBUFRSV4(x) (((x) >> S_DBPTBUFRSV4) & M_DBPTBUFRSV4)
2874 
2875 #define A_SGE_TBUF_CONTROL3 0x1158
2876 
2877 #define S_DBPTBUFRSV7    9
2878 #define M_DBPTBUFRSV7    0x1ffU
2879 #define V_DBPTBUFRSV7(x) ((x) << S_DBPTBUFRSV7)
2880 #define G_DBPTBUFRSV7(x) (((x) >> S_DBPTBUFRSV7) & M_DBPTBUFRSV7)
2881 
2882 #define S_DBPTBUFRSV6    0
2883 #define M_DBPTBUFRSV6    0x1ffU
2884 #define V_DBPTBUFRSV6(x) ((x) << S_DBPTBUFRSV6)
2885 #define G_DBPTBUFRSV6(x) (((x) >> S_DBPTBUFRSV6) & M_DBPTBUFRSV6)
2886 
2887 #define A_SGE_TBUF_CONTROL4 0x115c
2888 
2889 #define S_DBPTBUFRSV9    9
2890 #define M_DBPTBUFRSV9    0x1ffU
2891 #define V_DBPTBUFRSV9(x) ((x) << S_DBPTBUFRSV9)
2892 #define G_DBPTBUFRSV9(x) (((x) >> S_DBPTBUFRSV9) & M_DBPTBUFRSV9)
2893 
2894 #define S_DBPTBUFRSV8    0
2895 #define M_DBPTBUFRSV8    0x1ffU
2896 #define V_DBPTBUFRSV8(x) ((x) << S_DBPTBUFRSV8)
2897 #define G_DBPTBUFRSV8(x) (((x) >> S_DBPTBUFRSV8) & M_DBPTBUFRSV8)
2898 
2899 #define A_SGE_PC0_REQ_BIST_CMD 0x1180
2900 #define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184
2901 #define A_SGE_PC1_REQ_BIST_CMD 0x1190
2902 #define A_SGE_PC1_REQ_BIST_ERROR_CNT 0x1194
2903 #define A_SGE_PC0_RSP_BIST_CMD 0x11a0
2904 #define A_SGE_PC0_RSP_BIST_ERROR_CNT 0x11a4
2905 #define A_SGE_PC1_RSP_BIST_CMD 0x11b0
2906 #define A_SGE_PC1_RSP_BIST_ERROR_CNT 0x11b4
2907 #define A_SGE_DBQ_TIMER_THRESH0 0x11b8
2908 
2909 #define S_TXTIMETH3    24
2910 #define M_TXTIMETH3    0x3fU
2911 #define V_TXTIMETH3(x) ((x) << S_TXTIMETH3)
2912 #define G_TXTIMETH3(x) (((x) >> S_TXTIMETH3) & M_TXTIMETH3)
2913 
2914 #define S_TXTIMETH2    16
2915 #define M_TXTIMETH2    0x3fU
2916 #define V_TXTIMETH2(x) ((x) << S_TXTIMETH2)
2917 #define G_TXTIMETH2(x) (((x) >> S_TXTIMETH2) & M_TXTIMETH2)
2918 
2919 #define S_TXTIMETH1    8
2920 #define M_TXTIMETH1    0x3fU
2921 #define V_TXTIMETH1(x) ((x) << S_TXTIMETH1)
2922 #define G_TXTIMETH1(x) (((x) >> S_TXTIMETH1) & M_TXTIMETH1)
2923 
2924 #define S_TXTIMETH0    0
2925 #define M_TXTIMETH0    0x3fU
2926 #define V_TXTIMETH0(x) ((x) << S_TXTIMETH0)
2927 #define G_TXTIMETH0(x) (((x) >> S_TXTIMETH0) & M_TXTIMETH0)
2928 
2929 #define A_SGE_DBQ_TIMER_THRESH1 0x11bc
2930 
2931 #define S_TXTIMETH7    24
2932 #define M_TXTIMETH7    0x3fU
2933 #define V_TXTIMETH7(x) ((x) << S_TXTIMETH7)
2934 #define G_TXTIMETH7(x) (((x) >> S_TXTIMETH7) & M_TXTIMETH7)
2935 
2936 #define S_TXTIMETH6    16
2937 #define M_TXTIMETH6    0x3fU
2938 #define V_TXTIMETH6(x) ((x) << S_TXTIMETH6)
2939 #define G_TXTIMETH6(x) (((x) >> S_TXTIMETH6) & M_TXTIMETH6)
2940 
2941 #define S_TXTIMETH5    8
2942 #define M_TXTIMETH5    0x3fU
2943 #define V_TXTIMETH5(x) ((x) << S_TXTIMETH5)
2944 #define G_TXTIMETH5(x) (((x) >> S_TXTIMETH5) & M_TXTIMETH5)
2945 
2946 #define S_TXTIMETH4    0
2947 #define M_TXTIMETH4    0x3fU
2948 #define V_TXTIMETH4(x) ((x) << S_TXTIMETH4)
2949 #define G_TXTIMETH4(x) (((x) >> S_TXTIMETH4) & M_TXTIMETH4)
2950 
2951 #define A_SGE_DBQ_TIMER_CONFIG 0x11c0
2952 
2953 #define S_DBQ_TIMER_OP    0
2954 #define M_DBQ_TIMER_OP    0xffU
2955 #define V_DBQ_TIMER_OP(x) ((x) << S_DBQ_TIMER_OP)
2956 #define G_DBQ_TIMER_OP(x) (((x) >> S_DBQ_TIMER_OP) & M_DBQ_TIMER_OP)
2957 
2958 #define A_SGE_DBQ_TIMER_DBG 0x11c4
2959 
2960 #define S_DBQ_TIMER_CMD    31
2961 #define V_DBQ_TIMER_CMD(x) ((x) << S_DBQ_TIMER_CMD)
2962 #define F_DBQ_TIMER_CMD    V_DBQ_TIMER_CMD(1U)
2963 
2964 #define S_DBQ_TIMER_INDEX    24
2965 #define M_DBQ_TIMER_INDEX    0x3fU
2966 #define V_DBQ_TIMER_INDEX(x) ((x) << S_DBQ_TIMER_INDEX)
2967 #define G_DBQ_TIMER_INDEX(x) (((x) >> S_DBQ_TIMER_INDEX) & M_DBQ_TIMER_INDEX)
2968 
2969 #define S_DBQ_TIMER_QCNT    0
2970 #define M_DBQ_TIMER_QCNT    0x1ffffU
2971 #define V_DBQ_TIMER_QCNT(x) ((x) << S_DBQ_TIMER_QCNT)
2972 #define G_DBQ_TIMER_QCNT(x) (((x) >> S_DBQ_TIMER_QCNT) & M_DBQ_TIMER_QCNT)
2973 
2974 #define A_SGE_INT_CAUSE8 0x11c8
2975 
2976 #define S_TRACE_RXPERR    8
2977 #define V_TRACE_RXPERR(x) ((x) << S_TRACE_RXPERR)
2978 #define F_TRACE_RXPERR    V_TRACE_RXPERR(1U)
2979 
2980 #define S_U3_RXPERR    7
2981 #define V_U3_RXPERR(x) ((x) << S_U3_RXPERR)
2982 #define F_U3_RXPERR    V_U3_RXPERR(1U)
2983 
2984 #define S_U2_RXPERR    6
2985 #define V_U2_RXPERR(x) ((x) << S_U2_RXPERR)
2986 #define F_U2_RXPERR    V_U2_RXPERR(1U)
2987 
2988 #define S_U1_RXPERR    5
2989 #define V_U1_RXPERR(x) ((x) << S_U1_RXPERR)
2990 #define F_U1_RXPERR    V_U1_RXPERR(1U)
2991 
2992 #define S_U0_RXPERR    4
2993 #define V_U0_RXPERR(x) ((x) << S_U0_RXPERR)
2994 #define F_U0_RXPERR    V_U0_RXPERR(1U)
2995 
2996 #define S_T3_RXPERR    3
2997 #define V_T3_RXPERR(x) ((x) << S_T3_RXPERR)
2998 #define F_T3_RXPERR    V_T3_RXPERR(1U)
2999 
3000 #define S_T2_RXPERR    2
3001 #define V_T2_RXPERR(x) ((x) << S_T2_RXPERR)
3002 #define F_T2_RXPERR    V_T2_RXPERR(1U)
3003 
3004 #define S_T1_RXPERR    1
3005 #define V_T1_RXPERR(x) ((x) << S_T1_RXPERR)
3006 #define F_T1_RXPERR    V_T1_RXPERR(1U)
3007 
3008 #define S_T0_RXPERR    0
3009 #define V_T0_RXPERR(x) ((x) << S_T0_RXPERR)
3010 #define F_T0_RXPERR    V_T0_RXPERR(1U)
3011 
3012 #define A_SGE_INT_ENABLE8 0x11cc
3013 #define A_SGE_PERR_ENABLE8 0x11d0
3014 #define A_SGE_CTXT_CMD 0x11fc
3015 
3016 #define S_BUSY    31
3017 #define V_BUSY(x) ((x) << S_BUSY)
3018 #define F_BUSY    V_BUSY(1U)
3019 
3020 #define S_CTXTOP    28
3021 #define M_CTXTOP    0x3U
3022 #define V_CTXTOP(x) ((x) << S_CTXTOP)
3023 #define G_CTXTOP(x) (((x) >> S_CTXTOP) & M_CTXTOP)
3024 
3025 #define S_CTXTTYPE    24
3026 #define M_CTXTTYPE    0x3U
3027 #define V_CTXTTYPE(x) ((x) << S_CTXTTYPE)
3028 #define G_CTXTTYPE(x) (((x) >> S_CTXTTYPE) & M_CTXTTYPE)
3029 
3030 #define S_CTXTQID    0
3031 #define M_CTXTQID    0x1ffffU
3032 #define V_CTXTQID(x) ((x) << S_CTXTQID)
3033 #define G_CTXTQID(x) (((x) >> S_CTXTQID) & M_CTXTQID)
3034 
3035 #define A_SGE_CTXT_DATA0 0x1200
3036 #define A_SGE_CTXT_DATA1 0x1204
3037 #define A_SGE_CTXT_DATA2 0x1208
3038 #define A_SGE_CTXT_DATA3 0x120c
3039 #define A_SGE_CTXT_DATA4 0x1210
3040 #define A_SGE_CTXT_DATA5 0x1214
3041 #define A_SGE_CTXT_DATA6 0x1218
3042 
3043 #define S_DATA_UNUSED    7
3044 #define M_DATA_UNUSED    0x1ffffffU
3045 #define V_DATA_UNUSED(x) ((x) << S_DATA_UNUSED)
3046 #define G_DATA_UNUSED(x) (((x) >> S_DATA_UNUSED) & M_DATA_UNUSED)
3047 
3048 #define S_DATA6    0
3049 #define M_DATA6    0x7fU
3050 #define V_DATA6(x) ((x) << S_DATA6)
3051 #define G_DATA6(x) (((x) >> S_DATA6) & M_DATA6)
3052 
3053 #define A_SGE_CTXT_DATA7 0x121c
3054 #define A_SGE_CTXT_MASK0 0x1220
3055 #define A_SGE_CTXT_MASK1 0x1224
3056 #define A_SGE_CTXT_MASK2 0x1228
3057 #define A_SGE_CTXT_MASK3 0x122c
3058 #define A_SGE_CTXT_MASK4 0x1230
3059 #define A_SGE_CTXT_MASK5 0x1234
3060 #define A_SGE_CTXT_MASK6 0x1238
3061 
3062 #define S_MASK_UNUSED    7
3063 #define M_MASK_UNUSED    0x1ffffffU
3064 #define V_MASK_UNUSED(x) ((x) << S_MASK_UNUSED)
3065 #define G_MASK_UNUSED(x) (((x) >> S_MASK_UNUSED) & M_MASK_UNUSED)
3066 
3067 #define S_MASK    0
3068 #define M_MASK    0x7fU
3069 #define V_MASK(x) ((x) << S_MASK)
3070 #define G_MASK(x) (((x) >> S_MASK) & M_MASK)
3071 
3072 #define A_SGE_CTXT_MASK7 0x123c
3073 #define A_SGE_QBASE_MAP0 0x1240
3074 
3075 #define S_EGRESS0_SIZE    24
3076 #define M_EGRESS0_SIZE    0x1fU
3077 #define V_EGRESS0_SIZE(x) ((x) << S_EGRESS0_SIZE)
3078 #define G_EGRESS0_SIZE(x) (((x) >> S_EGRESS0_SIZE) & M_EGRESS0_SIZE)
3079 
3080 #define S_EGRESS1_SIZE    16
3081 #define M_EGRESS1_SIZE    0x1fU
3082 #define V_EGRESS1_SIZE(x) ((x) << S_EGRESS1_SIZE)
3083 #define G_EGRESS1_SIZE(x) (((x) >> S_EGRESS1_SIZE) & M_EGRESS1_SIZE)
3084 
3085 #define S_INGRESS0_SIZE    8
3086 #define M_INGRESS0_SIZE    0x1fU
3087 #define V_INGRESS0_SIZE(x) ((x) << S_INGRESS0_SIZE)
3088 #define G_INGRESS0_SIZE(x) (((x) >> S_INGRESS0_SIZE) & M_INGRESS0_SIZE)
3089 
3090 #define S_DESTINATION    31
3091 #define V_DESTINATION(x) ((x) << S_DESTINATION)
3092 #define F_DESTINATION    V_DESTINATION(1U)
3093 
3094 #define A_SGE_QBASE_MAP1 0x1244
3095 
3096 #define S_EGRESS0_BASE    0
3097 #define M_EGRESS0_BASE    0x1ffffU
3098 #define V_EGRESS0_BASE(x) ((x) << S_EGRESS0_BASE)
3099 #define G_EGRESS0_BASE(x) (((x) >> S_EGRESS0_BASE) & M_EGRESS0_BASE)
3100 
3101 #define A_SGE_QBASE_MAP2 0x1248
3102 
3103 #define S_EGRESS1_BASE    0
3104 #define M_EGRESS1_BASE    0x1ffffU
3105 #define V_EGRESS1_BASE(x) ((x) << S_EGRESS1_BASE)
3106 #define G_EGRESS1_BASE(x) (((x) >> S_EGRESS1_BASE) & M_EGRESS1_BASE)
3107 
3108 #define A_SGE_QBASE_MAP3 0x124c
3109 
3110 #define S_INGRESS1_BASE_256VF    16
3111 #define M_INGRESS1_BASE_256VF    0xffffU
3112 #define V_INGRESS1_BASE_256VF(x) ((x) << S_INGRESS1_BASE_256VF)
3113 #define G_INGRESS1_BASE_256VF(x) (((x) >> S_INGRESS1_BASE_256VF) & M_INGRESS1_BASE_256VF)
3114 
3115 #define S_INGRESS0_BASE    0
3116 #define M_INGRESS0_BASE    0xffffU
3117 #define V_INGRESS0_BASE(x) ((x) << S_INGRESS0_BASE)
3118 #define G_INGRESS0_BASE(x) (((x) >> S_INGRESS0_BASE) & M_INGRESS0_BASE)
3119 
3120 #define A_SGE_QBASE_INDEX 0x1250
3121 
3122 #define S_QIDX    0
3123 #define M_QIDX    0x1ffU
3124 #define V_QIDX(x) ((x) << S_QIDX)
3125 #define G_QIDX(x) (((x) >> S_QIDX) & M_QIDX)
3126 
3127 #define A_SGE_CONM_CTRL2 0x1254
3128 
3129 #define S_FLMTHRESHPACK    8
3130 #define M_FLMTHRESHPACK    0x7fU
3131 #define V_FLMTHRESHPACK(x) ((x) << S_FLMTHRESHPACK)
3132 #define G_FLMTHRESHPACK(x) (((x) >> S_FLMTHRESHPACK) & M_FLMTHRESHPACK)
3133 
3134 #define S_FLMTHRESH    0
3135 #define M_FLMTHRESH    0x7fU
3136 #define V_FLMTHRESH(x) ((x) << S_FLMTHRESH)
3137 #define G_FLMTHRESH(x) (((x) >> S_FLMTHRESH) & M_FLMTHRESH)
3138 
3139 #define S_CONENMIDDLE    7
3140 #define V_CONENMIDDLE(x) ((x) << S_CONENMIDDLE)
3141 #define F_CONENMIDDLE    V_CONENMIDDLE(1U)
3142 
3143 #define A_SGE_DEBUG_CONM 0x1258
3144 
3145 #define S_MPS_CH_CNG    16
3146 #define M_MPS_CH_CNG    0xffffU
3147 #define V_MPS_CH_CNG(x) ((x) << S_MPS_CH_CNG)
3148 #define G_MPS_CH_CNG(x) (((x) >> S_MPS_CH_CNG) & M_MPS_CH_CNG)
3149 
3150 #define S_TP_CH_CNG    14
3151 #define M_TP_CH_CNG    0x3U
3152 #define V_TP_CH_CNG(x) ((x) << S_TP_CH_CNG)
3153 #define G_TP_CH_CNG(x) (((x) >> S_TP_CH_CNG) & M_TP_CH_CNG)
3154 
3155 #define S_ST_CONG    12
3156 #define M_ST_CONG    0x3U
3157 #define V_ST_CONG(x) ((x) << S_ST_CONG)
3158 #define G_ST_CONG(x) (((x) >> S_ST_CONG) & M_ST_CONG)
3159 
3160 #define S_LAST_XOFF    10
3161 #define V_LAST_XOFF(x) ((x) << S_LAST_XOFF)
3162 #define F_LAST_XOFF    V_LAST_XOFF(1U)
3163 
3164 #define S_LAST_QID    0
3165 #define M_LAST_QID    0x3ffU
3166 #define V_LAST_QID(x) ((x) << S_LAST_QID)
3167 #define G_LAST_QID(x) (((x) >> S_LAST_QID) & M_LAST_QID)
3168 
3169 #define S_CH_CNG    16
3170 #define M_CH_CNG    0xffffU
3171 #define V_CH_CNG(x) ((x) << S_CH_CNG)
3172 #define G_CH_CNG(x) (((x) >> S_CH_CNG) & M_CH_CNG)
3173 
3174 #define S_CH_SEL    14
3175 #define M_CH_SEL    0x3U
3176 #define V_CH_SEL(x) ((x) << S_CH_SEL)
3177 #define G_CH_SEL(x) (((x) >> S_CH_SEL) & M_CH_SEL)
3178 
3179 #define A_SGE_DBG_QUEUE_STAT0_CTRL 0x125c
3180 
3181 #define S_IMSG_GTS_SEL    18
3182 #define V_IMSG_GTS_SEL(x) ((x) << S_IMSG_GTS_SEL)
3183 #define F_IMSG_GTS_SEL    V_IMSG_GTS_SEL(1U)
3184 
3185 #define S_MGT_SEL    17
3186 #define V_MGT_SEL(x) ((x) << S_MGT_SEL)
3187 #define F_MGT_SEL    V_MGT_SEL(1U)
3188 
3189 #define S_DB_GTS_QID    0
3190 #define M_DB_GTS_QID    0x1ffffU
3191 #define V_DB_GTS_QID(x) ((x) << S_DB_GTS_QID)
3192 #define G_DB_GTS_QID(x) (((x) >> S_DB_GTS_QID) & M_DB_GTS_QID)
3193 
3194 #define A_SGE_DBG_QUEUE_STAT1_CTRL 0x1260
3195 #define A_SGE_DBG_QUEUE_STAT0 0x1264
3196 #define A_SGE_DBG_QUEUE_STAT1 0x1268
3197 #define A_SGE_DBG_BAR2_PKT_CNT 0x126c
3198 #define A_SGE_DBG_DB_PKT_CNT 0x1270
3199 #define A_SGE_DBG_GTS_PKT_CNT 0x1274
3200 #define A_SGE_DEBUG_DATA_HIGH_INDEX_16 0x1278
3201 #define A_SGE_DEBUG_DATA_HIGH_INDEX_0 0x1280
3202 
3203 #define S_CIM_WM    24
3204 #define M_CIM_WM    0x3U
3205 #define V_CIM_WM(x) ((x) << S_CIM_WM)
3206 #define G_CIM_WM(x) (((x) >> S_CIM_WM) & M_CIM_WM)
3207 
3208 #define S_DEBUG_UP_SOP_CNT    20
3209 #define M_DEBUG_UP_SOP_CNT    0xfU
3210 #define V_DEBUG_UP_SOP_CNT(x) ((x) << S_DEBUG_UP_SOP_CNT)
3211 #define G_DEBUG_UP_SOP_CNT(x) (((x) >> S_DEBUG_UP_SOP_CNT) & M_DEBUG_UP_SOP_CNT)
3212 
3213 #define S_DEBUG_UP_EOP_CNT    16
3214 #define M_DEBUG_UP_EOP_CNT    0xfU
3215 #define V_DEBUG_UP_EOP_CNT(x) ((x) << S_DEBUG_UP_EOP_CNT)
3216 #define G_DEBUG_UP_EOP_CNT(x) (((x) >> S_DEBUG_UP_EOP_CNT) & M_DEBUG_UP_EOP_CNT)
3217 
3218 #define S_DEBUG_CIM_SOP1_CNT    12
3219 #define M_DEBUG_CIM_SOP1_CNT    0xfU
3220 #define V_DEBUG_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CIM_SOP1_CNT)
3221 #define G_DEBUG_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CIM_SOP1_CNT) & M_DEBUG_CIM_SOP1_CNT)
3222 
3223 #define S_DEBUG_CIM_EOP1_CNT    8
3224 #define M_DEBUG_CIM_EOP1_CNT    0xfU
3225 #define V_DEBUG_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CIM_EOP1_CNT)
3226 #define G_DEBUG_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CIM_EOP1_CNT) & M_DEBUG_CIM_EOP1_CNT)
3227 
3228 #define S_DEBUG_CIM_SOP0_CNT    4
3229 #define M_DEBUG_CIM_SOP0_CNT    0xfU
3230 #define V_DEBUG_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CIM_SOP0_CNT)
3231 #define G_DEBUG_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CIM_SOP0_CNT) & M_DEBUG_CIM_SOP0_CNT)
3232 
3233 #define S_DEBUG_CIM_EOP0_CNT    0
3234 #define M_DEBUG_CIM_EOP0_CNT    0xfU
3235 #define V_DEBUG_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CIM_EOP0_CNT)
3236 #define G_DEBUG_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CIM_EOP0_CNT) & M_DEBUG_CIM_EOP0_CNT)
3237 
3238 #define S_DEBUG_BAR2_SOP_CNT    28
3239 #define M_DEBUG_BAR2_SOP_CNT    0xfU
3240 #define V_DEBUG_BAR2_SOP_CNT(x) ((x) << S_DEBUG_BAR2_SOP_CNT)
3241 #define G_DEBUG_BAR2_SOP_CNT(x) (((x) >> S_DEBUG_BAR2_SOP_CNT) & M_DEBUG_BAR2_SOP_CNT)
3242 
3243 #define S_DEBUG_BAR2_EOP_CNT    24
3244 #define M_DEBUG_BAR2_EOP_CNT    0xfU
3245 #define V_DEBUG_BAR2_EOP_CNT(x) ((x) << S_DEBUG_BAR2_EOP_CNT)
3246 #define G_DEBUG_BAR2_EOP_CNT(x) (((x) >> S_DEBUG_BAR2_EOP_CNT) & M_DEBUG_BAR2_EOP_CNT)
3247 
3248 #define A_SGE_DEBUG_DATA_HIGH_INDEX_1 0x1284
3249 
3250 #define S_DEBUG_T_RX_SOP1_CNT    28
3251 #define M_DEBUG_T_RX_SOP1_CNT    0xfU
3252 #define V_DEBUG_T_RX_SOP1_CNT(x) ((x) << S_DEBUG_T_RX_SOP1_CNT)
3253 #define G_DEBUG_T_RX_SOP1_CNT(x) (((x) >> S_DEBUG_T_RX_SOP1_CNT) & M_DEBUG_T_RX_SOP1_CNT)
3254 
3255 #define S_DEBUG_T_RX_EOP1_CNT    24
3256 #define M_DEBUG_T_RX_EOP1_CNT    0xfU
3257 #define V_DEBUG_T_RX_EOP1_CNT(x) ((x) << S_DEBUG_T_RX_EOP1_CNT)
3258 #define G_DEBUG_T_RX_EOP1_CNT(x) (((x) >> S_DEBUG_T_RX_EOP1_CNT) & M_DEBUG_T_RX_EOP1_CNT)
3259 
3260 #define S_DEBUG_T_RX_SOP0_CNT    20
3261 #define M_DEBUG_T_RX_SOP0_CNT    0xfU
3262 #define V_DEBUG_T_RX_SOP0_CNT(x) ((x) << S_DEBUG_T_RX_SOP0_CNT)
3263 #define G_DEBUG_T_RX_SOP0_CNT(x) (((x) >> S_DEBUG_T_RX_SOP0_CNT) & M_DEBUG_T_RX_SOP0_CNT)
3264 
3265 #define S_DEBUG_T_RX_EOP0_CNT    16
3266 #define M_DEBUG_T_RX_EOP0_CNT    0xfU
3267 #define V_DEBUG_T_RX_EOP0_CNT(x) ((x) << S_DEBUG_T_RX_EOP0_CNT)
3268 #define G_DEBUG_T_RX_EOP0_CNT(x) (((x) >> S_DEBUG_T_RX_EOP0_CNT) & M_DEBUG_T_RX_EOP0_CNT)
3269 
3270 #define S_DEBUG_U_RX_SOP1_CNT    12
3271 #define M_DEBUG_U_RX_SOP1_CNT    0xfU
3272 #define V_DEBUG_U_RX_SOP1_CNT(x) ((x) << S_DEBUG_U_RX_SOP1_CNT)
3273 #define G_DEBUG_U_RX_SOP1_CNT(x) (((x) >> S_DEBUG_U_RX_SOP1_CNT) & M_DEBUG_U_RX_SOP1_CNT)
3274 
3275 #define S_DEBUG_U_RX_EOP1_CNT    8
3276 #define M_DEBUG_U_RX_EOP1_CNT    0xfU
3277 #define V_DEBUG_U_RX_EOP1_CNT(x) ((x) << S_DEBUG_U_RX_EOP1_CNT)
3278 #define G_DEBUG_U_RX_EOP1_CNT(x) (((x) >> S_DEBUG_U_RX_EOP1_CNT) & M_DEBUG_U_RX_EOP1_CNT)
3279 
3280 #define S_DEBUG_U_RX_SOP0_CNT    4
3281 #define M_DEBUG_U_RX_SOP0_CNT    0xfU
3282 #define V_DEBUG_U_RX_SOP0_CNT(x) ((x) << S_DEBUG_U_RX_SOP0_CNT)
3283 #define G_DEBUG_U_RX_SOP0_CNT(x) (((x) >> S_DEBUG_U_RX_SOP0_CNT) & M_DEBUG_U_RX_SOP0_CNT)
3284 
3285 #define S_DEBUG_U_RX_EOP0_CNT    0
3286 #define M_DEBUG_U_RX_EOP0_CNT    0xfU
3287 #define V_DEBUG_U_RX_EOP0_CNT(x) ((x) << S_DEBUG_U_RX_EOP0_CNT)
3288 #define G_DEBUG_U_RX_EOP0_CNT(x) (((x) >> S_DEBUG_U_RX_EOP0_CNT) & M_DEBUG_U_RX_EOP0_CNT)
3289 
3290 #define A_SGE_DEBUG_DATA_HIGH_INDEX_2 0x1288
3291 
3292 #define S_DEBUG_UD_RX_SOP3_CNT    28
3293 #define M_DEBUG_UD_RX_SOP3_CNT    0xfU
3294 #define V_DEBUG_UD_RX_SOP3_CNT(x) ((x) << S_DEBUG_UD_RX_SOP3_CNT)
3295 #define G_DEBUG_UD_RX_SOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP3_CNT) & M_DEBUG_UD_RX_SOP3_CNT)
3296 
3297 #define S_DEBUG_UD_RX_EOP3_CNT    24
3298 #define M_DEBUG_UD_RX_EOP3_CNT    0xfU
3299 #define V_DEBUG_UD_RX_EOP3_CNT(x) ((x) << S_DEBUG_UD_RX_EOP3_CNT)
3300 #define G_DEBUG_UD_RX_EOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP3_CNT) & M_DEBUG_UD_RX_EOP3_CNT)
3301 
3302 #define S_DEBUG_UD_RX_SOP2_CNT    20
3303 #define M_DEBUG_UD_RX_SOP2_CNT    0xfU
3304 #define V_DEBUG_UD_RX_SOP2_CNT(x) ((x) << S_DEBUG_UD_RX_SOP2_CNT)
3305 #define G_DEBUG_UD_RX_SOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP2_CNT) & M_DEBUG_UD_RX_SOP2_CNT)
3306 
3307 #define S_DEBUG_UD_RX_EOP2_CNT    16
3308 #define M_DEBUG_UD_RX_EOP2_CNT    0xfU
3309 #define V_DEBUG_UD_RX_EOP2_CNT(x) ((x) << S_DEBUG_UD_RX_EOP2_CNT)
3310 #define G_DEBUG_UD_RX_EOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP2_CNT) & M_DEBUG_UD_RX_EOP2_CNT)
3311 
3312 #define S_DEBUG_UD_RX_SOP1_CNT    12
3313 #define M_DEBUG_UD_RX_SOP1_CNT    0xfU
3314 #define V_DEBUG_UD_RX_SOP1_CNT(x) ((x) << S_DEBUG_UD_RX_SOP1_CNT)
3315 #define G_DEBUG_UD_RX_SOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP1_CNT) & M_DEBUG_UD_RX_SOP1_CNT)
3316 
3317 #define S_DEBUG_UD_RX_EOP1_CNT    8
3318 #define M_DEBUG_UD_RX_EOP1_CNT    0xfU
3319 #define V_DEBUG_UD_RX_EOP1_CNT(x) ((x) << S_DEBUG_UD_RX_EOP1_CNT)
3320 #define G_DEBUG_UD_RX_EOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP1_CNT) & M_DEBUG_UD_RX_EOP1_CNT)
3321 
3322 #define S_DEBUG_UD_RX_SOP0_CNT    4
3323 #define M_DEBUG_UD_RX_SOP0_CNT    0xfU
3324 #define V_DEBUG_UD_RX_SOP0_CNT(x) ((x) << S_DEBUG_UD_RX_SOP0_CNT)
3325 #define G_DEBUG_UD_RX_SOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP0_CNT) & M_DEBUG_UD_RX_SOP0_CNT)
3326 
3327 #define S_DEBUG_UD_RX_EOP0_CNT    0
3328 #define M_DEBUG_UD_RX_EOP0_CNT    0xfU
3329 #define V_DEBUG_UD_RX_EOP0_CNT(x) ((x) << S_DEBUG_UD_RX_EOP0_CNT)
3330 #define G_DEBUG_UD_RX_EOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP0_CNT) & M_DEBUG_UD_RX_EOP0_CNT)
3331 
3332 #define S_DBG_TBUF_USED1    9
3333 #define M_DBG_TBUF_USED1    0x1ffU
3334 #define V_DBG_TBUF_USED1(x) ((x) << S_DBG_TBUF_USED1)
3335 #define G_DBG_TBUF_USED1(x) (((x) >> S_DBG_TBUF_USED1) & M_DBG_TBUF_USED1)
3336 
3337 #define S_DBG_TBUF_USED0    0
3338 #define M_DBG_TBUF_USED0    0x1ffU
3339 #define V_DBG_TBUF_USED0(x) ((x) << S_DBG_TBUF_USED0)
3340 #define G_DBG_TBUF_USED0(x) (((x) >> S_DBG_TBUF_USED0) & M_DBG_TBUF_USED0)
3341 
3342 #define A_SGE_DEBUG_DATA_HIGH_INDEX_3 0x128c
3343 
3344 #define S_DEBUG_U_TX_SOP3_CNT    28
3345 #define M_DEBUG_U_TX_SOP3_CNT    0xfU
3346 #define V_DEBUG_U_TX_SOP3_CNT(x) ((x) << S_DEBUG_U_TX_SOP3_CNT)
3347 #define G_DEBUG_U_TX_SOP3_CNT(x) (((x) >> S_DEBUG_U_TX_SOP3_CNT) & M_DEBUG_U_TX_SOP3_CNT)
3348 
3349 #define S_DEBUG_U_TX_EOP3_CNT    24
3350 #define M_DEBUG_U_TX_EOP3_CNT    0xfU
3351 #define V_DEBUG_U_TX_EOP3_CNT(x) ((x) << S_DEBUG_U_TX_EOP3_CNT)
3352 #define G_DEBUG_U_TX_EOP3_CNT(x) (((x) >> S_DEBUG_U_TX_EOP3_CNT) & M_DEBUG_U_TX_EOP3_CNT)
3353 
3354 #define S_DEBUG_U_TX_SOP2_CNT    20
3355 #define M_DEBUG_U_TX_SOP2_CNT    0xfU
3356 #define V_DEBUG_U_TX_SOP2_CNT(x) ((x) << S_DEBUG_U_TX_SOP2_CNT)
3357 #define G_DEBUG_U_TX_SOP2_CNT(x) (((x) >> S_DEBUG_U_TX_SOP2_CNT) & M_DEBUG_U_TX_SOP2_CNT)
3358 
3359 #define S_DEBUG_U_TX_EOP2_CNT    16
3360 #define M_DEBUG_U_TX_EOP2_CNT    0xfU
3361 #define V_DEBUG_U_TX_EOP2_CNT(x) ((x) << S_DEBUG_U_TX_EOP2_CNT)
3362 #define G_DEBUG_U_TX_EOP2_CNT(x) (((x) >> S_DEBUG_U_TX_EOP2_CNT) & M_DEBUG_U_TX_EOP2_CNT)
3363 
3364 #define S_DEBUG_U_TX_SOP1_CNT    12
3365 #define M_DEBUG_U_TX_SOP1_CNT    0xfU
3366 #define V_DEBUG_U_TX_SOP1_CNT(x) ((x) << S_DEBUG_U_TX_SOP1_CNT)
3367 #define G_DEBUG_U_TX_SOP1_CNT(x) (((x) >> S_DEBUG_U_TX_SOP1_CNT) & M_DEBUG_U_TX_SOP1_CNT)
3368 
3369 #define S_DEBUG_U_TX_EOP1_CNT    8
3370 #define M_DEBUG_U_TX_EOP1_CNT    0xfU
3371 #define V_DEBUG_U_TX_EOP1_CNT(x) ((x) << S_DEBUG_U_TX_EOP1_CNT)
3372 #define G_DEBUG_U_TX_EOP1_CNT(x) (((x) >> S_DEBUG_U_TX_EOP1_CNT) & M_DEBUG_U_TX_EOP1_CNT)
3373 
3374 #define S_DEBUG_U_TX_SOP0_CNT    4
3375 #define M_DEBUG_U_TX_SOP0_CNT    0xfU
3376 #define V_DEBUG_U_TX_SOP0_CNT(x) ((x) << S_DEBUG_U_TX_SOP0_CNT)
3377 #define G_DEBUG_U_TX_SOP0_CNT(x) (((x) >> S_DEBUG_U_TX_SOP0_CNT) & M_DEBUG_U_TX_SOP0_CNT)
3378 
3379 #define S_DEBUG_U_TX_EOP0_CNT    0
3380 #define M_DEBUG_U_TX_EOP0_CNT    0xfU
3381 #define V_DEBUG_U_TX_EOP0_CNT(x) ((x) << S_DEBUG_U_TX_EOP0_CNT)
3382 #define G_DEBUG_U_TX_EOP0_CNT(x) (((x) >> S_DEBUG_U_TX_EOP0_CNT) & M_DEBUG_U_TX_EOP0_CNT)
3383 
3384 #define A_SGE_DEBUG1_DBP_THREAD 0x128c
3385 
3386 #define S_WR_DEQ_CNT    12
3387 #define M_WR_DEQ_CNT    0xfU
3388 #define V_WR_DEQ_CNT(x) ((x) << S_WR_DEQ_CNT)
3389 #define G_WR_DEQ_CNT(x) (((x) >> S_WR_DEQ_CNT) & M_WR_DEQ_CNT)
3390 
3391 #define S_WR_ENQ_CNT    8
3392 #define M_WR_ENQ_CNT    0xfU
3393 #define V_WR_ENQ_CNT(x) ((x) << S_WR_ENQ_CNT)
3394 #define G_WR_ENQ_CNT(x) (((x) >> S_WR_ENQ_CNT) & M_WR_ENQ_CNT)
3395 
3396 #define S_FL_DEQ_CNT    4
3397 #define M_FL_DEQ_CNT    0xfU
3398 #define V_FL_DEQ_CNT(x) ((x) << S_FL_DEQ_CNT)
3399 #define G_FL_DEQ_CNT(x) (((x) >> S_FL_DEQ_CNT) & M_FL_DEQ_CNT)
3400 
3401 #define S_FL_ENQ_CNT    0
3402 #define M_FL_ENQ_CNT    0xfU
3403 #define V_FL_ENQ_CNT(x) ((x) << S_FL_ENQ_CNT)
3404 #define G_FL_ENQ_CNT(x) (((x) >> S_FL_ENQ_CNT) & M_FL_ENQ_CNT)
3405 
3406 #define A_SGE_DEBUG_DATA_HIGH_INDEX_4 0x1290
3407 
3408 #define S_DEBUG_PC_RSP_SOP1_CNT    28
3409 #define M_DEBUG_PC_RSP_SOP1_CNT    0xfU
3410 #define V_DEBUG_PC_RSP_SOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP1_CNT)
3411 #define G_DEBUG_PC_RSP_SOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP1_CNT) & M_DEBUG_PC_RSP_SOP1_CNT)
3412 
3413 #define S_DEBUG_PC_RSP_EOP1_CNT    24
3414 #define M_DEBUG_PC_RSP_EOP1_CNT    0xfU
3415 #define V_DEBUG_PC_RSP_EOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP1_CNT)
3416 #define G_DEBUG_PC_RSP_EOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP1_CNT) & M_DEBUG_PC_RSP_EOP1_CNT)
3417 
3418 #define S_DEBUG_PC_RSP_SOP0_CNT    20
3419 #define M_DEBUG_PC_RSP_SOP0_CNT    0xfU
3420 #define V_DEBUG_PC_RSP_SOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP0_CNT)
3421 #define G_DEBUG_PC_RSP_SOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP0_CNT) & M_DEBUG_PC_RSP_SOP0_CNT)
3422 
3423 #define S_DEBUG_PC_RSP_EOP0_CNT    16
3424 #define M_DEBUG_PC_RSP_EOP0_CNT    0xfU
3425 #define V_DEBUG_PC_RSP_EOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP0_CNT)
3426 #define G_DEBUG_PC_RSP_EOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP0_CNT) & M_DEBUG_PC_RSP_EOP0_CNT)
3427 
3428 #define S_DEBUG_PC_REQ_SOP1_CNT    12
3429 #define M_DEBUG_PC_REQ_SOP1_CNT    0xfU
3430 #define V_DEBUG_PC_REQ_SOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP1_CNT)
3431 #define G_DEBUG_PC_REQ_SOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP1_CNT) & M_DEBUG_PC_REQ_SOP1_CNT)
3432 
3433 #define S_DEBUG_PC_REQ_EOP1_CNT    8
3434 #define M_DEBUG_PC_REQ_EOP1_CNT    0xfU
3435 #define V_DEBUG_PC_REQ_EOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP1_CNT)
3436 #define G_DEBUG_PC_REQ_EOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP1_CNT) & M_DEBUG_PC_REQ_EOP1_CNT)
3437 
3438 #define S_DEBUG_PC_REQ_SOP0_CNT    4
3439 #define M_DEBUG_PC_REQ_SOP0_CNT    0xfU
3440 #define V_DEBUG_PC_REQ_SOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP0_CNT)
3441 #define G_DEBUG_PC_REQ_SOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP0_CNT) & M_DEBUG_PC_REQ_SOP0_CNT)
3442 
3443 #define S_DEBUG_PC_REQ_EOP0_CNT    0
3444 #define M_DEBUG_PC_REQ_EOP0_CNT    0xfU
3445 #define V_DEBUG_PC_REQ_EOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP0_CNT)
3446 #define G_DEBUG_PC_REQ_EOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP0_CNT) & M_DEBUG_PC_REQ_EOP0_CNT)
3447 
3448 #define A_SGE_DEBUG_DATA_HIGH_INDEX_5 0x1294
3449 
3450 #define S_DEBUG_PD_RDREQ_SOP3_CNT    28
3451 #define M_DEBUG_PD_RDREQ_SOP3_CNT    0xfU
3452 #define V_DEBUG_PD_RDREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP3_CNT)
3453 #define G_DEBUG_PD_RDREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP3_CNT) & M_DEBUG_PD_RDREQ_SOP3_CNT)
3454 
3455 #define S_DEBUG_PD_RDREQ_EOP3_CNT    24
3456 #define M_DEBUG_PD_RDREQ_EOP3_CNT    0xfU
3457 #define V_DEBUG_PD_RDREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP3_CNT)
3458 #define G_DEBUG_PD_RDREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP3_CNT) & M_DEBUG_PD_RDREQ_EOP3_CNT)
3459 
3460 #define S_DEBUG_PD_RDREQ_SOP2_CNT    20
3461 #define M_DEBUG_PD_RDREQ_SOP2_CNT    0xfU
3462 #define V_DEBUG_PD_RDREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP2_CNT)
3463 #define G_DEBUG_PD_RDREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP2_CNT) & M_DEBUG_PD_RDREQ_SOP2_CNT)
3464 
3465 #define S_DEBUG_PD_RDREQ_EOP2_CNT    16
3466 #define M_DEBUG_PD_RDREQ_EOP2_CNT    0xfU
3467 #define V_DEBUG_PD_RDREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP2_CNT)
3468 #define G_DEBUG_PD_RDREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP2_CNT) & M_DEBUG_PD_RDREQ_EOP2_CNT)
3469 
3470 #define S_DEBUG_PD_RDREQ_SOP1_CNT    12
3471 #define M_DEBUG_PD_RDREQ_SOP1_CNT    0xfU
3472 #define V_DEBUG_PD_RDREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP1_CNT)
3473 #define G_DEBUG_PD_RDREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP1_CNT) & M_DEBUG_PD_RDREQ_SOP1_CNT)
3474 
3475 #define S_DEBUG_PD_RDREQ_EOP1_CNT    8
3476 #define M_DEBUG_PD_RDREQ_EOP1_CNT    0xfU
3477 #define V_DEBUG_PD_RDREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP1_CNT)
3478 #define G_DEBUG_PD_RDREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP1_CNT) & M_DEBUG_PD_RDREQ_EOP1_CNT)
3479 
3480 #define S_DEBUG_PD_RDREQ_SOP0_CNT    4
3481 #define M_DEBUG_PD_RDREQ_SOP0_CNT    0xfU
3482 #define V_DEBUG_PD_RDREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP0_CNT)
3483 #define G_DEBUG_PD_RDREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP0_CNT) & M_DEBUG_PD_RDREQ_SOP0_CNT)
3484 
3485 #define S_DEBUG_PD_RDREQ_EOP0_CNT    0
3486 #define M_DEBUG_PD_RDREQ_EOP0_CNT    0xfU
3487 #define V_DEBUG_PD_RDREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP0_CNT)
3488 #define G_DEBUG_PD_RDREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP0_CNT) & M_DEBUG_PD_RDREQ_EOP0_CNT)
3489 
3490 #define A_SGE_DEBUG_DATA_HIGH_INDEX_6 0x1298
3491 
3492 #define S_DEBUG_PD_RDRSP_SOP3_CNT    28
3493 #define M_DEBUG_PD_RDRSP_SOP3_CNT    0xfU
3494 #define V_DEBUG_PD_RDRSP_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP3_CNT)
3495 #define G_DEBUG_PD_RDRSP_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP3_CNT) & M_DEBUG_PD_RDRSP_SOP3_CNT)
3496 
3497 #define S_DEBUG_PD_RDRSP_EOP3_CNT    24
3498 #define M_DEBUG_PD_RDRSP_EOP3_CNT    0xfU
3499 #define V_DEBUG_PD_RDRSP_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP3_CNT)
3500 #define G_DEBUG_PD_RDRSP_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP3_CNT) & M_DEBUG_PD_RDRSP_EOP3_CNT)
3501 
3502 #define S_DEBUG_PD_RDRSP_SOP2_CNT    20
3503 #define M_DEBUG_PD_RDRSP_SOP2_CNT    0xfU
3504 #define V_DEBUG_PD_RDRSP_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP2_CNT)
3505 #define G_DEBUG_PD_RDRSP_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP2_CNT) & M_DEBUG_PD_RDRSP_SOP2_CNT)
3506 
3507 #define S_DEBUG_PD_RDRSP_EOP2_CNT    16
3508 #define M_DEBUG_PD_RDRSP_EOP2_CNT    0xfU
3509 #define V_DEBUG_PD_RDRSP_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP2_CNT)
3510 #define G_DEBUG_PD_RDRSP_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP2_CNT) & M_DEBUG_PD_RDRSP_EOP2_CNT)
3511 
3512 #define S_DEBUG_PD_RDRSP_SOP1_CNT    12
3513 #define M_DEBUG_PD_RDRSP_SOP1_CNT    0xfU
3514 #define V_DEBUG_PD_RDRSP_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP1_CNT)
3515 #define G_DEBUG_PD_RDRSP_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP1_CNT) & M_DEBUG_PD_RDRSP_SOP1_CNT)
3516 
3517 #define S_DEBUG_PD_RDRSP_EOP1_CNT    8
3518 #define M_DEBUG_PD_RDRSP_EOP1_CNT    0xfU
3519 #define V_DEBUG_PD_RDRSP_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP1_CNT)
3520 #define G_DEBUG_PD_RDRSP_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP1_CNT) & M_DEBUG_PD_RDRSP_EOP1_CNT)
3521 
3522 #define S_DEBUG_PD_RDRSP_SOP0_CNT    4
3523 #define M_DEBUG_PD_RDRSP_SOP0_CNT    0xfU
3524 #define V_DEBUG_PD_RDRSP_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP0_CNT)
3525 #define G_DEBUG_PD_RDRSP_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP0_CNT) & M_DEBUG_PD_RDRSP_SOP0_CNT)
3526 
3527 #define S_DEBUG_PD_RDRSP_EOP0_CNT    0
3528 #define M_DEBUG_PD_RDRSP_EOP0_CNT    0xfU
3529 #define V_DEBUG_PD_RDRSP_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP0_CNT)
3530 #define G_DEBUG_PD_RDRSP_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP0_CNT) & M_DEBUG_PD_RDRSP_EOP0_CNT)
3531 
3532 #define A_SGE_DEBUG_DATA_HIGH_INDEX_7 0x129c
3533 
3534 #define S_DEBUG_PD_WRREQ_SOP3_CNT    28
3535 #define M_DEBUG_PD_WRREQ_SOP3_CNT    0xfU
3536 #define V_DEBUG_PD_WRREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP3_CNT)
3537 #define G_DEBUG_PD_WRREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP3_CNT) & M_DEBUG_PD_WRREQ_SOP3_CNT)
3538 
3539 #define S_DEBUG_PD_WRREQ_EOP3_CNT    24
3540 #define M_DEBUG_PD_WRREQ_EOP3_CNT    0xfU
3541 #define V_DEBUG_PD_WRREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP3_CNT)
3542 #define G_DEBUG_PD_WRREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP3_CNT) & M_DEBUG_PD_WRREQ_EOP3_CNT)
3543 
3544 #define S_DEBUG_PD_WRREQ_SOP2_CNT    20
3545 #define M_DEBUG_PD_WRREQ_SOP2_CNT    0xfU
3546 #define V_DEBUG_PD_WRREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP2_CNT)
3547 #define G_DEBUG_PD_WRREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP2_CNT) & M_DEBUG_PD_WRREQ_SOP2_CNT)
3548 
3549 #define S_DEBUG_PD_WRREQ_EOP2_CNT    16
3550 #define M_DEBUG_PD_WRREQ_EOP2_CNT    0xfU
3551 #define V_DEBUG_PD_WRREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP2_CNT)
3552 #define G_DEBUG_PD_WRREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP2_CNT) & M_DEBUG_PD_WRREQ_EOP2_CNT)
3553 
3554 #define S_DEBUG_PD_WRREQ_SOP1_CNT    12
3555 #define M_DEBUG_PD_WRREQ_SOP1_CNT    0xfU
3556 #define V_DEBUG_PD_WRREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP1_CNT)
3557 #define G_DEBUG_PD_WRREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP1_CNT) & M_DEBUG_PD_WRREQ_SOP1_CNT)
3558 
3559 #define S_DEBUG_PD_WRREQ_EOP1_CNT    8
3560 #define M_DEBUG_PD_WRREQ_EOP1_CNT    0xfU
3561 #define V_DEBUG_PD_WRREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP1_CNT)
3562 #define G_DEBUG_PD_WRREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP1_CNT) & M_DEBUG_PD_WRREQ_EOP1_CNT)
3563 
3564 #define S_DEBUG_PD_WRREQ_SOP0_CNT    4
3565 #define M_DEBUG_PD_WRREQ_SOP0_CNT    0xfU
3566 #define V_DEBUG_PD_WRREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP0_CNT)
3567 #define G_DEBUG_PD_WRREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP0_CNT) & M_DEBUG_PD_WRREQ_SOP0_CNT)
3568 
3569 #define S_DEBUG_PD_WRREQ_EOP0_CNT    0
3570 #define M_DEBUG_PD_WRREQ_EOP0_CNT    0xfU
3571 #define V_DEBUG_PD_WRREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP0_CNT)
3572 #define G_DEBUG_PD_WRREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP0_CNT) & M_DEBUG_PD_WRREQ_EOP0_CNT)
3573 
3574 #define S_DEBUG_PC_RSP_SOP_CNT    28
3575 #define M_DEBUG_PC_RSP_SOP_CNT    0xfU
3576 #define V_DEBUG_PC_RSP_SOP_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP_CNT)
3577 #define G_DEBUG_PC_RSP_SOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP_CNT) & M_DEBUG_PC_RSP_SOP_CNT)
3578 
3579 #define S_DEBUG_PC_RSP_EOP_CNT    24
3580 #define M_DEBUG_PC_RSP_EOP_CNT    0xfU
3581 #define V_DEBUG_PC_RSP_EOP_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP_CNT)
3582 #define G_DEBUG_PC_RSP_EOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP_CNT) & M_DEBUG_PC_RSP_EOP_CNT)
3583 
3584 #define S_DEBUG_PC_REQ_SOP_CNT    20
3585 #define M_DEBUG_PC_REQ_SOP_CNT    0xfU
3586 #define V_DEBUG_PC_REQ_SOP_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP_CNT)
3587 #define G_DEBUG_PC_REQ_SOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP_CNT) & M_DEBUG_PC_REQ_SOP_CNT)
3588 
3589 #define S_DEBUG_PC_REQ_EOP_CNT    16
3590 #define M_DEBUG_PC_REQ_EOP_CNT    0xfU
3591 #define V_DEBUG_PC_REQ_EOP_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP_CNT)
3592 #define G_DEBUG_PC_REQ_EOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP_CNT) & M_DEBUG_PC_REQ_EOP_CNT)
3593 
3594 #define A_SGE_DEBUG_DATA_HIGH_INDEX_8 0x12a0
3595 
3596 #define S_GLOBALENABLE_OFF    29
3597 #define V_GLOBALENABLE_OFF(x) ((x) << S_GLOBALENABLE_OFF)
3598 #define F_GLOBALENABLE_OFF    V_GLOBALENABLE_OFF(1U)
3599 
3600 #define S_DEBUG_CIM2SGE_RXAFULL_D    27
3601 #define M_DEBUG_CIM2SGE_RXAFULL_D    0x3U
3602 #define V_DEBUG_CIM2SGE_RXAFULL_D(x) ((x) << S_DEBUG_CIM2SGE_RXAFULL_D)
3603 #define G_DEBUG_CIM2SGE_RXAFULL_D(x) (((x) >> S_DEBUG_CIM2SGE_RXAFULL_D) & M_DEBUG_CIM2SGE_RXAFULL_D)
3604 
3605 #define S_DEBUG_CPLSW_CIM_TXAFULL_D    25
3606 #define M_DEBUG_CPLSW_CIM_TXAFULL_D    0x3U
3607 #define V_DEBUG_CPLSW_CIM_TXAFULL_D(x) ((x) << S_DEBUG_CPLSW_CIM_TXAFULL_D)
3608 #define G_DEBUG_CPLSW_CIM_TXAFULL_D(x) (((x) >> S_DEBUG_CPLSW_CIM_TXAFULL_D) & M_DEBUG_CPLSW_CIM_TXAFULL_D)
3609 
3610 #define S_DEBUG_UP_FULL    24
3611 #define V_DEBUG_UP_FULL(x) ((x) << S_DEBUG_UP_FULL)
3612 #define F_DEBUG_UP_FULL    V_DEBUG_UP_FULL(1U)
3613 
3614 #define S_DEBUG_M_RD_REQ_OUTSTANDING_PC    23
3615 #define V_DEBUG_M_RD_REQ_OUTSTANDING_PC(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_PC)
3616 #define F_DEBUG_M_RD_REQ_OUTSTANDING_PC    V_DEBUG_M_RD_REQ_OUTSTANDING_PC(1U)
3617 
3618 #define S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO    22
3619 #define V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO)
3620 #define F_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO    V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(1U)
3621 
3622 #define S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG    21
3623 #define V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG)
3624 #define F_DEBUG_M_RD_REQ_OUTSTANDING_IMSG    V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(1U)
3625 
3626 #define S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB    20
3627 #define V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB)
3628 #define F_DEBUG_M_RD_REQ_OUTSTANDING_CMARB    V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(1U)
3629 
3630 #define S_DEBUG_M_RD_REQ_OUTSTANDING_FLM    19
3631 #define V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_FLM)
3632 #define F_DEBUG_M_RD_REQ_OUTSTANDING_FLM    V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(1U)
3633 
3634 #define S_DEBUG_M_REQVLD    18
3635 #define V_DEBUG_M_REQVLD(x) ((x) << S_DEBUG_M_REQVLD)
3636 #define F_DEBUG_M_REQVLD    V_DEBUG_M_REQVLD(1U)
3637 
3638 #define S_DEBUG_M_REQRDY    17
3639 #define V_DEBUG_M_REQRDY(x) ((x) << S_DEBUG_M_REQRDY)
3640 #define F_DEBUG_M_REQRDY    V_DEBUG_M_REQRDY(1U)
3641 
3642 #define S_DEBUG_M_RSPVLD    16
3643 #define V_DEBUG_M_RSPVLD(x) ((x) << S_DEBUG_M_RSPVLD)
3644 #define F_DEBUG_M_RSPVLD    V_DEBUG_M_RSPVLD(1U)
3645 
3646 #define S_DEBUG_PD_WRREQ_INT3_CNT    12
3647 #define M_DEBUG_PD_WRREQ_INT3_CNT    0xfU
3648 #define V_DEBUG_PD_WRREQ_INT3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT3_CNT)
3649 #define G_DEBUG_PD_WRREQ_INT3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT3_CNT) & M_DEBUG_PD_WRREQ_INT3_CNT)
3650 
3651 #define S_DEBUG_PD_WRREQ_INT2_CNT    8
3652 #define M_DEBUG_PD_WRREQ_INT2_CNT    0xfU
3653 #define V_DEBUG_PD_WRREQ_INT2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT2_CNT)
3654 #define G_DEBUG_PD_WRREQ_INT2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT2_CNT) & M_DEBUG_PD_WRREQ_INT2_CNT)
3655 
3656 #define S_DEBUG_PD_WRREQ_INT1_CNT    4
3657 #define M_DEBUG_PD_WRREQ_INT1_CNT    0xfU
3658 #define V_DEBUG_PD_WRREQ_INT1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT1_CNT)
3659 #define G_DEBUG_PD_WRREQ_INT1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT1_CNT) & M_DEBUG_PD_WRREQ_INT1_CNT)
3660 
3661 #define S_DEBUG_PD_WRREQ_INT0_CNT    0
3662 #define M_DEBUG_PD_WRREQ_INT0_CNT    0xfU
3663 #define V_DEBUG_PD_WRREQ_INT0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT0_CNT)
3664 #define G_DEBUG_PD_WRREQ_INT0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT0_CNT) & M_DEBUG_PD_WRREQ_INT0_CNT)
3665 
3666 #define S_DEBUG_PL_BAR2_REQVLD    31
3667 #define V_DEBUG_PL_BAR2_REQVLD(x) ((x) << S_DEBUG_PL_BAR2_REQVLD)
3668 #define F_DEBUG_PL_BAR2_REQVLD    V_DEBUG_PL_BAR2_REQVLD(1U)
3669 
3670 #define S_DEBUG_PL_BAR2_REQFULL    30
3671 #define V_DEBUG_PL_BAR2_REQFULL(x) ((x) << S_DEBUG_PL_BAR2_REQFULL)
3672 #define F_DEBUG_PL_BAR2_REQFULL    V_DEBUG_PL_BAR2_REQFULL(1U)
3673 
3674 #define A_SGE_DEBUG_DATA_HIGH_INDEX_9 0x12a4
3675 
3676 #define S_DEBUG_CPLSW_TP_RX_SOP1_CNT    28
3677 #define M_DEBUG_CPLSW_TP_RX_SOP1_CNT    0xfU
3678 #define V_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP1_CNT)
3679 #define G_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP1_CNT) & M_DEBUG_CPLSW_TP_RX_SOP1_CNT)
3680 
3681 #define S_DEBUG_CPLSW_TP_RX_EOP1_CNT    24
3682 #define M_DEBUG_CPLSW_TP_RX_EOP1_CNT    0xfU
3683 #define V_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP1_CNT)
3684 #define G_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP1_CNT) & M_DEBUG_CPLSW_TP_RX_EOP1_CNT)
3685 
3686 #define S_DEBUG_CPLSW_TP_RX_SOP0_CNT    20
3687 #define M_DEBUG_CPLSW_TP_RX_SOP0_CNT    0xfU
3688 #define V_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP0_CNT)
3689 #define G_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP0_CNT) & M_DEBUG_CPLSW_TP_RX_SOP0_CNT)
3690 
3691 #define S_DEBUG_CPLSW_TP_RX_EOP0_CNT    16
3692 #define M_DEBUG_CPLSW_TP_RX_EOP0_CNT    0xfU
3693 #define V_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP0_CNT)
3694 #define G_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP0_CNT) & M_DEBUG_CPLSW_TP_RX_EOP0_CNT)
3695 
3696 #define S_DEBUG_CPLSW_CIM_SOP1_CNT    12
3697 #define M_DEBUG_CPLSW_CIM_SOP1_CNT    0xfU
3698 #define V_DEBUG_CPLSW_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP1_CNT)
3699 #define G_DEBUG_CPLSW_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP1_CNT) & M_DEBUG_CPLSW_CIM_SOP1_CNT)
3700 
3701 #define S_DEBUG_CPLSW_CIM_EOP1_CNT    8
3702 #define M_DEBUG_CPLSW_CIM_EOP1_CNT    0xfU
3703 #define V_DEBUG_CPLSW_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP1_CNT)
3704 #define G_DEBUG_CPLSW_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP1_CNT) & M_DEBUG_CPLSW_CIM_EOP1_CNT)
3705 
3706 #define S_DEBUG_CPLSW_CIM_SOP0_CNT    4
3707 #define M_DEBUG_CPLSW_CIM_SOP0_CNT    0xfU
3708 #define V_DEBUG_CPLSW_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP0_CNT)
3709 #define G_DEBUG_CPLSW_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP0_CNT) & M_DEBUG_CPLSW_CIM_SOP0_CNT)
3710 
3711 #define S_DEBUG_CPLSW_CIM_EOP0_CNT    0
3712 #define M_DEBUG_CPLSW_CIM_EOP0_CNT    0xfU
3713 #define V_DEBUG_CPLSW_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP0_CNT)
3714 #define G_DEBUG_CPLSW_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP0_CNT) & M_DEBUG_CPLSW_CIM_EOP0_CNT)
3715 
3716 #define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
3717 
3718 #define S_DEBUG_T_RXAFULL_D    30
3719 #define M_DEBUG_T_RXAFULL_D    0x3U
3720 #define V_DEBUG_T_RXAFULL_D(x) ((x) << S_DEBUG_T_RXAFULL_D)
3721 #define G_DEBUG_T_RXAFULL_D(x) (((x) >> S_DEBUG_T_RXAFULL_D) & M_DEBUG_T_RXAFULL_D)
3722 
3723 #define S_DEBUG_PD_RDRSPAFULL_D    26
3724 #define M_DEBUG_PD_RDRSPAFULL_D    0xfU
3725 #define V_DEBUG_PD_RDRSPAFULL_D(x) ((x) << S_DEBUG_PD_RDRSPAFULL_D)
3726 #define G_DEBUG_PD_RDRSPAFULL_D(x) (((x) >> S_DEBUG_PD_RDRSPAFULL_D) & M_DEBUG_PD_RDRSPAFULL_D)
3727 
3728 #define S_DEBUG_PD_RDREQAFULL_D    22
3729 #define M_DEBUG_PD_RDREQAFULL_D    0xfU
3730 #define V_DEBUG_PD_RDREQAFULL_D(x) ((x) << S_DEBUG_PD_RDREQAFULL_D)
3731 #define G_DEBUG_PD_RDREQAFULL_D(x) (((x) >> S_DEBUG_PD_RDREQAFULL_D) & M_DEBUG_PD_RDREQAFULL_D)
3732 
3733 #define S_DEBUG_PD_WRREQAFULL_D    18
3734 #define M_DEBUG_PD_WRREQAFULL_D    0xfU
3735 #define V_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_DEBUG_PD_WRREQAFULL_D)
3736 #define G_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_DEBUG_PD_WRREQAFULL_D) & M_DEBUG_PD_WRREQAFULL_D)
3737 
3738 #define S_DEBUG_PC_RSPAFULL_D    15
3739 #define M_DEBUG_PC_RSPAFULL_D    0x7U
3740 #define V_DEBUG_PC_RSPAFULL_D(x) ((x) << S_DEBUG_PC_RSPAFULL_D)
3741 #define G_DEBUG_PC_RSPAFULL_D(x) (((x) >> S_DEBUG_PC_RSPAFULL_D) & M_DEBUG_PC_RSPAFULL_D)
3742 
3743 #define S_DEBUG_PC_REQAFULL_D    12
3744 #define M_DEBUG_PC_REQAFULL_D    0x7U
3745 #define V_DEBUG_PC_REQAFULL_D(x) ((x) << S_DEBUG_PC_REQAFULL_D)
3746 #define G_DEBUG_PC_REQAFULL_D(x) (((x) >> S_DEBUG_PC_REQAFULL_D) & M_DEBUG_PC_REQAFULL_D)
3747 
3748 #define S_DEBUG_U_TXAFULL_D    8
3749 #define M_DEBUG_U_TXAFULL_D    0xfU
3750 #define V_DEBUG_U_TXAFULL_D(x) ((x) << S_DEBUG_U_TXAFULL_D)
3751 #define G_DEBUG_U_TXAFULL_D(x) (((x) >> S_DEBUG_U_TXAFULL_D) & M_DEBUG_U_TXAFULL_D)
3752 
3753 #define S_DEBUG_UD_RXAFULL_D    4
3754 #define M_DEBUG_UD_RXAFULL_D    0xfU
3755 #define V_DEBUG_UD_RXAFULL_D(x) ((x) << S_DEBUG_UD_RXAFULL_D)
3756 #define G_DEBUG_UD_RXAFULL_D(x) (((x) >> S_DEBUG_UD_RXAFULL_D) & M_DEBUG_UD_RXAFULL_D)
3757 
3758 #define S_DEBUG_U_RXAFULL_D    2
3759 #define M_DEBUG_U_RXAFULL_D    0x3U
3760 #define V_DEBUG_U_RXAFULL_D(x) ((x) << S_DEBUG_U_RXAFULL_D)
3761 #define G_DEBUG_U_RXAFULL_D(x) (((x) >> S_DEBUG_U_RXAFULL_D) & M_DEBUG_U_RXAFULL_D)
3762 
3763 #define S_DEBUG_CIM_AFULL_D    0
3764 #define M_DEBUG_CIM_AFULL_D    0x3U
3765 #define V_DEBUG_CIM_AFULL_D(x) ((x) << S_DEBUG_CIM_AFULL_D)
3766 #define G_DEBUG_CIM_AFULL_D(x) (((x) >> S_DEBUG_CIM_AFULL_D) & M_DEBUG_CIM_AFULL_D)
3767 
3768 #define S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING    28
3769 #define M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING    0xfU
3770 #define V_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING)
3771 #define G_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING)
3772 
3773 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY    27
3774 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY)
3775 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(1U)
3776 
3777 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS    26
3778 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS)
3779 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(1U)
3780 
3781 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL    25
3782 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL)
3783 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(1U)
3784 
3785 #define S_DEBUG_IDMA1_IDMA2IMSG_FULL    24
3786 #define V_DEBUG_IDMA1_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FULL)
3787 #define F_DEBUG_IDMA1_IDMA2IMSG_FULL    V_DEBUG_IDMA1_IDMA2IMSG_FULL(1U)
3788 
3789 #define S_DEBUG_IDMA1_IDMA2IMSG_EOP    23
3790 #define V_DEBUG_IDMA1_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_EOP)
3791 #define F_DEBUG_IDMA1_IDMA2IMSG_EOP    V_DEBUG_IDMA1_IDMA2IMSG_EOP(1U)
3792 
3793 #define S_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY    22
3794 #define V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY)
3795 #define F_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY    V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(1U)
3796 
3797 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY    21
3798 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY)
3799 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY    V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(1U)
3800 
3801 #define S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING    17
3802 #define M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING    0xfU
3803 #define V_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING)
3804 #define G_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING)
3805 
3806 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY    16
3807 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY)
3808 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(1U)
3809 
3810 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS    15
3811 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS)
3812 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(1U)
3813 
3814 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL    14
3815 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL)
3816 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(1U)
3817 
3818 #define S_DEBUG_IDMA0_IDMA2IMSG_FULL    13
3819 #define V_DEBUG_IDMA0_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FULL)
3820 #define F_DEBUG_IDMA0_IDMA2IMSG_FULL    V_DEBUG_IDMA0_IDMA2IMSG_FULL(1U)
3821 
3822 #define S_DEBUG_IDMA0_IDMA2IMSG_EOP    12
3823 #define V_DEBUG_IDMA0_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_EOP)
3824 #define F_DEBUG_IDMA0_IDMA2IMSG_EOP    V_DEBUG_IDMA0_IDMA2IMSG_EOP(1U)
3825 
3826 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY    11
3827 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY)
3828 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY    V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(1U)
3829 
3830 #define S_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY    10
3831 #define V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY)
3832 #define F_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY    V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(1U)
3833 
3834 #define S_T6_DEBUG_T_RXAFULL_D    8
3835 #define M_T6_DEBUG_T_RXAFULL_D    0x3U
3836 #define V_T6_DEBUG_T_RXAFULL_D(x) ((x) << S_T6_DEBUG_T_RXAFULL_D)
3837 #define G_T6_DEBUG_T_RXAFULL_D(x) (((x) >> S_T6_DEBUG_T_RXAFULL_D) & M_T6_DEBUG_T_RXAFULL_D)
3838 
3839 #define S_T6_DEBUG_PD_WRREQAFULL_D    6
3840 #define M_T6_DEBUG_PD_WRREQAFULL_D    0x3U
3841 #define V_T6_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_T6_DEBUG_PD_WRREQAFULL_D)
3842 #define G_T6_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_T6_DEBUG_PD_WRREQAFULL_D) & M_T6_DEBUG_PD_WRREQAFULL_D)
3843 
3844 #define S_T6_DEBUG_PC_RSPAFULL_D    5
3845 #define V_T6_DEBUG_PC_RSPAFULL_D(x) ((x) << S_T6_DEBUG_PC_RSPAFULL_D)
3846 #define F_T6_DEBUG_PC_RSPAFULL_D    V_T6_DEBUG_PC_RSPAFULL_D(1U)
3847 
3848 #define S_T6_DEBUG_PC_REQAFULL_D    4
3849 #define V_T6_DEBUG_PC_REQAFULL_D(x) ((x) << S_T6_DEBUG_PC_REQAFULL_D)
3850 #define F_T6_DEBUG_PC_REQAFULL_D    V_T6_DEBUG_PC_REQAFULL_D(1U)
3851 
3852 #define S_T6_DEBUG_CIM_AFULL_D    0
3853 #define V_T6_DEBUG_CIM_AFULL_D(x) ((x) << S_T6_DEBUG_CIM_AFULL_D)
3854 #define F_T6_DEBUG_CIM_AFULL_D    V_T6_DEBUG_CIM_AFULL_D(1U)
3855 
3856 #define A_SGE_DEBUG_DATA_HIGH_INDEX_11 0x12ac
3857 
3858 #define S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE    24
3859 #define V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE)
3860 #define F_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE    V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(1U)
3861 
3862 #define S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE    23
3863 #define V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE)
3864 #define F_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE    V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(1U)
3865 
3866 #define S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE    22
3867 #define V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE)
3868 #define F_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE    V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(1U)
3869 
3870 #define S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE    21
3871 #define V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE)
3872 #define F_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE    V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(1U)
3873 
3874 #define S_DEBUG_ST_FLM_IDMA1_CACHE    19
3875 #define M_DEBUG_ST_FLM_IDMA1_CACHE    0x3U
3876 #define V_DEBUG_ST_FLM_IDMA1_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CACHE)
3877 #define G_DEBUG_ST_FLM_IDMA1_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CACHE) & M_DEBUG_ST_FLM_IDMA1_CACHE)
3878 
3879 #define S_DEBUG_ST_FLM_IDMA1_CTXT    16
3880 #define M_DEBUG_ST_FLM_IDMA1_CTXT    0x7U
3881 #define V_DEBUG_ST_FLM_IDMA1_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CTXT)
3882 #define G_DEBUG_ST_FLM_IDMA1_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CTXT) & M_DEBUG_ST_FLM_IDMA1_CTXT)
3883 
3884 #define S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE    8
3885 #define V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE)
3886 #define F_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE    V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(1U)
3887 
3888 #define S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE    7
3889 #define V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE)
3890 #define F_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE    V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(1U)
3891 
3892 #define S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE    6
3893 #define V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE)
3894 #define F_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE    V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(1U)
3895 
3896 #define S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE    5
3897 #define V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE)
3898 #define F_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE    V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(1U)
3899 
3900 #define S_DEBUG_ST_FLM_IDMA0_CACHE    3
3901 #define M_DEBUG_ST_FLM_IDMA0_CACHE    0x3U
3902 #define V_DEBUG_ST_FLM_IDMA0_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CACHE)
3903 #define G_DEBUG_ST_FLM_IDMA0_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CACHE) & M_DEBUG_ST_FLM_IDMA0_CACHE)
3904 
3905 #define S_DEBUG_ST_FLM_IDMA0_CTXT    0
3906 #define M_DEBUG_ST_FLM_IDMA0_CTXT    0x7U
3907 #define V_DEBUG_ST_FLM_IDMA0_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CTXT)
3908 #define G_DEBUG_ST_FLM_IDMA0_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CTXT) & M_DEBUG_ST_FLM_IDMA0_CTXT)
3909 
3910 #define A_SGE_DEBUG_DATA_HIGH_INDEX_12 0x12b0
3911 
3912 #define S_DEBUG_CPLSW_SOP1_CNT    28
3913 #define M_DEBUG_CPLSW_SOP1_CNT    0xfU
3914 #define V_DEBUG_CPLSW_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_SOP1_CNT)
3915 #define G_DEBUG_CPLSW_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP1_CNT) & M_DEBUG_CPLSW_SOP1_CNT)
3916 
3917 #define S_DEBUG_CPLSW_EOP1_CNT    24
3918 #define M_DEBUG_CPLSW_EOP1_CNT    0xfU
3919 #define V_DEBUG_CPLSW_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_EOP1_CNT)
3920 #define G_DEBUG_CPLSW_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP1_CNT) & M_DEBUG_CPLSW_EOP1_CNT)
3921 
3922 #define S_DEBUG_CPLSW_SOP0_CNT    20
3923 #define M_DEBUG_CPLSW_SOP0_CNT    0xfU
3924 #define V_DEBUG_CPLSW_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_SOP0_CNT)
3925 #define G_DEBUG_CPLSW_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP0_CNT) & M_DEBUG_CPLSW_SOP0_CNT)
3926 
3927 #define S_DEBUG_CPLSW_EOP0_CNT    16
3928 #define M_DEBUG_CPLSW_EOP0_CNT    0xfU
3929 #define V_DEBUG_CPLSW_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_EOP0_CNT)
3930 #define G_DEBUG_CPLSW_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP0_CNT) & M_DEBUG_CPLSW_EOP0_CNT)
3931 
3932 #define S_DEBUG_PC_RSP_SOP2_CNT    12
3933 #define M_DEBUG_PC_RSP_SOP2_CNT    0xfU
3934 #define V_DEBUG_PC_RSP_SOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP2_CNT)
3935 #define G_DEBUG_PC_RSP_SOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP2_CNT) & M_DEBUG_PC_RSP_SOP2_CNT)
3936 
3937 #define S_DEBUG_PC_RSP_EOP2_CNT    8
3938 #define M_DEBUG_PC_RSP_EOP2_CNT    0xfU
3939 #define V_DEBUG_PC_RSP_EOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP2_CNT)
3940 #define G_DEBUG_PC_RSP_EOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP2_CNT) & M_DEBUG_PC_RSP_EOP2_CNT)
3941 
3942 #define S_DEBUG_PC_REQ_SOP2_CNT    4
3943 #define M_DEBUG_PC_REQ_SOP2_CNT    0xfU
3944 #define V_DEBUG_PC_REQ_SOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP2_CNT)
3945 #define G_DEBUG_PC_REQ_SOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP2_CNT) & M_DEBUG_PC_REQ_SOP2_CNT)
3946 
3947 #define S_DEBUG_PC_REQ_EOP2_CNT    0
3948 #define M_DEBUG_PC_REQ_EOP2_CNT    0xfU
3949 #define V_DEBUG_PC_REQ_EOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP2_CNT)
3950 #define G_DEBUG_PC_REQ_EOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP2_CNT) & M_DEBUG_PC_REQ_EOP2_CNT)
3951 
3952 #define S_DEBUG_IDMA1_ISHIFT_TX_SIZE    8
3953 #define M_DEBUG_IDMA1_ISHIFT_TX_SIZE    0x7fU
3954 #define V_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA1_ISHIFT_TX_SIZE)
3955 #define G_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA1_ISHIFT_TX_SIZE) & M_DEBUG_IDMA1_ISHIFT_TX_SIZE)
3956 
3957 #define S_DEBUG_IDMA0_ISHIFT_TX_SIZE    0
3958 #define M_DEBUG_IDMA0_ISHIFT_TX_SIZE    0x7fU
3959 #define V_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA0_ISHIFT_TX_SIZE)
3960 #define G_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA0_ISHIFT_TX_SIZE) & M_DEBUG_IDMA0_ISHIFT_TX_SIZE)
3961 
3962 #define A_SGE_DEBUG_DATA_HIGH_INDEX_13 0x12b4
3963 #define A_SGE_DEBUG_DATA_HIGH_INDEX_14 0x12b8
3964 #define A_SGE_DEBUG_DATA_HIGH_INDEX_15 0x12bc
3965 #define A_SGE_DEBUG_DATA_LOW_INDEX_0 0x12c0
3966 
3967 #define S_DEBUG_ST_IDMA1_FLM_REQ    29
3968 #define M_DEBUG_ST_IDMA1_FLM_REQ    0x7U
3969 #define V_DEBUG_ST_IDMA1_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA1_FLM_REQ)
3970 #define G_DEBUG_ST_IDMA1_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA1_FLM_REQ) & M_DEBUG_ST_IDMA1_FLM_REQ)
3971 
3972 #define S_DEBUG_ST_IDMA0_FLM_REQ    26
3973 #define M_DEBUG_ST_IDMA0_FLM_REQ    0x7U
3974 #define V_DEBUG_ST_IDMA0_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA0_FLM_REQ)
3975 #define G_DEBUG_ST_IDMA0_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA0_FLM_REQ) & M_DEBUG_ST_IDMA0_FLM_REQ)
3976 
3977 #define S_DEBUG_ST_IMSG_CTXT    23
3978 #define M_DEBUG_ST_IMSG_CTXT    0x7U
3979 #define V_DEBUG_ST_IMSG_CTXT(x) ((x) << S_DEBUG_ST_IMSG_CTXT)
3980 #define G_DEBUG_ST_IMSG_CTXT(x) (((x) >> S_DEBUG_ST_IMSG_CTXT) & M_DEBUG_ST_IMSG_CTXT)
3981 
3982 #define S_DEBUG_ST_IMSG    18
3983 #define M_DEBUG_ST_IMSG    0x1fU
3984 #define V_DEBUG_ST_IMSG(x) ((x) << S_DEBUG_ST_IMSG)
3985 #define G_DEBUG_ST_IMSG(x) (((x) >> S_DEBUG_ST_IMSG) & M_DEBUG_ST_IMSG)
3986 
3987 #define S_DEBUG_ST_IDMA1_IALN    16
3988 #define M_DEBUG_ST_IDMA1_IALN    0x3U
3989 #define V_DEBUG_ST_IDMA1_IALN(x) ((x) << S_DEBUG_ST_IDMA1_IALN)
3990 #define G_DEBUG_ST_IDMA1_IALN(x) (((x) >> S_DEBUG_ST_IDMA1_IALN) & M_DEBUG_ST_IDMA1_IALN)
3991 
3992 #define S_DEBUG_ST_IDMA1_IDMA_SM    9
3993 #define M_DEBUG_ST_IDMA1_IDMA_SM    0x3fU
3994 #define V_DEBUG_ST_IDMA1_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA1_IDMA_SM)
3995 #define G_DEBUG_ST_IDMA1_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA1_IDMA_SM) & M_DEBUG_ST_IDMA1_IDMA_SM)
3996 
3997 #define S_DEBUG_ST_IDMA0_IALN    7
3998 #define M_DEBUG_ST_IDMA0_IALN    0x3U
3999 #define V_DEBUG_ST_IDMA0_IALN(x) ((x) << S_DEBUG_ST_IDMA0_IALN)
4000 #define G_DEBUG_ST_IDMA0_IALN(x) (((x) >> S_DEBUG_ST_IDMA0_IALN) & M_DEBUG_ST_IDMA0_IALN)
4001 
4002 #define S_DEBUG_ST_IDMA0_IDMA_SM    0
4003 #define M_DEBUG_ST_IDMA0_IDMA_SM    0x3fU
4004 #define V_DEBUG_ST_IDMA0_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA0_IDMA_SM)
4005 #define G_DEBUG_ST_IDMA0_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA0_IDMA_SM) & M_DEBUG_ST_IDMA0_IDMA_SM)
4006 
4007 #define S_DEBUG_ST_IDMA1_IDMA2IMSG    15
4008 #define V_DEBUG_ST_IDMA1_IDMA2IMSG(x) ((x) << S_DEBUG_ST_IDMA1_IDMA2IMSG)
4009 #define F_DEBUG_ST_IDMA1_IDMA2IMSG    V_DEBUG_ST_IDMA1_IDMA2IMSG(1U)
4010 
4011 #define S_DEBUG_ST_IDMA0_IDMA2IMSG    6
4012 #define V_DEBUG_ST_IDMA0_IDMA2IMSG(x) ((x) << S_DEBUG_ST_IDMA0_IDMA2IMSG)
4013 #define F_DEBUG_ST_IDMA0_IDMA2IMSG    V_DEBUG_ST_IDMA0_IDMA2IMSG(1U)
4014 
4015 #define A_SGE_DEBUG_DATA_LOW_INDEX_1 0x12c4
4016 
4017 #define S_DEBUG_ITP_EMPTY    12
4018 #define M_DEBUG_ITP_EMPTY    0x3fU
4019 #define V_DEBUG_ITP_EMPTY(x) ((x) << S_DEBUG_ITP_EMPTY)
4020 #define G_DEBUG_ITP_EMPTY(x) (((x) >> S_DEBUG_ITP_EMPTY) & M_DEBUG_ITP_EMPTY)
4021 
4022 #define S_DEBUG_ITP_EXPIRED    6
4023 #define M_DEBUG_ITP_EXPIRED    0x3fU
4024 #define V_DEBUG_ITP_EXPIRED(x) ((x) << S_DEBUG_ITP_EXPIRED)
4025 #define G_DEBUG_ITP_EXPIRED(x) (((x) >> S_DEBUG_ITP_EXPIRED) & M_DEBUG_ITP_EXPIRED)
4026 
4027 #define S_DEBUG_ITP_PAUSE    5
4028 #define V_DEBUG_ITP_PAUSE(x) ((x) << S_DEBUG_ITP_PAUSE)
4029 #define F_DEBUG_ITP_PAUSE    V_DEBUG_ITP_PAUSE(1U)
4030 
4031 #define S_DEBUG_ITP_DEL_DONE    4
4032 #define V_DEBUG_ITP_DEL_DONE(x) ((x) << S_DEBUG_ITP_DEL_DONE)
4033 #define F_DEBUG_ITP_DEL_DONE    V_DEBUG_ITP_DEL_DONE(1U)
4034 
4035 #define S_DEBUG_ITP_ADD_DONE    3
4036 #define V_DEBUG_ITP_ADD_DONE(x) ((x) << S_DEBUG_ITP_ADD_DONE)
4037 #define F_DEBUG_ITP_ADD_DONE    V_DEBUG_ITP_ADD_DONE(1U)
4038 
4039 #define S_DEBUG_ITP_EVR_STATE    0
4040 #define M_DEBUG_ITP_EVR_STATE    0x7U
4041 #define V_DEBUG_ITP_EVR_STATE(x) ((x) << S_DEBUG_ITP_EVR_STATE)
4042 #define G_DEBUG_ITP_EVR_STATE(x) (((x) >> S_DEBUG_ITP_EVR_STATE) & M_DEBUG_ITP_EVR_STATE)
4043 
4044 #define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
4045 
4046 #define S_DEBUG_ST_DBP_THREAD2_CIMFL    25
4047 #define M_DEBUG_ST_DBP_THREAD2_CIMFL    0x1fU
4048 #define V_DEBUG_ST_DBP_THREAD2_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD2_CIMFL)
4049 #define G_DEBUG_ST_DBP_THREAD2_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_CIMFL) & M_DEBUG_ST_DBP_THREAD2_CIMFL)
4050 
4051 #define S_DEBUG_ST_DBP_THREAD2_MAIN    20
4052 #define M_DEBUG_ST_DBP_THREAD2_MAIN    0x1fU
4053 #define V_DEBUG_ST_DBP_THREAD2_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD2_MAIN)
4054 #define G_DEBUG_ST_DBP_THREAD2_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_MAIN) & M_DEBUG_ST_DBP_THREAD2_MAIN)
4055 
4056 #define S_DEBUG_ST_DBP_THREAD1_CIMFL    15
4057 #define M_DEBUG_ST_DBP_THREAD1_CIMFL    0x1fU
4058 #define V_DEBUG_ST_DBP_THREAD1_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD1_CIMFL)
4059 #define G_DEBUG_ST_DBP_THREAD1_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_CIMFL) & M_DEBUG_ST_DBP_THREAD1_CIMFL)
4060 
4061 #define S_DEBUG_ST_DBP_THREAD1_MAIN    10
4062 #define M_DEBUG_ST_DBP_THREAD1_MAIN    0x1fU
4063 #define V_DEBUG_ST_DBP_THREAD1_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD1_MAIN)
4064 #define G_DEBUG_ST_DBP_THREAD1_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_MAIN) & M_DEBUG_ST_DBP_THREAD1_MAIN)
4065 
4066 #define S_DEBUG_ST_DBP_THREAD0_CIMFL    5
4067 #define M_DEBUG_ST_DBP_THREAD0_CIMFL    0x1fU
4068 #define V_DEBUG_ST_DBP_THREAD0_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD0_CIMFL)
4069 #define G_DEBUG_ST_DBP_THREAD0_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_CIMFL) & M_DEBUG_ST_DBP_THREAD0_CIMFL)
4070 
4071 #define S_DEBUG_ST_DBP_THREAD0_MAIN    0
4072 #define M_DEBUG_ST_DBP_THREAD0_MAIN    0x1fU
4073 #define V_DEBUG_ST_DBP_THREAD0_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD0_MAIN)
4074 #define G_DEBUG_ST_DBP_THREAD0_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_MAIN) & M_DEBUG_ST_DBP_THREAD0_MAIN)
4075 
4076 #define S_T6_DEBUG_ST_DBP_UPCP_MAIN    14
4077 #define M_T6_DEBUG_ST_DBP_UPCP_MAIN    0x7U
4078 #define V_T6_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_T6_DEBUG_ST_DBP_UPCP_MAIN)
4079 #define G_T6_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_T6_DEBUG_ST_DBP_UPCP_MAIN) & M_T6_DEBUG_ST_DBP_UPCP_MAIN)
4080 
4081 #define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
4082 
4083 #define S_DEBUG_ST_DBP_UPCP_MAIN    14
4084 #define M_DEBUG_ST_DBP_UPCP_MAIN    0x1fU
4085 #define V_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_DEBUG_ST_DBP_UPCP_MAIN)
4086 #define G_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_DEBUG_ST_DBP_UPCP_MAIN) & M_DEBUG_ST_DBP_UPCP_MAIN)
4087 
4088 #define S_DEBUG_ST_DBP_DBFIFO_MAIN    13
4089 #define V_DEBUG_ST_DBP_DBFIFO_MAIN(x) ((x) << S_DEBUG_ST_DBP_DBFIFO_MAIN)
4090 #define F_DEBUG_ST_DBP_DBFIFO_MAIN    V_DEBUG_ST_DBP_DBFIFO_MAIN(1U)
4091 
4092 #define S_DEBUG_ST_DBP_CTXT    10
4093 #define M_DEBUG_ST_DBP_CTXT    0x7U
4094 #define V_DEBUG_ST_DBP_CTXT(x) ((x) << S_DEBUG_ST_DBP_CTXT)
4095 #define G_DEBUG_ST_DBP_CTXT(x) (((x) >> S_DEBUG_ST_DBP_CTXT) & M_DEBUG_ST_DBP_CTXT)
4096 
4097 #define S_DEBUG_ST_DBP_THREAD3_CIMFL    5
4098 #define M_DEBUG_ST_DBP_THREAD3_CIMFL    0x1fU
4099 #define V_DEBUG_ST_DBP_THREAD3_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD3_CIMFL)
4100 #define G_DEBUG_ST_DBP_THREAD3_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_CIMFL) & M_DEBUG_ST_DBP_THREAD3_CIMFL)
4101 
4102 #define S_DEBUG_ST_DBP_THREAD3_MAIN    0
4103 #define M_DEBUG_ST_DBP_THREAD3_MAIN    0x1fU
4104 #define V_DEBUG_ST_DBP_THREAD3_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD3_MAIN)
4105 #define G_DEBUG_ST_DBP_THREAD3_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_MAIN) & M_DEBUG_ST_DBP_THREAD3_MAIN)
4106 
4107 #define A_SGE_DEBUG_DATA_LOW_INDEX_4 0x12d0
4108 
4109 #define S_DEBUG_ST_EDMA3_ALIGN_SUB    29
4110 #define M_DEBUG_ST_EDMA3_ALIGN_SUB    0x7U
4111 #define V_DEBUG_ST_EDMA3_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN_SUB)
4112 #define G_DEBUG_ST_EDMA3_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN_SUB) & M_DEBUG_ST_EDMA3_ALIGN_SUB)
4113 
4114 #define S_DEBUG_ST_EDMA3_ALIGN    27
4115 #define M_DEBUG_ST_EDMA3_ALIGN    0x3U
4116 #define V_DEBUG_ST_EDMA3_ALIGN(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN)
4117 #define G_DEBUG_ST_EDMA3_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN) & M_DEBUG_ST_EDMA3_ALIGN)
4118 
4119 #define S_DEBUG_ST_EDMA3_REQ    24
4120 #define M_DEBUG_ST_EDMA3_REQ    0x7U
4121 #define V_DEBUG_ST_EDMA3_REQ(x) ((x) << S_DEBUG_ST_EDMA3_REQ)
4122 #define G_DEBUG_ST_EDMA3_REQ(x) (((x) >> S_DEBUG_ST_EDMA3_REQ) & M_DEBUG_ST_EDMA3_REQ)
4123 
4124 #define S_DEBUG_ST_EDMA2_ALIGN_SUB    21
4125 #define M_DEBUG_ST_EDMA2_ALIGN_SUB    0x7U
4126 #define V_DEBUG_ST_EDMA2_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN_SUB)
4127 #define G_DEBUG_ST_EDMA2_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN_SUB) & M_DEBUG_ST_EDMA2_ALIGN_SUB)
4128 
4129 #define S_DEBUG_ST_EDMA2_ALIGN    19
4130 #define M_DEBUG_ST_EDMA2_ALIGN    0x3U
4131 #define V_DEBUG_ST_EDMA2_ALIGN(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN)
4132 #define G_DEBUG_ST_EDMA2_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN) & M_DEBUG_ST_EDMA2_ALIGN)
4133 
4134 #define S_DEBUG_ST_EDMA2_REQ    16
4135 #define M_DEBUG_ST_EDMA2_REQ    0x7U
4136 #define V_DEBUG_ST_EDMA2_REQ(x) ((x) << S_DEBUG_ST_EDMA2_REQ)
4137 #define G_DEBUG_ST_EDMA2_REQ(x) (((x) >> S_DEBUG_ST_EDMA2_REQ) & M_DEBUG_ST_EDMA2_REQ)
4138 
4139 #define S_DEBUG_ST_EDMA1_ALIGN_SUB    13
4140 #define M_DEBUG_ST_EDMA1_ALIGN_SUB    0x7U
4141 #define V_DEBUG_ST_EDMA1_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN_SUB)
4142 #define G_DEBUG_ST_EDMA1_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN_SUB) & M_DEBUG_ST_EDMA1_ALIGN_SUB)
4143 
4144 #define S_DEBUG_ST_EDMA1_ALIGN    11
4145 #define M_DEBUG_ST_EDMA1_ALIGN    0x3U
4146 #define V_DEBUG_ST_EDMA1_ALIGN(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN)
4147 #define G_DEBUG_ST_EDMA1_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN) & M_DEBUG_ST_EDMA1_ALIGN)
4148 
4149 #define S_DEBUG_ST_EDMA1_REQ    8
4150 #define M_DEBUG_ST_EDMA1_REQ    0x7U
4151 #define V_DEBUG_ST_EDMA1_REQ(x) ((x) << S_DEBUG_ST_EDMA1_REQ)
4152 #define G_DEBUG_ST_EDMA1_REQ(x) (((x) >> S_DEBUG_ST_EDMA1_REQ) & M_DEBUG_ST_EDMA1_REQ)
4153 
4154 #define S_DEBUG_ST_EDMA0_ALIGN_SUB    5
4155 #define M_DEBUG_ST_EDMA0_ALIGN_SUB    0x7U
4156 #define V_DEBUG_ST_EDMA0_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN_SUB)
4157 #define G_DEBUG_ST_EDMA0_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN_SUB) & M_DEBUG_ST_EDMA0_ALIGN_SUB)
4158 
4159 #define S_DEBUG_ST_EDMA0_ALIGN    3
4160 #define M_DEBUG_ST_EDMA0_ALIGN    0x3U
4161 #define V_DEBUG_ST_EDMA0_ALIGN(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN)
4162 #define G_DEBUG_ST_EDMA0_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN) & M_DEBUG_ST_EDMA0_ALIGN)
4163 
4164 #define S_DEBUG_ST_EDMA0_REQ    0
4165 #define M_DEBUG_ST_EDMA0_REQ    0x7U
4166 #define V_DEBUG_ST_EDMA0_REQ(x) ((x) << S_DEBUG_ST_EDMA0_REQ)
4167 #define G_DEBUG_ST_EDMA0_REQ(x) (((x) >> S_DEBUG_ST_EDMA0_REQ) & M_DEBUG_ST_EDMA0_REQ)
4168 
4169 #define A_SGE_DEBUG_DATA_LOW_INDEX_5 0x12d4
4170 
4171 #define S_DEBUG_ST_FLM_DBPTR    30
4172 #define M_DEBUG_ST_FLM_DBPTR    0x3U
4173 #define V_DEBUG_ST_FLM_DBPTR(x) ((x) << S_DEBUG_ST_FLM_DBPTR)
4174 #define G_DEBUG_ST_FLM_DBPTR(x) (((x) >> S_DEBUG_ST_FLM_DBPTR) & M_DEBUG_ST_FLM_DBPTR)
4175 
4176 #define S_DEBUG_FLM_CACHE_LOCKED_COUNT    23
4177 #define M_DEBUG_FLM_CACHE_LOCKED_COUNT    0x7fU
4178 #define V_DEBUG_FLM_CACHE_LOCKED_COUNT(x) ((x) << S_DEBUG_FLM_CACHE_LOCKED_COUNT)
4179 #define G_DEBUG_FLM_CACHE_LOCKED_COUNT(x) (((x) >> S_DEBUG_FLM_CACHE_LOCKED_COUNT) & M_DEBUG_FLM_CACHE_LOCKED_COUNT)
4180 
4181 #define S_DEBUG_FLM_CACHE_AGENT    20
4182 #define M_DEBUG_FLM_CACHE_AGENT    0x7U
4183 #define V_DEBUG_FLM_CACHE_AGENT(x) ((x) << S_DEBUG_FLM_CACHE_AGENT)
4184 #define G_DEBUG_FLM_CACHE_AGENT(x) (((x) >> S_DEBUG_FLM_CACHE_AGENT) & M_DEBUG_FLM_CACHE_AGENT)
4185 
4186 #define S_DEBUG_ST_FLM_CACHE    16
4187 #define M_DEBUG_ST_FLM_CACHE    0xfU
4188 #define V_DEBUG_ST_FLM_CACHE(x) ((x) << S_DEBUG_ST_FLM_CACHE)
4189 #define G_DEBUG_ST_FLM_CACHE(x) (((x) >> S_DEBUG_ST_FLM_CACHE) & M_DEBUG_ST_FLM_CACHE)
4190 
4191 #define S_DEBUG_FLM_DBPTR_CIDX_STALL    12
4192 #define V_DEBUG_FLM_DBPTR_CIDX_STALL(x) ((x) << S_DEBUG_FLM_DBPTR_CIDX_STALL)
4193 #define F_DEBUG_FLM_DBPTR_CIDX_STALL    V_DEBUG_FLM_DBPTR_CIDX_STALL(1U)
4194 
4195 #define S_DEBUG_FLM_DBPTR_QID    0
4196 #define M_DEBUG_FLM_DBPTR_QID    0xfffU
4197 #define V_DEBUG_FLM_DBPTR_QID(x) ((x) << S_DEBUG_FLM_DBPTR_QID)
4198 #define G_DEBUG_FLM_DBPTR_QID(x) (((x) >> S_DEBUG_FLM_DBPTR_QID) & M_DEBUG_FLM_DBPTR_QID)
4199 
4200 #define A_SGE_DEBUG0_DBP_THREAD 0x12d4
4201 
4202 #define S_THREAD_ST_MAIN    25
4203 #define M_THREAD_ST_MAIN    0x3fU
4204 #define V_THREAD_ST_MAIN(x) ((x) << S_THREAD_ST_MAIN)
4205 #define G_THREAD_ST_MAIN(x) (((x) >> S_THREAD_ST_MAIN) & M_THREAD_ST_MAIN)
4206 
4207 #define S_THREAD_ST_CIMFL    21
4208 #define M_THREAD_ST_CIMFL    0xfU
4209 #define V_THREAD_ST_CIMFL(x) ((x) << S_THREAD_ST_CIMFL)
4210 #define G_THREAD_ST_CIMFL(x) (((x) >> S_THREAD_ST_CIMFL) & M_THREAD_ST_CIMFL)
4211 
4212 #define S_THREAD_CMDOP    17
4213 #define M_THREAD_CMDOP    0xfU
4214 #define V_THREAD_CMDOP(x) ((x) << S_THREAD_CMDOP)
4215 #define G_THREAD_CMDOP(x) (((x) >> S_THREAD_CMDOP) & M_THREAD_CMDOP)
4216 
4217 #define S_THREAD_QID    0
4218 #define M_THREAD_QID    0x1ffffU
4219 #define V_THREAD_QID(x) ((x) << S_THREAD_QID)
4220 #define G_THREAD_QID(x) (((x) >> S_THREAD_QID) & M_THREAD_QID)
4221 
4222 #define A_SGE_DEBUG_DATA_LOW_INDEX_6 0x12d8
4223 
4224 #define S_DEBUG_DBP_THREAD0_QID    0
4225 #define M_DEBUG_DBP_THREAD0_QID    0x1ffffU
4226 #define V_DEBUG_DBP_THREAD0_QID(x) ((x) << S_DEBUG_DBP_THREAD0_QID)
4227 #define G_DEBUG_DBP_THREAD0_QID(x) (((x) >> S_DEBUG_DBP_THREAD0_QID) & M_DEBUG_DBP_THREAD0_QID)
4228 
4229 #define A_SGE_DEBUG_DATA_LOW_INDEX_7 0x12dc
4230 
4231 #define S_DEBUG_DBP_THREAD1_QID    0
4232 #define M_DEBUG_DBP_THREAD1_QID    0x1ffffU
4233 #define V_DEBUG_DBP_THREAD1_QID(x) ((x) << S_DEBUG_DBP_THREAD1_QID)
4234 #define G_DEBUG_DBP_THREAD1_QID(x) (((x) >> S_DEBUG_DBP_THREAD1_QID) & M_DEBUG_DBP_THREAD1_QID)
4235 
4236 #define A_SGE_DEBUG_DATA_LOW_INDEX_8 0x12e0
4237 
4238 #define S_DEBUG_DBP_THREAD2_QID    0
4239 #define M_DEBUG_DBP_THREAD2_QID    0x1ffffU
4240 #define V_DEBUG_DBP_THREAD2_QID(x) ((x) << S_DEBUG_DBP_THREAD2_QID)
4241 #define G_DEBUG_DBP_THREAD2_QID(x) (((x) >> S_DEBUG_DBP_THREAD2_QID) & M_DEBUG_DBP_THREAD2_QID)
4242 
4243 #define A_SGE_DEBUG_DATA_LOW_INDEX_9 0x12e4
4244 
4245 #define S_DEBUG_DBP_THREAD3_QID    0
4246 #define M_DEBUG_DBP_THREAD3_QID    0x1ffffU
4247 #define V_DEBUG_DBP_THREAD3_QID(x) ((x) << S_DEBUG_DBP_THREAD3_QID)
4248 #define G_DEBUG_DBP_THREAD3_QID(x) (((x) >> S_DEBUG_DBP_THREAD3_QID) & M_DEBUG_DBP_THREAD3_QID)
4249 
4250 #define A_SGE_DEBUG_DATA_LOW_INDEX_10 0x12e8
4251 
4252 #define S_DEBUG_IMSG_CPL    16
4253 #define M_DEBUG_IMSG_CPL    0xffU
4254 #define V_DEBUG_IMSG_CPL(x) ((x) << S_DEBUG_IMSG_CPL)
4255 #define G_DEBUG_IMSG_CPL(x) (((x) >> S_DEBUG_IMSG_CPL) & M_DEBUG_IMSG_CPL)
4256 
4257 #define S_DEBUG_IMSG_QID    0
4258 #define M_DEBUG_IMSG_QID    0xffffU
4259 #define V_DEBUG_IMSG_QID(x) ((x) << S_DEBUG_IMSG_QID)
4260 #define G_DEBUG_IMSG_QID(x) (((x) >> S_DEBUG_IMSG_QID) & M_DEBUG_IMSG_QID)
4261 
4262 #define A_SGE_DEBUG_DATA_LOW_INDEX_11 0x12ec
4263 
4264 #define S_DEBUG_IDMA1_QID    16
4265 #define M_DEBUG_IDMA1_QID    0xffffU
4266 #define V_DEBUG_IDMA1_QID(x) ((x) << S_DEBUG_IDMA1_QID)
4267 #define G_DEBUG_IDMA1_QID(x) (((x) >> S_DEBUG_IDMA1_QID) & M_DEBUG_IDMA1_QID)
4268 
4269 #define S_DEBUG_IDMA0_QID    0
4270 #define M_DEBUG_IDMA0_QID    0xffffU
4271 #define V_DEBUG_IDMA0_QID(x) ((x) << S_DEBUG_IDMA0_QID)
4272 #define G_DEBUG_IDMA0_QID(x) (((x) >> S_DEBUG_IDMA0_QID) & M_DEBUG_IDMA0_QID)
4273 
4274 #define A_SGE_DEBUG_DATA_LOW_INDEX_12 0x12f0
4275 
4276 #define S_DEBUG_IDMA1_FLM_REQ_QID    16
4277 #define M_DEBUG_IDMA1_FLM_REQ_QID    0xffffU
4278 #define V_DEBUG_IDMA1_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA1_FLM_REQ_QID)
4279 #define G_DEBUG_IDMA1_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA1_FLM_REQ_QID) & M_DEBUG_IDMA1_FLM_REQ_QID)
4280 
4281 #define S_DEBUG_IDMA0_FLM_REQ_QID    0
4282 #define M_DEBUG_IDMA0_FLM_REQ_QID    0xffffU
4283 #define V_DEBUG_IDMA0_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA0_FLM_REQ_QID)
4284 #define G_DEBUG_IDMA0_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA0_FLM_REQ_QID) & M_DEBUG_IDMA0_FLM_REQ_QID)
4285 
4286 #define A_SGE_DEBUG_DATA_LOW_INDEX_13 0x12f4
4287 #define A_SGE_DEBUG_DATA_LOW_INDEX_14 0x12f8
4288 #define A_SGE_DEBUG_DATA_LOW_INDEX_15 0x12fc
4289 #define A_SGE_QUEUE_BASE_MAP_HIGH 0x1300
4290 
4291 #define S_EGRESS_LOG2SIZE    27
4292 #define M_EGRESS_LOG2SIZE    0x1fU
4293 #define V_EGRESS_LOG2SIZE(x) ((x) << S_EGRESS_LOG2SIZE)
4294 #define G_EGRESS_LOG2SIZE(x) (((x) >> S_EGRESS_LOG2SIZE) & M_EGRESS_LOG2SIZE)
4295 
4296 #define S_EGRESS_BASE    10
4297 #define M_EGRESS_BASE    0x1ffffU
4298 #define V_EGRESS_BASE(x) ((x) << S_EGRESS_BASE)
4299 #define G_EGRESS_BASE(x) (((x) >> S_EGRESS_BASE) & M_EGRESS_BASE)
4300 
4301 #define S_INGRESS2_LOG2SIZE    5
4302 #define M_INGRESS2_LOG2SIZE    0x1fU
4303 #define V_INGRESS2_LOG2SIZE(x) ((x) << S_INGRESS2_LOG2SIZE)
4304 #define G_INGRESS2_LOG2SIZE(x) (((x) >> S_INGRESS2_LOG2SIZE) & M_INGRESS2_LOG2SIZE)
4305 
4306 #define S_INGRESS1_LOG2SIZE    0
4307 #define M_INGRESS1_LOG2SIZE    0x1fU
4308 #define V_INGRESS1_LOG2SIZE(x) ((x) << S_INGRESS1_LOG2SIZE)
4309 #define G_INGRESS1_LOG2SIZE(x) (((x) >> S_INGRESS1_LOG2SIZE) & M_INGRESS1_LOG2SIZE)
4310 
4311 #define S_EGRESS_SIZE    27
4312 #define M_EGRESS_SIZE    0x1fU
4313 #define V_EGRESS_SIZE(x) ((x) << S_EGRESS_SIZE)
4314 #define G_EGRESS_SIZE(x) (((x) >> S_EGRESS_SIZE) & M_EGRESS_SIZE)
4315 
4316 #define S_INGRESS2_SIZE    5
4317 #define M_INGRESS2_SIZE    0x1fU
4318 #define V_INGRESS2_SIZE(x) ((x) << S_INGRESS2_SIZE)
4319 #define G_INGRESS2_SIZE(x) (((x) >> S_INGRESS2_SIZE) & M_INGRESS2_SIZE)
4320 
4321 #define S_INGRESS1_SIZE    0
4322 #define M_INGRESS1_SIZE    0x1fU
4323 #define V_INGRESS1_SIZE(x) ((x) << S_INGRESS1_SIZE)
4324 #define G_INGRESS1_SIZE(x) (((x) >> S_INGRESS1_SIZE) & M_INGRESS1_SIZE)
4325 
4326 #define A_SGE_WC_EGRS_BAR2_OFF_PF 0x1300
4327 
4328 #define S_PFIQSPERPAGE    28
4329 #define M_PFIQSPERPAGE    0xfU
4330 #define V_PFIQSPERPAGE(x) ((x) << S_PFIQSPERPAGE)
4331 #define G_PFIQSPERPAGE(x) (((x) >> S_PFIQSPERPAGE) & M_PFIQSPERPAGE)
4332 
4333 #define S_PFEQSPERPAGE    24
4334 #define M_PFEQSPERPAGE    0xfU
4335 #define V_PFEQSPERPAGE(x) ((x) << S_PFEQSPERPAGE)
4336 #define G_PFEQSPERPAGE(x) (((x) >> S_PFEQSPERPAGE) & M_PFEQSPERPAGE)
4337 
4338 #define S_PFWCQSPERPAGE    20
4339 #define M_PFWCQSPERPAGE    0xfU
4340 #define V_PFWCQSPERPAGE(x) ((x) << S_PFWCQSPERPAGE)
4341 #define G_PFWCQSPERPAGE(x) (((x) >> S_PFWCQSPERPAGE) & M_PFWCQSPERPAGE)
4342 
4343 #define S_PFWCOFFEN    19
4344 #define V_PFWCOFFEN(x) ((x) << S_PFWCOFFEN)
4345 #define F_PFWCOFFEN    V_PFWCOFFEN(1U)
4346 
4347 #define S_PFMAXWCSIZE    17
4348 #define M_PFMAXWCSIZE    0x3U
4349 #define V_PFMAXWCSIZE(x) ((x) << S_PFMAXWCSIZE)
4350 #define G_PFMAXWCSIZE(x) (((x) >> S_PFMAXWCSIZE) & M_PFMAXWCSIZE)
4351 
4352 #define S_PFWCOFFSET    0
4353 #define M_PFWCOFFSET    0x1ffffU
4354 #define V_PFWCOFFSET(x) ((x) << S_PFWCOFFSET)
4355 #define G_PFWCOFFSET(x) (((x) >> S_PFWCOFFSET) & M_PFWCOFFSET)
4356 
4357 #define A_SGE_QUEUE_BASE_MAP_LOW 0x1304
4358 
4359 #define S_INGRESS2_BASE    16
4360 #define M_INGRESS2_BASE    0xffffU
4361 #define V_INGRESS2_BASE(x) ((x) << S_INGRESS2_BASE)
4362 #define G_INGRESS2_BASE(x) (((x) >> S_INGRESS2_BASE) & M_INGRESS2_BASE)
4363 
4364 #define S_INGRESS1_BASE    0
4365 #define M_INGRESS1_BASE    0xffffU
4366 #define V_INGRESS1_BASE(x) ((x) << S_INGRESS1_BASE)
4367 #define G_INGRESS1_BASE(x) (((x) >> S_INGRESS1_BASE) & M_INGRESS1_BASE)
4368 
4369 #define A_SGE_WC_EGRS_BAR2_OFF_VF 0x1320
4370 
4371 #define S_VFIQSPERPAGE    28
4372 #define M_VFIQSPERPAGE    0xfU
4373 #define V_VFIQSPERPAGE(x) ((x) << S_VFIQSPERPAGE)
4374 #define G_VFIQSPERPAGE(x) (((x) >> S_VFIQSPERPAGE) & M_VFIQSPERPAGE)
4375 
4376 #define S_VFEQSPERPAGE    24
4377 #define M_VFEQSPERPAGE    0xfU
4378 #define V_VFEQSPERPAGE(x) ((x) << S_VFEQSPERPAGE)
4379 #define G_VFEQSPERPAGE(x) (((x) >> S_VFEQSPERPAGE) & M_VFEQSPERPAGE)
4380 
4381 #define S_VFWCQSPERPAGE    20
4382 #define M_VFWCQSPERPAGE    0xfU
4383 #define V_VFWCQSPERPAGE(x) ((x) << S_VFWCQSPERPAGE)
4384 #define G_VFWCQSPERPAGE(x) (((x) >> S_VFWCQSPERPAGE) & M_VFWCQSPERPAGE)
4385 
4386 #define S_VFWCOFFEN    19
4387 #define V_VFWCOFFEN(x) ((x) << S_VFWCOFFEN)
4388 #define F_VFWCOFFEN    V_VFWCOFFEN(1U)
4389 
4390 #define S_VFMAXWCSIZE    17
4391 #define M_VFMAXWCSIZE    0x3U
4392 #define V_VFMAXWCSIZE(x) ((x) << S_VFMAXWCSIZE)
4393 #define G_VFMAXWCSIZE(x) (((x) >> S_VFMAXWCSIZE) & M_VFMAXWCSIZE)
4394 
4395 #define S_VFWCOFFSET    0
4396 #define M_VFWCOFFSET    0x1ffffU
4397 #define V_VFWCOFFSET(x) ((x) << S_VFWCOFFSET)
4398 #define G_VFWCOFFSET(x) (((x) >> S_VFWCOFFSET) & M_VFWCOFFSET)
4399 
4400 #define A_SGE_DEBUG_DATA_HIGH_INDEX_17 0x1340
4401 #define A_SGE_DEBUG_DATA_HIGH_INDEX_18 0x1344
4402 #define A_SGE_DEBUG_DATA_HIGH_INDEX_19 0x1348
4403 #define A_SGE_DEBUG_DATA_HIGH_INDEX_20 0x134c
4404 #define A_SGE_DEBUG_DATA_HIGH_INDEX_21 0x1350
4405 #define A_SGE_DEBUG_DATA_LOW_INDEX_16 0x1354
4406 #define A_SGE_DEBUG_DATA_LOW_INDEX_17 0x1358
4407 #define A_SGE_DEBUG_DATA_LOW_INDEX_18 0x135c
4408 #define A_SGE_INT_CAUSE7 0x1360
4409 
4410 #define S_HINT_FIFO_FULL    25
4411 #define V_HINT_FIFO_FULL(x) ((x) << S_HINT_FIFO_FULL)
4412 #define F_HINT_FIFO_FULL    V_HINT_FIFO_FULL(1U)
4413 
4414 #define S_CERR_HINT_DELAY_FIFO    24
4415 #define V_CERR_HINT_DELAY_FIFO(x) ((x) << S_CERR_HINT_DELAY_FIFO)
4416 #define F_CERR_HINT_DELAY_FIFO    V_CERR_HINT_DELAY_FIFO(1U)
4417 
4418 #define S_COAL_TIMER_FIFO_PERR    23
4419 #define V_COAL_TIMER_FIFO_PERR(x) ((x) << S_COAL_TIMER_FIFO_PERR)
4420 #define F_COAL_TIMER_FIFO_PERR    V_COAL_TIMER_FIFO_PERR(1U)
4421 
4422 #define S_CMP_FIFO_PERR    22
4423 #define V_CMP_FIFO_PERR(x) ((x) << S_CMP_FIFO_PERR)
4424 #define F_CMP_FIFO_PERR    V_CMP_FIFO_PERR(1U)
4425 
4426 #define S_SGE_IPP_FIFO_CERR    21
4427 #define V_SGE_IPP_FIFO_CERR(x) ((x) << S_SGE_IPP_FIFO_CERR)
4428 #define F_SGE_IPP_FIFO_CERR    V_SGE_IPP_FIFO_CERR(1U)
4429 
4430 #define S_CERR_ING_CTXT_CACHE    20
4431 #define V_CERR_ING_CTXT_CACHE(x) ((x) << S_CERR_ING_CTXT_CACHE)
4432 #define F_CERR_ING_CTXT_CACHE    V_CERR_ING_CTXT_CACHE(1U)
4433 
4434 #define S_IMSG_CNTX_PERR    19
4435 #define V_IMSG_CNTX_PERR(x) ((x) << S_IMSG_CNTX_PERR)
4436 #define F_IMSG_CNTX_PERR    V_IMSG_CNTX_PERR(1U)
4437 
4438 #define S_PD_FIFO_PERR    18
4439 #define V_PD_FIFO_PERR(x) ((x) << S_PD_FIFO_PERR)
4440 #define F_PD_FIFO_PERR    V_PD_FIFO_PERR(1U)
4441 
4442 #define S_IMSG_512_FIFO_PERR    17
4443 #define V_IMSG_512_FIFO_PERR(x) ((x) << S_IMSG_512_FIFO_PERR)
4444 #define F_IMSG_512_FIFO_PERR    V_IMSG_512_FIFO_PERR(1U)
4445 
4446 #define S_CPLSW_FIFO_PERR    16
4447 #define V_CPLSW_FIFO_PERR(x) ((x) << S_CPLSW_FIFO_PERR)
4448 #define F_CPLSW_FIFO_PERR    V_CPLSW_FIFO_PERR(1U)
4449 
4450 #define S_IMSG_FIFO_PERR    15
4451 #define V_IMSG_FIFO_PERR(x) ((x) << S_IMSG_FIFO_PERR)
4452 #define F_IMSG_FIFO_PERR    V_IMSG_FIFO_PERR(1U)
4453 
4454 #define S_CERR_ITP_EVR    14
4455 #define V_CERR_ITP_EVR(x) ((x) << S_CERR_ITP_EVR)
4456 #define F_CERR_ITP_EVR    V_CERR_ITP_EVR(1U)
4457 
4458 #define S_CERR_CONM_SRAM    13
4459 #define V_CERR_CONM_SRAM(x) ((x) << S_CERR_CONM_SRAM)
4460 #define F_CERR_CONM_SRAM    V_CERR_CONM_SRAM(1U)
4461 
4462 #define S_CERR_EGR_CTXT_CACHE    12
4463 #define V_CERR_EGR_CTXT_CACHE(x) ((x) << S_CERR_EGR_CTXT_CACHE)
4464 #define F_CERR_EGR_CTXT_CACHE    V_CERR_EGR_CTXT_CACHE(1U)
4465 
4466 #define S_CERR_FLM_CNTXMEM    11
4467 #define V_CERR_FLM_CNTXMEM(x) ((x) << S_CERR_FLM_CNTXMEM)
4468 #define F_CERR_FLM_CNTXMEM    V_CERR_FLM_CNTXMEM(1U)
4469 
4470 #define S_CERR_FUNC_QBASE    10
4471 #define V_CERR_FUNC_QBASE(x) ((x) << S_CERR_FUNC_QBASE)
4472 #define F_CERR_FUNC_QBASE    V_CERR_FUNC_QBASE(1U)
4473 
4474 #define S_IMSG_CNTX_CERR    9
4475 #define V_IMSG_CNTX_CERR(x) ((x) << S_IMSG_CNTX_CERR)
4476 #define F_IMSG_CNTX_CERR    V_IMSG_CNTX_CERR(1U)
4477 
4478 #define S_PD_FIFO_CERR    8
4479 #define V_PD_FIFO_CERR(x) ((x) << S_PD_FIFO_CERR)
4480 #define F_PD_FIFO_CERR    V_PD_FIFO_CERR(1U)
4481 
4482 #define S_IMSG_512_FIFO_CERR    7
4483 #define V_IMSG_512_FIFO_CERR(x) ((x) << S_IMSG_512_FIFO_CERR)
4484 #define F_IMSG_512_FIFO_CERR    V_IMSG_512_FIFO_CERR(1U)
4485 
4486 #define S_CPLSW_FIFO_CERR    6
4487 #define V_CPLSW_FIFO_CERR(x) ((x) << S_CPLSW_FIFO_CERR)
4488 #define F_CPLSW_FIFO_CERR    V_CPLSW_FIFO_CERR(1U)
4489 
4490 #define S_IMSG_FIFO_CERR    5
4491 #define V_IMSG_FIFO_CERR(x) ((x) << S_IMSG_FIFO_CERR)
4492 #define F_IMSG_FIFO_CERR    V_IMSG_FIFO_CERR(1U)
4493 
4494 #define S_CERR_HEADERSPLIT_FIFO3    4
4495 #define V_CERR_HEADERSPLIT_FIFO3(x) ((x) << S_CERR_HEADERSPLIT_FIFO3)
4496 #define F_CERR_HEADERSPLIT_FIFO3    V_CERR_HEADERSPLIT_FIFO3(1U)
4497 
4498 #define S_CERR_HEADERSPLIT_FIFO2    3
4499 #define V_CERR_HEADERSPLIT_FIFO2(x) ((x) << S_CERR_HEADERSPLIT_FIFO2)
4500 #define F_CERR_HEADERSPLIT_FIFO2    V_CERR_HEADERSPLIT_FIFO2(1U)
4501 
4502 #define S_CERR_HEADERSPLIT_FIFO1    2
4503 #define V_CERR_HEADERSPLIT_FIFO1(x) ((x) << S_CERR_HEADERSPLIT_FIFO1)
4504 #define F_CERR_HEADERSPLIT_FIFO1    V_CERR_HEADERSPLIT_FIFO1(1U)
4505 
4506 #define S_CERR_HEADERSPLIT_FIFO0    1
4507 #define V_CERR_HEADERSPLIT_FIFO0(x) ((x) << S_CERR_HEADERSPLIT_FIFO0)
4508 #define F_CERR_HEADERSPLIT_FIFO0    V_CERR_HEADERSPLIT_FIFO0(1U)
4509 
4510 #define S_CERR_FLM_L1CACHE    0
4511 #define V_CERR_FLM_L1CACHE(x) ((x) << S_CERR_FLM_L1CACHE)
4512 #define F_CERR_FLM_L1CACHE    V_CERR_FLM_L1CACHE(1U)
4513 
4514 #define A_SGE_INT_ENABLE7 0x1364
4515 #define A_SGE_PERR_ENABLE7 0x1368
4516 #define A_SGE_ING_COMP_COAL_CFG 0x1700
4517 
4518 #define S_USE_PTP_TIMER    27
4519 #define V_USE_PTP_TIMER(x) ((x) << S_USE_PTP_TIMER)
4520 #define F_USE_PTP_TIMER    V_USE_PTP_TIMER(1U)
4521 
4522 #define S_IMSG_SET_OFLOW_ALL_ENTRIES_43060    26
4523 #define V_IMSG_SET_OFLOW_ALL_ENTRIES_43060(x) ((x) << S_IMSG_SET_OFLOW_ALL_ENTRIES_43060)
4524 #define F_IMSG_SET_OFLOW_ALL_ENTRIES_43060    V_IMSG_SET_OFLOW_ALL_ENTRIES_43060(1U)
4525 
4526 #define S_IMSG_STUCK_INDIRECT_QUEUE_42907    25
4527 #define V_IMSG_STUCK_INDIRECT_QUEUE_42907(x) ((x) << S_IMSG_STUCK_INDIRECT_QUEUE_42907)
4528 #define F_IMSG_STUCK_INDIRECT_QUEUE_42907    V_IMSG_STUCK_INDIRECT_QUEUE_42907(1U)
4529 
4530 #define S_COMP_COAL_PIDX_INCR    24
4531 #define V_COMP_COAL_PIDX_INCR(x) ((x) << S_COMP_COAL_PIDX_INCR)
4532 #define F_COMP_COAL_PIDX_INCR    V_COMP_COAL_PIDX_INCR(1U)
4533 
4534 #define S_COMP_COAL_TIMER_CNT    16
4535 #define M_COMP_COAL_TIMER_CNT    0xffU
4536 #define V_COMP_COAL_TIMER_CNT(x) ((x) << S_COMP_COAL_TIMER_CNT)
4537 #define G_COMP_COAL_TIMER_CNT(x) (((x) >> S_COMP_COAL_TIMER_CNT) & M_COMP_COAL_TIMER_CNT)
4538 
4539 #define S_COMP_COAL_CNTR_TH    8
4540 #define M_COMP_COAL_CNTR_TH    0xffU
4541 #define V_COMP_COAL_CNTR_TH(x) ((x) << S_COMP_COAL_CNTR_TH)
4542 #define G_COMP_COAL_CNTR_TH(x) (((x) >> S_COMP_COAL_CNTR_TH) & M_COMP_COAL_CNTR_TH)
4543 
4544 #define S_COMP_COAL_OPCODE    0
4545 #define M_COMP_COAL_OPCODE    0xffU
4546 #define V_COMP_COAL_OPCODE(x) ((x) << S_COMP_COAL_OPCODE)
4547 #define G_COMP_COAL_OPCODE(x) (((x) >> S_COMP_COAL_OPCODE) & M_COMP_COAL_OPCODE)
4548 
4549 #define A_SGE_ING_IMSG_DBG 0x1704
4550 
4551 #define S_STUCK_CTR_TH    1
4552 #define M_STUCK_CTR_TH    0xffU
4553 #define V_STUCK_CTR_TH(x) ((x) << S_STUCK_CTR_TH)
4554 #define G_STUCK_CTR_TH(x) (((x) >> S_STUCK_CTR_TH) & M_STUCK_CTR_TH)
4555 
4556 #define S_STUCK_INT_EN    0
4557 #define V_STUCK_INT_EN(x) ((x) << S_STUCK_INT_EN)
4558 #define F_STUCK_INT_EN    V_STUCK_INT_EN(1U)
4559 
4560 #define A_SGE_ING_IMSG_RSP0_DBG 0x1708
4561 
4562 #define S_IDMA1_QID    16
4563 #define M_IDMA1_QID    0xffffU
4564 #define V_IDMA1_QID(x) ((x) << S_IDMA1_QID)
4565 #define G_IDMA1_QID(x) (((x) >> S_IDMA1_QID) & M_IDMA1_QID)
4566 
4567 #define S_IDMA0_QID    0
4568 #define M_IDMA0_QID    0xffffU
4569 #define V_IDMA0_QID(x) ((x) << S_IDMA0_QID)
4570 #define G_IDMA0_QID(x) (((x) >> S_IDMA0_QID) & M_IDMA0_QID)
4571 
4572 #define A_SGE_ING_IMSG_RSP1_DBG 0x170c
4573 
4574 #define S_IDMA3_QID    16
4575 #define M_IDMA3_QID    0xffffU
4576 #define V_IDMA3_QID(x) ((x) << S_IDMA3_QID)
4577 #define G_IDMA3_QID(x) (((x) >> S_IDMA3_QID) & M_IDMA3_QID)
4578 
4579 #define S_IDMA2_QID    0
4580 #define M_IDMA2_QID    0xffffU
4581 #define V_IDMA2_QID(x) ((x) << S_IDMA2_QID)
4582 #define G_IDMA2_QID(x) (((x) >> S_IDMA2_QID) & M_IDMA2_QID)
4583 
4584 #define A_SGE_LB_MODE 0x1710
4585 
4586 #define S_LB_MODE    0
4587 #define M_LB_MODE    0x3U
4588 #define V_LB_MODE(x) ((x) << S_LB_MODE)
4589 #define G_LB_MODE(x) (((x) >> S_LB_MODE) & M_LB_MODE)
4590 
4591 #define A_SGE_IMSG_QUESCENT 0x1714
4592 
4593 #define S_IMSG_QUESCENT    0
4594 #define V_IMSG_QUESCENT(x) ((x) << S_IMSG_QUESCENT)
4595 #define F_IMSG_QUESCENT    V_IMSG_QUESCENT(1U)
4596 
4597 #define A_SGE_LA_CTRL 0x1718
4598 
4599 #define S_LA_GLOBAL_EN    8
4600 #define V_LA_GLOBAL_EN(x) ((x) << S_LA_GLOBAL_EN)
4601 #define F_LA_GLOBAL_EN    V_LA_GLOBAL_EN(1U)
4602 
4603 #define S_PTP_TIMESTAMP_SEL    7
4604 #define V_PTP_TIMESTAMP_SEL(x) ((x) << S_PTP_TIMESTAMP_SEL)
4605 #define F_PTP_TIMESTAMP_SEL    V_PTP_TIMESTAMP_SEL(1U)
4606 
4607 #define S_CIM2SGE_ID_CHK_VLD    6
4608 #define V_CIM2SGE_ID_CHK_VLD(x) ((x) << S_CIM2SGE_ID_CHK_VLD)
4609 #define F_CIM2SGE_ID_CHK_VLD    V_CIM2SGE_ID_CHK_VLD(1U)
4610 
4611 #define S_CPLSW_ID_CHK_VLD    5
4612 #define V_CPLSW_ID_CHK_VLD(x) ((x) << S_CPLSW_ID_CHK_VLD)
4613 #define F_CPLSW_ID_CHK_VLD    V_CPLSW_ID_CHK_VLD(1U)
4614 
4615 #define S_FLM_ID_CHK_VLD    4
4616 #define V_FLM_ID_CHK_VLD(x) ((x) << S_FLM_ID_CHK_VLD)
4617 #define F_FLM_ID_CHK_VLD    V_FLM_ID_CHK_VLD(1U)
4618 
4619 #define S_IQ_DBP_ID_CHK_VLD    3
4620 #define V_IQ_DBP_ID_CHK_VLD(x) ((x) << S_IQ_DBP_ID_CHK_VLD)
4621 #define F_IQ_DBP_ID_CHK_VLD    V_IQ_DBP_ID_CHK_VLD(1U)
4622 
4623 #define S_UP_OBQ_ID_CHK_VLD    2
4624 #define V_UP_OBQ_ID_CHK_VLD(x) ((x) << S_UP_OBQ_ID_CHK_VLD)
4625 #define F_UP_OBQ_ID_CHK_VLD    V_UP_OBQ_ID_CHK_VLD(1U)
4626 
4627 #define S_CIM_ID_CHK_VLD    1
4628 #define V_CIM_ID_CHK_VLD(x) ((x) << S_CIM_ID_CHK_VLD)
4629 #define F_CIM_ID_CHK_VLD    V_CIM_ID_CHK_VLD(1U)
4630 
4631 #define S_DBP_ID_CHK_VLD    0
4632 #define V_DBP_ID_CHK_VLD(x) ((x) << S_DBP_ID_CHK_VLD)
4633 #define F_DBP_ID_CHK_VLD    V_DBP_ID_CHK_VLD(1U)
4634 
4635 #define A_SGE_LA_CTRL_EQID_LOW 0x171c
4636 
4637 #define S_EQ_ID_CHK_LOW    0
4638 #define M_EQ_ID_CHK_LOW    0x1ffffU
4639 #define V_EQ_ID_CHK_LOW(x) ((x) << S_EQ_ID_CHK_LOW)
4640 #define G_EQ_ID_CHK_LOW(x) (((x) >> S_EQ_ID_CHK_LOW) & M_EQ_ID_CHK_LOW)
4641 
4642 #define A_SGE_LA_CTRL_EQID_HIGH 0x1720
4643 
4644 #define S_EQ_ID_CHK_HIGH    0
4645 #define M_EQ_ID_CHK_HIGH    0x1ffffU
4646 #define V_EQ_ID_CHK_HIGH(x) ((x) << S_EQ_ID_CHK_HIGH)
4647 #define G_EQ_ID_CHK_HIGH(x) (((x) >> S_EQ_ID_CHK_HIGH) & M_EQ_ID_CHK_HIGH)
4648 
4649 #define A_SGE_LA_CTRL_IQID 0x1724
4650 
4651 #define S_IQ_ID_CHK_HIGH    16
4652 #define M_IQ_ID_CHK_HIGH    0xffffU
4653 #define V_IQ_ID_CHK_HIGH(x) ((x) << S_IQ_ID_CHK_HIGH)
4654 #define G_IQ_ID_CHK_HIGH(x) (((x) >> S_IQ_ID_CHK_HIGH) & M_IQ_ID_CHK_HIGH)
4655 
4656 #define S_IQ_ID_CHK_LOW    0
4657 #define M_IQ_ID_CHK_LOW    0xffffU
4658 #define V_IQ_ID_CHK_LOW(x) ((x) << S_IQ_ID_CHK_LOW)
4659 #define G_IQ_ID_CHK_LOW(x) (((x) >> S_IQ_ID_CHK_LOW) & M_IQ_ID_CHK_LOW)
4660 
4661 #define A_SGE_LA_CTRL_TID_LOW 0x1728
4662 
4663 #define S_TID_CHK_LOW    0
4664 #define M_TID_CHK_LOW    0xffffffU
4665 #define V_TID_CHK_LOW(x) ((x) << S_TID_CHK_LOW)
4666 #define G_TID_CHK_LOW(x) (((x) >> S_TID_CHK_LOW) & M_TID_CHK_LOW)
4667 
4668 #define A_SGE_LA_CTRL_TID_HIGH 0x172c
4669 
4670 #define S_TID_CHK_HIGH    0
4671 #define M_TID_CHK_HIGH    0xffffffU
4672 #define V_TID_CHK_HIGH(x) ((x) << S_TID_CHK_HIGH)
4673 #define G_TID_CHK_HIGH(x) (((x) >> S_TID_CHK_HIGH) & M_TID_CHK_HIGH)
4674 
4675 #define A_SGE_CFG_TP_ERR 0x173c
4676 
4677 #define S_TP_ERR_STATUS_CH3    30
4678 #define M_TP_ERR_STATUS_CH3    0x3U
4679 #define V_TP_ERR_STATUS_CH3(x) ((x) << S_TP_ERR_STATUS_CH3)
4680 #define G_TP_ERR_STATUS_CH3(x) (((x) >> S_TP_ERR_STATUS_CH3) & M_TP_ERR_STATUS_CH3)
4681 
4682 #define S_TP_ERR_STATUS_CH2    28
4683 #define M_TP_ERR_STATUS_CH2    0x3U
4684 #define V_TP_ERR_STATUS_CH2(x) ((x) << S_TP_ERR_STATUS_CH2)
4685 #define G_TP_ERR_STATUS_CH2(x) (((x) >> S_TP_ERR_STATUS_CH2) & M_TP_ERR_STATUS_CH2)
4686 
4687 #define S_TP_ERR_STATUS_CH1    26
4688 #define M_TP_ERR_STATUS_CH1    0x3U
4689 #define V_TP_ERR_STATUS_CH1(x) ((x) << S_TP_ERR_STATUS_CH1)
4690 #define G_TP_ERR_STATUS_CH1(x) (((x) >> S_TP_ERR_STATUS_CH1) & M_TP_ERR_STATUS_CH1)
4691 
4692 #define S_TP_ERR_STATUS_CH0    24
4693 #define M_TP_ERR_STATUS_CH0    0x3U
4694 #define V_TP_ERR_STATUS_CH0(x) ((x) << S_TP_ERR_STATUS_CH0)
4695 #define G_TP_ERR_STATUS_CH0(x) (((x) >> S_TP_ERR_STATUS_CH0) & M_TP_ERR_STATUS_CH0)
4696 
4697 #define S_CPL0_SIZE    16
4698 #define M_CPL0_SIZE    0xffU
4699 #define V_CPL0_SIZE(x) ((x) << S_CPL0_SIZE)
4700 #define G_CPL0_SIZE(x) (((x) >> S_CPL0_SIZE) & M_CPL0_SIZE)
4701 
4702 #define S_CPL1_SIZE    8
4703 #define M_CPL1_SIZE    0xffU
4704 #define V_CPL1_SIZE(x) ((x) << S_CPL1_SIZE)
4705 #define G_CPL1_SIZE(x) (((x) >> S_CPL1_SIZE) & M_CPL1_SIZE)
4706 
4707 #define S_SIZE_LATCH_CLR    3
4708 #define V_SIZE_LATCH_CLR(x) ((x) << S_SIZE_LATCH_CLR)
4709 #define F_SIZE_LATCH_CLR    V_SIZE_LATCH_CLR(1U)
4710 
4711 #define S_EXT_LATCH_CLR    2
4712 #define V_EXT_LATCH_CLR(x) ((x) << S_EXT_LATCH_CLR)
4713 #define F_EXT_LATCH_CLR    V_EXT_LATCH_CLR(1U)
4714 
4715 #define S_EXT_CHANGE_42875    1
4716 #define V_EXT_CHANGE_42875(x) ((x) << S_EXT_CHANGE_42875)
4717 #define F_EXT_CHANGE_42875    V_EXT_CHANGE_42875(1U)
4718 
4719 #define S_SIZE_CHANGE_42913    0
4720 #define V_SIZE_CHANGE_42913(x) ((x) << S_SIZE_CHANGE_42913)
4721 #define F_SIZE_CHANGE_42913    V_SIZE_CHANGE_42913(1U)
4722 
4723 #define A_SGE_CHNL0_CTX_ERROR_COUNT_PER_TID 0x1740
4724 #define A_SGE_CHNL1_CTX_ERROR_COUNT_PER_TID 0x1744
4725 #define A_SGE_CHNL2_CTX_ERROR_COUNT_PER_TID 0x1748
4726 #define A_SGE_CHNL3_CTX_ERROR_COUNT_PER_TID 0x174c
4727 #define A_SGE_CTX_ACC_CH0 0x1750
4728 
4729 #define S_RDMA_INV_HANDLING    24
4730 #define M_RDMA_INV_HANDLING    0x3U
4731 #define V_RDMA_INV_HANDLING(x) ((x) << S_RDMA_INV_HANDLING)
4732 #define G_RDMA_INV_HANDLING(x) (((x) >> S_RDMA_INV_HANDLING) & M_RDMA_INV_HANDLING)
4733 
4734 #define S_T7_TERMINATE_STATUS_EN    23
4735 #define V_T7_TERMINATE_STATUS_EN(x) ((x) << S_T7_TERMINATE_STATUS_EN)
4736 #define F_T7_TERMINATE_STATUS_EN    V_T7_TERMINATE_STATUS_EN(1U)
4737 
4738 #define S_T7_DISABLE    22
4739 #define V_T7_DISABLE(x) ((x) << S_T7_DISABLE)
4740 #define F_T7_DISABLE    V_T7_DISABLE(1U)
4741 
4742 #define A_SGE_CTX_ACC_CH1 0x1754
4743 #define A_SGE_CTX_ACC_CH2 0x1758
4744 #define A_SGE_CTX_ACC_CH3 0x175c
4745 #define A_SGE_CTX_BASE 0x1760
4746 #define A_SGE_LA_RDPTR_0 0x1800
4747 #define A_SGE_LA_RDDATA_0 0x1804
4748 #define A_SGE_LA_WRPTR_0 0x1808
4749 #define A_SGE_LA_RESERVED_0 0x180c
4750 #define A_SGE_LA_RDPTR_1 0x1810
4751 #define A_SGE_LA_RDDATA_1 0x1814
4752 #define A_SGE_LA_WRPTR_1 0x1818
4753 #define A_SGE_LA_RESERVED_1 0x181c
4754 #define A_SGE_LA_RDPTR_2 0x1820
4755 #define A_SGE_LA_RDDATA_2 0x1824
4756 #define A_SGE_LA_WRPTR_2 0x1828
4757 #define A_SGE_LA_RESERVED_2 0x182c
4758 #define A_SGE_LA_RDPTR_3 0x1830
4759 #define A_SGE_LA_RDDATA_3 0x1834
4760 #define A_SGE_LA_WRPTR_3 0x1838
4761 #define A_SGE_LA_RESERVED_3 0x183c
4762 #define A_SGE_LA_RDPTR_4 0x1840
4763 #define A_SGE_LA_RDDATA_4 0x1844
4764 #define A_SGE_LA_WRPTR_4 0x1848
4765 #define A_SGE_LA_RESERVED_4 0x184c
4766 #define A_SGE_LA_RDPTR_5 0x1850
4767 #define A_SGE_LA_RDDATA_5 0x1854
4768 #define A_SGE_LA_WRPTR_5 0x1858
4769 #define A_SGE_LA_RESERVED_5 0x185c
4770 #define A_SGE_LA_RDPTR_6 0x1860
4771 #define A_SGE_LA_RDDATA_6 0x1864
4772 #define A_SGE_LA_WRPTR_6 0x1868
4773 #define A_SGE_LA_RESERVED_6 0x186c
4774 #define A_SGE_LA_RDPTR_7 0x1870
4775 #define A_SGE_LA_RDDATA_7 0x1874
4776 #define A_SGE_LA_WRPTR_7 0x1878
4777 #define A_SGE_LA_RESERVED_7 0x187c
4778 #define A_SGE_LA_RDPTR_8 0x1880
4779 #define A_SGE_LA_RDDATA_8 0x1884
4780 #define A_SGE_LA_WRPTR_8 0x1888
4781 #define A_SGE_LA_RESERVED_8 0x188c
4782 #define A_SGE_LA_RDPTR_9 0x1890
4783 #define A_SGE_LA_RDDATA_9 0x1894
4784 #define A_SGE_LA_WRPTR_9 0x1898
4785 #define A_SGE_LA_RESERVED_9 0x189c
4786 #define A_SGE_LA_RDPTR_10 0x18a0
4787 #define A_SGE_LA_RDDATA_10 0x18a4
4788 #define A_SGE_LA_WRPTR_10 0x18a8
4789 #define A_SGE_LA_RESERVED_10 0x18ac
4790 #define A_SGE_LA_RDPTR_11 0x18b0
4791 #define A_SGE_LA_RDDATA_11 0x18b4
4792 #define A_SGE_LA_WRPTR_11 0x18b8
4793 #define A_SGE_LA_RESERVED_11 0x18bc
4794 #define A_SGE_LA_RDPTR_12 0x18c0
4795 #define A_SGE_LA_RDDATA_12 0x18c4
4796 #define A_SGE_LA_WRPTR_12 0x18c8
4797 #define A_SGE_LA_RESERVED_12 0x18cc
4798 #define A_SGE_LA_RDPTR_13 0x18d0
4799 #define A_SGE_LA_RDDATA_13 0x18d4
4800 #define A_SGE_LA_WRPTR_13 0x18d8
4801 #define A_SGE_LA_RESERVED_13 0x18dc
4802 #define A_SGE_LA_RDPTR_14 0x18e0
4803 #define A_SGE_LA_RDDATA_14 0x18e4
4804 #define A_SGE_LA_WRPTR_14 0x18e8
4805 #define A_SGE_LA_RESERVED_14 0x18ec
4806 #define A_SGE_LA_RDPTR_15 0x18f0
4807 #define A_SGE_LA_RDDATA_15 0x18f4
4808 #define A_SGE_LA_WRPTR_15 0x18f8
4809 #define A_SGE_LA_RESERVED_15 0x18fc
4810 
4811 /* registers for module PCIE */
4812 #define PCIE_BASE_ADDR 0x3000
4813 
4814 #define A_PCIE_PF_CFG 0x40
4815 
4816 #define S_INTXSTAT    16
4817 #define V_INTXSTAT(x) ((x) << S_INTXSTAT)
4818 #define F_INTXSTAT    V_INTXSTAT(1U)
4819 
4820 #define S_AUXPWRPMEN    15
4821 #define V_AUXPWRPMEN(x) ((x) << S_AUXPWRPMEN)
4822 #define F_AUXPWRPMEN    V_AUXPWRPMEN(1U)
4823 
4824 #define S_NOSOFTRESET    14
4825 #define V_NOSOFTRESET(x) ((x) << S_NOSOFTRESET)
4826 #define F_NOSOFTRESET    V_NOSOFTRESET(1U)
4827 
4828 #define S_AIVEC    4
4829 #define M_AIVEC    0x3ffU
4830 #define V_AIVEC(x) ((x) << S_AIVEC)
4831 #define G_AIVEC(x) (((x) >> S_AIVEC) & M_AIVEC)
4832 
4833 #define S_INTXTYPE    2
4834 #define M_INTXTYPE    0x3U
4835 #define V_INTXTYPE(x) ((x) << S_INTXTYPE)
4836 #define G_INTXTYPE(x) (((x) >> S_INTXTYPE) & M_INTXTYPE)
4837 
4838 #define S_D3HOTEN    1
4839 #define V_D3HOTEN(x) ((x) << S_D3HOTEN)
4840 #define F_D3HOTEN    V_D3HOTEN(1U)
4841 
4842 #define S_CLIDECEN    0
4843 #define V_CLIDECEN(x) ((x) << S_CLIDECEN)
4844 #define F_CLIDECEN    V_CLIDECEN(1U)
4845 
4846 #define A_PCIE_PF_CLI 0x44
4847 #define A_PCIE_PF_GEN_MSG 0x48
4848 
4849 #define S_MSGTYPE    0
4850 #define M_MSGTYPE    0xffU
4851 #define V_MSGTYPE(x) ((x) << S_MSGTYPE)
4852 #define G_MSGTYPE(x) (((x) >> S_MSGTYPE) & M_MSGTYPE)
4853 
4854 #define A_PCIE_PF_EXPROM_OFST 0x4c
4855 
4856 #define S_OFFSET    10
4857 #define M_OFFSET    0x3fffU
4858 #define V_OFFSET(x) ((x) << S_OFFSET)
4859 #define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET)
4860 
4861 #define A_PCIE_INT_ENABLE 0x3000
4862 
4863 #define S_NONFATALERR    30
4864 #define V_NONFATALERR(x) ((x) << S_NONFATALERR)
4865 #define F_NONFATALERR    V_NONFATALERR(1U)
4866 
4867 #define S_UNXSPLCPLERR    29
4868 #define V_UNXSPLCPLERR(x) ((x) << S_UNXSPLCPLERR)
4869 #define F_UNXSPLCPLERR    V_UNXSPLCPLERR(1U)
4870 
4871 #define S_PCIEPINT    28
4872 #define V_PCIEPINT(x) ((x) << S_PCIEPINT)
4873 #define F_PCIEPINT    V_PCIEPINT(1U)
4874 
4875 #define S_PCIESINT    27
4876 #define V_PCIESINT(x) ((x) << S_PCIESINT)
4877 #define F_PCIESINT    V_PCIESINT(1U)
4878 
4879 #define S_RPLPERR    26
4880 #define V_RPLPERR(x) ((x) << S_RPLPERR)
4881 #define F_RPLPERR    V_RPLPERR(1U)
4882 
4883 #define S_RXWRPERR    25
4884 #define V_RXWRPERR(x) ((x) << S_RXWRPERR)
4885 #define F_RXWRPERR    V_RXWRPERR(1U)
4886 
4887 #define S_RXCPLPERR    24
4888 #define V_RXCPLPERR(x) ((x) << S_RXCPLPERR)
4889 #define F_RXCPLPERR    V_RXCPLPERR(1U)
4890 
4891 #define S_PIOTAGPERR    23
4892 #define V_PIOTAGPERR(x) ((x) << S_PIOTAGPERR)
4893 #define F_PIOTAGPERR    V_PIOTAGPERR(1U)
4894 
4895 #define S_MATAGPERR    22
4896 #define V_MATAGPERR(x) ((x) << S_MATAGPERR)
4897 #define F_MATAGPERR    V_MATAGPERR(1U)
4898 
4899 #define S_INTXCLRPERR    21
4900 #define V_INTXCLRPERR(x) ((x) << S_INTXCLRPERR)
4901 #define F_INTXCLRPERR    V_INTXCLRPERR(1U)
4902 
4903 #define S_FIDPERR    20
4904 #define V_FIDPERR(x) ((x) << S_FIDPERR)
4905 #define F_FIDPERR    V_FIDPERR(1U)
4906 
4907 #define S_CFGSNPPERR    19
4908 #define V_CFGSNPPERR(x) ((x) << S_CFGSNPPERR)
4909 #define F_CFGSNPPERR    V_CFGSNPPERR(1U)
4910 
4911 #define S_HRSPPERR    18
4912 #define V_HRSPPERR(x) ((x) << S_HRSPPERR)
4913 #define F_HRSPPERR    V_HRSPPERR(1U)
4914 
4915 #define S_HREQPERR    17
4916 #define V_HREQPERR(x) ((x) << S_HREQPERR)
4917 #define F_HREQPERR    V_HREQPERR(1U)
4918 
4919 #define S_HCNTPERR    16
4920 #define V_HCNTPERR(x) ((x) << S_HCNTPERR)
4921 #define F_HCNTPERR    V_HCNTPERR(1U)
4922 
4923 #define S_DRSPPERR    15
4924 #define V_DRSPPERR(x) ((x) << S_DRSPPERR)
4925 #define F_DRSPPERR    V_DRSPPERR(1U)
4926 
4927 #define S_DREQPERR    14
4928 #define V_DREQPERR(x) ((x) << S_DREQPERR)
4929 #define F_DREQPERR    V_DREQPERR(1U)
4930 
4931 #define S_DCNTPERR    13
4932 #define V_DCNTPERR(x) ((x) << S_DCNTPERR)
4933 #define F_DCNTPERR    V_DCNTPERR(1U)
4934 
4935 #define S_CRSPPERR    12
4936 #define V_CRSPPERR(x) ((x) << S_CRSPPERR)
4937 #define F_CRSPPERR    V_CRSPPERR(1U)
4938 
4939 #define S_CREQPERR    11
4940 #define V_CREQPERR(x) ((x) << S_CREQPERR)
4941 #define F_CREQPERR    V_CREQPERR(1U)
4942 
4943 #define S_CCNTPERR    10
4944 #define V_CCNTPERR(x) ((x) << S_CCNTPERR)
4945 #define F_CCNTPERR    V_CCNTPERR(1U)
4946 
4947 #define S_TARTAGPERR    9
4948 #define V_TARTAGPERR(x) ((x) << S_TARTAGPERR)
4949 #define F_TARTAGPERR    V_TARTAGPERR(1U)
4950 
4951 #define S_PIOREQPERR    8
4952 #define V_PIOREQPERR(x) ((x) << S_PIOREQPERR)
4953 #define F_PIOREQPERR    V_PIOREQPERR(1U)
4954 
4955 #define S_PIOCPLPERR    7
4956 #define V_PIOCPLPERR(x) ((x) << S_PIOCPLPERR)
4957 #define F_PIOCPLPERR    V_PIOCPLPERR(1U)
4958 
4959 #define S_MSIXDIPERR    6
4960 #define V_MSIXDIPERR(x) ((x) << S_MSIXDIPERR)
4961 #define F_MSIXDIPERR    V_MSIXDIPERR(1U)
4962 
4963 #define S_MSIXDATAPERR    5
4964 #define V_MSIXDATAPERR(x) ((x) << S_MSIXDATAPERR)
4965 #define F_MSIXDATAPERR    V_MSIXDATAPERR(1U)
4966 
4967 #define S_MSIXADDRHPERR    4
4968 #define V_MSIXADDRHPERR(x) ((x) << S_MSIXADDRHPERR)
4969 #define F_MSIXADDRHPERR    V_MSIXADDRHPERR(1U)
4970 
4971 #define S_MSIXADDRLPERR    3
4972 #define V_MSIXADDRLPERR(x) ((x) << S_MSIXADDRLPERR)
4973 #define F_MSIXADDRLPERR    V_MSIXADDRLPERR(1U)
4974 
4975 #define S_MSIDATAPERR    2
4976 #define V_MSIDATAPERR(x) ((x) << S_MSIDATAPERR)
4977 #define F_MSIDATAPERR    V_MSIDATAPERR(1U)
4978 
4979 #define S_MSIADDRHPERR    1
4980 #define V_MSIADDRHPERR(x) ((x) << S_MSIADDRHPERR)
4981 #define F_MSIADDRHPERR    V_MSIADDRHPERR(1U)
4982 
4983 #define S_MSIADDRLPERR    0
4984 #define V_MSIADDRLPERR(x) ((x) << S_MSIADDRLPERR)
4985 #define F_MSIADDRLPERR    V_MSIADDRLPERR(1U)
4986 
4987 #define S_IPGRPPERR    31
4988 #define V_IPGRPPERR(x) ((x) << S_IPGRPPERR)
4989 #define F_IPGRPPERR    V_IPGRPPERR(1U)
4990 
4991 #define S_READRSPERR    29
4992 #define V_READRSPERR(x) ((x) << S_READRSPERR)
4993 #define F_READRSPERR    V_READRSPERR(1U)
4994 
4995 #define S_TRGT1GRPPERR    28
4996 #define V_TRGT1GRPPERR(x) ((x) << S_TRGT1GRPPERR)
4997 #define F_TRGT1GRPPERR    V_TRGT1GRPPERR(1U)
4998 
4999 #define S_IPSOTPERR    27
5000 #define V_IPSOTPERR(x) ((x) << S_IPSOTPERR)
5001 #define F_IPSOTPERR    V_IPSOTPERR(1U)
5002 
5003 #define S_IPRETRYPERR    26
5004 #define V_IPRETRYPERR(x) ((x) << S_IPRETRYPERR)
5005 #define F_IPRETRYPERR    V_IPRETRYPERR(1U)
5006 
5007 #define S_IPRXDATAGRPPERR    25
5008 #define V_IPRXDATAGRPPERR(x) ((x) << S_IPRXDATAGRPPERR)
5009 #define F_IPRXDATAGRPPERR    V_IPRXDATAGRPPERR(1U)
5010 
5011 #define S_IPRXHDRGRPPERR    24
5012 #define V_IPRXHDRGRPPERR(x) ((x) << S_IPRXHDRGRPPERR)
5013 #define F_IPRXHDRGRPPERR    V_IPRXHDRGRPPERR(1U)
5014 
5015 #define S_PIOTAGQPERR    23
5016 #define V_PIOTAGQPERR(x) ((x) << S_PIOTAGQPERR)
5017 #define F_PIOTAGQPERR    V_PIOTAGQPERR(1U)
5018 
5019 #define S_MAGRPPERR    22
5020 #define V_MAGRPPERR(x) ((x) << S_MAGRPPERR)
5021 #define F_MAGRPPERR    V_MAGRPPERR(1U)
5022 
5023 #define S_VFIDPERR    21
5024 #define V_VFIDPERR(x) ((x) << S_VFIDPERR)
5025 #define F_VFIDPERR    V_VFIDPERR(1U)
5026 
5027 #define S_HREQRDPERR    17
5028 #define V_HREQRDPERR(x) ((x) << S_HREQRDPERR)
5029 #define F_HREQRDPERR    V_HREQRDPERR(1U)
5030 
5031 #define S_HREQWRPERR    16
5032 #define V_HREQWRPERR(x) ((x) << S_HREQWRPERR)
5033 #define F_HREQWRPERR    V_HREQWRPERR(1U)
5034 
5035 #define S_DREQRDPERR    14
5036 #define V_DREQRDPERR(x) ((x) << S_DREQRDPERR)
5037 #define F_DREQRDPERR    V_DREQRDPERR(1U)
5038 
5039 #define S_DREQWRPERR    13
5040 #define V_DREQWRPERR(x) ((x) << S_DREQWRPERR)
5041 #define F_DREQWRPERR    V_DREQWRPERR(1U)
5042 
5043 #define S_CREQRDPERR    11
5044 #define V_CREQRDPERR(x) ((x) << S_CREQRDPERR)
5045 #define F_CREQRDPERR    V_CREQRDPERR(1U)
5046 
5047 #define S_MSTTAGQPERR    10
5048 #define V_MSTTAGQPERR(x) ((x) << S_MSTTAGQPERR)
5049 #define F_MSTTAGQPERR    V_MSTTAGQPERR(1U)
5050 
5051 #define S_TGTTAGQPERR    9
5052 #define V_TGTTAGQPERR(x) ((x) << S_TGTTAGQPERR)
5053 #define F_TGTTAGQPERR    V_TGTTAGQPERR(1U)
5054 
5055 #define S_PIOREQGRPPERR    8
5056 #define V_PIOREQGRPPERR(x) ((x) << S_PIOREQGRPPERR)
5057 #define F_PIOREQGRPPERR    V_PIOREQGRPPERR(1U)
5058 
5059 #define S_PIOCPLGRPPERR    7
5060 #define V_PIOCPLGRPPERR(x) ((x) << S_PIOCPLGRPPERR)
5061 #define F_PIOCPLGRPPERR    V_PIOCPLGRPPERR(1U)
5062 
5063 #define S_MSIXSTIPERR    2
5064 #define V_MSIXSTIPERR(x) ((x) << S_MSIXSTIPERR)
5065 #define F_MSIXSTIPERR    V_MSIXSTIPERR(1U)
5066 
5067 #define S_MSTTIMEOUTPERR    1
5068 #define V_MSTTIMEOUTPERR(x) ((x) << S_MSTTIMEOUTPERR)
5069 #define F_MSTTIMEOUTPERR    V_MSTTIMEOUTPERR(1U)
5070 
5071 #define S_MSTGRPPERR    0
5072 #define V_MSTGRPPERR(x) ((x) << S_MSTGRPPERR)
5073 #define F_MSTGRPPERR    V_MSTGRPPERR(1U)
5074 
5075 #define A_PCIE_INT_CAUSE 0x3004
5076 #define A_PCIE_PERR_ENABLE 0x3008
5077 
5078 #define S_TGTTAGQCLIENT1PERR    29
5079 #define V_TGTTAGQCLIENT1PERR(x) ((x) << S_TGTTAGQCLIENT1PERR)
5080 #define F_TGTTAGQCLIENT1PERR    V_TGTTAGQCLIENT1PERR(1U)
5081 
5082 #define A_PCIE_PERR_INJECT 0x300c
5083 
5084 #define S_IDE    0
5085 #define V_IDE(x) ((x) << S_IDE)
5086 #define F_IDE    V_IDE(1U)
5087 
5088 #define S_MEMSEL_PCIE    1
5089 #define M_MEMSEL_PCIE    0x1fU
5090 #define V_MEMSEL_PCIE(x) ((x) << S_MEMSEL_PCIE)
5091 #define G_MEMSEL_PCIE(x) (((x) >> S_MEMSEL_PCIE) & M_MEMSEL_PCIE)
5092 
5093 #define A_PCIE_NONFAT_ERR 0x3010
5094 
5095 #define S_RDRSPERR    9
5096 #define V_RDRSPERR(x) ((x) << S_RDRSPERR)
5097 #define F_RDRSPERR    V_RDRSPERR(1U)
5098 
5099 #define S_VPDRSPERR    8
5100 #define V_VPDRSPERR(x) ((x) << S_VPDRSPERR)
5101 #define F_VPDRSPERR    V_VPDRSPERR(1U)
5102 
5103 #define S_POPD    7
5104 #define V_POPD(x) ((x) << S_POPD)
5105 #define F_POPD    V_POPD(1U)
5106 
5107 #define S_POPH    6
5108 #define V_POPH(x) ((x) << S_POPH)
5109 #define F_POPH    V_POPH(1U)
5110 
5111 #define S_POPC    5
5112 #define V_POPC(x) ((x) << S_POPC)
5113 #define F_POPC    V_POPC(1U)
5114 
5115 #define S_MEMREQ    4
5116 #define V_MEMREQ(x) ((x) << S_MEMREQ)
5117 #define F_MEMREQ    V_MEMREQ(1U)
5118 
5119 #define S_PIOREQ    3
5120 #define V_PIOREQ(x) ((x) << S_PIOREQ)
5121 #define F_PIOREQ    V_PIOREQ(1U)
5122 
5123 #define S_TAGDROP    2
5124 #define V_TAGDROP(x) ((x) << S_TAGDROP)
5125 #define F_TAGDROP    V_TAGDROP(1U)
5126 
5127 #define S_TAGCPL    1
5128 #define V_TAGCPL(x) ((x) << S_TAGCPL)
5129 #define F_TAGCPL    V_TAGCPL(1U)
5130 
5131 #define S_CFGSNP    0
5132 #define V_CFGSNP(x) ((x) << S_CFGSNP)
5133 #define F_CFGSNP    V_CFGSNP(1U)
5134 
5135 #define S_MAREQTIMEOUT    29
5136 #define V_MAREQTIMEOUT(x) ((x) << S_MAREQTIMEOUT)
5137 #define F_MAREQTIMEOUT    V_MAREQTIMEOUT(1U)
5138 
5139 #define S_TRGT1BARTYPEERR    28
5140 #define V_TRGT1BARTYPEERR(x) ((x) << S_TRGT1BARTYPEERR)
5141 #define F_TRGT1BARTYPEERR    V_TRGT1BARTYPEERR(1U)
5142 
5143 #define S_MAEXTRARSPERR    27
5144 #define V_MAEXTRARSPERR(x) ((x) << S_MAEXTRARSPERR)
5145 #define F_MAEXTRARSPERR    V_MAEXTRARSPERR(1U)
5146 
5147 #define S_MARSPTIMEOUT    26
5148 #define V_MARSPTIMEOUT(x) ((x) << S_MARSPTIMEOUT)
5149 #define F_MARSPTIMEOUT    V_MARSPTIMEOUT(1U)
5150 
5151 #define S_INTVFALLMSIDISERR    25
5152 #define V_INTVFALLMSIDISERR(x) ((x) << S_INTVFALLMSIDISERR)
5153 #define F_INTVFALLMSIDISERR    V_INTVFALLMSIDISERR(1U)
5154 
5155 #define S_INTVFRANGEERR    24
5156 #define V_INTVFRANGEERR(x) ((x) << S_INTVFRANGEERR)
5157 #define F_INTVFRANGEERR    V_INTVFRANGEERR(1U)
5158 
5159 #define S_INTPLIRSPERR    23
5160 #define V_INTPLIRSPERR(x) ((x) << S_INTPLIRSPERR)
5161 #define F_INTPLIRSPERR    V_INTPLIRSPERR(1U)
5162 
5163 #define S_MEMREQRDTAGERR    22
5164 #define V_MEMREQRDTAGERR(x) ((x) << S_MEMREQRDTAGERR)
5165 #define F_MEMREQRDTAGERR    V_MEMREQRDTAGERR(1U)
5166 
5167 #define S_CFGINITDONEERR    21
5168 #define V_CFGINITDONEERR(x) ((x) << S_CFGINITDONEERR)
5169 #define F_CFGINITDONEERR    V_CFGINITDONEERR(1U)
5170 
5171 #define S_BAR2TIMEOUT    20
5172 #define V_BAR2TIMEOUT(x) ((x) << S_BAR2TIMEOUT)
5173 #define F_BAR2TIMEOUT    V_BAR2TIMEOUT(1U)
5174 
5175 #define S_VPDTIMEOUT    19
5176 #define V_VPDTIMEOUT(x) ((x) << S_VPDTIMEOUT)
5177 #define F_VPDTIMEOUT    V_VPDTIMEOUT(1U)
5178 
5179 #define S_MEMRSPRDTAGERR    18
5180 #define V_MEMRSPRDTAGERR(x) ((x) << S_MEMRSPRDTAGERR)
5181 #define F_MEMRSPRDTAGERR    V_MEMRSPRDTAGERR(1U)
5182 
5183 #define S_MEMRSPWRTAGERR    17
5184 #define V_MEMRSPWRTAGERR(x) ((x) << S_MEMRSPWRTAGERR)
5185 #define F_MEMRSPWRTAGERR    V_MEMRSPWRTAGERR(1U)
5186 
5187 #define S_PIORSPRDTAGERR    16
5188 #define V_PIORSPRDTAGERR(x) ((x) << S_PIORSPRDTAGERR)
5189 #define F_PIORSPRDTAGERR    V_PIORSPRDTAGERR(1U)
5190 
5191 #define S_PIORSPWRTAGERR    15
5192 #define V_PIORSPWRTAGERR(x) ((x) << S_PIORSPWRTAGERR)
5193 #define F_PIORSPWRTAGERR    V_PIORSPWRTAGERR(1U)
5194 
5195 #define S_DBITIMEOUT    14
5196 #define V_DBITIMEOUT(x) ((x) << S_DBITIMEOUT)
5197 #define F_DBITIMEOUT    V_DBITIMEOUT(1U)
5198 
5199 #define S_PIOUNALINDWR    13
5200 #define V_PIOUNALINDWR(x) ((x) << S_PIOUNALINDWR)
5201 #define F_PIOUNALINDWR    V_PIOUNALINDWR(1U)
5202 
5203 #define S_BAR2RDERR    12
5204 #define V_BAR2RDERR(x) ((x) << S_BAR2RDERR)
5205 #define F_BAR2RDERR    V_BAR2RDERR(1U)
5206 
5207 #define S_MAWREOPERR    11
5208 #define V_MAWREOPERR(x) ((x) << S_MAWREOPERR)
5209 #define F_MAWREOPERR    V_MAWREOPERR(1U)
5210 
5211 #define S_MARDEOPERR    10
5212 #define V_MARDEOPERR(x) ((x) << S_MARDEOPERR)
5213 #define F_MARDEOPERR    V_MARDEOPERR(1U)
5214 
5215 #define S_BAR2REQ    2
5216 #define V_BAR2REQ(x) ((x) << S_BAR2REQ)
5217 #define F_BAR2REQ    V_BAR2REQ(1U)
5218 
5219 #define S_MARSPUE    30
5220 #define V_MARSPUE(x) ((x) << S_MARSPUE)
5221 #define F_MARSPUE    V_MARSPUE(1U)
5222 
5223 #define S_KDBEOPERR    7
5224 #define V_KDBEOPERR(x) ((x) << S_KDBEOPERR)
5225 #define F_KDBEOPERR    V_KDBEOPERR(1U)
5226 
5227 #define A_PCIE_CFG 0x3014
5228 
5229 #define S_CFGDMAXPYLDSZRX    26
5230 #define M_CFGDMAXPYLDSZRX    0x7U
5231 #define V_CFGDMAXPYLDSZRX(x) ((x) << S_CFGDMAXPYLDSZRX)
5232 #define G_CFGDMAXPYLDSZRX(x) (((x) >> S_CFGDMAXPYLDSZRX) & M_CFGDMAXPYLDSZRX)
5233 
5234 #define S_CFGDMAXPYLDSZTX    23
5235 #define M_CFGDMAXPYLDSZTX    0x7U
5236 #define V_CFGDMAXPYLDSZTX(x) ((x) << S_CFGDMAXPYLDSZTX)
5237 #define G_CFGDMAXPYLDSZTX(x) (((x) >> S_CFGDMAXPYLDSZTX) & M_CFGDMAXPYLDSZTX)
5238 
5239 #define S_CFGDMAXRDREQSZ    20
5240 #define M_CFGDMAXRDREQSZ    0x7U
5241 #define V_CFGDMAXRDREQSZ(x) ((x) << S_CFGDMAXRDREQSZ)
5242 #define G_CFGDMAXRDREQSZ(x) (((x) >> S_CFGDMAXRDREQSZ) & M_CFGDMAXRDREQSZ)
5243 
5244 #define S_MASYNCEN    19
5245 #define V_MASYNCEN(x) ((x) << S_MASYNCEN)
5246 #define F_MASYNCEN    V_MASYNCEN(1U)
5247 
5248 #define S_DCAENDMA    18
5249 #define V_DCAENDMA(x) ((x) << S_DCAENDMA)
5250 #define F_DCAENDMA    V_DCAENDMA(1U)
5251 
5252 #define S_DCAENCMD    17
5253 #define V_DCAENCMD(x) ((x) << S_DCAENCMD)
5254 #define F_DCAENCMD    V_DCAENCMD(1U)
5255 
5256 #define S_VFMSIPNDEN    16
5257 #define V_VFMSIPNDEN(x) ((x) << S_VFMSIPNDEN)
5258 #define F_VFMSIPNDEN    V_VFMSIPNDEN(1U)
5259 
5260 #define S_FORCETXERROR    15
5261 #define V_FORCETXERROR(x) ((x) << S_FORCETXERROR)
5262 #define F_FORCETXERROR    V_FORCETXERROR(1U)
5263 
5264 #define S_VPDREQPROTECT    14
5265 #define V_VPDREQPROTECT(x) ((x) << S_VPDREQPROTECT)
5266 #define F_VPDREQPROTECT    V_VPDREQPROTECT(1U)
5267 
5268 #define S_FIDTABLEINVALID    13
5269 #define V_FIDTABLEINVALID(x) ((x) << S_FIDTABLEINVALID)
5270 #define F_FIDTABLEINVALID    V_FIDTABLEINVALID(1U)
5271 
5272 #define S_BYPASSMSIXCACHE    12
5273 #define V_BYPASSMSIXCACHE(x) ((x) << S_BYPASSMSIXCACHE)
5274 #define F_BYPASSMSIXCACHE    V_BYPASSMSIXCACHE(1U)
5275 
5276 #define S_BYPASSMSICACHE    11
5277 #define V_BYPASSMSICACHE(x) ((x) << S_BYPASSMSICACHE)
5278 #define F_BYPASSMSICACHE    V_BYPASSMSICACHE(1U)
5279 
5280 #define S_SIMSPEED    10
5281 #define V_SIMSPEED(x) ((x) << S_SIMSPEED)
5282 #define F_SIMSPEED    V_SIMSPEED(1U)
5283 
5284 #define S_TC0_STAMP    9
5285 #define V_TC0_STAMP(x) ((x) << S_TC0_STAMP)
5286 #define F_TC0_STAMP    V_TC0_STAMP(1U)
5287 
5288 #define S_AI_TCVAL    6
5289 #define M_AI_TCVAL    0x7U
5290 #define V_AI_TCVAL(x) ((x) << S_AI_TCVAL)
5291 #define G_AI_TCVAL(x) (((x) >> S_AI_TCVAL) & M_AI_TCVAL)
5292 
5293 #define S_DMASTOPEN    5
5294 #define V_DMASTOPEN(x) ((x) << S_DMASTOPEN)
5295 #define F_DMASTOPEN    V_DMASTOPEN(1U)
5296 
5297 #define S_DEVSTATERSTMODE    4
5298 #define V_DEVSTATERSTMODE(x) ((x) << S_DEVSTATERSTMODE)
5299 #define F_DEVSTATERSTMODE    V_DEVSTATERSTMODE(1U)
5300 
5301 #define S_HOTRSTPCIECRSTMODE    3
5302 #define V_HOTRSTPCIECRSTMODE(x) ((x) << S_HOTRSTPCIECRSTMODE)
5303 #define F_HOTRSTPCIECRSTMODE    V_HOTRSTPCIECRSTMODE(1U)
5304 
5305 #define S_DLDNPCIECRSTMODE    2
5306 #define V_DLDNPCIECRSTMODE(x) ((x) << S_DLDNPCIECRSTMODE)
5307 #define F_DLDNPCIECRSTMODE    V_DLDNPCIECRSTMODE(1U)
5308 
5309 #define S_DLDNPCIEPRECRSTMODE    1
5310 #define V_DLDNPCIEPRECRSTMODE(x) ((x) << S_DLDNPCIEPRECRSTMODE)
5311 #define F_DLDNPCIEPRECRSTMODE    V_DLDNPCIEPRECRSTMODE(1U)
5312 
5313 #define S_LINKDNRSTEN    0
5314 #define V_LINKDNRSTEN(x) ((x) << S_LINKDNRSTEN)
5315 #define F_LINKDNRSTEN    V_LINKDNRSTEN(1U)
5316 
5317 #define S_T5_PIOSTOPEN    31
5318 #define V_T5_PIOSTOPEN(x) ((x) << S_T5_PIOSTOPEN)
5319 #define F_T5_PIOSTOPEN    V_T5_PIOSTOPEN(1U)
5320 
5321 #define S_DIAGCTRLBUS    28
5322 #define M_DIAGCTRLBUS    0x7U
5323 #define V_DIAGCTRLBUS(x) ((x) << S_DIAGCTRLBUS)
5324 #define G_DIAGCTRLBUS(x) (((x) >> S_DIAGCTRLBUS) & M_DIAGCTRLBUS)
5325 
5326 #define S_IPPERREN    27
5327 #define V_IPPERREN(x) ((x) << S_IPPERREN)
5328 #define F_IPPERREN    V_IPPERREN(1U)
5329 
5330 #define S_CFGDEXTTAGEN    26
5331 #define V_CFGDEXTTAGEN(x) ((x) << S_CFGDEXTTAGEN)
5332 #define F_CFGDEXTTAGEN    V_CFGDEXTTAGEN(1U)
5333 
5334 #define S_CFGDMAXPYLDSZ    23
5335 #define M_CFGDMAXPYLDSZ    0x7U
5336 #define V_CFGDMAXPYLDSZ(x) ((x) << S_CFGDMAXPYLDSZ)
5337 #define G_CFGDMAXPYLDSZ(x) (((x) >> S_CFGDMAXPYLDSZ) & M_CFGDMAXPYLDSZ)
5338 
5339 #define S_DCAEN    17
5340 #define V_DCAEN(x) ((x) << S_DCAEN)
5341 #define F_DCAEN    V_DCAEN(1U)
5342 
5343 #define S_T5CMDREQPRIORITY    16
5344 #define V_T5CMDREQPRIORITY(x) ((x) << S_T5CMDREQPRIORITY)
5345 #define F_T5CMDREQPRIORITY    V_T5CMDREQPRIORITY(1U)
5346 
5347 #define S_T5VPDREQPROTECT    14
5348 #define M_T5VPDREQPROTECT    0x3U
5349 #define V_T5VPDREQPROTECT(x) ((x) << S_T5VPDREQPROTECT)
5350 #define G_T5VPDREQPROTECT(x) (((x) >> S_T5VPDREQPROTECT) & M_T5VPDREQPROTECT)
5351 
5352 #define S_DROPPEDRDRSPDATA    12
5353 #define V_DROPPEDRDRSPDATA(x) ((x) << S_DROPPEDRDRSPDATA)
5354 #define F_DROPPEDRDRSPDATA    V_DROPPEDRDRSPDATA(1U)
5355 
5356 #define S_AI_INTX_REASSERTEN    11
5357 #define V_AI_INTX_REASSERTEN(x) ((x) << S_AI_INTX_REASSERTEN)
5358 #define F_AI_INTX_REASSERTEN    V_AI_INTX_REASSERTEN(1U)
5359 
5360 #define S_AUTOTXNDISABLE    10
5361 #define V_AUTOTXNDISABLE(x) ((x) << S_AUTOTXNDISABLE)
5362 #define F_AUTOTXNDISABLE    V_AUTOTXNDISABLE(1U)
5363 
5364 #define S_LINKREQRSTPCIECRSTMODE    3
5365 #define V_LINKREQRSTPCIECRSTMODE(x) ((x) << S_LINKREQRSTPCIECRSTMODE)
5366 #define F_LINKREQRSTPCIECRSTMODE    V_LINKREQRSTPCIECRSTMODE(1U)
5367 
5368 #define A_PCIE_DMA_CTRL 0x3018
5369 
5370 #define S_LITTLEENDIAN    7
5371 #define V_LITTLEENDIAN(x) ((x) << S_LITTLEENDIAN)
5372 #define F_LITTLEENDIAN    V_LITTLEENDIAN(1U)
5373 
5374 #define A_PCIE_CFG2 0x3018
5375 
5376 #define S_VPDTIMER    16
5377 #define M_VPDTIMER    0xffffU
5378 #define V_VPDTIMER(x) ((x) << S_VPDTIMER)
5379 #define G_VPDTIMER(x) (((x) >> S_VPDTIMER) & M_VPDTIMER)
5380 
5381 #define S_BAR2TIMER    4
5382 #define M_BAR2TIMER    0xfffU
5383 #define V_BAR2TIMER(x) ((x) << S_BAR2TIMER)
5384 #define G_BAR2TIMER(x) (((x) >> S_BAR2TIMER) & M_BAR2TIMER)
5385 
5386 #define S_MSTREQRDRRASIMPLE    3
5387 #define V_MSTREQRDRRASIMPLE(x) ((x) << S_MSTREQRDRRASIMPLE)
5388 #define F_MSTREQRDRRASIMPLE    V_MSTREQRDRRASIMPLE(1U)
5389 
5390 #define S_TOTMAXTAG    0
5391 #define M_TOTMAXTAG    0x3U
5392 #define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG)
5393 #define G_TOTMAXTAG(x) (((x) >> S_TOTMAXTAG) & M_TOTMAXTAG)
5394 
5395 #define S_T6_TOTMAXTAG    0
5396 #define M_T6_TOTMAXTAG    0x7U
5397 #define V_T6_TOTMAXTAG(x) ((x) << S_T6_TOTMAXTAG)
5398 #define G_T6_TOTMAXTAG(x) (((x) >> S_T6_TOTMAXTAG) & M_T6_TOTMAXTAG)
5399 
5400 #define S_REG_VDM_ONLY    17
5401 #define V_REG_VDM_ONLY(x) ((x) << S_REG_VDM_ONLY)
5402 #define F_REG_VDM_ONLY    V_REG_VDM_ONLY(1U)
5403 
5404 #define S_MULT_REQID_SUP    16
5405 #define V_MULT_REQID_SUP(x) ((x) << S_MULT_REQID_SUP)
5406 #define F_MULT_REQID_SUP    V_MULT_REQID_SUP(1U)
5407 
5408 #define A_PCIE_DMA_CFG 0x301c
5409 
5410 #define S_MAXPYLDSIZE    28
5411 #define M_MAXPYLDSIZE    0x7U
5412 #define V_MAXPYLDSIZE(x) ((x) << S_MAXPYLDSIZE)
5413 #define G_MAXPYLDSIZE(x) (((x) >> S_MAXPYLDSIZE) & M_MAXPYLDSIZE)
5414 
5415 #define S_MAXRDREQSIZE    25
5416 #define M_MAXRDREQSIZE    0x7U
5417 #define V_MAXRDREQSIZE(x) ((x) << S_MAXRDREQSIZE)
5418 #define G_MAXRDREQSIZE(x) (((x) >> S_MAXRDREQSIZE) & M_MAXRDREQSIZE)
5419 
5420 #define S_DMA_MAXRSPCNT    16
5421 #define M_DMA_MAXRSPCNT    0x1ffU
5422 #define V_DMA_MAXRSPCNT(x) ((x) << S_DMA_MAXRSPCNT)
5423 #define G_DMA_MAXRSPCNT(x) (((x) >> S_DMA_MAXRSPCNT) & M_DMA_MAXRSPCNT)
5424 
5425 #define S_DMA_MAXREQCNT    8
5426 #define M_DMA_MAXREQCNT    0xffU
5427 #define V_DMA_MAXREQCNT(x) ((x) << S_DMA_MAXREQCNT)
5428 #define G_DMA_MAXREQCNT(x) (((x) >> S_DMA_MAXREQCNT) & M_DMA_MAXREQCNT)
5429 
5430 #define S_MAXTAG    0
5431 #define M_MAXTAG    0x7fU
5432 #define V_MAXTAG(x) ((x) << S_MAXTAG)
5433 #define G_MAXTAG(x) (((x) >> S_MAXTAG) & M_MAXTAG)
5434 
5435 #define A_PCIE_CFG3 0x301c
5436 
5437 #define S_AUTOPIOCOOKIEMATCH    6
5438 #define V_AUTOPIOCOOKIEMATCH(x) ((x) << S_AUTOPIOCOOKIEMATCH)
5439 #define F_AUTOPIOCOOKIEMATCH    V_AUTOPIOCOOKIEMATCH(1U)
5440 
5441 #define S_FLRPNDCPLMODE    4
5442 #define M_FLRPNDCPLMODE    0x3U
5443 #define V_FLRPNDCPLMODE(x) ((x) << S_FLRPNDCPLMODE)
5444 #define G_FLRPNDCPLMODE(x) (((x) >> S_FLRPNDCPLMODE) & M_FLRPNDCPLMODE)
5445 
5446 #define S_HMADCASTFIRSTONLY    2
5447 #define V_HMADCASTFIRSTONLY(x) ((x) << S_HMADCASTFIRSTONLY)
5448 #define F_HMADCASTFIRSTONLY    V_HMADCASTFIRSTONLY(1U)
5449 
5450 #define S_CMDDCASTFIRSTONLY    1
5451 #define V_CMDDCASTFIRSTONLY(x) ((x) << S_CMDDCASTFIRSTONLY)
5452 #define F_CMDDCASTFIRSTONLY    V_CMDDCASTFIRSTONLY(1U)
5453 
5454 #define S_DMADCASTFIRSTONLY    0
5455 #define V_DMADCASTFIRSTONLY(x) ((x) << S_DMADCASTFIRSTONLY)
5456 #define F_DMADCASTFIRSTONLY    V_DMADCASTFIRSTONLY(1U)
5457 
5458 #define S_ARMDCASTFIRSTONLY    7
5459 #define V_ARMDCASTFIRSTONLY(x) ((x) << S_ARMDCASTFIRSTONLY)
5460 #define F_ARMDCASTFIRSTONLY    V_ARMDCASTFIRSTONLY(1U)
5461 
5462 #define A_PCIE_DMA_STAT 0x3020
5463 
5464 #define S_STATEREQ    28
5465 #define M_STATEREQ    0xfU
5466 #define V_STATEREQ(x) ((x) << S_STATEREQ)
5467 #define G_STATEREQ(x) (((x) >> S_STATEREQ) & M_STATEREQ)
5468 
5469 #define S_DMA_RSPCNT    16
5470 #define M_DMA_RSPCNT    0xfffU
5471 #define V_DMA_RSPCNT(x) ((x) << S_DMA_RSPCNT)
5472 #define G_DMA_RSPCNT(x) (((x) >> S_DMA_RSPCNT) & M_DMA_RSPCNT)
5473 
5474 #define S_STATEAREQ    13
5475 #define M_STATEAREQ    0x7U
5476 #define V_STATEAREQ(x) ((x) << S_STATEAREQ)
5477 #define G_STATEAREQ(x) (((x) >> S_STATEAREQ) & M_STATEAREQ)
5478 
5479 #define S_TAGFREE    12
5480 #define V_TAGFREE(x) ((x) << S_TAGFREE)
5481 #define F_TAGFREE    V_TAGFREE(1U)
5482 
5483 #define S_DMA_REQCNT    0
5484 #define M_DMA_REQCNT    0x7ffU
5485 #define V_DMA_REQCNT(x) ((x) << S_DMA_REQCNT)
5486 #define G_DMA_REQCNT(x) (((x) >> S_DMA_REQCNT) & M_DMA_REQCNT)
5487 
5488 #define A_PCIE_CFG4 0x3020
5489 
5490 #define S_L1CLKREMOVALEN    17
5491 #define V_L1CLKREMOVALEN(x) ((x) << S_L1CLKREMOVALEN)
5492 #define F_L1CLKREMOVALEN    V_L1CLKREMOVALEN(1U)
5493 
5494 #define S_READYENTERL23    16
5495 #define V_READYENTERL23(x) ((x) << S_READYENTERL23)
5496 #define F_READYENTERL23    V_READYENTERL23(1U)
5497 
5498 #define S_EXITL1    12
5499 #define V_EXITL1(x) ((x) << S_EXITL1)
5500 #define F_EXITL1    V_EXITL1(1U)
5501 
5502 #define S_ENTERL1    8
5503 #define V_ENTERL1(x) ((x) << S_ENTERL1)
5504 #define F_ENTERL1    V_ENTERL1(1U)
5505 
5506 #define S_GENPME    0
5507 #define M_GENPME    0xffU
5508 #define V_GENPME(x) ((x) << S_GENPME)
5509 #define G_GENPME(x) (((x) >> S_GENPME) & M_GENPME)
5510 
5511 #define A_PCIE_CFG5 0x3024
5512 
5513 #define S_ENABLESKPPARITYFIX    2
5514 #define V_ENABLESKPPARITYFIX(x) ((x) << S_ENABLESKPPARITYFIX)
5515 #define F_ENABLESKPPARITYFIX    V_ENABLESKPPARITYFIX(1U)
5516 
5517 #define S_ENABLEL2ENTRYINL1    1
5518 #define V_ENABLEL2ENTRYINL1(x) ((x) << S_ENABLEL2ENTRYINL1)
5519 #define F_ENABLEL2ENTRYINL1    V_ENABLEL2ENTRYINL1(1U)
5520 
5521 #define S_HOLDCPLENTERINGL1    0
5522 #define V_HOLDCPLENTERINGL1(x) ((x) << S_HOLDCPLENTERINGL1)
5523 #define F_HOLDCPLENTERINGL1    V_HOLDCPLENTERINGL1(1U)
5524 
5525 #define A_PCIE_CFG6 0x3028
5526 
5527 #define S_PERSTTIMERCOUNT    12
5528 #define M_PERSTTIMERCOUNT    0x3fffU
5529 #define V_PERSTTIMERCOUNT(x) ((x) << S_PERSTTIMERCOUNT)
5530 #define G_PERSTTIMERCOUNT(x) (((x) >> S_PERSTTIMERCOUNT) & M_PERSTTIMERCOUNT)
5531 
5532 #define S_PERSTTIMEOUT    8
5533 #define V_PERSTTIMEOUT(x) ((x) << S_PERSTTIMEOUT)
5534 #define F_PERSTTIMEOUT    V_PERSTTIMEOUT(1U)
5535 
5536 #define S_PERSTTIMER    0
5537 #define M_PERSTTIMER    0xfU
5538 #define V_PERSTTIMER(x) ((x) << S_PERSTTIMER)
5539 #define G_PERSTTIMER(x) (((x) >> S_PERSTTIMER) & M_PERSTTIMER)
5540 
5541 #define A_PCIE_CFG7 0x302c
5542 #define A_PCIE_INT_ENABLE_EXT 0x3030
5543 
5544 #define S_TCAMRSPERR    31
5545 #define V_TCAMRSPERR(x) ((x) << S_TCAMRSPERR)
5546 #define F_TCAMRSPERR    V_TCAMRSPERR(1U)
5547 
5548 #define S_IPFORMQPERR    30
5549 #define V_IPFORMQPERR(x) ((x) << S_IPFORMQPERR)
5550 #define F_IPFORMQPERR    V_IPFORMQPERR(1U)
5551 
5552 #define S_IPFORMQCERR    29
5553 #define V_IPFORMQCERR(x) ((x) << S_IPFORMQCERR)
5554 #define F_IPFORMQCERR    V_IPFORMQCERR(1U)
5555 
5556 #define S_TRGT1GRPCERR    28
5557 #define V_TRGT1GRPCERR(x) ((x) << S_TRGT1GRPCERR)
5558 #define F_TRGT1GRPCERR    V_TRGT1GRPCERR(1U)
5559 
5560 #define S_IPSOTCERR    27
5561 #define V_IPSOTCERR(x) ((x) << S_IPSOTCERR)
5562 #define F_IPSOTCERR    V_IPSOTCERR(1U)
5563 
5564 #define S_IPRETRYCERR    26
5565 #define V_IPRETRYCERR(x) ((x) << S_IPRETRYCERR)
5566 #define F_IPRETRYCERR    V_IPRETRYCERR(1U)
5567 
5568 #define S_IPRXDATAGRPCERR    25
5569 #define V_IPRXDATAGRPCERR(x) ((x) << S_IPRXDATAGRPCERR)
5570 #define F_IPRXDATAGRPCERR    V_IPRXDATAGRPCERR(1U)
5571 
5572 #define S_IPRXHDRGRPCERR    24
5573 #define V_IPRXHDRGRPCERR(x) ((x) << S_IPRXHDRGRPCERR)
5574 #define F_IPRXHDRGRPCERR    V_IPRXHDRGRPCERR(1U)
5575 
5576 #define S_A0ARBRSPORDFIFOPERR    19
5577 #define V_A0ARBRSPORDFIFOPERR(x) ((x) << S_A0ARBRSPORDFIFOPERR)
5578 #define F_A0ARBRSPORDFIFOPERR    V_A0ARBRSPORDFIFOPERR(1U)
5579 
5580 #define S_HRSPCERR    18
5581 #define V_HRSPCERR(x) ((x) << S_HRSPCERR)
5582 #define F_HRSPCERR    V_HRSPCERR(1U)
5583 
5584 #define S_HREQRDCERR    17
5585 #define V_HREQRDCERR(x) ((x) << S_HREQRDCERR)
5586 #define F_HREQRDCERR    V_HREQRDCERR(1U)
5587 
5588 #define S_HREQWRCERR    16
5589 #define V_HREQWRCERR(x) ((x) << S_HREQWRCERR)
5590 #define F_HREQWRCERR    V_HREQWRCERR(1U)
5591 
5592 #define S_DRSPCERR    15
5593 #define V_DRSPCERR(x) ((x) << S_DRSPCERR)
5594 #define F_DRSPCERR    V_DRSPCERR(1U)
5595 
5596 #define S_DREQRDCERR    14
5597 #define V_DREQRDCERR(x) ((x) << S_DREQRDCERR)
5598 #define F_DREQRDCERR    V_DREQRDCERR(1U)
5599 
5600 #define S_DREQWRCERR    13
5601 #define V_DREQWRCERR(x) ((x) << S_DREQWRCERR)
5602 #define F_DREQWRCERR    V_DREQWRCERR(1U)
5603 
5604 #define S_CRSPCERR    12
5605 #define V_CRSPCERR(x) ((x) << S_CRSPCERR)
5606 #define F_CRSPCERR    V_CRSPCERR(1U)
5607 
5608 #define S_ARSPPERR    11
5609 #define V_ARSPPERR(x) ((x) << S_ARSPPERR)
5610 #define F_ARSPPERR    V_ARSPPERR(1U)
5611 
5612 #define S_AREQRDPERR    10
5613 #define V_AREQRDPERR(x) ((x) << S_AREQRDPERR)
5614 #define F_AREQRDPERR    V_AREQRDPERR(1U)
5615 
5616 #define S_AREQWRPERR    9
5617 #define V_AREQWRPERR(x) ((x) << S_AREQWRPERR)
5618 #define F_AREQWRPERR    V_AREQWRPERR(1U)
5619 
5620 #define S_PIOREQGRPCERR    8
5621 #define V_PIOREQGRPCERR(x) ((x) << S_PIOREQGRPCERR)
5622 #define F_PIOREQGRPCERR    V_PIOREQGRPCERR(1U)
5623 
5624 #define S_ARSPCERR    7
5625 #define V_ARSPCERR(x) ((x) << S_ARSPCERR)
5626 #define F_ARSPCERR    V_ARSPCERR(1U)
5627 
5628 #define S_AREQRDCERR    6
5629 #define V_AREQRDCERR(x) ((x) << S_AREQRDCERR)
5630 #define F_AREQRDCERR    V_AREQRDCERR(1U)
5631 
5632 #define S_AREQWRCERR    5
5633 #define V_AREQWRCERR(x) ((x) << S_AREQWRCERR)
5634 #define F_AREQWRCERR    V_AREQWRCERR(1U)
5635 
5636 #define S_MARSPPERR    4
5637 #define V_MARSPPERR(x) ((x) << S_MARSPPERR)
5638 #define F_MARSPPERR    V_MARSPPERR(1U)
5639 
5640 #define S_INICMAWDATAORDPERR    3
5641 #define V_INICMAWDATAORDPERR(x) ((x) << S_INICMAWDATAORDPERR)
5642 #define F_INICMAWDATAORDPERR    V_INICMAWDATAORDPERR(1U)
5643 
5644 #define S_EMUPERR    2
5645 #define V_EMUPERR(x) ((x) << S_EMUPERR)
5646 #define F_EMUPERR    V_EMUPERR(1U)
5647 
5648 #define S_ERRSPPERR    1
5649 #define V_ERRSPPERR(x) ((x) << S_ERRSPPERR)
5650 #define F_ERRSPPERR    V_ERRSPPERR(1U)
5651 
5652 #define S_MSTGRPCERR    0
5653 #define V_MSTGRPCERR(x) ((x) << S_MSTGRPCERR)
5654 #define F_MSTGRPCERR    V_MSTGRPCERR(1U)
5655 
5656 #define A_PCIE_INT_ENABLE_X8 0x3034
5657 
5658 #define S_X8TGTGRPPERR    23
5659 #define V_X8TGTGRPPERR(x) ((x) << S_X8TGTGRPPERR)
5660 #define F_X8TGTGRPPERR    V_X8TGTGRPPERR(1U)
5661 
5662 #define S_X8IPSOTPERR    22
5663 #define V_X8IPSOTPERR(x) ((x) << S_X8IPSOTPERR)
5664 #define F_X8IPSOTPERR    V_X8IPSOTPERR(1U)
5665 
5666 #define S_X8IPRETRYPERR    21
5667 #define V_X8IPRETRYPERR(x) ((x) << S_X8IPRETRYPERR)
5668 #define F_X8IPRETRYPERR    V_X8IPRETRYPERR(1U)
5669 
5670 #define S_X8IPRXDATAGRPPERR    20
5671 #define V_X8IPRXDATAGRPPERR(x) ((x) << S_X8IPRXDATAGRPPERR)
5672 #define F_X8IPRXDATAGRPPERR    V_X8IPRXDATAGRPPERR(1U)
5673 
5674 #define S_X8IPRXHDRGRPPERR    19
5675 #define V_X8IPRXHDRGRPPERR(x) ((x) << S_X8IPRXHDRGRPPERR)
5676 #define F_X8IPRXHDRGRPPERR    V_X8IPRXHDRGRPPERR(1U)
5677 
5678 #define S_X8IPCORECERR    3
5679 #define V_X8IPCORECERR(x) ((x) << S_X8IPCORECERR)
5680 #define F_X8IPCORECERR    V_X8IPCORECERR(1U)
5681 
5682 #define S_X8MSTGRPPERR    2
5683 #define V_X8MSTGRPPERR(x) ((x) << S_X8MSTGRPPERR)
5684 #define F_X8MSTGRPPERR    V_X8MSTGRPPERR(1U)
5685 
5686 #define S_X8MSTGRPCERR    1
5687 #define V_X8MSTGRPCERR(x) ((x) << S_X8MSTGRPCERR)
5688 #define F_X8MSTGRPCERR    V_X8MSTGRPCERR(1U)
5689 
5690 #define A_PCIE_INT_CAUSE_EXT 0x3038
5691 #define A_PCIE_CMD_CTRL 0x303c
5692 #define A_PCIE_INT_CAUSE_X8 0x303c
5693 #define A_PCIE_CMD_CFG 0x3040
5694 
5695 #define S_MAXRSPCNT    16
5696 #define M_MAXRSPCNT    0xfU
5697 #define V_MAXRSPCNT(x) ((x) << S_MAXRSPCNT)
5698 #define G_MAXRSPCNT(x) (((x) >> S_MAXRSPCNT) & M_MAXRSPCNT)
5699 
5700 #define S_MAXREQCNT    8
5701 #define M_MAXREQCNT    0x1fU
5702 #define V_MAXREQCNT(x) ((x) << S_MAXREQCNT)
5703 #define G_MAXREQCNT(x) (((x) >> S_MAXREQCNT) & M_MAXREQCNT)
5704 
5705 #define A_PCIE_PERR_ENABLE_EXT 0x3040
5706 
5707 #define S_T7_ARSPPERR    18
5708 #define V_T7_ARSPPERR(x) ((x) << S_T7_ARSPPERR)
5709 #define F_T7_ARSPPERR    V_T7_ARSPPERR(1U)
5710 
5711 #define S_T7_AREQRDPERR    17
5712 #define V_T7_AREQRDPERR(x) ((x) << S_T7_AREQRDPERR)
5713 #define F_T7_AREQRDPERR    V_T7_AREQRDPERR(1U)
5714 
5715 #define S_T7_AREQWRPERR    16
5716 #define V_T7_AREQWRPERR(x) ((x) << S_T7_AREQWRPERR)
5717 #define F_T7_AREQWRPERR    V_T7_AREQWRPERR(1U)
5718 
5719 #define S_T7_A0ARBRSPORDFIFOPERR    15
5720 #define V_T7_A0ARBRSPORDFIFOPERR(x) ((x) << S_T7_A0ARBRSPORDFIFOPERR)
5721 #define F_T7_A0ARBRSPORDFIFOPERR    V_T7_A0ARBRSPORDFIFOPERR(1U)
5722 
5723 #define S_T7_MARSPPERR    14
5724 #define V_T7_MARSPPERR(x) ((x) << S_T7_MARSPPERR)
5725 #define F_T7_MARSPPERR    V_T7_MARSPPERR(1U)
5726 
5727 #define S_T7_INICMAWDATAORDPERR    13
5728 #define V_T7_INICMAWDATAORDPERR(x) ((x) << S_T7_INICMAWDATAORDPERR)
5729 #define F_T7_INICMAWDATAORDPERR    V_T7_INICMAWDATAORDPERR(1U)
5730 
5731 #define S_T7_EMUPERR    12
5732 #define V_T7_EMUPERR(x) ((x) << S_T7_EMUPERR)
5733 #define F_T7_EMUPERR    V_T7_EMUPERR(1U)
5734 
5735 #define S_T7_ERRSPPERR    11
5736 #define V_T7_ERRSPPERR(x) ((x) << S_T7_ERRSPPERR)
5737 #define F_T7_ERRSPPERR    V_T7_ERRSPPERR(1U)
5738 
5739 #define A_PCIE_CMD_STAT 0x3044
5740 
5741 #define S_RSPCNT    16
5742 #define M_RSPCNT    0x7fU
5743 #define V_RSPCNT(x) ((x) << S_RSPCNT)
5744 #define G_RSPCNT(x) (((x) >> S_RSPCNT) & M_RSPCNT)
5745 
5746 #define S_REQCNT    0
5747 #define M_REQCNT    0xffU
5748 #define V_REQCNT(x) ((x) << S_REQCNT)
5749 #define G_REQCNT(x) (((x) >> S_REQCNT) & M_REQCNT)
5750 
5751 #define A_PCIE_PERR_ENABLE_X8 0x3044
5752 
5753 #define S_T7_X8TGTGRPPERR    28
5754 #define V_T7_X8TGTGRPPERR(x) ((x) << S_T7_X8TGTGRPPERR)
5755 #define F_T7_X8TGTGRPPERR    V_T7_X8TGTGRPPERR(1U)
5756 
5757 #define S_T7_X8IPSOTPERR    27
5758 #define V_T7_X8IPSOTPERR(x) ((x) << S_T7_X8IPSOTPERR)
5759 #define F_T7_X8IPSOTPERR    V_T7_X8IPSOTPERR(1U)
5760 
5761 #define S_T7_X8IPRETRYPERR    26
5762 #define V_T7_X8IPRETRYPERR(x) ((x) << S_T7_X8IPRETRYPERR)
5763 #define F_T7_X8IPRETRYPERR    V_T7_X8IPRETRYPERR(1U)
5764 
5765 #define S_T7_X8IPRXDATAGRPPERR    25
5766 #define V_T7_X8IPRXDATAGRPPERR(x) ((x) << S_T7_X8IPRXDATAGRPPERR)
5767 #define F_T7_X8IPRXDATAGRPPERR    V_T7_X8IPRXDATAGRPPERR(1U)
5768 
5769 #define S_T7_X8IPRXHDRGRPPERR    24
5770 #define V_T7_X8IPRXHDRGRPPERR(x) ((x) << S_T7_X8IPRXHDRGRPPERR)
5771 #define F_T7_X8IPRXHDRGRPPERR    V_T7_X8IPRXHDRGRPPERR(1U)
5772 
5773 #define S_T7_X8MSTGRPPERR    0
5774 #define V_T7_X8MSTGRPPERR(x) ((x) << S_T7_X8MSTGRPPERR)
5775 #define F_T7_X8MSTGRPPERR    V_T7_X8MSTGRPPERR(1U)
5776 
5777 #define A_PCIE_HMA_CTRL 0x3050
5778 
5779 #define S_IPLTSSM    12
5780 #define M_IPLTSSM    0xfU
5781 #define V_IPLTSSM(x) ((x) << S_IPLTSSM)
5782 #define G_IPLTSSM(x) (((x) >> S_IPLTSSM) & M_IPLTSSM)
5783 
5784 #define S_IPCONFIGDOWN    8
5785 #define M_IPCONFIGDOWN    0x7U
5786 #define V_IPCONFIGDOWN(x) ((x) << S_IPCONFIGDOWN)
5787 #define G_IPCONFIGDOWN(x) (((x) >> S_IPCONFIGDOWN) & M_IPCONFIGDOWN)
5788 
5789 #define A_PCIE_HMA_CFG 0x3054
5790 
5791 #define S_HMA_MAXRSPCNT    16
5792 #define M_HMA_MAXRSPCNT    0x1fU
5793 #define V_HMA_MAXRSPCNT(x) ((x) << S_HMA_MAXRSPCNT)
5794 #define G_HMA_MAXRSPCNT(x) (((x) >> S_HMA_MAXRSPCNT) & M_HMA_MAXRSPCNT)
5795 
5796 #define A_PCIE_HMA_STAT 0x3058
5797 
5798 #define S_HMA_RSPCNT    16
5799 #define M_HMA_RSPCNT    0xffU
5800 #define V_HMA_RSPCNT(x) ((x) << S_HMA_RSPCNT)
5801 #define G_HMA_RSPCNT(x) (((x) >> S_HMA_RSPCNT) & M_HMA_RSPCNT)
5802 
5803 #define A_PCIE_PIO_FIFO_CFG 0x305c
5804 
5805 #define S_CPLCONFIG    16
5806 #define M_CPLCONFIG    0xffffU
5807 #define V_CPLCONFIG(x) ((x) << S_CPLCONFIG)
5808 #define G_CPLCONFIG(x) (((x) >> S_CPLCONFIG) & M_CPLCONFIG)
5809 
5810 #define S_PIOSTOPEN    12
5811 #define V_PIOSTOPEN(x) ((x) << S_PIOSTOPEN)
5812 #define F_PIOSTOPEN    V_PIOSTOPEN(1U)
5813 
5814 #define S_IPLANESWAP    11
5815 #define V_IPLANESWAP(x) ((x) << S_IPLANESWAP)
5816 #define F_IPLANESWAP    V_IPLANESWAP(1U)
5817 
5818 #define S_FORCESTRICTTS1    10
5819 #define V_FORCESTRICTTS1(x) ((x) << S_FORCESTRICTTS1)
5820 #define F_FORCESTRICTTS1    V_FORCESTRICTTS1(1U)
5821 
5822 #define S_FORCEPROGRESSCNT    0
5823 #define M_FORCEPROGRESSCNT    0x3ffU
5824 #define V_FORCEPROGRESSCNT(x) ((x) << S_FORCEPROGRESSCNT)
5825 #define G_FORCEPROGRESSCNT(x) (((x) >> S_FORCEPROGRESSCNT) & M_FORCEPROGRESSCNT)
5826 
5827 #define A_PCIE_CFG_SPACE_REQ 0x3060
5828 
5829 #define S_ENABLE    30
5830 #define V_ENABLE(x) ((x) << S_ENABLE)
5831 #define F_ENABLE    V_ENABLE(1U)
5832 
5833 #define S_AI    29
5834 #define V_AI(x) ((x) << S_AI)
5835 #define F_AI    V_AI(1U)
5836 
5837 #define S_LOCALCFG    28
5838 #define V_LOCALCFG(x) ((x) << S_LOCALCFG)
5839 #define F_LOCALCFG    V_LOCALCFG(1U)
5840 
5841 #define S_BUS    20
5842 #define M_BUS    0xffU
5843 #define V_BUS(x) ((x) << S_BUS)
5844 #define G_BUS(x) (((x) >> S_BUS) & M_BUS)
5845 
5846 #define S_DEVICE    15
5847 #define M_DEVICE    0x1fU
5848 #define V_DEVICE(x) ((x) << S_DEVICE)
5849 #define G_DEVICE(x) (((x) >> S_DEVICE) & M_DEVICE)
5850 
5851 #define S_FUNCTION    12
5852 #define M_FUNCTION    0x7U
5853 #define V_FUNCTION(x) ((x) << S_FUNCTION)
5854 #define G_FUNCTION(x) (((x) >> S_FUNCTION) & M_FUNCTION)
5855 
5856 #define S_EXTREGISTER    8
5857 #define M_EXTREGISTER    0xfU
5858 #define V_EXTREGISTER(x) ((x) << S_EXTREGISTER)
5859 #define G_EXTREGISTER(x) (((x) >> S_EXTREGISTER) & M_EXTREGISTER)
5860 
5861 #define S_REGISTER    0
5862 #define M_REGISTER    0xffU
5863 #define V_REGISTER(x) ((x) << S_REGISTER)
5864 #define G_REGISTER(x) (((x) >> S_REGISTER) & M_REGISTER)
5865 
5866 #define S_CS2    28
5867 #define V_CS2(x) ((x) << S_CS2)
5868 #define F_CS2    V_CS2(1U)
5869 
5870 #define S_WRBE    24
5871 #define M_WRBE    0xfU
5872 #define V_WRBE(x) ((x) << S_WRBE)
5873 #define G_WRBE(x) (((x) >> S_WRBE) & M_WRBE)
5874 
5875 #define S_CFG_SPACE_VFVLD    23
5876 #define V_CFG_SPACE_VFVLD(x) ((x) << S_CFG_SPACE_VFVLD)
5877 #define F_CFG_SPACE_VFVLD    V_CFG_SPACE_VFVLD(1U)
5878 
5879 #define S_CFG_SPACE_RVF    16
5880 #define M_CFG_SPACE_RVF    0x7fU
5881 #define V_CFG_SPACE_RVF(x) ((x) << S_CFG_SPACE_RVF)
5882 #define G_CFG_SPACE_RVF(x) (((x) >> S_CFG_SPACE_RVF) & M_CFG_SPACE_RVF)
5883 
5884 #define S_CFG_SPACE_PF    12
5885 #define M_CFG_SPACE_PF    0x7U
5886 #define V_CFG_SPACE_PF(x) ((x) << S_CFG_SPACE_PF)
5887 #define G_CFG_SPACE_PF(x) (((x) >> S_CFG_SPACE_PF) & M_CFG_SPACE_PF)
5888 
5889 #define S_T6_ENABLE    31
5890 #define V_T6_ENABLE(x) ((x) << S_T6_ENABLE)
5891 #define F_T6_ENABLE    V_T6_ENABLE(1U)
5892 
5893 #define S_T6_1_AI    30
5894 #define V_T6_1_AI(x) ((x) << S_T6_1_AI)
5895 #define F_T6_1_AI    V_T6_1_AI(1U)
5896 
5897 #define S_T6_CS2    29
5898 #define V_T6_CS2(x) ((x) << S_T6_CS2)
5899 #define F_T6_CS2    V_T6_CS2(1U)
5900 
5901 #define S_T6_WRBE    25
5902 #define M_T6_WRBE    0xfU
5903 #define V_T6_WRBE(x) ((x) << S_T6_WRBE)
5904 #define G_T6_WRBE(x) (((x) >> S_T6_WRBE) & M_T6_WRBE)
5905 
5906 #define S_T6_CFG_SPACE_VFVLD    24
5907 #define V_T6_CFG_SPACE_VFVLD(x) ((x) << S_T6_CFG_SPACE_VFVLD)
5908 #define F_T6_CFG_SPACE_VFVLD    V_T6_CFG_SPACE_VFVLD(1U)
5909 
5910 #define S_T6_CFG_SPACE_RVF    16
5911 #define M_T6_CFG_SPACE_RVF    0xffU
5912 #define V_T6_CFG_SPACE_RVF(x) ((x) << S_T6_CFG_SPACE_RVF)
5913 #define G_T6_CFG_SPACE_RVF(x) (((x) >> S_T6_CFG_SPACE_RVF) & M_T6_CFG_SPACE_RVF)
5914 
5915 #define A_PCIE_CFG_SPACE_DATA 0x3064
5916 #define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068
5917 
5918 #define S_PCIEOFST    10
5919 #define M_PCIEOFST    0x3fffffU
5920 #define V_PCIEOFST(x) ((x) << S_PCIEOFST)
5921 #define G_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
5922 
5923 #define S_BIR    8
5924 #define M_BIR    0x3U
5925 #define V_BIR(x) ((x) << S_BIR)
5926 #define G_BIR(x) (((x) >> S_BIR) & M_BIR)
5927 
5928 #define S_WINDOW    0
5929 #define M_WINDOW    0xffU
5930 #define V_WINDOW(x) ((x) << S_WINDOW)
5931 #define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW)
5932 
5933 #define A_PCIE_MEM_ACCESS_OFFSET 0x306c
5934 
5935 #define S_MEMOFST    7
5936 #define M_MEMOFST    0x1ffffffU
5937 #define V_MEMOFST(x) ((x) << S_MEMOFST)
5938 #define G_MEMOFST(x) (((x) >> S_MEMOFST) & M_MEMOFST)
5939 
5940 #define A_T7_PCIE_MAILBOX_BASE_WIN 0x30a4
5941 #define A_PCIE_MAILBOX_BASE_WIN 0x30a8
5942 
5943 #define S_MBOXPCIEOFST    6
5944 #define M_MBOXPCIEOFST    0x3ffffffU
5945 #define V_MBOXPCIEOFST(x) ((x) << S_MBOXPCIEOFST)
5946 #define G_MBOXPCIEOFST(x) (((x) >> S_MBOXPCIEOFST) & M_MBOXPCIEOFST)
5947 
5948 #define S_MBOXBIR    4
5949 #define M_MBOXBIR    0x3U
5950 #define V_MBOXBIR(x) ((x) << S_MBOXBIR)
5951 #define G_MBOXBIR(x) (((x) >> S_MBOXBIR) & M_MBOXBIR)
5952 
5953 #define S_MBOXWIN    0
5954 #define M_MBOXWIN    0x3U
5955 #define V_MBOXWIN(x) ((x) << S_MBOXWIN)
5956 #define G_MBOXWIN(x) (((x) >> S_MBOXWIN) & M_MBOXWIN)
5957 
5958 #define A_PCIE_MAILBOX_OFFSET0 0x30a8
5959 
5960 #define S_MEMOFST0    3
5961 #define M_MEMOFST0    0x1fffffffU
5962 #define V_MEMOFST0(x) ((x) << S_MEMOFST0)
5963 #define G_MEMOFST0(x) (((x) >> S_MEMOFST0) & M_MEMOFST0)
5964 
5965 #define A_PCIE_MAILBOX_OFFSET 0x30ac
5966 #define A_PCIE_MAILBOX_OFFSET1 0x30ac
5967 
5968 #define S_MEMOFST1    0
5969 #define M_MEMOFST1    0xfU
5970 #define V_MEMOFST1(x) ((x) << S_MEMOFST1)
5971 #define G_MEMOFST1(x) (((x) >> S_MEMOFST1) & M_MEMOFST1)
5972 
5973 #define A_PCIE_MA_CTRL 0x30b0
5974 
5975 #define S_MA_TAGFREE    29
5976 #define V_MA_TAGFREE(x) ((x) << S_MA_TAGFREE)
5977 #define F_MA_TAGFREE    V_MA_TAGFREE(1U)
5978 
5979 #define S_MA_MAXRSPCNT    24
5980 #define M_MA_MAXRSPCNT    0x1fU
5981 #define V_MA_MAXRSPCNT(x) ((x) << S_MA_MAXRSPCNT)
5982 #define G_MA_MAXRSPCNT(x) (((x) >> S_MA_MAXRSPCNT) & M_MA_MAXRSPCNT)
5983 
5984 #define S_MA_MAXREQCNT    16
5985 #define M_MA_MAXREQCNT    0x1fU
5986 #define V_MA_MAXREQCNT(x) ((x) << S_MA_MAXREQCNT)
5987 #define G_MA_MAXREQCNT(x) (((x) >> S_MA_MAXREQCNT) & M_MA_MAXREQCNT)
5988 
5989 #define S_MA_LE    15
5990 #define V_MA_LE(x) ((x) << S_MA_LE)
5991 #define F_MA_LE    V_MA_LE(1U)
5992 
5993 #define S_MA_MAXPYLDSIZE    12
5994 #define M_MA_MAXPYLDSIZE    0x7U
5995 #define V_MA_MAXPYLDSIZE(x) ((x) << S_MA_MAXPYLDSIZE)
5996 #define G_MA_MAXPYLDSIZE(x) (((x) >> S_MA_MAXPYLDSIZE) & M_MA_MAXPYLDSIZE)
5997 
5998 #define S_MA_MAXRDREQSIZE    8
5999 #define M_MA_MAXRDREQSIZE    0x7U
6000 #define V_MA_MAXRDREQSIZE(x) ((x) << S_MA_MAXRDREQSIZE)
6001 #define G_MA_MAXRDREQSIZE(x) (((x) >> S_MA_MAXRDREQSIZE) & M_MA_MAXRDREQSIZE)
6002 
6003 #define S_MA_MAXTAG    0
6004 #define M_MA_MAXTAG    0x1fU
6005 #define V_MA_MAXTAG(x) ((x) << S_MA_MAXTAG)
6006 #define G_MA_MAXTAG(x) (((x) >> S_MA_MAXTAG) & M_MA_MAXTAG)
6007 
6008 #define S_T5_MA_MAXREQCNT    16
6009 #define M_T5_MA_MAXREQCNT    0x7fU
6010 #define V_T5_MA_MAXREQCNT(x) ((x) << S_T5_MA_MAXREQCNT)
6011 #define G_T5_MA_MAXREQCNT(x) (((x) >> S_T5_MA_MAXREQCNT) & M_T5_MA_MAXREQCNT)
6012 
6013 #define S_MA_MAXREQSIZE    8
6014 #define M_MA_MAXREQSIZE    0x7U
6015 #define V_MA_MAXREQSIZE(x) ((x) << S_MA_MAXREQSIZE)
6016 #define G_MA_MAXREQSIZE(x) (((x) >> S_MA_MAXREQSIZE) & M_MA_MAXREQSIZE)
6017 
6018 #define A_PCIE_MA_SYNC 0x30b4
6019 #define A_PCIE_FW 0x30b8
6020 #define A_PCIE_FW_PF 0x30bc
6021 #define A_PCIE_PIO_PAUSE 0x30dc
6022 
6023 #define S_PIOPAUSEDONE    31
6024 #define V_PIOPAUSEDONE(x) ((x) << S_PIOPAUSEDONE)
6025 #define F_PIOPAUSEDONE    V_PIOPAUSEDONE(1U)
6026 
6027 #define S_PIOPAUSETIME    4
6028 #define M_PIOPAUSETIME    0xffffffU
6029 #define V_PIOPAUSETIME(x) ((x) << S_PIOPAUSETIME)
6030 #define G_PIOPAUSETIME(x) (((x) >> S_PIOPAUSETIME) & M_PIOPAUSETIME)
6031 
6032 #define S_PIOPAUSE    0
6033 #define V_PIOPAUSE(x) ((x) << S_PIOPAUSE)
6034 #define F_PIOPAUSE    V_PIOPAUSE(1U)
6035 
6036 #define S_MSTPAUSEDONE    30
6037 #define V_MSTPAUSEDONE(x) ((x) << S_MSTPAUSEDONE)
6038 #define F_MSTPAUSEDONE    V_MSTPAUSEDONE(1U)
6039 
6040 #define S_MSTPAUSE    1
6041 #define V_MSTPAUSE(x) ((x) << S_MSTPAUSE)
6042 #define F_MSTPAUSE    V_MSTPAUSE(1U)
6043 
6044 #define A_PCIE_SYS_CFG_READY 0x30e0
6045 #define A_PCIE_MA_STAT 0x30e0
6046 #define A_PCIE_STATIC_CFG1 0x30e4
6047 
6048 #define S_LINKDOWN_RESET_EN    26
6049 #define V_LINKDOWN_RESET_EN(x) ((x) << S_LINKDOWN_RESET_EN)
6050 #define F_LINKDOWN_RESET_EN    V_LINKDOWN_RESET_EN(1U)
6051 
6052 #define S_IN_WR_DISCONTIG    25
6053 #define V_IN_WR_DISCONTIG(x) ((x) << S_IN_WR_DISCONTIG)
6054 #define F_IN_WR_DISCONTIG    V_IN_WR_DISCONTIG(1U)
6055 
6056 #define S_IN_RD_CPLSIZE    22
6057 #define M_IN_RD_CPLSIZE    0x7U
6058 #define V_IN_RD_CPLSIZE(x) ((x) << S_IN_RD_CPLSIZE)
6059 #define G_IN_RD_CPLSIZE(x) (((x) >> S_IN_RD_CPLSIZE) & M_IN_RD_CPLSIZE)
6060 
6061 #define S_IN_RD_BUFMODE    20
6062 #define M_IN_RD_BUFMODE    0x3U
6063 #define V_IN_RD_BUFMODE(x) ((x) << S_IN_RD_BUFMODE)
6064 #define G_IN_RD_BUFMODE(x) (((x) >> S_IN_RD_BUFMODE) & M_IN_RD_BUFMODE)
6065 
6066 #define S_GBIF_NPTRANS_TOT    18
6067 #define M_GBIF_NPTRANS_TOT    0x3U
6068 #define V_GBIF_NPTRANS_TOT(x) ((x) << S_GBIF_NPTRANS_TOT)
6069 #define G_GBIF_NPTRANS_TOT(x) (((x) >> S_GBIF_NPTRANS_TOT) & M_GBIF_NPTRANS_TOT)
6070 
6071 #define S_IN_PDAT_TOT    15
6072 #define M_IN_PDAT_TOT    0x7U
6073 #define V_IN_PDAT_TOT(x) ((x) << S_IN_PDAT_TOT)
6074 #define G_IN_PDAT_TOT(x) (((x) >> S_IN_PDAT_TOT) & M_IN_PDAT_TOT)
6075 
6076 #define S_PCIE_NPTRANS_TOT    12
6077 #define M_PCIE_NPTRANS_TOT    0x7U
6078 #define V_PCIE_NPTRANS_TOT(x) ((x) << S_PCIE_NPTRANS_TOT)
6079 #define G_PCIE_NPTRANS_TOT(x) (((x) >> S_PCIE_NPTRANS_TOT) & M_PCIE_NPTRANS_TOT)
6080 
6081 #define S_OUT_PDAT_TOT    9
6082 #define M_OUT_PDAT_TOT    0x7U
6083 #define V_OUT_PDAT_TOT(x) ((x) << S_OUT_PDAT_TOT)
6084 #define G_OUT_PDAT_TOT(x) (((x) >> S_OUT_PDAT_TOT) & M_OUT_PDAT_TOT)
6085 
6086 #define S_GBIF_MAX_WRSIZE    6
6087 #define M_GBIF_MAX_WRSIZE    0x7U
6088 #define V_GBIF_MAX_WRSIZE(x) ((x) << S_GBIF_MAX_WRSIZE)
6089 #define G_GBIF_MAX_WRSIZE(x) (((x) >> S_GBIF_MAX_WRSIZE) & M_GBIF_MAX_WRSIZE)
6090 
6091 #define S_GBIF_MAX_RDSIZE    3
6092 #define M_GBIF_MAX_RDSIZE    0x7U
6093 #define V_GBIF_MAX_RDSIZE(x) ((x) << S_GBIF_MAX_RDSIZE)
6094 #define G_GBIF_MAX_RDSIZE(x) (((x) >> S_GBIF_MAX_RDSIZE) & M_GBIF_MAX_RDSIZE)
6095 
6096 #define S_PCIE_MAX_RDSIZE    0
6097 #define M_PCIE_MAX_RDSIZE    0x7U
6098 #define V_PCIE_MAX_RDSIZE(x) ((x) << S_PCIE_MAX_RDSIZE)
6099 #define G_PCIE_MAX_RDSIZE(x) (((x) >> S_PCIE_MAX_RDSIZE) & M_PCIE_MAX_RDSIZE)
6100 
6101 #define S_AUXPOWER_DETECTED    27
6102 #define V_AUXPOWER_DETECTED(x) ((x) << S_AUXPOWER_DETECTED)
6103 #define F_AUXPOWER_DETECTED    V_AUXPOWER_DETECTED(1U)
6104 
6105 #define A_PCIE_STATIC_CFG2 0x30e8
6106 
6107 #define S_PL_CONTROL    16
6108 #define M_PL_CONTROL    0xffffU
6109 #define V_PL_CONTROL(x) ((x) << S_PL_CONTROL)
6110 #define G_PL_CONTROL(x) (((x) >> S_PL_CONTROL) & M_PL_CONTROL)
6111 
6112 #define S_STATIC_SPARE3    0
6113 #define M_STATIC_SPARE3    0x3fffU
6114 #define V_STATIC_SPARE3(x) ((x) << S_STATIC_SPARE3)
6115 #define G_STATIC_SPARE3(x) (((x) >> S_STATIC_SPARE3) & M_STATIC_SPARE3)
6116 
6117 #define S_T7_STATIC_SPARE3    0
6118 #define M_T7_STATIC_SPARE3    0x7fffU
6119 #define V_T7_STATIC_SPARE3(x) ((x) << S_T7_STATIC_SPARE3)
6120 #define G_T7_STATIC_SPARE3(x) (((x) >> S_T7_STATIC_SPARE3) & M_T7_STATIC_SPARE3)
6121 
6122 #define A_PCIE_DBG_INDIR_REQ 0x30ec
6123 
6124 #define S_DBGENABLE    31
6125 #define V_DBGENABLE(x) ((x) << S_DBGENABLE)
6126 #define F_DBGENABLE    V_DBGENABLE(1U)
6127 
6128 #define S_DBGAUTOINC    30
6129 #define V_DBGAUTOINC(x) ((x) << S_DBGAUTOINC)
6130 #define F_DBGAUTOINC    V_DBGAUTOINC(1U)
6131 
6132 #define S_POINTER    8
6133 #define M_POINTER    0xffffU
6134 #define V_POINTER(x) ((x) << S_POINTER)
6135 #define G_POINTER(x) (((x) >> S_POINTER) & M_POINTER)
6136 
6137 #define S_SELECT    0
6138 #define M_SELECT    0xfU
6139 #define V_SELECT(x) ((x) << S_SELECT)
6140 #define G_SELECT(x) (((x) >> S_SELECT) & M_SELECT)
6141 
6142 #define A_PCIE_DBG_INDIR_DATA_0 0x30f0
6143 #define A_PCIE_DBG_INDIR_DATA_1 0x30f4
6144 #define A_PCIE_DBG_INDIR_DATA_2 0x30f8
6145 #define A_PCIE_DBG_INDIR_DATA_3 0x30fc
6146 #define A_PCIE_FUNC_INT_CFG 0x3100
6147 
6148 #define S_PBAOFST    28
6149 #define M_PBAOFST    0xfU
6150 #define V_PBAOFST(x) ((x) << S_PBAOFST)
6151 #define G_PBAOFST(x) (((x) >> S_PBAOFST) & M_PBAOFST)
6152 
6153 #define S_TABOFST    24
6154 #define M_TABOFST    0xfU
6155 #define V_TABOFST(x) ((x) << S_TABOFST)
6156 #define G_TABOFST(x) (((x) >> S_TABOFST) & M_TABOFST)
6157 
6158 #define S_VECNUM    12
6159 #define M_VECNUM    0x3ffU
6160 #define V_VECNUM(x) ((x) << S_VECNUM)
6161 #define G_VECNUM(x) (((x) >> S_VECNUM) & M_VECNUM)
6162 
6163 #define S_VECBASE    0
6164 #define M_VECBASE    0x7ffU
6165 #define V_VECBASE(x) ((x) << S_VECBASE)
6166 #define G_VECBASE(x) (((x) >> S_VECBASE) & M_VECBASE)
6167 
6168 #define A_PCIE_FUNC_CTL_STAT 0x3104
6169 
6170 #define S_SENDFLRRSP    31
6171 #define V_SENDFLRRSP(x) ((x) << S_SENDFLRRSP)
6172 #define F_SENDFLRRSP    V_SENDFLRRSP(1U)
6173 
6174 #define S_IMMFLRRSP    24
6175 #define V_IMMFLRRSP(x) ((x) << S_IMMFLRRSP)
6176 #define F_IMMFLRRSP    V_IMMFLRRSP(1U)
6177 
6178 #define S_TXNDISABLE    20
6179 #define V_TXNDISABLE(x) ((x) << S_TXNDISABLE)
6180 #define F_TXNDISABLE    V_TXNDISABLE(1U)
6181 
6182 #define S_PNDTXNS    8
6183 #define M_PNDTXNS    0x3ffU
6184 #define V_PNDTXNS(x) ((x) << S_PNDTXNS)
6185 #define G_PNDTXNS(x) (((x) >> S_PNDTXNS) & M_PNDTXNS)
6186 
6187 #define S_VFVLD    3
6188 #define V_VFVLD(x) ((x) << S_VFVLD)
6189 #define F_VFVLD    V_VFVLD(1U)
6190 
6191 #define S_PFNUM    0
6192 #define M_PFNUM    0x7U
6193 #define V_PFNUM(x) ((x) << S_PFNUM)
6194 #define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM)
6195 
6196 #define A_PCIE_PF_INT_CFG 0x3140
6197 
6198 #define S_T7_VECNUM    12
6199 #define M_T7_VECNUM    0x7ffU
6200 #define V_T7_VECNUM(x) ((x) << S_T7_VECNUM)
6201 #define G_T7_VECNUM(x) (((x) >> S_T7_VECNUM) & M_T7_VECNUM)
6202 
6203 #define S_T7_VECBASE    0
6204 #define M_T7_VECBASE    0xfffU
6205 #define V_T7_VECBASE(x) ((x) << S_T7_VECBASE)
6206 #define G_T7_VECBASE(x) (((x) >> S_T7_VECBASE) & M_T7_VECBASE)
6207 
6208 #define A_PCIE_PF_INT_CFG2 0x3144
6209 #define A_PCIE_VF_INT_CFG 0x3180
6210 #define A_PCIE_VF_INT_CFG2 0x3184
6211 #define A_PCIE_PF_MSI_EN 0x35a8
6212 
6213 #define S_PFMSIEN_7_0    0
6214 #define M_PFMSIEN_7_0    0xffU
6215 #define V_PFMSIEN_7_0(x) ((x) << S_PFMSIEN_7_0)
6216 #define G_PFMSIEN_7_0(x) (((x) >> S_PFMSIEN_7_0) & M_PFMSIEN_7_0)
6217 
6218 #define A_PCIE_VF_MSI_EN_0 0x35ac
6219 #define A_PCIE_VF_MSI_EN_1 0x35b0
6220 #define A_PCIE_VF_MSI_EN_2 0x35b4
6221 #define A_PCIE_VF_MSI_EN_3 0x35b8
6222 #define A_PCIE_PF_MSIX_EN 0x35bc
6223 
6224 #define S_PFMSIXEN_7_0    0
6225 #define M_PFMSIXEN_7_0    0xffU
6226 #define V_PFMSIXEN_7_0(x) ((x) << S_PFMSIXEN_7_0)
6227 #define G_PFMSIXEN_7_0(x) (((x) >> S_PFMSIXEN_7_0) & M_PFMSIXEN_7_0)
6228 
6229 #define A_PCIE_VF_MSIX_EN_0 0x35c0
6230 #define A_PCIE_VF_MSIX_EN_1 0x35c4
6231 #define A_PCIE_VF_MSIX_EN_2 0x35c8
6232 #define A_PCIE_VF_MSIX_EN_3 0x35cc
6233 #define A_PCIE_FID_PASID 0x35e0
6234 #define A_PCIE_FID_VFID_CTL 0x35e4
6235 
6236 #define S_T7_WRITE    0
6237 #define V_T7_WRITE(x) ((x) << S_T7_WRITE)
6238 #define F_T7_WRITE    V_T7_WRITE(1U)
6239 
6240 #define A_T7_PCIE_FID_VFID_SEL 0x35e8
6241 
6242 #define S_T7_ADDR    2
6243 #define M_T7_ADDR    0x1fffU
6244 #define V_T7_ADDR(x) ((x) << S_T7_ADDR)
6245 #define G_T7_ADDR(x) (((x) >> S_T7_ADDR) & M_T7_ADDR)
6246 
6247 #define A_PCIE_FID_VFID_SEL 0x35ec
6248 
6249 #define S_FID_VFID_SEL_SELECT    0
6250 #define M_FID_VFID_SEL_SELECT    0x3U
6251 #define V_FID_VFID_SEL_SELECT(x) ((x) << S_FID_VFID_SEL_SELECT)
6252 #define G_FID_VFID_SEL_SELECT(x) (((x) >> S_FID_VFID_SEL_SELECT) & M_FID_VFID_SEL_SELECT)
6253 
6254 #define A_T7_PCIE_FID_VFID 0x35ec
6255 
6256 #define S_FID_VFID_NVMEGROUPEN    29
6257 #define V_FID_VFID_NVMEGROUPEN(x) ((x) << S_FID_VFID_NVMEGROUPEN)
6258 #define F_FID_VFID_NVMEGROUPEN    V_FID_VFID_NVMEGROUPEN(1U)
6259 
6260 #define S_FID_VFID_GROUPSEL    25
6261 #define M_FID_VFID_GROUPSEL    0xfU
6262 #define V_FID_VFID_GROUPSEL(x) ((x) << S_FID_VFID_GROUPSEL)
6263 #define G_FID_VFID_GROUPSEL(x) (((x) >> S_FID_VFID_GROUPSEL) & M_FID_VFID_GROUPSEL)
6264 
6265 #define A_PCIE_FID_VFID 0x3600
6266 
6267 #define S_FID_VFID_SELECT    30
6268 #define M_FID_VFID_SELECT    0x3U
6269 #define V_FID_VFID_SELECT(x) ((x) << S_FID_VFID_SELECT)
6270 #define G_FID_VFID_SELECT(x) (((x) >> S_FID_VFID_SELECT) & M_FID_VFID_SELECT)
6271 
6272 #define S_IDO    24
6273 #define V_IDO(x) ((x) << S_IDO)
6274 #define F_IDO    V_IDO(1U)
6275 
6276 #define S_FID_VFID_VFID    16
6277 #define M_FID_VFID_VFID    0xffU
6278 #define V_FID_VFID_VFID(x) ((x) << S_FID_VFID_VFID)
6279 #define G_FID_VFID_VFID(x) (((x) >> S_FID_VFID_VFID) & M_FID_VFID_VFID)
6280 
6281 #define S_FID_VFID_TC    11
6282 #define M_FID_VFID_TC    0x7U
6283 #define V_FID_VFID_TC(x) ((x) << S_FID_VFID_TC)
6284 #define G_FID_VFID_TC(x) (((x) >> S_FID_VFID_TC) & M_FID_VFID_TC)
6285 
6286 #define S_FID_VFID_VFVLD    10
6287 #define V_FID_VFID_VFVLD(x) ((x) << S_FID_VFID_VFVLD)
6288 #define F_FID_VFID_VFVLD    V_FID_VFID_VFVLD(1U)
6289 
6290 #define S_FID_VFID_PF    7
6291 #define M_FID_VFID_PF    0x7U
6292 #define V_FID_VFID_PF(x) ((x) << S_FID_VFID_PF)
6293 #define G_FID_VFID_PF(x) (((x) >> S_FID_VFID_PF) & M_FID_VFID_PF)
6294 
6295 #define S_FID_VFID_RVF    0
6296 #define M_FID_VFID_RVF    0x7fU
6297 #define V_FID_VFID_RVF(x) ((x) << S_FID_VFID_RVF)
6298 #define G_FID_VFID_RVF(x) (((x) >> S_FID_VFID_RVF) & M_FID_VFID_RVF)
6299 
6300 #define S_T6_FID_VFID_VFID    15
6301 #define M_T6_FID_VFID_VFID    0x1ffU
6302 #define V_T6_FID_VFID_VFID(x) ((x) << S_T6_FID_VFID_VFID)
6303 #define G_T6_FID_VFID_VFID(x) (((x) >> S_T6_FID_VFID_VFID) & M_T6_FID_VFID_VFID)
6304 
6305 #define S_T6_FID_VFID_TC    12
6306 #define M_T6_FID_VFID_TC    0x7U
6307 #define V_T6_FID_VFID_TC(x) ((x) << S_T6_FID_VFID_TC)
6308 #define G_T6_FID_VFID_TC(x) (((x) >> S_T6_FID_VFID_TC) & M_T6_FID_VFID_TC)
6309 
6310 #define S_T6_FID_VFID_VFVLD    11
6311 #define V_T6_FID_VFID_VFVLD(x) ((x) << S_T6_FID_VFID_VFVLD)
6312 #define F_T6_FID_VFID_VFVLD    V_T6_FID_VFID_VFVLD(1U)
6313 
6314 #define S_T6_FID_VFID_PF    8
6315 #define M_T6_FID_VFID_PF    0x7U
6316 #define V_T6_FID_VFID_PF(x) ((x) << S_T6_FID_VFID_PF)
6317 #define G_T6_FID_VFID_PF(x) (((x) >> S_T6_FID_VFID_PF) & M_T6_FID_VFID_PF)
6318 
6319 #define S_T6_FID_VFID_RVF    0
6320 #define M_T6_FID_VFID_RVF    0xffU
6321 #define V_T6_FID_VFID_RVF(x) ((x) << S_T6_FID_VFID_RVF)
6322 #define G_T6_FID_VFID_RVF(x) (((x) >> S_T6_FID_VFID_RVF) & M_T6_FID_VFID_RVF)
6323 
6324 #define A_PCIE_JBOF_NVME_HIGH_DW_START_ADDR 0x3600
6325 #define A_PCIE_JBOF_NVME_LOW_DW_START_ADDR 0x3604
6326 #define A_PCIE_JBOF_NVME_LENGTH 0x3608
6327 
6328 #define S_NVMEDISABLE    31
6329 #define V_NVMEDISABLE(x) ((x) << S_NVMEDISABLE)
6330 #define F_NVMEDISABLE    V_NVMEDISABLE(1U)
6331 
6332 #define S_NVMELENGTH    0
6333 #define M_NVMELENGTH    0x3fffffffU
6334 #define V_NVMELENGTH(x) ((x) << S_NVMELENGTH)
6335 #define G_NVMELENGTH(x) (((x) >> S_NVMELENGTH) & M_NVMELENGTH)
6336 
6337 #define A_PCIE_JBOF_NVME_GROUP 0x360c
6338 
6339 #define S_NVMEGROUPSEL    0
6340 #define M_NVMEGROUPSEL    0xfU
6341 #define V_NVMEGROUPSEL(x) ((x) << S_NVMEGROUPSEL)
6342 #define G_NVMEGROUPSEL(x) (((x) >> S_NVMEGROUPSEL) & M_NVMEGROUPSEL)
6343 
6344 #define A_T7_PCIE_MEM_ACCESS_BASE_WIN 0x3700
6345 #define A_PCIE_MEM_ACCESS_BASE_WIN1 0x3704
6346 
6347 #define S_PCIEOFST1    0
6348 #define M_PCIEOFST1    0xffU
6349 #define V_PCIEOFST1(x) ((x) << S_PCIEOFST1)
6350 #define G_PCIEOFST1(x) (((x) >> S_PCIEOFST1) & M_PCIEOFST1)
6351 
6352 #define A_PCIE_MEM_ACCESS_OFFSET0 0x3708
6353 #define A_PCIE_MEM_ACCESS_OFFSET1 0x370c
6354 #define A_PCIE_PTM_EP_EXT_STROBE 0x3804
6355 
6356 #define S_PTM_AUTO_UPDATE    1
6357 #define V_PTM_AUTO_UPDATE(x) ((x) << S_PTM_AUTO_UPDATE)
6358 #define F_PTM_AUTO_UPDATE    V_PTM_AUTO_UPDATE(1U)
6359 
6360 #define S_PTM_EXT_STROBE    0
6361 #define V_PTM_EXT_STROBE(x) ((x) << S_PTM_EXT_STROBE)
6362 #define F_PTM_EXT_STROBE    V_PTM_EXT_STROBE(1U)
6363 
6364 #define A_PCIE_PTM_EP_EXT_TIME0 0x3808
6365 #define A_PCIE_PTM_EP_EXT_TIME1 0x380c
6366 #define A_PCIE_PTM_MAN_UPD_PULSE 0x3810
6367 
6368 #define S_PTM_MAN_UPD_PULSE    0
6369 #define V_PTM_MAN_UPD_PULSE(x) ((x) << S_PTM_MAN_UPD_PULSE)
6370 #define F_PTM_MAN_UPD_PULSE    V_PTM_MAN_UPD_PULSE(1U)
6371 
6372 #define A_PCIE_SWAP_DATA_B2L_X16 0x3814
6373 #define A_PCIE_PCIE_RC_RST 0x3818
6374 
6375 #define S_PERST    0
6376 #define V_PERST(x) ((x) << S_PERST)
6377 #define F_PERST    V_PERST(1U)
6378 
6379 #define A_PCIE_PCIE_LN_CLKSEL 0x3880
6380 
6381 #define S_DS8_SEL    30
6382 #define M_DS8_SEL    0x3U
6383 #define V_DS8_SEL(x) ((x) << S_DS8_SEL)
6384 #define G_DS8_SEL(x) (((x) >> S_DS8_SEL) & M_DS8_SEL)
6385 
6386 #define S_DS7_SEL    28
6387 #define M_DS7_SEL    0x3U
6388 #define V_DS7_SEL(x) ((x) << S_DS7_SEL)
6389 #define G_DS7_SEL(x) (((x) >> S_DS7_SEL) & M_DS7_SEL)
6390 
6391 #define S_DS6_SEL    26
6392 #define M_DS6_SEL    0x3U
6393 #define V_DS6_SEL(x) ((x) << S_DS6_SEL)
6394 #define G_DS6_SEL(x) (((x) >> S_DS6_SEL) & M_DS6_SEL)
6395 
6396 #define S_DS5_SEL    24
6397 #define M_DS5_SEL    0x3U
6398 #define V_DS5_SEL(x) ((x) << S_DS5_SEL)
6399 #define G_DS5_SEL(x) (((x) >> S_DS5_SEL) & M_DS5_SEL)
6400 
6401 #define S_DS4_SEL    22
6402 #define M_DS4_SEL    0x3U
6403 #define V_DS4_SEL(x) ((x) << S_DS4_SEL)
6404 #define G_DS4_SEL(x) (((x) >> S_DS4_SEL) & M_DS4_SEL)
6405 
6406 #define S_DS3_SEL    20
6407 #define M_DS3_SEL    0x3U
6408 #define V_DS3_SEL(x) ((x) << S_DS3_SEL)
6409 #define G_DS3_SEL(x) (((x) >> S_DS3_SEL) & M_DS3_SEL)
6410 
6411 #define S_DS2_SEL    18
6412 #define M_DS2_SEL    0x3U
6413 #define V_DS2_SEL(x) ((x) << S_DS2_SEL)
6414 #define G_DS2_SEL(x) (((x) >> S_DS2_SEL) & M_DS2_SEL)
6415 
6416 #define S_DS1_SEL    16
6417 #define M_DS1_SEL    0x3U
6418 #define V_DS1_SEL(x) ((x) << S_DS1_SEL)
6419 #define G_DS1_SEL(x) (((x) >> S_DS1_SEL) & M_DS1_SEL)
6420 
6421 #define S_LN14_SEL    14
6422 #define M_LN14_SEL    0x3U
6423 #define V_LN14_SEL(x) ((x) << S_LN14_SEL)
6424 #define G_LN14_SEL(x) (((x) >> S_LN14_SEL) & M_LN14_SEL)
6425 
6426 #define S_LN12_SEL    12
6427 #define M_LN12_SEL    0x3U
6428 #define V_LN12_SEL(x) ((x) << S_LN12_SEL)
6429 #define G_LN12_SEL(x) (((x) >> S_LN12_SEL) & M_LN12_SEL)
6430 
6431 #define S_LN10_SEL    10
6432 #define M_LN10_SEL    0x3U
6433 #define V_LN10_SEL(x) ((x) << S_LN10_SEL)
6434 #define G_LN10_SEL(x) (((x) >> S_LN10_SEL) & M_LN10_SEL)
6435 
6436 #define S_LN8_SEL    8
6437 #define M_LN8_SEL    0x3U
6438 #define V_LN8_SEL(x) ((x) << S_LN8_SEL)
6439 #define G_LN8_SEL(x) (((x) >> S_LN8_SEL) & M_LN8_SEL)
6440 
6441 #define S_LN6_SEL    6
6442 #define M_LN6_SEL    0x3U
6443 #define V_LN6_SEL(x) ((x) << S_LN6_SEL)
6444 #define G_LN6_SEL(x) (((x) >> S_LN6_SEL) & M_LN6_SEL)
6445 
6446 #define S_LN4_SEL    4
6447 #define M_LN4_SEL    0x3U
6448 #define V_LN4_SEL(x) ((x) << S_LN4_SEL)
6449 #define G_LN4_SEL(x) (((x) >> S_LN4_SEL) & M_LN4_SEL)
6450 
6451 #define S_LN2_SEL    2
6452 #define M_LN2_SEL    0x3U
6453 #define V_LN2_SEL(x) ((x) << S_LN2_SEL)
6454 #define G_LN2_SEL(x) (((x) >> S_LN2_SEL) & M_LN2_SEL)
6455 
6456 #define S_LN0_SEL    0
6457 #define M_LN0_SEL    0x3U
6458 #define V_LN0_SEL(x) ((x) << S_LN0_SEL)
6459 #define G_LN0_SEL(x) (((x) >> S_LN0_SEL) & M_LN0_SEL)
6460 
6461 #define A_PCIE_PCIE_MSIX_EN 0x3884
6462 
6463 #define S_MSIX_ENABLE    0
6464 #define M_MSIX_ENABLE    0xffU
6465 #define V_MSIX_ENABLE(x) ((x) << S_MSIX_ENABLE)
6466 #define G_MSIX_ENABLE(x) (((x) >> S_MSIX_ENABLE) & M_MSIX_ENABLE)
6467 
6468 #define A_PCIE_LFSR_WRCTRL 0x3888
6469 
6470 #define S_WR_LFSR_CMP_DATA    16
6471 #define M_WR_LFSR_CMP_DATA    0xffffU
6472 #define V_WR_LFSR_CMP_DATA(x) ((x) << S_WR_LFSR_CMP_DATA)
6473 #define G_WR_LFSR_CMP_DATA(x) (((x) >> S_WR_LFSR_CMP_DATA) & M_WR_LFSR_CMP_DATA)
6474 
6475 #define S_WR_LFSR_RSVD    2
6476 #define M_WR_LFSR_RSVD    0x3fffU
6477 #define V_WR_LFSR_RSVD(x) ((x) << S_WR_LFSR_RSVD)
6478 #define G_WR_LFSR_RSVD(x) (((x) >> S_WR_LFSR_RSVD) & M_WR_LFSR_RSVD)
6479 
6480 #define S_WR_LFSR_EN    1
6481 #define V_WR_LFSR_EN(x) ((x) << S_WR_LFSR_EN)
6482 #define F_WR_LFSR_EN    V_WR_LFSR_EN(1U)
6483 
6484 #define S_WR_LFSR_START    0
6485 #define V_WR_LFSR_START(x) ((x) << S_WR_LFSR_START)
6486 #define F_WR_LFSR_START    V_WR_LFSR_START(1U)
6487 
6488 #define A_PCIE_LFSR_RDCTRL 0x388c
6489 
6490 #define S_CMD_LFSR_CMP_DATA    24
6491 #define M_CMD_LFSR_CMP_DATA    0xffU
6492 #define V_CMD_LFSR_CMP_DATA(x) ((x) << S_CMD_LFSR_CMP_DATA)
6493 #define G_CMD_LFSR_CMP_DATA(x) (((x) >> S_CMD_LFSR_CMP_DATA) & M_CMD_LFSR_CMP_DATA)
6494 
6495 #define S_RD_LFSR_CMD_DATA    16
6496 #define M_RD_LFSR_CMD_DATA    0xffU
6497 #define V_RD_LFSR_CMD_DATA(x) ((x) << S_RD_LFSR_CMD_DATA)
6498 #define G_RD_LFSR_CMD_DATA(x) (((x) >> S_RD_LFSR_CMD_DATA) & M_RD_LFSR_CMD_DATA)
6499 
6500 #define S_RD_LFSR_RSVD    10
6501 #define M_RD_LFSR_RSVD    0x3fU
6502 #define V_RD_LFSR_RSVD(x) ((x) << S_RD_LFSR_RSVD)
6503 #define G_RD_LFSR_RSVD(x) (((x) >> S_RD_LFSR_RSVD) & M_RD_LFSR_RSVD)
6504 
6505 #define S_RD3_LFSR_EN    9
6506 #define V_RD3_LFSR_EN(x) ((x) << S_RD3_LFSR_EN)
6507 #define F_RD3_LFSR_EN    V_RD3_LFSR_EN(1U)
6508 
6509 #define S_RD3_LFSR_START    8
6510 #define V_RD3_LFSR_START(x) ((x) << S_RD3_LFSR_START)
6511 #define F_RD3_LFSR_START    V_RD3_LFSR_START(1U)
6512 
6513 #define S_RD2_LFSR_EN    7
6514 #define V_RD2_LFSR_EN(x) ((x) << S_RD2_LFSR_EN)
6515 #define F_RD2_LFSR_EN    V_RD2_LFSR_EN(1U)
6516 
6517 #define S_RD2_LFSR_START    6
6518 #define V_RD2_LFSR_START(x) ((x) << S_RD2_LFSR_START)
6519 #define F_RD2_LFSR_START    V_RD2_LFSR_START(1U)
6520 
6521 #define S_RD1_LFSR_EN    5
6522 #define V_RD1_LFSR_EN(x) ((x) << S_RD1_LFSR_EN)
6523 #define F_RD1_LFSR_EN    V_RD1_LFSR_EN(1U)
6524 
6525 #define S_RD1_LFSR_START    4
6526 #define V_RD1_LFSR_START(x) ((x) << S_RD1_LFSR_START)
6527 #define F_RD1_LFSR_START    V_RD1_LFSR_START(1U)
6528 
6529 #define S_RD0_LFSR_EN    3
6530 #define V_RD0_LFSR_EN(x) ((x) << S_RD0_LFSR_EN)
6531 #define F_RD0_LFSR_EN    V_RD0_LFSR_EN(1U)
6532 
6533 #define S_RD0_LFSR_START    2
6534 #define V_RD0_LFSR_START(x) ((x) << S_RD0_LFSR_START)
6535 #define F_RD0_LFSR_START    V_RD0_LFSR_START(1U)
6536 
6537 #define S_CMD_LFSR_EN    1
6538 #define V_CMD_LFSR_EN(x) ((x) << S_CMD_LFSR_EN)
6539 #define F_CMD_LFSR_EN    V_CMD_LFSR_EN(1U)
6540 
6541 #define S_CMD_LFSR_START    0
6542 #define V_CMD_LFSR_START(x) ((x) << S_CMD_LFSR_START)
6543 #define F_CMD_LFSR_START    V_CMD_LFSR_START(1U)
6544 
6545 #define A_PCIE_FID 0x3900
6546 
6547 #define S_PAD    11
6548 #define V_PAD(x) ((x) << S_PAD)
6549 #define F_PAD    V_PAD(1U)
6550 
6551 #define S_TC    8
6552 #define M_TC    0x7U
6553 #define V_TC(x) ((x) << S_TC)
6554 #define G_TC(x) (((x) >> S_TC) & M_TC)
6555 
6556 #define S_FUNC    0
6557 #define M_FUNC    0xffU
6558 #define V_FUNC(x) ((x) << S_FUNC)
6559 #define G_FUNC(x) (((x) >> S_FUNC) & M_FUNC)
6560 
6561 #define A_PCIE_EMU_ADDR 0x3900
6562 
6563 #define S_EMU_ADDR    0
6564 #define M_EMU_ADDR    0x1ffU
6565 #define V_EMU_ADDR(x) ((x) << S_EMU_ADDR)
6566 #define G_EMU_ADDR(x) (((x) >> S_EMU_ADDR) & M_EMU_ADDR)
6567 
6568 #define A_PCIE_EMU_CFG 0x3904
6569 
6570 #define S_EMUENABLE    16
6571 #define V_EMUENABLE(x) ((x) << S_EMUENABLE)
6572 #define F_EMUENABLE    V_EMUENABLE(1U)
6573 
6574 #define S_EMUTYPE    14
6575 #define M_EMUTYPE    0x3U
6576 #define V_EMUTYPE(x) ((x) << S_EMUTYPE)
6577 #define G_EMUTYPE(x) (((x) >> S_EMUTYPE) & M_EMUTYPE)
6578 
6579 #define S_BAR0TARGET    12
6580 #define M_BAR0TARGET    0x3U
6581 #define V_BAR0TARGET(x) ((x) << S_BAR0TARGET)
6582 #define G_BAR0TARGET(x) (((x) >> S_BAR0TARGET) & M_BAR0TARGET)
6583 
6584 #define S_BAR2TARGET    10
6585 #define M_BAR2TARGET    0x3U
6586 #define V_BAR2TARGET(x) ((x) << S_BAR2TARGET)
6587 #define G_BAR2TARGET(x) (((x) >> S_BAR2TARGET) & M_BAR2TARGET)
6588 
6589 #define S_BAR4TARGET    8
6590 #define M_BAR4TARGET    0x3U
6591 #define V_BAR4TARGET(x) ((x) << S_BAR4TARGET)
6592 #define G_BAR4TARGET(x) (((x) >> S_BAR4TARGET) & M_BAR4TARGET)
6593 
6594 #define S_RELEATIVEEMUID    0
6595 #define M_RELEATIVEEMUID    0xffU
6596 #define V_RELEATIVEEMUID(x) ((x) << S_RELEATIVEEMUID)
6597 #define G_RELEATIVEEMUID(x) (((x) >> S_RELEATIVEEMUID) & M_RELEATIVEEMUID)
6598 
6599 #define A_PCIE_EMUADRRMAP_MEM_OFFSET0_BAR0 0x3910
6600 
6601 #define S_T7_MEMOFST0    0
6602 #define M_T7_MEMOFST0    0xfffffffU
6603 #define V_T7_MEMOFST0(x) ((x) << S_T7_MEMOFST0)
6604 #define G_T7_MEMOFST0(x) (((x) >> S_T7_MEMOFST0) & M_T7_MEMOFST0)
6605 
6606 #define A_PCIE_EMUADRRMAP_MEM_CFG0_BAR0 0x3914
6607 
6608 #define S_SIZE0    0
6609 #define M_SIZE0    0x1fU
6610 #define V_SIZE0(x) ((x) << S_SIZE0)
6611 #define G_SIZE0(x) (((x) >> S_SIZE0) & M_SIZE0)
6612 
6613 #define A_PCIE_EMUADRRMAP_MEM_OFFSET1_BAR0 0x3918
6614 
6615 #define S_T7_MEMOFST1    0
6616 #define M_T7_MEMOFST1    0xfffffffU
6617 #define V_T7_MEMOFST1(x) ((x) << S_T7_MEMOFST1)
6618 #define G_T7_MEMOFST1(x) (((x) >> S_T7_MEMOFST1) & M_T7_MEMOFST1)
6619 
6620 #define A_PCIE_EMUADRRMAP_MEM_CFG1_BAR0 0x391c
6621 
6622 #define S_SIZE1    0
6623 #define M_SIZE1    0x1fU
6624 #define V_SIZE1(x) ((x) << S_SIZE1)
6625 #define G_SIZE1(x) (((x) >> S_SIZE1) & M_SIZE1)
6626 
6627 #define A_PCIE_EMUADRRMAP_MEM_OFFSET2_BAR0 0x3920
6628 
6629 #define S_MEMOFST2    0
6630 #define M_MEMOFST2    0xfffffffU
6631 #define V_MEMOFST2(x) ((x) << S_MEMOFST2)
6632 #define G_MEMOFST2(x) (((x) >> S_MEMOFST2) & M_MEMOFST2)
6633 
6634 #define A_PCIE_EMUADRRMAP_MEM_CFG2_BAR0 0x3924
6635 
6636 #define S_SIZE2    0
6637 #define M_SIZE2    0x1fU
6638 #define V_SIZE2(x) ((x) << S_SIZE2)
6639 #define G_SIZE2(x) (((x) >> S_SIZE2) & M_SIZE2)
6640 
6641 #define A_PCIE_EMUADRRMAP_MEM_OFFSET3_BAR0 0x3928
6642 
6643 #define S_MEMOFST3    0
6644 #define M_MEMOFST3    0xfffffffU
6645 #define V_MEMOFST3(x) ((x) << S_MEMOFST3)
6646 #define G_MEMOFST3(x) (((x) >> S_MEMOFST3) & M_MEMOFST3)
6647 
6648 #define A_PCIE_EMUADRRMAP_MEM_CFG3_BAR0 0x392c
6649 
6650 #define S_SIZE3    0
6651 #define M_SIZE3    0x1fU
6652 #define V_SIZE3(x) ((x) << S_SIZE3)
6653 #define G_SIZE3(x) (((x) >> S_SIZE3) & M_SIZE3)
6654 
6655 #define A_PCIE_TCAM_DATA 0x3970
6656 #define A_PCIE_TCAM_CTL 0x3974
6657 
6658 #define S_TCAMADDR    8
6659 #define M_TCAMADDR    0x3ffU
6660 #define V_TCAMADDR(x) ((x) << S_TCAMADDR)
6661 #define G_TCAMADDR(x) (((x) >> S_TCAMADDR) & M_TCAMADDR)
6662 
6663 #define S_CAMEN    0
6664 #define V_CAMEN(x) ((x) << S_CAMEN)
6665 #define F_CAMEN    V_CAMEN(1U)
6666 
6667 #define A_PCIE_TCAM_DBG 0x3978
6668 
6669 #define S_CBPASS    24
6670 #define V_CBPASS(x) ((x) << S_CBPASS)
6671 #define F_CBPASS    V_CBPASS(1U)
6672 
6673 #define S_CBBUSY    20
6674 #define V_CBBUSY(x) ((x) << S_CBBUSY)
6675 #define F_CBBUSY    V_CBBUSY(1U)
6676 
6677 #define S_CBSTART    17
6678 #define V_CBSTART(x) ((x) << S_CBSTART)
6679 #define F_CBSTART    V_CBSTART(1U)
6680 
6681 #define S_RSTCB    16
6682 #define V_RSTCB(x) ((x) << S_RSTCB)
6683 #define F_RSTCB    V_RSTCB(1U)
6684 
6685 #define S_TCAM_DBG_DATA    0
6686 #define M_TCAM_DBG_DATA    0xffffU
6687 #define V_TCAM_DBG_DATA(x) ((x) << S_TCAM_DBG_DATA)
6688 #define G_TCAM_DBG_DATA(x) (((x) >> S_TCAM_DBG_DATA) & M_TCAM_DBG_DATA)
6689 
6690 #define A_PCIE_TEST_CTRL0 0x3980
6691 #define A_PCIE_TEST_CTRL1 0x3984
6692 #define A_PCIE_TEST_CTRL2 0x3988
6693 #define A_PCIE_TEST_CTRL3 0x398c
6694 #define A_PCIE_TEST_STS0 0x3990
6695 #define A_PCIE_TEST_STS1 0x3994
6696 #define A_PCIE_TEST_STS2 0x3998
6697 #define A_PCIE_TEST_STS3 0x399c
6698 #define A_PCIE_X8_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER 0x4700
6699 #define A_PCIE_X8_CORE_VENDOR_SPECIFIC_DLLP 0x4704
6700 #define A_PCIE_X8_CORE_PORT_FORCE_LINK 0x4708
6701 #define A_PCIE_X8_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL 0x470c
6702 #define A_PCIE_X8_CORE_PORT_LINK_CONTROL 0x4710
6703 #define A_PCIE_X8_CORE_LANE_SKEW 0x4714
6704 #define A_PCIE_X8_CORE_SYMBOL_NUMBER 0x4718
6705 #define A_PCIE_X8_CORE_SYMBOL_TIMER_FILTER_MASK1 0x471c
6706 #define A_PCIE_X8_CORE_FILTER_MASK2 0x4720
6707 #define A_PCIE_X8_CORE_DEBUG_0 0x4728
6708 #define A_PCIE_X8_CORE_DEBUG_1 0x472c
6709 #define A_PCIE_X8_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS 0x4730
6710 #define A_PCIE_X8_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS 0x4734
6711 #define A_PCIE_X8_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS 0x4738
6712 #define A_PCIE_X8_CORE_QUEUE_STATUS 0x473c
6713 #define A_PCIE_X8_CORE_VC_TRANSMIT_ARBITRATION_1 0x4740
6714 #define A_PCIE_X8_CORE_VC_TRANSMIT_ARBITRATION_2 0x4744
6715 #define A_PCIE_X8_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL 0x4748
6716 #define A_PCIE_X8_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x474c
6717 #define A_PCIE_X8_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL 0x4750
6718 #define A_PCIE_X8_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL 0x4754
6719 #define A_PCIE_X8_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x4758
6720 #define A_PCIE_X8_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL 0x475c
6721 #define A_PCIE_X8_CORE_LINK_WIDTH_SPEED_CHANGE 0x480c
6722 #define A_PCIE_X8_CORE_PHY_STATUS 0x4810
6723 #define A_PCIE_X8_CORE_PHY_CONTROL 0x4814
6724 #define A_PCIE_X8_CORE_GEN3_CONTROL 0x4890
6725 #define A_PCIE_X8_CORE_GEN3_EQ_FS_LF 0x4894
6726 #define A_PCIE_X8_CORE_GEN3_EQ_PRESET_COEFF 0x4898
6727 #define A_PCIE_X8_CORE_GEN3_EQ_PRESET_INDEX 0x489c
6728 #define A_PCIE_X8_CORE_GEN3_EQ_STATUS 0x48a4
6729 #define A_PCIE_X8_CORE_GEN3_EQ_CONTROL 0x48a8
6730 #define A_PCIE_X8_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK 0x48ac
6731 #define A_PCIE_X8_CORE_PIPE_CONTROL 0x48b8
6732 #define A_PCIE_X8_CORE_DBI_RO_WE 0x48bc
6733 #define A_PCIE_X8_CFG_SPACE_REQ 0x48c0
6734 #define A_PCIE_X8_CFG_SPACE_DATA 0x48c4
6735 #define A_PCIE_X8_CFG_MPS_MRS 0x4900
6736 
6737 #define S_MRS    3
6738 #define M_MRS    0x7U
6739 #define V_MRS(x) ((x) << S_MRS)
6740 #define G_MRS(x) (((x) >> S_MRS) & M_MRS)
6741 
6742 #define S_T7_MPS    0
6743 #define M_T7_MPS    0x7U
6744 #define V_T7_MPS(x) ((x) << S_T7_MPS)
6745 #define G_T7_MPS(x) (((x) >> S_T7_MPS) & M_T7_MPS)
6746 
6747 #define A_PCIE_X8_CFG_ATTRIBUTES 0x4904
6748 
6749 #define S_T7_DCAEN    2
6750 #define V_T7_DCAEN(x) ((x) << S_T7_DCAEN)
6751 #define F_T7_DCAEN    V_T7_DCAEN(1U)
6752 
6753 #define S_DCASTFITTRAONLEN    1
6754 #define V_DCASTFITTRAONLEN(x) ((x) << S_DCASTFITTRAONLEN)
6755 #define F_DCASTFITTRAONLEN    V_DCASTFITTRAONLEN(1U)
6756 
6757 #define S_REQCTLDYNSTCLKEN    0
6758 #define V_REQCTLDYNSTCLKEN(x) ((x) << S_REQCTLDYNSTCLKEN)
6759 #define F_REQCTLDYNSTCLKEN    V_REQCTLDYNSTCLKEN(1U)
6760 
6761 #define A_PCIE_X8_CFG_LTSSM 0x4908
6762 
6763 #define S_APP_LTSSM_ENABLE    0
6764 #define V_APP_LTSSM_ENABLE(x) ((x) << S_APP_LTSSM_ENABLE)
6765 #define F_APP_LTSSM_ENABLE    V_APP_LTSSM_ENABLE(1U)
6766 
6767 #define A_PCIE_ARM_REQUESTER_ID_X8 0x490c
6768 
6769 #define S_A1_RSVD1    24
6770 #define M_A1_RSVD1    0xffU
6771 #define V_A1_RSVD1(x) ((x) << S_A1_RSVD1)
6772 #define G_A1_RSVD1(x) (((x) >> S_A1_RSVD1) & M_A1_RSVD1)
6773 
6774 #define S_A1_PRIMBUSNUMBER    16
6775 #define M_A1_PRIMBUSNUMBER    0xffU
6776 #define V_A1_PRIMBUSNUMBER(x) ((x) << S_A1_PRIMBUSNUMBER)
6777 #define G_A1_PRIMBUSNUMBER(x) (((x) >> S_A1_PRIMBUSNUMBER) & M_A1_PRIMBUSNUMBER)
6778 
6779 #define S_A1_REQUESTERID    0
6780 #define M_A1_REQUESTERID    0xffffU
6781 #define V_A1_REQUESTERID(x) ((x) << S_A1_REQUESTERID)
6782 #define G_A1_REQUESTERID(x) (((x) >> S_A1_REQUESTERID) & M_A1_REQUESTERID)
6783 
6784 #define A_PCIE_SWAP_DATA_B2L_X8 0x4910
6785 
6786 #define S_CFGRD_SWAP_EN    1
6787 #define V_CFGRD_SWAP_EN(x) ((x) << S_CFGRD_SWAP_EN)
6788 #define F_CFGRD_SWAP_EN    V_CFGRD_SWAP_EN(1U)
6789 
6790 #define S_CFGWR_SWAP_EN    0
6791 #define V_CFGWR_SWAP_EN(x) ((x) << S_CFGWR_SWAP_EN)
6792 #define F_CFGWR_SWAP_EN    V_CFGWR_SWAP_EN(1U)
6793 
6794 #define A_PCIE_PDEBUG_DATA0_X8 0x4914
6795 #define A_PCIE_PDEBUG_DATA1_X8 0x4918
6796 #define A_PCIE_PDEBUG_DATA2_X8 0x491c
6797 #define A_PCIE_PDEBUG_CTRL_X8 0x4920
6798 #define A_PCIE_PDEBUG_DATA_X8 0x4924
6799 #define A_PCIE_SPARE_REGISTER_SPACES_X8 0x4ffc
6800 #define A_PCIE_PIPE_LANE0_REG0 0x5500
6801 #define A_PCIE_PIPE_LANE0_REG1 0x5504
6802 #define A_PCIE_PIPE_LANE0_REG2 0x5508
6803 #define A_PCIE_PIPE_LANE0_REG3 0x550c
6804 #define A_PCIE_PIPE_LANE1_REG0 0x5510
6805 #define A_PCIE_PIPE_LANE1_REG1 0x5514
6806 #define A_PCIE_PIPE_LANE1_REG2 0x5518
6807 #define A_PCIE_PIPE_LANE1_REG3 0x551c
6808 #define A_PCIE_PIPE_LANE2_REG0 0x5520
6809 #define A_PCIE_PIPE_LANE2_REG1 0x5524
6810 #define A_PCIE_PIPE_LANE2_REG2 0x5528
6811 #define A_PCIE_PIPE_LANE2_REG3 0x552c
6812 #define A_PCIE_PIPE_LANE3_REG0 0x5530
6813 #define A_PCIE_PIPE_LANE3_REG1 0x5534
6814 #define A_PCIE_PIPE_LANE3_REG2 0x5538
6815 #define A_PCIE_PIPE_LANE3_REG3 0x553c
6816 #define A_PCIE_PIPE_LANE4_REG0 0x5540
6817 #define A_PCIE_PIPE_LANE4_REG1 0x5544
6818 #define A_PCIE_PIPE_LANE4_REG2 0x5548
6819 #define A_PCIE_PIPE_LANE4_REG3 0x554c
6820 #define A_PCIE_PIPE_LANE5_REG0 0x5550
6821 #define A_PCIE_PIPE_LANE5_REG1 0x5554
6822 #define A_PCIE_PIPE_LANE5_REG2 0x5558
6823 #define A_PCIE_PIPE_LANE5_REG3 0x555c
6824 #define A_PCIE_PIPE_LANE6_REG0 0x5560
6825 #define A_PCIE_PIPE_LANE6_REG1 0x5564
6826 #define A_PCIE_PIPE_LANE6_REG2 0x5568
6827 #define A_PCIE_PIPE_LANE6_REG3 0x556c
6828 #define A_PCIE_PIPE_LANE7_REG0 0x5570
6829 #define A_PCIE_PIPE_LANE7_REG1 0x5574
6830 #define A_PCIE_PIPE_LANE7_REG2 0x5578
6831 #define A_PCIE_PIPE_LANE7_REG3 0x557c
6832 #define A_PCIE_PIPE_LANE8_REG0 0x5580
6833 #define A_PCIE_PIPE_LANE8_REG1 0x5584
6834 #define A_PCIE_PIPE_LANE8_REG2 0x5588
6835 #define A_PCIE_PIPE_LANE8_REG3 0x558c
6836 #define A_PCIE_PIPE_LANE9_REG0 0x5590
6837 #define A_PCIE_PIPE_LANE9_REG1 0x5594
6838 #define A_PCIE_PIPE_LANE9_REG2 0x5598
6839 #define A_PCIE_PIPE_LANE9_REG3 0x559c
6840 #define A_PCIE_PIPE_LANE10_REG0 0x55a0
6841 #define A_PCIE_PIPE_LANE10_REG1 0x55a4
6842 #define A_PCIE_PIPE_LANE10_REG2 0x55a8
6843 #define A_PCIE_PIPE_LANE10_REG3 0x55ac
6844 #define A_PCIE_PIPE_LANE11_REG0 0x55b0
6845 #define A_PCIE_PIPE_LANE11_REG1 0x55b4
6846 #define A_PCIE_PIPE_LANE11_REG2 0x55b8
6847 #define A_PCIE_PIPE_LANE11_REG3 0x55bc
6848 #define A_PCIE_PIPE_LANE12_REG0 0x55c0
6849 #define A_PCIE_PIPE_LANE12_REG1 0x55c4
6850 #define A_PCIE_PIPE_LANE12_REG2 0x55c8
6851 #define A_PCIE_PIPE_LANE12_REG3 0x55cc
6852 #define A_PCIE_PIPE_LANE13_REG0 0x55d0
6853 #define A_PCIE_PIPE_LANE13_REG1 0x55d4
6854 #define A_PCIE_PIPE_LANE13_REG2 0x55d8
6855 #define A_PCIE_PIPE_LANE13_REG3 0x55dc
6856 #define A_PCIE_PIPE_LANE14_REG0 0x55e0
6857 #define A_PCIE_PIPE_LANE14_REG1 0x55e4
6858 #define A_PCIE_PIPE_LANE14_REG2 0x55e8
6859 #define A_PCIE_PIPE_LANE14_REG3 0x55ec
6860 #define A_PCIE_PIPE_LANE15_REG0 0x55f0
6861 #define A_PCIE_PIPE_LANE15_REG1 0x55f4
6862 #define A_PCIE_PIPE_LANE15_REG2 0x55f8
6863 #define A_PCIE_PIPE_LANE15_REG3 0x55fc
6864 #define A_PCIE_COOKIE_STAT 0x5600
6865 
6866 #define S_COOKIEB    16
6867 #define M_COOKIEB    0x3ffU
6868 #define V_COOKIEB(x) ((x) << S_COOKIEB)
6869 #define G_COOKIEB(x) (((x) >> S_COOKIEB) & M_COOKIEB)
6870 
6871 #define S_COOKIEA    0
6872 #define M_COOKIEA    0x3ffU
6873 #define V_COOKIEA(x) ((x) << S_COOKIEA)
6874 #define G_COOKIEA(x) (((x) >> S_COOKIEA) & M_COOKIEA)
6875 
6876 #define A_PCIE_FLR_PIO 0x5620
6877 
6878 #define S_RCVDBAR2COOKIE    24
6879 #define M_RCVDBAR2COOKIE    0xffU
6880 #define V_RCVDBAR2COOKIE(x) ((x) << S_RCVDBAR2COOKIE)
6881 #define G_RCVDBAR2COOKIE(x) (((x) >> S_RCVDBAR2COOKIE) & M_RCVDBAR2COOKIE)
6882 
6883 #define S_RCVDMARSPCOOKIE    16
6884 #define M_RCVDMARSPCOOKIE    0xffU
6885 #define V_RCVDMARSPCOOKIE(x) ((x) << S_RCVDMARSPCOOKIE)
6886 #define G_RCVDMARSPCOOKIE(x) (((x) >> S_RCVDMARSPCOOKIE) & M_RCVDMARSPCOOKIE)
6887 
6888 #define S_RCVDPIORSPCOOKIE    8
6889 #define M_RCVDPIORSPCOOKIE    0xffU
6890 #define V_RCVDPIORSPCOOKIE(x) ((x) << S_RCVDPIORSPCOOKIE)
6891 #define G_RCVDPIORSPCOOKIE(x) (((x) >> S_RCVDPIORSPCOOKIE) & M_RCVDPIORSPCOOKIE)
6892 
6893 #define S_EXPDCOOKIE    0
6894 #define M_EXPDCOOKIE    0xffU
6895 #define V_EXPDCOOKIE(x) ((x) << S_EXPDCOOKIE)
6896 #define G_EXPDCOOKIE(x) (((x) >> S_EXPDCOOKIE) & M_EXPDCOOKIE)
6897 
6898 #define A_PCIE_FLR_PIO2 0x5624
6899 
6900 #define S_RCVDMAREQCOOKIE    16
6901 #define M_RCVDMAREQCOOKIE    0xffU
6902 #define V_RCVDMAREQCOOKIE(x) ((x) << S_RCVDMAREQCOOKIE)
6903 #define G_RCVDMAREQCOOKIE(x) (((x) >> S_RCVDMAREQCOOKIE) & M_RCVDMAREQCOOKIE)
6904 
6905 #define S_RCVDPIOREQCOOKIE    8
6906 #define M_RCVDPIOREQCOOKIE    0xffU
6907 #define V_RCVDPIOREQCOOKIE(x) ((x) << S_RCVDPIOREQCOOKIE)
6908 #define G_RCVDPIOREQCOOKIE(x) (((x) >> S_RCVDPIOREQCOOKIE) & M_RCVDPIOREQCOOKIE)
6909 
6910 #define S_RCVDVDMRXCOOKIE    24
6911 #define M_RCVDVDMRXCOOKIE    0xffU
6912 #define V_RCVDVDMRXCOOKIE(x) ((x) << S_RCVDVDMRXCOOKIE)
6913 #define G_RCVDVDMRXCOOKIE(x) (((x) >> S_RCVDVDMRXCOOKIE) & M_RCVDVDMRXCOOKIE)
6914 
6915 #define S_RCVDVDMTXCOOKIE    16
6916 #define M_RCVDVDMTXCOOKIE    0xffU
6917 #define V_RCVDVDMTXCOOKIE(x) ((x) << S_RCVDVDMTXCOOKIE)
6918 #define G_RCVDVDMTXCOOKIE(x) (((x) >> S_RCVDVDMTXCOOKIE) & M_RCVDVDMTXCOOKIE)
6919 
6920 #define S_T6_RCVDMAREQCOOKIE    8
6921 #define M_T6_RCVDMAREQCOOKIE    0xffU
6922 #define V_T6_RCVDMAREQCOOKIE(x) ((x) << S_T6_RCVDMAREQCOOKIE)
6923 #define G_T6_RCVDMAREQCOOKIE(x) (((x) >> S_T6_RCVDMAREQCOOKIE) & M_T6_RCVDMAREQCOOKIE)
6924 
6925 #define S_T6_RCVDPIOREQCOOKIE    0
6926 #define M_T6_RCVDPIOREQCOOKIE    0xffU
6927 #define V_T6_RCVDPIOREQCOOKIE(x) ((x) << S_T6_RCVDPIOREQCOOKIE)
6928 #define G_T6_RCVDPIOREQCOOKIE(x) (((x) >> S_T6_RCVDPIOREQCOOKIE) & M_T6_RCVDPIOREQCOOKIE)
6929 
6930 #define A_T7_PCIE_VC0_CDTS0 0x56c4
6931 
6932 #define S_T7_CPLD0    16
6933 #define M_T7_CPLD0    0xffffU
6934 #define V_T7_CPLD0(x) ((x) << S_T7_CPLD0)
6935 #define G_T7_CPLD0(x) (((x) >> S_T7_CPLD0) & M_T7_CPLD0)
6936 
6937 #define S_T7_CPLH0    0
6938 #define M_T7_CPLH0    0xfffU
6939 #define V_T7_CPLH0(x) ((x) << S_T7_CPLH0)
6940 #define G_T7_CPLH0(x) (((x) >> S_T7_CPLH0) & M_T7_CPLH0)
6941 
6942 #define A_T7_PCIE_VC0_CDTS1 0x56c8
6943 
6944 #define S_T7_PD0    16
6945 #define M_T7_PD0    0xffffU
6946 #define V_T7_PD0(x) ((x) << S_T7_PD0)
6947 #define G_T7_PD0(x) (((x) >> S_T7_PD0) & M_T7_PD0)
6948 
6949 #define S_T7_PH0    0
6950 #define M_T7_PH0    0xfffU
6951 #define V_T7_PH0(x) ((x) << S_T7_PH0)
6952 #define G_T7_PH0(x) (((x) >> S_T7_PH0) & M_T7_PH0)
6953 
6954 #define A_PCIE_VC0_CDTS0 0x56cc
6955 
6956 #define S_CPLD0    20
6957 #define M_CPLD0    0xfffU
6958 #define V_CPLD0(x) ((x) << S_CPLD0)
6959 #define G_CPLD0(x) (((x) >> S_CPLD0) & M_CPLD0)
6960 
6961 #define S_PH0    12
6962 #define M_PH0    0xffU
6963 #define V_PH0(x) ((x) << S_PH0)
6964 #define G_PH0(x) (((x) >> S_PH0) & M_PH0)
6965 
6966 #define S_PD0    0
6967 #define M_PD0    0xfffU
6968 #define V_PD0(x) ((x) << S_PD0)
6969 #define G_PD0(x) (((x) >> S_PD0) & M_PD0)
6970 
6971 #define A_PCIE_VC0_CDTS2 0x56cc
6972 
6973 #define S_T7_NPD0    16
6974 #define M_T7_NPD0    0xffffU
6975 #define V_T7_NPD0(x) ((x) << S_T7_NPD0)
6976 #define G_T7_NPD0(x) (((x) >> S_T7_NPD0) & M_T7_NPD0)
6977 
6978 #define S_T7_NPH0    0
6979 #define M_T7_NPH0    0xfffU
6980 #define V_T7_NPH0(x) ((x) << S_T7_NPH0)
6981 #define G_T7_NPH0(x) (((x) >> S_T7_NPH0) & M_T7_NPH0)
6982 
6983 #define A_PCIE_VC0_CDTS1 0x56d0
6984 
6985 #define S_CPLH0    20
6986 #define M_CPLH0    0xffU
6987 #define V_CPLH0(x) ((x) << S_CPLH0)
6988 #define G_CPLH0(x) (((x) >> S_CPLH0) & M_CPLH0)
6989 
6990 #define S_NPH0    12
6991 #define M_NPH0    0xffU
6992 #define V_NPH0(x) ((x) << S_NPH0)
6993 #define G_NPH0(x) (((x) >> S_NPH0) & M_NPH0)
6994 
6995 #define S_NPD0    0
6996 #define M_NPD0    0xfffU
6997 #define V_NPD0(x) ((x) << S_NPD0)
6998 #define G_NPD0(x) (((x) >> S_NPD0) & M_NPD0)
6999 
7000 #define A_T7_PCIE_VC1_CDTS0 0x56d0
7001 #define A_PCIE_VC1_CDTS0 0x56d4
7002 
7003 #define S_CPLD1    20
7004 #define M_CPLD1    0xfffU
7005 #define V_CPLD1(x) ((x) << S_CPLD1)
7006 #define G_CPLD1(x) (((x) >> S_CPLD1) & M_CPLD1)
7007 
7008 #define S_PH1    12
7009 #define M_PH1    0xffU
7010 #define V_PH1(x) ((x) << S_PH1)
7011 #define G_PH1(x) (((x) >> S_PH1) & M_PH1)
7012 
7013 #define S_PD1    0
7014 #define M_PD1    0xfffU
7015 #define V_PD1(x) ((x) << S_PD1)
7016 #define G_PD1(x) (((x) >> S_PD1) & M_PD1)
7017 
7018 #define A_T7_PCIE_VC1_CDTS1 0x56d4
7019 #define A_PCIE_VC1_CDTS1 0x56d8
7020 
7021 #define S_CPLH1    20
7022 #define M_CPLH1    0xffU
7023 #define V_CPLH1(x) ((x) << S_CPLH1)
7024 #define G_CPLH1(x) (((x) >> S_CPLH1) & M_CPLH1)
7025 
7026 #define S_NPH1    12
7027 #define M_NPH1    0xffU
7028 #define V_NPH1(x) ((x) << S_NPH1)
7029 #define G_NPH1(x) (((x) >> S_NPH1) & M_NPH1)
7030 
7031 #define S_NPD1    0
7032 #define M_NPD1    0xfffU
7033 #define V_NPD1(x) ((x) << S_NPD1)
7034 #define G_NPD1(x) (((x) >> S_NPD1) & M_NPD1)
7035 
7036 #define A_PCIE_VC1_CDTS2 0x56d8
7037 #define A_PCIE_FLR_PF_STATUS 0x56dc
7038 #define A_PCIE_FLR_VF0_STATUS 0x56e0
7039 #define A_PCIE_FLR_VF1_STATUS 0x56e4
7040 #define A_PCIE_FLR_VF2_STATUS 0x56e8
7041 #define A_PCIE_FLR_VF3_STATUS 0x56ec
7042 #define A_PCIE_STAT 0x56f4
7043 
7044 #define S_PM_STATUS    24
7045 #define M_PM_STATUS    0xffU
7046 #define V_PM_STATUS(x) ((x) << S_PM_STATUS)
7047 #define G_PM_STATUS(x) (((x) >> S_PM_STATUS) & M_PM_STATUS)
7048 
7049 #define S_PM_CURRENTSTATE    20
7050 #define M_PM_CURRENTSTATE    0x7U
7051 #define V_PM_CURRENTSTATE(x) ((x) << S_PM_CURRENTSTATE)
7052 #define G_PM_CURRENTSTATE(x) (((x) >> S_PM_CURRENTSTATE) & M_PM_CURRENTSTATE)
7053 
7054 #define S_LTSSMENABLE    12
7055 #define V_LTSSMENABLE(x) ((x) << S_LTSSMENABLE)
7056 #define F_LTSSMENABLE    V_LTSSMENABLE(1U)
7057 
7058 #define S_STATECFGINITF    4
7059 #define M_STATECFGINITF    0x7fU
7060 #define V_STATECFGINITF(x) ((x) << S_STATECFGINITF)
7061 #define G_STATECFGINITF(x) (((x) >> S_STATECFGINITF) & M_STATECFGINITF)
7062 
7063 #define S_STATECFGINIT    0
7064 #define M_STATECFGINIT    0xfU
7065 #define V_STATECFGINIT(x) ((x) << S_STATECFGINIT)
7066 #define G_STATECFGINIT(x) (((x) >> S_STATECFGINIT) & M_STATECFGINIT)
7067 
7068 #define S_LTSSMENABLE_PCIE    12
7069 #define V_LTSSMENABLE_PCIE(x) ((x) << S_LTSSMENABLE_PCIE)
7070 #define F_LTSSMENABLE_PCIE    V_LTSSMENABLE_PCIE(1U)
7071 
7072 #define S_STATECFGINITF_PCIE    4
7073 #define M_STATECFGINITF_PCIE    0xffU
7074 #define V_STATECFGINITF_PCIE(x) ((x) << S_STATECFGINITF_PCIE)
7075 #define G_STATECFGINITF_PCIE(x) (((x) >> S_STATECFGINITF_PCIE) & M_STATECFGINITF_PCIE)
7076 
7077 #define S_STATECFGINIT_PCIE    0
7078 #define M_STATECFGINIT_PCIE    0xfU
7079 #define V_STATECFGINIT_PCIE(x) ((x) << S_STATECFGINIT_PCIE)
7080 #define G_STATECFGINIT_PCIE(x) (((x) >> S_STATECFGINIT_PCIE) & M_STATECFGINIT_PCIE)
7081 
7082 #define A_PCIE_CRS 0x56f8
7083 
7084 #define S_CRS_ENABLE    0
7085 #define V_CRS_ENABLE(x) ((x) << S_CRS_ENABLE)
7086 #define F_CRS_ENABLE    V_CRS_ENABLE(1U)
7087 
7088 #define A_PCIE_LTSSM 0x56fc
7089 
7090 #define S_LTSSM_ENABLE    0
7091 #define V_LTSSM_ENABLE(x) ((x) << S_LTSSM_ENABLE)
7092 #define F_LTSSM_ENABLE    V_LTSSM_ENABLE(1U)
7093 
7094 #define S_LTSSM_STALL_DISABLE    1
7095 #define V_LTSSM_STALL_DISABLE(x) ((x) << S_LTSSM_STALL_DISABLE)
7096 #define F_LTSSM_STALL_DISABLE    V_LTSSM_STALL_DISABLE(1U)
7097 
7098 #define A_PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER 0x5700
7099 
7100 #define S_REPLAY_TIME_LIMIT    16
7101 #define M_REPLAY_TIME_LIMIT    0xffffU
7102 #define V_REPLAY_TIME_LIMIT(x) ((x) << S_REPLAY_TIME_LIMIT)
7103 #define G_REPLAY_TIME_LIMIT(x) (((x) >> S_REPLAY_TIME_LIMIT) & M_REPLAY_TIME_LIMIT)
7104 
7105 #define S_ACK_LATENCY_TIMER_LIMIT    0
7106 #define M_ACK_LATENCY_TIMER_LIMIT    0xffffU
7107 #define V_ACK_LATENCY_TIMER_LIMIT(x) ((x) << S_ACK_LATENCY_TIMER_LIMIT)
7108 #define G_ACK_LATENCY_TIMER_LIMIT(x) (((x) >> S_ACK_LATENCY_TIMER_LIMIT) & M_ACK_LATENCY_TIMER_LIMIT)
7109 
7110 #define A_PCIE_CORE_VENDOR_SPECIFIC_DLLP 0x5704
7111 #define A_PCIE_CORE_PORT_FORCE_LINK 0x5708
7112 
7113 #define S_LOW_POWER_ENTRANCE_COUNT    24
7114 #define M_LOW_POWER_ENTRANCE_COUNT    0xffU
7115 #define V_LOW_POWER_ENTRANCE_COUNT(x) ((x) << S_LOW_POWER_ENTRANCE_COUNT)
7116 #define G_LOW_POWER_ENTRANCE_COUNT(x) (((x) >> S_LOW_POWER_ENTRANCE_COUNT) & M_LOW_POWER_ENTRANCE_COUNT)
7117 
7118 #define S_LINK_STATE    16
7119 #define M_LINK_STATE    0x3fU
7120 #define V_LINK_STATE(x) ((x) << S_LINK_STATE)
7121 #define G_LINK_STATE(x) (((x) >> S_LINK_STATE) & M_LINK_STATE)
7122 
7123 #define S_FORCE_LINK    15
7124 #define V_FORCE_LINK(x) ((x) << S_FORCE_LINK)
7125 #define F_FORCE_LINK    V_FORCE_LINK(1U)
7126 
7127 #define S_LINK_NUMBER    0
7128 #define M_LINK_NUMBER    0xffU
7129 #define V_LINK_NUMBER(x) ((x) << S_LINK_NUMBER)
7130 #define G_LINK_NUMBER(x) (((x) >> S_LINK_NUMBER) & M_LINK_NUMBER)
7131 
7132 #define A_PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL 0x570c
7133 
7134 #define S_ENTER_ASPM_L1_WO_L0S    30
7135 #define V_ENTER_ASPM_L1_WO_L0S(x) ((x) << S_ENTER_ASPM_L1_WO_L0S)
7136 #define F_ENTER_ASPM_L1_WO_L0S    V_ENTER_ASPM_L1_WO_L0S(1U)
7137 
7138 #define S_L1_ENTRANCE_LATENCY    27
7139 #define M_L1_ENTRANCE_LATENCY    0x7U
7140 #define V_L1_ENTRANCE_LATENCY(x) ((x) << S_L1_ENTRANCE_LATENCY)
7141 #define G_L1_ENTRANCE_LATENCY(x) (((x) >> S_L1_ENTRANCE_LATENCY) & M_L1_ENTRANCE_LATENCY)
7142 
7143 #define S_L0S_ENTRANCE_LATENCY    24
7144 #define M_L0S_ENTRANCE_LATENCY    0x7U
7145 #define V_L0S_ENTRANCE_LATENCY(x) ((x) << S_L0S_ENTRANCE_LATENCY)
7146 #define G_L0S_ENTRANCE_LATENCY(x) (((x) >> S_L0S_ENTRANCE_LATENCY) & M_L0S_ENTRANCE_LATENCY)
7147 
7148 #define S_COMMON_CLOCK_N_FTS    16
7149 #define M_COMMON_CLOCK_N_FTS    0xffU
7150 #define V_COMMON_CLOCK_N_FTS(x) ((x) << S_COMMON_CLOCK_N_FTS)
7151 #define G_COMMON_CLOCK_N_FTS(x) (((x) >> S_COMMON_CLOCK_N_FTS) & M_COMMON_CLOCK_N_FTS)
7152 
7153 #define S_N_FTS    8
7154 #define M_N_FTS    0xffU
7155 #define V_N_FTS(x) ((x) << S_N_FTS)
7156 #define G_N_FTS(x) (((x) >> S_N_FTS) & M_N_FTS)
7157 
7158 #define S_ACK_FREQUENCY    0
7159 #define M_ACK_FREQUENCY    0xffU
7160 #define V_ACK_FREQUENCY(x) ((x) << S_ACK_FREQUENCY)
7161 #define G_ACK_FREQUENCY(x) (((x) >> S_ACK_FREQUENCY) & M_ACK_FREQUENCY)
7162 
7163 #define A_PCIE_CORE_PORT_LINK_CONTROL 0x5710
7164 
7165 #define S_CROSSLINK_ACTIVE    23
7166 #define V_CROSSLINK_ACTIVE(x) ((x) << S_CROSSLINK_ACTIVE)
7167 #define F_CROSSLINK_ACTIVE    V_CROSSLINK_ACTIVE(1U)
7168 
7169 #define S_CROSSLINK_ENABLE    22
7170 #define V_CROSSLINK_ENABLE(x) ((x) << S_CROSSLINK_ENABLE)
7171 #define F_CROSSLINK_ENABLE    V_CROSSLINK_ENABLE(1U)
7172 
7173 #define S_LINK_MODE_ENABLE    16
7174 #define M_LINK_MODE_ENABLE    0x3fU
7175 #define V_LINK_MODE_ENABLE(x) ((x) << S_LINK_MODE_ENABLE)
7176 #define G_LINK_MODE_ENABLE(x) (((x) >> S_LINK_MODE_ENABLE) & M_LINK_MODE_ENABLE)
7177 
7178 #define S_FAST_LINK_MODE    7
7179 #define V_FAST_LINK_MODE(x) ((x) << S_FAST_LINK_MODE)
7180 #define F_FAST_LINK_MODE    V_FAST_LINK_MODE(1U)
7181 
7182 #define S_DLL_LINK_ENABLE    5
7183 #define V_DLL_LINK_ENABLE(x) ((x) << S_DLL_LINK_ENABLE)
7184 #define F_DLL_LINK_ENABLE    V_DLL_LINK_ENABLE(1U)
7185 
7186 #define S_RESET_ASSERT    3
7187 #define V_RESET_ASSERT(x) ((x) << S_RESET_ASSERT)
7188 #define F_RESET_ASSERT    V_RESET_ASSERT(1U)
7189 
7190 #define S_LOOPBACK_ENABLE    2
7191 #define V_LOOPBACK_ENABLE(x) ((x) << S_LOOPBACK_ENABLE)
7192 #define F_LOOPBACK_ENABLE    V_LOOPBACK_ENABLE(1U)
7193 
7194 #define S_SCRAMBLE_DISABLE    1
7195 #define V_SCRAMBLE_DISABLE(x) ((x) << S_SCRAMBLE_DISABLE)
7196 #define F_SCRAMBLE_DISABLE    V_SCRAMBLE_DISABLE(1U)
7197 
7198 #define S_VENDOR_SPECIFIC_DLLP_REQUEST    0
7199 #define V_VENDOR_SPECIFIC_DLLP_REQUEST(x) ((x) << S_VENDOR_SPECIFIC_DLLP_REQUEST)
7200 #define F_VENDOR_SPECIFIC_DLLP_REQUEST    V_VENDOR_SPECIFIC_DLLP_REQUEST(1U)
7201 
7202 #define A_PCIE_CORE_LANE_SKEW 0x5714
7203 
7204 #define S_DISABLE_DESKEW    31
7205 #define V_DISABLE_DESKEW(x) ((x) << S_DISABLE_DESKEW)
7206 #define F_DISABLE_DESKEW    V_DISABLE_DESKEW(1U)
7207 
7208 #define S_ACK_NAK_DISABLE    25
7209 #define V_ACK_NAK_DISABLE(x) ((x) << S_ACK_NAK_DISABLE)
7210 #define F_ACK_NAK_DISABLE    V_ACK_NAK_DISABLE(1U)
7211 
7212 #define S_FLOW_CONTROL_DISABLE    24
7213 #define V_FLOW_CONTROL_DISABLE(x) ((x) << S_FLOW_CONTROL_DISABLE)
7214 #define F_FLOW_CONTROL_DISABLE    V_FLOW_CONTROL_DISABLE(1U)
7215 
7216 #define S_INSERT_TXSKEW    0
7217 #define M_INSERT_TXSKEW    0xffffffU
7218 #define V_INSERT_TXSKEW(x) ((x) << S_INSERT_TXSKEW)
7219 #define G_INSERT_TXSKEW(x) (((x) >> S_INSERT_TXSKEW) & M_INSERT_TXSKEW)
7220 
7221 #define A_PCIE_CORE_SYMBOL_NUMBER 0x5718
7222 
7223 #define S_FLOW_CONTROL_TIMER_MODIFIER    24
7224 #define M_FLOW_CONTROL_TIMER_MODIFIER    0x1fU
7225 #define V_FLOW_CONTROL_TIMER_MODIFIER(x) ((x) << S_FLOW_CONTROL_TIMER_MODIFIER)
7226 #define G_FLOW_CONTROL_TIMER_MODIFIER(x) (((x) >> S_FLOW_CONTROL_TIMER_MODIFIER) & M_FLOW_CONTROL_TIMER_MODIFIER)
7227 
7228 #define S_ACK_NAK_TIMER_MODIFIER    19
7229 #define M_ACK_NAK_TIMER_MODIFIER    0x1fU
7230 #define V_ACK_NAK_TIMER_MODIFIER(x) ((x) << S_ACK_NAK_TIMER_MODIFIER)
7231 #define G_ACK_NAK_TIMER_MODIFIER(x) (((x) >> S_ACK_NAK_TIMER_MODIFIER) & M_ACK_NAK_TIMER_MODIFIER)
7232 
7233 #define S_REPLAY_TIMER_MODIFIER    14
7234 #define M_REPLAY_TIMER_MODIFIER    0x1fU
7235 #define V_REPLAY_TIMER_MODIFIER(x) ((x) << S_REPLAY_TIMER_MODIFIER)
7236 #define G_REPLAY_TIMER_MODIFIER(x) (((x) >> S_REPLAY_TIMER_MODIFIER) & M_REPLAY_TIMER_MODIFIER)
7237 
7238 #define S_MAXFUNC    0
7239 #define M_MAXFUNC    0x7U
7240 #define V_MAXFUNC(x) ((x) << S_MAXFUNC)
7241 #define G_MAXFUNC(x) (((x) >> S_MAXFUNC) & M_MAXFUNC)
7242 
7243 #define A_PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1 0x571c
7244 
7245 #define S_MASK_RADM_FILTER    16
7246 #define M_MASK_RADM_FILTER    0xffffU
7247 #define V_MASK_RADM_FILTER(x) ((x) << S_MASK_RADM_FILTER)
7248 #define G_MASK_RADM_FILTER(x) (((x) >> S_MASK_RADM_FILTER) & M_MASK_RADM_FILTER)
7249 
7250 #define S_DISABLE_FC_WATCHDOG    15
7251 #define V_DISABLE_FC_WATCHDOG(x) ((x) << S_DISABLE_FC_WATCHDOG)
7252 #define F_DISABLE_FC_WATCHDOG    V_DISABLE_FC_WATCHDOG(1U)
7253 
7254 #define S_SKP_INTERVAL    0
7255 #define M_SKP_INTERVAL    0x7ffU
7256 #define V_SKP_INTERVAL(x) ((x) << S_SKP_INTERVAL)
7257 #define G_SKP_INTERVAL(x) (((x) >> S_SKP_INTERVAL) & M_SKP_INTERVAL)
7258 
7259 #define A_PCIE_CORE_FILTER_MASK2 0x5720
7260 #define A_PCIE_CORE_DEBUG_0 0x5728
7261 #define A_PCIE_CORE_DEBUG_1 0x572c
7262 #define A_PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS 0x5730
7263 
7264 #define S_TXPH_FC    12
7265 #define M_TXPH_FC    0xffU
7266 #define V_TXPH_FC(x) ((x) << S_TXPH_FC)
7267 #define G_TXPH_FC(x) (((x) >> S_TXPH_FC) & M_TXPH_FC)
7268 
7269 #define S_TXPD_FC    0
7270 #define M_TXPD_FC    0xfffU
7271 #define V_TXPD_FC(x) ((x) << S_TXPD_FC)
7272 #define G_TXPD_FC(x) (((x) >> S_TXPD_FC) & M_TXPD_FC)
7273 
7274 #define A_PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS 0x5734
7275 
7276 #define S_TXNPH_FC    12
7277 #define M_TXNPH_FC    0xffU
7278 #define V_TXNPH_FC(x) ((x) << S_TXNPH_FC)
7279 #define G_TXNPH_FC(x) (((x) >> S_TXNPH_FC) & M_TXNPH_FC)
7280 
7281 #define S_TXNPD_FC    0
7282 #define M_TXNPD_FC    0xfffU
7283 #define V_TXNPD_FC(x) ((x) << S_TXNPD_FC)
7284 #define G_TXNPD_FC(x) (((x) >> S_TXNPD_FC) & M_TXNPD_FC)
7285 
7286 #define A_PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS 0x5738
7287 
7288 #define S_TXCPLH_FC    12
7289 #define M_TXCPLH_FC    0xffU
7290 #define V_TXCPLH_FC(x) ((x) << S_TXCPLH_FC)
7291 #define G_TXCPLH_FC(x) (((x) >> S_TXCPLH_FC) & M_TXCPLH_FC)
7292 
7293 #define S_TXCPLD_FC    0
7294 #define M_TXCPLD_FC    0xfffU
7295 #define V_TXCPLD_FC(x) ((x) << S_TXCPLD_FC)
7296 #define G_TXCPLD_FC(x) (((x) >> S_TXCPLD_FC) & M_TXCPLD_FC)
7297 
7298 #define A_PCIE_CORE_QUEUE_STATUS 0x573c
7299 
7300 #define S_RXQUEUE_NOT_EMPTY    2
7301 #define V_RXQUEUE_NOT_EMPTY(x) ((x) << S_RXQUEUE_NOT_EMPTY)
7302 #define F_RXQUEUE_NOT_EMPTY    V_RXQUEUE_NOT_EMPTY(1U)
7303 
7304 #define S_TXRETRYBUF_NOT_EMPTY    1
7305 #define V_TXRETRYBUF_NOT_EMPTY(x) ((x) << S_TXRETRYBUF_NOT_EMPTY)
7306 #define F_TXRETRYBUF_NOT_EMPTY    V_TXRETRYBUF_NOT_EMPTY(1U)
7307 
7308 #define S_RXTLP_FC_NOT_RETURNED    0
7309 #define V_RXTLP_FC_NOT_RETURNED(x) ((x) << S_RXTLP_FC_NOT_RETURNED)
7310 #define F_RXTLP_FC_NOT_RETURNED    V_RXTLP_FC_NOT_RETURNED(1U)
7311 
7312 #define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_1 0x5740
7313 
7314 #define S_VC3_WRR    24
7315 #define M_VC3_WRR    0xffU
7316 #define V_VC3_WRR(x) ((x) << S_VC3_WRR)
7317 #define G_VC3_WRR(x) (((x) >> S_VC3_WRR) & M_VC3_WRR)
7318 
7319 #define S_VC2_WRR    16
7320 #define M_VC2_WRR    0xffU
7321 #define V_VC2_WRR(x) ((x) << S_VC2_WRR)
7322 #define G_VC2_WRR(x) (((x) >> S_VC2_WRR) & M_VC2_WRR)
7323 
7324 #define S_VC1_WRR    8
7325 #define M_VC1_WRR    0xffU
7326 #define V_VC1_WRR(x) ((x) << S_VC1_WRR)
7327 #define G_VC1_WRR(x) (((x) >> S_VC1_WRR) & M_VC1_WRR)
7328 
7329 #define S_VC0_WRR    0
7330 #define M_VC0_WRR    0xffU
7331 #define V_VC0_WRR(x) ((x) << S_VC0_WRR)
7332 #define G_VC0_WRR(x) (((x) >> S_VC0_WRR) & M_VC0_WRR)
7333 
7334 #define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_2 0x5744
7335 
7336 #define S_VC7_WRR    24
7337 #define M_VC7_WRR    0xffU
7338 #define V_VC7_WRR(x) ((x) << S_VC7_WRR)
7339 #define G_VC7_WRR(x) (((x) >> S_VC7_WRR) & M_VC7_WRR)
7340 
7341 #define S_VC6_WRR    16
7342 #define M_VC6_WRR    0xffU
7343 #define V_VC6_WRR(x) ((x) << S_VC6_WRR)
7344 #define G_VC6_WRR(x) (((x) >> S_VC6_WRR) & M_VC6_WRR)
7345 
7346 #define S_VC5_WRR    8
7347 #define M_VC5_WRR    0xffU
7348 #define V_VC5_WRR(x) ((x) << S_VC5_WRR)
7349 #define G_VC5_WRR(x) (((x) >> S_VC5_WRR) & M_VC5_WRR)
7350 
7351 #define S_VC4_WRR    0
7352 #define M_VC4_WRR    0xffU
7353 #define V_VC4_WRR(x) ((x) << S_VC4_WRR)
7354 #define G_VC4_WRR(x) (((x) >> S_VC4_WRR) & M_VC4_WRR)
7355 
7356 #define A_PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL 0x5748
7357 
7358 #define S_VC0_RX_ORDERING    31
7359 #define V_VC0_RX_ORDERING(x) ((x) << S_VC0_RX_ORDERING)
7360 #define F_VC0_RX_ORDERING    V_VC0_RX_ORDERING(1U)
7361 
7362 #define S_VC0_TLP_ORDERING    30
7363 #define V_VC0_TLP_ORDERING(x) ((x) << S_VC0_TLP_ORDERING)
7364 #define F_VC0_TLP_ORDERING    V_VC0_TLP_ORDERING(1U)
7365 
7366 #define S_VC0_PTLP_QUEUE_MODE    21
7367 #define M_VC0_PTLP_QUEUE_MODE    0x7U
7368 #define V_VC0_PTLP_QUEUE_MODE(x) ((x) << S_VC0_PTLP_QUEUE_MODE)
7369 #define G_VC0_PTLP_QUEUE_MODE(x) (((x) >> S_VC0_PTLP_QUEUE_MODE) & M_VC0_PTLP_QUEUE_MODE)
7370 
7371 #define S_VC0_PH_CREDITS    12
7372 #define M_VC0_PH_CREDITS    0xffU
7373 #define V_VC0_PH_CREDITS(x) ((x) << S_VC0_PH_CREDITS)
7374 #define G_VC0_PH_CREDITS(x) (((x) >> S_VC0_PH_CREDITS) & M_VC0_PH_CREDITS)
7375 
7376 #define S_VC0_PD_CREDITS    0
7377 #define M_VC0_PD_CREDITS    0xfffU
7378 #define V_VC0_PD_CREDITS(x) ((x) << S_VC0_PD_CREDITS)
7379 #define G_VC0_PD_CREDITS(x) (((x) >> S_VC0_PD_CREDITS) & M_VC0_PD_CREDITS)
7380 
7381 #define A_PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x574c
7382 
7383 #define S_VC0_NPTLP_QUEUE_MODE    21
7384 #define M_VC0_NPTLP_QUEUE_MODE    0x7U
7385 #define V_VC0_NPTLP_QUEUE_MODE(x) ((x) << S_VC0_NPTLP_QUEUE_MODE)
7386 #define G_VC0_NPTLP_QUEUE_MODE(x) (((x) >> S_VC0_NPTLP_QUEUE_MODE) & M_VC0_NPTLP_QUEUE_MODE)
7387 
7388 #define S_VC0_NPH_CREDITS    12
7389 #define M_VC0_NPH_CREDITS    0xffU
7390 #define V_VC0_NPH_CREDITS(x) ((x) << S_VC0_NPH_CREDITS)
7391 #define G_VC0_NPH_CREDITS(x) (((x) >> S_VC0_NPH_CREDITS) & M_VC0_NPH_CREDITS)
7392 
7393 #define S_VC0_NPD_CREDITS    0
7394 #define M_VC0_NPD_CREDITS    0xfffU
7395 #define V_VC0_NPD_CREDITS(x) ((x) << S_VC0_NPD_CREDITS)
7396 #define G_VC0_NPD_CREDITS(x) (((x) >> S_VC0_NPD_CREDITS) & M_VC0_NPD_CREDITS)
7397 
7398 #define A_PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL 0x5750
7399 
7400 #define S_VC0_CPLTLP_QUEUE_MODE    21
7401 #define M_VC0_CPLTLP_QUEUE_MODE    0x7U
7402 #define V_VC0_CPLTLP_QUEUE_MODE(x) ((x) << S_VC0_CPLTLP_QUEUE_MODE)
7403 #define G_VC0_CPLTLP_QUEUE_MODE(x) (((x) >> S_VC0_CPLTLP_QUEUE_MODE) & M_VC0_CPLTLP_QUEUE_MODE)
7404 
7405 #define S_VC0_CPLH_CREDITS    12
7406 #define M_VC0_CPLH_CREDITS    0xffU
7407 #define V_VC0_CPLH_CREDITS(x) ((x) << S_VC0_CPLH_CREDITS)
7408 #define G_VC0_CPLH_CREDITS(x) (((x) >> S_VC0_CPLH_CREDITS) & M_VC0_CPLH_CREDITS)
7409 
7410 #define S_VC0_CPLD_CREDITS    0
7411 #define M_VC0_CPLD_CREDITS    0xfffU
7412 #define V_VC0_CPLD_CREDITS(x) ((x) << S_VC0_CPLD_CREDITS)
7413 #define G_VC0_CPLD_CREDITS(x) (((x) >> S_VC0_CPLD_CREDITS) & M_VC0_CPLD_CREDITS)
7414 
7415 #define A_PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL 0x5754
7416 
7417 #define S_VC1_TLP_ORDERING    30
7418 #define V_VC1_TLP_ORDERING(x) ((x) << S_VC1_TLP_ORDERING)
7419 #define F_VC1_TLP_ORDERING    V_VC1_TLP_ORDERING(1U)
7420 
7421 #define S_VC1_PTLP_QUEUE_MODE    21
7422 #define M_VC1_PTLP_QUEUE_MODE    0x7U
7423 #define V_VC1_PTLP_QUEUE_MODE(x) ((x) << S_VC1_PTLP_QUEUE_MODE)
7424 #define G_VC1_PTLP_QUEUE_MODE(x) (((x) >> S_VC1_PTLP_QUEUE_MODE) & M_VC1_PTLP_QUEUE_MODE)
7425 
7426 #define S_VC1_PH_CREDITS    12
7427 #define M_VC1_PH_CREDITS    0xffU
7428 #define V_VC1_PH_CREDITS(x) ((x) << S_VC1_PH_CREDITS)
7429 #define G_VC1_PH_CREDITS(x) (((x) >> S_VC1_PH_CREDITS) & M_VC1_PH_CREDITS)
7430 
7431 #define S_VC1_PD_CREDITS    0
7432 #define M_VC1_PD_CREDITS    0xfffU
7433 #define V_VC1_PD_CREDITS(x) ((x) << S_VC1_PD_CREDITS)
7434 #define G_VC1_PD_CREDITS(x) (((x) >> S_VC1_PD_CREDITS) & M_VC1_PD_CREDITS)
7435 
7436 #define A_PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x5758
7437 
7438 #define S_VC1_NPTLP_QUEUE_MODE    21
7439 #define M_VC1_NPTLP_QUEUE_MODE    0x7U
7440 #define V_VC1_NPTLP_QUEUE_MODE(x) ((x) << S_VC1_NPTLP_QUEUE_MODE)
7441 #define G_VC1_NPTLP_QUEUE_MODE(x) (((x) >> S_VC1_NPTLP_QUEUE_MODE) & M_VC1_NPTLP_QUEUE_MODE)
7442 
7443 #define S_VC1_NPH_CREDITS    12
7444 #define M_VC1_NPH_CREDITS    0xffU
7445 #define V_VC1_NPH_CREDITS(x) ((x) << S_VC1_NPH_CREDITS)
7446 #define G_VC1_NPH_CREDITS(x) (((x) >> S_VC1_NPH_CREDITS) & M_VC1_NPH_CREDITS)
7447 
7448 #define S_VC1_NPD_CREDITS    0
7449 #define M_VC1_NPD_CREDITS    0xfffU
7450 #define V_VC1_NPD_CREDITS(x) ((x) << S_VC1_NPD_CREDITS)
7451 #define G_VC1_NPD_CREDITS(x) (((x) >> S_VC1_NPD_CREDITS) & M_VC1_NPD_CREDITS)
7452 
7453 #define A_PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL 0x575c
7454 
7455 #define S_VC1_CPLTLP_QUEUE_MODE    21
7456 #define M_VC1_CPLTLP_QUEUE_MODE    0x7U
7457 #define V_VC1_CPLTLP_QUEUE_MODE(x) ((x) << S_VC1_CPLTLP_QUEUE_MODE)
7458 #define G_VC1_CPLTLP_QUEUE_MODE(x) (((x) >> S_VC1_CPLTLP_QUEUE_MODE) & M_VC1_CPLTLP_QUEUE_MODE)
7459 
7460 #define S_VC1_CPLH_CREDITS    12
7461 #define M_VC1_CPLH_CREDITS    0xffU
7462 #define V_VC1_CPLH_CREDITS(x) ((x) << S_VC1_CPLH_CREDITS)
7463 #define G_VC1_CPLH_CREDITS(x) (((x) >> S_VC1_CPLH_CREDITS) & M_VC1_CPLH_CREDITS)
7464 
7465 #define S_VC1_CPLD_CREDITS    0
7466 #define M_VC1_CPLD_CREDITS    0xfffU
7467 #define V_VC1_CPLD_CREDITS(x) ((x) << S_VC1_CPLD_CREDITS)
7468 #define G_VC1_CPLD_CREDITS(x) (((x) >> S_VC1_CPLD_CREDITS) & M_VC1_CPLD_CREDITS)
7469 
7470 #define A_PCIE_CORE_LINK_WIDTH_SPEED_CHANGE 0x580c
7471 
7472 #define S_SEL_DEEMPHASIS    20
7473 #define V_SEL_DEEMPHASIS(x) ((x) << S_SEL_DEEMPHASIS)
7474 #define F_SEL_DEEMPHASIS    V_SEL_DEEMPHASIS(1U)
7475 
7476 #define S_TXCMPLRCV    19
7477 #define V_TXCMPLRCV(x) ((x) << S_TXCMPLRCV)
7478 #define F_TXCMPLRCV    V_TXCMPLRCV(1U)
7479 
7480 #define S_PHYTXSWING    18
7481 #define V_PHYTXSWING(x) ((x) << S_PHYTXSWING)
7482 #define F_PHYTXSWING    V_PHYTXSWING(1U)
7483 
7484 #define S_DIRSPDCHANGE    17
7485 #define V_DIRSPDCHANGE(x) ((x) << S_DIRSPDCHANGE)
7486 #define F_DIRSPDCHANGE    V_DIRSPDCHANGE(1U)
7487 
7488 #define S_NUM_LANES    8
7489 #define M_NUM_LANES    0x1ffU
7490 #define V_NUM_LANES(x) ((x) << S_NUM_LANES)
7491 #define G_NUM_LANES(x) (((x) >> S_NUM_LANES) & M_NUM_LANES)
7492 
7493 #define S_NFTS_GEN2_3    0
7494 #define M_NFTS_GEN2_3    0xffU
7495 #define V_NFTS_GEN2_3(x) ((x) << S_NFTS_GEN2_3)
7496 #define G_NFTS_GEN2_3(x) (((x) >> S_NFTS_GEN2_3) & M_NFTS_GEN2_3)
7497 
7498 #define S_AUTO_LANE_FLIP_CTRL_EN    16
7499 #define V_AUTO_LANE_FLIP_CTRL_EN(x) ((x) << S_AUTO_LANE_FLIP_CTRL_EN)
7500 #define F_AUTO_LANE_FLIP_CTRL_EN    V_AUTO_LANE_FLIP_CTRL_EN(1U)
7501 
7502 #define S_T6_NUM_LANES    8
7503 #define M_T6_NUM_LANES    0x1fU
7504 #define V_T6_NUM_LANES(x) ((x) << S_T6_NUM_LANES)
7505 #define G_T6_NUM_LANES(x) (((x) >> S_T6_NUM_LANES) & M_T6_NUM_LANES)
7506 
7507 #define A_PCIE_CORE_PHY_STATUS 0x5810
7508 #define A_PCIE_CORE_PHY_CONTROL 0x5814
7509 #define A_PCIE_CORE_GEN3_CONTROL 0x5890
7510 
7511 #define S_DC_BALANCE_DISABLE    18
7512 #define V_DC_BALANCE_DISABLE(x) ((x) << S_DC_BALANCE_DISABLE)
7513 #define F_DC_BALANCE_DISABLE    V_DC_BALANCE_DISABLE(1U)
7514 
7515 #define S_DLLP_DELAY_DISABLE    17
7516 #define V_DLLP_DELAY_DISABLE(x) ((x) << S_DLLP_DELAY_DISABLE)
7517 #define F_DLLP_DELAY_DISABLE    V_DLLP_DELAY_DISABLE(1U)
7518 
7519 #define S_EQL_DISABLE    16
7520 #define V_EQL_DISABLE(x) ((x) << S_EQL_DISABLE)
7521 #define F_EQL_DISABLE    V_EQL_DISABLE(1U)
7522 
7523 #define S_EQL_REDO_DISABLE    11
7524 #define V_EQL_REDO_DISABLE(x) ((x) << S_EQL_REDO_DISABLE)
7525 #define F_EQL_REDO_DISABLE    V_EQL_REDO_DISABLE(1U)
7526 
7527 #define S_EQL_EIEOS_CNTRST_DISABLE    10
7528 #define V_EQL_EIEOS_CNTRST_DISABLE(x) ((x) << S_EQL_EIEOS_CNTRST_DISABLE)
7529 #define F_EQL_EIEOS_CNTRST_DISABLE    V_EQL_EIEOS_CNTRST_DISABLE(1U)
7530 
7531 #define S_EQL_PH2_PH3_DISABLE    9
7532 #define V_EQL_PH2_PH3_DISABLE(x) ((x) << S_EQL_PH2_PH3_DISABLE)
7533 #define F_EQL_PH2_PH3_DISABLE    V_EQL_PH2_PH3_DISABLE(1U)
7534 
7535 #define S_DISABLE_SCRAMBLER    8
7536 #define V_DISABLE_SCRAMBLER(x) ((x) << S_DISABLE_SCRAMBLER)
7537 #define F_DISABLE_SCRAMBLER    V_DISABLE_SCRAMBLER(1U)
7538 
7539 #define S_RATE_SHADOW_SEL    24
7540 #define M_RATE_SHADOW_SEL    0x3U
7541 #define V_RATE_SHADOW_SEL(x) ((x) << S_RATE_SHADOW_SEL)
7542 #define G_RATE_SHADOW_SEL(x) (((x) >> S_RATE_SHADOW_SEL) & M_RATE_SHADOW_SEL)
7543 
7544 #define A_PCIE_CORE_GEN3_EQ_FS_LF 0x5894
7545 
7546 #define S_FULL_SWING    6
7547 #define M_FULL_SWING    0x3fU
7548 #define V_FULL_SWING(x) ((x) << S_FULL_SWING)
7549 #define G_FULL_SWING(x) (((x) >> S_FULL_SWING) & M_FULL_SWING)
7550 
7551 #define S_LOW_FREQUENCY    0
7552 #define M_LOW_FREQUENCY    0x3fU
7553 #define V_LOW_FREQUENCY(x) ((x) << S_LOW_FREQUENCY)
7554 #define G_LOW_FREQUENCY(x) (((x) >> S_LOW_FREQUENCY) & M_LOW_FREQUENCY)
7555 
7556 #define A_PCIE_CORE_GEN3_EQ_PRESET_COEFF 0x5898
7557 
7558 #define S_POSTCURSOR    12
7559 #define M_POSTCURSOR    0x3fU
7560 #define V_POSTCURSOR(x) ((x) << S_POSTCURSOR)
7561 #define G_POSTCURSOR(x) (((x) >> S_POSTCURSOR) & M_POSTCURSOR)
7562 
7563 #define S_CURSOR    6
7564 #define M_CURSOR    0x3fU
7565 #define V_CURSOR(x) ((x) << S_CURSOR)
7566 #define G_CURSOR(x) (((x) >> S_CURSOR) & M_CURSOR)
7567 
7568 #define S_PRECURSOR    0
7569 #define M_PRECURSOR    0x3fU
7570 #define V_PRECURSOR(x) ((x) << S_PRECURSOR)
7571 #define G_PRECURSOR(x) (((x) >> S_PRECURSOR) & M_PRECURSOR)
7572 
7573 #define A_PCIE_CORE_GEN3_EQ_PRESET_INDEX 0x589c
7574 
7575 #define S_INDEX    0
7576 #define M_INDEX    0xfU
7577 #define V_INDEX(x) ((x) << S_INDEX)
7578 #define G_INDEX(x) (((x) >> S_INDEX) & M_INDEX)
7579 
7580 #define A_PCIE_CORE_GEN3_EQ_STATUS 0x58a4
7581 
7582 #define S_LEGALITY_STATUS    0
7583 #define V_LEGALITY_STATUS(x) ((x) << S_LEGALITY_STATUS)
7584 #define F_LEGALITY_STATUS    V_LEGALITY_STATUS(1U)
7585 
7586 #define A_PCIE_CORE_GEN3_EQ_CONTROL 0x58a8
7587 
7588 #define S_INCLUDE_INITIAL_FOM    24
7589 #define V_INCLUDE_INITIAL_FOM(x) ((x) << S_INCLUDE_INITIAL_FOM)
7590 #define F_INCLUDE_INITIAL_FOM    V_INCLUDE_INITIAL_FOM(1U)
7591 
7592 #define S_PRESET_REQUEST_VECTOR    8
7593 #define M_PRESET_REQUEST_VECTOR    0xffffU
7594 #define V_PRESET_REQUEST_VECTOR(x) ((x) << S_PRESET_REQUEST_VECTOR)
7595 #define G_PRESET_REQUEST_VECTOR(x) (((x) >> S_PRESET_REQUEST_VECTOR) & M_PRESET_REQUEST_VECTOR)
7596 
7597 #define S_PHASE23_2MS_TIMEOUT_DISABLE    5
7598 #define V_PHASE23_2MS_TIMEOUT_DISABLE(x) ((x) << S_PHASE23_2MS_TIMEOUT_DISABLE)
7599 #define F_PHASE23_2MS_TIMEOUT_DISABLE    V_PHASE23_2MS_TIMEOUT_DISABLE(1U)
7600 
7601 #define S_AFTER24MS    4
7602 #define V_AFTER24MS(x) ((x) << S_AFTER24MS)
7603 #define F_AFTER24MS    V_AFTER24MS(1U)
7604 
7605 #define S_FEEDBACK_MODE    0
7606 #define M_FEEDBACK_MODE    0xfU
7607 #define V_FEEDBACK_MODE(x) ((x) << S_FEEDBACK_MODE)
7608 #define G_FEEDBACK_MODE(x) (((x) >> S_FEEDBACK_MODE) & M_FEEDBACK_MODE)
7609 
7610 #define A_PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK 0x58ac
7611 
7612 #define S_WINAPERTURE_CPLUS1    14
7613 #define M_WINAPERTURE_CPLUS1    0xfU
7614 #define V_WINAPERTURE_CPLUS1(x) ((x) << S_WINAPERTURE_CPLUS1)
7615 #define G_WINAPERTURE_CPLUS1(x) (((x) >> S_WINAPERTURE_CPLUS1) & M_WINAPERTURE_CPLUS1)
7616 
7617 #define S_WINAPERTURE_CMINS1    10
7618 #define M_WINAPERTURE_CMINS1    0xfU
7619 #define V_WINAPERTURE_CMINS1(x) ((x) << S_WINAPERTURE_CMINS1)
7620 #define G_WINAPERTURE_CMINS1(x) (((x) >> S_WINAPERTURE_CMINS1) & M_WINAPERTURE_CMINS1)
7621 
7622 #define S_CONVERGENCE_WINDEPTH    5
7623 #define M_CONVERGENCE_WINDEPTH    0x1fU
7624 #define V_CONVERGENCE_WINDEPTH(x) ((x) << S_CONVERGENCE_WINDEPTH)
7625 #define G_CONVERGENCE_WINDEPTH(x) (((x) >> S_CONVERGENCE_WINDEPTH) & M_CONVERGENCE_WINDEPTH)
7626 
7627 #define S_EQMASTERPHASE_MINTIME    0
7628 #define M_EQMASTERPHASE_MINTIME    0x1fU
7629 #define V_EQMASTERPHASE_MINTIME(x) ((x) << S_EQMASTERPHASE_MINTIME)
7630 #define G_EQMASTERPHASE_MINTIME(x) (((x) >> S_EQMASTERPHASE_MINTIME) & M_EQMASTERPHASE_MINTIME)
7631 
7632 #define A_PCIE_CORE_PIPE_CONTROL 0x58b8
7633 
7634 #define S_PIPE_LOOPBACK_EN    0
7635 #define V_PIPE_LOOPBACK_EN(x) ((x) << S_PIPE_LOOPBACK_EN)
7636 #define F_PIPE_LOOPBACK_EN    V_PIPE_LOOPBACK_EN(1U)
7637 
7638 #define S_T6_PIPE_LOOPBACK_EN    31
7639 #define V_T6_PIPE_LOOPBACK_EN(x) ((x) << S_T6_PIPE_LOOPBACK_EN)
7640 #define F_T6_PIPE_LOOPBACK_EN    V_T6_PIPE_LOOPBACK_EN(1U)
7641 
7642 #define A_PCIE_CORE_DBI_RO_WE 0x58bc
7643 
7644 #define S_READONLY_WRITEEN    0
7645 #define V_READONLY_WRITEEN(x) ((x) << S_READONLY_WRITEEN)
7646 #define F_READONLY_WRITEEN    V_READONLY_WRITEEN(1U)
7647 
7648 #define A_PCIE_CORE_UTL_SYSTEM_BUS_CONTROL 0x5900
7649 
7650 #define S_SMTD    27
7651 #define V_SMTD(x) ((x) << S_SMTD)
7652 #define F_SMTD    V_SMTD(1U)
7653 
7654 #define S_SSTD    26
7655 #define V_SSTD(x) ((x) << S_SSTD)
7656 #define F_SSTD    V_SSTD(1U)
7657 
7658 #define S_SWD0    23
7659 #define V_SWD0(x) ((x) << S_SWD0)
7660 #define F_SWD0    V_SWD0(1U)
7661 
7662 #define S_SWD1    22
7663 #define V_SWD1(x) ((x) << S_SWD1)
7664 #define F_SWD1    V_SWD1(1U)
7665 
7666 #define S_SWD2    21
7667 #define V_SWD2(x) ((x) << S_SWD2)
7668 #define F_SWD2    V_SWD2(1U)
7669 
7670 #define S_SWD3    20
7671 #define V_SWD3(x) ((x) << S_SWD3)
7672 #define F_SWD3    V_SWD3(1U)
7673 
7674 #define S_SWD4    19
7675 #define V_SWD4(x) ((x) << S_SWD4)
7676 #define F_SWD4    V_SWD4(1U)
7677 
7678 #define S_SWD5    18
7679 #define V_SWD5(x) ((x) << S_SWD5)
7680 #define F_SWD5    V_SWD5(1U)
7681 
7682 #define S_SWD6    17
7683 #define V_SWD6(x) ((x) << S_SWD6)
7684 #define F_SWD6    V_SWD6(1U)
7685 
7686 #define S_SWD7    16
7687 #define V_SWD7(x) ((x) << S_SWD7)
7688 #define F_SWD7    V_SWD7(1U)
7689 
7690 #define S_SWD8    15
7691 #define V_SWD8(x) ((x) << S_SWD8)
7692 #define F_SWD8    V_SWD8(1U)
7693 
7694 #define S_SRD0    13
7695 #define V_SRD0(x) ((x) << S_SRD0)
7696 #define F_SRD0    V_SRD0(1U)
7697 
7698 #define S_SRD1    12
7699 #define V_SRD1(x) ((x) << S_SRD1)
7700 #define F_SRD1    V_SRD1(1U)
7701 
7702 #define S_SRD2    11
7703 #define V_SRD2(x) ((x) << S_SRD2)
7704 #define F_SRD2    V_SRD2(1U)
7705 
7706 #define S_SRD3    10
7707 #define V_SRD3(x) ((x) << S_SRD3)
7708 #define F_SRD3    V_SRD3(1U)
7709 
7710 #define S_SRD4    9
7711 #define V_SRD4(x) ((x) << S_SRD4)
7712 #define F_SRD4    V_SRD4(1U)
7713 
7714 #define S_SRD5    8
7715 #define V_SRD5(x) ((x) << S_SRD5)
7716 #define F_SRD5    V_SRD5(1U)
7717 
7718 #define S_SRD6    7
7719 #define V_SRD6(x) ((x) << S_SRD6)
7720 #define F_SRD6    V_SRD6(1U)
7721 
7722 #define S_SRD7    6
7723 #define V_SRD7(x) ((x) << S_SRD7)
7724 #define F_SRD7    V_SRD7(1U)
7725 
7726 #define S_SRD8    5
7727 #define V_SRD8(x) ((x) << S_SRD8)
7728 #define F_SRD8    V_SRD8(1U)
7729 
7730 #define S_CRRE    3
7731 #define V_CRRE(x) ((x) << S_CRRE)
7732 #define F_CRRE    V_CRRE(1U)
7733 
7734 #define S_CRMC    0
7735 #define M_CRMC    0x7U
7736 #define V_CRMC(x) ((x) << S_CRMC)
7737 #define G_CRMC(x) (((x) >> S_CRMC) & M_CRMC)
7738 
7739 #define A_PCIE_CORE_UTL_STATUS 0x5904
7740 
7741 #define S_USBP    31
7742 #define V_USBP(x) ((x) << S_USBP)
7743 #define F_USBP    V_USBP(1U)
7744 
7745 #define S_UPEP    30
7746 #define V_UPEP(x) ((x) << S_UPEP)
7747 #define F_UPEP    V_UPEP(1U)
7748 
7749 #define S_RCEP    29
7750 #define V_RCEP(x) ((x) << S_RCEP)
7751 #define F_RCEP    V_RCEP(1U)
7752 
7753 #define S_EPEP    28
7754 #define V_EPEP(x) ((x) << S_EPEP)
7755 #define F_EPEP    V_EPEP(1U)
7756 
7757 #define S_USBS    27
7758 #define V_USBS(x) ((x) << S_USBS)
7759 #define F_USBS    V_USBS(1U)
7760 
7761 #define S_UPES    26
7762 #define V_UPES(x) ((x) << S_UPES)
7763 #define F_UPES    V_UPES(1U)
7764 
7765 #define S_RCES    25
7766 #define V_RCES(x) ((x) << S_RCES)
7767 #define F_RCES    V_RCES(1U)
7768 
7769 #define S_EPES    24
7770 #define V_EPES(x) ((x) << S_EPES)
7771 #define F_EPES    V_EPES(1U)
7772 
7773 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
7774 
7775 #define S_RNPP    31
7776 #define V_RNPP(x) ((x) << S_RNPP)
7777 #define F_RNPP    V_RNPP(1U)
7778 
7779 #define S_RPCP    29
7780 #define V_RPCP(x) ((x) << S_RPCP)
7781 #define F_RPCP    V_RPCP(1U)
7782 
7783 #define S_RCIP    27
7784 #define V_RCIP(x) ((x) << S_RCIP)
7785 #define F_RCIP    V_RCIP(1U)
7786 
7787 #define S_RCCP    26
7788 #define V_RCCP(x) ((x) << S_RCCP)
7789 #define F_RCCP    V_RCCP(1U)
7790 
7791 #define S_RFTP    23
7792 #define V_RFTP(x) ((x) << S_RFTP)
7793 #define F_RFTP    V_RFTP(1U)
7794 
7795 #define S_PTRP    20
7796 #define V_PTRP(x) ((x) << S_PTRP)
7797 #define F_PTRP    V_PTRP(1U)
7798 
7799 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_ERROR_SEVERITY 0x590c
7800 
7801 #define S_RNPS    31
7802 #define V_RNPS(x) ((x) << S_RNPS)
7803 #define F_RNPS    V_RNPS(1U)
7804 
7805 #define S_RPCS    29
7806 #define V_RPCS(x) ((x) << S_RPCS)
7807 #define F_RPCS    V_RPCS(1U)
7808 
7809 #define S_RCIS    27
7810 #define V_RCIS(x) ((x) << S_RCIS)
7811 #define F_RCIS    V_RCIS(1U)
7812 
7813 #define S_RCCS    26
7814 #define V_RCCS(x) ((x) << S_RCCS)
7815 #define F_RCCS    V_RCCS(1U)
7816 
7817 #define S_RFTS    23
7818 #define V_RFTS(x) ((x) << S_RFTS)
7819 #define F_RFTS    V_RFTS(1U)
7820 
7821 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE 0x5910
7822 
7823 #define S_RNPI    31
7824 #define V_RNPI(x) ((x) << S_RNPI)
7825 #define F_RNPI    V_RNPI(1U)
7826 
7827 #define S_RPCI    29
7828 #define V_RPCI(x) ((x) << S_RPCI)
7829 #define F_RPCI    V_RPCI(1U)
7830 
7831 #define S_RCII    27
7832 #define V_RCII(x) ((x) << S_RCII)
7833 #define F_RCII    V_RCII(1U)
7834 
7835 #define S_RCCI    26
7836 #define V_RCCI(x) ((x) << S_RCCI)
7837 #define F_RCCI    V_RCCI(1U)
7838 
7839 #define S_RFTI    23
7840 #define V_RFTI(x) ((x) << S_RFTI)
7841 #define F_RFTI    V_RFTI(1U)
7842 
7843 #define A_PCIE_CORE_SYSTEM_BUS_BURST_SIZE_CONFIGURATION 0x5920
7844 
7845 #define S_SBRS    28
7846 #define M_SBRS    0x7U
7847 #define V_SBRS(x) ((x) << S_SBRS)
7848 #define G_SBRS(x) (((x) >> S_SBRS) & M_SBRS)
7849 
7850 #define S_OTWS    20
7851 #define M_OTWS    0x7U
7852 #define V_OTWS(x) ((x) << S_OTWS)
7853 #define G_OTWS(x) (((x) >> S_OTWS) & M_OTWS)
7854 
7855 #define A_PCIE_CORE_REVISION_ID 0x5924
7856 
7857 #define S_RVID    20
7858 #define M_RVID    0xfffU
7859 #define V_RVID(x) ((x) << S_RVID)
7860 #define G_RVID(x) (((x) >> S_RVID) & M_RVID)
7861 
7862 #define S_BRVN    12
7863 #define M_BRVN    0xffU
7864 #define V_BRVN(x) ((x) << S_BRVN)
7865 #define G_BRVN(x) (((x) >> S_BRVN) & M_BRVN)
7866 
7867 #define A_PCIE_T5_DMA_CFG 0x5940
7868 
7869 #define S_T5_DMA_MAXREQCNT    20
7870 #define M_T5_DMA_MAXREQCNT    0xffU
7871 #define V_T5_DMA_MAXREQCNT(x) ((x) << S_T5_DMA_MAXREQCNT)
7872 #define G_T5_DMA_MAXREQCNT(x) (((x) >> S_T5_DMA_MAXREQCNT) & M_T5_DMA_MAXREQCNT)
7873 
7874 #define S_T5_DMA_MAXRDREQSIZE    17
7875 #define M_T5_DMA_MAXRDREQSIZE    0x7U
7876 #define V_T5_DMA_MAXRDREQSIZE(x) ((x) << S_T5_DMA_MAXRDREQSIZE)
7877 #define G_T5_DMA_MAXRDREQSIZE(x) (((x) >> S_T5_DMA_MAXRDREQSIZE) & M_T5_DMA_MAXRDREQSIZE)
7878 
7879 #define S_T5_DMA_MAXRSPCNT    8
7880 #define M_T5_DMA_MAXRSPCNT    0x1ffU
7881 #define V_T5_DMA_MAXRSPCNT(x) ((x) << S_T5_DMA_MAXRSPCNT)
7882 #define G_T5_DMA_MAXRSPCNT(x) (((x) >> S_T5_DMA_MAXRSPCNT) & M_T5_DMA_MAXRSPCNT)
7883 
7884 #define S_SEQCHKDIS    7
7885 #define V_SEQCHKDIS(x) ((x) << S_SEQCHKDIS)
7886 #define F_SEQCHKDIS    V_SEQCHKDIS(1U)
7887 
7888 #define S_MINTAG    0
7889 #define M_MINTAG    0x7fU
7890 #define V_MINTAG(x) ((x) << S_MINTAG)
7891 #define G_MINTAG(x) (((x) >> S_MINTAG) & M_MINTAG)
7892 
7893 #define S_T6_T5_DMA_MAXREQCNT    20
7894 #define M_T6_T5_DMA_MAXREQCNT    0x7fU
7895 #define V_T6_T5_DMA_MAXREQCNT(x) ((x) << S_T6_T5_DMA_MAXREQCNT)
7896 #define G_T6_T5_DMA_MAXREQCNT(x) (((x) >> S_T6_T5_DMA_MAXREQCNT) & M_T6_T5_DMA_MAXREQCNT)
7897 
7898 #define S_T6_T5_DMA_MAXRSPCNT    9
7899 #define M_T6_T5_DMA_MAXRSPCNT    0xffU
7900 #define V_T6_T5_DMA_MAXRSPCNT(x) ((x) << S_T6_T5_DMA_MAXRSPCNT)
7901 #define G_T6_T5_DMA_MAXRSPCNT(x) (((x) >> S_T6_T5_DMA_MAXRSPCNT) & M_T6_T5_DMA_MAXRSPCNT)
7902 
7903 #define S_T6_SEQCHKDIS    8
7904 #define V_T6_SEQCHKDIS(x) ((x) << S_T6_SEQCHKDIS)
7905 #define F_T6_SEQCHKDIS    V_T6_SEQCHKDIS(1U)
7906 
7907 #define S_T6_MINTAG    0
7908 #define M_T6_MINTAG    0xffU
7909 #define V_T6_MINTAG(x) ((x) << S_T6_MINTAG)
7910 #define G_T6_MINTAG(x) (((x) >> S_T6_MINTAG) & M_T6_MINTAG)
7911 
7912 #define A_PCIE_T5_DMA_STAT 0x5944
7913 
7914 #define S_DMA_RESPCNT    20
7915 #define M_DMA_RESPCNT    0xfffU
7916 #define V_DMA_RESPCNT(x) ((x) << S_DMA_RESPCNT)
7917 #define G_DMA_RESPCNT(x) (((x) >> S_DMA_RESPCNT) & M_DMA_RESPCNT)
7918 
7919 #define S_DMA_RDREQCNT    12
7920 #define M_DMA_RDREQCNT    0xffU
7921 #define V_DMA_RDREQCNT(x) ((x) << S_DMA_RDREQCNT)
7922 #define G_DMA_RDREQCNT(x) (((x) >> S_DMA_RDREQCNT) & M_DMA_RDREQCNT)
7923 
7924 #define S_DMA_WRREQCNT    0
7925 #define M_DMA_WRREQCNT    0x7ffU
7926 #define V_DMA_WRREQCNT(x) ((x) << S_DMA_WRREQCNT)
7927 #define G_DMA_WRREQCNT(x) (((x) >> S_DMA_WRREQCNT) & M_DMA_WRREQCNT)
7928 
7929 #define S_T6_DMA_RESPCNT    20
7930 #define M_T6_DMA_RESPCNT    0x3ffU
7931 #define V_T6_DMA_RESPCNT(x) ((x) << S_T6_DMA_RESPCNT)
7932 #define G_T6_DMA_RESPCNT(x) (((x) >> S_T6_DMA_RESPCNT) & M_T6_DMA_RESPCNT)
7933 
7934 #define S_T6_DMA_RDREQCNT    12
7935 #define M_T6_DMA_RDREQCNT    0x3fU
7936 #define V_T6_DMA_RDREQCNT(x) ((x) << S_T6_DMA_RDREQCNT)
7937 #define G_T6_DMA_RDREQCNT(x) (((x) >> S_T6_DMA_RDREQCNT) & M_T6_DMA_RDREQCNT)
7938 
7939 #define S_T6_DMA_WRREQCNT    0
7940 #define M_T6_DMA_WRREQCNT    0x1ffU
7941 #define V_T6_DMA_WRREQCNT(x) ((x) << S_T6_DMA_WRREQCNT)
7942 #define G_T6_DMA_WRREQCNT(x) (((x) >> S_T6_DMA_WRREQCNT) & M_T6_DMA_WRREQCNT)
7943 
7944 #define A_PCIE_T5_DMA_STAT2 0x5948
7945 
7946 #define S_COOKIECNT    24
7947 #define M_COOKIECNT    0xfU
7948 #define V_COOKIECNT(x) ((x) << S_COOKIECNT)
7949 #define G_COOKIECNT(x) (((x) >> S_COOKIECNT) & M_COOKIECNT)
7950 
7951 #define S_RDSEQNUMUPDCNT    20
7952 #define M_RDSEQNUMUPDCNT    0xfU
7953 #define V_RDSEQNUMUPDCNT(x) ((x) << S_RDSEQNUMUPDCNT)
7954 #define G_RDSEQNUMUPDCNT(x) (((x) >> S_RDSEQNUMUPDCNT) & M_RDSEQNUMUPDCNT)
7955 
7956 #define S_SIREQCNT    16
7957 #define M_SIREQCNT    0xfU
7958 #define V_SIREQCNT(x) ((x) << S_SIREQCNT)
7959 #define G_SIREQCNT(x) (((x) >> S_SIREQCNT) & M_SIREQCNT)
7960 
7961 #define S_WREOPMATCHSOP    12
7962 #define V_WREOPMATCHSOP(x) ((x) << S_WREOPMATCHSOP)
7963 #define F_WREOPMATCHSOP    V_WREOPMATCHSOP(1U)
7964 
7965 #define S_WRSOPCNT    8
7966 #define M_WRSOPCNT    0xfU
7967 #define V_WRSOPCNT(x) ((x) << S_WRSOPCNT)
7968 #define G_WRSOPCNT(x) (((x) >> S_WRSOPCNT) & M_WRSOPCNT)
7969 
7970 #define S_RDSOPCNT    0
7971 #define M_RDSOPCNT    0xffU
7972 #define V_RDSOPCNT(x) ((x) << S_RDSOPCNT)
7973 #define G_RDSOPCNT(x) (((x) >> S_RDSOPCNT) & M_RDSOPCNT)
7974 
7975 #define S_DMA_COOKIECNT    24
7976 #define M_DMA_COOKIECNT    0xfU
7977 #define V_DMA_COOKIECNT(x) ((x) << S_DMA_COOKIECNT)
7978 #define G_DMA_COOKIECNT(x) (((x) >> S_DMA_COOKIECNT) & M_DMA_COOKIECNT)
7979 
7980 #define S_DMA_RDSEQNUMUPDCNT    20
7981 #define M_DMA_RDSEQNUMUPDCNT    0xfU
7982 #define V_DMA_RDSEQNUMUPDCNT(x) ((x) << S_DMA_RDSEQNUMUPDCNT)
7983 #define G_DMA_RDSEQNUMUPDCNT(x) (((x) >> S_DMA_RDSEQNUMUPDCNT) & M_DMA_RDSEQNUMUPDCNT)
7984 
7985 #define S_DMA_SIREQCNT    16
7986 #define M_DMA_SIREQCNT    0xfU
7987 #define V_DMA_SIREQCNT(x) ((x) << S_DMA_SIREQCNT)
7988 #define G_DMA_SIREQCNT(x) (((x) >> S_DMA_SIREQCNT) & M_DMA_SIREQCNT)
7989 
7990 #define S_DMA_WREOPMATCHSOP    12
7991 #define V_DMA_WREOPMATCHSOP(x) ((x) << S_DMA_WREOPMATCHSOP)
7992 #define F_DMA_WREOPMATCHSOP    V_DMA_WREOPMATCHSOP(1U)
7993 
7994 #define S_DMA_WRSOPCNT    8
7995 #define M_DMA_WRSOPCNT    0xfU
7996 #define V_DMA_WRSOPCNT(x) ((x) << S_DMA_WRSOPCNT)
7997 #define G_DMA_WRSOPCNT(x) (((x) >> S_DMA_WRSOPCNT) & M_DMA_WRSOPCNT)
7998 
7999 #define S_DMA_RDSOPCNT    0
8000 #define M_DMA_RDSOPCNT    0xffU
8001 #define V_DMA_RDSOPCNT(x) ((x) << S_DMA_RDSOPCNT)
8002 #define G_DMA_RDSOPCNT(x) (((x) >> S_DMA_RDSOPCNT) & M_DMA_RDSOPCNT)
8003 
8004 #define A_PCIE_T5_DMA_STAT3 0x594c
8005 
8006 #define S_ATMREQSOPCNT    24
8007 #define M_ATMREQSOPCNT    0xffU
8008 #define V_ATMREQSOPCNT(x) ((x) << S_ATMREQSOPCNT)
8009 #define G_ATMREQSOPCNT(x) (((x) >> S_ATMREQSOPCNT) & M_ATMREQSOPCNT)
8010 
8011 #define S_ATMEOPMATCHSOP    17
8012 #define V_ATMEOPMATCHSOP(x) ((x) << S_ATMEOPMATCHSOP)
8013 #define F_ATMEOPMATCHSOP    V_ATMEOPMATCHSOP(1U)
8014 
8015 #define S_RSPEOPMATCHSOP    16
8016 #define V_RSPEOPMATCHSOP(x) ((x) << S_RSPEOPMATCHSOP)
8017 #define F_RSPEOPMATCHSOP    V_RSPEOPMATCHSOP(1U)
8018 
8019 #define S_RSPERRCNT    8
8020 #define M_RSPERRCNT    0xffU
8021 #define V_RSPERRCNT(x) ((x) << S_RSPERRCNT)
8022 #define G_RSPERRCNT(x) (((x) >> S_RSPERRCNT) & M_RSPERRCNT)
8023 
8024 #define S_RSPSOPCNT    0
8025 #define M_RSPSOPCNT    0xffU
8026 #define V_RSPSOPCNT(x) ((x) << S_RSPSOPCNT)
8027 #define G_RSPSOPCNT(x) (((x) >> S_RSPSOPCNT) & M_RSPSOPCNT)
8028 
8029 #define S_DMA_ATMREQSOPCNT    24
8030 #define M_DMA_ATMREQSOPCNT    0xffU
8031 #define V_DMA_ATMREQSOPCNT(x) ((x) << S_DMA_ATMREQSOPCNT)
8032 #define G_DMA_ATMREQSOPCNT(x) (((x) >> S_DMA_ATMREQSOPCNT) & M_DMA_ATMREQSOPCNT)
8033 
8034 #define S_DMA_ATMEOPMATCHSOP    17
8035 #define V_DMA_ATMEOPMATCHSOP(x) ((x) << S_DMA_ATMEOPMATCHSOP)
8036 #define F_DMA_ATMEOPMATCHSOP    V_DMA_ATMEOPMATCHSOP(1U)
8037 
8038 #define S_DMA_RSPEOPMATCHSOP    16
8039 #define V_DMA_RSPEOPMATCHSOP(x) ((x) << S_DMA_RSPEOPMATCHSOP)
8040 #define F_DMA_RSPEOPMATCHSOP    V_DMA_RSPEOPMATCHSOP(1U)
8041 
8042 #define S_DMA_RSPERRCNT    8
8043 #define M_DMA_RSPERRCNT    0xffU
8044 #define V_DMA_RSPERRCNT(x) ((x) << S_DMA_RSPERRCNT)
8045 #define G_DMA_RSPERRCNT(x) (((x) >> S_DMA_RSPERRCNT) & M_DMA_RSPERRCNT)
8046 
8047 #define S_DMA_RSPSOPCNT    0
8048 #define M_DMA_RSPSOPCNT    0xffU
8049 #define V_DMA_RSPSOPCNT(x) ((x) << S_DMA_RSPSOPCNT)
8050 #define G_DMA_RSPSOPCNT(x) (((x) >> S_DMA_RSPSOPCNT) & M_DMA_RSPSOPCNT)
8051 
8052 #define A_PCIE_CORE_OUTBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5960
8053 
8054 #define S_OP0H    24
8055 #define M_OP0H    0xfU
8056 #define V_OP0H(x) ((x) << S_OP0H)
8057 #define G_OP0H(x) (((x) >> S_OP0H) & M_OP0H)
8058 
8059 #define S_OP1H    16
8060 #define M_OP1H    0xfU
8061 #define V_OP1H(x) ((x) << S_OP1H)
8062 #define G_OP1H(x) (((x) >> S_OP1H) & M_OP1H)
8063 
8064 #define S_OP2H    8
8065 #define M_OP2H    0xfU
8066 #define V_OP2H(x) ((x) << S_OP2H)
8067 #define G_OP2H(x) (((x) >> S_OP2H) & M_OP2H)
8068 
8069 #define S_OP3H    0
8070 #define M_OP3H    0xfU
8071 #define V_OP3H(x) ((x) << S_OP3H)
8072 #define G_OP3H(x) (((x) >> S_OP3H) & M_OP3H)
8073 
8074 #define A_PCIE_CORE_OUTBOUND_POSTED_DATA_BUFFER_ALLOCATION 0x5968
8075 
8076 #define S_OP0D    24
8077 #define M_OP0D    0x7fU
8078 #define V_OP0D(x) ((x) << S_OP0D)
8079 #define G_OP0D(x) (((x) >> S_OP0D) & M_OP0D)
8080 
8081 #define S_OP1D    16
8082 #define M_OP1D    0x7fU
8083 #define V_OP1D(x) ((x) << S_OP1D)
8084 #define G_OP1D(x) (((x) >> S_OP1D) & M_OP1D)
8085 
8086 #define S_OP2D    8
8087 #define M_OP2D    0x7fU
8088 #define V_OP2D(x) ((x) << S_OP2D)
8089 #define G_OP2D(x) (((x) >> S_OP2D) & M_OP2D)
8090 
8091 #define S_OP3D    0
8092 #define M_OP3D    0x7fU
8093 #define V_OP3D(x) ((x) << S_OP3D)
8094 #define G_OP3D(x) (((x) >> S_OP3D) & M_OP3D)
8095 
8096 #define A_PCIE_CORE_INBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5970
8097 
8098 #define S_IP0H    24
8099 #define M_IP0H    0x3fU
8100 #define V_IP0H(x) ((x) << S_IP0H)
8101 #define G_IP0H(x) (((x) >> S_IP0H) & M_IP0H)
8102 
8103 #define S_IP1H    16
8104 #define M_IP1H    0x3fU
8105 #define V_IP1H(x) ((x) << S_IP1H)
8106 #define G_IP1H(x) (((x) >> S_IP1H) & M_IP1H)
8107 
8108 #define S_IP2H    8
8109 #define M_IP2H    0x3fU
8110 #define V_IP2H(x) ((x) << S_IP2H)
8111 #define G_IP2H(x) (((x) >> S_IP2H) & M_IP2H)
8112 
8113 #define S_IP3H    0
8114 #define M_IP3H    0x3fU
8115 #define V_IP3H(x) ((x) << S_IP3H)
8116 #define G_IP3H(x) (((x) >> S_IP3H) & M_IP3H)
8117 
8118 #define A_PCIE_CORE_INBOUND_POSTED_DATA_BUFFER_ALLOCATION 0x5978
8119 
8120 #define S_IP0D    24
8121 #define M_IP0D    0xffU
8122 #define V_IP0D(x) ((x) << S_IP0D)
8123 #define G_IP0D(x) (((x) >> S_IP0D) & M_IP0D)
8124 
8125 #define S_IP1D    16
8126 #define M_IP1D    0xffU
8127 #define V_IP1D(x) ((x) << S_IP1D)
8128 #define G_IP1D(x) (((x) >> S_IP1D) & M_IP1D)
8129 
8130 #define S_IP2D    8
8131 #define M_IP2D    0xffU
8132 #define V_IP2D(x) ((x) << S_IP2D)
8133 #define G_IP2D(x) (((x) >> S_IP2D) & M_IP2D)
8134 
8135 #define S_IP3D    0
8136 #define M_IP3D    0xffU
8137 #define V_IP3D(x) ((x) << S_IP3D)
8138 #define G_IP3D(x) (((x) >> S_IP3D) & M_IP3D)
8139 
8140 #define A_PCIE_CORE_OUTBOUND_NON_POSTED_BUFFER_ALLOCATION 0x5980
8141 
8142 #define S_ON0H    24
8143 #define M_ON0H    0xfU
8144 #define V_ON0H(x) ((x) << S_ON0H)
8145 #define G_ON0H(x) (((x) >> S_ON0H) & M_ON0H)
8146 
8147 #define S_ON1H    16
8148 #define M_ON1H    0xfU
8149 #define V_ON1H(x) ((x) << S_ON1H)
8150 #define G_ON1H(x) (((x) >> S_ON1H) & M_ON1H)
8151 
8152 #define S_ON2H    8
8153 #define M_ON2H    0xfU
8154 #define V_ON2H(x) ((x) << S_ON2H)
8155 #define G_ON2H(x) (((x) >> S_ON2H) & M_ON2H)
8156 
8157 #define S_ON3H    0
8158 #define M_ON3H    0xfU
8159 #define V_ON3H(x) ((x) << S_ON3H)
8160 #define G_ON3H(x) (((x) >> S_ON3H) & M_ON3H)
8161 
8162 #define A_PCIE_T5_CMD_CFG 0x5980
8163 
8164 #define S_T5_CMD_MAXRDREQSIZE    17
8165 #define M_T5_CMD_MAXRDREQSIZE    0x7U
8166 #define V_T5_CMD_MAXRDREQSIZE(x) ((x) << S_T5_CMD_MAXRDREQSIZE)
8167 #define G_T5_CMD_MAXRDREQSIZE(x) (((x) >> S_T5_CMD_MAXRDREQSIZE) & M_T5_CMD_MAXRDREQSIZE)
8168 
8169 #define S_T5_CMD_MAXRSPCNT    8
8170 #define M_T5_CMD_MAXRSPCNT    0xffU
8171 #define V_T5_CMD_MAXRSPCNT(x) ((x) << S_T5_CMD_MAXRSPCNT)
8172 #define G_T5_CMD_MAXRSPCNT(x) (((x) >> S_T5_CMD_MAXRSPCNT) & M_T5_CMD_MAXRSPCNT)
8173 
8174 #define S_USECMDPOOL    7
8175 #define V_USECMDPOOL(x) ((x) << S_USECMDPOOL)
8176 #define F_USECMDPOOL    V_USECMDPOOL(1U)
8177 
8178 #define S_T6_T5_CMD_MAXRSPCNT    9
8179 #define M_T6_T5_CMD_MAXRSPCNT    0x3fU
8180 #define V_T6_T5_CMD_MAXRSPCNT(x) ((x) << S_T6_T5_CMD_MAXRSPCNT)
8181 #define G_T6_T5_CMD_MAXRSPCNT(x) (((x) >> S_T6_T5_CMD_MAXRSPCNT) & M_T6_T5_CMD_MAXRSPCNT)
8182 
8183 #define S_T6_USECMDPOOL    8
8184 #define V_T6_USECMDPOOL(x) ((x) << S_T6_USECMDPOOL)
8185 #define F_T6_USECMDPOOL    V_T6_USECMDPOOL(1U)
8186 
8187 #define A_PCIE_T5_CMD_STAT 0x5984
8188 
8189 #define S_T5_STAT_RSPCNT    20
8190 #define M_T5_STAT_RSPCNT    0x7ffU
8191 #define V_T5_STAT_RSPCNT(x) ((x) << S_T5_STAT_RSPCNT)
8192 #define G_T5_STAT_RSPCNT(x) (((x) >> S_T5_STAT_RSPCNT) & M_T5_STAT_RSPCNT)
8193 
8194 #define S_RDREQCNT    12
8195 #define M_RDREQCNT    0x1fU
8196 #define V_RDREQCNT(x) ((x) << S_RDREQCNT)
8197 #define G_RDREQCNT(x) (((x) >> S_RDREQCNT) & M_RDREQCNT)
8198 
8199 #define S_T6_T5_STAT_RSPCNT    20
8200 #define M_T6_T5_STAT_RSPCNT    0xffU
8201 #define V_T6_T5_STAT_RSPCNT(x) ((x) << S_T6_T5_STAT_RSPCNT)
8202 #define G_T6_T5_STAT_RSPCNT(x) (((x) >> S_T6_T5_STAT_RSPCNT) & M_T6_T5_STAT_RSPCNT)
8203 
8204 #define S_T6_RDREQCNT    12
8205 #define M_T6_RDREQCNT    0xfU
8206 #define V_T6_RDREQCNT(x) ((x) << S_T6_RDREQCNT)
8207 #define G_T6_RDREQCNT(x) (((x) >> S_T6_RDREQCNT) & M_T6_RDREQCNT)
8208 
8209 #define A_PCIE_CORE_INBOUND_NON_POSTED_REQUESTS_BUFFER_ALLOCATION 0x5988
8210 
8211 #define S_IN0H    24
8212 #define M_IN0H    0x3fU
8213 #define V_IN0H(x) ((x) << S_IN0H)
8214 #define G_IN0H(x) (((x) >> S_IN0H) & M_IN0H)
8215 
8216 #define S_IN1H    16
8217 #define M_IN1H    0x3fU
8218 #define V_IN1H(x) ((x) << S_IN1H)
8219 #define G_IN1H(x) (((x) >> S_IN1H) & M_IN1H)
8220 
8221 #define S_IN2H    8
8222 #define M_IN2H    0x3fU
8223 #define V_IN2H(x) ((x) << S_IN2H)
8224 #define G_IN2H(x) (((x) >> S_IN2H) & M_IN2H)
8225 
8226 #define S_IN3H    0
8227 #define M_IN3H    0x3fU
8228 #define V_IN3H(x) ((x) << S_IN3H)
8229 #define G_IN3H(x) (((x) >> S_IN3H) & M_IN3H)
8230 
8231 #define A_PCIE_T5_CMD_STAT2 0x5988
8232 #define A_PCIE_T5_CMD_STAT3 0x598c
8233 
8234 #define S_CMD_RSPEOPMATCHSOP    16
8235 #define V_CMD_RSPEOPMATCHSOP(x) ((x) << S_CMD_RSPEOPMATCHSOP)
8236 #define F_CMD_RSPEOPMATCHSOP    V_CMD_RSPEOPMATCHSOP(1U)
8237 
8238 #define S_CMD_RSPERRCNT    8
8239 #define M_CMD_RSPERRCNT    0xffU
8240 #define V_CMD_RSPERRCNT(x) ((x) << S_CMD_RSPERRCNT)
8241 #define G_CMD_RSPERRCNT(x) (((x) >> S_CMD_RSPERRCNT) & M_CMD_RSPERRCNT)
8242 
8243 #define S_CMD_RSPSOPCNT    0
8244 #define M_CMD_RSPSOPCNT    0xffU
8245 #define V_CMD_RSPSOPCNT(x) ((x) << S_CMD_RSPSOPCNT)
8246 #define G_CMD_RSPSOPCNT(x) (((x) >> S_CMD_RSPSOPCNT) & M_CMD_RSPSOPCNT)
8247 
8248 #define A_PCIE_CORE_PCI_EXPRESS_TAGS_ALLOCATION 0x5990
8249 
8250 #define S_OC0T    24
8251 #define M_OC0T    0xffU
8252 #define V_OC0T(x) ((x) << S_OC0T)
8253 #define G_OC0T(x) (((x) >> S_OC0T) & M_OC0T)
8254 
8255 #define S_OC1T    16
8256 #define M_OC1T    0xffU
8257 #define V_OC1T(x) ((x) << S_OC1T)
8258 #define G_OC1T(x) (((x) >> S_OC1T) & M_OC1T)
8259 
8260 #define S_OC2T    8
8261 #define M_OC2T    0xffU
8262 #define V_OC2T(x) ((x) << S_OC2T)
8263 #define G_OC2T(x) (((x) >> S_OC2T) & M_OC2T)
8264 
8265 #define S_OC3T    0
8266 #define M_OC3T    0xffU
8267 #define V_OC3T(x) ((x) << S_OC3T)
8268 #define G_OC3T(x) (((x) >> S_OC3T) & M_OC3T)
8269 
8270 #define A_PCIE_CORE_GBIF_READ_TAGS_ALLOCATION 0x5998
8271 
8272 #define S_IC0T    24
8273 #define M_IC0T    0x3fU
8274 #define V_IC0T(x) ((x) << S_IC0T)
8275 #define G_IC0T(x) (((x) >> S_IC0T) & M_IC0T)
8276 
8277 #define S_IC1T    16
8278 #define M_IC1T    0x3fU
8279 #define V_IC1T(x) ((x) << S_IC1T)
8280 #define G_IC1T(x) (((x) >> S_IC1T) & M_IC1T)
8281 
8282 #define S_IC2T    8
8283 #define M_IC2T    0x3fU
8284 #define V_IC2T(x) ((x) << S_IC2T)
8285 #define G_IC2T(x) (((x) >> S_IC2T) & M_IC2T)
8286 
8287 #define S_IC3T    0
8288 #define M_IC3T    0x3fU
8289 #define V_IC3T(x) ((x) << S_IC3T)
8290 #define G_IC3T(x) (((x) >> S_IC3T) & M_IC3T)
8291 
8292 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_CONTROL 0x59a0
8293 
8294 #define S_VRB0    31
8295 #define V_VRB0(x) ((x) << S_VRB0)
8296 #define F_VRB0    V_VRB0(1U)
8297 
8298 #define S_VRB1    30
8299 #define V_VRB1(x) ((x) << S_VRB1)
8300 #define F_VRB1    V_VRB1(1U)
8301 
8302 #define S_VRB2    29
8303 #define V_VRB2(x) ((x) << S_VRB2)
8304 #define F_VRB2    V_VRB2(1U)
8305 
8306 #define S_VRB3    28
8307 #define V_VRB3(x) ((x) << S_VRB3)
8308 #define F_VRB3    V_VRB3(1U)
8309 
8310 #define S_PSFE    26
8311 #define V_PSFE(x) ((x) << S_PSFE)
8312 #define F_PSFE    V_PSFE(1U)
8313 
8314 #define S_RVDE    25
8315 #define V_RVDE(x) ((x) << S_RVDE)
8316 #define F_RVDE    V_RVDE(1U)
8317 
8318 #define S_TXE0    23
8319 #define V_TXE0(x) ((x) << S_TXE0)
8320 #define F_TXE0    V_TXE0(1U)
8321 
8322 #define S_TXE1    22
8323 #define V_TXE1(x) ((x) << S_TXE1)
8324 #define F_TXE1    V_TXE1(1U)
8325 
8326 #define S_TXE2    21
8327 #define V_TXE2(x) ((x) << S_TXE2)
8328 #define F_TXE2    V_TXE2(1U)
8329 
8330 #define S_TXE3    20
8331 #define V_TXE3(x) ((x) << S_TXE3)
8332 #define F_TXE3    V_TXE3(1U)
8333 
8334 #define S_RPAM    13
8335 #define V_RPAM(x) ((x) << S_RPAM)
8336 #define F_RPAM    V_RPAM(1U)
8337 
8338 #define S_RTOS    4
8339 #define M_RTOS    0xfU
8340 #define V_RTOS(x) ((x) << S_RTOS)
8341 #define G_RTOS(x) (((x) >> S_RTOS) & M_RTOS)
8342 
8343 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
8344 
8345 #define S_TPCP    30
8346 #define V_TPCP(x) ((x) << S_TPCP)
8347 #define F_TPCP    V_TPCP(1U)
8348 
8349 #define S_TNPP    29
8350 #define V_TNPP(x) ((x) << S_TNPP)
8351 #define F_TNPP    V_TNPP(1U)
8352 
8353 #define S_TFTP    28
8354 #define V_TFTP(x) ((x) << S_TFTP)
8355 #define F_TFTP    V_TFTP(1U)
8356 
8357 #define S_TCAP    27
8358 #define V_TCAP(x) ((x) << S_TCAP)
8359 #define F_TCAP    V_TCAP(1U)
8360 
8361 #define S_TCIP    26
8362 #define V_TCIP(x) ((x) << S_TCIP)
8363 #define F_TCIP    V_TCIP(1U)
8364 
8365 #define S_RCAP    25
8366 #define V_RCAP(x) ((x) << S_RCAP)
8367 #define F_RCAP    V_RCAP(1U)
8368 
8369 #define S_PLUP    23
8370 #define V_PLUP(x) ((x) << S_PLUP)
8371 #define F_PLUP    V_PLUP(1U)
8372 
8373 #define S_PLDN    22
8374 #define V_PLDN(x) ((x) << S_PLDN)
8375 #define F_PLDN    V_PLDN(1U)
8376 
8377 #define S_OTDD    21
8378 #define V_OTDD(x) ((x) << S_OTDD)
8379 #define F_OTDD    V_OTDD(1U)
8380 
8381 #define S_GTRP    20
8382 #define V_GTRP(x) ((x) << S_GTRP)
8383 #define F_GTRP    V_GTRP(1U)
8384 
8385 #define S_RDPE    18
8386 #define V_RDPE(x) ((x) << S_RDPE)
8387 #define F_RDPE    V_RDPE(1U)
8388 
8389 #define S_TDCE    17
8390 #define V_TDCE(x) ((x) << S_TDCE)
8391 #define F_TDCE    V_TDCE(1U)
8392 
8393 #define S_TDUE    16
8394 #define V_TDUE(x) ((x) << S_TDUE)
8395 #define F_TDUE    V_TDUE(1U)
8396 
8397 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_ERROR_SEVERITY 0x59a8
8398 
8399 #define S_TPCS    30
8400 #define V_TPCS(x) ((x) << S_TPCS)
8401 #define F_TPCS    V_TPCS(1U)
8402 
8403 #define S_TNPS    29
8404 #define V_TNPS(x) ((x) << S_TNPS)
8405 #define F_TNPS    V_TNPS(1U)
8406 
8407 #define S_TFTS    28
8408 #define V_TFTS(x) ((x) << S_TFTS)
8409 #define F_TFTS    V_TFTS(1U)
8410 
8411 #define S_TCAS    27
8412 #define V_TCAS(x) ((x) << S_TCAS)
8413 #define F_TCAS    V_TCAS(1U)
8414 
8415 #define S_TCIS    26
8416 #define V_TCIS(x) ((x) << S_TCIS)
8417 #define F_TCIS    V_TCIS(1U)
8418 
8419 #define S_RCAS    25
8420 #define V_RCAS(x) ((x) << S_RCAS)
8421 #define F_RCAS    V_RCAS(1U)
8422 
8423 #define S_PLUS    23
8424 #define V_PLUS(x) ((x) << S_PLUS)
8425 #define F_PLUS    V_PLUS(1U)
8426 
8427 #define S_PLDS    22
8428 #define V_PLDS(x) ((x) << S_PLDS)
8429 #define F_PLDS    V_PLDS(1U)
8430 
8431 #define S_OTDS    21
8432 #define V_OTDS(x) ((x) << S_OTDS)
8433 #define F_OTDS    V_OTDS(1U)
8434 
8435 #define S_RDPS    18
8436 #define V_RDPS(x) ((x) << S_RDPS)
8437 #define F_RDPS    V_RDPS(1U)
8438 
8439 #define S_TDCS    17
8440 #define V_TDCS(x) ((x) << S_TDCS)
8441 #define F_TDCS    V_TDCS(1U)
8442 
8443 #define S_TDUS    16
8444 #define V_TDUS(x) ((x) << S_TDUS)
8445 #define F_TDUS    V_TDUS(1U)
8446 
8447 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE 0x59ac
8448 
8449 #define S_TPCI    30
8450 #define V_TPCI(x) ((x) << S_TPCI)
8451 #define F_TPCI    V_TPCI(1U)
8452 
8453 #define S_TNPI    29
8454 #define V_TNPI(x) ((x) << S_TNPI)
8455 #define F_TNPI    V_TNPI(1U)
8456 
8457 #define S_TFTI    28
8458 #define V_TFTI(x) ((x) << S_TFTI)
8459 #define F_TFTI    V_TFTI(1U)
8460 
8461 #define S_TCAI    27
8462 #define V_TCAI(x) ((x) << S_TCAI)
8463 #define F_TCAI    V_TCAI(1U)
8464 
8465 #define S_TCII    26
8466 #define V_TCII(x) ((x) << S_TCII)
8467 #define F_TCII    V_TCII(1U)
8468 
8469 #define S_RCAI    25
8470 #define V_RCAI(x) ((x) << S_RCAI)
8471 #define F_RCAI    V_RCAI(1U)
8472 
8473 #define S_PLUI    23
8474 #define V_PLUI(x) ((x) << S_PLUI)
8475 #define F_PLUI    V_PLUI(1U)
8476 
8477 #define S_PLDI    22
8478 #define V_PLDI(x) ((x) << S_PLDI)
8479 #define F_PLDI    V_PLDI(1U)
8480 
8481 #define S_OTDI    21
8482 #define V_OTDI(x) ((x) << S_OTDI)
8483 #define F_OTDI    V_OTDI(1U)
8484 
8485 #define A_PCIE_CORE_ROOT_COMPLEX_STATUS 0x59b0
8486 
8487 #define S_RLCE    31
8488 #define V_RLCE(x) ((x) << S_RLCE)
8489 #define F_RLCE    V_RLCE(1U)
8490 
8491 #define S_RLNE    30
8492 #define V_RLNE(x) ((x) << S_RLNE)
8493 #define F_RLNE    V_RLNE(1U)
8494 
8495 #define S_RLFE    29
8496 #define V_RLFE(x) ((x) << S_RLFE)
8497 #define F_RLFE    V_RLFE(1U)
8498 
8499 #define S_RCPE    25
8500 #define V_RCPE(x) ((x) << S_RCPE)
8501 #define F_RCPE    V_RCPE(1U)
8502 
8503 #define S_RCTO    24
8504 #define V_RCTO(x) ((x) << S_RCTO)
8505 #define F_RCTO    V_RCTO(1U)
8506 
8507 #define S_PINA    23
8508 #define V_PINA(x) ((x) << S_PINA)
8509 #define F_PINA    V_PINA(1U)
8510 
8511 #define S_PINB    22
8512 #define V_PINB(x) ((x) << S_PINB)
8513 #define F_PINB    V_PINB(1U)
8514 
8515 #define S_PINC    21
8516 #define V_PINC(x) ((x) << S_PINC)
8517 #define F_PINC    V_PINC(1U)
8518 
8519 #define S_PIND    20
8520 #define V_PIND(x) ((x) << S_PIND)
8521 #define F_PIND    V_PIND(1U)
8522 
8523 #define S_ALER    19
8524 #define V_ALER(x) ((x) << S_ALER)
8525 #define F_ALER    V_ALER(1U)
8526 
8527 #define S_CRSE    18
8528 #define V_CRSE(x) ((x) << S_CRSE)
8529 #define F_CRSE    V_CRSE(1U)
8530 
8531 #define A_PCIE_T5_HMA_CFG 0x59b0
8532 
8533 #define S_HMA_MAXREQCNT    20
8534 #define M_HMA_MAXREQCNT    0x1fU
8535 #define V_HMA_MAXREQCNT(x) ((x) << S_HMA_MAXREQCNT)
8536 #define G_HMA_MAXREQCNT(x) (((x) >> S_HMA_MAXREQCNT) & M_HMA_MAXREQCNT)
8537 
8538 #define S_T5_HMA_MAXRDREQSIZE    17
8539 #define M_T5_HMA_MAXRDREQSIZE    0x7U
8540 #define V_T5_HMA_MAXRDREQSIZE(x) ((x) << S_T5_HMA_MAXRDREQSIZE)
8541 #define G_T5_HMA_MAXRDREQSIZE(x) (((x) >> S_T5_HMA_MAXRDREQSIZE) & M_T5_HMA_MAXRDREQSIZE)
8542 
8543 #define S_T5_HMA_MAXRSPCNT    8
8544 #define M_T5_HMA_MAXRSPCNT    0x1fU
8545 #define V_T5_HMA_MAXRSPCNT(x) ((x) << S_T5_HMA_MAXRSPCNT)
8546 #define G_T5_HMA_MAXRSPCNT(x) (((x) >> S_T5_HMA_MAXRSPCNT) & M_T5_HMA_MAXRSPCNT)
8547 
8548 #define S_T6_HMA_MAXREQCNT    20
8549 #define M_T6_HMA_MAXREQCNT    0x7fU
8550 #define V_T6_HMA_MAXREQCNT(x) ((x) << S_T6_HMA_MAXREQCNT)
8551 #define G_T6_HMA_MAXREQCNT(x) (((x) >> S_T6_HMA_MAXREQCNT) & M_T6_HMA_MAXREQCNT)
8552 
8553 #define S_T6_T5_HMA_MAXRSPCNT    9
8554 #define M_T6_T5_HMA_MAXRSPCNT    0xffU
8555 #define V_T6_T5_HMA_MAXRSPCNT(x) ((x) << S_T6_T5_HMA_MAXRSPCNT)
8556 #define G_T6_T5_HMA_MAXRSPCNT(x) (((x) >> S_T6_T5_HMA_MAXRSPCNT) & M_T6_T5_HMA_MAXRSPCNT)
8557 
8558 #define S_T5_HMA_SEQCHKDIS    8
8559 #define V_T5_HMA_SEQCHKDIS(x) ((x) << S_T5_HMA_SEQCHKDIS)
8560 #define F_T5_HMA_SEQCHKDIS    V_T5_HMA_SEQCHKDIS(1U)
8561 
8562 #define S_T5_MINTAG    0
8563 #define M_T5_MINTAG    0xffU
8564 #define V_T5_MINTAG(x) ((x) << S_T5_MINTAG)
8565 #define G_T5_MINTAG(x) (((x) >> S_T5_MINTAG) & M_T5_MINTAG)
8566 
8567 #define A_PCIE_CORE_ROOT_COMPLEX_ERROR_SEVERITY 0x59b4
8568 
8569 #define S_RLCS    31
8570 #define V_RLCS(x) ((x) << S_RLCS)
8571 #define F_RLCS    V_RLCS(1U)
8572 
8573 #define S_RLNS    30
8574 #define V_RLNS(x) ((x) << S_RLNS)
8575 #define F_RLNS    V_RLNS(1U)
8576 
8577 #define S_RLFS    29
8578 #define V_RLFS(x) ((x) << S_RLFS)
8579 #define F_RLFS    V_RLFS(1U)
8580 
8581 #define S_RCPS    25
8582 #define V_RCPS(x) ((x) << S_RCPS)
8583 #define F_RCPS    V_RCPS(1U)
8584 
8585 #define S_RCTS    24
8586 #define V_RCTS(x) ((x) << S_RCTS)
8587 #define F_RCTS    V_RCTS(1U)
8588 
8589 #define S_PAAS    23
8590 #define V_PAAS(x) ((x) << S_PAAS)
8591 #define F_PAAS    V_PAAS(1U)
8592 
8593 #define S_PABS    22
8594 #define V_PABS(x) ((x) << S_PABS)
8595 #define F_PABS    V_PABS(1U)
8596 
8597 #define S_PACS    21
8598 #define V_PACS(x) ((x) << S_PACS)
8599 #define F_PACS    V_PACS(1U)
8600 
8601 #define S_PADS    20
8602 #define V_PADS(x) ((x) << S_PADS)
8603 #define F_PADS    V_PADS(1U)
8604 
8605 #define S_ALES    19
8606 #define V_ALES(x) ((x) << S_ALES)
8607 #define F_ALES    V_ALES(1U)
8608 
8609 #define S_CRSS    18
8610 #define V_CRSS(x) ((x) << S_CRSS)
8611 #define F_CRSS    V_CRSS(1U)
8612 
8613 #define A_PCIE_T5_HMA_STAT 0x59b4
8614 
8615 #define S_HMA_RESPCNT    20
8616 #define M_HMA_RESPCNT    0x1ffU
8617 #define V_HMA_RESPCNT(x) ((x) << S_HMA_RESPCNT)
8618 #define G_HMA_RESPCNT(x) (((x) >> S_HMA_RESPCNT) & M_HMA_RESPCNT)
8619 
8620 #define S_HMA_RDREQCNT    12
8621 #define M_HMA_RDREQCNT    0x3fU
8622 #define V_HMA_RDREQCNT(x) ((x) << S_HMA_RDREQCNT)
8623 #define G_HMA_RDREQCNT(x) (((x) >> S_HMA_RDREQCNT) & M_HMA_RDREQCNT)
8624 
8625 #define S_HMA_WRREQCNT    0
8626 #define M_HMA_WRREQCNT    0x1ffU
8627 #define V_HMA_WRREQCNT(x) ((x) << S_HMA_WRREQCNT)
8628 #define G_HMA_WRREQCNT(x) (((x) >> S_HMA_WRREQCNT) & M_HMA_WRREQCNT)
8629 
8630 #define S_T6_HMA_RESPCNT    20
8631 #define M_T6_HMA_RESPCNT    0x3ffU
8632 #define V_T6_HMA_RESPCNT(x) ((x) << S_T6_HMA_RESPCNT)
8633 #define G_T6_HMA_RESPCNT(x) (((x) >> S_T6_HMA_RESPCNT) & M_T6_HMA_RESPCNT)
8634 
8635 #define A_PCIE_CORE_ROOT_COMPLEX_INTERRUPT_ENABLE 0x59b8
8636 
8637 #define S_RLCI    31
8638 #define V_RLCI(x) ((x) << S_RLCI)
8639 #define F_RLCI    V_RLCI(1U)
8640 
8641 #define S_RLNI    30
8642 #define V_RLNI(x) ((x) << S_RLNI)
8643 #define F_RLNI    V_RLNI(1U)
8644 
8645 #define S_RLFI    29
8646 #define V_RLFI(x) ((x) << S_RLFI)
8647 #define F_RLFI    V_RLFI(1U)
8648 
8649 #define S_RCPI    25
8650 #define V_RCPI(x) ((x) << S_RCPI)
8651 #define F_RCPI    V_RCPI(1U)
8652 
8653 #define S_RCTI    24
8654 #define V_RCTI(x) ((x) << S_RCTI)
8655 #define F_RCTI    V_RCTI(1U)
8656 
8657 #define S_PAAI    23
8658 #define V_PAAI(x) ((x) << S_PAAI)
8659 #define F_PAAI    V_PAAI(1U)
8660 
8661 #define S_PABI    22
8662 #define V_PABI(x) ((x) << S_PABI)
8663 #define F_PABI    V_PABI(1U)
8664 
8665 #define S_PACI    21
8666 #define V_PACI(x) ((x) << S_PACI)
8667 #define F_PACI    V_PACI(1U)
8668 
8669 #define S_PADI    20
8670 #define V_PADI(x) ((x) << S_PADI)
8671 #define F_PADI    V_PADI(1U)
8672 
8673 #define S_ALEI    19
8674 #define V_ALEI(x) ((x) << S_ALEI)
8675 #define F_ALEI    V_ALEI(1U)
8676 
8677 #define S_CRSI    18
8678 #define V_CRSI(x) ((x) << S_CRSI)
8679 #define F_CRSI    V_CRSI(1U)
8680 
8681 #define A_PCIE_T5_HMA_STAT2 0x59b8
8682 
8683 #define S_HMA_COOKIECNT    24
8684 #define M_HMA_COOKIECNT    0xfU
8685 #define V_HMA_COOKIECNT(x) ((x) << S_HMA_COOKIECNT)
8686 #define G_HMA_COOKIECNT(x) (((x) >> S_HMA_COOKIECNT) & M_HMA_COOKIECNT)
8687 
8688 #define S_HMA_RDSEQNUMUPDCNT    20
8689 #define M_HMA_RDSEQNUMUPDCNT    0xfU
8690 #define V_HMA_RDSEQNUMUPDCNT(x) ((x) << S_HMA_RDSEQNUMUPDCNT)
8691 #define G_HMA_RDSEQNUMUPDCNT(x) (((x) >> S_HMA_RDSEQNUMUPDCNT) & M_HMA_RDSEQNUMUPDCNT)
8692 
8693 #define S_HMA_WREOPMATCHSOP    12
8694 #define V_HMA_WREOPMATCHSOP(x) ((x) << S_HMA_WREOPMATCHSOP)
8695 #define F_HMA_WREOPMATCHSOP    V_HMA_WREOPMATCHSOP(1U)
8696 
8697 #define S_HMA_WRSOPCNT    8
8698 #define M_HMA_WRSOPCNT    0xfU
8699 #define V_HMA_WRSOPCNT(x) ((x) << S_HMA_WRSOPCNT)
8700 #define G_HMA_WRSOPCNT(x) (((x) >> S_HMA_WRSOPCNT) & M_HMA_WRSOPCNT)
8701 
8702 #define S_HMA_RDSOPCNT    0
8703 #define M_HMA_RDSOPCNT    0xffU
8704 #define V_HMA_RDSOPCNT(x) ((x) << S_HMA_RDSOPCNT)
8705 #define G_HMA_RDSOPCNT(x) (((x) >> S_HMA_RDSOPCNT) & M_HMA_RDSOPCNT)
8706 
8707 #define A_PCIE_CORE_ENDPOINT_STATUS 0x59bc
8708 
8709 #define S_PTOM    31
8710 #define V_PTOM(x) ((x) << S_PTOM)
8711 #define F_PTOM    V_PTOM(1U)
8712 
8713 #define S_ALEA    29
8714 #define V_ALEA(x) ((x) << S_ALEA)
8715 #define F_ALEA    V_ALEA(1U)
8716 
8717 #define S_PMC0    23
8718 #define V_PMC0(x) ((x) << S_PMC0)
8719 #define F_PMC0    V_PMC0(1U)
8720 
8721 #define S_PMC1    22
8722 #define V_PMC1(x) ((x) << S_PMC1)
8723 #define F_PMC1    V_PMC1(1U)
8724 
8725 #define S_PMC2    21
8726 #define V_PMC2(x) ((x) << S_PMC2)
8727 #define F_PMC2    V_PMC2(1U)
8728 
8729 #define S_PMC3    20
8730 #define V_PMC3(x) ((x) << S_PMC3)
8731 #define F_PMC3    V_PMC3(1U)
8732 
8733 #define S_PMC4    19
8734 #define V_PMC4(x) ((x) << S_PMC4)
8735 #define F_PMC4    V_PMC4(1U)
8736 
8737 #define S_PMC5    18
8738 #define V_PMC5(x) ((x) << S_PMC5)
8739 #define F_PMC5    V_PMC5(1U)
8740 
8741 #define S_PMC6    17
8742 #define V_PMC6(x) ((x) << S_PMC6)
8743 #define F_PMC6    V_PMC6(1U)
8744 
8745 #define S_PMC7    16
8746 #define V_PMC7(x) ((x) << S_PMC7)
8747 #define F_PMC7    V_PMC7(1U)
8748 
8749 #define A_PCIE_T5_HMA_STAT3 0x59bc
8750 
8751 #define S_HMA_RSPEOPMATCHSOP    16
8752 #define V_HMA_RSPEOPMATCHSOP(x) ((x) << S_HMA_RSPEOPMATCHSOP)
8753 #define F_HMA_RSPEOPMATCHSOP    V_HMA_RSPEOPMATCHSOP(1U)
8754 
8755 #define S_HMA_RSPERRCNT    8
8756 #define M_HMA_RSPERRCNT    0xffU
8757 #define V_HMA_RSPERRCNT(x) ((x) << S_HMA_RSPERRCNT)
8758 #define G_HMA_RSPERRCNT(x) (((x) >> S_HMA_RSPERRCNT) & M_HMA_RSPERRCNT)
8759 
8760 #define S_HMA_RSPSOPCNT    0
8761 #define M_HMA_RSPSOPCNT    0xffU
8762 #define V_HMA_RSPSOPCNT(x) ((x) << S_HMA_RSPSOPCNT)
8763 #define G_HMA_RSPSOPCNT(x) (((x) >> S_HMA_RSPSOPCNT) & M_HMA_RSPSOPCNT)
8764 
8765 #define A_PCIE_CORE_ENDPOINT_ERROR_SEVERITY 0x59c0
8766 
8767 #define S_PTOS    31
8768 #define V_PTOS(x) ((x) << S_PTOS)
8769 #define F_PTOS    V_PTOS(1U)
8770 
8771 #define S_AENS    29
8772 #define V_AENS(x) ((x) << S_AENS)
8773 #define F_AENS    V_AENS(1U)
8774 
8775 #define S_PC0S    23
8776 #define V_PC0S(x) ((x) << S_PC0S)
8777 #define F_PC0S    V_PC0S(1U)
8778 
8779 #define S_PC1S    22
8780 #define V_PC1S(x) ((x) << S_PC1S)
8781 #define F_PC1S    V_PC1S(1U)
8782 
8783 #define S_PC2S    21
8784 #define V_PC2S(x) ((x) << S_PC2S)
8785 #define F_PC2S    V_PC2S(1U)
8786 
8787 #define S_PC3S    20
8788 #define V_PC3S(x) ((x) << S_PC3S)
8789 #define F_PC3S    V_PC3S(1U)
8790 
8791 #define S_PC4S    19
8792 #define V_PC4S(x) ((x) << S_PC4S)
8793 #define F_PC4S    V_PC4S(1U)
8794 
8795 #define S_PC5S    18
8796 #define V_PC5S(x) ((x) << S_PC5S)
8797 #define F_PC5S    V_PC5S(1U)
8798 
8799 #define S_PC6S    17
8800 #define V_PC6S(x) ((x) << S_PC6S)
8801 #define F_PC6S    V_PC6S(1U)
8802 
8803 #define S_PC7S    16
8804 #define V_PC7S(x) ((x) << S_PC7S)
8805 #define F_PC7S    V_PC7S(1U)
8806 
8807 #define S_PME0    15
8808 #define V_PME0(x) ((x) << S_PME0)
8809 #define F_PME0    V_PME0(1U)
8810 
8811 #define S_PME1    14
8812 #define V_PME1(x) ((x) << S_PME1)
8813 #define F_PME1    V_PME1(1U)
8814 
8815 #define S_PME2    13
8816 #define V_PME2(x) ((x) << S_PME2)
8817 #define F_PME2    V_PME2(1U)
8818 
8819 #define S_PME3    12
8820 #define V_PME3(x) ((x) << S_PME3)
8821 #define F_PME3    V_PME3(1U)
8822 
8823 #define S_PME4    11
8824 #define V_PME4(x) ((x) << S_PME4)
8825 #define F_PME4    V_PME4(1U)
8826 
8827 #define S_PME5    10
8828 #define V_PME5(x) ((x) << S_PME5)
8829 #define F_PME5    V_PME5(1U)
8830 
8831 #define S_PME6    9
8832 #define V_PME6(x) ((x) << S_PME6)
8833 #define F_PME6    V_PME6(1U)
8834 
8835 #define S_PME7    8
8836 #define V_PME7(x) ((x) << S_PME7)
8837 #define F_PME7    V_PME7(1U)
8838 
8839 #define A_PCIE_CGEN 0x59c0
8840 
8841 #define S_VPD_DYNAMIC_CGEN    26
8842 #define V_VPD_DYNAMIC_CGEN(x) ((x) << S_VPD_DYNAMIC_CGEN)
8843 #define F_VPD_DYNAMIC_CGEN    V_VPD_DYNAMIC_CGEN(1U)
8844 
8845 #define S_MA_DYNAMIC_CGEN    25
8846 #define V_MA_DYNAMIC_CGEN(x) ((x) << S_MA_DYNAMIC_CGEN)
8847 #define F_MA_DYNAMIC_CGEN    V_MA_DYNAMIC_CGEN(1U)
8848 
8849 #define S_TAGQ_DYNAMIC_CGEN    24
8850 #define V_TAGQ_DYNAMIC_CGEN(x) ((x) << S_TAGQ_DYNAMIC_CGEN)
8851 #define F_TAGQ_DYNAMIC_CGEN    V_TAGQ_DYNAMIC_CGEN(1U)
8852 
8853 #define S_REQCTL_DYNAMIC_CGEN    23
8854 #define V_REQCTL_DYNAMIC_CGEN(x) ((x) << S_REQCTL_DYNAMIC_CGEN)
8855 #define F_REQCTL_DYNAMIC_CGEN    V_REQCTL_DYNAMIC_CGEN(1U)
8856 
8857 #define S_RSPDATAPROC_DYNAMIC_CGEN    22
8858 #define V_RSPDATAPROC_DYNAMIC_CGEN(x) ((x) << S_RSPDATAPROC_DYNAMIC_CGEN)
8859 #define F_RSPDATAPROC_DYNAMIC_CGEN    V_RSPDATAPROC_DYNAMIC_CGEN(1U)
8860 
8861 #define S_RSPRDQ_DYNAMIC_CGEN    21
8862 #define V_RSPRDQ_DYNAMIC_CGEN(x) ((x) << S_RSPRDQ_DYNAMIC_CGEN)
8863 #define F_RSPRDQ_DYNAMIC_CGEN    V_RSPRDQ_DYNAMIC_CGEN(1U)
8864 
8865 #define S_RSPIPIF_DYNAMIC_CGEN    20
8866 #define V_RSPIPIF_DYNAMIC_CGEN(x) ((x) << S_RSPIPIF_DYNAMIC_CGEN)
8867 #define F_RSPIPIF_DYNAMIC_CGEN    V_RSPIPIF_DYNAMIC_CGEN(1U)
8868 
8869 #define S_HMA_STATIC_CGEN    19
8870 #define V_HMA_STATIC_CGEN(x) ((x) << S_HMA_STATIC_CGEN)
8871 #define F_HMA_STATIC_CGEN    V_HMA_STATIC_CGEN(1U)
8872 
8873 #define S_HMA_DYNAMIC_CGEN    18
8874 #define V_HMA_DYNAMIC_CGEN(x) ((x) << S_HMA_DYNAMIC_CGEN)
8875 #define F_HMA_DYNAMIC_CGEN    V_HMA_DYNAMIC_CGEN(1U)
8876 
8877 #define S_CMD_STATIC_CGEN    16
8878 #define V_CMD_STATIC_CGEN(x) ((x) << S_CMD_STATIC_CGEN)
8879 #define F_CMD_STATIC_CGEN    V_CMD_STATIC_CGEN(1U)
8880 
8881 #define S_CMD_DYNAMIC_CGEN    15
8882 #define V_CMD_DYNAMIC_CGEN(x) ((x) << S_CMD_DYNAMIC_CGEN)
8883 #define F_CMD_DYNAMIC_CGEN    V_CMD_DYNAMIC_CGEN(1U)
8884 
8885 #define S_DMA_STATIC_CGEN    13
8886 #define V_DMA_STATIC_CGEN(x) ((x) << S_DMA_STATIC_CGEN)
8887 #define F_DMA_STATIC_CGEN    V_DMA_STATIC_CGEN(1U)
8888 
8889 #define S_DMA_DYNAMIC_CGEN    12
8890 #define V_DMA_DYNAMIC_CGEN(x) ((x) << S_DMA_DYNAMIC_CGEN)
8891 #define F_DMA_DYNAMIC_CGEN    V_DMA_DYNAMIC_CGEN(1U)
8892 
8893 #define S_VFID_SLEEPSTATUS    10
8894 #define V_VFID_SLEEPSTATUS(x) ((x) << S_VFID_SLEEPSTATUS)
8895 #define F_VFID_SLEEPSTATUS    V_VFID_SLEEPSTATUS(1U)
8896 
8897 #define S_VC1_SLEEPSTATUS    9
8898 #define V_VC1_SLEEPSTATUS(x) ((x) << S_VC1_SLEEPSTATUS)
8899 #define F_VC1_SLEEPSTATUS    V_VC1_SLEEPSTATUS(1U)
8900 
8901 #define S_STI_SLEEPSTATUS    8
8902 #define V_STI_SLEEPSTATUS(x) ((x) << S_STI_SLEEPSTATUS)
8903 #define F_STI_SLEEPSTATUS    V_STI_SLEEPSTATUS(1U)
8904 
8905 #define S_VFID_SLEEPREQ    2
8906 #define V_VFID_SLEEPREQ(x) ((x) << S_VFID_SLEEPREQ)
8907 #define F_VFID_SLEEPREQ    V_VFID_SLEEPREQ(1U)
8908 
8909 #define S_VC1_SLEEPREQ    1
8910 #define V_VC1_SLEEPREQ(x) ((x) << S_VC1_SLEEPREQ)
8911 #define F_VC1_SLEEPREQ    V_VC1_SLEEPREQ(1U)
8912 
8913 #define S_STI_SLEEPREQ    0
8914 #define V_STI_SLEEPREQ(x) ((x) << S_STI_SLEEPREQ)
8915 #define F_STI_SLEEPREQ    V_STI_SLEEPREQ(1U)
8916 
8917 #define S_ARM_STATIC_CGEN    28
8918 #define V_ARM_STATIC_CGEN(x) ((x) << S_ARM_STATIC_CGEN)
8919 #define F_ARM_STATIC_CGEN    V_ARM_STATIC_CGEN(1U)
8920 
8921 #define S_ARM_DYNAMIC_CGEN    27
8922 #define V_ARM_DYNAMIC_CGEN(x) ((x) << S_ARM_DYNAMIC_CGEN)
8923 #define F_ARM_DYNAMIC_CGEN    V_ARM_DYNAMIC_CGEN(1U)
8924 
8925 #define A_PCIE_CORE_ENDPOINT_INTERRUPT_ENABLE 0x59c4
8926 
8927 #define S_PTOI    31
8928 #define V_PTOI(x) ((x) << S_PTOI)
8929 #define F_PTOI    V_PTOI(1U)
8930 
8931 #define S_AENI    29
8932 #define V_AENI(x) ((x) << S_AENI)
8933 #define F_AENI    V_AENI(1U)
8934 
8935 #define S_PC0I    23
8936 #define V_PC0I(x) ((x) << S_PC0I)
8937 #define F_PC0I    V_PC0I(1U)
8938 
8939 #define S_PC1I    22
8940 #define V_PC1I(x) ((x) << S_PC1I)
8941 #define F_PC1I    V_PC1I(1U)
8942 
8943 #define S_PC2I    21
8944 #define V_PC2I(x) ((x) << S_PC2I)
8945 #define F_PC2I    V_PC2I(1U)
8946 
8947 #define S_PC3I    20
8948 #define V_PC3I(x) ((x) << S_PC3I)
8949 #define F_PC3I    V_PC3I(1U)
8950 
8951 #define S_PC4I    19
8952 #define V_PC4I(x) ((x) << S_PC4I)
8953 #define F_PC4I    V_PC4I(1U)
8954 
8955 #define S_PC5I    18
8956 #define V_PC5I(x) ((x) << S_PC5I)
8957 #define F_PC5I    V_PC5I(1U)
8958 
8959 #define S_PC6I    17
8960 #define V_PC6I(x) ((x) << S_PC6I)
8961 #define F_PC6I    V_PC6I(1U)
8962 
8963 #define S_PC7I    16
8964 #define V_PC7I(x) ((x) << S_PC7I)
8965 #define F_PC7I    V_PC7I(1U)
8966 
8967 #define A_PCIE_MA_RSP 0x59c4
8968 
8969 #define S_TIMERVALUE    8
8970 #define M_TIMERVALUE    0xffffffU
8971 #define V_TIMERVALUE(x) ((x) << S_TIMERVALUE)
8972 #define G_TIMERVALUE(x) (((x) >> S_TIMERVALUE) & M_TIMERVALUE)
8973 
8974 #define S_MAREQTIMEREN    1
8975 #define V_MAREQTIMEREN(x) ((x) << S_MAREQTIMEREN)
8976 #define F_MAREQTIMEREN    V_MAREQTIMEREN(1U)
8977 
8978 #define S_MARSPTIMEREN    0
8979 #define V_MARSPTIMEREN(x) ((x) << S_MARSPTIMEREN)
8980 #define F_MARSPTIMEREN    V_MARSPTIMEREN(1U)
8981 
8982 #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_1 0x59c8
8983 
8984 #define S_TOAK    31
8985 #define V_TOAK(x) ((x) << S_TOAK)
8986 #define F_TOAK    V_TOAK(1U)
8987 
8988 #define S_L1RS    23
8989 #define V_L1RS(x) ((x) << S_L1RS)
8990 #define F_L1RS    V_L1RS(1U)
8991 
8992 #define S_L23S    22
8993 #define V_L23S(x) ((x) << S_L23S)
8994 #define F_L23S    V_L23S(1U)
8995 
8996 #define S_AL1S    21
8997 #define V_AL1S(x) ((x) << S_AL1S)
8998 #define F_AL1S    V_AL1S(1U)
8999 
9000 #define S_ALET    19
9001 #define V_ALET(x) ((x) << S_ALET)
9002 #define F_ALET    V_ALET(1U)
9003 
9004 #define A_PCIE_HPRD 0x59c8
9005 
9006 #define S_NPH_CREDITSAVAILVC0    19
9007 #define M_NPH_CREDITSAVAILVC0    0x3U
9008 #define V_NPH_CREDITSAVAILVC0(x) ((x) << S_NPH_CREDITSAVAILVC0)
9009 #define G_NPH_CREDITSAVAILVC0(x) (((x) >> S_NPH_CREDITSAVAILVC0) & M_NPH_CREDITSAVAILVC0)
9010 
9011 #define S_NPD_CREDITSAVAILVC0    17
9012 #define M_NPD_CREDITSAVAILVC0    0x3U
9013 #define V_NPD_CREDITSAVAILVC0(x) ((x) << S_NPD_CREDITSAVAILVC0)
9014 #define G_NPD_CREDITSAVAILVC0(x) (((x) >> S_NPD_CREDITSAVAILVC0) & M_NPD_CREDITSAVAILVC0)
9015 
9016 #define S_NPH_CREDITSAVAILVC1    15
9017 #define M_NPH_CREDITSAVAILVC1    0x3U
9018 #define V_NPH_CREDITSAVAILVC1(x) ((x) << S_NPH_CREDITSAVAILVC1)
9019 #define G_NPH_CREDITSAVAILVC1(x) (((x) >> S_NPH_CREDITSAVAILVC1) & M_NPH_CREDITSAVAILVC1)
9020 
9021 #define S_NPD_CREDITSAVAILVC1    13
9022 #define M_NPD_CREDITSAVAILVC1    0x3U
9023 #define V_NPD_CREDITSAVAILVC1(x) ((x) << S_NPD_CREDITSAVAILVC1)
9024 #define G_NPD_CREDITSAVAILVC1(x) (((x) >> S_NPD_CREDITSAVAILVC1) & M_NPD_CREDITSAVAILVC1)
9025 
9026 #define S_NPH_CREDITSREQUIRED    11
9027 #define M_NPH_CREDITSREQUIRED    0x3U
9028 #define V_NPH_CREDITSREQUIRED(x) ((x) << S_NPH_CREDITSREQUIRED)
9029 #define G_NPH_CREDITSREQUIRED(x) (((x) >> S_NPH_CREDITSREQUIRED) & M_NPH_CREDITSREQUIRED)
9030 
9031 #define S_NPD_CREDITSREQUIRED    9
9032 #define M_NPD_CREDITSREQUIRED    0x3U
9033 #define V_NPD_CREDITSREQUIRED(x) ((x) << S_NPD_CREDITSREQUIRED)
9034 #define G_NPD_CREDITSREQUIRED(x) (((x) >> S_NPD_CREDITSREQUIRED) & M_NPD_CREDITSREQUIRED)
9035 
9036 #define S_REQBURSTCOUNT    5
9037 #define M_REQBURSTCOUNT    0xfU
9038 #define V_REQBURSTCOUNT(x) ((x) << S_REQBURSTCOUNT)
9039 #define G_REQBURSTCOUNT(x) (((x) >> S_REQBURSTCOUNT) & M_REQBURSTCOUNT)
9040 
9041 #define S_REQBURSTFREQUENCY    1
9042 #define M_REQBURSTFREQUENCY    0xfU
9043 #define V_REQBURSTFREQUENCY(x) ((x) << S_REQBURSTFREQUENCY)
9044 #define G_REQBURSTFREQUENCY(x) (((x) >> S_REQBURSTFREQUENCY) & M_REQBURSTFREQUENCY)
9045 
9046 #define S_ENABLEVC1    0
9047 #define V_ENABLEVC1(x) ((x) << S_ENABLEVC1)
9048 #define F_ENABLEVC1    V_ENABLEVC1(1U)
9049 
9050 #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_2 0x59cc
9051 
9052 #define S_CPM0    30
9053 #define M_CPM0    0x3U
9054 #define V_CPM0(x) ((x) << S_CPM0)
9055 #define G_CPM0(x) (((x) >> S_CPM0) & M_CPM0)
9056 
9057 #define S_CPM1    28
9058 #define M_CPM1    0x3U
9059 #define V_CPM1(x) ((x) << S_CPM1)
9060 #define G_CPM1(x) (((x) >> S_CPM1) & M_CPM1)
9061 
9062 #define S_CPM2    26
9063 #define M_CPM2    0x3U
9064 #define V_CPM2(x) ((x) << S_CPM2)
9065 #define G_CPM2(x) (((x) >> S_CPM2) & M_CPM2)
9066 
9067 #define S_CPM3    24
9068 #define M_CPM3    0x3U
9069 #define V_CPM3(x) ((x) << S_CPM3)
9070 #define G_CPM3(x) (((x) >> S_CPM3) & M_CPM3)
9071 
9072 #define S_CPM4    22
9073 #define M_CPM4    0x3U
9074 #define V_CPM4(x) ((x) << S_CPM4)
9075 #define G_CPM4(x) (((x) >> S_CPM4) & M_CPM4)
9076 
9077 #define S_CPM5    20
9078 #define M_CPM5    0x3U
9079 #define V_CPM5(x) ((x) << S_CPM5)
9080 #define G_CPM5(x) (((x) >> S_CPM5) & M_CPM5)
9081 
9082 #define S_CPM6    18
9083 #define M_CPM6    0x3U
9084 #define V_CPM6(x) ((x) << S_CPM6)
9085 #define G_CPM6(x) (((x) >> S_CPM6) & M_CPM6)
9086 
9087 #define S_CPM7    16
9088 #define M_CPM7    0x3U
9089 #define V_CPM7(x) ((x) << S_CPM7)
9090 #define G_CPM7(x) (((x) >> S_CPM7) & M_CPM7)
9091 
9092 #define S_OPM0    14
9093 #define M_OPM0    0x3U
9094 #define V_OPM0(x) ((x) << S_OPM0)
9095 #define G_OPM0(x) (((x) >> S_OPM0) & M_OPM0)
9096 
9097 #define S_OPM1    12
9098 #define M_OPM1    0x3U
9099 #define V_OPM1(x) ((x) << S_OPM1)
9100 #define G_OPM1(x) (((x) >> S_OPM1) & M_OPM1)
9101 
9102 #define S_OPM2    10
9103 #define M_OPM2    0x3U
9104 #define V_OPM2(x) ((x) << S_OPM2)
9105 #define G_OPM2(x) (((x) >> S_OPM2) & M_OPM2)
9106 
9107 #define S_OPM3    8
9108 #define M_OPM3    0x3U
9109 #define V_OPM3(x) ((x) << S_OPM3)
9110 #define G_OPM3(x) (((x) >> S_OPM3) & M_OPM3)
9111 
9112 #define S_OPM4    6
9113 #define M_OPM4    0x3U
9114 #define V_OPM4(x) ((x) << S_OPM4)
9115 #define G_OPM4(x) (((x) >> S_OPM4) & M_OPM4)
9116 
9117 #define S_OPM5    4
9118 #define M_OPM5    0x3U
9119 #define V_OPM5(x) ((x) << S_OPM5)
9120 #define G_OPM5(x) (((x) >> S_OPM5) & M_OPM5)
9121 
9122 #define S_OPM6    2
9123 #define M_OPM6    0x3U
9124 #define V_OPM6(x) ((x) << S_OPM6)
9125 #define G_OPM6(x) (((x) >> S_OPM6) & M_OPM6)
9126 
9127 #define S_OPM7    0
9128 #define M_OPM7    0x3U
9129 #define V_OPM7(x) ((x) << S_OPM7)
9130 #define G_OPM7(x) (((x) >> S_OPM7) & M_OPM7)
9131 
9132 #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_1 0x59d0
9133 #define A_PCIE_PERR_GROUP 0x59d0
9134 
9135 #define S_MST_DATAPATHPERR    25
9136 #define V_MST_DATAPATHPERR(x) ((x) << S_MST_DATAPATHPERR)
9137 #define F_MST_DATAPATHPERR    V_MST_DATAPATHPERR(1U)
9138 
9139 #define S_MST_RSPRDQPERR    24
9140 #define V_MST_RSPRDQPERR(x) ((x) << S_MST_RSPRDQPERR)
9141 #define F_MST_RSPRDQPERR    V_MST_RSPRDQPERR(1U)
9142 
9143 #define S_IP_RXPERR    23
9144 #define V_IP_RXPERR(x) ((x) << S_IP_RXPERR)
9145 #define F_IP_RXPERR    V_IP_RXPERR(1U)
9146 
9147 #define S_IP_BACKTXPERR    22
9148 #define V_IP_BACKTXPERR(x) ((x) << S_IP_BACKTXPERR)
9149 #define F_IP_BACKTXPERR    V_IP_BACKTXPERR(1U)
9150 
9151 #define S_IP_FRONTTXPERR    21
9152 #define V_IP_FRONTTXPERR(x) ((x) << S_IP_FRONTTXPERR)
9153 #define F_IP_FRONTTXPERR    V_IP_FRONTTXPERR(1U)
9154 
9155 #define S_TRGT1_FIDLKUPHDRPERR    20
9156 #define V_TRGT1_FIDLKUPHDRPERR(x) ((x) << S_TRGT1_FIDLKUPHDRPERR)
9157 #define F_TRGT1_FIDLKUPHDRPERR    V_TRGT1_FIDLKUPHDRPERR(1U)
9158 
9159 #define S_TRGT1_ALINDDATAPERR    19
9160 #define V_TRGT1_ALINDDATAPERR(x) ((x) << S_TRGT1_ALINDDATAPERR)
9161 #define F_TRGT1_ALINDDATAPERR    V_TRGT1_ALINDDATAPERR(1U)
9162 
9163 #define S_TRGT1_UNALINDATAPERR    18
9164 #define V_TRGT1_UNALINDATAPERR(x) ((x) << S_TRGT1_UNALINDATAPERR)
9165 #define F_TRGT1_UNALINDATAPERR    V_TRGT1_UNALINDATAPERR(1U)
9166 
9167 #define S_TRGT1_REQDATAPERR    17
9168 #define V_TRGT1_REQDATAPERR(x) ((x) << S_TRGT1_REQDATAPERR)
9169 #define F_TRGT1_REQDATAPERR    V_TRGT1_REQDATAPERR(1U)
9170 
9171 #define S_TRGT1_REQHDRPERR    16
9172 #define V_TRGT1_REQHDRPERR(x) ((x) << S_TRGT1_REQHDRPERR)
9173 #define F_TRGT1_REQHDRPERR    V_TRGT1_REQHDRPERR(1U)
9174 
9175 #define S_IPRXDATA_VC1PERR    15
9176 #define V_IPRXDATA_VC1PERR(x) ((x) << S_IPRXDATA_VC1PERR)
9177 #define F_IPRXDATA_VC1PERR    V_IPRXDATA_VC1PERR(1U)
9178 
9179 #define S_IPRXDATA_VC0PERR    14
9180 #define V_IPRXDATA_VC0PERR(x) ((x) << S_IPRXDATA_VC0PERR)
9181 #define F_IPRXDATA_VC0PERR    V_IPRXDATA_VC0PERR(1U)
9182 
9183 #define S_IPRXHDR_VC1PERR    13
9184 #define V_IPRXHDR_VC1PERR(x) ((x) << S_IPRXHDR_VC1PERR)
9185 #define F_IPRXHDR_VC1PERR    V_IPRXHDR_VC1PERR(1U)
9186 
9187 #define S_IPRXHDR_VC0PERR    12
9188 #define V_IPRXHDR_VC0PERR(x) ((x) << S_IPRXHDR_VC0PERR)
9189 #define F_IPRXHDR_VC0PERR    V_IPRXHDR_VC0PERR(1U)
9190 
9191 #define S_MA_RSPDATAPERR    11
9192 #define V_MA_RSPDATAPERR(x) ((x) << S_MA_RSPDATAPERR)
9193 #define F_MA_RSPDATAPERR    V_MA_RSPDATAPERR(1U)
9194 
9195 #define S_MA_CPLTAGQPERR    10
9196 #define V_MA_CPLTAGQPERR(x) ((x) << S_MA_CPLTAGQPERR)
9197 #define F_MA_CPLTAGQPERR    V_MA_CPLTAGQPERR(1U)
9198 
9199 #define S_MA_REQTAGQPERR    9
9200 #define V_MA_REQTAGQPERR(x) ((x) << S_MA_REQTAGQPERR)
9201 #define F_MA_REQTAGQPERR    V_MA_REQTAGQPERR(1U)
9202 
9203 #define S_PIOREQ_BAR2CTLPERR    8
9204 #define V_PIOREQ_BAR2CTLPERR(x) ((x) << S_PIOREQ_BAR2CTLPERR)
9205 #define F_PIOREQ_BAR2CTLPERR    V_PIOREQ_BAR2CTLPERR(1U)
9206 
9207 #define S_PIOREQ_MEMCTLPERR    7
9208 #define V_PIOREQ_MEMCTLPERR(x) ((x) << S_PIOREQ_MEMCTLPERR)
9209 #define F_PIOREQ_MEMCTLPERR    V_PIOREQ_MEMCTLPERR(1U)
9210 
9211 #define S_PIOREQ_PLMCTLPERR    6
9212 #define V_PIOREQ_PLMCTLPERR(x) ((x) << S_PIOREQ_PLMCTLPERR)
9213 #define F_PIOREQ_PLMCTLPERR    V_PIOREQ_PLMCTLPERR(1U)
9214 
9215 #define S_PIOREQ_BAR2DATAPERR    5
9216 #define V_PIOREQ_BAR2DATAPERR(x) ((x) << S_PIOREQ_BAR2DATAPERR)
9217 #define F_PIOREQ_BAR2DATAPERR    V_PIOREQ_BAR2DATAPERR(1U)
9218 
9219 #define S_PIOREQ_MEMDATAPERR    4
9220 #define V_PIOREQ_MEMDATAPERR(x) ((x) << S_PIOREQ_MEMDATAPERR)
9221 #define F_PIOREQ_MEMDATAPERR    V_PIOREQ_MEMDATAPERR(1U)
9222 
9223 #define S_PIOREQ_PLMDATAPERR    3
9224 #define V_PIOREQ_PLMDATAPERR(x) ((x) << S_PIOREQ_PLMDATAPERR)
9225 #define F_PIOREQ_PLMDATAPERR    V_PIOREQ_PLMDATAPERR(1U)
9226 
9227 #define S_PIOCPL_CTLPERR    2
9228 #define V_PIOCPL_CTLPERR(x) ((x) << S_PIOCPL_CTLPERR)
9229 #define F_PIOCPL_CTLPERR    V_PIOCPL_CTLPERR(1U)
9230 
9231 #define S_PIOCPL_DATAPERR    1
9232 #define V_PIOCPL_DATAPERR(x) ((x) << S_PIOCPL_DATAPERR)
9233 #define F_PIOCPL_DATAPERR    V_PIOCPL_DATAPERR(1U)
9234 
9235 #define S_PIOCPL_PLMRSPPERR    0
9236 #define V_PIOCPL_PLMRSPPERR(x) ((x) << S_PIOCPL_PLMRSPPERR)
9237 #define F_PIOCPL_PLMRSPPERR    V_PIOCPL_PLMRSPPERR(1U)
9238 
9239 #define S_MA_RSPCTLPERR    26
9240 #define V_MA_RSPCTLPERR(x) ((x) << S_MA_RSPCTLPERR)
9241 #define F_MA_RSPCTLPERR    V_MA_RSPCTLPERR(1U)
9242 
9243 #define S_T6_IPRXDATA_VC0PERR    15
9244 #define V_T6_IPRXDATA_VC0PERR(x) ((x) << S_T6_IPRXDATA_VC0PERR)
9245 #define F_T6_IPRXDATA_VC0PERR    V_T6_IPRXDATA_VC0PERR(1U)
9246 
9247 #define S_T6_IPRXHDR_VC0PERR    14
9248 #define V_T6_IPRXHDR_VC0PERR(x) ((x) << S_T6_IPRXHDR_VC0PERR)
9249 #define F_T6_IPRXHDR_VC0PERR    V_T6_IPRXHDR_VC0PERR(1U)
9250 
9251 #define S_PIOCPL_VDMTXCTLPERR    13
9252 #define V_PIOCPL_VDMTXCTLPERR(x) ((x) << S_PIOCPL_VDMTXCTLPERR)
9253 #define F_PIOCPL_VDMTXCTLPERR    V_PIOCPL_VDMTXCTLPERR(1U)
9254 
9255 #define S_PIOCPL_VDMTXDATAPERR    12
9256 #define V_PIOCPL_VDMTXDATAPERR(x) ((x) << S_PIOCPL_VDMTXDATAPERR)
9257 #define F_PIOCPL_VDMTXDATAPERR    V_PIOCPL_VDMTXDATAPERR(1U)
9258 
9259 #define S_TGT1_MEM_PERR    28
9260 #define V_TGT1_MEM_PERR(x) ((x) << S_TGT1_MEM_PERR)
9261 #define F_TGT1_MEM_PERR    V_TGT1_MEM_PERR(1U)
9262 
9263 #define S_TGT2_MEM_PERR    27
9264 #define V_TGT2_MEM_PERR(x) ((x) << S_TGT2_MEM_PERR)
9265 #define F_TGT2_MEM_PERR    V_TGT2_MEM_PERR(1U)
9266 
9267 #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_2 0x59d4
9268 #define A_PCIE_RSP_ERR_INT_LOG_EN 0x59d4
9269 
9270 #define S_CPLSTATUSINTEN    12
9271 #define V_CPLSTATUSINTEN(x) ((x) << S_CPLSTATUSINTEN)
9272 #define F_CPLSTATUSINTEN    V_CPLSTATUSINTEN(1U)
9273 
9274 #define S_REQTIMEOUTINTEN    11
9275 #define V_REQTIMEOUTINTEN(x) ((x) << S_REQTIMEOUTINTEN)
9276 #define F_REQTIMEOUTINTEN    V_REQTIMEOUTINTEN(1U)
9277 
9278 #define S_DISABLEDINTEN    10
9279 #define V_DISABLEDINTEN(x) ((x) << S_DISABLEDINTEN)
9280 #define F_DISABLEDINTEN    V_DISABLEDINTEN(1U)
9281 
9282 #define S_RSPDROPFLRINTEN    9
9283 #define V_RSPDROPFLRINTEN(x) ((x) << S_RSPDROPFLRINTEN)
9284 #define F_RSPDROPFLRINTEN    V_RSPDROPFLRINTEN(1U)
9285 
9286 #define S_REQUNDERFLRINTEN    8
9287 #define V_REQUNDERFLRINTEN(x) ((x) << S_REQUNDERFLRINTEN)
9288 #define F_REQUNDERFLRINTEN    V_REQUNDERFLRINTEN(1U)
9289 
9290 #define S_CPLSTATUSLOGEN    4
9291 #define V_CPLSTATUSLOGEN(x) ((x) << S_CPLSTATUSLOGEN)
9292 #define F_CPLSTATUSLOGEN    V_CPLSTATUSLOGEN(1U)
9293 
9294 #define S_TIMEOUTLOGEN    3
9295 #define V_TIMEOUTLOGEN(x) ((x) << S_TIMEOUTLOGEN)
9296 #define F_TIMEOUTLOGEN    V_TIMEOUTLOGEN(1U)
9297 
9298 #define S_DISABLEDLOGEN    2
9299 #define V_DISABLEDLOGEN(x) ((x) << S_DISABLEDLOGEN)
9300 #define F_DISABLEDLOGEN    V_DISABLEDLOGEN(1U)
9301 
9302 #define S_RSPDROPFLRLOGEN    1
9303 #define V_RSPDROPFLRLOGEN(x) ((x) << S_RSPDROPFLRLOGEN)
9304 #define F_RSPDROPFLRLOGEN    V_RSPDROPFLRLOGEN(1U)
9305 
9306 #define S_REQUNDERFLRLOGEN    0
9307 #define V_REQUNDERFLRLOGEN(x) ((x) << S_REQUNDERFLRLOGEN)
9308 #define F_REQUNDERFLRLOGEN    V_REQUNDERFLRLOGEN(1U)
9309 
9310 #define A_PCIE_RSP_ERR_LOG1 0x59d8
9311 
9312 #define S_REQTAG    25
9313 #define M_REQTAG    0x7fU
9314 #define V_REQTAG(x) ((x) << S_REQTAG)
9315 #define G_REQTAG(x) (((x) >> S_REQTAG) & M_REQTAG)
9316 
9317 #define S_CID    22
9318 #define M_CID    0x7U
9319 #define V_CID(x) ((x) << S_CID)
9320 #define G_CID(x) (((x) >> S_CID) & M_CID)
9321 
9322 #define S_CHNUM    19
9323 #define M_CHNUM    0x7U
9324 #define V_CHNUM(x) ((x) << S_CHNUM)
9325 #define G_CHNUM(x) (((x) >> S_CHNUM) & M_CHNUM)
9326 
9327 #define S_BYTELEN    6
9328 #define M_BYTELEN    0x1fffU
9329 #define V_BYTELEN(x) ((x) << S_BYTELEN)
9330 #define G_BYTELEN(x) (((x) >> S_BYTELEN) & M_BYTELEN)
9331 
9332 #define S_REASON    3
9333 #define M_REASON    0x7U
9334 #define V_REASON(x) ((x) << S_REASON)
9335 #define G_REASON(x) (((x) >> S_REASON) & M_REASON)
9336 
9337 #define S_CPLSTATUS    0
9338 #define M_CPLSTATUS    0x7U
9339 #define V_CPLSTATUS(x) ((x) << S_CPLSTATUS)
9340 #define G_CPLSTATUS(x) (((x) >> S_CPLSTATUS) & M_CPLSTATUS)
9341 
9342 #define A_PCIE_RSP_ERR_LOG2 0x59dc
9343 
9344 #define S_LOGVALID    31
9345 #define V_LOGVALID(x) ((x) << S_LOGVALID)
9346 #define F_LOGVALID    V_LOGVALID(1U)
9347 
9348 #define S_ADDR10B    8
9349 #define M_ADDR10B    0x3ffU
9350 #define V_ADDR10B(x) ((x) << S_ADDR10B)
9351 #define G_ADDR10B(x) (((x) >> S_ADDR10B) & M_ADDR10B)
9352 
9353 #define S_REQVFID    0
9354 #define M_REQVFID    0xffU
9355 #define V_REQVFID(x) ((x) << S_REQVFID)
9356 #define G_REQVFID(x) (((x) >> S_REQVFID) & M_REQVFID)
9357 
9358 #define S_T6_ADDR10B    9
9359 #define M_T6_ADDR10B    0x3ffU
9360 #define V_T6_ADDR10B(x) ((x) << S_T6_ADDR10B)
9361 #define G_T6_ADDR10B(x) (((x) >> S_T6_ADDR10B) & M_T6_ADDR10B)
9362 
9363 #define S_T6_REQVFID    0
9364 #define M_T6_REQVFID    0x1ffU
9365 #define V_T6_REQVFID(x) ((x) << S_T6_REQVFID)
9366 #define G_T6_REQVFID(x) (((x) >> S_T6_REQVFID) & M_T6_REQVFID)
9367 
9368 #define S_LOGADDR10B    9
9369 #define M_LOGADDR10B    0x3ffU
9370 #define V_LOGADDR10B(x) ((x) << S_LOGADDR10B)
9371 #define G_LOGADDR10B(x) (((x) >> S_LOGADDR10B) & M_LOGADDR10B)
9372 
9373 #define S_LOGREQVFID    0
9374 #define M_LOGREQVFID    0x1ffU
9375 #define V_LOGREQVFID(x) ((x) << S_LOGREQVFID)
9376 #define G_LOGREQVFID(x) (((x) >> S_LOGREQVFID) & M_LOGREQVFID)
9377 
9378 #define A_PCIE_CHANGESET 0x59fc
9379 #define A_PCIE_REVISION 0x5a00
9380 #define A_PCIE_PDEBUG_INDEX 0x5a04
9381 
9382 #define S_PDEBUGSELH    16
9383 #define M_PDEBUGSELH    0x3fU
9384 #define V_PDEBUGSELH(x) ((x) << S_PDEBUGSELH)
9385 #define G_PDEBUGSELH(x) (((x) >> S_PDEBUGSELH) & M_PDEBUGSELH)
9386 
9387 #define S_PDEBUGSELL    0
9388 #define M_PDEBUGSELL    0x3fU
9389 #define V_PDEBUGSELL(x) ((x) << S_PDEBUGSELL)
9390 #define G_PDEBUGSELL(x) (((x) >> S_PDEBUGSELL) & M_PDEBUGSELL)
9391 
9392 #define S_T6_PDEBUGSELH    16
9393 #define M_T6_PDEBUGSELH    0x7fU
9394 #define V_T6_PDEBUGSELH(x) ((x) << S_T6_PDEBUGSELH)
9395 #define G_T6_PDEBUGSELH(x) (((x) >> S_T6_PDEBUGSELH) & M_T6_PDEBUGSELH)
9396 
9397 #define S_T6_PDEBUGSELL    0
9398 #define M_T6_PDEBUGSELL    0x7fU
9399 #define V_T6_PDEBUGSELL(x) ((x) << S_T6_PDEBUGSELL)
9400 #define G_T6_PDEBUGSELL(x) (((x) >> S_T6_PDEBUGSELL) & M_T6_PDEBUGSELL)
9401 
9402 #define S_T7_1_PDEBUGSELH    16
9403 #define M_T7_1_PDEBUGSELH    0xffU
9404 #define V_T7_1_PDEBUGSELH(x) ((x) << S_T7_1_PDEBUGSELH)
9405 #define G_T7_1_PDEBUGSELH(x) (((x) >> S_T7_1_PDEBUGSELH) & M_T7_1_PDEBUGSELH)
9406 
9407 #define S_T7_1_PDEBUGSELL    0
9408 #define M_T7_1_PDEBUGSELL    0xffU
9409 #define V_T7_1_PDEBUGSELL(x) ((x) << S_T7_1_PDEBUGSELL)
9410 #define G_T7_1_PDEBUGSELL(x) (((x) >> S_T7_1_PDEBUGSELL) & M_T7_1_PDEBUGSELL)
9411 
9412 #define A_PCIE_PDEBUG_DATA_HIGH 0x5a08
9413 #define A_PCIE_PDEBUG_DATA_LOW 0x5a0c
9414 #define A_PCIE_CDEBUG_INDEX 0x5a10
9415 
9416 #define S_CDEBUGSELH    16
9417 #define M_CDEBUGSELH    0xffU
9418 #define V_CDEBUGSELH(x) ((x) << S_CDEBUGSELH)
9419 #define G_CDEBUGSELH(x) (((x) >> S_CDEBUGSELH) & M_CDEBUGSELH)
9420 
9421 #define S_CDEBUGSELL    0
9422 #define M_CDEBUGSELL    0xffU
9423 #define V_CDEBUGSELL(x) ((x) << S_CDEBUGSELL)
9424 #define G_CDEBUGSELL(x) (((x) >> S_CDEBUGSELL) & M_CDEBUGSELL)
9425 
9426 #define A_PCIE_CDEBUG_DATA_HIGH 0x5a14
9427 #define A_PCIE_CDEBUG_DATA_LOW 0x5a18
9428 #define A_PCIE_DMAW_SOP_CNT 0x5a1c
9429 
9430 #define S_CH3    24
9431 #define M_CH3    0xffU
9432 #define V_CH3(x) ((x) << S_CH3)
9433 #define G_CH3(x) (((x) >> S_CH3) & M_CH3)
9434 
9435 #define S_CH2    16
9436 #define M_CH2    0xffU
9437 #define V_CH2(x) ((x) << S_CH2)
9438 #define G_CH2(x) (((x) >> S_CH2) & M_CH2)
9439 
9440 #define S_CH1    8
9441 #define M_CH1    0xffU
9442 #define V_CH1(x) ((x) << S_CH1)
9443 #define G_CH1(x) (((x) >> S_CH1) & M_CH1)
9444 
9445 #define S_CH0    0
9446 #define M_CH0    0xffU
9447 #define V_CH0(x) ((x) << S_CH0)
9448 #define G_CH0(x) (((x) >> S_CH0) & M_CH0)
9449 
9450 #define A_PCIE_DMAW_EOP_CNT 0x5a20
9451 #define A_PCIE_DMAR_REQ_CNT 0x5a24
9452 #define A_PCIE_DMAR_RSP_SOP_CNT 0x5a28
9453 #define A_PCIE_DMAR_RSP_EOP_CNT 0x5a2c
9454 #define A_PCIE_DMAR_RSP_ERR_CNT 0x5a30
9455 #define A_PCIE_DMAI_CNT 0x5a34
9456 #define A_PCIE_CMDW_CNT 0x5a38
9457 
9458 #define S_CH1_EOP    24
9459 #define M_CH1_EOP    0xffU
9460 #define V_CH1_EOP(x) ((x) << S_CH1_EOP)
9461 #define G_CH1_EOP(x) (((x) >> S_CH1_EOP) & M_CH1_EOP)
9462 
9463 #define S_CH1_SOP    16
9464 #define M_CH1_SOP    0xffU
9465 #define V_CH1_SOP(x) ((x) << S_CH1_SOP)
9466 #define G_CH1_SOP(x) (((x) >> S_CH1_SOP) & M_CH1_SOP)
9467 
9468 #define S_CH0_EOP    8
9469 #define M_CH0_EOP    0xffU
9470 #define V_CH0_EOP(x) ((x) << S_CH0_EOP)
9471 #define G_CH0_EOP(x) (((x) >> S_CH0_EOP) & M_CH0_EOP)
9472 
9473 #define S_CH0_SOP    0
9474 #define M_CH0_SOP    0xffU
9475 #define V_CH0_SOP(x) ((x) << S_CH0_SOP)
9476 #define G_CH0_SOP(x) (((x) >> S_CH0_SOP) & M_CH0_SOP)
9477 
9478 #define A_PCIE_CMDR_REQ_CNT 0x5a3c
9479 #define A_PCIE_CMDR_RSP_CNT 0x5a40
9480 #define A_PCIE_CMDR_RSP_ERR_CNT 0x5a44
9481 #define A_PCIE_HMA_REQ_CNT 0x5a48
9482 
9483 #define S_CH0_READ    16
9484 #define M_CH0_READ    0xffU
9485 #define V_CH0_READ(x) ((x) << S_CH0_READ)
9486 #define G_CH0_READ(x) (((x) >> S_CH0_READ) & M_CH0_READ)
9487 
9488 #define S_CH0_WEOP    8
9489 #define M_CH0_WEOP    0xffU
9490 #define V_CH0_WEOP(x) ((x) << S_CH0_WEOP)
9491 #define G_CH0_WEOP(x) (((x) >> S_CH0_WEOP) & M_CH0_WEOP)
9492 
9493 #define S_CH0_WSOP    0
9494 #define M_CH0_WSOP    0xffU
9495 #define V_CH0_WSOP(x) ((x) << S_CH0_WSOP)
9496 #define G_CH0_WSOP(x) (((x) >> S_CH0_WSOP) & M_CH0_WSOP)
9497 
9498 #define A_PCIE_HMA_RSP_CNT 0x5a4c
9499 #define A_PCIE_DMA10_RSP_FREE 0x5a50
9500 
9501 #define S_CH1_RSP_FREE    16
9502 #define M_CH1_RSP_FREE    0xfffU
9503 #define V_CH1_RSP_FREE(x) ((x) << S_CH1_RSP_FREE)
9504 #define G_CH1_RSP_FREE(x) (((x) >> S_CH1_RSP_FREE) & M_CH1_RSP_FREE)
9505 
9506 #define S_CH0_RSP_FREE    0
9507 #define M_CH0_RSP_FREE    0xfffU
9508 #define V_CH0_RSP_FREE(x) ((x) << S_CH0_RSP_FREE)
9509 #define G_CH0_RSP_FREE(x) (((x) >> S_CH0_RSP_FREE) & M_CH0_RSP_FREE)
9510 
9511 #define A_PCIE_DMA32_RSP_FREE 0x5a54
9512 
9513 #define S_CH3_RSP_FREE    16
9514 #define M_CH3_RSP_FREE    0xfffU
9515 #define V_CH3_RSP_FREE(x) ((x) << S_CH3_RSP_FREE)
9516 #define G_CH3_RSP_FREE(x) (((x) >> S_CH3_RSP_FREE) & M_CH3_RSP_FREE)
9517 
9518 #define S_CH2_RSP_FREE    0
9519 #define M_CH2_RSP_FREE    0xfffU
9520 #define V_CH2_RSP_FREE(x) ((x) << S_CH2_RSP_FREE)
9521 #define G_CH2_RSP_FREE(x) (((x) >> S_CH2_RSP_FREE) & M_CH2_RSP_FREE)
9522 
9523 #define A_PCIE_CMD_RSP_FREE 0x5a58
9524 
9525 #define S_CMD_CH1_RSP_FREE    16
9526 #define M_CMD_CH1_RSP_FREE    0x7fU
9527 #define V_CMD_CH1_RSP_FREE(x) ((x) << S_CMD_CH1_RSP_FREE)
9528 #define G_CMD_CH1_RSP_FREE(x) (((x) >> S_CMD_CH1_RSP_FREE) & M_CMD_CH1_RSP_FREE)
9529 
9530 #define S_CMD_CH0_RSP_FREE    0
9531 #define M_CMD_CH0_RSP_FREE    0x7fU
9532 #define V_CMD_CH0_RSP_FREE(x) ((x) << S_CMD_CH0_RSP_FREE)
9533 #define G_CMD_CH0_RSP_FREE(x) (((x) >> S_CMD_CH0_RSP_FREE) & M_CMD_CH0_RSP_FREE)
9534 
9535 #define A_PCIE_HMA_RSP_FREE 0x5a5c
9536 #define A_PCIE_BUS_MST_STAT_0 0x5a60
9537 #define A_PCIE_BUS_MST_STAT_1 0x5a64
9538 #define A_PCIE_BUS_MST_STAT_2 0x5a68
9539 #define A_PCIE_BUS_MST_STAT_3 0x5a6c
9540 #define A_PCIE_BUS_MST_STAT_4 0x5a70
9541 
9542 #define S_BUSMST_135_128    0
9543 #define M_BUSMST_135_128    0xffU
9544 #define V_BUSMST_135_128(x) ((x) << S_BUSMST_135_128)
9545 #define G_BUSMST_135_128(x) (((x) >> S_BUSMST_135_128) & M_BUSMST_135_128)
9546 
9547 #define A_PCIE_BUS_MST_STAT_5 0x5a74
9548 #define A_PCIE_BUS_MST_STAT_6 0x5a78
9549 #define A_PCIE_BUS_MST_STAT_7 0x5a7c
9550 #define A_PCIE_RSP_ERR_STAT_0 0x5a80
9551 #define A_PCIE_RSP_ERR_STAT_1 0x5a84
9552 #define A_PCIE_RSP_ERR_STAT_2 0x5a88
9553 #define A_PCIE_RSP_ERR_STAT_3 0x5a8c
9554 #define A_PCIE_RSP_ERR_STAT_4 0x5a90
9555 
9556 #define S_RSPERR_135_128    0
9557 #define M_RSPERR_135_128    0xffU
9558 #define V_RSPERR_135_128(x) ((x) << S_RSPERR_135_128)
9559 #define G_RSPERR_135_128(x) (((x) >> S_RSPERR_135_128) & M_RSPERR_135_128)
9560 
9561 #define A_PCIE_RSP_ERR_STAT_5 0x5a94
9562 #define A_PCIE_DBI_TIMEOUT_CTL 0x5a94
9563 
9564 #define S_DBI_TIMER    0
9565 #define M_DBI_TIMER    0xffffU
9566 #define V_DBI_TIMER(x) ((x) << S_DBI_TIMER)
9567 #define G_DBI_TIMER(x) (((x) >> S_DBI_TIMER) & M_DBI_TIMER)
9568 
9569 #define A_PCIE_RSP_ERR_STAT_6 0x5a98
9570 #define A_PCIE_DBI_TIMEOUT_STATUS0 0x5a98
9571 #define A_PCIE_RSP_ERR_STAT_7 0x5a9c
9572 #define A_PCIE_DBI_TIMEOUT_STATUS1 0x5a9c
9573 
9574 #define S_SOURCE    16
9575 #define M_SOURCE    0x3U
9576 #define V_SOURCE(x) ((x) << S_SOURCE)
9577 #define G_SOURCE(x) (((x) >> S_SOURCE) & M_SOURCE)
9578 
9579 #define S_DBI_WRITE    12
9580 #define M_DBI_WRITE    0xfU
9581 #define V_DBI_WRITE(x) ((x) << S_DBI_WRITE)
9582 #define G_DBI_WRITE(x) (((x) >> S_DBI_WRITE) & M_DBI_WRITE)
9583 
9584 #define S_DBI_CS2    11
9585 #define V_DBI_CS2(x) ((x) << S_DBI_CS2)
9586 #define F_DBI_CS2    V_DBI_CS2(1U)
9587 
9588 #define S_DBI_PF    8
9589 #define M_DBI_PF    0x7U
9590 #define V_DBI_PF(x) ((x) << S_DBI_PF)
9591 #define G_DBI_PF(x) (((x) >> S_DBI_PF) & M_DBI_PF)
9592 
9593 #define S_PL_TOVFVLD    7
9594 #define V_PL_TOVFVLD(x) ((x) << S_PL_TOVFVLD)
9595 #define F_PL_TOVFVLD    V_PL_TOVFVLD(1U)
9596 
9597 #define S_PL_TOVF    0
9598 #define M_PL_TOVF    0x7fU
9599 #define V_PL_TOVF(x) ((x) << S_PL_TOVF)
9600 #define G_PL_TOVF(x) (((x) >> S_PL_TOVF) & M_PL_TOVF)
9601 
9602 #define S_T6_SOURCE    17
9603 #define M_T6_SOURCE    0x3U
9604 #define V_T6_SOURCE(x) ((x) << S_T6_SOURCE)
9605 #define G_T6_SOURCE(x) (((x) >> S_T6_SOURCE) & M_T6_SOURCE)
9606 
9607 #define S_T6_DBI_WRITE    13
9608 #define M_T6_DBI_WRITE    0xfU
9609 #define V_T6_DBI_WRITE(x) ((x) << S_T6_DBI_WRITE)
9610 #define G_T6_DBI_WRITE(x) (((x) >> S_T6_DBI_WRITE) & M_T6_DBI_WRITE)
9611 
9612 #define S_T6_DBI_CS2    12
9613 #define V_T6_DBI_CS2(x) ((x) << S_T6_DBI_CS2)
9614 #define F_T6_DBI_CS2    V_T6_DBI_CS2(1U)
9615 
9616 #define S_T6_DBI_PF    9
9617 #define M_T6_DBI_PF    0x7U
9618 #define V_T6_DBI_PF(x) ((x) << S_T6_DBI_PF)
9619 #define G_T6_DBI_PF(x) (((x) >> S_T6_DBI_PF) & M_T6_DBI_PF)
9620 
9621 #define S_T6_PL_TOVFVLD    8
9622 #define V_T6_PL_TOVFVLD(x) ((x) << S_T6_PL_TOVFVLD)
9623 #define F_T6_PL_TOVFVLD    V_T6_PL_TOVFVLD(1U)
9624 
9625 #define S_T6_PL_TOVF    0
9626 #define M_T6_PL_TOVF    0xffU
9627 #define V_T6_PL_TOVF(x) ((x) << S_T6_PL_TOVF)
9628 #define G_T6_PL_TOVF(x) (((x) >> S_T6_PL_TOVF) & M_T6_PL_TOVF)
9629 
9630 #define A_PCIE_MSI_EN_0 0x5aa0
9631 #define A_PCIE_MSI_EN_1 0x5aa4
9632 #define A_PCIE_MSI_EN_2 0x5aa8
9633 #define A_PCIE_MSI_EN_3 0x5aac
9634 #define A_PCIE_MSI_EN_4 0x5ab0
9635 #define A_PCIE_MSI_EN_5 0x5ab4
9636 #define A_PCIE_MSI_EN_6 0x5ab8
9637 #define A_PCIE_MSI_EN_7 0x5abc
9638 #define A_PCIE_MSIX_EN_0 0x5ac0
9639 #define A_PCIE_MSIX_EN_1 0x5ac4
9640 #define A_PCIE_MSIX_EN_2 0x5ac8
9641 #define A_PCIE_MSIX_EN_3 0x5acc
9642 #define A_PCIE_MSIX_EN_4 0x5ad0
9643 #define A_PCIE_MSIX_EN_5 0x5ad4
9644 #define A_PCIE_MSIX_EN_6 0x5ad8
9645 #define A_PCIE_MSIX_EN_7 0x5adc
9646 #define A_PCIE_DMA_BUF_CTL 0x5ae0
9647 
9648 #define S_BUFRDCNT    18
9649 #define M_BUFRDCNT    0x3fffU
9650 #define V_BUFRDCNT(x) ((x) << S_BUFRDCNT)
9651 #define G_BUFRDCNT(x) (((x) >> S_BUFRDCNT) & M_BUFRDCNT)
9652 
9653 #define S_BUFWRCNT    9
9654 #define M_BUFWRCNT    0x1ffU
9655 #define V_BUFWRCNT(x) ((x) << S_BUFWRCNT)
9656 #define G_BUFWRCNT(x) (((x) >> S_BUFWRCNT) & M_BUFWRCNT)
9657 
9658 #define S_MAXBUFWRREQ    0
9659 #define M_MAXBUFWRREQ    0x1ffU
9660 #define V_MAXBUFWRREQ(x) ((x) << S_MAXBUFWRREQ)
9661 #define G_MAXBUFWRREQ(x) (((x) >> S_MAXBUFWRREQ) & M_MAXBUFWRREQ)
9662 
9663 #define A_PCIE_PB_CTL 0x5b94
9664 
9665 #define S_PB_SEL    16
9666 #define M_PB_SEL    0xffU
9667 #define V_PB_SEL(x) ((x) << S_PB_SEL)
9668 #define G_PB_SEL(x) (((x) >> S_PB_SEL) & M_PB_SEL)
9669 
9670 #define S_PB_SELREG    8
9671 #define M_PB_SELREG    0xffU
9672 #define V_PB_SELREG(x) ((x) << S_PB_SELREG)
9673 #define G_PB_SELREG(x) (((x) >> S_PB_SELREG) & M_PB_SELREG)
9674 
9675 #define S_PB_FUNC    0
9676 #define M_PB_FUNC    0x7U
9677 #define V_PB_FUNC(x) ((x) << S_PB_FUNC)
9678 #define G_PB_FUNC(x) (((x) >> S_PB_FUNC) & M_PB_FUNC)
9679 
9680 #define A_PCIE_PB_DATA 0x5b98
9681 #define A_PCIE_CUR_LINK 0x5b9c
9682 
9683 #define S_CFGINITCOEFFDONESEEN    22
9684 #define V_CFGINITCOEFFDONESEEN(x) ((x) << S_CFGINITCOEFFDONESEEN)
9685 #define F_CFGINITCOEFFDONESEEN    V_CFGINITCOEFFDONESEEN(1U)
9686 
9687 #define S_CFGINITCOEFFDONE    21
9688 #define V_CFGINITCOEFFDONE(x) ((x) << S_CFGINITCOEFFDONE)
9689 #define F_CFGINITCOEFFDONE    V_CFGINITCOEFFDONE(1U)
9690 
9691 #define S_XMLH_LINK_UP    20
9692 #define V_XMLH_LINK_UP(x) ((x) << S_XMLH_LINK_UP)
9693 #define F_XMLH_LINK_UP    V_XMLH_LINK_UP(1U)
9694 
9695 #define S_PM_LINKST_IN_L0S    19
9696 #define V_PM_LINKST_IN_L0S(x) ((x) << S_PM_LINKST_IN_L0S)
9697 #define F_PM_LINKST_IN_L0S    V_PM_LINKST_IN_L0S(1U)
9698 
9699 #define S_PM_LINKST_IN_L1    18
9700 #define V_PM_LINKST_IN_L1(x) ((x) << S_PM_LINKST_IN_L1)
9701 #define F_PM_LINKST_IN_L1    V_PM_LINKST_IN_L1(1U)
9702 
9703 #define S_PM_LINKST_IN_L2    17
9704 #define V_PM_LINKST_IN_L2(x) ((x) << S_PM_LINKST_IN_L2)
9705 #define F_PM_LINKST_IN_L2    V_PM_LINKST_IN_L2(1U)
9706 
9707 #define S_PM_LINKST_L2_EXIT    16
9708 #define V_PM_LINKST_L2_EXIT(x) ((x) << S_PM_LINKST_L2_EXIT)
9709 #define F_PM_LINKST_L2_EXIT    V_PM_LINKST_L2_EXIT(1U)
9710 
9711 #define S_XMLH_IN_RL0S    15
9712 #define V_XMLH_IN_RL0S(x) ((x) << S_XMLH_IN_RL0S)
9713 #define F_XMLH_IN_RL0S    V_XMLH_IN_RL0S(1U)
9714 
9715 #define S_XMLH_LTSSM_STATE_RCVRY_EQ    14
9716 #define V_XMLH_LTSSM_STATE_RCVRY_EQ(x) ((x) << S_XMLH_LTSSM_STATE_RCVRY_EQ)
9717 #define F_XMLH_LTSSM_STATE_RCVRY_EQ    V_XMLH_LTSSM_STATE_RCVRY_EQ(1U)
9718 
9719 #define S_NEGOTIATEDWIDTH    8
9720 #define M_NEGOTIATEDWIDTH    0x3fU
9721 #define V_NEGOTIATEDWIDTH(x) ((x) << S_NEGOTIATEDWIDTH)
9722 #define G_NEGOTIATEDWIDTH(x) (((x) >> S_NEGOTIATEDWIDTH) & M_NEGOTIATEDWIDTH)
9723 
9724 #define S_ACTIVELANES    0
9725 #define M_ACTIVELANES    0xffU
9726 #define V_ACTIVELANES(x) ((x) << S_ACTIVELANES)
9727 #define G_ACTIVELANES(x) (((x) >> S_ACTIVELANES) & M_ACTIVELANES)
9728 
9729 #define A_PCIE_PHY_REQRXPWR 0x5ba0
9730 
9731 #define S_LNH_RXSTATEDONE    31
9732 #define V_LNH_RXSTATEDONE(x) ((x) << S_LNH_RXSTATEDONE)
9733 #define F_LNH_RXSTATEDONE    V_LNH_RXSTATEDONE(1U)
9734 
9735 #define S_LNH_RXSTATEREQ    30
9736 #define V_LNH_RXSTATEREQ(x) ((x) << S_LNH_RXSTATEREQ)
9737 #define F_LNH_RXSTATEREQ    V_LNH_RXSTATEREQ(1U)
9738 
9739 #define S_LNH_RXPWRSTATE    28
9740 #define M_LNH_RXPWRSTATE    0x3U
9741 #define V_LNH_RXPWRSTATE(x) ((x) << S_LNH_RXPWRSTATE)
9742 #define G_LNH_RXPWRSTATE(x) (((x) >> S_LNH_RXPWRSTATE) & M_LNH_RXPWRSTATE)
9743 
9744 #define S_LNG_RXSTATEDONE    27
9745 #define V_LNG_RXSTATEDONE(x) ((x) << S_LNG_RXSTATEDONE)
9746 #define F_LNG_RXSTATEDONE    V_LNG_RXSTATEDONE(1U)
9747 
9748 #define S_LNG_RXSTATEREQ    26
9749 #define V_LNG_RXSTATEREQ(x) ((x) << S_LNG_RXSTATEREQ)
9750 #define F_LNG_RXSTATEREQ    V_LNG_RXSTATEREQ(1U)
9751 
9752 #define S_LNG_RXPWRSTATE    24
9753 #define M_LNG_RXPWRSTATE    0x3U
9754 #define V_LNG_RXPWRSTATE(x) ((x) << S_LNG_RXPWRSTATE)
9755 #define G_LNG_RXPWRSTATE(x) (((x) >> S_LNG_RXPWRSTATE) & M_LNG_RXPWRSTATE)
9756 
9757 #define S_LNF_RXSTATEDONE    23
9758 #define V_LNF_RXSTATEDONE(x) ((x) << S_LNF_RXSTATEDONE)
9759 #define F_LNF_RXSTATEDONE    V_LNF_RXSTATEDONE(1U)
9760 
9761 #define S_LNF_RXSTATEREQ    22
9762 #define V_LNF_RXSTATEREQ(x) ((x) << S_LNF_RXSTATEREQ)
9763 #define F_LNF_RXSTATEREQ    V_LNF_RXSTATEREQ(1U)
9764 
9765 #define S_LNF_RXPWRSTATE    20
9766 #define M_LNF_RXPWRSTATE    0x3U
9767 #define V_LNF_RXPWRSTATE(x) ((x) << S_LNF_RXPWRSTATE)
9768 #define G_LNF_RXPWRSTATE(x) (((x) >> S_LNF_RXPWRSTATE) & M_LNF_RXPWRSTATE)
9769 
9770 #define S_LNE_RXSTATEDONE    19
9771 #define V_LNE_RXSTATEDONE(x) ((x) << S_LNE_RXSTATEDONE)
9772 #define F_LNE_RXSTATEDONE    V_LNE_RXSTATEDONE(1U)
9773 
9774 #define S_LNE_RXSTATEREQ    18
9775 #define V_LNE_RXSTATEREQ(x) ((x) << S_LNE_RXSTATEREQ)
9776 #define F_LNE_RXSTATEREQ    V_LNE_RXSTATEREQ(1U)
9777 
9778 #define S_LNE_RXPWRSTATE    16
9779 #define M_LNE_RXPWRSTATE    0x3U
9780 #define V_LNE_RXPWRSTATE(x) ((x) << S_LNE_RXPWRSTATE)
9781 #define G_LNE_RXPWRSTATE(x) (((x) >> S_LNE_RXPWRSTATE) & M_LNE_RXPWRSTATE)
9782 
9783 #define S_LND_RXSTATEDONE    15
9784 #define V_LND_RXSTATEDONE(x) ((x) << S_LND_RXSTATEDONE)
9785 #define F_LND_RXSTATEDONE    V_LND_RXSTATEDONE(1U)
9786 
9787 #define S_LND_RXSTATEREQ    14
9788 #define V_LND_RXSTATEREQ(x) ((x) << S_LND_RXSTATEREQ)
9789 #define F_LND_RXSTATEREQ    V_LND_RXSTATEREQ(1U)
9790 
9791 #define S_LND_RXPWRSTATE    12
9792 #define M_LND_RXPWRSTATE    0x3U
9793 #define V_LND_RXPWRSTATE(x) ((x) << S_LND_RXPWRSTATE)
9794 #define G_LND_RXPWRSTATE(x) (((x) >> S_LND_RXPWRSTATE) & M_LND_RXPWRSTATE)
9795 
9796 #define S_LNC_RXSTATEDONE    11
9797 #define V_LNC_RXSTATEDONE(x) ((x) << S_LNC_RXSTATEDONE)
9798 #define F_LNC_RXSTATEDONE    V_LNC_RXSTATEDONE(1U)
9799 
9800 #define S_LNC_RXSTATEREQ    10
9801 #define V_LNC_RXSTATEREQ(x) ((x) << S_LNC_RXSTATEREQ)
9802 #define F_LNC_RXSTATEREQ    V_LNC_RXSTATEREQ(1U)
9803 
9804 #define S_LNC_RXPWRSTATE    8
9805 #define M_LNC_RXPWRSTATE    0x3U
9806 #define V_LNC_RXPWRSTATE(x) ((x) << S_LNC_RXPWRSTATE)
9807 #define G_LNC_RXPWRSTATE(x) (((x) >> S_LNC_RXPWRSTATE) & M_LNC_RXPWRSTATE)
9808 
9809 #define S_LNB_RXSTATEDONE    7
9810 #define V_LNB_RXSTATEDONE(x) ((x) << S_LNB_RXSTATEDONE)
9811 #define F_LNB_RXSTATEDONE    V_LNB_RXSTATEDONE(1U)
9812 
9813 #define S_LNB_RXSTATEREQ    6
9814 #define V_LNB_RXSTATEREQ(x) ((x) << S_LNB_RXSTATEREQ)
9815 #define F_LNB_RXSTATEREQ    V_LNB_RXSTATEREQ(1U)
9816 
9817 #define S_LNB_RXPWRSTATE    4
9818 #define M_LNB_RXPWRSTATE    0x3U
9819 #define V_LNB_RXPWRSTATE(x) ((x) << S_LNB_RXPWRSTATE)
9820 #define G_LNB_RXPWRSTATE(x) (((x) >> S_LNB_RXPWRSTATE) & M_LNB_RXPWRSTATE)
9821 
9822 #define S_LNA_RXSTATEDONE    3
9823 #define V_LNA_RXSTATEDONE(x) ((x) << S_LNA_RXSTATEDONE)
9824 #define F_LNA_RXSTATEDONE    V_LNA_RXSTATEDONE(1U)
9825 
9826 #define S_LNA_RXSTATEREQ    2
9827 #define V_LNA_RXSTATEREQ(x) ((x) << S_LNA_RXSTATEREQ)
9828 #define F_LNA_RXSTATEREQ    V_LNA_RXSTATEREQ(1U)
9829 
9830 #define S_LNA_RXPWRSTATE    0
9831 #define M_LNA_RXPWRSTATE    0x3U
9832 #define V_LNA_RXPWRSTATE(x) ((x) << S_LNA_RXPWRSTATE)
9833 #define G_LNA_RXPWRSTATE(x) (((x) >> S_LNA_RXPWRSTATE) & M_LNA_RXPWRSTATE)
9834 
9835 #define S_REQ_LNH_RXSTATEDONE    31
9836 #define V_REQ_LNH_RXSTATEDONE(x) ((x) << S_REQ_LNH_RXSTATEDONE)
9837 #define F_REQ_LNH_RXSTATEDONE    V_REQ_LNH_RXSTATEDONE(1U)
9838 
9839 #define S_REQ_LNH_RXSTATEREQ    30
9840 #define V_REQ_LNH_RXSTATEREQ(x) ((x) << S_REQ_LNH_RXSTATEREQ)
9841 #define F_REQ_LNH_RXSTATEREQ    V_REQ_LNH_RXSTATEREQ(1U)
9842 
9843 #define S_REQ_LNH_RXPWRSTATE    28
9844 #define M_REQ_LNH_RXPWRSTATE    0x3U
9845 #define V_REQ_LNH_RXPWRSTATE(x) ((x) << S_REQ_LNH_RXPWRSTATE)
9846 #define G_REQ_LNH_RXPWRSTATE(x) (((x) >> S_REQ_LNH_RXPWRSTATE) & M_REQ_LNH_RXPWRSTATE)
9847 
9848 #define S_REQ_LNG_RXSTATEDONE    27
9849 #define V_REQ_LNG_RXSTATEDONE(x) ((x) << S_REQ_LNG_RXSTATEDONE)
9850 #define F_REQ_LNG_RXSTATEDONE    V_REQ_LNG_RXSTATEDONE(1U)
9851 
9852 #define S_REQ_LNG_RXSTATEREQ    26
9853 #define V_REQ_LNG_RXSTATEREQ(x) ((x) << S_REQ_LNG_RXSTATEREQ)
9854 #define F_REQ_LNG_RXSTATEREQ    V_REQ_LNG_RXSTATEREQ(1U)
9855 
9856 #define S_REQ_LNG_RXPWRSTATE    24
9857 #define M_REQ_LNG_RXPWRSTATE    0x3U
9858 #define V_REQ_LNG_RXPWRSTATE(x) ((x) << S_REQ_LNG_RXPWRSTATE)
9859 #define G_REQ_LNG_RXPWRSTATE(x) (((x) >> S_REQ_LNG_RXPWRSTATE) & M_REQ_LNG_RXPWRSTATE)
9860 
9861 #define S_REQ_LNF_RXSTATEDONE    23
9862 #define V_REQ_LNF_RXSTATEDONE(x) ((x) << S_REQ_LNF_RXSTATEDONE)
9863 #define F_REQ_LNF_RXSTATEDONE    V_REQ_LNF_RXSTATEDONE(1U)
9864 
9865 #define S_REQ_LNF_RXSTATEREQ    22
9866 #define V_REQ_LNF_RXSTATEREQ(x) ((x) << S_REQ_LNF_RXSTATEREQ)
9867 #define F_REQ_LNF_RXSTATEREQ    V_REQ_LNF_RXSTATEREQ(1U)
9868 
9869 #define S_REQ_LNF_RXPWRSTATE    20
9870 #define M_REQ_LNF_RXPWRSTATE    0x3U
9871 #define V_REQ_LNF_RXPWRSTATE(x) ((x) << S_REQ_LNF_RXPWRSTATE)
9872 #define G_REQ_LNF_RXPWRSTATE(x) (((x) >> S_REQ_LNF_RXPWRSTATE) & M_REQ_LNF_RXPWRSTATE)
9873 
9874 #define S_REQ_LNE_RXSTATEDONE    19
9875 #define V_REQ_LNE_RXSTATEDONE(x) ((x) << S_REQ_LNE_RXSTATEDONE)
9876 #define F_REQ_LNE_RXSTATEDONE    V_REQ_LNE_RXSTATEDONE(1U)
9877 
9878 #define S_REQ_LNE_RXSTATEREQ    18
9879 #define V_REQ_LNE_RXSTATEREQ(x) ((x) << S_REQ_LNE_RXSTATEREQ)
9880 #define F_REQ_LNE_RXSTATEREQ    V_REQ_LNE_RXSTATEREQ(1U)
9881 
9882 #define S_REQ_LNE_RXPWRSTATE    16
9883 #define M_REQ_LNE_RXPWRSTATE    0x3U
9884 #define V_REQ_LNE_RXPWRSTATE(x) ((x) << S_REQ_LNE_RXPWRSTATE)
9885 #define G_REQ_LNE_RXPWRSTATE(x) (((x) >> S_REQ_LNE_RXPWRSTATE) & M_REQ_LNE_RXPWRSTATE)
9886 
9887 #define S_REQ_LND_RXSTATEDONE    15
9888 #define V_REQ_LND_RXSTATEDONE(x) ((x) << S_REQ_LND_RXSTATEDONE)
9889 #define F_REQ_LND_RXSTATEDONE    V_REQ_LND_RXSTATEDONE(1U)
9890 
9891 #define S_REQ_LND_RXSTATEREQ    14
9892 #define V_REQ_LND_RXSTATEREQ(x) ((x) << S_REQ_LND_RXSTATEREQ)
9893 #define F_REQ_LND_RXSTATEREQ    V_REQ_LND_RXSTATEREQ(1U)
9894 
9895 #define S_REQ_LND_RXPWRSTATE    12
9896 #define M_REQ_LND_RXPWRSTATE    0x3U
9897 #define V_REQ_LND_RXPWRSTATE(x) ((x) << S_REQ_LND_RXPWRSTATE)
9898 #define G_REQ_LND_RXPWRSTATE(x) (((x) >> S_REQ_LND_RXPWRSTATE) & M_REQ_LND_RXPWRSTATE)
9899 
9900 #define S_REQ_LNC_RXSTATEDONE    11
9901 #define V_REQ_LNC_RXSTATEDONE(x) ((x) << S_REQ_LNC_RXSTATEDONE)
9902 #define F_REQ_LNC_RXSTATEDONE    V_REQ_LNC_RXSTATEDONE(1U)
9903 
9904 #define S_REQ_LNC_RXSTATEREQ    10
9905 #define V_REQ_LNC_RXSTATEREQ(x) ((x) << S_REQ_LNC_RXSTATEREQ)
9906 #define F_REQ_LNC_RXSTATEREQ    V_REQ_LNC_RXSTATEREQ(1U)
9907 
9908 #define S_REQ_LNC_RXPWRSTATE    8
9909 #define M_REQ_LNC_RXPWRSTATE    0x3U
9910 #define V_REQ_LNC_RXPWRSTATE(x) ((x) << S_REQ_LNC_RXPWRSTATE)
9911 #define G_REQ_LNC_RXPWRSTATE(x) (((x) >> S_REQ_LNC_RXPWRSTATE) & M_REQ_LNC_RXPWRSTATE)
9912 
9913 #define S_REQ_LNB_RXSTATEDONE    7
9914 #define V_REQ_LNB_RXSTATEDONE(x) ((x) << S_REQ_LNB_RXSTATEDONE)
9915 #define F_REQ_LNB_RXSTATEDONE    V_REQ_LNB_RXSTATEDONE(1U)
9916 
9917 #define S_REQ_LNB_RXSTATEREQ    6
9918 #define V_REQ_LNB_RXSTATEREQ(x) ((x) << S_REQ_LNB_RXSTATEREQ)
9919 #define F_REQ_LNB_RXSTATEREQ    V_REQ_LNB_RXSTATEREQ(1U)
9920 
9921 #define S_REQ_LNB_RXPWRSTATE    4
9922 #define M_REQ_LNB_RXPWRSTATE    0x3U
9923 #define V_REQ_LNB_RXPWRSTATE(x) ((x) << S_REQ_LNB_RXPWRSTATE)
9924 #define G_REQ_LNB_RXPWRSTATE(x) (((x) >> S_REQ_LNB_RXPWRSTATE) & M_REQ_LNB_RXPWRSTATE)
9925 
9926 #define S_REQ_LNA_RXSTATEDONE    3
9927 #define V_REQ_LNA_RXSTATEDONE(x) ((x) << S_REQ_LNA_RXSTATEDONE)
9928 #define F_REQ_LNA_RXSTATEDONE    V_REQ_LNA_RXSTATEDONE(1U)
9929 
9930 #define S_REQ_LNA_RXSTATEREQ    2
9931 #define V_REQ_LNA_RXSTATEREQ(x) ((x) << S_REQ_LNA_RXSTATEREQ)
9932 #define F_REQ_LNA_RXSTATEREQ    V_REQ_LNA_RXSTATEREQ(1U)
9933 
9934 #define S_REQ_LNA_RXPWRSTATE    0
9935 #define M_REQ_LNA_RXPWRSTATE    0x3U
9936 #define V_REQ_LNA_RXPWRSTATE(x) ((x) << S_REQ_LNA_RXPWRSTATE)
9937 #define G_REQ_LNA_RXPWRSTATE(x) (((x) >> S_REQ_LNA_RXPWRSTATE) & M_REQ_LNA_RXPWRSTATE)
9938 
9939 #define A_PCIE_PHY_CURRXPWR 0x5ba4
9940 
9941 #define S_T5_LNH_RXPWRSTATE    28
9942 #define M_T5_LNH_RXPWRSTATE    0x7U
9943 #define V_T5_LNH_RXPWRSTATE(x) ((x) << S_T5_LNH_RXPWRSTATE)
9944 #define G_T5_LNH_RXPWRSTATE(x) (((x) >> S_T5_LNH_RXPWRSTATE) & M_T5_LNH_RXPWRSTATE)
9945 
9946 #define S_T5_LNG_RXPWRSTATE    24
9947 #define M_T5_LNG_RXPWRSTATE    0x7U
9948 #define V_T5_LNG_RXPWRSTATE(x) ((x) << S_T5_LNG_RXPWRSTATE)
9949 #define G_T5_LNG_RXPWRSTATE(x) (((x) >> S_T5_LNG_RXPWRSTATE) & M_T5_LNG_RXPWRSTATE)
9950 
9951 #define S_T5_LNF_RXPWRSTATE    20
9952 #define M_T5_LNF_RXPWRSTATE    0x7U
9953 #define V_T5_LNF_RXPWRSTATE(x) ((x) << S_T5_LNF_RXPWRSTATE)
9954 #define G_T5_LNF_RXPWRSTATE(x) (((x) >> S_T5_LNF_RXPWRSTATE) & M_T5_LNF_RXPWRSTATE)
9955 
9956 #define S_T5_LNE_RXPWRSTATE    16
9957 #define M_T5_LNE_RXPWRSTATE    0x7U
9958 #define V_T5_LNE_RXPWRSTATE(x) ((x) << S_T5_LNE_RXPWRSTATE)
9959 #define G_T5_LNE_RXPWRSTATE(x) (((x) >> S_T5_LNE_RXPWRSTATE) & M_T5_LNE_RXPWRSTATE)
9960 
9961 #define S_T5_LND_RXPWRSTATE    12
9962 #define M_T5_LND_RXPWRSTATE    0x7U
9963 #define V_T5_LND_RXPWRSTATE(x) ((x) << S_T5_LND_RXPWRSTATE)
9964 #define G_T5_LND_RXPWRSTATE(x) (((x) >> S_T5_LND_RXPWRSTATE) & M_T5_LND_RXPWRSTATE)
9965 
9966 #define S_T5_LNC_RXPWRSTATE    8
9967 #define M_T5_LNC_RXPWRSTATE    0x7U
9968 #define V_T5_LNC_RXPWRSTATE(x) ((x) << S_T5_LNC_RXPWRSTATE)
9969 #define G_T5_LNC_RXPWRSTATE(x) (((x) >> S_T5_LNC_RXPWRSTATE) & M_T5_LNC_RXPWRSTATE)
9970 
9971 #define S_T5_LNB_RXPWRSTATE    4
9972 #define M_T5_LNB_RXPWRSTATE    0x7U
9973 #define V_T5_LNB_RXPWRSTATE(x) ((x) << S_T5_LNB_RXPWRSTATE)
9974 #define G_T5_LNB_RXPWRSTATE(x) (((x) >> S_T5_LNB_RXPWRSTATE) & M_T5_LNB_RXPWRSTATE)
9975 
9976 #define S_T5_LNA_RXPWRSTATE    0
9977 #define M_T5_LNA_RXPWRSTATE    0x7U
9978 #define V_T5_LNA_RXPWRSTATE(x) ((x) << S_T5_LNA_RXPWRSTATE)
9979 #define G_T5_LNA_RXPWRSTATE(x) (((x) >> S_T5_LNA_RXPWRSTATE) & M_T5_LNA_RXPWRSTATE)
9980 
9981 #define S_CUR_LNH_RXPWRSTATE    28
9982 #define M_CUR_LNH_RXPWRSTATE    0x7U
9983 #define V_CUR_LNH_RXPWRSTATE(x) ((x) << S_CUR_LNH_RXPWRSTATE)
9984 #define G_CUR_LNH_RXPWRSTATE(x) (((x) >> S_CUR_LNH_RXPWRSTATE) & M_CUR_LNH_RXPWRSTATE)
9985 
9986 #define S_CUR_LNG_RXPWRSTATE    24
9987 #define M_CUR_LNG_RXPWRSTATE    0x7U
9988 #define V_CUR_LNG_RXPWRSTATE(x) ((x) << S_CUR_LNG_RXPWRSTATE)
9989 #define G_CUR_LNG_RXPWRSTATE(x) (((x) >> S_CUR_LNG_RXPWRSTATE) & M_CUR_LNG_RXPWRSTATE)
9990 
9991 #define S_CUR_LNF_RXPWRSTATE    20
9992 #define M_CUR_LNF_RXPWRSTATE    0x7U
9993 #define V_CUR_LNF_RXPWRSTATE(x) ((x) << S_CUR_LNF_RXPWRSTATE)
9994 #define G_CUR_LNF_RXPWRSTATE(x) (((x) >> S_CUR_LNF_RXPWRSTATE) & M_CUR_LNF_RXPWRSTATE)
9995 
9996 #define S_CUR_LNE_RXPWRSTATE    16
9997 #define M_CUR_LNE_RXPWRSTATE    0x7U
9998 #define V_CUR_LNE_RXPWRSTATE(x) ((x) << S_CUR_LNE_RXPWRSTATE)
9999 #define G_CUR_LNE_RXPWRSTATE(x) (((x) >> S_CUR_LNE_RXPWRSTATE) & M_CUR_LNE_RXPWRSTATE)
10000 
10001 #define S_CUR_LND_RXPWRSTATE    12
10002 #define M_CUR_LND_RXPWRSTATE    0x7U
10003 #define V_CUR_LND_RXPWRSTATE(x) ((x) << S_CUR_LND_RXPWRSTATE)
10004 #define G_CUR_LND_RXPWRSTATE(x) (((x) >> S_CUR_LND_RXPWRSTATE) & M_CUR_LND_RXPWRSTATE)
10005 
10006 #define S_CUR_LNC_RXPWRSTATE    8
10007 #define M_CUR_LNC_RXPWRSTATE    0x7U
10008 #define V_CUR_LNC_RXPWRSTATE(x) ((x) << S_CUR_LNC_RXPWRSTATE)
10009 #define G_CUR_LNC_RXPWRSTATE(x) (((x) >> S_CUR_LNC_RXPWRSTATE) & M_CUR_LNC_RXPWRSTATE)
10010 
10011 #define S_CUR_LNB_RXPWRSTATE    4
10012 #define M_CUR_LNB_RXPWRSTATE    0x7U
10013 #define V_CUR_LNB_RXPWRSTATE(x) ((x) << S_CUR_LNB_RXPWRSTATE)
10014 #define G_CUR_LNB_RXPWRSTATE(x) (((x) >> S_CUR_LNB_RXPWRSTATE) & M_CUR_LNB_RXPWRSTATE)
10015 
10016 #define S_CUR_LNA_RXPWRSTATE    0
10017 #define M_CUR_LNA_RXPWRSTATE    0x7U
10018 #define V_CUR_LNA_RXPWRSTATE(x) ((x) << S_CUR_LNA_RXPWRSTATE)
10019 #define G_CUR_LNA_RXPWRSTATE(x) (((x) >> S_CUR_LNA_RXPWRSTATE) & M_CUR_LNA_RXPWRSTATE)
10020 
10021 #define A_PCIE_PHY_GEN3_AE0 0x5ba8
10022 
10023 #define S_LND_STAT    28
10024 #define M_LND_STAT    0x7U
10025 #define V_LND_STAT(x) ((x) << S_LND_STAT)
10026 #define G_LND_STAT(x) (((x) >> S_LND_STAT) & M_LND_STAT)
10027 
10028 #define S_LND_CMD    24
10029 #define M_LND_CMD    0x7U
10030 #define V_LND_CMD(x) ((x) << S_LND_CMD)
10031 #define G_LND_CMD(x) (((x) >> S_LND_CMD) & M_LND_CMD)
10032 
10033 #define S_LNC_STAT    20
10034 #define M_LNC_STAT    0x7U
10035 #define V_LNC_STAT(x) ((x) << S_LNC_STAT)
10036 #define G_LNC_STAT(x) (((x) >> S_LNC_STAT) & M_LNC_STAT)
10037 
10038 #define S_LNC_CMD    16
10039 #define M_LNC_CMD    0x7U
10040 #define V_LNC_CMD(x) ((x) << S_LNC_CMD)
10041 #define G_LNC_CMD(x) (((x) >> S_LNC_CMD) & M_LNC_CMD)
10042 
10043 #define S_LNB_STAT    12
10044 #define M_LNB_STAT    0x7U
10045 #define V_LNB_STAT(x) ((x) << S_LNB_STAT)
10046 #define G_LNB_STAT(x) (((x) >> S_LNB_STAT) & M_LNB_STAT)
10047 
10048 #define S_LNB_CMD    8
10049 #define M_LNB_CMD    0x7U
10050 #define V_LNB_CMD(x) ((x) << S_LNB_CMD)
10051 #define G_LNB_CMD(x) (((x) >> S_LNB_CMD) & M_LNB_CMD)
10052 
10053 #define S_LNA_STAT    4
10054 #define M_LNA_STAT    0x7U
10055 #define V_LNA_STAT(x) ((x) << S_LNA_STAT)
10056 #define G_LNA_STAT(x) (((x) >> S_LNA_STAT) & M_LNA_STAT)
10057 
10058 #define S_LNA_CMD    0
10059 #define M_LNA_CMD    0x7U
10060 #define V_LNA_CMD(x) ((x) << S_LNA_CMD)
10061 #define G_LNA_CMD(x) (((x) >> S_LNA_CMD) & M_LNA_CMD)
10062 
10063 #define A_PCIE_PHY_GEN3_AE1 0x5bac
10064 
10065 #define S_LNH_STAT    28
10066 #define M_LNH_STAT    0x7U
10067 #define V_LNH_STAT(x) ((x) << S_LNH_STAT)
10068 #define G_LNH_STAT(x) (((x) >> S_LNH_STAT) & M_LNH_STAT)
10069 
10070 #define S_LNH_CMD    24
10071 #define M_LNH_CMD    0x7U
10072 #define V_LNH_CMD(x) ((x) << S_LNH_CMD)
10073 #define G_LNH_CMD(x) (((x) >> S_LNH_CMD) & M_LNH_CMD)
10074 
10075 #define S_LNG_STAT    20
10076 #define M_LNG_STAT    0x7U
10077 #define V_LNG_STAT(x) ((x) << S_LNG_STAT)
10078 #define G_LNG_STAT(x) (((x) >> S_LNG_STAT) & M_LNG_STAT)
10079 
10080 #define S_LNG_CMD    16
10081 #define M_LNG_CMD    0x7U
10082 #define V_LNG_CMD(x) ((x) << S_LNG_CMD)
10083 #define G_LNG_CMD(x) (((x) >> S_LNG_CMD) & M_LNG_CMD)
10084 
10085 #define S_LNF_STAT    12
10086 #define M_LNF_STAT    0x7U
10087 #define V_LNF_STAT(x) ((x) << S_LNF_STAT)
10088 #define G_LNF_STAT(x) (((x) >> S_LNF_STAT) & M_LNF_STAT)
10089 
10090 #define S_LNF_CMD    8
10091 #define M_LNF_CMD    0x7U
10092 #define V_LNF_CMD(x) ((x) << S_LNF_CMD)
10093 #define G_LNF_CMD(x) (((x) >> S_LNF_CMD) & M_LNF_CMD)
10094 
10095 #define S_LNE_STAT    4
10096 #define M_LNE_STAT    0x7U
10097 #define V_LNE_STAT(x) ((x) << S_LNE_STAT)
10098 #define G_LNE_STAT(x) (((x) >> S_LNE_STAT) & M_LNE_STAT)
10099 
10100 #define S_LNE_CMD    0
10101 #define M_LNE_CMD    0x7U
10102 #define V_LNE_CMD(x) ((x) << S_LNE_CMD)
10103 #define G_LNE_CMD(x) (((x) >> S_LNE_CMD) & M_LNE_CMD)
10104 
10105 #define A_PCIE_PHY_FS_LF0 0x5bb0
10106 
10107 #define S_LANE1LF    24
10108 #define M_LANE1LF    0x3fU
10109 #define V_LANE1LF(x) ((x) << S_LANE1LF)
10110 #define G_LANE1LF(x) (((x) >> S_LANE1LF) & M_LANE1LF)
10111 
10112 #define S_LANE1FS    16
10113 #define M_LANE1FS    0x3fU
10114 #define V_LANE1FS(x) ((x) << S_LANE1FS)
10115 #define G_LANE1FS(x) (((x) >> S_LANE1FS) & M_LANE1FS)
10116 
10117 #define S_LANE0LF    8
10118 #define M_LANE0LF    0x3fU
10119 #define V_LANE0LF(x) ((x) << S_LANE0LF)
10120 #define G_LANE0LF(x) (((x) >> S_LANE0LF) & M_LANE0LF)
10121 
10122 #define S_LANE0FS    0
10123 #define M_LANE0FS    0x3fU
10124 #define V_LANE0FS(x) ((x) << S_LANE0FS)
10125 #define G_LANE0FS(x) (((x) >> S_LANE0FS) & M_LANE0FS)
10126 
10127 #define A_PCIE_PHY_FS_LF1 0x5bb4
10128 
10129 #define S_LANE3LF    24
10130 #define M_LANE3LF    0x3fU
10131 #define V_LANE3LF(x) ((x) << S_LANE3LF)
10132 #define G_LANE3LF(x) (((x) >> S_LANE3LF) & M_LANE3LF)
10133 
10134 #define S_LANE3FS    16
10135 #define M_LANE3FS    0x3fU
10136 #define V_LANE3FS(x) ((x) << S_LANE3FS)
10137 #define G_LANE3FS(x) (((x) >> S_LANE3FS) & M_LANE3FS)
10138 
10139 #define S_LANE2LF    8
10140 #define M_LANE2LF    0x3fU
10141 #define V_LANE2LF(x) ((x) << S_LANE2LF)
10142 #define G_LANE2LF(x) (((x) >> S_LANE2LF) & M_LANE2LF)
10143 
10144 #define S_LANE2FS    0
10145 #define M_LANE2FS    0x3fU
10146 #define V_LANE2FS(x) ((x) << S_LANE2FS)
10147 #define G_LANE2FS(x) (((x) >> S_LANE2FS) & M_LANE2FS)
10148 
10149 #define A_PCIE_PHY_FS_LF2 0x5bb8
10150 
10151 #define S_LANE5LF    24
10152 #define M_LANE5LF    0x3fU
10153 #define V_LANE5LF(x) ((x) << S_LANE5LF)
10154 #define G_LANE5LF(x) (((x) >> S_LANE5LF) & M_LANE5LF)
10155 
10156 #define S_LANE5FS    16
10157 #define M_LANE5FS    0x3fU
10158 #define V_LANE5FS(x) ((x) << S_LANE5FS)
10159 #define G_LANE5FS(x) (((x) >> S_LANE5FS) & M_LANE5FS)
10160 
10161 #define S_LANE4LF    8
10162 #define M_LANE4LF    0x3fU
10163 #define V_LANE4LF(x) ((x) << S_LANE4LF)
10164 #define G_LANE4LF(x) (((x) >> S_LANE4LF) & M_LANE4LF)
10165 
10166 #define S_LANE4FS    0
10167 #define M_LANE4FS    0x3fU
10168 #define V_LANE4FS(x) ((x) << S_LANE4FS)
10169 #define G_LANE4FS(x) (((x) >> S_LANE4FS) & M_LANE4FS)
10170 
10171 #define A_PCIE_PHY_FS_LF3 0x5bbc
10172 
10173 #define S_LANE7LF    24
10174 #define M_LANE7LF    0x3fU
10175 #define V_LANE7LF(x) ((x) << S_LANE7LF)
10176 #define G_LANE7LF(x) (((x) >> S_LANE7LF) & M_LANE7LF)
10177 
10178 #define S_LANE7FS    16
10179 #define M_LANE7FS    0x3fU
10180 #define V_LANE7FS(x) ((x) << S_LANE7FS)
10181 #define G_LANE7FS(x) (((x) >> S_LANE7FS) & M_LANE7FS)
10182 
10183 #define S_LANE6LF    8
10184 #define M_LANE6LF    0x3fU
10185 #define V_LANE6LF(x) ((x) << S_LANE6LF)
10186 #define G_LANE6LF(x) (((x) >> S_LANE6LF) & M_LANE6LF)
10187 
10188 #define S_LANE6FS    0
10189 #define M_LANE6FS    0x3fU
10190 #define V_LANE6FS(x) ((x) << S_LANE6FS)
10191 #define G_LANE6FS(x) (((x) >> S_LANE6FS) & M_LANE6FS)
10192 
10193 #define A_PCIE_PHY_PRESET_REQ 0x5bc0
10194 
10195 #define S_COEFFDONE    16
10196 #define V_COEFFDONE(x) ((x) << S_COEFFDONE)
10197 #define F_COEFFDONE    V_COEFFDONE(1U)
10198 
10199 #define S_COEFFLANE    8
10200 #define M_COEFFLANE    0x7U
10201 #define V_COEFFLANE(x) ((x) << S_COEFFLANE)
10202 #define G_COEFFLANE(x) (((x) >> S_COEFFLANE) & M_COEFFLANE)
10203 
10204 #define S_COEFFSTART    0
10205 #define V_COEFFSTART(x) ((x) << S_COEFFSTART)
10206 #define F_COEFFSTART    V_COEFFSTART(1U)
10207 
10208 #define S_T6_COEFFLANE    8
10209 #define M_T6_COEFFLANE    0xfU
10210 #define V_T6_COEFFLANE(x) ((x) << S_T6_COEFFLANE)
10211 #define G_T6_COEFFLANE(x) (((x) >> S_T6_COEFFLANE) & M_T6_COEFFLANE)
10212 
10213 #define A_PCIE_PHY_PRESET_COEFF 0x5bc4
10214 
10215 #define S_COEFF    0
10216 #define M_COEFF    0x3ffffU
10217 #define V_COEFF(x) ((x) << S_COEFF)
10218 #define G_COEFF(x) (((x) >> S_COEFF) & M_COEFF)
10219 
10220 #define A_PCIE_PHY_INDIR_REQ 0x5bf0
10221 
10222 #define S_PHYENABLE    31
10223 #define V_PHYENABLE(x) ((x) << S_PHYENABLE)
10224 #define F_PHYENABLE    V_PHYENABLE(1U)
10225 
10226 #define S_PCIE_PHY_REGADDR    0
10227 #define M_PCIE_PHY_REGADDR    0xffffU
10228 #define V_PCIE_PHY_REGADDR(x) ((x) << S_PCIE_PHY_REGADDR)
10229 #define G_PCIE_PHY_REGADDR(x) (((x) >> S_PCIE_PHY_REGADDR) & M_PCIE_PHY_REGADDR)
10230 
10231 #define A_PCIE_PHY_INDIR_DATA 0x5bf4
10232 #define A_PCIE_STATIC_SPARE1 0x5bf8
10233 #define A_PCIE_STATIC_SPARE2 0x5bfc
10234 
10235 #define S_X8_SW_EN    30
10236 #define V_X8_SW_EN(x) ((x) << S_X8_SW_EN)
10237 #define F_X8_SW_EN    V_X8_SW_EN(1U)
10238 
10239 #define S_SWITCHCFG    28
10240 #define M_SWITCHCFG    0x3U
10241 #define V_SWITCHCFG(x) ((x) << S_SWITCHCFG)
10242 #define G_SWITCHCFG(x) (((x) >> S_SWITCHCFG) & M_SWITCHCFG)
10243 
10244 #define S_STATIC_SPARE2    0
10245 #define M_STATIC_SPARE2    0xfffffffU
10246 #define V_STATIC_SPARE2(x) ((x) << S_STATIC_SPARE2)
10247 #define G_STATIC_SPARE2(x) (((x) >> S_STATIC_SPARE2) & M_STATIC_SPARE2)
10248 
10249 #define A_PCIE_KDOORBELL_GTS_PF_BASE_LEN 0x5c10
10250 
10251 #define S_KDB_PF_LEN    24
10252 #define M_KDB_PF_LEN    0x1fU
10253 #define V_KDB_PF_LEN(x) ((x) << S_KDB_PF_LEN)
10254 #define G_KDB_PF_LEN(x) (((x) >> S_KDB_PF_LEN) & M_KDB_PF_LEN)
10255 
10256 #define S_KDB_PF_BASEADDR    0
10257 #define M_KDB_PF_BASEADDR    0xfffffU
10258 #define V_KDB_PF_BASEADDR(x) ((x) << S_KDB_PF_BASEADDR)
10259 #define G_KDB_PF_BASEADDR(x) (((x) >> S_KDB_PF_BASEADDR) & M_KDB_PF_BASEADDR)
10260 
10261 #define A_PCIE_KDOORBELL_GTS_VF_BASE_LEN 0x5c14
10262 
10263 #define S_KDB_VF_LEN    24
10264 #define M_KDB_VF_LEN    0x1fU
10265 #define V_KDB_VF_LEN(x) ((x) << S_KDB_VF_LEN)
10266 #define G_KDB_VF_LEN(x) (((x) >> S_KDB_VF_LEN) & M_KDB_VF_LEN)
10267 
10268 #define S_KDB_VF_BASEADDR    0
10269 #define M_KDB_VF_BASEADDR    0xfffffU
10270 #define V_KDB_VF_BASEADDR(x) ((x) << S_KDB_VF_BASEADDR)
10271 #define G_KDB_VF_BASEADDR(x) (((x) >> S_KDB_VF_BASEADDR) & M_KDB_VF_BASEADDR)
10272 
10273 #define A_PCIE_KDOORBELL_GTS_VF_OFFSET 0x5c18
10274 
10275 #define S_KDB_VF_MODOFST    0
10276 #define M_KDB_VF_MODOFST    0xfffU
10277 #define V_KDB_VF_MODOFST(x) ((x) << S_KDB_VF_MODOFST)
10278 #define G_KDB_VF_MODOFST(x) (((x) >> S_KDB_VF_MODOFST) & M_KDB_VF_MODOFST)
10279 
10280 #define A_PCIE_PHY_REQRXPWR1 0x5c1c
10281 
10282 #define S_REQ_LNP_RXSTATEDONE    31
10283 #define V_REQ_LNP_RXSTATEDONE(x) ((x) << S_REQ_LNP_RXSTATEDONE)
10284 #define F_REQ_LNP_RXSTATEDONE    V_REQ_LNP_RXSTATEDONE(1U)
10285 
10286 #define S_REQ_LNP_RXSTATEREQ    30
10287 #define V_REQ_LNP_RXSTATEREQ(x) ((x) << S_REQ_LNP_RXSTATEREQ)
10288 #define F_REQ_LNP_RXSTATEREQ    V_REQ_LNP_RXSTATEREQ(1U)
10289 
10290 #define S_REQ_LNP_RXPWRSTATE    28
10291 #define M_REQ_LNP_RXPWRSTATE    0x3U
10292 #define V_REQ_LNP_RXPWRSTATE(x) ((x) << S_REQ_LNP_RXPWRSTATE)
10293 #define G_REQ_LNP_RXPWRSTATE(x) (((x) >> S_REQ_LNP_RXPWRSTATE) & M_REQ_LNP_RXPWRSTATE)
10294 
10295 #define S_REQ_LNO_RXSTATEDONE    27
10296 #define V_REQ_LNO_RXSTATEDONE(x) ((x) << S_REQ_LNO_RXSTATEDONE)
10297 #define F_REQ_LNO_RXSTATEDONE    V_REQ_LNO_RXSTATEDONE(1U)
10298 
10299 #define S_REQ_LNO_RXSTATEREQ    26
10300 #define V_REQ_LNO_RXSTATEREQ(x) ((x) << S_REQ_LNO_RXSTATEREQ)
10301 #define F_REQ_LNO_RXSTATEREQ    V_REQ_LNO_RXSTATEREQ(1U)
10302 
10303 #define S_REQ_LNO_RXPWRSTATE    24
10304 #define M_REQ_LNO_RXPWRSTATE    0x3U
10305 #define V_REQ_LNO_RXPWRSTATE(x) ((x) << S_REQ_LNO_RXPWRSTATE)
10306 #define G_REQ_LNO_RXPWRSTATE(x) (((x) >> S_REQ_LNO_RXPWRSTATE) & M_REQ_LNO_RXPWRSTATE)
10307 
10308 #define S_REQ_LNN_RXSTATEDONE    23
10309 #define V_REQ_LNN_RXSTATEDONE(x) ((x) << S_REQ_LNN_RXSTATEDONE)
10310 #define F_REQ_LNN_RXSTATEDONE    V_REQ_LNN_RXSTATEDONE(1U)
10311 
10312 #define S_REQ_LNN_RXSTATEREQ    22
10313 #define V_REQ_LNN_RXSTATEREQ(x) ((x) << S_REQ_LNN_RXSTATEREQ)
10314 #define F_REQ_LNN_RXSTATEREQ    V_REQ_LNN_RXSTATEREQ(1U)
10315 
10316 #define S_REQ_LNN_RXPWRSTATE    20
10317 #define M_REQ_LNN_RXPWRSTATE    0x3U
10318 #define V_REQ_LNN_RXPWRSTATE(x) ((x) << S_REQ_LNN_RXPWRSTATE)
10319 #define G_REQ_LNN_RXPWRSTATE(x) (((x) >> S_REQ_LNN_RXPWRSTATE) & M_REQ_LNN_RXPWRSTATE)
10320 
10321 #define S_REQ_LNM_RXSTATEDONE    19
10322 #define V_REQ_LNM_RXSTATEDONE(x) ((x) << S_REQ_LNM_RXSTATEDONE)
10323 #define F_REQ_LNM_RXSTATEDONE    V_REQ_LNM_RXSTATEDONE(1U)
10324 
10325 #define S_REQ_LNM_RXSTATEREQ    18
10326 #define V_REQ_LNM_RXSTATEREQ(x) ((x) << S_REQ_LNM_RXSTATEREQ)
10327 #define F_REQ_LNM_RXSTATEREQ    V_REQ_LNM_RXSTATEREQ(1U)
10328 
10329 #define S_REQ_LNM_RXPWRSTATE    16
10330 #define M_REQ_LNM_RXPWRSTATE    0x3U
10331 #define V_REQ_LNM_RXPWRSTATE(x) ((x) << S_REQ_LNM_RXPWRSTATE)
10332 #define G_REQ_LNM_RXPWRSTATE(x) (((x) >> S_REQ_LNM_RXPWRSTATE) & M_REQ_LNM_RXPWRSTATE)
10333 
10334 #define S_REQ_LNL_RXSTATEDONE    15
10335 #define V_REQ_LNL_RXSTATEDONE(x) ((x) << S_REQ_LNL_RXSTATEDONE)
10336 #define F_REQ_LNL_RXSTATEDONE    V_REQ_LNL_RXSTATEDONE(1U)
10337 
10338 #define S_REQ_LNL_RXSTATEREQ    14
10339 #define V_REQ_LNL_RXSTATEREQ(x) ((x) << S_REQ_LNL_RXSTATEREQ)
10340 #define F_REQ_LNL_RXSTATEREQ    V_REQ_LNL_RXSTATEREQ(1U)
10341 
10342 #define S_REQ_LNL_RXPWRSTATE    12
10343 #define M_REQ_LNL_RXPWRSTATE    0x3U
10344 #define V_REQ_LNL_RXPWRSTATE(x) ((x) << S_REQ_LNL_RXPWRSTATE)
10345 #define G_REQ_LNL_RXPWRSTATE(x) (((x) >> S_REQ_LNL_RXPWRSTATE) & M_REQ_LNL_RXPWRSTATE)
10346 
10347 #define S_REQ_LNK_RXSTATEDONE    11
10348 #define V_REQ_LNK_RXSTATEDONE(x) ((x) << S_REQ_LNK_RXSTATEDONE)
10349 #define F_REQ_LNK_RXSTATEDONE    V_REQ_LNK_RXSTATEDONE(1U)
10350 
10351 #define S_REQ_LNK_RXSTATEREQ    10
10352 #define V_REQ_LNK_RXSTATEREQ(x) ((x) << S_REQ_LNK_RXSTATEREQ)
10353 #define F_REQ_LNK_RXSTATEREQ    V_REQ_LNK_RXSTATEREQ(1U)
10354 
10355 #define S_REQ_LNK_RXPWRSTATE    8
10356 #define M_REQ_LNK_RXPWRSTATE    0x3U
10357 #define V_REQ_LNK_RXPWRSTATE(x) ((x) << S_REQ_LNK_RXPWRSTATE)
10358 #define G_REQ_LNK_RXPWRSTATE(x) (((x) >> S_REQ_LNK_RXPWRSTATE) & M_REQ_LNK_RXPWRSTATE)
10359 
10360 #define S_REQ_LNJ_RXSTATEDONE    7
10361 #define V_REQ_LNJ_RXSTATEDONE(x) ((x) << S_REQ_LNJ_RXSTATEDONE)
10362 #define F_REQ_LNJ_RXSTATEDONE    V_REQ_LNJ_RXSTATEDONE(1U)
10363 
10364 #define S_REQ_LNJ_RXSTATEREQ    6
10365 #define V_REQ_LNJ_RXSTATEREQ(x) ((x) << S_REQ_LNJ_RXSTATEREQ)
10366 #define F_REQ_LNJ_RXSTATEREQ    V_REQ_LNJ_RXSTATEREQ(1U)
10367 
10368 #define S_REQ_LNJ_RXPWRSTATE    4
10369 #define M_REQ_LNJ_RXPWRSTATE    0x3U
10370 #define V_REQ_LNJ_RXPWRSTATE(x) ((x) << S_REQ_LNJ_RXPWRSTATE)
10371 #define G_REQ_LNJ_RXPWRSTATE(x) (((x) >> S_REQ_LNJ_RXPWRSTATE) & M_REQ_LNJ_RXPWRSTATE)
10372 
10373 #define S_REQ_LNI_RXSTATEDONE    3
10374 #define V_REQ_LNI_RXSTATEDONE(x) ((x) << S_REQ_LNI_RXSTATEDONE)
10375 #define F_REQ_LNI_RXSTATEDONE    V_REQ_LNI_RXSTATEDONE(1U)
10376 
10377 #define S_REQ_LNI_RXSTATEREQ    2
10378 #define V_REQ_LNI_RXSTATEREQ(x) ((x) << S_REQ_LNI_RXSTATEREQ)
10379 #define F_REQ_LNI_RXSTATEREQ    V_REQ_LNI_RXSTATEREQ(1U)
10380 
10381 #define S_REQ_LNI_RXPWRSTATE    0
10382 #define M_REQ_LNI_RXPWRSTATE    0x3U
10383 #define V_REQ_LNI_RXPWRSTATE(x) ((x) << S_REQ_LNI_RXPWRSTATE)
10384 #define G_REQ_LNI_RXPWRSTATE(x) (((x) >> S_REQ_LNI_RXPWRSTATE) & M_REQ_LNI_RXPWRSTATE)
10385 
10386 #define A_PCIE_PHY_CURRXPWR1 0x5c20
10387 
10388 #define S_CUR_LNP_RXPWRSTATE    28
10389 #define M_CUR_LNP_RXPWRSTATE    0x7U
10390 #define V_CUR_LNP_RXPWRSTATE(x) ((x) << S_CUR_LNP_RXPWRSTATE)
10391 #define G_CUR_LNP_RXPWRSTATE(x) (((x) >> S_CUR_LNP_RXPWRSTATE) & M_CUR_LNP_RXPWRSTATE)
10392 
10393 #define S_CUR_LNO_RXPWRSTATE    24
10394 #define M_CUR_LNO_RXPWRSTATE    0x7U
10395 #define V_CUR_LNO_RXPWRSTATE(x) ((x) << S_CUR_LNO_RXPWRSTATE)
10396 #define G_CUR_LNO_RXPWRSTATE(x) (((x) >> S_CUR_LNO_RXPWRSTATE) & M_CUR_LNO_RXPWRSTATE)
10397 
10398 #define S_CUR_LNN_RXPWRSTATE    20
10399 #define M_CUR_LNN_RXPWRSTATE    0x7U
10400 #define V_CUR_LNN_RXPWRSTATE(x) ((x) << S_CUR_LNN_RXPWRSTATE)
10401 #define G_CUR_LNN_RXPWRSTATE(x) (((x) >> S_CUR_LNN_RXPWRSTATE) & M_CUR_LNN_RXPWRSTATE)
10402 
10403 #define S_CUR_LNM_RXPWRSTATE    16
10404 #define M_CUR_LNM_RXPWRSTATE    0x7U
10405 #define V_CUR_LNM_RXPWRSTATE(x) ((x) << S_CUR_LNM_RXPWRSTATE)
10406 #define G_CUR_LNM_RXPWRSTATE(x) (((x) >> S_CUR_LNM_RXPWRSTATE) & M_CUR_LNM_RXPWRSTATE)
10407 
10408 #define S_CUR_LNL_RXPWRSTATE    12
10409 #define M_CUR_LNL_RXPWRSTATE    0x7U
10410 #define V_CUR_LNL_RXPWRSTATE(x) ((x) << S_CUR_LNL_RXPWRSTATE)
10411 #define G_CUR_LNL_RXPWRSTATE(x) (((x) >> S_CUR_LNL_RXPWRSTATE) & M_CUR_LNL_RXPWRSTATE)
10412 
10413 #define S_CUR_LNK_RXPWRSTATE    8
10414 #define M_CUR_LNK_RXPWRSTATE    0x7U
10415 #define V_CUR_LNK_RXPWRSTATE(x) ((x) << S_CUR_LNK_RXPWRSTATE)
10416 #define G_CUR_LNK_RXPWRSTATE(x) (((x) >> S_CUR_LNK_RXPWRSTATE) & M_CUR_LNK_RXPWRSTATE)
10417 
10418 #define S_CUR_LNJ_RXPWRSTATE    4
10419 #define M_CUR_LNJ_RXPWRSTATE    0x7U
10420 #define V_CUR_LNJ_RXPWRSTATE(x) ((x) << S_CUR_LNJ_RXPWRSTATE)
10421 #define G_CUR_LNJ_RXPWRSTATE(x) (((x) >> S_CUR_LNJ_RXPWRSTATE) & M_CUR_LNJ_RXPWRSTATE)
10422 
10423 #define S_CUR_LNI_RXPWRSTATE    0
10424 #define M_CUR_LNI_RXPWRSTATE    0x7U
10425 #define V_CUR_LNI_RXPWRSTATE(x) ((x) << S_CUR_LNI_RXPWRSTATE)
10426 #define G_CUR_LNI_RXPWRSTATE(x) (((x) >> S_CUR_LNI_RXPWRSTATE) & M_CUR_LNI_RXPWRSTATE)
10427 
10428 #define A_PCIE_PHY_GEN3_AE2 0x5c24
10429 
10430 #define S_LNL_STAT    28
10431 #define M_LNL_STAT    0x7U
10432 #define V_LNL_STAT(x) ((x) << S_LNL_STAT)
10433 #define G_LNL_STAT(x) (((x) >> S_LNL_STAT) & M_LNL_STAT)
10434 
10435 #define S_LNL_CMD    24
10436 #define M_LNL_CMD    0x7U
10437 #define V_LNL_CMD(x) ((x) << S_LNL_CMD)
10438 #define G_LNL_CMD(x) (((x) >> S_LNL_CMD) & M_LNL_CMD)
10439 
10440 #define S_LNK_STAT    20
10441 #define M_LNK_STAT    0x7U
10442 #define V_LNK_STAT(x) ((x) << S_LNK_STAT)
10443 #define G_LNK_STAT(x) (((x) >> S_LNK_STAT) & M_LNK_STAT)
10444 
10445 #define S_LNK_CMD    16
10446 #define M_LNK_CMD    0x7U
10447 #define V_LNK_CMD(x) ((x) << S_LNK_CMD)
10448 #define G_LNK_CMD(x) (((x) >> S_LNK_CMD) & M_LNK_CMD)
10449 
10450 #define S_LNJ_STAT    12
10451 #define M_LNJ_STAT    0x7U
10452 #define V_LNJ_STAT(x) ((x) << S_LNJ_STAT)
10453 #define G_LNJ_STAT(x) (((x) >> S_LNJ_STAT) & M_LNJ_STAT)
10454 
10455 #define S_LNJ_CMD    8
10456 #define M_LNJ_CMD    0x7U
10457 #define V_LNJ_CMD(x) ((x) << S_LNJ_CMD)
10458 #define G_LNJ_CMD(x) (((x) >> S_LNJ_CMD) & M_LNJ_CMD)
10459 
10460 #define S_LNI_STAT    4
10461 #define M_LNI_STAT    0x7U
10462 #define V_LNI_STAT(x) ((x) << S_LNI_STAT)
10463 #define G_LNI_STAT(x) (((x) >> S_LNI_STAT) & M_LNI_STAT)
10464 
10465 #define S_LNI_CMD    0
10466 #define M_LNI_CMD    0x7U
10467 #define V_LNI_CMD(x) ((x) << S_LNI_CMD)
10468 #define G_LNI_CMD(x) (((x) >> S_LNI_CMD) & M_LNI_CMD)
10469 
10470 #define A_PCIE_PHY_GEN3_AE3 0x5c28
10471 
10472 #define S_LNP_STAT    28
10473 #define M_LNP_STAT    0x7U
10474 #define V_LNP_STAT(x) ((x) << S_LNP_STAT)
10475 #define G_LNP_STAT(x) (((x) >> S_LNP_STAT) & M_LNP_STAT)
10476 
10477 #define S_LNP_CMD    24
10478 #define M_LNP_CMD    0x7U
10479 #define V_LNP_CMD(x) ((x) << S_LNP_CMD)
10480 #define G_LNP_CMD(x) (((x) >> S_LNP_CMD) & M_LNP_CMD)
10481 
10482 #define S_LNO_STAT    20
10483 #define M_LNO_STAT    0x7U
10484 #define V_LNO_STAT(x) ((x) << S_LNO_STAT)
10485 #define G_LNO_STAT(x) (((x) >> S_LNO_STAT) & M_LNO_STAT)
10486 
10487 #define S_LNO_CMD    16
10488 #define M_LNO_CMD    0x7U
10489 #define V_LNO_CMD(x) ((x) << S_LNO_CMD)
10490 #define G_LNO_CMD(x) (((x) >> S_LNO_CMD) & M_LNO_CMD)
10491 
10492 #define S_LNN_STAT    12
10493 #define M_LNN_STAT    0x7U
10494 #define V_LNN_STAT(x) ((x) << S_LNN_STAT)
10495 #define G_LNN_STAT(x) (((x) >> S_LNN_STAT) & M_LNN_STAT)
10496 
10497 #define S_LNN_CMD    8
10498 #define M_LNN_CMD    0x7U
10499 #define V_LNN_CMD(x) ((x) << S_LNN_CMD)
10500 #define G_LNN_CMD(x) (((x) >> S_LNN_CMD) & M_LNN_CMD)
10501 
10502 #define S_LNM_STAT    4
10503 #define M_LNM_STAT    0x7U
10504 #define V_LNM_STAT(x) ((x) << S_LNM_STAT)
10505 #define G_LNM_STAT(x) (((x) >> S_LNM_STAT) & M_LNM_STAT)
10506 
10507 #define S_LNM_CMD    0
10508 #define M_LNM_CMD    0x7U
10509 #define V_LNM_CMD(x) ((x) << S_LNM_CMD)
10510 #define G_LNM_CMD(x) (((x) >> S_LNM_CMD) & M_LNM_CMD)
10511 
10512 #define A_PCIE_PHY_FS_LF4 0x5c2c
10513 
10514 #define S_LANE9LF    24
10515 #define M_LANE9LF    0x3fU
10516 #define V_LANE9LF(x) ((x) << S_LANE9LF)
10517 #define G_LANE9LF(x) (((x) >> S_LANE9LF) & M_LANE9LF)
10518 
10519 #define S_LANE9FS    16
10520 #define M_LANE9FS    0x3fU
10521 #define V_LANE9FS(x) ((x) << S_LANE9FS)
10522 #define G_LANE9FS(x) (((x) >> S_LANE9FS) & M_LANE9FS)
10523 
10524 #define S_LANE8LF    8
10525 #define M_LANE8LF    0x3fU
10526 #define V_LANE8LF(x) ((x) << S_LANE8LF)
10527 #define G_LANE8LF(x) (((x) >> S_LANE8LF) & M_LANE8LF)
10528 
10529 #define S_LANE8FS    0
10530 #define M_LANE8FS    0x3fU
10531 #define V_LANE8FS(x) ((x) << S_LANE8FS)
10532 #define G_LANE8FS(x) (((x) >> S_LANE8FS) & M_LANE8FS)
10533 
10534 #define A_PCIE_PHY_FS_LF5 0x5c30
10535 
10536 #define S_LANE11LF    24
10537 #define M_LANE11LF    0x3fU
10538 #define V_LANE11LF(x) ((x) << S_LANE11LF)
10539 #define G_LANE11LF(x) (((x) >> S_LANE11LF) & M_LANE11LF)
10540 
10541 #define S_LANE11FS    16
10542 #define M_LANE11FS    0x3fU
10543 #define V_LANE11FS(x) ((x) << S_LANE11FS)
10544 #define G_LANE11FS(x) (((x) >> S_LANE11FS) & M_LANE11FS)
10545 
10546 #define S_LANE10LF    8
10547 #define M_LANE10LF    0x3fU
10548 #define V_LANE10LF(x) ((x) << S_LANE10LF)
10549 #define G_LANE10LF(x) (((x) >> S_LANE10LF) & M_LANE10LF)
10550 
10551 #define S_LANE10FS    0
10552 #define M_LANE10FS    0x3fU
10553 #define V_LANE10FS(x) ((x) << S_LANE10FS)
10554 #define G_LANE10FS(x) (((x) >> S_LANE10FS) & M_LANE10FS)
10555 
10556 #define A_PCIE_PHY_FS_LF6 0x5c34
10557 
10558 #define S_LANE13LF    24
10559 #define M_LANE13LF    0x3fU
10560 #define V_LANE13LF(x) ((x) << S_LANE13LF)
10561 #define G_LANE13LF(x) (((x) >> S_LANE13LF) & M_LANE13LF)
10562 
10563 #define S_LANE13FS    16
10564 #define M_LANE13FS    0x3fU
10565 #define V_LANE13FS(x) ((x) << S_LANE13FS)
10566 #define G_LANE13FS(x) (((x) >> S_LANE13FS) & M_LANE13FS)
10567 
10568 #define S_LANE12LF    8
10569 #define M_LANE12LF    0x3fU
10570 #define V_LANE12LF(x) ((x) << S_LANE12LF)
10571 #define G_LANE12LF(x) (((x) >> S_LANE12LF) & M_LANE12LF)
10572 
10573 #define S_LANE12FS    0
10574 #define M_LANE12FS    0x3fU
10575 #define V_LANE12FS(x) ((x) << S_LANE12FS)
10576 #define G_LANE12FS(x) (((x) >> S_LANE12FS) & M_LANE12FS)
10577 
10578 #define A_PCIE_PHY_FS_LF7 0x5c38
10579 
10580 #define S_LANE15LF    24
10581 #define M_LANE15LF    0x3fU
10582 #define V_LANE15LF(x) ((x) << S_LANE15LF)
10583 #define G_LANE15LF(x) (((x) >> S_LANE15LF) & M_LANE15LF)
10584 
10585 #define S_LANE15FS    16
10586 #define M_LANE15FS    0x3fU
10587 #define V_LANE15FS(x) ((x) << S_LANE15FS)
10588 #define G_LANE15FS(x) (((x) >> S_LANE15FS) & M_LANE15FS)
10589 
10590 #define S_LANE14LF    8
10591 #define M_LANE14LF    0x3fU
10592 #define V_LANE14LF(x) ((x) << S_LANE14LF)
10593 #define G_LANE14LF(x) (((x) >> S_LANE14LF) & M_LANE14LF)
10594 
10595 #define S_LANE14FS    0
10596 #define M_LANE14FS    0x3fU
10597 #define V_LANE14FS(x) ((x) << S_LANE14FS)
10598 #define G_LANE14FS(x) (((x) >> S_LANE14FS) & M_LANE14FS)
10599 
10600 #define A_PCIE_MULTI_PHY_INDIR_REQ 0x5c3c
10601 
10602 #define S_PHY_REG_ENABLE    31
10603 #define V_PHY_REG_ENABLE(x) ((x) << S_PHY_REG_ENABLE)
10604 #define F_PHY_REG_ENABLE    V_PHY_REG_ENABLE(1U)
10605 
10606 #define S_PHY_REG_SELECT    22
10607 #define M_PHY_REG_SELECT    0x3U
10608 #define V_PHY_REG_SELECT(x) ((x) << S_PHY_REG_SELECT)
10609 #define G_PHY_REG_SELECT(x) (((x) >> S_PHY_REG_SELECT) & M_PHY_REG_SELECT)
10610 
10611 #define S_PHY_REG_REGADDR    0
10612 #define M_PHY_REG_REGADDR    0xffffU
10613 #define V_PHY_REG_REGADDR(x) ((x) << S_PHY_REG_REGADDR)
10614 #define G_PHY_REG_REGADDR(x) (((x) >> S_PHY_REG_REGADDR) & M_PHY_REG_REGADDR)
10615 
10616 #define A_PCIE_MULTI_PHY_INDIR_DATA 0x5c40
10617 
10618 #define S_PHY_REG_DATA    0
10619 #define M_PHY_REG_DATA    0xffffU
10620 #define V_PHY_REG_DATA(x) ((x) << S_PHY_REG_DATA)
10621 #define G_PHY_REG_DATA(x) (((x) >> S_PHY_REG_DATA) & M_PHY_REG_DATA)
10622 
10623 #define A_PCIE_VF_INT_INDIR_REQ 0x5c44
10624 
10625 #define S_ENABLE_VF    24
10626 #define V_ENABLE_VF(x) ((x) << S_ENABLE_VF)
10627 #define F_ENABLE_VF    V_ENABLE_VF(1U)
10628 
10629 #define S_AI_VF    23
10630 #define V_AI_VF(x) ((x) << S_AI_VF)
10631 #define F_AI_VF    V_AI_VF(1U)
10632 
10633 #define S_VFID_PCIE    0
10634 #define M_VFID_PCIE    0x3ffU
10635 #define V_VFID_PCIE(x) ((x) << S_VFID_PCIE)
10636 #define G_VFID_PCIE(x) (((x) >> S_VFID_PCIE) & M_VFID_PCIE)
10637 
10638 #define A_PCIE_VF_INT_INDIR_DATA 0x5c48
10639 #define A_PCIE_VF_256_INT_CFG2 0x5c4c
10640 #define A_PCIE_VF_MSI_EN_4 0x5e50
10641 #define A_PCIE_VF_MSI_EN_5 0x5e54
10642 #define A_PCIE_VF_MSI_EN_6 0x5e58
10643 #define A_PCIE_VF_MSI_EN_7 0x5e5c
10644 #define A_PCIE_VF_MSIX_EN_4 0x5e60
10645 #define A_PCIE_VF_MSIX_EN_5 0x5e64
10646 #define A_PCIE_VF_MSIX_EN_6 0x5e68
10647 #define A_PCIE_VF_MSIX_EN_7 0x5e6c
10648 #define A_PCIE_FLR_VF4_STATUS 0x5e70
10649 #define A_PCIE_FLR_VF5_STATUS 0x5e74
10650 #define A_PCIE_FLR_VF6_STATUS 0x5e78
10651 #define A_PCIE_FLR_VF7_STATUS 0x5e7c
10652 #define A_T6_PCIE_BUS_MST_STAT_4 0x5e80
10653 #define A_T7_PCIE_BUS_MST_STAT_4 0x5e80
10654 #define A_T6_PCIE_BUS_MST_STAT_5 0x5e84
10655 #define A_T7_PCIE_BUS_MST_STAT_5 0x5e84
10656 #define A_T6_PCIE_BUS_MST_STAT_6 0x5e88
10657 #define A_T7_PCIE_BUS_MST_STAT_6 0x5e88
10658 #define A_T6_PCIE_BUS_MST_STAT_7 0x5e8c
10659 #define A_T7_PCIE_BUS_MST_STAT_7 0x5e8c
10660 #define A_PCIE_BUS_MST_STAT_8 0x5e90
10661 
10662 #define S_BUSMST_263_256    0
10663 #define M_BUSMST_263_256    0xffU
10664 #define V_BUSMST_263_256(x) ((x) << S_BUSMST_263_256)
10665 #define G_BUSMST_263_256(x) (((x) >> S_BUSMST_263_256) & M_BUSMST_263_256)
10666 
10667 #define A_PCIE_TGT_SKID_FIFO 0x5e94
10668 
10669 #define S_HDRFREECNT    16
10670 #define M_HDRFREECNT    0xfffU
10671 #define V_HDRFREECNT(x) ((x) << S_HDRFREECNT)
10672 #define G_HDRFREECNT(x) (((x) >> S_HDRFREECNT) & M_HDRFREECNT)
10673 
10674 #define S_DATAFREECNT    0
10675 #define M_DATAFREECNT    0xfffU
10676 #define V_DATAFREECNT(x) ((x) << S_DATAFREECNT)
10677 #define G_DATAFREECNT(x) (((x) >> S_DATAFREECNT) & M_DATAFREECNT)
10678 
10679 #define A_T6_PCIE_RSP_ERR_STAT_4 0x5ea0
10680 #define A_T7_PCIE_RSP_ERR_STAT_4 0x5ea0
10681 #define A_T6_PCIE_RSP_ERR_STAT_5 0x5ea4
10682 #define A_T7_PCIE_RSP_ERR_STAT_5 0x5ea4
10683 #define A_T6_PCIE_RSP_ERR_STAT_6 0x5ea8
10684 #define A_T7_PCIE_RSP_ERR_STAT_6 0x5ea8
10685 #define A_T6_PCIE_RSP_ERR_STAT_7 0x5eac
10686 #define A_T7_PCIE_RSP_ERR_STAT_7 0x5eac
10687 #define A_PCIE_RSP_ERR_STAT_8 0x5eb0
10688 
10689 #define S_RSPERR_263_256    0
10690 #define M_RSPERR_263_256    0xffU
10691 #define V_RSPERR_263_256(x) ((x) << S_RSPERR_263_256)
10692 #define G_RSPERR_263_256(x) (((x) >> S_RSPERR_263_256) & M_RSPERR_263_256)
10693 
10694 #define A_PCIE_PHY_STAT1 0x5ec0
10695 
10696 #define S_PHY0_RTUNE_ACK    31
10697 #define V_PHY0_RTUNE_ACK(x) ((x) << S_PHY0_RTUNE_ACK)
10698 #define F_PHY0_RTUNE_ACK    V_PHY0_RTUNE_ACK(1U)
10699 
10700 #define S_PHY1_RTUNE_ACK    30
10701 #define V_PHY1_RTUNE_ACK(x) ((x) << S_PHY1_RTUNE_ACK)
10702 #define F_PHY1_RTUNE_ACK    V_PHY1_RTUNE_ACK(1U)
10703 
10704 #define A_PCIE_PHY_CTRL1 0x5ec4
10705 
10706 #define S_PHY0_RTUNE_REQ    31
10707 #define V_PHY0_RTUNE_REQ(x) ((x) << S_PHY0_RTUNE_REQ)
10708 #define F_PHY0_RTUNE_REQ    V_PHY0_RTUNE_REQ(1U)
10709 
10710 #define S_PHY1_RTUNE_REQ    30
10711 #define V_PHY1_RTUNE_REQ(x) ((x) << S_PHY1_RTUNE_REQ)
10712 #define F_PHY1_RTUNE_REQ    V_PHY1_RTUNE_REQ(1U)
10713 
10714 #define S_TXDEEMPH_GEN1    16
10715 #define M_TXDEEMPH_GEN1    0xffU
10716 #define V_TXDEEMPH_GEN1(x) ((x) << S_TXDEEMPH_GEN1)
10717 #define G_TXDEEMPH_GEN1(x) (((x) >> S_TXDEEMPH_GEN1) & M_TXDEEMPH_GEN1)
10718 
10719 #define S_TXDEEMPH_GEN2_3P5DB    8
10720 #define M_TXDEEMPH_GEN2_3P5DB    0xffU
10721 #define V_TXDEEMPH_GEN2_3P5DB(x) ((x) << S_TXDEEMPH_GEN2_3P5DB)
10722 #define G_TXDEEMPH_GEN2_3P5DB(x) (((x) >> S_TXDEEMPH_GEN2_3P5DB) & M_TXDEEMPH_GEN2_3P5DB)
10723 
10724 #define S_TXDEEMPH_GEN2_6DB    0
10725 #define M_TXDEEMPH_GEN2_6DB    0xffU
10726 #define V_TXDEEMPH_GEN2_6DB(x) ((x) << S_TXDEEMPH_GEN2_6DB)
10727 #define G_TXDEEMPH_GEN2_6DB(x) (((x) >> S_TXDEEMPH_GEN2_6DB) & M_TXDEEMPH_GEN2_6DB)
10728 
10729 #define A_PCIE_PCIE_SPARE0 0x5ec8
10730 #define A_PCIE_RESET_STAT 0x5ecc
10731 
10732 #define S_PON_RST_STATE_FLAG    11
10733 #define V_PON_RST_STATE_FLAG(x) ((x) << S_PON_RST_STATE_FLAG)
10734 #define F_PON_RST_STATE_FLAG    V_PON_RST_STATE_FLAG(1U)
10735 
10736 #define S_BUS_RST_STATE_FLAG    10
10737 #define V_BUS_RST_STATE_FLAG(x) ((x) << S_BUS_RST_STATE_FLAG)
10738 #define F_BUS_RST_STATE_FLAG    V_BUS_RST_STATE_FLAG(1U)
10739 
10740 #define S_DL_DOWN_PCIECRST_MODE0_STATE_FLAG    9
10741 #define V_DL_DOWN_PCIECRST_MODE0_STATE_FLAG(x) ((x) << S_DL_DOWN_PCIECRST_MODE0_STATE_FLAG)
10742 #define F_DL_DOWN_PCIECRST_MODE0_STATE_FLAG    V_DL_DOWN_PCIECRST_MODE0_STATE_FLAG(1U)
10743 
10744 #define S_DL_DOWN_PCIECRST_MODE1_STATE_FLAG    8
10745 #define V_DL_DOWN_PCIECRST_MODE1_STATE_FLAG(x) ((x) << S_DL_DOWN_PCIECRST_MODE1_STATE_FLAG)
10746 #define F_DL_DOWN_PCIECRST_MODE1_STATE_FLAG    V_DL_DOWN_PCIECRST_MODE1_STATE_FLAG(1U)
10747 
10748 #define S_PCIE_WARM_RST_MODE0_STATE_FLAG    7
10749 #define V_PCIE_WARM_RST_MODE0_STATE_FLAG(x) ((x) << S_PCIE_WARM_RST_MODE0_STATE_FLAG)
10750 #define F_PCIE_WARM_RST_MODE0_STATE_FLAG    V_PCIE_WARM_RST_MODE0_STATE_FLAG(1U)
10751 
10752 #define S_PCIE_WARM_RST_MODE1_STATE_FLAG    6
10753 #define V_PCIE_WARM_RST_MODE1_STATE_FLAG(x) ((x) << S_PCIE_WARM_RST_MODE1_STATE_FLAG)
10754 #define F_PCIE_WARM_RST_MODE1_STATE_FLAG    V_PCIE_WARM_RST_MODE1_STATE_FLAG(1U)
10755 
10756 #define S_PIO_WARM_RST_MODE0_STATE_FLAG    5
10757 #define V_PIO_WARM_RST_MODE0_STATE_FLAG(x) ((x) << S_PIO_WARM_RST_MODE0_STATE_FLAG)
10758 #define F_PIO_WARM_RST_MODE0_STATE_FLAG    V_PIO_WARM_RST_MODE0_STATE_FLAG(1U)
10759 
10760 #define S_PIO_WARM_RST_MODE1_STATE_FLAG    4
10761 #define V_PIO_WARM_RST_MODE1_STATE_FLAG(x) ((x) << S_PIO_WARM_RST_MODE1_STATE_FLAG)
10762 #define F_PIO_WARM_RST_MODE1_STATE_FLAG    V_PIO_WARM_RST_MODE1_STATE_FLAG(1U)
10763 
10764 #define S_LASTRESETSTATE    0
10765 #define M_LASTRESETSTATE    0x7U
10766 #define V_LASTRESETSTATE(x) ((x) << S_LASTRESETSTATE)
10767 #define G_LASTRESETSTATE(x) (((x) >> S_LASTRESETSTATE) & M_LASTRESETSTATE)
10768 
10769 #define A_PCIE_FUNC_DSTATE 0x5ed0
10770 
10771 #define S_PF7_DSTATE    21
10772 #define M_PF7_DSTATE    0x7U
10773 #define V_PF7_DSTATE(x) ((x) << S_PF7_DSTATE)
10774 #define G_PF7_DSTATE(x) (((x) >> S_PF7_DSTATE) & M_PF7_DSTATE)
10775 
10776 #define S_PF6_DSTATE    18
10777 #define M_PF6_DSTATE    0x7U
10778 #define V_PF6_DSTATE(x) ((x) << S_PF6_DSTATE)
10779 #define G_PF6_DSTATE(x) (((x) >> S_PF6_DSTATE) & M_PF6_DSTATE)
10780 
10781 #define S_PF5_DSTATE    15
10782 #define M_PF5_DSTATE    0x7U
10783 #define V_PF5_DSTATE(x) ((x) << S_PF5_DSTATE)
10784 #define G_PF5_DSTATE(x) (((x) >> S_PF5_DSTATE) & M_PF5_DSTATE)
10785 
10786 #define S_PF4_DSTATE    12
10787 #define M_PF4_DSTATE    0x7U
10788 #define V_PF4_DSTATE(x) ((x) << S_PF4_DSTATE)
10789 #define G_PF4_DSTATE(x) (((x) >> S_PF4_DSTATE) & M_PF4_DSTATE)
10790 
10791 #define S_PF3_DSTATE    9
10792 #define M_PF3_DSTATE    0x7U
10793 #define V_PF3_DSTATE(x) ((x) << S_PF3_DSTATE)
10794 #define G_PF3_DSTATE(x) (((x) >> S_PF3_DSTATE) & M_PF3_DSTATE)
10795 
10796 #define S_PF2_DSTATE    6
10797 #define M_PF2_DSTATE    0x7U
10798 #define V_PF2_DSTATE(x) ((x) << S_PF2_DSTATE)
10799 #define G_PF2_DSTATE(x) (((x) >> S_PF2_DSTATE) & M_PF2_DSTATE)
10800 
10801 #define S_PF1_DSTATE    3
10802 #define M_PF1_DSTATE    0x7U
10803 #define V_PF1_DSTATE(x) ((x) << S_PF1_DSTATE)
10804 #define G_PF1_DSTATE(x) (((x) >> S_PF1_DSTATE) & M_PF1_DSTATE)
10805 
10806 #define S_PF0_DSTATE    0
10807 #define M_PF0_DSTATE    0x7U
10808 #define V_PF0_DSTATE(x) ((x) << S_PF0_DSTATE)
10809 #define G_PF0_DSTATE(x) (((x) >> S_PF0_DSTATE) & M_PF0_DSTATE)
10810 
10811 #define A_PCIE_DEBUG_ADDR_RANGE1 0x5ee0
10812 #define A_PCIE_DEBUG_ADDR_RANGE2 0x5ef0
10813 #define A_PCIE_DEBUG_ADDR_RANGE_CNT 0x5f00
10814 #define A_PCIE_PHY_PGM_LOAD_CTRL 0x5f04
10815 
10816 #define S_HSS_PMLD_ACC_EN    31
10817 #define V_HSS_PMLD_ACC_EN(x) ((x) << S_HSS_PMLD_ACC_EN)
10818 #define F_HSS_PMLD_ACC_EN    V_HSS_PMLD_ACC_EN(1U)
10819 
10820 #define S_HSS_PMRDWR_ADDR    0
10821 #define M_HSS_PMRDWR_ADDR    0x3ffffU
10822 #define V_HSS_PMRDWR_ADDR(x) ((x) << S_HSS_PMRDWR_ADDR)
10823 #define G_HSS_PMRDWR_ADDR(x) (((x) >> S_HSS_PMRDWR_ADDR) & M_HSS_PMRDWR_ADDR)
10824 
10825 #define A_PCIE_PHY_PGM_LOAD_DATA 0x5f08
10826 #define A_PCIE_HSS_CFG 0x5f0c
10827 
10828 #define S_HSS_PCS_AGGREGATION_MODE    30
10829 #define M_HSS_PCS_AGGREGATION_MODE    0x3U
10830 #define V_HSS_PCS_AGGREGATION_MODE(x) ((x) << S_HSS_PCS_AGGREGATION_MODE)
10831 #define G_HSS_PCS_AGGREGATION_MODE(x) (((x) >> S_HSS_PCS_AGGREGATION_MODE) & M_HSS_PCS_AGGREGATION_MODE)
10832 
10833 #define S_HSS_PCS_FURCATE_MODE    28
10834 #define M_HSS_PCS_FURCATE_MODE    0x3U
10835 #define V_HSS_PCS_FURCATE_MODE(x) ((x) << S_HSS_PCS_FURCATE_MODE)
10836 #define G_HSS_PCS_FURCATE_MODE(x) (((x) >> S_HSS_PCS_FURCATE_MODE) & M_HSS_PCS_FURCATE_MODE)
10837 
10838 #define S_HSS_PCS_PCLK_ON_IN_P2    27
10839 #define V_HSS_PCS_PCLK_ON_IN_P2(x) ((x) << S_HSS_PCS_PCLK_ON_IN_P2)
10840 #define F_HSS_PCS_PCLK_ON_IN_P2    V_HSS_PCS_PCLK_ON_IN_P2(1U)
10841 
10842 #define S_HSS0_PHY_CTRL_REFCLK    17
10843 #define M_HSS0_PHY_CTRL_REFCLK    0x1fU
10844 #define V_HSS0_PHY_CTRL_REFCLK(x) ((x) << S_HSS0_PHY_CTRL_REFCLK)
10845 #define G_HSS0_PHY_CTRL_REFCLK(x) (((x) >> S_HSS0_PHY_CTRL_REFCLK) & M_HSS0_PHY_CTRL_REFCLK)
10846 
10847 #define S_HSS1_PHY_CTRL_REFCLK    12
10848 #define M_HSS1_PHY_CTRL_REFCLK    0x1fU
10849 #define V_HSS1_PHY_CTRL_REFCLK(x) ((x) << S_HSS1_PHY_CTRL_REFCLK)
10850 #define G_HSS1_PHY_CTRL_REFCLK(x) (((x) >> S_HSS1_PHY_CTRL_REFCLK) & M_HSS1_PHY_CTRL_REFCLK)
10851 
10852 #define S_HSS0_PHY_REXT_MASTER    11
10853 #define V_HSS0_PHY_REXT_MASTER(x) ((x) << S_HSS0_PHY_REXT_MASTER)
10854 #define F_HSS0_PHY_REXT_MASTER    V_HSS0_PHY_REXT_MASTER(1U)
10855 
10856 #define S_HSS1_PHY_REXT_MASTER    10
10857 #define V_HSS1_PHY_REXT_MASTER(x) ((x) << S_HSS1_PHY_REXT_MASTER)
10858 #define F_HSS1_PHY_REXT_MASTER    V_HSS1_PHY_REXT_MASTER(1U)
10859 
10860 #define S_HSS0_PHY_CTRL_VDDA_SEL    9
10861 #define V_HSS0_PHY_CTRL_VDDA_SEL(x) ((x) << S_HSS0_PHY_CTRL_VDDA_SEL)
10862 #define F_HSS0_PHY_CTRL_VDDA_SEL    V_HSS0_PHY_CTRL_VDDA_SEL(1U)
10863 
10864 #define S_HSS0_PHY_CTRL_VDDHA_SEL    8
10865 #define V_HSS0_PHY_CTRL_VDDHA_SEL(x) ((x) << S_HSS0_PHY_CTRL_VDDHA_SEL)
10866 #define F_HSS0_PHY_CTRL_VDDHA_SEL    V_HSS0_PHY_CTRL_VDDHA_SEL(1U)
10867 
10868 #define S_HSS1_PHY_CTRL_VDDA_SEL    7
10869 #define V_HSS1_PHY_CTRL_VDDA_SEL(x) ((x) << S_HSS1_PHY_CTRL_VDDA_SEL)
10870 #define F_HSS1_PHY_CTRL_VDDA_SEL    V_HSS1_PHY_CTRL_VDDA_SEL(1U)
10871 
10872 #define S_HSS1_PHY_CTRL_VDDHA_SEL    6
10873 #define V_HSS1_PHY_CTRL_VDDHA_SEL(x) ((x) << S_HSS1_PHY_CTRL_VDDHA_SEL)
10874 #define F_HSS1_PHY_CTRL_VDDHA_SEL    V_HSS1_PHY_CTRL_VDDHA_SEL(1U)
10875 
10876 #define S_HSS1_CPU_MEMPSACK    5
10877 #define V_HSS1_CPU_MEMPSACK(x) ((x) << S_HSS1_CPU_MEMPSACK)
10878 #define F_HSS1_CPU_MEMPSACK    V_HSS1_CPU_MEMPSACK(1U)
10879 
10880 #define S_HSS0_CPU_MEMPSACK    3
10881 #define V_HSS0_CPU_MEMPSACK(x) ((x) << S_HSS0_CPU_MEMPSACK)
10882 #define F_HSS0_CPU_MEMPSACK    V_HSS0_CPU_MEMPSACK(1U)
10883 
10884 #define S_HSS1_CPU_MEMACK    4
10885 #define V_HSS1_CPU_MEMACK(x) ((x) << S_HSS1_CPU_MEMACK)
10886 #define F_HSS1_CPU_MEMACK    V_HSS1_CPU_MEMACK(1U)
10887 
10888 #define S_HSS0_CPU_MEMACK    2
10889 #define V_HSS0_CPU_MEMACK(x) ((x) << S_HSS0_CPU_MEMACK)
10890 #define F_HSS0_CPU_MEMACK    V_HSS0_CPU_MEMACK(1U)
10891 
10892 #define S_HSS_PM_IS_ROM    1
10893 #define V_HSS_PM_IS_ROM(x) ((x) << S_HSS_PM_IS_ROM)
10894 #define F_HSS_PM_IS_ROM    V_HSS_PM_IS_ROM(1U)
10895 
10896 #define A_PCIE_HSS_RST 0x5f10
10897 
10898 #define S_HSS_RST_CTRL_BY_FW    31
10899 #define V_HSS_RST_CTRL_BY_FW(x) ((x) << S_HSS_RST_CTRL_BY_FW)
10900 #define F_HSS_RST_CTRL_BY_FW    V_HSS_RST_CTRL_BY_FW(1U)
10901 
10902 #define S_HSS_PIPE0_RESET_N    30
10903 #define V_HSS_PIPE0_RESET_N(x) ((x) << S_HSS_PIPE0_RESET_N)
10904 #define F_HSS_PIPE0_RESET_N    V_HSS_PIPE0_RESET_N(1U)
10905 
10906 #define S_HSS0_POR_N    29
10907 #define V_HSS0_POR_N(x) ((x) << S_HSS0_POR_N)
10908 #define F_HSS0_POR_N    V_HSS0_POR_N(1U)
10909 
10910 #define S_HSS1_POR_N    28
10911 #define V_HSS1_POR_N(x) ((x) << S_HSS1_POR_N)
10912 #define F_HSS1_POR_N    V_HSS1_POR_N(1U)
10913 
10914 #define S_HSS0_CPU_RESET    27
10915 #define V_HSS0_CPU_RESET(x) ((x) << S_HSS0_CPU_RESET)
10916 #define F_HSS0_CPU_RESET    V_HSS0_CPU_RESET(1U)
10917 
10918 #define S_HSS1_CPU_RESET    26
10919 #define V_HSS1_CPU_RESET(x) ((x) << S_HSS1_CPU_RESET)
10920 #define F_HSS1_CPU_RESET    V_HSS1_CPU_RESET(1U)
10921 
10922 #define S_HSS_PCS_POR_N    25
10923 #define V_HSS_PCS_POR_N(x) ((x) << S_HSS_PCS_POR_N)
10924 #define F_HSS_PCS_POR_N    V_HSS_PCS_POR_N(1U)
10925 
10926 #define S_SW_CRST_    24
10927 #define V_SW_CRST_(x) ((x) << S_SW_CRST_)
10928 #define F_SW_CRST_    V_SW_CRST_(1U)
10929 
10930 #define S_SW_PCIECRST_    23
10931 #define V_SW_PCIECRST_(x) ((x) << S_SW_PCIECRST_)
10932 #define F_SW_PCIECRST_    V_SW_PCIECRST_(1U)
10933 
10934 #define S_SW_PCIEPIPERST_    22
10935 #define V_SW_PCIEPIPERST_(x) ((x) << S_SW_PCIEPIPERST_)
10936 #define F_SW_PCIEPIPERST_    V_SW_PCIEPIPERST_(1U)
10937 
10938 #define S_SW_PCIEPHYRST_    21
10939 #define V_SW_PCIEPHYRST_(x) ((x) << S_SW_PCIEPHYRST_)
10940 #define F_SW_PCIEPHYRST_    V_SW_PCIEPHYRST_(1U)
10941 
10942 #define S_HSS1_ERR_O    3
10943 #define V_HSS1_ERR_O(x) ((x) << S_HSS1_ERR_O)
10944 #define F_HSS1_ERR_O    V_HSS1_ERR_O(1U)
10945 
10946 #define S_HSS0_ERR_O    2
10947 #define V_HSS0_ERR_O(x) ((x) << S_HSS0_ERR_O)
10948 #define F_HSS0_ERR_O    V_HSS0_ERR_O(1U)
10949 
10950 #define S_HSS1_PLL_LOCK    1
10951 #define V_HSS1_PLL_LOCK(x) ((x) << S_HSS1_PLL_LOCK)
10952 #define F_HSS1_PLL_LOCK    V_HSS1_PLL_LOCK(1U)
10953 
10954 #define S_HSS0_PLL_LOCK    0
10955 #define V_HSS0_PLL_LOCK(x) ((x) << S_HSS0_PLL_LOCK)
10956 #define F_HSS0_PLL_LOCK    V_HSS0_PLL_LOCK(1U)
10957 
10958 #define A_PCIE_T5_ARM_CFG 0x5f20
10959 
10960 #define S_T5_ARM_MAXREQCNT    20
10961 #define M_T5_ARM_MAXREQCNT    0x7fU
10962 #define V_T5_ARM_MAXREQCNT(x) ((x) << S_T5_ARM_MAXREQCNT)
10963 #define G_T5_ARM_MAXREQCNT(x) (((x) >> S_T5_ARM_MAXREQCNT) & M_T5_ARM_MAXREQCNT)
10964 
10965 #define S_T5_ARM_MAXRDREQSIZE    17
10966 #define M_T5_ARM_MAXRDREQSIZE    0x7U
10967 #define V_T5_ARM_MAXRDREQSIZE(x) ((x) << S_T5_ARM_MAXRDREQSIZE)
10968 #define G_T5_ARM_MAXRDREQSIZE(x) (((x) >> S_T5_ARM_MAXRDREQSIZE) & M_T5_ARM_MAXRDREQSIZE)
10969 
10970 #define S_T5_ARM_MAXRSPCNT    9
10971 #define M_T5_ARM_MAXRSPCNT    0xffU
10972 #define V_T5_ARM_MAXRSPCNT(x) ((x) << S_T5_ARM_MAXRSPCNT)
10973 #define G_T5_ARM_MAXRSPCNT(x) (((x) >> S_T5_ARM_MAXRSPCNT) & M_T5_ARM_MAXRSPCNT)
10974 
10975 #define A_PCIE_T5_ARM_STAT 0x5f24
10976 
10977 #define S_ARM_RESPCNT    20
10978 #define M_ARM_RESPCNT    0x1ffU
10979 #define V_ARM_RESPCNT(x) ((x) << S_ARM_RESPCNT)
10980 #define G_ARM_RESPCNT(x) (((x) >> S_ARM_RESPCNT) & M_ARM_RESPCNT)
10981 
10982 #define S_ARM_RDREQCNT    12
10983 #define M_ARM_RDREQCNT    0x3fU
10984 #define V_ARM_RDREQCNT(x) ((x) << S_ARM_RDREQCNT)
10985 #define G_ARM_RDREQCNT(x) (((x) >> S_ARM_RDREQCNT) & M_ARM_RDREQCNT)
10986 
10987 #define S_ARM_WRREQCNT    0
10988 #define M_ARM_WRREQCNT    0x1ffU
10989 #define V_ARM_WRREQCNT(x) ((x) << S_ARM_WRREQCNT)
10990 #define G_ARM_WRREQCNT(x) (((x) >> S_ARM_WRREQCNT) & M_ARM_WRREQCNT)
10991 
10992 #define A_PCIE_T5_ARM_STAT2 0x5f28
10993 
10994 #define S_ARM_COOKIECNT    24
10995 #define M_ARM_COOKIECNT    0xfU
10996 #define V_ARM_COOKIECNT(x) ((x) << S_ARM_COOKIECNT)
10997 #define G_ARM_COOKIECNT(x) (((x) >> S_ARM_COOKIECNT) & M_ARM_COOKIECNT)
10998 
10999 #define S_ARM_RDSEQNUMUPDCNT    20
11000 #define M_ARM_RDSEQNUMUPDCNT    0xfU
11001 #define V_ARM_RDSEQNUMUPDCNT(x) ((x) << S_ARM_RDSEQNUMUPDCNT)
11002 #define G_ARM_RDSEQNUMUPDCNT(x) (((x) >> S_ARM_RDSEQNUMUPDCNT) & M_ARM_RDSEQNUMUPDCNT)
11003 
11004 #define S_ARM_SIREQCNT    16
11005 #define M_ARM_SIREQCNT    0xfU
11006 #define V_ARM_SIREQCNT(x) ((x) << S_ARM_SIREQCNT)
11007 #define G_ARM_SIREQCNT(x) (((x) >> S_ARM_SIREQCNT) & M_ARM_SIREQCNT)
11008 
11009 #define S_ARM_WREOPMATCHSOP    12
11010 #define V_ARM_WREOPMATCHSOP(x) ((x) << S_ARM_WREOPMATCHSOP)
11011 #define F_ARM_WREOPMATCHSOP    V_ARM_WREOPMATCHSOP(1U)
11012 
11013 #define S_ARM_WRSOPCNT    8
11014 #define M_ARM_WRSOPCNT    0xfU
11015 #define V_ARM_WRSOPCNT(x) ((x) << S_ARM_WRSOPCNT)
11016 #define G_ARM_WRSOPCNT(x) (((x) >> S_ARM_WRSOPCNT) & M_ARM_WRSOPCNT)
11017 
11018 #define S_ARM_RDSOPCNT    0
11019 #define M_ARM_RDSOPCNT    0xffU
11020 #define V_ARM_RDSOPCNT(x) ((x) << S_ARM_RDSOPCNT)
11021 #define G_ARM_RDSOPCNT(x) (((x) >> S_ARM_RDSOPCNT) & M_ARM_RDSOPCNT)
11022 
11023 #define A_PCIE_T5_ARM_STAT3 0x5f2c
11024 
11025 #define S_ARM_ATMREQSOPCNT    24
11026 #define M_ARM_ATMREQSOPCNT    0xffU
11027 #define V_ARM_ATMREQSOPCNT(x) ((x) << S_ARM_ATMREQSOPCNT)
11028 #define G_ARM_ATMREQSOPCNT(x) (((x) >> S_ARM_ATMREQSOPCNT) & M_ARM_ATMREQSOPCNT)
11029 
11030 #define S_ARM_ATMEOPMATCHSOP    17
11031 #define V_ARM_ATMEOPMATCHSOP(x) ((x) << S_ARM_ATMEOPMATCHSOP)
11032 #define F_ARM_ATMEOPMATCHSOP    V_ARM_ATMEOPMATCHSOP(1U)
11033 
11034 #define S_ARM_RSPEOPMATCHSOP    16
11035 #define V_ARM_RSPEOPMATCHSOP(x) ((x) << S_ARM_RSPEOPMATCHSOP)
11036 #define F_ARM_RSPEOPMATCHSOP    V_ARM_RSPEOPMATCHSOP(1U)
11037 
11038 #define S_ARM_RSPERRCNT    8
11039 #define M_ARM_RSPERRCNT    0xffU
11040 #define V_ARM_RSPERRCNT(x) ((x) << S_ARM_RSPERRCNT)
11041 #define G_ARM_RSPERRCNT(x) (((x) >> S_ARM_RSPERRCNT) & M_ARM_RSPERRCNT)
11042 
11043 #define S_ARM_RSPSOPCNT    0
11044 #define M_ARM_RSPSOPCNT    0xffU
11045 #define V_ARM_RSPSOPCNT(x) ((x) << S_ARM_RSPSOPCNT)
11046 #define G_ARM_RSPSOPCNT(x) (((x) >> S_ARM_RSPSOPCNT) & M_ARM_RSPSOPCNT)
11047 
11048 #define A_PCIE_ARM_REQUESTER_ID 0x5f30
11049 
11050 #define S_A0_RSVD1    24
11051 #define M_A0_RSVD1    0xffU
11052 #define V_A0_RSVD1(x) ((x) << S_A0_RSVD1)
11053 #define G_A0_RSVD1(x) (((x) >> S_A0_RSVD1) & M_A0_RSVD1)
11054 
11055 #define S_A0_PRIMBUSNUMBER    16
11056 #define M_A0_PRIMBUSNUMBER    0xffU
11057 #define V_A0_PRIMBUSNUMBER(x) ((x) << S_A0_PRIMBUSNUMBER)
11058 #define G_A0_PRIMBUSNUMBER(x) (((x) >> S_A0_PRIMBUSNUMBER) & M_A0_PRIMBUSNUMBER)
11059 
11060 #define S_A0_REQUESTERID    0
11061 #define M_A0_REQUESTERID    0xffffU
11062 #define V_A0_REQUESTERID(x) ((x) << S_A0_REQUESTERID)
11063 #define G_A0_REQUESTERID(x) (((x) >> S_A0_REQUESTERID) & M_A0_REQUESTERID)
11064 
11065 #define A_PCIE_SWITCH_CFG_SPACE_REQ0 0x5f34
11066 
11067 #define S_REQ0ENABLE    31
11068 #define V_REQ0ENABLE(x) ((x) << S_REQ0ENABLE)
11069 #define F_REQ0ENABLE    V_REQ0ENABLE(1U)
11070 
11071 #define S_RDREQ0TYPE    19
11072 #define V_RDREQ0TYPE(x) ((x) << S_RDREQ0TYPE)
11073 #define F_RDREQ0TYPE    V_RDREQ0TYPE(1U)
11074 
11075 #define S_BYTEENABLE0    15
11076 #define M_BYTEENABLE0    0xfU
11077 #define V_BYTEENABLE0(x) ((x) << S_BYTEENABLE0)
11078 #define G_BYTEENABLE0(x) (((x) >> S_BYTEENABLE0) & M_BYTEENABLE0)
11079 
11080 #define S_REGADDR0    0
11081 #define M_REGADDR0    0x7fffU
11082 #define V_REGADDR0(x) ((x) << S_REGADDR0)
11083 #define G_REGADDR0(x) (((x) >> S_REGADDR0) & M_REGADDR0)
11084 
11085 #define A_PCIE_SWITCH_CFG_SPACE_DATA0 0x5f38
11086 #define A_PCIE_SWITCH_CFG_SPACE_REQ1 0x5f3c
11087 
11088 #define S_REQ1ENABLE    31
11089 #define V_REQ1ENABLE(x) ((x) << S_REQ1ENABLE)
11090 #define F_REQ1ENABLE    V_REQ1ENABLE(1U)
11091 
11092 #define S_RDREQ1TYPE    26
11093 #define M_RDREQ1TYPE    0xfU
11094 #define V_RDREQ1TYPE(x) ((x) << S_RDREQ1TYPE)
11095 #define G_RDREQ1TYPE(x) (((x) >> S_RDREQ1TYPE) & M_RDREQ1TYPE)
11096 
11097 #define S_BYTEENABLE1    15
11098 #define M_BYTEENABLE1    0x7ffU
11099 #define V_BYTEENABLE1(x) ((x) << S_BYTEENABLE1)
11100 #define G_BYTEENABLE1(x) (((x) >> S_BYTEENABLE1) & M_BYTEENABLE1)
11101 
11102 #define S_REGADDR1    0
11103 #define M_REGADDR1    0x7fffU
11104 #define V_REGADDR1(x) ((x) << S_REGADDR1)
11105 #define G_REGADDR1(x) (((x) >> S_REGADDR1) & M_REGADDR1)
11106 
11107 #define A_PCIE_SWITCH_CFG_SPACE_DATA1 0x5f40
11108 #define A_PCIE_SWITCH_CFG_SPACE_REQ2 0x5f44
11109 
11110 #define S_REQ2ENABLE    31
11111 #define V_REQ2ENABLE(x) ((x) << S_REQ2ENABLE)
11112 #define F_REQ2ENABLE    V_REQ2ENABLE(1U)
11113 
11114 #define S_RDREQ2TYPE    26
11115 #define M_RDREQ2TYPE    0xfU
11116 #define V_RDREQ2TYPE(x) ((x) << S_RDREQ2TYPE)
11117 #define G_RDREQ2TYPE(x) (((x) >> S_RDREQ2TYPE) & M_RDREQ2TYPE)
11118 
11119 #define S_BYTEENABLE2    15
11120 #define M_BYTEENABLE2    0x7ffU
11121 #define V_BYTEENABLE2(x) ((x) << S_BYTEENABLE2)
11122 #define G_BYTEENABLE2(x) (((x) >> S_BYTEENABLE2) & M_BYTEENABLE2)
11123 
11124 #define S_REGADDR2    0
11125 #define M_REGADDR2    0x7fffU
11126 #define V_REGADDR2(x) ((x) << S_REGADDR2)
11127 #define G_REGADDR2(x) (((x) >> S_REGADDR2) & M_REGADDR2)
11128 
11129 #define A_PCIE_SWITCH_CFG_SPACE_DATA2 0x5f48
11130 #define A_PCIE_SWITCH_CFG_SPACE_REQ3 0x5f4c
11131 
11132 #define S_REQ3ENABLE    31
11133 #define V_REQ3ENABLE(x) ((x) << S_REQ3ENABLE)
11134 #define F_REQ3ENABLE    V_REQ3ENABLE(1U)
11135 
11136 #define S_RDREQ3TYPE    26
11137 #define M_RDREQ3TYPE    0xfU
11138 #define V_RDREQ3TYPE(x) ((x) << S_RDREQ3TYPE)
11139 #define G_RDREQ3TYPE(x) (((x) >> S_RDREQ3TYPE) & M_RDREQ3TYPE)
11140 
11141 #define S_BYTEENABLE3    15
11142 #define M_BYTEENABLE3    0x7ffU
11143 #define V_BYTEENABLE3(x) ((x) << S_BYTEENABLE3)
11144 #define G_BYTEENABLE3(x) (((x) >> S_BYTEENABLE3) & M_BYTEENABLE3)
11145 
11146 #define S_REGADDR3    0
11147 #define M_REGADDR3    0x7fffU
11148 #define V_REGADDR3(x) ((x) << S_REGADDR3)
11149 #define G_REGADDR3(x) (((x) >> S_REGADDR3) & M_REGADDR3)
11150 
11151 #define A_PCIE_SWITCH_CFG_SPACE_DATA3 0x5f50
11152 #define A_PCIE_SWITCH_CFG_SPACE_REQ4 0x5f54
11153 
11154 #define S_REQ4ENABLE    31
11155 #define V_REQ4ENABLE(x) ((x) << S_REQ4ENABLE)
11156 #define F_REQ4ENABLE    V_REQ4ENABLE(1U)
11157 
11158 #define S_RDREQ4TYPE    26
11159 #define M_RDREQ4TYPE    0xfU
11160 #define V_RDREQ4TYPE(x) ((x) << S_RDREQ4TYPE)
11161 #define G_RDREQ4TYPE(x) (((x) >> S_RDREQ4TYPE) & M_RDREQ4TYPE)
11162 
11163 #define S_BYTEENABLE4    15
11164 #define M_BYTEENABLE4    0x7ffU
11165 #define V_BYTEENABLE4(x) ((x) << S_BYTEENABLE4)
11166 #define G_BYTEENABLE4(x) (((x) >> S_BYTEENABLE4) & M_BYTEENABLE4)
11167 
11168 #define S_REGADDR4    0
11169 #define M_REGADDR4    0x7fffU
11170 #define V_REGADDR4(x) ((x) << S_REGADDR4)
11171 #define G_REGADDR4(x) (((x) >> S_REGADDR4) & M_REGADDR4)
11172 
11173 #define A_PCIE_SWITCH_CFG_SPACE_DATA4 0x5f58
11174 #define A_PCIE_SWITCH_CFG_SPACE_REQ5 0x5f5c
11175 
11176 #define S_REQ5ENABLE    31
11177 #define V_REQ5ENABLE(x) ((x) << S_REQ5ENABLE)
11178 #define F_REQ5ENABLE    V_REQ5ENABLE(1U)
11179 
11180 #define S_RDREQ5TYPE    26
11181 #define M_RDREQ5TYPE    0xfU
11182 #define V_RDREQ5TYPE(x) ((x) << S_RDREQ5TYPE)
11183 #define G_RDREQ5TYPE(x) (((x) >> S_RDREQ5TYPE) & M_RDREQ5TYPE)
11184 
11185 #define S_BYTEENABLE5    15
11186 #define M_BYTEENABLE5    0x7ffU
11187 #define V_BYTEENABLE5(x) ((x) << S_BYTEENABLE5)
11188 #define G_BYTEENABLE5(x) (((x) >> S_BYTEENABLE5) & M_BYTEENABLE5)
11189 
11190 #define S_REGADDR5    0
11191 #define M_REGADDR5    0x7fffU
11192 #define V_REGADDR5(x) ((x) << S_REGADDR5)
11193 #define G_REGADDR5(x) (((x) >> S_REGADDR5) & M_REGADDR5)
11194 
11195 #define A_PCIE_SWITCH_CFG_SPACE_DATA5 0x5f60
11196 #define A_PCIE_SWITCH_CFG_SPACE_REQ6 0x5f64
11197 
11198 #define S_REQ6ENABLE    31
11199 #define V_REQ6ENABLE(x) ((x) << S_REQ6ENABLE)
11200 #define F_REQ6ENABLE    V_REQ6ENABLE(1U)
11201 
11202 #define S_RDREQ6TYPE    26
11203 #define M_RDREQ6TYPE    0xfU
11204 #define V_RDREQ6TYPE(x) ((x) << S_RDREQ6TYPE)
11205 #define G_RDREQ6TYPE(x) (((x) >> S_RDREQ6TYPE) & M_RDREQ6TYPE)
11206 
11207 #define S_BYTEENABLE6    15
11208 #define M_BYTEENABLE6    0x7ffU
11209 #define V_BYTEENABLE6(x) ((x) << S_BYTEENABLE6)
11210 #define G_BYTEENABLE6(x) (((x) >> S_BYTEENABLE6) & M_BYTEENABLE6)
11211 
11212 #define S_REGADDR6    0
11213 #define M_REGADDR6    0x7fffU
11214 #define V_REGADDR6(x) ((x) << S_REGADDR6)
11215 #define G_REGADDR6(x) (((x) >> S_REGADDR6) & M_REGADDR6)
11216 
11217 #define A_PCIE_SWITCH_CFG_SPACE_DATA6 0x5f68
11218 #define A_PCIE_SWITCH_CFG_SPACE_REQ7 0x5f6c
11219 
11220 #define S_REQ7ENABLE    31
11221 #define V_REQ7ENABLE(x) ((x) << S_REQ7ENABLE)
11222 #define F_REQ7ENABLE    V_REQ7ENABLE(1U)
11223 
11224 #define S_RDREQ7TYPE    26
11225 #define M_RDREQ7TYPE    0xfU
11226 #define V_RDREQ7TYPE(x) ((x) << S_RDREQ7TYPE)
11227 #define G_RDREQ7TYPE(x) (((x) >> S_RDREQ7TYPE) & M_RDREQ7TYPE)
11228 
11229 #define S_BYTEENABLE7    15
11230 #define M_BYTEENABLE7    0x7ffU
11231 #define V_BYTEENABLE7(x) ((x) << S_BYTEENABLE7)
11232 #define G_BYTEENABLE7(x) (((x) >> S_BYTEENABLE7) & M_BYTEENABLE7)
11233 
11234 #define S_REGADDR7    0
11235 #define M_REGADDR7    0x7fffU
11236 #define V_REGADDR7(x) ((x) << S_REGADDR7)
11237 #define G_REGADDR7(x) (((x) >> S_REGADDR7) & M_REGADDR7)
11238 
11239 #define A_PCIE_SWITCH_CFG_SPACE_DATA7 0x5f70
11240 #define A_PCIE_SWITCH_CFG_SPACE_REQ8 0x5f74
11241 
11242 #define S_REQ8ENABLE    31
11243 #define V_REQ8ENABLE(x) ((x) << S_REQ8ENABLE)
11244 #define F_REQ8ENABLE    V_REQ8ENABLE(1U)
11245 
11246 #define S_RDREQ8TYPE    26
11247 #define M_RDREQ8TYPE    0xfU
11248 #define V_RDREQ8TYPE(x) ((x) << S_RDREQ8TYPE)
11249 #define G_RDREQ8TYPE(x) (((x) >> S_RDREQ8TYPE) & M_RDREQ8TYPE)
11250 
11251 #define S_BYTEENABLE8    15
11252 #define M_BYTEENABLE8    0x7ffU
11253 #define V_BYTEENABLE8(x) ((x) << S_BYTEENABLE8)
11254 #define G_BYTEENABLE8(x) (((x) >> S_BYTEENABLE8) & M_BYTEENABLE8)
11255 
11256 #define S_REGADDR8    0
11257 #define M_REGADDR8    0x7fffU
11258 #define V_REGADDR8(x) ((x) << S_REGADDR8)
11259 #define G_REGADDR8(x) (((x) >> S_REGADDR8) & M_REGADDR8)
11260 
11261 #define A_PCIE_SWITCH_CFG_SPACE_DATA8 0x5f78
11262 #define A_PCIE_SNPS_G5_PHY_CR_REQ 0x5f7c
11263 
11264 #define S_REGSEL    31
11265 #define V_REGSEL(x) ((x) << S_REGSEL)
11266 #define F_REGSEL    V_REGSEL(1U)
11267 
11268 #define S_RDENABLE    30
11269 #define V_RDENABLE(x) ((x) << S_RDENABLE)
11270 #define F_RDENABLE    V_RDENABLE(1U)
11271 
11272 #define S_WRENABLE    29
11273 #define V_WRENABLE(x) ((x) << S_WRENABLE)
11274 #define F_WRENABLE    V_WRENABLE(1U)
11275 
11276 #define S_AUTOINCRVAL    21
11277 #define M_AUTOINCRVAL    0x3U
11278 #define V_AUTOINCRVAL(x) ((x) << S_AUTOINCRVAL)
11279 #define G_AUTOINCRVAL(x) (((x) >> S_AUTOINCRVAL) & M_AUTOINCRVAL)
11280 
11281 #define S_AUTOINCR    20
11282 #define V_AUTOINCR(x) ((x) << S_AUTOINCR)
11283 #define F_AUTOINCR    V_AUTOINCR(1U)
11284 
11285 #define S_PHYSEL    16
11286 #define M_PHYSEL    0xfU
11287 #define V_PHYSEL(x) ((x) << S_PHYSEL)
11288 #define G_PHYSEL(x) (((x) >> S_PHYSEL) & M_PHYSEL)
11289 
11290 #define S_T7_REGADDR    0
11291 #define M_T7_REGADDR    0xffffU
11292 #define V_T7_REGADDR(x) ((x) << S_T7_REGADDR)
11293 #define G_T7_REGADDR(x) (((x) >> S_T7_REGADDR) & M_T7_REGADDR)
11294 
11295 #define A_PCIE_SNPS_G5_PHY_CR_DATA 0x5f80
11296 #define A_PCIE_SNPS_G5_PHY_SRAM_CFG 0x5f84
11297 
11298 #define S_PHY3_SRAM_BOOTLOAD_BYPASS    27
11299 #define V_PHY3_SRAM_BOOTLOAD_BYPASS(x) ((x) << S_PHY3_SRAM_BOOTLOAD_BYPASS)
11300 #define F_PHY3_SRAM_BOOTLOAD_BYPASS    V_PHY3_SRAM_BOOTLOAD_BYPASS(1U)
11301 
11302 #define S_PHY3_SRAM_BYPASS    26
11303 #define V_PHY3_SRAM_BYPASS(x) ((x) << S_PHY3_SRAM_BYPASS)
11304 #define F_PHY3_SRAM_BYPASS    V_PHY3_SRAM_BYPASS(1U)
11305 
11306 #define S_PHY3_SRAM_ECC_EN    25
11307 #define V_PHY3_SRAM_ECC_EN(x) ((x) << S_PHY3_SRAM_ECC_EN)
11308 #define F_PHY3_SRAM_ECC_EN    V_PHY3_SRAM_ECC_EN(1U)
11309 
11310 #define S_PHY3_SRAM_EXT_LD_DONE    24
11311 #define V_PHY3_SRAM_EXT_LD_DONE(x) ((x) << S_PHY3_SRAM_EXT_LD_DONE)
11312 #define F_PHY3_SRAM_EXT_LD_DONE    V_PHY3_SRAM_EXT_LD_DONE(1U)
11313 
11314 #define S_PHY2_SRAM_BOOTLOAD_BYPASS    19
11315 #define V_PHY2_SRAM_BOOTLOAD_BYPASS(x) ((x) << S_PHY2_SRAM_BOOTLOAD_BYPASS)
11316 #define F_PHY2_SRAM_BOOTLOAD_BYPASS    V_PHY2_SRAM_BOOTLOAD_BYPASS(1U)
11317 
11318 #define S_PHY2_SRAM_BYPASS    18
11319 #define V_PHY2_SRAM_BYPASS(x) ((x) << S_PHY2_SRAM_BYPASS)
11320 #define F_PHY2_SRAM_BYPASS    V_PHY2_SRAM_BYPASS(1U)
11321 
11322 #define S_PHY2_SRAM_ECC_EN    17
11323 #define V_PHY2_SRAM_ECC_EN(x) ((x) << S_PHY2_SRAM_ECC_EN)
11324 #define F_PHY2_SRAM_ECC_EN    V_PHY2_SRAM_ECC_EN(1U)
11325 
11326 #define S_PHY2_SRAM_EXT_LD_DONE    16
11327 #define V_PHY2_SRAM_EXT_LD_DONE(x) ((x) << S_PHY2_SRAM_EXT_LD_DONE)
11328 #define F_PHY2_SRAM_EXT_LD_DONE    V_PHY2_SRAM_EXT_LD_DONE(1U)
11329 
11330 #define S_PHY1_SRAM_BOOTLOAD_BYPASS    11
11331 #define V_PHY1_SRAM_BOOTLOAD_BYPASS(x) ((x) << S_PHY1_SRAM_BOOTLOAD_BYPASS)
11332 #define F_PHY1_SRAM_BOOTLOAD_BYPASS    V_PHY1_SRAM_BOOTLOAD_BYPASS(1U)
11333 
11334 #define S_PHY1_SRAM_BYPASS    10
11335 #define V_PHY1_SRAM_BYPASS(x) ((x) << S_PHY1_SRAM_BYPASS)
11336 #define F_PHY1_SRAM_BYPASS    V_PHY1_SRAM_BYPASS(1U)
11337 
11338 #define S_PHY1_SRAM_ECC_EN    9
11339 #define V_PHY1_SRAM_ECC_EN(x) ((x) << S_PHY1_SRAM_ECC_EN)
11340 #define F_PHY1_SRAM_ECC_EN    V_PHY1_SRAM_ECC_EN(1U)
11341 
11342 #define S_PHY1_SRAM_EXT_LD_DONE    8
11343 #define V_PHY1_SRAM_EXT_LD_DONE(x) ((x) << S_PHY1_SRAM_EXT_LD_DONE)
11344 #define F_PHY1_SRAM_EXT_LD_DONE    V_PHY1_SRAM_EXT_LD_DONE(1U)
11345 
11346 #define S_PHY_CR_PARA_SEL    4
11347 #define M_PHY_CR_PARA_SEL    0xfU
11348 #define V_PHY_CR_PARA_SEL(x) ((x) << S_PHY_CR_PARA_SEL)
11349 #define G_PHY_CR_PARA_SEL(x) (((x) >> S_PHY_CR_PARA_SEL) & M_PHY_CR_PARA_SEL)
11350 
11351 #define S_PHY0_SRAM_BOOTLOAD_BYPASS    3
11352 #define V_PHY0_SRAM_BOOTLOAD_BYPASS(x) ((x) << S_PHY0_SRAM_BOOTLOAD_BYPASS)
11353 #define F_PHY0_SRAM_BOOTLOAD_BYPASS    V_PHY0_SRAM_BOOTLOAD_BYPASS(1U)
11354 
11355 #define S_PHY0_SRAM_BYPASS    2
11356 #define V_PHY0_SRAM_BYPASS(x) ((x) << S_PHY0_SRAM_BYPASS)
11357 #define F_PHY0_SRAM_BYPASS    V_PHY0_SRAM_BYPASS(1U)
11358 
11359 #define S_PHY0_SRAM_ECC_EN    1
11360 #define V_PHY0_SRAM_ECC_EN(x) ((x) << S_PHY0_SRAM_ECC_EN)
11361 #define F_PHY0_SRAM_ECC_EN    V_PHY0_SRAM_ECC_EN(1U)
11362 
11363 #define S_PHY0_SRAM_EXT_LD_DONE    0
11364 #define V_PHY0_SRAM_EXT_LD_DONE(x) ((x) << S_PHY0_SRAM_EXT_LD_DONE)
11365 #define F_PHY0_SRAM_EXT_LD_DONE    V_PHY0_SRAM_EXT_LD_DONE(1U)
11366 
11367 #define A_PCIE_SNPS_G5_PHY_SRAM_STS 0x5f88
11368 
11369 #define S_PHY3_SRAM_INIT_DONE    3
11370 #define V_PHY3_SRAM_INIT_DONE(x) ((x) << S_PHY3_SRAM_INIT_DONE)
11371 #define F_PHY3_SRAM_INIT_DONE    V_PHY3_SRAM_INIT_DONE(1U)
11372 
11373 #define S_PHY2_SRAM_INIT_DONE    2
11374 #define V_PHY2_SRAM_INIT_DONE(x) ((x) << S_PHY2_SRAM_INIT_DONE)
11375 #define F_PHY2_SRAM_INIT_DONE    V_PHY2_SRAM_INIT_DONE(1U)
11376 
11377 #define S_PHY1_SRAM_INIT_DONE    1
11378 #define V_PHY1_SRAM_INIT_DONE(x) ((x) << S_PHY1_SRAM_INIT_DONE)
11379 #define F_PHY1_SRAM_INIT_DONE    V_PHY1_SRAM_INIT_DONE(1U)
11380 
11381 #define S_PHY0_SRAM_INIT_DONE    0
11382 #define V_PHY0_SRAM_INIT_DONE(x) ((x) << S_PHY0_SRAM_INIT_DONE)
11383 #define F_PHY0_SRAM_INIT_DONE    V_PHY0_SRAM_INIT_DONE(1U)
11384 
11385 #define A_PCIE_SNPS_G5_PHY_CTRL_PHY_0_TO_3 0x5f90
11386 #define A_PCIE_SNPS_G5_PHY_CTRL_PHY_0_DATA 0x5f94
11387 #define A_PCIE_SNPS_G5_PHY_CTRL_PHY_1_DATA 0x5f98
11388 #define A_PCIE_SNPS_G5_PHY_CTRL_PHY_2_DATA 0x5f9c
11389 #define A_PCIE_SNPS_G5_PHY_CTRL_PHY_3_DATA 0x5fa0
11390 #define A_PCIE_SNPS_G5_PHY_DEFAULTS 0x5fa4
11391 #define A_PCIE_SNPS_G5_PHY_0_VALUES 0x5fa8
11392 
11393 #define S_RX_TERM_OFFSET    28
11394 #define V_RX_TERM_OFFSET(x) ((x) << S_RX_TERM_OFFSET)
11395 #define F_RX_TERM_OFFSET    V_RX_TERM_OFFSET(1U)
11396 
11397 #define S_REFB_RAW_CLK_DIV2_EN    27
11398 #define V_REFB_RAW_CLK_DIV2_EN(x) ((x) << S_REFB_RAW_CLK_DIV2_EN)
11399 #define F_REFB_RAW_CLK_DIV2_EN    V_REFB_RAW_CLK_DIV2_EN(1U)
11400 
11401 #define S_REFB_RANGE    23
11402 #define M_REFB_RANGE    0xfU
11403 #define V_REFB_RANGE(x) ((x) << S_REFB_RANGE)
11404 #define G_REFB_RANGE(x) (((x) >> S_REFB_RANGE) & M_REFB_RANGE)
11405 
11406 #define S_REFB_LANE_CLK_EN    22
11407 #define V_REFB_LANE_CLK_EN(x) ((x) << S_REFB_LANE_CLK_EN)
11408 #define F_REFB_LANE_CLK_EN    V_REFB_LANE_CLK_EN(1U)
11409 
11410 #define S_REFB_CLK_DIV2_EN    21
11411 #define V_REFB_CLK_DIV2_EN(x) ((x) << S_REFB_CLK_DIV2_EN)
11412 #define F_REFB_CLK_DIV2_EN    V_REFB_CLK_DIV2_EN(1U)
11413 
11414 #define S_REFA_RAW_CLK_DIV2_EN    20
11415 #define V_REFA_RAW_CLK_DIV2_EN(x) ((x) << S_REFA_RAW_CLK_DIV2_EN)
11416 #define F_REFA_RAW_CLK_DIV2_EN    V_REFA_RAW_CLK_DIV2_EN(1U)
11417 
11418 #define S_REFA_RANGE    16
11419 #define M_REFA_RANGE    0xfU
11420 #define V_REFA_RANGE(x) ((x) << S_REFA_RANGE)
11421 #define G_REFA_RANGE(x) (((x) >> S_REFA_RANGE) & M_REFA_RANGE)
11422 
11423 #define S_REFA_LANE_CLK_EN    15
11424 #define V_REFA_LANE_CLK_EN(x) ((x) << S_REFA_LANE_CLK_EN)
11425 #define F_REFA_LANE_CLK_EN    V_REFA_LANE_CLK_EN(1U)
11426 
11427 #define S_REFA_CLK_DIV2_EN    14
11428 #define V_REFA_CLK_DIV2_EN(x) ((x) << S_REFA_CLK_DIV2_EN)
11429 #define F_REFA_CLK_DIV2_EN    V_REFA_CLK_DIV2_EN(1U)
11430 
11431 #define S_NOMINAL_VPH_SEL    10
11432 #define M_NOMINAL_VPH_SEL    0x3U
11433 #define V_NOMINAL_VPH_SEL(x) ((x) << S_NOMINAL_VPH_SEL)
11434 #define G_NOMINAL_VPH_SEL(x) (((x) >> S_NOMINAL_VPH_SEL) & M_NOMINAL_VPH_SEL)
11435 
11436 #define S_NOMINAL_VP_SEL    8
11437 #define M_NOMINAL_VP_SEL    0x3U
11438 #define V_NOMINAL_VP_SEL(x) ((x) << S_NOMINAL_VP_SEL)
11439 #define G_NOMINAL_VP_SEL(x) (((x) >> S_NOMINAL_VP_SEL) & M_NOMINAL_VP_SEL)
11440 
11441 #define S_MPLLB_WORD_CLK_EN    7
11442 #define V_MPLLB_WORD_CLK_EN(x) ((x) << S_MPLLB_WORD_CLK_EN)
11443 #define F_MPLLB_WORD_CLK_EN    V_MPLLB_WORD_CLK_EN(1U)
11444 
11445 #define S_MPLLB_SSC_EN    6
11446 #define V_MPLLB_SSC_EN(x) ((x) << S_MPLLB_SSC_EN)
11447 #define F_MPLLB_SSC_EN    V_MPLLB_SSC_EN(1U)
11448 
11449 #define S_MPLLB_SHORT_LOCK_EN    5
11450 #define V_MPLLB_SHORT_LOCK_EN(x) ((x) << S_MPLLB_SHORT_LOCK_EN)
11451 #define F_MPLLB_SHORT_LOCK_EN    V_MPLLB_SHORT_LOCK_EN(1U)
11452 
11453 #define S_MPLLB_FORCE_EN    4
11454 #define V_MPLLB_FORCE_EN(x) ((x) << S_MPLLB_FORCE_EN)
11455 #define F_MPLLB_FORCE_EN    V_MPLLB_FORCE_EN(1U)
11456 
11457 #define S_MPLLA_WORD_CLK_EN    3
11458 #define V_MPLLA_WORD_CLK_EN(x) ((x) << S_MPLLA_WORD_CLK_EN)
11459 #define F_MPLLA_WORD_CLK_EN    V_MPLLA_WORD_CLK_EN(1U)
11460 
11461 #define S_MPLLA_SSC_EN    2
11462 #define V_MPLLA_SSC_EN(x) ((x) << S_MPLLA_SSC_EN)
11463 #define F_MPLLA_SSC_EN    V_MPLLA_SSC_EN(1U)
11464 
11465 #define S_MPLLA_SHORT_LOCK_EN    1
11466 #define V_MPLLA_SHORT_LOCK_EN(x) ((x) << S_MPLLA_SHORT_LOCK_EN)
11467 #define F_MPLLA_SHORT_LOCK_EN    V_MPLLA_SHORT_LOCK_EN(1U)
11468 
11469 #define S_MPLLA_FORCE_EN    0
11470 #define V_MPLLA_FORCE_EN(x) ((x) << S_MPLLA_FORCE_EN)
11471 #define F_MPLLA_FORCE_EN    V_MPLLA_FORCE_EN(1U)
11472 
11473 #define A_PCIE_SNPS_G5_PHY_1_VALUES 0x5fac
11474 
11475 #define S_REF_ALT1_CLK_M    13
11476 #define V_REF_ALT1_CLK_M(x) ((x) << S_REF_ALT1_CLK_M)
11477 #define F_REF_ALT1_CLK_M    V_REF_ALT1_CLK_M(1U)
11478 
11479 #define S_REF_ALT1_CLK_P    12
11480 #define V_REF_ALT1_CLK_P(x) ((x) << S_REF_ALT1_CLK_P)
11481 #define F_REF_ALT1_CLK_P    V_REF_ALT1_CLK_P(1U)
11482 
11483 #define A_PCIE_SNPS_G5_PHY_2_VALUES 0x5fb0
11484 #define A_PCIE_SNPS_G5_PHY_3_VALUES 0x5fb4
11485 #define A_PCIE_SNPS_G5_PHY_0_RX_LANEPLL_BYPASS_MODE 0x5fb8
11486 
11487 #define S_T7_LANE3    15
11488 #define M_T7_LANE3    0x1fU
11489 #define V_T7_LANE3(x) ((x) << S_T7_LANE3)
11490 #define G_T7_LANE3(x) (((x) >> S_T7_LANE3) & M_T7_LANE3)
11491 
11492 #define S_T7_LANE2    10
11493 #define M_T7_LANE2    0x1fU
11494 #define V_T7_LANE2(x) ((x) << S_T7_LANE2)
11495 #define G_T7_LANE2(x) (((x) >> S_T7_LANE2) & M_T7_LANE2)
11496 
11497 #define S_T7_LANE1    5
11498 #define M_T7_LANE1    0x1fU
11499 #define V_T7_LANE1(x) ((x) << S_T7_LANE1)
11500 #define G_T7_LANE1(x) (((x) >> S_T7_LANE1) & M_T7_LANE1)
11501 
11502 #define S_T7_LANE0    0
11503 #define M_T7_LANE0    0x1fU
11504 #define V_T7_LANE0(x) ((x) << S_T7_LANE0)
11505 #define G_T7_LANE0(x) (((x) >> S_T7_LANE0) & M_T7_LANE0)
11506 
11507 #define A_PCIE_SNPS_G5_PHY_1_RX_LANEPLL_BYPASS_MODE 0x5fbc
11508 #define A_PCIE_SNPS_G5_PHY_2_RX_LANEPLL_BYPASS_MODE 0x5fc0
11509 #define A_PCIE_SNPS_G5_PHY_3_RX_LANEPLL_BYPASS_MODE 0x5fc4
11510 #define A_PCIE_SNPS_G5_PHY_0_1_RX_LANEPLL_SRC_SEL 0x5fc8
11511 
11512 #define S_LANE7_LANEPLL_SRC_SEL    28
11513 #define M_LANE7_LANEPLL_SRC_SEL    0xfU
11514 #define V_LANE7_LANEPLL_SRC_SEL(x) ((x) << S_LANE7_LANEPLL_SRC_SEL)
11515 #define G_LANE7_LANEPLL_SRC_SEL(x) (((x) >> S_LANE7_LANEPLL_SRC_SEL) & M_LANE7_LANEPLL_SRC_SEL)
11516 
11517 #define S_LANE6_LANEPLL_SRC_SEL    24
11518 #define M_LANE6_LANEPLL_SRC_SEL    0xfU
11519 #define V_LANE6_LANEPLL_SRC_SEL(x) ((x) << S_LANE6_LANEPLL_SRC_SEL)
11520 #define G_LANE6_LANEPLL_SRC_SEL(x) (((x) >> S_LANE6_LANEPLL_SRC_SEL) & M_LANE6_LANEPLL_SRC_SEL)
11521 
11522 #define S_LANE5_LANEPLL_SRC_SEL    20
11523 #define M_LANE5_LANEPLL_SRC_SEL    0xfU
11524 #define V_LANE5_LANEPLL_SRC_SEL(x) ((x) << S_LANE5_LANEPLL_SRC_SEL)
11525 #define G_LANE5_LANEPLL_SRC_SEL(x) (((x) >> S_LANE5_LANEPLL_SRC_SEL) & M_LANE5_LANEPLL_SRC_SEL)
11526 
11527 #define S_LANE4_LANEPLL_SRC_SEL    16
11528 #define M_LANE4_LANEPLL_SRC_SEL    0xfU
11529 #define V_LANE4_LANEPLL_SRC_SEL(x) ((x) << S_LANE4_LANEPLL_SRC_SEL)
11530 #define G_LANE4_LANEPLL_SRC_SEL(x) (((x) >> S_LANE4_LANEPLL_SRC_SEL) & M_LANE4_LANEPLL_SRC_SEL)
11531 
11532 #define S_LANE3_LANEPLL_SRC_SEL    12
11533 #define M_LANE3_LANEPLL_SRC_SEL    0xfU
11534 #define V_LANE3_LANEPLL_SRC_SEL(x) ((x) << S_LANE3_LANEPLL_SRC_SEL)
11535 #define G_LANE3_LANEPLL_SRC_SEL(x) (((x) >> S_LANE3_LANEPLL_SRC_SEL) & M_LANE3_LANEPLL_SRC_SEL)
11536 
11537 #define S_LANE2_LANEPLL_SRC_SEL    8
11538 #define M_LANE2_LANEPLL_SRC_SEL    0xfU
11539 #define V_LANE2_LANEPLL_SRC_SEL(x) ((x) << S_LANE2_LANEPLL_SRC_SEL)
11540 #define G_LANE2_LANEPLL_SRC_SEL(x) (((x) >> S_LANE2_LANEPLL_SRC_SEL) & M_LANE2_LANEPLL_SRC_SEL)
11541 
11542 #define S_LANE1_LANEPLL_SRC_SEL    4
11543 #define M_LANE1_LANEPLL_SRC_SEL    0xfU
11544 #define V_LANE1_LANEPLL_SRC_SEL(x) ((x) << S_LANE1_LANEPLL_SRC_SEL)
11545 #define G_LANE1_LANEPLL_SRC_SEL(x) (((x) >> S_LANE1_LANEPLL_SRC_SEL) & M_LANE1_LANEPLL_SRC_SEL)
11546 
11547 #define S_LANE0_LANEPLL_SRC_SEL    0
11548 #define M_LANE0_LANEPLL_SRC_SEL    0xfU
11549 #define V_LANE0_LANEPLL_SRC_SEL(x) ((x) << S_LANE0_LANEPLL_SRC_SEL)
11550 #define G_LANE0_LANEPLL_SRC_SEL(x) (((x) >> S_LANE0_LANEPLL_SRC_SEL) & M_LANE0_LANEPLL_SRC_SEL)
11551 
11552 #define A_PCIE_SNPS_G5_PHY_2_3_RX_LANEPLL_SRC_SEL 0x5fcc
11553 #define A_PCIE_SNPS_G5_PHY_RX_DECERR 0x5fd0
11554 
11555 #define S_LANE15_REC_OVRD_8B10B_DECERR    30
11556 #define M_LANE15_REC_OVRD_8B10B_DECERR    0x3U
11557 #define V_LANE15_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE15_REC_OVRD_8B10B_DECERR)
11558 #define G_LANE15_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE15_REC_OVRD_8B10B_DECERR) & M_LANE15_REC_OVRD_8B10B_DECERR)
11559 
11560 #define S_LANE14_REC_OVRD_8B10B_DECERR    28
11561 #define M_LANE14_REC_OVRD_8B10B_DECERR    0x3U
11562 #define V_LANE14_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE14_REC_OVRD_8B10B_DECERR)
11563 #define G_LANE14_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE14_REC_OVRD_8B10B_DECERR) & M_LANE14_REC_OVRD_8B10B_DECERR)
11564 
11565 #define S_LANE13_REC_OVRD_8B10B_DECERR    26
11566 #define M_LANE13_REC_OVRD_8B10B_DECERR    0x3U
11567 #define V_LANE13_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE13_REC_OVRD_8B10B_DECERR)
11568 #define G_LANE13_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE13_REC_OVRD_8B10B_DECERR) & M_LANE13_REC_OVRD_8B10B_DECERR)
11569 
11570 #define S_LANE12_REC_OVRD_8B10B_DECERR    24
11571 #define M_LANE12_REC_OVRD_8B10B_DECERR    0x3U
11572 #define V_LANE12_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE12_REC_OVRD_8B10B_DECERR)
11573 #define G_LANE12_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE12_REC_OVRD_8B10B_DECERR) & M_LANE12_REC_OVRD_8B10B_DECERR)
11574 
11575 #define S_LANE11_REC_OVRD_8B10B_DECERR    22
11576 #define M_LANE11_REC_OVRD_8B10B_DECERR    0x3U
11577 #define V_LANE11_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE11_REC_OVRD_8B10B_DECERR)
11578 #define G_LANE11_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE11_REC_OVRD_8B10B_DECERR) & M_LANE11_REC_OVRD_8B10B_DECERR)
11579 
11580 #define S_LANE10_REC_OVRD_8B10B_DECERR    20
11581 #define M_LANE10_REC_OVRD_8B10B_DECERR    0x3U
11582 #define V_LANE10_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE10_REC_OVRD_8B10B_DECERR)
11583 #define G_LANE10_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE10_REC_OVRD_8B10B_DECERR) & M_LANE10_REC_OVRD_8B10B_DECERR)
11584 
11585 #define S_LANE9_REC_OVRD_8B10B_DECERR    18
11586 #define M_LANE9_REC_OVRD_8B10B_DECERR    0x3U
11587 #define V_LANE9_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE9_REC_OVRD_8B10B_DECERR)
11588 #define G_LANE9_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE9_REC_OVRD_8B10B_DECERR) & M_LANE9_REC_OVRD_8B10B_DECERR)
11589 
11590 #define S_LANE8_REC_OVRD_8B10B_DECERR    16
11591 #define M_LANE8_REC_OVRD_8B10B_DECERR    0x3U
11592 #define V_LANE8_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE8_REC_OVRD_8B10B_DECERR)
11593 #define G_LANE8_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE8_REC_OVRD_8B10B_DECERR) & M_LANE8_REC_OVRD_8B10B_DECERR)
11594 
11595 #define S_LANE7_REC_OVRD_8B10B_DECERR    14
11596 #define M_LANE7_REC_OVRD_8B10B_DECERR    0x3U
11597 #define V_LANE7_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE7_REC_OVRD_8B10B_DECERR)
11598 #define G_LANE7_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE7_REC_OVRD_8B10B_DECERR) & M_LANE7_REC_OVRD_8B10B_DECERR)
11599 
11600 #define S_LANE6_REC_OVRD_8B10B_DECERR    12
11601 #define M_LANE6_REC_OVRD_8B10B_DECERR    0x3U
11602 #define V_LANE6_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE6_REC_OVRD_8B10B_DECERR)
11603 #define G_LANE6_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE6_REC_OVRD_8B10B_DECERR) & M_LANE6_REC_OVRD_8B10B_DECERR)
11604 
11605 #define S_LANE5_REC_OVRD_8B10B_DECERR    10
11606 #define M_LANE5_REC_OVRD_8B10B_DECERR    0x3U
11607 #define V_LANE5_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE5_REC_OVRD_8B10B_DECERR)
11608 #define G_LANE5_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE5_REC_OVRD_8B10B_DECERR) & M_LANE5_REC_OVRD_8B10B_DECERR)
11609 
11610 #define S_LANE4_REC_OVRD_8B10B_DECERR    8
11611 #define M_LANE4_REC_OVRD_8B10B_DECERR    0x3U
11612 #define V_LANE4_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE4_REC_OVRD_8B10B_DECERR)
11613 #define G_LANE4_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE4_REC_OVRD_8B10B_DECERR) & M_LANE4_REC_OVRD_8B10B_DECERR)
11614 
11615 #define S_LANE3_REC_OVRD_8B10B_DECERR    6
11616 #define M_LANE3_REC_OVRD_8B10B_DECERR    0x3U
11617 #define V_LANE3_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE3_REC_OVRD_8B10B_DECERR)
11618 #define G_LANE3_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE3_REC_OVRD_8B10B_DECERR) & M_LANE3_REC_OVRD_8B10B_DECERR)
11619 
11620 #define S_LANE2_REC_OVRD_8B10B_DECERR    4
11621 #define M_LANE2_REC_OVRD_8B10B_DECERR    0x3U
11622 #define V_LANE2_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE2_REC_OVRD_8B10B_DECERR)
11623 #define G_LANE2_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE2_REC_OVRD_8B10B_DECERR) & M_LANE2_REC_OVRD_8B10B_DECERR)
11624 
11625 #define S_LANE1_REC_OVRD_8B10B_DECERR    2
11626 #define M_LANE1_REC_OVRD_8B10B_DECERR    0x3U
11627 #define V_LANE1_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE1_REC_OVRD_8B10B_DECERR)
11628 #define G_LANE1_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE1_REC_OVRD_8B10B_DECERR) & M_LANE1_REC_OVRD_8B10B_DECERR)
11629 
11630 #define S_LANE0_REC_OVRD_8B10B_DECERR    0
11631 #define M_LANE0_REC_OVRD_8B10B_DECERR    0x3U
11632 #define V_LANE0_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE0_REC_OVRD_8B10B_DECERR)
11633 #define G_LANE0_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE0_REC_OVRD_8B10B_DECERR) & M_LANE0_REC_OVRD_8B10B_DECERR)
11634 
11635 #define A_PCIE_SNPS_G5_PHY_TX2RX_LOOPBK_REC_OVRD_EN 0x5fd4
11636 
11637 #define S_LANE15_REC_OVRD_EN    31
11638 #define V_LANE15_REC_OVRD_EN(x) ((x) << S_LANE15_REC_OVRD_EN)
11639 #define F_LANE15_REC_OVRD_EN    V_LANE15_REC_OVRD_EN(1U)
11640 
11641 #define S_LANE14_REC_OVRD_EN    30
11642 #define V_LANE14_REC_OVRD_EN(x) ((x) << S_LANE14_REC_OVRD_EN)
11643 #define F_LANE14_REC_OVRD_EN    V_LANE14_REC_OVRD_EN(1U)
11644 
11645 #define S_LANE13_REC_OVRD_EN    29
11646 #define V_LANE13_REC_OVRD_EN(x) ((x) << S_LANE13_REC_OVRD_EN)
11647 #define F_LANE13_REC_OVRD_EN    V_LANE13_REC_OVRD_EN(1U)
11648 
11649 #define S_LANE11_REC_OVRD_EN    27
11650 #define V_LANE11_REC_OVRD_EN(x) ((x) << S_LANE11_REC_OVRD_EN)
11651 #define F_LANE11_REC_OVRD_EN    V_LANE11_REC_OVRD_EN(1U)
11652 
11653 #define S_LANE12_REC_OVRD_EN    28
11654 #define V_LANE12_REC_OVRD_EN(x) ((x) << S_LANE12_REC_OVRD_EN)
11655 #define F_LANE12_REC_OVRD_EN    V_LANE12_REC_OVRD_EN(1U)
11656 
11657 #define S_LANE10_REC_OVRD_EN    26
11658 #define V_LANE10_REC_OVRD_EN(x) ((x) << S_LANE10_REC_OVRD_EN)
11659 #define F_LANE10_REC_OVRD_EN    V_LANE10_REC_OVRD_EN(1U)
11660 
11661 #define S_LANE9_REC_OVRD_EN    25
11662 #define V_LANE9_REC_OVRD_EN(x) ((x) << S_LANE9_REC_OVRD_EN)
11663 #define F_LANE9_REC_OVRD_EN    V_LANE9_REC_OVRD_EN(1U)
11664 
11665 #define S_LANE8_REC_OVRD_EN    24
11666 #define V_LANE8_REC_OVRD_EN(x) ((x) << S_LANE8_REC_OVRD_EN)
11667 #define F_LANE8_REC_OVRD_EN    V_LANE8_REC_OVRD_EN(1U)
11668 
11669 #define S_LANE7_REC_OVRD_EN    23
11670 #define V_LANE7_REC_OVRD_EN(x) ((x) << S_LANE7_REC_OVRD_EN)
11671 #define F_LANE7_REC_OVRD_EN    V_LANE7_REC_OVRD_EN(1U)
11672 
11673 #define S_LANE6_REC_OVRD_EN    22
11674 #define V_LANE6_REC_OVRD_EN(x) ((x) << S_LANE6_REC_OVRD_EN)
11675 #define F_LANE6_REC_OVRD_EN    V_LANE6_REC_OVRD_EN(1U)
11676 
11677 #define S_LANE5_REC_OVRD_EN    21
11678 #define V_LANE5_REC_OVRD_EN(x) ((x) << S_LANE5_REC_OVRD_EN)
11679 #define F_LANE5_REC_OVRD_EN    V_LANE5_REC_OVRD_EN(1U)
11680 
11681 #define S_LANE4_REC_OVRD_EN    20
11682 #define V_LANE4_REC_OVRD_EN(x) ((x) << S_LANE4_REC_OVRD_EN)
11683 #define F_LANE4_REC_OVRD_EN    V_LANE4_REC_OVRD_EN(1U)
11684 
11685 #define S_LANE3_REC_OVRD_EN    19
11686 #define V_LANE3_REC_OVRD_EN(x) ((x) << S_LANE3_REC_OVRD_EN)
11687 #define F_LANE3_REC_OVRD_EN    V_LANE3_REC_OVRD_EN(1U)
11688 
11689 #define S_LANE2_REC_OVRD_EN    18
11690 #define V_LANE2_REC_OVRD_EN(x) ((x) << S_LANE2_REC_OVRD_EN)
11691 #define F_LANE2_REC_OVRD_EN    V_LANE2_REC_OVRD_EN(1U)
11692 
11693 #define S_LANE1_REC_OVRD_EN    17
11694 #define V_LANE1_REC_OVRD_EN(x) ((x) << S_LANE1_REC_OVRD_EN)
11695 #define F_LANE1_REC_OVRD_EN    V_LANE1_REC_OVRD_EN(1U)
11696 
11697 #define S_LANE0_REC_OVRD_EN    16
11698 #define V_LANE0_REC_OVRD_EN(x) ((x) << S_LANE0_REC_OVRD_EN)
11699 #define F_LANE0_REC_OVRD_EN    V_LANE0_REC_OVRD_EN(1U)
11700 
11701 #define S_LANE15_TX2RX_LOOPBK    15
11702 #define V_LANE15_TX2RX_LOOPBK(x) ((x) << S_LANE15_TX2RX_LOOPBK)
11703 #define F_LANE15_TX2RX_LOOPBK    V_LANE15_TX2RX_LOOPBK(1U)
11704 
11705 #define S_LANE14_TX2RX_LOOPBK    14
11706 #define V_LANE14_TX2RX_LOOPBK(x) ((x) << S_LANE14_TX2RX_LOOPBK)
11707 #define F_LANE14_TX2RX_LOOPBK    V_LANE14_TX2RX_LOOPBK(1U)
11708 
11709 #define S_LANE13_TX2RX_LOOPBK    13
11710 #define V_LANE13_TX2RX_LOOPBK(x) ((x) << S_LANE13_TX2RX_LOOPBK)
11711 #define F_LANE13_TX2RX_LOOPBK    V_LANE13_TX2RX_LOOPBK(1U)
11712 
11713 #define S_LANE12_TX2RX_LOOPBK    12
11714 #define V_LANE12_TX2RX_LOOPBK(x) ((x) << S_LANE12_TX2RX_LOOPBK)
11715 #define F_LANE12_TX2RX_LOOPBK    V_LANE12_TX2RX_LOOPBK(1U)
11716 
11717 #define S_LANE11_TX2RX_LOOPBK    11
11718 #define V_LANE11_TX2RX_LOOPBK(x) ((x) << S_LANE11_TX2RX_LOOPBK)
11719 #define F_LANE11_TX2RX_LOOPBK    V_LANE11_TX2RX_LOOPBK(1U)
11720 
11721 #define S_LANE10_TX2RX_LOOPBK    10
11722 #define V_LANE10_TX2RX_LOOPBK(x) ((x) << S_LANE10_TX2RX_LOOPBK)
11723 #define F_LANE10_TX2RX_LOOPBK    V_LANE10_TX2RX_LOOPBK(1U)
11724 
11725 #define S_LANE9_TX2RX_LOOPBK    9
11726 #define V_LANE9_TX2RX_LOOPBK(x) ((x) << S_LANE9_TX2RX_LOOPBK)
11727 #define F_LANE9_TX2RX_LOOPBK    V_LANE9_TX2RX_LOOPBK(1U)
11728 
11729 #define S_LANE8_TX2RX_LOOPBK    8
11730 #define V_LANE8_TX2RX_LOOPBK(x) ((x) << S_LANE8_TX2RX_LOOPBK)
11731 #define F_LANE8_TX2RX_LOOPBK    V_LANE8_TX2RX_LOOPBK(1U)
11732 
11733 #define S_LANE7_TX2RX_LOOPBK    7
11734 #define V_LANE7_TX2RX_LOOPBK(x) ((x) << S_LANE7_TX2RX_LOOPBK)
11735 #define F_LANE7_TX2RX_LOOPBK    V_LANE7_TX2RX_LOOPBK(1U)
11736 
11737 #define S_LANE6_TX2RX_LOOPBK    6
11738 #define V_LANE6_TX2RX_LOOPBK(x) ((x) << S_LANE6_TX2RX_LOOPBK)
11739 #define F_LANE6_TX2RX_LOOPBK    V_LANE6_TX2RX_LOOPBK(1U)
11740 
11741 #define S_LANE5_TX2RX_LOOPBK    5
11742 #define V_LANE5_TX2RX_LOOPBK(x) ((x) << S_LANE5_TX2RX_LOOPBK)
11743 #define F_LANE5_TX2RX_LOOPBK    V_LANE5_TX2RX_LOOPBK(1U)
11744 
11745 #define S_LANE4_TX2RX_LOOPBK    4
11746 #define V_LANE4_TX2RX_LOOPBK(x) ((x) << S_LANE4_TX2RX_LOOPBK)
11747 #define F_LANE4_TX2RX_LOOPBK    V_LANE4_TX2RX_LOOPBK(1U)
11748 
11749 #define S_LANE3_TX2RX_LOOPBK    3
11750 #define V_LANE3_TX2RX_LOOPBK(x) ((x) << S_LANE3_TX2RX_LOOPBK)
11751 #define F_LANE3_TX2RX_LOOPBK    V_LANE3_TX2RX_LOOPBK(1U)
11752 
11753 #define S_LANE2_TX2RX_LOOPBK    2
11754 #define V_LANE2_TX2RX_LOOPBK(x) ((x) << S_LANE2_TX2RX_LOOPBK)
11755 #define F_LANE2_TX2RX_LOOPBK    V_LANE2_TX2RX_LOOPBK(1U)
11756 
11757 #define S_LANE1_TX2RX_LOOPBK    1
11758 #define V_LANE1_TX2RX_LOOPBK(x) ((x) << S_LANE1_TX2RX_LOOPBK)
11759 #define F_LANE1_TX2RX_LOOPBK    V_LANE1_TX2RX_LOOPBK(1U)
11760 
11761 #define S_LANE0_TX2RX_LOOPBK    0
11762 #define V_LANE0_TX2RX_LOOPBK(x) ((x) << S_LANE0_TX2RX_LOOPBK)
11763 #define F_LANE0_TX2RX_LOOPBK    V_LANE0_TX2RX_LOOPBK(1U)
11764 
11765 #define A_PCIE_PHY_TX_DISABLE_UPCS_PIPE_CONFIG 0x5fd8
11766 
11767 #define S_UPCS_PIPE_CONFIG    16
11768 #define M_UPCS_PIPE_CONFIG    0xffffU
11769 #define V_UPCS_PIPE_CONFIG(x) ((x) << S_UPCS_PIPE_CONFIG)
11770 #define G_UPCS_PIPE_CONFIG(x) (((x) >> S_UPCS_PIPE_CONFIG) & M_UPCS_PIPE_CONFIG)
11771 
11772 #define S_TX15_DISABLE    15
11773 #define V_TX15_DISABLE(x) ((x) << S_TX15_DISABLE)
11774 #define F_TX15_DISABLE    V_TX15_DISABLE(1U)
11775 
11776 #define S_TX14_DISABLE    14
11777 #define V_TX14_DISABLE(x) ((x) << S_TX14_DISABLE)
11778 #define F_TX14_DISABLE    V_TX14_DISABLE(1U)
11779 
11780 #define S_TX13_DISABLE    13
11781 #define V_TX13_DISABLE(x) ((x) << S_TX13_DISABLE)
11782 #define F_TX13_DISABLE    V_TX13_DISABLE(1U)
11783 
11784 #define S_TX12_DISABLE    12
11785 #define V_TX12_DISABLE(x) ((x) << S_TX12_DISABLE)
11786 #define F_TX12_DISABLE    V_TX12_DISABLE(1U)
11787 
11788 #define S_TX11_DISABLE    11
11789 #define V_TX11_DISABLE(x) ((x) << S_TX11_DISABLE)
11790 #define F_TX11_DISABLE    V_TX11_DISABLE(1U)
11791 
11792 #define S_TX10_DISABLE    10
11793 #define V_TX10_DISABLE(x) ((x) << S_TX10_DISABLE)
11794 #define F_TX10_DISABLE    V_TX10_DISABLE(1U)
11795 
11796 #define S_TX9_DISABLE    9
11797 #define V_TX9_DISABLE(x) ((x) << S_TX9_DISABLE)
11798 #define F_TX9_DISABLE    V_TX9_DISABLE(1U)
11799 
11800 #define S_TX8_DISABLE    8
11801 #define V_TX8_DISABLE(x) ((x) << S_TX8_DISABLE)
11802 #define F_TX8_DISABLE    V_TX8_DISABLE(1U)
11803 
11804 #define S_TX7_DISABLE    7
11805 #define V_TX7_DISABLE(x) ((x) << S_TX7_DISABLE)
11806 #define F_TX7_DISABLE    V_TX7_DISABLE(1U)
11807 
11808 #define S_TX6_DISABLE    6
11809 #define V_TX6_DISABLE(x) ((x) << S_TX6_DISABLE)
11810 #define F_TX6_DISABLE    V_TX6_DISABLE(1U)
11811 
11812 #define S_TX5_DISABLE    5
11813 #define V_TX5_DISABLE(x) ((x) << S_TX5_DISABLE)
11814 #define F_TX5_DISABLE    V_TX5_DISABLE(1U)
11815 
11816 #define S_TX4_DISABLE    4
11817 #define V_TX4_DISABLE(x) ((x) << S_TX4_DISABLE)
11818 #define F_TX4_DISABLE    V_TX4_DISABLE(1U)
11819 
11820 #define S_TX3_DISABLE    3
11821 #define V_TX3_DISABLE(x) ((x) << S_TX3_DISABLE)
11822 #define F_TX3_DISABLE    V_TX3_DISABLE(1U)
11823 
11824 #define S_TX2_DISABLE    2
11825 #define V_TX2_DISABLE(x) ((x) << S_TX2_DISABLE)
11826 #define F_TX2_DISABLE    V_TX2_DISABLE(1U)
11827 
11828 #define S_TX1_DISABLE    1
11829 #define V_TX1_DISABLE(x) ((x) << S_TX1_DISABLE)
11830 #define F_TX1_DISABLE    V_TX1_DISABLE(1U)
11831 
11832 #define S_TX0_DISABLE    0
11833 #define V_TX0_DISABLE(x) ((x) << S_TX0_DISABLE)
11834 #define F_TX0_DISABLE    V_TX0_DISABLE(1U)
11835 
11836 #define A_PCIE_PDEBUG_REG_0X0 0x0
11837 #define A_PCIE_PDEBUG_REG_0X1 0x1
11838 #define A_PCIE_PDEBUG_REG_0X2 0x2
11839 
11840 #define S_TAGQ_CH0_TAGS_USED    11
11841 #define M_TAGQ_CH0_TAGS_USED    0xffU
11842 #define V_TAGQ_CH0_TAGS_USED(x) ((x) << S_TAGQ_CH0_TAGS_USED)
11843 #define G_TAGQ_CH0_TAGS_USED(x) (((x) >> S_TAGQ_CH0_TAGS_USED) & M_TAGQ_CH0_TAGS_USED)
11844 
11845 #define S_REQ_CH0_DATA_EMPTY    10
11846 #define V_REQ_CH0_DATA_EMPTY(x) ((x) << S_REQ_CH0_DATA_EMPTY)
11847 #define F_REQ_CH0_DATA_EMPTY    V_REQ_CH0_DATA_EMPTY(1U)
11848 
11849 #define S_RDQ_CH0_REQ_EMPTY    9
11850 #define V_RDQ_CH0_REQ_EMPTY(x) ((x) << S_RDQ_CH0_REQ_EMPTY)
11851 #define F_RDQ_CH0_REQ_EMPTY    V_RDQ_CH0_REQ_EMPTY(1U)
11852 
11853 #define S_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ    8
11854 #define V_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ)
11855 #define F_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ(1U)
11856 
11857 #define S_REQ_CTL_RD_CH0_WAIT_FOR_CMD    7
11858 #define V_REQ_CTL_RD_CH0_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_CMD)
11859 #define F_REQ_CTL_RD_CH0_WAIT_FOR_CMD    V_REQ_CTL_RD_CH0_WAIT_FOR_CMD(1U)
11860 
11861 #define S_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM    6
11862 #define V_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM)
11863 #define F_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM(1U)
11864 
11865 #define S_REQ_CTL_RD_CH0_WAIT_FOR_RDQ    5
11866 #define V_REQ_CTL_RD_CH0_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_RDQ)
11867 #define F_REQ_CTL_RD_CH0_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH0_WAIT_FOR_RDQ(1U)
11868 
11869 #define S_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO    4
11870 #define V_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO)
11871 #define F_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO(1U)
11872 
11873 #define S_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED    3
11874 #define V_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED)
11875 #define F_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED(1U)
11876 
11877 #define S_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED    2
11878 #define V_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED)
11879 #define F_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED(1U)
11880 
11881 #define S_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE    1
11882 #define V_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE)
11883 #define F_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE(1U)
11884 
11885 #define S_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA    0
11886 #define V_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA)
11887 #define F_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA(1U)
11888 
11889 #define A_PCIE_PDEBUG_REG_0X3 0x3
11890 
11891 #define S_TAGQ_CH1_TAGS_USED    11
11892 #define M_TAGQ_CH1_TAGS_USED    0xffU
11893 #define V_TAGQ_CH1_TAGS_USED(x) ((x) << S_TAGQ_CH1_TAGS_USED)
11894 #define G_TAGQ_CH1_TAGS_USED(x) (((x) >> S_TAGQ_CH1_TAGS_USED) & M_TAGQ_CH1_TAGS_USED)
11895 
11896 #define S_REQ_CH1_DATA_EMPTY    10
11897 #define V_REQ_CH1_DATA_EMPTY(x) ((x) << S_REQ_CH1_DATA_EMPTY)
11898 #define F_REQ_CH1_DATA_EMPTY    V_REQ_CH1_DATA_EMPTY(1U)
11899 
11900 #define S_RDQ_CH1_REQ_EMPTY    9
11901 #define V_RDQ_CH1_REQ_EMPTY(x) ((x) << S_RDQ_CH1_REQ_EMPTY)
11902 #define F_RDQ_CH1_REQ_EMPTY    V_RDQ_CH1_REQ_EMPTY(1U)
11903 
11904 #define S_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ    8
11905 #define V_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ)
11906 #define F_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ(1U)
11907 
11908 #define S_REQ_CTL_RD_CH1_WAIT_FOR_CMD    7
11909 #define V_REQ_CTL_RD_CH1_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_CMD)
11910 #define F_REQ_CTL_RD_CH1_WAIT_FOR_CMD    V_REQ_CTL_RD_CH1_WAIT_FOR_CMD(1U)
11911 
11912 #define S_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM    6
11913 #define V_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM)
11914 #define F_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM(1U)
11915 
11916 #define S_REQ_CTL_RD_CH1_WAIT_FOR_RDQ    5
11917 #define V_REQ_CTL_RD_CH1_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_RDQ)
11918 #define F_REQ_CTL_RD_CH1_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH1_WAIT_FOR_RDQ(1U)
11919 
11920 #define S_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO    4
11921 #define V_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO)
11922 #define F_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO(1U)
11923 
11924 #define S_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED    3
11925 #define V_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED)
11926 #define F_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED(1U)
11927 
11928 #define S_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED    2
11929 #define V_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED)
11930 #define F_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED(1U)
11931 
11932 #define S_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE    1
11933 #define V_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE)
11934 #define F_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE(1U)
11935 
11936 #define S_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA    0
11937 #define V_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA)
11938 #define F_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA(1U)
11939 
11940 #define A_PCIE_PDEBUG_REG_0X4 0x4
11941 
11942 #define S_TAGQ_CH2_TAGS_USED    11
11943 #define M_TAGQ_CH2_TAGS_USED    0xffU
11944 #define V_TAGQ_CH2_TAGS_USED(x) ((x) << S_TAGQ_CH2_TAGS_USED)
11945 #define G_TAGQ_CH2_TAGS_USED(x) (((x) >> S_TAGQ_CH2_TAGS_USED) & M_TAGQ_CH2_TAGS_USED)
11946 
11947 #define S_REQ_CH2_DATA_EMPTY    10
11948 #define V_REQ_CH2_DATA_EMPTY(x) ((x) << S_REQ_CH2_DATA_EMPTY)
11949 #define F_REQ_CH2_DATA_EMPTY    V_REQ_CH2_DATA_EMPTY(1U)
11950 
11951 #define S_RDQ_CH2_REQ_EMPTY    9
11952 #define V_RDQ_CH2_REQ_EMPTY(x) ((x) << S_RDQ_CH2_REQ_EMPTY)
11953 #define F_RDQ_CH2_REQ_EMPTY    V_RDQ_CH2_REQ_EMPTY(1U)
11954 
11955 #define S_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ    8
11956 #define V_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ)
11957 #define F_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ(1U)
11958 
11959 #define S_REQ_CTL_RD_CH2_WAIT_FOR_CMD    7
11960 #define V_REQ_CTL_RD_CH2_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_CMD)
11961 #define F_REQ_CTL_RD_CH2_WAIT_FOR_CMD    V_REQ_CTL_RD_CH2_WAIT_FOR_CMD(1U)
11962 
11963 #define S_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM    6
11964 #define V_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM)
11965 #define F_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM(1U)
11966 
11967 #define S_REQ_CTL_RD_CH2_WAIT_FOR_RDQ    5
11968 #define V_REQ_CTL_RD_CH2_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_RDQ)
11969 #define F_REQ_CTL_RD_CH2_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH2_WAIT_FOR_RDQ(1U)
11970 
11971 #define S_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO    4
11972 #define V_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO)
11973 #define F_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO(1U)
11974 
11975 #define S_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED    3
11976 #define V_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED)
11977 #define F_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED(1U)
11978 
11979 #define S_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED    2
11980 #define V_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED)
11981 #define F_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED(1U)
11982 
11983 #define S_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE    1
11984 #define V_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE)
11985 #define F_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE(1U)
11986 
11987 #define S_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA    0
11988 #define V_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA)
11989 #define F_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA(1U)
11990 
11991 #define A_PCIE_PDEBUG_REG_0X5 0x5
11992 
11993 #define S_TAGQ_CH3_TAGS_USED    11
11994 #define M_TAGQ_CH3_TAGS_USED    0xffU
11995 #define V_TAGQ_CH3_TAGS_USED(x) ((x) << S_TAGQ_CH3_TAGS_USED)
11996 #define G_TAGQ_CH3_TAGS_USED(x) (((x) >> S_TAGQ_CH3_TAGS_USED) & M_TAGQ_CH3_TAGS_USED)
11997 
11998 #define S_REQ_CH3_DATA_EMPTY    10
11999 #define V_REQ_CH3_DATA_EMPTY(x) ((x) << S_REQ_CH3_DATA_EMPTY)
12000 #define F_REQ_CH3_DATA_EMPTY    V_REQ_CH3_DATA_EMPTY(1U)
12001 
12002 #define S_RDQ_CH3_REQ_EMPTY    9
12003 #define V_RDQ_CH3_REQ_EMPTY(x) ((x) << S_RDQ_CH3_REQ_EMPTY)
12004 #define F_RDQ_CH3_REQ_EMPTY    V_RDQ_CH3_REQ_EMPTY(1U)
12005 
12006 #define S_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ    8
12007 #define V_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ)
12008 #define F_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ(1U)
12009 
12010 #define S_REQ_CTL_RD_CH3_WAIT_FOR_CMD    7
12011 #define V_REQ_CTL_RD_CH3_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_CMD)
12012 #define F_REQ_CTL_RD_CH3_WAIT_FOR_CMD    V_REQ_CTL_RD_CH3_WAIT_FOR_CMD(1U)
12013 
12014 #define S_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM    6
12015 #define V_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM)
12016 #define F_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM(1U)
12017 
12018 #define S_REQ_CTL_RD_CH3_WAIT_FOR_RDQ    5
12019 #define V_REQ_CTL_RD_CH3_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_RDQ)
12020 #define F_REQ_CTL_RD_CH3_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH3_WAIT_FOR_RDQ(1U)
12021 
12022 #define S_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO    4
12023 #define V_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO)
12024 #define F_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO(1U)
12025 
12026 #define S_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED    3
12027 #define V_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED)
12028 #define F_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED(1U)
12029 
12030 #define S_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED    2
12031 #define V_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED)
12032 #define F_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED(1U)
12033 
12034 #define S_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE    1
12035 #define V_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE)
12036 #define F_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE(1U)
12037 
12038 #define S_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA    0
12039 #define V_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA)
12040 #define F_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA(1U)
12041 
12042 #define A_PCIE_PDEBUG_REG_0X6 0x6
12043 
12044 #define S_TAGQ_CH4_TAGS_USED    11
12045 #define M_TAGQ_CH4_TAGS_USED    0xffU
12046 #define V_TAGQ_CH4_TAGS_USED(x) ((x) << S_TAGQ_CH4_TAGS_USED)
12047 #define G_TAGQ_CH4_TAGS_USED(x) (((x) >> S_TAGQ_CH4_TAGS_USED) & M_TAGQ_CH4_TAGS_USED)
12048 
12049 #define S_REQ_CH4_DATA_EMPTY    10
12050 #define V_REQ_CH4_DATA_EMPTY(x) ((x) << S_REQ_CH4_DATA_EMPTY)
12051 #define F_REQ_CH4_DATA_EMPTY    V_REQ_CH4_DATA_EMPTY(1U)
12052 
12053 #define S_RDQ_CH4_REQ_EMPTY    9
12054 #define V_RDQ_CH4_REQ_EMPTY(x) ((x) << S_RDQ_CH4_REQ_EMPTY)
12055 #define F_RDQ_CH4_REQ_EMPTY    V_RDQ_CH4_REQ_EMPTY(1U)
12056 
12057 #define S_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ    8
12058 #define V_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ)
12059 #define F_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ(1U)
12060 
12061 #define S_REQ_CTL_RD_CH4_WAIT_FOR_CMD    7
12062 #define V_REQ_CTL_RD_CH4_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_CMD)
12063 #define F_REQ_CTL_RD_CH4_WAIT_FOR_CMD    V_REQ_CTL_RD_CH4_WAIT_FOR_CMD(1U)
12064 
12065 #define S_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM    6
12066 #define V_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM)
12067 #define F_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM(1U)
12068 
12069 #define S_REQ_CTL_RD_CH4_WAIT_FOR_RDQ    5
12070 #define V_REQ_CTL_RD_CH4_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_RDQ)
12071 #define F_REQ_CTL_RD_CH4_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH4_WAIT_FOR_RDQ(1U)
12072 
12073 #define S_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO    4
12074 #define V_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO)
12075 #define F_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO(1U)
12076 
12077 #define S_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED    3
12078 #define V_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED)
12079 #define F_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED(1U)
12080 
12081 #define S_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED    2
12082 #define V_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED)
12083 #define F_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED(1U)
12084 
12085 #define S_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE    1
12086 #define V_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE)
12087 #define F_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE(1U)
12088 
12089 #define S_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA    0
12090 #define V_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA)
12091 #define F_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA(1U)
12092 
12093 #define A_PCIE_PDEBUG_REG_0X7 0x7
12094 
12095 #define S_TAGQ_CH5_TAGS_USED    11
12096 #define M_TAGQ_CH5_TAGS_USED    0xffU
12097 #define V_TAGQ_CH5_TAGS_USED(x) ((x) << S_TAGQ_CH5_TAGS_USED)
12098 #define G_TAGQ_CH5_TAGS_USED(x) (((x) >> S_TAGQ_CH5_TAGS_USED) & M_TAGQ_CH5_TAGS_USED)
12099 
12100 #define S_REQ_CH5_DATA_EMPTY    10
12101 #define V_REQ_CH5_DATA_EMPTY(x) ((x) << S_REQ_CH5_DATA_EMPTY)
12102 #define F_REQ_CH5_DATA_EMPTY    V_REQ_CH5_DATA_EMPTY(1U)
12103 
12104 #define S_RDQ_CH5_REQ_EMPTY    9
12105 #define V_RDQ_CH5_REQ_EMPTY(x) ((x) << S_RDQ_CH5_REQ_EMPTY)
12106 #define F_RDQ_CH5_REQ_EMPTY    V_RDQ_CH5_REQ_EMPTY(1U)
12107 
12108 #define S_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ    8
12109 #define V_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ)
12110 #define F_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ(1U)
12111 
12112 #define S_REQ_CTL_RD_CH5_WAIT_FOR_CMD    7
12113 #define V_REQ_CTL_RD_CH5_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_CMD)
12114 #define F_REQ_CTL_RD_CH5_WAIT_FOR_CMD    V_REQ_CTL_RD_CH5_WAIT_FOR_CMD(1U)
12115 
12116 #define S_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM    6
12117 #define V_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM)
12118 #define F_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM(1U)
12119 
12120 #define S_REQ_CTL_RD_CH5_WAIT_FOR_RDQ    5
12121 #define V_REQ_CTL_RD_CH5_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_RDQ)
12122 #define F_REQ_CTL_RD_CH5_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH5_WAIT_FOR_RDQ(1U)
12123 
12124 #define S_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO    4
12125 #define V_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO)
12126 #define F_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO(1U)
12127 
12128 #define S_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED    3
12129 #define V_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED)
12130 #define F_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED(1U)
12131 
12132 #define S_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED    2
12133 #define V_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED)
12134 #define F_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED(1U)
12135 
12136 #define S_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE    1
12137 #define V_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE)
12138 #define F_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE(1U)
12139 
12140 #define S_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA    0
12141 #define V_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA)
12142 #define F_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA(1U)
12143 
12144 #define A_PCIE_PDEBUG_REG_0X8 0x8
12145 
12146 #define S_TAGQ_CH6_TAGS_USED    11
12147 #define M_TAGQ_CH6_TAGS_USED    0xffU
12148 #define V_TAGQ_CH6_TAGS_USED(x) ((x) << S_TAGQ_CH6_TAGS_USED)
12149 #define G_TAGQ_CH6_TAGS_USED(x) (((x) >> S_TAGQ_CH6_TAGS_USED) & M_TAGQ_CH6_TAGS_USED)
12150 
12151 #define S_REQ_CH6_DATA_EMPTY    10
12152 #define V_REQ_CH6_DATA_EMPTY(x) ((x) << S_REQ_CH6_DATA_EMPTY)
12153 #define F_REQ_CH6_DATA_EMPTY    V_REQ_CH6_DATA_EMPTY(1U)
12154 
12155 #define S_RDQ_CH6_REQ_EMPTY    9
12156 #define V_RDQ_CH6_REQ_EMPTY(x) ((x) << S_RDQ_CH6_REQ_EMPTY)
12157 #define F_RDQ_CH6_REQ_EMPTY    V_RDQ_CH6_REQ_EMPTY(1U)
12158 
12159 #define S_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ    8
12160 #define V_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ)
12161 #define F_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ(1U)
12162 
12163 #define S_REQ_CTL_RD_CH6_WAIT_FOR_CMD    7
12164 #define V_REQ_CTL_RD_CH6_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_CMD)
12165 #define F_REQ_CTL_RD_CH6_WAIT_FOR_CMD    V_REQ_CTL_RD_CH6_WAIT_FOR_CMD(1U)
12166 
12167 #define S_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM    6
12168 #define V_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM)
12169 #define F_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM(1U)
12170 
12171 #define S_REQ_CTL_RD_CH6_WAIT_FOR_RDQ    5
12172 #define V_REQ_CTL_RD_CH6_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_RDQ)
12173 #define F_REQ_CTL_RD_CH6_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH6_WAIT_FOR_RDQ(1U)
12174 
12175 #define S_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO    4
12176 #define V_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO)
12177 #define F_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO(1U)
12178 
12179 #define S_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED    3
12180 #define V_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED)
12181 #define F_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED(1U)
12182 
12183 #define S_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED    2
12184 #define V_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED)
12185 #define F_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED(1U)
12186 
12187 #define S_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE    1
12188 #define V_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE)
12189 #define F_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE(1U)
12190 
12191 #define S_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA    0
12192 #define V_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA)
12193 #define F_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA(1U)
12194 
12195 #define A_PCIE_PDEBUG_REG_0X9 0x9
12196 
12197 #define S_TAGQ_CH7_TAGS_USED    11
12198 #define M_TAGQ_CH7_TAGS_USED    0xffU
12199 #define V_TAGQ_CH7_TAGS_USED(x) ((x) << S_TAGQ_CH7_TAGS_USED)
12200 #define G_TAGQ_CH7_TAGS_USED(x) (((x) >> S_TAGQ_CH7_TAGS_USED) & M_TAGQ_CH7_TAGS_USED)
12201 
12202 #define S_REQ_CH7_DATA_EMPTY    10
12203 #define V_REQ_CH7_DATA_EMPTY(x) ((x) << S_REQ_CH7_DATA_EMPTY)
12204 #define F_REQ_CH7_DATA_EMPTY    V_REQ_CH7_DATA_EMPTY(1U)
12205 
12206 #define S_RDQ_CH7_REQ_EMPTY    9
12207 #define V_RDQ_CH7_REQ_EMPTY(x) ((x) << S_RDQ_CH7_REQ_EMPTY)
12208 #define F_RDQ_CH7_REQ_EMPTY    V_RDQ_CH7_REQ_EMPTY(1U)
12209 
12210 #define S_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ    8
12211 #define V_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ)
12212 #define F_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ(1U)
12213 
12214 #define S_REQ_CTL_RD_CH7_WAIT_FOR_CMD    7
12215 #define V_REQ_CTL_RD_CH7_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_CMD)
12216 #define F_REQ_CTL_RD_CH7_WAIT_FOR_CMD    V_REQ_CTL_RD_CH7_WAIT_FOR_CMD(1U)
12217 
12218 #define S_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM    6
12219 #define V_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM)
12220 #define F_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM(1U)
12221 
12222 #define S_REQ_CTL_RD_CH7_WAIT_FOR_RDQ    5
12223 #define V_REQ_CTL_RD_CH7_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_RDQ)
12224 #define F_REQ_CTL_RD_CH7_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH7_WAIT_FOR_RDQ(1U)
12225 
12226 #define S_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO    4
12227 #define V_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO)
12228 #define F_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO(1U)
12229 
12230 #define S_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED    3
12231 #define V_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED)
12232 #define F_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED(1U)
12233 
12234 #define S_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED    2
12235 #define V_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED)
12236 #define F_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED(1U)
12237 
12238 #define S_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE    1
12239 #define V_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE)
12240 #define F_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE(1U)
12241 
12242 #define S_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA    0
12243 #define V_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA)
12244 #define F_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA(1U)
12245 
12246 #define A_PCIE_PDEBUG_REG_0XA 0xa
12247 
12248 #define S_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM    27
12249 #define V_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM)
12250 #define F_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM(1U)
12251 
12252 #define S_REQ_CTL_WR_CH0_SEQNUM    19
12253 #define M_REQ_CTL_WR_CH0_SEQNUM    0xffU
12254 #define V_REQ_CTL_WR_CH0_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH0_SEQNUM)
12255 #define G_REQ_CTL_WR_CH0_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH0_SEQNUM) & M_REQ_CTL_WR_CH0_SEQNUM)
12256 
12257 #define S_REQ_CTL_RD_CH0_SEQNUM    11
12258 #define M_REQ_CTL_RD_CH0_SEQNUM    0xffU
12259 #define V_REQ_CTL_RD_CH0_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH0_SEQNUM)
12260 #define G_REQ_CTL_RD_CH0_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH0_SEQNUM) & M_REQ_CTL_RD_CH0_SEQNUM)
12261 
12262 #define S_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO    4
12263 #define V_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO)
12264 #define F_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO(1U)
12265 
12266 #define S_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED    3
12267 #define V_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED)
12268 #define F_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED(1U)
12269 
12270 #define S_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED    2
12271 #define V_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED)
12272 #define F_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED(1U)
12273 
12274 #define S_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE    1
12275 #define V_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE)
12276 #define F_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE(1U)
12277 
12278 #define S_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA    0
12279 #define V_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA)
12280 #define F_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA(1U)
12281 
12282 #define A_PCIE_PDEBUG_REG_0XB 0xb
12283 
12284 #define S_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM    27
12285 #define V_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM)
12286 #define F_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM(1U)
12287 
12288 #define S_REQ_CTL_WR_CH1_SEQNUM    19
12289 #define M_REQ_CTL_WR_CH1_SEQNUM    0xffU
12290 #define V_REQ_CTL_WR_CH1_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH1_SEQNUM)
12291 #define G_REQ_CTL_WR_CH1_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH1_SEQNUM) & M_REQ_CTL_WR_CH1_SEQNUM)
12292 
12293 #define S_REQ_CTL_RD_CH1_SEQNUM    11
12294 #define M_REQ_CTL_RD_CH1_SEQNUM    0xffU
12295 #define V_REQ_CTL_RD_CH1_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH1_SEQNUM)
12296 #define G_REQ_CTL_RD_CH1_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH1_SEQNUM) & M_REQ_CTL_RD_CH1_SEQNUM)
12297 
12298 #define S_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO    4
12299 #define V_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO)
12300 #define F_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO(1U)
12301 
12302 #define S_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED    3
12303 #define V_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED)
12304 #define F_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED(1U)
12305 
12306 #define S_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED    2
12307 #define V_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED)
12308 #define F_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED(1U)
12309 
12310 #define S_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE    1
12311 #define V_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE)
12312 #define F_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE(1U)
12313 
12314 #define S_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA    0
12315 #define V_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA)
12316 #define F_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA(1U)
12317 
12318 #define A_PCIE_PDEBUG_REG_0XC 0xc
12319 
12320 #define S_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM    27
12321 #define V_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM)
12322 #define F_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM(1U)
12323 
12324 #define S_REQ_CTL_WR_CH2_SEQNUM    19
12325 #define M_REQ_CTL_WR_CH2_SEQNUM    0xffU
12326 #define V_REQ_CTL_WR_CH2_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH2_SEQNUM)
12327 #define G_REQ_CTL_WR_CH2_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH2_SEQNUM) & M_REQ_CTL_WR_CH2_SEQNUM)
12328 
12329 #define S_REQ_CTL_RD_CH2_SEQNUM    11
12330 #define M_REQ_CTL_RD_CH2_SEQNUM    0xffU
12331 #define V_REQ_CTL_RD_CH2_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH2_SEQNUM)
12332 #define G_REQ_CTL_RD_CH2_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH2_SEQNUM) & M_REQ_CTL_RD_CH2_SEQNUM)
12333 
12334 #define S_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO    4
12335 #define V_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO)
12336 #define F_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO(1U)
12337 
12338 #define S_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED    3
12339 #define V_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED)
12340 #define F_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED(1U)
12341 
12342 #define S_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED    2
12343 #define V_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED)
12344 #define F_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED(1U)
12345 
12346 #define S_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE    1
12347 #define V_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE)
12348 #define F_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE(1U)
12349 
12350 #define S_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA    0
12351 #define V_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA)
12352 #define F_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA(1U)
12353 
12354 #define A_PCIE_PDEBUG_REG_0XD 0xd
12355 
12356 #define S_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM    27
12357 #define V_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM)
12358 #define F_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM(1U)
12359 
12360 #define S_REQ_CTL_WR_CH3_SEQNUM    19
12361 #define M_REQ_CTL_WR_CH3_SEQNUM    0xffU
12362 #define V_REQ_CTL_WR_CH3_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH3_SEQNUM)
12363 #define G_REQ_CTL_WR_CH3_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH3_SEQNUM) & M_REQ_CTL_WR_CH3_SEQNUM)
12364 
12365 #define S_REQ_CTL_RD_CH3_SEQNUM    11
12366 #define M_REQ_CTL_RD_CH3_SEQNUM    0xffU
12367 #define V_REQ_CTL_RD_CH3_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH3_SEQNUM)
12368 #define G_REQ_CTL_RD_CH3_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH3_SEQNUM) & M_REQ_CTL_RD_CH3_SEQNUM)
12369 
12370 #define S_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO    4
12371 #define V_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO)
12372 #define F_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO(1U)
12373 
12374 #define S_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED    3
12375 #define V_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED)
12376 #define F_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED(1U)
12377 
12378 #define S_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED    2
12379 #define V_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED)
12380 #define F_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED(1U)
12381 
12382 #define S_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE    1
12383 #define V_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE)
12384 #define F_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE(1U)
12385 
12386 #define S_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA    0
12387 #define V_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA)
12388 #define F_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA(1U)
12389 
12390 #define A_PCIE_PDEBUG_REG_0XE 0xe
12391 
12392 #define S_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM    27
12393 #define V_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM)
12394 #define F_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM(1U)
12395 
12396 #define S_REQ_CTL_WR_CH4_SEQNUM    19
12397 #define M_REQ_CTL_WR_CH4_SEQNUM    0xffU
12398 #define V_REQ_CTL_WR_CH4_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH4_SEQNUM)
12399 #define G_REQ_CTL_WR_CH4_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH4_SEQNUM) & M_REQ_CTL_WR_CH4_SEQNUM)
12400 
12401 #define S_REQ_CTL_RD_CH4_SEQNUM    11
12402 #define M_REQ_CTL_RD_CH4_SEQNUM    0xffU
12403 #define V_REQ_CTL_RD_CH4_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH4_SEQNUM)
12404 #define G_REQ_CTL_RD_CH4_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH4_SEQNUM) & M_REQ_CTL_RD_CH4_SEQNUM)
12405 
12406 #define S_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO    4
12407 #define V_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO)
12408 #define F_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO(1U)
12409 
12410 #define S_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED    3
12411 #define V_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED)
12412 #define F_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED(1U)
12413 
12414 #define S_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED    2
12415 #define V_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED)
12416 #define F_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED(1U)
12417 
12418 #define S_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE    1
12419 #define V_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE)
12420 #define F_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE(1U)
12421 
12422 #define S_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA    0
12423 #define V_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA)
12424 #define F_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA(1U)
12425 
12426 #define A_PCIE_PDEBUG_REG_0XF 0xf
12427 #define A_PCIE_PDEBUG_REG_0X10 0x10
12428 
12429 #define S_PIPE0_TX3_DATAK_0    31
12430 #define V_PIPE0_TX3_DATAK_0(x) ((x) << S_PIPE0_TX3_DATAK_0)
12431 #define F_PIPE0_TX3_DATAK_0    V_PIPE0_TX3_DATAK_0(1U)
12432 
12433 #define S_PIPE0_TX3_DATA_6_0    24
12434 #define M_PIPE0_TX3_DATA_6_0    0x7fU
12435 #define V_PIPE0_TX3_DATA_6_0(x) ((x) << S_PIPE0_TX3_DATA_6_0)
12436 #define G_PIPE0_TX3_DATA_6_0(x) (((x) >> S_PIPE0_TX3_DATA_6_0) & M_PIPE0_TX3_DATA_6_0)
12437 
12438 #define S_PIPE0_TX2_DATA_7_0    16
12439 #define M_PIPE0_TX2_DATA_7_0    0xffU
12440 #define V_PIPE0_TX2_DATA_7_0(x) ((x) << S_PIPE0_TX2_DATA_7_0)
12441 #define G_PIPE0_TX2_DATA_7_0(x) (((x) >> S_PIPE0_TX2_DATA_7_0) & M_PIPE0_TX2_DATA_7_0)
12442 
12443 #define S_PIPE0_TX1_DATA_7_0    8
12444 #define M_PIPE0_TX1_DATA_7_0    0xffU
12445 #define V_PIPE0_TX1_DATA_7_0(x) ((x) << S_PIPE0_TX1_DATA_7_0)
12446 #define G_PIPE0_TX1_DATA_7_0(x) (((x) >> S_PIPE0_TX1_DATA_7_0) & M_PIPE0_TX1_DATA_7_0)
12447 
12448 #define S_PIPE0_TX0_DATAK_0    7
12449 #define V_PIPE0_TX0_DATAK_0(x) ((x) << S_PIPE0_TX0_DATAK_0)
12450 #define F_PIPE0_TX0_DATAK_0    V_PIPE0_TX0_DATAK_0(1U)
12451 
12452 #define S_PIPE0_TX0_DATA_6_0    0
12453 #define M_PIPE0_TX0_DATA_6_0    0x7fU
12454 #define V_PIPE0_TX0_DATA_6_0(x) ((x) << S_PIPE0_TX0_DATA_6_0)
12455 #define G_PIPE0_TX0_DATA_6_0(x) (((x) >> S_PIPE0_TX0_DATA_6_0) & M_PIPE0_TX0_DATA_6_0)
12456 
12457 #define A_PCIE_PDEBUG_REG_0X11 0x11
12458 
12459 #define S_PIPE0_TX3_DATAK_1    31
12460 #define V_PIPE0_TX3_DATAK_1(x) ((x) << S_PIPE0_TX3_DATAK_1)
12461 #define F_PIPE0_TX3_DATAK_1    V_PIPE0_TX3_DATAK_1(1U)
12462 
12463 #define S_PIPE0_TX3_DATA_14_8    24
12464 #define M_PIPE0_TX3_DATA_14_8    0x7fU
12465 #define V_PIPE0_TX3_DATA_14_8(x) ((x) << S_PIPE0_TX3_DATA_14_8)
12466 #define G_PIPE0_TX3_DATA_14_8(x) (((x) >> S_PIPE0_TX3_DATA_14_8) & M_PIPE0_TX3_DATA_14_8)
12467 
12468 #define S_PIPE0_TX2_DATA_15_8    16
12469 #define M_PIPE0_TX2_DATA_15_8    0xffU
12470 #define V_PIPE0_TX2_DATA_15_8(x) ((x) << S_PIPE0_TX2_DATA_15_8)
12471 #define G_PIPE0_TX2_DATA_15_8(x) (((x) >> S_PIPE0_TX2_DATA_15_8) & M_PIPE0_TX2_DATA_15_8)
12472 
12473 #define S_PIPE0_TX1_DATA_15_8    8
12474 #define M_PIPE0_TX1_DATA_15_8    0xffU
12475 #define V_PIPE0_TX1_DATA_15_8(x) ((x) << S_PIPE0_TX1_DATA_15_8)
12476 #define G_PIPE0_TX1_DATA_15_8(x) (((x) >> S_PIPE0_TX1_DATA_15_8) & M_PIPE0_TX1_DATA_15_8)
12477 
12478 #define S_PIPE0_TX0_DATAK_1    7
12479 #define V_PIPE0_TX0_DATAK_1(x) ((x) << S_PIPE0_TX0_DATAK_1)
12480 #define F_PIPE0_TX0_DATAK_1    V_PIPE0_TX0_DATAK_1(1U)
12481 
12482 #define S_PIPE0_TX0_DATA_14_8    0
12483 #define M_PIPE0_TX0_DATA_14_8    0x7fU
12484 #define V_PIPE0_TX0_DATA_14_8(x) ((x) << S_PIPE0_TX0_DATA_14_8)
12485 #define G_PIPE0_TX0_DATA_14_8(x) (((x) >> S_PIPE0_TX0_DATA_14_8) & M_PIPE0_TX0_DATA_14_8)
12486 
12487 #define A_PCIE_PDEBUG_REG_0X12 0x12
12488 
12489 #define S_PIPE0_TX7_DATAK_0    31
12490 #define V_PIPE0_TX7_DATAK_0(x) ((x) << S_PIPE0_TX7_DATAK_0)
12491 #define F_PIPE0_TX7_DATAK_0    V_PIPE0_TX7_DATAK_0(1U)
12492 
12493 #define S_PIPE0_TX7_DATA_6_0    24
12494 #define M_PIPE0_TX7_DATA_6_0    0x7fU
12495 #define V_PIPE0_TX7_DATA_6_0(x) ((x) << S_PIPE0_TX7_DATA_6_0)
12496 #define G_PIPE0_TX7_DATA_6_0(x) (((x) >> S_PIPE0_TX7_DATA_6_0) & M_PIPE0_TX7_DATA_6_0)
12497 
12498 #define S_PIPE0_TX6_DATA_7_0    16
12499 #define M_PIPE0_TX6_DATA_7_0    0xffU
12500 #define V_PIPE0_TX6_DATA_7_0(x) ((x) << S_PIPE0_TX6_DATA_7_0)
12501 #define G_PIPE0_TX6_DATA_7_0(x) (((x) >> S_PIPE0_TX6_DATA_7_0) & M_PIPE0_TX6_DATA_7_0)
12502 
12503 #define S_PIPE0_TX5_DATA_7_0    8
12504 #define M_PIPE0_TX5_DATA_7_0    0xffU
12505 #define V_PIPE0_TX5_DATA_7_0(x) ((x) << S_PIPE0_TX5_DATA_7_0)
12506 #define G_PIPE0_TX5_DATA_7_0(x) (((x) >> S_PIPE0_TX5_DATA_7_0) & M_PIPE0_TX5_DATA_7_0)
12507 
12508 #define S_PIPE0_TX4_DATAK_0    7
12509 #define V_PIPE0_TX4_DATAK_0(x) ((x) << S_PIPE0_TX4_DATAK_0)
12510 #define F_PIPE0_TX4_DATAK_0    V_PIPE0_TX4_DATAK_0(1U)
12511 
12512 #define S_PIPE0_TX4_DATA_6_0    0
12513 #define M_PIPE0_TX4_DATA_6_0    0x7fU
12514 #define V_PIPE0_TX4_DATA_6_0(x) ((x) << S_PIPE0_TX4_DATA_6_0)
12515 #define G_PIPE0_TX4_DATA_6_0(x) (((x) >> S_PIPE0_TX4_DATA_6_0) & M_PIPE0_TX4_DATA_6_0)
12516 
12517 #define A_PCIE_PDEBUG_REG_0X13 0x13
12518 
12519 #define S_PIPE0_TX7_DATAK_1    31
12520 #define V_PIPE0_TX7_DATAK_1(x) ((x) << S_PIPE0_TX7_DATAK_1)
12521 #define F_PIPE0_TX7_DATAK_1    V_PIPE0_TX7_DATAK_1(1U)
12522 
12523 #define S_PIPE0_TX7_DATA_14_8    24
12524 #define M_PIPE0_TX7_DATA_14_8    0x7fU
12525 #define V_PIPE0_TX7_DATA_14_8(x) ((x) << S_PIPE0_TX7_DATA_14_8)
12526 #define G_PIPE0_TX7_DATA_14_8(x) (((x) >> S_PIPE0_TX7_DATA_14_8) & M_PIPE0_TX7_DATA_14_8)
12527 
12528 #define S_PIPE0_TX6_DATA_15_8    16
12529 #define M_PIPE0_TX6_DATA_15_8    0xffU
12530 #define V_PIPE0_TX6_DATA_15_8(x) ((x) << S_PIPE0_TX6_DATA_15_8)
12531 #define G_PIPE0_TX6_DATA_15_8(x) (((x) >> S_PIPE0_TX6_DATA_15_8) & M_PIPE0_TX6_DATA_15_8)
12532 
12533 #define S_PIPE0_TX5_DATA_15_8    8
12534 #define M_PIPE0_TX5_DATA_15_8    0xffU
12535 #define V_PIPE0_TX5_DATA_15_8(x) ((x) << S_PIPE0_TX5_DATA_15_8)
12536 #define G_PIPE0_TX5_DATA_15_8(x) (((x) >> S_PIPE0_TX5_DATA_15_8) & M_PIPE0_TX5_DATA_15_8)
12537 
12538 #define S_PIPE0_TX4_DATAK_1    7
12539 #define V_PIPE0_TX4_DATAK_1(x) ((x) << S_PIPE0_TX4_DATAK_1)
12540 #define F_PIPE0_TX4_DATAK_1    V_PIPE0_TX4_DATAK_1(1U)
12541 
12542 #define S_PIPE0_TX4_DATA_14_8    0
12543 #define M_PIPE0_TX4_DATA_14_8    0x7fU
12544 #define V_PIPE0_TX4_DATA_14_8(x) ((x) << S_PIPE0_TX4_DATA_14_8)
12545 #define G_PIPE0_TX4_DATA_14_8(x) (((x) >> S_PIPE0_TX4_DATA_14_8) & M_PIPE0_TX4_DATA_14_8)
12546 
12547 #define A_PCIE_PDEBUG_REG_0X14 0x14
12548 
12549 #define S_PIPE0_RX3_VALID_14    31
12550 #define V_PIPE0_RX3_VALID_14(x) ((x) << S_PIPE0_RX3_VALID_14)
12551 #define F_PIPE0_RX3_VALID_14    V_PIPE0_RX3_VALID_14(1U)
12552 
12553 #define S_PIPE0_RX3_VALID2_14    24
12554 #define M_PIPE0_RX3_VALID2_14    0x7fU
12555 #define V_PIPE0_RX3_VALID2_14(x) ((x) << S_PIPE0_RX3_VALID2_14)
12556 #define G_PIPE0_RX3_VALID2_14(x) (((x) >> S_PIPE0_RX3_VALID2_14) & M_PIPE0_RX3_VALID2_14)
12557 
12558 #define S_PIPE0_RX2_VALID_14    16
12559 #define M_PIPE0_RX2_VALID_14    0xffU
12560 #define V_PIPE0_RX2_VALID_14(x) ((x) << S_PIPE0_RX2_VALID_14)
12561 #define G_PIPE0_RX2_VALID_14(x) (((x) >> S_PIPE0_RX2_VALID_14) & M_PIPE0_RX2_VALID_14)
12562 
12563 #define S_PIPE0_RX1_VALID_14    8
12564 #define M_PIPE0_RX1_VALID_14    0xffU
12565 #define V_PIPE0_RX1_VALID_14(x) ((x) << S_PIPE0_RX1_VALID_14)
12566 #define G_PIPE0_RX1_VALID_14(x) (((x) >> S_PIPE0_RX1_VALID_14) & M_PIPE0_RX1_VALID_14)
12567 
12568 #define S_PIPE0_RX0_VALID_14    7
12569 #define V_PIPE0_RX0_VALID_14(x) ((x) << S_PIPE0_RX0_VALID_14)
12570 #define F_PIPE0_RX0_VALID_14    V_PIPE0_RX0_VALID_14(1U)
12571 
12572 #define S_PIPE0_RX0_VALID2_14    0
12573 #define M_PIPE0_RX0_VALID2_14    0x7fU
12574 #define V_PIPE0_RX0_VALID2_14(x) ((x) << S_PIPE0_RX0_VALID2_14)
12575 #define G_PIPE0_RX0_VALID2_14(x) (((x) >> S_PIPE0_RX0_VALID2_14) & M_PIPE0_RX0_VALID2_14)
12576 
12577 #define A_PCIE_PDEBUG_REG_0X15 0x15
12578 
12579 #define S_PIPE0_RX3_VALID_15    31
12580 #define V_PIPE0_RX3_VALID_15(x) ((x) << S_PIPE0_RX3_VALID_15)
12581 #define F_PIPE0_RX3_VALID_15    V_PIPE0_RX3_VALID_15(1U)
12582 
12583 #define S_PIPE0_RX3_VALID2_15    24
12584 #define M_PIPE0_RX3_VALID2_15    0x7fU
12585 #define V_PIPE0_RX3_VALID2_15(x) ((x) << S_PIPE0_RX3_VALID2_15)
12586 #define G_PIPE0_RX3_VALID2_15(x) (((x) >> S_PIPE0_RX3_VALID2_15) & M_PIPE0_RX3_VALID2_15)
12587 
12588 #define S_PIPE0_RX2_VALID_15    16
12589 #define M_PIPE0_RX2_VALID_15    0xffU
12590 #define V_PIPE0_RX2_VALID_15(x) ((x) << S_PIPE0_RX2_VALID_15)
12591 #define G_PIPE0_RX2_VALID_15(x) (((x) >> S_PIPE0_RX2_VALID_15) & M_PIPE0_RX2_VALID_15)
12592 
12593 #define S_PIPE0_RX1_VALID_15    8
12594 #define M_PIPE0_RX1_VALID_15    0xffU
12595 #define V_PIPE0_RX1_VALID_15(x) ((x) << S_PIPE0_RX1_VALID_15)
12596 #define G_PIPE0_RX1_VALID_15(x) (((x) >> S_PIPE0_RX1_VALID_15) & M_PIPE0_RX1_VALID_15)
12597 
12598 #define S_PIPE0_RX0_VALID_15    7
12599 #define V_PIPE0_RX0_VALID_15(x) ((x) << S_PIPE0_RX0_VALID_15)
12600 #define F_PIPE0_RX0_VALID_15    V_PIPE0_RX0_VALID_15(1U)
12601 
12602 #define S_PIPE0_RX0_VALID2_15    0
12603 #define M_PIPE0_RX0_VALID2_15    0x7fU
12604 #define V_PIPE0_RX0_VALID2_15(x) ((x) << S_PIPE0_RX0_VALID2_15)
12605 #define G_PIPE0_RX0_VALID2_15(x) (((x) >> S_PIPE0_RX0_VALID2_15) & M_PIPE0_RX0_VALID2_15)
12606 
12607 #define A_PCIE_PDEBUG_REG_0X16 0x16
12608 
12609 #define S_PIPE0_RX7_VALID_16    31
12610 #define V_PIPE0_RX7_VALID_16(x) ((x) << S_PIPE0_RX7_VALID_16)
12611 #define F_PIPE0_RX7_VALID_16    V_PIPE0_RX7_VALID_16(1U)
12612 
12613 #define S_PIPE0_RX7_VALID2_16    24
12614 #define M_PIPE0_RX7_VALID2_16    0x7fU
12615 #define V_PIPE0_RX7_VALID2_16(x) ((x) << S_PIPE0_RX7_VALID2_16)
12616 #define G_PIPE0_RX7_VALID2_16(x) (((x) >> S_PIPE0_RX7_VALID2_16) & M_PIPE0_RX7_VALID2_16)
12617 
12618 #define S_PIPE0_RX6_VALID_16    16
12619 #define M_PIPE0_RX6_VALID_16    0xffU
12620 #define V_PIPE0_RX6_VALID_16(x) ((x) << S_PIPE0_RX6_VALID_16)
12621 #define G_PIPE0_RX6_VALID_16(x) (((x) >> S_PIPE0_RX6_VALID_16) & M_PIPE0_RX6_VALID_16)
12622 
12623 #define S_PIPE0_RX5_VALID_16    8
12624 #define M_PIPE0_RX5_VALID_16    0xffU
12625 #define V_PIPE0_RX5_VALID_16(x) ((x) << S_PIPE0_RX5_VALID_16)
12626 #define G_PIPE0_RX5_VALID_16(x) (((x) >> S_PIPE0_RX5_VALID_16) & M_PIPE0_RX5_VALID_16)
12627 
12628 #define S_PIPE0_RX4_VALID_16    7
12629 #define V_PIPE0_RX4_VALID_16(x) ((x) << S_PIPE0_RX4_VALID_16)
12630 #define F_PIPE0_RX4_VALID_16    V_PIPE0_RX4_VALID_16(1U)
12631 
12632 #define S_PIPE0_RX4_VALID2_16    0
12633 #define M_PIPE0_RX4_VALID2_16    0x7fU
12634 #define V_PIPE0_RX4_VALID2_16(x) ((x) << S_PIPE0_RX4_VALID2_16)
12635 #define G_PIPE0_RX4_VALID2_16(x) (((x) >> S_PIPE0_RX4_VALID2_16) & M_PIPE0_RX4_VALID2_16)
12636 
12637 #define A_PCIE_PDEBUG_REG_0X17 0x17
12638 
12639 #define S_PIPE0_RX7_VALID_17    31
12640 #define V_PIPE0_RX7_VALID_17(x) ((x) << S_PIPE0_RX7_VALID_17)
12641 #define F_PIPE0_RX7_VALID_17    V_PIPE0_RX7_VALID_17(1U)
12642 
12643 #define S_PIPE0_RX7_VALID2_17    24
12644 #define M_PIPE0_RX7_VALID2_17    0x7fU
12645 #define V_PIPE0_RX7_VALID2_17(x) ((x) << S_PIPE0_RX7_VALID2_17)
12646 #define G_PIPE0_RX7_VALID2_17(x) (((x) >> S_PIPE0_RX7_VALID2_17) & M_PIPE0_RX7_VALID2_17)
12647 
12648 #define S_PIPE0_RX6_VALID_17    16
12649 #define M_PIPE0_RX6_VALID_17    0xffU
12650 #define V_PIPE0_RX6_VALID_17(x) ((x) << S_PIPE0_RX6_VALID_17)
12651 #define G_PIPE0_RX6_VALID_17(x) (((x) >> S_PIPE0_RX6_VALID_17) & M_PIPE0_RX6_VALID_17)
12652 
12653 #define S_PIPE0_RX5_VALID_17    8
12654 #define M_PIPE0_RX5_VALID_17    0xffU
12655 #define V_PIPE0_RX5_VALID_17(x) ((x) << S_PIPE0_RX5_VALID_17)
12656 #define G_PIPE0_RX5_VALID_17(x) (((x) >> S_PIPE0_RX5_VALID_17) & M_PIPE0_RX5_VALID_17)
12657 
12658 #define S_PIPE0_RX4_VALID_17    7
12659 #define V_PIPE0_RX4_VALID_17(x) ((x) << S_PIPE0_RX4_VALID_17)
12660 #define F_PIPE0_RX4_VALID_17    V_PIPE0_RX4_VALID_17(1U)
12661 
12662 #define S_PIPE0_RX4_VALID2_17    0
12663 #define M_PIPE0_RX4_VALID2_17    0x7fU
12664 #define V_PIPE0_RX4_VALID2_17(x) ((x) << S_PIPE0_RX4_VALID2_17)
12665 #define G_PIPE0_RX4_VALID2_17(x) (((x) >> S_PIPE0_RX4_VALID2_17) & M_PIPE0_RX4_VALID2_17)
12666 
12667 #define A_PCIE_PDEBUG_REG_0X18 0x18
12668 
12669 #define S_PIPE0_RX7_POLARITY    31
12670 #define V_PIPE0_RX7_POLARITY(x) ((x) << S_PIPE0_RX7_POLARITY)
12671 #define F_PIPE0_RX7_POLARITY    V_PIPE0_RX7_POLARITY(1U)
12672 
12673 #define S_PIPE0_RX7_STATUS    28
12674 #define M_PIPE0_RX7_STATUS    0x7U
12675 #define V_PIPE0_RX7_STATUS(x) ((x) << S_PIPE0_RX7_STATUS)
12676 #define G_PIPE0_RX7_STATUS(x) (((x) >> S_PIPE0_RX7_STATUS) & M_PIPE0_RX7_STATUS)
12677 
12678 #define S_PIPE0_RX6_POLARITY    27
12679 #define V_PIPE0_RX6_POLARITY(x) ((x) << S_PIPE0_RX6_POLARITY)
12680 #define F_PIPE0_RX6_POLARITY    V_PIPE0_RX6_POLARITY(1U)
12681 
12682 #define S_PIPE0_RX6_STATUS    24
12683 #define M_PIPE0_RX6_STATUS    0x7U
12684 #define V_PIPE0_RX6_STATUS(x) ((x) << S_PIPE0_RX6_STATUS)
12685 #define G_PIPE0_RX6_STATUS(x) (((x) >> S_PIPE0_RX6_STATUS) & M_PIPE0_RX6_STATUS)
12686 
12687 #define S_PIPE0_RX5_POLARITY    23
12688 #define V_PIPE0_RX5_POLARITY(x) ((x) << S_PIPE0_RX5_POLARITY)
12689 #define F_PIPE0_RX5_POLARITY    V_PIPE0_RX5_POLARITY(1U)
12690 
12691 #define S_PIPE0_RX5_STATUS    20
12692 #define M_PIPE0_RX5_STATUS    0x7U
12693 #define V_PIPE0_RX5_STATUS(x) ((x) << S_PIPE0_RX5_STATUS)
12694 #define G_PIPE0_RX5_STATUS(x) (((x) >> S_PIPE0_RX5_STATUS) & M_PIPE0_RX5_STATUS)
12695 
12696 #define S_PIPE0_RX4_POLARITY    19
12697 #define V_PIPE0_RX4_POLARITY(x) ((x) << S_PIPE0_RX4_POLARITY)
12698 #define F_PIPE0_RX4_POLARITY    V_PIPE0_RX4_POLARITY(1U)
12699 
12700 #define S_PIPE0_RX4_STATUS    16
12701 #define M_PIPE0_RX4_STATUS    0x7U
12702 #define V_PIPE0_RX4_STATUS(x) ((x) << S_PIPE0_RX4_STATUS)
12703 #define G_PIPE0_RX4_STATUS(x) (((x) >> S_PIPE0_RX4_STATUS) & M_PIPE0_RX4_STATUS)
12704 
12705 #define S_PIPE0_RX3_POLARITY    15
12706 #define V_PIPE0_RX3_POLARITY(x) ((x) << S_PIPE0_RX3_POLARITY)
12707 #define F_PIPE0_RX3_POLARITY    V_PIPE0_RX3_POLARITY(1U)
12708 
12709 #define S_PIPE0_RX3_STATUS    12
12710 #define M_PIPE0_RX3_STATUS    0x7U
12711 #define V_PIPE0_RX3_STATUS(x) ((x) << S_PIPE0_RX3_STATUS)
12712 #define G_PIPE0_RX3_STATUS(x) (((x) >> S_PIPE0_RX3_STATUS) & M_PIPE0_RX3_STATUS)
12713 
12714 #define S_PIPE0_RX2_POLARITY    11
12715 #define V_PIPE0_RX2_POLARITY(x) ((x) << S_PIPE0_RX2_POLARITY)
12716 #define F_PIPE0_RX2_POLARITY    V_PIPE0_RX2_POLARITY(1U)
12717 
12718 #define S_PIPE0_RX2_STATUS    8
12719 #define M_PIPE0_RX2_STATUS    0x7U
12720 #define V_PIPE0_RX2_STATUS(x) ((x) << S_PIPE0_RX2_STATUS)
12721 #define G_PIPE0_RX2_STATUS(x) (((x) >> S_PIPE0_RX2_STATUS) & M_PIPE0_RX2_STATUS)
12722 
12723 #define S_PIPE0_RX1_POLARITY    7
12724 #define V_PIPE0_RX1_POLARITY(x) ((x) << S_PIPE0_RX1_POLARITY)
12725 #define F_PIPE0_RX1_POLARITY    V_PIPE0_RX1_POLARITY(1U)
12726 
12727 #define S_PIPE0_RX1_STATUS    4
12728 #define M_PIPE0_RX1_STATUS    0x7U
12729 #define V_PIPE0_RX1_STATUS(x) ((x) << S_PIPE0_RX1_STATUS)
12730 #define G_PIPE0_RX1_STATUS(x) (((x) >> S_PIPE0_RX1_STATUS) & M_PIPE0_RX1_STATUS)
12731 
12732 #define S_PIPE0_RX0_POLARITY    3
12733 #define V_PIPE0_RX0_POLARITY(x) ((x) << S_PIPE0_RX0_POLARITY)
12734 #define F_PIPE0_RX0_POLARITY    V_PIPE0_RX0_POLARITY(1U)
12735 
12736 #define S_PIPE0_RX0_STATUS    0
12737 #define M_PIPE0_RX0_STATUS    0x7U
12738 #define V_PIPE0_RX0_STATUS(x) ((x) << S_PIPE0_RX0_STATUS)
12739 #define G_PIPE0_RX0_STATUS(x) (((x) >> S_PIPE0_RX0_STATUS) & M_PIPE0_RX0_STATUS)
12740 
12741 #define A_PCIE_PDEBUG_REG_0X19 0x19
12742 
12743 #define S_PIPE0_TX7_COMPLIANCE    31
12744 #define V_PIPE0_TX7_COMPLIANCE(x) ((x) << S_PIPE0_TX7_COMPLIANCE)
12745 #define F_PIPE0_TX7_COMPLIANCE    V_PIPE0_TX7_COMPLIANCE(1U)
12746 
12747 #define S_PIPE0_TX6_COMPLIANCE    30
12748 #define V_PIPE0_TX6_COMPLIANCE(x) ((x) << S_PIPE0_TX6_COMPLIANCE)
12749 #define F_PIPE0_TX6_COMPLIANCE    V_PIPE0_TX6_COMPLIANCE(1U)
12750 
12751 #define S_PIPE0_TX5_COMPLIANCE    29
12752 #define V_PIPE0_TX5_COMPLIANCE(x) ((x) << S_PIPE0_TX5_COMPLIANCE)
12753 #define F_PIPE0_TX5_COMPLIANCE    V_PIPE0_TX5_COMPLIANCE(1U)
12754 
12755 #define S_PIPE0_TX4_COMPLIANCE    28
12756 #define V_PIPE0_TX4_COMPLIANCE(x) ((x) << S_PIPE0_TX4_COMPLIANCE)
12757 #define F_PIPE0_TX4_COMPLIANCE    V_PIPE0_TX4_COMPLIANCE(1U)
12758 
12759 #define S_PIPE0_TX3_COMPLIANCE    27
12760 #define V_PIPE0_TX3_COMPLIANCE(x) ((x) << S_PIPE0_TX3_COMPLIANCE)
12761 #define F_PIPE0_TX3_COMPLIANCE    V_PIPE0_TX3_COMPLIANCE(1U)
12762 
12763 #define S_PIPE0_TX2_COMPLIANCE    26
12764 #define V_PIPE0_TX2_COMPLIANCE(x) ((x) << S_PIPE0_TX2_COMPLIANCE)
12765 #define F_PIPE0_TX2_COMPLIANCE    V_PIPE0_TX2_COMPLIANCE(1U)
12766 
12767 #define S_PIPE0_TX1_COMPLIANCE    25
12768 #define V_PIPE0_TX1_COMPLIANCE(x) ((x) << S_PIPE0_TX1_COMPLIANCE)
12769 #define F_PIPE0_TX1_COMPLIANCE    V_PIPE0_TX1_COMPLIANCE(1U)
12770 
12771 #define S_PIPE0_TX0_COMPLIANCE    24
12772 #define V_PIPE0_TX0_COMPLIANCE(x) ((x) << S_PIPE0_TX0_COMPLIANCE)
12773 #define F_PIPE0_TX0_COMPLIANCE    V_PIPE0_TX0_COMPLIANCE(1U)
12774 
12775 #define S_PIPE0_TX7_ELECIDLE    23
12776 #define V_PIPE0_TX7_ELECIDLE(x) ((x) << S_PIPE0_TX7_ELECIDLE)
12777 #define F_PIPE0_TX7_ELECIDLE    V_PIPE0_TX7_ELECIDLE(1U)
12778 
12779 #define S_PIPE0_TX6_ELECIDLE    22
12780 #define V_PIPE0_TX6_ELECIDLE(x) ((x) << S_PIPE0_TX6_ELECIDLE)
12781 #define F_PIPE0_TX6_ELECIDLE    V_PIPE0_TX6_ELECIDLE(1U)
12782 
12783 #define S_PIPE0_TX5_ELECIDLE    21
12784 #define V_PIPE0_TX5_ELECIDLE(x) ((x) << S_PIPE0_TX5_ELECIDLE)
12785 #define F_PIPE0_TX5_ELECIDLE    V_PIPE0_TX5_ELECIDLE(1U)
12786 
12787 #define S_PIPE0_TX4_ELECIDLE    20
12788 #define V_PIPE0_TX4_ELECIDLE(x) ((x) << S_PIPE0_TX4_ELECIDLE)
12789 #define F_PIPE0_TX4_ELECIDLE    V_PIPE0_TX4_ELECIDLE(1U)
12790 
12791 #define S_PIPE0_TX3_ELECIDLE    19
12792 #define V_PIPE0_TX3_ELECIDLE(x) ((x) << S_PIPE0_TX3_ELECIDLE)
12793 #define F_PIPE0_TX3_ELECIDLE    V_PIPE0_TX3_ELECIDLE(1U)
12794 
12795 #define S_PIPE0_TX2_ELECIDLE    18
12796 #define V_PIPE0_TX2_ELECIDLE(x) ((x) << S_PIPE0_TX2_ELECIDLE)
12797 #define F_PIPE0_TX2_ELECIDLE    V_PIPE0_TX2_ELECIDLE(1U)
12798 
12799 #define S_PIPE0_TX1_ELECIDLE    17
12800 #define V_PIPE0_TX1_ELECIDLE(x) ((x) << S_PIPE0_TX1_ELECIDLE)
12801 #define F_PIPE0_TX1_ELECIDLE    V_PIPE0_TX1_ELECIDLE(1U)
12802 
12803 #define S_PIPE0_TX0_ELECIDLE    16
12804 #define V_PIPE0_TX0_ELECIDLE(x) ((x) << S_PIPE0_TX0_ELECIDLE)
12805 #define F_PIPE0_TX0_ELECIDLE    V_PIPE0_TX0_ELECIDLE(1U)
12806 
12807 #define S_PIPE0_RX7_POLARITY_19    15
12808 #define V_PIPE0_RX7_POLARITY_19(x) ((x) << S_PIPE0_RX7_POLARITY_19)
12809 #define F_PIPE0_RX7_POLARITY_19    V_PIPE0_RX7_POLARITY_19(1U)
12810 
12811 #define S_PIPE0_RX6_POLARITY_19    14
12812 #define V_PIPE0_RX6_POLARITY_19(x) ((x) << S_PIPE0_RX6_POLARITY_19)
12813 #define F_PIPE0_RX6_POLARITY_19    V_PIPE0_RX6_POLARITY_19(1U)
12814 
12815 #define S_PIPE0_RX5_POLARITY_19    13
12816 #define V_PIPE0_RX5_POLARITY_19(x) ((x) << S_PIPE0_RX5_POLARITY_19)
12817 #define F_PIPE0_RX5_POLARITY_19    V_PIPE0_RX5_POLARITY_19(1U)
12818 
12819 #define S_PIPE0_RX4_POLARITY_19    12
12820 #define V_PIPE0_RX4_POLARITY_19(x) ((x) << S_PIPE0_RX4_POLARITY_19)
12821 #define F_PIPE0_RX4_POLARITY_19    V_PIPE0_RX4_POLARITY_19(1U)
12822 
12823 #define S_PIPE0_RX3_POLARITY_19    11
12824 #define V_PIPE0_RX3_POLARITY_19(x) ((x) << S_PIPE0_RX3_POLARITY_19)
12825 #define F_PIPE0_RX3_POLARITY_19    V_PIPE0_RX3_POLARITY_19(1U)
12826 
12827 #define S_PIPE0_RX2_POLARITY_19    10
12828 #define V_PIPE0_RX2_POLARITY_19(x) ((x) << S_PIPE0_RX2_POLARITY_19)
12829 #define F_PIPE0_RX2_POLARITY_19    V_PIPE0_RX2_POLARITY_19(1U)
12830 
12831 #define S_PIPE0_RX1_POLARITY_19    9
12832 #define V_PIPE0_RX1_POLARITY_19(x) ((x) << S_PIPE0_RX1_POLARITY_19)
12833 #define F_PIPE0_RX1_POLARITY_19    V_PIPE0_RX1_POLARITY_19(1U)
12834 
12835 #define S_PIPE0_RX0_POLARITY_19    8
12836 #define V_PIPE0_RX0_POLARITY_19(x) ((x) << S_PIPE0_RX0_POLARITY_19)
12837 #define F_PIPE0_RX0_POLARITY_19    V_PIPE0_RX0_POLARITY_19(1U)
12838 
12839 #define S_PIPE0_RX7_ELECIDLE    7
12840 #define V_PIPE0_RX7_ELECIDLE(x) ((x) << S_PIPE0_RX7_ELECIDLE)
12841 #define F_PIPE0_RX7_ELECIDLE    V_PIPE0_RX7_ELECIDLE(1U)
12842 
12843 #define S_PIPE0_RX6_ELECIDLE    6
12844 #define V_PIPE0_RX6_ELECIDLE(x) ((x) << S_PIPE0_RX6_ELECIDLE)
12845 #define F_PIPE0_RX6_ELECIDLE    V_PIPE0_RX6_ELECIDLE(1U)
12846 
12847 #define S_PIPE0_RX5_ELECIDLE    5
12848 #define V_PIPE0_RX5_ELECIDLE(x) ((x) << S_PIPE0_RX5_ELECIDLE)
12849 #define F_PIPE0_RX5_ELECIDLE    V_PIPE0_RX5_ELECIDLE(1U)
12850 
12851 #define S_PIPE0_RX4_ELECIDLE    4
12852 #define V_PIPE0_RX4_ELECIDLE(x) ((x) << S_PIPE0_RX4_ELECIDLE)
12853 #define F_PIPE0_RX4_ELECIDLE    V_PIPE0_RX4_ELECIDLE(1U)
12854 
12855 #define S_PIPE0_RX3_ELECIDLE    3
12856 #define V_PIPE0_RX3_ELECIDLE(x) ((x) << S_PIPE0_RX3_ELECIDLE)
12857 #define F_PIPE0_RX3_ELECIDLE    V_PIPE0_RX3_ELECIDLE(1U)
12858 
12859 #define S_PIPE0_RX2_ELECIDLE    2
12860 #define V_PIPE0_RX2_ELECIDLE(x) ((x) << S_PIPE0_RX2_ELECIDLE)
12861 #define F_PIPE0_RX2_ELECIDLE    V_PIPE0_RX2_ELECIDLE(1U)
12862 
12863 #define S_PIPE0_RX1_ELECIDLE    1
12864 #define V_PIPE0_RX1_ELECIDLE(x) ((x) << S_PIPE0_RX1_ELECIDLE)
12865 #define F_PIPE0_RX1_ELECIDLE    V_PIPE0_RX1_ELECIDLE(1U)
12866 
12867 #define S_PIPE0_RX0_ELECIDLE    0
12868 #define V_PIPE0_RX0_ELECIDLE(x) ((x) << S_PIPE0_RX0_ELECIDLE)
12869 #define F_PIPE0_RX0_ELECIDLE    V_PIPE0_RX0_ELECIDLE(1U)
12870 
12871 #define A_PCIE_PDEBUG_REG_0X1A 0x1a
12872 
12873 #define S_PIPE0_RESET_N    21
12874 #define V_PIPE0_RESET_N(x) ((x) << S_PIPE0_RESET_N)
12875 #define F_PIPE0_RESET_N    V_PIPE0_RESET_N(1U)
12876 
12877 #define S_PCS_COMMON_CLOCKS    20
12878 #define V_PCS_COMMON_CLOCKS(x) ((x) << S_PCS_COMMON_CLOCKS)
12879 #define F_PCS_COMMON_CLOCKS    V_PCS_COMMON_CLOCKS(1U)
12880 
12881 #define S_PCS_CLK_REQ    19
12882 #define V_PCS_CLK_REQ(x) ((x) << S_PCS_CLK_REQ)
12883 #define F_PCS_CLK_REQ    V_PCS_CLK_REQ(1U)
12884 
12885 #define S_PIPE_CLKREQ_N    18
12886 #define V_PIPE_CLKREQ_N(x) ((x) << S_PIPE_CLKREQ_N)
12887 #define F_PIPE_CLKREQ_N    V_PIPE_CLKREQ_N(1U)
12888 
12889 #define S_MAC_CLKREQ_N_TO_MUX    17
12890 #define V_MAC_CLKREQ_N_TO_MUX(x) ((x) << S_MAC_CLKREQ_N_TO_MUX)
12891 #define F_MAC_CLKREQ_N_TO_MUX    V_MAC_CLKREQ_N_TO_MUX(1U)
12892 
12893 #define S_PIPE0_TX2RX_LOOPBK    16
12894 #define V_PIPE0_TX2RX_LOOPBK(x) ((x) << S_PIPE0_TX2RX_LOOPBK)
12895 #define F_PIPE0_TX2RX_LOOPBK    V_PIPE0_TX2RX_LOOPBK(1U)
12896 
12897 #define S_PIPE0_TX_SWING    15
12898 #define V_PIPE0_TX_SWING(x) ((x) << S_PIPE0_TX_SWING)
12899 #define F_PIPE0_TX_SWING    V_PIPE0_TX_SWING(1U)
12900 
12901 #define S_PIPE0_TX_MARGIN    12
12902 #define M_PIPE0_TX_MARGIN    0x7U
12903 #define V_PIPE0_TX_MARGIN(x) ((x) << S_PIPE0_TX_MARGIN)
12904 #define G_PIPE0_TX_MARGIN(x) (((x) >> S_PIPE0_TX_MARGIN) & M_PIPE0_TX_MARGIN)
12905 
12906 #define S_PIPE0_TX_DEEMPH    11
12907 #define V_PIPE0_TX_DEEMPH(x) ((x) << S_PIPE0_TX_DEEMPH)
12908 #define F_PIPE0_TX_DEEMPH    V_PIPE0_TX_DEEMPH(1U)
12909 
12910 #define S_PIPE0_TX_DETECTRX    10
12911 #define V_PIPE0_TX_DETECTRX(x) ((x) << S_PIPE0_TX_DETECTRX)
12912 #define F_PIPE0_TX_DETECTRX    V_PIPE0_TX_DETECTRX(1U)
12913 
12914 #define S_PIPE0_POWERDOWN    8
12915 #define M_PIPE0_POWERDOWN    0x3U
12916 #define V_PIPE0_POWERDOWN(x) ((x) << S_PIPE0_POWERDOWN)
12917 #define G_PIPE0_POWERDOWN(x) (((x) >> S_PIPE0_POWERDOWN) & M_PIPE0_POWERDOWN)
12918 
12919 #define S_PHY_MAC_PHYSTATUS    0
12920 #define M_PHY_MAC_PHYSTATUS    0xffU
12921 #define V_PHY_MAC_PHYSTATUS(x) ((x) << S_PHY_MAC_PHYSTATUS)
12922 #define G_PHY_MAC_PHYSTATUS(x) (((x) >> S_PHY_MAC_PHYSTATUS) & M_PHY_MAC_PHYSTATUS)
12923 
12924 #define A_PCIE_PDEBUG_REG_0X1B 0x1b
12925 
12926 #define S_PIPE0_RX7_EQ_IN_PROG    31
12927 #define V_PIPE0_RX7_EQ_IN_PROG(x) ((x) << S_PIPE0_RX7_EQ_IN_PROG)
12928 #define F_PIPE0_RX7_EQ_IN_PROG    V_PIPE0_RX7_EQ_IN_PROG(1U)
12929 
12930 #define S_PIPE0_RX7_EQ_INVLD_REQ    30
12931 #define V_PIPE0_RX7_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX7_EQ_INVLD_REQ)
12932 #define F_PIPE0_RX7_EQ_INVLD_REQ    V_PIPE0_RX7_EQ_INVLD_REQ(1U)
12933 
12934 #define S_PIPE0_RX7_SYNCHEADER    28
12935 #define M_PIPE0_RX7_SYNCHEADER    0x3U
12936 #define V_PIPE0_RX7_SYNCHEADER(x) ((x) << S_PIPE0_RX7_SYNCHEADER)
12937 #define G_PIPE0_RX7_SYNCHEADER(x) (((x) >> S_PIPE0_RX7_SYNCHEADER) & M_PIPE0_RX7_SYNCHEADER)
12938 
12939 #define S_PIPE0_RX6_EQ_IN_PROG    27
12940 #define V_PIPE0_RX6_EQ_IN_PROG(x) ((x) << S_PIPE0_RX6_EQ_IN_PROG)
12941 #define F_PIPE0_RX6_EQ_IN_PROG    V_PIPE0_RX6_EQ_IN_PROG(1U)
12942 
12943 #define S_PIPE0_RX6_EQ_INVLD_REQ    26
12944 #define V_PIPE0_RX6_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX6_EQ_INVLD_REQ)
12945 #define F_PIPE0_RX6_EQ_INVLD_REQ    V_PIPE0_RX6_EQ_INVLD_REQ(1U)
12946 
12947 #define S_PIPE0_RX6_SYNCHEADER    24
12948 #define M_PIPE0_RX6_SYNCHEADER    0x3U
12949 #define V_PIPE0_RX6_SYNCHEADER(x) ((x) << S_PIPE0_RX6_SYNCHEADER)
12950 #define G_PIPE0_RX6_SYNCHEADER(x) (((x) >> S_PIPE0_RX6_SYNCHEADER) & M_PIPE0_RX6_SYNCHEADER)
12951 
12952 #define S_PIPE0_RX5_EQ_IN_PROG    23
12953 #define V_PIPE0_RX5_EQ_IN_PROG(x) ((x) << S_PIPE0_RX5_EQ_IN_PROG)
12954 #define F_PIPE0_RX5_EQ_IN_PROG    V_PIPE0_RX5_EQ_IN_PROG(1U)
12955 
12956 #define S_PIPE0_RX5_EQ_INVLD_REQ    22
12957 #define V_PIPE0_RX5_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX5_EQ_INVLD_REQ)
12958 #define F_PIPE0_RX5_EQ_INVLD_REQ    V_PIPE0_RX5_EQ_INVLD_REQ(1U)
12959 
12960 #define S_PIPE0_RX5_SYNCHEADER    20
12961 #define M_PIPE0_RX5_SYNCHEADER    0x3U
12962 #define V_PIPE0_RX5_SYNCHEADER(x) ((x) << S_PIPE0_RX5_SYNCHEADER)
12963 #define G_PIPE0_RX5_SYNCHEADER(x) (((x) >> S_PIPE0_RX5_SYNCHEADER) & M_PIPE0_RX5_SYNCHEADER)
12964 
12965 #define S_PIPE0_RX4_EQ_IN_PROG    19
12966 #define V_PIPE0_RX4_EQ_IN_PROG(x) ((x) << S_PIPE0_RX4_EQ_IN_PROG)
12967 #define F_PIPE0_RX4_EQ_IN_PROG    V_PIPE0_RX4_EQ_IN_PROG(1U)
12968 
12969 #define S_PIPE0_RX4_EQ_INVLD_REQ    18
12970 #define V_PIPE0_RX4_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX4_EQ_INVLD_REQ)
12971 #define F_PIPE0_RX4_EQ_INVLD_REQ    V_PIPE0_RX4_EQ_INVLD_REQ(1U)
12972 
12973 #define S_PIPE0_RX4_SYNCHEADER    16
12974 #define M_PIPE0_RX4_SYNCHEADER    0x3U
12975 #define V_PIPE0_RX4_SYNCHEADER(x) ((x) << S_PIPE0_RX4_SYNCHEADER)
12976 #define G_PIPE0_RX4_SYNCHEADER(x) (((x) >> S_PIPE0_RX4_SYNCHEADER) & M_PIPE0_RX4_SYNCHEADER)
12977 
12978 #define S_PIPE0_RX3_EQ_IN_PROG    15
12979 #define V_PIPE0_RX3_EQ_IN_PROG(x) ((x) << S_PIPE0_RX3_EQ_IN_PROG)
12980 #define F_PIPE0_RX3_EQ_IN_PROG    V_PIPE0_RX3_EQ_IN_PROG(1U)
12981 
12982 #define S_PIPE0_RX3_EQ_INVLD_REQ    14
12983 #define V_PIPE0_RX3_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX3_EQ_INVLD_REQ)
12984 #define F_PIPE0_RX3_EQ_INVLD_REQ    V_PIPE0_RX3_EQ_INVLD_REQ(1U)
12985 
12986 #define S_PIPE0_RX3_SYNCHEADER    12
12987 #define M_PIPE0_RX3_SYNCHEADER    0x3U
12988 #define V_PIPE0_RX3_SYNCHEADER(x) ((x) << S_PIPE0_RX3_SYNCHEADER)
12989 #define G_PIPE0_RX3_SYNCHEADER(x) (((x) >> S_PIPE0_RX3_SYNCHEADER) & M_PIPE0_RX3_SYNCHEADER)
12990 
12991 #define S_PIPE0_RX2_EQ_IN_PROG    11
12992 #define V_PIPE0_RX2_EQ_IN_PROG(x) ((x) << S_PIPE0_RX2_EQ_IN_PROG)
12993 #define F_PIPE0_RX2_EQ_IN_PROG    V_PIPE0_RX2_EQ_IN_PROG(1U)
12994 
12995 #define S_PIPE0_RX2_EQ_INVLD_REQ    10
12996 #define V_PIPE0_RX2_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX2_EQ_INVLD_REQ)
12997 #define F_PIPE0_RX2_EQ_INVLD_REQ    V_PIPE0_RX2_EQ_INVLD_REQ(1U)
12998 
12999 #define S_PIPE0_RX2_SYNCHEADER    8
13000 #define M_PIPE0_RX2_SYNCHEADER    0x3U
13001 #define V_PIPE0_RX2_SYNCHEADER(x) ((x) << S_PIPE0_RX2_SYNCHEADER)
13002 #define G_PIPE0_RX2_SYNCHEADER(x) (((x) >> S_PIPE0_RX2_SYNCHEADER) & M_PIPE0_RX2_SYNCHEADER)
13003 
13004 #define S_PIPE0_RX1_EQ_IN_PROG    7
13005 #define V_PIPE0_RX1_EQ_IN_PROG(x) ((x) << S_PIPE0_RX1_EQ_IN_PROG)
13006 #define F_PIPE0_RX1_EQ_IN_PROG    V_PIPE0_RX1_EQ_IN_PROG(1U)
13007 
13008 #define S_PIPE0_RX1_EQ_INVLD_REQ    6
13009 #define V_PIPE0_RX1_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX1_EQ_INVLD_REQ)
13010 #define F_PIPE0_RX1_EQ_INVLD_REQ    V_PIPE0_RX1_EQ_INVLD_REQ(1U)
13011 
13012 #define S_PIPE0_RX1_SYNCHEADER    4
13013 #define M_PIPE0_RX1_SYNCHEADER    0x3U
13014 #define V_PIPE0_RX1_SYNCHEADER(x) ((x) << S_PIPE0_RX1_SYNCHEADER)
13015 #define G_PIPE0_RX1_SYNCHEADER(x) (((x) >> S_PIPE0_RX1_SYNCHEADER) & M_PIPE0_RX1_SYNCHEADER)
13016 
13017 #define S_PIPE0_RX0_EQ_IN_PROG    3
13018 #define V_PIPE0_RX0_EQ_IN_PROG(x) ((x) << S_PIPE0_RX0_EQ_IN_PROG)
13019 #define F_PIPE0_RX0_EQ_IN_PROG    V_PIPE0_RX0_EQ_IN_PROG(1U)
13020 
13021 #define S_PIPE0_RX0_EQ_INVLD_REQ    2
13022 #define V_PIPE0_RX0_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX0_EQ_INVLD_REQ)
13023 #define F_PIPE0_RX0_EQ_INVLD_REQ    V_PIPE0_RX0_EQ_INVLD_REQ(1U)
13024 
13025 #define S_PIPE0_RX0_SYNCHEADER    0
13026 #define M_PIPE0_RX0_SYNCHEADER    0x3U
13027 #define V_PIPE0_RX0_SYNCHEADER(x) ((x) << S_PIPE0_RX0_SYNCHEADER)
13028 #define G_PIPE0_RX0_SYNCHEADER(x) (((x) >> S_PIPE0_RX0_SYNCHEADER) & M_PIPE0_RX0_SYNCHEADER)
13029 
13030 #define A_PCIE_PDEBUG_REG_0X1C 0x1c
13031 
13032 #define S_SI_REQVFID    24
13033 #define M_SI_REQVFID    0xffU
13034 #define V_SI_REQVFID(x) ((x) << S_SI_REQVFID)
13035 #define G_SI_REQVFID(x) (((x) >> S_SI_REQVFID) & M_SI_REQVFID)
13036 
13037 #define S_SI_REQVEC    13
13038 #define M_SI_REQVEC    0x7ffU
13039 #define V_SI_REQVEC(x) ((x) << S_SI_REQVEC)
13040 #define G_SI_REQVEC(x) (((x) >> S_SI_REQVEC) & M_SI_REQVEC)
13041 
13042 #define S_SI_REQTCVAL    10
13043 #define M_SI_REQTCVAL    0x7U
13044 #define V_SI_REQTCVAL(x) ((x) << S_SI_REQTCVAL)
13045 #define G_SI_REQTCVAL(x) (((x) >> S_SI_REQTCVAL) & M_SI_REQTCVAL)
13046 
13047 #define S_SI_REQRDY    9
13048 #define V_SI_REQRDY(x) ((x) << S_SI_REQRDY)
13049 #define F_SI_REQRDY    V_SI_REQRDY(1U)
13050 
13051 #define S_SI_REQVLD    8
13052 #define V_SI_REQVLD(x) ((x) << S_SI_REQVLD)
13053 #define F_SI_REQVLD    V_SI_REQVLD(1U)
13054 
13055 #define S_T5_AI    0
13056 #define M_T5_AI    0xffU
13057 #define V_T5_AI(x) ((x) << S_T5_AI)
13058 #define G_T5_AI(x) (((x) >> S_T5_AI) & M_T5_AI)
13059 
13060 #define A_PCIE_PDEBUG_REG_0X1D 0x1d
13061 
13062 #define S_GNTSI    31
13063 #define V_GNTSI(x) ((x) << S_GNTSI)
13064 #define F_GNTSI    V_GNTSI(1U)
13065 
13066 #define S_DROPINTFORFLR    30
13067 #define V_DROPINTFORFLR(x) ((x) << S_DROPINTFORFLR)
13068 #define F_DROPINTFORFLR    V_DROPINTFORFLR(1U)
13069 
13070 #define S_SMARB    27
13071 #define M_SMARB    0x7U
13072 #define V_SMARB(x) ((x) << S_SMARB)
13073 #define G_SMARB(x) (((x) >> S_SMARB) & M_SMARB)
13074 
13075 #define S_SMDEFR    24
13076 #define M_SMDEFR    0x7U
13077 #define V_SMDEFR(x) ((x) << S_SMDEFR)
13078 #define G_SMDEFR(x) (((x) >> S_SMDEFR) & M_SMDEFR)
13079 
13080 #define S_SYS_INT    16
13081 #define M_SYS_INT    0xffU
13082 #define V_SYS_INT(x) ((x) << S_SYS_INT)
13083 #define G_SYS_INT(x) (((x) >> S_SYS_INT) & M_SYS_INT)
13084 
13085 #define S_CFG_INTXCLR    8
13086 #define M_CFG_INTXCLR    0xffU
13087 #define V_CFG_INTXCLR(x) ((x) << S_CFG_INTXCLR)
13088 #define G_CFG_INTXCLR(x) (((x) >> S_CFG_INTXCLR) & M_CFG_INTXCLR)
13089 
13090 #define S_PIO_INTXCLR    0
13091 #define M_PIO_INTXCLR    0xffU
13092 #define V_PIO_INTXCLR(x) ((x) << S_PIO_INTXCLR)
13093 #define G_PIO_INTXCLR(x) (((x) >> S_PIO_INTXCLR) & M_PIO_INTXCLR)
13094 
13095 #define A_PCIE_PDEBUG_REG_0X1E 0x1e
13096 
13097 #define S_PLI_TABDATWREN    31
13098 #define V_PLI_TABDATWREN(x) ((x) << S_PLI_TABDATWREN)
13099 #define F_PLI_TABDATWREN    V_PLI_TABDATWREN(1U)
13100 
13101 #define S_TAB_RDENA    30
13102 #define V_TAB_RDENA(x) ((x) << S_TAB_RDENA)
13103 #define F_TAB_RDENA    V_TAB_RDENA(1U)
13104 
13105 #define S_TAB_RDENA2    19
13106 #define M_TAB_RDENA2    0x7ffU
13107 #define V_TAB_RDENA2(x) ((x) << S_TAB_RDENA2)
13108 #define G_TAB_RDENA2(x) (((x) >> S_TAB_RDENA2) & M_TAB_RDENA2)
13109 
13110 #define S_PLI_REQADDR    10
13111 #define M_PLI_REQADDR    0x1ffU
13112 #define V_PLI_REQADDR(x) ((x) << S_PLI_REQADDR)
13113 #define G_PLI_REQADDR(x) (((x) >> S_PLI_REQADDR) & M_PLI_REQADDR)
13114 
13115 #define S_PLI_REQVFID    2
13116 #define M_PLI_REQVFID    0xffU
13117 #define V_PLI_REQVFID(x) ((x) << S_PLI_REQVFID)
13118 #define G_PLI_REQVFID(x) (((x) >> S_PLI_REQVFID) & M_PLI_REQVFID)
13119 
13120 #define S_PLI_REQTABHIT    1
13121 #define V_PLI_REQTABHIT(x) ((x) << S_PLI_REQTABHIT)
13122 #define F_PLI_REQTABHIT    V_PLI_REQTABHIT(1U)
13123 
13124 #define S_PLI_REQRDVLD    0
13125 #define V_PLI_REQRDVLD(x) ((x) << S_PLI_REQRDVLD)
13126 #define F_PLI_REQRDVLD    V_PLI_REQRDVLD(1U)
13127 
13128 #define A_PCIE_PDEBUG_REG_0X1F 0x1f
13129 #define A_PCIE_PDEBUG_REG_0X20 0x20
13130 #define A_PCIE_PDEBUG_REG_0X21 0x21
13131 
13132 #define S_PLI_REQPBASTART    20
13133 #define M_PLI_REQPBASTART    0xfffU
13134 #define V_PLI_REQPBASTART(x) ((x) << S_PLI_REQPBASTART)
13135 #define G_PLI_REQPBASTART(x) (((x) >> S_PLI_REQPBASTART) & M_PLI_REQPBASTART)
13136 
13137 #define S_PLI_REQPBAEND    9
13138 #define M_PLI_REQPBAEND    0x7ffU
13139 #define V_PLI_REQPBAEND(x) ((x) << S_PLI_REQPBAEND)
13140 #define G_PLI_REQPBAEND(x) (((x) >> S_PLI_REQPBAEND) & M_PLI_REQPBAEND)
13141 
13142 #define S_T5_PLI_REQVFID    2
13143 #define M_T5_PLI_REQVFID    0x7fU
13144 #define V_T5_PLI_REQVFID(x) ((x) << S_T5_PLI_REQVFID)
13145 #define G_T5_PLI_REQVFID(x) (((x) >> S_T5_PLI_REQVFID) & M_T5_PLI_REQVFID)
13146 
13147 #define S_PLI_REQPBAHIT    1
13148 #define V_PLI_REQPBAHIT(x) ((x) << S_PLI_REQPBAHIT)
13149 #define F_PLI_REQPBAHIT    V_PLI_REQPBAHIT(1U)
13150 
13151 #define A_PCIE_PDEBUG_REG_0X22 0x22
13152 
13153 #define S_GNTSI1    31
13154 #define V_GNTSI1(x) ((x) << S_GNTSI1)
13155 #define F_GNTSI1    V_GNTSI1(1U)
13156 
13157 #define S_GNTSI2    30
13158 #define V_GNTSI2(x) ((x) << S_GNTSI2)
13159 #define F_GNTSI2    V_GNTSI2(1U)
13160 
13161 #define S_GNTSI3    27
13162 #define M_GNTSI3    0x7U
13163 #define V_GNTSI3(x) ((x) << S_GNTSI3)
13164 #define G_GNTSI3(x) (((x) >> S_GNTSI3) & M_GNTSI3)
13165 
13166 #define S_GNTSI4    16
13167 #define M_GNTSI4    0x7ffU
13168 #define V_GNTSI4(x) ((x) << S_GNTSI4)
13169 #define G_GNTSI4(x) (((x) >> S_GNTSI4) & M_GNTSI4)
13170 
13171 #define S_GNTSI5    8
13172 #define M_GNTSI5    0xffU
13173 #define V_GNTSI5(x) ((x) << S_GNTSI5)
13174 #define G_GNTSI5(x) (((x) >> S_GNTSI5) & M_GNTSI5)
13175 
13176 #define S_GNTSI6    7
13177 #define V_GNTSI6(x) ((x) << S_GNTSI6)
13178 #define F_GNTSI6    V_GNTSI6(1U)
13179 
13180 #define S_GNTSI7    6
13181 #define V_GNTSI7(x) ((x) << S_GNTSI7)
13182 #define F_GNTSI7    V_GNTSI7(1U)
13183 
13184 #define S_GNTSI8    5
13185 #define V_GNTSI8(x) ((x) << S_GNTSI8)
13186 #define F_GNTSI8    V_GNTSI8(1U)
13187 
13188 #define S_GNTSI9    4
13189 #define V_GNTSI9(x) ((x) << S_GNTSI9)
13190 #define F_GNTSI9    V_GNTSI9(1U)
13191 
13192 #define S_GNTSIA    3
13193 #define V_GNTSIA(x) ((x) << S_GNTSIA)
13194 #define F_GNTSIA    V_GNTSIA(1U)
13195 
13196 #define S_GNTAI    2
13197 #define V_GNTAI(x) ((x) << S_GNTAI)
13198 #define F_GNTAI    V_GNTAI(1U)
13199 
13200 #define S_GNTDB    1
13201 #define V_GNTDB(x) ((x) << S_GNTDB)
13202 #define F_GNTDB    V_GNTDB(1U)
13203 
13204 #define S_GNTDI    0
13205 #define V_GNTDI(x) ((x) << S_GNTDI)
13206 #define F_GNTDI    V_GNTDI(1U)
13207 
13208 #define A_PCIE_PDEBUG_REG_0X23 0x23
13209 
13210 #define S_DI_REQVLD    31
13211 #define V_DI_REQVLD(x) ((x) << S_DI_REQVLD)
13212 #define F_DI_REQVLD    V_DI_REQVLD(1U)
13213 
13214 #define S_DI_REQRDY    30
13215 #define V_DI_REQRDY(x) ((x) << S_DI_REQRDY)
13216 #define F_DI_REQRDY    V_DI_REQRDY(1U)
13217 
13218 #define S_DI_REQWREN    19
13219 #define M_DI_REQWREN    0x7ffU
13220 #define V_DI_REQWREN(x) ((x) << S_DI_REQWREN)
13221 #define G_DI_REQWREN(x) (((x) >> S_DI_REQWREN) & M_DI_REQWREN)
13222 
13223 #define S_DI_REQMSIEN    18
13224 #define V_DI_REQMSIEN(x) ((x) << S_DI_REQMSIEN)
13225 #define F_DI_REQMSIEN    V_DI_REQMSIEN(1U)
13226 
13227 #define S_DI_REQMSXEN    17
13228 #define V_DI_REQMSXEN(x) ((x) << S_DI_REQMSXEN)
13229 #define F_DI_REQMSXEN    V_DI_REQMSXEN(1U)
13230 
13231 #define S_DI_REQMSXVFIDMSK    16
13232 #define V_DI_REQMSXVFIDMSK(x) ((x) << S_DI_REQMSXVFIDMSK)
13233 #define F_DI_REQMSXVFIDMSK    V_DI_REQMSXVFIDMSK(1U)
13234 
13235 #define S_DI_REQWREN2    2
13236 #define M_DI_REQWREN2    0x3fffU
13237 #define V_DI_REQWREN2(x) ((x) << S_DI_REQWREN2)
13238 #define G_DI_REQWREN2(x) (((x) >> S_DI_REQWREN2) & M_DI_REQWREN2)
13239 
13240 #define S_DI_REQRDEN    1
13241 #define V_DI_REQRDEN(x) ((x) << S_DI_REQRDEN)
13242 #define F_DI_REQRDEN    V_DI_REQRDEN(1U)
13243 
13244 #define S_DI_REQWREN3    0
13245 #define V_DI_REQWREN3(x) ((x) << S_DI_REQWREN3)
13246 #define F_DI_REQWREN3    V_DI_REQWREN3(1U)
13247 
13248 #define A_PCIE_PDEBUG_REG_0X24 0x24
13249 #define A_PCIE_PDEBUG_REG_0X25 0x25
13250 #define A_PCIE_PDEBUG_REG_0X26 0x26
13251 #define A_PCIE_PDEBUG_REG_0X27 0x27
13252 
13253 #define S_FID_STI_RSPVLD    31
13254 #define V_FID_STI_RSPVLD(x) ((x) << S_FID_STI_RSPVLD)
13255 #define F_FID_STI_RSPVLD    V_FID_STI_RSPVLD(1U)
13256 
13257 #define S_TAB_STIRDENA    30
13258 #define V_TAB_STIRDENA(x) ((x) << S_TAB_STIRDENA)
13259 #define F_TAB_STIRDENA    V_TAB_STIRDENA(1U)
13260 
13261 #define S_TAB_STIWRENA    29
13262 #define V_TAB_STIWRENA(x) ((x) << S_TAB_STIWRENA)
13263 #define F_TAB_STIWRENA    V_TAB_STIWRENA(1U)
13264 
13265 #define S_TAB_STIRDENA2    18
13266 #define M_TAB_STIRDENA2    0x7ffU
13267 #define V_TAB_STIRDENA2(x) ((x) << S_TAB_STIRDENA2)
13268 #define G_TAB_STIRDENA2(x) (((x) >> S_TAB_STIRDENA2) & M_TAB_STIRDENA2)
13269 
13270 #define S_T5_PLI_REQTABHIT    7
13271 #define M_T5_PLI_REQTABHIT    0x7ffU
13272 #define V_T5_PLI_REQTABHIT(x) ((x) << S_T5_PLI_REQTABHIT)
13273 #define G_T5_PLI_REQTABHIT(x) (((x) >> S_T5_PLI_REQTABHIT) & M_T5_PLI_REQTABHIT)
13274 
13275 #define S_T5_GNTSI    0
13276 #define M_T5_GNTSI    0x7fU
13277 #define V_T5_GNTSI(x) ((x) << S_T5_GNTSI)
13278 #define G_T5_GNTSI(x) (((x) >> S_T5_GNTSI) & M_T5_GNTSI)
13279 
13280 #define A_PCIE_PDEBUG_REG_0X28 0x28
13281 
13282 #define S_PLI_REQWRVLD    31
13283 #define V_PLI_REQWRVLD(x) ((x) << S_PLI_REQWRVLD)
13284 #define F_PLI_REQWRVLD    V_PLI_REQWRVLD(1U)
13285 
13286 #define S_T5_PLI_REQPBAHIT    30
13287 #define V_T5_PLI_REQPBAHIT(x) ((x) << S_T5_PLI_REQPBAHIT)
13288 #define F_T5_PLI_REQPBAHIT    V_T5_PLI_REQPBAHIT(1U)
13289 
13290 #define S_PLI_TABADDRLWREN    29
13291 #define V_PLI_TABADDRLWREN(x) ((x) << S_PLI_TABADDRLWREN)
13292 #define F_PLI_TABADDRLWREN    V_PLI_TABADDRLWREN(1U)
13293 
13294 #define S_PLI_TABADDRHWREN    28
13295 #define V_PLI_TABADDRHWREN(x) ((x) << S_PLI_TABADDRHWREN)
13296 #define F_PLI_TABADDRHWREN    V_PLI_TABADDRHWREN(1U)
13297 
13298 #define S_T5_PLI_TABDATWREN    27
13299 #define V_T5_PLI_TABDATWREN(x) ((x) << S_T5_PLI_TABDATWREN)
13300 #define F_T5_PLI_TABDATWREN    V_T5_PLI_TABDATWREN(1U)
13301 
13302 #define S_PLI_TABMSKWREN    26
13303 #define V_PLI_TABMSKWREN(x) ((x) << S_PLI_TABMSKWREN)
13304 #define F_PLI_TABMSKWREN    V_PLI_TABMSKWREN(1U)
13305 
13306 #define S_AI_REQVLD    23
13307 #define M_AI_REQVLD    0x7U
13308 #define V_AI_REQVLD(x) ((x) << S_AI_REQVLD)
13309 #define G_AI_REQVLD(x) (((x) >> S_AI_REQVLD) & M_AI_REQVLD)
13310 
13311 #define S_AI_REQVLD2    22
13312 #define V_AI_REQVLD2(x) ((x) << S_AI_REQVLD2)
13313 #define F_AI_REQVLD2    V_AI_REQVLD2(1U)
13314 
13315 #define S_AI_REQRDY    21
13316 #define V_AI_REQRDY(x) ((x) << S_AI_REQRDY)
13317 #define F_AI_REQRDY    V_AI_REQRDY(1U)
13318 
13319 #define S_VEN_MSI_REQ_28    18
13320 #define M_VEN_MSI_REQ_28    0x7U
13321 #define V_VEN_MSI_REQ_28(x) ((x) << S_VEN_MSI_REQ_28)
13322 #define G_VEN_MSI_REQ_28(x) (((x) >> S_VEN_MSI_REQ_28) & M_VEN_MSI_REQ_28)
13323 
13324 #define S_VEN_MSI_REQ2    11
13325 #define M_VEN_MSI_REQ2    0x7fU
13326 #define V_VEN_MSI_REQ2(x) ((x) << S_VEN_MSI_REQ2)
13327 #define G_VEN_MSI_REQ2(x) (((x) >> S_VEN_MSI_REQ2) & M_VEN_MSI_REQ2)
13328 
13329 #define S_VEN_MSI_REQ3    6
13330 #define M_VEN_MSI_REQ3    0x1fU
13331 #define V_VEN_MSI_REQ3(x) ((x) << S_VEN_MSI_REQ3)
13332 #define G_VEN_MSI_REQ3(x) (((x) >> S_VEN_MSI_REQ3) & M_VEN_MSI_REQ3)
13333 
13334 #define S_VEN_MSI_REQ4    3
13335 #define M_VEN_MSI_REQ4    0x7U
13336 #define V_VEN_MSI_REQ4(x) ((x) << S_VEN_MSI_REQ4)
13337 #define G_VEN_MSI_REQ4(x) (((x) >> S_VEN_MSI_REQ4) & M_VEN_MSI_REQ4)
13338 
13339 #define S_VEN_MSI_REQ5    2
13340 #define V_VEN_MSI_REQ5(x) ((x) << S_VEN_MSI_REQ5)
13341 #define F_VEN_MSI_REQ5    V_VEN_MSI_REQ5(1U)
13342 
13343 #define S_VEN_MSI_GRANT    1
13344 #define V_VEN_MSI_GRANT(x) ((x) << S_VEN_MSI_GRANT)
13345 #define F_VEN_MSI_GRANT    V_VEN_MSI_GRANT(1U)
13346 
13347 #define S_VEN_MSI_REQ6    0
13348 #define V_VEN_MSI_REQ6(x) ((x) << S_VEN_MSI_REQ6)
13349 #define F_VEN_MSI_REQ6    V_VEN_MSI_REQ6(1U)
13350 
13351 #define A_PCIE_PDEBUG_REG_0X29 0x29
13352 
13353 #define S_TRGT1_REQDATAVLD    16
13354 #define M_TRGT1_REQDATAVLD    0xffffU
13355 #define V_TRGT1_REQDATAVLD(x) ((x) << S_TRGT1_REQDATAVLD)
13356 #define G_TRGT1_REQDATAVLD(x) (((x) >> S_TRGT1_REQDATAVLD) & M_TRGT1_REQDATAVLD)
13357 
13358 #define S_TRGT1_REQDATAVLD2    12
13359 #define M_TRGT1_REQDATAVLD2    0xfU
13360 #define V_TRGT1_REQDATAVLD2(x) ((x) << S_TRGT1_REQDATAVLD2)
13361 #define G_TRGT1_REQDATAVLD2(x) (((x) >> S_TRGT1_REQDATAVLD2) & M_TRGT1_REQDATAVLD2)
13362 
13363 #define S_TRGT1_REQDATAVLD3    11
13364 #define V_TRGT1_REQDATAVLD3(x) ((x) << S_TRGT1_REQDATAVLD3)
13365 #define F_TRGT1_REQDATAVLD3    V_TRGT1_REQDATAVLD3(1U)
13366 
13367 #define S_TRGT1_REQDATAVLD4    10
13368 #define V_TRGT1_REQDATAVLD4(x) ((x) << S_TRGT1_REQDATAVLD4)
13369 #define F_TRGT1_REQDATAVLD4    V_TRGT1_REQDATAVLD4(1U)
13370 
13371 #define S_TRGT1_REQDATAVLD5    9
13372 #define V_TRGT1_REQDATAVLD5(x) ((x) << S_TRGT1_REQDATAVLD5)
13373 #define F_TRGT1_REQDATAVLD5    V_TRGT1_REQDATAVLD5(1U)
13374 
13375 #define S_TRGT1_REQDATAVLD6    8
13376 #define V_TRGT1_REQDATAVLD6(x) ((x) << S_TRGT1_REQDATAVLD6)
13377 #define F_TRGT1_REQDATAVLD6    V_TRGT1_REQDATAVLD6(1U)
13378 
13379 #define S_TRGT1_REQDATAVLD7    4
13380 #define M_TRGT1_REQDATAVLD7    0xfU
13381 #define V_TRGT1_REQDATAVLD7(x) ((x) << S_TRGT1_REQDATAVLD7)
13382 #define G_TRGT1_REQDATAVLD7(x) (((x) >> S_TRGT1_REQDATAVLD7) & M_TRGT1_REQDATAVLD7)
13383 
13384 #define S_TRGT1_REQDATAVLD8    2
13385 #define M_TRGT1_REQDATAVLD8    0x3U
13386 #define V_TRGT1_REQDATAVLD8(x) ((x) << S_TRGT1_REQDATAVLD8)
13387 #define G_TRGT1_REQDATAVLD8(x) (((x) >> S_TRGT1_REQDATAVLD8) & M_TRGT1_REQDATAVLD8)
13388 
13389 #define S_TRGT1_REQDATARDY    1
13390 #define V_TRGT1_REQDATARDY(x) ((x) << S_TRGT1_REQDATARDY)
13391 #define F_TRGT1_REQDATARDY    V_TRGT1_REQDATARDY(1U)
13392 
13393 #define S_TRGT1_REQDATAVLD0    0
13394 #define V_TRGT1_REQDATAVLD0(x) ((x) << S_TRGT1_REQDATAVLD0)
13395 #define F_TRGT1_REQDATAVLD0    V_TRGT1_REQDATAVLD0(1U)
13396 
13397 #define A_PCIE_PDEBUG_REG_0X2A 0x2a
13398 #define A_PCIE_PDEBUG_REG_0X2B 0x2b
13399 
13400 #define S_RADM_TRGT1_ADDR    20
13401 #define M_RADM_TRGT1_ADDR    0xfffU
13402 #define V_RADM_TRGT1_ADDR(x) ((x) << S_RADM_TRGT1_ADDR)
13403 #define G_RADM_TRGT1_ADDR(x) (((x) >> S_RADM_TRGT1_ADDR) & M_RADM_TRGT1_ADDR)
13404 
13405 #define S_RADM_TRGT1_DWEN    16
13406 #define M_RADM_TRGT1_DWEN    0xfU
13407 #define V_RADM_TRGT1_DWEN(x) ((x) << S_RADM_TRGT1_DWEN)
13408 #define G_RADM_TRGT1_DWEN(x) (((x) >> S_RADM_TRGT1_DWEN) & M_RADM_TRGT1_DWEN)
13409 
13410 #define S_RADM_TRGT1_FMT    14
13411 #define M_RADM_TRGT1_FMT    0x3U
13412 #define V_RADM_TRGT1_FMT(x) ((x) << S_RADM_TRGT1_FMT)
13413 #define G_RADM_TRGT1_FMT(x) (((x) >> S_RADM_TRGT1_FMT) & M_RADM_TRGT1_FMT)
13414 
13415 #define S_RADM_TRGT1_TYPE    9
13416 #define M_RADM_TRGT1_TYPE    0x1fU
13417 #define V_RADM_TRGT1_TYPE(x) ((x) << S_RADM_TRGT1_TYPE)
13418 #define G_RADM_TRGT1_TYPE(x) (((x) >> S_RADM_TRGT1_TYPE) & M_RADM_TRGT1_TYPE)
13419 
13420 #define S_RADM_TRGT1_IN_MEMBAR_RANGE    6
13421 #define M_RADM_TRGT1_IN_MEMBAR_RANGE    0x7U
13422 #define V_RADM_TRGT1_IN_MEMBAR_RANGE(x) ((x) << S_RADM_TRGT1_IN_MEMBAR_RANGE)
13423 #define G_RADM_TRGT1_IN_MEMBAR_RANGE(x) (((x) >> S_RADM_TRGT1_IN_MEMBAR_RANGE) & M_RADM_TRGT1_IN_MEMBAR_RANGE)
13424 
13425 #define S_RADM_TRGT1_ECRC_ERR    5
13426 #define V_RADM_TRGT1_ECRC_ERR(x) ((x) << S_RADM_TRGT1_ECRC_ERR)
13427 #define F_RADM_TRGT1_ECRC_ERR    V_RADM_TRGT1_ECRC_ERR(1U)
13428 
13429 #define S_RADM_TRGT1_DLLP_ABORT    4
13430 #define V_RADM_TRGT1_DLLP_ABORT(x) ((x) << S_RADM_TRGT1_DLLP_ABORT)
13431 #define F_RADM_TRGT1_DLLP_ABORT    V_RADM_TRGT1_DLLP_ABORT(1U)
13432 
13433 #define S_RADM_TRGT1_TLP_ABORT    3
13434 #define V_RADM_TRGT1_TLP_ABORT(x) ((x) << S_RADM_TRGT1_TLP_ABORT)
13435 #define F_RADM_TRGT1_TLP_ABORT    V_RADM_TRGT1_TLP_ABORT(1U)
13436 
13437 #define S_RADM_TRGT1_EOT    2
13438 #define V_RADM_TRGT1_EOT(x) ((x) << S_RADM_TRGT1_EOT)
13439 #define F_RADM_TRGT1_EOT    V_RADM_TRGT1_EOT(1U)
13440 
13441 #define S_RADM_TRGT1_DV_2B    1
13442 #define V_RADM_TRGT1_DV_2B(x) ((x) << S_RADM_TRGT1_DV_2B)
13443 #define F_RADM_TRGT1_DV_2B    V_RADM_TRGT1_DV_2B(1U)
13444 
13445 #define S_RADM_TRGT1_HV_2B    0
13446 #define V_RADM_TRGT1_HV_2B(x) ((x) << S_RADM_TRGT1_HV_2B)
13447 #define F_RADM_TRGT1_HV_2B    V_RADM_TRGT1_HV_2B(1U)
13448 
13449 #define A_PCIE_PDEBUG_REG_0X2C 0x2c
13450 
13451 #define S_STATEMPIO    29
13452 #define M_STATEMPIO    0x7U
13453 #define V_STATEMPIO(x) ((x) << S_STATEMPIO)
13454 #define G_STATEMPIO(x) (((x) >> S_STATEMPIO) & M_STATEMPIO)
13455 
13456 #define S_STATECPL    25
13457 #define M_STATECPL    0xfU
13458 #define V_STATECPL(x) ((x) << S_STATECPL)
13459 #define G_STATECPL(x) (((x) >> S_STATECPL) & M_STATECPL)
13460 
13461 #define S_STATEALIN    22
13462 #define M_STATEALIN    0x7U
13463 #define V_STATEALIN(x) ((x) << S_STATEALIN)
13464 #define G_STATEALIN(x) (((x) >> S_STATEALIN) & M_STATEALIN)
13465 
13466 #define S_STATEPL    19
13467 #define M_STATEPL    0x7U
13468 #define V_STATEPL(x) ((x) << S_STATEPL)
13469 #define G_STATEPL(x) (((x) >> S_STATEPL) & M_STATEPL)
13470 
13471 #define S_STATEMARSP    18
13472 #define V_STATEMARSP(x) ((x) << S_STATEMARSP)
13473 #define F_STATEMARSP    V_STATEMARSP(1U)
13474 
13475 #define S_MA_TAGSINUSE    11
13476 #define M_MA_TAGSINUSE    0x7fU
13477 #define V_MA_TAGSINUSE(x) ((x) << S_MA_TAGSINUSE)
13478 #define G_MA_TAGSINUSE(x) (((x) >> S_MA_TAGSINUSE) & M_MA_TAGSINUSE)
13479 
13480 #define S_RADM_TRGT1_HSRDY    10
13481 #define V_RADM_TRGT1_HSRDY(x) ((x) << S_RADM_TRGT1_HSRDY)
13482 #define F_RADM_TRGT1_HSRDY    V_RADM_TRGT1_HSRDY(1U)
13483 
13484 #define S_RADM_TRGT1_DSRDY    9
13485 #define V_RADM_TRGT1_DSRDY(x) ((x) << S_RADM_TRGT1_DSRDY)
13486 #define F_RADM_TRGT1_DSRDY    V_RADM_TRGT1_DSRDY(1U)
13487 
13488 #define S_ALIND_REQWRDATAVLD    8
13489 #define V_ALIND_REQWRDATAVLD(x) ((x) << S_ALIND_REQWRDATAVLD)
13490 #define F_ALIND_REQWRDATAVLD    V_ALIND_REQWRDATAVLD(1U)
13491 
13492 #define S_FID_LKUPWRHDRVLD    7
13493 #define V_FID_LKUPWRHDRVLD(x) ((x) << S_FID_LKUPWRHDRVLD)
13494 #define F_FID_LKUPWRHDRVLD    V_FID_LKUPWRHDRVLD(1U)
13495 
13496 #define S_MPIO_WRVLD    6
13497 #define V_MPIO_WRVLD(x) ((x) << S_MPIO_WRVLD)
13498 #define F_MPIO_WRVLD    V_MPIO_WRVLD(1U)
13499 
13500 #define S_TRGT1_RADM_HALT    5
13501 #define V_TRGT1_RADM_HALT(x) ((x) << S_TRGT1_RADM_HALT)
13502 #define F_TRGT1_RADM_HALT    V_TRGT1_RADM_HALT(1U)
13503 
13504 #define S_RADM_TRGT1_DV_2C    4
13505 #define V_RADM_TRGT1_DV_2C(x) ((x) << S_RADM_TRGT1_DV_2C)
13506 #define F_RADM_TRGT1_DV_2C    V_RADM_TRGT1_DV_2C(1U)
13507 
13508 #define S_RADM_TRGT1_DV_2C_2    3
13509 #define V_RADM_TRGT1_DV_2C_2(x) ((x) << S_RADM_TRGT1_DV_2C_2)
13510 #define F_RADM_TRGT1_DV_2C_2    V_RADM_TRGT1_DV_2C_2(1U)
13511 
13512 #define S_RADM_TRGT1_TLP_ABORT_2C    2
13513 #define V_RADM_TRGT1_TLP_ABORT_2C(x) ((x) << S_RADM_TRGT1_TLP_ABORT_2C)
13514 #define F_RADM_TRGT1_TLP_ABORT_2C    V_RADM_TRGT1_TLP_ABORT_2C(1U)
13515 
13516 #define S_RADM_TRGT1_DLLP_ABORT_2C    1
13517 #define V_RADM_TRGT1_DLLP_ABORT_2C(x) ((x) << S_RADM_TRGT1_DLLP_ABORT_2C)
13518 #define F_RADM_TRGT1_DLLP_ABORT_2C    V_RADM_TRGT1_DLLP_ABORT_2C(1U)
13519 
13520 #define S_RADM_TRGT1_ECRC_ERR_2C    0
13521 #define V_RADM_TRGT1_ECRC_ERR_2C(x) ((x) << S_RADM_TRGT1_ECRC_ERR_2C)
13522 #define F_RADM_TRGT1_ECRC_ERR_2C    V_RADM_TRGT1_ECRC_ERR_2C(1U)
13523 
13524 #define A_PCIE_PDEBUG_REG_0X2D 0x2d
13525 
13526 #define S_RADM_TRGT1_HV_2D    31
13527 #define V_RADM_TRGT1_HV_2D(x) ((x) << S_RADM_TRGT1_HV_2D)
13528 #define F_RADM_TRGT1_HV_2D    V_RADM_TRGT1_HV_2D(1U)
13529 
13530 #define S_RADM_TRGT1_DV_2D    30
13531 #define V_RADM_TRGT1_DV_2D(x) ((x) << S_RADM_TRGT1_DV_2D)
13532 #define F_RADM_TRGT1_DV_2D    V_RADM_TRGT1_DV_2D(1U)
13533 
13534 #define S_RADM_TRGT1_HV2    23
13535 #define M_RADM_TRGT1_HV2    0x7fU
13536 #define V_RADM_TRGT1_HV2(x) ((x) << S_RADM_TRGT1_HV2)
13537 #define G_RADM_TRGT1_HV2(x) (((x) >> S_RADM_TRGT1_HV2) & M_RADM_TRGT1_HV2)
13538 
13539 #define S_RADM_TRGT1_HV3    20
13540 #define M_RADM_TRGT1_HV3    0x7U
13541 #define V_RADM_TRGT1_HV3(x) ((x) << S_RADM_TRGT1_HV3)
13542 #define G_RADM_TRGT1_HV3(x) (((x) >> S_RADM_TRGT1_HV3) & M_RADM_TRGT1_HV3)
13543 
13544 #define S_RADM_TRGT1_HV4    16
13545 #define M_RADM_TRGT1_HV4    0xfU
13546 #define V_RADM_TRGT1_HV4(x) ((x) << S_RADM_TRGT1_HV4)
13547 #define G_RADM_TRGT1_HV4(x) (((x) >> S_RADM_TRGT1_HV4) & M_RADM_TRGT1_HV4)
13548 
13549 #define S_RADM_TRGT1_HV5    12
13550 #define M_RADM_TRGT1_HV5    0xfU
13551 #define V_RADM_TRGT1_HV5(x) ((x) << S_RADM_TRGT1_HV5)
13552 #define G_RADM_TRGT1_HV5(x) (((x) >> S_RADM_TRGT1_HV5) & M_RADM_TRGT1_HV5)
13553 
13554 #define S_RADM_TRGT1_HV6    11
13555 #define V_RADM_TRGT1_HV6(x) ((x) << S_RADM_TRGT1_HV6)
13556 #define F_RADM_TRGT1_HV6    V_RADM_TRGT1_HV6(1U)
13557 
13558 #define S_RADM_TRGT1_HV7    10
13559 #define V_RADM_TRGT1_HV7(x) ((x) << S_RADM_TRGT1_HV7)
13560 #define F_RADM_TRGT1_HV7    V_RADM_TRGT1_HV7(1U)
13561 
13562 #define S_RADM_TRGT1_HV8    7
13563 #define M_RADM_TRGT1_HV8    0x7U
13564 #define V_RADM_TRGT1_HV8(x) ((x) << S_RADM_TRGT1_HV8)
13565 #define G_RADM_TRGT1_HV8(x) (((x) >> S_RADM_TRGT1_HV8) & M_RADM_TRGT1_HV8)
13566 
13567 #define S_RADM_TRGT1_HV9    6
13568 #define V_RADM_TRGT1_HV9(x) ((x) << S_RADM_TRGT1_HV9)
13569 #define F_RADM_TRGT1_HV9    V_RADM_TRGT1_HV9(1U)
13570 
13571 #define S_RADM_TRGT1_HVA    5
13572 #define V_RADM_TRGT1_HVA(x) ((x) << S_RADM_TRGT1_HVA)
13573 #define F_RADM_TRGT1_HVA    V_RADM_TRGT1_HVA(1U)
13574 
13575 #define S_RADM_TRGT1_DSRDY_2D    4
13576 #define V_RADM_TRGT1_DSRDY_2D(x) ((x) << S_RADM_TRGT1_DSRDY_2D)
13577 #define F_RADM_TRGT1_DSRDY_2D    V_RADM_TRGT1_DSRDY_2D(1U)
13578 
13579 #define S_RADM_TRGT1_WRCNT    0
13580 #define M_RADM_TRGT1_WRCNT    0xfU
13581 #define V_RADM_TRGT1_WRCNT(x) ((x) << S_RADM_TRGT1_WRCNT)
13582 #define G_RADM_TRGT1_WRCNT(x) (((x) >> S_RADM_TRGT1_WRCNT) & M_RADM_TRGT1_WRCNT)
13583 
13584 #define A_PCIE_PDEBUG_REG_0X2E 0x2e
13585 
13586 #define S_RADM_TRGT1_HV_2E    30
13587 #define M_RADM_TRGT1_HV_2E    0x3U
13588 #define V_RADM_TRGT1_HV_2E(x) ((x) << S_RADM_TRGT1_HV_2E)
13589 #define G_RADM_TRGT1_HV_2E(x) (((x) >> S_RADM_TRGT1_HV_2E) & M_RADM_TRGT1_HV_2E)
13590 
13591 #define S_RADM_TRGT1_HV_2E_2    20
13592 #define M_RADM_TRGT1_HV_2E_2    0x3ffU
13593 #define V_RADM_TRGT1_HV_2E_2(x) ((x) << S_RADM_TRGT1_HV_2E_2)
13594 #define G_RADM_TRGT1_HV_2E_2(x) (((x) >> S_RADM_TRGT1_HV_2E_2) & M_RADM_TRGT1_HV_2E_2)
13595 
13596 #define S_RADM_TRGT1_HV_WE_3    12
13597 #define M_RADM_TRGT1_HV_WE_3    0xffU
13598 #define V_RADM_TRGT1_HV_WE_3(x) ((x) << S_RADM_TRGT1_HV_WE_3)
13599 #define G_RADM_TRGT1_HV_WE_3(x) (((x) >> S_RADM_TRGT1_HV_WE_3) & M_RADM_TRGT1_HV_WE_3)
13600 
13601 #define S_ALIN_REQDATAVLD4    8
13602 #define M_ALIN_REQDATAVLD4    0xfU
13603 #define V_ALIN_REQDATAVLD4(x) ((x) << S_ALIN_REQDATAVLD4)
13604 #define G_ALIN_REQDATAVLD4(x) (((x) >> S_ALIN_REQDATAVLD4) & M_ALIN_REQDATAVLD4)
13605 
13606 #define S_ALIN_REQDATAVLD5    7
13607 #define V_ALIN_REQDATAVLD5(x) ((x) << S_ALIN_REQDATAVLD5)
13608 #define F_ALIN_REQDATAVLD5    V_ALIN_REQDATAVLD5(1U)
13609 
13610 #define S_ALIN_REQDATAVLD6    6
13611 #define V_ALIN_REQDATAVLD6(x) ((x) << S_ALIN_REQDATAVLD6)
13612 #define F_ALIN_REQDATAVLD6    V_ALIN_REQDATAVLD6(1U)
13613 
13614 #define S_ALIN_REQDATAVLD7    4
13615 #define M_ALIN_REQDATAVLD7    0x3U
13616 #define V_ALIN_REQDATAVLD7(x) ((x) << S_ALIN_REQDATAVLD7)
13617 #define G_ALIN_REQDATAVLD7(x) (((x) >> S_ALIN_REQDATAVLD7) & M_ALIN_REQDATAVLD7)
13618 
13619 #define S_ALIN_REQDATAVLD8    3
13620 #define V_ALIN_REQDATAVLD8(x) ((x) << S_ALIN_REQDATAVLD8)
13621 #define F_ALIN_REQDATAVLD8    V_ALIN_REQDATAVLD8(1U)
13622 
13623 #define S_ALIN_REQDATAVLD9    2
13624 #define V_ALIN_REQDATAVLD9(x) ((x) << S_ALIN_REQDATAVLD9)
13625 #define F_ALIN_REQDATAVLD9    V_ALIN_REQDATAVLD9(1U)
13626 
13627 #define S_ALIN_REQDATARDY    1
13628 #define V_ALIN_REQDATARDY(x) ((x) << S_ALIN_REQDATARDY)
13629 #define F_ALIN_REQDATARDY    V_ALIN_REQDATARDY(1U)
13630 
13631 #define S_ALIN_REQDATAVLDA    0
13632 #define V_ALIN_REQDATAVLDA(x) ((x) << S_ALIN_REQDATAVLDA)
13633 #define F_ALIN_REQDATAVLDA    V_ALIN_REQDATAVLDA(1U)
13634 
13635 #define A_PCIE_PDEBUG_REG_0X2F 0x2f
13636 #define A_PCIE_PDEBUG_REG_0X30 0x30
13637 
13638 #define S_RADM_TRGT1_HV_30    25
13639 #define M_RADM_TRGT1_HV_30    0x7fU
13640 #define V_RADM_TRGT1_HV_30(x) ((x) << S_RADM_TRGT1_HV_30)
13641 #define G_RADM_TRGT1_HV_30(x) (((x) >> S_RADM_TRGT1_HV_30) & M_RADM_TRGT1_HV_30)
13642 
13643 #define S_PIO_WRCNT    15
13644 #define M_PIO_WRCNT    0x3ffU
13645 #define V_PIO_WRCNT(x) ((x) << S_PIO_WRCNT)
13646 #define G_PIO_WRCNT(x) (((x) >> S_PIO_WRCNT) & M_PIO_WRCNT)
13647 
13648 #define S_ALIND_REQWRCNT    12
13649 #define M_ALIND_REQWRCNT    0x7U
13650 #define V_ALIND_REQWRCNT(x) ((x) << S_ALIND_REQWRCNT)
13651 #define G_ALIND_REQWRCNT(x) (((x) >> S_ALIND_REQWRCNT) & M_ALIND_REQWRCNT)
13652 
13653 #define S_FID_LKUPWRCNT    9
13654 #define M_FID_LKUPWRCNT    0x7U
13655 #define V_FID_LKUPWRCNT(x) ((x) << S_FID_LKUPWRCNT)
13656 #define G_FID_LKUPWRCNT(x) (((x) >> S_FID_LKUPWRCNT) & M_FID_LKUPWRCNT)
13657 
13658 #define S_ALIND_REQRDDATAVLD    8
13659 #define V_ALIND_REQRDDATAVLD(x) ((x) << S_ALIND_REQRDDATAVLD)
13660 #define F_ALIND_REQRDDATAVLD    V_ALIND_REQRDDATAVLD(1U)
13661 
13662 #define S_ALIND_REQRDDATARDY    7
13663 #define V_ALIND_REQRDDATARDY(x) ((x) << S_ALIND_REQRDDATARDY)
13664 #define F_ALIND_REQRDDATARDY    V_ALIND_REQRDDATARDY(1U)
13665 
13666 #define S_ALIND_REQRDDATAVLD2    6
13667 #define V_ALIND_REQRDDATAVLD2(x) ((x) << S_ALIND_REQRDDATAVLD2)
13668 #define F_ALIND_REQRDDATAVLD2    V_ALIND_REQRDDATAVLD2(1U)
13669 
13670 #define S_ALIND_REQWRDATAVLD3    3
13671 #define M_ALIND_REQWRDATAVLD3    0x7U
13672 #define V_ALIND_REQWRDATAVLD3(x) ((x) << S_ALIND_REQWRDATAVLD3)
13673 #define G_ALIND_REQWRDATAVLD3(x) (((x) >> S_ALIND_REQWRDATAVLD3) & M_ALIND_REQWRDATAVLD3)
13674 
13675 #define S_ALIND_REQWRDATAVLD4    2
13676 #define V_ALIND_REQWRDATAVLD4(x) ((x) << S_ALIND_REQWRDATAVLD4)
13677 #define F_ALIND_REQWRDATAVLD4    V_ALIND_REQWRDATAVLD4(1U)
13678 
13679 #define S_ALIND_REQWRDATARDYOPEN    1
13680 #define V_ALIND_REQWRDATARDYOPEN(x) ((x) << S_ALIND_REQWRDATARDYOPEN)
13681 #define F_ALIND_REQWRDATARDYOPEN    V_ALIND_REQWRDATARDYOPEN(1U)
13682 
13683 #define S_ALIND_REQWRDATAVLD5    0
13684 #define V_ALIND_REQWRDATAVLD5(x) ((x) << S_ALIND_REQWRDATAVLD5)
13685 #define F_ALIND_REQWRDATAVLD5    V_ALIND_REQWRDATAVLD5(1U)
13686 
13687 #define A_PCIE_PDEBUG_REG_0X31 0x31
13688 #define A_PCIE_PDEBUG_REG_0X32 0x32
13689 #define A_PCIE_PDEBUG_REG_0X33 0x33
13690 #define A_PCIE_PDEBUG_REG_0X34 0x34
13691 #define A_PCIE_PDEBUG_REG_0X35 0x35
13692 
13693 #define S_T5_MPIO_WRVLD    19
13694 #define M_T5_MPIO_WRVLD    0x1fffU
13695 #define V_T5_MPIO_WRVLD(x) ((x) << S_T5_MPIO_WRVLD)
13696 #define G_T5_MPIO_WRVLD(x) (((x) >> S_T5_MPIO_WRVLD) & M_T5_MPIO_WRVLD)
13697 
13698 #define S_FID_LKUPRDHDRVLD    18
13699 #define V_FID_LKUPRDHDRVLD(x) ((x) << S_FID_LKUPRDHDRVLD)
13700 #define F_FID_LKUPRDHDRVLD    V_FID_LKUPRDHDRVLD(1U)
13701 
13702 #define S_FID_LKUPRDHDRVLD2    17
13703 #define V_FID_LKUPRDHDRVLD2(x) ((x) << S_FID_LKUPRDHDRVLD2)
13704 #define F_FID_LKUPRDHDRVLD2    V_FID_LKUPRDHDRVLD2(1U)
13705 
13706 #define S_FID_LKUPRDHDRVLD3    16
13707 #define V_FID_LKUPRDHDRVLD3(x) ((x) << S_FID_LKUPRDHDRVLD3)
13708 #define F_FID_LKUPRDHDRVLD3    V_FID_LKUPRDHDRVLD3(1U)
13709 
13710 #define S_FID_LKUPRDHDRVLD4    15
13711 #define V_FID_LKUPRDHDRVLD4(x) ((x) << S_FID_LKUPRDHDRVLD4)
13712 #define F_FID_LKUPRDHDRVLD4    V_FID_LKUPRDHDRVLD4(1U)
13713 
13714 #define S_FID_LKUPRDHDRVLD5    14
13715 #define V_FID_LKUPRDHDRVLD5(x) ((x) << S_FID_LKUPRDHDRVLD5)
13716 #define F_FID_LKUPRDHDRVLD5    V_FID_LKUPRDHDRVLD5(1U)
13717 
13718 #define S_FID_LKUPRDHDRVLD6    13
13719 #define V_FID_LKUPRDHDRVLD6(x) ((x) << S_FID_LKUPRDHDRVLD6)
13720 #define F_FID_LKUPRDHDRVLD6    V_FID_LKUPRDHDRVLD6(1U)
13721 
13722 #define S_FID_LKUPRDHDRVLD7    12
13723 #define V_FID_LKUPRDHDRVLD7(x) ((x) << S_FID_LKUPRDHDRVLD7)
13724 #define F_FID_LKUPRDHDRVLD7    V_FID_LKUPRDHDRVLD7(1U)
13725 
13726 #define S_FID_LKUPRDHDRVLD8    11
13727 #define V_FID_LKUPRDHDRVLD8(x) ((x) << S_FID_LKUPRDHDRVLD8)
13728 #define F_FID_LKUPRDHDRVLD8    V_FID_LKUPRDHDRVLD8(1U)
13729 
13730 #define S_FID_LKUPRDHDRVLD9    10
13731 #define V_FID_LKUPRDHDRVLD9(x) ((x) << S_FID_LKUPRDHDRVLD9)
13732 #define F_FID_LKUPRDHDRVLD9    V_FID_LKUPRDHDRVLD9(1U)
13733 
13734 #define S_FID_LKUPRDHDRVLDA    9
13735 #define V_FID_LKUPRDHDRVLDA(x) ((x) << S_FID_LKUPRDHDRVLDA)
13736 #define F_FID_LKUPRDHDRVLDA    V_FID_LKUPRDHDRVLDA(1U)
13737 
13738 #define S_FID_LKUPRDHDRVLDB    8
13739 #define V_FID_LKUPRDHDRVLDB(x) ((x) << S_FID_LKUPRDHDRVLDB)
13740 #define F_FID_LKUPRDHDRVLDB    V_FID_LKUPRDHDRVLDB(1U)
13741 
13742 #define S_FID_LKUPRDHDRVLDC    7
13743 #define V_FID_LKUPRDHDRVLDC(x) ((x) << S_FID_LKUPRDHDRVLDC)
13744 #define F_FID_LKUPRDHDRVLDC    V_FID_LKUPRDHDRVLDC(1U)
13745 
13746 #define S_MPIO_WRVLD1    6
13747 #define V_MPIO_WRVLD1(x) ((x) << S_MPIO_WRVLD1)
13748 #define F_MPIO_WRVLD1    V_MPIO_WRVLD1(1U)
13749 
13750 #define S_MPIO_WRVLD2    5
13751 #define V_MPIO_WRVLD2(x) ((x) << S_MPIO_WRVLD2)
13752 #define F_MPIO_WRVLD2    V_MPIO_WRVLD2(1U)
13753 
13754 #define S_MPIO_WRVLD3    4
13755 #define V_MPIO_WRVLD3(x) ((x) << S_MPIO_WRVLD3)
13756 #define F_MPIO_WRVLD3    V_MPIO_WRVLD3(1U)
13757 
13758 #define S_MPIO_WRVLD4    0
13759 #define M_MPIO_WRVLD4    0xfU
13760 #define V_MPIO_WRVLD4(x) ((x) << S_MPIO_WRVLD4)
13761 #define G_MPIO_WRVLD4(x) (((x) >> S_MPIO_WRVLD4) & M_MPIO_WRVLD4)
13762 
13763 #define A_PCIE_PDEBUG_REG_0X36 0x36
13764 #define A_PCIE_PDEBUG_REG_0X37 0x37
13765 #define A_PCIE_PDEBUG_REG_0X38 0x38
13766 #define A_PCIE_PDEBUG_REG_0X39 0x39
13767 #define A_PCIE_PDEBUG_REG_0X3A 0x3a
13768 
13769 #define S_CLIENT0_TLP_VFUNC_ACTIVE    31
13770 #define V_CLIENT0_TLP_VFUNC_ACTIVE(x) ((x) << S_CLIENT0_TLP_VFUNC_ACTIVE)
13771 #define F_CLIENT0_TLP_VFUNC_ACTIVE    V_CLIENT0_TLP_VFUNC_ACTIVE(1U)
13772 
13773 #define S_CLIENT0_TLP_VFUNC_NUM    24
13774 #define M_CLIENT0_TLP_VFUNC_NUM    0x7fU
13775 #define V_CLIENT0_TLP_VFUNC_NUM(x) ((x) << S_CLIENT0_TLP_VFUNC_NUM)
13776 #define G_CLIENT0_TLP_VFUNC_NUM(x) (((x) >> S_CLIENT0_TLP_VFUNC_NUM) & M_CLIENT0_TLP_VFUNC_NUM)
13777 
13778 #define S_CLIENT0_TLP_FUNC_NUM    21
13779 #define M_CLIENT0_TLP_FUNC_NUM    0x7U
13780 #define V_CLIENT0_TLP_FUNC_NUM(x) ((x) << S_CLIENT0_TLP_FUNC_NUM)
13781 #define G_CLIENT0_TLP_FUNC_NUM(x) (((x) >> S_CLIENT0_TLP_FUNC_NUM) & M_CLIENT0_TLP_FUNC_NUM)
13782 
13783 #define S_CLIENT0_TLP_BYTE_EN    13
13784 #define M_CLIENT0_TLP_BYTE_EN    0xffU
13785 #define V_CLIENT0_TLP_BYTE_EN(x) ((x) << S_CLIENT0_TLP_BYTE_EN)
13786 #define G_CLIENT0_TLP_BYTE_EN(x) (((x) >> S_CLIENT0_TLP_BYTE_EN) & M_CLIENT0_TLP_BYTE_EN)
13787 
13788 #define S_CLIENT0_TLP_BYTE_LEN    0
13789 #define M_CLIENT0_TLP_BYTE_LEN    0x1fffU
13790 #define V_CLIENT0_TLP_BYTE_LEN(x) ((x) << S_CLIENT0_TLP_BYTE_LEN)
13791 #define G_CLIENT0_TLP_BYTE_LEN(x) (((x) >> S_CLIENT0_TLP_BYTE_LEN) & M_CLIENT0_TLP_BYTE_LEN)
13792 
13793 #define A_PCIE_PDEBUG_REG_0X3B 0x3b
13794 
13795 #define S_XADM_CLIENT0_HALT    31
13796 #define V_XADM_CLIENT0_HALT(x) ((x) << S_XADM_CLIENT0_HALT)
13797 #define F_XADM_CLIENT0_HALT    V_XADM_CLIENT0_HALT(1U)
13798 
13799 #define S_CLIENT0_TLP_DV    30
13800 #define V_CLIENT0_TLP_DV(x) ((x) << S_CLIENT0_TLP_DV)
13801 #define F_CLIENT0_TLP_DV    V_CLIENT0_TLP_DV(1U)
13802 
13803 #define S_CLIENT0_ADDR_ALIGN_EN    29
13804 #define V_CLIENT0_ADDR_ALIGN_EN(x) ((x) << S_CLIENT0_ADDR_ALIGN_EN)
13805 #define F_CLIENT0_ADDR_ALIGN_EN    V_CLIENT0_ADDR_ALIGN_EN(1U)
13806 
13807 #define S_CLIENT0_CPL_BCM    28
13808 #define V_CLIENT0_CPL_BCM(x) ((x) << S_CLIENT0_CPL_BCM)
13809 #define F_CLIENT0_CPL_BCM    V_CLIENT0_CPL_BCM(1U)
13810 
13811 #define S_CLIENT0_TLP_EP    27
13812 #define V_CLIENT0_TLP_EP(x) ((x) << S_CLIENT0_TLP_EP)
13813 #define F_CLIENT0_TLP_EP    V_CLIENT0_TLP_EP(1U)
13814 
13815 #define S_CLIENT0_CPL_STATUS    24
13816 #define M_CLIENT0_CPL_STATUS    0x7U
13817 #define V_CLIENT0_CPL_STATUS(x) ((x) << S_CLIENT0_CPL_STATUS)
13818 #define G_CLIENT0_CPL_STATUS(x) (((x) >> S_CLIENT0_CPL_STATUS) & M_CLIENT0_CPL_STATUS)
13819 
13820 #define S_CLIENT0_TLP_TD    23
13821 #define V_CLIENT0_TLP_TD(x) ((x) << S_CLIENT0_TLP_TD)
13822 #define F_CLIENT0_TLP_TD    V_CLIENT0_TLP_TD(1U)
13823 
13824 #define S_CLIENT0_TLP_TYPE    18
13825 #define M_CLIENT0_TLP_TYPE    0x1fU
13826 #define V_CLIENT0_TLP_TYPE(x) ((x) << S_CLIENT0_TLP_TYPE)
13827 #define G_CLIENT0_TLP_TYPE(x) (((x) >> S_CLIENT0_TLP_TYPE) & M_CLIENT0_TLP_TYPE)
13828 
13829 #define S_CLIENT0_TLP_FMT    16
13830 #define M_CLIENT0_TLP_FMT    0x3U
13831 #define V_CLIENT0_TLP_FMT(x) ((x) << S_CLIENT0_TLP_FMT)
13832 #define G_CLIENT0_TLP_FMT(x) (((x) >> S_CLIENT0_TLP_FMT) & M_CLIENT0_TLP_FMT)
13833 
13834 #define S_CLIENT0_TLP_BAD_EOT    15
13835 #define V_CLIENT0_TLP_BAD_EOT(x) ((x) << S_CLIENT0_TLP_BAD_EOT)
13836 #define F_CLIENT0_TLP_BAD_EOT    V_CLIENT0_TLP_BAD_EOT(1U)
13837 
13838 #define S_CLIENT0_TLP_EOT    14
13839 #define V_CLIENT0_TLP_EOT(x) ((x) << S_CLIENT0_TLP_EOT)
13840 #define F_CLIENT0_TLP_EOT    V_CLIENT0_TLP_EOT(1U)
13841 
13842 #define S_CLIENT0_TLP_ATTR    11
13843 #define M_CLIENT0_TLP_ATTR    0x7U
13844 #define V_CLIENT0_TLP_ATTR(x) ((x) << S_CLIENT0_TLP_ATTR)
13845 #define G_CLIENT0_TLP_ATTR(x) (((x) >> S_CLIENT0_TLP_ATTR) & M_CLIENT0_TLP_ATTR)
13846 
13847 #define S_CLIENT0_TLP_TC    8
13848 #define M_CLIENT0_TLP_TC    0x7U
13849 #define V_CLIENT0_TLP_TC(x) ((x) << S_CLIENT0_TLP_TC)
13850 #define G_CLIENT0_TLP_TC(x) (((x) >> S_CLIENT0_TLP_TC) & M_CLIENT0_TLP_TC)
13851 
13852 #define S_CLIENT0_TLP_TID    0
13853 #define M_CLIENT0_TLP_TID    0xffU
13854 #define V_CLIENT0_TLP_TID(x) ((x) << S_CLIENT0_TLP_TID)
13855 #define G_CLIENT0_TLP_TID(x) (((x) >> S_CLIENT0_TLP_TID) & M_CLIENT0_TLP_TID)
13856 
13857 #define A_PCIE_PDEBUG_REG_0X3C 0x3c
13858 
13859 #define S_MEM_RSPRRAVLD    31
13860 #define V_MEM_RSPRRAVLD(x) ((x) << S_MEM_RSPRRAVLD)
13861 #define F_MEM_RSPRRAVLD    V_MEM_RSPRRAVLD(1U)
13862 
13863 #define S_MEM_RSPRRARDY    30
13864 #define V_MEM_RSPRRARDY(x) ((x) << S_MEM_RSPRRARDY)
13865 #define F_MEM_RSPRRARDY    V_MEM_RSPRRARDY(1U)
13866 
13867 #define S_PIO_RSPRRAVLD    29
13868 #define V_PIO_RSPRRAVLD(x) ((x) << S_PIO_RSPRRAVLD)
13869 #define F_PIO_RSPRRAVLD    V_PIO_RSPRRAVLD(1U)
13870 
13871 #define S_PIO_RSPRRARDY    28
13872 #define V_PIO_RSPRRARDY(x) ((x) << S_PIO_RSPRRARDY)
13873 #define F_PIO_RSPRRARDY    V_PIO_RSPRRARDY(1U)
13874 
13875 #define S_MEM_RSPRDVLD    27
13876 #define V_MEM_RSPRDVLD(x) ((x) << S_MEM_RSPRDVLD)
13877 #define F_MEM_RSPRDVLD    V_MEM_RSPRDVLD(1U)
13878 
13879 #define S_MEM_RSPRDRRARDY    26
13880 #define V_MEM_RSPRDRRARDY(x) ((x) << S_MEM_RSPRDRRARDY)
13881 #define F_MEM_RSPRDRRARDY    V_MEM_RSPRDRRARDY(1U)
13882 
13883 #define S_PIO_RSPRDVLD    25
13884 #define V_PIO_RSPRDVLD(x) ((x) << S_PIO_RSPRDVLD)
13885 #define F_PIO_RSPRDVLD    V_PIO_RSPRDVLD(1U)
13886 
13887 #define S_PIO_RSPRDRRARDY    24
13888 #define V_PIO_RSPRDRRARDY(x) ((x) << S_PIO_RSPRDRRARDY)
13889 #define F_PIO_RSPRDRRARDY    V_PIO_RSPRDRRARDY(1U)
13890 
13891 #define S_TGT_TAGQ_RDVLD    16
13892 #define M_TGT_TAGQ_RDVLD    0xffU
13893 #define V_TGT_TAGQ_RDVLD(x) ((x) << S_TGT_TAGQ_RDVLD)
13894 #define G_TGT_TAGQ_RDVLD(x) (((x) >> S_TGT_TAGQ_RDVLD) & M_TGT_TAGQ_RDVLD)
13895 
13896 #define S_CPLTXNDISABLE    8
13897 #define M_CPLTXNDISABLE    0xffU
13898 #define V_CPLTXNDISABLE(x) ((x) << S_CPLTXNDISABLE)
13899 #define G_CPLTXNDISABLE(x) (((x) >> S_CPLTXNDISABLE) & M_CPLTXNDISABLE)
13900 
13901 #define S_CPLTXNDISABLE2    7
13902 #define V_CPLTXNDISABLE2(x) ((x) << S_CPLTXNDISABLE2)
13903 #define F_CPLTXNDISABLE2    V_CPLTXNDISABLE2(1U)
13904 
13905 #define S_CLIENT0_TLP_HV    0
13906 #define M_CLIENT0_TLP_HV    0x7fU
13907 #define V_CLIENT0_TLP_HV(x) ((x) << S_CLIENT0_TLP_HV)
13908 #define G_CLIENT0_TLP_HV(x) (((x) >> S_CLIENT0_TLP_HV) & M_CLIENT0_TLP_HV)
13909 
13910 #define A_PCIE_PDEBUG_REG_0X3D 0x3d
13911 #define A_PCIE_PDEBUG_REG_0X3E 0x3e
13912 #define A_PCIE_PDEBUG_REG_0X3F 0x3f
13913 #define A_PCIE_PDEBUG_REG_0X40 0x40
13914 #define A_PCIE_PDEBUG_REG_0X41 0x41
13915 #define A_PCIE_PDEBUG_REG_0X42 0x42
13916 #define A_PCIE_PDEBUG_REG_0X43 0x43
13917 #define A_PCIE_PDEBUG_REG_0X44 0x44
13918 #define A_PCIE_PDEBUG_REG_0X45 0x45
13919 #define A_PCIE_PDEBUG_REG_0X46 0x46
13920 #define A_PCIE_PDEBUG_REG_0X47 0x47
13921 #define A_PCIE_PDEBUG_REG_0X48 0x48
13922 #define A_PCIE_PDEBUG_REG_0X49 0x49
13923 #define A_PCIE_PDEBUG_REG_0X4A 0x4a
13924 #define A_PCIE_PDEBUG_REG_0X4B 0x4b
13925 #define A_PCIE_PDEBUG_REG_0X4C 0x4c
13926 #define A_PCIE_PDEBUG_REG_0X4D 0x4d
13927 #define A_PCIE_PDEBUG_REG_0X4E 0x4e
13928 #define A_PCIE_PDEBUG_REG_0X4F 0x4f
13929 #define A_PCIE_PDEBUG_REG_0X50 0x50
13930 #define A_PCIE_CDEBUG_REG_0X0 0x0
13931 #define A_PCIE_CDEBUG_REG_0X1 0x1
13932 #define A_PCIE_CDEBUG_REG_0X2 0x2
13933 
13934 #define S_FLR_REQVLD    31
13935 #define V_FLR_REQVLD(x) ((x) << S_FLR_REQVLD)
13936 #define F_FLR_REQVLD    V_FLR_REQVLD(1U)
13937 
13938 #define S_D_RSPVLD    28
13939 #define M_D_RSPVLD    0x7U
13940 #define V_D_RSPVLD(x) ((x) << S_D_RSPVLD)
13941 #define G_D_RSPVLD(x) (((x) >> S_D_RSPVLD) & M_D_RSPVLD)
13942 
13943 #define S_D_RSPVLD2    27
13944 #define V_D_RSPVLD2(x) ((x) << S_D_RSPVLD2)
13945 #define F_D_RSPVLD2    V_D_RSPVLD2(1U)
13946 
13947 #define S_D_RSPVLD3    26
13948 #define V_D_RSPVLD3(x) ((x) << S_D_RSPVLD3)
13949 #define F_D_RSPVLD3    V_D_RSPVLD3(1U)
13950 
13951 #define S_D_RSPVLD4    25
13952 #define V_D_RSPVLD4(x) ((x) << S_D_RSPVLD4)
13953 #define F_D_RSPVLD4    V_D_RSPVLD4(1U)
13954 
13955 #define S_D_RSPVLD5    24
13956 #define V_D_RSPVLD5(x) ((x) << S_D_RSPVLD5)
13957 #define F_D_RSPVLD5    V_D_RSPVLD5(1U)
13958 
13959 #define S_D_RSPVLD6    20
13960 #define M_D_RSPVLD6    0xfU
13961 #define V_D_RSPVLD6(x) ((x) << S_D_RSPVLD6)
13962 #define G_D_RSPVLD6(x) (((x) >> S_D_RSPVLD6) & M_D_RSPVLD6)
13963 
13964 #define S_D_RSPAFULL    16
13965 #define M_D_RSPAFULL    0xfU
13966 #define V_D_RSPAFULL(x) ((x) << S_D_RSPAFULL)
13967 #define G_D_RSPAFULL(x) (((x) >> S_D_RSPAFULL) & M_D_RSPAFULL)
13968 
13969 #define S_D_RDREQVLD    12
13970 #define M_D_RDREQVLD    0xfU
13971 #define V_D_RDREQVLD(x) ((x) << S_D_RDREQVLD)
13972 #define G_D_RDREQVLD(x) (((x) >> S_D_RDREQVLD) & M_D_RDREQVLD)
13973 
13974 #define S_D_RDREQAFULL    8
13975 #define M_D_RDREQAFULL    0xfU
13976 #define V_D_RDREQAFULL(x) ((x) << S_D_RDREQAFULL)
13977 #define G_D_RDREQAFULL(x) (((x) >> S_D_RDREQAFULL) & M_D_RDREQAFULL)
13978 
13979 #define S_D_WRREQVLD    4
13980 #define M_D_WRREQVLD    0xfU
13981 #define V_D_WRREQVLD(x) ((x) << S_D_WRREQVLD)
13982 #define G_D_WRREQVLD(x) (((x) >> S_D_WRREQVLD) & M_D_WRREQVLD)
13983 
13984 #define S_D_WRREQAFULL    0
13985 #define M_D_WRREQAFULL    0xfU
13986 #define V_D_WRREQAFULL(x) ((x) << S_D_WRREQAFULL)
13987 #define G_D_WRREQAFULL(x) (((x) >> S_D_WRREQAFULL) & M_D_WRREQAFULL)
13988 
13989 #define A_PCIE_CDEBUG_REG_0X3 0x3
13990 
13991 #define S_C_REQVLD    19
13992 #define M_C_REQVLD    0x1fffU
13993 #define V_C_REQVLD(x) ((x) << S_C_REQVLD)
13994 #define G_C_REQVLD(x) (((x) >> S_C_REQVLD) & M_C_REQVLD)
13995 
13996 #define S_C_RSPVLD2    16
13997 #define M_C_RSPVLD2    0x7U
13998 #define V_C_RSPVLD2(x) ((x) << S_C_RSPVLD2)
13999 #define G_C_RSPVLD2(x) (((x) >> S_C_RSPVLD2) & M_C_RSPVLD2)
14000 
14001 #define S_C_RSPVLD3    15
14002 #define V_C_RSPVLD3(x) ((x) << S_C_RSPVLD3)
14003 #define F_C_RSPVLD3    V_C_RSPVLD3(1U)
14004 
14005 #define S_C_RSPVLD4    14
14006 #define V_C_RSPVLD4(x) ((x) << S_C_RSPVLD4)
14007 #define F_C_RSPVLD4    V_C_RSPVLD4(1U)
14008 
14009 #define S_C_RSPVLD5    13
14010 #define V_C_RSPVLD5(x) ((x) << S_C_RSPVLD5)
14011 #define F_C_RSPVLD5    V_C_RSPVLD5(1U)
14012 
14013 #define S_C_RSPVLD6    12
14014 #define V_C_RSPVLD6(x) ((x) << S_C_RSPVLD6)
14015 #define F_C_RSPVLD6    V_C_RSPVLD6(1U)
14016 
14017 #define S_C_RSPVLD7    9
14018 #define M_C_RSPVLD7    0x7U
14019 #define V_C_RSPVLD7(x) ((x) << S_C_RSPVLD7)
14020 #define G_C_RSPVLD7(x) (((x) >> S_C_RSPVLD7) & M_C_RSPVLD7)
14021 
14022 #define S_C_RSPAFULL    6
14023 #define M_C_RSPAFULL    0x7U
14024 #define V_C_RSPAFULL(x) ((x) << S_C_RSPAFULL)
14025 #define G_C_RSPAFULL(x) (((x) >> S_C_RSPAFULL) & M_C_RSPAFULL)
14026 
14027 #define S_C_REQVLD8    3
14028 #define M_C_REQVLD8    0x7U
14029 #define V_C_REQVLD8(x) ((x) << S_C_REQVLD8)
14030 #define G_C_REQVLD8(x) (((x) >> S_C_REQVLD8) & M_C_REQVLD8)
14031 
14032 #define S_C_REQAFULL    0
14033 #define M_C_REQAFULL    0x7U
14034 #define V_C_REQAFULL(x) ((x) << S_C_REQAFULL)
14035 #define G_C_REQAFULL(x) (((x) >> S_C_REQAFULL) & M_C_REQAFULL)
14036 
14037 #define A_PCIE_CDEBUG_REG_0X4 0x4
14038 
14039 #define S_H_REQVLD    7
14040 #define M_H_REQVLD    0x1ffffffU
14041 #define V_H_REQVLD(x) ((x) << S_H_REQVLD)
14042 #define G_H_REQVLD(x) (((x) >> S_H_REQVLD) & M_H_REQVLD)
14043 
14044 #define S_H_RSPVLD    6
14045 #define V_H_RSPVLD(x) ((x) << S_H_RSPVLD)
14046 #define F_H_RSPVLD    V_H_RSPVLD(1U)
14047 
14048 #define S_H_RSPVLD2    5
14049 #define V_H_RSPVLD2(x) ((x) << S_H_RSPVLD2)
14050 #define F_H_RSPVLD2    V_H_RSPVLD2(1U)
14051 
14052 #define S_H_RSPVLD3    4
14053 #define V_H_RSPVLD3(x) ((x) << S_H_RSPVLD3)
14054 #define F_H_RSPVLD3    V_H_RSPVLD3(1U)
14055 
14056 #define S_H_RSPVLD4    3
14057 #define V_H_RSPVLD4(x) ((x) << S_H_RSPVLD4)
14058 #define F_H_RSPVLD4    V_H_RSPVLD4(1U)
14059 
14060 #define S_H_RSPAFULL    2
14061 #define V_H_RSPAFULL(x) ((x) << S_H_RSPAFULL)
14062 #define F_H_RSPAFULL    V_H_RSPAFULL(1U)
14063 
14064 #define S_H_REQVLD2    1
14065 #define V_H_REQVLD2(x) ((x) << S_H_REQVLD2)
14066 #define F_H_REQVLD2    V_H_REQVLD2(1U)
14067 
14068 #define S_H_REQAFULL    0
14069 #define V_H_REQAFULL(x) ((x) << S_H_REQAFULL)
14070 #define F_H_REQAFULL    V_H_REQAFULL(1U)
14071 
14072 #define A_PCIE_CDEBUG_REG_0X5 0x5
14073 
14074 #define S_ER_RSPVLD    16
14075 #define M_ER_RSPVLD    0xffffU
14076 #define V_ER_RSPVLD(x) ((x) << S_ER_RSPVLD)
14077 #define G_ER_RSPVLD(x) (((x) >> S_ER_RSPVLD) & M_ER_RSPVLD)
14078 
14079 #define S_ER_REQVLD2    5
14080 #define M_ER_REQVLD2    0x7ffU
14081 #define V_ER_REQVLD2(x) ((x) << S_ER_REQVLD2)
14082 #define G_ER_REQVLD2(x) (((x) >> S_ER_REQVLD2) & M_ER_REQVLD2)
14083 
14084 #define S_ER_REQVLD3    2
14085 #define M_ER_REQVLD3    0x7U
14086 #define V_ER_REQVLD3(x) ((x) << S_ER_REQVLD3)
14087 #define G_ER_REQVLD3(x) (((x) >> S_ER_REQVLD3) & M_ER_REQVLD3)
14088 
14089 #define S_ER_RSPVLD4    1
14090 #define V_ER_RSPVLD4(x) ((x) << S_ER_RSPVLD4)
14091 #define F_ER_RSPVLD4    V_ER_RSPVLD4(1U)
14092 
14093 #define S_ER_REQVLD5    0
14094 #define V_ER_REQVLD5(x) ((x) << S_ER_REQVLD5)
14095 #define F_ER_REQVLD5    V_ER_REQVLD5(1U)
14096 
14097 #define A_PCIE_CDEBUG_REG_0X6 0x6
14098 
14099 #define S_PL_BAR2_REQVLD    4
14100 #define M_PL_BAR2_REQVLD    0xfffffffU
14101 #define V_PL_BAR2_REQVLD(x) ((x) << S_PL_BAR2_REQVLD)
14102 #define G_PL_BAR2_REQVLD(x) (((x) >> S_PL_BAR2_REQVLD) & M_PL_BAR2_REQVLD)
14103 
14104 #define S_PL_BAR2_REQVLD2    3
14105 #define V_PL_BAR2_REQVLD2(x) ((x) << S_PL_BAR2_REQVLD2)
14106 #define F_PL_BAR2_REQVLD2    V_PL_BAR2_REQVLD2(1U)
14107 
14108 #define S_PL_BAR2_REQVLDE    2
14109 #define V_PL_BAR2_REQVLDE(x) ((x) << S_PL_BAR2_REQVLDE)
14110 #define F_PL_BAR2_REQVLDE    V_PL_BAR2_REQVLDE(1U)
14111 
14112 #define S_PL_BAR2_REQFULL    1
14113 #define V_PL_BAR2_REQFULL(x) ((x) << S_PL_BAR2_REQFULL)
14114 #define F_PL_BAR2_REQFULL    V_PL_BAR2_REQFULL(1U)
14115 
14116 #define S_PL_BAR2_REQVLD4    0
14117 #define V_PL_BAR2_REQVLD4(x) ((x) << S_PL_BAR2_REQVLD4)
14118 #define F_PL_BAR2_REQVLD4    V_PL_BAR2_REQVLD4(1U)
14119 
14120 #define A_PCIE_CDEBUG_REG_0X7 0x7
14121 #define A_PCIE_CDEBUG_REG_0X8 0x8
14122 #define A_PCIE_CDEBUG_REG_0X9 0x9
14123 #define A_PCIE_CDEBUG_REG_0XA 0xa
14124 
14125 #define S_VPD_RSPVLD    20
14126 #define M_VPD_RSPVLD    0xfffU
14127 #define V_VPD_RSPVLD(x) ((x) << S_VPD_RSPVLD)
14128 #define G_VPD_RSPVLD(x) (((x) >> S_VPD_RSPVLD) & M_VPD_RSPVLD)
14129 
14130 #define S_VPD_REQVLD2    9
14131 #define M_VPD_REQVLD2    0x7ffU
14132 #define V_VPD_REQVLD2(x) ((x) << S_VPD_REQVLD2)
14133 #define G_VPD_REQVLD2(x) (((x) >> S_VPD_REQVLD2) & M_VPD_REQVLD2)
14134 
14135 #define S_VPD_REQVLD3    6
14136 #define M_VPD_REQVLD3    0x7U
14137 #define V_VPD_REQVLD3(x) ((x) << S_VPD_REQVLD3)
14138 #define G_VPD_REQVLD3(x) (((x) >> S_VPD_REQVLD3) & M_VPD_REQVLD3)
14139 
14140 #define S_VPD_REQVLD4    5
14141 #define V_VPD_REQVLD4(x) ((x) << S_VPD_REQVLD4)
14142 #define F_VPD_REQVLD4    V_VPD_REQVLD4(1U)
14143 
14144 #define S_VPD_REQVLD5    3
14145 #define M_VPD_REQVLD5    0x3U
14146 #define V_VPD_REQVLD5(x) ((x) << S_VPD_REQVLD5)
14147 #define G_VPD_REQVLD5(x) (((x) >> S_VPD_REQVLD5) & M_VPD_REQVLD5)
14148 
14149 #define S_VPD_RSPVLD2    2
14150 #define V_VPD_RSPVLD2(x) ((x) << S_VPD_RSPVLD2)
14151 #define F_VPD_RSPVLD2    V_VPD_RSPVLD2(1U)
14152 
14153 #define S_VPD_RSPVLD3    1
14154 #define V_VPD_RSPVLD3(x) ((x) << S_VPD_RSPVLD3)
14155 #define F_VPD_RSPVLD3    V_VPD_RSPVLD3(1U)
14156 
14157 #define S_VPD_REQVLD6    0
14158 #define V_VPD_REQVLD6(x) ((x) << S_VPD_REQVLD6)
14159 #define F_VPD_REQVLD6    V_VPD_REQVLD6(1U)
14160 
14161 #define A_PCIE_CDEBUG_REG_0XB 0xb
14162 
14163 #define S_MA_REQDATAVLD    28
14164 #define M_MA_REQDATAVLD    0xfU
14165 #define V_MA_REQDATAVLD(x) ((x) << S_MA_REQDATAVLD)
14166 #define G_MA_REQDATAVLD(x) (((x) >> S_MA_REQDATAVLD) & M_MA_REQDATAVLD)
14167 
14168 #define S_MA_REQADDRVLD    27
14169 #define V_MA_REQADDRVLD(x) ((x) << S_MA_REQADDRVLD)
14170 #define F_MA_REQADDRVLD    V_MA_REQADDRVLD(1U)
14171 
14172 #define S_MA_REQADDRVLD2    26
14173 #define V_MA_REQADDRVLD2(x) ((x) << S_MA_REQADDRVLD2)
14174 #define F_MA_REQADDRVLD2    V_MA_REQADDRVLD2(1U)
14175 
14176 #define S_MA_RSPDATAVLD2    22
14177 #define M_MA_RSPDATAVLD2    0xfU
14178 #define V_MA_RSPDATAVLD2(x) ((x) << S_MA_RSPDATAVLD2)
14179 #define G_MA_RSPDATAVLD2(x) (((x) >> S_MA_RSPDATAVLD2) & M_MA_RSPDATAVLD2)
14180 
14181 #define S_MA_REQADDRVLD3    20
14182 #define M_MA_REQADDRVLD3    0x3U
14183 #define V_MA_REQADDRVLD3(x) ((x) << S_MA_REQADDRVLD3)
14184 #define G_MA_REQADDRVLD3(x) (((x) >> S_MA_REQADDRVLD3) & M_MA_REQADDRVLD3)
14185 
14186 #define S_MA_REQADDRVLD4    4
14187 #define M_MA_REQADDRVLD4    0xffffU
14188 #define V_MA_REQADDRVLD4(x) ((x) << S_MA_REQADDRVLD4)
14189 #define G_MA_REQADDRVLD4(x) (((x) >> S_MA_REQADDRVLD4) & M_MA_REQADDRVLD4)
14190 
14191 #define S_MA_REQADDRVLD5    3
14192 #define V_MA_REQADDRVLD5(x) ((x) << S_MA_REQADDRVLD5)
14193 #define F_MA_REQADDRVLD5    V_MA_REQADDRVLD5(1U)
14194 
14195 #define S_MA_REQADDRVLD6    2
14196 #define V_MA_REQADDRVLD6(x) ((x) << S_MA_REQADDRVLD6)
14197 #define F_MA_REQADDRVLD6    V_MA_REQADDRVLD6(1U)
14198 
14199 #define S_MA_REQADDRRDY    1
14200 #define V_MA_REQADDRRDY(x) ((x) << S_MA_REQADDRRDY)
14201 #define F_MA_REQADDRRDY    V_MA_REQADDRRDY(1U)
14202 
14203 #define S_MA_REQADDRVLD7    0
14204 #define V_MA_REQADDRVLD7(x) ((x) << S_MA_REQADDRVLD7)
14205 #define F_MA_REQADDRVLD7    V_MA_REQADDRVLD7(1U)
14206 
14207 #define A_PCIE_CDEBUG_REG_0XC 0xc
14208 #define A_PCIE_CDEBUG_REG_0XD 0xd
14209 #define A_PCIE_CDEBUG_REG_0XE 0xe
14210 #define A_PCIE_CDEBUG_REG_0XF 0xf
14211 #define A_PCIE_CDEBUG_REG_0X10 0x10
14212 #define A_PCIE_CDEBUG_REG_0X11 0x11
14213 #define A_PCIE_CDEBUG_REG_0X12 0x12
14214 #define A_PCIE_CDEBUG_REG_0X13 0x13
14215 #define A_PCIE_CDEBUG_REG_0X14 0x14
14216 #define A_PCIE_CDEBUG_REG_0X15 0x15
14217 
14218 #define S_PLM_REQVLD    19
14219 #define M_PLM_REQVLD    0x1fffU
14220 #define V_PLM_REQVLD(x) ((x) << S_PLM_REQVLD)
14221 #define G_PLM_REQVLD(x) (((x) >> S_PLM_REQVLD) & M_PLM_REQVLD)
14222 
14223 #define S_PLM_REQVLD2    18
14224 #define V_PLM_REQVLD2(x) ((x) << S_PLM_REQVLD2)
14225 #define F_PLM_REQVLD2    V_PLM_REQVLD2(1U)
14226 
14227 #define S_PLM_RSPVLD3    17
14228 #define V_PLM_RSPVLD3(x) ((x) << S_PLM_RSPVLD3)
14229 #define F_PLM_RSPVLD3    V_PLM_RSPVLD3(1U)
14230 
14231 #define S_PLM_REQVLD4    16
14232 #define V_PLM_REQVLD4(x) ((x) << S_PLM_REQVLD4)
14233 #define F_PLM_REQVLD4    V_PLM_REQVLD4(1U)
14234 
14235 #define S_PLM_REQVLD5    15
14236 #define V_PLM_REQVLD5(x) ((x) << S_PLM_REQVLD5)
14237 #define F_PLM_REQVLD5    V_PLM_REQVLD5(1U)
14238 
14239 #define S_PLM_REQVLD6    14
14240 #define V_PLM_REQVLD6(x) ((x) << S_PLM_REQVLD6)
14241 #define F_PLM_REQVLD6    V_PLM_REQVLD6(1U)
14242 
14243 #define S_PLM_REQVLD7    13
14244 #define V_PLM_REQVLD7(x) ((x) << S_PLM_REQVLD7)
14245 #define F_PLM_REQVLD7    V_PLM_REQVLD7(1U)
14246 
14247 #define S_PLM_REQVLD8    12
14248 #define V_PLM_REQVLD8(x) ((x) << S_PLM_REQVLD8)
14249 #define F_PLM_REQVLD8    V_PLM_REQVLD8(1U)
14250 
14251 #define S_PLM_REQVLD9    4
14252 #define M_PLM_REQVLD9    0xffU
14253 #define V_PLM_REQVLD9(x) ((x) << S_PLM_REQVLD9)
14254 #define G_PLM_REQVLD9(x) (((x) >> S_PLM_REQVLD9) & M_PLM_REQVLD9)
14255 
14256 #define S_PLM_REQVLDA    1
14257 #define M_PLM_REQVLDA    0x7U
14258 #define V_PLM_REQVLDA(x) ((x) << S_PLM_REQVLDA)
14259 #define G_PLM_REQVLDA(x) (((x) >> S_PLM_REQVLDA) & M_PLM_REQVLDA)
14260 
14261 #define S_PLM_REQVLDB    0
14262 #define V_PLM_REQVLDB(x) ((x) << S_PLM_REQVLDB)
14263 #define F_PLM_REQVLDB    V_PLM_REQVLDB(1U)
14264 
14265 #define A_PCIE_CDEBUG_REG_0X16 0x16
14266 #define A_PCIE_CDEBUG_REG_0X17 0x17
14267 #define A_PCIE_CDEBUG_REG_0X18 0x18
14268 #define A_PCIE_CDEBUG_REG_0X19 0x19
14269 #define A_PCIE_CDEBUG_REG_0X1A 0x1a
14270 #define A_PCIE_CDEBUG_REG_0X1B 0x1b
14271 #define A_PCIE_CDEBUG_REG_0X1C 0x1c
14272 #define A_PCIE_CDEBUG_REG_0X1D 0x1d
14273 #define A_PCIE_CDEBUG_REG_0X1E 0x1e
14274 #define A_PCIE_CDEBUG_REG_0X1F 0x1f
14275 #define A_PCIE_CDEBUG_REG_0X20 0x20
14276 #define A_PCIE_CDEBUG_REG_0X21 0x21
14277 #define A_PCIE_CDEBUG_REG_0X22 0x22
14278 #define A_PCIE_CDEBUG_REG_0X23 0x23
14279 #define A_PCIE_CDEBUG_REG_0X24 0x24
14280 #define A_PCIE_CDEBUG_REG_0X25 0x25
14281 #define A_PCIE_CDEBUG_REG_0X26 0x26
14282 #define A_PCIE_CDEBUG_REG_0X27 0x27
14283 #define A_PCIE_CDEBUG_REG_0X28 0x28
14284 #define A_PCIE_CDEBUG_REG_0X29 0x29
14285 #define A_PCIE_CDEBUG_REG_0X2A 0x2a
14286 #define A_PCIE_CDEBUG_REG_0X2B 0x2b
14287 #define A_PCIE_CDEBUG_REG_0X2C 0x2c
14288 #define A_PCIE_CDEBUG_REG_0X2D 0x2d
14289 #define A_PCIE_CDEBUG_REG_0X2E 0x2e
14290 #define A_PCIE_CDEBUG_REG_0X2F 0x2f
14291 #define A_PCIE_CDEBUG_REG_0X30 0x30
14292 #define A_PCIE_CDEBUG_REG_0X31 0x31
14293 #define A_PCIE_CDEBUG_REG_0X32 0x32
14294 #define A_PCIE_CDEBUG_REG_0X33 0x33
14295 #define A_PCIE_CDEBUG_REG_0X34 0x34
14296 #define A_PCIE_CDEBUG_REG_0X35 0x35
14297 #define A_PCIE_CDEBUG_REG_0X36 0x36
14298 #define A_PCIE_CDEBUG_REG_0X37 0x37
14299 
14300 /* registers for module DBG */
14301 #define DBG_BASE_ADDR 0x6000
14302 
14303 #define A_DBG_DBG0_CFG 0x6000
14304 
14305 #define S_MODULESELECT    12
14306 #define M_MODULESELECT    0xffU
14307 #define V_MODULESELECT(x) ((x) << S_MODULESELECT)
14308 #define G_MODULESELECT(x) (((x) >> S_MODULESELECT) & M_MODULESELECT)
14309 
14310 #define S_REGSELECT    4
14311 #define M_REGSELECT    0xffU
14312 #define V_REGSELECT(x) ((x) << S_REGSELECT)
14313 #define G_REGSELECT(x) (((x) >> S_REGSELECT) & M_REGSELECT)
14314 
14315 #define S_CLKSELECT    0
14316 #define M_CLKSELECT    0xfU
14317 #define V_CLKSELECT(x) ((x) << S_CLKSELECT)
14318 #define G_CLKSELECT(x) (((x) >> S_CLKSELECT) & M_CLKSELECT)
14319 
14320 #define A_DBG_DBG0_EN 0x6004
14321 
14322 #define S_PORTEN_PONR    16
14323 #define V_PORTEN_PONR(x) ((x) << S_PORTEN_PONR)
14324 #define F_PORTEN_PONR    V_PORTEN_PONR(1U)
14325 
14326 #define S_PORTEN_POND    12
14327 #define V_PORTEN_POND(x) ((x) << S_PORTEN_POND)
14328 #define F_PORTEN_POND    V_PORTEN_POND(1U)
14329 
14330 #define S_SDRHALFWORD0    8
14331 #define V_SDRHALFWORD0(x) ((x) << S_SDRHALFWORD0)
14332 #define F_SDRHALFWORD0    V_SDRHALFWORD0(1U)
14333 
14334 #define S_DDREN    4
14335 #define V_DDREN(x) ((x) << S_DDREN)
14336 #define F_DDREN    V_DDREN(1U)
14337 
14338 #define S_DBG_PORTEN    0
14339 #define V_DBG_PORTEN(x) ((x) << S_DBG_PORTEN)
14340 #define F_DBG_PORTEN    V_DBG_PORTEN(1U)
14341 
14342 #define A_DBG_DBG1_CFG 0x6008
14343 #define A_DBG_DBG1_EN 0x600c
14344 
14345 #define S_CLK_EN_ON_DBG1    20
14346 #define V_CLK_EN_ON_DBG1(x) ((x) << S_CLK_EN_ON_DBG1)
14347 #define F_CLK_EN_ON_DBG1    V_CLK_EN_ON_DBG1(1U)
14348 
14349 #define A_DBG_GPIO_EN 0x6010
14350 
14351 #define S_GPIO15_OEN    31
14352 #define V_GPIO15_OEN(x) ((x) << S_GPIO15_OEN)
14353 #define F_GPIO15_OEN    V_GPIO15_OEN(1U)
14354 
14355 #define S_GPIO14_OEN    30
14356 #define V_GPIO14_OEN(x) ((x) << S_GPIO14_OEN)
14357 #define F_GPIO14_OEN    V_GPIO14_OEN(1U)
14358 
14359 #define S_GPIO13_OEN    29
14360 #define V_GPIO13_OEN(x) ((x) << S_GPIO13_OEN)
14361 #define F_GPIO13_OEN    V_GPIO13_OEN(1U)
14362 
14363 #define S_GPIO12_OEN    28
14364 #define V_GPIO12_OEN(x) ((x) << S_GPIO12_OEN)
14365 #define F_GPIO12_OEN    V_GPIO12_OEN(1U)
14366 
14367 #define S_GPIO11_OEN    27
14368 #define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
14369 #define F_GPIO11_OEN    V_GPIO11_OEN(1U)
14370 
14371 #define S_GPIO10_OEN    26
14372 #define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
14373 #define F_GPIO10_OEN    V_GPIO10_OEN(1U)
14374 
14375 #define S_GPIO9_OEN    25
14376 #define V_GPIO9_OEN(x) ((x) << S_GPIO9_OEN)
14377 #define F_GPIO9_OEN    V_GPIO9_OEN(1U)
14378 
14379 #define S_GPIO8_OEN    24
14380 #define V_GPIO8_OEN(x) ((x) << S_GPIO8_OEN)
14381 #define F_GPIO8_OEN    V_GPIO8_OEN(1U)
14382 
14383 #define S_GPIO7_OEN    23
14384 #define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
14385 #define F_GPIO7_OEN    V_GPIO7_OEN(1U)
14386 
14387 #define S_GPIO6_OEN    22
14388 #define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
14389 #define F_GPIO6_OEN    V_GPIO6_OEN(1U)
14390 
14391 #define S_GPIO5_OEN    21
14392 #define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
14393 #define F_GPIO5_OEN    V_GPIO5_OEN(1U)
14394 
14395 #define S_GPIO4_OEN    20
14396 #define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
14397 #define F_GPIO4_OEN    V_GPIO4_OEN(1U)
14398 
14399 #define S_GPIO3_OEN    19
14400 #define V_GPIO3_OEN(x) ((x) << S_GPIO3_OEN)
14401 #define F_GPIO3_OEN    V_GPIO3_OEN(1U)
14402 
14403 #define S_GPIO2_OEN    18
14404 #define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
14405 #define F_GPIO2_OEN    V_GPIO2_OEN(1U)
14406 
14407 #define S_GPIO1_OEN    17
14408 #define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
14409 #define F_GPIO1_OEN    V_GPIO1_OEN(1U)
14410 
14411 #define S_GPIO0_OEN    16
14412 #define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
14413 #define F_GPIO0_OEN    V_GPIO0_OEN(1U)
14414 
14415 #define S_GPIO15_OUT_VAL    15
14416 #define V_GPIO15_OUT_VAL(x) ((x) << S_GPIO15_OUT_VAL)
14417 #define F_GPIO15_OUT_VAL    V_GPIO15_OUT_VAL(1U)
14418 
14419 #define S_GPIO14_OUT_VAL    14
14420 #define V_GPIO14_OUT_VAL(x) ((x) << S_GPIO14_OUT_VAL)
14421 #define F_GPIO14_OUT_VAL    V_GPIO14_OUT_VAL(1U)
14422 
14423 #define S_GPIO13_OUT_VAL    13
14424 #define V_GPIO13_OUT_VAL(x) ((x) << S_GPIO13_OUT_VAL)
14425 #define F_GPIO13_OUT_VAL    V_GPIO13_OUT_VAL(1U)
14426 
14427 #define S_GPIO12_OUT_VAL    12
14428 #define V_GPIO12_OUT_VAL(x) ((x) << S_GPIO12_OUT_VAL)
14429 #define F_GPIO12_OUT_VAL    V_GPIO12_OUT_VAL(1U)
14430 
14431 #define S_GPIO11_OUT_VAL    11
14432 #define V_GPIO11_OUT_VAL(x) ((x) << S_GPIO11_OUT_VAL)
14433 #define F_GPIO11_OUT_VAL    V_GPIO11_OUT_VAL(1U)
14434 
14435 #define S_GPIO10_OUT_VAL    10
14436 #define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
14437 #define F_GPIO10_OUT_VAL    V_GPIO10_OUT_VAL(1U)
14438 
14439 #define S_GPIO9_OUT_VAL    9
14440 #define V_GPIO9_OUT_VAL(x) ((x) << S_GPIO9_OUT_VAL)
14441 #define F_GPIO9_OUT_VAL    V_GPIO9_OUT_VAL(1U)
14442 
14443 #define S_GPIO8_OUT_VAL    8
14444 #define V_GPIO8_OUT_VAL(x) ((x) << S_GPIO8_OUT_VAL)
14445 #define F_GPIO8_OUT_VAL    V_GPIO8_OUT_VAL(1U)
14446 
14447 #define S_GPIO7_OUT_VAL    7
14448 #define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
14449 #define F_GPIO7_OUT_VAL    V_GPIO7_OUT_VAL(1U)
14450 
14451 #define S_GPIO6_OUT_VAL    6
14452 #define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
14453 #define F_GPIO6_OUT_VAL    V_GPIO6_OUT_VAL(1U)
14454 
14455 #define S_GPIO5_OUT_VAL    5
14456 #define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
14457 #define F_GPIO5_OUT_VAL    V_GPIO5_OUT_VAL(1U)
14458 
14459 #define S_GPIO4_OUT_VAL    4
14460 #define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
14461 #define F_GPIO4_OUT_VAL    V_GPIO4_OUT_VAL(1U)
14462 
14463 #define S_GPIO3_OUT_VAL    3
14464 #define V_GPIO3_OUT_VAL(x) ((x) << S_GPIO3_OUT_VAL)
14465 #define F_GPIO3_OUT_VAL    V_GPIO3_OUT_VAL(1U)
14466 
14467 #define S_GPIO2_OUT_VAL    2
14468 #define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
14469 #define F_GPIO2_OUT_VAL    V_GPIO2_OUT_VAL(1U)
14470 
14471 #define S_GPIO1_OUT_VAL    1
14472 #define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
14473 #define F_GPIO1_OUT_VAL    V_GPIO1_OUT_VAL(1U)
14474 
14475 #define S_GPIO0_OUT_VAL    0
14476 #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
14477 #define F_GPIO0_OUT_VAL    V_GPIO0_OUT_VAL(1U)
14478 
14479 #define A_DBG_GPIO_OUT 0x6010
14480 
14481 #define S_GPIO23_OUT_VAL    23
14482 #define V_GPIO23_OUT_VAL(x) ((x) << S_GPIO23_OUT_VAL)
14483 #define F_GPIO23_OUT_VAL    V_GPIO23_OUT_VAL(1U)
14484 
14485 #define S_GPIO22_OUT_VAL    22
14486 #define V_GPIO22_OUT_VAL(x) ((x) << S_GPIO22_OUT_VAL)
14487 #define F_GPIO22_OUT_VAL    V_GPIO22_OUT_VAL(1U)
14488 
14489 #define S_GPIO21_OUT_VAL    21
14490 #define V_GPIO21_OUT_VAL(x) ((x) << S_GPIO21_OUT_VAL)
14491 #define F_GPIO21_OUT_VAL    V_GPIO21_OUT_VAL(1U)
14492 
14493 #define S_GPIO20_OUT_VAL    20
14494 #define V_GPIO20_OUT_VAL(x) ((x) << S_GPIO20_OUT_VAL)
14495 #define F_GPIO20_OUT_VAL    V_GPIO20_OUT_VAL(1U)
14496 
14497 #define S_T7_GPIO19_OUT_VAL    19
14498 #define V_T7_GPIO19_OUT_VAL(x) ((x) << S_T7_GPIO19_OUT_VAL)
14499 #define F_T7_GPIO19_OUT_VAL    V_T7_GPIO19_OUT_VAL(1U)
14500 
14501 #define S_T7_GPIO18_OUT_VAL    18
14502 #define V_T7_GPIO18_OUT_VAL(x) ((x) << S_T7_GPIO18_OUT_VAL)
14503 #define F_T7_GPIO18_OUT_VAL    V_T7_GPIO18_OUT_VAL(1U)
14504 
14505 #define S_T7_GPIO17_OUT_VAL    17
14506 #define V_T7_GPIO17_OUT_VAL(x) ((x) << S_T7_GPIO17_OUT_VAL)
14507 #define F_T7_GPIO17_OUT_VAL    V_T7_GPIO17_OUT_VAL(1U)
14508 
14509 #define S_T7_GPIO16_OUT_VAL    16
14510 #define V_T7_GPIO16_OUT_VAL(x) ((x) << S_T7_GPIO16_OUT_VAL)
14511 #define F_T7_GPIO16_OUT_VAL    V_T7_GPIO16_OUT_VAL(1U)
14512 
14513 #define A_DBG_GPIO_IN 0x6014
14514 
14515 #define S_GPIO15_CHG_DET    31
14516 #define V_GPIO15_CHG_DET(x) ((x) << S_GPIO15_CHG_DET)
14517 #define F_GPIO15_CHG_DET    V_GPIO15_CHG_DET(1U)
14518 
14519 #define S_GPIO14_CHG_DET    30
14520 #define V_GPIO14_CHG_DET(x) ((x) << S_GPIO14_CHG_DET)
14521 #define F_GPIO14_CHG_DET    V_GPIO14_CHG_DET(1U)
14522 
14523 #define S_GPIO13_CHG_DET    29
14524 #define V_GPIO13_CHG_DET(x) ((x) << S_GPIO13_CHG_DET)
14525 #define F_GPIO13_CHG_DET    V_GPIO13_CHG_DET(1U)
14526 
14527 #define S_GPIO12_CHG_DET    28
14528 #define V_GPIO12_CHG_DET(x) ((x) << S_GPIO12_CHG_DET)
14529 #define F_GPIO12_CHG_DET    V_GPIO12_CHG_DET(1U)
14530 
14531 #define S_GPIO11_CHG_DET    27
14532 #define V_GPIO11_CHG_DET(x) ((x) << S_GPIO11_CHG_DET)
14533 #define F_GPIO11_CHG_DET    V_GPIO11_CHG_DET(1U)
14534 
14535 #define S_GPIO10_CHG_DET    26
14536 #define V_GPIO10_CHG_DET(x) ((x) << S_GPIO10_CHG_DET)
14537 #define F_GPIO10_CHG_DET    V_GPIO10_CHG_DET(1U)
14538 
14539 #define S_GPIO9_CHG_DET    25
14540 #define V_GPIO9_CHG_DET(x) ((x) << S_GPIO9_CHG_DET)
14541 #define F_GPIO9_CHG_DET    V_GPIO9_CHG_DET(1U)
14542 
14543 #define S_GPIO8_CHG_DET    24
14544 #define V_GPIO8_CHG_DET(x) ((x) << S_GPIO8_CHG_DET)
14545 #define F_GPIO8_CHG_DET    V_GPIO8_CHG_DET(1U)
14546 
14547 #define S_GPIO7_CHG_DET    23
14548 #define V_GPIO7_CHG_DET(x) ((x) << S_GPIO7_CHG_DET)
14549 #define F_GPIO7_CHG_DET    V_GPIO7_CHG_DET(1U)
14550 
14551 #define S_GPIO6_CHG_DET    22
14552 #define V_GPIO6_CHG_DET(x) ((x) << S_GPIO6_CHG_DET)
14553 #define F_GPIO6_CHG_DET    V_GPIO6_CHG_DET(1U)
14554 
14555 #define S_GPIO5_CHG_DET    21
14556 #define V_GPIO5_CHG_DET(x) ((x) << S_GPIO5_CHG_DET)
14557 #define F_GPIO5_CHG_DET    V_GPIO5_CHG_DET(1U)
14558 
14559 #define S_GPIO4_CHG_DET    20
14560 #define V_GPIO4_CHG_DET(x) ((x) << S_GPIO4_CHG_DET)
14561 #define F_GPIO4_CHG_DET    V_GPIO4_CHG_DET(1U)
14562 
14563 #define S_GPIO3_CHG_DET    19
14564 #define V_GPIO3_CHG_DET(x) ((x) << S_GPIO3_CHG_DET)
14565 #define F_GPIO3_CHG_DET    V_GPIO3_CHG_DET(1U)
14566 
14567 #define S_GPIO2_CHG_DET    18
14568 #define V_GPIO2_CHG_DET(x) ((x) << S_GPIO2_CHG_DET)
14569 #define F_GPIO2_CHG_DET    V_GPIO2_CHG_DET(1U)
14570 
14571 #define S_GPIO1_CHG_DET    17
14572 #define V_GPIO1_CHG_DET(x) ((x) << S_GPIO1_CHG_DET)
14573 #define F_GPIO1_CHG_DET    V_GPIO1_CHG_DET(1U)
14574 
14575 #define S_GPIO0_CHG_DET    16
14576 #define V_GPIO0_CHG_DET(x) ((x) << S_GPIO0_CHG_DET)
14577 #define F_GPIO0_CHG_DET    V_GPIO0_CHG_DET(1U)
14578 
14579 #define S_GPIO15_IN    15
14580 #define V_GPIO15_IN(x) ((x) << S_GPIO15_IN)
14581 #define F_GPIO15_IN    V_GPIO15_IN(1U)
14582 
14583 #define S_GPIO14_IN    14
14584 #define V_GPIO14_IN(x) ((x) << S_GPIO14_IN)
14585 #define F_GPIO14_IN    V_GPIO14_IN(1U)
14586 
14587 #define S_GPIO13_IN    13
14588 #define V_GPIO13_IN(x) ((x) << S_GPIO13_IN)
14589 #define F_GPIO13_IN    V_GPIO13_IN(1U)
14590 
14591 #define S_GPIO12_IN    12
14592 #define V_GPIO12_IN(x) ((x) << S_GPIO12_IN)
14593 #define F_GPIO12_IN    V_GPIO12_IN(1U)
14594 
14595 #define S_GPIO11_IN    11
14596 #define V_GPIO11_IN(x) ((x) << S_GPIO11_IN)
14597 #define F_GPIO11_IN    V_GPIO11_IN(1U)
14598 
14599 #define S_GPIO10_IN    10
14600 #define V_GPIO10_IN(x) ((x) << S_GPIO10_IN)
14601 #define F_GPIO10_IN    V_GPIO10_IN(1U)
14602 
14603 #define S_GPIO9_IN    9
14604 #define V_GPIO9_IN(x) ((x) << S_GPIO9_IN)
14605 #define F_GPIO9_IN    V_GPIO9_IN(1U)
14606 
14607 #define S_GPIO8_IN    8
14608 #define V_GPIO8_IN(x) ((x) << S_GPIO8_IN)
14609 #define F_GPIO8_IN    V_GPIO8_IN(1U)
14610 
14611 #define S_GPIO7_IN    7
14612 #define V_GPIO7_IN(x) ((x) << S_GPIO7_IN)
14613 #define F_GPIO7_IN    V_GPIO7_IN(1U)
14614 
14615 #define S_GPIO6_IN    6
14616 #define V_GPIO6_IN(x) ((x) << S_GPIO6_IN)
14617 #define F_GPIO6_IN    V_GPIO6_IN(1U)
14618 
14619 #define S_GPIO5_IN    5
14620 #define V_GPIO5_IN(x) ((x) << S_GPIO5_IN)
14621 #define F_GPIO5_IN    V_GPIO5_IN(1U)
14622 
14623 #define S_GPIO4_IN    4
14624 #define V_GPIO4_IN(x) ((x) << S_GPIO4_IN)
14625 #define F_GPIO4_IN    V_GPIO4_IN(1U)
14626 
14627 #define S_GPIO3_IN    3
14628 #define V_GPIO3_IN(x) ((x) << S_GPIO3_IN)
14629 #define F_GPIO3_IN    V_GPIO3_IN(1U)
14630 
14631 #define S_GPIO2_IN    2
14632 #define V_GPIO2_IN(x) ((x) << S_GPIO2_IN)
14633 #define F_GPIO2_IN    V_GPIO2_IN(1U)
14634 
14635 #define S_GPIO1_IN    1
14636 #define V_GPIO1_IN(x) ((x) << S_GPIO1_IN)
14637 #define F_GPIO1_IN    V_GPIO1_IN(1U)
14638 
14639 #define S_GPIO0_IN    0
14640 #define V_GPIO0_IN(x) ((x) << S_GPIO0_IN)
14641 #define F_GPIO0_IN    V_GPIO0_IN(1U)
14642 
14643 #define S_GPIO23_IN    23
14644 #define V_GPIO23_IN(x) ((x) << S_GPIO23_IN)
14645 #define F_GPIO23_IN    V_GPIO23_IN(1U)
14646 
14647 #define S_GPIO22_IN    22
14648 #define V_GPIO22_IN(x) ((x) << S_GPIO22_IN)
14649 #define F_GPIO22_IN    V_GPIO22_IN(1U)
14650 
14651 #define S_GPIO21_IN    21
14652 #define V_GPIO21_IN(x) ((x) << S_GPIO21_IN)
14653 #define F_GPIO21_IN    V_GPIO21_IN(1U)
14654 
14655 #define S_GPIO20_IN    20
14656 #define V_GPIO20_IN(x) ((x) << S_GPIO20_IN)
14657 #define F_GPIO20_IN    V_GPIO20_IN(1U)
14658 
14659 #define S_T7_GPIO19_IN    19
14660 #define V_T7_GPIO19_IN(x) ((x) << S_T7_GPIO19_IN)
14661 #define F_T7_GPIO19_IN    V_T7_GPIO19_IN(1U)
14662 
14663 #define S_T7_GPIO18_IN    18
14664 #define V_T7_GPIO18_IN(x) ((x) << S_T7_GPIO18_IN)
14665 #define F_T7_GPIO18_IN    V_T7_GPIO18_IN(1U)
14666 
14667 #define S_T7_GPIO17_IN    17
14668 #define V_T7_GPIO17_IN(x) ((x) << S_T7_GPIO17_IN)
14669 #define F_T7_GPIO17_IN    V_T7_GPIO17_IN(1U)
14670 
14671 #define S_T7_GPIO16_IN    16
14672 #define V_T7_GPIO16_IN(x) ((x) << S_T7_GPIO16_IN)
14673 #define F_T7_GPIO16_IN    V_T7_GPIO16_IN(1U)
14674 
14675 #define A_DBG_INT_ENABLE 0x6018
14676 
14677 #define S_IBM_FDL_FAIL_INT_ENBL    25
14678 #define V_IBM_FDL_FAIL_INT_ENBL(x) ((x) << S_IBM_FDL_FAIL_INT_ENBL)
14679 #define F_IBM_FDL_FAIL_INT_ENBL    V_IBM_FDL_FAIL_INT_ENBL(1U)
14680 
14681 #define S_ARM_FAIL_INT_ENBL    24
14682 #define V_ARM_FAIL_INT_ENBL(x) ((x) << S_ARM_FAIL_INT_ENBL)
14683 #define F_ARM_FAIL_INT_ENBL    V_ARM_FAIL_INT_ENBL(1U)
14684 
14685 #define S_ARM_ERROR_OUT_INT_ENBL    23
14686 #define V_ARM_ERROR_OUT_INT_ENBL(x) ((x) << S_ARM_ERROR_OUT_INT_ENBL)
14687 #define F_ARM_ERROR_OUT_INT_ENBL    V_ARM_ERROR_OUT_INT_ENBL(1U)
14688 
14689 #define S_PLL_LOCK_LOST_INT_ENBL    22
14690 #define V_PLL_LOCK_LOST_INT_ENBL(x) ((x) << S_PLL_LOCK_LOST_INT_ENBL)
14691 #define F_PLL_LOCK_LOST_INT_ENBL    V_PLL_LOCK_LOST_INT_ENBL(1U)
14692 
14693 #define S_C_LOCK    21
14694 #define V_C_LOCK(x) ((x) << S_C_LOCK)
14695 #define F_C_LOCK    V_C_LOCK(1U)
14696 
14697 #define S_M_LOCK    20
14698 #define V_M_LOCK(x) ((x) << S_M_LOCK)
14699 #define F_M_LOCK    V_M_LOCK(1U)
14700 
14701 #define S_U_LOCK    19
14702 #define V_U_LOCK(x) ((x) << S_U_LOCK)
14703 #define F_U_LOCK    V_U_LOCK(1U)
14704 
14705 #define S_PCIE_LOCK    18
14706 #define V_PCIE_LOCK(x) ((x) << S_PCIE_LOCK)
14707 #define F_PCIE_LOCK    V_PCIE_LOCK(1U)
14708 
14709 #define S_KX_LOCK    17
14710 #define V_KX_LOCK(x) ((x) << S_KX_LOCK)
14711 #define F_KX_LOCK    V_KX_LOCK(1U)
14712 
14713 #define S_KR_LOCK    16
14714 #define V_KR_LOCK(x) ((x) << S_KR_LOCK)
14715 #define F_KR_LOCK    V_KR_LOCK(1U)
14716 
14717 #define S_GPIO15    15
14718 #define V_GPIO15(x) ((x) << S_GPIO15)
14719 #define F_GPIO15    V_GPIO15(1U)
14720 
14721 #define S_GPIO14    14
14722 #define V_GPIO14(x) ((x) << S_GPIO14)
14723 #define F_GPIO14    V_GPIO14(1U)
14724 
14725 #define S_GPIO13    13
14726 #define V_GPIO13(x) ((x) << S_GPIO13)
14727 #define F_GPIO13    V_GPIO13(1U)
14728 
14729 #define S_GPIO12    12
14730 #define V_GPIO12(x) ((x) << S_GPIO12)
14731 #define F_GPIO12    V_GPIO12(1U)
14732 
14733 #define S_GPIO11    11
14734 #define V_GPIO11(x) ((x) << S_GPIO11)
14735 #define F_GPIO11    V_GPIO11(1U)
14736 
14737 #define S_GPIO10    10
14738 #define V_GPIO10(x) ((x) << S_GPIO10)
14739 #define F_GPIO10    V_GPIO10(1U)
14740 
14741 #define S_GPIO9    9
14742 #define V_GPIO9(x) ((x) << S_GPIO9)
14743 #define F_GPIO9    V_GPIO9(1U)
14744 
14745 #define S_GPIO8    8
14746 #define V_GPIO8(x) ((x) << S_GPIO8)
14747 #define F_GPIO8    V_GPIO8(1U)
14748 
14749 #define S_GPIO7    7
14750 #define V_GPIO7(x) ((x) << S_GPIO7)
14751 #define F_GPIO7    V_GPIO7(1U)
14752 
14753 #define S_GPIO6    6
14754 #define V_GPIO6(x) ((x) << S_GPIO6)
14755 #define F_GPIO6    V_GPIO6(1U)
14756 
14757 #define S_GPIO5    5
14758 #define V_GPIO5(x) ((x) << S_GPIO5)
14759 #define F_GPIO5    V_GPIO5(1U)
14760 
14761 #define S_GPIO4    4
14762 #define V_GPIO4(x) ((x) << S_GPIO4)
14763 #define F_GPIO4    V_GPIO4(1U)
14764 
14765 #define S_GPIO3    3
14766 #define V_GPIO3(x) ((x) << S_GPIO3)
14767 #define F_GPIO3    V_GPIO3(1U)
14768 
14769 #define S_GPIO2    2
14770 #define V_GPIO2(x) ((x) << S_GPIO2)
14771 #define F_GPIO2    V_GPIO2(1U)
14772 
14773 #define S_GPIO1    1
14774 #define V_GPIO1(x) ((x) << S_GPIO1)
14775 #define F_GPIO1    V_GPIO1(1U)
14776 
14777 #define S_GPIO0    0
14778 #define V_GPIO0(x) ((x) << S_GPIO0)
14779 #define F_GPIO0    V_GPIO0(1U)
14780 
14781 #define S_GPIO19    29
14782 #define V_GPIO19(x) ((x) << S_GPIO19)
14783 #define F_GPIO19    V_GPIO19(1U)
14784 
14785 #define S_GPIO18    28
14786 #define V_GPIO18(x) ((x) << S_GPIO18)
14787 #define F_GPIO18    V_GPIO18(1U)
14788 
14789 #define S_GPIO17    27
14790 #define V_GPIO17(x) ((x) << S_GPIO17)
14791 #define F_GPIO17    V_GPIO17(1U)
14792 
14793 #define S_GPIO16    26
14794 #define V_GPIO16(x) ((x) << S_GPIO16)
14795 #define F_GPIO16    V_GPIO16(1U)
14796 
14797 #define S_USBFIFOPARERR    12
14798 #define V_USBFIFOPARERR(x) ((x) << S_USBFIFOPARERR)
14799 #define F_USBFIFOPARERR    V_USBFIFOPARERR(1U)
14800 
14801 #define S_T7_IBM_FDL_FAIL_INT_ENBL    11
14802 #define V_T7_IBM_FDL_FAIL_INT_ENBL(x) ((x) << S_T7_IBM_FDL_FAIL_INT_ENBL)
14803 #define F_T7_IBM_FDL_FAIL_INT_ENBL    V_T7_IBM_FDL_FAIL_INT_ENBL(1U)
14804 
14805 #define S_T7_PLL_LOCK_LOST_INT_ENBL    10
14806 #define V_T7_PLL_LOCK_LOST_INT_ENBL(x) ((x) << S_T7_PLL_LOCK_LOST_INT_ENBL)
14807 #define F_T7_PLL_LOCK_LOST_INT_ENBL    V_T7_PLL_LOCK_LOST_INT_ENBL(1U)
14808 
14809 #define S_M1_LOCK    9
14810 #define V_M1_LOCK(x) ((x) << S_M1_LOCK)
14811 #define F_M1_LOCK    V_M1_LOCK(1U)
14812 
14813 #define S_T7_PCIE_LOCK    8
14814 #define V_T7_PCIE_LOCK(x) ((x) << S_T7_PCIE_LOCK)
14815 #define F_T7_PCIE_LOCK    V_T7_PCIE_LOCK(1U)
14816 
14817 #define S_T7_U_LOCK    7
14818 #define V_T7_U_LOCK(x) ((x) << S_T7_U_LOCK)
14819 #define F_T7_U_LOCK    V_T7_U_LOCK(1U)
14820 
14821 #define S_MAC_LOCK    6
14822 #define V_MAC_LOCK(x) ((x) << S_MAC_LOCK)
14823 #define F_MAC_LOCK    V_MAC_LOCK(1U)
14824 
14825 #define S_ARM_LOCK    5
14826 #define V_ARM_LOCK(x) ((x) << S_ARM_LOCK)
14827 #define F_ARM_LOCK    V_ARM_LOCK(1U)
14828 
14829 #define S_M0_LOCK    4
14830 #define V_M0_LOCK(x) ((x) << S_M0_LOCK)
14831 #define F_M0_LOCK    V_M0_LOCK(1U)
14832 
14833 #define S_XGPBUS_LOCK    3
14834 #define V_XGPBUS_LOCK(x) ((x) << S_XGPBUS_LOCK)
14835 #define F_XGPBUS_LOCK    V_XGPBUS_LOCK(1U)
14836 
14837 #define S_XGPHY_LOCK    2
14838 #define V_XGPHY_LOCK(x) ((x) << S_XGPHY_LOCK)
14839 #define F_XGPHY_LOCK    V_XGPHY_LOCK(1U)
14840 
14841 #define S_USB_LOCK    1
14842 #define V_USB_LOCK(x) ((x) << S_USB_LOCK)
14843 #define F_USB_LOCK    V_USB_LOCK(1U)
14844 
14845 #define S_T7_C_LOCK    0
14846 #define V_T7_C_LOCK(x) ((x) << S_T7_C_LOCK)
14847 #define F_T7_C_LOCK    V_T7_C_LOCK(1U)
14848 
14849 #define A_DBG_INT_CAUSE 0x601c
14850 
14851 #define S_IBM_FDL_FAIL_INT_CAUSE    25
14852 #define V_IBM_FDL_FAIL_INT_CAUSE(x) ((x) << S_IBM_FDL_FAIL_INT_CAUSE)
14853 #define F_IBM_FDL_FAIL_INT_CAUSE    V_IBM_FDL_FAIL_INT_CAUSE(1U)
14854 
14855 #define S_ARM_FAIL_INT_CAUSE    24
14856 #define V_ARM_FAIL_INT_CAUSE(x) ((x) << S_ARM_FAIL_INT_CAUSE)
14857 #define F_ARM_FAIL_INT_CAUSE    V_ARM_FAIL_INT_CAUSE(1U)
14858 
14859 #define S_ARM_ERROR_OUT_INT_CAUSE    23
14860 #define V_ARM_ERROR_OUT_INT_CAUSE(x) ((x) << S_ARM_ERROR_OUT_INT_CAUSE)
14861 #define F_ARM_ERROR_OUT_INT_CAUSE    V_ARM_ERROR_OUT_INT_CAUSE(1U)
14862 
14863 #define S_PLL_LOCK_LOST_INT_CAUSE    22
14864 #define V_PLL_LOCK_LOST_INT_CAUSE(x) ((x) << S_PLL_LOCK_LOST_INT_CAUSE)
14865 #define F_PLL_LOCK_LOST_INT_CAUSE    V_PLL_LOCK_LOST_INT_CAUSE(1U)
14866 
14867 #define S_T7_IBM_FDL_FAIL_INT_CAUSE    11
14868 #define V_T7_IBM_FDL_FAIL_INT_CAUSE(x) ((x) << S_T7_IBM_FDL_FAIL_INT_CAUSE)
14869 #define F_T7_IBM_FDL_FAIL_INT_CAUSE    V_T7_IBM_FDL_FAIL_INT_CAUSE(1U)
14870 
14871 #define S_T7_PLL_LOCK_LOST_INT_CAUSE    10
14872 #define V_T7_PLL_LOCK_LOST_INT_CAUSE(x) ((x) << S_T7_PLL_LOCK_LOST_INT_CAUSE)
14873 #define F_T7_PLL_LOCK_LOST_INT_CAUSE    V_T7_PLL_LOCK_LOST_INT_CAUSE(1U)
14874 
14875 #define A_DBG_DBG0_RST_VALUE 0x6020
14876 
14877 #define S_DEBUGDATA    0
14878 #define M_DEBUGDATA    0xffffU
14879 #define V_DEBUGDATA(x) ((x) << S_DEBUGDATA)
14880 #define G_DEBUGDATA(x) (((x) >> S_DEBUGDATA) & M_DEBUGDATA)
14881 
14882 #define A_DBG_OVERWRSERCFG_EN 0x6024
14883 
14884 #define S_OVERWRSERCFG_EN    0
14885 #define V_OVERWRSERCFG_EN(x) ((x) << S_OVERWRSERCFG_EN)
14886 #define F_OVERWRSERCFG_EN    V_OVERWRSERCFG_EN(1U)
14887 
14888 #define A_DBG_PLL_OCLK_PAD_EN 0x6028
14889 
14890 #define S_PCIE_OCLK_EN    20
14891 #define V_PCIE_OCLK_EN(x) ((x) << S_PCIE_OCLK_EN)
14892 #define F_PCIE_OCLK_EN    V_PCIE_OCLK_EN(1U)
14893 
14894 #define S_KX_OCLK_EN    16
14895 #define V_KX_OCLK_EN(x) ((x) << S_KX_OCLK_EN)
14896 #define F_KX_OCLK_EN    V_KX_OCLK_EN(1U)
14897 
14898 #define S_U_OCLK_EN    12
14899 #define V_U_OCLK_EN(x) ((x) << S_U_OCLK_EN)
14900 #define F_U_OCLK_EN    V_U_OCLK_EN(1U)
14901 
14902 #define S_KR_OCLK_EN    8
14903 #define V_KR_OCLK_EN(x) ((x) << S_KR_OCLK_EN)
14904 #define F_KR_OCLK_EN    V_KR_OCLK_EN(1U)
14905 
14906 #define S_M_OCLK_EN    4
14907 #define V_M_OCLK_EN(x) ((x) << S_M_OCLK_EN)
14908 #define F_M_OCLK_EN    V_M_OCLK_EN(1U)
14909 
14910 #define S_C_OCLK_EN    0
14911 #define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN)
14912 #define F_C_OCLK_EN    V_C_OCLK_EN(1U)
14913 
14914 #define S_INIC_MODE_EN    0
14915 #define V_INIC_MODE_EN(x) ((x) << S_INIC_MODE_EN)
14916 #define F_INIC_MODE_EN    V_INIC_MODE_EN(1U)
14917 
14918 #define A_DBG_PLL_LOCK 0x602c
14919 
14920 #define S_PLL_P_LOCK    20
14921 #define V_PLL_P_LOCK(x) ((x) << S_PLL_P_LOCK)
14922 #define F_PLL_P_LOCK    V_PLL_P_LOCK(1U)
14923 
14924 #define S_PLL_KX_LOCK    16
14925 #define V_PLL_KX_LOCK(x) ((x) << S_PLL_KX_LOCK)
14926 #define F_PLL_KX_LOCK    V_PLL_KX_LOCK(1U)
14927 
14928 #define S_PLL_U_LOCK    12
14929 #define V_PLL_U_LOCK(x) ((x) << S_PLL_U_LOCK)
14930 #define F_PLL_U_LOCK    V_PLL_U_LOCK(1U)
14931 
14932 #define S_PLL_KR_LOCK    8
14933 #define V_PLL_KR_LOCK(x) ((x) << S_PLL_KR_LOCK)
14934 #define F_PLL_KR_LOCK    V_PLL_KR_LOCK(1U)
14935 
14936 #define S_PLL_M_LOCK    4
14937 #define V_PLL_M_LOCK(x) ((x) << S_PLL_M_LOCK)
14938 #define F_PLL_M_LOCK    V_PLL_M_LOCK(1U)
14939 
14940 #define S_PLL_C_LOCK    0
14941 #define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK)
14942 #define F_PLL_C_LOCK    V_PLL_C_LOCK(1U)
14943 
14944 #define S_T7_PLL_M_LOCK    9
14945 #define V_T7_PLL_M_LOCK(x) ((x) << S_T7_PLL_M_LOCK)
14946 #define F_T7_PLL_M_LOCK    V_T7_PLL_M_LOCK(1U)
14947 
14948 #define S_PLL_PCIE_LOCK    8
14949 #define V_PLL_PCIE_LOCK(x) ((x) << S_PLL_PCIE_LOCK)
14950 #define F_PLL_PCIE_LOCK    V_PLL_PCIE_LOCK(1U)
14951 
14952 #define S_T7_PLL_U_LOCK    7
14953 #define V_T7_PLL_U_LOCK(x) ((x) << S_T7_PLL_U_LOCK)
14954 #define F_T7_PLL_U_LOCK    V_T7_PLL_U_LOCK(1U)
14955 
14956 #define S_PLL_MAC_LOCK    6
14957 #define V_PLL_MAC_LOCK(x) ((x) << S_PLL_MAC_LOCK)
14958 #define F_PLL_MAC_LOCK    V_PLL_MAC_LOCK(1U)
14959 
14960 #define S_PLL_ARM_LOCK    5
14961 #define V_PLL_ARM_LOCK(x) ((x) << S_PLL_ARM_LOCK)
14962 #define F_PLL_ARM_LOCK    V_PLL_ARM_LOCK(1U)
14963 
14964 #define S_PLL_XGPBUS_LOCK    3
14965 #define V_PLL_XGPBUS_LOCK(x) ((x) << S_PLL_XGPBUS_LOCK)
14966 #define F_PLL_XGPBUS_LOCK    V_PLL_XGPBUS_LOCK(1U)
14967 
14968 #define S_PLL_XGPHY_LOCK    2
14969 #define V_PLL_XGPHY_LOCK(x) ((x) << S_PLL_XGPHY_LOCK)
14970 #define F_PLL_XGPHY_LOCK    V_PLL_XGPHY_LOCK(1U)
14971 
14972 #define S_PLL_USB_LOCK    1
14973 #define V_PLL_USB_LOCK(x) ((x) << S_PLL_USB_LOCK)
14974 #define F_PLL_USB_LOCK    V_PLL_USB_LOCK(1U)
14975 
14976 #define A_DBG_GPIO_ACT_LOW 0x6030
14977 
14978 #define S_P_LOCK_ACT_LOW    21
14979 #define V_P_LOCK_ACT_LOW(x) ((x) << S_P_LOCK_ACT_LOW)
14980 #define F_P_LOCK_ACT_LOW    V_P_LOCK_ACT_LOW(1U)
14981 
14982 #define S_C_LOCK_ACT_LOW    20
14983 #define V_C_LOCK_ACT_LOW(x) ((x) << S_C_LOCK_ACT_LOW)
14984 #define F_C_LOCK_ACT_LOW    V_C_LOCK_ACT_LOW(1U)
14985 
14986 #define S_M_LOCK_ACT_LOW    19
14987 #define V_M_LOCK_ACT_LOW(x) ((x) << S_M_LOCK_ACT_LOW)
14988 #define F_M_LOCK_ACT_LOW    V_M_LOCK_ACT_LOW(1U)
14989 
14990 #define S_U_LOCK_ACT_LOW    18
14991 #define V_U_LOCK_ACT_LOW(x) ((x) << S_U_LOCK_ACT_LOW)
14992 #define F_U_LOCK_ACT_LOW    V_U_LOCK_ACT_LOW(1U)
14993 
14994 #define S_KR_LOCK_ACT_LOW    17
14995 #define V_KR_LOCK_ACT_LOW(x) ((x) << S_KR_LOCK_ACT_LOW)
14996 #define F_KR_LOCK_ACT_LOW    V_KR_LOCK_ACT_LOW(1U)
14997 
14998 #define S_KX_LOCK_ACT_LOW    16
14999 #define V_KX_LOCK_ACT_LOW(x) ((x) << S_KX_LOCK_ACT_LOW)
15000 #define F_KX_LOCK_ACT_LOW    V_KX_LOCK_ACT_LOW(1U)
15001 
15002 #define S_GPIO15_ACT_LOW    15
15003 #define V_GPIO15_ACT_LOW(x) ((x) << S_GPIO15_ACT_LOW)
15004 #define F_GPIO15_ACT_LOW    V_GPIO15_ACT_LOW(1U)
15005 
15006 #define S_GPIO14_ACT_LOW    14
15007 #define V_GPIO14_ACT_LOW(x) ((x) << S_GPIO14_ACT_LOW)
15008 #define F_GPIO14_ACT_LOW    V_GPIO14_ACT_LOW(1U)
15009 
15010 #define S_GPIO13_ACT_LOW    13
15011 #define V_GPIO13_ACT_LOW(x) ((x) << S_GPIO13_ACT_LOW)
15012 #define F_GPIO13_ACT_LOW    V_GPIO13_ACT_LOW(1U)
15013 
15014 #define S_GPIO12_ACT_LOW    12
15015 #define V_GPIO12_ACT_LOW(x) ((x) << S_GPIO12_ACT_LOW)
15016 #define F_GPIO12_ACT_LOW    V_GPIO12_ACT_LOW(1U)
15017 
15018 #define S_GPIO11_ACT_LOW    11
15019 #define V_GPIO11_ACT_LOW(x) ((x) << S_GPIO11_ACT_LOW)
15020 #define F_GPIO11_ACT_LOW    V_GPIO11_ACT_LOW(1U)
15021 
15022 #define S_GPIO10_ACT_LOW    10
15023 #define V_GPIO10_ACT_LOW(x) ((x) << S_GPIO10_ACT_LOW)
15024 #define F_GPIO10_ACT_LOW    V_GPIO10_ACT_LOW(1U)
15025 
15026 #define S_GPIO9_ACT_LOW    9
15027 #define V_GPIO9_ACT_LOW(x) ((x) << S_GPIO9_ACT_LOW)
15028 #define F_GPIO9_ACT_LOW    V_GPIO9_ACT_LOW(1U)
15029 
15030 #define S_GPIO8_ACT_LOW    8
15031 #define V_GPIO8_ACT_LOW(x) ((x) << S_GPIO8_ACT_LOW)
15032 #define F_GPIO8_ACT_LOW    V_GPIO8_ACT_LOW(1U)
15033 
15034 #define S_GPIO7_ACT_LOW    7
15035 #define V_GPIO7_ACT_LOW(x) ((x) << S_GPIO7_ACT_LOW)
15036 #define F_GPIO7_ACT_LOW    V_GPIO7_ACT_LOW(1U)
15037 
15038 #define S_GPIO6_ACT_LOW    6
15039 #define V_GPIO6_ACT_LOW(x) ((x) << S_GPIO6_ACT_LOW)
15040 #define F_GPIO6_ACT_LOW    V_GPIO6_ACT_LOW(1U)
15041 
15042 #define S_GPIO5_ACT_LOW    5
15043 #define V_GPIO5_ACT_LOW(x) ((x) << S_GPIO5_ACT_LOW)
15044 #define F_GPIO5_ACT_LOW    V_GPIO5_ACT_LOW(1U)
15045 
15046 #define S_GPIO4_ACT_LOW    4
15047 #define V_GPIO4_ACT_LOW(x) ((x) << S_GPIO4_ACT_LOW)
15048 #define F_GPIO4_ACT_LOW    V_GPIO4_ACT_LOW(1U)
15049 
15050 #define S_GPIO3_ACT_LOW    3
15051 #define V_GPIO3_ACT_LOW(x) ((x) << S_GPIO3_ACT_LOW)
15052 #define F_GPIO3_ACT_LOW    V_GPIO3_ACT_LOW(1U)
15053 
15054 #define S_GPIO2_ACT_LOW    2
15055 #define V_GPIO2_ACT_LOW(x) ((x) << S_GPIO2_ACT_LOW)
15056 #define F_GPIO2_ACT_LOW    V_GPIO2_ACT_LOW(1U)
15057 
15058 #define S_GPIO1_ACT_LOW    1
15059 #define V_GPIO1_ACT_LOW(x) ((x) << S_GPIO1_ACT_LOW)
15060 #define F_GPIO1_ACT_LOW    V_GPIO1_ACT_LOW(1U)
15061 
15062 #define S_GPIO0_ACT_LOW    0
15063 #define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW)
15064 #define F_GPIO0_ACT_LOW    V_GPIO0_ACT_LOW(1U)
15065 
15066 #define S_GPIO19_ACT_LOW    25
15067 #define V_GPIO19_ACT_LOW(x) ((x) << S_GPIO19_ACT_LOW)
15068 #define F_GPIO19_ACT_LOW    V_GPIO19_ACT_LOW(1U)
15069 
15070 #define S_GPIO18_ACT_LOW    24
15071 #define V_GPIO18_ACT_LOW(x) ((x) << S_GPIO18_ACT_LOW)
15072 #define F_GPIO18_ACT_LOW    V_GPIO18_ACT_LOW(1U)
15073 
15074 #define S_GPIO17_ACT_LOW    23
15075 #define V_GPIO17_ACT_LOW(x) ((x) << S_GPIO17_ACT_LOW)
15076 #define F_GPIO17_ACT_LOW    V_GPIO17_ACT_LOW(1U)
15077 
15078 #define S_GPIO16_ACT_LOW    22
15079 #define V_GPIO16_ACT_LOW(x) ((x) << S_GPIO16_ACT_LOW)
15080 #define F_GPIO16_ACT_LOW    V_GPIO16_ACT_LOW(1U)
15081 
15082 #define A_DBG_PLL_LOCK_ACT_LOW 0x6030
15083 
15084 #define S_M1_LOCK_ACT_LOW    9
15085 #define V_M1_LOCK_ACT_LOW(x) ((x) << S_M1_LOCK_ACT_LOW)
15086 #define F_M1_LOCK_ACT_LOW    V_M1_LOCK_ACT_LOW(1U)
15087 
15088 #define S_PCIE_LOCK_ACT_LOW    8
15089 #define V_PCIE_LOCK_ACT_LOW(x) ((x) << S_PCIE_LOCK_ACT_LOW)
15090 #define F_PCIE_LOCK_ACT_LOW    V_PCIE_LOCK_ACT_LOW(1U)
15091 
15092 #define S_T7_U_LOCK_ACT_LOW    7
15093 #define V_T7_U_LOCK_ACT_LOW(x) ((x) << S_T7_U_LOCK_ACT_LOW)
15094 #define F_T7_U_LOCK_ACT_LOW    V_T7_U_LOCK_ACT_LOW(1U)
15095 
15096 #define S_MAC_LOCK_ACT_LOW    6
15097 #define V_MAC_LOCK_ACT_LOW(x) ((x) << S_MAC_LOCK_ACT_LOW)
15098 #define F_MAC_LOCK_ACT_LOW    V_MAC_LOCK_ACT_LOW(1U)
15099 
15100 #define S_ARM_LOCK_ACT_LOW    5
15101 #define V_ARM_LOCK_ACT_LOW(x) ((x) << S_ARM_LOCK_ACT_LOW)
15102 #define F_ARM_LOCK_ACT_LOW    V_ARM_LOCK_ACT_LOW(1U)
15103 
15104 #define S_M0_LOCK_ACT_LOW    4
15105 #define V_M0_LOCK_ACT_LOW(x) ((x) << S_M0_LOCK_ACT_LOW)
15106 #define F_M0_LOCK_ACT_LOW    V_M0_LOCK_ACT_LOW(1U)
15107 
15108 #define S_XGPBUS_LOCK_ACT_LOW    3
15109 #define V_XGPBUS_LOCK_ACT_LOW(x) ((x) << S_XGPBUS_LOCK_ACT_LOW)
15110 #define F_XGPBUS_LOCK_ACT_LOW    V_XGPBUS_LOCK_ACT_LOW(1U)
15111 
15112 #define S_XGPHY_LOCK_ACT_LOW    2
15113 #define V_XGPHY_LOCK_ACT_LOW(x) ((x) << S_XGPHY_LOCK_ACT_LOW)
15114 #define F_XGPHY_LOCK_ACT_LOW    V_XGPHY_LOCK_ACT_LOW(1U)
15115 
15116 #define S_USB_LOCK_ACT_LOW    1
15117 #define V_USB_LOCK_ACT_LOW(x) ((x) << S_USB_LOCK_ACT_LOW)
15118 #define F_USB_LOCK_ACT_LOW    V_USB_LOCK_ACT_LOW(1U)
15119 
15120 #define S_T7_C_LOCK_ACT_LOW    0
15121 #define V_T7_C_LOCK_ACT_LOW(x) ((x) << S_T7_C_LOCK_ACT_LOW)
15122 #define F_T7_C_LOCK_ACT_LOW    V_T7_C_LOCK_ACT_LOW(1U)
15123 
15124 #define A_DBG_EFUSE_BYTE0_3 0x6034
15125 #define A_DBG_EFUSE_BYTE4_7 0x6038
15126 #define A_DBG_EFUSE_BYTE8_11 0x603c
15127 #define A_DBG_EFUSE_BYTE12_15 0x6040
15128 #define A_DBG_STATIC_U_PLL_CONF 0x6044
15129 
15130 #define S_STATIC_U_PLL_MULT    23
15131 #define M_STATIC_U_PLL_MULT    0x1ffU
15132 #define V_STATIC_U_PLL_MULT(x) ((x) << S_STATIC_U_PLL_MULT)
15133 #define G_STATIC_U_PLL_MULT(x) (((x) >> S_STATIC_U_PLL_MULT) & M_STATIC_U_PLL_MULT)
15134 
15135 #define S_STATIC_U_PLL_PREDIV    18
15136 #define M_STATIC_U_PLL_PREDIV    0x1fU
15137 #define V_STATIC_U_PLL_PREDIV(x) ((x) << S_STATIC_U_PLL_PREDIV)
15138 #define G_STATIC_U_PLL_PREDIV(x) (((x) >> S_STATIC_U_PLL_PREDIV) & M_STATIC_U_PLL_PREDIV)
15139 
15140 #define S_STATIC_U_PLL_RANGEA    14
15141 #define M_STATIC_U_PLL_RANGEA    0xfU
15142 #define V_STATIC_U_PLL_RANGEA(x) ((x) << S_STATIC_U_PLL_RANGEA)
15143 #define G_STATIC_U_PLL_RANGEA(x) (((x) >> S_STATIC_U_PLL_RANGEA) & M_STATIC_U_PLL_RANGEA)
15144 
15145 #define S_STATIC_U_PLL_RANGEB    10
15146 #define M_STATIC_U_PLL_RANGEB    0xfU
15147 #define V_STATIC_U_PLL_RANGEB(x) ((x) << S_STATIC_U_PLL_RANGEB)
15148 #define G_STATIC_U_PLL_RANGEB(x) (((x) >> S_STATIC_U_PLL_RANGEB) & M_STATIC_U_PLL_RANGEB)
15149 
15150 #define S_STATIC_U_PLL_TUNE    0
15151 #define M_STATIC_U_PLL_TUNE    0x3ffU
15152 #define V_STATIC_U_PLL_TUNE(x) ((x) << S_STATIC_U_PLL_TUNE)
15153 #define G_STATIC_U_PLL_TUNE(x) (((x) >> S_STATIC_U_PLL_TUNE) & M_STATIC_U_PLL_TUNE)
15154 
15155 #define A_T7_DBG_STATIC_U_PLL_CONF1 0x6044
15156 
15157 #define S_STATIC_U_PLL_RANGE    22
15158 #define M_STATIC_U_PLL_RANGE    0x7U
15159 #define V_STATIC_U_PLL_RANGE(x) ((x) << S_STATIC_U_PLL_RANGE)
15160 #define G_STATIC_U_PLL_RANGE(x) (((x) >> S_STATIC_U_PLL_RANGE) & M_STATIC_U_PLL_RANGE)
15161 
15162 #define S_STATIC_U_PLL_DIVQ    17
15163 #define M_STATIC_U_PLL_DIVQ    0x1fU
15164 #define V_STATIC_U_PLL_DIVQ(x) ((x) << S_STATIC_U_PLL_DIVQ)
15165 #define G_STATIC_U_PLL_DIVQ(x) (((x) >> S_STATIC_U_PLL_DIVQ) & M_STATIC_U_PLL_DIVQ)
15166 
15167 #define S_STATIC_U_PLL_DIVFI    8
15168 #define M_STATIC_U_PLL_DIVFI    0x1ffU
15169 #define V_STATIC_U_PLL_DIVFI(x) ((x) << S_STATIC_U_PLL_DIVFI)
15170 #define G_STATIC_U_PLL_DIVFI(x) (((x) >> S_STATIC_U_PLL_DIVFI) & M_STATIC_U_PLL_DIVFI)
15171 
15172 #define S_STATIC_U_PLL_DIVR    2
15173 #define M_STATIC_U_PLL_DIVR    0x3fU
15174 #define V_STATIC_U_PLL_DIVR(x) ((x) << S_STATIC_U_PLL_DIVR)
15175 #define G_STATIC_U_PLL_DIVR(x) (((x) >> S_STATIC_U_PLL_DIVR) & M_STATIC_U_PLL_DIVR)
15176 
15177 #define S_T7_1_STATIC_U_PLL_BYPASS    1
15178 #define V_T7_1_STATIC_U_PLL_BYPASS(x) ((x) << S_T7_1_STATIC_U_PLL_BYPASS)
15179 #define F_T7_1_STATIC_U_PLL_BYPASS    V_T7_1_STATIC_U_PLL_BYPASS(1U)
15180 
15181 #define A_DBG_STATIC_C_PLL_CONF 0x6048
15182 
15183 #define S_STATIC_C_PLL_MULT    23
15184 #define M_STATIC_C_PLL_MULT    0x1ffU
15185 #define V_STATIC_C_PLL_MULT(x) ((x) << S_STATIC_C_PLL_MULT)
15186 #define G_STATIC_C_PLL_MULT(x) (((x) >> S_STATIC_C_PLL_MULT) & M_STATIC_C_PLL_MULT)
15187 
15188 #define S_STATIC_C_PLL_PREDIV    18
15189 #define M_STATIC_C_PLL_PREDIV    0x1fU
15190 #define V_STATIC_C_PLL_PREDIV(x) ((x) << S_STATIC_C_PLL_PREDIV)
15191 #define G_STATIC_C_PLL_PREDIV(x) (((x) >> S_STATIC_C_PLL_PREDIV) & M_STATIC_C_PLL_PREDIV)
15192 
15193 #define S_STATIC_C_PLL_RANGEA    14
15194 #define M_STATIC_C_PLL_RANGEA    0xfU
15195 #define V_STATIC_C_PLL_RANGEA(x) ((x) << S_STATIC_C_PLL_RANGEA)
15196 #define G_STATIC_C_PLL_RANGEA(x) (((x) >> S_STATIC_C_PLL_RANGEA) & M_STATIC_C_PLL_RANGEA)
15197 
15198 #define S_STATIC_C_PLL_RANGEB    10
15199 #define M_STATIC_C_PLL_RANGEB    0xfU
15200 #define V_STATIC_C_PLL_RANGEB(x) ((x) << S_STATIC_C_PLL_RANGEB)
15201 #define G_STATIC_C_PLL_RANGEB(x) (((x) >> S_STATIC_C_PLL_RANGEB) & M_STATIC_C_PLL_RANGEB)
15202 
15203 #define S_STATIC_C_PLL_TUNE    0
15204 #define M_STATIC_C_PLL_TUNE    0x3ffU
15205 #define V_STATIC_C_PLL_TUNE(x) ((x) << S_STATIC_C_PLL_TUNE)
15206 #define G_STATIC_C_PLL_TUNE(x) (((x) >> S_STATIC_C_PLL_TUNE) & M_STATIC_C_PLL_TUNE)
15207 
15208 #define A_T7_DBG_STATIC_U_PLL_CONF2 0x6048
15209 
15210 #define S_STATIC_U_PLL_SSMF    5
15211 #define M_STATIC_U_PLL_SSMF    0xfU
15212 #define V_STATIC_U_PLL_SSMF(x) ((x) << S_STATIC_U_PLL_SSMF)
15213 #define G_STATIC_U_PLL_SSMF(x) (((x) >> S_STATIC_U_PLL_SSMF) & M_STATIC_U_PLL_SSMF)
15214 
15215 #define S_STATIC_U_PLL_SSMD    2
15216 #define M_STATIC_U_PLL_SSMD    0x7U
15217 #define V_STATIC_U_PLL_SSMD(x) ((x) << S_STATIC_U_PLL_SSMD)
15218 #define G_STATIC_U_PLL_SSMD(x) (((x) >> S_STATIC_U_PLL_SSMD) & M_STATIC_U_PLL_SSMD)
15219 
15220 #define S_STATIC_U_PLL_SSDS    1
15221 #define V_STATIC_U_PLL_SSDS(x) ((x) << S_STATIC_U_PLL_SSDS)
15222 #define F_STATIC_U_PLL_SSDS    V_STATIC_U_PLL_SSDS(1U)
15223 
15224 #define S_STATIC_U_PLL_SSE    0
15225 #define V_STATIC_U_PLL_SSE(x) ((x) << S_STATIC_U_PLL_SSE)
15226 #define F_STATIC_U_PLL_SSE    V_STATIC_U_PLL_SSE(1U)
15227 
15228 #define A_DBG_STATIC_M_PLL_CONF 0x604c
15229 
15230 #define S_STATIC_M_PLL_MULT    23
15231 #define M_STATIC_M_PLL_MULT    0x1ffU
15232 #define V_STATIC_M_PLL_MULT(x) ((x) << S_STATIC_M_PLL_MULT)
15233 #define G_STATIC_M_PLL_MULT(x) (((x) >> S_STATIC_M_PLL_MULT) & M_STATIC_M_PLL_MULT)
15234 
15235 #define S_STATIC_M_PLL_PREDIV    18
15236 #define M_STATIC_M_PLL_PREDIV    0x1fU
15237 #define V_STATIC_M_PLL_PREDIV(x) ((x) << S_STATIC_M_PLL_PREDIV)
15238 #define G_STATIC_M_PLL_PREDIV(x) (((x) >> S_STATIC_M_PLL_PREDIV) & M_STATIC_M_PLL_PREDIV)
15239 
15240 #define S_STATIC_M_PLL_RANGEA    14
15241 #define M_STATIC_M_PLL_RANGEA    0xfU
15242 #define V_STATIC_M_PLL_RANGEA(x) ((x) << S_STATIC_M_PLL_RANGEA)
15243 #define G_STATIC_M_PLL_RANGEA(x) (((x) >> S_STATIC_M_PLL_RANGEA) & M_STATIC_M_PLL_RANGEA)
15244 
15245 #define S_STATIC_M_PLL_RANGEB    10
15246 #define M_STATIC_M_PLL_RANGEB    0xfU
15247 #define V_STATIC_M_PLL_RANGEB(x) ((x) << S_STATIC_M_PLL_RANGEB)
15248 #define G_STATIC_M_PLL_RANGEB(x) (((x) >> S_STATIC_M_PLL_RANGEB) & M_STATIC_M_PLL_RANGEB)
15249 
15250 #define S_STATIC_M_PLL_TUNE    0
15251 #define M_STATIC_M_PLL_TUNE    0x3ffU
15252 #define V_STATIC_M_PLL_TUNE(x) ((x) << S_STATIC_M_PLL_TUNE)
15253 #define G_STATIC_M_PLL_TUNE(x) (((x) >> S_STATIC_M_PLL_TUNE) & M_STATIC_M_PLL_TUNE)
15254 
15255 #define A_T7_DBG_STATIC_C_PLL_CONF1 0x604c
15256 
15257 #define S_STATIC_C_PLL_RANGE    22
15258 #define M_STATIC_C_PLL_RANGE    0x7U
15259 #define V_STATIC_C_PLL_RANGE(x) ((x) << S_STATIC_C_PLL_RANGE)
15260 #define G_STATIC_C_PLL_RANGE(x) (((x) >> S_STATIC_C_PLL_RANGE) & M_STATIC_C_PLL_RANGE)
15261 
15262 #define S_STATIC_C_PLL_DIVQ    17
15263 #define M_STATIC_C_PLL_DIVQ    0x1fU
15264 #define V_STATIC_C_PLL_DIVQ(x) ((x) << S_STATIC_C_PLL_DIVQ)
15265 #define G_STATIC_C_PLL_DIVQ(x) (((x) >> S_STATIC_C_PLL_DIVQ) & M_STATIC_C_PLL_DIVQ)
15266 
15267 #define S_STATIC_C_PLL_DIVFI    8
15268 #define M_STATIC_C_PLL_DIVFI    0x1ffU
15269 #define V_STATIC_C_PLL_DIVFI(x) ((x) << S_STATIC_C_PLL_DIVFI)
15270 #define G_STATIC_C_PLL_DIVFI(x) (((x) >> S_STATIC_C_PLL_DIVFI) & M_STATIC_C_PLL_DIVFI)
15271 
15272 #define S_STATIC_C_PLL_DIVR    2
15273 #define M_STATIC_C_PLL_DIVR    0x3fU
15274 #define V_STATIC_C_PLL_DIVR(x) ((x) << S_STATIC_C_PLL_DIVR)
15275 #define G_STATIC_C_PLL_DIVR(x) (((x) >> S_STATIC_C_PLL_DIVR) & M_STATIC_C_PLL_DIVR)
15276 
15277 #define S_T7_1_STATIC_C_PLL_BYPASS    1
15278 #define V_T7_1_STATIC_C_PLL_BYPASS(x) ((x) << S_T7_1_STATIC_C_PLL_BYPASS)
15279 #define F_T7_1_STATIC_C_PLL_BYPASS    V_T7_1_STATIC_C_PLL_BYPASS(1U)
15280 
15281 #define A_DBG_STATIC_KX_PLL_CONF 0x6050
15282 
15283 #define S_STATIC_KX_PLL_C    21
15284 #define M_STATIC_KX_PLL_C    0xffU
15285 #define V_STATIC_KX_PLL_C(x) ((x) << S_STATIC_KX_PLL_C)
15286 #define G_STATIC_KX_PLL_C(x) (((x) >> S_STATIC_KX_PLL_C) & M_STATIC_KX_PLL_C)
15287 
15288 #define S_STATIC_KX_PLL_M    15
15289 #define M_STATIC_KX_PLL_M    0x3fU
15290 #define V_STATIC_KX_PLL_M(x) ((x) << S_STATIC_KX_PLL_M)
15291 #define G_STATIC_KX_PLL_M(x) (((x) >> S_STATIC_KX_PLL_M) & M_STATIC_KX_PLL_M)
15292 
15293 #define S_STATIC_KX_PLL_N1    11
15294 #define M_STATIC_KX_PLL_N1    0xfU
15295 #define V_STATIC_KX_PLL_N1(x) ((x) << S_STATIC_KX_PLL_N1)
15296 #define G_STATIC_KX_PLL_N1(x) (((x) >> S_STATIC_KX_PLL_N1) & M_STATIC_KX_PLL_N1)
15297 
15298 #define S_STATIC_KX_PLL_N2    7
15299 #define M_STATIC_KX_PLL_N2    0xfU
15300 #define V_STATIC_KX_PLL_N2(x) ((x) << S_STATIC_KX_PLL_N2)
15301 #define G_STATIC_KX_PLL_N2(x) (((x) >> S_STATIC_KX_PLL_N2) & M_STATIC_KX_PLL_N2)
15302 
15303 #define S_STATIC_KX_PLL_N3    3
15304 #define M_STATIC_KX_PLL_N3    0xfU
15305 #define V_STATIC_KX_PLL_N3(x) ((x) << S_STATIC_KX_PLL_N3)
15306 #define G_STATIC_KX_PLL_N3(x) (((x) >> S_STATIC_KX_PLL_N3) & M_STATIC_KX_PLL_N3)
15307 
15308 #define S_STATIC_KX_PLL_P    0
15309 #define M_STATIC_KX_PLL_P    0x7U
15310 #define V_STATIC_KX_PLL_P(x) ((x) << S_STATIC_KX_PLL_P)
15311 #define G_STATIC_KX_PLL_P(x) (((x) >> S_STATIC_KX_PLL_P) & M_STATIC_KX_PLL_P)
15312 
15313 #define A_T7_DBG_STATIC_C_PLL_CONF2 0x6050
15314 
15315 #define S_STATIC_C_PLL_SSMF    5
15316 #define M_STATIC_C_PLL_SSMF    0xfU
15317 #define V_STATIC_C_PLL_SSMF(x) ((x) << S_STATIC_C_PLL_SSMF)
15318 #define G_STATIC_C_PLL_SSMF(x) (((x) >> S_STATIC_C_PLL_SSMF) & M_STATIC_C_PLL_SSMF)
15319 
15320 #define S_STATIC_C_PLL_SSMD    2
15321 #define M_STATIC_C_PLL_SSMD    0x7U
15322 #define V_STATIC_C_PLL_SSMD(x) ((x) << S_STATIC_C_PLL_SSMD)
15323 #define G_STATIC_C_PLL_SSMD(x) (((x) >> S_STATIC_C_PLL_SSMD) & M_STATIC_C_PLL_SSMD)
15324 
15325 #define S_STATIC_C_PLL_SSDS    1
15326 #define V_STATIC_C_PLL_SSDS(x) ((x) << S_STATIC_C_PLL_SSDS)
15327 #define F_STATIC_C_PLL_SSDS    V_STATIC_C_PLL_SSDS(1U)
15328 
15329 #define S_STATIC_C_PLL_SSE    0
15330 #define V_STATIC_C_PLL_SSE(x) ((x) << S_STATIC_C_PLL_SSE)
15331 #define F_STATIC_C_PLL_SSE    V_STATIC_C_PLL_SSE(1U)
15332 
15333 #define A_DBG_STATIC_KR_PLL_CONF 0x6054
15334 
15335 #define S_STATIC_KR_PLL_C    21
15336 #define M_STATIC_KR_PLL_C    0xffU
15337 #define V_STATIC_KR_PLL_C(x) ((x) << S_STATIC_KR_PLL_C)
15338 #define G_STATIC_KR_PLL_C(x) (((x) >> S_STATIC_KR_PLL_C) & M_STATIC_KR_PLL_C)
15339 
15340 #define S_STATIC_KR_PLL_M    15
15341 #define M_STATIC_KR_PLL_M    0x3fU
15342 #define V_STATIC_KR_PLL_M(x) ((x) << S_STATIC_KR_PLL_M)
15343 #define G_STATIC_KR_PLL_M(x) (((x) >> S_STATIC_KR_PLL_M) & M_STATIC_KR_PLL_M)
15344 
15345 #define S_STATIC_KR_PLL_N1    11
15346 #define M_STATIC_KR_PLL_N1    0xfU
15347 #define V_STATIC_KR_PLL_N1(x) ((x) << S_STATIC_KR_PLL_N1)
15348 #define G_STATIC_KR_PLL_N1(x) (((x) >> S_STATIC_KR_PLL_N1) & M_STATIC_KR_PLL_N1)
15349 
15350 #define S_STATIC_KR_PLL_N2    7
15351 #define M_STATIC_KR_PLL_N2    0xfU
15352 #define V_STATIC_KR_PLL_N2(x) ((x) << S_STATIC_KR_PLL_N2)
15353 #define G_STATIC_KR_PLL_N2(x) (((x) >> S_STATIC_KR_PLL_N2) & M_STATIC_KR_PLL_N2)
15354 
15355 #define S_STATIC_KR_PLL_N3    3
15356 #define M_STATIC_KR_PLL_N3    0xfU
15357 #define V_STATIC_KR_PLL_N3(x) ((x) << S_STATIC_KR_PLL_N3)
15358 #define G_STATIC_KR_PLL_N3(x) (((x) >> S_STATIC_KR_PLL_N3) & M_STATIC_KR_PLL_N3)
15359 
15360 #define S_STATIC_KR_PLL_P    0
15361 #define M_STATIC_KR_PLL_P    0x7U
15362 #define V_STATIC_KR_PLL_P(x) ((x) << S_STATIC_KR_PLL_P)
15363 #define G_STATIC_KR_PLL_P(x) (((x) >> S_STATIC_KR_PLL_P) & M_STATIC_KR_PLL_P)
15364 
15365 #define A_DBG_STATIC_PLL_DFS_CONF 0x6054
15366 
15367 #define S_STATIC_U_DFS_ACK    23
15368 #define V_STATIC_U_DFS_ACK(x) ((x) << S_STATIC_U_DFS_ACK)
15369 #define F_STATIC_U_DFS_ACK    V_STATIC_U_DFS_ACK(1U)
15370 
15371 #define S_STATIC_C_DFS_ACK    22
15372 #define V_STATIC_C_DFS_ACK(x) ((x) << S_STATIC_C_DFS_ACK)
15373 #define F_STATIC_C_DFS_ACK    V_STATIC_C_DFS_ACK(1U)
15374 
15375 #define S_STATIC_U_DFS_DIVFI    13
15376 #define M_STATIC_U_DFS_DIVFI    0x1ffU
15377 #define V_STATIC_U_DFS_DIVFI(x) ((x) << S_STATIC_U_DFS_DIVFI)
15378 #define G_STATIC_U_DFS_DIVFI(x) (((x) >> S_STATIC_U_DFS_DIVFI) & M_STATIC_U_DFS_DIVFI)
15379 
15380 #define S_STATIC_U_DFS_NEWDIV    12
15381 #define V_STATIC_U_DFS_NEWDIV(x) ((x) << S_STATIC_U_DFS_NEWDIV)
15382 #define F_STATIC_U_DFS_NEWDIV    V_STATIC_U_DFS_NEWDIV(1U)
15383 
15384 #define S_T7_STATIC_U_DFS_ENABLE    11
15385 #define V_T7_STATIC_U_DFS_ENABLE(x) ((x) << S_T7_STATIC_U_DFS_ENABLE)
15386 #define F_T7_STATIC_U_DFS_ENABLE    V_T7_STATIC_U_DFS_ENABLE(1U)
15387 
15388 #define S_STATIC_C_DFS_DIVFI    2
15389 #define M_STATIC_C_DFS_DIVFI    0x1ffU
15390 #define V_STATIC_C_DFS_DIVFI(x) ((x) << S_STATIC_C_DFS_DIVFI)
15391 #define G_STATIC_C_DFS_DIVFI(x) (((x) >> S_STATIC_C_DFS_DIVFI) & M_STATIC_C_DFS_DIVFI)
15392 
15393 #define S_STATIC_C_DFS_NEWDIV    1
15394 #define V_STATIC_C_DFS_NEWDIV(x) ((x) << S_STATIC_C_DFS_NEWDIV)
15395 #define F_STATIC_C_DFS_NEWDIV    V_STATIC_C_DFS_NEWDIV(1U)
15396 
15397 #define A_DBG_EXTRA_STATIC_BITS_CONF 0x6058
15398 
15399 #define S_STATIC_M_PLL_RESET    30
15400 #define V_STATIC_M_PLL_RESET(x) ((x) << S_STATIC_M_PLL_RESET)
15401 #define F_STATIC_M_PLL_RESET    V_STATIC_M_PLL_RESET(1U)
15402 
15403 #define S_STATIC_M_PLL_SLEEP    29
15404 #define V_STATIC_M_PLL_SLEEP(x) ((x) << S_STATIC_M_PLL_SLEEP)
15405 #define F_STATIC_M_PLL_SLEEP    V_STATIC_M_PLL_SLEEP(1U)
15406 
15407 #define S_STATIC_M_PLL_BYPASS    28
15408 #define V_STATIC_M_PLL_BYPASS(x) ((x) << S_STATIC_M_PLL_BYPASS)
15409 #define F_STATIC_M_PLL_BYPASS    V_STATIC_M_PLL_BYPASS(1U)
15410 
15411 #define S_STATIC_MPLL_CLK_SEL    27
15412 #define V_STATIC_MPLL_CLK_SEL(x) ((x) << S_STATIC_MPLL_CLK_SEL)
15413 #define F_STATIC_MPLL_CLK_SEL    V_STATIC_MPLL_CLK_SEL(1U)
15414 
15415 #define S_STATIC_U_PLL_SLEEP    26
15416 #define V_STATIC_U_PLL_SLEEP(x) ((x) << S_STATIC_U_PLL_SLEEP)
15417 #define F_STATIC_U_PLL_SLEEP    V_STATIC_U_PLL_SLEEP(1U)
15418 
15419 #define S_STATIC_C_PLL_SLEEP    25
15420 #define V_STATIC_C_PLL_SLEEP(x) ((x) << S_STATIC_C_PLL_SLEEP)
15421 #define F_STATIC_C_PLL_SLEEP    V_STATIC_C_PLL_SLEEP(1U)
15422 
15423 #define S_STATIC_LVDS_CLKOUT_SEL    23
15424 #define M_STATIC_LVDS_CLKOUT_SEL    0x3U
15425 #define V_STATIC_LVDS_CLKOUT_SEL(x) ((x) << S_STATIC_LVDS_CLKOUT_SEL)
15426 #define G_STATIC_LVDS_CLKOUT_SEL(x) (((x) >> S_STATIC_LVDS_CLKOUT_SEL) & M_STATIC_LVDS_CLKOUT_SEL)
15427 
15428 #define S_STATIC_LVDS_CLKOUT_EN    22
15429 #define V_STATIC_LVDS_CLKOUT_EN(x) ((x) << S_STATIC_LVDS_CLKOUT_EN)
15430 #define F_STATIC_LVDS_CLKOUT_EN    V_STATIC_LVDS_CLKOUT_EN(1U)
15431 
15432 #define S_STATIC_CCLK_FREQ_SEL    20
15433 #define M_STATIC_CCLK_FREQ_SEL    0x3U
15434 #define V_STATIC_CCLK_FREQ_SEL(x) ((x) << S_STATIC_CCLK_FREQ_SEL)
15435 #define G_STATIC_CCLK_FREQ_SEL(x) (((x) >> S_STATIC_CCLK_FREQ_SEL) & M_STATIC_CCLK_FREQ_SEL)
15436 
15437 #define S_STATIC_UCLK_FREQ_SEL    18
15438 #define M_STATIC_UCLK_FREQ_SEL    0x3U
15439 #define V_STATIC_UCLK_FREQ_SEL(x) ((x) << S_STATIC_UCLK_FREQ_SEL)
15440 #define G_STATIC_UCLK_FREQ_SEL(x) (((x) >> S_STATIC_UCLK_FREQ_SEL) & M_STATIC_UCLK_FREQ_SEL)
15441 
15442 #define S_EXPHYCLK_SEL_EN    17
15443 #define V_EXPHYCLK_SEL_EN(x) ((x) << S_EXPHYCLK_SEL_EN)
15444 #define F_EXPHYCLK_SEL_EN    V_EXPHYCLK_SEL_EN(1U)
15445 
15446 #define S_EXPHYCLK_SEL    15
15447 #define M_EXPHYCLK_SEL    0x3U
15448 #define V_EXPHYCLK_SEL(x) ((x) << S_EXPHYCLK_SEL)
15449 #define G_EXPHYCLK_SEL(x) (((x) >> S_EXPHYCLK_SEL) & M_EXPHYCLK_SEL)
15450 
15451 #define S_STATIC_U_PLL_BYPASS    14
15452 #define V_STATIC_U_PLL_BYPASS(x) ((x) << S_STATIC_U_PLL_BYPASS)
15453 #define F_STATIC_U_PLL_BYPASS    V_STATIC_U_PLL_BYPASS(1U)
15454 
15455 #define S_STATIC_C_PLL_BYPASS    13
15456 #define V_STATIC_C_PLL_BYPASS(x) ((x) << S_STATIC_C_PLL_BYPASS)
15457 #define F_STATIC_C_PLL_BYPASS    V_STATIC_C_PLL_BYPASS(1U)
15458 
15459 #define S_STATIC_KR_PLL_BYPASS    12
15460 #define V_STATIC_KR_PLL_BYPASS(x) ((x) << S_STATIC_KR_PLL_BYPASS)
15461 #define F_STATIC_KR_PLL_BYPASS    V_STATIC_KR_PLL_BYPASS(1U)
15462 
15463 #define S_STATIC_KX_PLL_BYPASS    11
15464 #define V_STATIC_KX_PLL_BYPASS(x) ((x) << S_STATIC_KX_PLL_BYPASS)
15465 #define F_STATIC_KX_PLL_BYPASS    V_STATIC_KX_PLL_BYPASS(1U)
15466 
15467 #define S_STATIC_KX_PLL_V    7
15468 #define M_STATIC_KX_PLL_V    0xfU
15469 #define V_STATIC_KX_PLL_V(x) ((x) << S_STATIC_KX_PLL_V)
15470 #define G_STATIC_KX_PLL_V(x) (((x) >> S_STATIC_KX_PLL_V) & M_STATIC_KX_PLL_V)
15471 
15472 #define S_STATIC_KR_PLL_V    3
15473 #define M_STATIC_KR_PLL_V    0xfU
15474 #define V_STATIC_KR_PLL_V(x) ((x) << S_STATIC_KR_PLL_V)
15475 #define G_STATIC_KR_PLL_V(x) (((x) >> S_STATIC_KR_PLL_V) & M_STATIC_KR_PLL_V)
15476 
15477 #define S_PSRO_SEL    0
15478 #define M_PSRO_SEL    0x7U
15479 #define V_PSRO_SEL(x) ((x) << S_PSRO_SEL)
15480 #define G_PSRO_SEL(x) (((x) >> S_PSRO_SEL) & M_PSRO_SEL)
15481 
15482 #define S_T7_STATIC_LVDS_CLKOUT_EN    21
15483 #define V_T7_STATIC_LVDS_CLKOUT_EN(x) ((x) << S_T7_STATIC_LVDS_CLKOUT_EN)
15484 #define F_T7_STATIC_LVDS_CLKOUT_EN    V_T7_STATIC_LVDS_CLKOUT_EN(1U)
15485 
15486 #define S_T7_EXPHYCLK_SEL_EN    16
15487 #define V_T7_EXPHYCLK_SEL_EN(x) ((x) << S_T7_EXPHYCLK_SEL_EN)
15488 #define F_T7_EXPHYCLK_SEL_EN    V_T7_EXPHYCLK_SEL_EN(1U)
15489 
15490 #define A_DBG_STATIC_OCLK_MUXSEL_CONF 0x605c
15491 
15492 #define S_M_OCLK_MUXSEL    12
15493 #define V_M_OCLK_MUXSEL(x) ((x) << S_M_OCLK_MUXSEL)
15494 #define F_M_OCLK_MUXSEL    V_M_OCLK_MUXSEL(1U)
15495 
15496 #define S_C_OCLK_MUXSEL    10
15497 #define M_C_OCLK_MUXSEL    0x3U
15498 #define V_C_OCLK_MUXSEL(x) ((x) << S_C_OCLK_MUXSEL)
15499 #define G_C_OCLK_MUXSEL(x) (((x) >> S_C_OCLK_MUXSEL) & M_C_OCLK_MUXSEL)
15500 
15501 #define S_U_OCLK_MUXSEL    8
15502 #define M_U_OCLK_MUXSEL    0x3U
15503 #define V_U_OCLK_MUXSEL(x) ((x) << S_U_OCLK_MUXSEL)
15504 #define G_U_OCLK_MUXSEL(x) (((x) >> S_U_OCLK_MUXSEL) & M_U_OCLK_MUXSEL)
15505 
15506 #define S_P_OCLK_MUXSEL    6
15507 #define M_P_OCLK_MUXSEL    0x3U
15508 #define V_P_OCLK_MUXSEL(x) ((x) << S_P_OCLK_MUXSEL)
15509 #define G_P_OCLK_MUXSEL(x) (((x) >> S_P_OCLK_MUXSEL) & M_P_OCLK_MUXSEL)
15510 
15511 #define S_KX_OCLK_MUXSEL    3
15512 #define M_KX_OCLK_MUXSEL    0x7U
15513 #define V_KX_OCLK_MUXSEL(x) ((x) << S_KX_OCLK_MUXSEL)
15514 #define G_KX_OCLK_MUXSEL(x) (((x) >> S_KX_OCLK_MUXSEL) & M_KX_OCLK_MUXSEL)
15515 
15516 #define S_KR_OCLK_MUXSEL    0
15517 #define M_KR_OCLK_MUXSEL    0x7U
15518 #define V_KR_OCLK_MUXSEL(x) ((x) << S_KR_OCLK_MUXSEL)
15519 #define G_KR_OCLK_MUXSEL(x) (((x) >> S_KR_OCLK_MUXSEL) & M_KR_OCLK_MUXSEL)
15520 
15521 #define S_T5_P_OCLK_MUXSEL    13
15522 #define M_T5_P_OCLK_MUXSEL    0xfU
15523 #define V_T5_P_OCLK_MUXSEL(x) ((x) << S_T5_P_OCLK_MUXSEL)
15524 #define G_T5_P_OCLK_MUXSEL(x) (((x) >> S_T5_P_OCLK_MUXSEL) & M_T5_P_OCLK_MUXSEL)
15525 
15526 #define S_T6_P_OCLK_MUXSEL    13
15527 #define M_T6_P_OCLK_MUXSEL    0xfU
15528 #define V_T6_P_OCLK_MUXSEL(x) ((x) << S_T6_P_OCLK_MUXSEL)
15529 #define G_T6_P_OCLK_MUXSEL(x) (((x) >> S_T6_P_OCLK_MUXSEL) & M_T6_P_OCLK_MUXSEL)
15530 
15531 #define A_DBG_TRACE0_CONF_COMPREG0 0x6060
15532 #define A_DBG_TRACE0_CONF_COMPREG1 0x6064
15533 #define A_DBG_TRACE1_CONF_COMPREG0 0x6068
15534 #define A_DBG_TRACE1_CONF_COMPREG1 0x606c
15535 #define A_DBG_TRACE0_CONF_MASKREG0 0x6070
15536 #define A_DBG_TRACE0_CONF_MASKREG1 0x6074
15537 #define A_DBG_TRACE1_CONF_MASKREG0 0x6078
15538 #define A_DBG_TRACE1_CONF_MASKREG1 0x607c
15539 #define A_DBG_TRACE_COUNTER 0x6080
15540 
15541 #define S_COUNTER1    16
15542 #define M_COUNTER1    0xffffU
15543 #define V_COUNTER1(x) ((x) << S_COUNTER1)
15544 #define G_COUNTER1(x) (((x) >> S_COUNTER1) & M_COUNTER1)
15545 
15546 #define S_COUNTER0    0
15547 #define M_COUNTER0    0xffffU
15548 #define V_COUNTER0(x) ((x) << S_COUNTER0)
15549 #define G_COUNTER0(x) (((x) >> S_COUNTER0) & M_COUNTER0)
15550 
15551 #define A_DBG_STATIC_REFCLK_PERIOD 0x6084
15552 
15553 #define S_STATIC_REFCLK_PERIOD    0
15554 #define M_STATIC_REFCLK_PERIOD    0xffffU
15555 #define V_STATIC_REFCLK_PERIOD(x) ((x) << S_STATIC_REFCLK_PERIOD)
15556 #define G_STATIC_REFCLK_PERIOD(x) (((x) >> S_STATIC_REFCLK_PERIOD) & M_STATIC_REFCLK_PERIOD)
15557 
15558 #define A_DBG_TRACE_CONF 0x6088
15559 
15560 #define S_DBG_TRACE_OPERATE_WITH_TRG    5
15561 #define V_DBG_TRACE_OPERATE_WITH_TRG(x) ((x) << S_DBG_TRACE_OPERATE_WITH_TRG)
15562 #define F_DBG_TRACE_OPERATE_WITH_TRG    V_DBG_TRACE_OPERATE_WITH_TRG(1U)
15563 
15564 #define S_DBG_TRACE_OPERATE_EN    4
15565 #define V_DBG_TRACE_OPERATE_EN(x) ((x) << S_DBG_TRACE_OPERATE_EN)
15566 #define F_DBG_TRACE_OPERATE_EN    V_DBG_TRACE_OPERATE_EN(1U)
15567 
15568 #define S_DBG_OPERATE_INDV_COMBINED    3
15569 #define V_DBG_OPERATE_INDV_COMBINED(x) ((x) << S_DBG_OPERATE_INDV_COMBINED)
15570 #define F_DBG_OPERATE_INDV_COMBINED    V_DBG_OPERATE_INDV_COMBINED(1U)
15571 
15572 #define S_DBG_OPERATE_ORDER_OF_TRIGGER    2
15573 #define V_DBG_OPERATE_ORDER_OF_TRIGGER(x) ((x) << S_DBG_OPERATE_ORDER_OF_TRIGGER)
15574 #define F_DBG_OPERATE_ORDER_OF_TRIGGER    V_DBG_OPERATE_ORDER_OF_TRIGGER(1U)
15575 
15576 #define S_DBG_OPERATE_SGL_DBL_TRIGGER    1
15577 #define V_DBG_OPERATE_SGL_DBL_TRIGGER(x) ((x) << S_DBG_OPERATE_SGL_DBL_TRIGGER)
15578 #define F_DBG_OPERATE_SGL_DBL_TRIGGER    V_DBG_OPERATE_SGL_DBL_TRIGGER(1U)
15579 
15580 #define S_DBG_OPERATE0_OR_1    0
15581 #define V_DBG_OPERATE0_OR_1(x) ((x) << S_DBG_OPERATE0_OR_1)
15582 #define F_DBG_OPERATE0_OR_1    V_DBG_OPERATE0_OR_1(1U)
15583 
15584 #define A_DBG_TRACE_RDEN 0x608c
15585 
15586 #define S_RD_ADDR1    10
15587 #define M_RD_ADDR1    0xffU
15588 #define V_RD_ADDR1(x) ((x) << S_RD_ADDR1)
15589 #define G_RD_ADDR1(x) (((x) >> S_RD_ADDR1) & M_RD_ADDR1)
15590 
15591 #define S_RD_ADDR0    2
15592 #define M_RD_ADDR0    0xffU
15593 #define V_RD_ADDR0(x) ((x) << S_RD_ADDR0)
15594 #define G_RD_ADDR0(x) (((x) >> S_RD_ADDR0) & M_RD_ADDR0)
15595 
15596 #define S_RD_EN1    1
15597 #define V_RD_EN1(x) ((x) << S_RD_EN1)
15598 #define F_RD_EN1    V_RD_EN1(1U)
15599 
15600 #define S_RD_EN0    0
15601 #define V_RD_EN0(x) ((x) << S_RD_EN0)
15602 #define F_RD_EN0    V_RD_EN0(1U)
15603 
15604 #define S_T5_RD_ADDR1    11
15605 #define M_T5_RD_ADDR1    0x1ffU
15606 #define V_T5_RD_ADDR1(x) ((x) << S_T5_RD_ADDR1)
15607 #define G_T5_RD_ADDR1(x) (((x) >> S_T5_RD_ADDR1) & M_T5_RD_ADDR1)
15608 
15609 #define S_T5_RD_ADDR0    2
15610 #define M_T5_RD_ADDR0    0x1ffU
15611 #define V_T5_RD_ADDR0(x) ((x) << S_T5_RD_ADDR0)
15612 #define G_T5_RD_ADDR0(x) (((x) >> S_T5_RD_ADDR0) & M_T5_RD_ADDR0)
15613 
15614 #define A_DBG_TRACE_WRADDR 0x6090
15615 
15616 #define S_WR_POINTER_ADDR1    16
15617 #define M_WR_POINTER_ADDR1    0xffU
15618 #define V_WR_POINTER_ADDR1(x) ((x) << S_WR_POINTER_ADDR1)
15619 #define G_WR_POINTER_ADDR1(x) (((x) >> S_WR_POINTER_ADDR1) & M_WR_POINTER_ADDR1)
15620 
15621 #define S_WR_POINTER_ADDR0    0
15622 #define M_WR_POINTER_ADDR0    0xffU
15623 #define V_WR_POINTER_ADDR0(x) ((x) << S_WR_POINTER_ADDR0)
15624 #define G_WR_POINTER_ADDR0(x) (((x) >> S_WR_POINTER_ADDR0) & M_WR_POINTER_ADDR0)
15625 
15626 #define S_T5_WR_POINTER_ADDR1    16
15627 #define M_T5_WR_POINTER_ADDR1    0x1ffU
15628 #define V_T5_WR_POINTER_ADDR1(x) ((x) << S_T5_WR_POINTER_ADDR1)
15629 #define G_T5_WR_POINTER_ADDR1(x) (((x) >> S_T5_WR_POINTER_ADDR1) & M_T5_WR_POINTER_ADDR1)
15630 
15631 #define S_T5_WR_POINTER_ADDR0    0
15632 #define M_T5_WR_POINTER_ADDR0    0x1ffU
15633 #define V_T5_WR_POINTER_ADDR0(x) ((x) << S_T5_WR_POINTER_ADDR0)
15634 #define G_T5_WR_POINTER_ADDR0(x) (((x) >> S_T5_WR_POINTER_ADDR0) & M_T5_WR_POINTER_ADDR0)
15635 
15636 #define A_DBG_TRACE0_DATA_OUT 0x6094
15637 #define A_DBG_TRACE1_DATA_OUT 0x6098
15638 #define A_DBG_FUSE_SENSE_DONE 0x609c
15639 
15640 #define S_STATIC_JTAG_VERSIONNR    5
15641 #define M_STATIC_JTAG_VERSIONNR    0xfU
15642 #define V_STATIC_JTAG_VERSIONNR(x) ((x) << S_STATIC_JTAG_VERSIONNR)
15643 #define G_STATIC_JTAG_VERSIONNR(x) (((x) >> S_STATIC_JTAG_VERSIONNR) & M_STATIC_JTAG_VERSIONNR)
15644 
15645 #define S_UNQ0    1
15646 #define M_UNQ0    0xfU
15647 #define V_UNQ0(x) ((x) << S_UNQ0)
15648 #define G_UNQ0(x) (((x) >> S_UNQ0) & M_UNQ0)
15649 
15650 #define S_FUSE_DONE_SENSE    0
15651 #define V_FUSE_DONE_SENSE(x) ((x) << S_FUSE_DONE_SENSE)
15652 #define F_FUSE_DONE_SENSE    V_FUSE_DONE_SENSE(1U)
15653 
15654 #define A_DBG_TVSENSE_EN 0x60a8
15655 
15656 #define S_MCIMPED1_OUT    29
15657 #define V_MCIMPED1_OUT(x) ((x) << S_MCIMPED1_OUT)
15658 #define F_MCIMPED1_OUT    V_MCIMPED1_OUT(1U)
15659 
15660 #define S_MCIMPED2_OUT    28
15661 #define V_MCIMPED2_OUT(x) ((x) << S_MCIMPED2_OUT)
15662 #define F_MCIMPED2_OUT    V_MCIMPED2_OUT(1U)
15663 
15664 #define S_TVSENSE_SNSOUT    17
15665 #define M_TVSENSE_SNSOUT    0x1ffU
15666 #define V_TVSENSE_SNSOUT(x) ((x) << S_TVSENSE_SNSOUT)
15667 #define G_TVSENSE_SNSOUT(x) (((x) >> S_TVSENSE_SNSOUT) & M_TVSENSE_SNSOUT)
15668 
15669 #define S_TVSENSE_OUTPUTVALID    16
15670 #define V_TVSENSE_OUTPUTVALID(x) ((x) << S_TVSENSE_OUTPUTVALID)
15671 #define F_TVSENSE_OUTPUTVALID    V_TVSENSE_OUTPUTVALID(1U)
15672 
15673 #define S_TVSENSE_SLEEP    10
15674 #define V_TVSENSE_SLEEP(x) ((x) << S_TVSENSE_SLEEP)
15675 #define F_TVSENSE_SLEEP    V_TVSENSE_SLEEP(1U)
15676 
15677 #define S_TVSENSE_SENSV    9
15678 #define V_TVSENSE_SENSV(x) ((x) << S_TVSENSE_SENSV)
15679 #define F_TVSENSE_SENSV    V_TVSENSE_SENSV(1U)
15680 
15681 #define S_TVSENSE_RST    8
15682 #define V_TVSENSE_RST(x) ((x) << S_TVSENSE_RST)
15683 #define F_TVSENSE_RST    V_TVSENSE_RST(1U)
15684 
15685 #define S_TVSENSE_RATIO    0
15686 #define M_TVSENSE_RATIO    0xffU
15687 #define V_TVSENSE_RATIO(x) ((x) << S_TVSENSE_RATIO)
15688 #define G_TVSENSE_RATIO(x) (((x) >> S_TVSENSE_RATIO) & M_TVSENSE_RATIO)
15689 
15690 #define S_T6_TVSENSE_SLEEP    11
15691 #define V_T6_TVSENSE_SLEEP(x) ((x) << S_T6_TVSENSE_SLEEP)
15692 #define F_T6_TVSENSE_SLEEP    V_T6_TVSENSE_SLEEP(1U)
15693 
15694 #define S_T6_TVSENSE_SENSV    10
15695 #define V_T6_TVSENSE_SENSV(x) ((x) << S_T6_TVSENSE_SENSV)
15696 #define F_T6_TVSENSE_SENSV    V_T6_TVSENSE_SENSV(1U)
15697 
15698 #define S_T6_TVSENSE_RST    9
15699 #define V_T6_TVSENSE_RST(x) ((x) << S_T6_TVSENSE_RST)
15700 #define F_T6_TVSENSE_RST    V_T6_TVSENSE_RST(1U)
15701 
15702 #define A_DBG_PVT_EN1 0x60a8
15703 
15704 #define S_PVT_TRIMO    18
15705 #define M_PVT_TRIMO    0x3fU
15706 #define V_PVT_TRIMO(x) ((x) << S_PVT_TRIMO)
15707 #define G_PVT_TRIMO(x) (((x) >> S_PVT_TRIMO) & M_PVT_TRIMO)
15708 
15709 #define S_PVT_TRIMG    13
15710 #define M_PVT_TRIMG    0x1fU
15711 #define V_PVT_TRIMG(x) ((x) << S_PVT_TRIMG)
15712 #define G_PVT_TRIMG(x) (((x) >> S_PVT_TRIMG) & M_PVT_TRIMG)
15713 
15714 #define S_PVT_VSAMPLE    12
15715 #define V_PVT_VSAMPLE(x) ((x) << S_PVT_VSAMPLE)
15716 #define F_PVT_VSAMPLE    V_PVT_VSAMPLE(1U)
15717 
15718 #define S_PVT_PSAMPLE    10
15719 #define M_PVT_PSAMPLE    0x3U
15720 #define V_PVT_PSAMPLE(x) ((x) << S_PVT_PSAMPLE)
15721 #define G_PVT_PSAMPLE(x) (((x) >> S_PVT_PSAMPLE) & M_PVT_PSAMPLE)
15722 
15723 #define S_PVT_ENA    9
15724 #define V_PVT_ENA(x) ((x) << S_PVT_ENA)
15725 #define F_PVT_ENA    V_PVT_ENA(1U)
15726 
15727 #define S_PVT_RESET    8
15728 #define V_PVT_RESET(x) ((x) << S_PVT_RESET)
15729 #define F_PVT_RESET    V_PVT_RESET(1U)
15730 
15731 #define S_PVT_DIV    0
15732 #define M_PVT_DIV    0xffU
15733 #define V_PVT_DIV(x) ((x) << S_PVT_DIV)
15734 #define G_PVT_DIV(x) (((x) >> S_PVT_DIV) & M_PVT_DIV)
15735 
15736 #define A_DBG_CUST_EFUSE_OUT_EN 0x60ac
15737 #define A_DBG_PVT_EN2 0x60ac
15738 
15739 #define S_PVT_DATA_OUT    1
15740 #define M_PVT_DATA_OUT    0x3ffU
15741 #define V_PVT_DATA_OUT(x) ((x) << S_PVT_DATA_OUT)
15742 #define G_PVT_DATA_OUT(x) (((x) >> S_PVT_DATA_OUT) & M_PVT_DATA_OUT)
15743 
15744 #define S_PVT_DATA_VALID    0
15745 #define V_PVT_DATA_VALID(x) ((x) << S_PVT_DATA_VALID)
15746 #define F_PVT_DATA_VALID    V_PVT_DATA_VALID(1U)
15747 
15748 #define A_DBG_CUST_EFUSE_SEL1_EN 0x60b0
15749 #define A_DBG_CUST_EFUSE_SEL2_EN 0x60b4
15750 
15751 #define S_DBG_FEENABLE    29
15752 #define V_DBG_FEENABLE(x) ((x) << S_DBG_FEENABLE)
15753 #define F_DBG_FEENABLE    V_DBG_FEENABLE(1U)
15754 
15755 #define S_DBG_FEF    23
15756 #define M_DBG_FEF    0x3fU
15757 #define V_DBG_FEF(x) ((x) << S_DBG_FEF)
15758 #define G_DBG_FEF(x) (((x) >> S_DBG_FEF) & M_DBG_FEF)
15759 
15760 #define S_DBG_FEMIMICN    22
15761 #define V_DBG_FEMIMICN(x) ((x) << S_DBG_FEMIMICN)
15762 #define F_DBG_FEMIMICN    V_DBG_FEMIMICN(1U)
15763 
15764 #define S_DBG_FEGATEC    21
15765 #define V_DBG_FEGATEC(x) ((x) << S_DBG_FEGATEC)
15766 #define F_DBG_FEGATEC    V_DBG_FEGATEC(1U)
15767 
15768 #define S_DBG_FEPROGP    20
15769 #define V_DBG_FEPROGP(x) ((x) << S_DBG_FEPROGP)
15770 #define F_DBG_FEPROGP    V_DBG_FEPROGP(1U)
15771 
15772 #define S_DBG_FEREADCLK    19
15773 #define V_DBG_FEREADCLK(x) ((x) << S_DBG_FEREADCLK)
15774 #define F_DBG_FEREADCLK    V_DBG_FEREADCLK(1U)
15775 
15776 #define S_DBG_FERSEL    3
15777 #define M_DBG_FERSEL    0xffffU
15778 #define V_DBG_FERSEL(x) ((x) << S_DBG_FERSEL)
15779 #define G_DBG_FERSEL(x) (((x) >> S_DBG_FERSEL) & M_DBG_FERSEL)
15780 
15781 #define S_DBG_FETIME    0
15782 #define M_DBG_FETIME    0x7U
15783 #define V_DBG_FETIME(x) ((x) << S_DBG_FETIME)
15784 #define G_DBG_FETIME(x) (((x) >> S_DBG_FETIME) & M_DBG_FETIME)
15785 
15786 #define A_DBG_T5_STATIC_M_PLL_CONF1 0x60b8
15787 
15788 #define S_T5_STATIC_M_PLL_MULTFRAC    8
15789 #define M_T5_STATIC_M_PLL_MULTFRAC    0xffffffU
15790 #define V_T5_STATIC_M_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_M_PLL_MULTFRAC)
15791 #define G_T5_STATIC_M_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_M_PLL_MULTFRAC) & M_T5_STATIC_M_PLL_MULTFRAC)
15792 
15793 #define S_T5_STATIC_M_PLL_FFSLEWRATE    0
15794 #define M_T5_STATIC_M_PLL_FFSLEWRATE    0xffU
15795 #define V_T5_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_M_PLL_FFSLEWRATE)
15796 #define G_T5_STATIC_M_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_M_PLL_FFSLEWRATE) & M_T5_STATIC_M_PLL_FFSLEWRATE)
15797 
15798 #define A_DBG_STATIC_M_PLL_CONF1 0x60b8
15799 
15800 #define S_STATIC_M_PLL_MULTFRAC    8
15801 #define M_STATIC_M_PLL_MULTFRAC    0xffffffU
15802 #define V_STATIC_M_PLL_MULTFRAC(x) ((x) << S_STATIC_M_PLL_MULTFRAC)
15803 #define G_STATIC_M_PLL_MULTFRAC(x) (((x) >> S_STATIC_M_PLL_MULTFRAC) & M_STATIC_M_PLL_MULTFRAC)
15804 
15805 #define S_STATIC_M_PLL_FFSLEWRATE    0
15806 #define M_STATIC_M_PLL_FFSLEWRATE    0xffU
15807 #define V_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_STATIC_M_PLL_FFSLEWRATE)
15808 #define G_STATIC_M_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_M_PLL_FFSLEWRATE) & M_STATIC_M_PLL_FFSLEWRATE)
15809 
15810 #define A_DBG_STATIC_M0_PLL_CONF1 0x60b8
15811 
15812 #define S_STATIC_M0_PLL_RANGE    22
15813 #define M_STATIC_M0_PLL_RANGE    0x7U
15814 #define V_STATIC_M0_PLL_RANGE(x) ((x) << S_STATIC_M0_PLL_RANGE)
15815 #define G_STATIC_M0_PLL_RANGE(x) (((x) >> S_STATIC_M0_PLL_RANGE) & M_STATIC_M0_PLL_RANGE)
15816 
15817 #define S_STATIC_M0_PLL_DIVQ    17
15818 #define M_STATIC_M0_PLL_DIVQ    0x1fU
15819 #define V_STATIC_M0_PLL_DIVQ(x) ((x) << S_STATIC_M0_PLL_DIVQ)
15820 #define G_STATIC_M0_PLL_DIVQ(x) (((x) >> S_STATIC_M0_PLL_DIVQ) & M_STATIC_M0_PLL_DIVQ)
15821 
15822 #define S_STATIC_M0_PLL_DIVFI    8
15823 #define M_STATIC_M0_PLL_DIVFI    0x1ffU
15824 #define V_STATIC_M0_PLL_DIVFI(x) ((x) << S_STATIC_M0_PLL_DIVFI)
15825 #define G_STATIC_M0_PLL_DIVFI(x) (((x) >> S_STATIC_M0_PLL_DIVFI) & M_STATIC_M0_PLL_DIVFI)
15826 
15827 #define S_STATIC_M0_PLL_DIVR    2
15828 #define M_STATIC_M0_PLL_DIVR    0x3fU
15829 #define V_STATIC_M0_PLL_DIVR(x) ((x) << S_STATIC_M0_PLL_DIVR)
15830 #define G_STATIC_M0_PLL_DIVR(x) (((x) >> S_STATIC_M0_PLL_DIVR) & M_STATIC_M0_PLL_DIVR)
15831 
15832 #define S_STATIC_M0_PLL_BYPASS    1
15833 #define V_STATIC_M0_PLL_BYPASS(x) ((x) << S_STATIC_M0_PLL_BYPASS)
15834 #define F_STATIC_M0_PLL_BYPASS    V_STATIC_M0_PLL_BYPASS(1U)
15835 
15836 #define S_STATIC_M0_PLL_RESET    0
15837 #define V_STATIC_M0_PLL_RESET(x) ((x) << S_STATIC_M0_PLL_RESET)
15838 #define F_STATIC_M0_PLL_RESET    V_STATIC_M0_PLL_RESET(1U)
15839 
15840 #define A_DBG_T5_STATIC_M_PLL_CONF2 0x60bc
15841 
15842 #define S_T5_STATIC_M_PLL_DCO_BYPASS    23
15843 #define V_T5_STATIC_M_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_DCO_BYPASS)
15844 #define F_T5_STATIC_M_PLL_DCO_BYPASS    V_T5_STATIC_M_PLL_DCO_BYPASS(1U)
15845 
15846 #define S_T5_STATIC_M_PLL_SDORDER    21
15847 #define M_T5_STATIC_M_PLL_SDORDER    0x3U
15848 #define V_T5_STATIC_M_PLL_SDORDER(x) ((x) << S_T5_STATIC_M_PLL_SDORDER)
15849 #define G_T5_STATIC_M_PLL_SDORDER(x) (((x) >> S_T5_STATIC_M_PLL_SDORDER) & M_T5_STATIC_M_PLL_SDORDER)
15850 
15851 #define S_T5_STATIC_M_PLL_FFENABLE    20
15852 #define V_T5_STATIC_M_PLL_FFENABLE(x) ((x) << S_T5_STATIC_M_PLL_FFENABLE)
15853 #define F_T5_STATIC_M_PLL_FFENABLE    V_T5_STATIC_M_PLL_FFENABLE(1U)
15854 
15855 #define S_T5_STATIC_M_PLL_STOPCLKB    19
15856 #define V_T5_STATIC_M_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKB)
15857 #define F_T5_STATIC_M_PLL_STOPCLKB    V_T5_STATIC_M_PLL_STOPCLKB(1U)
15858 
15859 #define S_T5_STATIC_M_PLL_STOPCLKA    18
15860 #define V_T5_STATIC_M_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKA)
15861 #define F_T5_STATIC_M_PLL_STOPCLKA    V_T5_STATIC_M_PLL_STOPCLKA(1U)
15862 
15863 #define S_T5_STATIC_M_PLL_SLEEP    17
15864 #define V_T5_STATIC_M_PLL_SLEEP(x) ((x) << S_T5_STATIC_M_PLL_SLEEP)
15865 #define F_T5_STATIC_M_PLL_SLEEP    V_T5_STATIC_M_PLL_SLEEP(1U)
15866 
15867 #define S_T5_STATIC_M_PLL_BYPASS    16
15868 #define V_T5_STATIC_M_PLL_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_BYPASS)
15869 #define F_T5_STATIC_M_PLL_BYPASS    V_T5_STATIC_M_PLL_BYPASS(1U)
15870 
15871 #define S_T5_STATIC_M_PLL_LOCKTUNE    0
15872 #define M_T5_STATIC_M_PLL_LOCKTUNE    0xffffU
15873 #define V_T5_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_M_PLL_LOCKTUNE)
15874 #define G_T5_STATIC_M_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_M_PLL_LOCKTUNE) & M_T5_STATIC_M_PLL_LOCKTUNE)
15875 
15876 #define A_DBG_STATIC_M_PLL_CONF2 0x60bc
15877 
15878 #define S_T6_STATIC_M_PLL_PREDIV    24
15879 #define M_T6_STATIC_M_PLL_PREDIV    0x3fU
15880 #define V_T6_STATIC_M_PLL_PREDIV(x) ((x) << S_T6_STATIC_M_PLL_PREDIV)
15881 #define G_T6_STATIC_M_PLL_PREDIV(x) (((x) >> S_T6_STATIC_M_PLL_PREDIV) & M_T6_STATIC_M_PLL_PREDIV)
15882 
15883 #define S_STATIC_M_PLL_DCO_BYPASS    23
15884 #define V_STATIC_M_PLL_DCO_BYPASS(x) ((x) << S_STATIC_M_PLL_DCO_BYPASS)
15885 #define F_STATIC_M_PLL_DCO_BYPASS    V_STATIC_M_PLL_DCO_BYPASS(1U)
15886 
15887 #define S_STATIC_M_PLL_SDORDER    21
15888 #define M_STATIC_M_PLL_SDORDER    0x3U
15889 #define V_STATIC_M_PLL_SDORDER(x) ((x) << S_STATIC_M_PLL_SDORDER)
15890 #define G_STATIC_M_PLL_SDORDER(x) (((x) >> S_STATIC_M_PLL_SDORDER) & M_STATIC_M_PLL_SDORDER)
15891 
15892 #define S_STATIC_M_PLL_FFENABLE    20
15893 #define V_STATIC_M_PLL_FFENABLE(x) ((x) << S_STATIC_M_PLL_FFENABLE)
15894 #define F_STATIC_M_PLL_FFENABLE    V_STATIC_M_PLL_FFENABLE(1U)
15895 
15896 #define S_STATIC_M_PLL_STOPCLKB    19
15897 #define V_STATIC_M_PLL_STOPCLKB(x) ((x) << S_STATIC_M_PLL_STOPCLKB)
15898 #define F_STATIC_M_PLL_STOPCLKB    V_STATIC_M_PLL_STOPCLKB(1U)
15899 
15900 #define S_STATIC_M_PLL_STOPCLKA    18
15901 #define V_STATIC_M_PLL_STOPCLKA(x) ((x) << S_STATIC_M_PLL_STOPCLKA)
15902 #define F_STATIC_M_PLL_STOPCLKA    V_STATIC_M_PLL_STOPCLKA(1U)
15903 
15904 #define S_T6_STATIC_M_PLL_SLEEP    17
15905 #define V_T6_STATIC_M_PLL_SLEEP(x) ((x) << S_T6_STATIC_M_PLL_SLEEP)
15906 #define F_T6_STATIC_M_PLL_SLEEP    V_T6_STATIC_M_PLL_SLEEP(1U)
15907 
15908 #define S_T6_STATIC_M_PLL_BYPASS    16
15909 #define V_T6_STATIC_M_PLL_BYPASS(x) ((x) << S_T6_STATIC_M_PLL_BYPASS)
15910 #define F_T6_STATIC_M_PLL_BYPASS    V_T6_STATIC_M_PLL_BYPASS(1U)
15911 
15912 #define S_STATIC_M_PLL_LOCKTUNE    0
15913 #define M_STATIC_M_PLL_LOCKTUNE    0x1fU
15914 #define V_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_STATIC_M_PLL_LOCKTUNE)
15915 #define G_STATIC_M_PLL_LOCKTUNE(x) (((x) >> S_STATIC_M_PLL_LOCKTUNE) & M_STATIC_M_PLL_LOCKTUNE)
15916 
15917 #define A_DBG_STATIC_M0_PLL_CONF2 0x60bc
15918 
15919 #define S_T7_STATIC_SWMC1RST_    14
15920 #define V_T7_STATIC_SWMC1RST_(x) ((x) << S_T7_STATIC_SWMC1RST_)
15921 #define F_T7_STATIC_SWMC1RST_    V_T7_STATIC_SWMC1RST_(1U)
15922 
15923 #define S_T7_STATIC_SWMC1CFGRST_    13
15924 #define V_T7_STATIC_SWMC1CFGRST_(x) ((x) << S_T7_STATIC_SWMC1CFGRST_)
15925 #define F_T7_STATIC_SWMC1CFGRST_    V_T7_STATIC_SWMC1CFGRST_(1U)
15926 
15927 #define S_T7_STATIC_PHY0RECRST_    12
15928 #define V_T7_STATIC_PHY0RECRST_(x) ((x) << S_T7_STATIC_PHY0RECRST_)
15929 #define F_T7_STATIC_PHY0RECRST_    V_T7_STATIC_PHY0RECRST_(1U)
15930 
15931 #define S_T7_STATIC_PHY1RECRST_    11
15932 #define V_T7_STATIC_PHY1RECRST_(x) ((x) << S_T7_STATIC_PHY1RECRST_)
15933 #define F_T7_STATIC_PHY1RECRST_    V_T7_STATIC_PHY1RECRST_(1U)
15934 
15935 #define S_T7_STATIC_SWMC0RST_    10
15936 #define V_T7_STATIC_SWMC0RST_(x) ((x) << S_T7_STATIC_SWMC0RST_)
15937 #define F_T7_STATIC_SWMC0RST_    V_T7_STATIC_SWMC0RST_(1U)
15938 
15939 #define S_T7_STATIC_SWMC0CFGRST_    9
15940 #define V_T7_STATIC_SWMC0CFGRST_(x) ((x) << S_T7_STATIC_SWMC0CFGRST_)
15941 #define F_T7_STATIC_SWMC0CFGRST_    V_T7_STATIC_SWMC0CFGRST_(1U)
15942 
15943 #define S_STATIC_M0_PLL_SSMF    5
15944 #define M_STATIC_M0_PLL_SSMF    0xfU
15945 #define V_STATIC_M0_PLL_SSMF(x) ((x) << S_STATIC_M0_PLL_SSMF)
15946 #define G_STATIC_M0_PLL_SSMF(x) (((x) >> S_STATIC_M0_PLL_SSMF) & M_STATIC_M0_PLL_SSMF)
15947 
15948 #define S_STATIC_M0_PLL_SSMD    2
15949 #define M_STATIC_M0_PLL_SSMD    0x7U
15950 #define V_STATIC_M0_PLL_SSMD(x) ((x) << S_STATIC_M0_PLL_SSMD)
15951 #define G_STATIC_M0_PLL_SSMD(x) (((x) >> S_STATIC_M0_PLL_SSMD) & M_STATIC_M0_PLL_SSMD)
15952 
15953 #define S_STATIC_M0_PLL_SSDS    1
15954 #define V_STATIC_M0_PLL_SSDS(x) ((x) << S_STATIC_M0_PLL_SSDS)
15955 #define F_STATIC_M0_PLL_SSDS    V_STATIC_M0_PLL_SSDS(1U)
15956 
15957 #define S_STATIC_M0_PLL_SSE    0
15958 #define V_STATIC_M0_PLL_SSE(x) ((x) << S_STATIC_M0_PLL_SSE)
15959 #define F_STATIC_M0_PLL_SSE    V_STATIC_M0_PLL_SSE(1U)
15960 
15961 #define A_DBG_T5_STATIC_M_PLL_CONF3 0x60c0
15962 
15963 #define S_T5_STATIC_M_PLL_MULTPRE    30
15964 #define M_T5_STATIC_M_PLL_MULTPRE    0x3U
15965 #define V_T5_STATIC_M_PLL_MULTPRE(x) ((x) << S_T5_STATIC_M_PLL_MULTPRE)
15966 #define G_T5_STATIC_M_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_M_PLL_MULTPRE) & M_T5_STATIC_M_PLL_MULTPRE)
15967 
15968 #define S_T5_STATIC_M_PLL_LOCKSEL    28
15969 #define M_T5_STATIC_M_PLL_LOCKSEL    0x3U
15970 #define V_T5_STATIC_M_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_M_PLL_LOCKSEL)
15971 #define G_T5_STATIC_M_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_M_PLL_LOCKSEL) & M_T5_STATIC_M_PLL_LOCKSEL)
15972 
15973 #define S_T5_STATIC_M_PLL_FFTUNE    12
15974 #define M_T5_STATIC_M_PLL_FFTUNE    0xffffU
15975 #define V_T5_STATIC_M_PLL_FFTUNE(x) ((x) << S_T5_STATIC_M_PLL_FFTUNE)
15976 #define G_T5_STATIC_M_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_M_PLL_FFTUNE) & M_T5_STATIC_M_PLL_FFTUNE)
15977 
15978 #define S_T5_STATIC_M_PLL_RANGEPRE    10
15979 #define M_T5_STATIC_M_PLL_RANGEPRE    0x3U
15980 #define V_T5_STATIC_M_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_M_PLL_RANGEPRE)
15981 #define G_T5_STATIC_M_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_M_PLL_RANGEPRE) & M_T5_STATIC_M_PLL_RANGEPRE)
15982 
15983 #define S_T5_STATIC_M_PLL_RANGEB    5
15984 #define M_T5_STATIC_M_PLL_RANGEB    0x1fU
15985 #define V_T5_STATIC_M_PLL_RANGEB(x) ((x) << S_T5_STATIC_M_PLL_RANGEB)
15986 #define G_T5_STATIC_M_PLL_RANGEB(x) (((x) >> S_T5_STATIC_M_PLL_RANGEB) & M_T5_STATIC_M_PLL_RANGEB)
15987 
15988 #define S_T5_STATIC_M_PLL_RANGEA    0
15989 #define M_T5_STATIC_M_PLL_RANGEA    0x1fU
15990 #define V_T5_STATIC_M_PLL_RANGEA(x) ((x) << S_T5_STATIC_M_PLL_RANGEA)
15991 #define G_T5_STATIC_M_PLL_RANGEA(x) (((x) >> S_T5_STATIC_M_PLL_RANGEA) & M_T5_STATIC_M_PLL_RANGEA)
15992 
15993 #define A_DBG_STATIC_M_PLL_CONF3 0x60c0
15994 
15995 #define S_STATIC_M_PLL_MULTPRE    30
15996 #define M_STATIC_M_PLL_MULTPRE    0x3U
15997 #define V_STATIC_M_PLL_MULTPRE(x) ((x) << S_STATIC_M_PLL_MULTPRE)
15998 #define G_STATIC_M_PLL_MULTPRE(x) (((x) >> S_STATIC_M_PLL_MULTPRE) & M_STATIC_M_PLL_MULTPRE)
15999 
16000 #define S_STATIC_M_PLL_LOCKSEL    28
16001 #define V_STATIC_M_PLL_LOCKSEL(x) ((x) << S_STATIC_M_PLL_LOCKSEL)
16002 #define F_STATIC_M_PLL_LOCKSEL    V_STATIC_M_PLL_LOCKSEL(1U)
16003 
16004 #define S_STATIC_M_PLL_FFTUNE    12
16005 #define M_STATIC_M_PLL_FFTUNE    0xffffU
16006 #define V_STATIC_M_PLL_FFTUNE(x) ((x) << S_STATIC_M_PLL_FFTUNE)
16007 #define G_STATIC_M_PLL_FFTUNE(x) (((x) >> S_STATIC_M_PLL_FFTUNE) & M_STATIC_M_PLL_FFTUNE)
16008 
16009 #define S_STATIC_M_PLL_RANGEPRE    10
16010 #define M_STATIC_M_PLL_RANGEPRE    0x3U
16011 #define V_STATIC_M_PLL_RANGEPRE(x) ((x) << S_STATIC_M_PLL_RANGEPRE)
16012 #define G_STATIC_M_PLL_RANGEPRE(x) (((x) >> S_STATIC_M_PLL_RANGEPRE) & M_STATIC_M_PLL_RANGEPRE)
16013 
16014 #define S_T6_STATIC_M_PLL_RANGEB    5
16015 #define M_T6_STATIC_M_PLL_RANGEB    0x1fU
16016 #define V_T6_STATIC_M_PLL_RANGEB(x) ((x) << S_T6_STATIC_M_PLL_RANGEB)
16017 #define G_T6_STATIC_M_PLL_RANGEB(x) (((x) >> S_T6_STATIC_M_PLL_RANGEB) & M_T6_STATIC_M_PLL_RANGEB)
16018 
16019 #define S_T6_STATIC_M_PLL_RANGEA    0
16020 #define M_T6_STATIC_M_PLL_RANGEA    0x1fU
16021 #define V_T6_STATIC_M_PLL_RANGEA(x) ((x) << S_T6_STATIC_M_PLL_RANGEA)
16022 #define G_T6_STATIC_M_PLL_RANGEA(x) (((x) >> S_T6_STATIC_M_PLL_RANGEA) & M_T6_STATIC_M_PLL_RANGEA)
16023 
16024 #define A_DBG_STATIC_MAC_PLL_CONF1 0x60c0
16025 
16026 #define S_STATIC_MAC_PLL_RANGE    22
16027 #define M_STATIC_MAC_PLL_RANGE    0x7U
16028 #define V_STATIC_MAC_PLL_RANGE(x) ((x) << S_STATIC_MAC_PLL_RANGE)
16029 #define G_STATIC_MAC_PLL_RANGE(x) (((x) >> S_STATIC_MAC_PLL_RANGE) & M_STATIC_MAC_PLL_RANGE)
16030 
16031 #define S_STATIC_MAC_PLL_DIVQ    17
16032 #define M_STATIC_MAC_PLL_DIVQ    0x1fU
16033 #define V_STATIC_MAC_PLL_DIVQ(x) ((x) << S_STATIC_MAC_PLL_DIVQ)
16034 #define G_STATIC_MAC_PLL_DIVQ(x) (((x) >> S_STATIC_MAC_PLL_DIVQ) & M_STATIC_MAC_PLL_DIVQ)
16035 
16036 #define S_STATIC_MAC_PLL_DIVFI    8
16037 #define M_STATIC_MAC_PLL_DIVFI    0x1ffU
16038 #define V_STATIC_MAC_PLL_DIVFI(x) ((x) << S_STATIC_MAC_PLL_DIVFI)
16039 #define G_STATIC_MAC_PLL_DIVFI(x) (((x) >> S_STATIC_MAC_PLL_DIVFI) & M_STATIC_MAC_PLL_DIVFI)
16040 
16041 #define S_STATIC_MAC_PLL_DIVR    2
16042 #define M_STATIC_MAC_PLL_DIVR    0x3fU
16043 #define V_STATIC_MAC_PLL_DIVR(x) ((x) << S_STATIC_MAC_PLL_DIVR)
16044 #define G_STATIC_MAC_PLL_DIVR(x) (((x) >> S_STATIC_MAC_PLL_DIVR) & M_STATIC_MAC_PLL_DIVR)
16045 
16046 #define S_STATIC_MAC_PLL_BYPASS    1
16047 #define V_STATIC_MAC_PLL_BYPASS(x) ((x) << S_STATIC_MAC_PLL_BYPASS)
16048 #define F_STATIC_MAC_PLL_BYPASS    V_STATIC_MAC_PLL_BYPASS(1U)
16049 
16050 #define S_STATIC_MAC_PLL_RESET    0
16051 #define V_STATIC_MAC_PLL_RESET(x) ((x) << S_STATIC_MAC_PLL_RESET)
16052 #define F_STATIC_MAC_PLL_RESET    V_STATIC_MAC_PLL_RESET(1U)
16053 
16054 #define A_DBG_T5_STATIC_M_PLL_CONF4 0x60c4
16055 #define A_DBG_STATIC_M_PLL_CONF4 0x60c4
16056 #define A_DBG_STATIC_MAC_PLL_CONF2 0x60c4
16057 
16058 #define S_STATIC_MAC_PLL_SSMF    5
16059 #define M_STATIC_MAC_PLL_SSMF    0xfU
16060 #define V_STATIC_MAC_PLL_SSMF(x) ((x) << S_STATIC_MAC_PLL_SSMF)
16061 #define G_STATIC_MAC_PLL_SSMF(x) (((x) >> S_STATIC_MAC_PLL_SSMF) & M_STATIC_MAC_PLL_SSMF)
16062 
16063 #define S_STATIC_MAC_PLL_SSMD    2
16064 #define M_STATIC_MAC_PLL_SSMD    0x7U
16065 #define V_STATIC_MAC_PLL_SSMD(x) ((x) << S_STATIC_MAC_PLL_SSMD)
16066 #define G_STATIC_MAC_PLL_SSMD(x) (((x) >> S_STATIC_MAC_PLL_SSMD) & M_STATIC_MAC_PLL_SSMD)
16067 
16068 #define S_STATIC_MAC_PLL_SSDS    1
16069 #define V_STATIC_MAC_PLL_SSDS(x) ((x) << S_STATIC_MAC_PLL_SSDS)
16070 #define F_STATIC_MAC_PLL_SSDS    V_STATIC_MAC_PLL_SSDS(1U)
16071 
16072 #define S_STATIC_MAC_PLL_SSE    0
16073 #define V_STATIC_MAC_PLL_SSE(x) ((x) << S_STATIC_MAC_PLL_SSE)
16074 #define F_STATIC_MAC_PLL_SSE    V_STATIC_MAC_PLL_SSE(1U)
16075 
16076 #define A_DBG_T5_STATIC_M_PLL_CONF5 0x60c8
16077 
16078 #define S_T5_STATIC_M_PLL_VCVTUNE    24
16079 #define M_T5_STATIC_M_PLL_VCVTUNE    0x7U
16080 #define V_T5_STATIC_M_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_M_PLL_VCVTUNE)
16081 #define G_T5_STATIC_M_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_M_PLL_VCVTUNE) & M_T5_STATIC_M_PLL_VCVTUNE)
16082 
16083 #define S_T5_STATIC_M_PLL_RESET    23
16084 #define V_T5_STATIC_M_PLL_RESET(x) ((x) << S_T5_STATIC_M_PLL_RESET)
16085 #define F_T5_STATIC_M_PLL_RESET    V_T5_STATIC_M_PLL_RESET(1U)
16086 
16087 #define S_T5_STATIC_MPLL_REFCLK_SEL    22
16088 #define V_T5_STATIC_MPLL_REFCLK_SEL(x) ((x) << S_T5_STATIC_MPLL_REFCLK_SEL)
16089 #define F_T5_STATIC_MPLL_REFCLK_SEL    V_T5_STATIC_MPLL_REFCLK_SEL(1U)
16090 
16091 #define S_T5_STATIC_M_PLL_LFTUNE_32_40    13
16092 #define M_T5_STATIC_M_PLL_LFTUNE_32_40    0x1ffU
16093 #define V_T5_STATIC_M_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_M_PLL_LFTUNE_32_40)
16094 #define G_T5_STATIC_M_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_M_PLL_LFTUNE_32_40) & M_T5_STATIC_M_PLL_LFTUNE_32_40)
16095 
16096 #define S_T5_STATIC_M_PLL_PREDIV    8
16097 #define M_T5_STATIC_M_PLL_PREDIV    0x1fU
16098 #define V_T5_STATIC_M_PLL_PREDIV(x) ((x) << S_T5_STATIC_M_PLL_PREDIV)
16099 #define G_T5_STATIC_M_PLL_PREDIV(x) (((x) >> S_T5_STATIC_M_PLL_PREDIV) & M_T5_STATIC_M_PLL_PREDIV)
16100 
16101 #define S_T5_STATIC_M_PLL_MULT    0
16102 #define M_T5_STATIC_M_PLL_MULT    0xffU
16103 #define V_T5_STATIC_M_PLL_MULT(x) ((x) << S_T5_STATIC_M_PLL_MULT)
16104 #define G_T5_STATIC_M_PLL_MULT(x) (((x) >> S_T5_STATIC_M_PLL_MULT) & M_T5_STATIC_M_PLL_MULT)
16105 
16106 #define A_DBG_STATIC_M_PLL_CONF5 0x60c8
16107 
16108 #define S_STATIC_M_PLL_VCVTUNE    24
16109 #define M_STATIC_M_PLL_VCVTUNE    0x7U
16110 #define V_STATIC_M_PLL_VCVTUNE(x) ((x) << S_STATIC_M_PLL_VCVTUNE)
16111 #define G_STATIC_M_PLL_VCVTUNE(x) (((x) >> S_STATIC_M_PLL_VCVTUNE) & M_STATIC_M_PLL_VCVTUNE)
16112 
16113 #define S_T6_STATIC_M_PLL_RESET    23
16114 #define V_T6_STATIC_M_PLL_RESET(x) ((x) << S_T6_STATIC_M_PLL_RESET)
16115 #define F_T6_STATIC_M_PLL_RESET    V_T6_STATIC_M_PLL_RESET(1U)
16116 
16117 #define S_STATIC_MPLL_REFCLK_SEL    22
16118 #define V_STATIC_MPLL_REFCLK_SEL(x) ((x) << S_STATIC_MPLL_REFCLK_SEL)
16119 #define F_STATIC_MPLL_REFCLK_SEL    V_STATIC_MPLL_REFCLK_SEL(1U)
16120 
16121 #define S_STATIC_M_PLL_LFTUNE_32_40    13
16122 #define M_STATIC_M_PLL_LFTUNE_32_40    0x1ffU
16123 #define V_STATIC_M_PLL_LFTUNE_32_40(x) ((x) << S_STATIC_M_PLL_LFTUNE_32_40)
16124 #define G_STATIC_M_PLL_LFTUNE_32_40(x) (((x) >> S_STATIC_M_PLL_LFTUNE_32_40) & M_STATIC_M_PLL_LFTUNE_32_40)
16125 
16126 #define S_T6_STATIC_M_PLL_MULT    0
16127 #define M_T6_STATIC_M_PLL_MULT    0xffU
16128 #define V_T6_STATIC_M_PLL_MULT(x) ((x) << S_T6_STATIC_M_PLL_MULT)
16129 #define G_T6_STATIC_M_PLL_MULT(x) (((x) >> S_T6_STATIC_M_PLL_MULT) & M_T6_STATIC_M_PLL_MULT)
16130 
16131 #define A_DBG_STATIC_ARM_PLL_CONF1 0x60c8
16132 
16133 #define S_STATIC_ARM_PLL_RANGE    22
16134 #define M_STATIC_ARM_PLL_RANGE    0x7U
16135 #define V_STATIC_ARM_PLL_RANGE(x) ((x) << S_STATIC_ARM_PLL_RANGE)
16136 #define G_STATIC_ARM_PLL_RANGE(x) (((x) >> S_STATIC_ARM_PLL_RANGE) & M_STATIC_ARM_PLL_RANGE)
16137 
16138 #define S_STATIC_ARM_PLL_DIVQ    17
16139 #define M_STATIC_ARM_PLL_DIVQ    0x1fU
16140 #define V_STATIC_ARM_PLL_DIVQ(x) ((x) << S_STATIC_ARM_PLL_DIVQ)
16141 #define G_STATIC_ARM_PLL_DIVQ(x) (((x) >> S_STATIC_ARM_PLL_DIVQ) & M_STATIC_ARM_PLL_DIVQ)
16142 
16143 #define S_STATIC_ARM_PLL_DIVFI    8
16144 #define M_STATIC_ARM_PLL_DIVFI    0x1ffU
16145 #define V_STATIC_ARM_PLL_DIVFI(x) ((x) << S_STATIC_ARM_PLL_DIVFI)
16146 #define G_STATIC_ARM_PLL_DIVFI(x) (((x) >> S_STATIC_ARM_PLL_DIVFI) & M_STATIC_ARM_PLL_DIVFI)
16147 
16148 #define S_STATIC_ARM_PLL_DIVR    2
16149 #define M_STATIC_ARM_PLL_DIVR    0x3fU
16150 #define V_STATIC_ARM_PLL_DIVR(x) ((x) << S_STATIC_ARM_PLL_DIVR)
16151 #define G_STATIC_ARM_PLL_DIVR(x) (((x) >> S_STATIC_ARM_PLL_DIVR) & M_STATIC_ARM_PLL_DIVR)
16152 
16153 #define S_STATIC_ARM_PLL_BYPASS    1
16154 #define V_STATIC_ARM_PLL_BYPASS(x) ((x) << S_STATIC_ARM_PLL_BYPASS)
16155 #define F_STATIC_ARM_PLL_BYPASS    V_STATIC_ARM_PLL_BYPASS(1U)
16156 
16157 #define S_STATIC_ARM_PLL_RESET    0
16158 #define V_STATIC_ARM_PLL_RESET(x) ((x) << S_STATIC_ARM_PLL_RESET)
16159 #define F_STATIC_ARM_PLL_RESET    V_STATIC_ARM_PLL_RESET(1U)
16160 
16161 #define A_DBG_T5_STATIC_M_PLL_CONF6 0x60cc
16162 
16163 #define S_T5_STATIC_PHY0RECRST_    5
16164 #define V_T5_STATIC_PHY0RECRST_(x) ((x) << S_T5_STATIC_PHY0RECRST_)
16165 #define F_T5_STATIC_PHY0RECRST_    V_T5_STATIC_PHY0RECRST_(1U)
16166 
16167 #define S_T5_STATIC_PHY1RECRST_    4
16168 #define V_T5_STATIC_PHY1RECRST_(x) ((x) << S_T5_STATIC_PHY1RECRST_)
16169 #define F_T5_STATIC_PHY1RECRST_    V_T5_STATIC_PHY1RECRST_(1U)
16170 
16171 #define S_T5_STATIC_SWMC0RST_    3
16172 #define V_T5_STATIC_SWMC0RST_(x) ((x) << S_T5_STATIC_SWMC0RST_)
16173 #define F_T5_STATIC_SWMC0RST_    V_T5_STATIC_SWMC0RST_(1U)
16174 
16175 #define S_T5_STATIC_SWMC0CFGRST_    2
16176 #define V_T5_STATIC_SWMC0CFGRST_(x) ((x) << S_T5_STATIC_SWMC0CFGRST_)
16177 #define F_T5_STATIC_SWMC0CFGRST_    V_T5_STATIC_SWMC0CFGRST_(1U)
16178 
16179 #define S_T5_STATIC_SWMC1RST_    1
16180 #define V_T5_STATIC_SWMC1RST_(x) ((x) << S_T5_STATIC_SWMC1RST_)
16181 #define F_T5_STATIC_SWMC1RST_    V_T5_STATIC_SWMC1RST_(1U)
16182 
16183 #define S_T5_STATIC_SWMC1CFGRST_    0
16184 #define V_T5_STATIC_SWMC1CFGRST_(x) ((x) << S_T5_STATIC_SWMC1CFGRST_)
16185 #define F_T5_STATIC_SWMC1CFGRST_    V_T5_STATIC_SWMC1CFGRST_(1U)
16186 
16187 #define A_DBG_STATIC_M_PLL_CONF6 0x60cc
16188 
16189 #define S_STATIC_M_PLL_DIVCHANGE    30
16190 #define V_STATIC_M_PLL_DIVCHANGE(x) ((x) << S_STATIC_M_PLL_DIVCHANGE)
16191 #define F_STATIC_M_PLL_DIVCHANGE    V_STATIC_M_PLL_DIVCHANGE(1U)
16192 
16193 #define S_STATIC_M_PLL_FRAMESTOP    29
16194 #define V_STATIC_M_PLL_FRAMESTOP(x) ((x) << S_STATIC_M_PLL_FRAMESTOP)
16195 #define F_STATIC_M_PLL_FRAMESTOP    V_STATIC_M_PLL_FRAMESTOP(1U)
16196 
16197 #define S_STATIC_M_PLL_FASTSTOP    28
16198 #define V_STATIC_M_PLL_FASTSTOP(x) ((x) << S_STATIC_M_PLL_FASTSTOP)
16199 #define F_STATIC_M_PLL_FASTSTOP    V_STATIC_M_PLL_FASTSTOP(1U)
16200 
16201 #define S_STATIC_M_PLL_FFBYPASS    27
16202 #define V_STATIC_M_PLL_FFBYPASS(x) ((x) << S_STATIC_M_PLL_FFBYPASS)
16203 #define F_STATIC_M_PLL_FFBYPASS    V_STATIC_M_PLL_FFBYPASS(1U)
16204 
16205 #define S_STATIC_M_PLL_STARTUP    25
16206 #define M_STATIC_M_PLL_STARTUP    0x3U
16207 #define V_STATIC_M_PLL_STARTUP(x) ((x) << S_STATIC_M_PLL_STARTUP)
16208 #define G_STATIC_M_PLL_STARTUP(x) (((x) >> S_STATIC_M_PLL_STARTUP) & M_STATIC_M_PLL_STARTUP)
16209 
16210 #define S_STATIC_M_PLL_VREGTUNE    6
16211 #define M_STATIC_M_PLL_VREGTUNE    0x7ffffU
16212 #define V_STATIC_M_PLL_VREGTUNE(x) ((x) << S_STATIC_M_PLL_VREGTUNE)
16213 #define G_STATIC_M_PLL_VREGTUNE(x) (((x) >> S_STATIC_M_PLL_VREGTUNE) & M_STATIC_M_PLL_VREGTUNE)
16214 
16215 #define S_STATIC_PHY0RECRST_    5
16216 #define V_STATIC_PHY0RECRST_(x) ((x) << S_STATIC_PHY0RECRST_)
16217 #define F_STATIC_PHY0RECRST_    V_STATIC_PHY0RECRST_(1U)
16218 
16219 #define S_STATIC_PHY1RECRST_    4
16220 #define V_STATIC_PHY1RECRST_(x) ((x) << S_STATIC_PHY1RECRST_)
16221 #define F_STATIC_PHY1RECRST_    V_STATIC_PHY1RECRST_(1U)
16222 
16223 #define S_STATIC_SWMC0RST_    3
16224 #define V_STATIC_SWMC0RST_(x) ((x) << S_STATIC_SWMC0RST_)
16225 #define F_STATIC_SWMC0RST_    V_STATIC_SWMC0RST_(1U)
16226 
16227 #define S_STATIC_SWMC0CFGRST_    2
16228 #define V_STATIC_SWMC0CFGRST_(x) ((x) << S_STATIC_SWMC0CFGRST_)
16229 #define F_STATIC_SWMC0CFGRST_    V_STATIC_SWMC0CFGRST_(1U)
16230 
16231 #define S_STATIC_SWMC1RST_    1
16232 #define V_STATIC_SWMC1RST_(x) ((x) << S_STATIC_SWMC1RST_)
16233 #define F_STATIC_SWMC1RST_    V_STATIC_SWMC1RST_(1U)
16234 
16235 #define S_STATIC_SWMC1CFGRST_    0
16236 #define V_STATIC_SWMC1CFGRST_(x) ((x) << S_STATIC_SWMC1CFGRST_)
16237 #define F_STATIC_SWMC1CFGRST_    V_STATIC_SWMC1CFGRST_(1U)
16238 
16239 #define A_DBG_STATIC_ARM_PLL_CONF2 0x60cc
16240 
16241 #define S_STATIC_ARM_PLL_SSMF    5
16242 #define M_STATIC_ARM_PLL_SSMF    0xfU
16243 #define V_STATIC_ARM_PLL_SSMF(x) ((x) << S_STATIC_ARM_PLL_SSMF)
16244 #define G_STATIC_ARM_PLL_SSMF(x) (((x) >> S_STATIC_ARM_PLL_SSMF) & M_STATIC_ARM_PLL_SSMF)
16245 
16246 #define S_STATIC_ARM_PLL_SSMD    2
16247 #define M_STATIC_ARM_PLL_SSMD    0x7U
16248 #define V_STATIC_ARM_PLL_SSMD(x) ((x) << S_STATIC_ARM_PLL_SSMD)
16249 #define G_STATIC_ARM_PLL_SSMD(x) (((x) >> S_STATIC_ARM_PLL_SSMD) & M_STATIC_ARM_PLL_SSMD)
16250 
16251 #define S_STATIC_ARM_PLL_SSDS    1
16252 #define V_STATIC_ARM_PLL_SSDS(x) ((x) << S_STATIC_ARM_PLL_SSDS)
16253 #define F_STATIC_ARM_PLL_SSDS    V_STATIC_ARM_PLL_SSDS(1U)
16254 
16255 #define S_STATIC_ARM_PLL_SSE    0
16256 #define V_STATIC_ARM_PLL_SSE(x) ((x) << S_STATIC_ARM_PLL_SSE)
16257 #define F_STATIC_ARM_PLL_SSE    V_STATIC_ARM_PLL_SSE(1U)
16258 
16259 #define A_DBG_T5_STATIC_C_PLL_CONF1 0x60d0
16260 
16261 #define S_T5_STATIC_C_PLL_MULTFRAC    8
16262 #define M_T5_STATIC_C_PLL_MULTFRAC    0xffffffU
16263 #define V_T5_STATIC_C_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_C_PLL_MULTFRAC)
16264 #define G_T5_STATIC_C_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_C_PLL_MULTFRAC) & M_T5_STATIC_C_PLL_MULTFRAC)
16265 
16266 #define S_T5_STATIC_C_PLL_FFSLEWRATE    0
16267 #define M_T5_STATIC_C_PLL_FFSLEWRATE    0xffU
16268 #define V_T5_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_C_PLL_FFSLEWRATE)
16269 #define G_T5_STATIC_C_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_C_PLL_FFSLEWRATE) & M_T5_STATIC_C_PLL_FFSLEWRATE)
16270 
16271 #define A_DBG_STATIC_C_PLL_CONF1 0x60d0
16272 
16273 #define S_STATIC_C_PLL_MULTFRAC    8
16274 #define M_STATIC_C_PLL_MULTFRAC    0xffffffU
16275 #define V_STATIC_C_PLL_MULTFRAC(x) ((x) << S_STATIC_C_PLL_MULTFRAC)
16276 #define G_STATIC_C_PLL_MULTFRAC(x) (((x) >> S_STATIC_C_PLL_MULTFRAC) & M_STATIC_C_PLL_MULTFRAC)
16277 
16278 #define S_STATIC_C_PLL_FFSLEWRATE    0
16279 #define M_STATIC_C_PLL_FFSLEWRATE    0xffU
16280 #define V_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_STATIC_C_PLL_FFSLEWRATE)
16281 #define G_STATIC_C_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_C_PLL_FFSLEWRATE) & M_STATIC_C_PLL_FFSLEWRATE)
16282 
16283 #define A_DBG_STATIC_USB_PLL_CONF1 0x60d0
16284 
16285 #define S_STATIC_USB_PLL_RANGE    22
16286 #define M_STATIC_USB_PLL_RANGE    0x7U
16287 #define V_STATIC_USB_PLL_RANGE(x) ((x) << S_STATIC_USB_PLL_RANGE)
16288 #define G_STATIC_USB_PLL_RANGE(x) (((x) >> S_STATIC_USB_PLL_RANGE) & M_STATIC_USB_PLL_RANGE)
16289 
16290 #define S_STATIC_USB_PLL_DIVQ    17
16291 #define M_STATIC_USB_PLL_DIVQ    0x1fU
16292 #define V_STATIC_USB_PLL_DIVQ(x) ((x) << S_STATIC_USB_PLL_DIVQ)
16293 #define G_STATIC_USB_PLL_DIVQ(x) (((x) >> S_STATIC_USB_PLL_DIVQ) & M_STATIC_USB_PLL_DIVQ)
16294 
16295 #define S_STATIC_USB_PLL_DIVFI    8
16296 #define M_STATIC_USB_PLL_DIVFI    0x1ffU
16297 #define V_STATIC_USB_PLL_DIVFI(x) ((x) << S_STATIC_USB_PLL_DIVFI)
16298 #define G_STATIC_USB_PLL_DIVFI(x) (((x) >> S_STATIC_USB_PLL_DIVFI) & M_STATIC_USB_PLL_DIVFI)
16299 
16300 #define S_STATIC_USB_PLL_DIVR    2
16301 #define M_STATIC_USB_PLL_DIVR    0x3fU
16302 #define V_STATIC_USB_PLL_DIVR(x) ((x) << S_STATIC_USB_PLL_DIVR)
16303 #define G_STATIC_USB_PLL_DIVR(x) (((x) >> S_STATIC_USB_PLL_DIVR) & M_STATIC_USB_PLL_DIVR)
16304 
16305 #define S_STATIC_USB_PLL_BYPASS    1
16306 #define V_STATIC_USB_PLL_BYPASS(x) ((x) << S_STATIC_USB_PLL_BYPASS)
16307 #define F_STATIC_USB_PLL_BYPASS    V_STATIC_USB_PLL_BYPASS(1U)
16308 
16309 #define S_STATIC_USB_PLL_RESET    0
16310 #define V_STATIC_USB_PLL_RESET(x) ((x) << S_STATIC_USB_PLL_RESET)
16311 #define F_STATIC_USB_PLL_RESET    V_STATIC_USB_PLL_RESET(1U)
16312 
16313 #define A_DBG_T5_STATIC_C_PLL_CONF2 0x60d4
16314 
16315 #define S_T5_STATIC_C_PLL_DCO_BYPASS    23
16316 #define V_T5_STATIC_C_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_DCO_BYPASS)
16317 #define F_T5_STATIC_C_PLL_DCO_BYPASS    V_T5_STATIC_C_PLL_DCO_BYPASS(1U)
16318 
16319 #define S_T5_STATIC_C_PLL_SDORDER    21
16320 #define M_T5_STATIC_C_PLL_SDORDER    0x3U
16321 #define V_T5_STATIC_C_PLL_SDORDER(x) ((x) << S_T5_STATIC_C_PLL_SDORDER)
16322 #define G_T5_STATIC_C_PLL_SDORDER(x) (((x) >> S_T5_STATIC_C_PLL_SDORDER) & M_T5_STATIC_C_PLL_SDORDER)
16323 
16324 #define S_T5_STATIC_C_PLL_FFENABLE    20
16325 #define V_T5_STATIC_C_PLL_FFENABLE(x) ((x) << S_T5_STATIC_C_PLL_FFENABLE)
16326 #define F_T5_STATIC_C_PLL_FFENABLE    V_T5_STATIC_C_PLL_FFENABLE(1U)
16327 
16328 #define S_T5_STATIC_C_PLL_STOPCLKB    19
16329 #define V_T5_STATIC_C_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKB)
16330 #define F_T5_STATIC_C_PLL_STOPCLKB    V_T5_STATIC_C_PLL_STOPCLKB(1U)
16331 
16332 #define S_T5_STATIC_C_PLL_STOPCLKA    18
16333 #define V_T5_STATIC_C_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKA)
16334 #define F_T5_STATIC_C_PLL_STOPCLKA    V_T5_STATIC_C_PLL_STOPCLKA(1U)
16335 
16336 #define S_T5_STATIC_C_PLL_SLEEP    17
16337 #define V_T5_STATIC_C_PLL_SLEEP(x) ((x) << S_T5_STATIC_C_PLL_SLEEP)
16338 #define F_T5_STATIC_C_PLL_SLEEP    V_T5_STATIC_C_PLL_SLEEP(1U)
16339 
16340 #define S_T5_STATIC_C_PLL_BYPASS    16
16341 #define V_T5_STATIC_C_PLL_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_BYPASS)
16342 #define F_T5_STATIC_C_PLL_BYPASS    V_T5_STATIC_C_PLL_BYPASS(1U)
16343 
16344 #define S_T5_STATIC_C_PLL_LOCKTUNE    0
16345 #define M_T5_STATIC_C_PLL_LOCKTUNE    0xffffU
16346 #define V_T5_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_C_PLL_LOCKTUNE)
16347 #define G_T5_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_C_PLL_LOCKTUNE) & M_T5_STATIC_C_PLL_LOCKTUNE)
16348 
16349 #define A_DBG_STATIC_C_PLL_CONF2 0x60d4
16350 
16351 #define S_T6_STATIC_C_PLL_PREDIV    26
16352 #define M_T6_STATIC_C_PLL_PREDIV    0x3fU
16353 #define V_T6_STATIC_C_PLL_PREDIV(x) ((x) << S_T6_STATIC_C_PLL_PREDIV)
16354 #define G_T6_STATIC_C_PLL_PREDIV(x) (((x) >> S_T6_STATIC_C_PLL_PREDIV) & M_T6_STATIC_C_PLL_PREDIV)
16355 
16356 #define S_STATIC_C_PLL_STARTUP    24
16357 #define M_STATIC_C_PLL_STARTUP    0x3U
16358 #define V_STATIC_C_PLL_STARTUP(x) ((x) << S_STATIC_C_PLL_STARTUP)
16359 #define G_STATIC_C_PLL_STARTUP(x) (((x) >> S_STATIC_C_PLL_STARTUP) & M_STATIC_C_PLL_STARTUP)
16360 
16361 #define S_STATIC_C_PLL_DCO_BYPASS    23
16362 #define V_STATIC_C_PLL_DCO_BYPASS(x) ((x) << S_STATIC_C_PLL_DCO_BYPASS)
16363 #define F_STATIC_C_PLL_DCO_BYPASS    V_STATIC_C_PLL_DCO_BYPASS(1U)
16364 
16365 #define S_STATIC_C_PLL_SDORDER    21
16366 #define M_STATIC_C_PLL_SDORDER    0x3U
16367 #define V_STATIC_C_PLL_SDORDER(x) ((x) << S_STATIC_C_PLL_SDORDER)
16368 #define G_STATIC_C_PLL_SDORDER(x) (((x) >> S_STATIC_C_PLL_SDORDER) & M_STATIC_C_PLL_SDORDER)
16369 
16370 #define S_STATIC_C_PLL_DIVCHANGE    20
16371 #define V_STATIC_C_PLL_DIVCHANGE(x) ((x) << S_STATIC_C_PLL_DIVCHANGE)
16372 #define F_STATIC_C_PLL_DIVCHANGE    V_STATIC_C_PLL_DIVCHANGE(1U)
16373 
16374 #define S_STATIC_C_PLL_STOPCLKB    19
16375 #define V_STATIC_C_PLL_STOPCLKB(x) ((x) << S_STATIC_C_PLL_STOPCLKB)
16376 #define F_STATIC_C_PLL_STOPCLKB    V_STATIC_C_PLL_STOPCLKB(1U)
16377 
16378 #define S_STATIC_C_PLL_STOPCLKA    18
16379 #define V_STATIC_C_PLL_STOPCLKA(x) ((x) << S_STATIC_C_PLL_STOPCLKA)
16380 #define F_STATIC_C_PLL_STOPCLKA    V_STATIC_C_PLL_STOPCLKA(1U)
16381 
16382 #define S_T6_STATIC_C_PLL_SLEEP    17
16383 #define V_T6_STATIC_C_PLL_SLEEP(x) ((x) << S_T6_STATIC_C_PLL_SLEEP)
16384 #define F_T6_STATIC_C_PLL_SLEEP    V_T6_STATIC_C_PLL_SLEEP(1U)
16385 
16386 #define S_T6_STATIC_C_PLL_BYPASS    16
16387 #define V_T6_STATIC_C_PLL_BYPASS(x) ((x) << S_T6_STATIC_C_PLL_BYPASS)
16388 #define F_T6_STATIC_C_PLL_BYPASS    V_T6_STATIC_C_PLL_BYPASS(1U)
16389 
16390 #define S_STATIC_C_PLL_LOCKTUNE    0
16391 #define M_STATIC_C_PLL_LOCKTUNE    0x1fU
16392 #define V_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_STATIC_C_PLL_LOCKTUNE)
16393 #define G_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_STATIC_C_PLL_LOCKTUNE) & M_STATIC_C_PLL_LOCKTUNE)
16394 
16395 #define A_DBG_STATIC_USB_PLL_CONF2 0x60d4
16396 
16397 #define S_STATIC_USB_PLL_SSMF    5
16398 #define M_STATIC_USB_PLL_SSMF    0xfU
16399 #define V_STATIC_USB_PLL_SSMF(x) ((x) << S_STATIC_USB_PLL_SSMF)
16400 #define G_STATIC_USB_PLL_SSMF(x) (((x) >> S_STATIC_USB_PLL_SSMF) & M_STATIC_USB_PLL_SSMF)
16401 
16402 #define S_STATIC_USB_PLL_SSMD    2
16403 #define M_STATIC_USB_PLL_SSMD    0x7U
16404 #define V_STATIC_USB_PLL_SSMD(x) ((x) << S_STATIC_USB_PLL_SSMD)
16405 #define G_STATIC_USB_PLL_SSMD(x) (((x) >> S_STATIC_USB_PLL_SSMD) & M_STATIC_USB_PLL_SSMD)
16406 
16407 #define S_STATIC_USB_PLL_SSDS    1
16408 #define V_STATIC_USB_PLL_SSDS(x) ((x) << S_STATIC_USB_PLL_SSDS)
16409 #define F_STATIC_USB_PLL_SSDS    V_STATIC_USB_PLL_SSDS(1U)
16410 
16411 #define S_STATIC_USB_PLL_SSE    0
16412 #define V_STATIC_USB_PLL_SSE(x) ((x) << S_STATIC_USB_PLL_SSE)
16413 #define F_STATIC_USB_PLL_SSE    V_STATIC_USB_PLL_SSE(1U)
16414 
16415 #define A_DBG_T5_STATIC_C_PLL_CONF3 0x60d8
16416 
16417 #define S_T5_STATIC_C_PLL_MULTPRE    30
16418 #define M_T5_STATIC_C_PLL_MULTPRE    0x3U
16419 #define V_T5_STATIC_C_PLL_MULTPRE(x) ((x) << S_T5_STATIC_C_PLL_MULTPRE)
16420 #define G_T5_STATIC_C_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_C_PLL_MULTPRE) & M_T5_STATIC_C_PLL_MULTPRE)
16421 
16422 #define S_T5_STATIC_C_PLL_LOCKSEL    28
16423 #define M_T5_STATIC_C_PLL_LOCKSEL    0x3U
16424 #define V_T5_STATIC_C_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_C_PLL_LOCKSEL)
16425 #define G_T5_STATIC_C_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_C_PLL_LOCKSEL) & M_T5_STATIC_C_PLL_LOCKSEL)
16426 
16427 #define S_T5_STATIC_C_PLL_FFTUNE    12
16428 #define M_T5_STATIC_C_PLL_FFTUNE    0xffffU
16429 #define V_T5_STATIC_C_PLL_FFTUNE(x) ((x) << S_T5_STATIC_C_PLL_FFTUNE)
16430 #define G_T5_STATIC_C_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_C_PLL_FFTUNE) & M_T5_STATIC_C_PLL_FFTUNE)
16431 
16432 #define S_T5_STATIC_C_PLL_RANGEPRE    10
16433 #define M_T5_STATIC_C_PLL_RANGEPRE    0x3U
16434 #define V_T5_STATIC_C_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_C_PLL_RANGEPRE)
16435 #define G_T5_STATIC_C_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_C_PLL_RANGEPRE) & M_T5_STATIC_C_PLL_RANGEPRE)
16436 
16437 #define S_T5_STATIC_C_PLL_RANGEB    5
16438 #define M_T5_STATIC_C_PLL_RANGEB    0x1fU
16439 #define V_T5_STATIC_C_PLL_RANGEB(x) ((x) << S_T5_STATIC_C_PLL_RANGEB)
16440 #define G_T5_STATIC_C_PLL_RANGEB(x) (((x) >> S_T5_STATIC_C_PLL_RANGEB) & M_T5_STATIC_C_PLL_RANGEB)
16441 
16442 #define S_T5_STATIC_C_PLL_RANGEA    0
16443 #define M_T5_STATIC_C_PLL_RANGEA    0x1fU
16444 #define V_T5_STATIC_C_PLL_RANGEA(x) ((x) << S_T5_STATIC_C_PLL_RANGEA)
16445 #define G_T5_STATIC_C_PLL_RANGEA(x) (((x) >> S_T5_STATIC_C_PLL_RANGEA) & M_T5_STATIC_C_PLL_RANGEA)
16446 
16447 #define A_DBG_STATIC_C_PLL_CONF3 0x60d8
16448 
16449 #define S_STATIC_C_PLL_MULTPRE    30
16450 #define M_STATIC_C_PLL_MULTPRE    0x3U
16451 #define V_STATIC_C_PLL_MULTPRE(x) ((x) << S_STATIC_C_PLL_MULTPRE)
16452 #define G_STATIC_C_PLL_MULTPRE(x) (((x) >> S_STATIC_C_PLL_MULTPRE) & M_STATIC_C_PLL_MULTPRE)
16453 
16454 #define S_STATIC_C_PLL_LOCKSEL    28
16455 #define V_STATIC_C_PLL_LOCKSEL(x) ((x) << S_STATIC_C_PLL_LOCKSEL)
16456 #define F_STATIC_C_PLL_LOCKSEL    V_STATIC_C_PLL_LOCKSEL(1U)
16457 
16458 #define S_STATIC_C_PLL_FFTUNE    12
16459 #define M_STATIC_C_PLL_FFTUNE    0xffffU
16460 #define V_STATIC_C_PLL_FFTUNE(x) ((x) << S_STATIC_C_PLL_FFTUNE)
16461 #define G_STATIC_C_PLL_FFTUNE(x) (((x) >> S_STATIC_C_PLL_FFTUNE) & M_STATIC_C_PLL_FFTUNE)
16462 
16463 #define S_STATIC_C_PLL_RANGEPRE    10
16464 #define M_STATIC_C_PLL_RANGEPRE    0x3U
16465 #define V_STATIC_C_PLL_RANGEPRE(x) ((x) << S_STATIC_C_PLL_RANGEPRE)
16466 #define G_STATIC_C_PLL_RANGEPRE(x) (((x) >> S_STATIC_C_PLL_RANGEPRE) & M_STATIC_C_PLL_RANGEPRE)
16467 
16468 #define S_T6_STATIC_C_PLL_RANGEB    5
16469 #define M_T6_STATIC_C_PLL_RANGEB    0x1fU
16470 #define V_T6_STATIC_C_PLL_RANGEB(x) ((x) << S_T6_STATIC_C_PLL_RANGEB)
16471 #define G_T6_STATIC_C_PLL_RANGEB(x) (((x) >> S_T6_STATIC_C_PLL_RANGEB) & M_T6_STATIC_C_PLL_RANGEB)
16472 
16473 #define S_T6_STATIC_C_PLL_RANGEA    0
16474 #define M_T6_STATIC_C_PLL_RANGEA    0x1fU
16475 #define V_T6_STATIC_C_PLL_RANGEA(x) ((x) << S_T6_STATIC_C_PLL_RANGEA)
16476 #define G_T6_STATIC_C_PLL_RANGEA(x) (((x) >> S_T6_STATIC_C_PLL_RANGEA) & M_T6_STATIC_C_PLL_RANGEA)
16477 
16478 #define A_DBG_STATIC_XGPHY_PLL_CONF1 0x60d8
16479 
16480 #define S_STATIC_XGPHY_PLL_RANGE    22
16481 #define M_STATIC_XGPHY_PLL_RANGE    0x7U
16482 #define V_STATIC_XGPHY_PLL_RANGE(x) ((x) << S_STATIC_XGPHY_PLL_RANGE)
16483 #define G_STATIC_XGPHY_PLL_RANGE(x) (((x) >> S_STATIC_XGPHY_PLL_RANGE) & M_STATIC_XGPHY_PLL_RANGE)
16484 
16485 #define S_STATIC_XGPHY_PLL_DIVQ    17
16486 #define M_STATIC_XGPHY_PLL_DIVQ    0x1fU
16487 #define V_STATIC_XGPHY_PLL_DIVQ(x) ((x) << S_STATIC_XGPHY_PLL_DIVQ)
16488 #define G_STATIC_XGPHY_PLL_DIVQ(x) (((x) >> S_STATIC_XGPHY_PLL_DIVQ) & M_STATIC_XGPHY_PLL_DIVQ)
16489 
16490 #define S_STATIC_XGPHY_PLL_DIVFI    8
16491 #define M_STATIC_XGPHY_PLL_DIVFI    0x1ffU
16492 #define V_STATIC_XGPHY_PLL_DIVFI(x) ((x) << S_STATIC_XGPHY_PLL_DIVFI)
16493 #define G_STATIC_XGPHY_PLL_DIVFI(x) (((x) >> S_STATIC_XGPHY_PLL_DIVFI) & M_STATIC_XGPHY_PLL_DIVFI)
16494 
16495 #define S_STATIC_XGPHY_PLL_DIVR    2
16496 #define M_STATIC_XGPHY_PLL_DIVR    0x3fU
16497 #define V_STATIC_XGPHY_PLL_DIVR(x) ((x) << S_STATIC_XGPHY_PLL_DIVR)
16498 #define G_STATIC_XGPHY_PLL_DIVR(x) (((x) >> S_STATIC_XGPHY_PLL_DIVR) & M_STATIC_XGPHY_PLL_DIVR)
16499 
16500 #define S_STATIC_XGPHY_PLL_BYPASS    1
16501 #define V_STATIC_XGPHY_PLL_BYPASS(x) ((x) << S_STATIC_XGPHY_PLL_BYPASS)
16502 #define F_STATIC_XGPHY_PLL_BYPASS    V_STATIC_XGPHY_PLL_BYPASS(1U)
16503 
16504 #define S_STATIC_XGPHY_PLL_RESET    0
16505 #define V_STATIC_XGPHY_PLL_RESET(x) ((x) << S_STATIC_XGPHY_PLL_RESET)
16506 #define F_STATIC_XGPHY_PLL_RESET    V_STATIC_XGPHY_PLL_RESET(1U)
16507 
16508 #define A_DBG_T5_STATIC_C_PLL_CONF4 0x60dc
16509 #define A_DBG_STATIC_C_PLL_CONF4 0x60dc
16510 #define A_DBG_STATIC_XGPHY_PLL_CONF2 0x60dc
16511 
16512 #define S_STATIC_XGPHY_PLL_SSMF    5
16513 #define M_STATIC_XGPHY_PLL_SSMF    0xfU
16514 #define V_STATIC_XGPHY_PLL_SSMF(x) ((x) << S_STATIC_XGPHY_PLL_SSMF)
16515 #define G_STATIC_XGPHY_PLL_SSMF(x) (((x) >> S_STATIC_XGPHY_PLL_SSMF) & M_STATIC_XGPHY_PLL_SSMF)
16516 
16517 #define S_STATIC_XGPHY_PLL_SSMD    2
16518 #define M_STATIC_XGPHY_PLL_SSMD    0x7U
16519 #define V_STATIC_XGPHY_PLL_SSMD(x) ((x) << S_STATIC_XGPHY_PLL_SSMD)
16520 #define G_STATIC_XGPHY_PLL_SSMD(x) (((x) >> S_STATIC_XGPHY_PLL_SSMD) & M_STATIC_XGPHY_PLL_SSMD)
16521 
16522 #define S_STATIC_XGPHY_PLL_SSDS    1
16523 #define V_STATIC_XGPHY_PLL_SSDS(x) ((x) << S_STATIC_XGPHY_PLL_SSDS)
16524 #define F_STATIC_XGPHY_PLL_SSDS    V_STATIC_XGPHY_PLL_SSDS(1U)
16525 
16526 #define S_STATIC_XGPHY_PLL_SSE    0
16527 #define V_STATIC_XGPHY_PLL_SSE(x) ((x) << S_STATIC_XGPHY_PLL_SSE)
16528 #define F_STATIC_XGPHY_PLL_SSE    V_STATIC_XGPHY_PLL_SSE(1U)
16529 
16530 #define A_DBG_T5_STATIC_C_PLL_CONF5 0x60e0
16531 
16532 #define S_T5_STATIC_C_PLL_VCVTUNE    22
16533 #define M_T5_STATIC_C_PLL_VCVTUNE    0x7U
16534 #define V_T5_STATIC_C_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_C_PLL_VCVTUNE)
16535 #define G_T5_STATIC_C_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_C_PLL_VCVTUNE) & M_T5_STATIC_C_PLL_VCVTUNE)
16536 
16537 #define S_T5_STATIC_C_PLL_LFTUNE_32_40    13
16538 #define M_T5_STATIC_C_PLL_LFTUNE_32_40    0x1ffU
16539 #define V_T5_STATIC_C_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_C_PLL_LFTUNE_32_40)
16540 #define G_T5_STATIC_C_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_C_PLL_LFTUNE_32_40) & M_T5_STATIC_C_PLL_LFTUNE_32_40)
16541 
16542 #define S_T5_STATIC_C_PLL_PREDIV    8
16543 #define M_T5_STATIC_C_PLL_PREDIV    0x1fU
16544 #define V_T5_STATIC_C_PLL_PREDIV(x) ((x) << S_T5_STATIC_C_PLL_PREDIV)
16545 #define G_T5_STATIC_C_PLL_PREDIV(x) (((x) >> S_T5_STATIC_C_PLL_PREDIV) & M_T5_STATIC_C_PLL_PREDIV)
16546 
16547 #define S_T5_STATIC_C_PLL_MULT    0
16548 #define M_T5_STATIC_C_PLL_MULT    0xffU
16549 #define V_T5_STATIC_C_PLL_MULT(x) ((x) << S_T5_STATIC_C_PLL_MULT)
16550 #define G_T5_STATIC_C_PLL_MULT(x) (((x) >> S_T5_STATIC_C_PLL_MULT) & M_T5_STATIC_C_PLL_MULT)
16551 
16552 #define A_DBG_STATIC_C_PLL_CONF5 0x60e0
16553 
16554 #define S_STATIC_C_PLL_FFBYPASS    27
16555 #define V_STATIC_C_PLL_FFBYPASS(x) ((x) << S_STATIC_C_PLL_FFBYPASS)
16556 #define F_STATIC_C_PLL_FFBYPASS    V_STATIC_C_PLL_FFBYPASS(1U)
16557 
16558 #define S_STATIC_C_PLL_FASTSTOP    26
16559 #define V_STATIC_C_PLL_FASTSTOP(x) ((x) << S_STATIC_C_PLL_FASTSTOP)
16560 #define F_STATIC_C_PLL_FASTSTOP    V_STATIC_C_PLL_FASTSTOP(1U)
16561 
16562 #define S_STATIC_C_PLL_FRAMESTOP    25
16563 #define V_STATIC_C_PLL_FRAMESTOP(x) ((x) << S_STATIC_C_PLL_FRAMESTOP)
16564 #define F_STATIC_C_PLL_FRAMESTOP    V_STATIC_C_PLL_FRAMESTOP(1U)
16565 
16566 #define S_STATIC_C_PLL_VCVTUNE    22
16567 #define M_STATIC_C_PLL_VCVTUNE    0x7U
16568 #define V_STATIC_C_PLL_VCVTUNE(x) ((x) << S_STATIC_C_PLL_VCVTUNE)
16569 #define G_STATIC_C_PLL_VCVTUNE(x) (((x) >> S_STATIC_C_PLL_VCVTUNE) & M_STATIC_C_PLL_VCVTUNE)
16570 
16571 #define S_STATIC_C_PLL_LFTUNE_32_40    13
16572 #define M_STATIC_C_PLL_LFTUNE_32_40    0x1ffU
16573 #define V_STATIC_C_PLL_LFTUNE_32_40(x) ((x) << S_STATIC_C_PLL_LFTUNE_32_40)
16574 #define G_STATIC_C_PLL_LFTUNE_32_40(x) (((x) >> S_STATIC_C_PLL_LFTUNE_32_40) & M_STATIC_C_PLL_LFTUNE_32_40)
16575 
16576 #define S_STATIC_C_PLL_PREDIV_CNF5    8
16577 #define M_STATIC_C_PLL_PREDIV_CNF5    0x1fU
16578 #define V_STATIC_C_PLL_PREDIV_CNF5(x) ((x) << S_STATIC_C_PLL_PREDIV_CNF5)
16579 #define G_STATIC_C_PLL_PREDIV_CNF5(x) (((x) >> S_STATIC_C_PLL_PREDIV_CNF5) & M_STATIC_C_PLL_PREDIV_CNF5)
16580 
16581 #define S_T6_STATIC_C_PLL_MULT    0
16582 #define M_T6_STATIC_C_PLL_MULT    0xffU
16583 #define V_T6_STATIC_C_PLL_MULT(x) ((x) << S_T6_STATIC_C_PLL_MULT)
16584 #define G_T6_STATIC_C_PLL_MULT(x) (((x) >> S_T6_STATIC_C_PLL_MULT) & M_T6_STATIC_C_PLL_MULT)
16585 
16586 #define A_DBG_STATIC_XGPBUS_PLL_CONF1 0x60e0
16587 
16588 #define S_STATIC_XGPBUS_SWRST_    25
16589 #define V_STATIC_XGPBUS_SWRST_(x) ((x) << S_STATIC_XGPBUS_SWRST_)
16590 #define F_STATIC_XGPBUS_SWRST_    V_STATIC_XGPBUS_SWRST_(1U)
16591 
16592 #define S_STATIC_XGPBUS_PLL_RANGE    22
16593 #define M_STATIC_XGPBUS_PLL_RANGE    0x7U
16594 #define V_STATIC_XGPBUS_PLL_RANGE(x) ((x) << S_STATIC_XGPBUS_PLL_RANGE)
16595 #define G_STATIC_XGPBUS_PLL_RANGE(x) (((x) >> S_STATIC_XGPBUS_PLL_RANGE) & M_STATIC_XGPBUS_PLL_RANGE)
16596 
16597 #define S_STATIC_XGPBUS_PLL_DIVQ    17
16598 #define M_STATIC_XGPBUS_PLL_DIVQ    0x1fU
16599 #define V_STATIC_XGPBUS_PLL_DIVQ(x) ((x) << S_STATIC_XGPBUS_PLL_DIVQ)
16600 #define G_STATIC_XGPBUS_PLL_DIVQ(x) (((x) >> S_STATIC_XGPBUS_PLL_DIVQ) & M_STATIC_XGPBUS_PLL_DIVQ)
16601 
16602 #define S_STATIC_XGPBUS_PLL_DIVFI    8
16603 #define M_STATIC_XGPBUS_PLL_DIVFI    0x1ffU
16604 #define V_STATIC_XGPBUS_PLL_DIVFI(x) ((x) << S_STATIC_XGPBUS_PLL_DIVFI)
16605 #define G_STATIC_XGPBUS_PLL_DIVFI(x) (((x) >> S_STATIC_XGPBUS_PLL_DIVFI) & M_STATIC_XGPBUS_PLL_DIVFI)
16606 
16607 #define S_STATIC_XGPBUS_PLL_DIVR    2
16608 #define M_STATIC_XGPBUS_PLL_DIVR    0x3fU
16609 #define V_STATIC_XGPBUS_PLL_DIVR(x) ((x) << S_STATIC_XGPBUS_PLL_DIVR)
16610 #define G_STATIC_XGPBUS_PLL_DIVR(x) (((x) >> S_STATIC_XGPBUS_PLL_DIVR) & M_STATIC_XGPBUS_PLL_DIVR)
16611 
16612 #define S_STATIC_XGPBUS_PLL_BYPASS    1
16613 #define V_STATIC_XGPBUS_PLL_BYPASS(x) ((x) << S_STATIC_XGPBUS_PLL_BYPASS)
16614 #define F_STATIC_XGPBUS_PLL_BYPASS    V_STATIC_XGPBUS_PLL_BYPASS(1U)
16615 
16616 #define S_STATIC_XGPBUS_PLL_RESET    0
16617 #define V_STATIC_XGPBUS_PLL_RESET(x) ((x) << S_STATIC_XGPBUS_PLL_RESET)
16618 #define F_STATIC_XGPBUS_PLL_RESET    V_STATIC_XGPBUS_PLL_RESET(1U)
16619 
16620 #define A_DBG_T5_STATIC_U_PLL_CONF1 0x60e4
16621 
16622 #define S_T5_STATIC_U_PLL_MULTFRAC    8
16623 #define M_T5_STATIC_U_PLL_MULTFRAC    0xffffffU
16624 #define V_T5_STATIC_U_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_U_PLL_MULTFRAC)
16625 #define G_T5_STATIC_U_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_U_PLL_MULTFRAC) & M_T5_STATIC_U_PLL_MULTFRAC)
16626 
16627 #define S_T5_STATIC_U_PLL_FFSLEWRATE    0
16628 #define M_T5_STATIC_U_PLL_FFSLEWRATE    0xffU
16629 #define V_T5_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_U_PLL_FFSLEWRATE)
16630 #define G_T5_STATIC_U_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_U_PLL_FFSLEWRATE) & M_T5_STATIC_U_PLL_FFSLEWRATE)
16631 
16632 #define A_DBG_STATIC_U_PLL_CONF1 0x60e4
16633 
16634 #define S_STATIC_U_PLL_MULTFRAC    8
16635 #define M_STATIC_U_PLL_MULTFRAC    0xffffffU
16636 #define V_STATIC_U_PLL_MULTFRAC(x) ((x) << S_STATIC_U_PLL_MULTFRAC)
16637 #define G_STATIC_U_PLL_MULTFRAC(x) (((x) >> S_STATIC_U_PLL_MULTFRAC) & M_STATIC_U_PLL_MULTFRAC)
16638 
16639 #define S_STATIC_U_PLL_FFSLEWRATE    0
16640 #define M_STATIC_U_PLL_FFSLEWRATE    0xffU
16641 #define V_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_STATIC_U_PLL_FFSLEWRATE)
16642 #define G_STATIC_U_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_U_PLL_FFSLEWRATE) & M_STATIC_U_PLL_FFSLEWRATE)
16643 
16644 #define A_DBG_STATIC_XGPBUS_PLL_CONF2 0x60e4
16645 
16646 #define S_STATIC_XGPBUS_PLL_SSMF    5
16647 #define M_STATIC_XGPBUS_PLL_SSMF    0xfU
16648 #define V_STATIC_XGPBUS_PLL_SSMF(x) ((x) << S_STATIC_XGPBUS_PLL_SSMF)
16649 #define G_STATIC_XGPBUS_PLL_SSMF(x) (((x) >> S_STATIC_XGPBUS_PLL_SSMF) & M_STATIC_XGPBUS_PLL_SSMF)
16650 
16651 #define S_STATIC_XGPBUS_PLL_SSMD    2
16652 #define M_STATIC_XGPBUS_PLL_SSMD    0x7U
16653 #define V_STATIC_XGPBUS_PLL_SSMD(x) ((x) << S_STATIC_XGPBUS_PLL_SSMD)
16654 #define G_STATIC_XGPBUS_PLL_SSMD(x) (((x) >> S_STATIC_XGPBUS_PLL_SSMD) & M_STATIC_XGPBUS_PLL_SSMD)
16655 
16656 #define S_STATIC_XGPBUS_PLL_SSDS    1
16657 #define V_STATIC_XGPBUS_PLL_SSDS(x) ((x) << S_STATIC_XGPBUS_PLL_SSDS)
16658 #define F_STATIC_XGPBUS_PLL_SSDS    V_STATIC_XGPBUS_PLL_SSDS(1U)
16659 
16660 #define S_STATIC_XGPBUS_PLL_SSE    0
16661 #define V_STATIC_XGPBUS_PLL_SSE(x) ((x) << S_STATIC_XGPBUS_PLL_SSE)
16662 #define F_STATIC_XGPBUS_PLL_SSE    V_STATIC_XGPBUS_PLL_SSE(1U)
16663 
16664 #define A_DBG_T5_STATIC_U_PLL_CONF2 0x60e8
16665 
16666 #define S_T5_STATIC_U_PLL_DCO_BYPASS    23
16667 #define V_T5_STATIC_U_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_DCO_BYPASS)
16668 #define F_T5_STATIC_U_PLL_DCO_BYPASS    V_T5_STATIC_U_PLL_DCO_BYPASS(1U)
16669 
16670 #define S_T5_STATIC_U_PLL_SDORDER    21
16671 #define M_T5_STATIC_U_PLL_SDORDER    0x3U
16672 #define V_T5_STATIC_U_PLL_SDORDER(x) ((x) << S_T5_STATIC_U_PLL_SDORDER)
16673 #define G_T5_STATIC_U_PLL_SDORDER(x) (((x) >> S_T5_STATIC_U_PLL_SDORDER) & M_T5_STATIC_U_PLL_SDORDER)
16674 
16675 #define S_T5_STATIC_U_PLL_FFENABLE    20
16676 #define V_T5_STATIC_U_PLL_FFENABLE(x) ((x) << S_T5_STATIC_U_PLL_FFENABLE)
16677 #define F_T5_STATIC_U_PLL_FFENABLE    V_T5_STATIC_U_PLL_FFENABLE(1U)
16678 
16679 #define S_T5_STATIC_U_PLL_STOPCLKB    19
16680 #define V_T5_STATIC_U_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKB)
16681 #define F_T5_STATIC_U_PLL_STOPCLKB    V_T5_STATIC_U_PLL_STOPCLKB(1U)
16682 
16683 #define S_T5_STATIC_U_PLL_STOPCLKA    18
16684 #define V_T5_STATIC_U_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKA)
16685 #define F_T5_STATIC_U_PLL_STOPCLKA    V_T5_STATIC_U_PLL_STOPCLKA(1U)
16686 
16687 #define S_T5_STATIC_U_PLL_SLEEP    17
16688 #define V_T5_STATIC_U_PLL_SLEEP(x) ((x) << S_T5_STATIC_U_PLL_SLEEP)
16689 #define F_T5_STATIC_U_PLL_SLEEP    V_T5_STATIC_U_PLL_SLEEP(1U)
16690 
16691 #define S_T5_STATIC_U_PLL_BYPASS    16
16692 #define V_T5_STATIC_U_PLL_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_BYPASS)
16693 #define F_T5_STATIC_U_PLL_BYPASS    V_T5_STATIC_U_PLL_BYPASS(1U)
16694 
16695 #define S_T5_STATIC_U_PLL_LOCKTUNE    0
16696 #define M_T5_STATIC_U_PLL_LOCKTUNE    0xffffU
16697 #define V_T5_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_U_PLL_LOCKTUNE)
16698 #define G_T5_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_U_PLL_LOCKTUNE) & M_T5_STATIC_U_PLL_LOCKTUNE)
16699 
16700 #define A_DBG_STATIC_U_PLL_CONF2 0x60e8
16701 
16702 #define S_T6_STATIC_U_PLL_PREDIV    26
16703 #define M_T6_STATIC_U_PLL_PREDIV    0x3fU
16704 #define V_T6_STATIC_U_PLL_PREDIV(x) ((x) << S_T6_STATIC_U_PLL_PREDIV)
16705 #define G_T6_STATIC_U_PLL_PREDIV(x) (((x) >> S_T6_STATIC_U_PLL_PREDIV) & M_T6_STATIC_U_PLL_PREDIV)
16706 
16707 #define S_STATIC_U_PLL_STARTUP    24
16708 #define M_STATIC_U_PLL_STARTUP    0x3U
16709 #define V_STATIC_U_PLL_STARTUP(x) ((x) << S_STATIC_U_PLL_STARTUP)
16710 #define G_STATIC_U_PLL_STARTUP(x) (((x) >> S_STATIC_U_PLL_STARTUP) & M_STATIC_U_PLL_STARTUP)
16711 
16712 #define S_STATIC_U_PLL_DCO_BYPASS    23
16713 #define V_STATIC_U_PLL_DCO_BYPASS(x) ((x) << S_STATIC_U_PLL_DCO_BYPASS)
16714 #define F_STATIC_U_PLL_DCO_BYPASS    V_STATIC_U_PLL_DCO_BYPASS(1U)
16715 
16716 #define S_STATIC_U_PLL_SDORDER    21
16717 #define M_STATIC_U_PLL_SDORDER    0x3U
16718 #define V_STATIC_U_PLL_SDORDER(x) ((x) << S_STATIC_U_PLL_SDORDER)
16719 #define G_STATIC_U_PLL_SDORDER(x) (((x) >> S_STATIC_U_PLL_SDORDER) & M_STATIC_U_PLL_SDORDER)
16720 
16721 #define S_STATIC_U_PLL_DIVCHANGE    20
16722 #define V_STATIC_U_PLL_DIVCHANGE(x) ((x) << S_STATIC_U_PLL_DIVCHANGE)
16723 #define F_STATIC_U_PLL_DIVCHANGE    V_STATIC_U_PLL_DIVCHANGE(1U)
16724 
16725 #define S_STATIC_U_PLL_STOPCLKB    19
16726 #define V_STATIC_U_PLL_STOPCLKB(x) ((x) << S_STATIC_U_PLL_STOPCLKB)
16727 #define F_STATIC_U_PLL_STOPCLKB    V_STATIC_U_PLL_STOPCLKB(1U)
16728 
16729 #define S_STATIC_U_PLL_STOPCLKA    18
16730 #define V_STATIC_U_PLL_STOPCLKA(x) ((x) << S_STATIC_U_PLL_STOPCLKA)
16731 #define F_STATIC_U_PLL_STOPCLKA    V_STATIC_U_PLL_STOPCLKA(1U)
16732 
16733 #define S_T6_STATIC_U_PLL_SLEEP    17
16734 #define V_T6_STATIC_U_PLL_SLEEP(x) ((x) << S_T6_STATIC_U_PLL_SLEEP)
16735 #define F_T6_STATIC_U_PLL_SLEEP    V_T6_STATIC_U_PLL_SLEEP(1U)
16736 
16737 #define S_T6_STATIC_U_PLL_BYPASS    16
16738 #define V_T6_STATIC_U_PLL_BYPASS(x) ((x) << S_T6_STATIC_U_PLL_BYPASS)
16739 #define F_T6_STATIC_U_PLL_BYPASS    V_T6_STATIC_U_PLL_BYPASS(1U)
16740 
16741 #define S_STATIC_U_PLL_LOCKTUNE    0
16742 #define M_STATIC_U_PLL_LOCKTUNE    0x1fU
16743 #define V_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_STATIC_U_PLL_LOCKTUNE)
16744 #define G_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_STATIC_U_PLL_LOCKTUNE) & M_STATIC_U_PLL_LOCKTUNE)
16745 
16746 #define A_DBG_STATIC_M1_PLL_CONF1 0x60e8
16747 
16748 #define S_STATIC_M1_PLL_RANGE    22
16749 #define M_STATIC_M1_PLL_RANGE    0x7U
16750 #define V_STATIC_M1_PLL_RANGE(x) ((x) << S_STATIC_M1_PLL_RANGE)
16751 #define G_STATIC_M1_PLL_RANGE(x) (((x) >> S_STATIC_M1_PLL_RANGE) & M_STATIC_M1_PLL_RANGE)
16752 
16753 #define S_STATIC_M1_PLL_DIVQ    17
16754 #define M_STATIC_M1_PLL_DIVQ    0x1fU
16755 #define V_STATIC_M1_PLL_DIVQ(x) ((x) << S_STATIC_M1_PLL_DIVQ)
16756 #define G_STATIC_M1_PLL_DIVQ(x) (((x) >> S_STATIC_M1_PLL_DIVQ) & M_STATIC_M1_PLL_DIVQ)
16757 
16758 #define S_STATIC_M1_PLL_DIVFI    8
16759 #define M_STATIC_M1_PLL_DIVFI    0x1ffU
16760 #define V_STATIC_M1_PLL_DIVFI(x) ((x) << S_STATIC_M1_PLL_DIVFI)
16761 #define G_STATIC_M1_PLL_DIVFI(x) (((x) >> S_STATIC_M1_PLL_DIVFI) & M_STATIC_M1_PLL_DIVFI)
16762 
16763 #define S_STATIC_M1_PLL_DIVR    2
16764 #define M_STATIC_M1_PLL_DIVR    0x3fU
16765 #define V_STATIC_M1_PLL_DIVR(x) ((x) << S_STATIC_M1_PLL_DIVR)
16766 #define G_STATIC_M1_PLL_DIVR(x) (((x) >> S_STATIC_M1_PLL_DIVR) & M_STATIC_M1_PLL_DIVR)
16767 
16768 #define S_STATIC_M1_PLL_BYPASS    1
16769 #define V_STATIC_M1_PLL_BYPASS(x) ((x) << S_STATIC_M1_PLL_BYPASS)
16770 #define F_STATIC_M1_PLL_BYPASS    V_STATIC_M1_PLL_BYPASS(1U)
16771 
16772 #define S_STATIC_M1_PLL_RESET    0
16773 #define V_STATIC_M1_PLL_RESET(x) ((x) << S_STATIC_M1_PLL_RESET)
16774 #define F_STATIC_M1_PLL_RESET    V_STATIC_M1_PLL_RESET(1U)
16775 
16776 #define A_DBG_T5_STATIC_U_PLL_CONF3 0x60ec
16777 
16778 #define S_T5_STATIC_U_PLL_MULTPRE    30
16779 #define M_T5_STATIC_U_PLL_MULTPRE    0x3U
16780 #define V_T5_STATIC_U_PLL_MULTPRE(x) ((x) << S_T5_STATIC_U_PLL_MULTPRE)
16781 #define G_T5_STATIC_U_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_U_PLL_MULTPRE) & M_T5_STATIC_U_PLL_MULTPRE)
16782 
16783 #define S_T5_STATIC_U_PLL_LOCKSEL    28
16784 #define M_T5_STATIC_U_PLL_LOCKSEL    0x3U
16785 #define V_T5_STATIC_U_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_U_PLL_LOCKSEL)
16786 #define G_T5_STATIC_U_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_U_PLL_LOCKSEL) & M_T5_STATIC_U_PLL_LOCKSEL)
16787 
16788 #define S_T5_STATIC_U_PLL_FFTUNE    12
16789 #define M_T5_STATIC_U_PLL_FFTUNE    0xffffU
16790 #define V_T5_STATIC_U_PLL_FFTUNE(x) ((x) << S_T5_STATIC_U_PLL_FFTUNE)
16791 #define G_T5_STATIC_U_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_U_PLL_FFTUNE) & M_T5_STATIC_U_PLL_FFTUNE)
16792 
16793 #define S_T5_STATIC_U_PLL_RANGEPRE    10
16794 #define M_T5_STATIC_U_PLL_RANGEPRE    0x3U
16795 #define V_T5_STATIC_U_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_U_PLL_RANGEPRE)
16796 #define G_T5_STATIC_U_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_U_PLL_RANGEPRE) & M_T5_STATIC_U_PLL_RANGEPRE)
16797 
16798 #define S_T5_STATIC_U_PLL_RANGEB    5
16799 #define M_T5_STATIC_U_PLL_RANGEB    0x1fU
16800 #define V_T5_STATIC_U_PLL_RANGEB(x) ((x) << S_T5_STATIC_U_PLL_RANGEB)
16801 #define G_T5_STATIC_U_PLL_RANGEB(x) (((x) >> S_T5_STATIC_U_PLL_RANGEB) & M_T5_STATIC_U_PLL_RANGEB)
16802 
16803 #define S_T5_STATIC_U_PLL_RANGEA    0
16804 #define M_T5_STATIC_U_PLL_RANGEA    0x1fU
16805 #define V_T5_STATIC_U_PLL_RANGEA(x) ((x) << S_T5_STATIC_U_PLL_RANGEA)
16806 #define G_T5_STATIC_U_PLL_RANGEA(x) (((x) >> S_T5_STATIC_U_PLL_RANGEA) & M_T5_STATIC_U_PLL_RANGEA)
16807 
16808 #define A_DBG_STATIC_U_PLL_CONF3 0x60ec
16809 
16810 #define S_STATIC_U_PLL_MULTPRE    30
16811 #define M_STATIC_U_PLL_MULTPRE    0x3U
16812 #define V_STATIC_U_PLL_MULTPRE(x) ((x) << S_STATIC_U_PLL_MULTPRE)
16813 #define G_STATIC_U_PLL_MULTPRE(x) (((x) >> S_STATIC_U_PLL_MULTPRE) & M_STATIC_U_PLL_MULTPRE)
16814 
16815 #define S_STATIC_U_PLL_LOCKSEL    28
16816 #define V_STATIC_U_PLL_LOCKSEL(x) ((x) << S_STATIC_U_PLL_LOCKSEL)
16817 #define F_STATIC_U_PLL_LOCKSEL    V_STATIC_U_PLL_LOCKSEL(1U)
16818 
16819 #define S_STATIC_U_PLL_FFTUNE    12
16820 #define M_STATIC_U_PLL_FFTUNE    0xffffU
16821 #define V_STATIC_U_PLL_FFTUNE(x) ((x) << S_STATIC_U_PLL_FFTUNE)
16822 #define G_STATIC_U_PLL_FFTUNE(x) (((x) >> S_STATIC_U_PLL_FFTUNE) & M_STATIC_U_PLL_FFTUNE)
16823 
16824 #define S_STATIC_U_PLL_RANGEPRE    10
16825 #define M_STATIC_U_PLL_RANGEPRE    0x3U
16826 #define V_STATIC_U_PLL_RANGEPRE(x) ((x) << S_STATIC_U_PLL_RANGEPRE)
16827 #define G_STATIC_U_PLL_RANGEPRE(x) (((x) >> S_STATIC_U_PLL_RANGEPRE) & M_STATIC_U_PLL_RANGEPRE)
16828 
16829 #define S_T6_STATIC_U_PLL_RANGEB    5
16830 #define M_T6_STATIC_U_PLL_RANGEB    0x1fU
16831 #define V_T6_STATIC_U_PLL_RANGEB(x) ((x) << S_T6_STATIC_U_PLL_RANGEB)
16832 #define G_T6_STATIC_U_PLL_RANGEB(x) (((x) >> S_T6_STATIC_U_PLL_RANGEB) & M_T6_STATIC_U_PLL_RANGEB)
16833 
16834 #define S_T6_STATIC_U_PLL_RANGEA    0
16835 #define M_T6_STATIC_U_PLL_RANGEA    0x1fU
16836 #define V_T6_STATIC_U_PLL_RANGEA(x) ((x) << S_T6_STATIC_U_PLL_RANGEA)
16837 #define G_T6_STATIC_U_PLL_RANGEA(x) (((x) >> S_T6_STATIC_U_PLL_RANGEA) & M_T6_STATIC_U_PLL_RANGEA)
16838 
16839 #define A_DBG_STATIC_M1_PLL_CONF2 0x60ec
16840 
16841 #define S_STATIC_M1_PLL_SSMF    5
16842 #define M_STATIC_M1_PLL_SSMF    0xfU
16843 #define V_STATIC_M1_PLL_SSMF(x) ((x) << S_STATIC_M1_PLL_SSMF)
16844 #define G_STATIC_M1_PLL_SSMF(x) (((x) >> S_STATIC_M1_PLL_SSMF) & M_STATIC_M1_PLL_SSMF)
16845 
16846 #define S_STATIC_M1_PLL_SSMD    2
16847 #define M_STATIC_M1_PLL_SSMD    0x7U
16848 #define V_STATIC_M1_PLL_SSMD(x) ((x) << S_STATIC_M1_PLL_SSMD)
16849 #define G_STATIC_M1_PLL_SSMD(x) (((x) >> S_STATIC_M1_PLL_SSMD) & M_STATIC_M1_PLL_SSMD)
16850 
16851 #define S_STATIC_M1_PLL_SSDS    1
16852 #define V_STATIC_M1_PLL_SSDS(x) ((x) << S_STATIC_M1_PLL_SSDS)
16853 #define F_STATIC_M1_PLL_SSDS    V_STATIC_M1_PLL_SSDS(1U)
16854 
16855 #define S_STATIC_M1_PLL_SSE    0
16856 #define V_STATIC_M1_PLL_SSE(x) ((x) << S_STATIC_M1_PLL_SSE)
16857 #define F_STATIC_M1_PLL_SSE    V_STATIC_M1_PLL_SSE(1U)
16858 
16859 #define A_DBG_T5_STATIC_U_PLL_CONF4 0x60f0
16860 #define A_DBG_STATIC_U_PLL_CONF4 0x60f0
16861 #define A_DBG_T5_STATIC_U_PLL_CONF5 0x60f4
16862 
16863 #define S_T5_STATIC_U_PLL_VCVTUNE    22
16864 #define M_T5_STATIC_U_PLL_VCVTUNE    0x7U
16865 #define V_T5_STATIC_U_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_U_PLL_VCVTUNE)
16866 #define G_T5_STATIC_U_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_U_PLL_VCVTUNE) & M_T5_STATIC_U_PLL_VCVTUNE)
16867 
16868 #define S_T5_STATIC_U_PLL_LFTUNE_32_40    13
16869 #define M_T5_STATIC_U_PLL_LFTUNE_32_40    0x1ffU
16870 #define V_T5_STATIC_U_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_U_PLL_LFTUNE_32_40)
16871 #define G_T5_STATIC_U_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_U_PLL_LFTUNE_32_40) & M_T5_STATIC_U_PLL_LFTUNE_32_40)
16872 
16873 #define S_T5_STATIC_U_PLL_PREDIV    8
16874 #define M_T5_STATIC_U_PLL_PREDIV    0x1fU
16875 #define V_T5_STATIC_U_PLL_PREDIV(x) ((x) << S_T5_STATIC_U_PLL_PREDIV)
16876 #define G_T5_STATIC_U_PLL_PREDIV(x) (((x) >> S_T5_STATIC_U_PLL_PREDIV) & M_T5_STATIC_U_PLL_PREDIV)
16877 
16878 #define S_T5_STATIC_U_PLL_MULT    0
16879 #define M_T5_STATIC_U_PLL_MULT    0xffU
16880 #define V_T5_STATIC_U_PLL_MULT(x) ((x) << S_T5_STATIC_U_PLL_MULT)
16881 #define G_T5_STATIC_U_PLL_MULT(x) (((x) >> S_T5_STATIC_U_PLL_MULT) & M_T5_STATIC_U_PLL_MULT)
16882 
16883 #define A_DBG_STATIC_U_PLL_CONF5 0x60f4
16884 
16885 #define S_STATIC_U_PLL_FFBYPASS    27
16886 #define V_STATIC_U_PLL_FFBYPASS(x) ((x) << S_STATIC_U_PLL_FFBYPASS)
16887 #define F_STATIC_U_PLL_FFBYPASS    V_STATIC_U_PLL_FFBYPASS(1U)
16888 
16889 #define S_STATIC_U_PLL_FASTSTOP    26
16890 #define V_STATIC_U_PLL_FASTSTOP(x) ((x) << S_STATIC_U_PLL_FASTSTOP)
16891 #define F_STATIC_U_PLL_FASTSTOP    V_STATIC_U_PLL_FASTSTOP(1U)
16892 
16893 #define S_STATIC_U_PLL_FRAMESTOP    25
16894 #define V_STATIC_U_PLL_FRAMESTOP(x) ((x) << S_STATIC_U_PLL_FRAMESTOP)
16895 #define F_STATIC_U_PLL_FRAMESTOP    V_STATIC_U_PLL_FRAMESTOP(1U)
16896 
16897 #define S_STATIC_U_PLL_VCVTUNE    22
16898 #define M_STATIC_U_PLL_VCVTUNE    0x7U
16899 #define V_STATIC_U_PLL_VCVTUNE(x) ((x) << S_STATIC_U_PLL_VCVTUNE)
16900 #define G_STATIC_U_PLL_VCVTUNE(x) (((x) >> S_STATIC_U_PLL_VCVTUNE) & M_STATIC_U_PLL_VCVTUNE)
16901 
16902 #define S_STATIC_U_PLL_LFTUNE_32_40    13
16903 #define M_STATIC_U_PLL_LFTUNE_32_40    0x1ffU
16904 #define V_STATIC_U_PLL_LFTUNE_32_40(x) ((x) << S_STATIC_U_PLL_LFTUNE_32_40)
16905 #define G_STATIC_U_PLL_LFTUNE_32_40(x) (((x) >> S_STATIC_U_PLL_LFTUNE_32_40) & M_STATIC_U_PLL_LFTUNE_32_40)
16906 
16907 #define S_STATIC_U_PLL_PREDIV_CNF5    8
16908 #define M_STATIC_U_PLL_PREDIV_CNF5    0x1fU
16909 #define V_STATIC_U_PLL_PREDIV_CNF5(x) ((x) << S_STATIC_U_PLL_PREDIV_CNF5)
16910 #define G_STATIC_U_PLL_PREDIV_CNF5(x) (((x) >> S_STATIC_U_PLL_PREDIV_CNF5) & M_STATIC_U_PLL_PREDIV_CNF5)
16911 
16912 #define S_T6_STATIC_U_PLL_MULT    0
16913 #define M_T6_STATIC_U_PLL_MULT    0xffU
16914 #define V_T6_STATIC_U_PLL_MULT(x) ((x) << S_T6_STATIC_U_PLL_MULT)
16915 #define G_T6_STATIC_U_PLL_MULT(x) (((x) >> S_T6_STATIC_U_PLL_MULT) & M_T6_STATIC_U_PLL_MULT)
16916 
16917 #define A_DBG_T5_STATIC_KR_PLL_CONF1 0x60f8
16918 
16919 #define S_T5_STATIC_KR_PLL_BYPASS    30
16920 #define V_T5_STATIC_KR_PLL_BYPASS(x) ((x) << S_T5_STATIC_KR_PLL_BYPASS)
16921 #define F_T5_STATIC_KR_PLL_BYPASS    V_T5_STATIC_KR_PLL_BYPASS(1U)
16922 
16923 #define S_T5_STATIC_KR_PLL_VBOOSTDIV    27
16924 #define M_T5_STATIC_KR_PLL_VBOOSTDIV    0x7U
16925 #define V_T5_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KR_PLL_VBOOSTDIV)
16926 #define G_T5_STATIC_KR_PLL_VBOOSTDIV(x) (((x) >> S_T5_STATIC_KR_PLL_VBOOSTDIV) & M_T5_STATIC_KR_PLL_VBOOSTDIV)
16927 
16928 #define S_T5_STATIC_KR_PLL_CPISEL    24
16929 #define M_T5_STATIC_KR_PLL_CPISEL    0x7U
16930 #define V_T5_STATIC_KR_PLL_CPISEL(x) ((x) << S_T5_STATIC_KR_PLL_CPISEL)
16931 #define G_T5_STATIC_KR_PLL_CPISEL(x) (((x) >> S_T5_STATIC_KR_PLL_CPISEL) & M_T5_STATIC_KR_PLL_CPISEL)
16932 
16933 #define S_T5_STATIC_KR_PLL_CCALMETHOD    23
16934 #define V_T5_STATIC_KR_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KR_PLL_CCALMETHOD)
16935 #define F_T5_STATIC_KR_PLL_CCALMETHOD    V_T5_STATIC_KR_PLL_CCALMETHOD(1U)
16936 
16937 #define S_T5_STATIC_KR_PLL_CCALLOAD    22
16938 #define V_T5_STATIC_KR_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KR_PLL_CCALLOAD)
16939 #define F_T5_STATIC_KR_PLL_CCALLOAD    V_T5_STATIC_KR_PLL_CCALLOAD(1U)
16940 
16941 #define S_T5_STATIC_KR_PLL_CCALFMIN    21
16942 #define V_T5_STATIC_KR_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMIN)
16943 #define F_T5_STATIC_KR_PLL_CCALFMIN    V_T5_STATIC_KR_PLL_CCALFMIN(1U)
16944 
16945 #define S_T5_STATIC_KR_PLL_CCALFMAX    20
16946 #define V_T5_STATIC_KR_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMAX)
16947 #define F_T5_STATIC_KR_PLL_CCALFMAX    V_T5_STATIC_KR_PLL_CCALFMAX(1U)
16948 
16949 #define S_T5_STATIC_KR_PLL_CCALCVHOLD    19
16950 #define V_T5_STATIC_KR_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KR_PLL_CCALCVHOLD)
16951 #define F_T5_STATIC_KR_PLL_CCALCVHOLD    V_T5_STATIC_KR_PLL_CCALCVHOLD(1U)
16952 
16953 #define S_T5_STATIC_KR_PLL_CCALBANDSEL    15
16954 #define M_T5_STATIC_KR_PLL_CCALBANDSEL    0xfU
16955 #define V_T5_STATIC_KR_PLL_CCALBANDSEL(x) ((x) << S_T5_STATIC_KR_PLL_CCALBANDSEL)
16956 #define G_T5_STATIC_KR_PLL_CCALBANDSEL(x) (((x) >> S_T5_STATIC_KR_PLL_CCALBANDSEL) & M_T5_STATIC_KR_PLL_CCALBANDSEL)
16957 
16958 #define S_T5_STATIC_KR_PLL_BGOFFSET    11
16959 #define M_T5_STATIC_KR_PLL_BGOFFSET    0xfU
16960 #define V_T5_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KR_PLL_BGOFFSET)
16961 #define G_T5_STATIC_KR_PLL_BGOFFSET(x) (((x) >> S_T5_STATIC_KR_PLL_BGOFFSET) & M_T5_STATIC_KR_PLL_BGOFFSET)
16962 
16963 #define S_T5_STATIC_KR_PLL_P    8
16964 #define M_T5_STATIC_KR_PLL_P    0x7U
16965 #define V_T5_STATIC_KR_PLL_P(x) ((x) << S_T5_STATIC_KR_PLL_P)
16966 #define G_T5_STATIC_KR_PLL_P(x) (((x) >> S_T5_STATIC_KR_PLL_P) & M_T5_STATIC_KR_PLL_P)
16967 
16968 #define S_T5_STATIC_KR_PLL_N2    4
16969 #define M_T5_STATIC_KR_PLL_N2    0xfU
16970 #define V_T5_STATIC_KR_PLL_N2(x) ((x) << S_T5_STATIC_KR_PLL_N2)
16971 #define G_T5_STATIC_KR_PLL_N2(x) (((x) >> S_T5_STATIC_KR_PLL_N2) & M_T5_STATIC_KR_PLL_N2)
16972 
16973 #define S_T5_STATIC_KR_PLL_N1    0
16974 #define M_T5_STATIC_KR_PLL_N1    0xfU
16975 #define V_T5_STATIC_KR_PLL_N1(x) ((x) << S_T5_STATIC_KR_PLL_N1)
16976 #define G_T5_STATIC_KR_PLL_N1(x) (((x) >> S_T5_STATIC_KR_PLL_N1) & M_T5_STATIC_KR_PLL_N1)
16977 
16978 #define A_DBG_STATIC_KR_PLL_CONF1 0x60f8
16979 
16980 #define S_T6_STATIC_KR_PLL_BYPASS    30
16981 #define V_T6_STATIC_KR_PLL_BYPASS(x) ((x) << S_T6_STATIC_KR_PLL_BYPASS)
16982 #define F_T6_STATIC_KR_PLL_BYPASS    V_T6_STATIC_KR_PLL_BYPASS(1U)
16983 
16984 #define S_STATIC_KR_PLL_VBOOSTDIV    27
16985 #define M_STATIC_KR_PLL_VBOOSTDIV    0x7U
16986 #define V_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KR_PLL_VBOOSTDIV)
16987 #define G_STATIC_KR_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KR_PLL_VBOOSTDIV) & M_STATIC_KR_PLL_VBOOSTDIV)
16988 
16989 #define S_STATIC_KR_PLL_CPISEL    24
16990 #define M_STATIC_KR_PLL_CPISEL    0x7U
16991 #define V_STATIC_KR_PLL_CPISEL(x) ((x) << S_STATIC_KR_PLL_CPISEL)
16992 #define G_STATIC_KR_PLL_CPISEL(x) (((x) >> S_STATIC_KR_PLL_CPISEL) & M_STATIC_KR_PLL_CPISEL)
16993 
16994 #define S_STATIC_KR_PLL_CCALMETHOD    23
16995 #define V_STATIC_KR_PLL_CCALMETHOD(x) ((x) << S_STATIC_KR_PLL_CCALMETHOD)
16996 #define F_STATIC_KR_PLL_CCALMETHOD    V_STATIC_KR_PLL_CCALMETHOD(1U)
16997 
16998 #define S_STATIC_KR_PLL_CCALLOAD    22
16999 #define V_STATIC_KR_PLL_CCALLOAD(x) ((x) << S_STATIC_KR_PLL_CCALLOAD)
17000 #define F_STATIC_KR_PLL_CCALLOAD    V_STATIC_KR_PLL_CCALLOAD(1U)
17001 
17002 #define S_STATIC_KR_PLL_CCALFMIN    21
17003 #define V_STATIC_KR_PLL_CCALFMIN(x) ((x) << S_STATIC_KR_PLL_CCALFMIN)
17004 #define F_STATIC_KR_PLL_CCALFMIN    V_STATIC_KR_PLL_CCALFMIN(1U)
17005 
17006 #define S_STATIC_KR_PLL_CCALFMAX    20
17007 #define V_STATIC_KR_PLL_CCALFMAX(x) ((x) << S_STATIC_KR_PLL_CCALFMAX)
17008 #define F_STATIC_KR_PLL_CCALFMAX    V_STATIC_KR_PLL_CCALFMAX(1U)
17009 
17010 #define S_STATIC_KR_PLL_CCALCVHOLD    19
17011 #define V_STATIC_KR_PLL_CCALCVHOLD(x) ((x) << S_STATIC_KR_PLL_CCALCVHOLD)
17012 #define F_STATIC_KR_PLL_CCALCVHOLD    V_STATIC_KR_PLL_CCALCVHOLD(1U)
17013 
17014 #define S_STATIC_KR_PLL_CCALBANDSEL    15
17015 #define M_STATIC_KR_PLL_CCALBANDSEL    0xfU
17016 #define V_STATIC_KR_PLL_CCALBANDSEL(x) ((x) << S_STATIC_KR_PLL_CCALBANDSEL)
17017 #define G_STATIC_KR_PLL_CCALBANDSEL(x) (((x) >> S_STATIC_KR_PLL_CCALBANDSEL) & M_STATIC_KR_PLL_CCALBANDSEL)
17018 
17019 #define S_STATIC_KR_PLL_BGOFFSET    11
17020 #define M_STATIC_KR_PLL_BGOFFSET    0xfU
17021 #define V_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_STATIC_KR_PLL_BGOFFSET)
17022 #define G_STATIC_KR_PLL_BGOFFSET(x) (((x) >> S_STATIC_KR_PLL_BGOFFSET) & M_STATIC_KR_PLL_BGOFFSET)
17023 
17024 #define S_T6_STATIC_KR_PLL_P    8
17025 #define M_T6_STATIC_KR_PLL_P    0x7U
17026 #define V_T6_STATIC_KR_PLL_P(x) ((x) << S_T6_STATIC_KR_PLL_P)
17027 #define G_T6_STATIC_KR_PLL_P(x) (((x) >> S_T6_STATIC_KR_PLL_P) & M_T6_STATIC_KR_PLL_P)
17028 
17029 #define S_T6_STATIC_KR_PLL_N2    4
17030 #define M_T6_STATIC_KR_PLL_N2    0xfU
17031 #define V_T6_STATIC_KR_PLL_N2(x) ((x) << S_T6_STATIC_KR_PLL_N2)
17032 #define G_T6_STATIC_KR_PLL_N2(x) (((x) >> S_T6_STATIC_KR_PLL_N2) & M_T6_STATIC_KR_PLL_N2)
17033 
17034 #define S_T6_STATIC_KR_PLL_N1    0
17035 #define M_T6_STATIC_KR_PLL_N1    0xfU
17036 #define V_T6_STATIC_KR_PLL_N1(x) ((x) << S_T6_STATIC_KR_PLL_N1)
17037 #define G_T6_STATIC_KR_PLL_N1(x) (((x) >> S_T6_STATIC_KR_PLL_N1) & M_T6_STATIC_KR_PLL_N1)
17038 
17039 #define A_DBG_T5_STATIC_KR_PLL_CONF2 0x60fc
17040 
17041 #define S_T5_STATIC_KR_PLL_M    11
17042 #define M_T5_STATIC_KR_PLL_M    0x1ffU
17043 #define V_T5_STATIC_KR_PLL_M(x) ((x) << S_T5_STATIC_KR_PLL_M)
17044 #define G_T5_STATIC_KR_PLL_M(x) (((x) >> S_T5_STATIC_KR_PLL_M) & M_T5_STATIC_KR_PLL_M)
17045 
17046 #define S_T5_STATIC_KR_PLL_ANALOGTUNE    0
17047 #define M_T5_STATIC_KR_PLL_ANALOGTUNE    0x7ffU
17048 #define V_T5_STATIC_KR_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KR_PLL_ANALOGTUNE)
17049 #define G_T5_STATIC_KR_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KR_PLL_ANALOGTUNE) & M_T5_STATIC_KR_PLL_ANALOGTUNE)
17050 
17051 #define A_DBG_STATIC_KR_PLL_CONF2 0x60fc
17052 
17053 #define S_T6_STATIC_KR_PLL_M    11
17054 #define M_T6_STATIC_KR_PLL_M    0x1ffU
17055 #define V_T6_STATIC_KR_PLL_M(x) ((x) << S_T6_STATIC_KR_PLL_M)
17056 #define G_T6_STATIC_KR_PLL_M(x) (((x) >> S_T6_STATIC_KR_PLL_M) & M_T6_STATIC_KR_PLL_M)
17057 
17058 #define S_STATIC_KR_PLL_ANALOGTUNE    0
17059 #define M_STATIC_KR_PLL_ANALOGTUNE    0x7ffU
17060 #define V_STATIC_KR_PLL_ANALOGTUNE(x) ((x) << S_STATIC_KR_PLL_ANALOGTUNE)
17061 #define G_STATIC_KR_PLL_ANALOGTUNE(x) (((x) >> S_STATIC_KR_PLL_ANALOGTUNE) & M_STATIC_KR_PLL_ANALOGTUNE)
17062 
17063 #define A_DBG_PVT_REG_CALIBRATE_CTL 0x6100
17064 
17065 #define S_HALT_CALIBRATE    1
17066 #define V_HALT_CALIBRATE(x) ((x) << S_HALT_CALIBRATE)
17067 #define F_HALT_CALIBRATE    V_HALT_CALIBRATE(1U)
17068 
17069 #define S_RESET_CALIBRATE    0
17070 #define V_RESET_CALIBRATE(x) ((x) << S_RESET_CALIBRATE)
17071 #define F_RESET_CALIBRATE    V_RESET_CALIBRATE(1U)
17072 
17073 #define A_DBG_GPIO_EN_NEW 0x6100
17074 
17075 #define S_GPIO16_OEN    7
17076 #define V_GPIO16_OEN(x) ((x) << S_GPIO16_OEN)
17077 #define F_GPIO16_OEN    V_GPIO16_OEN(1U)
17078 
17079 #define S_GPIO17_OEN    6
17080 #define V_GPIO17_OEN(x) ((x) << S_GPIO17_OEN)
17081 #define F_GPIO17_OEN    V_GPIO17_OEN(1U)
17082 
17083 #define S_GPIO18_OEN    5
17084 #define V_GPIO18_OEN(x) ((x) << S_GPIO18_OEN)
17085 #define F_GPIO18_OEN    V_GPIO18_OEN(1U)
17086 
17087 #define S_GPIO19_OEN    4
17088 #define V_GPIO19_OEN(x) ((x) << S_GPIO19_OEN)
17089 #define F_GPIO19_OEN    V_GPIO19_OEN(1U)
17090 
17091 #define S_GPIO16_OUT_VAL    3
17092 #define V_GPIO16_OUT_VAL(x) ((x) << S_GPIO16_OUT_VAL)
17093 #define F_GPIO16_OUT_VAL    V_GPIO16_OUT_VAL(1U)
17094 
17095 #define S_GPIO17_OUT_VAL    2
17096 #define V_GPIO17_OUT_VAL(x) ((x) << S_GPIO17_OUT_VAL)
17097 #define F_GPIO17_OUT_VAL    V_GPIO17_OUT_VAL(1U)
17098 
17099 #define S_GPIO18_OUT_VAL    1
17100 #define V_GPIO18_OUT_VAL(x) ((x) << S_GPIO18_OUT_VAL)
17101 #define F_GPIO18_OUT_VAL    V_GPIO18_OUT_VAL(1U)
17102 
17103 #define S_GPIO19_OUT_VAL    0
17104 #define V_GPIO19_OUT_VAL(x) ((x) << S_GPIO19_OUT_VAL)
17105 #define F_GPIO19_OUT_VAL    V_GPIO19_OUT_VAL(1U)
17106 
17107 #define A_DBG_GPIO_OEN 0x6100
17108 
17109 #define S_GPIO23_OEN    23
17110 #define V_GPIO23_OEN(x) ((x) << S_GPIO23_OEN)
17111 #define F_GPIO23_OEN    V_GPIO23_OEN(1U)
17112 
17113 #define S_GPIO22_OEN    22
17114 #define V_GPIO22_OEN(x) ((x) << S_GPIO22_OEN)
17115 #define F_GPIO22_OEN    V_GPIO22_OEN(1U)
17116 
17117 #define S_GPIO21_OEN    21
17118 #define V_GPIO21_OEN(x) ((x) << S_GPIO21_OEN)
17119 #define F_GPIO21_OEN    V_GPIO21_OEN(1U)
17120 
17121 #define S_GPIO20_OEN    20
17122 #define V_GPIO20_OEN(x) ((x) << S_GPIO20_OEN)
17123 #define F_GPIO20_OEN    V_GPIO20_OEN(1U)
17124 
17125 #define S_T7_GPIO19_OEN    19
17126 #define V_T7_GPIO19_OEN(x) ((x) << S_T7_GPIO19_OEN)
17127 #define F_T7_GPIO19_OEN    V_T7_GPIO19_OEN(1U)
17128 
17129 #define S_T7_GPIO18_OEN    18
17130 #define V_T7_GPIO18_OEN(x) ((x) << S_T7_GPIO18_OEN)
17131 #define F_T7_GPIO18_OEN    V_T7_GPIO18_OEN(1U)
17132 
17133 #define S_T7_GPIO17_OEN    17
17134 #define V_T7_GPIO17_OEN(x) ((x) << S_T7_GPIO17_OEN)
17135 #define F_T7_GPIO17_OEN    V_T7_GPIO17_OEN(1U)
17136 
17137 #define S_T7_GPIO16_OEN    16
17138 #define V_T7_GPIO16_OEN(x) ((x) << S_T7_GPIO16_OEN)
17139 #define F_T7_GPIO16_OEN    V_T7_GPIO16_OEN(1U)
17140 
17141 #define S_T7_GPIO15_OEN    15
17142 #define V_T7_GPIO15_OEN(x) ((x) << S_T7_GPIO15_OEN)
17143 #define F_T7_GPIO15_OEN    V_T7_GPIO15_OEN(1U)
17144 
17145 #define S_T7_GPIO14_OEN    14
17146 #define V_T7_GPIO14_OEN(x) ((x) << S_T7_GPIO14_OEN)
17147 #define F_T7_GPIO14_OEN    V_T7_GPIO14_OEN(1U)
17148 
17149 #define S_T7_GPIO13_OEN    13
17150 #define V_T7_GPIO13_OEN(x) ((x) << S_T7_GPIO13_OEN)
17151 #define F_T7_GPIO13_OEN    V_T7_GPIO13_OEN(1U)
17152 
17153 #define S_T7_GPIO12_OEN    12
17154 #define V_T7_GPIO12_OEN(x) ((x) << S_T7_GPIO12_OEN)
17155 #define F_T7_GPIO12_OEN    V_T7_GPIO12_OEN(1U)
17156 
17157 #define S_T7_GPIO11_OEN    11
17158 #define V_T7_GPIO11_OEN(x) ((x) << S_T7_GPIO11_OEN)
17159 #define F_T7_GPIO11_OEN    V_T7_GPIO11_OEN(1U)
17160 
17161 #define S_T7_GPIO10_OEN    10
17162 #define V_T7_GPIO10_OEN(x) ((x) << S_T7_GPIO10_OEN)
17163 #define F_T7_GPIO10_OEN    V_T7_GPIO10_OEN(1U)
17164 
17165 #define S_T7_GPIO9_OEN    9
17166 #define V_T7_GPIO9_OEN(x) ((x) << S_T7_GPIO9_OEN)
17167 #define F_T7_GPIO9_OEN    V_T7_GPIO9_OEN(1U)
17168 
17169 #define S_T7_GPIO8_OEN    8
17170 #define V_T7_GPIO8_OEN(x) ((x) << S_T7_GPIO8_OEN)
17171 #define F_T7_GPIO8_OEN    V_T7_GPIO8_OEN(1U)
17172 
17173 #define S_T7_GPIO7_OEN    7
17174 #define V_T7_GPIO7_OEN(x) ((x) << S_T7_GPIO7_OEN)
17175 #define F_T7_GPIO7_OEN    V_T7_GPIO7_OEN(1U)
17176 
17177 #define S_T7_GPIO6_OEN    6
17178 #define V_T7_GPIO6_OEN(x) ((x) << S_T7_GPIO6_OEN)
17179 #define F_T7_GPIO6_OEN    V_T7_GPIO6_OEN(1U)
17180 
17181 #define S_T7_GPIO5_OEN    5
17182 #define V_T7_GPIO5_OEN(x) ((x) << S_T7_GPIO5_OEN)
17183 #define F_T7_GPIO5_OEN    V_T7_GPIO5_OEN(1U)
17184 
17185 #define S_T7_GPIO4_OEN    4
17186 #define V_T7_GPIO4_OEN(x) ((x) << S_T7_GPIO4_OEN)
17187 #define F_T7_GPIO4_OEN    V_T7_GPIO4_OEN(1U)
17188 
17189 #define S_T7_GPIO3_OEN    3
17190 #define V_T7_GPIO3_OEN(x) ((x) << S_T7_GPIO3_OEN)
17191 #define F_T7_GPIO3_OEN    V_T7_GPIO3_OEN(1U)
17192 
17193 #define S_T7_GPIO2_OEN    2
17194 #define V_T7_GPIO2_OEN(x) ((x) << S_T7_GPIO2_OEN)
17195 #define F_T7_GPIO2_OEN    V_T7_GPIO2_OEN(1U)
17196 
17197 #define S_T7_GPIO1_OEN    1
17198 #define V_T7_GPIO1_OEN(x) ((x) << S_T7_GPIO1_OEN)
17199 #define F_T7_GPIO1_OEN    V_T7_GPIO1_OEN(1U)
17200 
17201 #define S_T7_GPIO0_OEN    0
17202 #define V_T7_GPIO0_OEN(x) ((x) << S_T7_GPIO0_OEN)
17203 #define F_T7_GPIO0_OEN    V_T7_GPIO0_OEN(1U)
17204 
17205 #define A_DBG_PVT_REG_UPDATE_CTL 0x6104
17206 
17207 #define S_FAST_UPDATE    8
17208 #define V_FAST_UPDATE(x) ((x) << S_FAST_UPDATE)
17209 #define F_FAST_UPDATE    V_FAST_UPDATE(1U)
17210 
17211 #define S_FORCE_REG_IN_VALUE    2
17212 #define V_FORCE_REG_IN_VALUE(x) ((x) << S_FORCE_REG_IN_VALUE)
17213 #define F_FORCE_REG_IN_VALUE    V_FORCE_REG_IN_VALUE(1U)
17214 
17215 #define S_HALT_UPDATE    1
17216 #define V_HALT_UPDATE(x) ((x) << S_HALT_UPDATE)
17217 #define F_HALT_UPDATE    V_HALT_UPDATE(1U)
17218 
17219 #define A_DBG_GPIO_IN_NEW 0x6104
17220 
17221 #define S_GPIO16_CHG_DET    7
17222 #define V_GPIO16_CHG_DET(x) ((x) << S_GPIO16_CHG_DET)
17223 #define F_GPIO16_CHG_DET    V_GPIO16_CHG_DET(1U)
17224 
17225 #define S_GPIO17_CHG_DET    6
17226 #define V_GPIO17_CHG_DET(x) ((x) << S_GPIO17_CHG_DET)
17227 #define F_GPIO17_CHG_DET    V_GPIO17_CHG_DET(1U)
17228 
17229 #define S_GPIO18_CHG_DET    5
17230 #define V_GPIO18_CHG_DET(x) ((x) << S_GPIO18_CHG_DET)
17231 #define F_GPIO18_CHG_DET    V_GPIO18_CHG_DET(1U)
17232 
17233 #define S_GPIO19_CHG_DET    4
17234 #define V_GPIO19_CHG_DET(x) ((x) << S_GPIO19_CHG_DET)
17235 #define F_GPIO19_CHG_DET    V_GPIO19_CHG_DET(1U)
17236 
17237 #define S_GPIO19_IN    3
17238 #define V_GPIO19_IN(x) ((x) << S_GPIO19_IN)
17239 #define F_GPIO19_IN    V_GPIO19_IN(1U)
17240 
17241 #define S_GPIO18_IN    2
17242 #define V_GPIO18_IN(x) ((x) << S_GPIO18_IN)
17243 #define F_GPIO18_IN    V_GPIO18_IN(1U)
17244 
17245 #define S_GPIO17_IN    1
17246 #define V_GPIO17_IN(x) ((x) << S_GPIO17_IN)
17247 #define F_GPIO17_IN    V_GPIO17_IN(1U)
17248 
17249 #define S_GPIO16_IN    0
17250 #define V_GPIO16_IN(x) ((x) << S_GPIO16_IN)
17251 #define F_GPIO16_IN    V_GPIO16_IN(1U)
17252 
17253 #define A_DBG_GPIO_CHG_DET 0x6104
17254 
17255 #define S_GPIO23_CHG_DET    23
17256 #define V_GPIO23_CHG_DET(x) ((x) << S_GPIO23_CHG_DET)
17257 #define F_GPIO23_CHG_DET    V_GPIO23_CHG_DET(1U)
17258 
17259 #define S_GPIO22_CHG_DET    22
17260 #define V_GPIO22_CHG_DET(x) ((x) << S_GPIO22_CHG_DET)
17261 #define F_GPIO22_CHG_DET    V_GPIO22_CHG_DET(1U)
17262 
17263 #define S_GPIO21_CHG_DET    21
17264 #define V_GPIO21_CHG_DET(x) ((x) << S_GPIO21_CHG_DET)
17265 #define F_GPIO21_CHG_DET    V_GPIO21_CHG_DET(1U)
17266 
17267 #define S_GPIO20_CHG_DET    20
17268 #define V_GPIO20_CHG_DET(x) ((x) << S_GPIO20_CHG_DET)
17269 #define F_GPIO20_CHG_DET    V_GPIO20_CHG_DET(1U)
17270 
17271 #define S_T7_GPIO19_CHG_DET    19
17272 #define V_T7_GPIO19_CHG_DET(x) ((x) << S_T7_GPIO19_CHG_DET)
17273 #define F_T7_GPIO19_CHG_DET    V_T7_GPIO19_CHG_DET(1U)
17274 
17275 #define S_T7_GPIO18_CHG_DET    18
17276 #define V_T7_GPIO18_CHG_DET(x) ((x) << S_T7_GPIO18_CHG_DET)
17277 #define F_T7_GPIO18_CHG_DET    V_T7_GPIO18_CHG_DET(1U)
17278 
17279 #define S_T7_GPIO17_CHG_DET    17
17280 #define V_T7_GPIO17_CHG_DET(x) ((x) << S_T7_GPIO17_CHG_DET)
17281 #define F_T7_GPIO17_CHG_DET    V_T7_GPIO17_CHG_DET(1U)
17282 
17283 #define S_T7_GPIO16_CHG_DET    16
17284 #define V_T7_GPIO16_CHG_DET(x) ((x) << S_T7_GPIO16_CHG_DET)
17285 #define F_T7_GPIO16_CHG_DET    V_T7_GPIO16_CHG_DET(1U)
17286 
17287 #define S_T7_GPIO15_CHG_DET    15
17288 #define V_T7_GPIO15_CHG_DET(x) ((x) << S_T7_GPIO15_CHG_DET)
17289 #define F_T7_GPIO15_CHG_DET    V_T7_GPIO15_CHG_DET(1U)
17290 
17291 #define S_T7_GPIO14_CHG_DET    14
17292 #define V_T7_GPIO14_CHG_DET(x) ((x) << S_T7_GPIO14_CHG_DET)
17293 #define F_T7_GPIO14_CHG_DET    V_T7_GPIO14_CHG_DET(1U)
17294 
17295 #define S_T7_GPIO13_CHG_DET    13
17296 #define V_T7_GPIO13_CHG_DET(x) ((x) << S_T7_GPIO13_CHG_DET)
17297 #define F_T7_GPIO13_CHG_DET    V_T7_GPIO13_CHG_DET(1U)
17298 
17299 #define S_T7_GPIO12_CHG_DET    12
17300 #define V_T7_GPIO12_CHG_DET(x) ((x) << S_T7_GPIO12_CHG_DET)
17301 #define F_T7_GPIO12_CHG_DET    V_T7_GPIO12_CHG_DET(1U)
17302 
17303 #define S_T7_GPIO11_CHG_DET    11
17304 #define V_T7_GPIO11_CHG_DET(x) ((x) << S_T7_GPIO11_CHG_DET)
17305 #define F_T7_GPIO11_CHG_DET    V_T7_GPIO11_CHG_DET(1U)
17306 
17307 #define S_T7_GPIO10_CHG_DET    10
17308 #define V_T7_GPIO10_CHG_DET(x) ((x) << S_T7_GPIO10_CHG_DET)
17309 #define F_T7_GPIO10_CHG_DET    V_T7_GPIO10_CHG_DET(1U)
17310 
17311 #define S_T7_GPIO9_CHG_DET    9
17312 #define V_T7_GPIO9_CHG_DET(x) ((x) << S_T7_GPIO9_CHG_DET)
17313 #define F_T7_GPIO9_CHG_DET    V_T7_GPIO9_CHG_DET(1U)
17314 
17315 #define S_T7_GPIO8_CHG_DET    8
17316 #define V_T7_GPIO8_CHG_DET(x) ((x) << S_T7_GPIO8_CHG_DET)
17317 #define F_T7_GPIO8_CHG_DET    V_T7_GPIO8_CHG_DET(1U)
17318 
17319 #define S_T7_GPIO7_CHG_DET    7
17320 #define V_T7_GPIO7_CHG_DET(x) ((x) << S_T7_GPIO7_CHG_DET)
17321 #define F_T7_GPIO7_CHG_DET    V_T7_GPIO7_CHG_DET(1U)
17322 
17323 #define S_T7_GPIO6_CHG_DET    6
17324 #define V_T7_GPIO6_CHG_DET(x) ((x) << S_T7_GPIO6_CHG_DET)
17325 #define F_T7_GPIO6_CHG_DET    V_T7_GPIO6_CHG_DET(1U)
17326 
17327 #define S_T7_GPIO5_CHG_DET    5
17328 #define V_T7_GPIO5_CHG_DET(x) ((x) << S_T7_GPIO5_CHG_DET)
17329 #define F_T7_GPIO5_CHG_DET    V_T7_GPIO5_CHG_DET(1U)
17330 
17331 #define S_T7_GPIO4_CHG_DET    4
17332 #define V_T7_GPIO4_CHG_DET(x) ((x) << S_T7_GPIO4_CHG_DET)
17333 #define F_T7_GPIO4_CHG_DET    V_T7_GPIO4_CHG_DET(1U)
17334 
17335 #define S_T7_GPIO3_CHG_DET    3
17336 #define V_T7_GPIO3_CHG_DET(x) ((x) << S_T7_GPIO3_CHG_DET)
17337 #define F_T7_GPIO3_CHG_DET    V_T7_GPIO3_CHG_DET(1U)
17338 
17339 #define S_T7_GPIO2_CHG_DET    2
17340 #define V_T7_GPIO2_CHG_DET(x) ((x) << S_T7_GPIO2_CHG_DET)
17341 #define F_T7_GPIO2_CHG_DET    V_T7_GPIO2_CHG_DET(1U)
17342 
17343 #define S_T7_GPIO1_CHG_DET    1
17344 #define V_T7_GPIO1_CHG_DET(x) ((x) << S_T7_GPIO1_CHG_DET)
17345 #define F_T7_GPIO1_CHG_DET    V_T7_GPIO1_CHG_DET(1U)
17346 
17347 #define S_T7_GPIO0_CHG_DET    0
17348 #define V_T7_GPIO0_CHG_DET(x) ((x) << S_T7_GPIO0_CHG_DET)
17349 #define F_T7_GPIO0_CHG_DET    V_T7_GPIO0_CHG_DET(1U)
17350 
17351 #define A_DBG_PVT_REG_LAST_MEASUREMENT 0x6108
17352 
17353 #define S_LAST_MEASUREMENT_SELECT    8
17354 #define M_LAST_MEASUREMENT_SELECT    0x3U
17355 #define V_LAST_MEASUREMENT_SELECT(x) ((x) << S_LAST_MEASUREMENT_SELECT)
17356 #define G_LAST_MEASUREMENT_SELECT(x) (((x) >> S_LAST_MEASUREMENT_SELECT) & M_LAST_MEASUREMENT_SELECT)
17357 
17358 #define S_LAST_MEASUREMENT_RESULT_BANK_B    4
17359 #define M_LAST_MEASUREMENT_RESULT_BANK_B    0xfU
17360 #define V_LAST_MEASUREMENT_RESULT_BANK_B(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_B)
17361 #define G_LAST_MEASUREMENT_RESULT_BANK_B(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_B) & M_LAST_MEASUREMENT_RESULT_BANK_B)
17362 
17363 #define S_LAST_MEASUREMENT_RESULT_BANK_A    0
17364 #define M_LAST_MEASUREMENT_RESULT_BANK_A    0xfU
17365 #define V_LAST_MEASUREMENT_RESULT_BANK_A(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_A)
17366 #define G_LAST_MEASUREMENT_RESULT_BANK_A(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_A) & M_LAST_MEASUREMENT_RESULT_BANK_A)
17367 
17368 #define A_DBG_T5_STATIC_KX_PLL_CONF1 0x6108
17369 
17370 #define S_T5_STATIC_KX_PLL_BYPASS    30
17371 #define V_T5_STATIC_KX_PLL_BYPASS(x) ((x) << S_T5_STATIC_KX_PLL_BYPASS)
17372 #define F_T5_STATIC_KX_PLL_BYPASS    V_T5_STATIC_KX_PLL_BYPASS(1U)
17373 
17374 #define S_T5_STATIC_KX_PLL_VBOOSTDIV    27
17375 #define M_T5_STATIC_KX_PLL_VBOOSTDIV    0x7U
17376 #define V_T5_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KX_PLL_VBOOSTDIV)
17377 #define G_T5_STATIC_KX_PLL_VBOOSTDIV(x) (((x) >> S_T5_STATIC_KX_PLL_VBOOSTDIV) & M_T5_STATIC_KX_PLL_VBOOSTDIV)
17378 
17379 #define S_T5_STATIC_KX_PLL_CPISEL    24
17380 #define M_T5_STATIC_KX_PLL_CPISEL    0x7U
17381 #define V_T5_STATIC_KX_PLL_CPISEL(x) ((x) << S_T5_STATIC_KX_PLL_CPISEL)
17382 #define G_T5_STATIC_KX_PLL_CPISEL(x) (((x) >> S_T5_STATIC_KX_PLL_CPISEL) & M_T5_STATIC_KX_PLL_CPISEL)
17383 
17384 #define S_T5_STATIC_KX_PLL_CCALMETHOD    23
17385 #define V_T5_STATIC_KX_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KX_PLL_CCALMETHOD)
17386 #define F_T5_STATIC_KX_PLL_CCALMETHOD    V_T5_STATIC_KX_PLL_CCALMETHOD(1U)
17387 
17388 #define S_T5_STATIC_KX_PLL_CCALLOAD    22
17389 #define V_T5_STATIC_KX_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KX_PLL_CCALLOAD)
17390 #define F_T5_STATIC_KX_PLL_CCALLOAD    V_T5_STATIC_KX_PLL_CCALLOAD(1U)
17391 
17392 #define S_T5_STATIC_KX_PLL_CCALFMIN    21
17393 #define V_T5_STATIC_KX_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMIN)
17394 #define F_T5_STATIC_KX_PLL_CCALFMIN    V_T5_STATIC_KX_PLL_CCALFMIN(1U)
17395 
17396 #define S_T5_STATIC_KX_PLL_CCALFMAX    20
17397 #define V_T5_STATIC_KX_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMAX)
17398 #define F_T5_STATIC_KX_PLL_CCALFMAX    V_T5_STATIC_KX_PLL_CCALFMAX(1U)
17399 
17400 #define S_T5_STATIC_KX_PLL_CCALCVHOLD    19
17401 #define V_T5_STATIC_KX_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KX_PLL_CCALCVHOLD)
17402 #define F_T5_STATIC_KX_PLL_CCALCVHOLD    V_T5_STATIC_KX_PLL_CCALCVHOLD(1U)
17403 
17404 #define S_T5_STATIC_KX_PLL_CCALBANDSEL    15
17405 #define M_T5_STATIC_KX_PLL_CCALBANDSEL    0xfU
17406 #define V_T5_STATIC_KX_PLL_CCALBANDSEL(x) ((x) << S_T5_STATIC_KX_PLL_CCALBANDSEL)
17407 #define G_T5_STATIC_KX_PLL_CCALBANDSEL(x) (((x) >> S_T5_STATIC_KX_PLL_CCALBANDSEL) & M_T5_STATIC_KX_PLL_CCALBANDSEL)
17408 
17409 #define S_T5_STATIC_KX_PLL_BGOFFSET    11
17410 #define M_T5_STATIC_KX_PLL_BGOFFSET    0xfU
17411 #define V_T5_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KX_PLL_BGOFFSET)
17412 #define G_T5_STATIC_KX_PLL_BGOFFSET(x) (((x) >> S_T5_STATIC_KX_PLL_BGOFFSET) & M_T5_STATIC_KX_PLL_BGOFFSET)
17413 
17414 #define S_T5_STATIC_KX_PLL_P    8
17415 #define M_T5_STATIC_KX_PLL_P    0x7U
17416 #define V_T5_STATIC_KX_PLL_P(x) ((x) << S_T5_STATIC_KX_PLL_P)
17417 #define G_T5_STATIC_KX_PLL_P(x) (((x) >> S_T5_STATIC_KX_PLL_P) & M_T5_STATIC_KX_PLL_P)
17418 
17419 #define S_T5_STATIC_KX_PLL_N2    4
17420 #define M_T5_STATIC_KX_PLL_N2    0xfU
17421 #define V_T5_STATIC_KX_PLL_N2(x) ((x) << S_T5_STATIC_KX_PLL_N2)
17422 #define G_T5_STATIC_KX_PLL_N2(x) (((x) >> S_T5_STATIC_KX_PLL_N2) & M_T5_STATIC_KX_PLL_N2)
17423 
17424 #define S_T5_STATIC_KX_PLL_N1    0
17425 #define M_T5_STATIC_KX_PLL_N1    0xfU
17426 #define V_T5_STATIC_KX_PLL_N1(x) ((x) << S_T5_STATIC_KX_PLL_N1)
17427 #define G_T5_STATIC_KX_PLL_N1(x) (((x) >> S_T5_STATIC_KX_PLL_N1) & M_T5_STATIC_KX_PLL_N1)
17428 
17429 #define A_DBG_STATIC_KX_PLL_CONF1 0x6108
17430 
17431 #define S_T6_STATIC_KX_PLL_BYPASS    30
17432 #define V_T6_STATIC_KX_PLL_BYPASS(x) ((x) << S_T6_STATIC_KX_PLL_BYPASS)
17433 #define F_T6_STATIC_KX_PLL_BYPASS    V_T6_STATIC_KX_PLL_BYPASS(1U)
17434 
17435 #define S_STATIC_KX_PLL_VBOOSTDIV    27
17436 #define M_STATIC_KX_PLL_VBOOSTDIV    0x7U
17437 #define V_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KX_PLL_VBOOSTDIV)
17438 #define G_STATIC_KX_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KX_PLL_VBOOSTDIV) & M_STATIC_KX_PLL_VBOOSTDIV)
17439 
17440 #define S_STATIC_KX_PLL_CPISEL    24
17441 #define M_STATIC_KX_PLL_CPISEL    0x7U
17442 #define V_STATIC_KX_PLL_CPISEL(x) ((x) << S_STATIC_KX_PLL_CPISEL)
17443 #define G_STATIC_KX_PLL_CPISEL(x) (((x) >> S_STATIC_KX_PLL_CPISEL) & M_STATIC_KX_PLL_CPISEL)
17444 
17445 #define S_STATIC_KX_PLL_CCALMETHOD    23
17446 #define V_STATIC_KX_PLL_CCALMETHOD(x) ((x) << S_STATIC_KX_PLL_CCALMETHOD)
17447 #define F_STATIC_KX_PLL_CCALMETHOD    V_STATIC_KX_PLL_CCALMETHOD(1U)
17448 
17449 #define S_STATIC_KX_PLL_CCALLOAD    22
17450 #define V_STATIC_KX_PLL_CCALLOAD(x) ((x) << S_STATIC_KX_PLL_CCALLOAD)
17451 #define F_STATIC_KX_PLL_CCALLOAD    V_STATIC_KX_PLL_CCALLOAD(1U)
17452 
17453 #define S_STATIC_KX_PLL_CCALFMIN    21
17454 #define V_STATIC_KX_PLL_CCALFMIN(x) ((x) << S_STATIC_KX_PLL_CCALFMIN)
17455 #define F_STATIC_KX_PLL_CCALFMIN    V_STATIC_KX_PLL_CCALFMIN(1U)
17456 
17457 #define S_STATIC_KX_PLL_CCALFMAX    20
17458 #define V_STATIC_KX_PLL_CCALFMAX(x) ((x) << S_STATIC_KX_PLL_CCALFMAX)
17459 #define F_STATIC_KX_PLL_CCALFMAX    V_STATIC_KX_PLL_CCALFMAX(1U)
17460 
17461 #define S_STATIC_KX_PLL_CCALCVHOLD    19
17462 #define V_STATIC_KX_PLL_CCALCVHOLD(x) ((x) << S_STATIC_KX_PLL_CCALCVHOLD)
17463 #define F_STATIC_KX_PLL_CCALCVHOLD    V_STATIC_KX_PLL_CCALCVHOLD(1U)
17464 
17465 #define S_STATIC_KX_PLL_CCALBANDSEL    15
17466 #define M_STATIC_KX_PLL_CCALBANDSEL    0xfU
17467 #define V_STATIC_KX_PLL_CCALBANDSEL(x) ((x) << S_STATIC_KX_PLL_CCALBANDSEL)
17468 #define G_STATIC_KX_PLL_CCALBANDSEL(x) (((x) >> S_STATIC_KX_PLL_CCALBANDSEL) & M_STATIC_KX_PLL_CCALBANDSEL)
17469 
17470 #define S_STATIC_KX_PLL_BGOFFSET    11
17471 #define M_STATIC_KX_PLL_BGOFFSET    0xfU
17472 #define V_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_STATIC_KX_PLL_BGOFFSET)
17473 #define G_STATIC_KX_PLL_BGOFFSET(x) (((x) >> S_STATIC_KX_PLL_BGOFFSET) & M_STATIC_KX_PLL_BGOFFSET)
17474 
17475 #define S_T6_STATIC_KX_PLL_P    8
17476 #define M_T6_STATIC_KX_PLL_P    0x7U
17477 #define V_T6_STATIC_KX_PLL_P(x) ((x) << S_T6_STATIC_KX_PLL_P)
17478 #define G_T6_STATIC_KX_PLL_P(x) (((x) >> S_T6_STATIC_KX_PLL_P) & M_T6_STATIC_KX_PLL_P)
17479 
17480 #define S_T6_STATIC_KX_PLL_N2    4
17481 #define M_T6_STATIC_KX_PLL_N2    0xfU
17482 #define V_T6_STATIC_KX_PLL_N2(x) ((x) << S_T6_STATIC_KX_PLL_N2)
17483 #define G_T6_STATIC_KX_PLL_N2(x) (((x) >> S_T6_STATIC_KX_PLL_N2) & M_T6_STATIC_KX_PLL_N2)
17484 
17485 #define S_T6_STATIC_KX_PLL_N1    0
17486 #define M_T6_STATIC_KX_PLL_N1    0xfU
17487 #define V_T6_STATIC_KX_PLL_N1(x) ((x) << S_T6_STATIC_KX_PLL_N1)
17488 #define G_T6_STATIC_KX_PLL_N1(x) (((x) >> S_T6_STATIC_KX_PLL_N1) & M_T6_STATIC_KX_PLL_N1)
17489 
17490 #define A_DBG_PVT_REG_DRVN 0x610c
17491 
17492 #define S_PVT_REG_DRVN_EN    8
17493 #define V_PVT_REG_DRVN_EN(x) ((x) << S_PVT_REG_DRVN_EN)
17494 #define F_PVT_REG_DRVN_EN    V_PVT_REG_DRVN_EN(1U)
17495 
17496 #define S_PVT_REG_DRVN_B    4
17497 #define M_PVT_REG_DRVN_B    0xfU
17498 #define V_PVT_REG_DRVN_B(x) ((x) << S_PVT_REG_DRVN_B)
17499 #define G_PVT_REG_DRVN_B(x) (((x) >> S_PVT_REG_DRVN_B) & M_PVT_REG_DRVN_B)
17500 
17501 #define S_PVT_REG_DRVN_A    0
17502 #define M_PVT_REG_DRVN_A    0xfU
17503 #define V_PVT_REG_DRVN_A(x) ((x) << S_PVT_REG_DRVN_A)
17504 #define G_PVT_REG_DRVN_A(x) (((x) >> S_PVT_REG_DRVN_A) & M_PVT_REG_DRVN_A)
17505 
17506 #define A_DBG_T5_STATIC_KX_PLL_CONF2 0x610c
17507 
17508 #define S_T5_STATIC_KX_PLL_M    11
17509 #define M_T5_STATIC_KX_PLL_M    0x1ffU
17510 #define V_T5_STATIC_KX_PLL_M(x) ((x) << S_T5_STATIC_KX_PLL_M)
17511 #define G_T5_STATIC_KX_PLL_M(x) (((x) >> S_T5_STATIC_KX_PLL_M) & M_T5_STATIC_KX_PLL_M)
17512 
17513 #define S_T5_STATIC_KX_PLL_ANALOGTUNE    0
17514 #define M_T5_STATIC_KX_PLL_ANALOGTUNE    0x7ffU
17515 #define V_T5_STATIC_KX_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KX_PLL_ANALOGTUNE)
17516 #define G_T5_STATIC_KX_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KX_PLL_ANALOGTUNE) & M_T5_STATIC_KX_PLL_ANALOGTUNE)
17517 
17518 #define A_DBG_STATIC_KX_PLL_CONF2 0x610c
17519 
17520 #define S_T6_STATIC_KX_PLL_M    11
17521 #define M_T6_STATIC_KX_PLL_M    0x1ffU
17522 #define V_T6_STATIC_KX_PLL_M(x) ((x) << S_T6_STATIC_KX_PLL_M)
17523 #define G_T6_STATIC_KX_PLL_M(x) (((x) >> S_T6_STATIC_KX_PLL_M) & M_T6_STATIC_KX_PLL_M)
17524 
17525 #define S_STATIC_KX_PLL_ANALOGTUNE    0
17526 #define M_STATIC_KX_PLL_ANALOGTUNE    0x7ffU
17527 #define V_STATIC_KX_PLL_ANALOGTUNE(x) ((x) << S_STATIC_KX_PLL_ANALOGTUNE)
17528 #define G_STATIC_KX_PLL_ANALOGTUNE(x) (((x) >> S_STATIC_KX_PLL_ANALOGTUNE) & M_STATIC_KX_PLL_ANALOGTUNE)
17529 
17530 #define A_DBG_PVT_REG_DRVP 0x6110
17531 
17532 #define S_PVT_REG_DRVP_EN    8
17533 #define V_PVT_REG_DRVP_EN(x) ((x) << S_PVT_REG_DRVP_EN)
17534 #define F_PVT_REG_DRVP_EN    V_PVT_REG_DRVP_EN(1U)
17535 
17536 #define S_PVT_REG_DRVP_B    4
17537 #define M_PVT_REG_DRVP_B    0xfU
17538 #define V_PVT_REG_DRVP_B(x) ((x) << S_PVT_REG_DRVP_B)
17539 #define G_PVT_REG_DRVP_B(x) (((x) >> S_PVT_REG_DRVP_B) & M_PVT_REG_DRVP_B)
17540 
17541 #define S_PVT_REG_DRVP_A    0
17542 #define M_PVT_REG_DRVP_A    0xfU
17543 #define V_PVT_REG_DRVP_A(x) ((x) << S_PVT_REG_DRVP_A)
17544 #define G_PVT_REG_DRVP_A(x) (((x) >> S_PVT_REG_DRVP_A) & M_PVT_REG_DRVP_A)
17545 
17546 #define A_DBG_T5_STATIC_C_DFS_CONF 0x6110
17547 
17548 #define S_STATIC_C_DFS_RANGEA    8
17549 #define M_STATIC_C_DFS_RANGEA    0x1fU
17550 #define V_STATIC_C_DFS_RANGEA(x) ((x) << S_STATIC_C_DFS_RANGEA)
17551 #define G_STATIC_C_DFS_RANGEA(x) (((x) >> S_STATIC_C_DFS_RANGEA) & M_STATIC_C_DFS_RANGEA)
17552 
17553 #define S_STATIC_C_DFS_RANGEB    3
17554 #define M_STATIC_C_DFS_RANGEB    0x1fU
17555 #define V_STATIC_C_DFS_RANGEB(x) ((x) << S_STATIC_C_DFS_RANGEB)
17556 #define G_STATIC_C_DFS_RANGEB(x) (((x) >> S_STATIC_C_DFS_RANGEB) & M_STATIC_C_DFS_RANGEB)
17557 
17558 #define S_STATIC_C_DFS_FFTUNE4    2
17559 #define V_STATIC_C_DFS_FFTUNE4(x) ((x) << S_STATIC_C_DFS_FFTUNE4)
17560 #define F_STATIC_C_DFS_FFTUNE4    V_STATIC_C_DFS_FFTUNE4(1U)
17561 
17562 #define S_STATIC_C_DFS_FFTUNE5    1
17563 #define V_STATIC_C_DFS_FFTUNE5(x) ((x) << S_STATIC_C_DFS_FFTUNE5)
17564 #define F_STATIC_C_DFS_FFTUNE5    V_STATIC_C_DFS_FFTUNE5(1U)
17565 
17566 #define S_STATIC_C_DFS_ENABLE    0
17567 #define V_STATIC_C_DFS_ENABLE(x) ((x) << S_STATIC_C_DFS_ENABLE)
17568 #define F_STATIC_C_DFS_ENABLE    V_STATIC_C_DFS_ENABLE(1U)
17569 
17570 #define A_DBG_STATIC_C_DFS_CONF 0x6110
17571 #define A_DBG_PVT_REG_TERMN 0x6114
17572 
17573 #define S_PVT_REG_TERMN_EN    8
17574 #define V_PVT_REG_TERMN_EN(x) ((x) << S_PVT_REG_TERMN_EN)
17575 #define F_PVT_REG_TERMN_EN    V_PVT_REG_TERMN_EN(1U)
17576 
17577 #define S_PVT_REG_TERMN_B    4
17578 #define M_PVT_REG_TERMN_B    0xfU
17579 #define V_PVT_REG_TERMN_B(x) ((x) << S_PVT_REG_TERMN_B)
17580 #define G_PVT_REG_TERMN_B(x) (((x) >> S_PVT_REG_TERMN_B) & M_PVT_REG_TERMN_B)
17581 
17582 #define S_PVT_REG_TERMN_A    0
17583 #define M_PVT_REG_TERMN_A    0xfU
17584 #define V_PVT_REG_TERMN_A(x) ((x) << S_PVT_REG_TERMN_A)
17585 #define G_PVT_REG_TERMN_A(x) (((x) >> S_PVT_REG_TERMN_A) & M_PVT_REG_TERMN_A)
17586 
17587 #define A_DBG_T5_STATIC_U_DFS_CONF 0x6114
17588 
17589 #define S_STATIC_U_DFS_RANGEA    8
17590 #define M_STATIC_U_DFS_RANGEA    0x1fU
17591 #define V_STATIC_U_DFS_RANGEA(x) ((x) << S_STATIC_U_DFS_RANGEA)
17592 #define G_STATIC_U_DFS_RANGEA(x) (((x) >> S_STATIC_U_DFS_RANGEA) & M_STATIC_U_DFS_RANGEA)
17593 
17594 #define S_STATIC_U_DFS_RANGEB    3
17595 #define M_STATIC_U_DFS_RANGEB    0x1fU
17596 #define V_STATIC_U_DFS_RANGEB(x) ((x) << S_STATIC_U_DFS_RANGEB)
17597 #define G_STATIC_U_DFS_RANGEB(x) (((x) >> S_STATIC_U_DFS_RANGEB) & M_STATIC_U_DFS_RANGEB)
17598 
17599 #define S_STATIC_U_DFS_FFTUNE4    2
17600 #define V_STATIC_U_DFS_FFTUNE4(x) ((x) << S_STATIC_U_DFS_FFTUNE4)
17601 #define F_STATIC_U_DFS_FFTUNE4    V_STATIC_U_DFS_FFTUNE4(1U)
17602 
17603 #define S_STATIC_U_DFS_FFTUNE5    1
17604 #define V_STATIC_U_DFS_FFTUNE5(x) ((x) << S_STATIC_U_DFS_FFTUNE5)
17605 #define F_STATIC_U_DFS_FFTUNE5    V_STATIC_U_DFS_FFTUNE5(1U)
17606 
17607 #define S_STATIC_U_DFS_ENABLE    0
17608 #define V_STATIC_U_DFS_ENABLE(x) ((x) << S_STATIC_U_DFS_ENABLE)
17609 #define F_STATIC_U_DFS_ENABLE    V_STATIC_U_DFS_ENABLE(1U)
17610 
17611 #define A_DBG_STATIC_U_DFS_CONF 0x6114
17612 #define A_DBG_PVT_REG_TERMP 0x6118
17613 
17614 #define S_PVT_REG_TERMP_EN    8
17615 #define V_PVT_REG_TERMP_EN(x) ((x) << S_PVT_REG_TERMP_EN)
17616 #define F_PVT_REG_TERMP_EN    V_PVT_REG_TERMP_EN(1U)
17617 
17618 #define S_PVT_REG_TERMP_B    4
17619 #define M_PVT_REG_TERMP_B    0xfU
17620 #define V_PVT_REG_TERMP_B(x) ((x) << S_PVT_REG_TERMP_B)
17621 #define G_PVT_REG_TERMP_B(x) (((x) >> S_PVT_REG_TERMP_B) & M_PVT_REG_TERMP_B)
17622 
17623 #define S_PVT_REG_TERMP_A    0
17624 #define M_PVT_REG_TERMP_A    0xfU
17625 #define V_PVT_REG_TERMP_A(x) ((x) << S_PVT_REG_TERMP_A)
17626 #define G_PVT_REG_TERMP_A(x) (((x) >> S_PVT_REG_TERMP_A) & M_PVT_REG_TERMP_A)
17627 
17628 #define A_DBG_GPIO_PE_EN 0x6118
17629 
17630 #define S_GPIO19_PE_EN    19
17631 #define V_GPIO19_PE_EN(x) ((x) << S_GPIO19_PE_EN)
17632 #define F_GPIO19_PE_EN    V_GPIO19_PE_EN(1U)
17633 
17634 #define S_GPIO18_PE_EN    18
17635 #define V_GPIO18_PE_EN(x) ((x) << S_GPIO18_PE_EN)
17636 #define F_GPIO18_PE_EN    V_GPIO18_PE_EN(1U)
17637 
17638 #define S_GPIO17_PE_EN    17
17639 #define V_GPIO17_PE_EN(x) ((x) << S_GPIO17_PE_EN)
17640 #define F_GPIO17_PE_EN    V_GPIO17_PE_EN(1U)
17641 
17642 #define S_GPIO16_PE_EN    16
17643 #define V_GPIO16_PE_EN(x) ((x) << S_GPIO16_PE_EN)
17644 #define F_GPIO16_PE_EN    V_GPIO16_PE_EN(1U)
17645 
17646 #define S_GPIO15_PE_EN    15
17647 #define V_GPIO15_PE_EN(x) ((x) << S_GPIO15_PE_EN)
17648 #define F_GPIO15_PE_EN    V_GPIO15_PE_EN(1U)
17649 
17650 #define S_GPIO14_PE_EN    14
17651 #define V_GPIO14_PE_EN(x) ((x) << S_GPIO14_PE_EN)
17652 #define F_GPIO14_PE_EN    V_GPIO14_PE_EN(1U)
17653 
17654 #define S_GPIO13_PE_EN    13
17655 #define V_GPIO13_PE_EN(x) ((x) << S_GPIO13_PE_EN)
17656 #define F_GPIO13_PE_EN    V_GPIO13_PE_EN(1U)
17657 
17658 #define S_GPIO12_PE_EN    12
17659 #define V_GPIO12_PE_EN(x) ((x) << S_GPIO12_PE_EN)
17660 #define F_GPIO12_PE_EN    V_GPIO12_PE_EN(1U)
17661 
17662 #define S_GPIO11_PE_EN    11
17663 #define V_GPIO11_PE_EN(x) ((x) << S_GPIO11_PE_EN)
17664 #define F_GPIO11_PE_EN    V_GPIO11_PE_EN(1U)
17665 
17666 #define S_GPIO10_PE_EN    10
17667 #define V_GPIO10_PE_EN(x) ((x) << S_GPIO10_PE_EN)
17668 #define F_GPIO10_PE_EN    V_GPIO10_PE_EN(1U)
17669 
17670 #define S_GPIO9_PE_EN    9
17671 #define V_GPIO9_PE_EN(x) ((x) << S_GPIO9_PE_EN)
17672 #define F_GPIO9_PE_EN    V_GPIO9_PE_EN(1U)
17673 
17674 #define S_GPIO8_PE_EN    8
17675 #define V_GPIO8_PE_EN(x) ((x) << S_GPIO8_PE_EN)
17676 #define F_GPIO8_PE_EN    V_GPIO8_PE_EN(1U)
17677 
17678 #define S_GPIO7_PE_EN    7
17679 #define V_GPIO7_PE_EN(x) ((x) << S_GPIO7_PE_EN)
17680 #define F_GPIO7_PE_EN    V_GPIO7_PE_EN(1U)
17681 
17682 #define S_GPIO6_PE_EN    6
17683 #define V_GPIO6_PE_EN(x) ((x) << S_GPIO6_PE_EN)
17684 #define F_GPIO6_PE_EN    V_GPIO6_PE_EN(1U)
17685 
17686 #define S_GPIO5_PE_EN    5
17687 #define V_GPIO5_PE_EN(x) ((x) << S_GPIO5_PE_EN)
17688 #define F_GPIO5_PE_EN    V_GPIO5_PE_EN(1U)
17689 
17690 #define S_GPIO4_PE_EN    4
17691 #define V_GPIO4_PE_EN(x) ((x) << S_GPIO4_PE_EN)
17692 #define F_GPIO4_PE_EN    V_GPIO4_PE_EN(1U)
17693 
17694 #define S_GPIO3_PE_EN    3
17695 #define V_GPIO3_PE_EN(x) ((x) << S_GPIO3_PE_EN)
17696 #define F_GPIO3_PE_EN    V_GPIO3_PE_EN(1U)
17697 
17698 #define S_GPIO2_PE_EN    2
17699 #define V_GPIO2_PE_EN(x) ((x) << S_GPIO2_PE_EN)
17700 #define F_GPIO2_PE_EN    V_GPIO2_PE_EN(1U)
17701 
17702 #define S_GPIO1_PE_EN    1
17703 #define V_GPIO1_PE_EN(x) ((x) << S_GPIO1_PE_EN)
17704 #define F_GPIO1_PE_EN    V_GPIO1_PE_EN(1U)
17705 
17706 #define S_GPIO0_PE_EN    0
17707 #define V_GPIO0_PE_EN(x) ((x) << S_GPIO0_PE_EN)
17708 #define F_GPIO0_PE_EN    V_GPIO0_PE_EN(1U)
17709 
17710 #define S_GPIO23_PE_EN    23
17711 #define V_GPIO23_PE_EN(x) ((x) << S_GPIO23_PE_EN)
17712 #define F_GPIO23_PE_EN    V_GPIO23_PE_EN(1U)
17713 
17714 #define S_GPIO22_PE_EN    22
17715 #define V_GPIO22_PE_EN(x) ((x) << S_GPIO22_PE_EN)
17716 #define F_GPIO22_PE_EN    V_GPIO22_PE_EN(1U)
17717 
17718 #define S_GPIO21_PE_EN    21
17719 #define V_GPIO21_PE_EN(x) ((x) << S_GPIO21_PE_EN)
17720 #define F_GPIO21_PE_EN    V_GPIO21_PE_EN(1U)
17721 
17722 #define S_GPIO20_PE_EN    20
17723 #define V_GPIO20_PE_EN(x) ((x) << S_GPIO20_PE_EN)
17724 #define F_GPIO20_PE_EN    V_GPIO20_PE_EN(1U)
17725 
17726 #define A_DBG_PVT_REG_THRESHOLD 0x611c
17727 
17728 #define S_PVT_CALIBRATION_DONE    8
17729 #define V_PVT_CALIBRATION_DONE(x) ((x) << S_PVT_CALIBRATION_DONE)
17730 #define F_PVT_CALIBRATION_DONE    V_PVT_CALIBRATION_DONE(1U)
17731 
17732 #define S_THRESHOLD_TERMP_MAX_SYNC    7
17733 #define V_THRESHOLD_TERMP_MAX_SYNC(x) ((x) << S_THRESHOLD_TERMP_MAX_SYNC)
17734 #define F_THRESHOLD_TERMP_MAX_SYNC    V_THRESHOLD_TERMP_MAX_SYNC(1U)
17735 
17736 #define S_THRESHOLD_TERMP_MIN_SYNC    6
17737 #define V_THRESHOLD_TERMP_MIN_SYNC(x) ((x) << S_THRESHOLD_TERMP_MIN_SYNC)
17738 #define F_THRESHOLD_TERMP_MIN_SYNC    V_THRESHOLD_TERMP_MIN_SYNC(1U)
17739 
17740 #define S_THRESHOLD_TERMN_MAX_SYNC    5
17741 #define V_THRESHOLD_TERMN_MAX_SYNC(x) ((x) << S_THRESHOLD_TERMN_MAX_SYNC)
17742 #define F_THRESHOLD_TERMN_MAX_SYNC    V_THRESHOLD_TERMN_MAX_SYNC(1U)
17743 
17744 #define S_THRESHOLD_TERMN_MIN_SYNC    4
17745 #define V_THRESHOLD_TERMN_MIN_SYNC(x) ((x) << S_THRESHOLD_TERMN_MIN_SYNC)
17746 #define F_THRESHOLD_TERMN_MIN_SYNC    V_THRESHOLD_TERMN_MIN_SYNC(1U)
17747 
17748 #define S_THRESHOLD_DRVP_MAX_SYNC    3
17749 #define V_THRESHOLD_DRVP_MAX_SYNC(x) ((x) << S_THRESHOLD_DRVP_MAX_SYNC)
17750 #define F_THRESHOLD_DRVP_MAX_SYNC    V_THRESHOLD_DRVP_MAX_SYNC(1U)
17751 
17752 #define S_THRESHOLD_DRVP_MIN_SYNC    2
17753 #define V_THRESHOLD_DRVP_MIN_SYNC(x) ((x) << S_THRESHOLD_DRVP_MIN_SYNC)
17754 #define F_THRESHOLD_DRVP_MIN_SYNC    V_THRESHOLD_DRVP_MIN_SYNC(1U)
17755 
17756 #define S_THRESHOLD_DRVN_MAX_SYNC    1
17757 #define V_THRESHOLD_DRVN_MAX_SYNC(x) ((x) << S_THRESHOLD_DRVN_MAX_SYNC)
17758 #define F_THRESHOLD_DRVN_MAX_SYNC    V_THRESHOLD_DRVN_MAX_SYNC(1U)
17759 
17760 #define S_THRESHOLD_DRVN_MIN_SYNC    0
17761 #define V_THRESHOLD_DRVN_MIN_SYNC(x) ((x) << S_THRESHOLD_DRVN_MIN_SYNC)
17762 #define F_THRESHOLD_DRVN_MIN_SYNC    V_THRESHOLD_DRVN_MIN_SYNC(1U)
17763 
17764 #define A_DBG_GPIO_PS_EN 0x611c
17765 
17766 #define S_GPIO19_PS_EN    19
17767 #define V_GPIO19_PS_EN(x) ((x) << S_GPIO19_PS_EN)
17768 #define F_GPIO19_PS_EN    V_GPIO19_PS_EN(1U)
17769 
17770 #define S_GPIO18_PS_EN    18
17771 #define V_GPIO18_PS_EN(x) ((x) << S_GPIO18_PS_EN)
17772 #define F_GPIO18_PS_EN    V_GPIO18_PS_EN(1U)
17773 
17774 #define S_GPIO17_PS_EN    17
17775 #define V_GPIO17_PS_EN(x) ((x) << S_GPIO17_PS_EN)
17776 #define F_GPIO17_PS_EN    V_GPIO17_PS_EN(1U)
17777 
17778 #define S_GPIO16_PS_EN    16
17779 #define V_GPIO16_PS_EN(x) ((x) << S_GPIO16_PS_EN)
17780 #define F_GPIO16_PS_EN    V_GPIO16_PS_EN(1U)
17781 
17782 #define S_GPIO15_PS_EN    15
17783 #define V_GPIO15_PS_EN(x) ((x) << S_GPIO15_PS_EN)
17784 #define F_GPIO15_PS_EN    V_GPIO15_PS_EN(1U)
17785 
17786 #define S_GPIO14_PS_EN    14
17787 #define V_GPIO14_PS_EN(x) ((x) << S_GPIO14_PS_EN)
17788 #define F_GPIO14_PS_EN    V_GPIO14_PS_EN(1U)
17789 
17790 #define S_GPIO13_PS_EN    13
17791 #define V_GPIO13_PS_EN(x) ((x) << S_GPIO13_PS_EN)
17792 #define F_GPIO13_PS_EN    V_GPIO13_PS_EN(1U)
17793 
17794 #define S_GPIO12_PS_EN    12
17795 #define V_GPIO12_PS_EN(x) ((x) << S_GPIO12_PS_EN)
17796 #define F_GPIO12_PS_EN    V_GPIO12_PS_EN(1U)
17797 
17798 #define S_GPIO11_PS_EN    11
17799 #define V_GPIO11_PS_EN(x) ((x) << S_GPIO11_PS_EN)
17800 #define F_GPIO11_PS_EN    V_GPIO11_PS_EN(1U)
17801 
17802 #define S_GPIO10_PS_EN    10
17803 #define V_GPIO10_PS_EN(x) ((x) << S_GPIO10_PS_EN)
17804 #define F_GPIO10_PS_EN    V_GPIO10_PS_EN(1U)
17805 
17806 #define S_GPIO9_PS_EN    9
17807 #define V_GPIO9_PS_EN(x) ((x) << S_GPIO9_PS_EN)
17808 #define F_GPIO9_PS_EN    V_GPIO9_PS_EN(1U)
17809 
17810 #define S_GPIO8_PS_EN    8
17811 #define V_GPIO8_PS_EN(x) ((x) << S_GPIO8_PS_EN)
17812 #define F_GPIO8_PS_EN    V_GPIO8_PS_EN(1U)
17813 
17814 #define S_GPIO7_PS_EN    7
17815 #define V_GPIO7_PS_EN(x) ((x) << S_GPIO7_PS_EN)
17816 #define F_GPIO7_PS_EN    V_GPIO7_PS_EN(1U)
17817 
17818 #define S_GPIO6_PS_EN    6
17819 #define V_GPIO6_PS_EN(x) ((x) << S_GPIO6_PS_EN)
17820 #define F_GPIO6_PS_EN    V_GPIO6_PS_EN(1U)
17821 
17822 #define S_GPIO5_PS_EN    5
17823 #define V_GPIO5_PS_EN(x) ((x) << S_GPIO5_PS_EN)
17824 #define F_GPIO5_PS_EN    V_GPIO5_PS_EN(1U)
17825 
17826 #define S_GPIO4_PS_EN    4
17827 #define V_GPIO4_PS_EN(x) ((x) << S_GPIO4_PS_EN)
17828 #define F_GPIO4_PS_EN    V_GPIO4_PS_EN(1U)
17829 
17830 #define S_GPIO3_PS_EN    3
17831 #define V_GPIO3_PS_EN(x) ((x) << S_GPIO3_PS_EN)
17832 #define F_GPIO3_PS_EN    V_GPIO3_PS_EN(1U)
17833 
17834 #define S_GPIO2_PS_EN    2
17835 #define V_GPIO2_PS_EN(x) ((x) << S_GPIO2_PS_EN)
17836 #define F_GPIO2_PS_EN    V_GPIO2_PS_EN(1U)
17837 
17838 #define S_GPIO1_PS_EN    1
17839 #define V_GPIO1_PS_EN(x) ((x) << S_GPIO1_PS_EN)
17840 #define F_GPIO1_PS_EN    V_GPIO1_PS_EN(1U)
17841 
17842 #define S_GPIO0_PS_EN    0
17843 #define V_GPIO0_PS_EN(x) ((x) << S_GPIO0_PS_EN)
17844 #define F_GPIO0_PS_EN    V_GPIO0_PS_EN(1U)
17845 
17846 #define S_GPIO23_PS_EN    23
17847 #define V_GPIO23_PS_EN(x) ((x) << S_GPIO23_PS_EN)
17848 #define F_GPIO23_PS_EN    V_GPIO23_PS_EN(1U)
17849 
17850 #define S_GPIO22_PS_EN    22
17851 #define V_GPIO22_PS_EN(x) ((x) << S_GPIO22_PS_EN)
17852 #define F_GPIO22_PS_EN    V_GPIO22_PS_EN(1U)
17853 
17854 #define S_GPIO21_PS_EN    21
17855 #define V_GPIO21_PS_EN(x) ((x) << S_GPIO21_PS_EN)
17856 #define F_GPIO21_PS_EN    V_GPIO21_PS_EN(1U)
17857 
17858 #define S_GPIO20_PS_EN    20
17859 #define V_GPIO20_PS_EN(x) ((x) << S_GPIO20_PS_EN)
17860 #define F_GPIO20_PS_EN    V_GPIO20_PS_EN(1U)
17861 
17862 #define A_DBG_PVT_REG_IN_TERMP 0x6120
17863 
17864 #define S_REG_IN_TERMP_B    4
17865 #define M_REG_IN_TERMP_B    0xfU
17866 #define V_REG_IN_TERMP_B(x) ((x) << S_REG_IN_TERMP_B)
17867 #define G_REG_IN_TERMP_B(x) (((x) >> S_REG_IN_TERMP_B) & M_REG_IN_TERMP_B)
17868 
17869 #define S_REG_IN_TERMP_A    0
17870 #define M_REG_IN_TERMP_A    0xfU
17871 #define V_REG_IN_TERMP_A(x) ((x) << S_REG_IN_TERMP_A)
17872 #define G_REG_IN_TERMP_A(x) (((x) >> S_REG_IN_TERMP_A) & M_REG_IN_TERMP_A)
17873 
17874 #define A_DBG_EFUSE_BYTE16_19 0x6120
17875 #define A_DBG_PVT_REG_IN_TERMN 0x6124
17876 
17877 #define S_REG_IN_TERMN_B    4
17878 #define M_REG_IN_TERMN_B    0xfU
17879 #define V_REG_IN_TERMN_B(x) ((x) << S_REG_IN_TERMN_B)
17880 #define G_REG_IN_TERMN_B(x) (((x) >> S_REG_IN_TERMN_B) & M_REG_IN_TERMN_B)
17881 
17882 #define S_REG_IN_TERMN_A    0
17883 #define M_REG_IN_TERMN_A    0xfU
17884 #define V_REG_IN_TERMN_A(x) ((x) << S_REG_IN_TERMN_A)
17885 #define G_REG_IN_TERMN_A(x) (((x) >> S_REG_IN_TERMN_A) & M_REG_IN_TERMN_A)
17886 
17887 #define A_DBG_EFUSE_BYTE20_23 0x6124
17888 #define A_DBG_PVT_REG_IN_DRVP 0x6128
17889 
17890 #define S_REG_IN_DRVP_B    4
17891 #define M_REG_IN_DRVP_B    0xfU
17892 #define V_REG_IN_DRVP_B(x) ((x) << S_REG_IN_DRVP_B)
17893 #define G_REG_IN_DRVP_B(x) (((x) >> S_REG_IN_DRVP_B) & M_REG_IN_DRVP_B)
17894 
17895 #define S_REG_IN_DRVP_A    0
17896 #define M_REG_IN_DRVP_A    0xfU
17897 #define V_REG_IN_DRVP_A(x) ((x) << S_REG_IN_DRVP_A)
17898 #define G_REG_IN_DRVP_A(x) (((x) >> S_REG_IN_DRVP_A) & M_REG_IN_DRVP_A)
17899 
17900 #define A_DBG_EFUSE_BYTE24_27 0x6128
17901 #define A_DBG_PVT_REG_IN_DRVN 0x612c
17902 
17903 #define S_REG_IN_DRVN_B    4
17904 #define M_REG_IN_DRVN_B    0xfU
17905 #define V_REG_IN_DRVN_B(x) ((x) << S_REG_IN_DRVN_B)
17906 #define G_REG_IN_DRVN_B(x) (((x) >> S_REG_IN_DRVN_B) & M_REG_IN_DRVN_B)
17907 
17908 #define S_REG_IN_DRVN_A    0
17909 #define M_REG_IN_DRVN_A    0xfU
17910 #define V_REG_IN_DRVN_A(x) ((x) << S_REG_IN_DRVN_A)
17911 #define G_REG_IN_DRVN_A(x) (((x) >> S_REG_IN_DRVN_A) & M_REG_IN_DRVN_A)
17912 
17913 #define A_DBG_EFUSE_BYTE28_31 0x612c
17914 #define A_DBG_PVT_REG_OUT_TERMP 0x6130
17915 
17916 #define S_REG_OUT_TERMP_B    4
17917 #define M_REG_OUT_TERMP_B    0xfU
17918 #define V_REG_OUT_TERMP_B(x) ((x) << S_REG_OUT_TERMP_B)
17919 #define G_REG_OUT_TERMP_B(x) (((x) >> S_REG_OUT_TERMP_B) & M_REG_OUT_TERMP_B)
17920 
17921 #define S_REG_OUT_TERMP_A    0
17922 #define M_REG_OUT_TERMP_A    0xfU
17923 #define V_REG_OUT_TERMP_A(x) ((x) << S_REG_OUT_TERMP_A)
17924 #define G_REG_OUT_TERMP_A(x) (((x) >> S_REG_OUT_TERMP_A) & M_REG_OUT_TERMP_A)
17925 
17926 #define A_DBG_EFUSE_BYTE32_35 0x6130
17927 #define A_DBG_PVT_REG_OUT_TERMN 0x6134
17928 
17929 #define S_REG_OUT_TERMN_B    4
17930 #define M_REG_OUT_TERMN_B    0xfU
17931 #define V_REG_OUT_TERMN_B(x) ((x) << S_REG_OUT_TERMN_B)
17932 #define G_REG_OUT_TERMN_B(x) (((x) >> S_REG_OUT_TERMN_B) & M_REG_OUT_TERMN_B)
17933 
17934 #define S_REG_OUT_TERMN_A    0
17935 #define M_REG_OUT_TERMN_A    0xfU
17936 #define V_REG_OUT_TERMN_A(x) ((x) << S_REG_OUT_TERMN_A)
17937 #define G_REG_OUT_TERMN_A(x) (((x) >> S_REG_OUT_TERMN_A) & M_REG_OUT_TERMN_A)
17938 
17939 #define A_DBG_EFUSE_BYTE36_39 0x6134
17940 #define A_DBG_PVT_REG_OUT_DRVP 0x6138
17941 
17942 #define S_REG_OUT_DRVP_B    4
17943 #define M_REG_OUT_DRVP_B    0xfU
17944 #define V_REG_OUT_DRVP_B(x) ((x) << S_REG_OUT_DRVP_B)
17945 #define G_REG_OUT_DRVP_B(x) (((x) >> S_REG_OUT_DRVP_B) & M_REG_OUT_DRVP_B)
17946 
17947 #define S_REG_OUT_DRVP_A    0
17948 #define M_REG_OUT_DRVP_A    0xfU
17949 #define V_REG_OUT_DRVP_A(x) ((x) << S_REG_OUT_DRVP_A)
17950 #define G_REG_OUT_DRVP_A(x) (((x) >> S_REG_OUT_DRVP_A) & M_REG_OUT_DRVP_A)
17951 
17952 #define A_DBG_EFUSE_BYTE40_43 0x6138
17953 #define A_DBG_PVT_REG_OUT_DRVN 0x613c
17954 
17955 #define S_REG_OUT_DRVN_B    4
17956 #define M_REG_OUT_DRVN_B    0xfU
17957 #define V_REG_OUT_DRVN_B(x) ((x) << S_REG_OUT_DRVN_B)
17958 #define G_REG_OUT_DRVN_B(x) (((x) >> S_REG_OUT_DRVN_B) & M_REG_OUT_DRVN_B)
17959 
17960 #define S_REG_OUT_DRVN_A    0
17961 #define M_REG_OUT_DRVN_A    0xfU
17962 #define V_REG_OUT_DRVN_A(x) ((x) << S_REG_OUT_DRVN_A)
17963 #define G_REG_OUT_DRVN_A(x) (((x) >> S_REG_OUT_DRVN_A) & M_REG_OUT_DRVN_A)
17964 
17965 #define A_DBG_EFUSE_BYTE44_47 0x613c
17966 #define A_DBG_PVT_REG_HISTORY_TERMP 0x6140
17967 
17968 #define S_TERMP_B_HISTORY    4
17969 #define M_TERMP_B_HISTORY    0xfU
17970 #define V_TERMP_B_HISTORY(x) ((x) << S_TERMP_B_HISTORY)
17971 #define G_TERMP_B_HISTORY(x) (((x) >> S_TERMP_B_HISTORY) & M_TERMP_B_HISTORY)
17972 
17973 #define S_TERMP_A_HISTORY    0
17974 #define M_TERMP_A_HISTORY    0xfU
17975 #define V_TERMP_A_HISTORY(x) ((x) << S_TERMP_A_HISTORY)
17976 #define G_TERMP_A_HISTORY(x) (((x) >> S_TERMP_A_HISTORY) & M_TERMP_A_HISTORY)
17977 
17978 #define A_DBG_EFUSE_BYTE48_51 0x6140
17979 #define A_DBG_PVT_REG_HISTORY_TERMN 0x6144
17980 
17981 #define S_TERMN_B_HISTORY    4
17982 #define M_TERMN_B_HISTORY    0xfU
17983 #define V_TERMN_B_HISTORY(x) ((x) << S_TERMN_B_HISTORY)
17984 #define G_TERMN_B_HISTORY(x) (((x) >> S_TERMN_B_HISTORY) & M_TERMN_B_HISTORY)
17985 
17986 #define S_TERMN_A_HISTORY    0
17987 #define M_TERMN_A_HISTORY    0xfU
17988 #define V_TERMN_A_HISTORY(x) ((x) << S_TERMN_A_HISTORY)
17989 #define G_TERMN_A_HISTORY(x) (((x) >> S_TERMN_A_HISTORY) & M_TERMN_A_HISTORY)
17990 
17991 #define A_DBG_EFUSE_BYTE52_55 0x6144
17992 #define A_DBG_PVT_REG_HISTORY_DRVP 0x6148
17993 
17994 #define S_DRVP_B_HISTORY    4
17995 #define M_DRVP_B_HISTORY    0xfU
17996 #define V_DRVP_B_HISTORY(x) ((x) << S_DRVP_B_HISTORY)
17997 #define G_DRVP_B_HISTORY(x) (((x) >> S_DRVP_B_HISTORY) & M_DRVP_B_HISTORY)
17998 
17999 #define S_DRVP_A_HISTORY    0
18000 #define M_DRVP_A_HISTORY    0xfU
18001 #define V_DRVP_A_HISTORY(x) ((x) << S_DRVP_A_HISTORY)
18002 #define G_DRVP_A_HISTORY(x) (((x) >> S_DRVP_A_HISTORY) & M_DRVP_A_HISTORY)
18003 
18004 #define A_DBG_EFUSE_BYTE56_59 0x6148
18005 #define A_DBG_PVT_REG_HISTORY_DRVN 0x614c
18006 
18007 #define S_DRVN_B_HISTORY    4
18008 #define M_DRVN_B_HISTORY    0xfU
18009 #define V_DRVN_B_HISTORY(x) ((x) << S_DRVN_B_HISTORY)
18010 #define G_DRVN_B_HISTORY(x) (((x) >> S_DRVN_B_HISTORY) & M_DRVN_B_HISTORY)
18011 
18012 #define S_DRVN_A_HISTORY    0
18013 #define M_DRVN_A_HISTORY    0xfU
18014 #define V_DRVN_A_HISTORY(x) ((x) << S_DRVN_A_HISTORY)
18015 #define G_DRVN_A_HISTORY(x) (((x) >> S_DRVN_A_HISTORY) & M_DRVN_A_HISTORY)
18016 
18017 #define A_DBG_EFUSE_BYTE60_63 0x614c
18018 #define A_DBG_PVT_REG_SAMPLE_WAIT_CLKS 0x6150
18019 
18020 #define S_SAMPLE_WAIT_CLKS    0
18021 #define M_SAMPLE_WAIT_CLKS    0x1fU
18022 #define V_SAMPLE_WAIT_CLKS(x) ((x) << S_SAMPLE_WAIT_CLKS)
18023 #define G_SAMPLE_WAIT_CLKS(x) (((x) >> S_SAMPLE_WAIT_CLKS) & M_SAMPLE_WAIT_CLKS)
18024 
18025 #define A_DBG_STATIC_U_PLL_CONF6 0x6150
18026 
18027 #define S_STATIC_U_PLL_VREGTUNE    0
18028 #define M_STATIC_U_PLL_VREGTUNE    0x7ffffU
18029 #define V_STATIC_U_PLL_VREGTUNE(x) ((x) << S_STATIC_U_PLL_VREGTUNE)
18030 #define G_STATIC_U_PLL_VREGTUNE(x) (((x) >> S_STATIC_U_PLL_VREGTUNE) & M_STATIC_U_PLL_VREGTUNE)
18031 
18032 #define A_DBG_STATIC_PLL_LOCK_WAIT_CONF 0x6150
18033 
18034 #define S_STATIC_WAIT_LOCK    24
18035 #define V_STATIC_WAIT_LOCK(x) ((x) << S_STATIC_WAIT_LOCK)
18036 #define F_STATIC_WAIT_LOCK    V_STATIC_WAIT_LOCK(1U)
18037 
18038 #define S_STATIC_LOCK_WAIT_TIME    0
18039 #define M_STATIC_LOCK_WAIT_TIME    0xffffffU
18040 #define V_STATIC_LOCK_WAIT_TIME(x) ((x) << S_STATIC_LOCK_WAIT_TIME)
18041 #define G_STATIC_LOCK_WAIT_TIME(x) (((x) >> S_STATIC_LOCK_WAIT_TIME) & M_STATIC_LOCK_WAIT_TIME)
18042 
18043 #define A_DBG_STATIC_C_PLL_CONF6 0x6154
18044 
18045 #define S_STATIC_C_PLL_VREGTUNE    0
18046 #define M_STATIC_C_PLL_VREGTUNE    0x7ffffU
18047 #define V_STATIC_C_PLL_VREGTUNE(x) ((x) << S_STATIC_C_PLL_VREGTUNE)
18048 #define G_STATIC_C_PLL_VREGTUNE(x) (((x) >> S_STATIC_C_PLL_VREGTUNE) & M_STATIC_C_PLL_VREGTUNE)
18049 
18050 #define A_DBG_CUST_EFUSE_PROGRAM 0x6158
18051 
18052 #define S_EFUSE_PROG_PERIOD    16
18053 #define M_EFUSE_PROG_PERIOD    0xffffU
18054 #define V_EFUSE_PROG_PERIOD(x) ((x) << S_EFUSE_PROG_PERIOD)
18055 #define G_EFUSE_PROG_PERIOD(x) (((x) >> S_EFUSE_PROG_PERIOD) & M_EFUSE_PROG_PERIOD)
18056 
18057 #define S_EFUSE_OPER_TYP    14
18058 #define M_EFUSE_OPER_TYP    0x3U
18059 #define V_EFUSE_OPER_TYP(x) ((x) << S_EFUSE_OPER_TYP)
18060 #define G_EFUSE_OPER_TYP(x) (((x) >> S_EFUSE_OPER_TYP) & M_EFUSE_OPER_TYP)
18061 
18062 #define S_EFUSE_ADDR    8
18063 #define M_EFUSE_ADDR    0x3fU
18064 #define V_EFUSE_ADDR(x) ((x) << S_EFUSE_ADDR)
18065 #define G_EFUSE_ADDR(x) (((x) >> S_EFUSE_ADDR) & M_EFUSE_ADDR)
18066 
18067 #define S_EFUSE_DIN    0
18068 #define M_EFUSE_DIN    0xffU
18069 #define V_EFUSE_DIN(x) ((x) << S_EFUSE_DIN)
18070 #define G_EFUSE_DIN(x) (((x) >> S_EFUSE_DIN) & M_EFUSE_DIN)
18071 
18072 #define A_DBG_CUST_EFUSE_OUT 0x615c
18073 
18074 #define S_EFUSE_OPER_DONE    8
18075 #define V_EFUSE_OPER_DONE(x) ((x) << S_EFUSE_OPER_DONE)
18076 #define F_EFUSE_OPER_DONE    V_EFUSE_OPER_DONE(1U)
18077 
18078 #define S_EFUSE_DOUT    0
18079 #define M_EFUSE_DOUT    0xffU
18080 #define V_EFUSE_DOUT(x) ((x) << S_EFUSE_DOUT)
18081 #define G_EFUSE_DOUT(x) (((x) >> S_EFUSE_DOUT) & M_EFUSE_DOUT)
18082 
18083 #define A_DBG_CUST_EFUSE_BYTE0_3 0x6160
18084 #define A_DBG_CUST_EFUSE_BYTE4_7 0x6164
18085 #define A_DBG_CUST_EFUSE_BYTE8_11 0x6168
18086 #define A_DBG_CUST_EFUSE_BYTE12_15 0x616c
18087 #define A_DBG_CUST_EFUSE_BYTE16_19 0x6170
18088 #define A_DBG_CUST_EFUSE_BYTE20_23 0x6174
18089 #define A_DBG_CUST_EFUSE_BYTE24_27 0x6178
18090 #define A_DBG_CUST_EFUSE_BYTE28_31 0x617c
18091 #define A_DBG_CUST_EFUSE_BYTE32_35 0x6180
18092 #define A_DBG_GPIO_INT_ENABLE 0x6180
18093 
18094 #define S_GPIO23    23
18095 #define V_GPIO23(x) ((x) << S_GPIO23)
18096 #define F_GPIO23    V_GPIO23(1U)
18097 
18098 #define S_GPIO22    22
18099 #define V_GPIO22(x) ((x) << S_GPIO22)
18100 #define F_GPIO22    V_GPIO22(1U)
18101 
18102 #define S_GPIO21    21
18103 #define V_GPIO21(x) ((x) << S_GPIO21)
18104 #define F_GPIO21    V_GPIO21(1U)
18105 
18106 #define S_GPIO20    20
18107 #define V_GPIO20(x) ((x) << S_GPIO20)
18108 #define F_GPIO20    V_GPIO20(1U)
18109 
18110 #define S_T7_GPIO19    19
18111 #define V_T7_GPIO19(x) ((x) << S_T7_GPIO19)
18112 #define F_T7_GPIO19    V_T7_GPIO19(1U)
18113 
18114 #define S_T7_GPIO18    18
18115 #define V_T7_GPIO18(x) ((x) << S_T7_GPIO18)
18116 #define F_T7_GPIO18    V_T7_GPIO18(1U)
18117 
18118 #define S_T7_GPIO17    17
18119 #define V_T7_GPIO17(x) ((x) << S_T7_GPIO17)
18120 #define F_T7_GPIO17    V_T7_GPIO17(1U)
18121 
18122 #define S_T7_GPIO16    16
18123 #define V_T7_GPIO16(x) ((x) << S_T7_GPIO16)
18124 #define F_T7_GPIO16    V_T7_GPIO16(1U)
18125 
18126 #define A_DBG_CUST_EFUSE_BYTE36_39 0x6184
18127 #define A_DBG_GPIO_INT_CAUSE 0x6184
18128 #define A_DBG_CUST_EFUSE_BYTE40_43 0x6188
18129 #define A_T7_DBG_GPIO_ACT_LOW 0x6188
18130 
18131 #define S_GPIO23_ACT_LOW    23
18132 #define V_GPIO23_ACT_LOW(x) ((x) << S_GPIO23_ACT_LOW)
18133 #define F_GPIO23_ACT_LOW    V_GPIO23_ACT_LOW(1U)
18134 
18135 #define S_GPIO22_ACT_LOW    22
18136 #define V_GPIO22_ACT_LOW(x) ((x) << S_GPIO22_ACT_LOW)
18137 #define F_GPIO22_ACT_LOW    V_GPIO22_ACT_LOW(1U)
18138 
18139 #define S_GPIO21_ACT_LOW    21
18140 #define V_GPIO21_ACT_LOW(x) ((x) << S_GPIO21_ACT_LOW)
18141 #define F_GPIO21_ACT_LOW    V_GPIO21_ACT_LOW(1U)
18142 
18143 #define S_GPIO20_ACT_LOW    20
18144 #define V_GPIO20_ACT_LOW(x) ((x) << S_GPIO20_ACT_LOW)
18145 #define F_GPIO20_ACT_LOW    V_GPIO20_ACT_LOW(1U)
18146 
18147 #define S_T7_GPIO19_ACT_LOW    19
18148 #define V_T7_GPIO19_ACT_LOW(x) ((x) << S_T7_GPIO19_ACT_LOW)
18149 #define F_T7_GPIO19_ACT_LOW    V_T7_GPIO19_ACT_LOW(1U)
18150 
18151 #define S_T7_GPIO18_ACT_LOW    18
18152 #define V_T7_GPIO18_ACT_LOW(x) ((x) << S_T7_GPIO18_ACT_LOW)
18153 #define F_T7_GPIO18_ACT_LOW    V_T7_GPIO18_ACT_LOW(1U)
18154 
18155 #define S_T7_GPIO17_ACT_LOW    17
18156 #define V_T7_GPIO17_ACT_LOW(x) ((x) << S_T7_GPIO17_ACT_LOW)
18157 #define F_T7_GPIO17_ACT_LOW    V_T7_GPIO17_ACT_LOW(1U)
18158 
18159 #define S_T7_GPIO16_ACT_LOW    16
18160 #define V_T7_GPIO16_ACT_LOW(x) ((x) << S_T7_GPIO16_ACT_LOW)
18161 #define F_T7_GPIO16_ACT_LOW    V_T7_GPIO16_ACT_LOW(1U)
18162 
18163 #define A_DBG_CUST_EFUSE_BYTE44_47 0x618c
18164 #define A_DBG_DDR_CAL 0x618c
18165 
18166 #define S_CAL_ENDC    9
18167 #define V_CAL_ENDC(x) ((x) << S_CAL_ENDC)
18168 #define F_CAL_ENDC    V_CAL_ENDC(1U)
18169 
18170 #define S_CAL_MODE    8
18171 #define V_CAL_MODE(x) ((x) << S_CAL_MODE)
18172 #define F_CAL_MODE    V_CAL_MODE(1U)
18173 
18174 #define S_CAL_REFSEL    7
18175 #define V_CAL_REFSEL(x) ((x) << S_CAL_REFSEL)
18176 #define F_CAL_REFSEL    V_CAL_REFSEL(1U)
18177 
18178 #define S_PD    6
18179 #define V_PD(x) ((x) << S_PD)
18180 #define F_PD    V_PD(1U)
18181 
18182 #define S_CAL_RST    5
18183 #define V_CAL_RST(x) ((x) << S_CAL_RST)
18184 #define F_CAL_RST    V_CAL_RST(1U)
18185 
18186 #define S_CAL_READ    4
18187 #define V_CAL_READ(x) ((x) << S_CAL_READ)
18188 #define F_CAL_READ    V_CAL_READ(1U)
18189 
18190 #define S_CAL_SC    3
18191 #define V_CAL_SC(x) ((x) << S_CAL_SC)
18192 #define F_CAL_SC    V_CAL_SC(1U)
18193 
18194 #define S_CAL_LC    2
18195 #define V_CAL_LC(x) ((x) << S_CAL_LC)
18196 #define F_CAL_LC    V_CAL_LC(1U)
18197 
18198 #define S_CAL_CCAL    1
18199 #define V_CAL_CCAL(x) ((x) << S_CAL_CCAL)
18200 #define F_CAL_CCAL    V_CAL_CCAL(1U)
18201 
18202 #define S_CAL_RES    0
18203 #define V_CAL_RES(x) ((x) << S_CAL_RES)
18204 #define F_CAL_RES    V_CAL_RES(1U)
18205 
18206 #define A_DBG_CUST_EFUSE_BYTE48_51 0x6190
18207 #define A_DBG_EFUSE_CTL_0 0x6190
18208 
18209 #define S_EFUSE_CSB    31
18210 #define V_EFUSE_CSB(x) ((x) << S_EFUSE_CSB)
18211 #define F_EFUSE_CSB    V_EFUSE_CSB(1U)
18212 
18213 #define S_EFUSE_STROBE    30
18214 #define V_EFUSE_STROBE(x) ((x) << S_EFUSE_STROBE)
18215 #define F_EFUSE_STROBE    V_EFUSE_STROBE(1U)
18216 
18217 #define S_EFUSE_LOAD    29
18218 #define V_EFUSE_LOAD(x) ((x) << S_EFUSE_LOAD)
18219 #define F_EFUSE_LOAD    V_EFUSE_LOAD(1U)
18220 
18221 #define S_EFUSE_PGENB    28
18222 #define V_EFUSE_PGENB(x) ((x) << S_EFUSE_PGENB)
18223 #define F_EFUSE_PGENB    V_EFUSE_PGENB(1U)
18224 
18225 #define S_EFUSE_PS    27
18226 #define V_EFUSE_PS(x) ((x) << S_EFUSE_PS)
18227 #define F_EFUSE_PS    V_EFUSE_PS(1U)
18228 
18229 #define S_EFUSE_MR    26
18230 #define V_EFUSE_MR(x) ((x) << S_EFUSE_MR)
18231 #define F_EFUSE_MR    V_EFUSE_MR(1U)
18232 
18233 #define S_EFUSE_PD    25
18234 #define V_EFUSE_PD(x) ((x) << S_EFUSE_PD)
18235 #define F_EFUSE_PD    V_EFUSE_PD(1U)
18236 
18237 #define S_EFUSE_RWL    24
18238 #define V_EFUSE_RWL(x) ((x) << S_EFUSE_RWL)
18239 #define F_EFUSE_RWL    V_EFUSE_RWL(1U)
18240 
18241 #define S_EFUSE_RSB    23
18242 #define V_EFUSE_RSB(x) ((x) << S_EFUSE_RSB)
18243 #define F_EFUSE_RSB    V_EFUSE_RSB(1U)
18244 
18245 #define S_EFUSE_TRCS    22
18246 #define V_EFUSE_TRCS(x) ((x) << S_EFUSE_TRCS)
18247 #define F_EFUSE_TRCS    V_EFUSE_TRCS(1U)
18248 
18249 #define S_EFUSE_AT    20
18250 #define M_EFUSE_AT    0x3U
18251 #define V_EFUSE_AT(x) ((x) << S_EFUSE_AT)
18252 #define G_EFUSE_AT(x) (((x) >> S_EFUSE_AT) & M_EFUSE_AT)
18253 
18254 #define S_EFUSE_RD_STATE    16
18255 #define M_EFUSE_RD_STATE    0xfU
18256 #define V_EFUSE_RD_STATE(x) ((x) << S_EFUSE_RD_STATE)
18257 #define G_EFUSE_RD_STATE(x) (((x) >> S_EFUSE_RD_STATE) & M_EFUSE_RD_STATE)
18258 
18259 #define S_EFUSE_BUSY    15
18260 #define V_EFUSE_BUSY(x) ((x) << S_EFUSE_BUSY)
18261 #define F_EFUSE_BUSY    V_EFUSE_BUSY(1U)
18262 
18263 #define S_EFUSE_WR_RD    13
18264 #define M_EFUSE_WR_RD    0x3U
18265 #define V_EFUSE_WR_RD(x) ((x) << S_EFUSE_WR_RD)
18266 #define G_EFUSE_WR_RD(x) (((x) >> S_EFUSE_WR_RD) & M_EFUSE_WR_RD)
18267 
18268 #define S_EFUSE_A    0
18269 #define M_EFUSE_A    0x7ffU
18270 #define V_EFUSE_A(x) ((x) << S_EFUSE_A)
18271 #define G_EFUSE_A(x) (((x) >> S_EFUSE_A) & M_EFUSE_A)
18272 
18273 #define A_DBG_CUST_EFUSE_BYTE52_55 0x6194
18274 #define A_DBG_EFUSE_CTL_1 0x6194
18275 #define A_DBG_CUST_EFUSE_BYTE56_59 0x6198
18276 #define A_DBG_EFUSE_RD_CTL 0x6198
18277 
18278 #define S_EFUSE_RD_ID    6
18279 #define M_EFUSE_RD_ID    0x3U
18280 #define V_EFUSE_RD_ID(x) ((x) << S_EFUSE_RD_ID)
18281 #define G_EFUSE_RD_ID(x) (((x) >> S_EFUSE_RD_ID) & M_EFUSE_RD_ID)
18282 
18283 #define S_EFUSE_RD_ADDR    0
18284 #define M_EFUSE_RD_ADDR    0x3fU
18285 #define V_EFUSE_RD_ADDR(x) ((x) << S_EFUSE_RD_ADDR)
18286 #define G_EFUSE_RD_ADDR(x) (((x) >> S_EFUSE_RD_ADDR) & M_EFUSE_RD_ADDR)
18287 
18288 #define A_DBG_CUST_EFUSE_BYTE60_63 0x619c
18289 #define A_DBG_EFUSE_RD_DATA 0x619c
18290 #define A_DBG_EFUSE_TIME_0 0x61a0
18291 
18292 #define S_EFUSE_TIME_1    16
18293 #define M_EFUSE_TIME_1    0xffffU
18294 #define V_EFUSE_TIME_1(x) ((x) << S_EFUSE_TIME_1)
18295 #define G_EFUSE_TIME_1(x) (((x) >> S_EFUSE_TIME_1) & M_EFUSE_TIME_1)
18296 
18297 #define S_EFUSE_TIME_0    0
18298 #define M_EFUSE_TIME_0    0xffffU
18299 #define V_EFUSE_TIME_0(x) ((x) << S_EFUSE_TIME_0)
18300 #define G_EFUSE_TIME_0(x) (((x) >> S_EFUSE_TIME_0) & M_EFUSE_TIME_0)
18301 
18302 #define A_DBG_EFUSE_TIME_1 0x61a4
18303 
18304 #define S_EFUSE_TIME_3    16
18305 #define M_EFUSE_TIME_3    0xffffU
18306 #define V_EFUSE_TIME_3(x) ((x) << S_EFUSE_TIME_3)
18307 #define G_EFUSE_TIME_3(x) (((x) >> S_EFUSE_TIME_3) & M_EFUSE_TIME_3)
18308 
18309 #define S_EFUSE_TIME_2    0
18310 #define M_EFUSE_TIME_2    0xffffU
18311 #define V_EFUSE_TIME_2(x) ((x) << S_EFUSE_TIME_2)
18312 #define G_EFUSE_TIME_2(x) (((x) >> S_EFUSE_TIME_2) & M_EFUSE_TIME_2)
18313 
18314 #define A_DBG_EFUSE_TIME_2 0x61a8
18315 
18316 #define S_EFUSE_TIME_5    16
18317 #define M_EFUSE_TIME_5    0xffffU
18318 #define V_EFUSE_TIME_5(x) ((x) << S_EFUSE_TIME_5)
18319 #define G_EFUSE_TIME_5(x) (((x) >> S_EFUSE_TIME_5) & M_EFUSE_TIME_5)
18320 
18321 #define S_EFUSE_TIME_4    0
18322 #define M_EFUSE_TIME_4    0xffffU
18323 #define V_EFUSE_TIME_4(x) ((x) << S_EFUSE_TIME_4)
18324 #define G_EFUSE_TIME_4(x) (((x) >> S_EFUSE_TIME_4) & M_EFUSE_TIME_4)
18325 
18326 #define A_DBG_EFUSE_TIME_3 0x61ac
18327 
18328 #define S_EFUSE_TIME_7    16
18329 #define M_EFUSE_TIME_7    0xffffU
18330 #define V_EFUSE_TIME_7(x) ((x) << S_EFUSE_TIME_7)
18331 #define G_EFUSE_TIME_7(x) (((x) >> S_EFUSE_TIME_7) & M_EFUSE_TIME_7)
18332 
18333 #define S_EFUSE_TIME_6    0
18334 #define M_EFUSE_TIME_6    0xffffU
18335 #define V_EFUSE_TIME_6(x) ((x) << S_EFUSE_TIME_6)
18336 #define G_EFUSE_TIME_6(x) (((x) >> S_EFUSE_TIME_6) & M_EFUSE_TIME_6)
18337 
18338 #define A_DBG_VREF_CTL 0x61b0
18339 
18340 #define S_VREF_SEL_1    15
18341 #define V_VREF_SEL_1(x) ((x) << S_VREF_SEL_1)
18342 #define F_VREF_SEL_1    V_VREF_SEL_1(1U)
18343 
18344 #define S_VREF_R_1    8
18345 #define M_VREF_R_1    0x7fU
18346 #define V_VREF_R_1(x) ((x) << S_VREF_R_1)
18347 #define G_VREF_R_1(x) (((x) >> S_VREF_R_1) & M_VREF_R_1)
18348 
18349 #define S_VREF_SEL_0    7
18350 #define V_VREF_SEL_0(x) ((x) << S_VREF_SEL_0)
18351 #define F_VREF_SEL_0    V_VREF_SEL_0(1U)
18352 
18353 #define S_VREF_R_0    0
18354 #define M_VREF_R_0    0x7fU
18355 #define V_VREF_R_0(x) ((x) << S_VREF_R_0)
18356 #define G_VREF_R_0(x) (((x) >> S_VREF_R_0) & M_VREF_R_0)
18357 
18358 #define A_DBG_FPGA_EFUSE_CTL 0x61b4
18359 #define A_DBG_FPGA_EFUSE_DATA 0x61b8
18360 
18361 /* registers for module MC */
18362 #define MC_BASE_ADDR 0x6200
18363 
18364 #define A_MC_PCTL_SCFG 0x6200
18365 
18366 #define S_RKINF_EN    5
18367 #define V_RKINF_EN(x) ((x) << S_RKINF_EN)
18368 #define F_RKINF_EN    V_RKINF_EN(1U)
18369 
18370 #define S_DUAL_PCTL_EN    4
18371 #define V_DUAL_PCTL_EN(x) ((x) << S_DUAL_PCTL_EN)
18372 #define F_DUAL_PCTL_EN    V_DUAL_PCTL_EN(1U)
18373 
18374 #define S_SLAVE_MODE    3
18375 #define V_SLAVE_MODE(x) ((x) << S_SLAVE_MODE)
18376 #define F_SLAVE_MODE    V_SLAVE_MODE(1U)
18377 
18378 #define S_LOOPBACK_EN    1
18379 #define V_LOOPBACK_EN(x) ((x) << S_LOOPBACK_EN)
18380 #define F_LOOPBACK_EN    V_LOOPBACK_EN(1U)
18381 
18382 #define S_HW_LOW_POWER_EN    0
18383 #define V_HW_LOW_POWER_EN(x) ((x) << S_HW_LOW_POWER_EN)
18384 #define F_HW_LOW_POWER_EN    V_HW_LOW_POWER_EN(1U)
18385 
18386 #define A_MC_PCTL_SCTL 0x6204
18387 
18388 #define S_STATE_CMD    0
18389 #define M_STATE_CMD    0x7U
18390 #define V_STATE_CMD(x) ((x) << S_STATE_CMD)
18391 #define G_STATE_CMD(x) (((x) >> S_STATE_CMD) & M_STATE_CMD)
18392 
18393 #define A_MC_PCTL_STAT 0x6208
18394 
18395 #define S_CTL_STAT    0
18396 #define M_CTL_STAT    0x7U
18397 #define V_CTL_STAT(x) ((x) << S_CTL_STAT)
18398 #define G_CTL_STAT(x) (((x) >> S_CTL_STAT) & M_CTL_STAT)
18399 
18400 #define A_MC_PCTL_MCMD 0x6240
18401 
18402 #define S_START_CMD    31
18403 #define V_START_CMD(x) ((x) << S_START_CMD)
18404 #define F_START_CMD    V_START_CMD(1U)
18405 
18406 #define S_CMD_ADD_DEL    24
18407 #define M_CMD_ADD_DEL    0xfU
18408 #define V_CMD_ADD_DEL(x) ((x) << S_CMD_ADD_DEL)
18409 #define G_CMD_ADD_DEL(x) (((x) >> S_CMD_ADD_DEL) & M_CMD_ADD_DEL)
18410 
18411 #define S_RANK_SEL    20
18412 #define M_RANK_SEL    0xfU
18413 #define V_RANK_SEL(x) ((x) << S_RANK_SEL)
18414 #define G_RANK_SEL(x) (((x) >> S_RANK_SEL) & M_RANK_SEL)
18415 
18416 #define S_BANK_ADDR    17
18417 #define M_BANK_ADDR    0x7U
18418 #define V_BANK_ADDR(x) ((x) << S_BANK_ADDR)
18419 #define G_BANK_ADDR(x) (((x) >> S_BANK_ADDR) & M_BANK_ADDR)
18420 
18421 #define S_CMD_ADDR    4
18422 #define M_CMD_ADDR    0x1fffU
18423 #define V_CMD_ADDR(x) ((x) << S_CMD_ADDR)
18424 #define G_CMD_ADDR(x) (((x) >> S_CMD_ADDR) & M_CMD_ADDR)
18425 
18426 #define S_CMD_OPCODE    0
18427 #define M_CMD_OPCODE    0x7U
18428 #define V_CMD_OPCODE(x) ((x) << S_CMD_OPCODE)
18429 #define G_CMD_OPCODE(x) (((x) >> S_CMD_OPCODE) & M_CMD_OPCODE)
18430 
18431 #define A_MC_PCTL_POWCTL 0x6244
18432 
18433 #define S_POWER_UP_START    0
18434 #define V_POWER_UP_START(x) ((x) << S_POWER_UP_START)
18435 #define F_POWER_UP_START    V_POWER_UP_START(1U)
18436 
18437 #define A_MC_PCTL_POWSTAT 0x6248
18438 
18439 #define S_PHY_CALIBDONE    1
18440 #define V_PHY_CALIBDONE(x) ((x) << S_PHY_CALIBDONE)
18441 #define F_PHY_CALIBDONE    V_PHY_CALIBDONE(1U)
18442 
18443 #define S_POWER_UP_DONE    0
18444 #define V_POWER_UP_DONE(x) ((x) << S_POWER_UP_DONE)
18445 #define F_POWER_UP_DONE    V_POWER_UP_DONE(1U)
18446 
18447 #define A_MC_PCTL_MCFG 0x6280
18448 
18449 #define S_TFAW_CFG    18
18450 #define M_TFAW_CFG    0x3U
18451 #define V_TFAW_CFG(x) ((x) << S_TFAW_CFG)
18452 #define G_TFAW_CFG(x) (((x) >> S_TFAW_CFG) & M_TFAW_CFG)
18453 
18454 #define S_PD_EXIT_MODE    17
18455 #define V_PD_EXIT_MODE(x) ((x) << S_PD_EXIT_MODE)
18456 #define F_PD_EXIT_MODE    V_PD_EXIT_MODE(1U)
18457 
18458 #define S_PD_TYPE    16
18459 #define V_PD_TYPE(x) ((x) << S_PD_TYPE)
18460 #define F_PD_TYPE    V_PD_TYPE(1U)
18461 
18462 #define S_PD_IDLE    8
18463 #define M_PD_IDLE    0xffU
18464 #define V_PD_IDLE(x) ((x) << S_PD_IDLE)
18465 #define G_PD_IDLE(x) (((x) >> S_PD_IDLE) & M_PD_IDLE)
18466 
18467 #define S_PAGE_POLICY    6
18468 #define M_PAGE_POLICY    0x3U
18469 #define V_PAGE_POLICY(x) ((x) << S_PAGE_POLICY)
18470 #define G_PAGE_POLICY(x) (((x) >> S_PAGE_POLICY) & M_PAGE_POLICY)
18471 
18472 #define S_DDR3_EN    5
18473 #define V_DDR3_EN(x) ((x) << S_DDR3_EN)
18474 #define F_DDR3_EN    V_DDR3_EN(1U)
18475 
18476 #define S_TWO_T_EN    3
18477 #define V_TWO_T_EN(x) ((x) << S_TWO_T_EN)
18478 #define F_TWO_T_EN    V_TWO_T_EN(1U)
18479 
18480 #define S_BL8INT_EN    2
18481 #define V_BL8INT_EN(x) ((x) << S_BL8INT_EN)
18482 #define F_BL8INT_EN    V_BL8INT_EN(1U)
18483 
18484 #define S_MEM_BL    0
18485 #define V_MEM_BL(x) ((x) << S_MEM_BL)
18486 #define F_MEM_BL    V_MEM_BL(1U)
18487 
18488 #define A_MC_PCTL_PPCFG 0x6284
18489 
18490 #define S_RPMEM_DIS    1
18491 #define M_RPMEM_DIS    0xffU
18492 #define V_RPMEM_DIS(x) ((x) << S_RPMEM_DIS)
18493 #define G_RPMEM_DIS(x) (((x) >> S_RPMEM_DIS) & M_RPMEM_DIS)
18494 
18495 #define S_PPMEM_EN    0
18496 #define V_PPMEM_EN(x) ((x) << S_PPMEM_EN)
18497 #define F_PPMEM_EN    V_PPMEM_EN(1U)
18498 
18499 #define A_MC_PCTL_MSTAT 0x6288
18500 
18501 #define S_POWER_DOWN    0
18502 #define V_POWER_DOWN(x) ((x) << S_POWER_DOWN)
18503 #define F_POWER_DOWN    V_POWER_DOWN(1U)
18504 
18505 #define A_MC_PCTL_ODTCFG 0x628c
18506 
18507 #define S_RANK3_ODT_DEFAULT    28
18508 #define V_RANK3_ODT_DEFAULT(x) ((x) << S_RANK3_ODT_DEFAULT)
18509 #define F_RANK3_ODT_DEFAULT    V_RANK3_ODT_DEFAULT(1U)
18510 
18511 #define S_RANK3_ODT_WRITE_SEL    27
18512 #define V_RANK3_ODT_WRITE_SEL(x) ((x) << S_RANK3_ODT_WRITE_SEL)
18513 #define F_RANK3_ODT_WRITE_SEL    V_RANK3_ODT_WRITE_SEL(1U)
18514 
18515 #define S_RANK3_ODT_WRITE_NSE    26
18516 #define V_RANK3_ODT_WRITE_NSE(x) ((x) << S_RANK3_ODT_WRITE_NSE)
18517 #define F_RANK3_ODT_WRITE_NSE    V_RANK3_ODT_WRITE_NSE(1U)
18518 
18519 #define S_RANK3_ODT_READ_SEL    25
18520 #define V_RANK3_ODT_READ_SEL(x) ((x) << S_RANK3_ODT_READ_SEL)
18521 #define F_RANK3_ODT_READ_SEL    V_RANK3_ODT_READ_SEL(1U)
18522 
18523 #define S_RANK3_ODT_READ_NSEL    24
18524 #define V_RANK3_ODT_READ_NSEL(x) ((x) << S_RANK3_ODT_READ_NSEL)
18525 #define F_RANK3_ODT_READ_NSEL    V_RANK3_ODT_READ_NSEL(1U)
18526 
18527 #define S_RANK2_ODT_DEFAULT    20
18528 #define V_RANK2_ODT_DEFAULT(x) ((x) << S_RANK2_ODT_DEFAULT)
18529 #define F_RANK2_ODT_DEFAULT    V_RANK2_ODT_DEFAULT(1U)
18530 
18531 #define S_RANK2_ODT_WRITE_SEL    19
18532 #define V_RANK2_ODT_WRITE_SEL(x) ((x) << S_RANK2_ODT_WRITE_SEL)
18533 #define F_RANK2_ODT_WRITE_SEL    V_RANK2_ODT_WRITE_SEL(1U)
18534 
18535 #define S_RANK2_ODT_WRITE_NSEL    18
18536 #define V_RANK2_ODT_WRITE_NSEL(x) ((x) << S_RANK2_ODT_WRITE_NSEL)
18537 #define F_RANK2_ODT_WRITE_NSEL    V_RANK2_ODT_WRITE_NSEL(1U)
18538 
18539 #define S_RANK2_ODT_READ_SEL    17
18540 #define V_RANK2_ODT_READ_SEL(x) ((x) << S_RANK2_ODT_READ_SEL)
18541 #define F_RANK2_ODT_READ_SEL    V_RANK2_ODT_READ_SEL(1U)
18542 
18543 #define S_RANK2_ODT_READ_NSEL    16
18544 #define V_RANK2_ODT_READ_NSEL(x) ((x) << S_RANK2_ODT_READ_NSEL)
18545 #define F_RANK2_ODT_READ_NSEL    V_RANK2_ODT_READ_NSEL(1U)
18546 
18547 #define S_RANK1_ODT_DEFAULT    12
18548 #define V_RANK1_ODT_DEFAULT(x) ((x) << S_RANK1_ODT_DEFAULT)
18549 #define F_RANK1_ODT_DEFAULT    V_RANK1_ODT_DEFAULT(1U)
18550 
18551 #define S_RANK1_ODT_WRITE_SEL    11
18552 #define V_RANK1_ODT_WRITE_SEL(x) ((x) << S_RANK1_ODT_WRITE_SEL)
18553 #define F_RANK1_ODT_WRITE_SEL    V_RANK1_ODT_WRITE_SEL(1U)
18554 
18555 #define S_RANK1_ODT_WRITE_NSEL    10
18556 #define V_RANK1_ODT_WRITE_NSEL(x) ((x) << S_RANK1_ODT_WRITE_NSEL)
18557 #define F_RANK1_ODT_WRITE_NSEL    V_RANK1_ODT_WRITE_NSEL(1U)
18558 
18559 #define S_RANK1_ODT_READ_SEL    9
18560 #define V_RANK1_ODT_READ_SEL(x) ((x) << S_RANK1_ODT_READ_SEL)
18561 #define F_RANK1_ODT_READ_SEL    V_RANK1_ODT_READ_SEL(1U)
18562 
18563 #define S_RANK1_ODT_READ_NSEL    8
18564 #define V_RANK1_ODT_READ_NSEL(x) ((x) << S_RANK1_ODT_READ_NSEL)
18565 #define F_RANK1_ODT_READ_NSEL    V_RANK1_ODT_READ_NSEL(1U)
18566 
18567 #define S_RANK0_ODT_DEFAULT    4
18568 #define V_RANK0_ODT_DEFAULT(x) ((x) << S_RANK0_ODT_DEFAULT)
18569 #define F_RANK0_ODT_DEFAULT    V_RANK0_ODT_DEFAULT(1U)
18570 
18571 #define S_RANK0_ODT_WRITE_SEL    3
18572 #define V_RANK0_ODT_WRITE_SEL(x) ((x) << S_RANK0_ODT_WRITE_SEL)
18573 #define F_RANK0_ODT_WRITE_SEL    V_RANK0_ODT_WRITE_SEL(1U)
18574 
18575 #define S_RANK0_ODT_WRITE_NSEL    2
18576 #define V_RANK0_ODT_WRITE_NSEL(x) ((x) << S_RANK0_ODT_WRITE_NSEL)
18577 #define F_RANK0_ODT_WRITE_NSEL    V_RANK0_ODT_WRITE_NSEL(1U)
18578 
18579 #define S_RANK0_ODT_READ_SEL    1
18580 #define V_RANK0_ODT_READ_SEL(x) ((x) << S_RANK0_ODT_READ_SEL)
18581 #define F_RANK0_ODT_READ_SEL    V_RANK0_ODT_READ_SEL(1U)
18582 
18583 #define S_RANK0_ODT_READ_NSEL    0
18584 #define V_RANK0_ODT_READ_NSEL(x) ((x) << S_RANK0_ODT_READ_NSEL)
18585 #define F_RANK0_ODT_READ_NSEL    V_RANK0_ODT_READ_NSEL(1U)
18586 
18587 #define A_MC_PCTL_DQSECFG 0x6290
18588 
18589 #define S_DV_ALAT    20
18590 #define M_DV_ALAT    0xfU
18591 #define V_DV_ALAT(x) ((x) << S_DV_ALAT)
18592 #define G_DV_ALAT(x) (((x) >> S_DV_ALAT) & M_DV_ALAT)
18593 
18594 #define S_DV_ALEN    16
18595 #define M_DV_ALEN    0x3U
18596 #define V_DV_ALEN(x) ((x) << S_DV_ALEN)
18597 #define G_DV_ALEN(x) (((x) >> S_DV_ALEN) & M_DV_ALEN)
18598 
18599 #define S_DSE_ALAT    12
18600 #define M_DSE_ALAT    0xfU
18601 #define V_DSE_ALAT(x) ((x) << S_DSE_ALAT)
18602 #define G_DSE_ALAT(x) (((x) >> S_DSE_ALAT) & M_DSE_ALAT)
18603 
18604 #define S_DSE_ALEN    8
18605 #define M_DSE_ALEN    0x3U
18606 #define V_DSE_ALEN(x) ((x) << S_DSE_ALEN)
18607 #define G_DSE_ALEN(x) (((x) >> S_DSE_ALEN) & M_DSE_ALEN)
18608 
18609 #define S_QSE_ALAT    4
18610 #define M_QSE_ALAT    0xfU
18611 #define V_QSE_ALAT(x) ((x) << S_QSE_ALAT)
18612 #define G_QSE_ALAT(x) (((x) >> S_QSE_ALAT) & M_QSE_ALAT)
18613 
18614 #define S_QSE_ALEN    0
18615 #define M_QSE_ALEN    0x3U
18616 #define V_QSE_ALEN(x) ((x) << S_QSE_ALEN)
18617 #define G_QSE_ALEN(x) (((x) >> S_QSE_ALEN) & M_QSE_ALEN)
18618 
18619 #define A_MC_PCTL_DTUPDES 0x6294
18620 
18621 #define S_DTU_RD_MISSING    13
18622 #define V_DTU_RD_MISSING(x) ((x) << S_DTU_RD_MISSING)
18623 #define F_DTU_RD_MISSING    V_DTU_RD_MISSING(1U)
18624 
18625 #define S_DTU_EAFFL    9
18626 #define M_DTU_EAFFL    0xfU
18627 #define V_DTU_EAFFL(x) ((x) << S_DTU_EAFFL)
18628 #define G_DTU_EAFFL(x) (((x) >> S_DTU_EAFFL) & M_DTU_EAFFL)
18629 
18630 #define S_DTU_RANDOM_ERROR    8
18631 #define V_DTU_RANDOM_ERROR(x) ((x) << S_DTU_RANDOM_ERROR)
18632 #define F_DTU_RANDOM_ERROR    V_DTU_RANDOM_ERROR(1U)
18633 
18634 #define S_DTU_ERROR_B7    7
18635 #define V_DTU_ERROR_B7(x) ((x) << S_DTU_ERROR_B7)
18636 #define F_DTU_ERROR_B7    V_DTU_ERROR_B7(1U)
18637 
18638 #define S_DTU_ERR_B6    6
18639 #define V_DTU_ERR_B6(x) ((x) << S_DTU_ERR_B6)
18640 #define F_DTU_ERR_B6    V_DTU_ERR_B6(1U)
18641 
18642 #define S_DTU_ERR_B5    5
18643 #define V_DTU_ERR_B5(x) ((x) << S_DTU_ERR_B5)
18644 #define F_DTU_ERR_B5    V_DTU_ERR_B5(1U)
18645 
18646 #define S_DTU_ERR_B4    4
18647 #define V_DTU_ERR_B4(x) ((x) << S_DTU_ERR_B4)
18648 #define F_DTU_ERR_B4    V_DTU_ERR_B4(1U)
18649 
18650 #define S_DTU_ERR_B3    3
18651 #define V_DTU_ERR_B3(x) ((x) << S_DTU_ERR_B3)
18652 #define F_DTU_ERR_B3    V_DTU_ERR_B3(1U)
18653 
18654 #define S_DTU_ERR_B2    2
18655 #define V_DTU_ERR_B2(x) ((x) << S_DTU_ERR_B2)
18656 #define F_DTU_ERR_B2    V_DTU_ERR_B2(1U)
18657 
18658 #define S_DTU_ERR_B1    1
18659 #define V_DTU_ERR_B1(x) ((x) << S_DTU_ERR_B1)
18660 #define F_DTU_ERR_B1    V_DTU_ERR_B1(1U)
18661 
18662 #define S_DTU_ERR_B0    0
18663 #define V_DTU_ERR_B0(x) ((x) << S_DTU_ERR_B0)
18664 #define F_DTU_ERR_B0    V_DTU_ERR_B0(1U)
18665 
18666 #define A_MC_PCTL_DTUNA 0x6298
18667 #define A_MC_PCTL_DTUNE 0x629c
18668 #define A_MC_PCTL_DTUPRDO 0x62a0
18669 
18670 #define S_DTU_ALLBITS_1    16
18671 #define M_DTU_ALLBITS_1    0xffffU
18672 #define V_DTU_ALLBITS_1(x) ((x) << S_DTU_ALLBITS_1)
18673 #define G_DTU_ALLBITS_1(x) (((x) >> S_DTU_ALLBITS_1) & M_DTU_ALLBITS_1)
18674 
18675 #define S_DTU_ALLBITS_0    0
18676 #define M_DTU_ALLBITS_0    0xffffU
18677 #define V_DTU_ALLBITS_0(x) ((x) << S_DTU_ALLBITS_0)
18678 #define G_DTU_ALLBITS_0(x) (((x) >> S_DTU_ALLBITS_0) & M_DTU_ALLBITS_0)
18679 
18680 #define A_MC_PCTL_DTUPRD1 0x62a4
18681 
18682 #define S_DTU_ALLBITS_3    16
18683 #define M_DTU_ALLBITS_3    0xffffU
18684 #define V_DTU_ALLBITS_3(x) ((x) << S_DTU_ALLBITS_3)
18685 #define G_DTU_ALLBITS_3(x) (((x) >> S_DTU_ALLBITS_3) & M_DTU_ALLBITS_3)
18686 
18687 #define S_DTU_ALLBITS_2    0
18688 #define M_DTU_ALLBITS_2    0xffffU
18689 #define V_DTU_ALLBITS_2(x) ((x) << S_DTU_ALLBITS_2)
18690 #define G_DTU_ALLBITS_2(x) (((x) >> S_DTU_ALLBITS_2) & M_DTU_ALLBITS_2)
18691 
18692 #define A_MC_PCTL_DTUPRD2 0x62a8
18693 
18694 #define S_DTU_ALLBITS_5    16
18695 #define M_DTU_ALLBITS_5    0xffffU
18696 #define V_DTU_ALLBITS_5(x) ((x) << S_DTU_ALLBITS_5)
18697 #define G_DTU_ALLBITS_5(x) (((x) >> S_DTU_ALLBITS_5) & M_DTU_ALLBITS_5)
18698 
18699 #define S_DTU_ALLBITS_4    0
18700 #define M_DTU_ALLBITS_4    0xffffU
18701 #define V_DTU_ALLBITS_4(x) ((x) << S_DTU_ALLBITS_4)
18702 #define G_DTU_ALLBITS_4(x) (((x) >> S_DTU_ALLBITS_4) & M_DTU_ALLBITS_4)
18703 
18704 #define A_MC_PCTL_DTUPRD3 0x62ac
18705 
18706 #define S_DTU_ALLBITS_7    16
18707 #define M_DTU_ALLBITS_7    0xffffU
18708 #define V_DTU_ALLBITS_7(x) ((x) << S_DTU_ALLBITS_7)
18709 #define G_DTU_ALLBITS_7(x) (((x) >> S_DTU_ALLBITS_7) & M_DTU_ALLBITS_7)
18710 
18711 #define S_DTU_ALLBITS_6    0
18712 #define M_DTU_ALLBITS_6    0xffffU
18713 #define V_DTU_ALLBITS_6(x) ((x) << S_DTU_ALLBITS_6)
18714 #define G_DTU_ALLBITS_6(x) (((x) >> S_DTU_ALLBITS_6) & M_DTU_ALLBITS_6)
18715 
18716 #define A_MC_PCTL_DTUAWDT 0x62b0
18717 
18718 #define S_NUMBER_RANKS    9
18719 #define M_NUMBER_RANKS    0x3U
18720 #define V_NUMBER_RANKS(x) ((x) << S_NUMBER_RANKS)
18721 #define G_NUMBER_RANKS(x) (((x) >> S_NUMBER_RANKS) & M_NUMBER_RANKS)
18722 
18723 #define S_ROW_ADDR_WIDTH    6
18724 #define M_ROW_ADDR_WIDTH    0x3U
18725 #define V_ROW_ADDR_WIDTH(x) ((x) << S_ROW_ADDR_WIDTH)
18726 #define G_ROW_ADDR_WIDTH(x) (((x) >> S_ROW_ADDR_WIDTH) & M_ROW_ADDR_WIDTH)
18727 
18728 #define S_BANK_ADDR_WIDTH    3
18729 #define M_BANK_ADDR_WIDTH    0x3U
18730 #define V_BANK_ADDR_WIDTH(x) ((x) << S_BANK_ADDR_WIDTH)
18731 #define G_BANK_ADDR_WIDTH(x) (((x) >> S_BANK_ADDR_WIDTH) & M_BANK_ADDR_WIDTH)
18732 
18733 #define S_COLUMN_ADDR_WIDTH    0
18734 #define M_COLUMN_ADDR_WIDTH    0x3U
18735 #define V_COLUMN_ADDR_WIDTH(x) ((x) << S_COLUMN_ADDR_WIDTH)
18736 #define G_COLUMN_ADDR_WIDTH(x) (((x) >> S_COLUMN_ADDR_WIDTH) & M_COLUMN_ADDR_WIDTH)
18737 
18738 #define A_MC_PCTL_TOGCNT1U 0x62c0
18739 
18740 #define S_TOGGLE_COUNTER_1U    0
18741 #define M_TOGGLE_COUNTER_1U    0x3ffU
18742 #define V_TOGGLE_COUNTER_1U(x) ((x) << S_TOGGLE_COUNTER_1U)
18743 #define G_TOGGLE_COUNTER_1U(x) (((x) >> S_TOGGLE_COUNTER_1U) & M_TOGGLE_COUNTER_1U)
18744 
18745 #define A_MC_PCTL_TINIT 0x62c4
18746 
18747 #define S_T_INIT    0
18748 #define M_T_INIT    0x1ffU
18749 #define V_T_INIT(x) ((x) << S_T_INIT)
18750 #define G_T_INIT(x) (((x) >> S_T_INIT) & M_T_INIT)
18751 
18752 #define A_MC_PCTL_TRSTH 0x62c8
18753 
18754 #define S_T_RSTH    0
18755 #define M_T_RSTH    0x3ffU
18756 #define V_T_RSTH(x) ((x) << S_T_RSTH)
18757 #define G_T_RSTH(x) (((x) >> S_T_RSTH) & M_T_RSTH)
18758 
18759 #define A_MC_PCTL_TOGCNT100N 0x62cc
18760 
18761 #define S_TOGGLE_COUNTER_100N    0
18762 #define M_TOGGLE_COUNTER_100N    0x7fU
18763 #define V_TOGGLE_COUNTER_100N(x) ((x) << S_TOGGLE_COUNTER_100N)
18764 #define G_TOGGLE_COUNTER_100N(x) (((x) >> S_TOGGLE_COUNTER_100N) & M_TOGGLE_COUNTER_100N)
18765 
18766 #define A_MC_PCTL_TREFI 0x62d0
18767 
18768 #define S_T_REFI    0
18769 #define M_T_REFI    0xffU
18770 #define V_T_REFI(x) ((x) << S_T_REFI)
18771 #define G_T_REFI(x) (((x) >> S_T_REFI) & M_T_REFI)
18772 
18773 #define A_MC_PCTL_TMRD 0x62d4
18774 
18775 #define S_T_MRD    0
18776 #define M_T_MRD    0x7U
18777 #define V_T_MRD(x) ((x) << S_T_MRD)
18778 #define G_T_MRD(x) (((x) >> S_T_MRD) & M_T_MRD)
18779 
18780 #define A_MC_PCTL_TRFC 0x62d8
18781 
18782 #define S_T_RFC    0
18783 #define M_T_RFC    0xffU
18784 #define V_T_RFC(x) ((x) << S_T_RFC)
18785 #define G_T_RFC(x) (((x) >> S_T_RFC) & M_T_RFC)
18786 
18787 #define A_MC_PCTL_TRP 0x62dc
18788 
18789 #define S_T_RP    0
18790 #define M_T_RP    0xfU
18791 #define V_T_RP(x) ((x) << S_T_RP)
18792 #define G_T_RP(x) (((x) >> S_T_RP) & M_T_RP)
18793 
18794 #define A_MC_PCTL_TRTW 0x62e0
18795 
18796 #define S_T_RTW    0
18797 #define M_T_RTW    0x7U
18798 #define V_T_RTW(x) ((x) << S_T_RTW)
18799 #define G_T_RTW(x) (((x) >> S_T_RTW) & M_T_RTW)
18800 
18801 #define A_MC_PCTL_TAL 0x62e4
18802 
18803 #define S_T_AL    0
18804 #define M_T_AL    0xfU
18805 #define V_T_AL(x) ((x) << S_T_AL)
18806 #define G_T_AL(x) (((x) >> S_T_AL) & M_T_AL)
18807 
18808 #define A_MC_PCTL_TCL 0x62e8
18809 
18810 #define S_T_CL    0
18811 #define M_T_CL    0xfU
18812 #define V_T_CL(x) ((x) << S_T_CL)
18813 #define G_T_CL(x) (((x) >> S_T_CL) & M_T_CL)
18814 
18815 #define A_MC_PCTL_TCWL 0x62ec
18816 
18817 #define S_T_CWL    0
18818 #define M_T_CWL    0xfU
18819 #define V_T_CWL(x) ((x) << S_T_CWL)
18820 #define G_T_CWL(x) (((x) >> S_T_CWL) & M_T_CWL)
18821 
18822 #define A_MC_PCTL_TRAS 0x62f0
18823 
18824 #define S_T_RAS    0
18825 #define M_T_RAS    0x3fU
18826 #define V_T_RAS(x) ((x) << S_T_RAS)
18827 #define G_T_RAS(x) (((x) >> S_T_RAS) & M_T_RAS)
18828 
18829 #define A_MC_PCTL_TRC 0x62f4
18830 
18831 #define S_T_RC    0
18832 #define M_T_RC    0x3fU
18833 #define V_T_RC(x) ((x) << S_T_RC)
18834 #define G_T_RC(x) (((x) >> S_T_RC) & M_T_RC)
18835 
18836 #define A_MC_PCTL_TRCD 0x62f8
18837 
18838 #define S_T_RCD    0
18839 #define M_T_RCD    0xfU
18840 #define V_T_RCD(x) ((x) << S_T_RCD)
18841 #define G_T_RCD(x) (((x) >> S_T_RCD) & M_T_RCD)
18842 
18843 #define A_MC_PCTL_TRRD 0x62fc
18844 
18845 #define S_T_RRD    0
18846 #define M_T_RRD    0xfU
18847 #define V_T_RRD(x) ((x) << S_T_RRD)
18848 #define G_T_RRD(x) (((x) >> S_T_RRD) & M_T_RRD)
18849 
18850 #define A_MC_PCTL_TRTP 0x6300
18851 
18852 #define S_T_RTP    0
18853 #define M_T_RTP    0x7U
18854 #define V_T_RTP(x) ((x) << S_T_RTP)
18855 #define G_T_RTP(x) (((x) >> S_T_RTP) & M_T_RTP)
18856 
18857 #define A_MC_PCTL_TWR 0x6304
18858 
18859 #define S_T_WR    0
18860 #define M_T_WR    0x7U
18861 #define V_T_WR(x) ((x) << S_T_WR)
18862 #define G_T_WR(x) (((x) >> S_T_WR) & M_T_WR)
18863 
18864 #define A_MC_PCTL_TWTR 0x6308
18865 
18866 #define S_T_WTR    0
18867 #define M_T_WTR    0x7U
18868 #define V_T_WTR(x) ((x) << S_T_WTR)
18869 #define G_T_WTR(x) (((x) >> S_T_WTR) & M_T_WTR)
18870 
18871 #define A_MC_PCTL_TEXSR 0x630c
18872 
18873 #define S_T_EXSR    0
18874 #define M_T_EXSR    0x3ffU
18875 #define V_T_EXSR(x) ((x) << S_T_EXSR)
18876 #define G_T_EXSR(x) (((x) >> S_T_EXSR) & M_T_EXSR)
18877 
18878 #define A_MC_PCTL_TXP 0x6310
18879 
18880 #define S_T_XP    0
18881 #define M_T_XP    0x7U
18882 #define V_T_XP(x) ((x) << S_T_XP)
18883 #define G_T_XP(x) (((x) >> S_T_XP) & M_T_XP)
18884 
18885 #define A_MC_PCTL_TXPDLL 0x6314
18886 
18887 #define S_T_XPDLL    0
18888 #define M_T_XPDLL    0x3fU
18889 #define V_T_XPDLL(x) ((x) << S_T_XPDLL)
18890 #define G_T_XPDLL(x) (((x) >> S_T_XPDLL) & M_T_XPDLL)
18891 
18892 #define A_MC_PCTL_TZQCS 0x6318
18893 
18894 #define S_T_ZQCS    0
18895 #define M_T_ZQCS    0x7fU
18896 #define V_T_ZQCS(x) ((x) << S_T_ZQCS)
18897 #define G_T_ZQCS(x) (((x) >> S_T_ZQCS) & M_T_ZQCS)
18898 
18899 #define A_MC_PCTL_TZQCSI 0x631c
18900 
18901 #define S_T_ZQCSI    0
18902 #define M_T_ZQCSI    0xfffU
18903 #define V_T_ZQCSI(x) ((x) << S_T_ZQCSI)
18904 #define G_T_ZQCSI(x) (((x) >> S_T_ZQCSI) & M_T_ZQCSI)
18905 
18906 #define A_MC_PCTL_TDQS 0x6320
18907 
18908 #define S_T_DQS    0
18909 #define M_T_DQS    0x7U
18910 #define V_T_DQS(x) ((x) << S_T_DQS)
18911 #define G_T_DQS(x) (((x) >> S_T_DQS) & M_T_DQS)
18912 
18913 #define A_MC_PCTL_TCKSRE 0x6324
18914 
18915 #define S_T_CKSRE    0
18916 #define M_T_CKSRE    0xfU
18917 #define V_T_CKSRE(x) ((x) << S_T_CKSRE)
18918 #define G_T_CKSRE(x) (((x) >> S_T_CKSRE) & M_T_CKSRE)
18919 
18920 #define A_MC_PCTL_TCKSRX 0x6328
18921 
18922 #define S_T_CKSRX    0
18923 #define M_T_CKSRX    0xfU
18924 #define V_T_CKSRX(x) ((x) << S_T_CKSRX)
18925 #define G_T_CKSRX(x) (((x) >> S_T_CKSRX) & M_T_CKSRX)
18926 
18927 #define A_MC_PCTL_TCKE 0x632c
18928 
18929 #define S_T_CKE    0
18930 #define M_T_CKE    0x7U
18931 #define V_T_CKE(x) ((x) << S_T_CKE)
18932 #define G_T_CKE(x) (((x) >> S_T_CKE) & M_T_CKE)
18933 
18934 #define A_MC_PCTL_TMOD 0x6330
18935 
18936 #define S_T_MOD    0
18937 #define M_T_MOD    0xfU
18938 #define V_T_MOD(x) ((x) << S_T_MOD)
18939 #define G_T_MOD(x) (((x) >> S_T_MOD) & M_T_MOD)
18940 
18941 #define A_MC_PCTL_TRSTL 0x6334
18942 
18943 #define S_RSTHOLD    0
18944 #define M_RSTHOLD    0x7fU
18945 #define V_RSTHOLD(x) ((x) << S_RSTHOLD)
18946 #define G_RSTHOLD(x) (((x) >> S_RSTHOLD) & M_RSTHOLD)
18947 
18948 #define A_MC_PCTL_TZQCL 0x6338
18949 
18950 #define S_T_ZQCL    0
18951 #define M_T_ZQCL    0x3ffU
18952 #define V_T_ZQCL(x) ((x) << S_T_ZQCL)
18953 #define G_T_ZQCL(x) (((x) >> S_T_ZQCL) & M_T_ZQCL)
18954 
18955 #define A_MC_PCTL_DWLCFG0 0x6370
18956 
18957 #define S_T_ADWL_VEC    0
18958 #define M_T_ADWL_VEC    0x1ffU
18959 #define V_T_ADWL_VEC(x) ((x) << S_T_ADWL_VEC)
18960 #define G_T_ADWL_VEC(x) (((x) >> S_T_ADWL_VEC) & M_T_ADWL_VEC)
18961 
18962 #define A_MC_PCTL_DWLCFG1 0x6374
18963 #define A_MC_PCTL_DWLCFG2 0x6378
18964 #define A_MC_PCTL_DWLCFG3 0x637c
18965 #define A_MC_PCTL_ECCCFG 0x6380
18966 
18967 #define S_INLINE_SYN_EN    4
18968 #define V_INLINE_SYN_EN(x) ((x) << S_INLINE_SYN_EN)
18969 #define F_INLINE_SYN_EN    V_INLINE_SYN_EN(1U)
18970 
18971 #define S_ECC_EN    3
18972 #define V_ECC_EN(x) ((x) << S_ECC_EN)
18973 #define F_ECC_EN    V_ECC_EN(1U)
18974 
18975 #define S_ECC_INTR_EN    2
18976 #define V_ECC_INTR_EN(x) ((x) << S_ECC_INTR_EN)
18977 #define F_ECC_INTR_EN    V_ECC_INTR_EN(1U)
18978 
18979 #define A_MC_PCTL_ECCTST 0x6384
18980 
18981 #define S_ECC_TEST_MASK    0
18982 #define M_ECC_TEST_MASK    0xffU
18983 #define V_ECC_TEST_MASK(x) ((x) << S_ECC_TEST_MASK)
18984 #define G_ECC_TEST_MASK(x) (((x) >> S_ECC_TEST_MASK) & M_ECC_TEST_MASK)
18985 
18986 #define A_MC_PCTL_ECCCLR 0x6388
18987 
18988 #define S_CLR_ECC_LOG    1
18989 #define V_CLR_ECC_LOG(x) ((x) << S_CLR_ECC_LOG)
18990 #define F_CLR_ECC_LOG    V_CLR_ECC_LOG(1U)
18991 
18992 #define S_CLR_ECC_INTR    0
18993 #define V_CLR_ECC_INTR(x) ((x) << S_CLR_ECC_INTR)
18994 #define F_CLR_ECC_INTR    V_CLR_ECC_INTR(1U)
18995 
18996 #define A_MC_PCTL_ECCLOG 0x638c
18997 #define A_MC_PCTL_DTUWACTL 0x6400
18998 
18999 #define S_DTU_WR_RANK    30
19000 #define M_DTU_WR_RANK    0x3U
19001 #define V_DTU_WR_RANK(x) ((x) << S_DTU_WR_RANK)
19002 #define G_DTU_WR_RANK(x) (((x) >> S_DTU_WR_RANK) & M_DTU_WR_RANK)
19003 
19004 #define S_DTU_WR_ROW    13
19005 #define M_DTU_WR_ROW    0x1ffffU
19006 #define V_DTU_WR_ROW(x) ((x) << S_DTU_WR_ROW)
19007 #define G_DTU_WR_ROW(x) (((x) >> S_DTU_WR_ROW) & M_DTU_WR_ROW)
19008 
19009 #define S_DTU_WR_BANK    10
19010 #define M_DTU_WR_BANK    0x7U
19011 #define V_DTU_WR_BANK(x) ((x) << S_DTU_WR_BANK)
19012 #define G_DTU_WR_BANK(x) (((x) >> S_DTU_WR_BANK) & M_DTU_WR_BANK)
19013 
19014 #define S_DTU_WR_COL    0
19015 #define M_DTU_WR_COL    0x3ffU
19016 #define V_DTU_WR_COL(x) ((x) << S_DTU_WR_COL)
19017 #define G_DTU_WR_COL(x) (((x) >> S_DTU_WR_COL) & M_DTU_WR_COL)
19018 
19019 #define A_MC_PCTL_DTURACTL 0x6404
19020 
19021 #define S_DTU_RD_RANK    30
19022 #define M_DTU_RD_RANK    0x3U
19023 #define V_DTU_RD_RANK(x) ((x) << S_DTU_RD_RANK)
19024 #define G_DTU_RD_RANK(x) (((x) >> S_DTU_RD_RANK) & M_DTU_RD_RANK)
19025 
19026 #define S_DTU_RD_ROW    13
19027 #define M_DTU_RD_ROW    0x1ffffU
19028 #define V_DTU_RD_ROW(x) ((x) << S_DTU_RD_ROW)
19029 #define G_DTU_RD_ROW(x) (((x) >> S_DTU_RD_ROW) & M_DTU_RD_ROW)
19030 
19031 #define S_DTU_RD_BANK    10
19032 #define M_DTU_RD_BANK    0x7U
19033 #define V_DTU_RD_BANK(x) ((x) << S_DTU_RD_BANK)
19034 #define G_DTU_RD_BANK(x) (((x) >> S_DTU_RD_BANK) & M_DTU_RD_BANK)
19035 
19036 #define S_DTU_RD_COL    0
19037 #define M_DTU_RD_COL    0x3ffU
19038 #define V_DTU_RD_COL(x) ((x) << S_DTU_RD_COL)
19039 #define G_DTU_RD_COL(x) (((x) >> S_DTU_RD_COL) & M_DTU_RD_COL)
19040 
19041 #define A_MC_PCTL_DTUCFG 0x6408
19042 
19043 #define S_DTU_ROW_INCREMENTS    16
19044 #define M_DTU_ROW_INCREMENTS    0x7fU
19045 #define V_DTU_ROW_INCREMENTS(x) ((x) << S_DTU_ROW_INCREMENTS)
19046 #define G_DTU_ROW_INCREMENTS(x) (((x) >> S_DTU_ROW_INCREMENTS) & M_DTU_ROW_INCREMENTS)
19047 
19048 #define S_DTU_WR_MULTI_RD    15
19049 #define V_DTU_WR_MULTI_RD(x) ((x) << S_DTU_WR_MULTI_RD)
19050 #define F_DTU_WR_MULTI_RD    V_DTU_WR_MULTI_RD(1U)
19051 
19052 #define S_DTU_DATA_MASK_EN    14
19053 #define V_DTU_DATA_MASK_EN(x) ((x) << S_DTU_DATA_MASK_EN)
19054 #define F_DTU_DATA_MASK_EN    V_DTU_DATA_MASK_EN(1U)
19055 
19056 #define S_DTU_TARGET_LANE    10
19057 #define M_DTU_TARGET_LANE    0xfU
19058 #define V_DTU_TARGET_LANE(x) ((x) << S_DTU_TARGET_LANE)
19059 #define G_DTU_TARGET_LANE(x) (((x) >> S_DTU_TARGET_LANE) & M_DTU_TARGET_LANE)
19060 
19061 #define S_DTU_GENERATE_RANDOM    9
19062 #define V_DTU_GENERATE_RANDOM(x) ((x) << S_DTU_GENERATE_RANDOM)
19063 #define F_DTU_GENERATE_RANDOM    V_DTU_GENERATE_RANDOM(1U)
19064 
19065 #define S_DTU_INCR_BANKS    8
19066 #define V_DTU_INCR_BANKS(x) ((x) << S_DTU_INCR_BANKS)
19067 #define F_DTU_INCR_BANKS    V_DTU_INCR_BANKS(1U)
19068 
19069 #define S_DTU_INCR_COLS    7
19070 #define V_DTU_INCR_COLS(x) ((x) << S_DTU_INCR_COLS)
19071 #define F_DTU_INCR_COLS    V_DTU_INCR_COLS(1U)
19072 
19073 #define S_DTU_NALEN    1
19074 #define M_DTU_NALEN    0x3fU
19075 #define V_DTU_NALEN(x) ((x) << S_DTU_NALEN)
19076 #define G_DTU_NALEN(x) (((x) >> S_DTU_NALEN) & M_DTU_NALEN)
19077 
19078 #define S_DTU_ENABLE    0
19079 #define V_DTU_ENABLE(x) ((x) << S_DTU_ENABLE)
19080 #define F_DTU_ENABLE    V_DTU_ENABLE(1U)
19081 
19082 #define A_MC_PCTL_DTUECTL 0x640c
19083 
19084 #define S_WR_MULTI_RD_RST    2
19085 #define V_WR_MULTI_RD_RST(x) ((x) << S_WR_MULTI_RD_RST)
19086 #define F_WR_MULTI_RD_RST    V_WR_MULTI_RD_RST(1U)
19087 
19088 #define S_RUN_ERROR_REPORTS    1
19089 #define V_RUN_ERROR_REPORTS(x) ((x) << S_RUN_ERROR_REPORTS)
19090 #define F_RUN_ERROR_REPORTS    V_RUN_ERROR_REPORTS(1U)
19091 
19092 #define S_RUN_DTU    0
19093 #define V_RUN_DTU(x) ((x) << S_RUN_DTU)
19094 #define F_RUN_DTU    V_RUN_DTU(1U)
19095 
19096 #define A_MC_PCTL_DTUWD0 0x6410
19097 
19098 #define S_DTU_WR_BYTE3    24
19099 #define M_DTU_WR_BYTE3    0xffU
19100 #define V_DTU_WR_BYTE3(x) ((x) << S_DTU_WR_BYTE3)
19101 #define G_DTU_WR_BYTE3(x) (((x) >> S_DTU_WR_BYTE3) & M_DTU_WR_BYTE3)
19102 
19103 #define S_DTU_WR_BYTE2    16
19104 #define M_DTU_WR_BYTE2    0xffU
19105 #define V_DTU_WR_BYTE2(x) ((x) << S_DTU_WR_BYTE2)
19106 #define G_DTU_WR_BYTE2(x) (((x) >> S_DTU_WR_BYTE2) & M_DTU_WR_BYTE2)
19107 
19108 #define S_DTU_WR_BYTE1    8
19109 #define M_DTU_WR_BYTE1    0xffU
19110 #define V_DTU_WR_BYTE1(x) ((x) << S_DTU_WR_BYTE1)
19111 #define G_DTU_WR_BYTE1(x) (((x) >> S_DTU_WR_BYTE1) & M_DTU_WR_BYTE1)
19112 
19113 #define S_DTU_WR_BYTE0    0
19114 #define M_DTU_WR_BYTE0    0xffU
19115 #define V_DTU_WR_BYTE0(x) ((x) << S_DTU_WR_BYTE0)
19116 #define G_DTU_WR_BYTE0(x) (((x) >> S_DTU_WR_BYTE0) & M_DTU_WR_BYTE0)
19117 
19118 #define A_MC_PCTL_DTUWD1 0x6414
19119 
19120 #define S_DTU_WR_BYTE7    24
19121 #define M_DTU_WR_BYTE7    0xffU
19122 #define V_DTU_WR_BYTE7(x) ((x) << S_DTU_WR_BYTE7)
19123 #define G_DTU_WR_BYTE7(x) (((x) >> S_DTU_WR_BYTE7) & M_DTU_WR_BYTE7)
19124 
19125 #define S_DTU_WR_BYTE6    16
19126 #define M_DTU_WR_BYTE6    0xffU
19127 #define V_DTU_WR_BYTE6(x) ((x) << S_DTU_WR_BYTE6)
19128 #define G_DTU_WR_BYTE6(x) (((x) >> S_DTU_WR_BYTE6) & M_DTU_WR_BYTE6)
19129 
19130 #define S_DTU_WR_BYTE5    8
19131 #define M_DTU_WR_BYTE5    0xffU
19132 #define V_DTU_WR_BYTE5(x) ((x) << S_DTU_WR_BYTE5)
19133 #define G_DTU_WR_BYTE5(x) (((x) >> S_DTU_WR_BYTE5) & M_DTU_WR_BYTE5)
19134 
19135 #define S_DTU_WR_BYTE4    0
19136 #define M_DTU_WR_BYTE4    0xffU
19137 #define V_DTU_WR_BYTE4(x) ((x) << S_DTU_WR_BYTE4)
19138 #define G_DTU_WR_BYTE4(x) (((x) >> S_DTU_WR_BYTE4) & M_DTU_WR_BYTE4)
19139 
19140 #define A_MC_PCTL_DTUWD2 0x6418
19141 
19142 #define S_DTU_WR_BYTE11    24
19143 #define M_DTU_WR_BYTE11    0xffU
19144 #define V_DTU_WR_BYTE11(x) ((x) << S_DTU_WR_BYTE11)
19145 #define G_DTU_WR_BYTE11(x) (((x) >> S_DTU_WR_BYTE11) & M_DTU_WR_BYTE11)
19146 
19147 #define S_DTU_WR_BYTE10    16
19148 #define M_DTU_WR_BYTE10    0xffU
19149 #define V_DTU_WR_BYTE10(x) ((x) << S_DTU_WR_BYTE10)
19150 #define G_DTU_WR_BYTE10(x) (((x) >> S_DTU_WR_BYTE10) & M_DTU_WR_BYTE10)
19151 
19152 #define S_DTU_WR_BYTE9    8
19153 #define M_DTU_WR_BYTE9    0xffU
19154 #define V_DTU_WR_BYTE9(x) ((x) << S_DTU_WR_BYTE9)
19155 #define G_DTU_WR_BYTE9(x) (((x) >> S_DTU_WR_BYTE9) & M_DTU_WR_BYTE9)
19156 
19157 #define S_DTU_WR_BYTE8    0
19158 #define M_DTU_WR_BYTE8    0xffU
19159 #define V_DTU_WR_BYTE8(x) ((x) << S_DTU_WR_BYTE8)
19160 #define G_DTU_WR_BYTE8(x) (((x) >> S_DTU_WR_BYTE8) & M_DTU_WR_BYTE8)
19161 
19162 #define A_MC_PCTL_DTUWD3 0x641c
19163 
19164 #define S_DTU_WR_BYTE15    24
19165 #define M_DTU_WR_BYTE15    0xffU
19166 #define V_DTU_WR_BYTE15(x) ((x) << S_DTU_WR_BYTE15)
19167 #define G_DTU_WR_BYTE15(x) (((x) >> S_DTU_WR_BYTE15) & M_DTU_WR_BYTE15)
19168 
19169 #define S_DTU_WR_BYTE14    16
19170 #define M_DTU_WR_BYTE14    0xffU
19171 #define V_DTU_WR_BYTE14(x) ((x) << S_DTU_WR_BYTE14)
19172 #define G_DTU_WR_BYTE14(x) (((x) >> S_DTU_WR_BYTE14) & M_DTU_WR_BYTE14)
19173 
19174 #define S_DTU_WR_BYTE13    8
19175 #define M_DTU_WR_BYTE13    0xffU
19176 #define V_DTU_WR_BYTE13(x) ((x) << S_DTU_WR_BYTE13)
19177 #define G_DTU_WR_BYTE13(x) (((x) >> S_DTU_WR_BYTE13) & M_DTU_WR_BYTE13)
19178 
19179 #define S_DTU_WR_BYTE12    0
19180 #define M_DTU_WR_BYTE12    0xffU
19181 #define V_DTU_WR_BYTE12(x) ((x) << S_DTU_WR_BYTE12)
19182 #define G_DTU_WR_BYTE12(x) (((x) >> S_DTU_WR_BYTE12) & M_DTU_WR_BYTE12)
19183 
19184 #define A_MC_PCTL_DTUWDM 0x6420
19185 
19186 #define S_DM_WR_BYTE0    0
19187 #define M_DM_WR_BYTE0    0xffffU
19188 #define V_DM_WR_BYTE0(x) ((x) << S_DM_WR_BYTE0)
19189 #define G_DM_WR_BYTE0(x) (((x) >> S_DM_WR_BYTE0) & M_DM_WR_BYTE0)
19190 
19191 #define A_MC_PCTL_DTURD0 0x6424
19192 
19193 #define S_DTU_RD_BYTE3    24
19194 #define M_DTU_RD_BYTE3    0xffU
19195 #define V_DTU_RD_BYTE3(x) ((x) << S_DTU_RD_BYTE3)
19196 #define G_DTU_RD_BYTE3(x) (((x) >> S_DTU_RD_BYTE3) & M_DTU_RD_BYTE3)
19197 
19198 #define S_DTU_RD_BYTE2    16
19199 #define M_DTU_RD_BYTE2    0xffU
19200 #define V_DTU_RD_BYTE2(x) ((x) << S_DTU_RD_BYTE2)
19201 #define G_DTU_RD_BYTE2(x) (((x) >> S_DTU_RD_BYTE2) & M_DTU_RD_BYTE2)
19202 
19203 #define S_DTU_RD_BYTE1    8
19204 #define M_DTU_RD_BYTE1    0xffU
19205 #define V_DTU_RD_BYTE1(x) ((x) << S_DTU_RD_BYTE1)
19206 #define G_DTU_RD_BYTE1(x) (((x) >> S_DTU_RD_BYTE1) & M_DTU_RD_BYTE1)
19207 
19208 #define S_DTU_RD_BYTE0    0
19209 #define M_DTU_RD_BYTE0    0xffU
19210 #define V_DTU_RD_BYTE0(x) ((x) << S_DTU_RD_BYTE0)
19211 #define G_DTU_RD_BYTE0(x) (((x) >> S_DTU_RD_BYTE0) & M_DTU_RD_BYTE0)
19212 
19213 #define A_MC_PCTL_DTURD1 0x6428
19214 
19215 #define S_DTU_RD_BYTE7    24
19216 #define M_DTU_RD_BYTE7    0xffU
19217 #define V_DTU_RD_BYTE7(x) ((x) << S_DTU_RD_BYTE7)
19218 #define G_DTU_RD_BYTE7(x) (((x) >> S_DTU_RD_BYTE7) & M_DTU_RD_BYTE7)
19219 
19220 #define S_DTU_RD_BYTE6    16
19221 #define M_DTU_RD_BYTE6    0xffU
19222 #define V_DTU_RD_BYTE6(x) ((x) << S_DTU_RD_BYTE6)
19223 #define G_DTU_RD_BYTE6(x) (((x) >> S_DTU_RD_BYTE6) & M_DTU_RD_BYTE6)
19224 
19225 #define S_DTU_RD_BYTE5    8
19226 #define M_DTU_RD_BYTE5    0xffU
19227 #define V_DTU_RD_BYTE5(x) ((x) << S_DTU_RD_BYTE5)
19228 #define G_DTU_RD_BYTE5(x) (((x) >> S_DTU_RD_BYTE5) & M_DTU_RD_BYTE5)
19229 
19230 #define S_DTU_RD_BYTE4    0
19231 #define M_DTU_RD_BYTE4    0xffU
19232 #define V_DTU_RD_BYTE4(x) ((x) << S_DTU_RD_BYTE4)
19233 #define G_DTU_RD_BYTE4(x) (((x) >> S_DTU_RD_BYTE4) & M_DTU_RD_BYTE4)
19234 
19235 #define A_MC_PCTL_DTURD2 0x642c
19236 
19237 #define S_DTU_RD_BYTE11    24
19238 #define M_DTU_RD_BYTE11    0xffU
19239 #define V_DTU_RD_BYTE11(x) ((x) << S_DTU_RD_BYTE11)
19240 #define G_DTU_RD_BYTE11(x) (((x) >> S_DTU_RD_BYTE11) & M_DTU_RD_BYTE11)
19241 
19242 #define S_DTU_RD_BYTE10    16
19243 #define M_DTU_RD_BYTE10    0xffU
19244 #define V_DTU_RD_BYTE10(x) ((x) << S_DTU_RD_BYTE10)
19245 #define G_DTU_RD_BYTE10(x) (((x) >> S_DTU_RD_BYTE10) & M_DTU_RD_BYTE10)
19246 
19247 #define S_DTU_RD_BYTE9    8
19248 #define M_DTU_RD_BYTE9    0xffU
19249 #define V_DTU_RD_BYTE9(x) ((x) << S_DTU_RD_BYTE9)
19250 #define G_DTU_RD_BYTE9(x) (((x) >> S_DTU_RD_BYTE9) & M_DTU_RD_BYTE9)
19251 
19252 #define S_DTU_RD_BYTE8    0
19253 #define M_DTU_RD_BYTE8    0xffU
19254 #define V_DTU_RD_BYTE8(x) ((x) << S_DTU_RD_BYTE8)
19255 #define G_DTU_RD_BYTE8(x) (((x) >> S_DTU_RD_BYTE8) & M_DTU_RD_BYTE8)
19256 
19257 #define A_MC_PCTL_DTURD3 0x6430
19258 
19259 #define S_DTU_RD_BYTE15    24
19260 #define M_DTU_RD_BYTE15    0xffU
19261 #define V_DTU_RD_BYTE15(x) ((x) << S_DTU_RD_BYTE15)
19262 #define G_DTU_RD_BYTE15(x) (((x) >> S_DTU_RD_BYTE15) & M_DTU_RD_BYTE15)
19263 
19264 #define S_DTU_RD_BYTE14    16
19265 #define M_DTU_RD_BYTE14    0xffU
19266 #define V_DTU_RD_BYTE14(x) ((x) << S_DTU_RD_BYTE14)
19267 #define G_DTU_RD_BYTE14(x) (((x) >> S_DTU_RD_BYTE14) & M_DTU_RD_BYTE14)
19268 
19269 #define S_DTU_RD_BYTE13    8
19270 #define M_DTU_RD_BYTE13    0xffU
19271 #define V_DTU_RD_BYTE13(x) ((x) << S_DTU_RD_BYTE13)
19272 #define G_DTU_RD_BYTE13(x) (((x) >> S_DTU_RD_BYTE13) & M_DTU_RD_BYTE13)
19273 
19274 #define S_DTU_RD_BYTE12    0
19275 #define M_DTU_RD_BYTE12    0xffU
19276 #define V_DTU_RD_BYTE12(x) ((x) << S_DTU_RD_BYTE12)
19277 #define G_DTU_RD_BYTE12(x) (((x) >> S_DTU_RD_BYTE12) & M_DTU_RD_BYTE12)
19278 
19279 #define A_MC_DTULFSRWD 0x6434
19280 #define A_MC_PCTL_DTULFSRRD 0x6438
19281 #define A_MC_PCTL_DTUEAF 0x643c
19282 
19283 #define S_EA_RANK    30
19284 #define M_EA_RANK    0x3U
19285 #define V_EA_RANK(x) ((x) << S_EA_RANK)
19286 #define G_EA_RANK(x) (((x) >> S_EA_RANK) & M_EA_RANK)
19287 
19288 #define S_EA_ROW    13
19289 #define M_EA_ROW    0x1ffffU
19290 #define V_EA_ROW(x) ((x) << S_EA_ROW)
19291 #define G_EA_ROW(x) (((x) >> S_EA_ROW) & M_EA_ROW)
19292 
19293 #define S_EA_BANK    10
19294 #define M_EA_BANK    0x7U
19295 #define V_EA_BANK(x) ((x) << S_EA_BANK)
19296 #define G_EA_BANK(x) (((x) >> S_EA_BANK) & M_EA_BANK)
19297 
19298 #define S_EA_COLUMN    0
19299 #define M_EA_COLUMN    0x3ffU
19300 #define V_EA_COLUMN(x) ((x) << S_EA_COLUMN)
19301 #define G_EA_COLUMN(x) (((x) >> S_EA_COLUMN) & M_EA_COLUMN)
19302 
19303 #define A_MC_PCTL_PHYPVTCFG 0x6500
19304 
19305 #define S_PVT_UPD_REQ_EN    15
19306 #define V_PVT_UPD_REQ_EN(x) ((x) << S_PVT_UPD_REQ_EN)
19307 #define F_PVT_UPD_REQ_EN    V_PVT_UPD_REQ_EN(1U)
19308 
19309 #define S_PVT_UPD_TRIG_POL    14
19310 #define V_PVT_UPD_TRIG_POL(x) ((x) << S_PVT_UPD_TRIG_POL)
19311 #define F_PVT_UPD_TRIG_POL    V_PVT_UPD_TRIG_POL(1U)
19312 
19313 #define S_PVT_UPD_TRIG_TYPE    12
19314 #define V_PVT_UPD_TRIG_TYPE(x) ((x) << S_PVT_UPD_TRIG_TYPE)
19315 #define F_PVT_UPD_TRIG_TYPE    V_PVT_UPD_TRIG_TYPE(1U)
19316 
19317 #define S_PVT_UPD_DONE_POL    10
19318 #define V_PVT_UPD_DONE_POL(x) ((x) << S_PVT_UPD_DONE_POL)
19319 #define F_PVT_UPD_DONE_POL    V_PVT_UPD_DONE_POL(1U)
19320 
19321 #define S_PVT_UPD_DONE_TYPE    8
19322 #define M_PVT_UPD_DONE_TYPE    0x3U
19323 #define V_PVT_UPD_DONE_TYPE(x) ((x) << S_PVT_UPD_DONE_TYPE)
19324 #define G_PVT_UPD_DONE_TYPE(x) (((x) >> S_PVT_UPD_DONE_TYPE) & M_PVT_UPD_DONE_TYPE)
19325 
19326 #define S_PHY_UPD_REQ_EN    7
19327 #define V_PHY_UPD_REQ_EN(x) ((x) << S_PHY_UPD_REQ_EN)
19328 #define F_PHY_UPD_REQ_EN    V_PHY_UPD_REQ_EN(1U)
19329 
19330 #define S_PHY_UPD_TRIG_POL    6
19331 #define V_PHY_UPD_TRIG_POL(x) ((x) << S_PHY_UPD_TRIG_POL)
19332 #define F_PHY_UPD_TRIG_POL    V_PHY_UPD_TRIG_POL(1U)
19333 
19334 #define S_PHY_UPD_TRIG_TYPE    4
19335 #define V_PHY_UPD_TRIG_TYPE(x) ((x) << S_PHY_UPD_TRIG_TYPE)
19336 #define F_PHY_UPD_TRIG_TYPE    V_PHY_UPD_TRIG_TYPE(1U)
19337 
19338 #define S_PHY_UPD_DONE_POL    2
19339 #define V_PHY_UPD_DONE_POL(x) ((x) << S_PHY_UPD_DONE_POL)
19340 #define F_PHY_UPD_DONE_POL    V_PHY_UPD_DONE_POL(1U)
19341 
19342 #define S_PHY_UPD_DONE_TYPE    0
19343 #define M_PHY_UPD_DONE_TYPE    0x3U
19344 #define V_PHY_UPD_DONE_TYPE(x) ((x) << S_PHY_UPD_DONE_TYPE)
19345 #define G_PHY_UPD_DONE_TYPE(x) (((x) >> S_PHY_UPD_DONE_TYPE) & M_PHY_UPD_DONE_TYPE)
19346 
19347 #define A_MC_PCTL_PHYPVTSTAT 0x6504
19348 
19349 #define S_I_PVT_UPD_TRIG    5
19350 #define V_I_PVT_UPD_TRIG(x) ((x) << S_I_PVT_UPD_TRIG)
19351 #define F_I_PVT_UPD_TRIG    V_I_PVT_UPD_TRIG(1U)
19352 
19353 #define S_I_PVT_UPD_DONE    4
19354 #define V_I_PVT_UPD_DONE(x) ((x) << S_I_PVT_UPD_DONE)
19355 #define F_I_PVT_UPD_DONE    V_I_PVT_UPD_DONE(1U)
19356 
19357 #define S_I_PHY_UPD_TRIG    1
19358 #define V_I_PHY_UPD_TRIG(x) ((x) << S_I_PHY_UPD_TRIG)
19359 #define F_I_PHY_UPD_TRIG    V_I_PHY_UPD_TRIG(1U)
19360 
19361 #define S_I_PHY_UPD_DONE    0
19362 #define V_I_PHY_UPD_DONE(x) ((x) << S_I_PHY_UPD_DONE)
19363 #define F_I_PHY_UPD_DONE    V_I_PHY_UPD_DONE(1U)
19364 
19365 #define A_MC_PCTL_PHYTUPDON 0x6508
19366 
19367 #define S_PHY_T_UPDON    0
19368 #define M_PHY_T_UPDON    0xffU
19369 #define V_PHY_T_UPDON(x) ((x) << S_PHY_T_UPDON)
19370 #define G_PHY_T_UPDON(x) (((x) >> S_PHY_T_UPDON) & M_PHY_T_UPDON)
19371 
19372 #define A_MC_PCTL_PHYTUPDDLY 0x650c
19373 
19374 #define S_PHY_T_UPDDLY    0
19375 #define M_PHY_T_UPDDLY    0xfU
19376 #define V_PHY_T_UPDDLY(x) ((x) << S_PHY_T_UPDDLY)
19377 #define G_PHY_T_UPDDLY(x) (((x) >> S_PHY_T_UPDDLY) & M_PHY_T_UPDDLY)
19378 
19379 #define A_MC_PCTL_PVTTUPON 0x6510
19380 
19381 #define S_PVT_T_UPDON    0
19382 #define M_PVT_T_UPDON    0xffU
19383 #define V_PVT_T_UPDON(x) ((x) << S_PVT_T_UPDON)
19384 #define G_PVT_T_UPDON(x) (((x) >> S_PVT_T_UPDON) & M_PVT_T_UPDON)
19385 
19386 #define A_MC_PCTL_PVTTUPDDLY 0x6514
19387 
19388 #define S_PVT_T_UPDDLY    0
19389 #define M_PVT_T_UPDDLY    0xfU
19390 #define V_PVT_T_UPDDLY(x) ((x) << S_PVT_T_UPDDLY)
19391 #define G_PVT_T_UPDDLY(x) (((x) >> S_PVT_T_UPDDLY) & M_PVT_T_UPDDLY)
19392 
19393 #define A_MC_PCTL_PHYPVTUPDI 0x6518
19394 
19395 #define S_PHYPVT_T_UPDI    0
19396 #define M_PHYPVT_T_UPDI    0xffU
19397 #define V_PHYPVT_T_UPDI(x) ((x) << S_PHYPVT_T_UPDI)
19398 #define G_PHYPVT_T_UPDI(x) (((x) >> S_PHYPVT_T_UPDI) & M_PHYPVT_T_UPDI)
19399 
19400 #define A_MC_PCTL_PHYIOCRV1 0x651c
19401 
19402 #define S_BYTE_OE_CTL    16
19403 #define M_BYTE_OE_CTL    0x3U
19404 #define V_BYTE_OE_CTL(x) ((x) << S_BYTE_OE_CTL)
19405 #define G_BYTE_OE_CTL(x) (((x) >> S_BYTE_OE_CTL) & M_BYTE_OE_CTL)
19406 
19407 #define S_DYN_SOC_ODT_ALAT    12
19408 #define M_DYN_SOC_ODT_ALAT    0xfU
19409 #define V_DYN_SOC_ODT_ALAT(x) ((x) << S_DYN_SOC_ODT_ALAT)
19410 #define G_DYN_SOC_ODT_ALAT(x) (((x) >> S_DYN_SOC_ODT_ALAT) & M_DYN_SOC_ODT_ALAT)
19411 
19412 #define S_DYN_SOC_ODT_ATEN    8
19413 #define M_DYN_SOC_ODT_ATEN    0x3U
19414 #define V_DYN_SOC_ODT_ATEN(x) ((x) << S_DYN_SOC_ODT_ATEN)
19415 #define G_DYN_SOC_ODT_ATEN(x) (((x) >> S_DYN_SOC_ODT_ATEN) & M_DYN_SOC_ODT_ATEN)
19416 
19417 #define S_DYN_SOC_ODT    2
19418 #define V_DYN_SOC_ODT(x) ((x) << S_DYN_SOC_ODT)
19419 #define F_DYN_SOC_ODT    V_DYN_SOC_ODT(1U)
19420 
19421 #define S_SOC_ODT_EN    0
19422 #define V_SOC_ODT_EN(x) ((x) << S_SOC_ODT_EN)
19423 #define F_SOC_ODT_EN    V_SOC_ODT_EN(1U)
19424 
19425 #define A_MC_PCTL_PHYTUPDWAIT 0x6520
19426 
19427 #define S_PHY_T_UPDWAIT    0
19428 #define M_PHY_T_UPDWAIT    0x3fU
19429 #define V_PHY_T_UPDWAIT(x) ((x) << S_PHY_T_UPDWAIT)
19430 #define G_PHY_T_UPDWAIT(x) (((x) >> S_PHY_T_UPDWAIT) & M_PHY_T_UPDWAIT)
19431 
19432 #define A_MC_PCTL_PVTTUPDWAIT 0x6524
19433 
19434 #define S_PVT_T_UPDWAIT    0
19435 #define M_PVT_T_UPDWAIT    0x3fU
19436 #define V_PVT_T_UPDWAIT(x) ((x) << S_PVT_T_UPDWAIT)
19437 #define G_PVT_T_UPDWAIT(x) (((x) >> S_PVT_T_UPDWAIT) & M_PVT_T_UPDWAIT)
19438 
19439 #define A_MC_DDR3PHYAC_GCR 0x6a00
19440 
19441 #define S_WLRANK    8
19442 #define M_WLRANK    0x3U
19443 #define V_WLRANK(x) ((x) << S_WLRANK)
19444 #define G_WLRANK(x) (((x) >> S_WLRANK) & M_WLRANK)
19445 
19446 #define S_FDEPTH    6
19447 #define M_FDEPTH    0x3U
19448 #define V_FDEPTH(x) ((x) << S_FDEPTH)
19449 #define G_FDEPTH(x) (((x) >> S_FDEPTH) & M_FDEPTH)
19450 
19451 #define S_LPFDEPTH    4
19452 #define M_LPFDEPTH    0x3U
19453 #define V_LPFDEPTH(x) ((x) << S_LPFDEPTH)
19454 #define G_LPFDEPTH(x) (((x) >> S_LPFDEPTH) & M_LPFDEPTH)
19455 
19456 #define S_LPFEN    3
19457 #define V_LPFEN(x) ((x) << S_LPFEN)
19458 #define F_LPFEN    V_LPFEN(1U)
19459 
19460 #define S_WL    2
19461 #define V_WL(x) ((x) << S_WL)
19462 #define F_WL    V_WL(1U)
19463 
19464 #define S_CAL    1
19465 #define V_CAL(x) ((x) << S_CAL)
19466 #define F_CAL    V_CAL(1U)
19467 
19468 #define S_MDLEN    0
19469 #define V_MDLEN(x) ((x) << S_MDLEN)
19470 #define F_MDLEN    V_MDLEN(1U)
19471 
19472 #define A_MC_DDR3PHYAC_RCR0 0x6a04
19473 
19474 #define S_OCPONR    8
19475 #define V_OCPONR(x) ((x) << S_OCPONR)
19476 #define F_OCPONR    V_OCPONR(1U)
19477 
19478 #define S_OCPOND    7
19479 #define V_OCPOND(x) ((x) << S_OCPOND)
19480 #define F_OCPOND    V_OCPOND(1U)
19481 
19482 #define S_OCOEN    6
19483 #define V_OCOEN(x) ((x) << S_OCOEN)
19484 #define F_OCOEN    V_OCOEN(1U)
19485 
19486 #define S_CKEPONR    5
19487 #define V_CKEPONR(x) ((x) << S_CKEPONR)
19488 #define F_CKEPONR    V_CKEPONR(1U)
19489 
19490 #define S_CKEPOND    4
19491 #define V_CKEPOND(x) ((x) << S_CKEPOND)
19492 #define F_CKEPOND    V_CKEPOND(1U)
19493 
19494 #define S_CKEOEN    3
19495 #define V_CKEOEN(x) ((x) << S_CKEOEN)
19496 #define F_CKEOEN    V_CKEOEN(1U)
19497 
19498 #define S_CKPONR    2
19499 #define V_CKPONR(x) ((x) << S_CKPONR)
19500 #define F_CKPONR    V_CKPONR(1U)
19501 
19502 #define S_CKPOND    1
19503 #define V_CKPOND(x) ((x) << S_CKPOND)
19504 #define F_CKPOND    V_CKPOND(1U)
19505 
19506 #define S_CKOEN    0
19507 #define V_CKOEN(x) ((x) << S_CKOEN)
19508 #define F_CKOEN    V_CKOEN(1U)
19509 
19510 #define A_MC_DDR3PHYAC_ACCR 0x6a14
19511 
19512 #define S_ACPONR    8
19513 #define V_ACPONR(x) ((x) << S_ACPONR)
19514 #define F_ACPONR    V_ACPONR(1U)
19515 
19516 #define S_ACPOND    7
19517 #define V_ACPOND(x) ((x) << S_ACPOND)
19518 #define F_ACPOND    V_ACPOND(1U)
19519 
19520 #define S_ACOEN    6
19521 #define V_ACOEN(x) ((x) << S_ACOEN)
19522 #define F_ACOEN    V_ACOEN(1U)
19523 
19524 #define S_CK5PONR    5
19525 #define V_CK5PONR(x) ((x) << S_CK5PONR)
19526 #define F_CK5PONR    V_CK5PONR(1U)
19527 
19528 #define S_CK5POND    4
19529 #define V_CK5POND(x) ((x) << S_CK5POND)
19530 #define F_CK5POND    V_CK5POND(1U)
19531 
19532 #define S_CK5OEN    3
19533 #define V_CK5OEN(x) ((x) << S_CK5OEN)
19534 #define F_CK5OEN    V_CK5OEN(1U)
19535 
19536 #define S_CK4PONR    2
19537 #define V_CK4PONR(x) ((x) << S_CK4PONR)
19538 #define F_CK4PONR    V_CK4PONR(1U)
19539 
19540 #define S_CK4POND    1
19541 #define V_CK4POND(x) ((x) << S_CK4POND)
19542 #define F_CK4POND    V_CK4POND(1U)
19543 
19544 #define S_CK4OEN    0
19545 #define V_CK4OEN(x) ((x) << S_CK4OEN)
19546 #define F_CK4OEN    V_CK4OEN(1U)
19547 
19548 #define A_MC_DDR3PHYAC_GSR 0x6a18
19549 
19550 #define S_WLERR    4
19551 #define V_WLERR(x) ((x) << S_WLERR)
19552 #define F_WLERR    V_WLERR(1U)
19553 
19554 #define S_INIT    3
19555 #define V_INIT(x) ((x) << S_INIT)
19556 #define F_INIT    V_INIT(1U)
19557 
19558 #define S_ACCAL    0
19559 #define V_ACCAL(x) ((x) << S_ACCAL)
19560 #define F_ACCAL    V_ACCAL(1U)
19561 
19562 #define A_MC_DDR3PHYAC_ECSR 0x6a1c
19563 
19564 #define S_WLDEC    1
19565 #define V_WLDEC(x) ((x) << S_WLDEC)
19566 #define F_WLDEC    V_WLDEC(1U)
19567 
19568 #define S_WLINC    0
19569 #define V_WLINC(x) ((x) << S_WLINC)
19570 #define F_WLINC    V_WLINC(1U)
19571 
19572 #define A_MC_DDR3PHYAC_OCSR 0x6a20
19573 #define A_MC_DDR3PHYAC_MDIPR 0x6a24
19574 
19575 #define S_PRD    0
19576 #define M_PRD    0x3ffU
19577 #define V_PRD(x) ((x) << S_PRD)
19578 #define G_PRD(x) (((x) >> S_PRD) & M_PRD)
19579 
19580 #define A_MC_DDR3PHYAC_MDTPR 0x6a28
19581 #define A_MC_DDR3PHYAC_MDPPR0 0x6a2c
19582 #define A_MC_DDR3PHYAC_MDPPR1 0x6a30
19583 #define A_MC_DDR3PHYAC_PMBDR0 0x6a34
19584 
19585 #define S_DFLTDLY    0
19586 #define M_DFLTDLY    0x7fU
19587 #define V_DFLTDLY(x) ((x) << S_DFLTDLY)
19588 #define G_DFLTDLY(x) (((x) >> S_DFLTDLY) & M_DFLTDLY)
19589 
19590 #define A_MC_DDR3PHYAC_PMBDR1 0x6a38
19591 #define A_MC_DDR3PHYAC_ACR 0x6a60
19592 
19593 #define S_TSEL    9
19594 #define V_TSEL(x) ((x) << S_TSEL)
19595 #define F_TSEL    V_TSEL(1U)
19596 
19597 #define S_ISEL    7
19598 #define M_ISEL    0x3U
19599 #define V_ISEL(x) ((x) << S_ISEL)
19600 #define G_ISEL(x) (((x) >> S_ISEL) & M_ISEL)
19601 
19602 #define S_CALBYP    2
19603 #define V_CALBYP(x) ((x) << S_CALBYP)
19604 #define F_CALBYP    V_CALBYP(1U)
19605 
19606 #define S_SDRSELINV    1
19607 #define V_SDRSELINV(x) ((x) << S_SDRSELINV)
19608 #define F_SDRSELINV    V_SDRSELINV(1U)
19609 
19610 #define S_CKINV    0
19611 #define V_CKINV(x) ((x) << S_CKINV)
19612 #define F_CKINV    V_CKINV(1U)
19613 
19614 #define A_MC_DDR3PHYAC_PSCR 0x6a64
19615 
19616 #define S_PSCALE    0
19617 #define M_PSCALE    0x3ffU
19618 #define V_PSCALE(x) ((x) << S_PSCALE)
19619 #define G_PSCALE(x) (((x) >> S_PSCALE) & M_PSCALE)
19620 
19621 #define A_MC_DDR3PHYAC_PRCR 0x6a68
19622 
19623 #define S_PHYINIT    9
19624 #define V_PHYINIT(x) ((x) << S_PHYINIT)
19625 #define F_PHYINIT    V_PHYINIT(1U)
19626 
19627 #define S_PHYHRST    7
19628 #define V_PHYHRST(x) ((x) << S_PHYHRST)
19629 #define F_PHYHRST    V_PHYHRST(1U)
19630 
19631 #define S_RSTCLKS    3
19632 #define M_RSTCLKS    0xfU
19633 #define V_RSTCLKS(x) ((x) << S_RSTCLKS)
19634 #define G_RSTCLKS(x) (((x) >> S_RSTCLKS) & M_RSTCLKS)
19635 
19636 #define S_PLLPD    2
19637 #define V_PLLPD(x) ((x) << S_PLLPD)
19638 #define F_PLLPD    V_PLLPD(1U)
19639 
19640 #define S_PLLRST    1
19641 #define V_PLLRST(x) ((x) << S_PLLRST)
19642 #define F_PLLRST    V_PLLRST(1U)
19643 
19644 #define S_PHYRST    0
19645 #define V_PHYRST(x) ((x) << S_PHYRST)
19646 #define F_PHYRST    V_PHYRST(1U)
19647 
19648 #define A_MC_DDR3PHYAC_PLLCR0 0x6a6c
19649 
19650 #define S_RSTCXKS    4
19651 #define M_RSTCXKS    0x1fU
19652 #define V_RSTCXKS(x) ((x) << S_RSTCXKS)
19653 #define G_RSTCXKS(x) (((x) >> S_RSTCXKS) & M_RSTCXKS)
19654 
19655 #define S_ICPSEL    3
19656 #define V_ICPSEL(x) ((x) << S_ICPSEL)
19657 #define F_ICPSEL    V_ICPSEL(1U)
19658 
19659 #define S_TESTA    0
19660 #define M_TESTA    0x7U
19661 #define V_TESTA(x) ((x) << S_TESTA)
19662 #define G_TESTA(x) (((x) >> S_TESTA) & M_TESTA)
19663 
19664 #define A_MC_DDR3PHYAC_PLLCR1 0x6a70
19665 
19666 #define S_BYPASS    9
19667 #define V_BYPASS(x) ((x) << S_BYPASS)
19668 #define F_BYPASS    V_BYPASS(1U)
19669 
19670 #define S_BDIV    3
19671 #define M_BDIV    0x3U
19672 #define V_BDIV(x) ((x) << S_BDIV)
19673 #define G_BDIV(x) (((x) >> S_BDIV) & M_BDIV)
19674 
19675 #define S_TESTD    0
19676 #define M_TESTD    0x7U
19677 #define V_TESTD(x) ((x) << S_TESTD)
19678 #define G_TESTD(x) (((x) >> S_TESTD) & M_TESTD)
19679 
19680 #define A_MC_DDR3PHYAC_CLKENR 0x6a78
19681 
19682 #define S_CKCLKEN    3
19683 #define M_CKCLKEN    0x3fU
19684 #define V_CKCLKEN(x) ((x) << S_CKCLKEN)
19685 #define G_CKCLKEN(x) (((x) >> S_CKCLKEN) & M_CKCLKEN)
19686 
19687 #define S_HDRCLKEN    2
19688 #define V_HDRCLKEN(x) ((x) << S_HDRCLKEN)
19689 #define F_HDRCLKEN    V_HDRCLKEN(1U)
19690 
19691 #define S_SDRCLKEN    1
19692 #define V_SDRCLKEN(x) ((x) << S_SDRCLKEN)
19693 #define F_SDRCLKEN    V_SDRCLKEN(1U)
19694 
19695 #define S_DDRCLKEN    0
19696 #define V_DDRCLKEN(x) ((x) << S_DDRCLKEN)
19697 #define F_DDRCLKEN    V_DDRCLKEN(1U)
19698 
19699 #define A_MC_DDR3PHYDATX8_GCR 0x6b00
19700 
19701 #define S_PONR    6
19702 #define V_PONR(x) ((x) << S_PONR)
19703 #define F_PONR    V_PONR(1U)
19704 
19705 #define S_POND    5
19706 #define V_POND(x) ((x) << S_POND)
19707 #define F_POND    V_POND(1U)
19708 
19709 #define S_RDBDVT    4
19710 #define V_RDBDVT(x) ((x) << S_RDBDVT)
19711 #define F_RDBDVT    V_RDBDVT(1U)
19712 
19713 #define S_WDBDVT    3
19714 #define V_WDBDVT(x) ((x) << S_WDBDVT)
19715 #define F_WDBDVT    V_WDBDVT(1U)
19716 
19717 #define S_RDSDVT    2
19718 #define V_RDSDVT(x) ((x) << S_RDSDVT)
19719 #define F_RDSDVT    V_RDSDVT(1U)
19720 
19721 #define S_WDSDVT    1
19722 #define V_WDSDVT(x) ((x) << S_WDSDVT)
19723 #define F_WDSDVT    V_WDSDVT(1U)
19724 
19725 #define S_WLSDVT    0
19726 #define V_WLSDVT(x) ((x) << S_WLSDVT)
19727 #define F_WLSDVT    V_WLSDVT(1U)
19728 
19729 #define A_MC_DDR3PHYDATX8_WDSDR 0x6b04
19730 
19731 #define S_WDSDR_DLY    0
19732 #define M_WDSDR_DLY    0x3ffU
19733 #define V_WDSDR_DLY(x) ((x) << S_WDSDR_DLY)
19734 #define G_WDSDR_DLY(x) (((x) >> S_WDSDR_DLY) & M_WDSDR_DLY)
19735 
19736 #define A_MC_DDR3PHYDATX8_WLDPR 0x6b08
19737 #define A_MC_DDR3PHYDATX8_WLDR 0x6b0c
19738 
19739 #define S_WL_DLY    0
19740 #define M_WL_DLY    0x3ffU
19741 #define V_WL_DLY(x) ((x) << S_WL_DLY)
19742 #define G_WL_DLY(x) (((x) >> S_WL_DLY) & M_WL_DLY)
19743 
19744 #define A_MC_DDR3PHYDATX8_WDBDR0 0x6b1c
19745 
19746 #define S_DLY    0
19747 #define M_DLY    0x7fU
19748 #define V_DLY(x) ((x) << S_DLY)
19749 #define G_DLY(x) (((x) >> S_DLY) & M_DLY)
19750 
19751 #define A_MC_DDR3PHYDATX8_WDBDR1 0x6b20
19752 #define A_MC_DDR3PHYDATX8_WDBDR2 0x6b24
19753 #define A_MC_DDR3PHYDATX8_WDBDR3 0x6b28
19754 #define A_MC_DDR3PHYDATX8_WDBDR4 0x6b2c
19755 #define A_MC_DDR3PHYDATX8_WDBDR5 0x6b30
19756 #define A_MC_DDR3PHYDATX8_WDBDR6 0x6b34
19757 #define A_MC_DDR3PHYDATX8_WDBDR7 0x6b38
19758 #define A_MC_DDR3PHYDATX8_WDBDR8 0x6b3c
19759 #define A_MC_DDR3PHYDATX8_WDBDMR 0x6b40
19760 
19761 #define S_MAXDLY    0
19762 #define M_MAXDLY    0x7fU
19763 #define V_MAXDLY(x) ((x) << S_MAXDLY)
19764 #define G_MAXDLY(x) (((x) >> S_MAXDLY) & M_MAXDLY)
19765 
19766 #define A_MC_DDR3PHYDATX8_RDSDR 0x6b44
19767 
19768 #define S_RDSDR_DLY    0
19769 #define M_RDSDR_DLY    0x3ffU
19770 #define V_RDSDR_DLY(x) ((x) << S_RDSDR_DLY)
19771 #define G_RDSDR_DLY(x) (((x) >> S_RDSDR_DLY) & M_RDSDR_DLY)
19772 
19773 #define A_MC_DDR3PHYDATX8_RDBDR0 0x6b48
19774 #define A_MC_DDR3PHYDATX8_RDBDR1 0x6b4c
19775 #define A_MC_DDR3PHYDATX8_RDBDR2 0x6b50
19776 #define A_MC_DDR3PHYDATX8_RDBDR3 0x6b54
19777 #define A_MC_DDR3PHYDATX8_RDBDR4 0x6b58
19778 #define A_MC_DDR3PHYDATX8_RDBDR5 0x6b5c
19779 #define A_MC_DDR3PHYDATX8_RDBDR6 0x6b60
19780 #define A_MC_DDR3PHYDATX8_RDBDR7 0x6b64
19781 #define A_MC_DDR3PHYDATX8_RDBDMR 0x6b68
19782 #define A_MC_DDR3PHYDATX8_PMBDR0 0x6b6c
19783 #define A_MC_DDR3PHYDATX8_PMBDR1 0x6b70
19784 #define A_MC_DDR3PHYDATX8_PMBDR2 0x6b74
19785 #define A_MC_DDR3PHYDATX8_PMBDR3 0x6b78
19786 #define A_MC_DDR3PHYDATX8_WDBDPR 0x6b7c
19787 
19788 #define S_DP_DLY    0
19789 #define M_DP_DLY    0x1ffU
19790 #define V_DP_DLY(x) ((x) << S_DP_DLY)
19791 #define G_DP_DLY(x) (((x) >> S_DP_DLY) & M_DP_DLY)
19792 
19793 #define A_MC_DDR3PHYDATX8_RDBDPR 0x6b80
19794 #define A_MC_DDR3PHYDATX8_GSR 0x6b84
19795 
19796 #define S_WLDONE    3
19797 #define V_WLDONE(x) ((x) << S_WLDONE)
19798 #define F_WLDONE    V_WLDONE(1U)
19799 
19800 #define S_WLCAL    2
19801 #define V_WLCAL(x) ((x) << S_WLCAL)
19802 #define F_WLCAL    V_WLCAL(1U)
19803 
19804 #define S_READ    1
19805 #define V_READ(x) ((x) << S_READ)
19806 #define F_READ    V_READ(1U)
19807 
19808 #define S_RDQSCAL    0
19809 #define V_RDQSCAL(x) ((x) << S_RDQSCAL)
19810 #define F_RDQSCAL    V_RDQSCAL(1U)
19811 
19812 #define A_MC_DDR3PHYDATX8_ACR 0x6bf0
19813 
19814 #define S_PHYHSRST    9
19815 #define V_PHYHSRST(x) ((x) << S_PHYHSRST)
19816 #define F_PHYHSRST    V_PHYHSRST(1U)
19817 
19818 #define S_WLSTEP    8
19819 #define V_WLSTEP(x) ((x) << S_WLSTEP)
19820 #define F_WLSTEP    V_WLSTEP(1U)
19821 
19822 #define S_SDR_SEL_INV    2
19823 #define V_SDR_SEL_INV(x) ((x) << S_SDR_SEL_INV)
19824 #define F_SDR_SEL_INV    V_SDR_SEL_INV(1U)
19825 
19826 #define S_DDRSELINV    1
19827 #define V_DDRSELINV(x) ((x) << S_DDRSELINV)
19828 #define F_DDRSELINV    V_DDRSELINV(1U)
19829 
19830 #define S_DSINV    0
19831 #define V_DSINV(x) ((x) << S_DSINV)
19832 #define F_DSINV    V_DSINV(1U)
19833 
19834 #define A_MC_DDR3PHYDATX8_RSR 0x6bf4
19835 
19836 #define S_WLRANKSEL    9
19837 #define V_WLRANKSEL(x) ((x) << S_WLRANKSEL)
19838 #define F_WLRANKSEL    V_WLRANKSEL(1U)
19839 
19840 #define S_RANK    0
19841 #define M_RANK    0x3U
19842 #define V_RANK(x) ((x) << S_RANK)
19843 #define G_RANK(x) (((x) >> S_RANK) & M_RANK)
19844 
19845 #define A_MC_DDR3PHYDATX8_CLKENR 0x6bf8
19846 
19847 #define S_DTOSEL    8
19848 #define M_DTOSEL    0x3U
19849 #define V_DTOSEL(x) ((x) << S_DTOSEL)
19850 #define G_DTOSEL(x) (((x) >> S_DTOSEL) & M_DTOSEL)
19851 
19852 #define A_MC_PVT_REG_CALIBRATE_CTL 0x7400
19853 #define A_MC_PVT_REG_UPDATE_CTL 0x7404
19854 #define A_MC_PVT_REG_LAST_MEASUREMENT 0x7408
19855 #define A_MC_PVT_REG_DRVN 0x740c
19856 #define A_MC_PVT_REG_DRVP 0x7410
19857 #define A_MC_PVT_REG_TERMN 0x7414
19858 #define A_MC_PVT_REG_TERMP 0x7418
19859 #define A_MC_PVT_REG_THRESHOLD 0x741c
19860 #define A_MC_PVT_REG_IN_TERMP 0x7420
19861 #define A_MC_PVT_REG_IN_TERMN 0x7424
19862 #define A_MC_PVT_REG_IN_DRVP 0x7428
19863 #define A_MC_PVT_REG_IN_DRVN 0x742c
19864 #define A_MC_PVT_REG_OUT_TERMP 0x7430
19865 #define A_MC_PVT_REG_OUT_TERMN 0x7434
19866 #define A_MC_PVT_REG_OUT_DRVP 0x7438
19867 #define A_MC_PVT_REG_OUT_DRVN 0x743c
19868 #define A_MC_PVT_REG_HISTORY_TERMP 0x7440
19869 #define A_MC_PVT_REG_HISTORY_TERMN 0x7444
19870 #define A_MC_PVT_REG_HISTORY_DRVP 0x7448
19871 #define A_MC_PVT_REG_HISTORY_DRVN 0x744c
19872 #define A_MC_PVT_REG_SAMPLE_WAIT_CLKS 0x7450
19873 #define A_MC_DDRPHY_RST_CTRL 0x7500
19874 
19875 #define S_DDRIO_ENABLE    1
19876 #define V_DDRIO_ENABLE(x) ((x) << S_DDRIO_ENABLE)
19877 #define F_DDRIO_ENABLE    V_DDRIO_ENABLE(1U)
19878 
19879 #define S_PHY_RST_N    0
19880 #define V_PHY_RST_N(x) ((x) << S_PHY_RST_N)
19881 #define F_PHY_RST_N    V_PHY_RST_N(1U)
19882 
19883 #define A_MC_PERFORMANCE_CTRL 0x7504
19884 
19885 #define S_STALL_CHK_BIT    2
19886 #define V_STALL_CHK_BIT(x) ((x) << S_STALL_CHK_BIT)
19887 #define F_STALL_CHK_BIT    V_STALL_CHK_BIT(1U)
19888 
19889 #define S_DDR3_BRC_MODE    1
19890 #define V_DDR3_BRC_MODE(x) ((x) << S_DDR3_BRC_MODE)
19891 #define F_DDR3_BRC_MODE    V_DDR3_BRC_MODE(1U)
19892 
19893 #define S_RMW_PERF_CTRL    0
19894 #define V_RMW_PERF_CTRL(x) ((x) << S_RMW_PERF_CTRL)
19895 #define F_RMW_PERF_CTRL    V_RMW_PERF_CTRL(1U)
19896 
19897 #define A_MC_ECC_CTRL 0x7508
19898 
19899 #define S_ECC_BYPASS_BIST    1
19900 #define V_ECC_BYPASS_BIST(x) ((x) << S_ECC_BYPASS_BIST)
19901 #define F_ECC_BYPASS_BIST    V_ECC_BYPASS_BIST(1U)
19902 
19903 #define S_ECC_DISABLE    0
19904 #define V_ECC_DISABLE(x) ((x) << S_ECC_DISABLE)
19905 #define F_ECC_DISABLE    V_ECC_DISABLE(1U)
19906 
19907 #define A_MC_PAR_ENABLE 0x750c
19908 
19909 #define S_ECC_UE_PAR_ENABLE    3
19910 #define V_ECC_UE_PAR_ENABLE(x) ((x) << S_ECC_UE_PAR_ENABLE)
19911 #define F_ECC_UE_PAR_ENABLE    V_ECC_UE_PAR_ENABLE(1U)
19912 
19913 #define S_ECC_CE_PAR_ENABLE    2
19914 #define V_ECC_CE_PAR_ENABLE(x) ((x) << S_ECC_CE_PAR_ENABLE)
19915 #define F_ECC_CE_PAR_ENABLE    V_ECC_CE_PAR_ENABLE(1U)
19916 
19917 #define S_PERR_REG_INT_ENABLE    1
19918 #define V_PERR_REG_INT_ENABLE(x) ((x) << S_PERR_REG_INT_ENABLE)
19919 #define F_PERR_REG_INT_ENABLE    V_PERR_REG_INT_ENABLE(1U)
19920 
19921 #define S_PERR_BLK_INT_ENABLE    0
19922 #define V_PERR_BLK_INT_ENABLE(x) ((x) << S_PERR_BLK_INT_ENABLE)
19923 #define F_PERR_BLK_INT_ENABLE    V_PERR_BLK_INT_ENABLE(1U)
19924 
19925 #define A_MC_PAR_CAUSE 0x7510
19926 
19927 #define S_ECC_UE_PAR_CAUSE    3
19928 #define V_ECC_UE_PAR_CAUSE(x) ((x) << S_ECC_UE_PAR_CAUSE)
19929 #define F_ECC_UE_PAR_CAUSE    V_ECC_UE_PAR_CAUSE(1U)
19930 
19931 #define S_ECC_CE_PAR_CAUSE    2
19932 #define V_ECC_CE_PAR_CAUSE(x) ((x) << S_ECC_CE_PAR_CAUSE)
19933 #define F_ECC_CE_PAR_CAUSE    V_ECC_CE_PAR_CAUSE(1U)
19934 
19935 #define S_FIFOR_PAR_CAUSE    1
19936 #define V_FIFOR_PAR_CAUSE(x) ((x) << S_FIFOR_PAR_CAUSE)
19937 #define F_FIFOR_PAR_CAUSE    V_FIFOR_PAR_CAUSE(1U)
19938 
19939 #define S_RDATA_FIFOR_PAR_CAUSE    0
19940 #define V_RDATA_FIFOR_PAR_CAUSE(x) ((x) << S_RDATA_FIFOR_PAR_CAUSE)
19941 #define F_RDATA_FIFOR_PAR_CAUSE    V_RDATA_FIFOR_PAR_CAUSE(1U)
19942 
19943 #define A_MC_INT_ENABLE 0x7514
19944 
19945 #define S_ECC_UE_INT_ENABLE    2
19946 #define V_ECC_UE_INT_ENABLE(x) ((x) << S_ECC_UE_INT_ENABLE)
19947 #define F_ECC_UE_INT_ENABLE    V_ECC_UE_INT_ENABLE(1U)
19948 
19949 #define S_ECC_CE_INT_ENABLE    1
19950 #define V_ECC_CE_INT_ENABLE(x) ((x) << S_ECC_CE_INT_ENABLE)
19951 #define F_ECC_CE_INT_ENABLE    V_ECC_CE_INT_ENABLE(1U)
19952 
19953 #define S_PERR_INT_ENABLE    0
19954 #define V_PERR_INT_ENABLE(x) ((x) << S_PERR_INT_ENABLE)
19955 #define F_PERR_INT_ENABLE    V_PERR_INT_ENABLE(1U)
19956 
19957 #define A_MC_INT_CAUSE 0x7518
19958 
19959 #define S_ECC_UE_INT_CAUSE    2
19960 #define V_ECC_UE_INT_CAUSE(x) ((x) << S_ECC_UE_INT_CAUSE)
19961 #define F_ECC_UE_INT_CAUSE    V_ECC_UE_INT_CAUSE(1U)
19962 
19963 #define S_ECC_CE_INT_CAUSE    1
19964 #define V_ECC_CE_INT_CAUSE(x) ((x) << S_ECC_CE_INT_CAUSE)
19965 #define F_ECC_CE_INT_CAUSE    V_ECC_CE_INT_CAUSE(1U)
19966 
19967 #define S_PERR_INT_CAUSE    0
19968 #define V_PERR_INT_CAUSE(x) ((x) << S_PERR_INT_CAUSE)
19969 #define F_PERR_INT_CAUSE    V_PERR_INT_CAUSE(1U)
19970 
19971 #define A_MC_ECC_STATUS 0x751c
19972 
19973 #define S_ECC_CECNT    16
19974 #define M_ECC_CECNT    0xffffU
19975 #define V_ECC_CECNT(x) ((x) << S_ECC_CECNT)
19976 #define G_ECC_CECNT(x) (((x) >> S_ECC_CECNT) & M_ECC_CECNT)
19977 
19978 #define S_ECC_UECNT    0
19979 #define M_ECC_UECNT    0xffffU
19980 #define V_ECC_UECNT(x) ((x) << S_ECC_UECNT)
19981 #define G_ECC_UECNT(x) (((x) >> S_ECC_UECNT) & M_ECC_UECNT)
19982 
19983 #define A_MC_PHY_CTRL 0x7520
19984 
19985 #define S_CTLPHYRR    0
19986 #define V_CTLPHYRR(x) ((x) << S_CTLPHYRR)
19987 #define F_CTLPHYRR    V_CTLPHYRR(1U)
19988 
19989 #define A_MC_STATIC_CFG_STATUS 0x7524
19990 
19991 #define S_STATIC_MODE    9
19992 #define V_STATIC_MODE(x) ((x) << S_STATIC_MODE)
19993 #define F_STATIC_MODE    V_STATIC_MODE(1U)
19994 
19995 #define S_STATIC_DEN    6
19996 #define M_STATIC_DEN    0x7U
19997 #define V_STATIC_DEN(x) ((x) << S_STATIC_DEN)
19998 #define G_STATIC_DEN(x) (((x) >> S_STATIC_DEN) & M_STATIC_DEN)
19999 
20000 #define S_STATIC_ORG    5
20001 #define V_STATIC_ORG(x) ((x) << S_STATIC_ORG)
20002 #define F_STATIC_ORG    V_STATIC_ORG(1U)
20003 
20004 #define S_STATIC_RKS    4
20005 #define V_STATIC_RKS(x) ((x) << S_STATIC_RKS)
20006 #define F_STATIC_RKS    V_STATIC_RKS(1U)
20007 
20008 #define S_STATIC_WIDTH    1
20009 #define M_STATIC_WIDTH    0x7U
20010 #define V_STATIC_WIDTH(x) ((x) << S_STATIC_WIDTH)
20011 #define G_STATIC_WIDTH(x) (((x) >> S_STATIC_WIDTH) & M_STATIC_WIDTH)
20012 
20013 #define S_STATIC_SLOW    0
20014 #define V_STATIC_SLOW(x) ((x) << S_STATIC_SLOW)
20015 #define F_STATIC_SLOW    V_STATIC_SLOW(1U)
20016 
20017 #define A_MC_CORE_PCTL_STAT 0x7528
20018 
20019 #define S_PCTL_ACCESS_STAT    0
20020 #define M_PCTL_ACCESS_STAT    0x7U
20021 #define V_PCTL_ACCESS_STAT(x) ((x) << S_PCTL_ACCESS_STAT)
20022 #define G_PCTL_ACCESS_STAT(x) (((x) >> S_PCTL_ACCESS_STAT) & M_PCTL_ACCESS_STAT)
20023 
20024 #define A_MC_DEBUG_CNT 0x752c
20025 
20026 #define S_WDATA_OCNT    8
20027 #define M_WDATA_OCNT    0x1fU
20028 #define V_WDATA_OCNT(x) ((x) << S_WDATA_OCNT)
20029 #define G_WDATA_OCNT(x) (((x) >> S_WDATA_OCNT) & M_WDATA_OCNT)
20030 
20031 #define S_RDATA_OCNT    0
20032 #define M_RDATA_OCNT    0x1fU
20033 #define V_RDATA_OCNT(x) ((x) << S_RDATA_OCNT)
20034 #define G_RDATA_OCNT(x) (((x) >> S_RDATA_OCNT) & M_RDATA_OCNT)
20035 
20036 #define A_MC_BONUS 0x7530
20037 #define A_MC_BIST_CMD 0x7600
20038 
20039 #define S_START_BIST    31
20040 #define V_START_BIST(x) ((x) << S_START_BIST)
20041 #define F_START_BIST    V_START_BIST(1U)
20042 
20043 #define S_BIST_CMD_GAP    8
20044 #define M_BIST_CMD_GAP    0xffU
20045 #define V_BIST_CMD_GAP(x) ((x) << S_BIST_CMD_GAP)
20046 #define G_BIST_CMD_GAP(x) (((x) >> S_BIST_CMD_GAP) & M_BIST_CMD_GAP)
20047 
20048 #define S_BIST_OPCODE    0
20049 #define M_BIST_OPCODE    0x3U
20050 #define V_BIST_OPCODE(x) ((x) << S_BIST_OPCODE)
20051 #define G_BIST_OPCODE(x) (((x) >> S_BIST_OPCODE) & M_BIST_OPCODE)
20052 
20053 #define A_MC_BIST_CMD_ADDR 0x7604
20054 #define A_MC_BIST_CMD_LEN 0x7608
20055 #define A_MC_BIST_DATA_PATTERN 0x760c
20056 
20057 #define S_BIST_DATA_TYPE    0
20058 #define M_BIST_DATA_TYPE    0xfU
20059 #define V_BIST_DATA_TYPE(x) ((x) << S_BIST_DATA_TYPE)
20060 #define G_BIST_DATA_TYPE(x) (((x) >> S_BIST_DATA_TYPE) & M_BIST_DATA_TYPE)
20061 
20062 #define A_MC_BIST_USER_WDATA0 0x7614
20063 #define A_MC_BIST_USER_WDATA1 0x7618
20064 #define A_MC_BIST_USER_WDATA2 0x761c
20065 
20066 #define S_USER_DATA2    0
20067 #define M_USER_DATA2    0xffU
20068 #define V_USER_DATA2(x) ((x) << S_USER_DATA2)
20069 #define G_USER_DATA2(x) (((x) >> S_USER_DATA2) & M_USER_DATA2)
20070 
20071 #define A_MC_BIST_NUM_ERR 0x7680
20072 #define A_MC_BIST_ERR_FIRST_ADDR 0x7684
20073 #define A_MC_BIST_STATUS_RDATA 0x7688
20074 
20075 /* registers for module MA */
20076 #define MA_BASE_ADDR 0x7700
20077 
20078 #define A_MA_CLIENT0_RD_LATENCY_THRESHOLD 0x7700
20079 
20080 #define S_THRESHOLD1    17
20081 #define M_THRESHOLD1    0x7fffU
20082 #define V_THRESHOLD1(x) ((x) << S_THRESHOLD1)
20083 #define G_THRESHOLD1(x) (((x) >> S_THRESHOLD1) & M_THRESHOLD1)
20084 
20085 #define S_THRESHOLD1_EN    16
20086 #define V_THRESHOLD1_EN(x) ((x) << S_THRESHOLD1_EN)
20087 #define F_THRESHOLD1_EN    V_THRESHOLD1_EN(1U)
20088 
20089 #define S_THRESHOLD0    1
20090 #define M_THRESHOLD0    0x7fffU
20091 #define V_THRESHOLD0(x) ((x) << S_THRESHOLD0)
20092 #define G_THRESHOLD0(x) (((x) >> S_THRESHOLD0) & M_THRESHOLD0)
20093 
20094 #define S_THRESHOLD0_EN    0
20095 #define V_THRESHOLD0_EN(x) ((x) << S_THRESHOLD0_EN)
20096 #define F_THRESHOLD0_EN    V_THRESHOLD0_EN(1U)
20097 
20098 #define A_MA_CLIENT0_PR_THRESHOLD 0x7700
20099 
20100 #define S_T7_THRESHOLD1_EN    31
20101 #define V_T7_THRESHOLD1_EN(x) ((x) << S_T7_THRESHOLD1_EN)
20102 #define F_T7_THRESHOLD1_EN    V_T7_THRESHOLD1_EN(1U)
20103 
20104 #define S_T7_THRESHOLD1    16
20105 #define M_T7_THRESHOLD1    0x7fffU
20106 #define V_T7_THRESHOLD1(x) ((x) << S_T7_THRESHOLD1)
20107 #define G_T7_THRESHOLD1(x) (((x) >> S_T7_THRESHOLD1) & M_T7_THRESHOLD1)
20108 
20109 #define S_T7_THRESHOLD0_EN    15
20110 #define V_T7_THRESHOLD0_EN(x) ((x) << S_T7_THRESHOLD0_EN)
20111 #define F_T7_THRESHOLD0_EN    V_T7_THRESHOLD0_EN(1U)
20112 
20113 #define S_T7_THRESHOLD0    0
20114 #define M_T7_THRESHOLD0    0x7fffU
20115 #define V_T7_THRESHOLD0(x) ((x) << S_T7_THRESHOLD0)
20116 #define G_T7_THRESHOLD0(x) (((x) >> S_T7_THRESHOLD0) & M_T7_THRESHOLD0)
20117 
20118 #define A_MA_CLIENT0_WR_LATENCY_THRESHOLD 0x7704
20119 #define A_MA_CLIENT0_CR_THRESHOLD 0x7704
20120 
20121 #define S_CREDITSHAPER_EN    31
20122 #define V_CREDITSHAPER_EN(x) ((x) << S_CREDITSHAPER_EN)
20123 #define F_CREDITSHAPER_EN    V_CREDITSHAPER_EN(1U)
20124 
20125 #define S_CREDIT_MAX    16
20126 #define M_CREDIT_MAX    0xfffU
20127 #define V_CREDIT_MAX(x) ((x) << S_CREDIT_MAX)
20128 #define G_CREDIT_MAX(x) (((x) >> S_CREDIT_MAX) & M_CREDIT_MAX)
20129 
20130 #define S_CREDIT_VAL    0
20131 #define M_CREDIT_VAL    0xfffU
20132 #define V_CREDIT_VAL(x) ((x) << S_CREDIT_VAL)
20133 #define G_CREDIT_VAL(x) (((x) >> S_CREDIT_VAL) & M_CREDIT_VAL)
20134 
20135 #define A_MA_CLIENT1_RD_LATENCY_THRESHOLD 0x7708
20136 #define A_MA_CLIENT1_PR_THRESHOLD 0x7708
20137 #define A_MA_CLIENT1_WR_LATENCY_THRESHOLD 0x770c
20138 #define A_MA_CLIENT1_CR_THRESHOLD 0x770c
20139 #define A_MA_CLIENT2_RD_LATENCY_THRESHOLD 0x7710
20140 #define A_MA_CLIENT2_PR_THRESHOLD 0x7710
20141 #define A_MA_CLIENT2_WR_LATENCY_THRESHOLD 0x7714
20142 #define A_MA_CLIENT2_CR_THRESHOLD 0x7714
20143 #define A_MA_CLIENT3_RD_LATENCY_THRESHOLD 0x7718
20144 #define A_MA_CLIENT3_PR_THRESHOLD 0x7718
20145 #define A_MA_CLIENT3_WR_LATENCY_THRESHOLD 0x771c
20146 #define A_MA_CLIENT3_CR_THRESHOLD 0x771c
20147 #define A_MA_CLIENT4_RD_LATENCY_THRESHOLD 0x7720
20148 #define A_MA_CLIENT4_PR_THRESHOLD 0x7720
20149 #define A_MA_CLIENT4_WR_LATENCY_THRESHOLD 0x7724
20150 #define A_MA_CLIENT4_CR_THRESHOLD 0x7724
20151 #define A_MA_CLIENT5_RD_LATENCY_THRESHOLD 0x7728
20152 #define A_MA_CLIENT5_PR_THRESHOLD 0x7728
20153 #define A_MA_CLIENT5_WR_LATENCY_THRESHOLD 0x772c
20154 #define A_MA_CLIENT5_CR_THRESHOLD 0x772c
20155 #define A_MA_CLIENT6_RD_LATENCY_THRESHOLD 0x7730
20156 #define A_MA_CLIENT6_PR_THRESHOLD 0x7730
20157 #define A_MA_CLIENT6_WR_LATENCY_THRESHOLD 0x7734
20158 #define A_MA_CLIENT6_CR_THRESHOLD 0x7734
20159 #define A_MA_CLIENT7_RD_LATENCY_THRESHOLD 0x7738
20160 #define A_MA_CLIENT7_PR_THRESHOLD 0x7738
20161 #define A_MA_CLIENT7_WR_LATENCY_THRESHOLD 0x773c
20162 #define A_MA_CLIENT7_CR_THRESHOLD 0x773c
20163 #define A_MA_CLIENT8_RD_LATENCY_THRESHOLD 0x7740
20164 #define A_MA_CLIENT8_PR_THRESHOLD 0x7740
20165 #define A_MA_CLIENT8_WR_LATENCY_THRESHOLD 0x7744
20166 #define A_MA_CLIENT8_CR_THRESHOLD 0x7744
20167 #define A_MA_CLIENT9_RD_LATENCY_THRESHOLD 0x7748
20168 #define A_MA_CLIENT9_PR_THRESHOLD 0x7748
20169 #define A_MA_CLIENT9_WR_LATENCY_THRESHOLD 0x774c
20170 #define A_MA_CLIENT9_CR_THRESHOLD 0x774c
20171 #define A_MA_CLIENT10_RD_LATENCY_THRESHOLD 0x7750
20172 #define A_MA_CLIENT10_PR_THRESHOLD 0x7750
20173 #define A_MA_CLIENT10_WR_LATENCY_THRESHOLD 0x7754
20174 #define A_MA_CLIENT10_CR_THRESHOLD 0x7754
20175 #define A_MA_CLIENT11_RD_LATENCY_THRESHOLD 0x7758
20176 #define A_MA_CLIENT11_PR_THRESHOLD 0x7758
20177 #define A_MA_CLIENT11_WR_LATENCY_THRESHOLD 0x775c
20178 #define A_MA_CLIENT11_CR_THRESHOLD 0x775c
20179 #define A_MA_CLIENT12_RD_LATENCY_THRESHOLD 0x7760
20180 #define A_MA_CLIENT12_PR_THRESHOLD 0x7760
20181 #define A_MA_CLIENT12_WR_LATENCY_THRESHOLD 0x7764
20182 #define A_MA_CLIENT12_CR_THRESHOLD 0x7764
20183 #define A_MA_SGE_TH0_DEBUG_CNT 0x7768
20184 
20185 #define S_DBG_READ_DATA_CNT    24
20186 #define M_DBG_READ_DATA_CNT    0xffU
20187 #define V_DBG_READ_DATA_CNT(x) ((x) << S_DBG_READ_DATA_CNT)
20188 #define G_DBG_READ_DATA_CNT(x) (((x) >> S_DBG_READ_DATA_CNT) & M_DBG_READ_DATA_CNT)
20189 
20190 #define S_DBG_READ_REQ_CNT    16
20191 #define M_DBG_READ_REQ_CNT    0xffU
20192 #define V_DBG_READ_REQ_CNT(x) ((x) << S_DBG_READ_REQ_CNT)
20193 #define G_DBG_READ_REQ_CNT(x) (((x) >> S_DBG_READ_REQ_CNT) & M_DBG_READ_REQ_CNT)
20194 
20195 #define S_DBG_WRITE_DATA_CNT    8
20196 #define M_DBG_WRITE_DATA_CNT    0xffU
20197 #define V_DBG_WRITE_DATA_CNT(x) ((x) << S_DBG_WRITE_DATA_CNT)
20198 #define G_DBG_WRITE_DATA_CNT(x) (((x) >> S_DBG_WRITE_DATA_CNT) & M_DBG_WRITE_DATA_CNT)
20199 
20200 #define S_DBG_WRITE_REQ_CNT    0
20201 #define M_DBG_WRITE_REQ_CNT    0xffU
20202 #define V_DBG_WRITE_REQ_CNT(x) ((x) << S_DBG_WRITE_REQ_CNT)
20203 #define G_DBG_WRITE_REQ_CNT(x) (((x) >> S_DBG_WRITE_REQ_CNT) & M_DBG_WRITE_REQ_CNT)
20204 
20205 #define A_MA_SGE_TH1_DEBUG_CNT 0x776c
20206 #define A_MA_ULPTX_DEBUG_CNT 0x7770
20207 #define A_MA_ULPRX_DEBUG_CNT 0x7774
20208 #define A_MA_ULPTXRX_DEBUG_CNT 0x7778
20209 #define A_MA_TP_TH0_DEBUG_CNT 0x777c
20210 #define A_MA_TP_TH1_DEBUG_CNT 0x7780
20211 #define A_MA_LE_DEBUG_CNT 0x7784
20212 #define A_MA_CIM_DEBUG_CNT 0x7788
20213 #define A_MA_CIM_TH0_DEBUG_CNT 0x7788
20214 #define A_MA_PCIE_DEBUG_CNT 0x778c
20215 #define A_MA_PMTX_DEBUG_CNT 0x7790
20216 #define A_MA_PMRX_DEBUG_CNT 0x7794
20217 #define A_MA_HMA_DEBUG_CNT 0x7798
20218 #define A_MA_COR_ERROR_ENABLE1 0x779c
20219 
20220 #define S_ARB4_COR_WRQUEUE_ERROR_EN    9
20221 #define V_ARB4_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB4_COR_WRQUEUE_ERROR_EN)
20222 #define F_ARB4_COR_WRQUEUE_ERROR_EN    V_ARB4_COR_WRQUEUE_ERROR_EN(1U)
20223 
20224 #define S_ARB3_COR_WRQUEUE_ERROR_EN    8
20225 #define V_ARB3_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB3_COR_WRQUEUE_ERROR_EN)
20226 #define F_ARB3_COR_WRQUEUE_ERROR_EN    V_ARB3_COR_WRQUEUE_ERROR_EN(1U)
20227 
20228 #define S_ARB2_COR_WRQUEUE_ERROR_EN    7
20229 #define V_ARB2_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB2_COR_WRQUEUE_ERROR_EN)
20230 #define F_ARB2_COR_WRQUEUE_ERROR_EN    V_ARB2_COR_WRQUEUE_ERROR_EN(1U)
20231 
20232 #define S_ARB1_COR_WRQUEUE_ERROR_EN    6
20233 #define V_ARB1_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB1_COR_WRQUEUE_ERROR_EN)
20234 #define F_ARB1_COR_WRQUEUE_ERROR_EN    V_ARB1_COR_WRQUEUE_ERROR_EN(1U)
20235 
20236 #define S_ARB0_COR_WRQUEUE_ERROR_EN    5
20237 #define V_ARB0_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB0_COR_WRQUEUE_ERROR_EN)
20238 #define F_ARB0_COR_WRQUEUE_ERROR_EN    V_ARB0_COR_WRQUEUE_ERROR_EN(1U)
20239 
20240 #define S_ARB4_COR_RDQUEUE_ERROR_EN    4
20241 #define V_ARB4_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB4_COR_RDQUEUE_ERROR_EN)
20242 #define F_ARB4_COR_RDQUEUE_ERROR_EN    V_ARB4_COR_RDQUEUE_ERROR_EN(1U)
20243 
20244 #define S_ARB3_COR_RDQUEUE_ERROR_EN    3
20245 #define V_ARB3_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB3_COR_RDQUEUE_ERROR_EN)
20246 #define F_ARB3_COR_RDQUEUE_ERROR_EN    V_ARB3_COR_RDQUEUE_ERROR_EN(1U)
20247 
20248 #define S_ARB2_COR_RDQUEUE_ERROR_EN    2
20249 #define V_ARB2_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB2_COR_RDQUEUE_ERROR_EN)
20250 #define F_ARB2_COR_RDQUEUE_ERROR_EN    V_ARB2_COR_RDQUEUE_ERROR_EN(1U)
20251 
20252 #define S_ARB1_COR_RDQUEUE_ERROR_EN    1
20253 #define V_ARB1_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB1_COR_RDQUEUE_ERROR_EN)
20254 #define F_ARB1_COR_RDQUEUE_ERROR_EN    V_ARB1_COR_RDQUEUE_ERROR_EN(1U)
20255 
20256 #define S_ARB0_COR_RDQUEUE_ERROR_EN    0
20257 #define V_ARB0_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB0_COR_RDQUEUE_ERROR_EN)
20258 #define F_ARB0_COR_RDQUEUE_ERROR_EN    V_ARB0_COR_RDQUEUE_ERROR_EN(1U)
20259 
20260 #define A_MA_COR_ERROR_STATUS1 0x77a0
20261 
20262 #define S_ARB4_COR_WRQUEUE_ERROR    9
20263 #define V_ARB4_COR_WRQUEUE_ERROR(x) ((x) << S_ARB4_COR_WRQUEUE_ERROR)
20264 #define F_ARB4_COR_WRQUEUE_ERROR    V_ARB4_COR_WRQUEUE_ERROR(1U)
20265 
20266 #define S_ARB3_COR_WRQUEUE_ERROR    8
20267 #define V_ARB3_COR_WRQUEUE_ERROR(x) ((x) << S_ARB3_COR_WRQUEUE_ERROR)
20268 #define F_ARB3_COR_WRQUEUE_ERROR    V_ARB3_COR_WRQUEUE_ERROR(1U)
20269 
20270 #define S_ARB2_COR_WRQUEUE_ERROR    7
20271 #define V_ARB2_COR_WRQUEUE_ERROR(x) ((x) << S_ARB2_COR_WRQUEUE_ERROR)
20272 #define F_ARB2_COR_WRQUEUE_ERROR    V_ARB2_COR_WRQUEUE_ERROR(1U)
20273 
20274 #define S_ARB1_COR_WRQUEUE_ERROR    6
20275 #define V_ARB1_COR_WRQUEUE_ERROR(x) ((x) << S_ARB1_COR_WRQUEUE_ERROR)
20276 #define F_ARB1_COR_WRQUEUE_ERROR    V_ARB1_COR_WRQUEUE_ERROR(1U)
20277 
20278 #define S_ARB0_COR_WRQUEUE_ERROR    5
20279 #define V_ARB0_COR_WRQUEUE_ERROR(x) ((x) << S_ARB0_COR_WRQUEUE_ERROR)
20280 #define F_ARB0_COR_WRQUEUE_ERROR    V_ARB0_COR_WRQUEUE_ERROR(1U)
20281 
20282 #define S_ARB4_COR_RDQUEUE_ERROR    4
20283 #define V_ARB4_COR_RDQUEUE_ERROR(x) ((x) << S_ARB4_COR_RDQUEUE_ERROR)
20284 #define F_ARB4_COR_RDQUEUE_ERROR    V_ARB4_COR_RDQUEUE_ERROR(1U)
20285 
20286 #define S_ARB3_COR_RDQUEUE_ERROR    3
20287 #define V_ARB3_COR_RDQUEUE_ERROR(x) ((x) << S_ARB3_COR_RDQUEUE_ERROR)
20288 #define F_ARB3_COR_RDQUEUE_ERROR    V_ARB3_COR_RDQUEUE_ERROR(1U)
20289 
20290 #define S_ARB2_COR_RDQUEUE_ERROR    2
20291 #define V_ARB2_COR_RDQUEUE_ERROR(x) ((x) << S_ARB2_COR_RDQUEUE_ERROR)
20292 #define F_ARB2_COR_RDQUEUE_ERROR    V_ARB2_COR_RDQUEUE_ERROR(1U)
20293 
20294 #define S_ARB1_COR_RDQUEUE_ERROR    1
20295 #define V_ARB1_COR_RDQUEUE_ERROR(x) ((x) << S_ARB1_COR_RDQUEUE_ERROR)
20296 #define F_ARB1_COR_RDQUEUE_ERROR    V_ARB1_COR_RDQUEUE_ERROR(1U)
20297 
20298 #define S_ARB0_COR_RDQUEUE_ERROR    0
20299 #define V_ARB0_COR_RDQUEUE_ERROR(x) ((x) << S_ARB0_COR_RDQUEUE_ERROR)
20300 #define F_ARB0_COR_RDQUEUE_ERROR    V_ARB0_COR_RDQUEUE_ERROR(1U)
20301 
20302 #define A_MA_DBG_CTL 0x77a4
20303 
20304 #define S_DATAH_SEL    20
20305 #define V_DATAH_SEL(x) ((x) << S_DATAH_SEL)
20306 #define F_DATAH_SEL    V_DATAH_SEL(1U)
20307 
20308 #define S_EN_DBG    16
20309 #define V_EN_DBG(x) ((x) << S_EN_DBG)
20310 #define F_EN_DBG    V_EN_DBG(1U)
20311 
20312 #define S_T7_SEL    0
20313 #define M_T7_SEL    0xffU
20314 #define V_T7_SEL(x) ((x) << S_T7_SEL)
20315 #define G_T7_SEL(x) (((x) >> S_T7_SEL) & M_T7_SEL)
20316 
20317 #define A_MA_DBG_DATA 0x77a8
20318 #define A_MA_COR_ERROR_ENABLE2 0x77b0
20319 
20320 #define S_CL14_COR_WRQUEUE_ERROR_EN    14
20321 #define V_CL14_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL14_COR_WRQUEUE_ERROR_EN)
20322 #define F_CL14_COR_WRQUEUE_ERROR_EN    V_CL14_COR_WRQUEUE_ERROR_EN(1U)
20323 
20324 #define S_CL13_COR_WRQUEUE_ERROR_EN    13
20325 #define V_CL13_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL13_COR_WRQUEUE_ERROR_EN)
20326 #define F_CL13_COR_WRQUEUE_ERROR_EN    V_CL13_COR_WRQUEUE_ERROR_EN(1U)
20327 
20328 #define S_CL12_COR_WRQUEUE_ERROR_EN    12
20329 #define V_CL12_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL12_COR_WRQUEUE_ERROR_EN)
20330 #define F_CL12_COR_WRQUEUE_ERROR_EN    V_CL12_COR_WRQUEUE_ERROR_EN(1U)
20331 
20332 #define S_CL11_COR_WRQUEUE_ERROR_EN    11
20333 #define V_CL11_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL11_COR_WRQUEUE_ERROR_EN)
20334 #define F_CL11_COR_WRQUEUE_ERROR_EN    V_CL11_COR_WRQUEUE_ERROR_EN(1U)
20335 
20336 #define S_CL10_COR_WRQUEUE_ERROR_EN    10
20337 #define V_CL10_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL10_COR_WRQUEUE_ERROR_EN)
20338 #define F_CL10_COR_WRQUEUE_ERROR_EN    V_CL10_COR_WRQUEUE_ERROR_EN(1U)
20339 
20340 #define S_CL9_COR_WRQUEUE_ERROR_EN    9
20341 #define V_CL9_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL9_COR_WRQUEUE_ERROR_EN)
20342 #define F_CL9_COR_WRQUEUE_ERROR_EN    V_CL9_COR_WRQUEUE_ERROR_EN(1U)
20343 
20344 #define S_CL8_COR_WRQUEUE_ERROR_EN    8
20345 #define V_CL8_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL8_COR_WRQUEUE_ERROR_EN)
20346 #define F_CL8_COR_WRQUEUE_ERROR_EN    V_CL8_COR_WRQUEUE_ERROR_EN(1U)
20347 
20348 #define S_CL7_COR_WRQUEUE_ERROR_EN    7
20349 #define V_CL7_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL7_COR_WRQUEUE_ERROR_EN)
20350 #define F_CL7_COR_WRQUEUE_ERROR_EN    V_CL7_COR_WRQUEUE_ERROR_EN(1U)
20351 
20352 #define S_CL6_COR_WRQUEUE_ERROR_EN    6
20353 #define V_CL6_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL6_COR_WRQUEUE_ERROR_EN)
20354 #define F_CL6_COR_WRQUEUE_ERROR_EN    V_CL6_COR_WRQUEUE_ERROR_EN(1U)
20355 
20356 #define S_CL5_COR_WRQUEUE_ERROR_EN    5
20357 #define V_CL5_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL5_COR_WRQUEUE_ERROR_EN)
20358 #define F_CL5_COR_WRQUEUE_ERROR_EN    V_CL5_COR_WRQUEUE_ERROR_EN(1U)
20359 
20360 #define S_CL4_COR_WRQUEUE_ERROR_EN    4
20361 #define V_CL4_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL4_COR_WRQUEUE_ERROR_EN)
20362 #define F_CL4_COR_WRQUEUE_ERROR_EN    V_CL4_COR_WRQUEUE_ERROR_EN(1U)
20363 
20364 #define S_CL3_COR_WRQUEUE_ERROR_EN    3
20365 #define V_CL3_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL3_COR_WRQUEUE_ERROR_EN)
20366 #define F_CL3_COR_WRQUEUE_ERROR_EN    V_CL3_COR_WRQUEUE_ERROR_EN(1U)
20367 
20368 #define S_CL2_COR_WRQUEUE_ERROR_EN    2
20369 #define V_CL2_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL2_COR_WRQUEUE_ERROR_EN)
20370 #define F_CL2_COR_WRQUEUE_ERROR_EN    V_CL2_COR_WRQUEUE_ERROR_EN(1U)
20371 
20372 #define S_CL1_COR_WRQUEUE_ERROR_EN    1
20373 #define V_CL1_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL1_COR_WRQUEUE_ERROR_EN)
20374 #define F_CL1_COR_WRQUEUE_ERROR_EN    V_CL1_COR_WRQUEUE_ERROR_EN(1U)
20375 
20376 #define S_CL0_COR_WRQUEUE_ERROR_EN    0
20377 #define V_CL0_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL0_COR_WRQUEUE_ERROR_EN)
20378 #define F_CL0_COR_WRQUEUE_ERROR_EN    V_CL0_COR_WRQUEUE_ERROR_EN(1U)
20379 
20380 #define A_MA_COR_ERROR_STATUS2 0x77b4
20381 
20382 #define S_CL14_COR_WRQUEUE_ERROR    14
20383 #define V_CL14_COR_WRQUEUE_ERROR(x) ((x) << S_CL14_COR_WRQUEUE_ERROR)
20384 #define F_CL14_COR_WRQUEUE_ERROR    V_CL14_COR_WRQUEUE_ERROR(1U)
20385 
20386 #define S_CL13_COR_WRQUEUE_ERROR    13
20387 #define V_CL13_COR_WRQUEUE_ERROR(x) ((x) << S_CL13_COR_WRQUEUE_ERROR)
20388 #define F_CL13_COR_WRQUEUE_ERROR    V_CL13_COR_WRQUEUE_ERROR(1U)
20389 
20390 #define S_CL12_COR_WRQUEUE_ERROR    12
20391 #define V_CL12_COR_WRQUEUE_ERROR(x) ((x) << S_CL12_COR_WRQUEUE_ERROR)
20392 #define F_CL12_COR_WRQUEUE_ERROR    V_CL12_COR_WRQUEUE_ERROR(1U)
20393 
20394 #define S_CL11_COR_WRQUEUE_ERROR    11
20395 #define V_CL11_COR_WRQUEUE_ERROR(x) ((x) << S_CL11_COR_WRQUEUE_ERROR)
20396 #define F_CL11_COR_WRQUEUE_ERROR    V_CL11_COR_WRQUEUE_ERROR(1U)
20397 
20398 #define S_CL10_COR_WRQUEUE_ERROR    10
20399 #define V_CL10_COR_WRQUEUE_ERROR(x) ((x) << S_CL10_COR_WRQUEUE_ERROR)
20400 #define F_CL10_COR_WRQUEUE_ERROR    V_CL10_COR_WRQUEUE_ERROR(1U)
20401 
20402 #define S_CL9_COR_WRQUEUE_ERROR    9
20403 #define V_CL9_COR_WRQUEUE_ERROR(x) ((x) << S_CL9_COR_WRQUEUE_ERROR)
20404 #define F_CL9_COR_WRQUEUE_ERROR    V_CL9_COR_WRQUEUE_ERROR(1U)
20405 
20406 #define S_CL8_COR_WRQUEUE_ERROR    8
20407 #define V_CL8_COR_WRQUEUE_ERROR(x) ((x) << S_CL8_COR_WRQUEUE_ERROR)
20408 #define F_CL8_COR_WRQUEUE_ERROR    V_CL8_COR_WRQUEUE_ERROR(1U)
20409 
20410 #define S_CL7_COR_WRQUEUE_ERROR    7
20411 #define V_CL7_COR_WRQUEUE_ERROR(x) ((x) << S_CL7_COR_WRQUEUE_ERROR)
20412 #define F_CL7_COR_WRQUEUE_ERROR    V_CL7_COR_WRQUEUE_ERROR(1U)
20413 
20414 #define S_CL6_COR_WRQUEUE_ERROR    6
20415 #define V_CL6_COR_WRQUEUE_ERROR(x) ((x) << S_CL6_COR_WRQUEUE_ERROR)
20416 #define F_CL6_COR_WRQUEUE_ERROR    V_CL6_COR_WRQUEUE_ERROR(1U)
20417 
20418 #define S_CL5_COR_WRQUEUE_ERROR    5
20419 #define V_CL5_COR_WRQUEUE_ERROR(x) ((x) << S_CL5_COR_WRQUEUE_ERROR)
20420 #define F_CL5_COR_WRQUEUE_ERROR    V_CL5_COR_WRQUEUE_ERROR(1U)
20421 
20422 #define S_CL4_COR_WRQUEUE_ERROR    4
20423 #define V_CL4_COR_WRQUEUE_ERROR(x) ((x) << S_CL4_COR_WRQUEUE_ERROR)
20424 #define F_CL4_COR_WRQUEUE_ERROR    V_CL4_COR_WRQUEUE_ERROR(1U)
20425 
20426 #define S_CL3_COR_WRQUEUE_ERROR    3
20427 #define V_CL3_COR_WRQUEUE_ERROR(x) ((x) << S_CL3_COR_WRQUEUE_ERROR)
20428 #define F_CL3_COR_WRQUEUE_ERROR    V_CL3_COR_WRQUEUE_ERROR(1U)
20429 
20430 #define S_CL2_COR_WRQUEUE_ERROR    2
20431 #define V_CL2_COR_WRQUEUE_ERROR(x) ((x) << S_CL2_COR_WRQUEUE_ERROR)
20432 #define F_CL2_COR_WRQUEUE_ERROR    V_CL2_COR_WRQUEUE_ERROR(1U)
20433 
20434 #define S_CL1_COR_WRQUEUE_ERROR    1
20435 #define V_CL1_COR_WRQUEUE_ERROR(x) ((x) << S_CL1_COR_WRQUEUE_ERROR)
20436 #define F_CL1_COR_WRQUEUE_ERROR    V_CL1_COR_WRQUEUE_ERROR(1U)
20437 
20438 #define S_CL0_COR_WRQUEUE_ERROR    0
20439 #define V_CL0_COR_WRQUEUE_ERROR(x) ((x) << S_CL0_COR_WRQUEUE_ERROR)
20440 #define F_CL0_COR_WRQUEUE_ERROR    V_CL0_COR_WRQUEUE_ERROR(1U)
20441 
20442 #define A_MA_COR_ERROR_ENABLE3 0x77b8
20443 
20444 #define S_CL14_COR_RDQUEUE_ERROR_EN    14
20445 #define V_CL14_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL14_COR_RDQUEUE_ERROR_EN)
20446 #define F_CL14_COR_RDQUEUE_ERROR_EN    V_CL14_COR_RDQUEUE_ERROR_EN(1U)
20447 
20448 #define S_CL13_COR_RDQUEUE_ERROR_EN    13
20449 #define V_CL13_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL13_COR_RDQUEUE_ERROR_EN)
20450 #define F_CL13_COR_RDQUEUE_ERROR_EN    V_CL13_COR_RDQUEUE_ERROR_EN(1U)
20451 
20452 #define S_CL12_COR_RDQUEUE_ERROR_EN    12
20453 #define V_CL12_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL12_COR_RDQUEUE_ERROR_EN)
20454 #define F_CL12_COR_RDQUEUE_ERROR_EN    V_CL12_COR_RDQUEUE_ERROR_EN(1U)
20455 
20456 #define S_CL11_COR_RDQUEUE_ERROR_EN    11
20457 #define V_CL11_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL11_COR_RDQUEUE_ERROR_EN)
20458 #define F_CL11_COR_RDQUEUE_ERROR_EN    V_CL11_COR_RDQUEUE_ERROR_EN(1U)
20459 
20460 #define S_CL10_COR_RDQUEUE_ERROR_EN    10
20461 #define V_CL10_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL10_COR_RDQUEUE_ERROR_EN)
20462 #define F_CL10_COR_RDQUEUE_ERROR_EN    V_CL10_COR_RDQUEUE_ERROR_EN(1U)
20463 
20464 #define S_CL9_COR_RDQUEUE_ERROR_EN    9
20465 #define V_CL9_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL9_COR_RDQUEUE_ERROR_EN)
20466 #define F_CL9_COR_RDQUEUE_ERROR_EN    V_CL9_COR_RDQUEUE_ERROR_EN(1U)
20467 
20468 #define S_CL8_COR_RDQUEUE_ERROR_EN    8
20469 #define V_CL8_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL8_COR_RDQUEUE_ERROR_EN)
20470 #define F_CL8_COR_RDQUEUE_ERROR_EN    V_CL8_COR_RDQUEUE_ERROR_EN(1U)
20471 
20472 #define S_CL7_COR_RDQUEUE_ERROR_EN    7
20473 #define V_CL7_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL7_COR_RDQUEUE_ERROR_EN)
20474 #define F_CL7_COR_RDQUEUE_ERROR_EN    V_CL7_COR_RDQUEUE_ERROR_EN(1U)
20475 
20476 #define S_CL6_COR_RDQUEUE_ERROR_EN    6
20477 #define V_CL6_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL6_COR_RDQUEUE_ERROR_EN)
20478 #define F_CL6_COR_RDQUEUE_ERROR_EN    V_CL6_COR_RDQUEUE_ERROR_EN(1U)
20479 
20480 #define S_CL5_COR_RDQUEUE_ERROR_EN    5
20481 #define V_CL5_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL5_COR_RDQUEUE_ERROR_EN)
20482 #define F_CL5_COR_RDQUEUE_ERROR_EN    V_CL5_COR_RDQUEUE_ERROR_EN(1U)
20483 
20484 #define S_CL4_COR_RDQUEUE_ERROR_EN    4
20485 #define V_CL4_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL4_COR_RDQUEUE_ERROR_EN)
20486 #define F_CL4_COR_RDQUEUE_ERROR_EN    V_CL4_COR_RDQUEUE_ERROR_EN(1U)
20487 
20488 #define S_CL3_COR_RDQUEUE_ERROR_EN    3
20489 #define V_CL3_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL3_COR_RDQUEUE_ERROR_EN)
20490 #define F_CL3_COR_RDQUEUE_ERROR_EN    V_CL3_COR_RDQUEUE_ERROR_EN(1U)
20491 
20492 #define S_CL2_COR_RDQUEUE_ERROR_EN    2
20493 #define V_CL2_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL2_COR_RDQUEUE_ERROR_EN)
20494 #define F_CL2_COR_RDQUEUE_ERROR_EN    V_CL2_COR_RDQUEUE_ERROR_EN(1U)
20495 
20496 #define S_CL1_COR_RDQUEUE_ERROR_EN    1
20497 #define V_CL1_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL1_COR_RDQUEUE_ERROR_EN)
20498 #define F_CL1_COR_RDQUEUE_ERROR_EN    V_CL1_COR_RDQUEUE_ERROR_EN(1U)
20499 
20500 #define S_CL0_COR_RDQUEUE_ERROR_EN    0
20501 #define V_CL0_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL0_COR_RDQUEUE_ERROR_EN)
20502 #define F_CL0_COR_RDQUEUE_ERROR_EN    V_CL0_COR_RDQUEUE_ERROR_EN(1U)
20503 
20504 #define A_MA_COR_ERROR_STATUS3 0x77bc
20505 
20506 #define S_CL14_COR_RDQUEUE_ERROR    14
20507 #define V_CL14_COR_RDQUEUE_ERROR(x) ((x) << S_CL14_COR_RDQUEUE_ERROR)
20508 #define F_CL14_COR_RDQUEUE_ERROR    V_CL14_COR_RDQUEUE_ERROR(1U)
20509 
20510 #define S_CL13_COR_RDQUEUE_ERROR    13
20511 #define V_CL13_COR_RDQUEUE_ERROR(x) ((x) << S_CL13_COR_RDQUEUE_ERROR)
20512 #define F_CL13_COR_RDQUEUE_ERROR    V_CL13_COR_RDQUEUE_ERROR(1U)
20513 
20514 #define S_CL12_COR_RDQUEUE_ERROR    12
20515 #define V_CL12_COR_RDQUEUE_ERROR(x) ((x) << S_CL12_COR_RDQUEUE_ERROR)
20516 #define F_CL12_COR_RDQUEUE_ERROR    V_CL12_COR_RDQUEUE_ERROR(1U)
20517 
20518 #define S_CL11_COR_RDQUEUE_ERROR    11
20519 #define V_CL11_COR_RDQUEUE_ERROR(x) ((x) << S_CL11_COR_RDQUEUE_ERROR)
20520 #define F_CL11_COR_RDQUEUE_ERROR    V_CL11_COR_RDQUEUE_ERROR(1U)
20521 
20522 #define S_CL10_COR_RDQUEUE_ERROR    10
20523 #define V_CL10_COR_RDQUEUE_ERROR(x) ((x) << S_CL10_COR_RDQUEUE_ERROR)
20524 #define F_CL10_COR_RDQUEUE_ERROR    V_CL10_COR_RDQUEUE_ERROR(1U)
20525 
20526 #define S_CL9_COR_RDQUEUE_ERROR    9
20527 #define V_CL9_COR_RDQUEUE_ERROR(x) ((x) << S_CL9_COR_RDQUEUE_ERROR)
20528 #define F_CL9_COR_RDQUEUE_ERROR    V_CL9_COR_RDQUEUE_ERROR(1U)
20529 
20530 #define S_CL8_COR_RDQUEUE_ERROR    8
20531 #define V_CL8_COR_RDQUEUE_ERROR(x) ((x) << S_CL8_COR_RDQUEUE_ERROR)
20532 #define F_CL8_COR_RDQUEUE_ERROR    V_CL8_COR_RDQUEUE_ERROR(1U)
20533 
20534 #define S_CL7_COR_RDQUEUE_ERROR    7
20535 #define V_CL7_COR_RDQUEUE_ERROR(x) ((x) << S_CL7_COR_RDQUEUE_ERROR)
20536 #define F_CL7_COR_RDQUEUE_ERROR    V_CL7_COR_RDQUEUE_ERROR(1U)
20537 
20538 #define S_CL6_COR_RDQUEUE_ERROR    6
20539 #define V_CL6_COR_RDQUEUE_ERROR(x) ((x) << S_CL6_COR_RDQUEUE_ERROR)
20540 #define F_CL6_COR_RDQUEUE_ERROR    V_CL6_COR_RDQUEUE_ERROR(1U)
20541 
20542 #define S_CL5_COR_RDQUEUE_ERROR    5
20543 #define V_CL5_COR_RDQUEUE_ERROR(x) ((x) << S_CL5_COR_RDQUEUE_ERROR)
20544 #define F_CL5_COR_RDQUEUE_ERROR    V_CL5_COR_RDQUEUE_ERROR(1U)
20545 
20546 #define S_CL4_COR_RDQUEUE_ERROR    4
20547 #define V_CL4_COR_RDQUEUE_ERROR(x) ((x) << S_CL4_COR_RDQUEUE_ERROR)
20548 #define F_CL4_COR_RDQUEUE_ERROR    V_CL4_COR_RDQUEUE_ERROR(1U)
20549 
20550 #define S_CL3_COR_RDQUEUE_ERROR    3
20551 #define V_CL3_COR_RDQUEUE_ERROR(x) ((x) << S_CL3_COR_RDQUEUE_ERROR)
20552 #define F_CL3_COR_RDQUEUE_ERROR    V_CL3_COR_RDQUEUE_ERROR(1U)
20553 
20554 #define S_CL2_COR_RDQUEUE_ERROR    2
20555 #define V_CL2_COR_RDQUEUE_ERROR(x) ((x) << S_CL2_COR_RDQUEUE_ERROR)
20556 #define F_CL2_COR_RDQUEUE_ERROR    V_CL2_COR_RDQUEUE_ERROR(1U)
20557 
20558 #define S_CL1_COR_RDQUEUE_ERROR    1
20559 #define V_CL1_COR_RDQUEUE_ERROR(x) ((x) << S_CL1_COR_RDQUEUE_ERROR)
20560 #define F_CL1_COR_RDQUEUE_ERROR    V_CL1_COR_RDQUEUE_ERROR(1U)
20561 
20562 #define S_CL0_COR_RDQUEUE_ERROR    0
20563 #define V_CL0_COR_RDQUEUE_ERROR(x) ((x) << S_CL0_COR_RDQUEUE_ERROR)
20564 #define F_CL0_COR_RDQUEUE_ERROR    V_CL0_COR_RDQUEUE_ERROR(1U)
20565 
20566 #define A_MA_EDRAM0_BAR 0x77c0
20567 
20568 #define S_EDRAM0_BASE    16
20569 #define M_EDRAM0_BASE    0xfffU
20570 #define V_EDRAM0_BASE(x) ((x) << S_EDRAM0_BASE)
20571 #define G_EDRAM0_BASE(x) (((x) >> S_EDRAM0_BASE) & M_EDRAM0_BASE)
20572 
20573 #define S_EDRAM0_SIZE    0
20574 #define M_EDRAM0_SIZE    0xfffU
20575 #define V_EDRAM0_SIZE(x) ((x) << S_EDRAM0_SIZE)
20576 #define G_EDRAM0_SIZE(x) (((x) >> S_EDRAM0_SIZE) & M_EDRAM0_SIZE)
20577 
20578 #define S_T7_EDRAM0_BASE    16
20579 #define M_T7_EDRAM0_BASE    0xffffU
20580 #define V_T7_EDRAM0_BASE(x) ((x) << S_T7_EDRAM0_BASE)
20581 #define G_T7_EDRAM0_BASE(x) (((x) >> S_T7_EDRAM0_BASE) & M_T7_EDRAM0_BASE)
20582 
20583 #define S_T7_EDRAM0_SIZE    0
20584 #define M_T7_EDRAM0_SIZE    0xffffU
20585 #define V_T7_EDRAM0_SIZE(x) ((x) << S_T7_EDRAM0_SIZE)
20586 #define G_T7_EDRAM0_SIZE(x) (((x) >> S_T7_EDRAM0_SIZE) & M_T7_EDRAM0_SIZE)
20587 
20588 #define A_MA_EDRAM1_BAR 0x77c4
20589 
20590 #define S_EDRAM1_BASE    16
20591 #define M_EDRAM1_BASE    0xfffU
20592 #define V_EDRAM1_BASE(x) ((x) << S_EDRAM1_BASE)
20593 #define G_EDRAM1_BASE(x) (((x) >> S_EDRAM1_BASE) & M_EDRAM1_BASE)
20594 
20595 #define S_EDRAM1_SIZE    0
20596 #define M_EDRAM1_SIZE    0xfffU
20597 #define V_EDRAM1_SIZE(x) ((x) << S_EDRAM1_SIZE)
20598 #define G_EDRAM1_SIZE(x) (((x) >> S_EDRAM1_SIZE) & M_EDRAM1_SIZE)
20599 
20600 #define S_T7_EDRAM1_BASE    16
20601 #define M_T7_EDRAM1_BASE    0xffffU
20602 #define V_T7_EDRAM1_BASE(x) ((x) << S_T7_EDRAM1_BASE)
20603 #define G_T7_EDRAM1_BASE(x) (((x) >> S_T7_EDRAM1_BASE) & M_T7_EDRAM1_BASE)
20604 
20605 #define S_T7_EDRAM1_SIZE    0
20606 #define M_T7_EDRAM1_SIZE    0xffffU
20607 #define V_T7_EDRAM1_SIZE(x) ((x) << S_T7_EDRAM1_SIZE)
20608 #define G_T7_EDRAM1_SIZE(x) (((x) >> S_T7_EDRAM1_SIZE) & M_T7_EDRAM1_SIZE)
20609 
20610 #define A_MA_EXT_MEMORY_BAR 0x77c8
20611 
20612 #define S_EXT_MEM_BASE    16
20613 #define M_EXT_MEM_BASE    0xfffU
20614 #define V_EXT_MEM_BASE(x) ((x) << S_EXT_MEM_BASE)
20615 #define G_EXT_MEM_BASE(x) (((x) >> S_EXT_MEM_BASE) & M_EXT_MEM_BASE)
20616 
20617 #define S_EXT_MEM_SIZE    0
20618 #define M_EXT_MEM_SIZE    0xfffU
20619 #define V_EXT_MEM_SIZE(x) ((x) << S_EXT_MEM_SIZE)
20620 #define G_EXT_MEM_SIZE(x) (((x) >> S_EXT_MEM_SIZE) & M_EXT_MEM_SIZE)
20621 
20622 #define A_MA_EXT_MEMORY0_BAR 0x77c8
20623 
20624 #define S_EXT_MEM0_BASE    16
20625 #define M_EXT_MEM0_BASE    0xfffU
20626 #define V_EXT_MEM0_BASE(x) ((x) << S_EXT_MEM0_BASE)
20627 #define G_EXT_MEM0_BASE(x) (((x) >> S_EXT_MEM0_BASE) & M_EXT_MEM0_BASE)
20628 
20629 #define S_EXT_MEM0_SIZE    0
20630 #define M_EXT_MEM0_SIZE    0xfffU
20631 #define V_EXT_MEM0_SIZE(x) ((x) << S_EXT_MEM0_SIZE)
20632 #define G_EXT_MEM0_SIZE(x) (((x) >> S_EXT_MEM0_SIZE) & M_EXT_MEM0_SIZE)
20633 
20634 #define S_T7_EXT_MEM0_BASE    16
20635 #define M_T7_EXT_MEM0_BASE    0xffffU
20636 #define V_T7_EXT_MEM0_BASE(x) ((x) << S_T7_EXT_MEM0_BASE)
20637 #define G_T7_EXT_MEM0_BASE(x) (((x) >> S_T7_EXT_MEM0_BASE) & M_T7_EXT_MEM0_BASE)
20638 
20639 #define S_T7_EXT_MEM0_SIZE    0
20640 #define M_T7_EXT_MEM0_SIZE    0xffffU
20641 #define V_T7_EXT_MEM0_SIZE(x) ((x) << S_T7_EXT_MEM0_SIZE)
20642 #define G_T7_EXT_MEM0_SIZE(x) (((x) >> S_T7_EXT_MEM0_SIZE) & M_T7_EXT_MEM0_SIZE)
20643 
20644 #define A_MA_HOST_MEMORY_BAR 0x77cc
20645 
20646 #define S_HMA_BASE    16
20647 #define M_HMA_BASE    0xfffU
20648 #define V_HMA_BASE(x) ((x) << S_HMA_BASE)
20649 #define G_HMA_BASE(x) (((x) >> S_HMA_BASE) & M_HMA_BASE)
20650 
20651 #define S_HMA_SIZE    0
20652 #define M_HMA_SIZE    0xfffU
20653 #define V_HMA_SIZE(x) ((x) << S_HMA_SIZE)
20654 #define G_HMA_SIZE(x) (((x) >> S_HMA_SIZE) & M_HMA_SIZE)
20655 
20656 #define S_HMATARGETBASE    16
20657 #define M_HMATARGETBASE    0xffffU
20658 #define V_HMATARGETBASE(x) ((x) << S_HMATARGETBASE)
20659 #define G_HMATARGETBASE(x) (((x) >> S_HMATARGETBASE) & M_HMATARGETBASE)
20660 
20661 #define S_T7_HMA_SIZE    0
20662 #define M_T7_HMA_SIZE    0xffffU
20663 #define V_T7_HMA_SIZE(x) ((x) << S_T7_HMA_SIZE)
20664 #define G_T7_HMA_SIZE(x) (((x) >> S_T7_HMA_SIZE) & M_T7_HMA_SIZE)
20665 
20666 #define A_MA_EXT_MEM_PAGE_SIZE 0x77d0
20667 
20668 #define S_BRC_MODE    2
20669 #define V_BRC_MODE(x) ((x) << S_BRC_MODE)
20670 #define F_BRC_MODE    V_BRC_MODE(1U)
20671 
20672 #define S_EXT_MEM_PAGE_SIZE    0
20673 #define M_EXT_MEM_PAGE_SIZE    0x3U
20674 #define V_EXT_MEM_PAGE_SIZE(x) ((x) << S_EXT_MEM_PAGE_SIZE)
20675 #define G_EXT_MEM_PAGE_SIZE(x) (((x) >> S_EXT_MEM_PAGE_SIZE) & M_EXT_MEM_PAGE_SIZE)
20676 
20677 #define S_BRC_MODE1    6
20678 #define V_BRC_MODE1(x) ((x) << S_BRC_MODE1)
20679 #define F_BRC_MODE1    V_BRC_MODE1(1U)
20680 
20681 #define S_EXT_MEM_PAGE_SIZE1    4
20682 #define M_EXT_MEM_PAGE_SIZE1    0x3U
20683 #define V_EXT_MEM_PAGE_SIZE1(x) ((x) << S_EXT_MEM_PAGE_SIZE1)
20684 #define G_EXT_MEM_PAGE_SIZE1(x) (((x) >> S_EXT_MEM_PAGE_SIZE1) & M_EXT_MEM_PAGE_SIZE1)
20685 
20686 #define S_BRBC_MODE    4
20687 #define V_BRBC_MODE(x) ((x) << S_BRBC_MODE)
20688 #define F_BRBC_MODE    V_BRBC_MODE(1U)
20689 
20690 #define S_T6_BRC_MODE    3
20691 #define V_T6_BRC_MODE(x) ((x) << S_T6_BRC_MODE)
20692 #define F_T6_BRC_MODE    V_T6_BRC_MODE(1U)
20693 
20694 #define S_T6_EXT_MEM_PAGE_SIZE    0
20695 #define M_T6_EXT_MEM_PAGE_SIZE    0x7U
20696 #define V_T6_EXT_MEM_PAGE_SIZE(x) ((x) << S_T6_EXT_MEM_PAGE_SIZE)
20697 #define G_T6_EXT_MEM_PAGE_SIZE(x) (((x) >> S_T6_EXT_MEM_PAGE_SIZE) & M_T6_EXT_MEM_PAGE_SIZE)
20698 
20699 #define A_MA_ARB_CTRL 0x77d4
20700 
20701 #define S_DIS_PAGE_HINT    1
20702 #define V_DIS_PAGE_HINT(x) ((x) << S_DIS_PAGE_HINT)
20703 #define F_DIS_PAGE_HINT    V_DIS_PAGE_HINT(1U)
20704 
20705 #define S_DIS_ADV_ARB    0
20706 #define V_DIS_ADV_ARB(x) ((x) << S_DIS_ADV_ARB)
20707 #define F_DIS_ADV_ARB    V_DIS_ADV_ARB(1U)
20708 
20709 #define S_DIS_BANK_FAIR    2
20710 #define V_DIS_BANK_FAIR(x) ((x) << S_DIS_BANK_FAIR)
20711 #define F_DIS_BANK_FAIR    V_DIS_BANK_FAIR(1U)
20712 
20713 #define S_HMA_WRT_EN    26
20714 #define V_HMA_WRT_EN(x) ((x) << S_HMA_WRT_EN)
20715 #define F_HMA_WRT_EN    V_HMA_WRT_EN(1U)
20716 
20717 #define S_HMA_NUM_PG_128B_FDBK    21
20718 #define M_HMA_NUM_PG_128B_FDBK    0x1fU
20719 #define V_HMA_NUM_PG_128B_FDBK(x) ((x) << S_HMA_NUM_PG_128B_FDBK)
20720 #define G_HMA_NUM_PG_128B_FDBK(x) (((x) >> S_HMA_NUM_PG_128B_FDBK) & M_HMA_NUM_PG_128B_FDBK)
20721 
20722 #define S_HMA_DIS_128B_PG_CNT_FDBK    20
20723 #define V_HMA_DIS_128B_PG_CNT_FDBK(x) ((x) << S_HMA_DIS_128B_PG_CNT_FDBK)
20724 #define F_HMA_DIS_128B_PG_CNT_FDBK    V_HMA_DIS_128B_PG_CNT_FDBK(1U)
20725 
20726 #define S_HMA_DIS_BG_ARB    19
20727 #define V_HMA_DIS_BG_ARB(x) ((x) << S_HMA_DIS_BG_ARB)
20728 #define F_HMA_DIS_BG_ARB    V_HMA_DIS_BG_ARB(1U)
20729 
20730 #define S_HMA_DIS_BANK_FAIR    18
20731 #define V_HMA_DIS_BANK_FAIR(x) ((x) << S_HMA_DIS_BANK_FAIR)
20732 #define F_HMA_DIS_BANK_FAIR    V_HMA_DIS_BANK_FAIR(1U)
20733 
20734 #define S_HMA_DIS_PAGE_HINT    17
20735 #define V_HMA_DIS_PAGE_HINT(x) ((x) << S_HMA_DIS_PAGE_HINT)
20736 #define F_HMA_DIS_PAGE_HINT    V_HMA_DIS_PAGE_HINT(1U)
20737 
20738 #define S_HMA_DIS_ADV_ARB    16
20739 #define V_HMA_DIS_ADV_ARB(x) ((x) << S_HMA_DIS_ADV_ARB)
20740 #define F_HMA_DIS_ADV_ARB    V_HMA_DIS_ADV_ARB(1U)
20741 
20742 #define S_NUM_PG_128B_FDBK    5
20743 #define M_NUM_PG_128B_FDBK    0x1fU
20744 #define V_NUM_PG_128B_FDBK(x) ((x) << S_NUM_PG_128B_FDBK)
20745 #define G_NUM_PG_128B_FDBK(x) (((x) >> S_NUM_PG_128B_FDBK) & M_NUM_PG_128B_FDBK)
20746 
20747 #define S_DIS_128B_PG_CNT_FDBK    4
20748 #define V_DIS_128B_PG_CNT_FDBK(x) ((x) << S_DIS_128B_PG_CNT_FDBK)
20749 #define F_DIS_128B_PG_CNT_FDBK    V_DIS_128B_PG_CNT_FDBK(1U)
20750 
20751 #define S_DIS_BG_ARB    3
20752 #define V_DIS_BG_ARB(x) ((x) << S_DIS_BG_ARB)
20753 #define F_DIS_BG_ARB    V_DIS_BG_ARB(1U)
20754 
20755 #define A_MA_TARGET_MEM_ENABLE 0x77d8
20756 
20757 #define S_HMA_ENABLE    3
20758 #define V_HMA_ENABLE(x) ((x) << S_HMA_ENABLE)
20759 #define F_HMA_ENABLE    V_HMA_ENABLE(1U)
20760 
20761 #define S_EXT_MEM_ENABLE    2
20762 #define V_EXT_MEM_ENABLE(x) ((x) << S_EXT_MEM_ENABLE)
20763 #define F_EXT_MEM_ENABLE    V_EXT_MEM_ENABLE(1U)
20764 
20765 #define S_EDRAM1_ENABLE    1
20766 #define V_EDRAM1_ENABLE(x) ((x) << S_EDRAM1_ENABLE)
20767 #define F_EDRAM1_ENABLE    V_EDRAM1_ENABLE(1U)
20768 
20769 #define S_EDRAM0_ENABLE    0
20770 #define V_EDRAM0_ENABLE(x) ((x) << S_EDRAM0_ENABLE)
20771 #define F_EDRAM0_ENABLE    V_EDRAM0_ENABLE(1U)
20772 
20773 #define S_HMA_MUX    5
20774 #define V_HMA_MUX(x) ((x) << S_HMA_MUX)
20775 #define F_HMA_MUX    V_HMA_MUX(1U)
20776 
20777 #define S_EXT_MEM1_ENABLE    4
20778 #define V_EXT_MEM1_ENABLE(x) ((x) << S_EXT_MEM1_ENABLE)
20779 #define F_EXT_MEM1_ENABLE    V_EXT_MEM1_ENABLE(1U)
20780 
20781 #define S_EXT_MEM0_ENABLE    2
20782 #define V_EXT_MEM0_ENABLE(x) ((x) << S_EXT_MEM0_ENABLE)
20783 #define F_EXT_MEM0_ENABLE    V_EXT_MEM0_ENABLE(1U)
20784 
20785 #define S_MC_SPLIT    6
20786 #define V_MC_SPLIT(x) ((x) << S_MC_SPLIT)
20787 #define F_MC_SPLIT    V_MC_SPLIT(1U)
20788 
20789 #define S_EDC512    8
20790 #define V_EDC512(x) ((x) << S_EDC512)
20791 #define F_EDC512    V_EDC512(1U)
20792 
20793 #define S_MC_SPLIT_BOUNDARY    7
20794 #define V_MC_SPLIT_BOUNDARY(x) ((x) << S_MC_SPLIT_BOUNDARY)
20795 #define F_MC_SPLIT_BOUNDARY    V_MC_SPLIT_BOUNDARY(1U)
20796 
20797 #define A_MA_INT_ENABLE 0x77dc
20798 
20799 #define S_MEM_PERR_INT_ENABLE    1
20800 #define V_MEM_PERR_INT_ENABLE(x) ((x) << S_MEM_PERR_INT_ENABLE)
20801 #define F_MEM_PERR_INT_ENABLE    V_MEM_PERR_INT_ENABLE(1U)
20802 
20803 #define S_MEM_WRAP_INT_ENABLE    0
20804 #define V_MEM_WRAP_INT_ENABLE(x) ((x) << S_MEM_WRAP_INT_ENABLE)
20805 #define F_MEM_WRAP_INT_ENABLE    V_MEM_WRAP_INT_ENABLE(1U)
20806 
20807 #define S_MEM_TO_INT_ENABLE    2
20808 #define V_MEM_TO_INT_ENABLE(x) ((x) << S_MEM_TO_INT_ENABLE)
20809 #define F_MEM_TO_INT_ENABLE    V_MEM_TO_INT_ENABLE(1U)
20810 
20811 #define A_MA_INT_CAUSE 0x77e0
20812 
20813 #define S_MEM_PERR_INT_CAUSE    1
20814 #define V_MEM_PERR_INT_CAUSE(x) ((x) << S_MEM_PERR_INT_CAUSE)
20815 #define F_MEM_PERR_INT_CAUSE    V_MEM_PERR_INT_CAUSE(1U)
20816 
20817 #define S_MEM_WRAP_INT_CAUSE    0
20818 #define V_MEM_WRAP_INT_CAUSE(x) ((x) << S_MEM_WRAP_INT_CAUSE)
20819 #define F_MEM_WRAP_INT_CAUSE    V_MEM_WRAP_INT_CAUSE(1U)
20820 
20821 #define S_MEM_TO_INT_CAUSE    2
20822 #define V_MEM_TO_INT_CAUSE(x) ((x) << S_MEM_TO_INT_CAUSE)
20823 #define F_MEM_TO_INT_CAUSE    V_MEM_TO_INT_CAUSE(1U)
20824 
20825 #define A_MA_INT_WRAP_STATUS 0x77e4
20826 
20827 #define S_MEM_WRAP_ADDRESS    4
20828 #define M_MEM_WRAP_ADDRESS    0xfffffffU
20829 #define V_MEM_WRAP_ADDRESS(x) ((x) << S_MEM_WRAP_ADDRESS)
20830 #define G_MEM_WRAP_ADDRESS(x) (((x) >> S_MEM_WRAP_ADDRESS) & M_MEM_WRAP_ADDRESS)
20831 
20832 #define S_MEM_WRAP_CLIENT_NUM    0
20833 #define M_MEM_WRAP_CLIENT_NUM    0xfU
20834 #define V_MEM_WRAP_CLIENT_NUM(x) ((x) << S_MEM_WRAP_CLIENT_NUM)
20835 #define G_MEM_WRAP_CLIENT_NUM(x) (((x) >> S_MEM_WRAP_CLIENT_NUM) & M_MEM_WRAP_CLIENT_NUM)
20836 
20837 #define A_MA_TP_THREAD1_MAPPER 0x77e8
20838 
20839 #define S_TP_THREAD1_EN    0
20840 #define M_TP_THREAD1_EN    0xffU
20841 #define V_TP_THREAD1_EN(x) ((x) << S_TP_THREAD1_EN)
20842 #define G_TP_THREAD1_EN(x) (((x) >> S_TP_THREAD1_EN) & M_TP_THREAD1_EN)
20843 
20844 #define A_MA_SGE_THREAD1_MAPPER 0x77ec
20845 
20846 #define S_SGE_THREAD1_EN    0
20847 #define M_SGE_THREAD1_EN    0xffU
20848 #define V_SGE_THREAD1_EN(x) ((x) << S_SGE_THREAD1_EN)
20849 #define G_SGE_THREAD1_EN(x) (((x) >> S_SGE_THREAD1_EN) & M_SGE_THREAD1_EN)
20850 
20851 #define A_MA_PARITY_ERROR_ENABLE 0x77f0
20852 
20853 #define S_TP_DMARBT_PAR_ERROR_EN    31
20854 #define V_TP_DMARBT_PAR_ERROR_EN(x) ((x) << S_TP_DMARBT_PAR_ERROR_EN)
20855 #define F_TP_DMARBT_PAR_ERROR_EN    V_TP_DMARBT_PAR_ERROR_EN(1U)
20856 
20857 #define S_LOGIC_FIFO_PAR_ERROR_EN    30
20858 #define V_LOGIC_FIFO_PAR_ERROR_EN(x) ((x) << S_LOGIC_FIFO_PAR_ERROR_EN)
20859 #define F_LOGIC_FIFO_PAR_ERROR_EN    V_LOGIC_FIFO_PAR_ERROR_EN(1U)
20860 
20861 #define S_ARB3_PAR_WRQUEUE_ERROR_EN    29
20862 #define V_ARB3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB3_PAR_WRQUEUE_ERROR_EN)
20863 #define F_ARB3_PAR_WRQUEUE_ERROR_EN    V_ARB3_PAR_WRQUEUE_ERROR_EN(1U)
20864 
20865 #define S_ARB2_PAR_WRQUEUE_ERROR_EN    28
20866 #define V_ARB2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB2_PAR_WRQUEUE_ERROR_EN)
20867 #define F_ARB2_PAR_WRQUEUE_ERROR_EN    V_ARB2_PAR_WRQUEUE_ERROR_EN(1U)
20868 
20869 #define S_ARB1_PAR_WRQUEUE_ERROR_EN    27
20870 #define V_ARB1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB1_PAR_WRQUEUE_ERROR_EN)
20871 #define F_ARB1_PAR_WRQUEUE_ERROR_EN    V_ARB1_PAR_WRQUEUE_ERROR_EN(1U)
20872 
20873 #define S_ARB0_PAR_WRQUEUE_ERROR_EN    26
20874 #define V_ARB0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB0_PAR_WRQUEUE_ERROR_EN)
20875 #define F_ARB0_PAR_WRQUEUE_ERROR_EN    V_ARB0_PAR_WRQUEUE_ERROR_EN(1U)
20876 
20877 #define S_ARB3_PAR_RDQUEUE_ERROR_EN    25
20878 #define V_ARB3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB3_PAR_RDQUEUE_ERROR_EN)
20879 #define F_ARB3_PAR_RDQUEUE_ERROR_EN    V_ARB3_PAR_RDQUEUE_ERROR_EN(1U)
20880 
20881 #define S_ARB2_PAR_RDQUEUE_ERROR_EN    24
20882 #define V_ARB2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB2_PAR_RDQUEUE_ERROR_EN)
20883 #define F_ARB2_PAR_RDQUEUE_ERROR_EN    V_ARB2_PAR_RDQUEUE_ERROR_EN(1U)
20884 
20885 #define S_ARB1_PAR_RDQUEUE_ERROR_EN    23
20886 #define V_ARB1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB1_PAR_RDQUEUE_ERROR_EN)
20887 #define F_ARB1_PAR_RDQUEUE_ERROR_EN    V_ARB1_PAR_RDQUEUE_ERROR_EN(1U)
20888 
20889 #define S_ARB0_PAR_RDQUEUE_ERROR_EN    22
20890 #define V_ARB0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB0_PAR_RDQUEUE_ERROR_EN)
20891 #define F_ARB0_PAR_RDQUEUE_ERROR_EN    V_ARB0_PAR_RDQUEUE_ERROR_EN(1U)
20892 
20893 #define S_CL10_PAR_WRQUEUE_ERROR_EN    21
20894 #define V_CL10_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL10_PAR_WRQUEUE_ERROR_EN)
20895 #define F_CL10_PAR_WRQUEUE_ERROR_EN    V_CL10_PAR_WRQUEUE_ERROR_EN(1U)
20896 
20897 #define S_CL9_PAR_WRQUEUE_ERROR_EN    20
20898 #define V_CL9_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL9_PAR_WRQUEUE_ERROR_EN)
20899 #define F_CL9_PAR_WRQUEUE_ERROR_EN    V_CL9_PAR_WRQUEUE_ERROR_EN(1U)
20900 
20901 #define S_CL8_PAR_WRQUEUE_ERROR_EN    19
20902 #define V_CL8_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL8_PAR_WRQUEUE_ERROR_EN)
20903 #define F_CL8_PAR_WRQUEUE_ERROR_EN    V_CL8_PAR_WRQUEUE_ERROR_EN(1U)
20904 
20905 #define S_CL7_PAR_WRQUEUE_ERROR_EN    18
20906 #define V_CL7_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL7_PAR_WRQUEUE_ERROR_EN)
20907 #define F_CL7_PAR_WRQUEUE_ERROR_EN    V_CL7_PAR_WRQUEUE_ERROR_EN(1U)
20908 
20909 #define S_CL6_PAR_WRQUEUE_ERROR_EN    17
20910 #define V_CL6_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL6_PAR_WRQUEUE_ERROR_EN)
20911 #define F_CL6_PAR_WRQUEUE_ERROR_EN    V_CL6_PAR_WRQUEUE_ERROR_EN(1U)
20912 
20913 #define S_CL5_PAR_WRQUEUE_ERROR_EN    16
20914 #define V_CL5_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL5_PAR_WRQUEUE_ERROR_EN)
20915 #define F_CL5_PAR_WRQUEUE_ERROR_EN    V_CL5_PAR_WRQUEUE_ERROR_EN(1U)
20916 
20917 #define S_CL4_PAR_WRQUEUE_ERROR_EN    15
20918 #define V_CL4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL4_PAR_WRQUEUE_ERROR_EN)
20919 #define F_CL4_PAR_WRQUEUE_ERROR_EN    V_CL4_PAR_WRQUEUE_ERROR_EN(1U)
20920 
20921 #define S_CL3_PAR_WRQUEUE_ERROR_EN    14
20922 #define V_CL3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL3_PAR_WRQUEUE_ERROR_EN)
20923 #define F_CL3_PAR_WRQUEUE_ERROR_EN    V_CL3_PAR_WRQUEUE_ERROR_EN(1U)
20924 
20925 #define S_CL2_PAR_WRQUEUE_ERROR_EN    13
20926 #define V_CL2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL2_PAR_WRQUEUE_ERROR_EN)
20927 #define F_CL2_PAR_WRQUEUE_ERROR_EN    V_CL2_PAR_WRQUEUE_ERROR_EN(1U)
20928 
20929 #define S_CL1_PAR_WRQUEUE_ERROR_EN    12
20930 #define V_CL1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL1_PAR_WRQUEUE_ERROR_EN)
20931 #define F_CL1_PAR_WRQUEUE_ERROR_EN    V_CL1_PAR_WRQUEUE_ERROR_EN(1U)
20932 
20933 #define S_CL0_PAR_WRQUEUE_ERROR_EN    11
20934 #define V_CL0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL0_PAR_WRQUEUE_ERROR_EN)
20935 #define F_CL0_PAR_WRQUEUE_ERROR_EN    V_CL0_PAR_WRQUEUE_ERROR_EN(1U)
20936 
20937 #define S_CL10_PAR_RDQUEUE_ERROR_EN    10
20938 #define V_CL10_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL10_PAR_RDQUEUE_ERROR_EN)
20939 #define F_CL10_PAR_RDQUEUE_ERROR_EN    V_CL10_PAR_RDQUEUE_ERROR_EN(1U)
20940 
20941 #define S_CL9_PAR_RDQUEUE_ERROR_EN    9
20942 #define V_CL9_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL9_PAR_RDQUEUE_ERROR_EN)
20943 #define F_CL9_PAR_RDQUEUE_ERROR_EN    V_CL9_PAR_RDQUEUE_ERROR_EN(1U)
20944 
20945 #define S_CL8_PAR_RDQUEUE_ERROR_EN    8
20946 #define V_CL8_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL8_PAR_RDQUEUE_ERROR_EN)
20947 #define F_CL8_PAR_RDQUEUE_ERROR_EN    V_CL8_PAR_RDQUEUE_ERROR_EN(1U)
20948 
20949 #define S_CL7_PAR_RDQUEUE_ERROR_EN    7
20950 #define V_CL7_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL7_PAR_RDQUEUE_ERROR_EN)
20951 #define F_CL7_PAR_RDQUEUE_ERROR_EN    V_CL7_PAR_RDQUEUE_ERROR_EN(1U)
20952 
20953 #define S_CL6_PAR_RDQUEUE_ERROR_EN    6
20954 #define V_CL6_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL6_PAR_RDQUEUE_ERROR_EN)
20955 #define F_CL6_PAR_RDQUEUE_ERROR_EN    V_CL6_PAR_RDQUEUE_ERROR_EN(1U)
20956 
20957 #define S_CL5_PAR_RDQUEUE_ERROR_EN    5
20958 #define V_CL5_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL5_PAR_RDQUEUE_ERROR_EN)
20959 #define F_CL5_PAR_RDQUEUE_ERROR_EN    V_CL5_PAR_RDQUEUE_ERROR_EN(1U)
20960 
20961 #define S_CL4_PAR_RDQUEUE_ERROR_EN    4
20962 #define V_CL4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL4_PAR_RDQUEUE_ERROR_EN)
20963 #define F_CL4_PAR_RDQUEUE_ERROR_EN    V_CL4_PAR_RDQUEUE_ERROR_EN(1U)
20964 
20965 #define S_CL3_PAR_RDQUEUE_ERROR_EN    3
20966 #define V_CL3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL3_PAR_RDQUEUE_ERROR_EN)
20967 #define F_CL3_PAR_RDQUEUE_ERROR_EN    V_CL3_PAR_RDQUEUE_ERROR_EN(1U)
20968 
20969 #define S_CL2_PAR_RDQUEUE_ERROR_EN    2
20970 #define V_CL2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL2_PAR_RDQUEUE_ERROR_EN)
20971 #define F_CL2_PAR_RDQUEUE_ERROR_EN    V_CL2_PAR_RDQUEUE_ERROR_EN(1U)
20972 
20973 #define S_CL1_PAR_RDQUEUE_ERROR_EN    1
20974 #define V_CL1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL1_PAR_RDQUEUE_ERROR_EN)
20975 #define F_CL1_PAR_RDQUEUE_ERROR_EN    V_CL1_PAR_RDQUEUE_ERROR_EN(1U)
20976 
20977 #define S_CL0_PAR_RDQUEUE_ERROR_EN    0
20978 #define V_CL0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR_EN)
20979 #define F_CL0_PAR_RDQUEUE_ERROR_EN    V_CL0_PAR_RDQUEUE_ERROR_EN(1U)
20980 
20981 #define A_MA_PARITY_ERROR_ENABLE1 0x77f0
20982 
20983 #define S_T7_ARB4_PAR_WRQUEUE_ERROR_EN    11
20984 #define V_T7_ARB4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB4_PAR_WRQUEUE_ERROR_EN)
20985 #define F_T7_ARB4_PAR_WRQUEUE_ERROR_EN    V_T7_ARB4_PAR_WRQUEUE_ERROR_EN(1U)
20986 
20987 #define S_T7_ARB3_PAR_WRQUEUE_ERROR_EN    10
20988 #define V_T7_ARB3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB3_PAR_WRQUEUE_ERROR_EN)
20989 #define F_T7_ARB3_PAR_WRQUEUE_ERROR_EN    V_T7_ARB3_PAR_WRQUEUE_ERROR_EN(1U)
20990 
20991 #define S_T7_ARB2_PAR_WRQUEUE_ERROR_EN    9
20992 #define V_T7_ARB2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB2_PAR_WRQUEUE_ERROR_EN)
20993 #define F_T7_ARB2_PAR_WRQUEUE_ERROR_EN    V_T7_ARB2_PAR_WRQUEUE_ERROR_EN(1U)
20994 
20995 #define S_T7_ARB1_PAR_WRQUEUE_ERROR_EN    8
20996 #define V_T7_ARB1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB1_PAR_WRQUEUE_ERROR_EN)
20997 #define F_T7_ARB1_PAR_WRQUEUE_ERROR_EN    V_T7_ARB1_PAR_WRQUEUE_ERROR_EN(1U)
20998 
20999 #define S_T7_ARB0_PAR_WRQUEUE_ERROR_EN    7
21000 #define V_T7_ARB0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB0_PAR_WRQUEUE_ERROR_EN)
21001 #define F_T7_ARB0_PAR_WRQUEUE_ERROR_EN    V_T7_ARB0_PAR_WRQUEUE_ERROR_EN(1U)
21002 
21003 #define S_T7_ARB4_PAR_RDQUEUE_ERROR_EN    6
21004 #define V_T7_ARB4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB4_PAR_RDQUEUE_ERROR_EN)
21005 #define F_T7_ARB4_PAR_RDQUEUE_ERROR_EN    V_T7_ARB4_PAR_RDQUEUE_ERROR_EN(1U)
21006 
21007 #define S_T7_ARB3_PAR_RDQUEUE_ERROR_EN    5
21008 #define V_T7_ARB3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB3_PAR_RDQUEUE_ERROR_EN)
21009 #define F_T7_ARB3_PAR_RDQUEUE_ERROR_EN    V_T7_ARB3_PAR_RDQUEUE_ERROR_EN(1U)
21010 
21011 #define S_T7_ARB2_PAR_RDQUEUE_ERROR_EN    4
21012 #define V_T7_ARB2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB2_PAR_RDQUEUE_ERROR_EN)
21013 #define F_T7_ARB2_PAR_RDQUEUE_ERROR_EN    V_T7_ARB2_PAR_RDQUEUE_ERROR_EN(1U)
21014 
21015 #define S_T7_ARB1_PAR_RDQUEUE_ERROR_EN    3
21016 #define V_T7_ARB1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB1_PAR_RDQUEUE_ERROR_EN)
21017 #define F_T7_ARB1_PAR_RDQUEUE_ERROR_EN    V_T7_ARB1_PAR_RDQUEUE_ERROR_EN(1U)
21018 
21019 #define S_T7_ARB0_PAR_RDQUEUE_ERROR_EN    2
21020 #define V_T7_ARB0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB0_PAR_RDQUEUE_ERROR_EN)
21021 #define F_T7_ARB0_PAR_RDQUEUE_ERROR_EN    V_T7_ARB0_PAR_RDQUEUE_ERROR_EN(1U)
21022 
21023 #define S_T7_TP_DMARBT_PAR_ERROR_EN    1
21024 #define V_T7_TP_DMARBT_PAR_ERROR_EN(x) ((x) << S_T7_TP_DMARBT_PAR_ERROR_EN)
21025 #define F_T7_TP_DMARBT_PAR_ERROR_EN    V_T7_TP_DMARBT_PAR_ERROR_EN(1U)
21026 
21027 #define S_T7_LOGIC_FIFO_PAR_ERROR_EN    0
21028 #define V_T7_LOGIC_FIFO_PAR_ERROR_EN(x) ((x) << S_T7_LOGIC_FIFO_PAR_ERROR_EN)
21029 #define F_T7_LOGIC_FIFO_PAR_ERROR_EN    V_T7_LOGIC_FIFO_PAR_ERROR_EN(1U)
21030 
21031 #define A_MA_PARITY_ERROR_STATUS 0x77f4
21032 
21033 #define S_TP_DMARBT_PAR_ERROR    31
21034 #define V_TP_DMARBT_PAR_ERROR(x) ((x) << S_TP_DMARBT_PAR_ERROR)
21035 #define F_TP_DMARBT_PAR_ERROR    V_TP_DMARBT_PAR_ERROR(1U)
21036 
21037 #define S_LOGIC_FIFO_PAR_ERROR    30
21038 #define V_LOGIC_FIFO_PAR_ERROR(x) ((x) << S_LOGIC_FIFO_PAR_ERROR)
21039 #define F_LOGIC_FIFO_PAR_ERROR    V_LOGIC_FIFO_PAR_ERROR(1U)
21040 
21041 #define S_ARB3_PAR_WRQUEUE_ERROR    29
21042 #define V_ARB3_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB3_PAR_WRQUEUE_ERROR)
21043 #define F_ARB3_PAR_WRQUEUE_ERROR    V_ARB3_PAR_WRQUEUE_ERROR(1U)
21044 
21045 #define S_ARB2_PAR_WRQUEUE_ERROR    28
21046 #define V_ARB2_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB2_PAR_WRQUEUE_ERROR)
21047 #define F_ARB2_PAR_WRQUEUE_ERROR    V_ARB2_PAR_WRQUEUE_ERROR(1U)
21048 
21049 #define S_ARB1_PAR_WRQUEUE_ERROR    27
21050 #define V_ARB1_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB1_PAR_WRQUEUE_ERROR)
21051 #define F_ARB1_PAR_WRQUEUE_ERROR    V_ARB1_PAR_WRQUEUE_ERROR(1U)
21052 
21053 #define S_ARB0_PAR_WRQUEUE_ERROR    26
21054 #define V_ARB0_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB0_PAR_WRQUEUE_ERROR)
21055 #define F_ARB0_PAR_WRQUEUE_ERROR    V_ARB0_PAR_WRQUEUE_ERROR(1U)
21056 
21057 #define S_ARB3_PAR_RDQUEUE_ERROR    25
21058 #define V_ARB3_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB3_PAR_RDQUEUE_ERROR)
21059 #define F_ARB3_PAR_RDQUEUE_ERROR    V_ARB3_PAR_RDQUEUE_ERROR(1U)
21060 
21061 #define S_ARB2_PAR_RDQUEUE_ERROR    24
21062 #define V_ARB2_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB2_PAR_RDQUEUE_ERROR)
21063 #define F_ARB2_PAR_RDQUEUE_ERROR    V_ARB2_PAR_RDQUEUE_ERROR(1U)
21064 
21065 #define S_ARB1_PAR_RDQUEUE_ERROR    23
21066 #define V_ARB1_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB1_PAR_RDQUEUE_ERROR)
21067 #define F_ARB1_PAR_RDQUEUE_ERROR    V_ARB1_PAR_RDQUEUE_ERROR(1U)
21068 
21069 #define S_ARB0_PAR_RDQUEUE_ERROR    22
21070 #define V_ARB0_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB0_PAR_RDQUEUE_ERROR)
21071 #define F_ARB0_PAR_RDQUEUE_ERROR    V_ARB0_PAR_RDQUEUE_ERROR(1U)
21072 
21073 #define S_CL10_PAR_WRQUEUE_ERROR    21
21074 #define V_CL10_PAR_WRQUEUE_ERROR(x) ((x) << S_CL10_PAR_WRQUEUE_ERROR)
21075 #define F_CL10_PAR_WRQUEUE_ERROR    V_CL10_PAR_WRQUEUE_ERROR(1U)
21076 
21077 #define S_CL9_PAR_WRQUEUE_ERROR    20
21078 #define V_CL9_PAR_WRQUEUE_ERROR(x) ((x) << S_CL9_PAR_WRQUEUE_ERROR)
21079 #define F_CL9_PAR_WRQUEUE_ERROR    V_CL9_PAR_WRQUEUE_ERROR(1U)
21080 
21081 #define S_CL8_PAR_WRQUEUE_ERROR    19
21082 #define V_CL8_PAR_WRQUEUE_ERROR(x) ((x) << S_CL8_PAR_WRQUEUE_ERROR)
21083 #define F_CL8_PAR_WRQUEUE_ERROR    V_CL8_PAR_WRQUEUE_ERROR(1U)
21084 
21085 #define S_CL7_PAR_WRQUEUE_ERROR    18
21086 #define V_CL7_PAR_WRQUEUE_ERROR(x) ((x) << S_CL7_PAR_WRQUEUE_ERROR)
21087 #define F_CL7_PAR_WRQUEUE_ERROR    V_CL7_PAR_WRQUEUE_ERROR(1U)
21088 
21089 #define S_CL6_PAR_WRQUEUE_ERROR    17
21090 #define V_CL6_PAR_WRQUEUE_ERROR(x) ((x) << S_CL6_PAR_WRQUEUE_ERROR)
21091 #define F_CL6_PAR_WRQUEUE_ERROR    V_CL6_PAR_WRQUEUE_ERROR(1U)
21092 
21093 #define S_CL5_PAR_WRQUEUE_ERROR    16
21094 #define V_CL5_PAR_WRQUEUE_ERROR(x) ((x) << S_CL5_PAR_WRQUEUE_ERROR)
21095 #define F_CL5_PAR_WRQUEUE_ERROR    V_CL5_PAR_WRQUEUE_ERROR(1U)
21096 
21097 #define S_CL4_PAR_WRQUEUE_ERROR    15
21098 #define V_CL4_PAR_WRQUEUE_ERROR(x) ((x) << S_CL4_PAR_WRQUEUE_ERROR)
21099 #define F_CL4_PAR_WRQUEUE_ERROR    V_CL4_PAR_WRQUEUE_ERROR(1U)
21100 
21101 #define S_CL3_PAR_WRQUEUE_ERROR    14
21102 #define V_CL3_PAR_WRQUEUE_ERROR(x) ((x) << S_CL3_PAR_WRQUEUE_ERROR)
21103 #define F_CL3_PAR_WRQUEUE_ERROR    V_CL3_PAR_WRQUEUE_ERROR(1U)
21104 
21105 #define S_CL2_PAR_WRQUEUE_ERROR    13
21106 #define V_CL2_PAR_WRQUEUE_ERROR(x) ((x) << S_CL2_PAR_WRQUEUE_ERROR)
21107 #define F_CL2_PAR_WRQUEUE_ERROR    V_CL2_PAR_WRQUEUE_ERROR(1U)
21108 
21109 #define S_CL1_PAR_WRQUEUE_ERROR    12
21110 #define V_CL1_PAR_WRQUEUE_ERROR(x) ((x) << S_CL1_PAR_WRQUEUE_ERROR)
21111 #define F_CL1_PAR_WRQUEUE_ERROR    V_CL1_PAR_WRQUEUE_ERROR(1U)
21112 
21113 #define S_CL0_PAR_WRQUEUE_ERROR    11
21114 #define V_CL0_PAR_WRQUEUE_ERROR(x) ((x) << S_CL0_PAR_WRQUEUE_ERROR)
21115 #define F_CL0_PAR_WRQUEUE_ERROR    V_CL0_PAR_WRQUEUE_ERROR(1U)
21116 
21117 #define S_CL10_PAR_RDQUEUE_ERROR    10
21118 #define V_CL10_PAR_RDQUEUE_ERROR(x) ((x) << S_CL10_PAR_RDQUEUE_ERROR)
21119 #define F_CL10_PAR_RDQUEUE_ERROR    V_CL10_PAR_RDQUEUE_ERROR(1U)
21120 
21121 #define S_CL9_PAR_RDQUEUE_ERROR    9
21122 #define V_CL9_PAR_RDQUEUE_ERROR(x) ((x) << S_CL9_PAR_RDQUEUE_ERROR)
21123 #define F_CL9_PAR_RDQUEUE_ERROR    V_CL9_PAR_RDQUEUE_ERROR(1U)
21124 
21125 #define S_CL8_PAR_RDQUEUE_ERROR    8
21126 #define V_CL8_PAR_RDQUEUE_ERROR(x) ((x) << S_CL8_PAR_RDQUEUE_ERROR)
21127 #define F_CL8_PAR_RDQUEUE_ERROR    V_CL8_PAR_RDQUEUE_ERROR(1U)
21128 
21129 #define S_CL7_PAR_RDQUEUE_ERROR    7
21130 #define V_CL7_PAR_RDQUEUE_ERROR(x) ((x) << S_CL7_PAR_RDQUEUE_ERROR)
21131 #define F_CL7_PAR_RDQUEUE_ERROR    V_CL7_PAR_RDQUEUE_ERROR(1U)
21132 
21133 #define S_CL6_PAR_RDQUEUE_ERROR    6
21134 #define V_CL6_PAR_RDQUEUE_ERROR(x) ((x) << S_CL6_PAR_RDQUEUE_ERROR)
21135 #define F_CL6_PAR_RDQUEUE_ERROR    V_CL6_PAR_RDQUEUE_ERROR(1U)
21136 
21137 #define S_CL5_PAR_RDQUEUE_ERROR    5
21138 #define V_CL5_PAR_RDQUEUE_ERROR(x) ((x) << S_CL5_PAR_RDQUEUE_ERROR)
21139 #define F_CL5_PAR_RDQUEUE_ERROR    V_CL5_PAR_RDQUEUE_ERROR(1U)
21140 
21141 #define S_CL4_PAR_RDQUEUE_ERROR    4
21142 #define V_CL4_PAR_RDQUEUE_ERROR(x) ((x) << S_CL4_PAR_RDQUEUE_ERROR)
21143 #define F_CL4_PAR_RDQUEUE_ERROR    V_CL4_PAR_RDQUEUE_ERROR(1U)
21144 
21145 #define S_CL3_PAR_RDQUEUE_ERROR    3
21146 #define V_CL3_PAR_RDQUEUE_ERROR(x) ((x) << S_CL3_PAR_RDQUEUE_ERROR)
21147 #define F_CL3_PAR_RDQUEUE_ERROR    V_CL3_PAR_RDQUEUE_ERROR(1U)
21148 
21149 #define S_CL2_PAR_RDQUEUE_ERROR    2
21150 #define V_CL2_PAR_RDQUEUE_ERROR(x) ((x) << S_CL2_PAR_RDQUEUE_ERROR)
21151 #define F_CL2_PAR_RDQUEUE_ERROR    V_CL2_PAR_RDQUEUE_ERROR(1U)
21152 
21153 #define S_CL1_PAR_RDQUEUE_ERROR    1
21154 #define V_CL1_PAR_RDQUEUE_ERROR(x) ((x) << S_CL1_PAR_RDQUEUE_ERROR)
21155 #define F_CL1_PAR_RDQUEUE_ERROR    V_CL1_PAR_RDQUEUE_ERROR(1U)
21156 
21157 #define S_CL0_PAR_RDQUEUE_ERROR    0
21158 #define V_CL0_PAR_RDQUEUE_ERROR(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR)
21159 #define F_CL0_PAR_RDQUEUE_ERROR    V_CL0_PAR_RDQUEUE_ERROR(1U)
21160 
21161 #define A_MA_PARITY_ERROR_STATUS1 0x77f4
21162 
21163 #define S_T7_ARB4_PAR_WRQUEUE_ERROR    11
21164 #define V_T7_ARB4_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB4_PAR_WRQUEUE_ERROR)
21165 #define F_T7_ARB4_PAR_WRQUEUE_ERROR    V_T7_ARB4_PAR_WRQUEUE_ERROR(1U)
21166 
21167 #define S_T7_ARB3_PAR_WRQUEUE_ERROR    10
21168 #define V_T7_ARB3_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB3_PAR_WRQUEUE_ERROR)
21169 #define F_T7_ARB3_PAR_WRQUEUE_ERROR    V_T7_ARB3_PAR_WRQUEUE_ERROR(1U)
21170 
21171 #define S_T7_ARB2_PAR_WRQUEUE_ERROR    9
21172 #define V_T7_ARB2_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB2_PAR_WRQUEUE_ERROR)
21173 #define F_T7_ARB2_PAR_WRQUEUE_ERROR    V_T7_ARB2_PAR_WRQUEUE_ERROR(1U)
21174 
21175 #define S_T7_ARB1_PAR_WRQUEUE_ERROR    8
21176 #define V_T7_ARB1_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB1_PAR_WRQUEUE_ERROR)
21177 #define F_T7_ARB1_PAR_WRQUEUE_ERROR    V_T7_ARB1_PAR_WRQUEUE_ERROR(1U)
21178 
21179 #define S_T7_ARB0_PAR_WRQUEUE_ERROR    7
21180 #define V_T7_ARB0_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB0_PAR_WRQUEUE_ERROR)
21181 #define F_T7_ARB0_PAR_WRQUEUE_ERROR    V_T7_ARB0_PAR_WRQUEUE_ERROR(1U)
21182 
21183 #define S_T7_ARB4_PAR_RDQUEUE_ERROR    6
21184 #define V_T7_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB4_PAR_RDQUEUE_ERROR)
21185 #define F_T7_ARB4_PAR_RDQUEUE_ERROR    V_T7_ARB4_PAR_RDQUEUE_ERROR(1U)
21186 
21187 #define S_T7_ARB3_PAR_RDQUEUE_ERROR    5
21188 #define V_T7_ARB3_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB3_PAR_RDQUEUE_ERROR)
21189 #define F_T7_ARB3_PAR_RDQUEUE_ERROR    V_T7_ARB3_PAR_RDQUEUE_ERROR(1U)
21190 
21191 #define S_T7_ARB2_PAR_RDQUEUE_ERROR    4
21192 #define V_T7_ARB2_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB2_PAR_RDQUEUE_ERROR)
21193 #define F_T7_ARB2_PAR_RDQUEUE_ERROR    V_T7_ARB2_PAR_RDQUEUE_ERROR(1U)
21194 
21195 #define S_T7_ARB1_PAR_RDQUEUE_ERROR    3
21196 #define V_T7_ARB1_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB1_PAR_RDQUEUE_ERROR)
21197 #define F_T7_ARB1_PAR_RDQUEUE_ERROR    V_T7_ARB1_PAR_RDQUEUE_ERROR(1U)
21198 
21199 #define S_T7_ARB0_PAR_RDQUEUE_ERROR    2
21200 #define V_T7_ARB0_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB0_PAR_RDQUEUE_ERROR)
21201 #define F_T7_ARB0_PAR_RDQUEUE_ERROR    V_T7_ARB0_PAR_RDQUEUE_ERROR(1U)
21202 
21203 #define S_T7_TP_DMARBT_PAR_ERROR    1
21204 #define V_T7_TP_DMARBT_PAR_ERROR(x) ((x) << S_T7_TP_DMARBT_PAR_ERROR)
21205 #define F_T7_TP_DMARBT_PAR_ERROR    V_T7_TP_DMARBT_PAR_ERROR(1U)
21206 
21207 #define S_T7_LOGIC_FIFO_PAR_ERROR    0
21208 #define V_T7_LOGIC_FIFO_PAR_ERROR(x) ((x) << S_T7_LOGIC_FIFO_PAR_ERROR)
21209 #define F_T7_LOGIC_FIFO_PAR_ERROR    V_T7_LOGIC_FIFO_PAR_ERROR(1U)
21210 
21211 #define A_MA_SGE_PCIE_COHERANCY_CTRL 0x77f8
21212 
21213 #define S_BONUS_REG    6
21214 #define M_BONUS_REG    0x3ffffffU
21215 #define V_BONUS_REG(x) ((x) << S_BONUS_REG)
21216 #define G_BONUS_REG(x) (((x) >> S_BONUS_REG) & M_BONUS_REG)
21217 
21218 #define S_COHERANCY_CMD_TYPE    4
21219 #define M_COHERANCY_CMD_TYPE    0x3U
21220 #define V_COHERANCY_CMD_TYPE(x) ((x) << S_COHERANCY_CMD_TYPE)
21221 #define G_COHERANCY_CMD_TYPE(x) (((x) >> S_COHERANCY_CMD_TYPE) & M_COHERANCY_CMD_TYPE)
21222 
21223 #define S_COHERANCY_THREAD_NUM    1
21224 #define M_COHERANCY_THREAD_NUM    0x7U
21225 #define V_COHERANCY_THREAD_NUM(x) ((x) << S_COHERANCY_THREAD_NUM)
21226 #define G_COHERANCY_THREAD_NUM(x) (((x) >> S_COHERANCY_THREAD_NUM) & M_COHERANCY_THREAD_NUM)
21227 
21228 #define S_COHERANCY_ENABLE    0
21229 #define V_COHERANCY_ENABLE(x) ((x) << S_COHERANCY_ENABLE)
21230 #define F_COHERANCY_ENABLE    V_COHERANCY_ENABLE(1U)
21231 
21232 #define A_MA_ERROR_ENABLE 0x77fc
21233 
21234 #define S_UE_ENABLE    0
21235 #define V_UE_ENABLE(x) ((x) << S_UE_ENABLE)
21236 #define F_UE_ENABLE    V_UE_ENABLE(1U)
21237 
21238 #define S_FUTURE_EXPANSION    1
21239 #define M_FUTURE_EXPANSION    0x7fffffffU
21240 #define V_FUTURE_EXPANSION(x) ((x) << S_FUTURE_EXPANSION)
21241 #define G_FUTURE_EXPANSION(x) (((x) >> S_FUTURE_EXPANSION) & M_FUTURE_EXPANSION)
21242 
21243 #define S_FUTURE_EXPANSION_EE    1
21244 #define M_FUTURE_EXPANSION_EE    0x7fffffffU
21245 #define V_FUTURE_EXPANSION_EE(x) ((x) << S_FUTURE_EXPANSION_EE)
21246 #define G_FUTURE_EXPANSION_EE(x) (((x) >> S_FUTURE_EXPANSION_EE) & M_FUTURE_EXPANSION_EE)
21247 
21248 #define A_MA_PARITY_ERROR_ENABLE2 0x7800
21249 
21250 #define S_ARB4_PAR_WRQUEUE_ERROR_EN    1
21251 #define V_ARB4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR_EN)
21252 #define F_ARB4_PAR_WRQUEUE_ERROR_EN    V_ARB4_PAR_WRQUEUE_ERROR_EN(1U)
21253 
21254 #define S_ARB4_PAR_RDQUEUE_ERROR_EN    0
21255 #define V_ARB4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR_EN)
21256 #define F_ARB4_PAR_RDQUEUE_ERROR_EN    V_ARB4_PAR_RDQUEUE_ERROR_EN(1U)
21257 
21258 #define S_CL14_PAR_WRQUEUE_ERROR_EN    14
21259 #define V_CL14_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL14_PAR_WRQUEUE_ERROR_EN)
21260 #define F_CL14_PAR_WRQUEUE_ERROR_EN    V_CL14_PAR_WRQUEUE_ERROR_EN(1U)
21261 
21262 #define S_CL13_PAR_WRQUEUE_ERROR_EN    13
21263 #define V_CL13_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL13_PAR_WRQUEUE_ERROR_EN)
21264 #define F_CL13_PAR_WRQUEUE_ERROR_EN    V_CL13_PAR_WRQUEUE_ERROR_EN(1U)
21265 
21266 #define S_CL12_PAR_WRQUEUE_ERROR_EN    12
21267 #define V_CL12_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL12_PAR_WRQUEUE_ERROR_EN)
21268 #define F_CL12_PAR_WRQUEUE_ERROR_EN    V_CL12_PAR_WRQUEUE_ERROR_EN(1U)
21269 
21270 #define S_CL11_PAR_WRQUEUE_ERROR_EN    11
21271 #define V_CL11_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL11_PAR_WRQUEUE_ERROR_EN)
21272 #define F_CL11_PAR_WRQUEUE_ERROR_EN    V_CL11_PAR_WRQUEUE_ERROR_EN(1U)
21273 
21274 #define S_T7_CL10_PAR_WRQUEUE_ERROR_EN    10
21275 #define V_T7_CL10_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL10_PAR_WRQUEUE_ERROR_EN)
21276 #define F_T7_CL10_PAR_WRQUEUE_ERROR_EN    V_T7_CL10_PAR_WRQUEUE_ERROR_EN(1U)
21277 
21278 #define S_T7_CL9_PAR_WRQUEUE_ERROR_EN    9
21279 #define V_T7_CL9_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL9_PAR_WRQUEUE_ERROR_EN)
21280 #define F_T7_CL9_PAR_WRQUEUE_ERROR_EN    V_T7_CL9_PAR_WRQUEUE_ERROR_EN(1U)
21281 
21282 #define S_T7_CL8_PAR_WRQUEUE_ERROR_EN    8
21283 #define V_T7_CL8_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL8_PAR_WRQUEUE_ERROR_EN)
21284 #define F_T7_CL8_PAR_WRQUEUE_ERROR_EN    V_T7_CL8_PAR_WRQUEUE_ERROR_EN(1U)
21285 
21286 #define S_T7_CL7_PAR_WRQUEUE_ERROR_EN    7
21287 #define V_T7_CL7_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL7_PAR_WRQUEUE_ERROR_EN)
21288 #define F_T7_CL7_PAR_WRQUEUE_ERROR_EN    V_T7_CL7_PAR_WRQUEUE_ERROR_EN(1U)
21289 
21290 #define S_T7_CL6_PAR_WRQUEUE_ERROR_EN    6
21291 #define V_T7_CL6_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL6_PAR_WRQUEUE_ERROR_EN)
21292 #define F_T7_CL6_PAR_WRQUEUE_ERROR_EN    V_T7_CL6_PAR_WRQUEUE_ERROR_EN(1U)
21293 
21294 #define S_T7_CL5_PAR_WRQUEUE_ERROR_EN    5
21295 #define V_T7_CL5_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL5_PAR_WRQUEUE_ERROR_EN)
21296 #define F_T7_CL5_PAR_WRQUEUE_ERROR_EN    V_T7_CL5_PAR_WRQUEUE_ERROR_EN(1U)
21297 
21298 #define S_T7_CL4_PAR_WRQUEUE_ERROR_EN    4
21299 #define V_T7_CL4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL4_PAR_WRQUEUE_ERROR_EN)
21300 #define F_T7_CL4_PAR_WRQUEUE_ERROR_EN    V_T7_CL4_PAR_WRQUEUE_ERROR_EN(1U)
21301 
21302 #define S_T7_CL3_PAR_WRQUEUE_ERROR_EN    3
21303 #define V_T7_CL3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL3_PAR_WRQUEUE_ERROR_EN)
21304 #define F_T7_CL3_PAR_WRQUEUE_ERROR_EN    V_T7_CL3_PAR_WRQUEUE_ERROR_EN(1U)
21305 
21306 #define S_T7_CL2_PAR_WRQUEUE_ERROR_EN    2
21307 #define V_T7_CL2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL2_PAR_WRQUEUE_ERROR_EN)
21308 #define F_T7_CL2_PAR_WRQUEUE_ERROR_EN    V_T7_CL2_PAR_WRQUEUE_ERROR_EN(1U)
21309 
21310 #define S_T7_CL1_PAR_WRQUEUE_ERROR_EN    1
21311 #define V_T7_CL1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL1_PAR_WRQUEUE_ERROR_EN)
21312 #define F_T7_CL1_PAR_WRQUEUE_ERROR_EN    V_T7_CL1_PAR_WRQUEUE_ERROR_EN(1U)
21313 
21314 #define S_T7_CL0_PAR_WRQUEUE_ERROR_EN    0
21315 #define V_T7_CL0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL0_PAR_WRQUEUE_ERROR_EN)
21316 #define F_T7_CL0_PAR_WRQUEUE_ERROR_EN    V_T7_CL0_PAR_WRQUEUE_ERROR_EN(1U)
21317 
21318 #define A_MA_PARITY_ERROR_STATUS2 0x7804
21319 
21320 #define S_ARB4_PAR_WRQUEUE_ERROR    1
21321 #define V_ARB4_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR)
21322 #define F_ARB4_PAR_WRQUEUE_ERROR    V_ARB4_PAR_WRQUEUE_ERROR(1U)
21323 
21324 #define S_ARB4_PAR_RDQUEUE_ERROR    0
21325 #define V_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR)
21326 #define F_ARB4_PAR_RDQUEUE_ERROR    V_ARB4_PAR_RDQUEUE_ERROR(1U)
21327 
21328 #define S_CL14_PAR_WRQUEUE_ERROR    14
21329 #define V_CL14_PAR_WRQUEUE_ERROR(x) ((x) << S_CL14_PAR_WRQUEUE_ERROR)
21330 #define F_CL14_PAR_WRQUEUE_ERROR    V_CL14_PAR_WRQUEUE_ERROR(1U)
21331 
21332 #define S_CL13_PAR_WRQUEUE_ERROR    13
21333 #define V_CL13_PAR_WRQUEUE_ERROR(x) ((x) << S_CL13_PAR_WRQUEUE_ERROR)
21334 #define F_CL13_PAR_WRQUEUE_ERROR    V_CL13_PAR_WRQUEUE_ERROR(1U)
21335 
21336 #define S_CL12_PAR_WRQUEUE_ERROR    12
21337 #define V_CL12_PAR_WRQUEUE_ERROR(x) ((x) << S_CL12_PAR_WRQUEUE_ERROR)
21338 #define F_CL12_PAR_WRQUEUE_ERROR    V_CL12_PAR_WRQUEUE_ERROR(1U)
21339 
21340 #define S_CL11_PAR_WRQUEUE_ERROR    11
21341 #define V_CL11_PAR_WRQUEUE_ERROR(x) ((x) << S_CL11_PAR_WRQUEUE_ERROR)
21342 #define F_CL11_PAR_WRQUEUE_ERROR    V_CL11_PAR_WRQUEUE_ERROR(1U)
21343 
21344 #define S_T7_CL10_PAR_WRQUEUE_ERROR    10
21345 #define V_T7_CL10_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL10_PAR_WRQUEUE_ERROR)
21346 #define F_T7_CL10_PAR_WRQUEUE_ERROR    V_T7_CL10_PAR_WRQUEUE_ERROR(1U)
21347 
21348 #define S_T7_CL9_PAR_WRQUEUE_ERROR    9
21349 #define V_T7_CL9_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL9_PAR_WRQUEUE_ERROR)
21350 #define F_T7_CL9_PAR_WRQUEUE_ERROR    V_T7_CL9_PAR_WRQUEUE_ERROR(1U)
21351 
21352 #define S_T7_CL8_PAR_WRQUEUE_ERROR    8
21353 #define V_T7_CL8_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL8_PAR_WRQUEUE_ERROR)
21354 #define F_T7_CL8_PAR_WRQUEUE_ERROR    V_T7_CL8_PAR_WRQUEUE_ERROR(1U)
21355 
21356 #define S_T7_CL7_PAR_WRQUEUE_ERROR    7
21357 #define V_T7_CL7_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL7_PAR_WRQUEUE_ERROR)
21358 #define F_T7_CL7_PAR_WRQUEUE_ERROR    V_T7_CL7_PAR_WRQUEUE_ERROR(1U)
21359 
21360 #define S_T7_CL6_PAR_WRQUEUE_ERROR    6
21361 #define V_T7_CL6_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL6_PAR_WRQUEUE_ERROR)
21362 #define F_T7_CL6_PAR_WRQUEUE_ERROR    V_T7_CL6_PAR_WRQUEUE_ERROR(1U)
21363 
21364 #define S_T7_CL5_PAR_WRQUEUE_ERROR    5
21365 #define V_T7_CL5_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL5_PAR_WRQUEUE_ERROR)
21366 #define F_T7_CL5_PAR_WRQUEUE_ERROR    V_T7_CL5_PAR_WRQUEUE_ERROR(1U)
21367 
21368 #define S_T7_CL4_PAR_WRQUEUE_ERROR    4
21369 #define V_T7_CL4_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL4_PAR_WRQUEUE_ERROR)
21370 #define F_T7_CL4_PAR_WRQUEUE_ERROR    V_T7_CL4_PAR_WRQUEUE_ERROR(1U)
21371 
21372 #define S_T7_CL3_PAR_WRQUEUE_ERROR    3
21373 #define V_T7_CL3_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL3_PAR_WRQUEUE_ERROR)
21374 #define F_T7_CL3_PAR_WRQUEUE_ERROR    V_T7_CL3_PAR_WRQUEUE_ERROR(1U)
21375 
21376 #define S_T7_CL2_PAR_WRQUEUE_ERROR    2
21377 #define V_T7_CL2_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL2_PAR_WRQUEUE_ERROR)
21378 #define F_T7_CL2_PAR_WRQUEUE_ERROR    V_T7_CL2_PAR_WRQUEUE_ERROR(1U)
21379 
21380 #define S_T7_CL1_PAR_WRQUEUE_ERROR    1
21381 #define V_T7_CL1_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL1_PAR_WRQUEUE_ERROR)
21382 #define F_T7_CL1_PAR_WRQUEUE_ERROR    V_T7_CL1_PAR_WRQUEUE_ERROR(1U)
21383 
21384 #define S_T7_CL0_PAR_WRQUEUE_ERROR    0
21385 #define V_T7_CL0_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL0_PAR_WRQUEUE_ERROR)
21386 #define F_T7_CL0_PAR_WRQUEUE_ERROR    V_T7_CL0_PAR_WRQUEUE_ERROR(1U)
21387 
21388 #define A_MA_EXT_MEMORY1_BAR 0x7808
21389 
21390 #define S_EXT_MEM1_BASE    16
21391 #define M_EXT_MEM1_BASE    0xfffU
21392 #define V_EXT_MEM1_BASE(x) ((x) << S_EXT_MEM1_BASE)
21393 #define G_EXT_MEM1_BASE(x) (((x) >> S_EXT_MEM1_BASE) & M_EXT_MEM1_BASE)
21394 
21395 #define S_EXT_MEM1_SIZE    0
21396 #define M_EXT_MEM1_SIZE    0xfffU
21397 #define V_EXT_MEM1_SIZE(x) ((x) << S_EXT_MEM1_SIZE)
21398 #define G_EXT_MEM1_SIZE(x) (((x) >> S_EXT_MEM1_SIZE) & M_EXT_MEM1_SIZE)
21399 
21400 #define S_T7_EXT_MEM1_BASE    16
21401 #define M_T7_EXT_MEM1_BASE    0xffffU
21402 #define V_T7_EXT_MEM1_BASE(x) ((x) << S_T7_EXT_MEM1_BASE)
21403 #define G_T7_EXT_MEM1_BASE(x) (((x) >> S_T7_EXT_MEM1_BASE) & M_T7_EXT_MEM1_BASE)
21404 
21405 #define S_T7_EXT_MEM1_SIZE    0
21406 #define M_T7_EXT_MEM1_SIZE    0xffffU
21407 #define V_T7_EXT_MEM1_SIZE(x) ((x) << S_T7_EXT_MEM1_SIZE)
21408 #define G_T7_EXT_MEM1_SIZE(x) (((x) >> S_T7_EXT_MEM1_SIZE) & M_T7_EXT_MEM1_SIZE)
21409 
21410 #define A_MA_PMTX_THROTTLE 0x780c
21411 
21412 #define S_FL_ENABLE    31
21413 #define V_FL_ENABLE(x) ((x) << S_FL_ENABLE)
21414 #define F_FL_ENABLE    V_FL_ENABLE(1U)
21415 
21416 #define S_FL_LIMIT    0
21417 #define M_FL_LIMIT    0xffU
21418 #define V_FL_LIMIT(x) ((x) << S_FL_LIMIT)
21419 #define G_FL_LIMIT(x) (((x) >> S_FL_LIMIT) & M_FL_LIMIT)
21420 
21421 #define A_MA_PMRX_THROTTLE 0x7810
21422 #define A_MA_SGE_TH0_WRDATA_CNT 0x7814
21423 #define A_MA_SGE_TH1_WRDATA_CNT 0x7818
21424 #define A_MA_ULPTX_WRDATA_CNT 0x781c
21425 #define A_MA_ULPRX_WRDATA_CNT 0x7820
21426 #define A_MA_ULPTXRX_WRDATA_CNT 0x7824
21427 #define A_MA_TP_TH0_WRDATA_CNT 0x7828
21428 #define A_MA_TP_TH1_WRDATA_CNT 0x782c
21429 #define A_MA_LE_WRDATA_CNT 0x7830
21430 #define A_MA_CIM_WRDATA_CNT 0x7834
21431 #define A_MA_CIM_TH0_WRDATA_CNT 0x7834
21432 #define A_MA_PCIE_WRDATA_CNT 0x7838
21433 #define A_MA_PMTX_WRDATA_CNT 0x783c
21434 #define A_MA_PMRX_WRDATA_CNT 0x7840
21435 #define A_MA_HMA_WRDATA_CNT 0x7844
21436 #define A_MA_SGE_TH0_RDDATA_CNT 0x7848
21437 #define A_MA_SGE_TH1_RDDATA_CNT 0x784c
21438 #define A_MA_ULPTX_RDDATA_CNT 0x7850
21439 #define A_MA_ULPRX_RDDATA_CNT 0x7854
21440 #define A_MA_ULPTXRX_RDDATA_CNT 0x7858
21441 #define A_MA_TP_TH0_RDDATA_CNT 0x785c
21442 #define A_MA_TP_TH1_RDDATA_CNT 0x7860
21443 #define A_MA_LE_RDDATA_CNT 0x7864
21444 #define A_MA_CIM_RDDATA_CNT 0x7868
21445 #define A_MA_CIM_TH0_RDDATA_CNT 0x7868
21446 #define A_MA_PCIE_RDDATA_CNT 0x786c
21447 #define A_MA_PMTX_RDDATA_CNT 0x7870
21448 #define A_MA_PMRX_RDDATA_CNT 0x7874
21449 #define A_MA_HMA_RDDATA_CNT 0x7878
21450 #define A_MA_EDRAM0_WRDATA_CNT1 0x787c
21451 #define A_MA_EXIT_ADDR_FAULT 0x787c
21452 
21453 #define S_EXIT_ADDR_FAULT    0
21454 #define V_EXIT_ADDR_FAULT(x) ((x) << S_EXIT_ADDR_FAULT)
21455 #define F_EXIT_ADDR_FAULT    V_EXIT_ADDR_FAULT(1U)
21456 
21457 #define A_MA_EDRAM0_WRDATA_CNT0 0x7880
21458 #define A_MA_DDR_DEVICE_CFG 0x7880
21459 
21460 #define S_MEM_WIDTH    1
21461 #define M_MEM_WIDTH    0x7U
21462 #define V_MEM_WIDTH(x) ((x) << S_MEM_WIDTH)
21463 #define G_MEM_WIDTH(x) (((x) >> S_MEM_WIDTH) & M_MEM_WIDTH)
21464 
21465 #define S_DDR_MODE    0
21466 #define V_DDR_MODE(x) ((x) << S_DDR_MODE)
21467 #define F_DDR_MODE    V_DDR_MODE(1U)
21468 
21469 #define A_MA_EDRAM1_WRDATA_CNT1 0x7884
21470 #define A_MA_PARITY_ERROR_ENABLE3 0x7884
21471 
21472 #define S_CL14_PAR_RDQUEUE_ERROR_EN    14
21473 #define V_CL14_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL14_PAR_RDQUEUE_ERROR_EN)
21474 #define F_CL14_PAR_RDQUEUE_ERROR_EN    V_CL14_PAR_RDQUEUE_ERROR_EN(1U)
21475 
21476 #define S_CL13_PAR_RDQUEUE_ERROR_EN    13
21477 #define V_CL13_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL13_PAR_RDQUEUE_ERROR_EN)
21478 #define F_CL13_PAR_RDQUEUE_ERROR_EN    V_CL13_PAR_RDQUEUE_ERROR_EN(1U)
21479 
21480 #define S_CL12_PAR_RDQUEUE_ERROR_EN    12
21481 #define V_CL12_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL12_PAR_RDQUEUE_ERROR_EN)
21482 #define F_CL12_PAR_RDQUEUE_ERROR_EN    V_CL12_PAR_RDQUEUE_ERROR_EN(1U)
21483 
21484 #define S_CL11_PAR_RDQUEUE_ERROR_EN    11
21485 #define V_CL11_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL11_PAR_RDQUEUE_ERROR_EN)
21486 #define F_CL11_PAR_RDQUEUE_ERROR_EN    V_CL11_PAR_RDQUEUE_ERROR_EN(1U)
21487 
21488 #define A_MA_EDRAM1_WRDATA_CNT0 0x7888
21489 #define A_MA_PARITY_ERROR_STATUS3 0x7888
21490 
21491 #define S_CL14_PAR_RDQUEUE_ERROR    14
21492 #define V_CL14_PAR_RDQUEUE_ERROR(x) ((x) << S_CL14_PAR_RDQUEUE_ERROR)
21493 #define F_CL14_PAR_RDQUEUE_ERROR    V_CL14_PAR_RDQUEUE_ERROR(1U)
21494 
21495 #define S_CL13_PAR_RDQUEUE_ERROR    13
21496 #define V_CL13_PAR_RDQUEUE_ERROR(x) ((x) << S_CL13_PAR_RDQUEUE_ERROR)
21497 #define F_CL13_PAR_RDQUEUE_ERROR    V_CL13_PAR_RDQUEUE_ERROR(1U)
21498 
21499 #define S_CL12_PAR_RDQUEUE_ERROR    12
21500 #define V_CL12_PAR_RDQUEUE_ERROR(x) ((x) << S_CL12_PAR_RDQUEUE_ERROR)
21501 #define F_CL12_PAR_RDQUEUE_ERROR    V_CL12_PAR_RDQUEUE_ERROR(1U)
21502 
21503 #define S_CL11_PAR_RDQUEUE_ERROR    11
21504 #define V_CL11_PAR_RDQUEUE_ERROR(x) ((x) << S_CL11_PAR_RDQUEUE_ERROR)
21505 #define F_CL11_PAR_RDQUEUE_ERROR    V_CL11_PAR_RDQUEUE_ERROR(1U)
21506 
21507 #define A_MA_EXT_MEMORY0_WRDATA_CNT1 0x788c
21508 #define A_MA_EXT_MEMORY0_WRDATA_CNT0 0x7890
21509 #define A_MA_HOST_MEMORY_WRDATA_CNT1 0x7894
21510 #define A_MA_HOST_MEMORY_WRDATA_CNT0 0x7898
21511 #define A_MA_EXT_MEMORY1_WRDATA_CNT1 0x789c
21512 #define A_MA_EXT_MEMORY1_WRDATA_CNT0 0x78a0
21513 #define A_MA_EDRAM0_RDDATA_CNT1 0x78a4
21514 #define A_MA_EDRAM0_RDDATA_CNT0 0x78a8
21515 #define A_MA_EDRAM1_RDDATA_CNT1 0x78ac
21516 #define A_MA_EDRAM1_RDDATA_CNT0 0x78b0
21517 #define A_MA_EXT_MEMORY0_RDDATA_CNT1 0x78b4
21518 #define A_MA_EXT_MEMORY0_RDDATA_CNT0 0x78b8
21519 #define A_MA_HOST_MEMORY_RDDATA_CNT1 0x78bc
21520 #define A_MA_HOST_MEMORY_RDDATA_CNT0 0x78c0
21521 #define A_MA_EXT_MEMORY1_RDDATA_CNT1 0x78c4
21522 #define A_MA_EXT_MEMORY1_RDDATA_CNT0 0x78c8
21523 #define A_MA_TIMEOUT_CFG 0x78cc
21524 
21525 #define S_CLR    31
21526 #define V_CLR(x) ((x) << S_CLR)
21527 #define F_CLR    V_CLR(1U)
21528 
21529 #define S_CNT_LOCK    30
21530 #define V_CNT_LOCK(x) ((x) << S_CNT_LOCK)
21531 #define F_CNT_LOCK    V_CNT_LOCK(1U)
21532 
21533 #define S_WRN    24
21534 #define V_WRN(x) ((x) << S_WRN)
21535 #define F_WRN    V_WRN(1U)
21536 
21537 #define S_DIR    23
21538 #define V_DIR(x) ((x) << S_DIR)
21539 #define F_DIR    V_DIR(1U)
21540 
21541 #define S_TO_BUS    22
21542 #define V_TO_BUS(x) ((x) << S_TO_BUS)
21543 #define F_TO_BUS    V_TO_BUS(1U)
21544 
21545 #define S_CLIENT    16
21546 #define M_CLIENT    0xfU
21547 #define V_CLIENT(x) ((x) << S_CLIENT)
21548 #define G_CLIENT(x) (((x) >> S_CLIENT) & M_CLIENT)
21549 
21550 #define S_DELAY    0
21551 #define M_DELAY    0xffffU
21552 #define V_DELAY(x) ((x) << S_DELAY)
21553 #define G_DELAY(x) (((x) >> S_DELAY) & M_DELAY)
21554 
21555 #define A_MA_TIMEOUT_CNT 0x78d0
21556 
21557 #define S_CNT_VAL    0
21558 #define M_CNT_VAL    0xffffU
21559 #define V_CNT_VAL(x) ((x) << S_CNT_VAL)
21560 #define G_CNT_VAL(x) (((x) >> S_CNT_VAL) & M_CNT_VAL)
21561 
21562 #define A_MA_WRITE_TIMEOUT_ERROR_ENABLE 0x78d4
21563 
21564 #define S_FUTURE_CEXPANSION    29
21565 #define M_FUTURE_CEXPANSION    0x7U
21566 #define V_FUTURE_CEXPANSION(x) ((x) << S_FUTURE_CEXPANSION)
21567 #define G_FUTURE_CEXPANSION(x) (((x) >> S_FUTURE_CEXPANSION) & M_FUTURE_CEXPANSION)
21568 
21569 #define S_CL12_WR_CMD_TO_EN    28
21570 #define V_CL12_WR_CMD_TO_EN(x) ((x) << S_CL12_WR_CMD_TO_EN)
21571 #define F_CL12_WR_CMD_TO_EN    V_CL12_WR_CMD_TO_EN(1U)
21572 
21573 #define S_CL11_WR_CMD_TO_EN    27
21574 #define V_CL11_WR_CMD_TO_EN(x) ((x) << S_CL11_WR_CMD_TO_EN)
21575 #define F_CL11_WR_CMD_TO_EN    V_CL11_WR_CMD_TO_EN(1U)
21576 
21577 #define S_CL10_WR_CMD_TO_EN    26
21578 #define V_CL10_WR_CMD_TO_EN(x) ((x) << S_CL10_WR_CMD_TO_EN)
21579 #define F_CL10_WR_CMD_TO_EN    V_CL10_WR_CMD_TO_EN(1U)
21580 
21581 #define S_CL9_WR_CMD_TO_EN    25
21582 #define V_CL9_WR_CMD_TO_EN(x) ((x) << S_CL9_WR_CMD_TO_EN)
21583 #define F_CL9_WR_CMD_TO_EN    V_CL9_WR_CMD_TO_EN(1U)
21584 
21585 #define S_CL8_WR_CMD_TO_EN    24
21586 #define V_CL8_WR_CMD_TO_EN(x) ((x) << S_CL8_WR_CMD_TO_EN)
21587 #define F_CL8_WR_CMD_TO_EN    V_CL8_WR_CMD_TO_EN(1U)
21588 
21589 #define S_CL7_WR_CMD_TO_EN    23
21590 #define V_CL7_WR_CMD_TO_EN(x) ((x) << S_CL7_WR_CMD_TO_EN)
21591 #define F_CL7_WR_CMD_TO_EN    V_CL7_WR_CMD_TO_EN(1U)
21592 
21593 #define S_CL6_WR_CMD_TO_EN    22
21594 #define V_CL6_WR_CMD_TO_EN(x) ((x) << S_CL6_WR_CMD_TO_EN)
21595 #define F_CL6_WR_CMD_TO_EN    V_CL6_WR_CMD_TO_EN(1U)
21596 
21597 #define S_CL5_WR_CMD_TO_EN    21
21598 #define V_CL5_WR_CMD_TO_EN(x) ((x) << S_CL5_WR_CMD_TO_EN)
21599 #define F_CL5_WR_CMD_TO_EN    V_CL5_WR_CMD_TO_EN(1U)
21600 
21601 #define S_CL4_WR_CMD_TO_EN    20
21602 #define V_CL4_WR_CMD_TO_EN(x) ((x) << S_CL4_WR_CMD_TO_EN)
21603 #define F_CL4_WR_CMD_TO_EN    V_CL4_WR_CMD_TO_EN(1U)
21604 
21605 #define S_CL3_WR_CMD_TO_EN    19
21606 #define V_CL3_WR_CMD_TO_EN(x) ((x) << S_CL3_WR_CMD_TO_EN)
21607 #define F_CL3_WR_CMD_TO_EN    V_CL3_WR_CMD_TO_EN(1U)
21608 
21609 #define S_CL2_WR_CMD_TO_EN    18
21610 #define V_CL2_WR_CMD_TO_EN(x) ((x) << S_CL2_WR_CMD_TO_EN)
21611 #define F_CL2_WR_CMD_TO_EN    V_CL2_WR_CMD_TO_EN(1U)
21612 
21613 #define S_CL1_WR_CMD_TO_EN    17
21614 #define V_CL1_WR_CMD_TO_EN(x) ((x) << S_CL1_WR_CMD_TO_EN)
21615 #define F_CL1_WR_CMD_TO_EN    V_CL1_WR_CMD_TO_EN(1U)
21616 
21617 #define S_CL0_WR_CMD_TO_EN    16
21618 #define V_CL0_WR_CMD_TO_EN(x) ((x) << S_CL0_WR_CMD_TO_EN)
21619 #define F_CL0_WR_CMD_TO_EN    V_CL0_WR_CMD_TO_EN(1U)
21620 
21621 #define S_FUTURE_DEXPANSION    13
21622 #define M_FUTURE_DEXPANSION    0x7U
21623 #define V_FUTURE_DEXPANSION(x) ((x) << S_FUTURE_DEXPANSION)
21624 #define G_FUTURE_DEXPANSION(x) (((x) >> S_FUTURE_DEXPANSION) & M_FUTURE_DEXPANSION)
21625 
21626 #define S_CL12_WR_DATA_TO_EN    12
21627 #define V_CL12_WR_DATA_TO_EN(x) ((x) << S_CL12_WR_DATA_TO_EN)
21628 #define F_CL12_WR_DATA_TO_EN    V_CL12_WR_DATA_TO_EN(1U)
21629 
21630 #define S_CL11_WR_DATA_TO_EN    11
21631 #define V_CL11_WR_DATA_TO_EN(x) ((x) << S_CL11_WR_DATA_TO_EN)
21632 #define F_CL11_WR_DATA_TO_EN    V_CL11_WR_DATA_TO_EN(1U)
21633 
21634 #define S_CL10_WR_DATA_TO_EN    10
21635 #define V_CL10_WR_DATA_TO_EN(x) ((x) << S_CL10_WR_DATA_TO_EN)
21636 #define F_CL10_WR_DATA_TO_EN    V_CL10_WR_DATA_TO_EN(1U)
21637 
21638 #define S_CL9_WR_DATA_TO_EN    9
21639 #define V_CL9_WR_DATA_TO_EN(x) ((x) << S_CL9_WR_DATA_TO_EN)
21640 #define F_CL9_WR_DATA_TO_EN    V_CL9_WR_DATA_TO_EN(1U)
21641 
21642 #define S_CL8_WR_DATA_TO_EN    8
21643 #define V_CL8_WR_DATA_TO_EN(x) ((x) << S_CL8_WR_DATA_TO_EN)
21644 #define F_CL8_WR_DATA_TO_EN    V_CL8_WR_DATA_TO_EN(1U)
21645 
21646 #define S_CL7_WR_DATA_TO_EN    7
21647 #define V_CL7_WR_DATA_TO_EN(x) ((x) << S_CL7_WR_DATA_TO_EN)
21648 #define F_CL7_WR_DATA_TO_EN    V_CL7_WR_DATA_TO_EN(1U)
21649 
21650 #define S_CL6_WR_DATA_TO_EN    6
21651 #define V_CL6_WR_DATA_TO_EN(x) ((x) << S_CL6_WR_DATA_TO_EN)
21652 #define F_CL6_WR_DATA_TO_EN    V_CL6_WR_DATA_TO_EN(1U)
21653 
21654 #define S_CL5_WR_DATA_TO_EN    5
21655 #define V_CL5_WR_DATA_TO_EN(x) ((x) << S_CL5_WR_DATA_TO_EN)
21656 #define F_CL5_WR_DATA_TO_EN    V_CL5_WR_DATA_TO_EN(1U)
21657 
21658 #define S_CL4_WR_DATA_TO_EN    4
21659 #define V_CL4_WR_DATA_TO_EN(x) ((x) << S_CL4_WR_DATA_TO_EN)
21660 #define F_CL4_WR_DATA_TO_EN    V_CL4_WR_DATA_TO_EN(1U)
21661 
21662 #define S_CL3_WR_DATA_TO_EN    3
21663 #define V_CL3_WR_DATA_TO_EN(x) ((x) << S_CL3_WR_DATA_TO_EN)
21664 #define F_CL3_WR_DATA_TO_EN    V_CL3_WR_DATA_TO_EN(1U)
21665 
21666 #define S_CL2_WR_DATA_TO_EN    2
21667 #define V_CL2_WR_DATA_TO_EN(x) ((x) << S_CL2_WR_DATA_TO_EN)
21668 #define F_CL2_WR_DATA_TO_EN    V_CL2_WR_DATA_TO_EN(1U)
21669 
21670 #define S_CL1_WR_DATA_TO_EN    1
21671 #define V_CL1_WR_DATA_TO_EN(x) ((x) << S_CL1_WR_DATA_TO_EN)
21672 #define F_CL1_WR_DATA_TO_EN    V_CL1_WR_DATA_TO_EN(1U)
21673 
21674 #define S_CL0_WR_DATA_TO_EN    0
21675 #define V_CL0_WR_DATA_TO_EN(x) ((x) << S_CL0_WR_DATA_TO_EN)
21676 #define F_CL0_WR_DATA_TO_EN    V_CL0_WR_DATA_TO_EN(1U)
21677 
21678 #define S_FUTURE_CEXPANSION_WTE    29
21679 #define M_FUTURE_CEXPANSION_WTE    0x7U
21680 #define V_FUTURE_CEXPANSION_WTE(x) ((x) << S_FUTURE_CEXPANSION_WTE)
21681 #define G_FUTURE_CEXPANSION_WTE(x) (((x) >> S_FUTURE_CEXPANSION_WTE) & M_FUTURE_CEXPANSION_WTE)
21682 
21683 #define S_FUTURE_DEXPANSION_WTE    13
21684 #define M_FUTURE_DEXPANSION_WTE    0x7U
21685 #define V_FUTURE_DEXPANSION_WTE(x) ((x) << S_FUTURE_DEXPANSION_WTE)
21686 #define G_FUTURE_DEXPANSION_WTE(x) (((x) >> S_FUTURE_DEXPANSION_WTE) & M_FUTURE_DEXPANSION_WTE)
21687 
21688 #define S_T7_FUTURE_CEXPANSION_WTE    31
21689 #define V_T7_FUTURE_CEXPANSION_WTE(x) ((x) << S_T7_FUTURE_CEXPANSION_WTE)
21690 #define F_T7_FUTURE_CEXPANSION_WTE    V_T7_FUTURE_CEXPANSION_WTE(1U)
21691 
21692 #define S_CL14_WR_CMD_TO_EN    30
21693 #define V_CL14_WR_CMD_TO_EN(x) ((x) << S_CL14_WR_CMD_TO_EN)
21694 #define F_CL14_WR_CMD_TO_EN    V_CL14_WR_CMD_TO_EN(1U)
21695 
21696 #define S_CL13_WR_CMD_TO_EN    29
21697 #define V_CL13_WR_CMD_TO_EN(x) ((x) << S_CL13_WR_CMD_TO_EN)
21698 #define F_CL13_WR_CMD_TO_EN    V_CL13_WR_CMD_TO_EN(1U)
21699 
21700 #define S_T7_FUTURE_DEXPANSION_WTE    15
21701 #define V_T7_FUTURE_DEXPANSION_WTE(x) ((x) << S_T7_FUTURE_DEXPANSION_WTE)
21702 #define F_T7_FUTURE_DEXPANSION_WTE    V_T7_FUTURE_DEXPANSION_WTE(1U)
21703 
21704 #define S_CL14_WR_DATA_TO_EN    14
21705 #define V_CL14_WR_DATA_TO_EN(x) ((x) << S_CL14_WR_DATA_TO_EN)
21706 #define F_CL14_WR_DATA_TO_EN    V_CL14_WR_DATA_TO_EN(1U)
21707 
21708 #define S_CL13_WR_DATA_TO_EN    13
21709 #define V_CL13_WR_DATA_TO_EN(x) ((x) << S_CL13_WR_DATA_TO_EN)
21710 #define F_CL13_WR_DATA_TO_EN    V_CL13_WR_DATA_TO_EN(1U)
21711 
21712 #define A_MA_WRITE_TIMEOUT_ERROR_STATUS 0x78d8
21713 
21714 #define S_CL12_WR_CMD_TO_ERROR    28
21715 #define V_CL12_WR_CMD_TO_ERROR(x) ((x) << S_CL12_WR_CMD_TO_ERROR)
21716 #define F_CL12_WR_CMD_TO_ERROR    V_CL12_WR_CMD_TO_ERROR(1U)
21717 
21718 #define S_CL11_WR_CMD_TO_ERROR    27
21719 #define V_CL11_WR_CMD_TO_ERROR(x) ((x) << S_CL11_WR_CMD_TO_ERROR)
21720 #define F_CL11_WR_CMD_TO_ERROR    V_CL11_WR_CMD_TO_ERROR(1U)
21721 
21722 #define S_CL10_WR_CMD_TO_ERROR    26
21723 #define V_CL10_WR_CMD_TO_ERROR(x) ((x) << S_CL10_WR_CMD_TO_ERROR)
21724 #define F_CL10_WR_CMD_TO_ERROR    V_CL10_WR_CMD_TO_ERROR(1U)
21725 
21726 #define S_CL9_WR_CMD_TO_ERROR    25
21727 #define V_CL9_WR_CMD_TO_ERROR(x) ((x) << S_CL9_WR_CMD_TO_ERROR)
21728 #define F_CL9_WR_CMD_TO_ERROR    V_CL9_WR_CMD_TO_ERROR(1U)
21729 
21730 #define S_CL8_WR_CMD_TO_ERROR    24
21731 #define V_CL8_WR_CMD_TO_ERROR(x) ((x) << S_CL8_WR_CMD_TO_ERROR)
21732 #define F_CL8_WR_CMD_TO_ERROR    V_CL8_WR_CMD_TO_ERROR(1U)
21733 
21734 #define S_CL7_WR_CMD_TO_ERROR    23
21735 #define V_CL7_WR_CMD_TO_ERROR(x) ((x) << S_CL7_WR_CMD_TO_ERROR)
21736 #define F_CL7_WR_CMD_TO_ERROR    V_CL7_WR_CMD_TO_ERROR(1U)
21737 
21738 #define S_CL6_WR_CMD_TO_ERROR    22
21739 #define V_CL6_WR_CMD_TO_ERROR(x) ((x) << S_CL6_WR_CMD_TO_ERROR)
21740 #define F_CL6_WR_CMD_TO_ERROR    V_CL6_WR_CMD_TO_ERROR(1U)
21741 
21742 #define S_CL5_WR_CMD_TO_ERROR    21
21743 #define V_CL5_WR_CMD_TO_ERROR(x) ((x) << S_CL5_WR_CMD_TO_ERROR)
21744 #define F_CL5_WR_CMD_TO_ERROR    V_CL5_WR_CMD_TO_ERROR(1U)
21745 
21746 #define S_CL4_WR_CMD_TO_ERROR    20
21747 #define V_CL4_WR_CMD_TO_ERROR(x) ((x) << S_CL4_WR_CMD_TO_ERROR)
21748 #define F_CL4_WR_CMD_TO_ERROR    V_CL4_WR_CMD_TO_ERROR(1U)
21749 
21750 #define S_CL3_WR_CMD_TO_ERROR    19
21751 #define V_CL3_WR_CMD_TO_ERROR(x) ((x) << S_CL3_WR_CMD_TO_ERROR)
21752 #define F_CL3_WR_CMD_TO_ERROR    V_CL3_WR_CMD_TO_ERROR(1U)
21753 
21754 #define S_CL2_WR_CMD_TO_ERROR    18
21755 #define V_CL2_WR_CMD_TO_ERROR(x) ((x) << S_CL2_WR_CMD_TO_ERROR)
21756 #define F_CL2_WR_CMD_TO_ERROR    V_CL2_WR_CMD_TO_ERROR(1U)
21757 
21758 #define S_CL1_WR_CMD_TO_ERROR    17
21759 #define V_CL1_WR_CMD_TO_ERROR(x) ((x) << S_CL1_WR_CMD_TO_ERROR)
21760 #define F_CL1_WR_CMD_TO_ERROR    V_CL1_WR_CMD_TO_ERROR(1U)
21761 
21762 #define S_CL0_WR_CMD_TO_ERROR    16
21763 #define V_CL0_WR_CMD_TO_ERROR(x) ((x) << S_CL0_WR_CMD_TO_ERROR)
21764 #define F_CL0_WR_CMD_TO_ERROR    V_CL0_WR_CMD_TO_ERROR(1U)
21765 
21766 #define S_CL12_WR_DATA_TO_ERROR    12
21767 #define V_CL12_WR_DATA_TO_ERROR(x) ((x) << S_CL12_WR_DATA_TO_ERROR)
21768 #define F_CL12_WR_DATA_TO_ERROR    V_CL12_WR_DATA_TO_ERROR(1U)
21769 
21770 #define S_CL11_WR_DATA_TO_ERROR    11
21771 #define V_CL11_WR_DATA_TO_ERROR(x) ((x) << S_CL11_WR_DATA_TO_ERROR)
21772 #define F_CL11_WR_DATA_TO_ERROR    V_CL11_WR_DATA_TO_ERROR(1U)
21773 
21774 #define S_CL10_WR_DATA_TO_ERROR    10
21775 #define V_CL10_WR_DATA_TO_ERROR(x) ((x) << S_CL10_WR_DATA_TO_ERROR)
21776 #define F_CL10_WR_DATA_TO_ERROR    V_CL10_WR_DATA_TO_ERROR(1U)
21777 
21778 #define S_CL9_WR_DATA_TO_ERROR    9
21779 #define V_CL9_WR_DATA_TO_ERROR(x) ((x) << S_CL9_WR_DATA_TO_ERROR)
21780 #define F_CL9_WR_DATA_TO_ERROR    V_CL9_WR_DATA_TO_ERROR(1U)
21781 
21782 #define S_CL8_WR_DATA_TO_ERROR    8
21783 #define V_CL8_WR_DATA_TO_ERROR(x) ((x) << S_CL8_WR_DATA_TO_ERROR)
21784 #define F_CL8_WR_DATA_TO_ERROR    V_CL8_WR_DATA_TO_ERROR(1U)
21785 
21786 #define S_CL7_WR_DATA_TO_ERROR    7
21787 #define V_CL7_WR_DATA_TO_ERROR(x) ((x) << S_CL7_WR_DATA_TO_ERROR)
21788 #define F_CL7_WR_DATA_TO_ERROR    V_CL7_WR_DATA_TO_ERROR(1U)
21789 
21790 #define S_CL6_WR_DATA_TO_ERROR    6
21791 #define V_CL6_WR_DATA_TO_ERROR(x) ((x) << S_CL6_WR_DATA_TO_ERROR)
21792 #define F_CL6_WR_DATA_TO_ERROR    V_CL6_WR_DATA_TO_ERROR(1U)
21793 
21794 #define S_CL5_WR_DATA_TO_ERROR    5
21795 #define V_CL5_WR_DATA_TO_ERROR(x) ((x) << S_CL5_WR_DATA_TO_ERROR)
21796 #define F_CL5_WR_DATA_TO_ERROR    V_CL5_WR_DATA_TO_ERROR(1U)
21797 
21798 #define S_CL4_WR_DATA_TO_ERROR    4
21799 #define V_CL4_WR_DATA_TO_ERROR(x) ((x) << S_CL4_WR_DATA_TO_ERROR)
21800 #define F_CL4_WR_DATA_TO_ERROR    V_CL4_WR_DATA_TO_ERROR(1U)
21801 
21802 #define S_CL3_WR_DATA_TO_ERROR    3
21803 #define V_CL3_WR_DATA_TO_ERROR(x) ((x) << S_CL3_WR_DATA_TO_ERROR)
21804 #define F_CL3_WR_DATA_TO_ERROR    V_CL3_WR_DATA_TO_ERROR(1U)
21805 
21806 #define S_CL2_WR_DATA_TO_ERROR    2
21807 #define V_CL2_WR_DATA_TO_ERROR(x) ((x) << S_CL2_WR_DATA_TO_ERROR)
21808 #define F_CL2_WR_DATA_TO_ERROR    V_CL2_WR_DATA_TO_ERROR(1U)
21809 
21810 #define S_CL1_WR_DATA_TO_ERROR    1
21811 #define V_CL1_WR_DATA_TO_ERROR(x) ((x) << S_CL1_WR_DATA_TO_ERROR)
21812 #define F_CL1_WR_DATA_TO_ERROR    V_CL1_WR_DATA_TO_ERROR(1U)
21813 
21814 #define S_CL0_WR_DATA_TO_ERROR    0
21815 #define V_CL0_WR_DATA_TO_ERROR(x) ((x) << S_CL0_WR_DATA_TO_ERROR)
21816 #define F_CL0_WR_DATA_TO_ERROR    V_CL0_WR_DATA_TO_ERROR(1U)
21817 
21818 #define S_FUTURE_CEXPANSION_WTS    29
21819 #define M_FUTURE_CEXPANSION_WTS    0x7U
21820 #define V_FUTURE_CEXPANSION_WTS(x) ((x) << S_FUTURE_CEXPANSION_WTS)
21821 #define G_FUTURE_CEXPANSION_WTS(x) (((x) >> S_FUTURE_CEXPANSION_WTS) & M_FUTURE_CEXPANSION_WTS)
21822 
21823 #define S_FUTURE_DEXPANSION_WTS    13
21824 #define M_FUTURE_DEXPANSION_WTS    0x7U
21825 #define V_FUTURE_DEXPANSION_WTS(x) ((x) << S_FUTURE_DEXPANSION_WTS)
21826 #define G_FUTURE_DEXPANSION_WTS(x) (((x) >> S_FUTURE_DEXPANSION_WTS) & M_FUTURE_DEXPANSION_WTS)
21827 
21828 #define S_T7_FUTURE_CEXPANSION_WTS    31
21829 #define V_T7_FUTURE_CEXPANSION_WTS(x) ((x) << S_T7_FUTURE_CEXPANSION_WTS)
21830 #define F_T7_FUTURE_CEXPANSION_WTS    V_T7_FUTURE_CEXPANSION_WTS(1U)
21831 
21832 #define S_CL14_WR_CMD_TO_ERROR    30
21833 #define V_CL14_WR_CMD_TO_ERROR(x) ((x) << S_CL14_WR_CMD_TO_ERROR)
21834 #define F_CL14_WR_CMD_TO_ERROR    V_CL14_WR_CMD_TO_ERROR(1U)
21835 
21836 #define S_CL13_WR_CMD_TO_ERROR    29
21837 #define V_CL13_WR_CMD_TO_ERROR(x) ((x) << S_CL13_WR_CMD_TO_ERROR)
21838 #define F_CL13_WR_CMD_TO_ERROR    V_CL13_WR_CMD_TO_ERROR(1U)
21839 
21840 #define S_T7_FUTURE_DEXPANSION_WTS    15
21841 #define V_T7_FUTURE_DEXPANSION_WTS(x) ((x) << S_T7_FUTURE_DEXPANSION_WTS)
21842 #define F_T7_FUTURE_DEXPANSION_WTS    V_T7_FUTURE_DEXPANSION_WTS(1U)
21843 
21844 #define S_CL14_WR_DATA_TO_ERROR    14
21845 #define V_CL14_WR_DATA_TO_ERROR(x) ((x) << S_CL14_WR_DATA_TO_ERROR)
21846 #define F_CL14_WR_DATA_TO_ERROR    V_CL14_WR_DATA_TO_ERROR(1U)
21847 
21848 #define S_CL13_WR_DATA_TO_ERROR    13
21849 #define V_CL13_WR_DATA_TO_ERROR(x) ((x) << S_CL13_WR_DATA_TO_ERROR)
21850 #define F_CL13_WR_DATA_TO_ERROR    V_CL13_WR_DATA_TO_ERROR(1U)
21851 
21852 #define A_MA_READ_TIMEOUT_ERROR_ENABLE 0x78dc
21853 
21854 #define S_CL12_RD_CMD_TO_EN    28
21855 #define V_CL12_RD_CMD_TO_EN(x) ((x) << S_CL12_RD_CMD_TO_EN)
21856 #define F_CL12_RD_CMD_TO_EN    V_CL12_RD_CMD_TO_EN(1U)
21857 
21858 #define S_CL11_RD_CMD_TO_EN    27
21859 #define V_CL11_RD_CMD_TO_EN(x) ((x) << S_CL11_RD_CMD_TO_EN)
21860 #define F_CL11_RD_CMD_TO_EN    V_CL11_RD_CMD_TO_EN(1U)
21861 
21862 #define S_CL10_RD_CMD_TO_EN    26
21863 #define V_CL10_RD_CMD_TO_EN(x) ((x) << S_CL10_RD_CMD_TO_EN)
21864 #define F_CL10_RD_CMD_TO_EN    V_CL10_RD_CMD_TO_EN(1U)
21865 
21866 #define S_CL9_RD_CMD_TO_EN    25
21867 #define V_CL9_RD_CMD_TO_EN(x) ((x) << S_CL9_RD_CMD_TO_EN)
21868 #define F_CL9_RD_CMD_TO_EN    V_CL9_RD_CMD_TO_EN(1U)
21869 
21870 #define S_CL8_RD_CMD_TO_EN    24
21871 #define V_CL8_RD_CMD_TO_EN(x) ((x) << S_CL8_RD_CMD_TO_EN)
21872 #define F_CL8_RD_CMD_TO_EN    V_CL8_RD_CMD_TO_EN(1U)
21873 
21874 #define S_CL7_RD_CMD_TO_EN    23
21875 #define V_CL7_RD_CMD_TO_EN(x) ((x) << S_CL7_RD_CMD_TO_EN)
21876 #define F_CL7_RD_CMD_TO_EN    V_CL7_RD_CMD_TO_EN(1U)
21877 
21878 #define S_CL6_RD_CMD_TO_EN    22
21879 #define V_CL6_RD_CMD_TO_EN(x) ((x) << S_CL6_RD_CMD_TO_EN)
21880 #define F_CL6_RD_CMD_TO_EN    V_CL6_RD_CMD_TO_EN(1U)
21881 
21882 #define S_CL5_RD_CMD_TO_EN    21
21883 #define V_CL5_RD_CMD_TO_EN(x) ((x) << S_CL5_RD_CMD_TO_EN)
21884 #define F_CL5_RD_CMD_TO_EN    V_CL5_RD_CMD_TO_EN(1U)
21885 
21886 #define S_CL4_RD_CMD_TO_EN    20
21887 #define V_CL4_RD_CMD_TO_EN(x) ((x) << S_CL4_RD_CMD_TO_EN)
21888 #define F_CL4_RD_CMD_TO_EN    V_CL4_RD_CMD_TO_EN(1U)
21889 
21890 #define S_CL3_RD_CMD_TO_EN    19
21891 #define V_CL3_RD_CMD_TO_EN(x) ((x) << S_CL3_RD_CMD_TO_EN)
21892 #define F_CL3_RD_CMD_TO_EN    V_CL3_RD_CMD_TO_EN(1U)
21893 
21894 #define S_CL2_RD_CMD_TO_EN    18
21895 #define V_CL2_RD_CMD_TO_EN(x) ((x) << S_CL2_RD_CMD_TO_EN)
21896 #define F_CL2_RD_CMD_TO_EN    V_CL2_RD_CMD_TO_EN(1U)
21897 
21898 #define S_CL1_RD_CMD_TO_EN    17
21899 #define V_CL1_RD_CMD_TO_EN(x) ((x) << S_CL1_RD_CMD_TO_EN)
21900 #define F_CL1_RD_CMD_TO_EN    V_CL1_RD_CMD_TO_EN(1U)
21901 
21902 #define S_CL0_RD_CMD_TO_EN    16
21903 #define V_CL0_RD_CMD_TO_EN(x) ((x) << S_CL0_RD_CMD_TO_EN)
21904 #define F_CL0_RD_CMD_TO_EN    V_CL0_RD_CMD_TO_EN(1U)
21905 
21906 #define S_CL12_RD_DATA_TO_EN    12
21907 #define V_CL12_RD_DATA_TO_EN(x) ((x) << S_CL12_RD_DATA_TO_EN)
21908 #define F_CL12_RD_DATA_TO_EN    V_CL12_RD_DATA_TO_EN(1U)
21909 
21910 #define S_CL11_RD_DATA_TO_EN    11
21911 #define V_CL11_RD_DATA_TO_EN(x) ((x) << S_CL11_RD_DATA_TO_EN)
21912 #define F_CL11_RD_DATA_TO_EN    V_CL11_RD_DATA_TO_EN(1U)
21913 
21914 #define S_CL10_RD_DATA_TO_EN    10
21915 #define V_CL10_RD_DATA_TO_EN(x) ((x) << S_CL10_RD_DATA_TO_EN)
21916 #define F_CL10_RD_DATA_TO_EN    V_CL10_RD_DATA_TO_EN(1U)
21917 
21918 #define S_CL9_RD_DATA_TO_EN    9
21919 #define V_CL9_RD_DATA_TO_EN(x) ((x) << S_CL9_RD_DATA_TO_EN)
21920 #define F_CL9_RD_DATA_TO_EN    V_CL9_RD_DATA_TO_EN(1U)
21921 
21922 #define S_CL8_RD_DATA_TO_EN    8
21923 #define V_CL8_RD_DATA_TO_EN(x) ((x) << S_CL8_RD_DATA_TO_EN)
21924 #define F_CL8_RD_DATA_TO_EN    V_CL8_RD_DATA_TO_EN(1U)
21925 
21926 #define S_CL7_RD_DATA_TO_EN    7
21927 #define V_CL7_RD_DATA_TO_EN(x) ((x) << S_CL7_RD_DATA_TO_EN)
21928 #define F_CL7_RD_DATA_TO_EN    V_CL7_RD_DATA_TO_EN(1U)
21929 
21930 #define S_CL6_RD_DATA_TO_EN    6
21931 #define V_CL6_RD_DATA_TO_EN(x) ((x) << S_CL6_RD_DATA_TO_EN)
21932 #define F_CL6_RD_DATA_TO_EN    V_CL6_RD_DATA_TO_EN(1U)
21933 
21934 #define S_CL5_RD_DATA_TO_EN    5
21935 #define V_CL5_RD_DATA_TO_EN(x) ((x) << S_CL5_RD_DATA_TO_EN)
21936 #define F_CL5_RD_DATA_TO_EN    V_CL5_RD_DATA_TO_EN(1U)
21937 
21938 #define S_CL4_RD_DATA_TO_EN    4
21939 #define V_CL4_RD_DATA_TO_EN(x) ((x) << S_CL4_RD_DATA_TO_EN)
21940 #define F_CL4_RD_DATA_TO_EN    V_CL4_RD_DATA_TO_EN(1U)
21941 
21942 #define S_CL3_RD_DATA_TO_EN    3
21943 #define V_CL3_RD_DATA_TO_EN(x) ((x) << S_CL3_RD_DATA_TO_EN)
21944 #define F_CL3_RD_DATA_TO_EN    V_CL3_RD_DATA_TO_EN(1U)
21945 
21946 #define S_CL2_RD_DATA_TO_EN    2
21947 #define V_CL2_RD_DATA_TO_EN(x) ((x) << S_CL2_RD_DATA_TO_EN)
21948 #define F_CL2_RD_DATA_TO_EN    V_CL2_RD_DATA_TO_EN(1U)
21949 
21950 #define S_CL1_RD_DATA_TO_EN    1
21951 #define V_CL1_RD_DATA_TO_EN(x) ((x) << S_CL1_RD_DATA_TO_EN)
21952 #define F_CL1_RD_DATA_TO_EN    V_CL1_RD_DATA_TO_EN(1U)
21953 
21954 #define S_CL0_RD_DATA_TO_EN    0
21955 #define V_CL0_RD_DATA_TO_EN(x) ((x) << S_CL0_RD_DATA_TO_EN)
21956 #define F_CL0_RD_DATA_TO_EN    V_CL0_RD_DATA_TO_EN(1U)
21957 
21958 #define S_FUTURE_CEXPANSION_RTE    29
21959 #define M_FUTURE_CEXPANSION_RTE    0x7U
21960 #define V_FUTURE_CEXPANSION_RTE(x) ((x) << S_FUTURE_CEXPANSION_RTE)
21961 #define G_FUTURE_CEXPANSION_RTE(x) (((x) >> S_FUTURE_CEXPANSION_RTE) & M_FUTURE_CEXPANSION_RTE)
21962 
21963 #define S_FUTURE_DEXPANSION_RTE    13
21964 #define M_FUTURE_DEXPANSION_RTE    0x7U
21965 #define V_FUTURE_DEXPANSION_RTE(x) ((x) << S_FUTURE_DEXPANSION_RTE)
21966 #define G_FUTURE_DEXPANSION_RTE(x) (((x) >> S_FUTURE_DEXPANSION_RTE) & M_FUTURE_DEXPANSION_RTE)
21967 
21968 #define S_T7_FUTURE_CEXPANSION_RTE    31
21969 #define V_T7_FUTURE_CEXPANSION_RTE(x) ((x) << S_T7_FUTURE_CEXPANSION_RTE)
21970 #define F_T7_FUTURE_CEXPANSION_RTE    V_T7_FUTURE_CEXPANSION_RTE(1U)
21971 
21972 #define S_CL14_RD_CMD_TO_EN    30
21973 #define V_CL14_RD_CMD_TO_EN(x) ((x) << S_CL14_RD_CMD_TO_EN)
21974 #define F_CL14_RD_CMD_TO_EN    V_CL14_RD_CMD_TO_EN(1U)
21975 
21976 #define S_CL13_RD_CMD_TO_EN    29
21977 #define V_CL13_RD_CMD_TO_EN(x) ((x) << S_CL13_RD_CMD_TO_EN)
21978 #define F_CL13_RD_CMD_TO_EN    V_CL13_RD_CMD_TO_EN(1U)
21979 
21980 #define S_T7_FUTURE_DEXPANSION_RTE    15
21981 #define V_T7_FUTURE_DEXPANSION_RTE(x) ((x) << S_T7_FUTURE_DEXPANSION_RTE)
21982 #define F_T7_FUTURE_DEXPANSION_RTE    V_T7_FUTURE_DEXPANSION_RTE(1U)
21983 
21984 #define S_CL14_RD_DATA_TO_EN    14
21985 #define V_CL14_RD_DATA_TO_EN(x) ((x) << S_CL14_RD_DATA_TO_EN)
21986 #define F_CL14_RD_DATA_TO_EN    V_CL14_RD_DATA_TO_EN(1U)
21987 
21988 #define S_CL13_RD_DATA_TO_EN    13
21989 #define V_CL13_RD_DATA_TO_EN(x) ((x) << S_CL13_RD_DATA_TO_EN)
21990 #define F_CL13_RD_DATA_TO_EN    V_CL13_RD_DATA_TO_EN(1U)
21991 
21992 #define A_MA_READ_TIMEOUT_ERROR_STATUS 0x78e0
21993 
21994 #define S_CL12_RD_CMD_TO_ERROR    28
21995 #define V_CL12_RD_CMD_TO_ERROR(x) ((x) << S_CL12_RD_CMD_TO_ERROR)
21996 #define F_CL12_RD_CMD_TO_ERROR    V_CL12_RD_CMD_TO_ERROR(1U)
21997 
21998 #define S_CL11_RD_CMD_TO_ERROR    27
21999 #define V_CL11_RD_CMD_TO_ERROR(x) ((x) << S_CL11_RD_CMD_TO_ERROR)
22000 #define F_CL11_RD_CMD_TO_ERROR    V_CL11_RD_CMD_TO_ERROR(1U)
22001 
22002 #define S_CL10_RD_CMD_TO_ERROR    26
22003 #define V_CL10_RD_CMD_TO_ERROR(x) ((x) << S_CL10_RD_CMD_TO_ERROR)
22004 #define F_CL10_RD_CMD_TO_ERROR    V_CL10_RD_CMD_TO_ERROR(1U)
22005 
22006 #define S_CL9_RD_CMD_TO_ERROR    25
22007 #define V_CL9_RD_CMD_TO_ERROR(x) ((x) << S_CL9_RD_CMD_TO_ERROR)
22008 #define F_CL9_RD_CMD_TO_ERROR    V_CL9_RD_CMD_TO_ERROR(1U)
22009 
22010 #define S_CL8_RD_CMD_TO_ERROR    24
22011 #define V_CL8_RD_CMD_TO_ERROR(x) ((x) << S_CL8_RD_CMD_TO_ERROR)
22012 #define F_CL8_RD_CMD_TO_ERROR    V_CL8_RD_CMD_TO_ERROR(1U)
22013 
22014 #define S_CL7_RD_CMD_TO_ERROR    23
22015 #define V_CL7_RD_CMD_TO_ERROR(x) ((x) << S_CL7_RD_CMD_TO_ERROR)
22016 #define F_CL7_RD_CMD_TO_ERROR    V_CL7_RD_CMD_TO_ERROR(1U)
22017 
22018 #define S_CL6_RD_CMD_TO_ERROR    22
22019 #define V_CL6_RD_CMD_TO_ERROR(x) ((x) << S_CL6_RD_CMD_TO_ERROR)
22020 #define F_CL6_RD_CMD_TO_ERROR    V_CL6_RD_CMD_TO_ERROR(1U)
22021 
22022 #define S_CL5_RD_CMD_TO_ERROR    21
22023 #define V_CL5_RD_CMD_TO_ERROR(x) ((x) << S_CL5_RD_CMD_TO_ERROR)
22024 #define F_CL5_RD_CMD_TO_ERROR    V_CL5_RD_CMD_TO_ERROR(1U)
22025 
22026 #define S_CL4_RD_CMD_TO_ERROR    20
22027 #define V_CL4_RD_CMD_TO_ERROR(x) ((x) << S_CL4_RD_CMD_TO_ERROR)
22028 #define F_CL4_RD_CMD_TO_ERROR    V_CL4_RD_CMD_TO_ERROR(1U)
22029 
22030 #define S_CL3_RD_CMD_TO_ERROR    19
22031 #define V_CL3_RD_CMD_TO_ERROR(x) ((x) << S_CL3_RD_CMD_TO_ERROR)
22032 #define F_CL3_RD_CMD_TO_ERROR    V_CL3_RD_CMD_TO_ERROR(1U)
22033 
22034 #define S_CL2_RD_CMD_TO_ERROR    18
22035 #define V_CL2_RD_CMD_TO_ERROR(x) ((x) << S_CL2_RD_CMD_TO_ERROR)
22036 #define F_CL2_RD_CMD_TO_ERROR    V_CL2_RD_CMD_TO_ERROR(1U)
22037 
22038 #define S_CL1_RD_CMD_TO_ERROR    17
22039 #define V_CL1_RD_CMD_TO_ERROR(x) ((x) << S_CL1_RD_CMD_TO_ERROR)
22040 #define F_CL1_RD_CMD_TO_ERROR    V_CL1_RD_CMD_TO_ERROR(1U)
22041 
22042 #define S_CL0_RD_CMD_TO_ERROR    16
22043 #define V_CL0_RD_CMD_TO_ERROR(x) ((x) << S_CL0_RD_CMD_TO_ERROR)
22044 #define F_CL0_RD_CMD_TO_ERROR    V_CL0_RD_CMD_TO_ERROR(1U)
22045 
22046 #define S_CL12_RD_DATA_TO_ERROR    12
22047 #define V_CL12_RD_DATA_TO_ERROR(x) ((x) << S_CL12_RD_DATA_TO_ERROR)
22048 #define F_CL12_RD_DATA_TO_ERROR    V_CL12_RD_DATA_TO_ERROR(1U)
22049 
22050 #define S_CL11_RD_DATA_TO_ERROR    11
22051 #define V_CL11_RD_DATA_TO_ERROR(x) ((x) << S_CL11_RD_DATA_TO_ERROR)
22052 #define F_CL11_RD_DATA_TO_ERROR    V_CL11_RD_DATA_TO_ERROR(1U)
22053 
22054 #define S_CL10_RD_DATA_TO_ERROR    10
22055 #define V_CL10_RD_DATA_TO_ERROR(x) ((x) << S_CL10_RD_DATA_TO_ERROR)
22056 #define F_CL10_RD_DATA_TO_ERROR    V_CL10_RD_DATA_TO_ERROR(1U)
22057 
22058 #define S_CL9_RD_DATA_TO_ERROR    9
22059 #define V_CL9_RD_DATA_TO_ERROR(x) ((x) << S_CL9_RD_DATA_TO_ERROR)
22060 #define F_CL9_RD_DATA_TO_ERROR    V_CL9_RD_DATA_TO_ERROR(1U)
22061 
22062 #define S_CL8_RD_DATA_TO_ERROR    8
22063 #define V_CL8_RD_DATA_TO_ERROR(x) ((x) << S_CL8_RD_DATA_TO_ERROR)
22064 #define F_CL8_RD_DATA_TO_ERROR    V_CL8_RD_DATA_TO_ERROR(1U)
22065 
22066 #define S_CL7_RD_DATA_TO_ERROR    7
22067 #define V_CL7_RD_DATA_TO_ERROR(x) ((x) << S_CL7_RD_DATA_TO_ERROR)
22068 #define F_CL7_RD_DATA_TO_ERROR    V_CL7_RD_DATA_TO_ERROR(1U)
22069 
22070 #define S_CL6_RD_DATA_TO_ERROR    6
22071 #define V_CL6_RD_DATA_TO_ERROR(x) ((x) << S_CL6_RD_DATA_TO_ERROR)
22072 #define F_CL6_RD_DATA_TO_ERROR    V_CL6_RD_DATA_TO_ERROR(1U)
22073 
22074 #define S_CL5_RD_DATA_TO_ERROR    5
22075 #define V_CL5_RD_DATA_TO_ERROR(x) ((x) << S_CL5_RD_DATA_TO_ERROR)
22076 #define F_CL5_RD_DATA_TO_ERROR    V_CL5_RD_DATA_TO_ERROR(1U)
22077 
22078 #define S_CL4_RD_DATA_TO_ERROR    4
22079 #define V_CL4_RD_DATA_TO_ERROR(x) ((x) << S_CL4_RD_DATA_TO_ERROR)
22080 #define F_CL4_RD_DATA_TO_ERROR    V_CL4_RD_DATA_TO_ERROR(1U)
22081 
22082 #define S_CL3_RD_DATA_TO_ERROR    3
22083 #define V_CL3_RD_DATA_TO_ERROR(x) ((x) << S_CL3_RD_DATA_TO_ERROR)
22084 #define F_CL3_RD_DATA_TO_ERROR    V_CL3_RD_DATA_TO_ERROR(1U)
22085 
22086 #define S_CL2_RD_DATA_TO_ERROR    2
22087 #define V_CL2_RD_DATA_TO_ERROR(x) ((x) << S_CL2_RD_DATA_TO_ERROR)
22088 #define F_CL2_RD_DATA_TO_ERROR    V_CL2_RD_DATA_TO_ERROR(1U)
22089 
22090 #define S_CL1_RD_DATA_TO_ERROR    1
22091 #define V_CL1_RD_DATA_TO_ERROR(x) ((x) << S_CL1_RD_DATA_TO_ERROR)
22092 #define F_CL1_RD_DATA_TO_ERROR    V_CL1_RD_DATA_TO_ERROR(1U)
22093 
22094 #define S_CL0_RD_DATA_TO_ERROR    0
22095 #define V_CL0_RD_DATA_TO_ERROR(x) ((x) << S_CL0_RD_DATA_TO_ERROR)
22096 #define F_CL0_RD_DATA_TO_ERROR    V_CL0_RD_DATA_TO_ERROR(1U)
22097 
22098 #define S_FUTURE_CEXPANSION_RTS    29
22099 #define M_FUTURE_CEXPANSION_RTS    0x7U
22100 #define V_FUTURE_CEXPANSION_RTS(x) ((x) << S_FUTURE_CEXPANSION_RTS)
22101 #define G_FUTURE_CEXPANSION_RTS(x) (((x) >> S_FUTURE_CEXPANSION_RTS) & M_FUTURE_CEXPANSION_RTS)
22102 
22103 #define S_FUTURE_DEXPANSION_RTS    13
22104 #define M_FUTURE_DEXPANSION_RTS    0x7U
22105 #define V_FUTURE_DEXPANSION_RTS(x) ((x) << S_FUTURE_DEXPANSION_RTS)
22106 #define G_FUTURE_DEXPANSION_RTS(x) (((x) >> S_FUTURE_DEXPANSION_RTS) & M_FUTURE_DEXPANSION_RTS)
22107 
22108 #define S_T7_FUTURE_CEXPANSION_RTS    31
22109 #define V_T7_FUTURE_CEXPANSION_RTS(x) ((x) << S_T7_FUTURE_CEXPANSION_RTS)
22110 #define F_T7_FUTURE_CEXPANSION_RTS    V_T7_FUTURE_CEXPANSION_RTS(1U)
22111 
22112 #define S_CL14_RD_CMD_TO_ERROR    30
22113 #define V_CL14_RD_CMD_TO_ERROR(x) ((x) << S_CL14_RD_CMD_TO_ERROR)
22114 #define F_CL14_RD_CMD_TO_ERROR    V_CL14_RD_CMD_TO_ERROR(1U)
22115 
22116 #define S_CL13_RD_CMD_TO_ERROR    29
22117 #define V_CL13_RD_CMD_TO_ERROR(x) ((x) << S_CL13_RD_CMD_TO_ERROR)
22118 #define F_CL13_RD_CMD_TO_ERROR    V_CL13_RD_CMD_TO_ERROR(1U)
22119 
22120 #define S_T7_FUTURE_DEXPANSION_RTS    14
22121 #define M_T7_FUTURE_DEXPANSION_RTS    0x3U
22122 #define V_T7_FUTURE_DEXPANSION_RTS(x) ((x) << S_T7_FUTURE_DEXPANSION_RTS)
22123 #define G_T7_FUTURE_DEXPANSION_RTS(x) (((x) >> S_T7_FUTURE_DEXPANSION_RTS) & M_T7_FUTURE_DEXPANSION_RTS)
22124 
22125 #define S_CL13_RD_DATA_TO_ERROR    13
22126 #define V_CL13_RD_DATA_TO_ERROR(x) ((x) << S_CL13_RD_DATA_TO_ERROR)
22127 #define F_CL13_RD_DATA_TO_ERROR    V_CL13_RD_DATA_TO_ERROR(1U)
22128 
22129 #define A_MA_BKP_CNT_SEL 0x78e4
22130 
22131 #define S_BKP_CNT_TYPE    30
22132 #define M_BKP_CNT_TYPE    0x3U
22133 #define V_BKP_CNT_TYPE(x) ((x) << S_BKP_CNT_TYPE)
22134 #define G_BKP_CNT_TYPE(x) (((x) >> S_BKP_CNT_TYPE) & M_BKP_CNT_TYPE)
22135 
22136 #define S_BKP_CLIENT    24
22137 #define M_BKP_CLIENT    0xfU
22138 #define V_BKP_CLIENT(x) ((x) << S_BKP_CLIENT)
22139 #define G_BKP_CLIENT(x) (((x) >> S_BKP_CLIENT) & M_BKP_CLIENT)
22140 
22141 #define A_MA_BKP_CNT 0x78e8
22142 #define A_MA_WRT_ARB 0x78ec
22143 
22144 #define S_WRT_EN    31
22145 #define V_WRT_EN(x) ((x) << S_WRT_EN)
22146 #define F_WRT_EN    V_WRT_EN(1U)
22147 
22148 #define S_WR_TIM    16
22149 #define M_WR_TIM    0xffU
22150 #define V_WR_TIM(x) ((x) << S_WR_TIM)
22151 #define G_WR_TIM(x) (((x) >> S_WR_TIM) & M_WR_TIM)
22152 
22153 #define S_RD_WIN    8
22154 #define M_RD_WIN    0xffU
22155 #define V_RD_WIN(x) ((x) << S_RD_WIN)
22156 #define G_RD_WIN(x) (((x) >> S_RD_WIN) & M_RD_WIN)
22157 
22158 #define S_WR_WIN    0
22159 #define M_WR_WIN    0xffU
22160 #define V_WR_WIN(x) ((x) << S_WR_WIN)
22161 #define G_WR_WIN(x) (((x) >> S_WR_WIN) & M_WR_WIN)
22162 
22163 #define A_MA_IF_PARITY_ERROR_ENABLE 0x78f0
22164 
22165 #define S_T5_FUTURE_DEXPANSION    13
22166 #define M_T5_FUTURE_DEXPANSION    0x7ffffU
22167 #define V_T5_FUTURE_DEXPANSION(x) ((x) << S_T5_FUTURE_DEXPANSION)
22168 #define G_T5_FUTURE_DEXPANSION(x) (((x) >> S_T5_FUTURE_DEXPANSION) & M_T5_FUTURE_DEXPANSION)
22169 
22170 #define S_CL12_IF_PAR_EN    12
22171 #define V_CL12_IF_PAR_EN(x) ((x) << S_CL12_IF_PAR_EN)
22172 #define F_CL12_IF_PAR_EN    V_CL12_IF_PAR_EN(1U)
22173 
22174 #define S_CL11_IF_PAR_EN    11
22175 #define V_CL11_IF_PAR_EN(x) ((x) << S_CL11_IF_PAR_EN)
22176 #define F_CL11_IF_PAR_EN    V_CL11_IF_PAR_EN(1U)
22177 
22178 #define S_CL10_IF_PAR_EN    10
22179 #define V_CL10_IF_PAR_EN(x) ((x) << S_CL10_IF_PAR_EN)
22180 #define F_CL10_IF_PAR_EN    V_CL10_IF_PAR_EN(1U)
22181 
22182 #define S_CL9_IF_PAR_EN    9
22183 #define V_CL9_IF_PAR_EN(x) ((x) << S_CL9_IF_PAR_EN)
22184 #define F_CL9_IF_PAR_EN    V_CL9_IF_PAR_EN(1U)
22185 
22186 #define S_CL8_IF_PAR_EN    8
22187 #define V_CL8_IF_PAR_EN(x) ((x) << S_CL8_IF_PAR_EN)
22188 #define F_CL8_IF_PAR_EN    V_CL8_IF_PAR_EN(1U)
22189 
22190 #define S_CL7_IF_PAR_EN    7
22191 #define V_CL7_IF_PAR_EN(x) ((x) << S_CL7_IF_PAR_EN)
22192 #define F_CL7_IF_PAR_EN    V_CL7_IF_PAR_EN(1U)
22193 
22194 #define S_CL6_IF_PAR_EN    6
22195 #define V_CL6_IF_PAR_EN(x) ((x) << S_CL6_IF_PAR_EN)
22196 #define F_CL6_IF_PAR_EN    V_CL6_IF_PAR_EN(1U)
22197 
22198 #define S_CL5_IF_PAR_EN    5
22199 #define V_CL5_IF_PAR_EN(x) ((x) << S_CL5_IF_PAR_EN)
22200 #define F_CL5_IF_PAR_EN    V_CL5_IF_PAR_EN(1U)
22201 
22202 #define S_CL4_IF_PAR_EN    4
22203 #define V_CL4_IF_PAR_EN(x) ((x) << S_CL4_IF_PAR_EN)
22204 #define F_CL4_IF_PAR_EN    V_CL4_IF_PAR_EN(1U)
22205 
22206 #define S_CL3_IF_PAR_EN    3
22207 #define V_CL3_IF_PAR_EN(x) ((x) << S_CL3_IF_PAR_EN)
22208 #define F_CL3_IF_PAR_EN    V_CL3_IF_PAR_EN(1U)
22209 
22210 #define S_CL2_IF_PAR_EN    2
22211 #define V_CL2_IF_PAR_EN(x) ((x) << S_CL2_IF_PAR_EN)
22212 #define F_CL2_IF_PAR_EN    V_CL2_IF_PAR_EN(1U)
22213 
22214 #define S_CL1_IF_PAR_EN    1
22215 #define V_CL1_IF_PAR_EN(x) ((x) << S_CL1_IF_PAR_EN)
22216 #define F_CL1_IF_PAR_EN    V_CL1_IF_PAR_EN(1U)
22217 
22218 #define S_CL0_IF_PAR_EN    0
22219 #define V_CL0_IF_PAR_EN(x) ((x) << S_CL0_IF_PAR_EN)
22220 #define F_CL0_IF_PAR_EN    V_CL0_IF_PAR_EN(1U)
22221 
22222 #define S_FUTURE_DEXPANSION_IPE    13
22223 #define M_FUTURE_DEXPANSION_IPE    0x7ffffU
22224 #define V_FUTURE_DEXPANSION_IPE(x) ((x) << S_FUTURE_DEXPANSION_IPE)
22225 #define G_FUTURE_DEXPANSION_IPE(x) (((x) >> S_FUTURE_DEXPANSION_IPE) & M_FUTURE_DEXPANSION_IPE)
22226 
22227 #define S_T7_FUTURE_DEXPANSION_IPE    14
22228 #define M_T7_FUTURE_DEXPANSION_IPE    0x3ffffU
22229 #define V_T7_FUTURE_DEXPANSION_IPE(x) ((x) << S_T7_FUTURE_DEXPANSION_IPE)
22230 #define G_T7_FUTURE_DEXPANSION_IPE(x) (((x) >> S_T7_FUTURE_DEXPANSION_IPE) & M_T7_FUTURE_DEXPANSION_IPE)
22231 
22232 #define S_CL13_IF_PAR_EN    13
22233 #define V_CL13_IF_PAR_EN(x) ((x) << S_CL13_IF_PAR_EN)
22234 #define F_CL13_IF_PAR_EN    V_CL13_IF_PAR_EN(1U)
22235 
22236 #define A_MA_IF_PARITY_ERROR_STATUS 0x78f4
22237 
22238 #define S_CL12_IF_PAR_ERROR    12
22239 #define V_CL12_IF_PAR_ERROR(x) ((x) << S_CL12_IF_PAR_ERROR)
22240 #define F_CL12_IF_PAR_ERROR    V_CL12_IF_PAR_ERROR(1U)
22241 
22242 #define S_CL11_IF_PAR_ERROR    11
22243 #define V_CL11_IF_PAR_ERROR(x) ((x) << S_CL11_IF_PAR_ERROR)
22244 #define F_CL11_IF_PAR_ERROR    V_CL11_IF_PAR_ERROR(1U)
22245 
22246 #define S_CL10_IF_PAR_ERROR    10
22247 #define V_CL10_IF_PAR_ERROR(x) ((x) << S_CL10_IF_PAR_ERROR)
22248 #define F_CL10_IF_PAR_ERROR    V_CL10_IF_PAR_ERROR(1U)
22249 
22250 #define S_CL9_IF_PAR_ERROR    9
22251 #define V_CL9_IF_PAR_ERROR(x) ((x) << S_CL9_IF_PAR_ERROR)
22252 #define F_CL9_IF_PAR_ERROR    V_CL9_IF_PAR_ERROR(1U)
22253 
22254 #define S_CL8_IF_PAR_ERROR    8
22255 #define V_CL8_IF_PAR_ERROR(x) ((x) << S_CL8_IF_PAR_ERROR)
22256 #define F_CL8_IF_PAR_ERROR    V_CL8_IF_PAR_ERROR(1U)
22257 
22258 #define S_CL7_IF_PAR_ERROR    7
22259 #define V_CL7_IF_PAR_ERROR(x) ((x) << S_CL7_IF_PAR_ERROR)
22260 #define F_CL7_IF_PAR_ERROR    V_CL7_IF_PAR_ERROR(1U)
22261 
22262 #define S_CL6_IF_PAR_ERROR    6
22263 #define V_CL6_IF_PAR_ERROR(x) ((x) << S_CL6_IF_PAR_ERROR)
22264 #define F_CL6_IF_PAR_ERROR    V_CL6_IF_PAR_ERROR(1U)
22265 
22266 #define S_CL5_IF_PAR_ERROR    5
22267 #define V_CL5_IF_PAR_ERROR(x) ((x) << S_CL5_IF_PAR_ERROR)
22268 #define F_CL5_IF_PAR_ERROR    V_CL5_IF_PAR_ERROR(1U)
22269 
22270 #define S_CL4_IF_PAR_ERROR    4
22271 #define V_CL4_IF_PAR_ERROR(x) ((x) << S_CL4_IF_PAR_ERROR)
22272 #define F_CL4_IF_PAR_ERROR    V_CL4_IF_PAR_ERROR(1U)
22273 
22274 #define S_CL3_IF_PAR_ERROR    3
22275 #define V_CL3_IF_PAR_ERROR(x) ((x) << S_CL3_IF_PAR_ERROR)
22276 #define F_CL3_IF_PAR_ERROR    V_CL3_IF_PAR_ERROR(1U)
22277 
22278 #define S_CL2_IF_PAR_ERROR    2
22279 #define V_CL2_IF_PAR_ERROR(x) ((x) << S_CL2_IF_PAR_ERROR)
22280 #define F_CL2_IF_PAR_ERROR    V_CL2_IF_PAR_ERROR(1U)
22281 
22282 #define S_CL1_IF_PAR_ERROR    1
22283 #define V_CL1_IF_PAR_ERROR(x) ((x) << S_CL1_IF_PAR_ERROR)
22284 #define F_CL1_IF_PAR_ERROR    V_CL1_IF_PAR_ERROR(1U)
22285 
22286 #define S_CL0_IF_PAR_ERROR    0
22287 #define V_CL0_IF_PAR_ERROR(x) ((x) << S_CL0_IF_PAR_ERROR)
22288 #define F_CL0_IF_PAR_ERROR    V_CL0_IF_PAR_ERROR(1U)
22289 
22290 #define S_FUTURE_DEXPANSION_IPS    13
22291 #define M_FUTURE_DEXPANSION_IPS    0x7ffffU
22292 #define V_FUTURE_DEXPANSION_IPS(x) ((x) << S_FUTURE_DEXPANSION_IPS)
22293 #define G_FUTURE_DEXPANSION_IPS(x) (((x) >> S_FUTURE_DEXPANSION_IPS) & M_FUTURE_DEXPANSION_IPS)
22294 
22295 #define S_T7_FUTURE_DEXPANSION_IPS    14
22296 #define M_T7_FUTURE_DEXPANSION_IPS    0x3ffffU
22297 #define V_T7_FUTURE_DEXPANSION_IPS(x) ((x) << S_T7_FUTURE_DEXPANSION_IPS)
22298 #define G_T7_FUTURE_DEXPANSION_IPS(x) (((x) >> S_T7_FUTURE_DEXPANSION_IPS) & M_T7_FUTURE_DEXPANSION_IPS)
22299 
22300 #define S_CL13_IF_PAR_ERROR    13
22301 #define V_CL13_IF_PAR_ERROR(x) ((x) << S_CL13_IF_PAR_ERROR)
22302 #define F_CL13_IF_PAR_ERROR    V_CL13_IF_PAR_ERROR(1U)
22303 
22304 #define A_MA_LOCAL_DEBUG_CFG 0x78f8
22305 
22306 #define S_DEBUG_OR    15
22307 #define V_DEBUG_OR(x) ((x) << S_DEBUG_OR)
22308 #define F_DEBUG_OR    V_DEBUG_OR(1U)
22309 
22310 #define S_DEBUG_HI    14
22311 #define V_DEBUG_HI(x) ((x) << S_DEBUG_HI)
22312 #define F_DEBUG_HI    V_DEBUG_HI(1U)
22313 
22314 #define S_DEBUG_RPT    13
22315 #define V_DEBUG_RPT(x) ((x) << S_DEBUG_RPT)
22316 #define F_DEBUG_RPT    V_DEBUG_RPT(1U)
22317 
22318 #define S_DEBUGPAGE    10
22319 #define M_DEBUGPAGE    0x7U
22320 #define V_DEBUGPAGE(x) ((x) << S_DEBUGPAGE)
22321 #define G_DEBUGPAGE(x) (((x) >> S_DEBUGPAGE) & M_DEBUGPAGE)
22322 
22323 #define A_MA_LOCAL_DEBUG_RPT 0x78fc
22324 #define A_MA_CLIENT13_PR_THRESHOLD 0x7900
22325 #define A_MA_CLIENT13_CR_THRESHOLD 0x7904
22326 #define A_MA_CRYPTO_DEBUG_CNT 0x7908
22327 #define A_MA_CRYPTO_WRDATA_CNT 0x790c
22328 #define A_MA_CRYPTO_RDDATA_CNT 0x7910
22329 #define A_MA_LOCAL_DEBUG_PERF_CFG 0x7914
22330 #define A_MA_LOCAL_DEBUG_PERF_RPT 0x7918
22331 #define A_MA_PCIE_THROTTLE 0x791c
22332 #define A_MA_CLIENT14_PR_THRESHOLD 0x7920
22333 #define A_MA_CLIENT14_CR_THRESHOLD 0x7924
22334 #define A_MA_CIM_TH1_DEBUG_CNT 0x7928
22335 #define A_MA_CIM_TH1_WRDATA_CNT 0x792c
22336 #define A_MA_CIM_TH1_RDDATA_CNT 0x7930
22337 #define A_MA_CIM_THREAD1_MAPPER 0x7934
22338 
22339 #define S_CIM_THREAD1_EN    0
22340 #define M_CIM_THREAD1_EN    0xffU
22341 #define V_CIM_THREAD1_EN(x) ((x) << S_CIM_THREAD1_EN)
22342 #define G_CIM_THREAD1_EN(x) (((x) >> S_CIM_THREAD1_EN) & M_CIM_THREAD1_EN)
22343 
22344 #define A_MA_PIO_CI_SGE_TH0_BASE 0x7938
22345 
22346 #define S_SGE_TH0_BASE    0
22347 #define M_SGE_TH0_BASE    0xffffU
22348 #define V_SGE_TH0_BASE(x) ((x) << S_SGE_TH0_BASE)
22349 #define G_SGE_TH0_BASE(x) (((x) >> S_SGE_TH0_BASE) & M_SGE_TH0_BASE)
22350 
22351 #define A_MA_PIO_CI_SGE_TH1_BASE 0x793c
22352 
22353 #define S_SGE_TH1_BASE    0
22354 #define M_SGE_TH1_BASE    0xffffU
22355 #define V_SGE_TH1_BASE(x) ((x) << S_SGE_TH1_BASE)
22356 #define G_SGE_TH1_BASE(x) (((x) >> S_SGE_TH1_BASE) & M_SGE_TH1_BASE)
22357 
22358 #define A_MA_PIO_CI_ULPTX_BASE 0x7940
22359 
22360 #define S_ULPTX_BASE    0
22361 #define M_ULPTX_BASE    0xffffU
22362 #define V_ULPTX_BASE(x) ((x) << S_ULPTX_BASE)
22363 #define G_ULPTX_BASE(x) (((x) >> S_ULPTX_BASE) & M_ULPTX_BASE)
22364 
22365 #define A_MA_PIO_CI_ULPRX_BASE 0x7944
22366 
22367 #define S_ULPRX_BASE    0
22368 #define M_ULPRX_BASE    0xffffU
22369 #define V_ULPRX_BASE(x) ((x) << S_ULPRX_BASE)
22370 #define G_ULPRX_BASE(x) (((x) >> S_ULPRX_BASE) & M_ULPRX_BASE)
22371 
22372 #define A_MA_PIO_CI_ULPTXRX_BASE 0x7948
22373 
22374 #define S_ULPTXRX_BASE    0
22375 #define M_ULPTXRX_BASE    0xffffU
22376 #define V_ULPTXRX_BASE(x) ((x) << S_ULPTXRX_BASE)
22377 #define G_ULPTXRX_BASE(x) (((x) >> S_ULPTXRX_BASE) & M_ULPTXRX_BASE)
22378 
22379 #define A_MA_PIO_CI_TP_TH0_BASE 0x794c
22380 
22381 #define S_TP_TH0_BASE    0
22382 #define M_TP_TH0_BASE    0xffffU
22383 #define V_TP_TH0_BASE(x) ((x) << S_TP_TH0_BASE)
22384 #define G_TP_TH0_BASE(x) (((x) >> S_TP_TH0_BASE) & M_TP_TH0_BASE)
22385 
22386 #define A_MA_PIO_CI_TP_TH1_BASE 0x7950
22387 
22388 #define S_TP_TH1_BASE    0
22389 #define M_TP_TH1_BASE    0xffffU
22390 #define V_TP_TH1_BASE(x) ((x) << S_TP_TH1_BASE)
22391 #define G_TP_TH1_BASE(x) (((x) >> S_TP_TH1_BASE) & M_TP_TH1_BASE)
22392 
22393 #define A_MA_PIO_CI_LE_BASE 0x7954
22394 
22395 #define S_LE_BASE    0
22396 #define M_LE_BASE    0xffffU
22397 #define V_LE_BASE(x) ((x) << S_LE_BASE)
22398 #define G_LE_BASE(x) (((x) >> S_LE_BASE) & M_LE_BASE)
22399 
22400 #define A_MA_PIO_CI_CIM_TH0_BASE 0x7958
22401 
22402 #define S_CIM_TH0_BASE    0
22403 #define M_CIM_TH0_BASE    0xffffU
22404 #define V_CIM_TH0_BASE(x) ((x) << S_CIM_TH0_BASE)
22405 #define G_CIM_TH0_BASE(x) (((x) >> S_CIM_TH0_BASE) & M_CIM_TH0_BASE)
22406 
22407 #define A_MA_PIO_CI_PCIE_BASE 0x795c
22408 
22409 #define S_PCIE_BASE    0
22410 #define M_PCIE_BASE    0xffffU
22411 #define V_PCIE_BASE(x) ((x) << S_PCIE_BASE)
22412 #define G_PCIE_BASE(x) (((x) >> S_PCIE_BASE) & M_PCIE_BASE)
22413 
22414 #define A_MA_PIO_CI_PMTX_BASE 0x7960
22415 
22416 #define S_PMTX_BASE    0
22417 #define M_PMTX_BASE    0xffffU
22418 #define V_PMTX_BASE(x) ((x) << S_PMTX_BASE)
22419 #define G_PMTX_BASE(x) (((x) >> S_PMTX_BASE) & M_PMTX_BASE)
22420 
22421 #define A_MA_PIO_CI_PMRX_BASE 0x7964
22422 
22423 #define S_PMRX_BASE    0
22424 #define M_PMRX_BASE    0xffffU
22425 #define V_PMRX_BASE(x) ((x) << S_PMRX_BASE)
22426 #define G_PMRX_BASE(x) (((x) >> S_PMRX_BASE) & M_PMRX_BASE)
22427 
22428 #define A_MA_PIO_CI_HMA_BASE 0x7968
22429 
22430 #define S_HMACLIENTBASE    0
22431 #define M_HMACLIENTBASE    0xffffU
22432 #define V_HMACLIENTBASE(x) ((x) << S_HMACLIENTBASE)
22433 #define G_HMACLIENTBASE(x) (((x) >> S_HMACLIENTBASE) & M_HMACLIENTBASE)
22434 
22435 #define A_MA_PIO_CI_CRYPTO_BASE 0x796c
22436 
22437 #define S_CRYPTO_BASE    0
22438 #define M_CRYPTO_BASE    0xffffU
22439 #define V_CRYPTO_BASE(x) ((x) << S_CRYPTO_BASE)
22440 #define G_CRYPTO_BASE(x) (((x) >> S_CRYPTO_BASE) & M_CRYPTO_BASE)
22441 
22442 #define A_MA_PIO_CI_CIM_TH1_BASE 0x7970
22443 
22444 #define S_CIM_TH1_BASE    0
22445 #define M_CIM_TH1_BASE    0xffffU
22446 #define V_CIM_TH1_BASE(x) ((x) << S_CIM_TH1_BASE)
22447 #define G_CIM_TH1_BASE(x) (((x) >> S_CIM_TH1_BASE) & M_CIM_TH1_BASE)
22448 
22449 #define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_EXTERNAL 0xa000
22450 
22451 #define S_CMDVLD0    31
22452 #define V_CMDVLD0(x) ((x) << S_CMDVLD0)
22453 #define F_CMDVLD0    V_CMDVLD0(1U)
22454 
22455 #define S_CMDRDY0    30
22456 #define V_CMDRDY0(x) ((x) << S_CMDRDY0)
22457 #define F_CMDRDY0    V_CMDRDY0(1U)
22458 
22459 #define S_CMDTYPE0    29
22460 #define V_CMDTYPE0(x) ((x) << S_CMDTYPE0)
22461 #define F_CMDTYPE0    V_CMDTYPE0(1U)
22462 
22463 #define S_CMDLEN0    21
22464 #define M_CMDLEN0    0xffU
22465 #define V_CMDLEN0(x) ((x) << S_CMDLEN0)
22466 #define G_CMDLEN0(x) (((x) >> S_CMDLEN0) & M_CMDLEN0)
22467 
22468 #define S_CMDADDR0    8
22469 #define M_CMDADDR0    0x1fffU
22470 #define V_CMDADDR0(x) ((x) << S_CMDADDR0)
22471 #define G_CMDADDR0(x) (((x) >> S_CMDADDR0) & M_CMDADDR0)
22472 
22473 #define S_WRDATAVLD0    7
22474 #define V_WRDATAVLD0(x) ((x) << S_WRDATAVLD0)
22475 #define F_WRDATAVLD0    V_WRDATAVLD0(1U)
22476 
22477 #define S_WRDATARDY0    6
22478 #define V_WRDATARDY0(x) ((x) << S_WRDATARDY0)
22479 #define F_WRDATARDY0    V_WRDATARDY0(1U)
22480 
22481 #define S_RDDATARDY0    5
22482 #define V_RDDATARDY0(x) ((x) << S_RDDATARDY0)
22483 #define F_RDDATARDY0    V_RDDATARDY0(1U)
22484 
22485 #define S_RDDATAVLD0    4
22486 #define V_RDDATAVLD0(x) ((x) << S_RDDATAVLD0)
22487 #define F_RDDATAVLD0    V_RDDATAVLD0(1U)
22488 
22489 #define S_RDDATA0    0
22490 #define M_RDDATA0    0xfU
22491 #define V_RDDATA0(x) ((x) << S_RDDATA0)
22492 #define G_RDDATA0(x) (((x) >> S_RDDATA0) & M_RDDATA0)
22493 
22494 #define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_EXTERNAL 0xa001
22495 
22496 #define S_CMDVLD1    31
22497 #define V_CMDVLD1(x) ((x) << S_CMDVLD1)
22498 #define F_CMDVLD1    V_CMDVLD1(1U)
22499 
22500 #define S_CMDRDY1    30
22501 #define V_CMDRDY1(x) ((x) << S_CMDRDY1)
22502 #define F_CMDRDY1    V_CMDRDY1(1U)
22503 
22504 #define S_CMDTYPE1    29
22505 #define V_CMDTYPE1(x) ((x) << S_CMDTYPE1)
22506 #define F_CMDTYPE1    V_CMDTYPE1(1U)
22507 
22508 #define S_CMDLEN1    21
22509 #define M_CMDLEN1    0xffU
22510 #define V_CMDLEN1(x) ((x) << S_CMDLEN1)
22511 #define G_CMDLEN1(x) (((x) >> S_CMDLEN1) & M_CMDLEN1)
22512 
22513 #define S_CMDADDR1    8
22514 #define M_CMDADDR1    0x1fffU
22515 #define V_CMDADDR1(x) ((x) << S_CMDADDR1)
22516 #define G_CMDADDR1(x) (((x) >> S_CMDADDR1) & M_CMDADDR1)
22517 
22518 #define S_WRDATAVLD1    7
22519 #define V_WRDATAVLD1(x) ((x) << S_WRDATAVLD1)
22520 #define F_WRDATAVLD1    V_WRDATAVLD1(1U)
22521 
22522 #define S_WRDATARDY1    6
22523 #define V_WRDATARDY1(x) ((x) << S_WRDATARDY1)
22524 #define F_WRDATARDY1    V_WRDATARDY1(1U)
22525 
22526 #define S_RDDATARDY1    5
22527 #define V_RDDATARDY1(x) ((x) << S_RDDATARDY1)
22528 #define F_RDDATARDY1    V_RDDATARDY1(1U)
22529 
22530 #define S_RDDATAVLD1    4
22531 #define V_RDDATAVLD1(x) ((x) << S_RDDATAVLD1)
22532 #define F_RDDATAVLD1    V_RDDATAVLD1(1U)
22533 
22534 #define S_RDDATA1    0
22535 #define M_RDDATA1    0xfU
22536 #define V_RDDATA1(x) ((x) << S_RDDATA1)
22537 #define G_RDDATA1(x) (((x) >> S_RDDATA1) & M_RDDATA1)
22538 
22539 #define A_MA_ULP_TX_CLIENT_INTERFACE_EXTERNAL 0xa002
22540 
22541 #define S_CMDVLD2    31
22542 #define V_CMDVLD2(x) ((x) << S_CMDVLD2)
22543 #define F_CMDVLD2    V_CMDVLD2(1U)
22544 
22545 #define S_CMDRDY2    30
22546 #define V_CMDRDY2(x) ((x) << S_CMDRDY2)
22547 #define F_CMDRDY2    V_CMDRDY2(1U)
22548 
22549 #define S_CMDTYPE2    29
22550 #define V_CMDTYPE2(x) ((x) << S_CMDTYPE2)
22551 #define F_CMDTYPE2    V_CMDTYPE2(1U)
22552 
22553 #define S_CMDLEN2    21
22554 #define M_CMDLEN2    0xffU
22555 #define V_CMDLEN2(x) ((x) << S_CMDLEN2)
22556 #define G_CMDLEN2(x) (((x) >> S_CMDLEN2) & M_CMDLEN2)
22557 
22558 #define S_CMDADDR2    8
22559 #define M_CMDADDR2    0x1fffU
22560 #define V_CMDADDR2(x) ((x) << S_CMDADDR2)
22561 #define G_CMDADDR2(x) (((x) >> S_CMDADDR2) & M_CMDADDR2)
22562 
22563 #define S_WRDATAVLD2    7
22564 #define V_WRDATAVLD2(x) ((x) << S_WRDATAVLD2)
22565 #define F_WRDATAVLD2    V_WRDATAVLD2(1U)
22566 
22567 #define S_WRDATARDY2    6
22568 #define V_WRDATARDY2(x) ((x) << S_WRDATARDY2)
22569 #define F_WRDATARDY2    V_WRDATARDY2(1U)
22570 
22571 #define S_RDDATARDY2    5
22572 #define V_RDDATARDY2(x) ((x) << S_RDDATARDY2)
22573 #define F_RDDATARDY2    V_RDDATARDY2(1U)
22574 
22575 #define S_RDDATAVLD2    4
22576 #define V_RDDATAVLD2(x) ((x) << S_RDDATAVLD2)
22577 #define F_RDDATAVLD2    V_RDDATAVLD2(1U)
22578 
22579 #define S_RDDATA2    0
22580 #define M_RDDATA2    0xfU
22581 #define V_RDDATA2(x) ((x) << S_RDDATA2)
22582 #define G_RDDATA2(x) (((x) >> S_RDDATA2) & M_RDDATA2)
22583 
22584 #define A_MA_ULP_RX_CLIENT_INTERFACE_EXTERNAL 0xa003
22585 
22586 #define S_CMDVLD3    31
22587 #define V_CMDVLD3(x) ((x) << S_CMDVLD3)
22588 #define F_CMDVLD3    V_CMDVLD3(1U)
22589 
22590 #define S_CMDRDY3    30
22591 #define V_CMDRDY3(x) ((x) << S_CMDRDY3)
22592 #define F_CMDRDY3    V_CMDRDY3(1U)
22593 
22594 #define S_CMDTYPE3    29
22595 #define V_CMDTYPE3(x) ((x) << S_CMDTYPE3)
22596 #define F_CMDTYPE3    V_CMDTYPE3(1U)
22597 
22598 #define S_CMDLEN3    21
22599 #define M_CMDLEN3    0xffU
22600 #define V_CMDLEN3(x) ((x) << S_CMDLEN3)
22601 #define G_CMDLEN3(x) (((x) >> S_CMDLEN3) & M_CMDLEN3)
22602 
22603 #define S_CMDADDR3    8
22604 #define M_CMDADDR3    0x1fffU
22605 #define V_CMDADDR3(x) ((x) << S_CMDADDR3)
22606 #define G_CMDADDR3(x) (((x) >> S_CMDADDR3) & M_CMDADDR3)
22607 
22608 #define S_WRDATAVLD3    7
22609 #define V_WRDATAVLD3(x) ((x) << S_WRDATAVLD3)
22610 #define F_WRDATAVLD3    V_WRDATAVLD3(1U)
22611 
22612 #define S_WRDATARDY3    6
22613 #define V_WRDATARDY3(x) ((x) << S_WRDATARDY3)
22614 #define F_WRDATARDY3    V_WRDATARDY3(1U)
22615 
22616 #define S_RDDATARDY3    5
22617 #define V_RDDATARDY3(x) ((x) << S_RDDATARDY3)
22618 #define F_RDDATARDY3    V_RDDATARDY3(1U)
22619 
22620 #define S_RDDATAVLD3    4
22621 #define V_RDDATAVLD3(x) ((x) << S_RDDATAVLD3)
22622 #define F_RDDATAVLD3    V_RDDATAVLD3(1U)
22623 
22624 #define S_RDDATA3    0
22625 #define M_RDDATA3    0xfU
22626 #define V_RDDATA3(x) ((x) << S_RDDATA3)
22627 #define G_RDDATA3(x) (((x) >> S_RDDATA3) & M_RDDATA3)
22628 
22629 #define A_MA_ULP_TX_RX_CLIENT_INTERFACE_EXTERNAL 0xa004
22630 
22631 #define S_CMDVLD4    31
22632 #define V_CMDVLD4(x) ((x) << S_CMDVLD4)
22633 #define F_CMDVLD4    V_CMDVLD4(1U)
22634 
22635 #define S_CMDRDY4    30
22636 #define V_CMDRDY4(x) ((x) << S_CMDRDY4)
22637 #define F_CMDRDY4    V_CMDRDY4(1U)
22638 
22639 #define S_CMDTYPE4    29
22640 #define V_CMDTYPE4(x) ((x) << S_CMDTYPE4)
22641 #define F_CMDTYPE4    V_CMDTYPE4(1U)
22642 
22643 #define S_CMDLEN4    21
22644 #define M_CMDLEN4    0xffU
22645 #define V_CMDLEN4(x) ((x) << S_CMDLEN4)
22646 #define G_CMDLEN4(x) (((x) >> S_CMDLEN4) & M_CMDLEN4)
22647 
22648 #define S_CMDADDR4    8
22649 #define M_CMDADDR4    0x1fffU
22650 #define V_CMDADDR4(x) ((x) << S_CMDADDR4)
22651 #define G_CMDADDR4(x) (((x) >> S_CMDADDR4) & M_CMDADDR4)
22652 
22653 #define S_WRDATAVLD4    7
22654 #define V_WRDATAVLD4(x) ((x) << S_WRDATAVLD4)
22655 #define F_WRDATAVLD4    V_WRDATAVLD4(1U)
22656 
22657 #define S_WRDATARDY4    6
22658 #define V_WRDATARDY4(x) ((x) << S_WRDATARDY4)
22659 #define F_WRDATARDY4    V_WRDATARDY4(1U)
22660 
22661 #define S_RDDATARDY4    5
22662 #define V_RDDATARDY4(x) ((x) << S_RDDATARDY4)
22663 #define F_RDDATARDY4    V_RDDATARDY4(1U)
22664 
22665 #define S_RDDATAVLD4    4
22666 #define V_RDDATAVLD4(x) ((x) << S_RDDATAVLD4)
22667 #define F_RDDATAVLD4    V_RDDATAVLD4(1U)
22668 
22669 #define S_RDDATA4    0
22670 #define M_RDDATA4    0xfU
22671 #define V_RDDATA4(x) ((x) << S_RDDATA4)
22672 #define G_RDDATA4(x) (((x) >> S_RDDATA4) & M_RDDATA4)
22673 
22674 #define A_MA_TP_THREAD_0_CLIENT_INTERFACE_EXTERNAL 0xa005
22675 
22676 #define S_CMDVLD5    31
22677 #define V_CMDVLD5(x) ((x) << S_CMDVLD5)
22678 #define F_CMDVLD5    V_CMDVLD5(1U)
22679 
22680 #define S_CMDRDY5    30
22681 #define V_CMDRDY5(x) ((x) << S_CMDRDY5)
22682 #define F_CMDRDY5    V_CMDRDY5(1U)
22683 
22684 #define S_CMDTYPE5    29
22685 #define V_CMDTYPE5(x) ((x) << S_CMDTYPE5)
22686 #define F_CMDTYPE5    V_CMDTYPE5(1U)
22687 
22688 #define S_CMDLEN5    21
22689 #define M_CMDLEN5    0xffU
22690 #define V_CMDLEN5(x) ((x) << S_CMDLEN5)
22691 #define G_CMDLEN5(x) (((x) >> S_CMDLEN5) & M_CMDLEN5)
22692 
22693 #define S_CMDADDR5    8
22694 #define M_CMDADDR5    0x1fffU
22695 #define V_CMDADDR5(x) ((x) << S_CMDADDR5)
22696 #define G_CMDADDR5(x) (((x) >> S_CMDADDR5) & M_CMDADDR5)
22697 
22698 #define S_WRDATAVLD5    7
22699 #define V_WRDATAVLD5(x) ((x) << S_WRDATAVLD5)
22700 #define F_WRDATAVLD5    V_WRDATAVLD5(1U)
22701 
22702 #define S_WRDATARDY5    6
22703 #define V_WRDATARDY5(x) ((x) << S_WRDATARDY5)
22704 #define F_WRDATARDY5    V_WRDATARDY5(1U)
22705 
22706 #define S_RDDATARDY5    5
22707 #define V_RDDATARDY5(x) ((x) << S_RDDATARDY5)
22708 #define F_RDDATARDY5    V_RDDATARDY5(1U)
22709 
22710 #define S_RDDATAVLD5    4
22711 #define V_RDDATAVLD5(x) ((x) << S_RDDATAVLD5)
22712 #define F_RDDATAVLD5    V_RDDATAVLD5(1U)
22713 
22714 #define S_RDDATA5    0
22715 #define M_RDDATA5    0xfU
22716 #define V_RDDATA5(x) ((x) << S_RDDATA5)
22717 #define G_RDDATA5(x) (((x) >> S_RDDATA5) & M_RDDATA5)
22718 
22719 #define A_MA_TP_THREAD_1_CLIENT_INTERFACE_EXTERNAL 0xa006
22720 
22721 #define S_CMDVLD6    31
22722 #define V_CMDVLD6(x) ((x) << S_CMDVLD6)
22723 #define F_CMDVLD6    V_CMDVLD6(1U)
22724 
22725 #define S_CMDRDY6    30
22726 #define V_CMDRDY6(x) ((x) << S_CMDRDY6)
22727 #define F_CMDRDY6    V_CMDRDY6(1U)
22728 
22729 #define S_CMDTYPE6    29
22730 #define V_CMDTYPE6(x) ((x) << S_CMDTYPE6)
22731 #define F_CMDTYPE6    V_CMDTYPE6(1U)
22732 
22733 #define S_CMDLEN6    21
22734 #define M_CMDLEN6    0xffU
22735 #define V_CMDLEN6(x) ((x) << S_CMDLEN6)
22736 #define G_CMDLEN6(x) (((x) >> S_CMDLEN6) & M_CMDLEN6)
22737 
22738 #define S_CMDADDR6    8
22739 #define M_CMDADDR6    0x1fffU
22740 #define V_CMDADDR6(x) ((x) << S_CMDADDR6)
22741 #define G_CMDADDR6(x) (((x) >> S_CMDADDR6) & M_CMDADDR6)
22742 
22743 #define S_WRDATAVLD6    7
22744 #define V_WRDATAVLD6(x) ((x) << S_WRDATAVLD6)
22745 #define F_WRDATAVLD6    V_WRDATAVLD6(1U)
22746 
22747 #define S_WRDATARDY6    6
22748 #define V_WRDATARDY6(x) ((x) << S_WRDATARDY6)
22749 #define F_WRDATARDY6    V_WRDATARDY6(1U)
22750 
22751 #define S_RDDATARDY6    5
22752 #define V_RDDATARDY6(x) ((x) << S_RDDATARDY6)
22753 #define F_RDDATARDY6    V_RDDATARDY6(1U)
22754 
22755 #define S_RDDATAVLD6    4
22756 #define V_RDDATAVLD6(x) ((x) << S_RDDATAVLD6)
22757 #define F_RDDATAVLD6    V_RDDATAVLD6(1U)
22758 
22759 #define S_RDDATA6    0
22760 #define M_RDDATA6    0xfU
22761 #define V_RDDATA6(x) ((x) << S_RDDATA6)
22762 #define G_RDDATA6(x) (((x) >> S_RDDATA6) & M_RDDATA6)
22763 
22764 #define A_MA_LE_CLIENT_INTERFACE_EXTERNAL 0xa007
22765 
22766 #define S_CMDVLD7    31
22767 #define V_CMDVLD7(x) ((x) << S_CMDVLD7)
22768 #define F_CMDVLD7    V_CMDVLD7(1U)
22769 
22770 #define S_CMDRDY7    30
22771 #define V_CMDRDY7(x) ((x) << S_CMDRDY7)
22772 #define F_CMDRDY7    V_CMDRDY7(1U)
22773 
22774 #define S_CMDTYPE7    29
22775 #define V_CMDTYPE7(x) ((x) << S_CMDTYPE7)
22776 #define F_CMDTYPE7    V_CMDTYPE7(1U)
22777 
22778 #define S_CMDLEN7    21
22779 #define M_CMDLEN7    0xffU
22780 #define V_CMDLEN7(x) ((x) << S_CMDLEN7)
22781 #define G_CMDLEN7(x) (((x) >> S_CMDLEN7) & M_CMDLEN7)
22782 
22783 #define S_CMDADDR7    8
22784 #define M_CMDADDR7    0x1fffU
22785 #define V_CMDADDR7(x) ((x) << S_CMDADDR7)
22786 #define G_CMDADDR7(x) (((x) >> S_CMDADDR7) & M_CMDADDR7)
22787 
22788 #define S_WRDATAVLD7    7
22789 #define V_WRDATAVLD7(x) ((x) << S_WRDATAVLD7)
22790 #define F_WRDATAVLD7    V_WRDATAVLD7(1U)
22791 
22792 #define S_WRDATARDY7    6
22793 #define V_WRDATARDY7(x) ((x) << S_WRDATARDY7)
22794 #define F_WRDATARDY7    V_WRDATARDY7(1U)
22795 
22796 #define S_RDDATARDY7    5
22797 #define V_RDDATARDY7(x) ((x) << S_RDDATARDY7)
22798 #define F_RDDATARDY7    V_RDDATARDY7(1U)
22799 
22800 #define S_RDDATAVLD7    4
22801 #define V_RDDATAVLD7(x) ((x) << S_RDDATAVLD7)
22802 #define F_RDDATAVLD7    V_RDDATAVLD7(1U)
22803 
22804 #define S_RDDATA7    0
22805 #define M_RDDATA7    0xfU
22806 #define V_RDDATA7(x) ((x) << S_RDDATA7)
22807 #define G_RDDATA7(x) (((x) >> S_RDDATA7) & M_RDDATA7)
22808 
22809 #define A_MA_CIM_CLIENT_INTERFACE_EXTERNAL 0xa008
22810 
22811 #define S_CMDVLD8    31
22812 #define V_CMDVLD8(x) ((x) << S_CMDVLD8)
22813 #define F_CMDVLD8    V_CMDVLD8(1U)
22814 
22815 #define S_CMDRDY8    30
22816 #define V_CMDRDY8(x) ((x) << S_CMDRDY8)
22817 #define F_CMDRDY8    V_CMDRDY8(1U)
22818 
22819 #define S_CMDTYPE8    29
22820 #define V_CMDTYPE8(x) ((x) << S_CMDTYPE8)
22821 #define F_CMDTYPE8    V_CMDTYPE8(1U)
22822 
22823 #define S_CMDLEN8    21
22824 #define M_CMDLEN8    0xffU
22825 #define V_CMDLEN8(x) ((x) << S_CMDLEN8)
22826 #define G_CMDLEN8(x) (((x) >> S_CMDLEN8) & M_CMDLEN8)
22827 
22828 #define S_CMDADDR8    8
22829 #define M_CMDADDR8    0x1fffU
22830 #define V_CMDADDR8(x) ((x) << S_CMDADDR8)
22831 #define G_CMDADDR8(x) (((x) >> S_CMDADDR8) & M_CMDADDR8)
22832 
22833 #define S_WRDATAVLD8    7
22834 #define V_WRDATAVLD8(x) ((x) << S_WRDATAVLD8)
22835 #define F_WRDATAVLD8    V_WRDATAVLD8(1U)
22836 
22837 #define S_WRDATARDY8    6
22838 #define V_WRDATARDY8(x) ((x) << S_WRDATARDY8)
22839 #define F_WRDATARDY8    V_WRDATARDY8(1U)
22840 
22841 #define S_RDDATARDY8    5
22842 #define V_RDDATARDY8(x) ((x) << S_RDDATARDY8)
22843 #define F_RDDATARDY8    V_RDDATARDY8(1U)
22844 
22845 #define S_RDDATAVLD8    4
22846 #define V_RDDATAVLD8(x) ((x) << S_RDDATAVLD8)
22847 #define F_RDDATAVLD8    V_RDDATAVLD8(1U)
22848 
22849 #define S_RDDATA8    0
22850 #define M_RDDATA8    0xfU
22851 #define V_RDDATA8(x) ((x) << S_RDDATA8)
22852 #define G_RDDATA8(x) (((x) >> S_RDDATA8) & M_RDDATA8)
22853 
22854 #define A_MA_PCIE_CLIENT_INTERFACE_EXTERNAL 0xa009
22855 
22856 #define S_CMDVLD9    31
22857 #define V_CMDVLD9(x) ((x) << S_CMDVLD9)
22858 #define F_CMDVLD9    V_CMDVLD9(1U)
22859 
22860 #define S_CMDRDY9    30
22861 #define V_CMDRDY9(x) ((x) << S_CMDRDY9)
22862 #define F_CMDRDY9    V_CMDRDY9(1U)
22863 
22864 #define S_CMDTYPE9    29
22865 #define V_CMDTYPE9(x) ((x) << S_CMDTYPE9)
22866 #define F_CMDTYPE9    V_CMDTYPE9(1U)
22867 
22868 #define S_CMDLEN9    21
22869 #define M_CMDLEN9    0xffU
22870 #define V_CMDLEN9(x) ((x) << S_CMDLEN9)
22871 #define G_CMDLEN9(x) (((x) >> S_CMDLEN9) & M_CMDLEN9)
22872 
22873 #define S_CMDADDR9    8
22874 #define M_CMDADDR9    0x1fffU
22875 #define V_CMDADDR9(x) ((x) << S_CMDADDR9)
22876 #define G_CMDADDR9(x) (((x) >> S_CMDADDR9) & M_CMDADDR9)
22877 
22878 #define S_WRDATAVLD9    7
22879 #define V_WRDATAVLD9(x) ((x) << S_WRDATAVLD9)
22880 #define F_WRDATAVLD9    V_WRDATAVLD9(1U)
22881 
22882 #define S_WRDATARDY9    6
22883 #define V_WRDATARDY9(x) ((x) << S_WRDATARDY9)
22884 #define F_WRDATARDY9    V_WRDATARDY9(1U)
22885 
22886 #define S_RDDATARDY9    5
22887 #define V_RDDATARDY9(x) ((x) << S_RDDATARDY9)
22888 #define F_RDDATARDY9    V_RDDATARDY9(1U)
22889 
22890 #define S_RDDATAVLD9    4
22891 #define V_RDDATAVLD9(x) ((x) << S_RDDATAVLD9)
22892 #define F_RDDATAVLD9    V_RDDATAVLD9(1U)
22893 
22894 #define S_RDDATA9    0
22895 #define M_RDDATA9    0xfU
22896 #define V_RDDATA9(x) ((x) << S_RDDATA9)
22897 #define G_RDDATA9(x) (((x) >> S_RDDATA9) & M_RDDATA9)
22898 
22899 #define A_MA_PM_TX_CLIENT_INTERFACE_EXTERNAL 0xa00a
22900 
22901 #define S_CMDVLD10    31
22902 #define V_CMDVLD10(x) ((x) << S_CMDVLD10)
22903 #define F_CMDVLD10    V_CMDVLD10(1U)
22904 
22905 #define S_CMDRDY10    30
22906 #define V_CMDRDY10(x) ((x) << S_CMDRDY10)
22907 #define F_CMDRDY10    V_CMDRDY10(1U)
22908 
22909 #define S_CMDTYPE10    29
22910 #define V_CMDTYPE10(x) ((x) << S_CMDTYPE10)
22911 #define F_CMDTYPE10    V_CMDTYPE10(1U)
22912 
22913 #define S_CMDLEN10    21
22914 #define M_CMDLEN10    0xffU
22915 #define V_CMDLEN10(x) ((x) << S_CMDLEN10)
22916 #define G_CMDLEN10(x) (((x) >> S_CMDLEN10) & M_CMDLEN10)
22917 
22918 #define S_CMDADDR10    8
22919 #define M_CMDADDR10    0x1fffU
22920 #define V_CMDADDR10(x) ((x) << S_CMDADDR10)
22921 #define G_CMDADDR10(x) (((x) >> S_CMDADDR10) & M_CMDADDR10)
22922 
22923 #define S_WRDATAVLD10    7
22924 #define V_WRDATAVLD10(x) ((x) << S_WRDATAVLD10)
22925 #define F_WRDATAVLD10    V_WRDATAVLD10(1U)
22926 
22927 #define S_WRDATARDY10    6
22928 #define V_WRDATARDY10(x) ((x) << S_WRDATARDY10)
22929 #define F_WRDATARDY10    V_WRDATARDY10(1U)
22930 
22931 #define S_RDDATARDY10    5
22932 #define V_RDDATARDY10(x) ((x) << S_RDDATARDY10)
22933 #define F_RDDATARDY10    V_RDDATARDY10(1U)
22934 
22935 #define S_RDDATAVLD10    4
22936 #define V_RDDATAVLD10(x) ((x) << S_RDDATAVLD10)
22937 #define F_RDDATAVLD10    V_RDDATAVLD10(1U)
22938 
22939 #define S_RDDATA10    0
22940 #define M_RDDATA10    0xfU
22941 #define V_RDDATA10(x) ((x) << S_RDDATA10)
22942 #define G_RDDATA10(x) (((x) >> S_RDDATA10) & M_RDDATA10)
22943 
22944 #define A_MA_PM_RX_CLIENT_INTERFACE_EXTERNAL 0xa00b
22945 
22946 #define S_CMDVLD11    31
22947 #define V_CMDVLD11(x) ((x) << S_CMDVLD11)
22948 #define F_CMDVLD11    V_CMDVLD11(1U)
22949 
22950 #define S_CMDRDY11    30
22951 #define V_CMDRDY11(x) ((x) << S_CMDRDY11)
22952 #define F_CMDRDY11    V_CMDRDY11(1U)
22953 
22954 #define S_CMDTYPE11    29
22955 #define V_CMDTYPE11(x) ((x) << S_CMDTYPE11)
22956 #define F_CMDTYPE11    V_CMDTYPE11(1U)
22957 
22958 #define S_CMDLEN11    21
22959 #define M_CMDLEN11    0xffU
22960 #define V_CMDLEN11(x) ((x) << S_CMDLEN11)
22961 #define G_CMDLEN11(x) (((x) >> S_CMDLEN11) & M_CMDLEN11)
22962 
22963 #define S_CMDADDR11    8
22964 #define M_CMDADDR11    0x1fffU
22965 #define V_CMDADDR11(x) ((x) << S_CMDADDR11)
22966 #define G_CMDADDR11(x) (((x) >> S_CMDADDR11) & M_CMDADDR11)
22967 
22968 #define S_WRDATAVLD11    7
22969 #define V_WRDATAVLD11(x) ((x) << S_WRDATAVLD11)
22970 #define F_WRDATAVLD11    V_WRDATAVLD11(1U)
22971 
22972 #define S_WRDATARDY11    6
22973 #define V_WRDATARDY11(x) ((x) << S_WRDATARDY11)
22974 #define F_WRDATARDY11    V_WRDATARDY11(1U)
22975 
22976 #define S_RDDATARDY11    5
22977 #define V_RDDATARDY11(x) ((x) << S_RDDATARDY11)
22978 #define F_RDDATARDY11    V_RDDATARDY11(1U)
22979 
22980 #define S_RDDATAVLD11    4
22981 #define V_RDDATAVLD11(x) ((x) << S_RDDATAVLD11)
22982 #define F_RDDATAVLD11    V_RDDATAVLD11(1U)
22983 
22984 #define S_RDDATA11    0
22985 #define M_RDDATA11    0xfU
22986 #define V_RDDATA11(x) ((x) << S_RDDATA11)
22987 #define G_RDDATA11(x) (((x) >> S_RDDATA11) & M_RDDATA11)
22988 
22989 #define A_MA_HMA_CLIENT_INTERFACE_EXTERNAL 0xa00c
22990 
22991 #define S_CMDVLD12    31
22992 #define V_CMDVLD12(x) ((x) << S_CMDVLD12)
22993 #define F_CMDVLD12    V_CMDVLD12(1U)
22994 
22995 #define S_CMDRDY12    30
22996 #define V_CMDRDY12(x) ((x) << S_CMDRDY12)
22997 #define F_CMDRDY12    V_CMDRDY12(1U)
22998 
22999 #define S_CMDTYPE12    29
23000 #define V_CMDTYPE12(x) ((x) << S_CMDTYPE12)
23001 #define F_CMDTYPE12    V_CMDTYPE12(1U)
23002 
23003 #define S_CMDLEN12    21
23004 #define M_CMDLEN12    0xffU
23005 #define V_CMDLEN12(x) ((x) << S_CMDLEN12)
23006 #define G_CMDLEN12(x) (((x) >> S_CMDLEN12) & M_CMDLEN12)
23007 
23008 #define S_CMDADDR12    8
23009 #define M_CMDADDR12    0x1fffU
23010 #define V_CMDADDR12(x) ((x) << S_CMDADDR12)
23011 #define G_CMDADDR12(x) (((x) >> S_CMDADDR12) & M_CMDADDR12)
23012 
23013 #define S_WRDATAVLD12    7
23014 #define V_WRDATAVLD12(x) ((x) << S_WRDATAVLD12)
23015 #define F_WRDATAVLD12    V_WRDATAVLD12(1U)
23016 
23017 #define S_WRDATARDY12    6
23018 #define V_WRDATARDY12(x) ((x) << S_WRDATARDY12)
23019 #define F_WRDATARDY12    V_WRDATARDY12(1U)
23020 
23021 #define S_RDDATARDY12    5
23022 #define V_RDDATARDY12(x) ((x) << S_RDDATARDY12)
23023 #define F_RDDATARDY12    V_RDDATARDY12(1U)
23024 
23025 #define S_RDDATAVLD12    4
23026 #define V_RDDATAVLD12(x) ((x) << S_RDDATAVLD12)
23027 #define F_RDDATAVLD12    V_RDDATAVLD12(1U)
23028 
23029 #define S_RDDATA12    0
23030 #define M_RDDATA12    0xfU
23031 #define V_RDDATA12(x) ((x) << S_RDDATA12)
23032 #define G_RDDATA12(x) (((x) >> S_RDDATA12) & M_RDDATA12)
23033 
23034 #define A_MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00d
23035 
23036 #define S_CI0_ARB0_REQ    31
23037 #define V_CI0_ARB0_REQ(x) ((x) << S_CI0_ARB0_REQ)
23038 #define F_CI0_ARB0_REQ    V_CI0_ARB0_REQ(1U)
23039 
23040 #define S_ARB0_CI0_GNT    30
23041 #define V_ARB0_CI0_GNT(x) ((x) << S_ARB0_CI0_GNT)
23042 #define F_ARB0_CI0_GNT    V_ARB0_CI0_GNT(1U)
23043 
23044 #define S_CI0_DM0_WDATA_VLD    29
23045 #define V_CI0_DM0_WDATA_VLD(x) ((x) << S_CI0_DM0_WDATA_VLD)
23046 #define F_CI0_DM0_WDATA_VLD    V_CI0_DM0_WDATA_VLD(1U)
23047 
23048 #define S_DM0_CI0_RDATA_VLD    28
23049 #define V_DM0_CI0_RDATA_VLD(x) ((x) << S_DM0_CI0_RDATA_VLD)
23050 #define F_DM0_CI0_RDATA_VLD    V_DM0_CI0_RDATA_VLD(1U)
23051 
23052 #define S_CI1_ARB0_REQ    27
23053 #define V_CI1_ARB0_REQ(x) ((x) << S_CI1_ARB0_REQ)
23054 #define F_CI1_ARB0_REQ    V_CI1_ARB0_REQ(1U)
23055 
23056 #define S_ARB0_CI1_GNT    26
23057 #define V_ARB0_CI1_GNT(x) ((x) << S_ARB0_CI1_GNT)
23058 #define F_ARB0_CI1_GNT    V_ARB0_CI1_GNT(1U)
23059 
23060 #define S_CI1_DM0_WDATA_VLD    25
23061 #define V_CI1_DM0_WDATA_VLD(x) ((x) << S_CI1_DM0_WDATA_VLD)
23062 #define F_CI1_DM0_WDATA_VLD    V_CI1_DM0_WDATA_VLD(1U)
23063 
23064 #define S_DM0_CI1_RDATA_VLD    24
23065 #define V_DM0_CI1_RDATA_VLD(x) ((x) << S_DM0_CI1_RDATA_VLD)
23066 #define F_DM0_CI1_RDATA_VLD    V_DM0_CI1_RDATA_VLD(1U)
23067 
23068 #define S_CI2_ARB0_REQ    23
23069 #define V_CI2_ARB0_REQ(x) ((x) << S_CI2_ARB0_REQ)
23070 #define F_CI2_ARB0_REQ    V_CI2_ARB0_REQ(1U)
23071 
23072 #define S_ARB0_CI2_GNT    22
23073 #define V_ARB0_CI2_GNT(x) ((x) << S_ARB0_CI2_GNT)
23074 #define F_ARB0_CI2_GNT    V_ARB0_CI2_GNT(1U)
23075 
23076 #define S_CI2_DM0_WDATA_VLD    21
23077 #define V_CI2_DM0_WDATA_VLD(x) ((x) << S_CI2_DM0_WDATA_VLD)
23078 #define F_CI2_DM0_WDATA_VLD    V_CI2_DM0_WDATA_VLD(1U)
23079 
23080 #define S_DM0_CI2_RDATA_VLD    20
23081 #define V_DM0_CI2_RDATA_VLD(x) ((x) << S_DM0_CI2_RDATA_VLD)
23082 #define F_DM0_CI2_RDATA_VLD    V_DM0_CI2_RDATA_VLD(1U)
23083 
23084 #define S_CI3_ARB0_REQ    19
23085 #define V_CI3_ARB0_REQ(x) ((x) << S_CI3_ARB0_REQ)
23086 #define F_CI3_ARB0_REQ    V_CI3_ARB0_REQ(1U)
23087 
23088 #define S_ARB0_CI3_GNT    18
23089 #define V_ARB0_CI3_GNT(x) ((x) << S_ARB0_CI3_GNT)
23090 #define F_ARB0_CI3_GNT    V_ARB0_CI3_GNT(1U)
23091 
23092 #define S_CI3_DM0_WDATA_VLD    17
23093 #define V_CI3_DM0_WDATA_VLD(x) ((x) << S_CI3_DM0_WDATA_VLD)
23094 #define F_CI3_DM0_WDATA_VLD    V_CI3_DM0_WDATA_VLD(1U)
23095 
23096 #define S_DM0_CI3_RDATA_VLD    16
23097 #define V_DM0_CI3_RDATA_VLD(x) ((x) << S_DM0_CI3_RDATA_VLD)
23098 #define F_DM0_CI3_RDATA_VLD    V_DM0_CI3_RDATA_VLD(1U)
23099 
23100 #define S_CI4_ARB0_REQ    15
23101 #define V_CI4_ARB0_REQ(x) ((x) << S_CI4_ARB0_REQ)
23102 #define F_CI4_ARB0_REQ    V_CI4_ARB0_REQ(1U)
23103 
23104 #define S_ARB0_CI4_GNT    14
23105 #define V_ARB0_CI4_GNT(x) ((x) << S_ARB0_CI4_GNT)
23106 #define F_ARB0_CI4_GNT    V_ARB0_CI4_GNT(1U)
23107 
23108 #define S_CI4_DM0_WDATA_VLD    13
23109 #define V_CI4_DM0_WDATA_VLD(x) ((x) << S_CI4_DM0_WDATA_VLD)
23110 #define F_CI4_DM0_WDATA_VLD    V_CI4_DM0_WDATA_VLD(1U)
23111 
23112 #define S_DM0_CI4_RDATA_VLD    12
23113 #define V_DM0_CI4_RDATA_VLD(x) ((x) << S_DM0_CI4_RDATA_VLD)
23114 #define F_DM0_CI4_RDATA_VLD    V_DM0_CI4_RDATA_VLD(1U)
23115 
23116 #define S_CI5_ARB0_REQ    11
23117 #define V_CI5_ARB0_REQ(x) ((x) << S_CI5_ARB0_REQ)
23118 #define F_CI5_ARB0_REQ    V_CI5_ARB0_REQ(1U)
23119 
23120 #define S_ARB0_CI5_GNT    10
23121 #define V_ARB0_CI5_GNT(x) ((x) << S_ARB0_CI5_GNT)
23122 #define F_ARB0_CI5_GNT    V_ARB0_CI5_GNT(1U)
23123 
23124 #define S_CI5_DM0_WDATA_VLD    9
23125 #define V_CI5_DM0_WDATA_VLD(x) ((x) << S_CI5_DM0_WDATA_VLD)
23126 #define F_CI5_DM0_WDATA_VLD    V_CI5_DM0_WDATA_VLD(1U)
23127 
23128 #define S_DM0_CI5_RDATA_VLD    8
23129 #define V_DM0_CI5_RDATA_VLD(x) ((x) << S_DM0_CI5_RDATA_VLD)
23130 #define F_DM0_CI5_RDATA_VLD    V_DM0_CI5_RDATA_VLD(1U)
23131 
23132 #define S_CI6_ARB0_REQ    7
23133 #define V_CI6_ARB0_REQ(x) ((x) << S_CI6_ARB0_REQ)
23134 #define F_CI6_ARB0_REQ    V_CI6_ARB0_REQ(1U)
23135 
23136 #define S_ARB0_CI6_GNT    6
23137 #define V_ARB0_CI6_GNT(x) ((x) << S_ARB0_CI6_GNT)
23138 #define F_ARB0_CI6_GNT    V_ARB0_CI6_GNT(1U)
23139 
23140 #define S_CI6_DM0_WDATA_VLD    5
23141 #define V_CI6_DM0_WDATA_VLD(x) ((x) << S_CI6_DM0_WDATA_VLD)
23142 #define F_CI6_DM0_WDATA_VLD    V_CI6_DM0_WDATA_VLD(1U)
23143 
23144 #define S_DM0_CI6_RDATA_VLD    4
23145 #define V_DM0_CI6_RDATA_VLD(x) ((x) << S_DM0_CI6_RDATA_VLD)
23146 #define F_DM0_CI6_RDATA_VLD    V_DM0_CI6_RDATA_VLD(1U)
23147 
23148 #define S_CI7_ARB0_REQ    3
23149 #define V_CI7_ARB0_REQ(x) ((x) << S_CI7_ARB0_REQ)
23150 #define F_CI7_ARB0_REQ    V_CI7_ARB0_REQ(1U)
23151 
23152 #define S_ARB0_CI7_GNT    2
23153 #define V_ARB0_CI7_GNT(x) ((x) << S_ARB0_CI7_GNT)
23154 #define F_ARB0_CI7_GNT    V_ARB0_CI7_GNT(1U)
23155 
23156 #define S_CI7_DM0_WDATA_VLD    1
23157 #define V_CI7_DM0_WDATA_VLD(x) ((x) << S_CI7_DM0_WDATA_VLD)
23158 #define F_CI7_DM0_WDATA_VLD    V_CI7_DM0_WDATA_VLD(1U)
23159 
23160 #define S_DM0_CI7_RDATA_VLD    0
23161 #define V_DM0_CI7_RDATA_VLD(x) ((x) << S_DM0_CI7_RDATA_VLD)
23162 #define F_DM0_CI7_RDATA_VLD    V_DM0_CI7_RDATA_VLD(1U)
23163 
23164 #define A_MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00e
23165 
23166 #define S_CI0_ARB1_REQ    31
23167 #define V_CI0_ARB1_REQ(x) ((x) << S_CI0_ARB1_REQ)
23168 #define F_CI0_ARB1_REQ    V_CI0_ARB1_REQ(1U)
23169 
23170 #define S_ARB1_CI0_GNT    30
23171 #define V_ARB1_CI0_GNT(x) ((x) << S_ARB1_CI0_GNT)
23172 #define F_ARB1_CI0_GNT    V_ARB1_CI0_GNT(1U)
23173 
23174 #define S_CI0_DM1_WDATA_VLD    29
23175 #define V_CI0_DM1_WDATA_VLD(x) ((x) << S_CI0_DM1_WDATA_VLD)
23176 #define F_CI0_DM1_WDATA_VLD    V_CI0_DM1_WDATA_VLD(1U)
23177 
23178 #define S_DM1_CI0_RDATA_VLD    28
23179 #define V_DM1_CI0_RDATA_VLD(x) ((x) << S_DM1_CI0_RDATA_VLD)
23180 #define F_DM1_CI0_RDATA_VLD    V_DM1_CI0_RDATA_VLD(1U)
23181 
23182 #define S_CI1_ARB1_REQ    27
23183 #define V_CI1_ARB1_REQ(x) ((x) << S_CI1_ARB1_REQ)
23184 #define F_CI1_ARB1_REQ    V_CI1_ARB1_REQ(1U)
23185 
23186 #define S_ARB1_CI1_GNT    26
23187 #define V_ARB1_CI1_GNT(x) ((x) << S_ARB1_CI1_GNT)
23188 #define F_ARB1_CI1_GNT    V_ARB1_CI1_GNT(1U)
23189 
23190 #define S_CI1_DM1_WDATA_VLD    25
23191 #define V_CI1_DM1_WDATA_VLD(x) ((x) << S_CI1_DM1_WDATA_VLD)
23192 #define F_CI1_DM1_WDATA_VLD    V_CI1_DM1_WDATA_VLD(1U)
23193 
23194 #define S_DM1_CI1_RDATA_VLD    24
23195 #define V_DM1_CI1_RDATA_VLD(x) ((x) << S_DM1_CI1_RDATA_VLD)
23196 #define F_DM1_CI1_RDATA_VLD    V_DM1_CI1_RDATA_VLD(1U)
23197 
23198 #define S_CI2_ARB1_REQ    23
23199 #define V_CI2_ARB1_REQ(x) ((x) << S_CI2_ARB1_REQ)
23200 #define F_CI2_ARB1_REQ    V_CI2_ARB1_REQ(1U)
23201 
23202 #define S_ARB1_CI2_GNT    22
23203 #define V_ARB1_CI2_GNT(x) ((x) << S_ARB1_CI2_GNT)
23204 #define F_ARB1_CI2_GNT    V_ARB1_CI2_GNT(1U)
23205 
23206 #define S_CI2_DM1_WDATA_VLD    21
23207 #define V_CI2_DM1_WDATA_VLD(x) ((x) << S_CI2_DM1_WDATA_VLD)
23208 #define F_CI2_DM1_WDATA_VLD    V_CI2_DM1_WDATA_VLD(1U)
23209 
23210 #define S_DM1_CI2_RDATA_VLD    20
23211 #define V_DM1_CI2_RDATA_VLD(x) ((x) << S_DM1_CI2_RDATA_VLD)
23212 #define F_DM1_CI2_RDATA_VLD    V_DM1_CI2_RDATA_VLD(1U)
23213 
23214 #define S_CI3_ARB1_REQ    19
23215 #define V_CI3_ARB1_REQ(x) ((x) << S_CI3_ARB1_REQ)
23216 #define F_CI3_ARB1_REQ    V_CI3_ARB1_REQ(1U)
23217 
23218 #define S_ARB1_CI3_GNT    18
23219 #define V_ARB1_CI3_GNT(x) ((x) << S_ARB1_CI3_GNT)
23220 #define F_ARB1_CI3_GNT    V_ARB1_CI3_GNT(1U)
23221 
23222 #define S_CI3_DM1_WDATA_VLD    17
23223 #define V_CI3_DM1_WDATA_VLD(x) ((x) << S_CI3_DM1_WDATA_VLD)
23224 #define F_CI3_DM1_WDATA_VLD    V_CI3_DM1_WDATA_VLD(1U)
23225 
23226 #define S_DM1_CI3_RDATA_VLD    16
23227 #define V_DM1_CI3_RDATA_VLD(x) ((x) << S_DM1_CI3_RDATA_VLD)
23228 #define F_DM1_CI3_RDATA_VLD    V_DM1_CI3_RDATA_VLD(1U)
23229 
23230 #define S_CI4_ARB1_REQ    15
23231 #define V_CI4_ARB1_REQ(x) ((x) << S_CI4_ARB1_REQ)
23232 #define F_CI4_ARB1_REQ    V_CI4_ARB1_REQ(1U)
23233 
23234 #define S_ARB1_CI4_GNT    14
23235 #define V_ARB1_CI4_GNT(x) ((x) << S_ARB1_CI4_GNT)
23236 #define F_ARB1_CI4_GNT    V_ARB1_CI4_GNT(1U)
23237 
23238 #define S_CI4_DM1_WDATA_VLD    13
23239 #define V_CI4_DM1_WDATA_VLD(x) ((x) << S_CI4_DM1_WDATA_VLD)
23240 #define F_CI4_DM1_WDATA_VLD    V_CI4_DM1_WDATA_VLD(1U)
23241 
23242 #define S_DM1_CI4_RDATA_VLD    12
23243 #define V_DM1_CI4_RDATA_VLD(x) ((x) << S_DM1_CI4_RDATA_VLD)
23244 #define F_DM1_CI4_RDATA_VLD    V_DM1_CI4_RDATA_VLD(1U)
23245 
23246 #define S_CI5_ARB1_REQ    11
23247 #define V_CI5_ARB1_REQ(x) ((x) << S_CI5_ARB1_REQ)
23248 #define F_CI5_ARB1_REQ    V_CI5_ARB1_REQ(1U)
23249 
23250 #define S_ARB1_CI5_GNT    10
23251 #define V_ARB1_CI5_GNT(x) ((x) << S_ARB1_CI5_GNT)
23252 #define F_ARB1_CI5_GNT    V_ARB1_CI5_GNT(1U)
23253 
23254 #define S_CI5_DM1_WDATA_VLD    9
23255 #define V_CI5_DM1_WDATA_VLD(x) ((x) << S_CI5_DM1_WDATA_VLD)
23256 #define F_CI5_DM1_WDATA_VLD    V_CI5_DM1_WDATA_VLD(1U)
23257 
23258 #define S_DM1_CI5_RDATA_VLD    8
23259 #define V_DM1_CI5_RDATA_VLD(x) ((x) << S_DM1_CI5_RDATA_VLD)
23260 #define F_DM1_CI5_RDATA_VLD    V_DM1_CI5_RDATA_VLD(1U)
23261 
23262 #define S_CI6_ARB1_REQ    7
23263 #define V_CI6_ARB1_REQ(x) ((x) << S_CI6_ARB1_REQ)
23264 #define F_CI6_ARB1_REQ    V_CI6_ARB1_REQ(1U)
23265 
23266 #define S_ARB1_CI6_GNT    6
23267 #define V_ARB1_CI6_GNT(x) ((x) << S_ARB1_CI6_GNT)
23268 #define F_ARB1_CI6_GNT    V_ARB1_CI6_GNT(1U)
23269 
23270 #define S_CI6_DM1_WDATA_VLD    5
23271 #define V_CI6_DM1_WDATA_VLD(x) ((x) << S_CI6_DM1_WDATA_VLD)
23272 #define F_CI6_DM1_WDATA_VLD    V_CI6_DM1_WDATA_VLD(1U)
23273 
23274 #define S_DM1_CI6_RDATA_VLD    4
23275 #define V_DM1_CI6_RDATA_VLD(x) ((x) << S_DM1_CI6_RDATA_VLD)
23276 #define F_DM1_CI6_RDATA_VLD    V_DM1_CI6_RDATA_VLD(1U)
23277 
23278 #define S_CI7_ARB1_REQ    3
23279 #define V_CI7_ARB1_REQ(x) ((x) << S_CI7_ARB1_REQ)
23280 #define F_CI7_ARB1_REQ    V_CI7_ARB1_REQ(1U)
23281 
23282 #define S_ARB1_CI7_GNT    2
23283 #define V_ARB1_CI7_GNT(x) ((x) << S_ARB1_CI7_GNT)
23284 #define F_ARB1_CI7_GNT    V_ARB1_CI7_GNT(1U)
23285 
23286 #define S_CI7_DM1_WDATA_VLD    1
23287 #define V_CI7_DM1_WDATA_VLD(x) ((x) << S_CI7_DM1_WDATA_VLD)
23288 #define F_CI7_DM1_WDATA_VLD    V_CI7_DM1_WDATA_VLD(1U)
23289 
23290 #define S_DM1_CI7_RDATA_VLD    0
23291 #define V_DM1_CI7_RDATA_VLD(x) ((x) << S_DM1_CI7_RDATA_VLD)
23292 #define F_DM1_CI7_RDATA_VLD    V_DM1_CI7_RDATA_VLD(1U)
23293 
23294 #define A_MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00f
23295 
23296 #define S_CI0_ARB2_REQ    31
23297 #define V_CI0_ARB2_REQ(x) ((x) << S_CI0_ARB2_REQ)
23298 #define F_CI0_ARB2_REQ    V_CI0_ARB2_REQ(1U)
23299 
23300 #define S_ARB2_CI0_GNT    30
23301 #define V_ARB2_CI0_GNT(x) ((x) << S_ARB2_CI0_GNT)
23302 #define F_ARB2_CI0_GNT    V_ARB2_CI0_GNT(1U)
23303 
23304 #define S_CI0_DM2_WDATA_VLD    29
23305 #define V_CI0_DM2_WDATA_VLD(x) ((x) << S_CI0_DM2_WDATA_VLD)
23306 #define F_CI0_DM2_WDATA_VLD    V_CI0_DM2_WDATA_VLD(1U)
23307 
23308 #define S_DM2_CI0_RDATA_VLD    28
23309 #define V_DM2_CI0_RDATA_VLD(x) ((x) << S_DM2_CI0_RDATA_VLD)
23310 #define F_DM2_CI0_RDATA_VLD    V_DM2_CI0_RDATA_VLD(1U)
23311 
23312 #define S_CI1_ARB2_REQ    27
23313 #define V_CI1_ARB2_REQ(x) ((x) << S_CI1_ARB2_REQ)
23314 #define F_CI1_ARB2_REQ    V_CI1_ARB2_REQ(1U)
23315 
23316 #define S_ARB2_CI1_GNT    26
23317 #define V_ARB2_CI1_GNT(x) ((x) << S_ARB2_CI1_GNT)
23318 #define F_ARB2_CI1_GNT    V_ARB2_CI1_GNT(1U)
23319 
23320 #define S_CI1_DM2_WDATA_VLD    25
23321 #define V_CI1_DM2_WDATA_VLD(x) ((x) << S_CI1_DM2_WDATA_VLD)
23322 #define F_CI1_DM2_WDATA_VLD    V_CI1_DM2_WDATA_VLD(1U)
23323 
23324 #define S_DM2_CI1_RDATA_VLD    24
23325 #define V_DM2_CI1_RDATA_VLD(x) ((x) << S_DM2_CI1_RDATA_VLD)
23326 #define F_DM2_CI1_RDATA_VLD    V_DM2_CI1_RDATA_VLD(1U)
23327 
23328 #define S_CI2_ARB2_REQ    23
23329 #define V_CI2_ARB2_REQ(x) ((x) << S_CI2_ARB2_REQ)
23330 #define F_CI2_ARB2_REQ    V_CI2_ARB2_REQ(1U)
23331 
23332 #define S_ARB2_CI2_GNT    22
23333 #define V_ARB2_CI2_GNT(x) ((x) << S_ARB2_CI2_GNT)
23334 #define F_ARB2_CI2_GNT    V_ARB2_CI2_GNT(1U)
23335 
23336 #define S_CI2_DM2_WDATA_VLD    21
23337 #define V_CI2_DM2_WDATA_VLD(x) ((x) << S_CI2_DM2_WDATA_VLD)
23338 #define F_CI2_DM2_WDATA_VLD    V_CI2_DM2_WDATA_VLD(1U)
23339 
23340 #define S_DM2_CI2_RDATA_VLD    20
23341 #define V_DM2_CI2_RDATA_VLD(x) ((x) << S_DM2_CI2_RDATA_VLD)
23342 #define F_DM2_CI2_RDATA_VLD    V_DM2_CI2_RDATA_VLD(1U)
23343 
23344 #define S_CI3_ARB2_REQ    19
23345 #define V_CI3_ARB2_REQ(x) ((x) << S_CI3_ARB2_REQ)
23346 #define F_CI3_ARB2_REQ    V_CI3_ARB2_REQ(1U)
23347 
23348 #define S_ARB2_CI3_GNT    18
23349 #define V_ARB2_CI3_GNT(x) ((x) << S_ARB2_CI3_GNT)
23350 #define F_ARB2_CI3_GNT    V_ARB2_CI3_GNT(1U)
23351 
23352 #define S_CI3_DM2_WDATA_VLD    17
23353 #define V_CI3_DM2_WDATA_VLD(x) ((x) << S_CI3_DM2_WDATA_VLD)
23354 #define F_CI3_DM2_WDATA_VLD    V_CI3_DM2_WDATA_VLD(1U)
23355 
23356 #define S_DM2_CI3_RDATA_VLD    16
23357 #define V_DM2_CI3_RDATA_VLD(x) ((x) << S_DM2_CI3_RDATA_VLD)
23358 #define F_DM2_CI3_RDATA_VLD    V_DM2_CI3_RDATA_VLD(1U)
23359 
23360 #define S_CI4_ARB2_REQ    15
23361 #define V_CI4_ARB2_REQ(x) ((x) << S_CI4_ARB2_REQ)
23362 #define F_CI4_ARB2_REQ    V_CI4_ARB2_REQ(1U)
23363 
23364 #define S_ARB2_CI4_GNT    14
23365 #define V_ARB2_CI4_GNT(x) ((x) << S_ARB2_CI4_GNT)
23366 #define F_ARB2_CI4_GNT    V_ARB2_CI4_GNT(1U)
23367 
23368 #define S_CI4_DM2_WDATA_VLD    13
23369 #define V_CI4_DM2_WDATA_VLD(x) ((x) << S_CI4_DM2_WDATA_VLD)
23370 #define F_CI4_DM2_WDATA_VLD    V_CI4_DM2_WDATA_VLD(1U)
23371 
23372 #define S_DM2_CI4_RDATA_VLD    12
23373 #define V_DM2_CI4_RDATA_VLD(x) ((x) << S_DM2_CI4_RDATA_VLD)
23374 #define F_DM2_CI4_RDATA_VLD    V_DM2_CI4_RDATA_VLD(1U)
23375 
23376 #define S_CI5_ARB2_REQ    11
23377 #define V_CI5_ARB2_REQ(x) ((x) << S_CI5_ARB2_REQ)
23378 #define F_CI5_ARB2_REQ    V_CI5_ARB2_REQ(1U)
23379 
23380 #define S_ARB2_CI5_GNT    10
23381 #define V_ARB2_CI5_GNT(x) ((x) << S_ARB2_CI5_GNT)
23382 #define F_ARB2_CI5_GNT    V_ARB2_CI5_GNT(1U)
23383 
23384 #define S_CI5_DM2_WDATA_VLD    9
23385 #define V_CI5_DM2_WDATA_VLD(x) ((x) << S_CI5_DM2_WDATA_VLD)
23386 #define F_CI5_DM2_WDATA_VLD    V_CI5_DM2_WDATA_VLD(1U)
23387 
23388 #define S_DM2_CI5_RDATA_VLD    8
23389 #define V_DM2_CI5_RDATA_VLD(x) ((x) << S_DM2_CI5_RDATA_VLD)
23390 #define F_DM2_CI5_RDATA_VLD    V_DM2_CI5_RDATA_VLD(1U)
23391 
23392 #define S_CI6_ARB2_REQ    7
23393 #define V_CI6_ARB2_REQ(x) ((x) << S_CI6_ARB2_REQ)
23394 #define F_CI6_ARB2_REQ    V_CI6_ARB2_REQ(1U)
23395 
23396 #define S_ARB2_CI6_GNT    6
23397 #define V_ARB2_CI6_GNT(x) ((x) << S_ARB2_CI6_GNT)
23398 #define F_ARB2_CI6_GNT    V_ARB2_CI6_GNT(1U)
23399 
23400 #define S_CI6_DM2_WDATA_VLD    5
23401 #define V_CI6_DM2_WDATA_VLD(x) ((x) << S_CI6_DM2_WDATA_VLD)
23402 #define F_CI6_DM2_WDATA_VLD    V_CI6_DM2_WDATA_VLD(1U)
23403 
23404 #define S_DM2_CI6_RDATA_VLD    4
23405 #define V_DM2_CI6_RDATA_VLD(x) ((x) << S_DM2_CI6_RDATA_VLD)
23406 #define F_DM2_CI6_RDATA_VLD    V_DM2_CI6_RDATA_VLD(1U)
23407 
23408 #define S_CI7_ARB2_REQ    3
23409 #define V_CI7_ARB2_REQ(x) ((x) << S_CI7_ARB2_REQ)
23410 #define F_CI7_ARB2_REQ    V_CI7_ARB2_REQ(1U)
23411 
23412 #define S_ARB2_CI7_GNT    2
23413 #define V_ARB2_CI7_GNT(x) ((x) << S_ARB2_CI7_GNT)
23414 #define F_ARB2_CI7_GNT    V_ARB2_CI7_GNT(1U)
23415 
23416 #define S_CI7_DM2_WDATA_VLD    1
23417 #define V_CI7_DM2_WDATA_VLD(x) ((x) << S_CI7_DM2_WDATA_VLD)
23418 #define F_CI7_DM2_WDATA_VLD    V_CI7_DM2_WDATA_VLD(1U)
23419 
23420 #define S_DM2_CI7_RDATA_VLD    0
23421 #define V_DM2_CI7_RDATA_VLD(x) ((x) << S_DM2_CI7_RDATA_VLD)
23422 #define F_DM2_CI7_RDATA_VLD    V_DM2_CI7_RDATA_VLD(1U)
23423 
23424 #define A_MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG0 0xa010
23425 
23426 #define S_CI0_ARB3_REQ    31
23427 #define V_CI0_ARB3_REQ(x) ((x) << S_CI0_ARB3_REQ)
23428 #define F_CI0_ARB3_REQ    V_CI0_ARB3_REQ(1U)
23429 
23430 #define S_ARB3_CI0_GNT    30
23431 #define V_ARB3_CI0_GNT(x) ((x) << S_ARB3_CI0_GNT)
23432 #define F_ARB3_CI0_GNT    V_ARB3_CI0_GNT(1U)
23433 
23434 #define S_CI0_DM3_WDATA_VLD    29
23435 #define V_CI0_DM3_WDATA_VLD(x) ((x) << S_CI0_DM3_WDATA_VLD)
23436 #define F_CI0_DM3_WDATA_VLD    V_CI0_DM3_WDATA_VLD(1U)
23437 
23438 #define S_DM3_CI0_RDATA_VLD    28
23439 #define V_DM3_CI0_RDATA_VLD(x) ((x) << S_DM3_CI0_RDATA_VLD)
23440 #define F_DM3_CI0_RDATA_VLD    V_DM3_CI0_RDATA_VLD(1U)
23441 
23442 #define S_CI1_ARB3_REQ    27
23443 #define V_CI1_ARB3_REQ(x) ((x) << S_CI1_ARB3_REQ)
23444 #define F_CI1_ARB3_REQ    V_CI1_ARB3_REQ(1U)
23445 
23446 #define S_ARB3_CI1_GNT    26
23447 #define V_ARB3_CI1_GNT(x) ((x) << S_ARB3_CI1_GNT)
23448 #define F_ARB3_CI1_GNT    V_ARB3_CI1_GNT(1U)
23449 
23450 #define S_CI1_DM3_WDATA_VLD    25
23451 #define V_CI1_DM3_WDATA_VLD(x) ((x) << S_CI1_DM3_WDATA_VLD)
23452 #define F_CI1_DM3_WDATA_VLD    V_CI1_DM3_WDATA_VLD(1U)
23453 
23454 #define S_DM3_CI1_RDATA_VLD    24
23455 #define V_DM3_CI1_RDATA_VLD(x) ((x) << S_DM3_CI1_RDATA_VLD)
23456 #define F_DM3_CI1_RDATA_VLD    V_DM3_CI1_RDATA_VLD(1U)
23457 
23458 #define S_CI2_ARB3_REQ    23
23459 #define V_CI2_ARB3_REQ(x) ((x) << S_CI2_ARB3_REQ)
23460 #define F_CI2_ARB3_REQ    V_CI2_ARB3_REQ(1U)
23461 
23462 #define S_ARB3_CI2_GNT    22
23463 #define V_ARB3_CI2_GNT(x) ((x) << S_ARB3_CI2_GNT)
23464 #define F_ARB3_CI2_GNT    V_ARB3_CI2_GNT(1U)
23465 
23466 #define S_CI2_DM3_WDATA_VLD    21
23467 #define V_CI2_DM3_WDATA_VLD(x) ((x) << S_CI2_DM3_WDATA_VLD)
23468 #define F_CI2_DM3_WDATA_VLD    V_CI2_DM3_WDATA_VLD(1U)
23469 
23470 #define S_DM3_CI2_RDATA_VLD    20
23471 #define V_DM3_CI2_RDATA_VLD(x) ((x) << S_DM3_CI2_RDATA_VLD)
23472 #define F_DM3_CI2_RDATA_VLD    V_DM3_CI2_RDATA_VLD(1U)
23473 
23474 #define S_CI3_ARB3_REQ    19
23475 #define V_CI3_ARB3_REQ(x) ((x) << S_CI3_ARB3_REQ)
23476 #define F_CI3_ARB3_REQ    V_CI3_ARB3_REQ(1U)
23477 
23478 #define S_ARB3_CI3_GNT    18
23479 #define V_ARB3_CI3_GNT(x) ((x) << S_ARB3_CI3_GNT)
23480 #define F_ARB3_CI3_GNT    V_ARB3_CI3_GNT(1U)
23481 
23482 #define S_CI3_DM3_WDATA_VLD    17
23483 #define V_CI3_DM3_WDATA_VLD(x) ((x) << S_CI3_DM3_WDATA_VLD)
23484 #define F_CI3_DM3_WDATA_VLD    V_CI3_DM3_WDATA_VLD(1U)
23485 
23486 #define S_DM3_CI3_RDATA_VLD    16
23487 #define V_DM3_CI3_RDATA_VLD(x) ((x) << S_DM3_CI3_RDATA_VLD)
23488 #define F_DM3_CI3_RDATA_VLD    V_DM3_CI3_RDATA_VLD(1U)
23489 
23490 #define S_CI4_ARB3_REQ    15
23491 #define V_CI4_ARB3_REQ(x) ((x) << S_CI4_ARB3_REQ)
23492 #define F_CI4_ARB3_REQ    V_CI4_ARB3_REQ(1U)
23493 
23494 #define S_ARB3_CI4_GNT    14
23495 #define V_ARB3_CI4_GNT(x) ((x) << S_ARB3_CI4_GNT)
23496 #define F_ARB3_CI4_GNT    V_ARB3_CI4_GNT(1U)
23497 
23498 #define S_CI4_DM3_WDATA_VLD    13
23499 #define V_CI4_DM3_WDATA_VLD(x) ((x) << S_CI4_DM3_WDATA_VLD)
23500 #define F_CI4_DM3_WDATA_VLD    V_CI4_DM3_WDATA_VLD(1U)
23501 
23502 #define S_DM3_CI4_RDATA_VLD    12
23503 #define V_DM3_CI4_RDATA_VLD(x) ((x) << S_DM3_CI4_RDATA_VLD)
23504 #define F_DM3_CI4_RDATA_VLD    V_DM3_CI4_RDATA_VLD(1U)
23505 
23506 #define S_CI5_ARB3_REQ    11
23507 #define V_CI5_ARB3_REQ(x) ((x) << S_CI5_ARB3_REQ)
23508 #define F_CI5_ARB3_REQ    V_CI5_ARB3_REQ(1U)
23509 
23510 #define S_ARB3_CI5_GNT    10
23511 #define V_ARB3_CI5_GNT(x) ((x) << S_ARB3_CI5_GNT)
23512 #define F_ARB3_CI5_GNT    V_ARB3_CI5_GNT(1U)
23513 
23514 #define S_CI5_DM3_WDATA_VLD    9
23515 #define V_CI5_DM3_WDATA_VLD(x) ((x) << S_CI5_DM3_WDATA_VLD)
23516 #define F_CI5_DM3_WDATA_VLD    V_CI5_DM3_WDATA_VLD(1U)
23517 
23518 #define S_DM3_CI5_RDATA_VLD    8
23519 #define V_DM3_CI5_RDATA_VLD(x) ((x) << S_DM3_CI5_RDATA_VLD)
23520 #define F_DM3_CI5_RDATA_VLD    V_DM3_CI5_RDATA_VLD(1U)
23521 
23522 #define S_CI6_ARB3_REQ    7
23523 #define V_CI6_ARB3_REQ(x) ((x) << S_CI6_ARB3_REQ)
23524 #define F_CI6_ARB3_REQ    V_CI6_ARB3_REQ(1U)
23525 
23526 #define S_ARB3_CI6_GNT    6
23527 #define V_ARB3_CI6_GNT(x) ((x) << S_ARB3_CI6_GNT)
23528 #define F_ARB3_CI6_GNT    V_ARB3_CI6_GNT(1U)
23529 
23530 #define S_CI6_DM3_WDATA_VLD    5
23531 #define V_CI6_DM3_WDATA_VLD(x) ((x) << S_CI6_DM3_WDATA_VLD)
23532 #define F_CI6_DM3_WDATA_VLD    V_CI6_DM3_WDATA_VLD(1U)
23533 
23534 #define S_DM3_CI6_RDATA_VLD    4
23535 #define V_DM3_CI6_RDATA_VLD(x) ((x) << S_DM3_CI6_RDATA_VLD)
23536 #define F_DM3_CI6_RDATA_VLD    V_DM3_CI6_RDATA_VLD(1U)
23537 
23538 #define S_CI7_ARB3_REQ    3
23539 #define V_CI7_ARB3_REQ(x) ((x) << S_CI7_ARB3_REQ)
23540 #define F_CI7_ARB3_REQ    V_CI7_ARB3_REQ(1U)
23541 
23542 #define S_ARB3_CI7_GNT    2
23543 #define V_ARB3_CI7_GNT(x) ((x) << S_ARB3_CI7_GNT)
23544 #define F_ARB3_CI7_GNT    V_ARB3_CI7_GNT(1U)
23545 
23546 #define S_CI7_DM3_WDATA_VLD    1
23547 #define V_CI7_DM3_WDATA_VLD(x) ((x) << S_CI7_DM3_WDATA_VLD)
23548 #define F_CI7_DM3_WDATA_VLD    V_CI7_DM3_WDATA_VLD(1U)
23549 
23550 #define S_DM3_CI7_RDATA_VLD    0
23551 #define V_DM3_CI7_RDATA_VLD(x) ((x) << S_DM3_CI7_RDATA_VLD)
23552 #define F_DM3_CI7_RDATA_VLD    V_DM3_CI7_RDATA_VLD(1U)
23553 
23554 #define A_MA_MA_DEBUG_SIGNATURE_LTL_END 0xa011
23555 #define A_MA_MA_DEBUG_SIGNATURE_BIG_END_INVERSE 0xa012
23556 #define A_MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG1 0xa013
23557 
23558 #define S_CI8_ARB0_REQ    31
23559 #define V_CI8_ARB0_REQ(x) ((x) << S_CI8_ARB0_REQ)
23560 #define F_CI8_ARB0_REQ    V_CI8_ARB0_REQ(1U)
23561 
23562 #define S_ARB0_CI8_GNT    30
23563 #define V_ARB0_CI8_GNT(x) ((x) << S_ARB0_CI8_GNT)
23564 #define F_ARB0_CI8_GNT    V_ARB0_CI8_GNT(1U)
23565 
23566 #define S_CI8_DM0_WDATA_VLD    29
23567 #define V_CI8_DM0_WDATA_VLD(x) ((x) << S_CI8_DM0_WDATA_VLD)
23568 #define F_CI8_DM0_WDATA_VLD    V_CI8_DM0_WDATA_VLD(1U)
23569 
23570 #define S_DM0_CI8_RDATA_VLD    28
23571 #define V_DM0_CI8_RDATA_VLD(x) ((x) << S_DM0_CI8_RDATA_VLD)
23572 #define F_DM0_CI8_RDATA_VLD    V_DM0_CI8_RDATA_VLD(1U)
23573 
23574 #define S_CI9_ARB0_REQ    27
23575 #define V_CI9_ARB0_REQ(x) ((x) << S_CI9_ARB0_REQ)
23576 #define F_CI9_ARB0_REQ    V_CI9_ARB0_REQ(1U)
23577 
23578 #define S_ARB0_CI9_GNT    26
23579 #define V_ARB0_CI9_GNT(x) ((x) << S_ARB0_CI9_GNT)
23580 #define F_ARB0_CI9_GNT    V_ARB0_CI9_GNT(1U)
23581 
23582 #define S_CI9_DM0_WDATA_VLD    25
23583 #define V_CI9_DM0_WDATA_VLD(x) ((x) << S_CI9_DM0_WDATA_VLD)
23584 #define F_CI9_DM0_WDATA_VLD    V_CI9_DM0_WDATA_VLD(1U)
23585 
23586 #define S_DM0_CI9_RDATA_VLD    24
23587 #define V_DM0_CI9_RDATA_VLD(x) ((x) << S_DM0_CI9_RDATA_VLD)
23588 #define F_DM0_CI9_RDATA_VLD    V_DM0_CI9_RDATA_VLD(1U)
23589 
23590 #define S_CI10_ARB0_REQ    23
23591 #define V_CI10_ARB0_REQ(x) ((x) << S_CI10_ARB0_REQ)
23592 #define F_CI10_ARB0_REQ    V_CI10_ARB0_REQ(1U)
23593 
23594 #define S_ARB0_CI10_GNT    22
23595 #define V_ARB0_CI10_GNT(x) ((x) << S_ARB0_CI10_GNT)
23596 #define F_ARB0_CI10_GNT    V_ARB0_CI10_GNT(1U)
23597 
23598 #define S_CI10_DM0_WDATA_VLD    21
23599 #define V_CI10_DM0_WDATA_VLD(x) ((x) << S_CI10_DM0_WDATA_VLD)
23600 #define F_CI10_DM0_WDATA_VLD    V_CI10_DM0_WDATA_VLD(1U)
23601 
23602 #define S_DM0_CI10_RDATA_VLD    20
23603 #define V_DM0_CI10_RDATA_VLD(x) ((x) << S_DM0_CI10_RDATA_VLD)
23604 #define F_DM0_CI10_RDATA_VLD    V_DM0_CI10_RDATA_VLD(1U)
23605 
23606 #define S_CI11_ARB0_REQ    19
23607 #define V_CI11_ARB0_REQ(x) ((x) << S_CI11_ARB0_REQ)
23608 #define F_CI11_ARB0_REQ    V_CI11_ARB0_REQ(1U)
23609 
23610 #define S_ARB0_CI11_GNT    18
23611 #define V_ARB0_CI11_GNT(x) ((x) << S_ARB0_CI11_GNT)
23612 #define F_ARB0_CI11_GNT    V_ARB0_CI11_GNT(1U)
23613 
23614 #define S_CI11_DM0_WDATA_VLD    17
23615 #define V_CI11_DM0_WDATA_VLD(x) ((x) << S_CI11_DM0_WDATA_VLD)
23616 #define F_CI11_DM0_WDATA_VLD    V_CI11_DM0_WDATA_VLD(1U)
23617 
23618 #define S_DM0_CI11_RDATA_VLD    16
23619 #define V_DM0_CI11_RDATA_VLD(x) ((x) << S_DM0_CI11_RDATA_VLD)
23620 #define F_DM0_CI11_RDATA_VLD    V_DM0_CI11_RDATA_VLD(1U)
23621 
23622 #define S_CI12_ARB0_REQ    15
23623 #define V_CI12_ARB0_REQ(x) ((x) << S_CI12_ARB0_REQ)
23624 #define F_CI12_ARB0_REQ    V_CI12_ARB0_REQ(1U)
23625 
23626 #define S_ARB0_CI12_GNT    14
23627 #define V_ARB0_CI12_GNT(x) ((x) << S_ARB0_CI12_GNT)
23628 #define F_ARB0_CI12_GNT    V_ARB0_CI12_GNT(1U)
23629 
23630 #define S_CI12_DM0_WDATA_VLD    13
23631 #define V_CI12_DM0_WDATA_VLD(x) ((x) << S_CI12_DM0_WDATA_VLD)
23632 #define F_CI12_DM0_WDATA_VLD    V_CI12_DM0_WDATA_VLD(1U)
23633 
23634 #define S_DM0_CI12_RDATA_VLD    12
23635 #define V_DM0_CI12_RDATA_VLD(x) ((x) << S_DM0_CI12_RDATA_VLD)
23636 #define F_DM0_CI12_RDATA_VLD    V_DM0_CI12_RDATA_VLD(1U)
23637 
23638 #define A_MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG1 0xa014
23639 
23640 #define S_CI8_ARB1_REQ    31
23641 #define V_CI8_ARB1_REQ(x) ((x) << S_CI8_ARB1_REQ)
23642 #define F_CI8_ARB1_REQ    V_CI8_ARB1_REQ(1U)
23643 
23644 #define S_ARB1_CI8_GNT    30
23645 #define V_ARB1_CI8_GNT(x) ((x) << S_ARB1_CI8_GNT)
23646 #define F_ARB1_CI8_GNT    V_ARB1_CI8_GNT(1U)
23647 
23648 #define S_CI8_DM1_WDATA_VLD    29
23649 #define V_CI8_DM1_WDATA_VLD(x) ((x) << S_CI8_DM1_WDATA_VLD)
23650 #define F_CI8_DM1_WDATA_VLD    V_CI8_DM1_WDATA_VLD(1U)
23651 
23652 #define S_DM1_CI8_RDATA_VLD    28
23653 #define V_DM1_CI8_RDATA_VLD(x) ((x) << S_DM1_CI8_RDATA_VLD)
23654 #define F_DM1_CI8_RDATA_VLD    V_DM1_CI8_RDATA_VLD(1U)
23655 
23656 #define S_CI9_ARB1_REQ    27
23657 #define V_CI9_ARB1_REQ(x) ((x) << S_CI9_ARB1_REQ)
23658 #define F_CI9_ARB1_REQ    V_CI9_ARB1_REQ(1U)
23659 
23660 #define S_ARB1_CI9_GNT    26
23661 #define V_ARB1_CI9_GNT(x) ((x) << S_ARB1_CI9_GNT)
23662 #define F_ARB1_CI9_GNT    V_ARB1_CI9_GNT(1U)
23663 
23664 #define S_CI9_DM1_WDATA_VLD    25
23665 #define V_CI9_DM1_WDATA_VLD(x) ((x) << S_CI9_DM1_WDATA_VLD)
23666 #define F_CI9_DM1_WDATA_VLD    V_CI9_DM1_WDATA_VLD(1U)
23667 
23668 #define S_DM1_CI9_RDATA_VLD    24
23669 #define V_DM1_CI9_RDATA_VLD(x) ((x) << S_DM1_CI9_RDATA_VLD)
23670 #define F_DM1_CI9_RDATA_VLD    V_DM1_CI9_RDATA_VLD(1U)
23671 
23672 #define S_CI10_ARB1_REQ    23
23673 #define V_CI10_ARB1_REQ(x) ((x) << S_CI10_ARB1_REQ)
23674 #define F_CI10_ARB1_REQ    V_CI10_ARB1_REQ(1U)
23675 
23676 #define S_ARB1_CI10_GNT    22
23677 #define V_ARB1_CI10_GNT(x) ((x) << S_ARB1_CI10_GNT)
23678 #define F_ARB1_CI10_GNT    V_ARB1_CI10_GNT(1U)
23679 
23680 #define S_CI10_DM1_WDATA_VLD    21
23681 #define V_CI10_DM1_WDATA_VLD(x) ((x) << S_CI10_DM1_WDATA_VLD)
23682 #define F_CI10_DM1_WDATA_VLD    V_CI10_DM1_WDATA_VLD(1U)
23683 
23684 #define S_DM1_CI10_RDATA_VLD    20
23685 #define V_DM1_CI10_RDATA_VLD(x) ((x) << S_DM1_CI10_RDATA_VLD)
23686 #define F_DM1_CI10_RDATA_VLD    V_DM1_CI10_RDATA_VLD(1U)
23687 
23688 #define S_CI11_ARB1_REQ    19
23689 #define V_CI11_ARB1_REQ(x) ((x) << S_CI11_ARB1_REQ)
23690 #define F_CI11_ARB1_REQ    V_CI11_ARB1_REQ(1U)
23691 
23692 #define S_ARB1_CI11_GNT    18
23693 #define V_ARB1_CI11_GNT(x) ((x) << S_ARB1_CI11_GNT)
23694 #define F_ARB1_CI11_GNT    V_ARB1_CI11_GNT(1U)
23695 
23696 #define S_CI11_DM1_WDATA_VLD    17
23697 #define V_CI11_DM1_WDATA_VLD(x) ((x) << S_CI11_DM1_WDATA_VLD)
23698 #define F_CI11_DM1_WDATA_VLD    V_CI11_DM1_WDATA_VLD(1U)
23699 
23700 #define S_DM1_CI11_RDATA_VLD    16
23701 #define V_DM1_CI11_RDATA_VLD(x) ((x) << S_DM1_CI11_RDATA_VLD)
23702 #define F_DM1_CI11_RDATA_VLD    V_DM1_CI11_RDATA_VLD(1U)
23703 
23704 #define S_CI12_ARB1_REQ    15
23705 #define V_CI12_ARB1_REQ(x) ((x) << S_CI12_ARB1_REQ)
23706 #define F_CI12_ARB1_REQ    V_CI12_ARB1_REQ(1U)
23707 
23708 #define S_ARB1_CI12_GNT    14
23709 #define V_ARB1_CI12_GNT(x) ((x) << S_ARB1_CI12_GNT)
23710 #define F_ARB1_CI12_GNT    V_ARB1_CI12_GNT(1U)
23711 
23712 #define S_CI12_DM1_WDATA_VLD    13
23713 #define V_CI12_DM1_WDATA_VLD(x) ((x) << S_CI12_DM1_WDATA_VLD)
23714 #define F_CI12_DM1_WDATA_VLD    V_CI12_DM1_WDATA_VLD(1U)
23715 
23716 #define S_DM1_CI12_RDATA_VLD    12
23717 #define V_DM1_CI12_RDATA_VLD(x) ((x) << S_DM1_CI12_RDATA_VLD)
23718 #define F_DM1_CI12_RDATA_VLD    V_DM1_CI12_RDATA_VLD(1U)
23719 
23720 #define A_MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG1 0xa015
23721 
23722 #define S_CI8_ARB2_REQ    31
23723 #define V_CI8_ARB2_REQ(x) ((x) << S_CI8_ARB2_REQ)
23724 #define F_CI8_ARB2_REQ    V_CI8_ARB2_REQ(1U)
23725 
23726 #define S_ARB2_CI8_GNT    30
23727 #define V_ARB2_CI8_GNT(x) ((x) << S_ARB2_CI8_GNT)
23728 #define F_ARB2_CI8_GNT    V_ARB2_CI8_GNT(1U)
23729 
23730 #define S_CI8_DM2_WDATA_VLD    29
23731 #define V_CI8_DM2_WDATA_VLD(x) ((x) << S_CI8_DM2_WDATA_VLD)
23732 #define F_CI8_DM2_WDATA_VLD    V_CI8_DM2_WDATA_VLD(1U)
23733 
23734 #define S_DM2_CI8_RDATA_VLD    28
23735 #define V_DM2_CI8_RDATA_VLD(x) ((x) << S_DM2_CI8_RDATA_VLD)
23736 #define F_DM2_CI8_RDATA_VLD    V_DM2_CI8_RDATA_VLD(1U)
23737 
23738 #define S_CI9_ARB2_REQ    27
23739 #define V_CI9_ARB2_REQ(x) ((x) << S_CI9_ARB2_REQ)
23740 #define F_CI9_ARB2_REQ    V_CI9_ARB2_REQ(1U)
23741 
23742 #define S_ARB2_CI9_GNT    26
23743 #define V_ARB2_CI9_GNT(x) ((x) << S_ARB2_CI9_GNT)
23744 #define F_ARB2_CI9_GNT    V_ARB2_CI9_GNT(1U)
23745 
23746 #define S_CI9_DM2_WDATA_VLD    25
23747 #define V_CI9_DM2_WDATA_VLD(x) ((x) << S_CI9_DM2_WDATA_VLD)
23748 #define F_CI9_DM2_WDATA_VLD    V_CI9_DM2_WDATA_VLD(1U)
23749 
23750 #define S_DM2_CI9_RDATA_VLD    24
23751 #define V_DM2_CI9_RDATA_VLD(x) ((x) << S_DM2_CI9_RDATA_VLD)
23752 #define F_DM2_CI9_RDATA_VLD    V_DM2_CI9_RDATA_VLD(1U)
23753 
23754 #define S_CI10_ARB2_REQ    23
23755 #define V_CI10_ARB2_REQ(x) ((x) << S_CI10_ARB2_REQ)
23756 #define F_CI10_ARB2_REQ    V_CI10_ARB2_REQ(1U)
23757 
23758 #define S_ARB2_CI10_GNT    22
23759 #define V_ARB2_CI10_GNT(x) ((x) << S_ARB2_CI10_GNT)
23760 #define F_ARB2_CI10_GNT    V_ARB2_CI10_GNT(1U)
23761 
23762 #define S_CI10_DM2_WDATA_VLD    21
23763 #define V_CI10_DM2_WDATA_VLD(x) ((x) << S_CI10_DM2_WDATA_VLD)
23764 #define F_CI10_DM2_WDATA_VLD    V_CI10_DM2_WDATA_VLD(1U)
23765 
23766 #define S_DM2_CI10_RDATA_VLD    20
23767 #define V_DM2_CI10_RDATA_VLD(x) ((x) << S_DM2_CI10_RDATA_VLD)
23768 #define F_DM2_CI10_RDATA_VLD    V_DM2_CI10_RDATA_VLD(1U)
23769 
23770 #define S_CI11_ARB2_REQ    19
23771 #define V_CI11_ARB2_REQ(x) ((x) << S_CI11_ARB2_REQ)
23772 #define F_CI11_ARB2_REQ    V_CI11_ARB2_REQ(1U)
23773 
23774 #define S_ARB2_CI11_GNT    18
23775 #define V_ARB2_CI11_GNT(x) ((x) << S_ARB2_CI11_GNT)
23776 #define F_ARB2_CI11_GNT    V_ARB2_CI11_GNT(1U)
23777 
23778 #define S_CI11_DM2_WDATA_VLD    17
23779 #define V_CI11_DM2_WDATA_VLD(x) ((x) << S_CI11_DM2_WDATA_VLD)
23780 #define F_CI11_DM2_WDATA_VLD    V_CI11_DM2_WDATA_VLD(1U)
23781 
23782 #define S_DM2_CI11_RDATA_VLD    16
23783 #define V_DM2_CI11_RDATA_VLD(x) ((x) << S_DM2_CI11_RDATA_VLD)
23784 #define F_DM2_CI11_RDATA_VLD    V_DM2_CI11_RDATA_VLD(1U)
23785 
23786 #define S_CI12_ARB2_REQ    15
23787 #define V_CI12_ARB2_REQ(x) ((x) << S_CI12_ARB2_REQ)
23788 #define F_CI12_ARB2_REQ    V_CI12_ARB2_REQ(1U)
23789 
23790 #define S_ARB2_CI12_GNT    14
23791 #define V_ARB2_CI12_GNT(x) ((x) << S_ARB2_CI12_GNT)
23792 #define F_ARB2_CI12_GNT    V_ARB2_CI12_GNT(1U)
23793 
23794 #define S_CI12_DM2_WDATA_VLD    13
23795 #define V_CI12_DM2_WDATA_VLD(x) ((x) << S_CI12_DM2_WDATA_VLD)
23796 #define F_CI12_DM2_WDATA_VLD    V_CI12_DM2_WDATA_VLD(1U)
23797 
23798 #define S_DM2_CI12_RDATA_VLD    12
23799 #define V_DM2_CI12_RDATA_VLD(x) ((x) << S_DM2_CI12_RDATA_VLD)
23800 #define F_DM2_CI12_RDATA_VLD    V_DM2_CI12_RDATA_VLD(1U)
23801 
23802 #define A_MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG1 0xa016
23803 
23804 #define S_CI8_ARB3_REQ    31
23805 #define V_CI8_ARB3_REQ(x) ((x) << S_CI8_ARB3_REQ)
23806 #define F_CI8_ARB3_REQ    V_CI8_ARB3_REQ(1U)
23807 
23808 #define S_ARB3_CI8_GNT    30
23809 #define V_ARB3_CI8_GNT(x) ((x) << S_ARB3_CI8_GNT)
23810 #define F_ARB3_CI8_GNT    V_ARB3_CI8_GNT(1U)
23811 
23812 #define S_CI8_DM3_WDATA_VLD    29
23813 #define V_CI8_DM3_WDATA_VLD(x) ((x) << S_CI8_DM3_WDATA_VLD)
23814 #define F_CI8_DM3_WDATA_VLD    V_CI8_DM3_WDATA_VLD(1U)
23815 
23816 #define S_DM3_CI8_RDATA_VLD    28
23817 #define V_DM3_CI8_RDATA_VLD(x) ((x) << S_DM3_CI8_RDATA_VLD)
23818 #define F_DM3_CI8_RDATA_VLD    V_DM3_CI8_RDATA_VLD(1U)
23819 
23820 #define S_CI9_ARB3_REQ    27
23821 #define V_CI9_ARB3_REQ(x) ((x) << S_CI9_ARB3_REQ)
23822 #define F_CI9_ARB3_REQ    V_CI9_ARB3_REQ(1U)
23823 
23824 #define S_ARB3_CI9_GNT    26
23825 #define V_ARB3_CI9_GNT(x) ((x) << S_ARB3_CI9_GNT)
23826 #define F_ARB3_CI9_GNT    V_ARB3_CI9_GNT(1U)
23827 
23828 #define S_CI9_DM3_WDATA_VLD    25
23829 #define V_CI9_DM3_WDATA_VLD(x) ((x) << S_CI9_DM3_WDATA_VLD)
23830 #define F_CI9_DM3_WDATA_VLD    V_CI9_DM3_WDATA_VLD(1U)
23831 
23832 #define S_DM3_CI9_RDATA_VLD    24
23833 #define V_DM3_CI9_RDATA_VLD(x) ((x) << S_DM3_CI9_RDATA_VLD)
23834 #define F_DM3_CI9_RDATA_VLD    V_DM3_CI9_RDATA_VLD(1U)
23835 
23836 #define S_CI10_ARB3_REQ    23
23837 #define V_CI10_ARB3_REQ(x) ((x) << S_CI10_ARB3_REQ)
23838 #define F_CI10_ARB3_REQ    V_CI10_ARB3_REQ(1U)
23839 
23840 #define S_ARB3_CI10_GNT    22
23841 #define V_ARB3_CI10_GNT(x) ((x) << S_ARB3_CI10_GNT)
23842 #define F_ARB3_CI10_GNT    V_ARB3_CI10_GNT(1U)
23843 
23844 #define S_CI10_DM3_WDATA_VLD    21
23845 #define V_CI10_DM3_WDATA_VLD(x) ((x) << S_CI10_DM3_WDATA_VLD)
23846 #define F_CI10_DM3_WDATA_VLD    V_CI10_DM3_WDATA_VLD(1U)
23847 
23848 #define S_DM3_CI10_RDATA_VLD    20
23849 #define V_DM3_CI10_RDATA_VLD(x) ((x) << S_DM3_CI10_RDATA_VLD)
23850 #define F_DM3_CI10_RDATA_VLD    V_DM3_CI10_RDATA_VLD(1U)
23851 
23852 #define S_CI11_ARB3_REQ    19
23853 #define V_CI11_ARB3_REQ(x) ((x) << S_CI11_ARB3_REQ)
23854 #define F_CI11_ARB3_REQ    V_CI11_ARB3_REQ(1U)
23855 
23856 #define S_ARB3_CI11_GNT    18
23857 #define V_ARB3_CI11_GNT(x) ((x) << S_ARB3_CI11_GNT)
23858 #define F_ARB3_CI11_GNT    V_ARB3_CI11_GNT(1U)
23859 
23860 #define S_CI11_DM3_WDATA_VLD    17
23861 #define V_CI11_DM3_WDATA_VLD(x) ((x) << S_CI11_DM3_WDATA_VLD)
23862 #define F_CI11_DM3_WDATA_VLD    V_CI11_DM3_WDATA_VLD(1U)
23863 
23864 #define S_DM3_CI11_RDATA_VLD    16
23865 #define V_DM3_CI11_RDATA_VLD(x) ((x) << S_DM3_CI11_RDATA_VLD)
23866 #define F_DM3_CI11_RDATA_VLD    V_DM3_CI11_RDATA_VLD(1U)
23867 
23868 #define S_CI12_ARB3_REQ    15
23869 #define V_CI12_ARB3_REQ(x) ((x) << S_CI12_ARB3_REQ)
23870 #define F_CI12_ARB3_REQ    V_CI12_ARB3_REQ(1U)
23871 
23872 #define S_ARB3_CI12_GNT    14
23873 #define V_ARB3_CI12_GNT(x) ((x) << S_ARB3_CI12_GNT)
23874 #define F_ARB3_CI12_GNT    V_ARB3_CI12_GNT(1U)
23875 
23876 #define S_CI12_DM3_WDATA_VLD    13
23877 #define V_CI12_DM3_WDATA_VLD(x) ((x) << S_CI12_DM3_WDATA_VLD)
23878 #define F_CI12_DM3_WDATA_VLD    V_CI12_DM3_WDATA_VLD(1U)
23879 
23880 #define S_DM3_CI12_RDATA_VLD    12
23881 #define V_DM3_CI12_RDATA_VLD(x) ((x) << S_DM3_CI12_RDATA_VLD)
23882 #define F_DM3_CI12_RDATA_VLD    V_DM3_CI12_RDATA_VLD(1U)
23883 
23884 #define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0 0xa400
23885 
23886 #define S_CMD_IN_FIFO_CNT0    30
23887 #define M_CMD_IN_FIFO_CNT0    0x3U
23888 #define V_CMD_IN_FIFO_CNT0(x) ((x) << S_CMD_IN_FIFO_CNT0)
23889 #define G_CMD_IN_FIFO_CNT0(x) (((x) >> S_CMD_IN_FIFO_CNT0) & M_CMD_IN_FIFO_CNT0)
23890 
23891 #define S_CMD_SPLIT_FIFO_CNT0    28
23892 #define M_CMD_SPLIT_FIFO_CNT0    0x3U
23893 #define V_CMD_SPLIT_FIFO_CNT0(x) ((x) << S_CMD_SPLIT_FIFO_CNT0)
23894 #define G_CMD_SPLIT_FIFO_CNT0(x) (((x) >> S_CMD_SPLIT_FIFO_CNT0) & M_CMD_SPLIT_FIFO_CNT0)
23895 
23896 #define S_CMD_THROTTLE_FIFO_CNT0    22
23897 #define M_CMD_THROTTLE_FIFO_CNT0    0x3fU
23898 #define V_CMD_THROTTLE_FIFO_CNT0(x) ((x) << S_CMD_THROTTLE_FIFO_CNT0)
23899 #define G_CMD_THROTTLE_FIFO_CNT0(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT0) & M_CMD_THROTTLE_FIFO_CNT0)
23900 
23901 #define S_RD_CHNL_FIFO_CNT0    15
23902 #define M_RD_CHNL_FIFO_CNT0    0x7fU
23903 #define V_RD_CHNL_FIFO_CNT0(x) ((x) << S_RD_CHNL_FIFO_CNT0)
23904 #define G_RD_CHNL_FIFO_CNT0(x) (((x) >> S_RD_CHNL_FIFO_CNT0) & M_RD_CHNL_FIFO_CNT0)
23905 
23906 #define S_RD_DATA_EXT_FIFO_CNT0    13
23907 #define M_RD_DATA_EXT_FIFO_CNT0    0x3U
23908 #define V_RD_DATA_EXT_FIFO_CNT0(x) ((x) << S_RD_DATA_EXT_FIFO_CNT0)
23909 #define G_RD_DATA_EXT_FIFO_CNT0(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT0) & M_RD_DATA_EXT_FIFO_CNT0)
23910 
23911 #define S_RD_DATA_512B_FIFO_CNT0    5
23912 #define M_RD_DATA_512B_FIFO_CNT0    0xffU
23913 #define V_RD_DATA_512B_FIFO_CNT0(x) ((x) << S_RD_DATA_512B_FIFO_CNT0)
23914 #define G_RD_DATA_512B_FIFO_CNT0(x) (((x) >> S_RD_DATA_512B_FIFO_CNT0) & M_RD_DATA_512B_FIFO_CNT0)
23915 
23916 #define S_RD_REQ_TAG_FIFO_CNT0    1
23917 #define M_RD_REQ_TAG_FIFO_CNT0    0xfU
23918 #define V_RD_REQ_TAG_FIFO_CNT0(x) ((x) << S_RD_REQ_TAG_FIFO_CNT0)
23919 #define G_RD_REQ_TAG_FIFO_CNT0(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT0) & M_RD_REQ_TAG_FIFO_CNT0)
23920 
23921 #define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0 0xa401
23922 
23923 #define S_CMD_IN_FIFO_CNT1    30
23924 #define M_CMD_IN_FIFO_CNT1    0x3U
23925 #define V_CMD_IN_FIFO_CNT1(x) ((x) << S_CMD_IN_FIFO_CNT1)
23926 #define G_CMD_IN_FIFO_CNT1(x) (((x) >> S_CMD_IN_FIFO_CNT1) & M_CMD_IN_FIFO_CNT1)
23927 
23928 #define S_CMD_SPLIT_FIFO_CNT1    28
23929 #define M_CMD_SPLIT_FIFO_CNT1    0x3U
23930 #define V_CMD_SPLIT_FIFO_CNT1(x) ((x) << S_CMD_SPLIT_FIFO_CNT1)
23931 #define G_CMD_SPLIT_FIFO_CNT1(x) (((x) >> S_CMD_SPLIT_FIFO_CNT1) & M_CMD_SPLIT_FIFO_CNT1)
23932 
23933 #define S_CMD_THROTTLE_FIFO_CNT1    22
23934 #define M_CMD_THROTTLE_FIFO_CNT1    0x3fU
23935 #define V_CMD_THROTTLE_FIFO_CNT1(x) ((x) << S_CMD_THROTTLE_FIFO_CNT1)
23936 #define G_CMD_THROTTLE_FIFO_CNT1(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT1) & M_CMD_THROTTLE_FIFO_CNT1)
23937 
23938 #define S_RD_CHNL_FIFO_CNT1    15
23939 #define M_RD_CHNL_FIFO_CNT1    0x7fU
23940 #define V_RD_CHNL_FIFO_CNT1(x) ((x) << S_RD_CHNL_FIFO_CNT1)
23941 #define G_RD_CHNL_FIFO_CNT1(x) (((x) >> S_RD_CHNL_FIFO_CNT1) & M_RD_CHNL_FIFO_CNT1)
23942 
23943 #define S_RD_DATA_EXT_FIFO_CNT1    13
23944 #define M_RD_DATA_EXT_FIFO_CNT1    0x3U
23945 #define V_RD_DATA_EXT_FIFO_CNT1(x) ((x) << S_RD_DATA_EXT_FIFO_CNT1)
23946 #define G_RD_DATA_EXT_FIFO_CNT1(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT1) & M_RD_DATA_EXT_FIFO_CNT1)
23947 
23948 #define S_RD_DATA_512B_FIFO_CNT1    5
23949 #define M_RD_DATA_512B_FIFO_CNT1    0xffU
23950 #define V_RD_DATA_512B_FIFO_CNT1(x) ((x) << S_RD_DATA_512B_FIFO_CNT1)
23951 #define G_RD_DATA_512B_FIFO_CNT1(x) (((x) >> S_RD_DATA_512B_FIFO_CNT1) & M_RD_DATA_512B_FIFO_CNT1)
23952 
23953 #define S_RD_REQ_TAG_FIFO_CNT1    1
23954 #define M_RD_REQ_TAG_FIFO_CNT1    0xfU
23955 #define V_RD_REQ_TAG_FIFO_CNT1(x) ((x) << S_RD_REQ_TAG_FIFO_CNT1)
23956 #define G_RD_REQ_TAG_FIFO_CNT1(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT1) & M_RD_REQ_TAG_FIFO_CNT1)
23957 
23958 #define A_MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG0 0xa402
23959 
23960 #define S_CMD_IN_FIFO_CNT2    30
23961 #define M_CMD_IN_FIFO_CNT2    0x3U
23962 #define V_CMD_IN_FIFO_CNT2(x) ((x) << S_CMD_IN_FIFO_CNT2)
23963 #define G_CMD_IN_FIFO_CNT2(x) (((x) >> S_CMD_IN_FIFO_CNT2) & M_CMD_IN_FIFO_CNT2)
23964 
23965 #define S_CMD_SPLIT_FIFO_CNT2    28
23966 #define M_CMD_SPLIT_FIFO_CNT2    0x3U
23967 #define V_CMD_SPLIT_FIFO_CNT2(x) ((x) << S_CMD_SPLIT_FIFO_CNT2)
23968 #define G_CMD_SPLIT_FIFO_CNT2(x) (((x) >> S_CMD_SPLIT_FIFO_CNT2) & M_CMD_SPLIT_FIFO_CNT2)
23969 
23970 #define S_CMD_THROTTLE_FIFO_CNT2    22
23971 #define M_CMD_THROTTLE_FIFO_CNT2    0x3fU
23972 #define V_CMD_THROTTLE_FIFO_CNT2(x) ((x) << S_CMD_THROTTLE_FIFO_CNT2)
23973 #define G_CMD_THROTTLE_FIFO_CNT2(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT2) & M_CMD_THROTTLE_FIFO_CNT2)
23974 
23975 #define S_RD_CHNL_FIFO_CNT2    15
23976 #define M_RD_CHNL_FIFO_CNT2    0x7fU
23977 #define V_RD_CHNL_FIFO_CNT2(x) ((x) << S_RD_CHNL_FIFO_CNT2)
23978 #define G_RD_CHNL_FIFO_CNT2(x) (((x) >> S_RD_CHNL_FIFO_CNT2) & M_RD_CHNL_FIFO_CNT2)
23979 
23980 #define S_RD_DATA_EXT_FIFO_CNT2    13
23981 #define M_RD_DATA_EXT_FIFO_CNT2    0x3U
23982 #define V_RD_DATA_EXT_FIFO_CNT2(x) ((x) << S_RD_DATA_EXT_FIFO_CNT2)
23983 #define G_RD_DATA_EXT_FIFO_CNT2(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT2) & M_RD_DATA_EXT_FIFO_CNT2)
23984 
23985 #define S_RD_DATA_512B_FIFO_CNT2    5
23986 #define M_RD_DATA_512B_FIFO_CNT2    0xffU
23987 #define V_RD_DATA_512B_FIFO_CNT2(x) ((x) << S_RD_DATA_512B_FIFO_CNT2)
23988 #define G_RD_DATA_512B_FIFO_CNT2(x) (((x) >> S_RD_DATA_512B_FIFO_CNT2) & M_RD_DATA_512B_FIFO_CNT2)
23989 
23990 #define S_RD_REQ_TAG_FIFO_CNT2    1
23991 #define M_RD_REQ_TAG_FIFO_CNT2    0xfU
23992 #define V_RD_REQ_TAG_FIFO_CNT2(x) ((x) << S_RD_REQ_TAG_FIFO_CNT2)
23993 #define G_RD_REQ_TAG_FIFO_CNT2(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT2) & M_RD_REQ_TAG_FIFO_CNT2)
23994 
23995 #define A_MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa403
23996 
23997 #define S_CMD_IN_FIFO_CNT3    30
23998 #define M_CMD_IN_FIFO_CNT3    0x3U
23999 #define V_CMD_IN_FIFO_CNT3(x) ((x) << S_CMD_IN_FIFO_CNT3)
24000 #define G_CMD_IN_FIFO_CNT3(x) (((x) >> S_CMD_IN_FIFO_CNT3) & M_CMD_IN_FIFO_CNT3)
24001 
24002 #define S_CMD_SPLIT_FIFO_CNT3    28
24003 #define M_CMD_SPLIT_FIFO_CNT3    0x3U
24004 #define V_CMD_SPLIT_FIFO_CNT3(x) ((x) << S_CMD_SPLIT_FIFO_CNT3)
24005 #define G_CMD_SPLIT_FIFO_CNT3(x) (((x) >> S_CMD_SPLIT_FIFO_CNT3) & M_CMD_SPLIT_FIFO_CNT3)
24006 
24007 #define S_CMD_THROTTLE_FIFO_CNT3    22
24008 #define M_CMD_THROTTLE_FIFO_CNT3    0x3fU
24009 #define V_CMD_THROTTLE_FIFO_CNT3(x) ((x) << S_CMD_THROTTLE_FIFO_CNT3)
24010 #define G_CMD_THROTTLE_FIFO_CNT3(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT3) & M_CMD_THROTTLE_FIFO_CNT3)
24011 
24012 #define S_RD_CHNL_FIFO_CNT3    15
24013 #define M_RD_CHNL_FIFO_CNT3    0x7fU
24014 #define V_RD_CHNL_FIFO_CNT3(x) ((x) << S_RD_CHNL_FIFO_CNT3)
24015 #define G_RD_CHNL_FIFO_CNT3(x) (((x) >> S_RD_CHNL_FIFO_CNT3) & M_RD_CHNL_FIFO_CNT3)
24016 
24017 #define S_RD_DATA_EXT_FIFO_CNT3    13
24018 #define M_RD_DATA_EXT_FIFO_CNT3    0x3U
24019 #define V_RD_DATA_EXT_FIFO_CNT3(x) ((x) << S_RD_DATA_EXT_FIFO_CNT3)
24020 #define G_RD_DATA_EXT_FIFO_CNT3(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT3) & M_RD_DATA_EXT_FIFO_CNT3)
24021 
24022 #define S_RD_DATA_512B_FIFO_CNT3    5
24023 #define M_RD_DATA_512B_FIFO_CNT3    0xffU
24024 #define V_RD_DATA_512B_FIFO_CNT3(x) ((x) << S_RD_DATA_512B_FIFO_CNT3)
24025 #define G_RD_DATA_512B_FIFO_CNT3(x) (((x) >> S_RD_DATA_512B_FIFO_CNT3) & M_RD_DATA_512B_FIFO_CNT3)
24026 
24027 #define S_RD_REQ_TAG_FIFO_CNT3    1
24028 #define M_RD_REQ_TAG_FIFO_CNT3    0xfU
24029 #define V_RD_REQ_TAG_FIFO_CNT3(x) ((x) << S_RD_REQ_TAG_FIFO_CNT3)
24030 #define G_RD_REQ_TAG_FIFO_CNT3(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT3) & M_RD_REQ_TAG_FIFO_CNT3)
24031 
24032 #define A_MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa404
24033 
24034 #define S_CMD_IN_FIFO_CNT4    30
24035 #define M_CMD_IN_FIFO_CNT4    0x3U
24036 #define V_CMD_IN_FIFO_CNT4(x) ((x) << S_CMD_IN_FIFO_CNT4)
24037 #define G_CMD_IN_FIFO_CNT4(x) (((x) >> S_CMD_IN_FIFO_CNT4) & M_CMD_IN_FIFO_CNT4)
24038 
24039 #define S_CMD_SPLIT_FIFO_CNT4    28
24040 #define M_CMD_SPLIT_FIFO_CNT4    0x3U
24041 #define V_CMD_SPLIT_FIFO_CNT4(x) ((x) << S_CMD_SPLIT_FIFO_CNT4)
24042 #define G_CMD_SPLIT_FIFO_CNT4(x) (((x) >> S_CMD_SPLIT_FIFO_CNT4) & M_CMD_SPLIT_FIFO_CNT4)
24043 
24044 #define S_CMD_THROTTLE_FIFO_CNT4    22
24045 #define M_CMD_THROTTLE_FIFO_CNT4    0x3fU
24046 #define V_CMD_THROTTLE_FIFO_CNT4(x) ((x) << S_CMD_THROTTLE_FIFO_CNT4)
24047 #define G_CMD_THROTTLE_FIFO_CNT4(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT4) & M_CMD_THROTTLE_FIFO_CNT4)
24048 
24049 #define S_RD_CHNL_FIFO_CNT4    15
24050 #define M_RD_CHNL_FIFO_CNT4    0x7fU
24051 #define V_RD_CHNL_FIFO_CNT4(x) ((x) << S_RD_CHNL_FIFO_CNT4)
24052 #define G_RD_CHNL_FIFO_CNT4(x) (((x) >> S_RD_CHNL_FIFO_CNT4) & M_RD_CHNL_FIFO_CNT4)
24053 
24054 #define S_RD_DATA_EXT_FIFO_CNT4    13
24055 #define M_RD_DATA_EXT_FIFO_CNT4    0x3U
24056 #define V_RD_DATA_EXT_FIFO_CNT4(x) ((x) << S_RD_DATA_EXT_FIFO_CNT4)
24057 #define G_RD_DATA_EXT_FIFO_CNT4(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT4) & M_RD_DATA_EXT_FIFO_CNT4)
24058 
24059 #define S_RD_DATA_512B_FIFO_CNT4    5
24060 #define M_RD_DATA_512B_FIFO_CNT4    0xffU
24061 #define V_RD_DATA_512B_FIFO_CNT4(x) ((x) << S_RD_DATA_512B_FIFO_CNT4)
24062 #define G_RD_DATA_512B_FIFO_CNT4(x) (((x) >> S_RD_DATA_512B_FIFO_CNT4) & M_RD_DATA_512B_FIFO_CNT4)
24063 
24064 #define S_RD_REQ_TAG_FIFO_CNT4    1
24065 #define M_RD_REQ_TAG_FIFO_CNT4    0xfU
24066 #define V_RD_REQ_TAG_FIFO_CNT4(x) ((x) << S_RD_REQ_TAG_FIFO_CNT4)
24067 #define G_RD_REQ_TAG_FIFO_CNT4(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT4) & M_RD_REQ_TAG_FIFO_CNT4)
24068 
24069 #define A_MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0 0xa405
24070 
24071 #define S_CMD_IN_FIFO_CNT5    30
24072 #define M_CMD_IN_FIFO_CNT5    0x3U
24073 #define V_CMD_IN_FIFO_CNT5(x) ((x) << S_CMD_IN_FIFO_CNT5)
24074 #define G_CMD_IN_FIFO_CNT5(x) (((x) >> S_CMD_IN_FIFO_CNT5) & M_CMD_IN_FIFO_CNT5)
24075 
24076 #define S_CMD_SPLIT_FIFO_CNT5    28
24077 #define M_CMD_SPLIT_FIFO_CNT5    0x3U
24078 #define V_CMD_SPLIT_FIFO_CNT5(x) ((x) << S_CMD_SPLIT_FIFO_CNT5)
24079 #define G_CMD_SPLIT_FIFO_CNT5(x) (((x) >> S_CMD_SPLIT_FIFO_CNT5) & M_CMD_SPLIT_FIFO_CNT5)
24080 
24081 #define S_CMD_THROTTLE_FIFO_CNT5    22
24082 #define M_CMD_THROTTLE_FIFO_CNT5    0x3fU
24083 #define V_CMD_THROTTLE_FIFO_CNT5(x) ((x) << S_CMD_THROTTLE_FIFO_CNT5)
24084 #define G_CMD_THROTTLE_FIFO_CNT5(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT5) & M_CMD_THROTTLE_FIFO_CNT5)
24085 
24086 #define S_RD_CHNL_FIFO_CNT5    15
24087 #define M_RD_CHNL_FIFO_CNT5    0x7fU
24088 #define V_RD_CHNL_FIFO_CNT5(x) ((x) << S_RD_CHNL_FIFO_CNT5)
24089 #define G_RD_CHNL_FIFO_CNT5(x) (((x) >> S_RD_CHNL_FIFO_CNT5) & M_RD_CHNL_FIFO_CNT5)
24090 
24091 #define S_RD_DATA_EXT_FIFO_CNT5    13
24092 #define M_RD_DATA_EXT_FIFO_CNT5    0x3U
24093 #define V_RD_DATA_EXT_FIFO_CNT5(x) ((x) << S_RD_DATA_EXT_FIFO_CNT5)
24094 #define G_RD_DATA_EXT_FIFO_CNT5(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT5) & M_RD_DATA_EXT_FIFO_CNT5)
24095 
24096 #define S_RD_DATA_512B_FIFO_CNT5    5
24097 #define M_RD_DATA_512B_FIFO_CNT5    0xffU
24098 #define V_RD_DATA_512B_FIFO_CNT5(x) ((x) << S_RD_DATA_512B_FIFO_CNT5)
24099 #define G_RD_DATA_512B_FIFO_CNT5(x) (((x) >> S_RD_DATA_512B_FIFO_CNT5) & M_RD_DATA_512B_FIFO_CNT5)
24100 
24101 #define S_RD_REQ_TAG_FIFO_CNT5    1
24102 #define M_RD_REQ_TAG_FIFO_CNT5    0xfU
24103 #define V_RD_REQ_TAG_FIFO_CNT5(x) ((x) << S_RD_REQ_TAG_FIFO_CNT5)
24104 #define G_RD_REQ_TAG_FIFO_CNT5(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT5) & M_RD_REQ_TAG_FIFO_CNT5)
24105 
24106 #define A_MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0 0xa406
24107 
24108 #define S_CMD_IN_FIFO_CNT6    30
24109 #define M_CMD_IN_FIFO_CNT6    0x3U
24110 #define V_CMD_IN_FIFO_CNT6(x) ((x) << S_CMD_IN_FIFO_CNT6)
24111 #define G_CMD_IN_FIFO_CNT6(x) (((x) >> S_CMD_IN_FIFO_CNT6) & M_CMD_IN_FIFO_CNT6)
24112 
24113 #define S_CMD_SPLIT_FIFO_CNT6    28
24114 #define M_CMD_SPLIT_FIFO_CNT6    0x3U
24115 #define V_CMD_SPLIT_FIFO_CNT6(x) ((x) << S_CMD_SPLIT_FIFO_CNT6)
24116 #define G_CMD_SPLIT_FIFO_CNT6(x) (((x) >> S_CMD_SPLIT_FIFO_CNT6) & M_CMD_SPLIT_FIFO_CNT6)
24117 
24118 #define S_CMD_THROTTLE_FIFO_CNT6    22
24119 #define M_CMD_THROTTLE_FIFO_CNT6    0x3fU
24120 #define V_CMD_THROTTLE_FIFO_CNT6(x) ((x) << S_CMD_THROTTLE_FIFO_CNT6)
24121 #define G_CMD_THROTTLE_FIFO_CNT6(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT6) & M_CMD_THROTTLE_FIFO_CNT6)
24122 
24123 #define S_RD_CHNL_FIFO_CNT6    15
24124 #define M_RD_CHNL_FIFO_CNT6    0x7fU
24125 #define V_RD_CHNL_FIFO_CNT6(x) ((x) << S_RD_CHNL_FIFO_CNT6)
24126 #define G_RD_CHNL_FIFO_CNT6(x) (((x) >> S_RD_CHNL_FIFO_CNT6) & M_RD_CHNL_FIFO_CNT6)
24127 
24128 #define S_RD_DATA_EXT_FIFO_CNT6    13
24129 #define M_RD_DATA_EXT_FIFO_CNT6    0x3U
24130 #define V_RD_DATA_EXT_FIFO_CNT6(x) ((x) << S_RD_DATA_EXT_FIFO_CNT6)
24131 #define G_RD_DATA_EXT_FIFO_CNT6(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT6) & M_RD_DATA_EXT_FIFO_CNT6)
24132 
24133 #define S_RD_DATA_512B_FIFO_CNT6    5
24134 #define M_RD_DATA_512B_FIFO_CNT6    0xffU
24135 #define V_RD_DATA_512B_FIFO_CNT6(x) ((x) << S_RD_DATA_512B_FIFO_CNT6)
24136 #define G_RD_DATA_512B_FIFO_CNT6(x) (((x) >> S_RD_DATA_512B_FIFO_CNT6) & M_RD_DATA_512B_FIFO_CNT6)
24137 
24138 #define S_RD_REQ_TAG_FIFO_CNT6    1
24139 #define M_RD_REQ_TAG_FIFO_CNT6    0xfU
24140 #define V_RD_REQ_TAG_FIFO_CNT6(x) ((x) << S_RD_REQ_TAG_FIFO_CNT6)
24141 #define G_RD_REQ_TAG_FIFO_CNT6(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT6) & M_RD_REQ_TAG_FIFO_CNT6)
24142 
24143 #define A_MA_LE_CLIENT_INTERFACE_INTERNAL_REG0 0xa407
24144 
24145 #define S_CMD_IN_FIFO_CNT7    30
24146 #define M_CMD_IN_FIFO_CNT7    0x3U
24147 #define V_CMD_IN_FIFO_CNT7(x) ((x) << S_CMD_IN_FIFO_CNT7)
24148 #define G_CMD_IN_FIFO_CNT7(x) (((x) >> S_CMD_IN_FIFO_CNT7) & M_CMD_IN_FIFO_CNT7)
24149 
24150 #define S_CMD_SPLIT_FIFO_CNT7    28
24151 #define M_CMD_SPLIT_FIFO_CNT7    0x3U
24152 #define V_CMD_SPLIT_FIFO_CNT7(x) ((x) << S_CMD_SPLIT_FIFO_CNT7)
24153 #define G_CMD_SPLIT_FIFO_CNT7(x) (((x) >> S_CMD_SPLIT_FIFO_CNT7) & M_CMD_SPLIT_FIFO_CNT7)
24154 
24155 #define S_CMD_THROTTLE_FIFO_CNT7    22
24156 #define M_CMD_THROTTLE_FIFO_CNT7    0x3fU
24157 #define V_CMD_THROTTLE_FIFO_CNT7(x) ((x) << S_CMD_THROTTLE_FIFO_CNT7)
24158 #define G_CMD_THROTTLE_FIFO_CNT7(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT7) & M_CMD_THROTTLE_FIFO_CNT7)
24159 
24160 #define S_RD_CHNL_FIFO_CNT7    15
24161 #define M_RD_CHNL_FIFO_CNT7    0x7fU
24162 #define V_RD_CHNL_FIFO_CNT7(x) ((x) << S_RD_CHNL_FIFO_CNT7)
24163 #define G_RD_CHNL_FIFO_CNT7(x) (((x) >> S_RD_CHNL_FIFO_CNT7) & M_RD_CHNL_FIFO_CNT7)
24164 
24165 #define S_RD_DATA_EXT_FIFO_CNT7    13
24166 #define M_RD_DATA_EXT_FIFO_CNT7    0x3U
24167 #define V_RD_DATA_EXT_FIFO_CNT7(x) ((x) << S_RD_DATA_EXT_FIFO_CNT7)
24168 #define G_RD_DATA_EXT_FIFO_CNT7(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT7) & M_RD_DATA_EXT_FIFO_CNT7)
24169 
24170 #define S_RD_DATA_512B_FIFO_CNT7    5
24171 #define M_RD_DATA_512B_FIFO_CNT7    0xffU
24172 #define V_RD_DATA_512B_FIFO_CNT7(x) ((x) << S_RD_DATA_512B_FIFO_CNT7)
24173 #define G_RD_DATA_512B_FIFO_CNT7(x) (((x) >> S_RD_DATA_512B_FIFO_CNT7) & M_RD_DATA_512B_FIFO_CNT7)
24174 
24175 #define S_RD_REQ_TAG_FIFO_CNT7    1
24176 #define M_RD_REQ_TAG_FIFO_CNT7    0xfU
24177 #define V_RD_REQ_TAG_FIFO_CNT7(x) ((x) << S_RD_REQ_TAG_FIFO_CNT7)
24178 #define G_RD_REQ_TAG_FIFO_CNT7(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT7) & M_RD_REQ_TAG_FIFO_CNT7)
24179 
24180 #define A_MA_CIM_CLIENT_INTERFACE_INTERNAL_REG0 0xa408
24181 
24182 #define S_CMD_IN_FIFO_CNT8    30
24183 #define M_CMD_IN_FIFO_CNT8    0x3U
24184 #define V_CMD_IN_FIFO_CNT8(x) ((x) << S_CMD_IN_FIFO_CNT8)
24185 #define G_CMD_IN_FIFO_CNT8(x) (((x) >> S_CMD_IN_FIFO_CNT8) & M_CMD_IN_FIFO_CNT8)
24186 
24187 #define S_CMD_SPLIT_FIFO_CNT8    28
24188 #define M_CMD_SPLIT_FIFO_CNT8    0x3U
24189 #define V_CMD_SPLIT_FIFO_CNT8(x) ((x) << S_CMD_SPLIT_FIFO_CNT8)
24190 #define G_CMD_SPLIT_FIFO_CNT8(x) (((x) >> S_CMD_SPLIT_FIFO_CNT8) & M_CMD_SPLIT_FIFO_CNT8)
24191 
24192 #define S_CMD_THROTTLE_FIFO_CNT8    22
24193 #define M_CMD_THROTTLE_FIFO_CNT8    0x3fU
24194 #define V_CMD_THROTTLE_FIFO_CNT8(x) ((x) << S_CMD_THROTTLE_FIFO_CNT8)
24195 #define G_CMD_THROTTLE_FIFO_CNT8(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT8) & M_CMD_THROTTLE_FIFO_CNT8)
24196 
24197 #define S_RD_CHNL_FIFO_CNT8    15
24198 #define M_RD_CHNL_FIFO_CNT8    0x7fU
24199 #define V_RD_CHNL_FIFO_CNT8(x) ((x) << S_RD_CHNL_FIFO_CNT8)
24200 #define G_RD_CHNL_FIFO_CNT8(x) (((x) >> S_RD_CHNL_FIFO_CNT8) & M_RD_CHNL_FIFO_CNT8)
24201 
24202 #define S_RD_DATA_EXT_FIFO_CNT8    13
24203 #define M_RD_DATA_EXT_FIFO_CNT8    0x3U
24204 #define V_RD_DATA_EXT_FIFO_CNT8(x) ((x) << S_RD_DATA_EXT_FIFO_CNT8)
24205 #define G_RD_DATA_EXT_FIFO_CNT8(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT8) & M_RD_DATA_EXT_FIFO_CNT8)
24206 
24207 #define S_RD_DATA_512B_FIFO_CNT8    5
24208 #define M_RD_DATA_512B_FIFO_CNT8    0xffU
24209 #define V_RD_DATA_512B_FIFO_CNT8(x) ((x) << S_RD_DATA_512B_FIFO_CNT8)
24210 #define G_RD_DATA_512B_FIFO_CNT8(x) (((x) >> S_RD_DATA_512B_FIFO_CNT8) & M_RD_DATA_512B_FIFO_CNT8)
24211 
24212 #define S_RD_REQ_TAG_FIFO_CNT8    1
24213 #define M_RD_REQ_TAG_FIFO_CNT8    0xfU
24214 #define V_RD_REQ_TAG_FIFO_CNT8(x) ((x) << S_RD_REQ_TAG_FIFO_CNT8)
24215 #define G_RD_REQ_TAG_FIFO_CNT8(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT8) & M_RD_REQ_TAG_FIFO_CNT8)
24216 
24217 #define A_MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG0 0xa409
24218 
24219 #define S_CMD_IN_FIFO_CNT9    30
24220 #define M_CMD_IN_FIFO_CNT9    0x3U
24221 #define V_CMD_IN_FIFO_CNT9(x) ((x) << S_CMD_IN_FIFO_CNT9)
24222 #define G_CMD_IN_FIFO_CNT9(x) (((x) >> S_CMD_IN_FIFO_CNT9) & M_CMD_IN_FIFO_CNT9)
24223 
24224 #define S_CMD_SPLIT_FIFO_CNT9    28
24225 #define M_CMD_SPLIT_FIFO_CNT9    0x3U
24226 #define V_CMD_SPLIT_FIFO_CNT9(x) ((x) << S_CMD_SPLIT_FIFO_CNT9)
24227 #define G_CMD_SPLIT_FIFO_CNT9(x) (((x) >> S_CMD_SPLIT_FIFO_CNT9) & M_CMD_SPLIT_FIFO_CNT9)
24228 
24229 #define S_CMD_THROTTLE_FIFO_CNT9    22
24230 #define M_CMD_THROTTLE_FIFO_CNT9    0x3fU
24231 #define V_CMD_THROTTLE_FIFO_CNT9(x) ((x) << S_CMD_THROTTLE_FIFO_CNT9)
24232 #define G_CMD_THROTTLE_FIFO_CNT9(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT9) & M_CMD_THROTTLE_FIFO_CNT9)
24233 
24234 #define S_RD_CHNL_FIFO_CNT9    15
24235 #define M_RD_CHNL_FIFO_CNT9    0x7fU
24236 #define V_RD_CHNL_FIFO_CNT9(x) ((x) << S_RD_CHNL_FIFO_CNT9)
24237 #define G_RD_CHNL_FIFO_CNT9(x) (((x) >> S_RD_CHNL_FIFO_CNT9) & M_RD_CHNL_FIFO_CNT9)
24238 
24239 #define S_RD_DATA_EXT_FIFO_CNT9    13
24240 #define M_RD_DATA_EXT_FIFO_CNT9    0x3U
24241 #define V_RD_DATA_EXT_FIFO_CNT9(x) ((x) << S_RD_DATA_EXT_FIFO_CNT9)
24242 #define G_RD_DATA_EXT_FIFO_CNT9(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT9) & M_RD_DATA_EXT_FIFO_CNT9)
24243 
24244 #define S_RD_DATA_512B_FIFO_CNT9    5
24245 #define M_RD_DATA_512B_FIFO_CNT9    0xffU
24246 #define V_RD_DATA_512B_FIFO_CNT9(x) ((x) << S_RD_DATA_512B_FIFO_CNT9)
24247 #define G_RD_DATA_512B_FIFO_CNT9(x) (((x) >> S_RD_DATA_512B_FIFO_CNT9) & M_RD_DATA_512B_FIFO_CNT9)
24248 
24249 #define S_RD_REQ_TAG_FIFO_CNT9    1
24250 #define M_RD_REQ_TAG_FIFO_CNT9    0xfU
24251 #define V_RD_REQ_TAG_FIFO_CNT9(x) ((x) << S_RD_REQ_TAG_FIFO_CNT9)
24252 #define G_RD_REQ_TAG_FIFO_CNT9(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT9) & M_RD_REQ_TAG_FIFO_CNT9)
24253 
24254 #define A_MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG0 0xa40a
24255 
24256 #define S_CMD_IN_FIFO_CNT10    30
24257 #define M_CMD_IN_FIFO_CNT10    0x3U
24258 #define V_CMD_IN_FIFO_CNT10(x) ((x) << S_CMD_IN_FIFO_CNT10)
24259 #define G_CMD_IN_FIFO_CNT10(x) (((x) >> S_CMD_IN_FIFO_CNT10) & M_CMD_IN_FIFO_CNT10)
24260 
24261 #define S_CMD_SPLIT_FIFO_CNT10    28
24262 #define M_CMD_SPLIT_FIFO_CNT10    0x3U
24263 #define V_CMD_SPLIT_FIFO_CNT10(x) ((x) << S_CMD_SPLIT_FIFO_CNT10)
24264 #define G_CMD_SPLIT_FIFO_CNT10(x) (((x) >> S_CMD_SPLIT_FIFO_CNT10) & M_CMD_SPLIT_FIFO_CNT10)
24265 
24266 #define S_CMD_THROTTLE_FIFO_CNT10    22
24267 #define M_CMD_THROTTLE_FIFO_CNT10    0x3fU
24268 #define V_CMD_THROTTLE_FIFO_CNT10(x) ((x) << S_CMD_THROTTLE_FIFO_CNT10)
24269 #define G_CMD_THROTTLE_FIFO_CNT10(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT10) & M_CMD_THROTTLE_FIFO_CNT10)
24270 
24271 #define S_RD_CHNL_FIFO_CNT10    15
24272 #define M_RD_CHNL_FIFO_CNT10    0x7fU
24273 #define V_RD_CHNL_FIFO_CNT10(x) ((x) << S_RD_CHNL_FIFO_CNT10)
24274 #define G_RD_CHNL_FIFO_CNT10(x) (((x) >> S_RD_CHNL_FIFO_CNT10) & M_RD_CHNL_FIFO_CNT10)
24275 
24276 #define S_RD_DATA_EXT_FIFO_CNT10    13
24277 #define M_RD_DATA_EXT_FIFO_CNT10    0x3U
24278 #define V_RD_DATA_EXT_FIFO_CNT10(x) ((x) << S_RD_DATA_EXT_FIFO_CNT10)
24279 #define G_RD_DATA_EXT_FIFO_CNT10(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT10) & M_RD_DATA_EXT_FIFO_CNT10)
24280 
24281 #define S_RD_DATA_512B_FIFO_CNT10    5
24282 #define M_RD_DATA_512B_FIFO_CNT10    0xffU
24283 #define V_RD_DATA_512B_FIFO_CNT10(x) ((x) << S_RD_DATA_512B_FIFO_CNT10)
24284 #define G_RD_DATA_512B_FIFO_CNT10(x) (((x) >> S_RD_DATA_512B_FIFO_CNT10) & M_RD_DATA_512B_FIFO_CNT10)
24285 
24286 #define S_RD_REQ_TAG_FIFO_CNT10    1
24287 #define M_RD_REQ_TAG_FIFO_CNT10    0xfU
24288 #define V_RD_REQ_TAG_FIFO_CNT10(x) ((x) << S_RD_REQ_TAG_FIFO_CNT10)
24289 #define G_RD_REQ_TAG_FIFO_CNT10(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT10) & M_RD_REQ_TAG_FIFO_CNT10)
24290 
24291 #define A_MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa40b
24292 
24293 #define S_CMD_IN_FIFO_CNT11    30
24294 #define M_CMD_IN_FIFO_CNT11    0x3U
24295 #define V_CMD_IN_FIFO_CNT11(x) ((x) << S_CMD_IN_FIFO_CNT11)
24296 #define G_CMD_IN_FIFO_CNT11(x) (((x) >> S_CMD_IN_FIFO_CNT11) & M_CMD_IN_FIFO_CNT11)
24297 
24298 #define S_CMD_SPLIT_FIFO_CNT11    28
24299 #define M_CMD_SPLIT_FIFO_CNT11    0x3U
24300 #define V_CMD_SPLIT_FIFO_CNT11(x) ((x) << S_CMD_SPLIT_FIFO_CNT11)
24301 #define G_CMD_SPLIT_FIFO_CNT11(x) (((x) >> S_CMD_SPLIT_FIFO_CNT11) & M_CMD_SPLIT_FIFO_CNT11)
24302 
24303 #define S_CMD_THROTTLE_FIFO_CNT11    22
24304 #define M_CMD_THROTTLE_FIFO_CNT11    0x3fU
24305 #define V_CMD_THROTTLE_FIFO_CNT11(x) ((x) << S_CMD_THROTTLE_FIFO_CNT11)
24306 #define G_CMD_THROTTLE_FIFO_CNT11(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT11) & M_CMD_THROTTLE_FIFO_CNT11)
24307 
24308 #define S_RD_CHNL_FIFO_CNT11    15
24309 #define M_RD_CHNL_FIFO_CNT11    0x7fU
24310 #define V_RD_CHNL_FIFO_CNT11(x) ((x) << S_RD_CHNL_FIFO_CNT11)
24311 #define G_RD_CHNL_FIFO_CNT11(x) (((x) >> S_RD_CHNL_FIFO_CNT11) & M_RD_CHNL_FIFO_CNT11)
24312 
24313 #define S_RD_DATA_EXT_FIFO_CNT11    13
24314 #define M_RD_DATA_EXT_FIFO_CNT11    0x3U
24315 #define V_RD_DATA_EXT_FIFO_CNT11(x) ((x) << S_RD_DATA_EXT_FIFO_CNT11)
24316 #define G_RD_DATA_EXT_FIFO_CNT11(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT11) & M_RD_DATA_EXT_FIFO_CNT11)
24317 
24318 #define S_RD_DATA_512B_FIFO_CNT11    5
24319 #define M_RD_DATA_512B_FIFO_CNT11    0xffU
24320 #define V_RD_DATA_512B_FIFO_CNT11(x) ((x) << S_RD_DATA_512B_FIFO_CNT11)
24321 #define G_RD_DATA_512B_FIFO_CNT11(x) (((x) >> S_RD_DATA_512B_FIFO_CNT11) & M_RD_DATA_512B_FIFO_CNT11)
24322 
24323 #define S_RD_REQ_TAG_FIFO_CNT11    1
24324 #define M_RD_REQ_TAG_FIFO_CNT11    0xfU
24325 #define V_RD_REQ_TAG_FIFO_CNT11(x) ((x) << S_RD_REQ_TAG_FIFO_CNT11)
24326 #define G_RD_REQ_TAG_FIFO_CNT11(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT11) & M_RD_REQ_TAG_FIFO_CNT11)
24327 
24328 #define A_MA_HMA_CLIENT_INTERFACE_INTERNAL_REG0 0xa40c
24329 
24330 #define S_CMD_IN_FIFO_CNT12    30
24331 #define M_CMD_IN_FIFO_CNT12    0x3U
24332 #define V_CMD_IN_FIFO_CNT12(x) ((x) << S_CMD_IN_FIFO_CNT12)
24333 #define G_CMD_IN_FIFO_CNT12(x) (((x) >> S_CMD_IN_FIFO_CNT12) & M_CMD_IN_FIFO_CNT12)
24334 
24335 #define S_CMD_SPLIT_FIFO_CNT12    28
24336 #define M_CMD_SPLIT_FIFO_CNT12    0x3U
24337 #define V_CMD_SPLIT_FIFO_CNT12(x) ((x) << S_CMD_SPLIT_FIFO_CNT12)
24338 #define G_CMD_SPLIT_FIFO_CNT12(x) (((x) >> S_CMD_SPLIT_FIFO_CNT12) & M_CMD_SPLIT_FIFO_CNT12)
24339 
24340 #define S_CMD_THROTTLE_FIFO_CNT12    22
24341 #define M_CMD_THROTTLE_FIFO_CNT12    0x3fU
24342 #define V_CMD_THROTTLE_FIFO_CNT12(x) ((x) << S_CMD_THROTTLE_FIFO_CNT12)
24343 #define G_CMD_THROTTLE_FIFO_CNT12(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT12) & M_CMD_THROTTLE_FIFO_CNT12)
24344 
24345 #define S_RD_CHNL_FIFO_CNT12    15
24346 #define M_RD_CHNL_FIFO_CNT12    0x7fU
24347 #define V_RD_CHNL_FIFO_CNT12(x) ((x) << S_RD_CHNL_FIFO_CNT12)
24348 #define G_RD_CHNL_FIFO_CNT12(x) (((x) >> S_RD_CHNL_FIFO_CNT12) & M_RD_CHNL_FIFO_CNT12)
24349 
24350 #define S_RD_DATA_EXT_FIFO_CNT12    13
24351 #define M_RD_DATA_EXT_FIFO_CNT12    0x3U
24352 #define V_RD_DATA_EXT_FIFO_CNT12(x) ((x) << S_RD_DATA_EXT_FIFO_CNT12)
24353 #define G_RD_DATA_EXT_FIFO_CNT12(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT12) & M_RD_DATA_EXT_FIFO_CNT12)
24354 
24355 #define S_RD_DATA_512B_FIFO_CNT12    5
24356 #define M_RD_DATA_512B_FIFO_CNT12    0xffU
24357 #define V_RD_DATA_512B_FIFO_CNT12(x) ((x) << S_RD_DATA_512B_FIFO_CNT12)
24358 #define G_RD_DATA_512B_FIFO_CNT12(x) (((x) >> S_RD_DATA_512B_FIFO_CNT12) & M_RD_DATA_512B_FIFO_CNT12)
24359 
24360 #define S_RD_REQ_TAG_FIFO_CNT12    1
24361 #define M_RD_REQ_TAG_FIFO_CNT12    0xfU
24362 #define V_RD_REQ_TAG_FIFO_CNT12(x) ((x) << S_RD_REQ_TAG_FIFO_CNT12)
24363 #define G_RD_REQ_TAG_FIFO_CNT12(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT12) & M_RD_REQ_TAG_FIFO_CNT12)
24364 
24365 #define A_MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG0 0xa40d
24366 
24367 #define S_WR_DATA_FSM0    23
24368 #define V_WR_DATA_FSM0(x) ((x) << S_WR_DATA_FSM0)
24369 #define F_WR_DATA_FSM0    V_WR_DATA_FSM0(1U)
24370 
24371 #define S_RD_DATA_FSM0    22
24372 #define V_RD_DATA_FSM0(x) ((x) << S_RD_DATA_FSM0)
24373 #define F_RD_DATA_FSM0    V_RD_DATA_FSM0(1U)
24374 
24375 #define S_TGT_CMD_FIFO_CNT0    19
24376 #define M_TGT_CMD_FIFO_CNT0    0x7U
24377 #define V_TGT_CMD_FIFO_CNT0(x) ((x) << S_TGT_CMD_FIFO_CNT0)
24378 #define G_TGT_CMD_FIFO_CNT0(x) (((x) >> S_TGT_CMD_FIFO_CNT0) & M_TGT_CMD_FIFO_CNT0)
24379 
24380 #define S_CLNT_NUM_FIFO_CNT0    16
24381 #define M_CLNT_NUM_FIFO_CNT0    0x7U
24382 #define V_CLNT_NUM_FIFO_CNT0(x) ((x) << S_CLNT_NUM_FIFO_CNT0)
24383 #define G_CLNT_NUM_FIFO_CNT0(x) (((x) >> S_CLNT_NUM_FIFO_CNT0) & M_CLNT_NUM_FIFO_CNT0)
24384 
24385 #define S_WR_CMD_TAG_FIFO_CNT_TGT0    8
24386 #define M_WR_CMD_TAG_FIFO_CNT_TGT0    0xffU
24387 #define V_WR_CMD_TAG_FIFO_CNT_TGT0(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT0)
24388 #define G_WR_CMD_TAG_FIFO_CNT_TGT0(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT0) & M_WR_CMD_TAG_FIFO_CNT_TGT0)
24389 
24390 #define S_WR_DATA_512B_FIFO_CNT_TGT0    0
24391 #define M_WR_DATA_512B_FIFO_CNT_TGT0    0xffU
24392 #define V_WR_DATA_512B_FIFO_CNT_TGT0(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT0)
24393 #define G_WR_DATA_512B_FIFO_CNT_TGT0(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT0) & M_WR_DATA_512B_FIFO_CNT_TGT0)
24394 
24395 #define A_MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG0 0xa40e
24396 
24397 #define S_WR_DATA_FSM1    23
24398 #define V_WR_DATA_FSM1(x) ((x) << S_WR_DATA_FSM1)
24399 #define F_WR_DATA_FSM1    V_WR_DATA_FSM1(1U)
24400 
24401 #define S_RD_DATA_FSM1    22
24402 #define V_RD_DATA_FSM1(x) ((x) << S_RD_DATA_FSM1)
24403 #define F_RD_DATA_FSM1    V_RD_DATA_FSM1(1U)
24404 
24405 #define S_TGT_CMD_FIFO_CNT1    19
24406 #define M_TGT_CMD_FIFO_CNT1    0x7U
24407 #define V_TGT_CMD_FIFO_CNT1(x) ((x) << S_TGT_CMD_FIFO_CNT1)
24408 #define G_TGT_CMD_FIFO_CNT1(x) (((x) >> S_TGT_CMD_FIFO_CNT1) & M_TGT_CMD_FIFO_CNT1)
24409 
24410 #define S_CLNT_NUM_FIFO_CNT1    16
24411 #define M_CLNT_NUM_FIFO_CNT1    0x7U
24412 #define V_CLNT_NUM_FIFO_CNT1(x) ((x) << S_CLNT_NUM_FIFO_CNT1)
24413 #define G_CLNT_NUM_FIFO_CNT1(x) (((x) >> S_CLNT_NUM_FIFO_CNT1) & M_CLNT_NUM_FIFO_CNT1)
24414 
24415 #define S_WR_CMD_TAG_FIFO_CNT_TGT1    8
24416 #define M_WR_CMD_TAG_FIFO_CNT_TGT1    0xffU
24417 #define V_WR_CMD_TAG_FIFO_CNT_TGT1(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT1)
24418 #define G_WR_CMD_TAG_FIFO_CNT_TGT1(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT1) & M_WR_CMD_TAG_FIFO_CNT_TGT1)
24419 
24420 #define S_WR_DATA_512B_FIFO_CNT_TGT1    0
24421 #define M_WR_DATA_512B_FIFO_CNT_TGT1    0xffU
24422 #define V_WR_DATA_512B_FIFO_CNT_TGT1(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT1)
24423 #define G_WR_DATA_512B_FIFO_CNT_TGT1(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT1) & M_WR_DATA_512B_FIFO_CNT_TGT1)
24424 
24425 #define A_MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG0 0xa40f
24426 
24427 #define S_WR_DATA_FSM2    23
24428 #define V_WR_DATA_FSM2(x) ((x) << S_WR_DATA_FSM2)
24429 #define F_WR_DATA_FSM2    V_WR_DATA_FSM2(1U)
24430 
24431 #define S_RD_DATA_FSM2    22
24432 #define V_RD_DATA_FSM2(x) ((x) << S_RD_DATA_FSM2)
24433 #define F_RD_DATA_FSM2    V_RD_DATA_FSM2(1U)
24434 
24435 #define S_TGT_CMD_FIFO_CNT2    19
24436 #define M_TGT_CMD_FIFO_CNT2    0x7U
24437 #define V_TGT_CMD_FIFO_CNT2(x) ((x) << S_TGT_CMD_FIFO_CNT2)
24438 #define G_TGT_CMD_FIFO_CNT2(x) (((x) >> S_TGT_CMD_FIFO_CNT2) & M_TGT_CMD_FIFO_CNT2)
24439 
24440 #define S_CLNT_NUM_FIFO_CNT2    16
24441 #define M_CLNT_NUM_FIFO_CNT2    0x7U
24442 #define V_CLNT_NUM_FIFO_CNT2(x) ((x) << S_CLNT_NUM_FIFO_CNT2)
24443 #define G_CLNT_NUM_FIFO_CNT2(x) (((x) >> S_CLNT_NUM_FIFO_CNT2) & M_CLNT_NUM_FIFO_CNT2)
24444 
24445 #define S_WR_CMD_TAG_FIFO_CNT_TGT2    8
24446 #define M_WR_CMD_TAG_FIFO_CNT_TGT2    0xffU
24447 #define V_WR_CMD_TAG_FIFO_CNT_TGT2(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT2)
24448 #define G_WR_CMD_TAG_FIFO_CNT_TGT2(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT2) & M_WR_CMD_TAG_FIFO_CNT_TGT2)
24449 
24450 #define S_WR_DATA_512B_FIFO_CNT_TGT2    0
24451 #define M_WR_DATA_512B_FIFO_CNT_TGT2    0xffU
24452 #define V_WR_DATA_512B_FIFO_CNT_TGT2(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT2)
24453 #define G_WR_DATA_512B_FIFO_CNT_TGT2(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT2) & M_WR_DATA_512B_FIFO_CNT_TGT2)
24454 
24455 #define A_MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG0 0xa410
24456 
24457 #define S_WR_DATA_FSM3    23
24458 #define V_WR_DATA_FSM3(x) ((x) << S_WR_DATA_FSM3)
24459 #define F_WR_DATA_FSM3    V_WR_DATA_FSM3(1U)
24460 
24461 #define S_RD_DATA_FSM3    22
24462 #define V_RD_DATA_FSM3(x) ((x) << S_RD_DATA_FSM3)
24463 #define F_RD_DATA_FSM3    V_RD_DATA_FSM3(1U)
24464 
24465 #define S_TGT_CMD_FIFO_CNT3    19
24466 #define M_TGT_CMD_FIFO_CNT3    0x7U
24467 #define V_TGT_CMD_FIFO_CNT3(x) ((x) << S_TGT_CMD_FIFO_CNT3)
24468 #define G_TGT_CMD_FIFO_CNT3(x) (((x) >> S_TGT_CMD_FIFO_CNT3) & M_TGT_CMD_FIFO_CNT3)
24469 
24470 #define S_CLNT_NUM_FIFO_CNT3    16
24471 #define M_CLNT_NUM_FIFO_CNT3    0x7U
24472 #define V_CLNT_NUM_FIFO_CNT3(x) ((x) << S_CLNT_NUM_FIFO_CNT3)
24473 #define G_CLNT_NUM_FIFO_CNT3(x) (((x) >> S_CLNT_NUM_FIFO_CNT3) & M_CLNT_NUM_FIFO_CNT3)
24474 
24475 #define S_WR_CMD_TAG_FIFO_CNT_TGT3    8
24476 #define M_WR_CMD_TAG_FIFO_CNT_TGT3    0xffU
24477 #define V_WR_CMD_TAG_FIFO_CNT_TGT3(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT3)
24478 #define G_WR_CMD_TAG_FIFO_CNT_TGT3(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT3) & M_WR_CMD_TAG_FIFO_CNT_TGT3)
24479 
24480 #define S_WR_DATA_512B_FIFO_CNT_TGT    0
24481 #define M_WR_DATA_512B_FIFO_CNT_TGT    0xffU
24482 #define V_WR_DATA_512B_FIFO_CNT_TGT(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT)
24483 #define G_WR_DATA_512B_FIFO_CNT_TGT(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT) & M_WR_DATA_512B_FIFO_CNT_TGT)
24484 
24485 #define A_MA_SGE_THREAD_0_CLNT_EXP_RD_CYC_CNT_LO 0xa412
24486 #define A_MA_SGE_THREAD_1_CLNT_EXP_RD_CYC_CNT_LO 0xa413
24487 #define A_MA_ULP_TX_CLNT_EXP_RD_CYC_CNT_LO 0xa414
24488 #define A_MA_ULP_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa415
24489 #define A_MA_ULP_TX_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa416
24490 #define A_MA_TP_THREAD_0_CLNT_EXP_RD_CYC_CNT_LO 0xa417
24491 #define A_MA_TP_THREAD_1_CLNT_EXP_RD_CYC_CNT_LO 0xa418
24492 #define A_MA_LE_CLNT_EXP_RD_CYC_CNT_LO 0xa419
24493 #define A_MA_CIM_CLNT_EXP_RD_CYC_CNT_LO 0xa41a
24494 #define A_MA_PCIE_CLNT_EXP_RD_CYC_CNT_LO 0xa41b
24495 #define A_MA_PM_TX_CLNT_EXP_RD_CYC_CNT_LO 0xa41c
24496 #define A_MA_PM_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa41d
24497 #define A_MA_HMA_CLNT_EXP_RD_CYC_CNT_LO 0xa41e
24498 #define A_T6_MA_EDRAM0_WRDATA_CNT1 0xa800
24499 #define A_T6_MA_EDRAM0_WRDATA_CNT0 0xa801
24500 #define A_T6_MA_EDRAM1_WRDATA_CNT1 0xa802
24501 #define A_T6_MA_EDRAM1_WRDATA_CNT0 0xa803
24502 #define A_T6_MA_EXT_MEMORY0_WRDATA_CNT1 0xa804
24503 #define A_T6_MA_EXT_MEMORY0_WRDATA_CNT0 0xa805
24504 #define A_T6_MA_HOST_MEMORY_WRDATA_CNT1 0xa806
24505 #define A_T6_MA_HOST_MEMORY_WRDATA_CNT0 0xa807
24506 #define A_T6_MA_EXT_MEMORY1_WRDATA_CNT1 0xa808
24507 #define A_T6_MA_EXT_MEMORY1_WRDATA_CNT0 0xa809
24508 #define A_T6_MA_EDRAM0_RDDATA_CNT1 0xa80a
24509 #define A_T6_MA_EDRAM0_RDDATA_CNT0 0xa80b
24510 #define A_T6_MA_EDRAM1_RDDATA_CNT1 0xa80c
24511 #define A_T6_MA_EDRAM1_RDDATA_CNT0 0xa80d
24512 #define A_T6_MA_EXT_MEMORY0_RDDATA_CNT1 0xa80e
24513 #define A_T6_MA_EXT_MEMORY0_RDDATA_CNT0 0xa80f
24514 #define A_T6_MA_HOST_MEMORY_RDDATA_CNT1 0xa810
24515 #define A_T6_MA_HOST_MEMORY_RDDATA_CNT0 0xa811
24516 #define A_T6_MA_EXT_MEMORY1_RDDATA_CNT1 0xa812
24517 #define A_T6_MA_EXT_MEMORY1_RDDATA_CNT0 0xa813
24518 #define A_MA_SGE_THREAD_0_CLNT_ACT_WR_CYC_CNT_HI 0xac00
24519 #define A_MA_SGE_THREAD_0_CLNT_ACT_WR_CYC_CNT_LO 0xac01
24520 #define A_MA_SGE_THREAD_1_CLNT_ACT_WR_CYC_CNT_HI 0xac02
24521 #define A_MA_SGE_THREAD_1_CLNT_ACT_WR_CYC_CNT_LO 0xac03
24522 #define A_MA_ULP_TX_CLNT_ACT_WR_CYC_CNT_HI 0xac04
24523 #define A_MA_ULP_TX_CLNT_ACT_WR_CYC_CNT_LO 0xac05
24524 #define A_MA_ULP_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac06
24525 #define A_MA_ULP_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac07
24526 #define A_MA_ULP_TX_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac08
24527 #define A_MA_ULP_TX_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac09
24528 #define A_MA_TP_THREAD_0_CLNT_ACT_WR_CYC_CNT_HI 0xac0a
24529 #define A_MA_TP_THREAD_0_CLNT_ACT_WR_CYC_CNT_LO 0xac0b
24530 #define A_MA_TP_THREAD_1_CLNT_ACT_WR_CYC_CNT_HI 0xac0c
24531 #define A_MA_TP_THREAD_1_CLNT_ACT_WR_CYC_CNT_LO 0xac0d
24532 #define A_MA_LE_CLNT_ACT_WR_CYC_CNT_HI 0xac0e
24533 #define A_MA_LE_CLNT_ACT_WR_CYC_CNT_LO 0xac0f
24534 #define A_MA_CIM_CLNT_ACT_WR_CYC_CNT_HI 0xac10
24535 #define A_MA_CIM_CLNT_ACT_WR_CYC_CNT_LO 0xac11
24536 #define A_MA_PCIE_CLNT_ACT_WR_CYC_CNT_HI 0xac12
24537 #define A_MA_PCIE_CLNT_ACT_WR_CYC_CNT_LO 0xac13
24538 #define A_MA_PM_TX_CLNT_ACT_WR_CYC_CNT_HI 0xac14
24539 #define A_MA_PM_TX_CLNT_ACT_WR_CYC_CNT_LO 0xac15
24540 #define A_MA_PM_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac16
24541 #define A_MA_PM_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac17
24542 #define A_MA_HMA_CLNT_ACT_WR_CYC_CNT_HI 0xac18
24543 #define A_MA_HMA_CLNT_ACT_WR_CYC_CNT_LO 0xac19
24544 #define A_MA_SGE_THREAD_0_CLNT_WR_REQ_CNT 0xb000
24545 #define A_MA_SGE_THREAD_1_CLNT_WR_REQ_CNT 0xb001
24546 #define A_MA_ULP_TX_CLNT_WR_REQ_CNT 0xb002
24547 #define A_MA_ULP_RX_CLNT_WR_REQ_CNT 0xb003
24548 #define A_MA_ULP_TX_RX_CLNT_WR_REQ_CNT 0xb004
24549 #define A_MA_TP_THREAD_0_CLNT_WR_REQ_CNT 0xb005
24550 #define A_MA_TP_THREAD_1_CLNT_WR_REQ_CNT 0xb006
24551 #define A_MA_LE_CLNT_WR_REQ_CNT 0xb007
24552 #define A_MA_CIM_CLNT_WR_REQ_CNT 0xb008
24553 #define A_MA_PCIE_CLNT_WR_REQ_CNT 0xb009
24554 #define A_MA_PM_TX_CLNT_WR_REQ_CNT 0xb00a
24555 #define A_MA_PM_RX_CLNT_WR_REQ_CNT 0xb00b
24556 #define A_MA_HMA_CLNT_WR_REQ_CNT 0xb00c
24557 #define A_MA_SGE_THREAD_0_CLNT_RD_REQ_CNT 0xb00d
24558 #define A_MA_SGE_THREAD_1_CLNT_RD_REQ_CNT 0xb00e
24559 #define A_MA_ULP_TX_CLNT_RD_REQ_CNT 0xb00f
24560 #define A_MA_ULP_RX_CLNT_RD_REQ_CNT 0xb010
24561 #define A_MA_ULP_TX_RX_CLNT_RD_REQ_CNT 0xb011
24562 #define A_MA_TP_THREAD_0_CLNT_RD_REQ_CNT 0xb012
24563 #define A_MA_TP_THREAD_1_CLNT_RD_REQ_CNT 0xb013
24564 #define A_MA_LE_CLNT_RD_REQ_CNT 0xb014
24565 #define A_MA_CIM_CLNT_RD_REQ_CNT 0xb015
24566 #define A_MA_PCIE_CLNT_RD_REQ_CNT 0xb016
24567 #define A_MA_PM_TX_CLNT_RD_REQ_CNT 0xb017
24568 #define A_MA_PM_RX_CLNT_RD_REQ_CNT 0xb018
24569 #define A_MA_HMA_CLNT_RD_REQ_CNT 0xb019
24570 #define A_MA_SGE_THREAD_0_CLNT_EXP_RD_CYC_CNT_HI 0xb400
24571 #define A_MA_SGE_THREAD_1_CLNT_EXP_RD_CYC_CNT_HI 0xb401
24572 #define A_MA_ULP_TX_CLNT_EXP_RD_CYC_CNT_HI 0xb402
24573 #define A_MA_ULP_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb403
24574 #define A_MA_ULP_TX_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb404
24575 #define A_MA_TP_THREAD_0_CLNT_EXP_RD_CYC_CNT_HI 0xb405
24576 #define A_MA_TP_THREAD_1_CLNT_EXP_RD_CYC_CNT_HI 0xb406
24577 #define A_MA_LE_CLNT_EXP_RD_CYC_CNT_HI 0xb407
24578 #define A_MA_CIM_CLNT_EXP_RD_CYC_CNT_HI 0xb408
24579 #define A_MA_PCIE_CLNT_EXP_RD_CYC_CNT_HI 0xb409
24580 #define A_MA_PM_TX_CLNT_EXP_RD_CYC_CNT_HI 0xb40a
24581 #define A_MA_PM_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb40b
24582 #define A_MA_HMA_CLNT_EXP_RD_CYC_CNT_HI 0xb40c
24583 #define A_MA_SGE_THREAD_0_CLNT_EXP_WR_CYC_CNT_HI 0xb40d
24584 #define A_MA_SGE_THREAD_1_CLNT_EXP_WR_CYC_CNT_HI 0xb40e
24585 #define A_MA_ULP_TX_CLNT_EXP_WR_CYC_CNT_HI 0xb40f
24586 #define A_MA_ULP_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb410
24587 #define A_MA_ULP_TX_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb411
24588 #define A_MA_TP_THREAD_0_CLNT_EXP_WR_CYC_CNT_HI 0xb412
24589 #define A_MA_TP_THREAD_1_CLNT_EXP_WR_CYC_CNT_HI 0xb413
24590 #define A_MA_LE_CLNT_EXP_WR_CYC_CNT_HI 0xb414
24591 #define A_MA_CIM_CLNT_EXP_WR_CYC_CNT_HI 0xb415
24592 #define A_MA_PCIE_CLNT_EXP_WR_CYC_CNT_HI 0xb416
24593 #define A_MA_PM_TX_CLNT_EXP_WR_CYC_CNT_HI 0xb417
24594 #define A_MA_PM_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb418
24595 #define A_MA_HMA_CLNT_EXP_WR_CYC_CNT_HI 0xb419
24596 #define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1 0xe400
24597 
24598 #define S_WR_DATA_EXT_FIFO_CNT0    30
24599 #define M_WR_DATA_EXT_FIFO_CNT0    0x3U
24600 #define V_WR_DATA_EXT_FIFO_CNT0(x) ((x) << S_WR_DATA_EXT_FIFO_CNT0)
24601 #define G_WR_DATA_EXT_FIFO_CNT0(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT0) & M_WR_DATA_EXT_FIFO_CNT0)
24602 
24603 #define S_WR_CMD_TAG_FIFO_CNT0    26
24604 #define M_WR_CMD_TAG_FIFO_CNT0    0xfU
24605 #define V_WR_CMD_TAG_FIFO_CNT0(x) ((x) << S_WR_CMD_TAG_FIFO_CNT0)
24606 #define G_WR_CMD_TAG_FIFO_CNT0(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT0) & M_WR_CMD_TAG_FIFO_CNT0)
24607 
24608 #define S_WR_DATA_512B_FIFO_CNT0    18
24609 #define M_WR_DATA_512B_FIFO_CNT0    0xffU
24610 #define V_WR_DATA_512B_FIFO_CNT0(x) ((x) << S_WR_DATA_512B_FIFO_CNT0)
24611 #define G_WR_DATA_512B_FIFO_CNT0(x) (((x) >> S_WR_DATA_512B_FIFO_CNT0) & M_WR_DATA_512B_FIFO_CNT0)
24612 
24613 #define S_RD_DATA_ALIGN_FSM0    17
24614 #define V_RD_DATA_ALIGN_FSM0(x) ((x) << S_RD_DATA_ALIGN_FSM0)
24615 #define F_RD_DATA_ALIGN_FSM0    V_RD_DATA_ALIGN_FSM0(1U)
24616 
24617 #define S_RD_DATA_FETCH_FSM0    16
24618 #define V_RD_DATA_FETCH_FSM0(x) ((x) << S_RD_DATA_FETCH_FSM0)
24619 #define F_RD_DATA_FETCH_FSM0    V_RD_DATA_FETCH_FSM0(1U)
24620 
24621 #define S_COHERENCY_TX_FSM0    15
24622 #define V_COHERENCY_TX_FSM0(x) ((x) << S_COHERENCY_TX_FSM0)
24623 #define F_COHERENCY_TX_FSM0    V_COHERENCY_TX_FSM0(1U)
24624 
24625 #define S_COHERENCY_RX_FSM0    14
24626 #define V_COHERENCY_RX_FSM0(x) ((x) << S_COHERENCY_RX_FSM0)
24627 #define F_COHERENCY_RX_FSM0    V_COHERENCY_RX_FSM0(1U)
24628 
24629 #define S_ARB_REQ_FSM0    13
24630 #define V_ARB_REQ_FSM0(x) ((x) << S_ARB_REQ_FSM0)
24631 #define F_ARB_REQ_FSM0    V_ARB_REQ_FSM0(1U)
24632 
24633 #define S_CMD_SPLIT_FSM0    10
24634 #define M_CMD_SPLIT_FSM0    0x7U
24635 #define V_CMD_SPLIT_FSM0(x) ((x) << S_CMD_SPLIT_FSM0)
24636 #define G_CMD_SPLIT_FSM0(x) (((x) >> S_CMD_SPLIT_FSM0) & M_CMD_SPLIT_FSM0)
24637 
24638 #define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1 0xe420
24639 
24640 #define S_WR_DATA_EXT_FIFO_CNT1    30
24641 #define M_WR_DATA_EXT_FIFO_CNT1    0x3U
24642 #define V_WR_DATA_EXT_FIFO_CNT1(x) ((x) << S_WR_DATA_EXT_FIFO_CNT1)
24643 #define G_WR_DATA_EXT_FIFO_CNT1(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT1) & M_WR_DATA_EXT_FIFO_CNT1)
24644 
24645 #define S_WR_CMD_TAG_FIFO_CNT1    26
24646 #define M_WR_CMD_TAG_FIFO_CNT1    0xfU
24647 #define V_WR_CMD_TAG_FIFO_CNT1(x) ((x) << S_WR_CMD_TAG_FIFO_CNT1)
24648 #define G_WR_CMD_TAG_FIFO_CNT1(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT1) & M_WR_CMD_TAG_FIFO_CNT1)
24649 
24650 #define S_WR_DATA_512B_FIFO_CNT1    18
24651 #define M_WR_DATA_512B_FIFO_CNT1    0xffU
24652 #define V_WR_DATA_512B_FIFO_CNT1(x) ((x) << S_WR_DATA_512B_FIFO_CNT1)
24653 #define G_WR_DATA_512B_FIFO_CNT1(x) (((x) >> S_WR_DATA_512B_FIFO_CNT1) & M_WR_DATA_512B_FIFO_CNT1)
24654 
24655 #define S_RD_DATA_ALIGN_FSM1    17
24656 #define V_RD_DATA_ALIGN_FSM1(x) ((x) << S_RD_DATA_ALIGN_FSM1)
24657 #define F_RD_DATA_ALIGN_FSM1    V_RD_DATA_ALIGN_FSM1(1U)
24658 
24659 #define S_RD_DATA_FETCH_FSM1    16
24660 #define V_RD_DATA_FETCH_FSM1(x) ((x) << S_RD_DATA_FETCH_FSM1)
24661 #define F_RD_DATA_FETCH_FSM1    V_RD_DATA_FETCH_FSM1(1U)
24662 
24663 #define S_COHERENCY_TX_FSM1    15
24664 #define V_COHERENCY_TX_FSM1(x) ((x) << S_COHERENCY_TX_FSM1)
24665 #define F_COHERENCY_TX_FSM1    V_COHERENCY_TX_FSM1(1U)
24666 
24667 #define S_COHERENCY_RX_FSM1    14
24668 #define V_COHERENCY_RX_FSM1(x) ((x) << S_COHERENCY_RX_FSM1)
24669 #define F_COHERENCY_RX_FSM1    V_COHERENCY_RX_FSM1(1U)
24670 
24671 #define S_ARB_REQ_FSM1    13
24672 #define V_ARB_REQ_FSM1(x) ((x) << S_ARB_REQ_FSM1)
24673 #define F_ARB_REQ_FSM1    V_ARB_REQ_FSM1(1U)
24674 
24675 #define S_CMD_SPLIT_FSM1    10
24676 #define M_CMD_SPLIT_FSM1    0x7U
24677 #define V_CMD_SPLIT_FSM1(x) ((x) << S_CMD_SPLIT_FSM1)
24678 #define G_CMD_SPLIT_FSM1(x) (((x) >> S_CMD_SPLIT_FSM1) & M_CMD_SPLIT_FSM1)
24679 
24680 #define A_MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG1 0xe440
24681 
24682 #define S_WR_DATA_EXT_FIFO_CNT2    30
24683 #define M_WR_DATA_EXT_FIFO_CNT2    0x3U
24684 #define V_WR_DATA_EXT_FIFO_CNT2(x) ((x) << S_WR_DATA_EXT_FIFO_CNT2)
24685 #define G_WR_DATA_EXT_FIFO_CNT2(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT2) & M_WR_DATA_EXT_FIFO_CNT2)
24686 
24687 #define S_WR_CMD_TAG_FIFO_CNT2    26
24688 #define M_WR_CMD_TAG_FIFO_CNT2    0xfU
24689 #define V_WR_CMD_TAG_FIFO_CNT2(x) ((x) << S_WR_CMD_TAG_FIFO_CNT2)
24690 #define G_WR_CMD_TAG_FIFO_CNT2(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT2) & M_WR_CMD_TAG_FIFO_CNT2)
24691 
24692 #define S_WR_DATA_512B_FIFO_CNT2    18
24693 #define M_WR_DATA_512B_FIFO_CNT2    0xffU
24694 #define V_WR_DATA_512B_FIFO_CNT2(x) ((x) << S_WR_DATA_512B_FIFO_CNT2)
24695 #define G_WR_DATA_512B_FIFO_CNT2(x) (((x) >> S_WR_DATA_512B_FIFO_CNT2) & M_WR_DATA_512B_FIFO_CNT2)
24696 
24697 #define S_RD_DATA_ALIGN_FSM2    17
24698 #define V_RD_DATA_ALIGN_FSM2(x) ((x) << S_RD_DATA_ALIGN_FSM2)
24699 #define F_RD_DATA_ALIGN_FSM2    V_RD_DATA_ALIGN_FSM2(1U)
24700 
24701 #define S_RD_DATA_FETCH_FSM2    16
24702 #define V_RD_DATA_FETCH_FSM2(x) ((x) << S_RD_DATA_FETCH_FSM2)
24703 #define F_RD_DATA_FETCH_FSM2    V_RD_DATA_FETCH_FSM2(1U)
24704 
24705 #define S_COHERENCY_TX_FSM2    15
24706 #define V_COHERENCY_TX_FSM2(x) ((x) << S_COHERENCY_TX_FSM2)
24707 #define F_COHERENCY_TX_FSM2    V_COHERENCY_TX_FSM2(1U)
24708 
24709 #define S_COHERENCY_RX_FSM2    14
24710 #define V_COHERENCY_RX_FSM2(x) ((x) << S_COHERENCY_RX_FSM2)
24711 #define F_COHERENCY_RX_FSM2    V_COHERENCY_RX_FSM2(1U)
24712 
24713 #define S_ARB_REQ_FSM2    13
24714 #define V_ARB_REQ_FSM2(x) ((x) << S_ARB_REQ_FSM2)
24715 #define F_ARB_REQ_FSM2    V_ARB_REQ_FSM2(1U)
24716 
24717 #define S_CMD_SPLIT_FSM2    10
24718 #define M_CMD_SPLIT_FSM2    0x7U
24719 #define V_CMD_SPLIT_FSM2(x) ((x) << S_CMD_SPLIT_FSM2)
24720 #define G_CMD_SPLIT_FSM2(x) (((x) >> S_CMD_SPLIT_FSM2) & M_CMD_SPLIT_FSM2)
24721 
24722 #define A_MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe460
24723 
24724 #define S_WR_DATA_EXT_FIFO_CNT3    30
24725 #define M_WR_DATA_EXT_FIFO_CNT3    0x3U
24726 #define V_WR_DATA_EXT_FIFO_CNT3(x) ((x) << S_WR_DATA_EXT_FIFO_CNT3)
24727 #define G_WR_DATA_EXT_FIFO_CNT3(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT3) & M_WR_DATA_EXT_FIFO_CNT3)
24728 
24729 #define S_WR_CMD_TAG_FIFO_CNT3    26
24730 #define M_WR_CMD_TAG_FIFO_CNT3    0xfU
24731 #define V_WR_CMD_TAG_FIFO_CNT3(x) ((x) << S_WR_CMD_TAG_FIFO_CNT3)
24732 #define G_WR_CMD_TAG_FIFO_CNT3(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT3) & M_WR_CMD_TAG_FIFO_CNT3)
24733 
24734 #define S_WR_DATA_512B_FIFO_CNT3    18
24735 #define M_WR_DATA_512B_FIFO_CNT3    0xffU
24736 #define V_WR_DATA_512B_FIFO_CNT3(x) ((x) << S_WR_DATA_512B_FIFO_CNT3)
24737 #define G_WR_DATA_512B_FIFO_CNT3(x) (((x) >> S_WR_DATA_512B_FIFO_CNT3) & M_WR_DATA_512B_FIFO_CNT3)
24738 
24739 #define S_RD_DATA_ALIGN_FSM3    17
24740 #define V_RD_DATA_ALIGN_FSM3(x) ((x) << S_RD_DATA_ALIGN_FSM3)
24741 #define F_RD_DATA_ALIGN_FSM3    V_RD_DATA_ALIGN_FSM3(1U)
24742 
24743 #define S_RD_DATA_FETCH_FSM3    16
24744 #define V_RD_DATA_FETCH_FSM3(x) ((x) << S_RD_DATA_FETCH_FSM3)
24745 #define F_RD_DATA_FETCH_FSM3    V_RD_DATA_FETCH_FSM3(1U)
24746 
24747 #define S_COHERENCY_TX_FSM3    15
24748 #define V_COHERENCY_TX_FSM3(x) ((x) << S_COHERENCY_TX_FSM3)
24749 #define F_COHERENCY_TX_FSM3    V_COHERENCY_TX_FSM3(1U)
24750 
24751 #define S_COHERENCY_RX_FSM3    14
24752 #define V_COHERENCY_RX_FSM3(x) ((x) << S_COHERENCY_RX_FSM3)
24753 #define F_COHERENCY_RX_FSM3    V_COHERENCY_RX_FSM3(1U)
24754 
24755 #define S_ARB_REQ_FSM3    13
24756 #define V_ARB_REQ_FSM3(x) ((x) << S_ARB_REQ_FSM3)
24757 #define F_ARB_REQ_FSM3    V_ARB_REQ_FSM3(1U)
24758 
24759 #define S_CMD_SPLIT_FSM3    10
24760 #define M_CMD_SPLIT_FSM3    0x7U
24761 #define V_CMD_SPLIT_FSM3(x) ((x) << S_CMD_SPLIT_FSM3)
24762 #define G_CMD_SPLIT_FSM3(x) (((x) >> S_CMD_SPLIT_FSM3) & M_CMD_SPLIT_FSM3)
24763 
24764 #define A_MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe480
24765 
24766 #define S_WR_DATA_EXT_FIFO_CNT4    30
24767 #define M_WR_DATA_EXT_FIFO_CNT4    0x3U
24768 #define V_WR_DATA_EXT_FIFO_CNT4(x) ((x) << S_WR_DATA_EXT_FIFO_CNT4)
24769 #define G_WR_DATA_EXT_FIFO_CNT4(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT4) & M_WR_DATA_EXT_FIFO_CNT4)
24770 
24771 #define S_WR_CMD_TAG_FIFO_CNT4    26
24772 #define M_WR_CMD_TAG_FIFO_CNT4    0xfU
24773 #define V_WR_CMD_TAG_FIFO_CNT4(x) ((x) << S_WR_CMD_TAG_FIFO_CNT4)
24774 #define G_WR_CMD_TAG_FIFO_CNT4(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT4) & M_WR_CMD_TAG_FIFO_CNT4)
24775 
24776 #define S_WR_DATA_512B_FIFO_CNT4    18
24777 #define M_WR_DATA_512B_FIFO_CNT4    0xffU
24778 #define V_WR_DATA_512B_FIFO_CNT4(x) ((x) << S_WR_DATA_512B_FIFO_CNT4)
24779 #define G_WR_DATA_512B_FIFO_CNT4(x) (((x) >> S_WR_DATA_512B_FIFO_CNT4) & M_WR_DATA_512B_FIFO_CNT4)
24780 
24781 #define S_RD_DATA_ALIGN_FSM4    17
24782 #define V_RD_DATA_ALIGN_FSM4(x) ((x) << S_RD_DATA_ALIGN_FSM4)
24783 #define F_RD_DATA_ALIGN_FSM4    V_RD_DATA_ALIGN_FSM4(1U)
24784 
24785 #define S_RD_DATA_FETCH_FSM4    16
24786 #define V_RD_DATA_FETCH_FSM4(x) ((x) << S_RD_DATA_FETCH_FSM4)
24787 #define F_RD_DATA_FETCH_FSM4    V_RD_DATA_FETCH_FSM4(1U)
24788 
24789 #define S_COHERENCY_TX_FSM4    15
24790 #define V_COHERENCY_TX_FSM4(x) ((x) << S_COHERENCY_TX_FSM4)
24791 #define F_COHERENCY_TX_FSM4    V_COHERENCY_TX_FSM4(1U)
24792 
24793 #define S_COHERENCY_RX_FSM4    14
24794 #define V_COHERENCY_RX_FSM4(x) ((x) << S_COHERENCY_RX_FSM4)
24795 #define F_COHERENCY_RX_FSM4    V_COHERENCY_RX_FSM4(1U)
24796 
24797 #define S_ARB_REQ_FSM4    13
24798 #define V_ARB_REQ_FSM4(x) ((x) << S_ARB_REQ_FSM4)
24799 #define F_ARB_REQ_FSM4    V_ARB_REQ_FSM4(1U)
24800 
24801 #define S_CMD_SPLIT_FSM4    10
24802 #define M_CMD_SPLIT_FSM4    0x7U
24803 #define V_CMD_SPLIT_FSM4(x) ((x) << S_CMD_SPLIT_FSM4)
24804 #define G_CMD_SPLIT_FSM4(x) (((x) >> S_CMD_SPLIT_FSM4) & M_CMD_SPLIT_FSM4)
24805 
24806 #define A_MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1 0xe4a0
24807 
24808 #define S_WR_DATA_EXT_FIFO_CNT5    30
24809 #define M_WR_DATA_EXT_FIFO_CNT5    0x3U
24810 #define V_WR_DATA_EXT_FIFO_CNT5(x) ((x) << S_WR_DATA_EXT_FIFO_CNT5)
24811 #define G_WR_DATA_EXT_FIFO_CNT5(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT5) & M_WR_DATA_EXT_FIFO_CNT5)
24812 
24813 #define S_WR_CMD_TAG_FIFO_CNT5    26
24814 #define M_WR_CMD_TAG_FIFO_CNT5    0xfU
24815 #define V_WR_CMD_TAG_FIFO_CNT5(x) ((x) << S_WR_CMD_TAG_FIFO_CNT5)
24816 #define G_WR_CMD_TAG_FIFO_CNT5(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT5) & M_WR_CMD_TAG_FIFO_CNT5)
24817 
24818 #define S_WR_DATA_512B_FIFO_CNT5    18
24819 #define M_WR_DATA_512B_FIFO_CNT5    0xffU
24820 #define V_WR_DATA_512B_FIFO_CNT5(x) ((x) << S_WR_DATA_512B_FIFO_CNT5)
24821 #define G_WR_DATA_512B_FIFO_CNT5(x) (((x) >> S_WR_DATA_512B_FIFO_CNT5) & M_WR_DATA_512B_FIFO_CNT5)
24822 
24823 #define S_RD_DATA_ALIGN_FSM5    17
24824 #define V_RD_DATA_ALIGN_FSM5(x) ((x) << S_RD_DATA_ALIGN_FSM5)
24825 #define F_RD_DATA_ALIGN_FSM5    V_RD_DATA_ALIGN_FSM5(1U)
24826 
24827 #define S_RD_DATA_FETCH_FSM5    16
24828 #define V_RD_DATA_FETCH_FSM5(x) ((x) << S_RD_DATA_FETCH_FSM5)
24829 #define F_RD_DATA_FETCH_FSM5    V_RD_DATA_FETCH_FSM5(1U)
24830 
24831 #define S_COHERENCY_TX_FSM5    15
24832 #define V_COHERENCY_TX_FSM5(x) ((x) << S_COHERENCY_TX_FSM5)
24833 #define F_COHERENCY_TX_FSM5    V_COHERENCY_TX_FSM5(1U)
24834 
24835 #define S_COHERENCY_RX_FSM5    14
24836 #define V_COHERENCY_RX_FSM5(x) ((x) << S_COHERENCY_RX_FSM5)
24837 #define F_COHERENCY_RX_FSM5    V_COHERENCY_RX_FSM5(1U)
24838 
24839 #define S_ARB_REQ_FSM5    13
24840 #define V_ARB_REQ_FSM5(x) ((x) << S_ARB_REQ_FSM5)
24841 #define F_ARB_REQ_FSM5    V_ARB_REQ_FSM5(1U)
24842 
24843 #define S_CMD_SPLIT_FSM5    10
24844 #define M_CMD_SPLIT_FSM5    0x7U
24845 #define V_CMD_SPLIT_FSM5(x) ((x) << S_CMD_SPLIT_FSM5)
24846 #define G_CMD_SPLIT_FSM5(x) (((x) >> S_CMD_SPLIT_FSM5) & M_CMD_SPLIT_FSM5)
24847 
24848 #define A_MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1 0xe4c0
24849 
24850 #define S_WR_DATA_EXT_FIFO_CNT6    30
24851 #define M_WR_DATA_EXT_FIFO_CNT6    0x3U
24852 #define V_WR_DATA_EXT_FIFO_CNT6(x) ((x) << S_WR_DATA_EXT_FIFO_CNT6)
24853 #define G_WR_DATA_EXT_FIFO_CNT6(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT6) & M_WR_DATA_EXT_FIFO_CNT6)
24854 
24855 #define S_WR_CMD_TAG_FIFO_CNT6    26
24856 #define M_WR_CMD_TAG_FIFO_CNT6    0xfU
24857 #define V_WR_CMD_TAG_FIFO_CNT6(x) ((x) << S_WR_CMD_TAG_FIFO_CNT6)
24858 #define G_WR_CMD_TAG_FIFO_CNT6(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT6) & M_WR_CMD_TAG_FIFO_CNT6)
24859 
24860 #define S_WR_DATA_512B_FIFO_CNT6    18
24861 #define M_WR_DATA_512B_FIFO_CNT6    0xffU
24862 #define V_WR_DATA_512B_FIFO_CNT6(x) ((x) << S_WR_DATA_512B_FIFO_CNT6)
24863 #define G_WR_DATA_512B_FIFO_CNT6(x) (((x) >> S_WR_DATA_512B_FIFO_CNT6) & M_WR_DATA_512B_FIFO_CNT6)
24864 
24865 #define S_RD_DATA_ALIGN_FSM6    17
24866 #define V_RD_DATA_ALIGN_FSM6(x) ((x) << S_RD_DATA_ALIGN_FSM6)
24867 #define F_RD_DATA_ALIGN_FSM6    V_RD_DATA_ALIGN_FSM6(1U)
24868 
24869 #define S_RD_DATA_FETCH_FSM6    16
24870 #define V_RD_DATA_FETCH_FSM6(x) ((x) << S_RD_DATA_FETCH_FSM6)
24871 #define F_RD_DATA_FETCH_FSM6    V_RD_DATA_FETCH_FSM6(1U)
24872 
24873 #define S_COHERENCY_TX_FSM6    15
24874 #define V_COHERENCY_TX_FSM6(x) ((x) << S_COHERENCY_TX_FSM6)
24875 #define F_COHERENCY_TX_FSM6    V_COHERENCY_TX_FSM6(1U)
24876 
24877 #define S_COHERENCY_RX_FSM6    14
24878 #define V_COHERENCY_RX_FSM6(x) ((x) << S_COHERENCY_RX_FSM6)
24879 #define F_COHERENCY_RX_FSM6    V_COHERENCY_RX_FSM6(1U)
24880 
24881 #define S_ARB_REQ_FSM6    13
24882 #define V_ARB_REQ_FSM6(x) ((x) << S_ARB_REQ_FSM6)
24883 #define F_ARB_REQ_FSM6    V_ARB_REQ_FSM6(1U)
24884 
24885 #define S_CMD_SPLIT_FSM6    10
24886 #define M_CMD_SPLIT_FSM6    0x7U
24887 #define V_CMD_SPLIT_FSM6(x) ((x) << S_CMD_SPLIT_FSM6)
24888 #define G_CMD_SPLIT_FSM6(x) (((x) >> S_CMD_SPLIT_FSM6) & M_CMD_SPLIT_FSM6)
24889 
24890 #define A_MA_LE_CLIENT_INTERFACE_INTERNAL_REG1 0xe4e0
24891 
24892 #define S_WR_DATA_EXT_FIFO_CNT7    30
24893 #define M_WR_DATA_EXT_FIFO_CNT7    0x3U
24894 #define V_WR_DATA_EXT_FIFO_CNT7(x) ((x) << S_WR_DATA_EXT_FIFO_CNT7)
24895 #define G_WR_DATA_EXT_FIFO_CNT7(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT7) & M_WR_DATA_EXT_FIFO_CNT7)
24896 
24897 #define S_WR_CMD_TAG_FIFO_CNT7    26
24898 #define M_WR_CMD_TAG_FIFO_CNT7    0xfU
24899 #define V_WR_CMD_TAG_FIFO_CNT7(x) ((x) << S_WR_CMD_TAG_FIFO_CNT7)
24900 #define G_WR_CMD_TAG_FIFO_CNT7(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT7) & M_WR_CMD_TAG_FIFO_CNT7)
24901 
24902 #define S_WR_DATA_512B_FIFO_CNT7    18
24903 #define M_WR_DATA_512B_FIFO_CNT7    0xffU
24904 #define V_WR_DATA_512B_FIFO_CNT7(x) ((x) << S_WR_DATA_512B_FIFO_CNT7)
24905 #define G_WR_DATA_512B_FIFO_CNT7(x) (((x) >> S_WR_DATA_512B_FIFO_CNT7) & M_WR_DATA_512B_FIFO_CNT7)
24906 
24907 #define S_RD_DATA_ALIGN_FSM7    17
24908 #define V_RD_DATA_ALIGN_FSM7(x) ((x) << S_RD_DATA_ALIGN_FSM7)
24909 #define F_RD_DATA_ALIGN_FSM7    V_RD_DATA_ALIGN_FSM7(1U)
24910 
24911 #define S_RD_DATA_FETCH_FSM7    16
24912 #define V_RD_DATA_FETCH_FSM7(x) ((x) << S_RD_DATA_FETCH_FSM7)
24913 #define F_RD_DATA_FETCH_FSM7    V_RD_DATA_FETCH_FSM7(1U)
24914 
24915 #define S_COHERENCY_TX_FSM7    15
24916 #define V_COHERENCY_TX_FSM7(x) ((x) << S_COHERENCY_TX_FSM7)
24917 #define F_COHERENCY_TX_FSM7    V_COHERENCY_TX_FSM7(1U)
24918 
24919 #define S_COHERENCY_RX_FSM7    14
24920 #define V_COHERENCY_RX_FSM7(x) ((x) << S_COHERENCY_RX_FSM7)
24921 #define F_COHERENCY_RX_FSM7    V_COHERENCY_RX_FSM7(1U)
24922 
24923 #define S_ARB_REQ_FSM7    13
24924 #define V_ARB_REQ_FSM7(x) ((x) << S_ARB_REQ_FSM7)
24925 #define F_ARB_REQ_FSM7    V_ARB_REQ_FSM7(1U)
24926 
24927 #define S_CMD_SPLIT_FSM7    10
24928 #define M_CMD_SPLIT_FSM7    0x7U
24929 #define V_CMD_SPLIT_FSM7(x) ((x) << S_CMD_SPLIT_FSM7)
24930 #define G_CMD_SPLIT_FSM7(x) (((x) >> S_CMD_SPLIT_FSM7) & M_CMD_SPLIT_FSM7)
24931 
24932 #define A_MA_CIM_CLIENT_INTERFACE_INTERNAL_REG1 0xe500
24933 
24934 #define S_WR_DATA_EXT_FIFO_CNT8    30
24935 #define M_WR_DATA_EXT_FIFO_CNT8    0x3U
24936 #define V_WR_DATA_EXT_FIFO_CNT8(x) ((x) << S_WR_DATA_EXT_FIFO_CNT8)
24937 #define G_WR_DATA_EXT_FIFO_CNT8(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT8) & M_WR_DATA_EXT_FIFO_CNT8)
24938 
24939 #define S_WR_CMD_TAG_FIFO_CNT8    26
24940 #define M_WR_CMD_TAG_FIFO_CNT8    0xfU
24941 #define V_WR_CMD_TAG_FIFO_CNT8(x) ((x) << S_WR_CMD_TAG_FIFO_CNT8)
24942 #define G_WR_CMD_TAG_FIFO_CNT8(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT8) & M_WR_CMD_TAG_FIFO_CNT8)
24943 
24944 #define S_WR_DATA_512B_FIFO_CNT8    18
24945 #define M_WR_DATA_512B_FIFO_CNT8    0xffU
24946 #define V_WR_DATA_512B_FIFO_CNT8(x) ((x) << S_WR_DATA_512B_FIFO_CNT8)
24947 #define G_WR_DATA_512B_FIFO_CNT8(x) (((x) >> S_WR_DATA_512B_FIFO_CNT8) & M_WR_DATA_512B_FIFO_CNT8)
24948 
24949 #define S_RD_DATA_ALIGN_FSM8    17
24950 #define V_RD_DATA_ALIGN_FSM8(x) ((x) << S_RD_DATA_ALIGN_FSM8)
24951 #define F_RD_DATA_ALIGN_FSM8    V_RD_DATA_ALIGN_FSM8(1U)
24952 
24953 #define S_RD_DATA_FETCH_FSM8    16
24954 #define V_RD_DATA_FETCH_FSM8(x) ((x) << S_RD_DATA_FETCH_FSM8)
24955 #define F_RD_DATA_FETCH_FSM8    V_RD_DATA_FETCH_FSM8(1U)
24956 
24957 #define S_COHERENCY_TX_FSM8    15
24958 #define V_COHERENCY_TX_FSM8(x) ((x) << S_COHERENCY_TX_FSM8)
24959 #define F_COHERENCY_TX_FSM8    V_COHERENCY_TX_FSM8(1U)
24960 
24961 #define S_COHERENCY_RX_FSM8    14
24962 #define V_COHERENCY_RX_FSM8(x) ((x) << S_COHERENCY_RX_FSM8)
24963 #define F_COHERENCY_RX_FSM8    V_COHERENCY_RX_FSM8(1U)
24964 
24965 #define S_ARB_REQ_FSM8    13
24966 #define V_ARB_REQ_FSM8(x) ((x) << S_ARB_REQ_FSM8)
24967 #define F_ARB_REQ_FSM8    V_ARB_REQ_FSM8(1U)
24968 
24969 #define S_CMD_SPLIT_FSM8    10
24970 #define M_CMD_SPLIT_FSM8    0x7U
24971 #define V_CMD_SPLIT_FSM8(x) ((x) << S_CMD_SPLIT_FSM8)
24972 #define G_CMD_SPLIT_FSM8(x) (((x) >> S_CMD_SPLIT_FSM8) & M_CMD_SPLIT_FSM8)
24973 
24974 #define A_MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG1 0xe520
24975 
24976 #define S_WR_DATA_EXT_FIFO_CNT9    30
24977 #define M_WR_DATA_EXT_FIFO_CNT9    0x3U
24978 #define V_WR_DATA_EXT_FIFO_CNT9(x) ((x) << S_WR_DATA_EXT_FIFO_CNT9)
24979 #define G_WR_DATA_EXT_FIFO_CNT9(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT9) & M_WR_DATA_EXT_FIFO_CNT9)
24980 
24981 #define S_WR_CMD_TAG_FIFO_CNT9    26
24982 #define M_WR_CMD_TAG_FIFO_CNT9    0xfU
24983 #define V_WR_CMD_TAG_FIFO_CNT9(x) ((x) << S_WR_CMD_TAG_FIFO_CNT9)
24984 #define G_WR_CMD_TAG_FIFO_CNT9(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT9) & M_WR_CMD_TAG_FIFO_CNT9)
24985 
24986 #define S_WR_DATA_512B_FIFO_CNT9    18
24987 #define M_WR_DATA_512B_FIFO_CNT9    0xffU
24988 #define V_WR_DATA_512B_FIFO_CNT9(x) ((x) << S_WR_DATA_512B_FIFO_CNT9)
24989 #define G_WR_DATA_512B_FIFO_CNT9(x) (((x) >> S_WR_DATA_512B_FIFO_CNT9) & M_WR_DATA_512B_FIFO_CNT9)
24990 
24991 #define S_RD_DATA_ALIGN_FSM9    17
24992 #define V_RD_DATA_ALIGN_FSM9(x) ((x) << S_RD_DATA_ALIGN_FSM9)
24993 #define F_RD_DATA_ALIGN_FSM9    V_RD_DATA_ALIGN_FSM9(1U)
24994 
24995 #define S_RD_DATA_FETCH_FSM9    16
24996 #define V_RD_DATA_FETCH_FSM9(x) ((x) << S_RD_DATA_FETCH_FSM9)
24997 #define F_RD_DATA_FETCH_FSM9    V_RD_DATA_FETCH_FSM9(1U)
24998 
24999 #define S_COHERENCY_TX_FSM9    15
25000 #define V_COHERENCY_TX_FSM9(x) ((x) << S_COHERENCY_TX_FSM9)
25001 #define F_COHERENCY_TX_FSM9    V_COHERENCY_TX_FSM9(1U)
25002 
25003 #define S_COHERENCY_RX_FSM9    14
25004 #define V_COHERENCY_RX_FSM9(x) ((x) << S_COHERENCY_RX_FSM9)
25005 #define F_COHERENCY_RX_FSM9    V_COHERENCY_RX_FSM9(1U)
25006 
25007 #define S_ARB_REQ_FSM9    13
25008 #define V_ARB_REQ_FSM9(x) ((x) << S_ARB_REQ_FSM9)
25009 #define F_ARB_REQ_FSM9    V_ARB_REQ_FSM9(1U)
25010 
25011 #define S_CMD_SPLIT_FSM9    10
25012 #define M_CMD_SPLIT_FSM9    0x7U
25013 #define V_CMD_SPLIT_FSM9(x) ((x) << S_CMD_SPLIT_FSM9)
25014 #define G_CMD_SPLIT_FSM9(x) (((x) >> S_CMD_SPLIT_FSM9) & M_CMD_SPLIT_FSM9)
25015 
25016 #define A_MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG1 0xe540
25017 
25018 #define S_WR_DATA_EXT_FIFO_CNT10    30
25019 #define M_WR_DATA_EXT_FIFO_CNT10    0x3U
25020 #define V_WR_DATA_EXT_FIFO_CNT10(x) ((x) << S_WR_DATA_EXT_FIFO_CNT10)
25021 #define G_WR_DATA_EXT_FIFO_CNT10(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT10) & M_WR_DATA_EXT_FIFO_CNT10)
25022 
25023 #define S_WR_CMD_TAG_FIFO_CNT10    26
25024 #define M_WR_CMD_TAG_FIFO_CNT10    0xfU
25025 #define V_WR_CMD_TAG_FIFO_CNT10(x) ((x) << S_WR_CMD_TAG_FIFO_CNT10)
25026 #define G_WR_CMD_TAG_FIFO_CNT10(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT10) & M_WR_CMD_TAG_FIFO_CNT10)
25027 
25028 #define S_WR_DATA_512B_FIFO_CNT10    18
25029 #define M_WR_DATA_512B_FIFO_CNT10    0xffU
25030 #define V_WR_DATA_512B_FIFO_CNT10(x) ((x) << S_WR_DATA_512B_FIFO_CNT10)
25031 #define G_WR_DATA_512B_FIFO_CNT10(x) (((x) >> S_WR_DATA_512B_FIFO_CNT10) & M_WR_DATA_512B_FIFO_CNT10)
25032 
25033 #define S_RD_DATA_ALIGN_FSM10    17
25034 #define V_RD_DATA_ALIGN_FSM10(x) ((x) << S_RD_DATA_ALIGN_FSM10)
25035 #define F_RD_DATA_ALIGN_FSM10    V_RD_DATA_ALIGN_FSM10(1U)
25036 
25037 #define S_RD_DATA_FETCH_FSM10    16
25038 #define V_RD_DATA_FETCH_FSM10(x) ((x) << S_RD_DATA_FETCH_FSM10)
25039 #define F_RD_DATA_FETCH_FSM10    V_RD_DATA_FETCH_FSM10(1U)
25040 
25041 #define S_COHERENCY_TX_FSM10    15
25042 #define V_COHERENCY_TX_FSM10(x) ((x) << S_COHERENCY_TX_FSM10)
25043 #define F_COHERENCY_TX_FSM10    V_COHERENCY_TX_FSM10(1U)
25044 
25045 #define S_COHERENCY_RX_FSM10    14
25046 #define V_COHERENCY_RX_FSM10(x) ((x) << S_COHERENCY_RX_FSM10)
25047 #define F_COHERENCY_RX_FSM10    V_COHERENCY_RX_FSM10(1U)
25048 
25049 #define S_ARB_REQ_FSM10    13
25050 #define V_ARB_REQ_FSM10(x) ((x) << S_ARB_REQ_FSM10)
25051 #define F_ARB_REQ_FSM10    V_ARB_REQ_FSM10(1U)
25052 
25053 #define S_CMD_SPLIT_FSM10    10
25054 #define M_CMD_SPLIT_FSM10    0x7U
25055 #define V_CMD_SPLIT_FSM10(x) ((x) << S_CMD_SPLIT_FSM10)
25056 #define G_CMD_SPLIT_FSM10(x) (((x) >> S_CMD_SPLIT_FSM10) & M_CMD_SPLIT_FSM10)
25057 
25058 #define A_MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe560
25059 
25060 #define S_WR_DATA_EXT_FIFO_CNT11    30
25061 #define M_WR_DATA_EXT_FIFO_CNT11    0x3U
25062 #define V_WR_DATA_EXT_FIFO_CNT11(x) ((x) << S_WR_DATA_EXT_FIFO_CNT11)
25063 #define G_WR_DATA_EXT_FIFO_CNT11(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT11) & M_WR_DATA_EXT_FIFO_CNT11)
25064 
25065 #define S_WR_CMD_TAG_FIFO_CNT11    26
25066 #define M_WR_CMD_TAG_FIFO_CNT11    0xfU
25067 #define V_WR_CMD_TAG_FIFO_CNT11(x) ((x) << S_WR_CMD_TAG_FIFO_CNT11)
25068 #define G_WR_CMD_TAG_FIFO_CNT11(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT11) & M_WR_CMD_TAG_FIFO_CNT11)
25069 
25070 #define S_WR_DATA_512B_FIFO_CNT11    18
25071 #define M_WR_DATA_512B_FIFO_CNT11    0xffU
25072 #define V_WR_DATA_512B_FIFO_CNT11(x) ((x) << S_WR_DATA_512B_FIFO_CNT11)
25073 #define G_WR_DATA_512B_FIFO_CNT11(x) (((x) >> S_WR_DATA_512B_FIFO_CNT11) & M_WR_DATA_512B_FIFO_CNT11)
25074 
25075 #define S_RD_DATA_ALIGN_FSM11    17
25076 #define V_RD_DATA_ALIGN_FSM11(x) ((x) << S_RD_DATA_ALIGN_FSM11)
25077 #define F_RD_DATA_ALIGN_FSM11    V_RD_DATA_ALIGN_FSM11(1U)
25078 
25079 #define S_RD_DATA_FETCH_FSM11    16
25080 #define V_RD_DATA_FETCH_FSM11(x) ((x) << S_RD_DATA_FETCH_FSM11)
25081 #define F_RD_DATA_FETCH_FSM11    V_RD_DATA_FETCH_FSM11(1U)
25082 
25083 #define S_COHERENCY_TX_FSM11    15
25084 #define V_COHERENCY_TX_FSM11(x) ((x) << S_COHERENCY_TX_FSM11)
25085 #define F_COHERENCY_TX_FSM11    V_COHERENCY_TX_FSM11(1U)
25086 
25087 #define S_COHERENCY_RX_FSM11    14
25088 #define V_COHERENCY_RX_FSM11(x) ((x) << S_COHERENCY_RX_FSM11)
25089 #define F_COHERENCY_RX_FSM11    V_COHERENCY_RX_FSM11(1U)
25090 
25091 #define S_ARB_REQ_FSM11    13
25092 #define V_ARB_REQ_FSM11(x) ((x) << S_ARB_REQ_FSM11)
25093 #define F_ARB_REQ_FSM11    V_ARB_REQ_FSM11(1U)
25094 
25095 #define S_CMD_SPLIT_FSM11    10
25096 #define M_CMD_SPLIT_FSM11    0x7U
25097 #define V_CMD_SPLIT_FSM11(x) ((x) << S_CMD_SPLIT_FSM11)
25098 #define G_CMD_SPLIT_FSM11(x) (((x) >> S_CMD_SPLIT_FSM11) & M_CMD_SPLIT_FSM11)
25099 
25100 #define A_MA_HMA_CLIENT_INTERFACE_INTERNAL_REG1 0xe580
25101 
25102 #define S_WR_DATA_EXT_FIFO_CNT12    30
25103 #define M_WR_DATA_EXT_FIFO_CNT12    0x3U
25104 #define V_WR_DATA_EXT_FIFO_CNT12(x) ((x) << S_WR_DATA_EXT_FIFO_CNT12)
25105 #define G_WR_DATA_EXT_FIFO_CNT12(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT12) & M_WR_DATA_EXT_FIFO_CNT12)
25106 
25107 #define S_WR_CMD_TAG_FIFO_CNT12    26
25108 #define M_WR_CMD_TAG_FIFO_CNT12    0xfU
25109 #define V_WR_CMD_TAG_FIFO_CNT12(x) ((x) << S_WR_CMD_TAG_FIFO_CNT12)
25110 #define G_WR_CMD_TAG_FIFO_CNT12(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT12) & M_WR_CMD_TAG_FIFO_CNT12)
25111 
25112 #define S_WR_DATA_512B_FIFO_CNT12    18
25113 #define M_WR_DATA_512B_FIFO_CNT12    0xffU
25114 #define V_WR_DATA_512B_FIFO_CNT12(x) ((x) << S_WR_DATA_512B_FIFO_CNT12)
25115 #define G_WR_DATA_512B_FIFO_CNT12(x) (((x) >> S_WR_DATA_512B_FIFO_CNT12) & M_WR_DATA_512B_FIFO_CNT12)
25116 
25117 #define S_RD_DATA_ALIGN_FSM12    17
25118 #define V_RD_DATA_ALIGN_FSM12(x) ((x) << S_RD_DATA_ALIGN_FSM12)
25119 #define F_RD_DATA_ALIGN_FSM12    V_RD_DATA_ALIGN_FSM12(1U)
25120 
25121 #define S_RD_DATA_FETCH_FSM12    16
25122 #define V_RD_DATA_FETCH_FSM12(x) ((x) << S_RD_DATA_FETCH_FSM12)
25123 #define F_RD_DATA_FETCH_FSM12    V_RD_DATA_FETCH_FSM12(1U)
25124 
25125 #define S_COHERENCY_TX_FSM12    15
25126 #define V_COHERENCY_TX_FSM12(x) ((x) << S_COHERENCY_TX_FSM12)
25127 #define F_COHERENCY_TX_FSM12    V_COHERENCY_TX_FSM12(1U)
25128 
25129 #define S_COHERENCY_RX_FSM12    14
25130 #define V_COHERENCY_RX_FSM12(x) ((x) << S_COHERENCY_RX_FSM12)
25131 #define F_COHERENCY_RX_FSM12    V_COHERENCY_RX_FSM12(1U)
25132 
25133 #define S_ARB_REQ_FSM12    13
25134 #define V_ARB_REQ_FSM12(x) ((x) << S_ARB_REQ_FSM12)
25135 #define F_ARB_REQ_FSM12    V_ARB_REQ_FSM12(1U)
25136 
25137 #define S_CMD_SPLIT_FSM12    10
25138 #define M_CMD_SPLIT_FSM12    0x7U
25139 #define V_CMD_SPLIT_FSM12(x) ((x) << S_CMD_SPLIT_FSM12)
25140 #define G_CMD_SPLIT_FSM12(x) (((x) >> S_CMD_SPLIT_FSM12) & M_CMD_SPLIT_FSM12)
25141 
25142 #define A_MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG1 0xe5a0
25143 
25144 #define S_RD_CMD_TAG_FIFO_CNT0    8
25145 #define M_RD_CMD_TAG_FIFO_CNT0    0xffU
25146 #define V_RD_CMD_TAG_FIFO_CNT0(x) ((x) << S_RD_CMD_TAG_FIFO_CNT0)
25147 #define G_RD_CMD_TAG_FIFO_CNT0(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT0) & M_RD_CMD_TAG_FIFO_CNT0)
25148 
25149 #define S_RD_DATA_FIFO_CNT0    0
25150 #define M_RD_DATA_FIFO_CNT0    0xffU
25151 #define V_RD_DATA_FIFO_CNT0(x) ((x) << S_RD_DATA_FIFO_CNT0)
25152 #define G_RD_DATA_FIFO_CNT0(x) (((x) >> S_RD_DATA_FIFO_CNT0) & M_RD_DATA_FIFO_CNT0)
25153 
25154 #define A_MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG1 0xe5c0
25155 
25156 #define S_RD_CMD_TAG_FIFO_CNT1    8
25157 #define M_RD_CMD_TAG_FIFO_CNT1    0xffU
25158 #define V_RD_CMD_TAG_FIFO_CNT1(x) ((x) << S_RD_CMD_TAG_FIFO_CNT1)
25159 #define G_RD_CMD_TAG_FIFO_CNT1(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT1) & M_RD_CMD_TAG_FIFO_CNT1)
25160 
25161 #define S_RD_DATA_FIFO_CNT1    0
25162 #define M_RD_DATA_FIFO_CNT1    0xffU
25163 #define V_RD_DATA_FIFO_CNT1(x) ((x) << S_RD_DATA_FIFO_CNT1)
25164 #define G_RD_DATA_FIFO_CNT1(x) (((x) >> S_RD_DATA_FIFO_CNT1) & M_RD_DATA_FIFO_CNT1)
25165 
25166 #define A_MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG1 0xe5e0
25167 
25168 #define S_RD_CMD_TAG_FIFO_CNT2    8
25169 #define M_RD_CMD_TAG_FIFO_CNT2    0xffU
25170 #define V_RD_CMD_TAG_FIFO_CNT2(x) ((x) << S_RD_CMD_TAG_FIFO_CNT2)
25171 #define G_RD_CMD_TAG_FIFO_CNT2(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT2) & M_RD_CMD_TAG_FIFO_CNT2)
25172 
25173 #define S_RD_DATA_FIFO_CNT2    0
25174 #define M_RD_DATA_FIFO_CNT2    0xffU
25175 #define V_RD_DATA_FIFO_CNT2(x) ((x) << S_RD_DATA_FIFO_CNT2)
25176 #define G_RD_DATA_FIFO_CNT2(x) (((x) >> S_RD_DATA_FIFO_CNT2) & M_RD_DATA_FIFO_CNT2)
25177 
25178 #define A_MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG1 0xe600
25179 
25180 #define S_RD_CMD_TAG_FIFO_CNT3    8
25181 #define M_RD_CMD_TAG_FIFO_CNT3    0xffU
25182 #define V_RD_CMD_TAG_FIFO_CNT3(x) ((x) << S_RD_CMD_TAG_FIFO_CNT3)
25183 #define G_RD_CMD_TAG_FIFO_CNT3(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT3) & M_RD_CMD_TAG_FIFO_CNT3)
25184 
25185 #define S_RD_DATA_FIFO_CNT3    0
25186 #define M_RD_DATA_FIFO_CNT3    0xffU
25187 #define V_RD_DATA_FIFO_CNT3(x) ((x) << S_RD_DATA_FIFO_CNT3)
25188 #define G_RD_DATA_FIFO_CNT3(x) (((x) >> S_RD_DATA_FIFO_CNT3) & M_RD_DATA_FIFO_CNT3)
25189 
25190 #define A_MA_SGE_THREAD_0_CLNT_EXP_WR_CYC_CNT_LO 0xe640
25191 #define A_MA_SGE_THREAD_1_CLNT_EXP_WR_CYC_CNT_LO 0xe660
25192 #define A_MA_ULP_TX_CLNT_EXP_WR_CYC_CNT_LO 0xe680
25193 #define A_MA_ULP_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe6a0
25194 #define A_MA_ULP_TX_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe6c0
25195 #define A_MA_TP_THREAD_0_CLNT_EXP_WR_CYC_CNT_LO 0xe6e0
25196 #define A_MA_TP_THREAD_1_CLNT_EXP_WR_CYC_CNT_LO 0xe700
25197 #define A_MA_LE_CLNT_EXP_WR_CYC_CNT_LO 0xe720
25198 #define A_MA_CIM_CLNT_EXP_WR_CYC_CNT_LO 0xe740
25199 #define A_MA_PCIE_CLNT_EXP_WR_CYC_CNT_LO 0xe760
25200 #define A_MA_PM_TX_CLNT_EXP_WR_CYC_CNT_LO 0xe780
25201 #define A_MA_PM_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe7a0
25202 #define A_MA_HMA_CLNT_EXP_WR_CYC_CNT_LO 0xe7c0
25203 #define A_MA_EDRAM0_WR_REQ_CNT_HI 0xe800
25204 #define A_MA_EDRAM0_WR_REQ_CNT_LO 0xe820
25205 #define A_MA_EDRAM1_WR_REQ_CNT_HI 0xe840
25206 #define A_MA_EDRAM1_WR_REQ_CNT_LO 0xe860
25207 #define A_MA_EXT_MEMORY0_WR_REQ_CNT_HI 0xe880
25208 #define A_MA_EXT_MEMORY0_WR_REQ_CNT_LO 0xe8a0
25209 #define A_MA_EXT_MEMORY1_WR_REQ_CNT_HI 0xe8c0
25210 #define A_MA_EXT_MEMORY1_WR_REQ_CNT_LO 0xe8e0
25211 #define A_MA_EDRAM0_RD_REQ_CNT_HI 0xe900
25212 #define A_MA_EDRAM0_RD_REQ_CNT_LO 0xe920
25213 #define A_MA_EDRAM1_RD_REQ_CNT_HI 0xe940
25214 #define A_MA_EDRAM1_RD_REQ_CNT_LO 0xe960
25215 #define A_MA_EXT_MEMORY0_RD_REQ_CNT_HI 0xe980
25216 #define A_MA_EXT_MEMORY0_RD_REQ_CNT_LO 0xe9a0
25217 #define A_MA_EXT_MEMORY1_RD_REQ_CNT_HI 0xe9c0
25218 #define A_MA_EXT_MEMORY1_RD_REQ_CNT_LO 0xe9e0
25219 #define A_MA_SGE_THREAD_0_CLNT_ACT_RD_CYC_CNT_HI 0xec00
25220 #define A_MA_SGE_THREAD_0_CLNT_ACT_RD_CYC_CNT_LO 0xec20
25221 #define A_MA_SGE_THREAD_1_CLNT_ACT_RD_CYC_CNT_HI 0xec40
25222 #define A_MA_SGE_THREAD_1_CLNT_ACT_RD_CYC_CNT_LO 0xec60
25223 #define A_MA_ULP_TX_CLNT_ACT_RD_CYC_CNT_HI 0xec80
25224 #define A_MA_ULP_TX_CLNT_ACT_RD_CYC_CNT_LO 0xeca0
25225 #define A_MA_ULP_RX_CLNT_ACT_RD_CYC_CNT_HI 0xecc0
25226 #define A_MA_ULP_RX_CLNT_ACT_RD_CYC_CNT_LO 0xece0
25227 #define A_MA_ULP_TX_RX_CLNT_ACT_RD_CYC_CNT_HI 0xed00
25228 #define A_MA_ULP_TX_RX_CLNT_ACT_RD_CYC_CNT_LO 0xed20
25229 #define A_MA_TP_THREAD_0_CLNT_ACT_RD_CYC_CNT_HI 0xed40
25230 #define A_MA_TP_THREAD_0_CLNT_ACT_RD_CYC_CNT_LO 0xed60
25231 #define A_MA_TP_THREAD_1_CLNT_ACT_RD_CYC_CNT_HI 0xed80
25232 #define A_MA_TP_THREAD_1_CLNT_ACT_RD_CYC_CNT_LO 0xeda0
25233 #define A_MA_LE_CLNT_ACT_RD_CYC_CNT_HI 0xedc0
25234 #define A_MA_LE_CLNT_ACT_RD_CYC_CNT_LO 0xede0
25235 #define A_MA_CIM_CLNT_ACT_RD_CYC_CNT_HI 0xee00
25236 #define A_MA_CIM_CLNT_ACT_RD_CYC_CNT_LO 0xee20
25237 #define A_MA_PCIE_CLNT_ACT_RD_CYC_CNT_HI 0xee40
25238 #define A_MA_PCIE_CLNT_ACT_RD_CYC_CNT_LO 0xee60
25239 #define A_MA_PM_TX_CLNT_ACT_RD_CYC_CNT_HI 0xee80
25240 #define A_MA_PM_TX_CLNT_ACT_RD_CYC_CNT_LO 0xeea0
25241 #define A_MA_PM_RX_CLNT_ACT_RD_CYC_CNT_HI 0xeec0
25242 #define A_MA_PM_RX_CLNT_ACT_RD_CYC_CNT_LO 0xeee0
25243 #define A_MA_HMA_CLNT_ACT_RD_CYC_CNT_HI 0xef00
25244 #define A_MA_HMA_CLNT_ACT_RD_CYC_CNT_LO 0xef20
25245 #define A_MA_PM_TX_RD_THROTTLE_STATUS 0xf000
25246 
25247 #define S_PTMAXTRANS    16
25248 #define V_PTMAXTRANS(x) ((x) << S_PTMAXTRANS)
25249 #define F_PTMAXTRANS    V_PTMAXTRANS(1U)
25250 
25251 #define S_PTFLITCNT    0
25252 #define M_PTFLITCNT    0xffU
25253 #define V_PTFLITCNT(x) ((x) << S_PTFLITCNT)
25254 #define G_PTFLITCNT(x) (((x) >> S_PTFLITCNT) & M_PTFLITCNT)
25255 
25256 #define A_MA_PM_RX_RD_THROTTLE_STATUS 0xf020
25257 
25258 #define S_PRMAXTRANS    16
25259 #define V_PRMAXTRANS(x) ((x) << S_PRMAXTRANS)
25260 #define F_PRMAXTRANS    V_PRMAXTRANS(1U)
25261 
25262 #define S_PRFLITCNT    0
25263 #define M_PRFLITCNT    0xffU
25264 #define V_PRFLITCNT(x) ((x) << S_PRFLITCNT)
25265 #define G_PRFLITCNT(x) (((x) >> S_PRFLITCNT) & M_PRFLITCNT)
25266 
25267 /* registers for module EDC_0 */
25268 #define EDC_0_BASE_ADDR 0x7900
25269 
25270 #define A_EDC_REF 0x7900
25271 
25272 #define S_EDC_INST_NUM    18
25273 #define V_EDC_INST_NUM(x) ((x) << S_EDC_INST_NUM)
25274 #define F_EDC_INST_NUM    V_EDC_INST_NUM(1U)
25275 
25276 #define S_ENABLE_PERF    17
25277 #define V_ENABLE_PERF(x) ((x) << S_ENABLE_PERF)
25278 #define F_ENABLE_PERF    V_ENABLE_PERF(1U)
25279 
25280 #define S_ECC_BYPASS    16
25281 #define V_ECC_BYPASS(x) ((x) << S_ECC_BYPASS)
25282 #define F_ECC_BYPASS    V_ECC_BYPASS(1U)
25283 
25284 #define S_REFFREQ    0
25285 #define M_REFFREQ    0xffffU
25286 #define V_REFFREQ(x) ((x) << S_REFFREQ)
25287 #define G_REFFREQ(x) (((x) >> S_REFFREQ) & M_REFFREQ)
25288 
25289 #define A_EDC_BIST_CMD 0x7904
25290 #define A_EDC_BIST_CMD_ADDR 0x7908
25291 #define A_EDC_BIST_CMD_LEN 0x790c
25292 #define A_EDC_BIST_DATA_PATTERN 0x7910
25293 #define A_EDC_BIST_USER_WDATA0 0x7914
25294 #define A_EDC_BIST_USER_WDATA1 0x7918
25295 #define A_EDC_BIST_USER_WDATA2 0x791c
25296 #define A_EDC_BIST_NUM_ERR 0x7920
25297 #define A_EDC_BIST_ERR_FIRST_ADDR 0x7924
25298 #define A_EDC_BIST_STATUS_RDATA 0x7928
25299 #define A_EDC_PAR_ENABLE 0x7970
25300 
25301 #define S_ECC_UE    2
25302 #define V_ECC_UE(x) ((x) << S_ECC_UE)
25303 #define F_ECC_UE    V_ECC_UE(1U)
25304 
25305 #define S_ECC_CE    1
25306 #define V_ECC_CE(x) ((x) << S_ECC_CE)
25307 #define F_ECC_CE    V_ECC_CE(1U)
25308 
25309 #define A_EDC_INT_ENABLE 0x7974
25310 #define A_EDC_INT_CAUSE 0x7978
25311 
25312 #define S_ECC_UE_PAR    5
25313 #define V_ECC_UE_PAR(x) ((x) << S_ECC_UE_PAR)
25314 #define F_ECC_UE_PAR    V_ECC_UE_PAR(1U)
25315 
25316 #define S_ECC_CE_PAR    4
25317 #define V_ECC_CE_PAR(x) ((x) << S_ECC_CE_PAR)
25318 #define F_ECC_CE_PAR    V_ECC_CE_PAR(1U)
25319 
25320 #define S_PERR_PAR_CAUSE    3
25321 #define V_PERR_PAR_CAUSE(x) ((x) << S_PERR_PAR_CAUSE)
25322 #define F_PERR_PAR_CAUSE    V_PERR_PAR_CAUSE(1U)
25323 
25324 #define A_EDC_ECC_STATUS 0x797c
25325 
25326 /* registers for module EDC_1 */
25327 #define EDC_1_BASE_ADDR 0x7980
25328 
25329 /* registers for module HMA */
25330 #define HMA_BASE_ADDR 0x7a00
25331 
25332 /* registers for module CIM */
25333 #define CIM_BASE_ADDR 0x7b00
25334 
25335 #define A_CIM_VF_EXT_MAILBOX_CTRL 0x0
25336 
25337 #define S_VFMBGENERIC    4
25338 #define M_VFMBGENERIC    0xfU
25339 #define V_VFMBGENERIC(x) ((x) << S_VFMBGENERIC)
25340 #define G_VFMBGENERIC(x) (((x) >> S_VFMBGENERIC) & M_VFMBGENERIC)
25341 
25342 #define A_CIM_VF_EXT_MAILBOX_STATUS 0x4
25343 
25344 #define S_MBVFREADY    0
25345 #define V_MBVFREADY(x) ((x) << S_MBVFREADY)
25346 #define F_MBVFREADY    V_MBVFREADY(1U)
25347 
25348 #define A_CIM_PF_MAILBOX_DATA 0x240
25349 #define A_CIM_PF_MAILBOX_CTRL 0x280
25350 
25351 #define S_MBGENERIC    4
25352 #define M_MBGENERIC    0xfffffffU
25353 #define V_MBGENERIC(x) ((x) << S_MBGENERIC)
25354 #define G_MBGENERIC(x) (((x) >> S_MBGENERIC) & M_MBGENERIC)
25355 
25356 #define S_MBMSGVALID    3
25357 #define V_MBMSGVALID(x) ((x) << S_MBMSGVALID)
25358 #define F_MBMSGVALID    V_MBMSGVALID(1U)
25359 
25360 #define S_MBINTREQ    2
25361 #define V_MBINTREQ(x) ((x) << S_MBINTREQ)
25362 #define F_MBINTREQ    V_MBINTREQ(1U)
25363 
25364 #define S_MBOWNER    0
25365 #define M_MBOWNER    0x3U
25366 #define V_MBOWNER(x) ((x) << S_MBOWNER)
25367 #define G_MBOWNER(x) (((x) >> S_MBOWNER) & M_MBOWNER)
25368 
25369 #define A_CIM_PF_MAILBOX_ACC_STATUS 0x284
25370 
25371 #define S_MBWRBUSY    31
25372 #define V_MBWRBUSY(x) ((x) << S_MBWRBUSY)
25373 #define F_MBWRBUSY    V_MBWRBUSY(1U)
25374 
25375 #define A_CIM_PF_HOST_INT_ENABLE 0x288
25376 
25377 #define S_MBMSGRDYINTEN    19
25378 #define V_MBMSGRDYINTEN(x) ((x) << S_MBMSGRDYINTEN)
25379 #define F_MBMSGRDYINTEN    V_MBMSGRDYINTEN(1U)
25380 
25381 #define A_CIM_PF_HOST_INT_CAUSE 0x28c
25382 
25383 #define S_MBMSGRDYINT    19
25384 #define V_MBMSGRDYINT(x) ((x) << S_MBMSGRDYINT)
25385 #define F_MBMSGRDYINT    V_MBMSGRDYINT(1U)
25386 
25387 #define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290
25388 #define A_CIM_BOOT_CFG 0x7b00
25389 
25390 #define S_BOOTADDR    8
25391 #define M_BOOTADDR    0xffffffU
25392 #define V_BOOTADDR(x) ((x) << S_BOOTADDR)
25393 #define G_BOOTADDR(x) (((x) >> S_BOOTADDR) & M_BOOTADDR)
25394 
25395 #define S_UPGEN    2
25396 #define M_UPGEN    0x3fU
25397 #define V_UPGEN(x) ((x) << S_UPGEN)
25398 #define G_UPGEN(x) (((x) >> S_UPGEN) & M_UPGEN)
25399 
25400 #define S_BOOTSDRAM    1
25401 #define V_BOOTSDRAM(x) ((x) << S_BOOTSDRAM)
25402 #define F_BOOTSDRAM    V_BOOTSDRAM(1U)
25403 
25404 #define S_UPCRST    0
25405 #define V_UPCRST(x) ((x) << S_UPCRST)
25406 #define F_UPCRST    V_UPCRST(1U)
25407 
25408 #define A_CIM_FLASH_BASE_ADDR 0x7b04
25409 
25410 #define S_FLASHBASEADDR    6
25411 #define M_FLASHBASEADDR    0x3ffffU
25412 #define V_FLASHBASEADDR(x) ((x) << S_FLASHBASEADDR)
25413 #define G_FLASHBASEADDR(x) (((x) >> S_FLASHBASEADDR) & M_FLASHBASEADDR)
25414 
25415 #define A_CIM_FLASH_ADDR_SIZE 0x7b08
25416 
25417 #define S_FLASHADDRSIZE    4
25418 #define M_FLASHADDRSIZE    0xfffffU
25419 #define V_FLASHADDRSIZE(x) ((x) << S_FLASHADDRSIZE)
25420 #define G_FLASHADDRSIZE(x) (((x) >> S_FLASHADDRSIZE) & M_FLASHADDRSIZE)
25421 
25422 #define A_T7_CIM_PERR_ENABLE 0x7b08
25423 
25424 #define S_T7_MA_CIM_INTFPERR    31
25425 #define V_T7_MA_CIM_INTFPERR(x) ((x) << S_T7_MA_CIM_INTFPERR)
25426 #define F_T7_MA_CIM_INTFPERR    V_T7_MA_CIM_INTFPERR(1U)
25427 
25428 #define S_T7_MBHOSTPARERR    30
25429 #define V_T7_MBHOSTPARERR(x) ((x) << S_T7_MBHOSTPARERR)
25430 #define F_T7_MBHOSTPARERR    V_T7_MBHOSTPARERR(1U)
25431 
25432 #define S_MAARBINVRSPTAG    29
25433 #define V_MAARBINVRSPTAG(x) ((x) << S_MAARBINVRSPTAG)
25434 #define F_MAARBINVRSPTAG    V_MAARBINVRSPTAG(1U)
25435 
25436 #define S_MAARBFIFOPARERR    28
25437 #define V_MAARBFIFOPARERR(x) ((x) << S_MAARBFIFOPARERR)
25438 #define F_MAARBFIFOPARERR    V_MAARBFIFOPARERR(1U)
25439 
25440 #define S_SEMSRAMPARERR    27
25441 #define V_SEMSRAMPARERR(x) ((x) << S_SEMSRAMPARERR)
25442 #define F_SEMSRAMPARERR    V_SEMSRAMPARERR(1U)
25443 
25444 #define S_RSACPARERR    26
25445 #define V_RSACPARERR(x) ((x) << S_RSACPARERR)
25446 #define F_RSACPARERR    V_RSACPARERR(1U)
25447 
25448 #define S_RSADPARERR    25
25449 #define V_RSADPARERR(x) ((x) << S_RSADPARERR)
25450 #define F_RSADPARERR    V_RSADPARERR(1U)
25451 
25452 #define S_T7_PLCIM_MSTRSPDATAPARERR    24
25453 #define V_T7_PLCIM_MSTRSPDATAPARERR(x) ((x) << S_T7_PLCIM_MSTRSPDATAPARERR)
25454 #define F_T7_PLCIM_MSTRSPDATAPARERR    V_T7_PLCIM_MSTRSPDATAPARERR(1U)
25455 
25456 #define S_T7_PCIE2CIMINTFPARERR    23
25457 #define V_T7_PCIE2CIMINTFPARERR(x) ((x) << S_T7_PCIE2CIMINTFPARERR)
25458 #define F_T7_PCIE2CIMINTFPARERR    V_T7_PCIE2CIMINTFPARERR(1U)
25459 
25460 #define S_T7_NCSI2CIMINTFPARERR    22
25461 #define V_T7_NCSI2CIMINTFPARERR(x) ((x) << S_T7_NCSI2CIMINTFPARERR)
25462 #define F_T7_NCSI2CIMINTFPARERR    V_T7_NCSI2CIMINTFPARERR(1U)
25463 
25464 #define S_T7_SGE2CIMINTFPARERR    21
25465 #define V_T7_SGE2CIMINTFPARERR(x) ((x) << S_T7_SGE2CIMINTFPARERR)
25466 #define F_T7_SGE2CIMINTFPARERR    V_T7_SGE2CIMINTFPARERR(1U)
25467 
25468 #define S_T7_ULP2CIMINTFPARERR    20
25469 #define V_T7_ULP2CIMINTFPARERR(x) ((x) << S_T7_ULP2CIMINTFPARERR)
25470 #define F_T7_ULP2CIMINTFPARERR    V_T7_ULP2CIMINTFPARERR(1U)
25471 
25472 #define S_T7_TP2CIMINTFPARERR    19
25473 #define V_T7_TP2CIMINTFPARERR(x) ((x) << S_T7_TP2CIMINTFPARERR)
25474 #define F_T7_TP2CIMINTFPARERR    V_T7_TP2CIMINTFPARERR(1U)
25475 
25476 #define S_CORE7PARERR    18
25477 #define V_CORE7PARERR(x) ((x) << S_CORE7PARERR)
25478 #define F_CORE7PARERR    V_CORE7PARERR(1U)
25479 
25480 #define S_CORE6PARERR    17
25481 #define V_CORE6PARERR(x) ((x) << S_CORE6PARERR)
25482 #define F_CORE6PARERR    V_CORE6PARERR(1U)
25483 
25484 #define S_CORE5PARERR    16
25485 #define V_CORE5PARERR(x) ((x) << S_CORE5PARERR)
25486 #define F_CORE5PARERR    V_CORE5PARERR(1U)
25487 
25488 #define S_CORE4PARERR    15
25489 #define V_CORE4PARERR(x) ((x) << S_CORE4PARERR)
25490 #define F_CORE4PARERR    V_CORE4PARERR(1U)
25491 
25492 #define S_CORE3PARERR    14
25493 #define V_CORE3PARERR(x) ((x) << S_CORE3PARERR)
25494 #define F_CORE3PARERR    V_CORE3PARERR(1U)
25495 
25496 #define S_CORE2PARERR    13
25497 #define V_CORE2PARERR(x) ((x) << S_CORE2PARERR)
25498 #define F_CORE2PARERR    V_CORE2PARERR(1U)
25499 
25500 #define S_CORE1PARERR    12
25501 #define V_CORE1PARERR(x) ((x) << S_CORE1PARERR)
25502 #define F_CORE1PARERR    V_CORE1PARERR(1U)
25503 
25504 #define S_GFTPARERR    10
25505 #define V_GFTPARERR(x) ((x) << S_GFTPARERR)
25506 #define F_GFTPARERR    V_GFTPARERR(1U)
25507 
25508 #define S_MPSRSPDATAPARERR    9
25509 #define V_MPSRSPDATAPARERR(x) ((x) << S_MPSRSPDATAPARERR)
25510 #define F_MPSRSPDATAPARERR    V_MPSRSPDATAPARERR(1U)
25511 
25512 #define S_ER_RSPDATAPARERR    8
25513 #define V_ER_RSPDATAPARERR(x) ((x) << S_ER_RSPDATAPARERR)
25514 #define F_ER_RSPDATAPARERR    V_ER_RSPDATAPARERR(1U)
25515 
25516 #define S_FLOWFIFOPARERR    7
25517 #define V_FLOWFIFOPARERR(x) ((x) << S_FLOWFIFOPARERR)
25518 #define F_FLOWFIFOPARERR    V_FLOWFIFOPARERR(1U)
25519 
25520 #define S_OBQSRAMPARERR    6
25521 #define V_OBQSRAMPARERR(x) ((x) << S_OBQSRAMPARERR)
25522 #define F_OBQSRAMPARERR    V_OBQSRAMPARERR(1U)
25523 
25524 #define S_TIEQOUTPARERR    3
25525 #define V_TIEQOUTPARERR(x) ((x) << S_TIEQOUTPARERR)
25526 #define F_TIEQOUTPARERR    V_TIEQOUTPARERR(1U)
25527 
25528 #define S_TIEQINPARERR    2
25529 #define V_TIEQINPARERR(x) ((x) << S_TIEQINPARERR)
25530 #define F_TIEQINPARERR    V_TIEQINPARERR(1U)
25531 
25532 #define S_PIFRSPPARERR    1
25533 #define V_PIFRSPPARERR(x) ((x) << S_PIFRSPPARERR)
25534 #define F_PIFRSPPARERR    V_PIFRSPPARERR(1U)
25535 
25536 #define S_PIFREQPARERR    0
25537 #define V_PIFREQPARERR(x) ((x) << S_PIFREQPARERR)
25538 #define F_PIFREQPARERR    V_PIFREQPARERR(1U)
25539 
25540 #define A_CIM_EEPROM_BASE_ADDR 0x7b0c
25541 
25542 #define S_EEPROMBASEADDR    6
25543 #define M_EEPROMBASEADDR    0x3ffffU
25544 #define V_EEPROMBASEADDR(x) ((x) << S_EEPROMBASEADDR)
25545 #define G_EEPROMBASEADDR(x) (((x) >> S_EEPROMBASEADDR) & M_EEPROMBASEADDR)
25546 
25547 #define A_CIM_PERR_CAUSE 0x7b0c
25548 #define A_CIM_EEPROM_ADDR_SIZE 0x7b10
25549 
25550 #define S_EEPROMADDRSIZE    4
25551 #define M_EEPROMADDRSIZE    0xfffffU
25552 #define V_EEPROMADDRSIZE(x) ((x) << S_EEPROMADDRSIZE)
25553 #define G_EEPROMADDRSIZE(x) (((x) >> S_EEPROMADDRSIZE) & M_EEPROMADDRSIZE)
25554 
25555 #define A_CIM_SDRAM_BASE_ADDR 0x7b14
25556 
25557 #define S_SDRAMBASEADDR    6
25558 #define M_SDRAMBASEADDR    0x3ffffffU
25559 #define V_SDRAMBASEADDR(x) ((x) << S_SDRAMBASEADDR)
25560 #define G_SDRAMBASEADDR(x) (((x) >> S_SDRAMBASEADDR) & M_SDRAMBASEADDR)
25561 
25562 #define A_CIM_SDRAM_ADDR_SIZE 0x7b18
25563 
25564 #define S_SDRAMADDRSIZE    4
25565 #define M_SDRAMADDRSIZE    0xfffffffU
25566 #define V_SDRAMADDRSIZE(x) ((x) << S_SDRAMADDRSIZE)
25567 #define G_SDRAMADDRSIZE(x) (((x) >> S_SDRAMADDRSIZE) & M_SDRAMADDRSIZE)
25568 
25569 #define A_CIM_EXTMEM2_BASE_ADDR 0x7b1c
25570 
25571 #define S_EXTMEM2BASEADDR    6
25572 #define M_EXTMEM2BASEADDR    0x3ffffffU
25573 #define V_EXTMEM2BASEADDR(x) ((x) << S_EXTMEM2BASEADDR)
25574 #define G_EXTMEM2BASEADDR(x) (((x) >> S_EXTMEM2BASEADDR) & M_EXTMEM2BASEADDR)
25575 
25576 #define A_CIM_EXTMEM2_ADDR_SIZE 0x7b20
25577 
25578 #define S_EXTMEM2ADDRSIZE    4
25579 #define M_EXTMEM2ADDRSIZE    0xfffffffU
25580 #define V_EXTMEM2ADDRSIZE(x) ((x) << S_EXTMEM2ADDRSIZE)
25581 #define G_EXTMEM2ADDRSIZE(x) (((x) >> S_EXTMEM2ADDRSIZE) & M_EXTMEM2ADDRSIZE)
25582 
25583 #define A_CIM_UP_SPARE_INT 0x7b24
25584 
25585 #define S_TDEBUGINT    4
25586 #define V_TDEBUGINT(x) ((x) << S_TDEBUGINT)
25587 #define F_TDEBUGINT    V_TDEBUGINT(1U)
25588 
25589 #define S_BOOTVECSEL    3
25590 #define V_BOOTVECSEL(x) ((x) << S_BOOTVECSEL)
25591 #define F_BOOTVECSEL    V_BOOTVECSEL(1U)
25592 
25593 #define S_UPSPAREINT    0
25594 #define M_UPSPAREINT    0x7U
25595 #define V_UPSPAREINT(x) ((x) << S_UPSPAREINT)
25596 #define G_UPSPAREINT(x) (((x) >> S_UPSPAREINT) & M_UPSPAREINT)
25597 
25598 #define A_CIM_HOST_INT_ENABLE 0x7b28
25599 
25600 #define S_TIEQOUTPARERRINTEN    20
25601 #define V_TIEQOUTPARERRINTEN(x) ((x) << S_TIEQOUTPARERRINTEN)
25602 #define F_TIEQOUTPARERRINTEN    V_TIEQOUTPARERRINTEN(1U)
25603 
25604 #define S_TIEQINPARERRINTEN    19
25605 #define V_TIEQINPARERRINTEN(x) ((x) << S_TIEQINPARERRINTEN)
25606 #define F_TIEQINPARERRINTEN    V_TIEQINPARERRINTEN(1U)
25607 
25608 #define S_MBHOSTPARERR    18
25609 #define V_MBHOSTPARERR(x) ((x) << S_MBHOSTPARERR)
25610 #define F_MBHOSTPARERR    V_MBHOSTPARERR(1U)
25611 
25612 #define S_MBUPPARERR    17
25613 #define V_MBUPPARERR(x) ((x) << S_MBUPPARERR)
25614 #define F_MBUPPARERR    V_MBUPPARERR(1U)
25615 
25616 #define S_IBQTP0PARERR    16
25617 #define V_IBQTP0PARERR(x) ((x) << S_IBQTP0PARERR)
25618 #define F_IBQTP0PARERR    V_IBQTP0PARERR(1U)
25619 
25620 #define S_IBQTP1PARERR    15
25621 #define V_IBQTP1PARERR(x) ((x) << S_IBQTP1PARERR)
25622 #define F_IBQTP1PARERR    V_IBQTP1PARERR(1U)
25623 
25624 #define S_IBQULPPARERR    14
25625 #define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR)
25626 #define F_IBQULPPARERR    V_IBQULPPARERR(1U)
25627 
25628 #define S_IBQSGELOPARERR    13
25629 #define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR)
25630 #define F_IBQSGELOPARERR    V_IBQSGELOPARERR(1U)
25631 
25632 #define S_IBQSGEHIPARERR    12
25633 #define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR)
25634 #define F_IBQSGEHIPARERR    V_IBQSGEHIPARERR(1U)
25635 
25636 #define S_IBQNCSIPARERR    11
25637 #define V_IBQNCSIPARERR(x) ((x) << S_IBQNCSIPARERR)
25638 #define F_IBQNCSIPARERR    V_IBQNCSIPARERR(1U)
25639 
25640 #define S_OBQULP0PARERR    10
25641 #define V_OBQULP0PARERR(x) ((x) << S_OBQULP0PARERR)
25642 #define F_OBQULP0PARERR    V_OBQULP0PARERR(1U)
25643 
25644 #define S_OBQULP1PARERR    9
25645 #define V_OBQULP1PARERR(x) ((x) << S_OBQULP1PARERR)
25646 #define F_OBQULP1PARERR    V_OBQULP1PARERR(1U)
25647 
25648 #define S_OBQULP2PARERR    8
25649 #define V_OBQULP2PARERR(x) ((x) << S_OBQULP2PARERR)
25650 #define F_OBQULP2PARERR    V_OBQULP2PARERR(1U)
25651 
25652 #define S_OBQULP3PARERR    7
25653 #define V_OBQULP3PARERR(x) ((x) << S_OBQULP3PARERR)
25654 #define F_OBQULP3PARERR    V_OBQULP3PARERR(1U)
25655 
25656 #define S_OBQSGEPARERR    6
25657 #define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR)
25658 #define F_OBQSGEPARERR    V_OBQSGEPARERR(1U)
25659 
25660 #define S_OBQNCSIPARERR    5
25661 #define V_OBQNCSIPARERR(x) ((x) << S_OBQNCSIPARERR)
25662 #define F_OBQNCSIPARERR    V_OBQNCSIPARERR(1U)
25663 
25664 #define S_TIMER1INTEN    3
25665 #define V_TIMER1INTEN(x) ((x) << S_TIMER1INTEN)
25666 #define F_TIMER1INTEN    V_TIMER1INTEN(1U)
25667 
25668 #define S_TIMER0INTEN    2
25669 #define V_TIMER0INTEN(x) ((x) << S_TIMER0INTEN)
25670 #define F_TIMER0INTEN    V_TIMER0INTEN(1U)
25671 
25672 #define S_PREFDROPINTEN    1
25673 #define V_PREFDROPINTEN(x) ((x) << S_PREFDROPINTEN)
25674 #define F_PREFDROPINTEN    V_PREFDROPINTEN(1U)
25675 
25676 #define S_MA_CIM_INTFPERR    28
25677 #define V_MA_CIM_INTFPERR(x) ((x) << S_MA_CIM_INTFPERR)
25678 #define F_MA_CIM_INTFPERR    V_MA_CIM_INTFPERR(1U)
25679 
25680 #define S_PLCIM_MSTRSPDATAPARERR    27
25681 #define V_PLCIM_MSTRSPDATAPARERR(x) ((x) << S_PLCIM_MSTRSPDATAPARERR)
25682 #define F_PLCIM_MSTRSPDATAPARERR    V_PLCIM_MSTRSPDATAPARERR(1U)
25683 
25684 #define S_NCSI2CIMINTFPARERR    26
25685 #define V_NCSI2CIMINTFPARERR(x) ((x) << S_NCSI2CIMINTFPARERR)
25686 #define F_NCSI2CIMINTFPARERR    V_NCSI2CIMINTFPARERR(1U)
25687 
25688 #define S_SGE2CIMINTFPARERR    25
25689 #define V_SGE2CIMINTFPARERR(x) ((x) << S_SGE2CIMINTFPARERR)
25690 #define F_SGE2CIMINTFPARERR    V_SGE2CIMINTFPARERR(1U)
25691 
25692 #define S_ULP2CIMINTFPARERR    24
25693 #define V_ULP2CIMINTFPARERR(x) ((x) << S_ULP2CIMINTFPARERR)
25694 #define F_ULP2CIMINTFPARERR    V_ULP2CIMINTFPARERR(1U)
25695 
25696 #define S_TP2CIMINTFPARERR    23
25697 #define V_TP2CIMINTFPARERR(x) ((x) << S_TP2CIMINTFPARERR)
25698 #define F_TP2CIMINTFPARERR    V_TP2CIMINTFPARERR(1U)
25699 
25700 #define S_OBQSGERX1PARERR    22
25701 #define V_OBQSGERX1PARERR(x) ((x) << S_OBQSGERX1PARERR)
25702 #define F_OBQSGERX1PARERR    V_OBQSGERX1PARERR(1U)
25703 
25704 #define S_OBQSGERX0PARERR    21
25705 #define V_OBQSGERX0PARERR(x) ((x) << S_OBQSGERX0PARERR)
25706 #define F_OBQSGERX0PARERR    V_OBQSGERX0PARERR(1U)
25707 
25708 #define S_PCIE2CIMINTFPARERR    29
25709 #define V_PCIE2CIMINTFPARERR(x) ((x) << S_PCIE2CIMINTFPARERR)
25710 #define F_PCIE2CIMINTFPARERR    V_PCIE2CIMINTFPARERR(1U)
25711 
25712 #define S_IBQPCIEPARERR    12
25713 #define V_IBQPCIEPARERR(x) ((x) << S_IBQPCIEPARERR)
25714 #define F_IBQPCIEPARERR    V_IBQPCIEPARERR(1U)
25715 
25716 #define S_CORE7ACCINT    22
25717 #define V_CORE7ACCINT(x) ((x) << S_CORE7ACCINT)
25718 #define F_CORE7ACCINT    V_CORE7ACCINT(1U)
25719 
25720 #define S_CORE6ACCINT    21
25721 #define V_CORE6ACCINT(x) ((x) << S_CORE6ACCINT)
25722 #define F_CORE6ACCINT    V_CORE6ACCINT(1U)
25723 
25724 #define S_CORE5ACCINT    20
25725 #define V_CORE5ACCINT(x) ((x) << S_CORE5ACCINT)
25726 #define F_CORE5ACCINT    V_CORE5ACCINT(1U)
25727 
25728 #define S_CORE4ACCINT    19
25729 #define V_CORE4ACCINT(x) ((x) << S_CORE4ACCINT)
25730 #define F_CORE4ACCINT    V_CORE4ACCINT(1U)
25731 
25732 #define S_CORE3ACCINT    18
25733 #define V_CORE3ACCINT(x) ((x) << S_CORE3ACCINT)
25734 #define F_CORE3ACCINT    V_CORE3ACCINT(1U)
25735 
25736 #define S_CORE2ACCINT    17
25737 #define V_CORE2ACCINT(x) ((x) << S_CORE2ACCINT)
25738 #define F_CORE2ACCINT    V_CORE2ACCINT(1U)
25739 
25740 #define S_CORE1ACCINT    16
25741 #define V_CORE1ACCINT(x) ((x) << S_CORE1ACCINT)
25742 #define F_CORE1ACCINT    V_CORE1ACCINT(1U)
25743 
25744 #define S_PERRNONZERO    1
25745 #define V_PERRNONZERO(x) ((x) << S_PERRNONZERO)
25746 #define F_PERRNONZERO    V_PERRNONZERO(1U)
25747 
25748 #define A_CIM_HOST_INT_CAUSE 0x7b2c
25749 
25750 #define S_TIEQOUTPARERRINT    20
25751 #define V_TIEQOUTPARERRINT(x) ((x) << S_TIEQOUTPARERRINT)
25752 #define F_TIEQOUTPARERRINT    V_TIEQOUTPARERRINT(1U)
25753 
25754 #define S_TIEQINPARERRINT    19
25755 #define V_TIEQINPARERRINT(x) ((x) << S_TIEQINPARERRINT)
25756 #define F_TIEQINPARERRINT    V_TIEQINPARERRINT(1U)
25757 
25758 #define S_TIMER1INT    3
25759 #define V_TIMER1INT(x) ((x) << S_TIMER1INT)
25760 #define F_TIMER1INT    V_TIMER1INT(1U)
25761 
25762 #define S_TIMER0INT    2
25763 #define V_TIMER0INT(x) ((x) << S_TIMER0INT)
25764 #define F_TIMER0INT    V_TIMER0INT(1U)
25765 
25766 #define S_PREFDROPINT    1
25767 #define V_PREFDROPINT(x) ((x) << S_PREFDROPINT)
25768 #define F_PREFDROPINT    V_PREFDROPINT(1U)
25769 
25770 #define S_UPACCNONZERO    0
25771 #define V_UPACCNONZERO(x) ((x) << S_UPACCNONZERO)
25772 #define F_UPACCNONZERO    V_UPACCNONZERO(1U)
25773 
25774 #define A_CIM_HOST_UPACC_INT_ENABLE 0x7b30
25775 
25776 #define S_EEPROMWRINTEN    30
25777 #define V_EEPROMWRINTEN(x) ((x) << S_EEPROMWRINTEN)
25778 #define F_EEPROMWRINTEN    V_EEPROMWRINTEN(1U)
25779 
25780 #define S_TIMEOUTMAINTEN    29
25781 #define V_TIMEOUTMAINTEN(x) ((x) << S_TIMEOUTMAINTEN)
25782 #define F_TIMEOUTMAINTEN    V_TIMEOUTMAINTEN(1U)
25783 
25784 #define S_TIMEOUTINTEN    28
25785 #define V_TIMEOUTINTEN(x) ((x) << S_TIMEOUTINTEN)
25786 #define F_TIMEOUTINTEN    V_TIMEOUTINTEN(1U)
25787 
25788 #define S_RSPOVRLOOKUPINTEN    27
25789 #define V_RSPOVRLOOKUPINTEN(x) ((x) << S_RSPOVRLOOKUPINTEN)
25790 #define F_RSPOVRLOOKUPINTEN    V_RSPOVRLOOKUPINTEN(1U)
25791 
25792 #define S_REQOVRLOOKUPINTEN    26
25793 #define V_REQOVRLOOKUPINTEN(x) ((x) << S_REQOVRLOOKUPINTEN)
25794 #define F_REQOVRLOOKUPINTEN    V_REQOVRLOOKUPINTEN(1U)
25795 
25796 #define S_BLKWRPLINTEN    25
25797 #define V_BLKWRPLINTEN(x) ((x) << S_BLKWRPLINTEN)
25798 #define F_BLKWRPLINTEN    V_BLKWRPLINTEN(1U)
25799 
25800 #define S_BLKRDPLINTEN    24
25801 #define V_BLKRDPLINTEN(x) ((x) << S_BLKRDPLINTEN)
25802 #define F_BLKRDPLINTEN    V_BLKRDPLINTEN(1U)
25803 
25804 #define S_SGLWRPLINTEN    23
25805 #define V_SGLWRPLINTEN(x) ((x) << S_SGLWRPLINTEN)
25806 #define F_SGLWRPLINTEN    V_SGLWRPLINTEN(1U)
25807 
25808 #define S_SGLRDPLINTEN    22
25809 #define V_SGLRDPLINTEN(x) ((x) << S_SGLRDPLINTEN)
25810 #define F_SGLRDPLINTEN    V_SGLRDPLINTEN(1U)
25811 
25812 #define S_BLKWRCTLINTEN    21
25813 #define V_BLKWRCTLINTEN(x) ((x) << S_BLKWRCTLINTEN)
25814 #define F_BLKWRCTLINTEN    V_BLKWRCTLINTEN(1U)
25815 
25816 #define S_BLKRDCTLINTEN    20
25817 #define V_BLKRDCTLINTEN(x) ((x) << S_BLKRDCTLINTEN)
25818 #define F_BLKRDCTLINTEN    V_BLKRDCTLINTEN(1U)
25819 
25820 #define S_SGLWRCTLINTEN    19
25821 #define V_SGLWRCTLINTEN(x) ((x) << S_SGLWRCTLINTEN)
25822 #define F_SGLWRCTLINTEN    V_SGLWRCTLINTEN(1U)
25823 
25824 #define S_SGLRDCTLINTEN    18
25825 #define V_SGLRDCTLINTEN(x) ((x) << S_SGLRDCTLINTEN)
25826 #define F_SGLRDCTLINTEN    V_SGLRDCTLINTEN(1U)
25827 
25828 #define S_BLKWREEPROMINTEN    17
25829 #define V_BLKWREEPROMINTEN(x) ((x) << S_BLKWREEPROMINTEN)
25830 #define F_BLKWREEPROMINTEN    V_BLKWREEPROMINTEN(1U)
25831 
25832 #define S_BLKRDEEPROMINTEN    16
25833 #define V_BLKRDEEPROMINTEN(x) ((x) << S_BLKRDEEPROMINTEN)
25834 #define F_BLKRDEEPROMINTEN    V_BLKRDEEPROMINTEN(1U)
25835 
25836 #define S_SGLWREEPROMINTEN    15
25837 #define V_SGLWREEPROMINTEN(x) ((x) << S_SGLWREEPROMINTEN)
25838 #define F_SGLWREEPROMINTEN    V_SGLWREEPROMINTEN(1U)
25839 
25840 #define S_SGLRDEEPROMINTEN    14
25841 #define V_SGLRDEEPROMINTEN(x) ((x) << S_SGLRDEEPROMINTEN)
25842 #define F_SGLRDEEPROMINTEN    V_SGLRDEEPROMINTEN(1U)
25843 
25844 #define S_BLKWRFLASHINTEN    13
25845 #define V_BLKWRFLASHINTEN(x) ((x) << S_BLKWRFLASHINTEN)
25846 #define F_BLKWRFLASHINTEN    V_BLKWRFLASHINTEN(1U)
25847 
25848 #define S_BLKRDFLASHINTEN    12
25849 #define V_BLKRDFLASHINTEN(x) ((x) << S_BLKRDFLASHINTEN)
25850 #define F_BLKRDFLASHINTEN    V_BLKRDFLASHINTEN(1U)
25851 
25852 #define S_SGLWRFLASHINTEN    11
25853 #define V_SGLWRFLASHINTEN(x) ((x) << S_SGLWRFLASHINTEN)
25854 #define F_SGLWRFLASHINTEN    V_SGLWRFLASHINTEN(1U)
25855 
25856 #define S_SGLRDFLASHINTEN    10
25857 #define V_SGLRDFLASHINTEN(x) ((x) << S_SGLRDFLASHINTEN)
25858 #define F_SGLRDFLASHINTEN    V_SGLRDFLASHINTEN(1U)
25859 
25860 #define S_BLKWRBOOTINTEN    9
25861 #define V_BLKWRBOOTINTEN(x) ((x) << S_BLKWRBOOTINTEN)
25862 #define F_BLKWRBOOTINTEN    V_BLKWRBOOTINTEN(1U)
25863 
25864 #define S_BLKRDBOOTINTEN    8
25865 #define V_BLKRDBOOTINTEN(x) ((x) << S_BLKRDBOOTINTEN)
25866 #define F_BLKRDBOOTINTEN    V_BLKRDBOOTINTEN(1U)
25867 
25868 #define S_SGLWRBOOTINTEN    7
25869 #define V_SGLWRBOOTINTEN(x) ((x) << S_SGLWRBOOTINTEN)
25870 #define F_SGLWRBOOTINTEN    V_SGLWRBOOTINTEN(1U)
25871 
25872 #define S_SGLRDBOOTINTEN    6
25873 #define V_SGLRDBOOTINTEN(x) ((x) << S_SGLRDBOOTINTEN)
25874 #define F_SGLRDBOOTINTEN    V_SGLRDBOOTINTEN(1U)
25875 
25876 #define S_ILLWRBEINTEN    5
25877 #define V_ILLWRBEINTEN(x) ((x) << S_ILLWRBEINTEN)
25878 #define F_ILLWRBEINTEN    V_ILLWRBEINTEN(1U)
25879 
25880 #define S_ILLRDBEINTEN    4
25881 #define V_ILLRDBEINTEN(x) ((x) << S_ILLRDBEINTEN)
25882 #define F_ILLRDBEINTEN    V_ILLRDBEINTEN(1U)
25883 
25884 #define S_ILLRDINTEN    3
25885 #define V_ILLRDINTEN(x) ((x) << S_ILLRDINTEN)
25886 #define F_ILLRDINTEN    V_ILLRDINTEN(1U)
25887 
25888 #define S_ILLWRINTEN    2
25889 #define V_ILLWRINTEN(x) ((x) << S_ILLWRINTEN)
25890 #define F_ILLWRINTEN    V_ILLWRINTEN(1U)
25891 
25892 #define S_ILLTRANSINTEN    1
25893 #define V_ILLTRANSINTEN(x) ((x) << S_ILLTRANSINTEN)
25894 #define F_ILLTRANSINTEN    V_ILLTRANSINTEN(1U)
25895 
25896 #define S_RSVDSPACEINTEN    0
25897 #define V_RSVDSPACEINTEN(x) ((x) << S_RSVDSPACEINTEN)
25898 #define F_RSVDSPACEINTEN    V_RSVDSPACEINTEN(1U)
25899 
25900 #define S_CONWRERRINTEN    31
25901 #define V_CONWRERRINTEN(x) ((x) << S_CONWRERRINTEN)
25902 #define F_CONWRERRINTEN    V_CONWRERRINTEN(1U)
25903 
25904 #define A_CIM_HOST_UPACC_INT_CAUSE 0x7b34
25905 
25906 #define S_EEPROMWRINT    30
25907 #define V_EEPROMWRINT(x) ((x) << S_EEPROMWRINT)
25908 #define F_EEPROMWRINT    V_EEPROMWRINT(1U)
25909 
25910 #define S_TIMEOUTMAINT    29
25911 #define V_TIMEOUTMAINT(x) ((x) << S_TIMEOUTMAINT)
25912 #define F_TIMEOUTMAINT    V_TIMEOUTMAINT(1U)
25913 
25914 #define S_TIMEOUTINT    28
25915 #define V_TIMEOUTINT(x) ((x) << S_TIMEOUTINT)
25916 #define F_TIMEOUTINT    V_TIMEOUTINT(1U)
25917 
25918 #define S_RSPOVRLOOKUPINT    27
25919 #define V_RSPOVRLOOKUPINT(x) ((x) << S_RSPOVRLOOKUPINT)
25920 #define F_RSPOVRLOOKUPINT    V_RSPOVRLOOKUPINT(1U)
25921 
25922 #define S_REQOVRLOOKUPINT    26
25923 #define V_REQOVRLOOKUPINT(x) ((x) << S_REQOVRLOOKUPINT)
25924 #define F_REQOVRLOOKUPINT    V_REQOVRLOOKUPINT(1U)
25925 
25926 #define S_BLKWRPLINT    25
25927 #define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
25928 #define F_BLKWRPLINT    V_BLKWRPLINT(1U)
25929 
25930 #define S_BLKRDPLINT    24
25931 #define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
25932 #define F_BLKRDPLINT    V_BLKRDPLINT(1U)
25933 
25934 #define S_SGLWRPLINT    23
25935 #define V_SGLWRPLINT(x) ((x) << S_SGLWRPLINT)
25936 #define F_SGLWRPLINT    V_SGLWRPLINT(1U)
25937 
25938 #define S_SGLRDPLINT    22
25939 #define V_SGLRDPLINT(x) ((x) << S_SGLRDPLINT)
25940 #define F_SGLRDPLINT    V_SGLRDPLINT(1U)
25941 
25942 #define S_BLKWRCTLINT    21
25943 #define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
25944 #define F_BLKWRCTLINT    V_BLKWRCTLINT(1U)
25945 
25946 #define S_BLKRDCTLINT    20
25947 #define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
25948 #define F_BLKRDCTLINT    V_BLKRDCTLINT(1U)
25949 
25950 #define S_SGLWRCTLINT    19
25951 #define V_SGLWRCTLINT(x) ((x) << S_SGLWRCTLINT)
25952 #define F_SGLWRCTLINT    V_SGLWRCTLINT(1U)
25953 
25954 #define S_SGLRDCTLINT    18
25955 #define V_SGLRDCTLINT(x) ((x) << S_SGLRDCTLINT)
25956 #define F_SGLRDCTLINT    V_SGLRDCTLINT(1U)
25957 
25958 #define S_BLKWREEPROMINT    17
25959 #define V_BLKWREEPROMINT(x) ((x) << S_BLKWREEPROMINT)
25960 #define F_BLKWREEPROMINT    V_BLKWREEPROMINT(1U)
25961 
25962 #define S_BLKRDEEPROMINT    16
25963 #define V_BLKRDEEPROMINT(x) ((x) << S_BLKRDEEPROMINT)
25964 #define F_BLKRDEEPROMINT    V_BLKRDEEPROMINT(1U)
25965 
25966 #define S_SGLWREEPROMINT    15
25967 #define V_SGLWREEPROMINT(x) ((x) << S_SGLWREEPROMINT)
25968 #define F_SGLWREEPROMINT    V_SGLWREEPROMINT(1U)
25969 
25970 #define S_SGLRDEEPROMINT    14
25971 #define V_SGLRDEEPROMINT(x) ((x) << S_SGLRDEEPROMINT)
25972 #define F_SGLRDEEPROMINT    V_SGLRDEEPROMINT(1U)
25973 
25974 #define S_BLKWRFLASHINT    13
25975 #define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
25976 #define F_BLKWRFLASHINT    V_BLKWRFLASHINT(1U)
25977 
25978 #define S_BLKRDFLASHINT    12
25979 #define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
25980 #define F_BLKRDFLASHINT    V_BLKRDFLASHINT(1U)
25981 
25982 #define S_SGLWRFLASHINT    11
25983 #define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
25984 #define F_SGLWRFLASHINT    V_SGLWRFLASHINT(1U)
25985 
25986 #define S_SGLRDFLASHINT    10
25987 #define V_SGLRDFLASHINT(x) ((x) << S_SGLRDFLASHINT)
25988 #define F_SGLRDFLASHINT    V_SGLRDFLASHINT(1U)
25989 
25990 #define S_BLKWRBOOTINT    9
25991 #define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
25992 #define F_BLKWRBOOTINT    V_BLKWRBOOTINT(1U)
25993 
25994 #define S_BLKRDBOOTINT    8
25995 #define V_BLKRDBOOTINT(x) ((x) << S_BLKRDBOOTINT)
25996 #define F_BLKRDBOOTINT    V_BLKRDBOOTINT(1U)
25997 
25998 #define S_SGLWRBOOTINT    7
25999 #define V_SGLWRBOOTINT(x) ((x) << S_SGLWRBOOTINT)
26000 #define F_SGLWRBOOTINT    V_SGLWRBOOTINT(1U)
26001 
26002 #define S_SGLRDBOOTINT    6
26003 #define V_SGLRDBOOTINT(x) ((x) << S_SGLRDBOOTINT)
26004 #define F_SGLRDBOOTINT    V_SGLRDBOOTINT(1U)
26005 
26006 #define S_ILLWRBEINT    5
26007 #define V_ILLWRBEINT(x) ((x) << S_ILLWRBEINT)
26008 #define F_ILLWRBEINT    V_ILLWRBEINT(1U)
26009 
26010 #define S_ILLRDBEINT    4
26011 #define V_ILLRDBEINT(x) ((x) << S_ILLRDBEINT)
26012 #define F_ILLRDBEINT    V_ILLRDBEINT(1U)
26013 
26014 #define S_ILLRDINT    3
26015 #define V_ILLRDINT(x) ((x) << S_ILLRDINT)
26016 #define F_ILLRDINT    V_ILLRDINT(1U)
26017 
26018 #define S_ILLWRINT    2
26019 #define V_ILLWRINT(x) ((x) << S_ILLWRINT)
26020 #define F_ILLWRINT    V_ILLWRINT(1U)
26021 
26022 #define S_ILLTRANSINT    1
26023 #define V_ILLTRANSINT(x) ((x) << S_ILLTRANSINT)
26024 #define F_ILLTRANSINT    V_ILLTRANSINT(1U)
26025 
26026 #define S_RSVDSPACEINT    0
26027 #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
26028 #define F_RSVDSPACEINT    V_RSVDSPACEINT(1U)
26029 
26030 #define S_CONWRERRINT    31
26031 #define V_CONWRERRINT(x) ((x) << S_CONWRERRINT)
26032 #define F_CONWRERRINT    V_CONWRERRINT(1U)
26033 
26034 #define A_CIM_UP_INT_ENABLE 0x7b38
26035 
26036 #define S_MSTPLINTEN    4
26037 #define V_MSTPLINTEN(x) ((x) << S_MSTPLINTEN)
26038 #define F_MSTPLINTEN    V_MSTPLINTEN(1U)
26039 
26040 #define S_SEMINT    8
26041 #define V_SEMINT(x) ((x) << S_SEMINT)
26042 #define F_SEMINT    V_SEMINT(1U)
26043 
26044 #define S_RSAINT    7
26045 #define V_RSAINT(x) ((x) << S_RSAINT)
26046 #define F_RSAINT    V_RSAINT(1U)
26047 
26048 #define S_TRNGINT    6
26049 #define V_TRNGINT(x) ((x) << S_TRNGINT)
26050 #define F_TRNGINT    V_TRNGINT(1U)
26051 
26052 #define S_PEERHALTINT    5
26053 #define V_PEERHALTINT(x) ((x) << S_PEERHALTINT)
26054 #define F_PEERHALTINT    V_PEERHALTINT(1U)
26055 
26056 #define A_CIM_UP_INT_CAUSE 0x7b3c
26057 
26058 #define S_MSTPLINT    4
26059 #define V_MSTPLINT(x) ((x) << S_MSTPLINT)
26060 #define F_MSTPLINT    V_MSTPLINT(1U)
26061 
26062 #define A_CIM_UP_ACC_INT_ENABLE 0x7b40
26063 #define A_CIM_UP_ACC_INT_CAUSE 0x7b44
26064 #define A_CIM_QUEUE_CONFIG_REF 0x7b48
26065 
26066 #define S_OBQSELECT    4
26067 #define V_OBQSELECT(x) ((x) << S_OBQSELECT)
26068 #define F_OBQSELECT    V_OBQSELECT(1U)
26069 
26070 #define S_IBQSELECT    3
26071 #define V_IBQSELECT(x) ((x) << S_IBQSELECT)
26072 #define F_IBQSELECT    V_IBQSELECT(1U)
26073 
26074 #define S_QUENUMSELECT    0
26075 #define M_QUENUMSELECT    0x7U
26076 #define V_QUENUMSELECT(x) ((x) << S_QUENUMSELECT)
26077 #define G_QUENUMSELECT(x) (((x) >> S_QUENUMSELECT) & M_QUENUMSELECT)
26078 
26079 #define S_MAPOFFSET    11
26080 #define M_MAPOFFSET    0x1fU
26081 #define V_MAPOFFSET(x) ((x) << S_MAPOFFSET)
26082 #define G_MAPOFFSET(x) (((x) >> S_MAPOFFSET) & M_MAPOFFSET)
26083 
26084 #define S_MAPSELECT    10
26085 #define V_MAPSELECT(x) ((x) << S_MAPSELECT)
26086 #define F_MAPSELECT    V_MAPSELECT(1U)
26087 
26088 #define S_CORESELECT    6
26089 #define M_CORESELECT    0xfU
26090 #define V_CORESELECT(x) ((x) << S_CORESELECT)
26091 #define G_CORESELECT(x) (((x) >> S_CORESELECT) & M_CORESELECT)
26092 
26093 #define S_T7_OBQSELECT    5
26094 #define V_T7_OBQSELECT(x) ((x) << S_T7_OBQSELECT)
26095 #define F_T7_OBQSELECT    V_T7_OBQSELECT(1U)
26096 
26097 #define S_T7_IBQSELECT    4
26098 #define V_T7_IBQSELECT(x) ((x) << S_T7_IBQSELECT)
26099 #define F_T7_IBQSELECT    V_T7_IBQSELECT(1U)
26100 
26101 #define S_T7_QUENUMSELECT    0
26102 #define M_T7_QUENUMSELECT    0xfU
26103 #define V_T7_QUENUMSELECT(x) ((x) << S_T7_QUENUMSELECT)
26104 #define G_T7_QUENUMSELECT(x) (((x) >> S_T7_QUENUMSELECT) & M_T7_QUENUMSELECT)
26105 
26106 #define A_CIM_QUEUE_CONFIG_CTRL 0x7b4c
26107 
26108 #define S_CIMQSIZE    24
26109 #define M_CIMQSIZE    0x3fU
26110 #define V_CIMQSIZE(x) ((x) << S_CIMQSIZE)
26111 #define G_CIMQSIZE(x) (((x) >> S_CIMQSIZE) & M_CIMQSIZE)
26112 
26113 #define S_CIMQBASE    16
26114 #define M_CIMQBASE    0x3fU
26115 #define V_CIMQBASE(x) ((x) << S_CIMQBASE)
26116 #define G_CIMQBASE(x) (((x) >> S_CIMQBASE) & M_CIMQBASE)
26117 
26118 #define S_CIMQDBG8BEN    9
26119 #define V_CIMQDBG8BEN(x) ((x) << S_CIMQDBG8BEN)
26120 #define F_CIMQDBG8BEN    V_CIMQDBG8BEN(1U)
26121 
26122 #define S_QUEFULLTHRSH    0
26123 #define M_QUEFULLTHRSH    0x1ffU
26124 #define V_QUEFULLTHRSH(x) ((x) << S_QUEFULLTHRSH)
26125 #define G_QUEFULLTHRSH(x) (((x) >> S_QUEFULLTHRSH) & M_QUEFULLTHRSH)
26126 
26127 #define S_CIMQ1KEN    30
26128 #define V_CIMQ1KEN(x) ((x) << S_CIMQ1KEN)
26129 #define F_CIMQ1KEN    V_CIMQ1KEN(1U)
26130 
26131 #define A_CIM_HOST_ACC_CTRL 0x7b50
26132 
26133 #define S_HOSTBUSY    17
26134 #define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
26135 #define F_HOSTBUSY    V_HOSTBUSY(1U)
26136 
26137 #define S_HOSTWRITE    16
26138 #define V_HOSTWRITE(x) ((x) << S_HOSTWRITE)
26139 #define F_HOSTWRITE    V_HOSTWRITE(1U)
26140 
26141 #define S_HOSTADDR    0
26142 #define M_HOSTADDR    0xffffU
26143 #define V_HOSTADDR(x) ((x) << S_HOSTADDR)
26144 #define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR)
26145 
26146 #define S_T7_HOSTBUSY    31
26147 #define V_T7_HOSTBUSY(x) ((x) << S_T7_HOSTBUSY)
26148 #define F_T7_HOSTBUSY    V_T7_HOSTBUSY(1U)
26149 
26150 #define S_T7_HOSTWRITE    30
26151 #define V_T7_HOSTWRITE(x) ((x) << S_T7_HOSTWRITE)
26152 #define F_T7_HOSTWRITE    V_T7_HOSTWRITE(1U)
26153 
26154 #define S_HOSTGRPSEL    28
26155 #define M_HOSTGRPSEL    0x3U
26156 #define V_HOSTGRPSEL(x) ((x) << S_HOSTGRPSEL)
26157 #define G_HOSTGRPSEL(x) (((x) >> S_HOSTGRPSEL) & M_HOSTGRPSEL)
26158 
26159 #define S_HOSTCORESEL    24
26160 #define M_HOSTCORESEL    0xfU
26161 #define V_HOSTCORESEL(x) ((x) << S_HOSTCORESEL)
26162 #define G_HOSTCORESEL(x) (((x) >> S_HOSTCORESEL) & M_HOSTCORESEL)
26163 
26164 #define S_T7_HOSTADDR    0
26165 #define M_T7_HOSTADDR    0xffffffU
26166 #define V_T7_HOSTADDR(x) ((x) << S_T7_HOSTADDR)
26167 #define G_T7_HOSTADDR(x) (((x) >> S_T7_HOSTADDR) & M_T7_HOSTADDR)
26168 
26169 #define A_CIM_HOST_ACC_DATA 0x7b54
26170 #define A_CIM_CDEBUGDATA 0x7b58
26171 
26172 #define S_CDEBUGDATAH    16
26173 #define M_CDEBUGDATAH    0xffffU
26174 #define V_CDEBUGDATAH(x) ((x) << S_CDEBUGDATAH)
26175 #define G_CDEBUGDATAH(x) (((x) >> S_CDEBUGDATAH) & M_CDEBUGDATAH)
26176 
26177 #define S_CDEBUGDATAL    0
26178 #define M_CDEBUGDATAL    0xffffU
26179 #define V_CDEBUGDATAL(x) ((x) << S_CDEBUGDATAL)
26180 #define G_CDEBUGDATAL(x) (((x) >> S_CDEBUGDATAL) & M_CDEBUGDATAL)
26181 
26182 #define A_CIM_DEBUG_CFG 0x7b58
26183 
26184 #define S_OR_EN    20
26185 #define V_OR_EN(x) ((x) << S_OR_EN)
26186 #define F_OR_EN    V_OR_EN(1U)
26187 
26188 #define S_USEL    19
26189 #define V_USEL(x) ((x) << S_USEL)
26190 #define F_USEL    V_USEL(1U)
26191 
26192 #define S_HI    18
26193 #define V_HI(x) ((x) << S_HI)
26194 #define F_HI    V_HI(1U)
26195 
26196 #define S_SELH    9
26197 #define M_SELH    0x1ffU
26198 #define V_SELH(x) ((x) << S_SELH)
26199 #define G_SELH(x) (((x) >> S_SELH) & M_SELH)
26200 
26201 #define S_SELL    0
26202 #define M_SELL    0x1ffU
26203 #define V_SELL(x) ((x) << S_SELL)
26204 #define G_SELL(x) (((x) >> S_SELL) & M_SELL)
26205 
26206 #define A_CIM_DEBUG_DATA 0x7b5c
26207 #define A_CIM_IBQ_DBG_CFG 0x7b60
26208 
26209 #define S_IBQDBGADDR    16
26210 #define M_IBQDBGADDR    0xfffU
26211 #define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR)
26212 #define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR)
26213 
26214 #define S_IBQDBGWR    2
26215 #define V_IBQDBGWR(x) ((x) << S_IBQDBGWR)
26216 #define F_IBQDBGWR    V_IBQDBGWR(1U)
26217 
26218 #define S_IBQDBGBUSY    1
26219 #define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY)
26220 #define F_IBQDBGBUSY    V_IBQDBGBUSY(1U)
26221 
26222 #define S_IBQDBGEN    0
26223 #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)
26224 #define F_IBQDBGEN    V_IBQDBGEN(1U)
26225 
26226 #define S_IBQDBGCORE    28
26227 #define M_IBQDBGCORE    0xfU
26228 #define V_IBQDBGCORE(x) ((x) << S_IBQDBGCORE)
26229 #define G_IBQDBGCORE(x) (((x) >> S_IBQDBGCORE) & M_IBQDBGCORE)
26230 
26231 #define S_T7_IBQDBGADDR    12
26232 #define M_T7_IBQDBGADDR    0x1fffU
26233 #define V_T7_IBQDBGADDR(x) ((x) << S_T7_IBQDBGADDR)
26234 #define G_T7_IBQDBGADDR(x) (((x) >> S_T7_IBQDBGADDR) & M_T7_IBQDBGADDR)
26235 
26236 #define S_IBQDBGSTATE    4
26237 #define M_IBQDBGSTATE    0x3U
26238 #define V_IBQDBGSTATE(x) ((x) << S_IBQDBGSTATE)
26239 #define G_IBQDBGSTATE(x) (((x) >> S_IBQDBGSTATE) & M_IBQDBGSTATE)
26240 
26241 #define S_PERRADDRCLR    3
26242 #define V_PERRADDRCLR(x) ((x) << S_PERRADDRCLR)
26243 #define F_PERRADDRCLR    V_PERRADDRCLR(1U)
26244 
26245 #define A_CIM_OBQ_DBG_CFG 0x7b64
26246 
26247 #define S_OBQDBGADDR    16
26248 #define M_OBQDBGADDR    0xfffU
26249 #define V_OBQDBGADDR(x) ((x) << S_OBQDBGADDR)
26250 #define G_OBQDBGADDR(x) (((x) >> S_OBQDBGADDR) & M_OBQDBGADDR)
26251 
26252 #define S_OBQDBGWR    2
26253 #define V_OBQDBGWR(x) ((x) << S_OBQDBGWR)
26254 #define F_OBQDBGWR    V_OBQDBGWR(1U)
26255 
26256 #define S_OBQDBGBUSY    1
26257 #define V_OBQDBGBUSY(x) ((x) << S_OBQDBGBUSY)
26258 #define F_OBQDBGBUSY    V_OBQDBGBUSY(1U)
26259 
26260 #define S_OBQDBGEN    0
26261 #define V_OBQDBGEN(x) ((x) << S_OBQDBGEN)
26262 #define F_OBQDBGEN    V_OBQDBGEN(1U)
26263 
26264 #define S_OBQDBGCORE    28
26265 #define M_OBQDBGCORE    0xfU
26266 #define V_OBQDBGCORE(x) ((x) << S_OBQDBGCORE)
26267 #define G_OBQDBGCORE(x) (((x) >> S_OBQDBGCORE) & M_OBQDBGCORE)
26268 
26269 #define S_T7_OBQDBGADDR    12
26270 #define M_T7_OBQDBGADDR    0x1fffU
26271 #define V_T7_OBQDBGADDR(x) ((x) << S_T7_OBQDBGADDR)
26272 #define G_T7_OBQDBGADDR(x) (((x) >> S_T7_OBQDBGADDR) & M_T7_OBQDBGADDR)
26273 
26274 #define S_OBQDBGSTATE    4
26275 #define M_OBQDBGSTATE    0x3U
26276 #define V_OBQDBGSTATE(x) ((x) << S_OBQDBGSTATE)
26277 #define G_OBQDBGSTATE(x) (((x) >> S_OBQDBGSTATE) & M_OBQDBGSTATE)
26278 
26279 #define A_CIM_IBQ_DBG_DATA 0x7b68
26280 #define A_CIM_OBQ_DBG_DATA 0x7b6c
26281 #define A_CIM_DEBUGCFG 0x7b70
26282 
26283 #define S_POLADBGRDPTR    23
26284 #define M_POLADBGRDPTR    0x1ffU
26285 #define V_POLADBGRDPTR(x) ((x) << S_POLADBGRDPTR)
26286 #define G_POLADBGRDPTR(x) (((x) >> S_POLADBGRDPTR) & M_POLADBGRDPTR)
26287 
26288 #define S_PILADBGRDPTR    14
26289 #define M_PILADBGRDPTR    0x1ffU
26290 #define V_PILADBGRDPTR(x) ((x) << S_PILADBGRDPTR)
26291 #define G_PILADBGRDPTR(x) (((x) >> S_PILADBGRDPTR) & M_PILADBGRDPTR)
26292 
26293 #define S_LAMASKTRIG    13
26294 #define V_LAMASKTRIG(x) ((x) << S_LAMASKTRIG)
26295 #define F_LAMASKTRIG    V_LAMASKTRIG(1U)
26296 
26297 #define S_LADBGEN    12
26298 #define V_LADBGEN(x) ((x) << S_LADBGEN)
26299 #define F_LADBGEN    V_LADBGEN(1U)
26300 
26301 #define S_LAFILLONCE    11
26302 #define V_LAFILLONCE(x) ((x) << S_LAFILLONCE)
26303 #define F_LAFILLONCE    V_LAFILLONCE(1U)
26304 
26305 #define S_LAMASKSTOP    10
26306 #define V_LAMASKSTOP(x) ((x) << S_LAMASKSTOP)
26307 #define F_LAMASKSTOP    V_LAMASKSTOP(1U)
26308 
26309 #define S_DEBUGSELH    5
26310 #define M_DEBUGSELH    0x1fU
26311 #define V_DEBUGSELH(x) ((x) << S_DEBUGSELH)
26312 #define G_DEBUGSELH(x) (((x) >> S_DEBUGSELH) & M_DEBUGSELH)
26313 
26314 #define S_DEBUGSELL    0
26315 #define M_DEBUGSELL    0x1fU
26316 #define V_DEBUGSELL(x) ((x) << S_DEBUGSELL)
26317 #define G_DEBUGSELL(x) (((x) >> S_DEBUGSELL) & M_DEBUGSELL)
26318 
26319 #define A_CIM_DEBUGSTS 0x7b74
26320 
26321 #define S_LARESET    31
26322 #define V_LARESET(x) ((x) << S_LARESET)
26323 #define F_LARESET    V_LARESET(1U)
26324 
26325 #define S_POLADBGWRPTR    16
26326 #define M_POLADBGWRPTR    0x1ffU
26327 #define V_POLADBGWRPTR(x) ((x) << S_POLADBGWRPTR)
26328 #define G_POLADBGWRPTR(x) (((x) >> S_POLADBGWRPTR) & M_POLADBGWRPTR)
26329 
26330 #define S_PILADBGWRPTR    0
26331 #define M_PILADBGWRPTR    0x1ffU
26332 #define V_PILADBGWRPTR(x) ((x) << S_PILADBGWRPTR)
26333 #define G_PILADBGWRPTR(x) (((x) >> S_PILADBGWRPTR) & M_PILADBGWRPTR)
26334 
26335 #define A_CIM_PO_LA_DEBUGDATA 0x7b78
26336 #define A_CIM_PI_LA_DEBUGDATA 0x7b7c
26337 #define A_CIM_PO_LA_MADEBUGDATA 0x7b80
26338 #define A_CIM_PI_LA_MADEBUGDATA 0x7b84
26339 #define A_CIM_PO_LA_PIFSMDEBUGDATA 0x7b8c
26340 #define A_CIM_MEM_ZONE0_VA 0x7b90
26341 
26342 #define S_MEM_ZONE_VA    4
26343 #define M_MEM_ZONE_VA    0xfffffffU
26344 #define V_MEM_ZONE_VA(x) ((x) << S_MEM_ZONE_VA)
26345 #define G_MEM_ZONE_VA(x) (((x) >> S_MEM_ZONE_VA) & M_MEM_ZONE_VA)
26346 
26347 #define A_CIM_MEM_ZONE0_BA 0x7b94
26348 
26349 #define S_MEM_ZONE_BA    6
26350 #define M_MEM_ZONE_BA    0x3ffffffU
26351 #define V_MEM_ZONE_BA(x) ((x) << S_MEM_ZONE_BA)
26352 #define G_MEM_ZONE_BA(x) (((x) >> S_MEM_ZONE_BA) & M_MEM_ZONE_BA)
26353 
26354 #define S_PBT_ENABLE    5
26355 #define V_PBT_ENABLE(x) ((x) << S_PBT_ENABLE)
26356 #define F_PBT_ENABLE    V_PBT_ENABLE(1U)
26357 
26358 #define S_ZONE_DST    0
26359 #define M_ZONE_DST    0x3U
26360 #define V_ZONE_DST(x) ((x) << S_ZONE_DST)
26361 #define G_ZONE_DST(x) (((x) >> S_ZONE_DST) & M_ZONE_DST)
26362 
26363 #define S_THREAD_ID    2
26364 #define M_THREAD_ID    0x7U
26365 #define V_THREAD_ID(x) ((x) << S_THREAD_ID)
26366 #define G_THREAD_ID(x) (((x) >> S_THREAD_ID) & M_THREAD_ID)
26367 
26368 #define A_CIM_MEM_ZONE0_LEN 0x7b98
26369 
26370 #define S_MEM_ZONE_LEN    4
26371 #define M_MEM_ZONE_LEN    0xfffffffU
26372 #define V_MEM_ZONE_LEN(x) ((x) << S_MEM_ZONE_LEN)
26373 #define G_MEM_ZONE_LEN(x) (((x) >> S_MEM_ZONE_LEN) & M_MEM_ZONE_LEN)
26374 
26375 #define A_CIM_MEM_ZONE1_VA 0x7b9c
26376 #define A_CIM_MEM_ZONE1_BA 0x7ba0
26377 #define A_CIM_MEM_ZONE1_LEN 0x7ba4
26378 #define A_CIM_MEM_ZONE2_VA 0x7ba8
26379 #define A_CIM_MEM_ZONE2_BA 0x7bac
26380 #define A_CIM_MEM_ZONE2_LEN 0x7bb0
26381 #define A_CIM_MEM_ZONE3_VA 0x7bb4
26382 #define A_CIM_MEM_ZONE3_BA 0x7bb8
26383 #define A_CIM_MEM_ZONE3_LEN 0x7bbc
26384 #define A_CIM_MEM_ZONE4_VA 0x7bc0
26385 #define A_CIM_MEM_ZONE4_BA 0x7bc4
26386 #define A_CIM_MEM_ZONE4_LEN 0x7bc8
26387 #define A_CIM_MEM_ZONE5_VA 0x7bcc
26388 #define A_CIM_MEM_ZONE5_BA 0x7bd0
26389 #define A_CIM_MEM_ZONE5_LEN 0x7bd4
26390 #define A_CIM_MEM_ZONE6_VA 0x7bd8
26391 #define A_CIM_MEM_ZONE6_BA 0x7bdc
26392 #define A_CIM_MEM_ZONE6_LEN 0x7be0
26393 #define A_CIM_MEM_ZONE7_VA 0x7be4
26394 #define A_CIM_MEM_ZONE7_BA 0x7be8
26395 #define A_CIM_MEM_ZONE7_LEN 0x7bec
26396 #define A_CIM_BOOT_LEN 0x7bf0
26397 
26398 #define S_BOOTLEN    4
26399 #define M_BOOTLEN    0xfffffffU
26400 #define V_BOOTLEN(x) ((x) << S_BOOTLEN)
26401 #define G_BOOTLEN(x) (((x) >> S_BOOTLEN) & M_BOOTLEN)
26402 
26403 #define A_CIM_GLB_TIMER_CTL 0x7bf4
26404 
26405 #define S_TIMER1EN    4
26406 #define V_TIMER1EN(x) ((x) << S_TIMER1EN)
26407 #define F_TIMER1EN    V_TIMER1EN(1U)
26408 
26409 #define S_TIMER0EN    3
26410 #define V_TIMER0EN(x) ((x) << S_TIMER0EN)
26411 #define F_TIMER0EN    V_TIMER0EN(1U)
26412 
26413 #define S_TIMEREN    1
26414 #define V_TIMEREN(x) ((x) << S_TIMEREN)
26415 #define F_TIMEREN    V_TIMEREN(1U)
26416 
26417 #define A_CIM_GLB_TIMER 0x7bf8
26418 #define A_CIM_GLB_TIMER_TICK 0x7bfc
26419 
26420 #define S_GLBLTTICK    0
26421 #define M_GLBLTTICK    0xffffU
26422 #define V_GLBLTTICK(x) ((x) << S_GLBLTTICK)
26423 #define G_GLBLTTICK(x) (((x) >> S_GLBLTTICK) & M_GLBLTTICK)
26424 
26425 #define A_CIM_TIMER0 0x7c00
26426 #define A_CIM_TIMER1 0x7c04
26427 #define A_CIM_DEBUG_ADDR_TIMEOUT 0x7c08
26428 
26429 #define S_DADDRTIMEOUT    2
26430 #define M_DADDRTIMEOUT    0x3fffffffU
26431 #define V_DADDRTIMEOUT(x) ((x) << S_DADDRTIMEOUT)
26432 #define G_DADDRTIMEOUT(x) (((x) >> S_DADDRTIMEOUT) & M_DADDRTIMEOUT)
26433 
26434 #define S_DADDRTIMEOUTTYPE    0
26435 #define M_DADDRTIMEOUTTYPE    0x3U
26436 #define V_DADDRTIMEOUTTYPE(x) ((x) << S_DADDRTIMEOUTTYPE)
26437 #define G_DADDRTIMEOUTTYPE(x) (((x) >> S_DADDRTIMEOUTTYPE) & M_DADDRTIMEOUTTYPE)
26438 
26439 #define A_CIM_DEBUG_ADDR_ILLEGAL 0x7c0c
26440 
26441 #define S_DADDRILLEGAL    2
26442 #define M_DADDRILLEGAL    0x3fffffffU
26443 #define V_DADDRILLEGAL(x) ((x) << S_DADDRILLEGAL)
26444 #define G_DADDRILLEGAL(x) (((x) >> S_DADDRILLEGAL) & M_DADDRILLEGAL)
26445 
26446 #define S_DADDRILLEGALTYPE    0
26447 #define M_DADDRILLEGALTYPE    0x3U
26448 #define V_DADDRILLEGALTYPE(x) ((x) << S_DADDRILLEGALTYPE)
26449 #define G_DADDRILLEGALTYPE(x) (((x) >> S_DADDRILLEGALTYPE) & M_DADDRILLEGALTYPE)
26450 
26451 #define A_CIM_DEBUG_PIF_CAUSE_MASK 0x7c10
26452 
26453 #define S_DPIFHOSTMASK    0
26454 #define M_DPIFHOSTMASK    0x1fffffU
26455 #define V_DPIFHOSTMASK(x) ((x) << S_DPIFHOSTMASK)
26456 #define G_DPIFHOSTMASK(x) (((x) >> S_DPIFHOSTMASK) & M_DPIFHOSTMASK)
26457 
26458 #define S_T5_DPIFHOSTMASK    0
26459 #define M_T5_DPIFHOSTMASK    0x1fffffffU
26460 #define V_T5_DPIFHOSTMASK(x) ((x) << S_T5_DPIFHOSTMASK)
26461 #define G_T5_DPIFHOSTMASK(x) (((x) >> S_T5_DPIFHOSTMASK) & M_T5_DPIFHOSTMASK)
26462 
26463 #define S_T6_T5_DPIFHOSTMASK    0
26464 #define M_T6_T5_DPIFHOSTMASK    0x3fffffffU
26465 #define V_T6_T5_DPIFHOSTMASK(x) ((x) << S_T6_T5_DPIFHOSTMASK)
26466 #define G_T6_T5_DPIFHOSTMASK(x) (((x) >> S_T6_T5_DPIFHOSTMASK) & M_T6_T5_DPIFHOSTMASK)
26467 
26468 #define A_CIM_DEBUG_PIF_UPACC_CAUSE_MASK 0x7c14
26469 
26470 #define S_DPIFHUPAMASK    0
26471 #define M_DPIFHUPAMASK    0x7fffffffU
26472 #define V_DPIFHUPAMASK(x) ((x) << S_DPIFHUPAMASK)
26473 #define G_DPIFHUPAMASK(x) (((x) >> S_DPIFHUPAMASK) & M_DPIFHUPAMASK)
26474 
26475 #define A_CIM_DEBUG_UP_CAUSE_MASK 0x7c18
26476 
26477 #define S_DUPMASK    0
26478 #define M_DUPMASK    0x1fffffU
26479 #define V_DUPMASK(x) ((x) << S_DUPMASK)
26480 #define G_DUPMASK(x) (((x) >> S_DUPMASK) & M_DUPMASK)
26481 
26482 #define S_T5_DUPMASK    0
26483 #define M_T5_DUPMASK    0x1fffffffU
26484 #define V_T5_DUPMASK(x) ((x) << S_T5_DUPMASK)
26485 #define G_T5_DUPMASK(x) (((x) >> S_T5_DUPMASK) & M_T5_DUPMASK)
26486 
26487 #define S_T6_T5_DUPMASK    0
26488 #define M_T6_T5_DUPMASK    0x3fffffffU
26489 #define V_T6_T5_DUPMASK(x) ((x) << S_T6_T5_DUPMASK)
26490 #define G_T6_T5_DUPMASK(x) (((x) >> S_T6_T5_DUPMASK) & M_T6_T5_DUPMASK)
26491 
26492 #define A_CIM_DEBUG_UP_UPACC_CAUSE_MASK 0x7c1c
26493 
26494 #define S_DUPUACCMASK    0
26495 #define M_DUPUACCMASK    0x7fffffffU
26496 #define V_DUPUACCMASK(x) ((x) << S_DUPUACCMASK)
26497 #define G_DUPUACCMASK(x) (((x) >> S_DUPUACCMASK) & M_DUPUACCMASK)
26498 
26499 #define A_CIM_PERR_INJECT 0x7c20
26500 #define A_CIM_FPGA_ROM_EFUSE_CMD 0x7c20
26501 #define A_CIM_PERR_ENABLE 0x7c24
26502 
26503 #define S_PERREN    0
26504 #define M_PERREN    0x1fffffU
26505 #define V_PERREN(x) ((x) << S_PERREN)
26506 #define G_PERREN(x) (((x) >> S_PERREN) & M_PERREN)
26507 
26508 #define S_T5_PERREN    0
26509 #define M_T5_PERREN    0x1fffffffU
26510 #define V_T5_PERREN(x) ((x) << S_T5_PERREN)
26511 #define G_T5_PERREN(x) (((x) >> S_T5_PERREN) & M_T5_PERREN)
26512 
26513 #define S_T6_T5_PERREN    0
26514 #define M_T6_T5_PERREN    0x3fffffffU
26515 #define V_T6_T5_PERREN(x) ((x) << S_T6_T5_PERREN)
26516 #define G_T6_T5_PERREN(x) (((x) >> S_T6_T5_PERREN) & M_T6_T5_PERREN)
26517 
26518 #define A_CIM_FPGA_ROM_EFUSE_DATA 0x7c24
26519 #define A_CIM_EEPROM_BUSY_BIT 0x7c28
26520 
26521 #define S_EEPROMBUSY    0
26522 #define V_EEPROMBUSY(x) ((x) << S_EEPROMBUSY)
26523 #define F_EEPROMBUSY    V_EEPROMBUSY(1U)
26524 
26525 #define A_CIM_MA_TIMER_EN 0x7c2c
26526 
26527 #define S_MA_TIMER_ENABLE    0
26528 #define V_MA_TIMER_ENABLE(x) ((x) << S_MA_TIMER_ENABLE)
26529 #define F_MA_TIMER_ENABLE    V_MA_TIMER_ENABLE(1U)
26530 
26531 #define S_SLOW_TIMER_ENABLE    1
26532 #define V_SLOW_TIMER_ENABLE(x) ((x) << S_SLOW_TIMER_ENABLE)
26533 #define F_SLOW_TIMER_ENABLE    V_SLOW_TIMER_ENABLE(1U)
26534 
26535 #define S_FLASHWRPAGEMORE    5
26536 #define V_FLASHWRPAGEMORE(x) ((x) << S_FLASHWRPAGEMORE)
26537 #define F_FLASHWRPAGEMORE    V_FLASHWRPAGEMORE(1U)
26538 
26539 #define S_FLASHWRENABLE    4
26540 #define V_FLASHWRENABLE(x) ((x) << S_FLASHWRENABLE)
26541 #define F_FLASHWRENABLE    V_FLASHWRENABLE(1U)
26542 
26543 #define S_FLASHMOREENABLE    3
26544 #define V_FLASHMOREENABLE(x) ((x) << S_FLASHMOREENABLE)
26545 #define F_FLASHMOREENABLE    V_FLASHMOREENABLE(1U)
26546 
26547 #define S_WR_RESP_ENABLE    2
26548 #define V_WR_RESP_ENABLE(x) ((x) << S_WR_RESP_ENABLE)
26549 #define F_WR_RESP_ENABLE    V_WR_RESP_ENABLE(1U)
26550 
26551 #define A_CIM_UP_PO_SINGLE_OUTSTANDING 0x7c30
26552 
26553 #define S_UP_PO_SINGLE_OUTSTANDING    0
26554 #define V_UP_PO_SINGLE_OUTSTANDING(x) ((x) << S_UP_PO_SINGLE_OUTSTANDING)
26555 #define F_UP_PO_SINGLE_OUTSTANDING    V_UP_PO_SINGLE_OUTSTANDING(1U)
26556 
26557 #define A_CIM_CIM_DEBUG_SPARE 0x7c34
26558 #define A_CIM_UP_OPERATION_FREQ 0x7c38
26559 #define A_CIM_CIM_IBQ_ERR_CODE 0x7c3c
26560 
26561 #define S_CIM_ULP_TX_PKT_ERR_CODE    16
26562 #define M_CIM_ULP_TX_PKT_ERR_CODE    0xffU
26563 #define V_CIM_ULP_TX_PKT_ERR_CODE(x) ((x) << S_CIM_ULP_TX_PKT_ERR_CODE)
26564 #define G_CIM_ULP_TX_PKT_ERR_CODE(x) (((x) >> S_CIM_ULP_TX_PKT_ERR_CODE) & M_CIM_ULP_TX_PKT_ERR_CODE)
26565 
26566 #define S_CIM_SGE1_PKT_ERR_CODE    8
26567 #define M_CIM_SGE1_PKT_ERR_CODE    0xffU
26568 #define V_CIM_SGE1_PKT_ERR_CODE(x) ((x) << S_CIM_SGE1_PKT_ERR_CODE)
26569 #define G_CIM_SGE1_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE1_PKT_ERR_CODE) & M_CIM_SGE1_PKT_ERR_CODE)
26570 
26571 #define S_CIM_SGE0_PKT_ERR_CODE    0
26572 #define M_CIM_SGE0_PKT_ERR_CODE    0xffU
26573 #define V_CIM_SGE0_PKT_ERR_CODE(x) ((x) << S_CIM_SGE0_PKT_ERR_CODE)
26574 #define G_CIM_SGE0_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE0_PKT_ERR_CODE) & M_CIM_SGE0_PKT_ERR_CODE)
26575 
26576 #define S_CIM_PCIE_PKT_ERR_CODE    8
26577 #define M_CIM_PCIE_PKT_ERR_CODE    0xffU
26578 #define V_CIM_PCIE_PKT_ERR_CODE(x) ((x) << S_CIM_PCIE_PKT_ERR_CODE)
26579 #define G_CIM_PCIE_PKT_ERR_CODE(x) (((x) >> S_CIM_PCIE_PKT_ERR_CODE) & M_CIM_PCIE_PKT_ERR_CODE)
26580 
26581 #define A_CIM_IBQ_DBG_WAIT_COUNTER 0x7c40
26582 #define A_CIM_QUE_PERR_ADDR 0x7c40
26583 
26584 #define S_IBQPERRADDR    16
26585 #define M_IBQPERRADDR    0xfffU
26586 #define V_IBQPERRADDR(x) ((x) << S_IBQPERRADDR)
26587 #define G_IBQPERRADDR(x) (((x) >> S_IBQPERRADDR) & M_IBQPERRADDR)
26588 
26589 #define S_OBQPERRADDR    0
26590 #define M_OBQPERRADDR    0xfffU
26591 #define V_OBQPERRADDR(x) ((x) << S_OBQPERRADDR)
26592 #define G_OBQPERRADDR(x) (((x) >> S_OBQPERRADDR) & M_OBQPERRADDR)
26593 
26594 #define A_CIM_PIO_UP_MST_CFG_SEL 0x7c44
26595 
26596 #define S_PIO_UP_MST_CFG_SEL    0
26597 #define V_PIO_UP_MST_CFG_SEL(x) ((x) << S_PIO_UP_MST_CFG_SEL)
26598 #define F_PIO_UP_MST_CFG_SEL    V_PIO_UP_MST_CFG_SEL(1U)
26599 
26600 #define A_CIM_CGEN 0x7c48
26601 
26602 #define S_TSCH_CGEN    0
26603 #define V_TSCH_CGEN(x) ((x) << S_TSCH_CGEN)
26604 #define F_TSCH_CGEN    V_TSCH_CGEN(1U)
26605 
26606 #define A_CIM_QUEUE_FEATURE_DISABLE 0x7c4c
26607 
26608 #define S_OBQ_THROUTTLE_ON_EOP    4
26609 #define V_OBQ_THROUTTLE_ON_EOP(x) ((x) << S_OBQ_THROUTTLE_ON_EOP)
26610 #define F_OBQ_THROUTTLE_ON_EOP    V_OBQ_THROUTTLE_ON_EOP(1U)
26611 
26612 #define S_OBQ_READ_CTL_PERF_MODE_DISABLE    3
26613 #define V_OBQ_READ_CTL_PERF_MODE_DISABLE(x) ((x) << S_OBQ_READ_CTL_PERF_MODE_DISABLE)
26614 #define F_OBQ_READ_CTL_PERF_MODE_DISABLE    V_OBQ_READ_CTL_PERF_MODE_DISABLE(1U)
26615 
26616 #define S_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE    2
26617 #define V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(x) ((x) << S_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE)
26618 #define F_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE    V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(1U)
26619 
26620 #define S_IBQ_RRA_DSBL    1
26621 #define V_IBQ_RRA_DSBL(x) ((x) << S_IBQ_RRA_DSBL)
26622 #define F_IBQ_RRA_DSBL    V_IBQ_RRA_DSBL(1U)
26623 
26624 #define S_IBQ_SKID_FIFO_EOP_FLSH_DSBL    0
26625 #define V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(x) ((x) << S_IBQ_SKID_FIFO_EOP_FLSH_DSBL)
26626 #define F_IBQ_SKID_FIFO_EOP_FLSH_DSBL    V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(1U)
26627 
26628 #define S_PCIE_OBQ_IF_DISABLE    5
26629 #define V_PCIE_OBQ_IF_DISABLE(x) ((x) << S_PCIE_OBQ_IF_DISABLE)
26630 #define F_PCIE_OBQ_IF_DISABLE    V_PCIE_OBQ_IF_DISABLE(1U)
26631 
26632 #define S_ULP_OBQ_SIZE    8
26633 #define M_ULP_OBQ_SIZE    0x3U
26634 #define V_ULP_OBQ_SIZE(x) ((x) << S_ULP_OBQ_SIZE)
26635 #define G_ULP_OBQ_SIZE(x) (((x) >> S_ULP_OBQ_SIZE) & M_ULP_OBQ_SIZE)
26636 
26637 #define S_TP_IBQ_SIZE    6
26638 #define M_TP_IBQ_SIZE    0x3U
26639 #define V_TP_IBQ_SIZE(x) ((x) << S_TP_IBQ_SIZE)
26640 #define G_TP_IBQ_SIZE(x) (((x) >> S_TP_IBQ_SIZE) & M_TP_IBQ_SIZE)
26641 
26642 #define S_OBQ_EOM_ENABLE    5
26643 #define V_OBQ_EOM_ENABLE(x) ((x) << S_OBQ_EOM_ENABLE)
26644 #define F_OBQ_EOM_ENABLE    V_OBQ_EOM_ENABLE(1U)
26645 
26646 #define A_CIM_CGEN_GLOBAL 0x7c50
26647 
26648 #define S_CGEN_GLOBAL    0
26649 #define V_CGEN_GLOBAL(x) ((x) << S_CGEN_GLOBAL)
26650 #define F_CGEN_GLOBAL    V_CGEN_GLOBAL(1U)
26651 
26652 #define A_CIM_DPSLP_EN 0x7c54
26653 
26654 #define S_PIFDBGLA_DPSLP_EN    0
26655 #define V_PIFDBGLA_DPSLP_EN(x) ((x) << S_PIFDBGLA_DPSLP_EN)
26656 #define F_PIFDBGLA_DPSLP_EN    V_PIFDBGLA_DPSLP_EN(1U)
26657 
26658 #define A_CIM_GFT_CMM_CONFIG 0x7c58
26659 
26660 #define S_GLFL    31
26661 #define V_GLFL(x) ((x) << S_GLFL)
26662 #define F_GLFL    V_GLFL(1U)
26663 
26664 #define S_T7_WRCNTIDLE    16
26665 #define M_T7_WRCNTIDLE    0x7fffU
26666 #define V_T7_WRCNTIDLE(x) ((x) << S_T7_WRCNTIDLE)
26667 #define G_T7_WRCNTIDLE(x) (((x) >> S_T7_WRCNTIDLE) & M_T7_WRCNTIDLE)
26668 
26669 #define A_CIM_GFT_CONFIG 0x7c5c
26670 
26671 #define S_GFTMABASE    16
26672 #define M_GFTMABASE    0xffffU
26673 #define V_GFTMABASE(x) ((x) << S_GFTMABASE)
26674 #define G_GFTMABASE(x) (((x) >> S_GFTMABASE) & M_GFTMABASE)
26675 
26676 #define S_GFTHASHTBLSIZE    12
26677 #define M_GFTHASHTBLSIZE    0xfU
26678 #define V_GFTHASHTBLSIZE(x) ((x) << S_GFTHASHTBLSIZE)
26679 #define G_GFTHASHTBLSIZE(x) (((x) >> S_GFTHASHTBLSIZE) & M_GFTHASHTBLSIZE)
26680 
26681 #define S_GFTTCAMPRIORITY    11
26682 #define V_GFTTCAMPRIORITY(x) ((x) << S_GFTTCAMPRIORITY)
26683 #define F_GFTTCAMPRIORITY    V_GFTTCAMPRIORITY(1U)
26684 
26685 #define S_GFTMATHREADID    8
26686 #define M_GFTMATHREADID    0x7U
26687 #define V_GFTMATHREADID(x) ((x) << S_GFTMATHREADID)
26688 #define G_GFTMATHREADID(x) (((x) >> S_GFTMATHREADID) & M_GFTMATHREADID)
26689 
26690 #define S_GFTTCAMINIT    7
26691 #define V_GFTTCAMINIT(x) ((x) << S_GFTTCAMINIT)
26692 #define F_GFTTCAMINIT    V_GFTTCAMINIT(1U)
26693 
26694 #define S_GFTTCAMINITDONE    6
26695 #define V_GFTTCAMINITDONE(x) ((x) << S_GFTTCAMINITDONE)
26696 #define F_GFTTCAMINITDONE    V_GFTTCAMINITDONE(1U)
26697 
26698 #define S_GFTTBLMODEEN    0
26699 #define V_GFTTBLMODEEN(x) ((x) << S_GFTTBLMODEEN)
26700 #define F_GFTTBLMODEEN    V_GFTTBLMODEEN(1U)
26701 
26702 #define A_CIM_TCAM_BIST_CTRL 0x7c60
26703 
26704 #define S_RST_CB    31
26705 #define V_RST_CB(x) ((x) << S_RST_CB)
26706 #define F_RST_CB    V_RST_CB(1U)
26707 
26708 #define S_CB_START    0
26709 #define M_CB_START    0xfffffffU
26710 #define V_CB_START(x) ((x) << S_CB_START)
26711 #define G_CB_START(x) (((x) >> S_CB_START) & M_CB_START)
26712 
26713 #define A_CIM_TCAM_BIST_CB_PASS 0x7c64
26714 
26715 #define S_CB_PASS    0
26716 #define M_CB_PASS    0xfffffffU
26717 #define V_CB_PASS(x) ((x) << S_CB_PASS)
26718 #define G_CB_PASS(x) (((x) >> S_CB_PASS) & M_CB_PASS)
26719 
26720 #define A_CIM_TCAM_BIST_CB_BUSY 0x7c68
26721 
26722 #define S_CB_BUSY    0
26723 #define M_CB_BUSY    0xfffffffU
26724 #define V_CB_BUSY(x) ((x) << S_CB_BUSY)
26725 #define G_CB_BUSY(x) (((x) >> S_CB_BUSY) & M_CB_BUSY)
26726 
26727 #define A_CIM_GFT_MASK 0x7c70
26728 
26729 /* registers for module TP */
26730 #define TP_BASE_ADDR 0x7d00
26731 
26732 #define A_TP_IN_CONFIG 0x7d00
26733 
26734 #define S_TCPOPTPARSERDISCH3    27
26735 #define V_TCPOPTPARSERDISCH3(x) ((x) << S_TCPOPTPARSERDISCH3)
26736 #define F_TCPOPTPARSERDISCH3    V_TCPOPTPARSERDISCH3(1U)
26737 
26738 #define S_TCPOPTPARSERDISCH2    26
26739 #define V_TCPOPTPARSERDISCH2(x) ((x) << S_TCPOPTPARSERDISCH2)
26740 #define F_TCPOPTPARSERDISCH2    V_TCPOPTPARSERDISCH2(1U)
26741 
26742 #define S_TCPOPTPARSERDISCH1    25
26743 #define V_TCPOPTPARSERDISCH1(x) ((x) << S_TCPOPTPARSERDISCH1)
26744 #define F_TCPOPTPARSERDISCH1    V_TCPOPTPARSERDISCH1(1U)
26745 
26746 #define S_TCPOPTPARSERDISCH0    24
26747 #define V_TCPOPTPARSERDISCH0(x) ((x) << S_TCPOPTPARSERDISCH0)
26748 #define F_TCPOPTPARSERDISCH0    V_TCPOPTPARSERDISCH0(1U)
26749 
26750 #define S_CRCPASSPRT3    23
26751 #define V_CRCPASSPRT3(x) ((x) << S_CRCPASSPRT3)
26752 #define F_CRCPASSPRT3    V_CRCPASSPRT3(1U)
26753 
26754 #define S_CRCPASSPRT2    22
26755 #define V_CRCPASSPRT2(x) ((x) << S_CRCPASSPRT2)
26756 #define F_CRCPASSPRT2    V_CRCPASSPRT2(1U)
26757 
26758 #define S_CRCPASSPRT1    21
26759 #define V_CRCPASSPRT1(x) ((x) << S_CRCPASSPRT1)
26760 #define F_CRCPASSPRT1    V_CRCPASSPRT1(1U)
26761 
26762 #define S_CRCPASSPRT0    20
26763 #define V_CRCPASSPRT0(x) ((x) << S_CRCPASSPRT0)
26764 #define F_CRCPASSPRT0    V_CRCPASSPRT0(1U)
26765 
26766 #define S_VEPAMODE    19
26767 #define V_VEPAMODE(x) ((x) << S_VEPAMODE)
26768 #define F_VEPAMODE    V_VEPAMODE(1U)
26769 
26770 #define S_FIPUPEN    18
26771 #define V_FIPUPEN(x) ((x) << S_FIPUPEN)
26772 #define F_FIPUPEN    V_FIPUPEN(1U)
26773 
26774 #define S_FCOEUPEN    17
26775 #define V_FCOEUPEN(x) ((x) << S_FCOEUPEN)
26776 #define F_FCOEUPEN    V_FCOEUPEN(1U)
26777 
26778 #define S_FCOEENABLE    16
26779 #define V_FCOEENABLE(x) ((x) << S_FCOEENABLE)
26780 #define F_FCOEENABLE    V_FCOEENABLE(1U)
26781 
26782 #define S_IPV6ENABLE    15
26783 #define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE)
26784 #define F_IPV6ENABLE    V_IPV6ENABLE(1U)
26785 
26786 #define S_NICMODE    14
26787 #define V_NICMODE(x) ((x) << S_NICMODE)
26788 #define F_NICMODE    V_NICMODE(1U)
26789 
26790 #define S_ECHECKSUMCHECKTCP    13
26791 #define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP)
26792 #define F_ECHECKSUMCHECKTCP    V_ECHECKSUMCHECKTCP(1U)
26793 
26794 #define S_ECHECKSUMCHECKIP    12
26795 #define V_ECHECKSUMCHECKIP(x) ((x) << S_ECHECKSUMCHECKIP)
26796 #define F_ECHECKSUMCHECKIP    V_ECHECKSUMCHECKIP(1U)
26797 
26798 #define S_EREPORTUDPHDRLEN    11
26799 #define V_EREPORTUDPHDRLEN(x) ((x) << S_EREPORTUDPHDRLEN)
26800 #define F_EREPORTUDPHDRLEN    V_EREPORTUDPHDRLEN(1U)
26801 
26802 #define S_IN_ECPL    10
26803 #define V_IN_ECPL(x) ((x) << S_IN_ECPL)
26804 #define F_IN_ECPL    V_IN_ECPL(1U)
26805 
26806 #define S_VNTAGENABLE    9
26807 #define V_VNTAGENABLE(x) ((x) << S_VNTAGENABLE)
26808 #define F_VNTAGENABLE    V_VNTAGENABLE(1U)
26809 
26810 #define S_IN_EETH    8
26811 #define V_IN_EETH(x) ((x) << S_IN_EETH)
26812 #define F_IN_EETH    V_IN_EETH(1U)
26813 
26814 #define S_CCHECKSUMCHECKTCP    6
26815 #define V_CCHECKSUMCHECKTCP(x) ((x) << S_CCHECKSUMCHECKTCP)
26816 #define F_CCHECKSUMCHECKTCP    V_CCHECKSUMCHECKTCP(1U)
26817 
26818 #define S_CCHECKSUMCHECKIP    5
26819 #define V_CCHECKSUMCHECKIP(x) ((x) << S_CCHECKSUMCHECKIP)
26820 #define F_CCHECKSUMCHECKIP    V_CCHECKSUMCHECKIP(1U)
26821 
26822 #define S_CTAG    4
26823 #define V_CTAG(x) ((x) << S_CTAG)
26824 #define F_CTAG    V_CTAG(1U)
26825 
26826 #define S_IN_CCPL    3
26827 #define V_IN_CCPL(x) ((x) << S_IN_CCPL)
26828 #define F_IN_CCPL    V_IN_CCPL(1U)
26829 
26830 #define S_IN_CETH    1
26831 #define V_IN_CETH(x) ((x) << S_IN_CETH)
26832 #define F_IN_CETH    V_IN_CETH(1U)
26833 
26834 #define S_CTUNNEL    0
26835 #define V_CTUNNEL(x) ((x) << S_CTUNNEL)
26836 #define F_CTUNNEL    V_CTUNNEL(1U)
26837 
26838 #define S_VLANEXTENPORT3    31
26839 #define V_VLANEXTENPORT3(x) ((x) << S_VLANEXTENPORT3)
26840 #define F_VLANEXTENPORT3    V_VLANEXTENPORT3(1U)
26841 
26842 #define S_VLANEXTENPORT2    30
26843 #define V_VLANEXTENPORT2(x) ((x) << S_VLANEXTENPORT2)
26844 #define F_VLANEXTENPORT2    V_VLANEXTENPORT2(1U)
26845 
26846 #define S_VLANEXTENPORT1    29
26847 #define V_VLANEXTENPORT1(x) ((x) << S_VLANEXTENPORT1)
26848 #define F_VLANEXTENPORT1    V_VLANEXTENPORT1(1U)
26849 
26850 #define S_VLANEXTENPORT0    28
26851 #define V_VLANEXTENPORT0(x) ((x) << S_VLANEXTENPORT0)
26852 #define F_VLANEXTENPORT0    V_VLANEXTENPORT0(1U)
26853 
26854 #define S_VNTAGDEFAULTVAL    13
26855 #define V_VNTAGDEFAULTVAL(x) ((x) << S_VNTAGDEFAULTVAL)
26856 #define F_VNTAGDEFAULTVAL    V_VNTAGDEFAULTVAL(1U)
26857 
26858 #define S_ECHECKUDPLEN    12
26859 #define V_ECHECKUDPLEN(x) ((x) << S_ECHECKUDPLEN)
26860 #define F_ECHECKUDPLEN    V_ECHECKUDPLEN(1U)
26861 
26862 #define S_FCOEFPMA    10
26863 #define V_FCOEFPMA(x) ((x) << S_FCOEFPMA)
26864 #define F_FCOEFPMA    V_FCOEFPMA(1U)
26865 
26866 #define S_VNTAGETHENABLE    8
26867 #define V_VNTAGETHENABLE(x) ((x) << S_VNTAGETHENABLE)
26868 #define F_VNTAGETHENABLE    V_VNTAGETHENABLE(1U)
26869 
26870 #define S_IP_CCSM    7
26871 #define V_IP_CCSM(x) ((x) << S_IP_CCSM)
26872 #define F_IP_CCSM    V_IP_CCSM(1U)
26873 
26874 #define S_CCHECKSUMCHECKUDP    6
26875 #define V_CCHECKSUMCHECKUDP(x) ((x) << S_CCHECKSUMCHECKUDP)
26876 #define F_CCHECKSUMCHECKUDP    V_CCHECKSUMCHECKUDP(1U)
26877 
26878 #define S_TCP_CCSM    5
26879 #define V_TCP_CCSM(x) ((x) << S_TCP_CCSM)
26880 #define F_TCP_CCSM    V_TCP_CCSM(1U)
26881 
26882 #define S_CDEMUX    3
26883 #define V_CDEMUX(x) ((x) << S_CDEMUX)
26884 #define F_CDEMUX    V_CDEMUX(1U)
26885 
26886 #define S_ETHUPEN    2
26887 #define V_ETHUPEN(x) ((x) << S_ETHUPEN)
26888 #define F_ETHUPEN    V_ETHUPEN(1U)
26889 
26890 #define S_CXOFFOVERRIDE    3
26891 #define V_CXOFFOVERRIDE(x) ((x) << S_CXOFFOVERRIDE)
26892 #define F_CXOFFOVERRIDE    V_CXOFFOVERRIDE(1U)
26893 
26894 #define S_EGREDROPEN    1
26895 #define V_EGREDROPEN(x) ((x) << S_EGREDROPEN)
26896 #define F_EGREDROPEN    V_EGREDROPEN(1U)
26897 
26898 #define S_CFASTDEMUXEN    0
26899 #define V_CFASTDEMUXEN(x) ((x) << S_CFASTDEMUXEN)
26900 #define F_CFASTDEMUXEN    V_CFASTDEMUXEN(1U)
26901 
26902 #define A_TP_OUT_CONFIG 0x7d04
26903 
26904 #define S_PORTQFCEN    28
26905 #define M_PORTQFCEN    0xfU
26906 #define V_PORTQFCEN(x) ((x) << S_PORTQFCEN)
26907 #define G_PORTQFCEN(x) (((x) >> S_PORTQFCEN) & M_PORTQFCEN)
26908 
26909 #define S_EPKTDISTCHN3    23
26910 #define V_EPKTDISTCHN3(x) ((x) << S_EPKTDISTCHN3)
26911 #define F_EPKTDISTCHN3    V_EPKTDISTCHN3(1U)
26912 
26913 #define S_EPKTDISTCHN2    22
26914 #define V_EPKTDISTCHN2(x) ((x) << S_EPKTDISTCHN2)
26915 #define F_EPKTDISTCHN2    V_EPKTDISTCHN2(1U)
26916 
26917 #define S_EPKTDISTCHN1    21
26918 #define V_EPKTDISTCHN1(x) ((x) << S_EPKTDISTCHN1)
26919 #define F_EPKTDISTCHN1    V_EPKTDISTCHN1(1U)
26920 
26921 #define S_EPKTDISTCHN0    20
26922 #define V_EPKTDISTCHN0(x) ((x) << S_EPKTDISTCHN0)
26923 #define F_EPKTDISTCHN0    V_EPKTDISTCHN0(1U)
26924 
26925 #define S_TTLMODE    19
26926 #define V_TTLMODE(x) ((x) << S_TTLMODE)
26927 #define F_TTLMODE    V_TTLMODE(1U)
26928 
26929 #define S_EQFCDMAC    18
26930 #define V_EQFCDMAC(x) ((x) << S_EQFCDMAC)
26931 #define F_EQFCDMAC    V_EQFCDMAC(1U)
26932 
26933 #define S_ELPBKINCMPSSTAT    17
26934 #define V_ELPBKINCMPSSTAT(x) ((x) << S_ELPBKINCMPSSTAT)
26935 #define F_ELPBKINCMPSSTAT    V_ELPBKINCMPSSTAT(1U)
26936 
26937 #define S_IPIDSPLITMODE    16
26938 #define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE)
26939 #define F_IPIDSPLITMODE    V_IPIDSPLITMODE(1U)
26940 
26941 #define S_VLANEXTENABLEPORT3    15
26942 #define V_VLANEXTENABLEPORT3(x) ((x) << S_VLANEXTENABLEPORT3)
26943 #define F_VLANEXTENABLEPORT3    V_VLANEXTENABLEPORT3(1U)
26944 
26945 #define S_VLANEXTENABLEPORT2    14
26946 #define V_VLANEXTENABLEPORT2(x) ((x) << S_VLANEXTENABLEPORT2)
26947 #define F_VLANEXTENABLEPORT2    V_VLANEXTENABLEPORT2(1U)
26948 
26949 #define S_VLANEXTENABLEPORT1    13
26950 #define V_VLANEXTENABLEPORT1(x) ((x) << S_VLANEXTENABLEPORT1)
26951 #define F_VLANEXTENABLEPORT1    V_VLANEXTENABLEPORT1(1U)
26952 
26953 #define S_VLANEXTENABLEPORT0    12
26954 #define V_VLANEXTENABLEPORT0(x) ((x) << S_VLANEXTENABLEPORT0)
26955 #define F_VLANEXTENABLEPORT0    V_VLANEXTENABLEPORT0(1U)
26956 
26957 #define S_ECHECKSUMINSERTTCP    11
26958 #define V_ECHECKSUMINSERTTCP(x) ((x) << S_ECHECKSUMINSERTTCP)
26959 #define F_ECHECKSUMINSERTTCP    V_ECHECKSUMINSERTTCP(1U)
26960 
26961 #define S_ECHECKSUMINSERTIP    10
26962 #define V_ECHECKSUMINSERTIP(x) ((x) << S_ECHECKSUMINSERTIP)
26963 #define F_ECHECKSUMINSERTIP    V_ECHECKSUMINSERTIP(1U)
26964 
26965 #define S_ECPL    8
26966 #define V_ECPL(x) ((x) << S_ECPL)
26967 #define F_ECPL    V_ECPL(1U)
26968 
26969 #define S_EPRIORITY    7
26970 #define V_EPRIORITY(x) ((x) << S_EPRIORITY)
26971 #define F_EPRIORITY    V_EPRIORITY(1U)
26972 
26973 #define S_EETHERNET    6
26974 #define V_EETHERNET(x) ((x) << S_EETHERNET)
26975 #define F_EETHERNET    V_EETHERNET(1U)
26976 
26977 #define S_CCHECKSUMINSERTTCP    5
26978 #define V_CCHECKSUMINSERTTCP(x) ((x) << S_CCHECKSUMINSERTTCP)
26979 #define F_CCHECKSUMINSERTTCP    V_CCHECKSUMINSERTTCP(1U)
26980 
26981 #define S_CCHECKSUMINSERTIP    4
26982 #define V_CCHECKSUMINSERTIP(x) ((x) << S_CCHECKSUMINSERTIP)
26983 #define F_CCHECKSUMINSERTIP    V_CCHECKSUMINSERTIP(1U)
26984 
26985 #define S_CCPL    2
26986 #define V_CCPL(x) ((x) << S_CCPL)
26987 #define F_CCPL    V_CCPL(1U)
26988 
26989 #define S_CETHERNET    0
26990 #define V_CETHERNET(x) ((x) << S_CETHERNET)
26991 #define F_CETHERNET    V_CETHERNET(1U)
26992 
26993 #define S_EVNTAGEN    9
26994 #define V_EVNTAGEN(x) ((x) << S_EVNTAGEN)
26995 #define F_EVNTAGEN    V_EVNTAGEN(1U)
26996 
26997 #define S_CCPLACKMODE    13
26998 #define V_CCPLACKMODE(x) ((x) << S_CCPLACKMODE)
26999 #define F_CCPLACKMODE    V_CCPLACKMODE(1U)
27000 
27001 #define S_RMWHINTENABLE    12
27002 #define V_RMWHINTENABLE(x) ((x) << S_RMWHINTENABLE)
27003 #define F_RMWHINTENABLE    V_RMWHINTENABLE(1U)
27004 
27005 #define S_EV6FLWEN    8
27006 #define V_EV6FLWEN(x) ((x) << S_EV6FLWEN)
27007 #define F_EV6FLWEN    V_EV6FLWEN(1U)
27008 
27009 #define S_EVLANPRIO    6
27010 #define V_EVLANPRIO(x) ((x) << S_EVLANPRIO)
27011 #define F_EVLANPRIO    V_EVLANPRIO(1U)
27012 
27013 #define S_CRXPKTENC    3
27014 #define V_CRXPKTENC(x) ((x) << S_CRXPKTENC)
27015 #define F_CRXPKTENC    V_CRXPKTENC(1U)
27016 
27017 #define S_CRXPKTXT    1
27018 #define V_CRXPKTXT(x) ((x) << S_CRXPKTXT)
27019 #define F_CRXPKTXT    V_CRXPKTXT(1U)
27020 
27021 #define S_ETOEBYPCSUMNOWAIT    15
27022 #define V_ETOEBYPCSUMNOWAIT(x) ((x) << S_ETOEBYPCSUMNOWAIT)
27023 #define F_ETOEBYPCSUMNOWAIT    V_ETOEBYPCSUMNOWAIT(1U)
27024 
27025 #define S_ENICCSUMNOWAIT    14
27026 #define V_ENICCSUMNOWAIT(x) ((x) << S_ENICCSUMNOWAIT)
27027 #define F_ENICCSUMNOWAIT    V_ENICCSUMNOWAIT(1U)
27028 
27029 #define A_TP_GLOBAL_CONFIG 0x7d08
27030 
27031 #define S_SYNCOOKIEPARAMS    26
27032 #define M_SYNCOOKIEPARAMS    0x3fU
27033 #define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS)
27034 #define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS)
27035 
27036 #define S_RXFLOWCONTROLDISABLE    25
27037 #define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE)
27038 #define F_RXFLOWCONTROLDISABLE    V_RXFLOWCONTROLDISABLE(1U)
27039 
27040 #define S_TXPACINGENABLE    24
27041 #define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
27042 #define F_TXPACINGENABLE    V_TXPACINGENABLE(1U)
27043 
27044 #define S_ATTACKFILTERENABLE    23
27045 #define V_ATTACKFILTERENABLE(x) ((x) << S_ATTACKFILTERENABLE)
27046 #define F_ATTACKFILTERENABLE    V_ATTACKFILTERENABLE(1U)
27047 
27048 #define S_SYNCOOKIENOOPTIONS    22
27049 #define V_SYNCOOKIENOOPTIONS(x) ((x) << S_SYNCOOKIENOOPTIONS)
27050 #define F_SYNCOOKIENOOPTIONS    V_SYNCOOKIENOOPTIONS(1U)
27051 
27052 #define S_PROTECTEDMODE    21
27053 #define V_PROTECTEDMODE(x) ((x) << S_PROTECTEDMODE)
27054 #define F_PROTECTEDMODE    V_PROTECTEDMODE(1U)
27055 
27056 #define S_PINGDROP    20
27057 #define V_PINGDROP(x) ((x) << S_PINGDROP)
27058 #define F_PINGDROP    V_PINGDROP(1U)
27059 
27060 #define S_FRAGMENTDROP    19
27061 #define V_FRAGMENTDROP(x) ((x) << S_FRAGMENTDROP)
27062 #define F_FRAGMENTDROP    V_FRAGMENTDROP(1U)
27063 
27064 #define S_FIVETUPLELOOKUP    17
27065 #define M_FIVETUPLELOOKUP    0x3U
27066 #define V_FIVETUPLELOOKUP(x) ((x) << S_FIVETUPLELOOKUP)
27067 #define G_FIVETUPLELOOKUP(x) (((x) >> S_FIVETUPLELOOKUP) & M_FIVETUPLELOOKUP)
27068 
27069 #define S_OFDMPSSTATS    16
27070 #define V_OFDMPSSTATS(x) ((x) << S_OFDMPSSTATS)
27071 #define F_OFDMPSSTATS    V_OFDMPSSTATS(1U)
27072 
27073 #define S_DONTFRAGMENT    15
27074 #define V_DONTFRAGMENT(x) ((x) << S_DONTFRAGMENT)
27075 #define F_DONTFRAGMENT    V_DONTFRAGMENT(1U)
27076 
27077 #define S_IPIDENTSPLIT    14
27078 #define V_IPIDENTSPLIT(x) ((x) << S_IPIDENTSPLIT)
27079 #define F_IPIDENTSPLIT    V_IPIDENTSPLIT(1U)
27080 
27081 #define S_IPCHECKSUMOFFLOAD    13
27082 #define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
27083 #define F_IPCHECKSUMOFFLOAD    V_IPCHECKSUMOFFLOAD(1U)
27084 
27085 #define S_UDPCHECKSUMOFFLOAD    12
27086 #define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
27087 #define F_UDPCHECKSUMOFFLOAD    V_UDPCHECKSUMOFFLOAD(1U)
27088 
27089 #define S_TCPCHECKSUMOFFLOAD    11
27090 #define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
27091 #define F_TCPCHECKSUMOFFLOAD    V_TCPCHECKSUMOFFLOAD(1U)
27092 
27093 #define S_RSSLOOPBACKENABLE    10
27094 #define V_RSSLOOPBACKENABLE(x) ((x) << S_RSSLOOPBACKENABLE)
27095 #define F_RSSLOOPBACKENABLE    V_RSSLOOPBACKENABLE(1U)
27096 
27097 #define S_TCAMSERVERUSE    8
27098 #define M_TCAMSERVERUSE    0x3U
27099 #define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE)
27100 #define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE)
27101 
27102 #define S_IPTTL    0
27103 #define M_IPTTL    0xffU
27104 #define V_IPTTL(x) ((x) << S_IPTTL)
27105 #define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL)
27106 
27107 #define S_RSSSYNSTEERENABLE    12
27108 #define V_RSSSYNSTEERENABLE(x) ((x) << S_RSSSYNSTEERENABLE)
27109 #define F_RSSSYNSTEERENABLE    V_RSSSYNSTEERENABLE(1U)
27110 
27111 #define S_ISSFROMCPLENABLE    11
27112 #define V_ISSFROMCPLENABLE(x) ((x) << S_ISSFROMCPLENABLE)
27113 #define F_ISSFROMCPLENABLE    V_ISSFROMCPLENABLE(1U)
27114 
27115 #define S_ACTIVEFILTERCOUNTS    22
27116 #define V_ACTIVEFILTERCOUNTS(x) ((x) << S_ACTIVEFILTERCOUNTS)
27117 #define F_ACTIVEFILTERCOUNTS    V_ACTIVEFILTERCOUNTS(1U)
27118 
27119 #define S_RXSACKPARSE    31
27120 #define V_RXSACKPARSE(x) ((x) << S_RXSACKPARSE)
27121 #define F_RXSACKPARSE    V_RXSACKPARSE(1U)
27122 
27123 #define S_RXSACKFWDMODE    29
27124 #define M_RXSACKFWDMODE    0x3U
27125 #define V_RXSACKFWDMODE(x) ((x) << S_RXSACKFWDMODE)
27126 #define G_RXSACKFWDMODE(x) (((x) >> S_RXSACKFWDMODE) & M_RXSACKFWDMODE)
27127 
27128 #define S_SRVRCHRSSEN    26
27129 #define V_SRVRCHRSSEN(x) ((x) << S_SRVRCHRSSEN)
27130 #define F_SRVRCHRSSEN    V_SRVRCHRSSEN(1U)
27131 
27132 #define S_LBCHNDISTEN    23
27133 #define V_LBCHNDISTEN(x) ((x) << S_LBCHNDISTEN)
27134 #define F_LBCHNDISTEN    V_LBCHNDISTEN(1U)
27135 
27136 #define S_ETHTNLLEN2X    20
27137 #define V_ETHTNLLEN2X(x) ((x) << S_ETHTNLLEN2X)
27138 #define F_ETHTNLLEN2X    V_ETHTNLLEN2X(1U)
27139 
27140 #define S_EGLBCHNDISTEN    19
27141 #define V_EGLBCHNDISTEN(x) ((x) << S_EGLBCHNDISTEN)
27142 #define F_EGLBCHNDISTEN    V_EGLBCHNDISTEN(1U)
27143 
27144 #define A_TP_DB_CONFIG 0x7d0c
27145 
27146 #define S_DBMAXOPCNT    24
27147 #define M_DBMAXOPCNT    0xffU
27148 #define V_DBMAXOPCNT(x) ((x) << S_DBMAXOPCNT)
27149 #define G_DBMAXOPCNT(x) (((x) >> S_DBMAXOPCNT) & M_DBMAXOPCNT)
27150 
27151 #define S_CXMAXOPCNTDISABLE    23
27152 #define V_CXMAXOPCNTDISABLE(x) ((x) << S_CXMAXOPCNTDISABLE)
27153 #define F_CXMAXOPCNTDISABLE    V_CXMAXOPCNTDISABLE(1U)
27154 
27155 #define S_CXMAXOPCNT    16
27156 #define M_CXMAXOPCNT    0x7fU
27157 #define V_CXMAXOPCNT(x) ((x) << S_CXMAXOPCNT)
27158 #define G_CXMAXOPCNT(x) (((x) >> S_CXMAXOPCNT) & M_CXMAXOPCNT)
27159 
27160 #define S_TXMAXOPCNTDISABLE    15
27161 #define V_TXMAXOPCNTDISABLE(x) ((x) << S_TXMAXOPCNTDISABLE)
27162 #define F_TXMAXOPCNTDISABLE    V_TXMAXOPCNTDISABLE(1U)
27163 
27164 #define S_TXMAXOPCNT    8
27165 #define M_TXMAXOPCNT    0x7fU
27166 #define V_TXMAXOPCNT(x) ((x) << S_TXMAXOPCNT)
27167 #define G_TXMAXOPCNT(x) (((x) >> S_TXMAXOPCNT) & M_TXMAXOPCNT)
27168 
27169 #define S_RXMAXOPCNTDISABLE    7
27170 #define V_RXMAXOPCNTDISABLE(x) ((x) << S_RXMAXOPCNTDISABLE)
27171 #define F_RXMAXOPCNTDISABLE    V_RXMAXOPCNTDISABLE(1U)
27172 
27173 #define S_RXMAXOPCNT    0
27174 #define M_RXMAXOPCNT    0x7fU
27175 #define V_RXMAXOPCNT(x) ((x) << S_RXMAXOPCNT)
27176 #define G_RXMAXOPCNT(x) (((x) >> S_RXMAXOPCNT) & M_RXMAXOPCNT)
27177 
27178 #define A_TP_CMM_TCB_BASE 0x7d10
27179 #define A_TP_CMM_MM_BASE 0x7d14
27180 #define A_TP_CMM_TIMER_BASE 0x7d18
27181 #define A_TP_CMM_MM_FLST_SIZE 0x7d1c
27182 
27183 #define S_RXPOOLSIZE    16
27184 #define M_RXPOOLSIZE    0xffffU
27185 #define V_RXPOOLSIZE(x) ((x) << S_RXPOOLSIZE)
27186 #define G_RXPOOLSIZE(x) (((x) >> S_RXPOOLSIZE) & M_RXPOOLSIZE)
27187 
27188 #define S_TXPOOLSIZE    0
27189 #define M_TXPOOLSIZE    0xffffU
27190 #define V_TXPOOLSIZE(x) ((x) << S_TXPOOLSIZE)
27191 #define G_TXPOOLSIZE(x) (((x) >> S_TXPOOLSIZE) & M_TXPOOLSIZE)
27192 
27193 #define A_TP_PMM_TX_BASE 0x7d20
27194 #define A_TP_PMM_DEFRAG_BASE 0x7d24
27195 #define A_TP_PMM_RX_BASE 0x7d28
27196 #define A_TP_PMM_RX_PAGE_SIZE 0x7d2c
27197 #define A_TP_PMM_RX_MAX_PAGE 0x7d30
27198 
27199 #define S_PMRXNUMCHN    31
27200 #define V_PMRXNUMCHN(x) ((x) << S_PMRXNUMCHN)
27201 #define F_PMRXNUMCHN    V_PMRXNUMCHN(1U)
27202 
27203 #define S_PMRXMAXPAGE    0
27204 #define M_PMRXMAXPAGE    0x1fffffU
27205 #define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE)
27206 #define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE)
27207 
27208 #define S_T7_PMRXNUMCHN    29
27209 #define M_T7_PMRXNUMCHN    0x7U
27210 #define V_T7_PMRXNUMCHN(x) ((x) << S_T7_PMRXNUMCHN)
27211 #define G_T7_PMRXNUMCHN(x) (((x) >> S_T7_PMRXNUMCHN) & M_T7_PMRXNUMCHN)
27212 
27213 #define A_TP_PMM_TX_PAGE_SIZE 0x7d34
27214 #define A_TP_PMM_TX_MAX_PAGE 0x7d38
27215 
27216 #define S_PMTXNUMCHN    30
27217 #define M_PMTXNUMCHN    0x3U
27218 #define V_PMTXNUMCHN(x) ((x) << S_PMTXNUMCHN)
27219 #define G_PMTXNUMCHN(x) (((x) >> S_PMTXNUMCHN) & M_PMTXNUMCHN)
27220 
27221 #define S_PMTXMAXPAGE    0
27222 #define M_PMTXMAXPAGE    0x1fffffU
27223 #define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE)
27224 #define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE)
27225 
27226 #define S_T7_PMTXNUMCHN    29
27227 #define M_T7_PMTXNUMCHN    0x7U
27228 #define V_T7_PMTXNUMCHN(x) ((x) << S_T7_PMTXNUMCHN)
27229 #define G_T7_PMTXNUMCHN(x) (((x) >> S_T7_PMTXNUMCHN) & M_T7_PMTXNUMCHN)
27230 
27231 #define A_TP_EXT_CONFIG 0x7d3c
27232 
27233 #define S_TNLERRORIPSECARW    29
27234 #define V_TNLERRORIPSECARW(x) ((x) << S_TNLERRORIPSECARW)
27235 #define F_TNLERRORIPSECARW    V_TNLERRORIPSECARW(1U)
27236 
27237 #define S_TNLERRORIPSECICV    28
27238 #define V_TNLERRORIPSECICV(x) ((x) << S_TNLERRORIPSECICV)
27239 #define F_TNLERRORIPSECICV    V_TNLERRORIPSECICV(1U)
27240 
27241 #define S_DROPERRORIPSECARW    25
27242 #define V_DROPERRORIPSECARW(x) ((x) << S_DROPERRORIPSECARW)
27243 #define F_DROPERRORIPSECARW    V_DROPERRORIPSECARW(1U)
27244 
27245 #define S_DROPERRORIPSECICV    24
27246 #define V_DROPERRORIPSECICV(x) ((x) << S_DROPERRORIPSECICV)
27247 #define F_DROPERRORIPSECICV    V_DROPERRORIPSECICV(1U)
27248 
27249 #define S_MIBRDMAROCEEN    19
27250 #define V_MIBRDMAROCEEN(x) ((x) << S_MIBRDMAROCEEN)
27251 #define F_MIBRDMAROCEEN    V_MIBRDMAROCEEN(1U)
27252 
27253 #define S_MIBRDMAIWARPEN    18
27254 #define V_MIBRDMAIWARPEN(x) ((x) << S_MIBRDMAIWARPEN)
27255 #define F_MIBRDMAIWARPEN    V_MIBRDMAIWARPEN(1U)
27256 
27257 #define S_BYPTXDATAACKALLEN    17
27258 #define V_BYPTXDATAACKALLEN(x) ((x) << S_BYPTXDATAACKALLEN)
27259 #define F_BYPTXDATAACKALLEN    V_BYPTXDATAACKALLEN(1U)
27260 
27261 #define S_DATAACKEXTEN    16
27262 #define V_DATAACKEXTEN(x) ((x) << S_DATAACKEXTEN)
27263 #define F_DATAACKEXTEN    V_DATAACKEXTEN(1U)
27264 
27265 #define S_MACMATCH11FWD    11
27266 #define V_MACMATCH11FWD(x) ((x) << S_MACMATCH11FWD)
27267 #define F_MACMATCH11FWD    V_MACMATCH11FWD(1U)
27268 
27269 #define S_USERTMSTPEN    10
27270 #define V_USERTMSTPEN(x) ((x) << S_USERTMSTPEN)
27271 #define F_USERTMSTPEN    V_USERTMSTPEN(1U)
27272 
27273 #define S_MMGRCACHEDIS    9
27274 #define V_MMGRCACHEDIS(x) ((x) << S_MMGRCACHEDIS)
27275 #define F_MMGRCACHEDIS    V_MMGRCACHEDIS(1U)
27276 
27277 #define S_TXPKTPACKOUTUDPEN    8
27278 #define V_TXPKTPACKOUTUDPEN(x) ((x) << S_TXPKTPACKOUTUDPEN)
27279 #define F_TXPKTPACKOUTUDPEN    V_TXPKTPACKOUTUDPEN(1U)
27280 
27281 #define S_IPSECROCECRCMODE    6
27282 #define M_IPSECROCECRCMODE    0x3U
27283 #define V_IPSECROCECRCMODE(x) ((x) << S_IPSECROCECRCMODE)
27284 #define G_IPSECROCECRCMODE(x) (((x) >> S_IPSECROCECRCMODE) & M_IPSECROCECRCMODE)
27285 
27286 #define S_IPSECIDXLOC    5
27287 #define V_IPSECIDXLOC(x) ((x) << S_IPSECIDXLOC)
27288 #define F_IPSECIDXLOC    V_IPSECIDXLOC(1U)
27289 
27290 #define S_IPSECIDXCAPEN    4
27291 #define V_IPSECIDXCAPEN(x) ((x) << S_IPSECIDXCAPEN)
27292 #define F_IPSECIDXCAPEN    V_IPSECIDXCAPEN(1U)
27293 
27294 #define S_IPSECOFEN    3
27295 #define V_IPSECOFEN(x) ((x) << S_IPSECOFEN)
27296 #define F_IPSECOFEN    V_IPSECOFEN(1U)
27297 
27298 #define S_IPSECCFG    0
27299 #define M_IPSECCFG    0x7U
27300 #define V_IPSECCFG(x) ((x) << S_IPSECCFG)
27301 #define G_IPSECCFG(x) (((x) >> S_IPSECCFG) & M_IPSECCFG)
27302 
27303 #define A_TP_TCP_OPTIONS 0x7d40
27304 
27305 #define S_MTUDEFAULT    16
27306 #define M_MTUDEFAULT    0xffffU
27307 #define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT)
27308 #define G_MTUDEFAULT(x) (((x) >> S_MTUDEFAULT) & M_MTUDEFAULT)
27309 
27310 #define S_MTUENABLE    10
27311 #define V_MTUENABLE(x) ((x) << S_MTUENABLE)
27312 #define F_MTUENABLE    V_MTUENABLE(1U)
27313 
27314 #define S_SACKTX    9
27315 #define V_SACKTX(x) ((x) << S_SACKTX)
27316 #define F_SACKTX    V_SACKTX(1U)
27317 
27318 #define S_SACKRX    8
27319 #define V_SACKRX(x) ((x) << S_SACKRX)
27320 #define F_SACKRX    V_SACKRX(1U)
27321 
27322 #define S_SACKMODE    4
27323 #define M_SACKMODE    0x3U
27324 #define V_SACKMODE(x) ((x) << S_SACKMODE)
27325 #define G_SACKMODE(x) (((x) >> S_SACKMODE) & M_SACKMODE)
27326 
27327 #define S_WINDOWSCALEMODE    2
27328 #define M_WINDOWSCALEMODE    0x3U
27329 #define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE)
27330 #define G_WINDOWSCALEMODE(x) (((x) >> S_WINDOWSCALEMODE) & M_WINDOWSCALEMODE)
27331 
27332 #define S_TIMESTAMPSMODE    0
27333 #define M_TIMESTAMPSMODE    0x3U
27334 #define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE)
27335 #define G_TIMESTAMPSMODE(x) (((x) >> S_TIMESTAMPSMODE) & M_TIMESTAMPSMODE)
27336 
27337 #define A_TP_DACK_CONFIG 0x7d44
27338 
27339 #define S_AUTOSTATE3    30
27340 #define M_AUTOSTATE3    0x3U
27341 #define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
27342 #define G_AUTOSTATE3(x) (((x) >> S_AUTOSTATE3) & M_AUTOSTATE3)
27343 
27344 #define S_AUTOSTATE2    28
27345 #define M_AUTOSTATE2    0x3U
27346 #define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
27347 #define G_AUTOSTATE2(x) (((x) >> S_AUTOSTATE2) & M_AUTOSTATE2)
27348 
27349 #define S_AUTOSTATE1    26
27350 #define M_AUTOSTATE1    0x3U
27351 #define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
27352 #define G_AUTOSTATE1(x) (((x) >> S_AUTOSTATE1) & M_AUTOSTATE1)
27353 
27354 #define S_BYTETHRESHOLD    8
27355 #define M_BYTETHRESHOLD    0x3ffffU
27356 #define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
27357 #define G_BYTETHRESHOLD(x) (((x) >> S_BYTETHRESHOLD) & M_BYTETHRESHOLD)
27358 
27359 #define S_MSSTHRESHOLD    4
27360 #define M_MSSTHRESHOLD    0x7U
27361 #define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
27362 #define G_MSSTHRESHOLD(x) (((x) >> S_MSSTHRESHOLD) & M_MSSTHRESHOLD)
27363 
27364 #define S_AUTOCAREFUL    2
27365 #define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL)
27366 #define F_AUTOCAREFUL    V_AUTOCAREFUL(1U)
27367 
27368 #define S_AUTOENABLE    1
27369 #define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
27370 #define F_AUTOENABLE    V_AUTOENABLE(1U)
27371 
27372 #define S_MODE    0
27373 #define V_MODE(x) ((x) << S_MODE)
27374 #define F_MODE    V_MODE(1U)
27375 
27376 #define A_TP_PC_CONFIG 0x7d48
27377 
27378 #define S_CMCACHEDISABLE    31
27379 #define V_CMCACHEDISABLE(x) ((x) << S_CMCACHEDISABLE)
27380 #define F_CMCACHEDISABLE    V_CMCACHEDISABLE(1U)
27381 
27382 #define S_ENABLEOCSPIFULL    30
27383 #define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL)
27384 #define F_ENABLEOCSPIFULL    V_ENABLEOCSPIFULL(1U)
27385 
27386 #define S_ENABLEFLMERRORDDP    29
27387 #define V_ENABLEFLMERRORDDP(x) ((x) << S_ENABLEFLMERRORDDP)
27388 #define F_ENABLEFLMERRORDDP    V_ENABLEFLMERRORDDP(1U)
27389 
27390 #define S_LOCKTID    28
27391 #define V_LOCKTID(x) ((x) << S_LOCKTID)
27392 #define F_LOCKTID    V_LOCKTID(1U)
27393 
27394 #define S_DISABLEINVPEND    27
27395 #define V_DISABLEINVPEND(x) ((x) << S_DISABLEINVPEND)
27396 #define F_DISABLEINVPEND    V_DISABLEINVPEND(1U)
27397 
27398 #define S_ENABLEFILTERCOUNT    26
27399 #define V_ENABLEFILTERCOUNT(x) ((x) << S_ENABLEFILTERCOUNT)
27400 #define F_ENABLEFILTERCOUNT    V_ENABLEFILTERCOUNT(1U)
27401 
27402 #define S_RDDPCONGEN    25
27403 #define V_RDDPCONGEN(x) ((x) << S_RDDPCONGEN)
27404 #define F_RDDPCONGEN    V_RDDPCONGEN(1U)
27405 
27406 #define S_ENABLEONFLYPDU    24
27407 #define V_ENABLEONFLYPDU(x) ((x) << S_ENABLEONFLYPDU)
27408 #define F_ENABLEONFLYPDU    V_ENABLEONFLYPDU(1U)
27409 
27410 #define S_ENABLEMINRCVWND    23
27411 #define V_ENABLEMINRCVWND(x) ((x) << S_ENABLEMINRCVWND)
27412 #define F_ENABLEMINRCVWND    V_ENABLEMINRCVWND(1U)
27413 
27414 #define S_ENABLEMAXRCVWND    22
27415 #define V_ENABLEMAXRCVWND(x) ((x) << S_ENABLEMAXRCVWND)
27416 #define F_ENABLEMAXRCVWND    V_ENABLEMAXRCVWND(1U)
27417 
27418 #define S_TXDATAACKRATEENABLE    21
27419 #define V_TXDATAACKRATEENABLE(x) ((x) << S_TXDATAACKRATEENABLE)
27420 #define F_TXDATAACKRATEENABLE    V_TXDATAACKRATEENABLE(1U)
27421 
27422 #define S_TXDEFERENABLE    20
27423 #define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE)
27424 #define F_TXDEFERENABLE    V_TXDEFERENABLE(1U)
27425 
27426 #define S_RXCONGESTIONMODE    19
27427 #define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE)
27428 #define F_RXCONGESTIONMODE    V_RXCONGESTIONMODE(1U)
27429 
27430 #define S_HEARBEATONCEDACK    18
27431 #define V_HEARBEATONCEDACK(x) ((x) << S_HEARBEATONCEDACK)
27432 #define F_HEARBEATONCEDACK    V_HEARBEATONCEDACK(1U)
27433 
27434 #define S_HEARBEATONCEHEAP    17
27435 #define V_HEARBEATONCEHEAP(x) ((x) << S_HEARBEATONCEHEAP)
27436 #define F_HEARBEATONCEHEAP    V_HEARBEATONCEHEAP(1U)
27437 
27438 #define S_HEARBEATDACK    16
27439 #define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK)
27440 #define F_HEARBEATDACK    V_HEARBEATDACK(1U)
27441 
27442 #define S_TXCONGESTIONMODE    15
27443 #define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE)
27444 #define F_TXCONGESTIONMODE    V_TXCONGESTIONMODE(1U)
27445 
27446 #define S_ACCEPTLATESTRCVADV    14
27447 #define V_ACCEPTLATESTRCVADV(x) ((x) << S_ACCEPTLATESTRCVADV)
27448 #define F_ACCEPTLATESTRCVADV    V_ACCEPTLATESTRCVADV(1U)
27449 
27450 #define S_DISABLESYNDATA    13
27451 #define V_DISABLESYNDATA(x) ((x) << S_DISABLESYNDATA)
27452 #define F_DISABLESYNDATA    V_DISABLESYNDATA(1U)
27453 
27454 #define S_DISABLEWINDOWPSH    12
27455 #define V_DISABLEWINDOWPSH(x) ((x) << S_DISABLEWINDOWPSH)
27456 #define F_DISABLEWINDOWPSH    V_DISABLEWINDOWPSH(1U)
27457 
27458 #define S_DISABLEFINOLDDATA    11
27459 #define V_DISABLEFINOLDDATA(x) ((x) << S_DISABLEFINOLDDATA)
27460 #define F_DISABLEFINOLDDATA    V_DISABLEFINOLDDATA(1U)
27461 
27462 #define S_ENABLEFLMERROR    10
27463 #define V_ENABLEFLMERROR(x) ((x) << S_ENABLEFLMERROR)
27464 #define F_ENABLEFLMERROR    V_ENABLEFLMERROR(1U)
27465 
27466 #define S_ENABLEOPTMTU    9
27467 #define V_ENABLEOPTMTU(x) ((x) << S_ENABLEOPTMTU)
27468 #define F_ENABLEOPTMTU    V_ENABLEOPTMTU(1U)
27469 
27470 #define S_FILTERPEERFIN    8
27471 #define V_FILTERPEERFIN(x) ((x) << S_FILTERPEERFIN)
27472 #define F_FILTERPEERFIN    V_FILTERPEERFIN(1U)
27473 
27474 #define S_ENABLEFEEDBACKSEND    7
27475 #define V_ENABLEFEEDBACKSEND(x) ((x) << S_ENABLEFEEDBACKSEND)
27476 #define F_ENABLEFEEDBACKSEND    V_ENABLEFEEDBACKSEND(1U)
27477 
27478 #define S_ENABLERDMAERROR    6
27479 #define V_ENABLERDMAERROR(x) ((x) << S_ENABLERDMAERROR)
27480 #define F_ENABLERDMAERROR    V_ENABLERDMAERROR(1U)
27481 
27482 #define S_ENABLEDDPFLOWCONTROL    5
27483 #define V_ENABLEDDPFLOWCONTROL(x) ((x) << S_ENABLEDDPFLOWCONTROL)
27484 #define F_ENABLEDDPFLOWCONTROL    V_ENABLEDDPFLOWCONTROL(1U)
27485 
27486 #define S_DISABLEHELDFIN    4
27487 #define V_DISABLEHELDFIN(x) ((x) << S_DISABLEHELDFIN)
27488 #define F_DISABLEHELDFIN    V_DISABLEHELDFIN(1U)
27489 
27490 #define S_ENABLEOFDOVLAN    3
27491 #define V_ENABLEOFDOVLAN(x) ((x) << S_ENABLEOFDOVLAN)
27492 #define F_ENABLEOFDOVLAN    V_ENABLEOFDOVLAN(1U)
27493 
27494 #define S_DISABLETIMEWAIT    2
27495 #define V_DISABLETIMEWAIT(x) ((x) << S_DISABLETIMEWAIT)
27496 #define F_DISABLETIMEWAIT    V_DISABLETIMEWAIT(1U)
27497 
27498 #define S_ENABLEVLANCHECK    1
27499 #define V_ENABLEVLANCHECK(x) ((x) << S_ENABLEVLANCHECK)
27500 #define F_ENABLEVLANCHECK    V_ENABLEVLANCHECK(1U)
27501 
27502 #define S_TXDATAACKPAGEENABLE    0
27503 #define V_TXDATAACKPAGEENABLE(x) ((x) << S_TXDATAACKPAGEENABLE)
27504 #define F_TXDATAACKPAGEENABLE    V_TXDATAACKPAGEENABLE(1U)
27505 
27506 #define S_ENABLEFILTERNAT    5
27507 #define V_ENABLEFILTERNAT(x) ((x) << S_ENABLEFILTERNAT)
27508 #define F_ENABLEFILTERNAT    V_ENABLEFILTERNAT(1U)
27509 
27510 #define S_ENABLEFINCHECK    31
27511 #define V_ENABLEFINCHECK(x) ((x) << S_ENABLEFINCHECK)
27512 #define F_ENABLEFINCHECK    V_ENABLEFINCHECK(1U)
27513 
27514 #define S_ENABLEMIBVFPLD    21
27515 #define V_ENABLEMIBVFPLD(x) ((x) << S_ENABLEMIBVFPLD)
27516 #define F_ENABLEMIBVFPLD    V_ENABLEMIBVFPLD(1U)
27517 
27518 #define S_DISABLESEPPSHFLAG    4
27519 #define V_DISABLESEPPSHFLAG(x) ((x) << S_DISABLESEPPSHFLAG)
27520 #define F_DISABLESEPPSHFLAG    V_DISABLESEPPSHFLAG(1U)
27521 
27522 #define A_TP_PC_CONFIG2 0x7d4c
27523 
27524 #define S_ENABLEMTUVFMODE    31
27525 #define V_ENABLEMTUVFMODE(x) ((x) << S_ENABLEMTUVFMODE)
27526 #define F_ENABLEMTUVFMODE    V_ENABLEMTUVFMODE(1U)
27527 
27528 #define S_ENABLEMIBVFMODE    30
27529 #define V_ENABLEMIBVFMODE(x) ((x) << S_ENABLEMIBVFMODE)
27530 #define F_ENABLEMIBVFMODE    V_ENABLEMIBVFMODE(1U)
27531 
27532 #define S_DISABLELBKCHECK    29
27533 #define V_DISABLELBKCHECK(x) ((x) << S_DISABLELBKCHECK)
27534 #define F_DISABLELBKCHECK    V_DISABLELBKCHECK(1U)
27535 
27536 #define S_ENABLEURGDDPOFF    28
27537 #define V_ENABLEURGDDPOFF(x) ((x) << S_ENABLEURGDDPOFF)
27538 #define F_ENABLEURGDDPOFF    V_ENABLEURGDDPOFF(1U)
27539 
27540 #define S_ENABLEFILTERLPBK    27
27541 #define V_ENABLEFILTERLPBK(x) ((x) << S_ENABLEFILTERLPBK)
27542 #define F_ENABLEFILTERLPBK    V_ENABLEFILTERLPBK(1U)
27543 
27544 #define S_DISABLETBLMMGR    26
27545 #define V_DISABLETBLMMGR(x) ((x) << S_DISABLETBLMMGR)
27546 #define F_DISABLETBLMMGR    V_DISABLETBLMMGR(1U)
27547 
27548 #define S_CNGRECSNDNXT    25
27549 #define V_CNGRECSNDNXT(x) ((x) << S_CNGRECSNDNXT)
27550 #define F_CNGRECSNDNXT    V_CNGRECSNDNXT(1U)
27551 
27552 #define S_ENABLELBKCHN    24
27553 #define V_ENABLELBKCHN(x) ((x) << S_ENABLELBKCHN)
27554 #define F_ENABLELBKCHN    V_ENABLELBKCHN(1U)
27555 
27556 #define S_ENABLELROECN    23
27557 #define V_ENABLELROECN(x) ((x) << S_ENABLELROECN)
27558 #define F_ENABLELROECN    V_ENABLELROECN(1U)
27559 
27560 #define S_ENABLEPCMDCHECK    22
27561 #define V_ENABLEPCMDCHECK(x) ((x) << S_ENABLEPCMDCHECK)
27562 #define F_ENABLEPCMDCHECK    V_ENABLEPCMDCHECK(1U)
27563 
27564 #define S_ENABLEELBKAFULL    21
27565 #define V_ENABLEELBKAFULL(x) ((x) << S_ENABLEELBKAFULL)
27566 #define F_ENABLEELBKAFULL    V_ENABLEELBKAFULL(1U)
27567 
27568 #define S_ENABLECLBKAFULL    20
27569 #define V_ENABLECLBKAFULL(x) ((x) << S_ENABLECLBKAFULL)
27570 #define F_ENABLECLBKAFULL    V_ENABLECLBKAFULL(1U)
27571 
27572 #define S_ENABLEOESPIFULL    19
27573 #define V_ENABLEOESPIFULL(x) ((x) << S_ENABLEOESPIFULL)
27574 #define F_ENABLEOESPIFULL    V_ENABLEOESPIFULL(1U)
27575 
27576 #define S_DISABLEHITCHECK    18
27577 #define V_DISABLEHITCHECK(x) ((x) << S_DISABLEHITCHECK)
27578 #define F_DISABLEHITCHECK    V_DISABLEHITCHECK(1U)
27579 
27580 #define S_ENABLERSSERRCHECK    17
27581 #define V_ENABLERSSERRCHECK(x) ((x) << S_ENABLERSSERRCHECK)
27582 #define F_ENABLERSSERRCHECK    V_ENABLERSSERRCHECK(1U)
27583 
27584 #define S_DISABLENEWPSHFLAG    16
27585 #define V_DISABLENEWPSHFLAG(x) ((x) << S_DISABLENEWPSHFLAG)
27586 #define F_DISABLENEWPSHFLAG    V_DISABLENEWPSHFLAG(1U)
27587 
27588 #define S_ENABLERDDPRCVADVCLR    15
27589 #define V_ENABLERDDPRCVADVCLR(x) ((x) << S_ENABLERDDPRCVADVCLR)
27590 #define F_ENABLERDDPRCVADVCLR    V_ENABLERDDPRCVADVCLR(1U)
27591 
27592 #define S_ENABLETXDATAARPMISS    14
27593 #define V_ENABLETXDATAARPMISS(x) ((x) << S_ENABLETXDATAARPMISS)
27594 #define F_ENABLETXDATAARPMISS    V_ENABLETXDATAARPMISS(1U)
27595 
27596 #define S_ENABLEARPMISS    13
27597 #define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS)
27598 #define F_ENABLEARPMISS    V_ENABLEARPMISS(1U)
27599 
27600 #define S_ENABLERSTPAWS    12
27601 #define V_ENABLERSTPAWS(x) ((x) << S_ENABLERSTPAWS)
27602 #define F_ENABLERSTPAWS    V_ENABLERSTPAWS(1U)
27603 
27604 #define S_ENABLEIPV6RSS    11
27605 #define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS)
27606 #define F_ENABLEIPV6RSS    V_ENABLEIPV6RSS(1U)
27607 
27608 #define S_ENABLENONOFDHYBRSS    10
27609 #define V_ENABLENONOFDHYBRSS(x) ((x) << S_ENABLENONOFDHYBRSS)
27610 #define F_ENABLENONOFDHYBRSS    V_ENABLENONOFDHYBRSS(1U)
27611 
27612 #define S_ENABLEUDP4TUPRSS    9
27613 #define V_ENABLEUDP4TUPRSS(x) ((x) << S_ENABLEUDP4TUPRSS)
27614 #define F_ENABLEUDP4TUPRSS    V_ENABLEUDP4TUPRSS(1U)
27615 
27616 #define S_ENABLERXPKTTMSTPRSS    8
27617 #define V_ENABLERXPKTTMSTPRSS(x) ((x) << S_ENABLERXPKTTMSTPRSS)
27618 #define F_ENABLERXPKTTMSTPRSS    V_ENABLERXPKTTMSTPRSS(1U)
27619 
27620 #define S_ENABLEEPCMDAFULL    7
27621 #define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL)
27622 #define F_ENABLEEPCMDAFULL    V_ENABLEEPCMDAFULL(1U)
27623 
27624 #define S_ENABLECPCMDAFULL    6
27625 #define V_ENABLECPCMDAFULL(x) ((x) << S_ENABLECPCMDAFULL)
27626 #define F_ENABLECPCMDAFULL    V_ENABLECPCMDAFULL(1U)
27627 
27628 #define S_ENABLEEHDRAFULL    5
27629 #define V_ENABLEEHDRAFULL(x) ((x) << S_ENABLEEHDRAFULL)
27630 #define F_ENABLEEHDRAFULL    V_ENABLEEHDRAFULL(1U)
27631 
27632 #define S_ENABLECHDRAFULL    4
27633 #define V_ENABLECHDRAFULL(x) ((x) << S_ENABLECHDRAFULL)
27634 #define F_ENABLECHDRAFULL    V_ENABLECHDRAFULL(1U)
27635 
27636 #define S_ENABLEEMACAFULL    3
27637 #define V_ENABLEEMACAFULL(x) ((x) << S_ENABLEEMACAFULL)
27638 #define F_ENABLEEMACAFULL    V_ENABLEEMACAFULL(1U)
27639 
27640 #define S_ENABLENONOFDTIDRSS    2
27641 #define V_ENABLENONOFDTIDRSS(x) ((x) << S_ENABLENONOFDTIDRSS)
27642 #define F_ENABLENONOFDTIDRSS    V_ENABLENONOFDTIDRSS(1U)
27643 
27644 #define S_ENABLENONOFDTCBRSS    1
27645 #define V_ENABLENONOFDTCBRSS(x) ((x) << S_ENABLENONOFDTCBRSS)
27646 #define F_ENABLENONOFDTCBRSS    V_ENABLENONOFDTCBRSS(1U)
27647 
27648 #define S_ENABLETNLOFDCLOSED    0
27649 #define V_ENABLETNLOFDCLOSED(x) ((x) << S_ENABLETNLOFDCLOSED)
27650 #define F_ENABLETNLOFDCLOSED    V_ENABLETNLOFDCLOSED(1U)
27651 
27652 #define S_ENABLEFINDDPOFF    14
27653 #define V_ENABLEFINDDPOFF(x) ((x) << S_ENABLEFINDDPOFF)
27654 #define F_ENABLEFINDDPOFF    V_ENABLEFINDDPOFF(1U)
27655 
27656 #define A_TP_TCP_BACKOFF_REG0 0x7d50
27657 
27658 #define S_TIMERBACKOFFINDEX3    24
27659 #define M_TIMERBACKOFFINDEX3    0xffU
27660 #define V_TIMERBACKOFFINDEX3(x) ((x) << S_TIMERBACKOFFINDEX3)
27661 #define G_TIMERBACKOFFINDEX3(x) (((x) >> S_TIMERBACKOFFINDEX3) & M_TIMERBACKOFFINDEX3)
27662 
27663 #define S_TIMERBACKOFFINDEX2    16
27664 #define M_TIMERBACKOFFINDEX2    0xffU
27665 #define V_TIMERBACKOFFINDEX2(x) ((x) << S_TIMERBACKOFFINDEX2)
27666 #define G_TIMERBACKOFFINDEX2(x) (((x) >> S_TIMERBACKOFFINDEX2) & M_TIMERBACKOFFINDEX2)
27667 
27668 #define S_TIMERBACKOFFINDEX1    8
27669 #define M_TIMERBACKOFFINDEX1    0xffU
27670 #define V_TIMERBACKOFFINDEX1(x) ((x) << S_TIMERBACKOFFINDEX1)
27671 #define G_TIMERBACKOFFINDEX1(x) (((x) >> S_TIMERBACKOFFINDEX1) & M_TIMERBACKOFFINDEX1)
27672 
27673 #define S_TIMERBACKOFFINDEX0    0
27674 #define M_TIMERBACKOFFINDEX0    0xffU
27675 #define V_TIMERBACKOFFINDEX0(x) ((x) << S_TIMERBACKOFFINDEX0)
27676 #define G_TIMERBACKOFFINDEX0(x) (((x) >> S_TIMERBACKOFFINDEX0) & M_TIMERBACKOFFINDEX0)
27677 
27678 #define A_TP_TCP_BACKOFF_REG1 0x7d54
27679 
27680 #define S_TIMERBACKOFFINDEX7    24
27681 #define M_TIMERBACKOFFINDEX7    0xffU
27682 #define V_TIMERBACKOFFINDEX7(x) ((x) << S_TIMERBACKOFFINDEX7)
27683 #define G_TIMERBACKOFFINDEX7(x) (((x) >> S_TIMERBACKOFFINDEX7) & M_TIMERBACKOFFINDEX7)
27684 
27685 #define S_TIMERBACKOFFINDEX6    16
27686 #define M_TIMERBACKOFFINDEX6    0xffU
27687 #define V_TIMERBACKOFFINDEX6(x) ((x) << S_TIMERBACKOFFINDEX6)
27688 #define G_TIMERBACKOFFINDEX6(x) (((x) >> S_TIMERBACKOFFINDEX6) & M_TIMERBACKOFFINDEX6)
27689 
27690 #define S_TIMERBACKOFFINDEX5    8
27691 #define M_TIMERBACKOFFINDEX5    0xffU
27692 #define V_TIMERBACKOFFINDEX5(x) ((x) << S_TIMERBACKOFFINDEX5)
27693 #define G_TIMERBACKOFFINDEX5(x) (((x) >> S_TIMERBACKOFFINDEX5) & M_TIMERBACKOFFINDEX5)
27694 
27695 #define S_TIMERBACKOFFINDEX4    0
27696 #define M_TIMERBACKOFFINDEX4    0xffU
27697 #define V_TIMERBACKOFFINDEX4(x) ((x) << S_TIMERBACKOFFINDEX4)
27698 #define G_TIMERBACKOFFINDEX4(x) (((x) >> S_TIMERBACKOFFINDEX4) & M_TIMERBACKOFFINDEX4)
27699 
27700 #define A_TP_TCP_BACKOFF_REG2 0x7d58
27701 
27702 #define S_TIMERBACKOFFINDEX11    24
27703 #define M_TIMERBACKOFFINDEX11    0xffU
27704 #define V_TIMERBACKOFFINDEX11(x) ((x) << S_TIMERBACKOFFINDEX11)
27705 #define G_TIMERBACKOFFINDEX11(x) (((x) >> S_TIMERBACKOFFINDEX11) & M_TIMERBACKOFFINDEX11)
27706 
27707 #define S_TIMERBACKOFFINDEX10    16
27708 #define M_TIMERBACKOFFINDEX10    0xffU
27709 #define V_TIMERBACKOFFINDEX10(x) ((x) << S_TIMERBACKOFFINDEX10)
27710 #define G_TIMERBACKOFFINDEX10(x) (((x) >> S_TIMERBACKOFFINDEX10) & M_TIMERBACKOFFINDEX10)
27711 
27712 #define S_TIMERBACKOFFINDEX9    8
27713 #define M_TIMERBACKOFFINDEX9    0xffU
27714 #define V_TIMERBACKOFFINDEX9(x) ((x) << S_TIMERBACKOFFINDEX9)
27715 #define G_TIMERBACKOFFINDEX9(x) (((x) >> S_TIMERBACKOFFINDEX9) & M_TIMERBACKOFFINDEX9)
27716 
27717 #define S_TIMERBACKOFFINDEX8    0
27718 #define M_TIMERBACKOFFINDEX8    0xffU
27719 #define V_TIMERBACKOFFINDEX8(x) ((x) << S_TIMERBACKOFFINDEX8)
27720 #define G_TIMERBACKOFFINDEX8(x) (((x) >> S_TIMERBACKOFFINDEX8) & M_TIMERBACKOFFINDEX8)
27721 
27722 #define A_TP_TCP_BACKOFF_REG3 0x7d5c
27723 
27724 #define S_TIMERBACKOFFINDEX15    24
27725 #define M_TIMERBACKOFFINDEX15    0xffU
27726 #define V_TIMERBACKOFFINDEX15(x) ((x) << S_TIMERBACKOFFINDEX15)
27727 #define G_TIMERBACKOFFINDEX15(x) (((x) >> S_TIMERBACKOFFINDEX15) & M_TIMERBACKOFFINDEX15)
27728 
27729 #define S_TIMERBACKOFFINDEX14    16
27730 #define M_TIMERBACKOFFINDEX14    0xffU
27731 #define V_TIMERBACKOFFINDEX14(x) ((x) << S_TIMERBACKOFFINDEX14)
27732 #define G_TIMERBACKOFFINDEX14(x) (((x) >> S_TIMERBACKOFFINDEX14) & M_TIMERBACKOFFINDEX14)
27733 
27734 #define S_TIMERBACKOFFINDEX13    8
27735 #define M_TIMERBACKOFFINDEX13    0xffU
27736 #define V_TIMERBACKOFFINDEX13(x) ((x) << S_TIMERBACKOFFINDEX13)
27737 #define G_TIMERBACKOFFINDEX13(x) (((x) >> S_TIMERBACKOFFINDEX13) & M_TIMERBACKOFFINDEX13)
27738 
27739 #define S_TIMERBACKOFFINDEX12    0
27740 #define M_TIMERBACKOFFINDEX12    0xffU
27741 #define V_TIMERBACKOFFINDEX12(x) ((x) << S_TIMERBACKOFFINDEX12)
27742 #define G_TIMERBACKOFFINDEX12(x) (((x) >> S_TIMERBACKOFFINDEX12) & M_TIMERBACKOFFINDEX12)
27743 
27744 #define A_TP_PARA_REG0 0x7d60
27745 
27746 #define S_INITCWNDIDLE    27
27747 #define V_INITCWNDIDLE(x) ((x) << S_INITCWNDIDLE)
27748 #define F_INITCWNDIDLE    V_INITCWNDIDLE(1U)
27749 
27750 #define S_INITCWND    24
27751 #define M_INITCWND    0x7U
27752 #define V_INITCWND(x) ((x) << S_INITCWND)
27753 #define G_INITCWND(x) (((x) >> S_INITCWND) & M_INITCWND)
27754 
27755 #define S_DUPACKTHRESH    20
27756 #define M_DUPACKTHRESH    0xfU
27757 #define V_DUPACKTHRESH(x) ((x) << S_DUPACKTHRESH)
27758 #define G_DUPACKTHRESH(x) (((x) >> S_DUPACKTHRESH) & M_DUPACKTHRESH)
27759 
27760 #define S_CPLERRENABLE    12
27761 #define V_CPLERRENABLE(x) ((x) << S_CPLERRENABLE)
27762 #define F_CPLERRENABLE    V_CPLERRENABLE(1U)
27763 
27764 #define S_FASTTNLCNT    11
27765 #define V_FASTTNLCNT(x) ((x) << S_FASTTNLCNT)
27766 #define F_FASTTNLCNT    V_FASTTNLCNT(1U)
27767 
27768 #define S_FASTTBLCNT    10
27769 #define V_FASTTBLCNT(x) ((x) << S_FASTTBLCNT)
27770 #define F_FASTTBLCNT    V_FASTTBLCNT(1U)
27771 
27772 #define S_TPTCAMKEY    9
27773 #define V_TPTCAMKEY(x) ((x) << S_TPTCAMKEY)
27774 #define F_TPTCAMKEY    V_TPTCAMKEY(1U)
27775 
27776 #define S_SWSMODE    8
27777 #define V_SWSMODE(x) ((x) << S_SWSMODE)
27778 #define F_SWSMODE    V_SWSMODE(1U)
27779 
27780 #define S_TSMPMODE    6
27781 #define M_TSMPMODE    0x3U
27782 #define V_TSMPMODE(x) ((x) << S_TSMPMODE)
27783 #define G_TSMPMODE(x) (((x) >> S_TSMPMODE) & M_TSMPMODE)
27784 
27785 #define S_BYTECOUNTLIMIT    4
27786 #define M_BYTECOUNTLIMIT    0x3U
27787 #define V_BYTECOUNTLIMIT(x) ((x) << S_BYTECOUNTLIMIT)
27788 #define G_BYTECOUNTLIMIT(x) (((x) >> S_BYTECOUNTLIMIT) & M_BYTECOUNTLIMIT)
27789 
27790 #define S_SWSSHOVE    3
27791 #define V_SWSSHOVE(x) ((x) << S_SWSSHOVE)
27792 #define F_SWSSHOVE    V_SWSSHOVE(1U)
27793 
27794 #define S_TBLTIMER    2
27795 #define V_TBLTIMER(x) ((x) << S_TBLTIMER)
27796 #define F_TBLTIMER    V_TBLTIMER(1U)
27797 
27798 #define S_RXTPACE    1
27799 #define V_RXTPACE(x) ((x) << S_RXTPACE)
27800 #define F_RXTPACE    V_RXTPACE(1U)
27801 
27802 #define S_SWSTIMER    0
27803 #define V_SWSTIMER(x) ((x) << S_SWSTIMER)
27804 #define F_SWSTIMER    V_SWSTIMER(1U)
27805 
27806 #define S_LIMTXTHRESH    28
27807 #define M_LIMTXTHRESH    0xfU
27808 #define V_LIMTXTHRESH(x) ((x) << S_LIMTXTHRESH)
27809 #define G_LIMTXTHRESH(x) (((x) >> S_LIMTXTHRESH) & M_LIMTXTHRESH)
27810 
27811 #define S_CHNERRENABLE    14
27812 #define V_CHNERRENABLE(x) ((x) << S_CHNERRENABLE)
27813 #define F_CHNERRENABLE    V_CHNERRENABLE(1U)
27814 
27815 #define S_SETTIMEENABLE    13
27816 #define V_SETTIMEENABLE(x) ((x) << S_SETTIMEENABLE)
27817 #define F_SETTIMEENABLE    V_SETTIMEENABLE(1U)
27818 
27819 #define S_ECNCNGFIFO    19
27820 #define V_ECNCNGFIFO(x) ((x) << S_ECNCNGFIFO)
27821 #define F_ECNCNGFIFO    V_ECNCNGFIFO(1U)
27822 
27823 #define S_ECNSYNACK    18
27824 #define V_ECNSYNACK(x) ((x) << S_ECNSYNACK)
27825 #define F_ECNSYNACK    V_ECNSYNACK(1U)
27826 
27827 #define S_ECNTHRESH    16
27828 #define M_ECNTHRESH    0x3U
27829 #define V_ECNTHRESH(x) ((x) << S_ECNTHRESH)
27830 #define G_ECNTHRESH(x) (((x) >> S_ECNTHRESH) & M_ECNTHRESH)
27831 
27832 #define S_ECNMODE    15
27833 #define V_ECNMODE(x) ((x) << S_ECNMODE)
27834 #define F_ECNMODE    V_ECNMODE(1U)
27835 
27836 #define S_ECNMODECWR    14
27837 #define V_ECNMODECWR(x) ((x) << S_ECNMODECWR)
27838 #define F_ECNMODECWR    V_ECNMODECWR(1U)
27839 
27840 #define S_FORCESHOVE    10
27841 #define V_FORCESHOVE(x) ((x) << S_FORCESHOVE)
27842 #define F_FORCESHOVE    V_FORCESHOVE(1U)
27843 
27844 #define A_TP_PARA_REG1 0x7d64
27845 
27846 #define S_INITRWND    16
27847 #define M_INITRWND    0xffffU
27848 #define V_INITRWND(x) ((x) << S_INITRWND)
27849 #define G_INITRWND(x) (((x) >> S_INITRWND) & M_INITRWND)
27850 
27851 #define S_INITIALSSTHRESH    0
27852 #define M_INITIALSSTHRESH    0xffffU
27853 #define V_INITIALSSTHRESH(x) ((x) << S_INITIALSSTHRESH)
27854 #define G_INITIALSSTHRESH(x) (((x) >> S_INITIALSSTHRESH) & M_INITIALSSTHRESH)
27855 
27856 #define A_TP_PARA_REG2 0x7d68
27857 
27858 #define S_MAXRXDATA    16
27859 #define M_MAXRXDATA    0xffffU
27860 #define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
27861 #define G_MAXRXDATA(x) (((x) >> S_MAXRXDATA) & M_MAXRXDATA)
27862 
27863 #define S_RXCOALESCESIZE    0
27864 #define M_RXCOALESCESIZE    0xffffU
27865 #define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
27866 #define G_RXCOALESCESIZE(x) (((x) >> S_RXCOALESCESIZE) & M_RXCOALESCESIZE)
27867 
27868 #define A_TP_PARA_REG3 0x7d6c
27869 
27870 #define S_ENABLETNLCNGLPBK    31
27871 #define V_ENABLETNLCNGLPBK(x) ((x) << S_ENABLETNLCNGLPBK)
27872 #define F_ENABLETNLCNGLPBK    V_ENABLETNLCNGLPBK(1U)
27873 
27874 #define S_ENABLETNLCNGFIFO    30
27875 #define V_ENABLETNLCNGFIFO(x) ((x) << S_ENABLETNLCNGFIFO)
27876 #define F_ENABLETNLCNGFIFO    V_ENABLETNLCNGFIFO(1U)
27877 
27878 #define S_ENABLETNLCNGHDR    29
27879 #define V_ENABLETNLCNGHDR(x) ((x) << S_ENABLETNLCNGHDR)
27880 #define F_ENABLETNLCNGHDR    V_ENABLETNLCNGHDR(1U)
27881 
27882 #define S_ENABLETNLCNGSGE    28
27883 #define V_ENABLETNLCNGSGE(x) ((x) << S_ENABLETNLCNGSGE)
27884 #define F_ENABLETNLCNGSGE    V_ENABLETNLCNGSGE(1U)
27885 
27886 #define S_RXMACCHECK    27
27887 #define V_RXMACCHECK(x) ((x) << S_RXMACCHECK)
27888 #define F_RXMACCHECK    V_RXMACCHECK(1U)
27889 
27890 #define S_RXSYNFILTER    26
27891 #define V_RXSYNFILTER(x) ((x) << S_RXSYNFILTER)
27892 #define F_RXSYNFILTER    V_RXSYNFILTER(1U)
27893 
27894 #define S_CNGCTRLECN    25
27895 #define V_CNGCTRLECN(x) ((x) << S_CNGCTRLECN)
27896 #define F_CNGCTRLECN    V_CNGCTRLECN(1U)
27897 
27898 #define S_RXDDPOFFINIT    24
27899 #define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT)
27900 #define F_RXDDPOFFINIT    V_RXDDPOFFINIT(1U)
27901 
27902 #define S_TUNNELCNGDROP3    23
27903 #define V_TUNNELCNGDROP3(x) ((x) << S_TUNNELCNGDROP3)
27904 #define F_TUNNELCNGDROP3    V_TUNNELCNGDROP3(1U)
27905 
27906 #define S_TUNNELCNGDROP2    22
27907 #define V_TUNNELCNGDROP2(x) ((x) << S_TUNNELCNGDROP2)
27908 #define F_TUNNELCNGDROP2    V_TUNNELCNGDROP2(1U)
27909 
27910 #define S_TUNNELCNGDROP1    21
27911 #define V_TUNNELCNGDROP1(x) ((x) << S_TUNNELCNGDROP1)
27912 #define F_TUNNELCNGDROP1    V_TUNNELCNGDROP1(1U)
27913 
27914 #define S_TUNNELCNGDROP0    20
27915 #define V_TUNNELCNGDROP0(x) ((x) << S_TUNNELCNGDROP0)
27916 #define F_TUNNELCNGDROP0    V_TUNNELCNGDROP0(1U)
27917 
27918 #define S_TXDATAACKIDX    16
27919 #define M_TXDATAACKIDX    0xfU
27920 #define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX)
27921 #define G_TXDATAACKIDX(x) (((x) >> S_TXDATAACKIDX) & M_TXDATAACKIDX)
27922 
27923 #define S_RXFRAGENABLE    12
27924 #define M_RXFRAGENABLE    0x7U
27925 #define V_RXFRAGENABLE(x) ((x) << S_RXFRAGENABLE)
27926 #define G_RXFRAGENABLE(x) (((x) >> S_RXFRAGENABLE) & M_RXFRAGENABLE)
27927 
27928 #define S_TXPACEFIXEDSTRICT    11
27929 #define V_TXPACEFIXEDSTRICT(x) ((x) << S_TXPACEFIXEDSTRICT)
27930 #define F_TXPACEFIXEDSTRICT    V_TXPACEFIXEDSTRICT(1U)
27931 
27932 #define S_TXPACEAUTOSTRICT    10
27933 #define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT)
27934 #define F_TXPACEAUTOSTRICT    V_TXPACEAUTOSTRICT(1U)
27935 
27936 #define S_TXPACEFIXED    9
27937 #define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED)
27938 #define F_TXPACEFIXED    V_TXPACEFIXED(1U)
27939 
27940 #define S_TXPACEAUTO    8
27941 #define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO)
27942 #define F_TXPACEAUTO    V_TXPACEAUTO(1U)
27943 
27944 #define S_RXCHNTUNNEL    7
27945 #define V_RXCHNTUNNEL(x) ((x) << S_RXCHNTUNNEL)
27946 #define F_RXCHNTUNNEL    V_RXCHNTUNNEL(1U)
27947 
27948 #define S_RXURGTUNNEL    6
27949 #define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL)
27950 #define F_RXURGTUNNEL    V_RXURGTUNNEL(1U)
27951 
27952 #define S_RXURGMODE    5
27953 #define V_RXURGMODE(x) ((x) << S_RXURGMODE)
27954 #define F_RXURGMODE    V_RXURGMODE(1U)
27955 
27956 #define S_TXURGMODE    4
27957 #define V_TXURGMODE(x) ((x) << S_TXURGMODE)
27958 #define F_TXURGMODE    V_TXURGMODE(1U)
27959 
27960 #define S_CNGCTRLMODE    2
27961 #define M_CNGCTRLMODE    0x3U
27962 #define V_CNGCTRLMODE(x) ((x) << S_CNGCTRLMODE)
27963 #define G_CNGCTRLMODE(x) (((x) >> S_CNGCTRLMODE) & M_CNGCTRLMODE)
27964 
27965 #define S_RXCOALESCEENABLE    1
27966 #define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE)
27967 #define F_RXCOALESCEENABLE    V_RXCOALESCEENABLE(1U)
27968 
27969 #define S_RXCOALESCEPSHEN    0
27970 #define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN)
27971 #define F_RXCOALESCEPSHEN    V_RXCOALESCEPSHEN(1U)
27972 
27973 #define A_TP_PARA_REG4 0x7d70
27974 
27975 #define S_HIGHSPEEDCFG    24
27976 #define M_HIGHSPEEDCFG    0xffU
27977 #define V_HIGHSPEEDCFG(x) ((x) << S_HIGHSPEEDCFG)
27978 #define G_HIGHSPEEDCFG(x) (((x) >> S_HIGHSPEEDCFG) & M_HIGHSPEEDCFG)
27979 
27980 #define S_NEWRENOCFG    16
27981 #define M_NEWRENOCFG    0xffU
27982 #define V_NEWRENOCFG(x) ((x) << S_NEWRENOCFG)
27983 #define G_NEWRENOCFG(x) (((x) >> S_NEWRENOCFG) & M_NEWRENOCFG)
27984 
27985 #define S_TAHOECFG    8
27986 #define M_TAHOECFG    0xffU
27987 #define V_TAHOECFG(x) ((x) << S_TAHOECFG)
27988 #define G_TAHOECFG(x) (((x) >> S_TAHOECFG) & M_TAHOECFG)
27989 
27990 #define S_RENOCFG    0
27991 #define M_RENOCFG    0xffU
27992 #define V_RENOCFG(x) ((x) << S_RENOCFG)
27993 #define G_RENOCFG(x) (((x) >> S_RENOCFG) & M_RENOCFG)
27994 
27995 #define S_IDLECWNDHIGHSPEED    28
27996 #define V_IDLECWNDHIGHSPEED(x) ((x) << S_IDLECWNDHIGHSPEED)
27997 #define F_IDLECWNDHIGHSPEED    V_IDLECWNDHIGHSPEED(1U)
27998 
27999 #define S_RXMTCWNDHIGHSPEED    27
28000 #define V_RXMTCWNDHIGHSPEED(x) ((x) << S_RXMTCWNDHIGHSPEED)
28001 #define F_RXMTCWNDHIGHSPEED    V_RXMTCWNDHIGHSPEED(1U)
28002 
28003 #define S_OVERDRIVEHIGHSPEED    25
28004 #define M_OVERDRIVEHIGHSPEED    0x3U
28005 #define V_OVERDRIVEHIGHSPEED(x) ((x) << S_OVERDRIVEHIGHSPEED)
28006 #define G_OVERDRIVEHIGHSPEED(x) (((x) >> S_OVERDRIVEHIGHSPEED) & M_OVERDRIVEHIGHSPEED)
28007 
28008 #define S_BYTECOUNTHIGHSPEED    24
28009 #define V_BYTECOUNTHIGHSPEED(x) ((x) << S_BYTECOUNTHIGHSPEED)
28010 #define F_BYTECOUNTHIGHSPEED    V_BYTECOUNTHIGHSPEED(1U)
28011 
28012 #define S_IDLECWNDNEWRENO    20
28013 #define V_IDLECWNDNEWRENO(x) ((x) << S_IDLECWNDNEWRENO)
28014 #define F_IDLECWNDNEWRENO    V_IDLECWNDNEWRENO(1U)
28015 
28016 #define S_RXMTCWNDNEWRENO    19
28017 #define V_RXMTCWNDNEWRENO(x) ((x) << S_RXMTCWNDNEWRENO)
28018 #define F_RXMTCWNDNEWRENO    V_RXMTCWNDNEWRENO(1U)
28019 
28020 #define S_OVERDRIVENEWRENO    17
28021 #define M_OVERDRIVENEWRENO    0x3U
28022 #define V_OVERDRIVENEWRENO(x) ((x) << S_OVERDRIVENEWRENO)
28023 #define G_OVERDRIVENEWRENO(x) (((x) >> S_OVERDRIVENEWRENO) & M_OVERDRIVENEWRENO)
28024 
28025 #define S_BYTECOUNTNEWRENO    16
28026 #define V_BYTECOUNTNEWRENO(x) ((x) << S_BYTECOUNTNEWRENO)
28027 #define F_BYTECOUNTNEWRENO    V_BYTECOUNTNEWRENO(1U)
28028 
28029 #define S_IDLECWNDTAHOE    12
28030 #define V_IDLECWNDTAHOE(x) ((x) << S_IDLECWNDTAHOE)
28031 #define F_IDLECWNDTAHOE    V_IDLECWNDTAHOE(1U)
28032 
28033 #define S_RXMTCWNDTAHOE    11
28034 #define V_RXMTCWNDTAHOE(x) ((x) << S_RXMTCWNDTAHOE)
28035 #define F_RXMTCWNDTAHOE    V_RXMTCWNDTAHOE(1U)
28036 
28037 #define S_OVERDRIVETAHOE    9
28038 #define M_OVERDRIVETAHOE    0x3U
28039 #define V_OVERDRIVETAHOE(x) ((x) << S_OVERDRIVETAHOE)
28040 #define G_OVERDRIVETAHOE(x) (((x) >> S_OVERDRIVETAHOE) & M_OVERDRIVETAHOE)
28041 
28042 #define S_BYTECOUNTTAHOE    8
28043 #define V_BYTECOUNTTAHOE(x) ((x) << S_BYTECOUNTTAHOE)
28044 #define F_BYTECOUNTTAHOE    V_BYTECOUNTTAHOE(1U)
28045 
28046 #define S_IDLECWNDRENO    4
28047 #define V_IDLECWNDRENO(x) ((x) << S_IDLECWNDRENO)
28048 #define F_IDLECWNDRENO    V_IDLECWNDRENO(1U)
28049 
28050 #define S_RXMTCWNDRENO    3
28051 #define V_RXMTCWNDRENO(x) ((x) << S_RXMTCWNDRENO)
28052 #define F_RXMTCWNDRENO    V_RXMTCWNDRENO(1U)
28053 
28054 #define S_OVERDRIVERENO    1
28055 #define M_OVERDRIVERENO    0x3U
28056 #define V_OVERDRIVERENO(x) ((x) << S_OVERDRIVERENO)
28057 #define G_OVERDRIVERENO(x) (((x) >> S_OVERDRIVERENO) & M_OVERDRIVERENO)
28058 
28059 #define S_BYTECOUNTRENO    0
28060 #define V_BYTECOUNTRENO(x) ((x) << S_BYTECOUNTRENO)
28061 #define F_BYTECOUNTRENO    V_BYTECOUNTRENO(1U)
28062 
28063 #define A_TP_PARA_REG5 0x7d74
28064 
28065 #define S_INDICATESIZE    16
28066 #define M_INDICATESIZE    0xffffU
28067 #define V_INDICATESIZE(x) ((x) << S_INDICATESIZE)
28068 #define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE)
28069 
28070 #define S_MAXPROXYSIZE    12
28071 #define M_MAXPROXYSIZE    0xfU
28072 #define V_MAXPROXYSIZE(x) ((x) << S_MAXPROXYSIZE)
28073 #define G_MAXPROXYSIZE(x) (((x) >> S_MAXPROXYSIZE) & M_MAXPROXYSIZE)
28074 
28075 #define S_ENABLEREADPDU    11
28076 #define V_ENABLEREADPDU(x) ((x) << S_ENABLEREADPDU)
28077 #define F_ENABLEREADPDU    V_ENABLEREADPDU(1U)
28078 
28079 #define S_RXREADAHEAD    10
28080 #define V_RXREADAHEAD(x) ((x) << S_RXREADAHEAD)
28081 #define F_RXREADAHEAD    V_RXREADAHEAD(1U)
28082 
28083 #define S_EMPTYRQENABLE    9
28084 #define V_EMPTYRQENABLE(x) ((x) << S_EMPTYRQENABLE)
28085 #define F_EMPTYRQENABLE    V_EMPTYRQENABLE(1U)
28086 
28087 #define S_SCHDENABLE    8
28088 #define V_SCHDENABLE(x) ((x) << S_SCHDENABLE)
28089 #define F_SCHDENABLE    V_SCHDENABLE(1U)
28090 
28091 #define S_REARMDDPOFFSET    4
28092 #define V_REARMDDPOFFSET(x) ((x) << S_REARMDDPOFFSET)
28093 #define F_REARMDDPOFFSET    V_REARMDDPOFFSET(1U)
28094 
28095 #define S_RESETDDPOFFSET    3
28096 #define V_RESETDDPOFFSET(x) ((x) << S_RESETDDPOFFSET)
28097 #define F_RESETDDPOFFSET    V_RESETDDPOFFSET(1U)
28098 
28099 #define S_ONFLYDDPENABLE    2
28100 #define V_ONFLYDDPENABLE(x) ((x) << S_ONFLYDDPENABLE)
28101 #define F_ONFLYDDPENABLE    V_ONFLYDDPENABLE(1U)
28102 
28103 #define S_DACKTIMERSPIN    1
28104 #define V_DACKTIMERSPIN(x) ((x) << S_DACKTIMERSPIN)
28105 #define F_DACKTIMERSPIN    V_DACKTIMERSPIN(1U)
28106 
28107 #define S_PUSHTIMERENABLE    0
28108 #define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE)
28109 #define F_PUSHTIMERENABLE    V_PUSHTIMERENABLE(1U)
28110 
28111 #define S_ENABLEXOFFPDU    7
28112 #define V_ENABLEXOFFPDU(x) ((x) << S_ENABLEXOFFPDU)
28113 #define F_ENABLEXOFFPDU    V_ENABLEXOFFPDU(1U)
28114 
28115 #define S_ENABLENEWFAR    6
28116 #define V_ENABLENEWFAR(x) ((x) << S_ENABLENEWFAR)
28117 #define F_ENABLENEWFAR    V_ENABLENEWFAR(1U)
28118 
28119 #define S_ENABLEFRAGCHECK    5
28120 #define V_ENABLEFRAGCHECK(x) ((x) << S_ENABLEFRAGCHECK)
28121 #define F_ENABLEFRAGCHECK    V_ENABLEFRAGCHECK(1U)
28122 
28123 #define S_ENABLEFCOECHECK    6
28124 #define V_ENABLEFCOECHECK(x) ((x) << S_ENABLEFCOECHECK)
28125 #define F_ENABLEFCOECHECK    V_ENABLEFCOECHECK(1U)
28126 
28127 #define S_ENABLERDMAFIX    1
28128 #define V_ENABLERDMAFIX(x) ((x) << S_ENABLERDMAFIX)
28129 #define F_ENABLERDMAFIX    V_ENABLERDMAFIX(1U)
28130 
28131 #define A_TP_PARA_REG6 0x7d78
28132 
28133 #define S_TXPDUSIZEADJ    24
28134 #define M_TXPDUSIZEADJ    0xffU
28135 #define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ)
28136 #define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ)
28137 
28138 #define S_LIMITEDTRANSMIT    20
28139 #define M_LIMITEDTRANSMIT    0xfU
28140 #define V_LIMITEDTRANSMIT(x) ((x) << S_LIMITEDTRANSMIT)
28141 #define G_LIMITEDTRANSMIT(x) (((x) >> S_LIMITEDTRANSMIT) & M_LIMITEDTRANSMIT)
28142 
28143 #define S_ENABLECSAV    19
28144 #define V_ENABLECSAV(x) ((x) << S_ENABLECSAV)
28145 #define F_ENABLECSAV    V_ENABLECSAV(1U)
28146 
28147 #define S_ENABLEDEFERPDU    18
28148 #define V_ENABLEDEFERPDU(x) ((x) << S_ENABLEDEFERPDU)
28149 #define F_ENABLEDEFERPDU    V_ENABLEDEFERPDU(1U)
28150 
28151 #define S_ENABLEFLUSH    17
28152 #define V_ENABLEFLUSH(x) ((x) << S_ENABLEFLUSH)
28153 #define F_ENABLEFLUSH    V_ENABLEFLUSH(1U)
28154 
28155 #define S_ENABLEBYTEPERSIST    16
28156 #define V_ENABLEBYTEPERSIST(x) ((x) << S_ENABLEBYTEPERSIST)
28157 #define F_ENABLEBYTEPERSIST    V_ENABLEBYTEPERSIST(1U)
28158 
28159 #define S_DISABLETMOCNG    15
28160 #define V_DISABLETMOCNG(x) ((x) << S_DISABLETMOCNG)
28161 #define F_DISABLETMOCNG    V_DISABLETMOCNG(1U)
28162 
28163 #define S_TXREADAHEAD    14
28164 #define V_TXREADAHEAD(x) ((x) << S_TXREADAHEAD)
28165 #define F_TXREADAHEAD    V_TXREADAHEAD(1U)
28166 
28167 #define S_ALLOWEXEPTION    13
28168 #define V_ALLOWEXEPTION(x) ((x) << S_ALLOWEXEPTION)
28169 #define F_ALLOWEXEPTION    V_ALLOWEXEPTION(1U)
28170 
28171 #define S_ENABLEDEFERACK    12
28172 #define V_ENABLEDEFERACK(x) ((x) << S_ENABLEDEFERACK)
28173 #define F_ENABLEDEFERACK    V_ENABLEDEFERACK(1U)
28174 
28175 #define S_ENABLEESND    11
28176 #define V_ENABLEESND(x) ((x) << S_ENABLEESND)
28177 #define F_ENABLEESND    V_ENABLEESND(1U)
28178 
28179 #define S_ENABLECSND    10
28180 #define V_ENABLECSND(x) ((x) << S_ENABLECSND)
28181 #define F_ENABLECSND    V_ENABLECSND(1U)
28182 
28183 #define S_ENABLEPDUE    9
28184 #define V_ENABLEPDUE(x) ((x) << S_ENABLEPDUE)
28185 #define F_ENABLEPDUE    V_ENABLEPDUE(1U)
28186 
28187 #define S_ENABLEPDUC    8
28188 #define V_ENABLEPDUC(x) ((x) << S_ENABLEPDUC)
28189 #define F_ENABLEPDUC    V_ENABLEPDUC(1U)
28190 
28191 #define S_ENABLEBUFI    7
28192 #define V_ENABLEBUFI(x) ((x) << S_ENABLEBUFI)
28193 #define F_ENABLEBUFI    V_ENABLEBUFI(1U)
28194 
28195 #define S_ENABLEBUFE    6
28196 #define V_ENABLEBUFE(x) ((x) << S_ENABLEBUFE)
28197 #define F_ENABLEBUFE    V_ENABLEBUFE(1U)
28198 
28199 #define S_ENABLEDEFER    5
28200 #define V_ENABLEDEFER(x) ((x) << S_ENABLEDEFER)
28201 #define F_ENABLEDEFER    V_ENABLEDEFER(1U)
28202 
28203 #define S_ENABLECLEARRXMTOOS    4
28204 #define V_ENABLECLEARRXMTOOS(x) ((x) << S_ENABLECLEARRXMTOOS)
28205 #define F_ENABLECLEARRXMTOOS    V_ENABLECLEARRXMTOOS(1U)
28206 
28207 #define S_DISABLEPDUCNG    3
28208 #define V_DISABLEPDUCNG(x) ((x) << S_DISABLEPDUCNG)
28209 #define F_DISABLEPDUCNG    V_DISABLEPDUCNG(1U)
28210 
28211 #define S_DISABLEPDUTIMEOUT    2
28212 #define V_DISABLEPDUTIMEOUT(x) ((x) << S_DISABLEPDUTIMEOUT)
28213 #define F_DISABLEPDUTIMEOUT    V_DISABLEPDUTIMEOUT(1U)
28214 
28215 #define S_DISABLEPDURXMT    1
28216 #define V_DISABLEPDURXMT(x) ((x) << S_DISABLEPDURXMT)
28217 #define F_DISABLEPDURXMT    V_DISABLEPDURXMT(1U)
28218 
28219 #define S_DISABLEPDUXMT    0
28220 #define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT)
28221 #define F_DISABLEPDUXMT    V_DISABLEPDUXMT(1U)
28222 
28223 #define S_DISABLEPDUACK    20
28224 #define V_DISABLEPDUACK(x) ((x) << S_DISABLEPDUACK)
28225 #define F_DISABLEPDUACK    V_DISABLEPDUACK(1U)
28226 
28227 #define S_TXTCAMKEY    22
28228 #define V_TXTCAMKEY(x) ((x) << S_TXTCAMKEY)
28229 #define F_TXTCAMKEY    V_TXTCAMKEY(1U)
28230 
28231 #define S_ENABLECBYP    21
28232 #define V_ENABLECBYP(x) ((x) << S_ENABLECBYP)
28233 #define F_ENABLECBYP    V_ENABLECBYP(1U)
28234 
28235 #define A_TP_PARA_REG7 0x7d7c
28236 
28237 #define S_PMMAXXFERLEN1    16
28238 #define M_PMMAXXFERLEN1    0xffffU
28239 #define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1)
28240 #define G_PMMAXXFERLEN1(x) (((x) >> S_PMMAXXFERLEN1) & M_PMMAXXFERLEN1)
28241 
28242 #define S_PMMAXXFERLEN0    0
28243 #define M_PMMAXXFERLEN0    0xffffU
28244 #define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0)
28245 #define G_PMMAXXFERLEN0(x) (((x) >> S_PMMAXXFERLEN0) & M_PMMAXXFERLEN0)
28246 
28247 #define A_TP_ENG_CONFIG 0x7d80
28248 
28249 #define S_TABLELATENCYDONE    28
28250 #define M_TABLELATENCYDONE    0xfU
28251 #define V_TABLELATENCYDONE(x) ((x) << S_TABLELATENCYDONE)
28252 #define G_TABLELATENCYDONE(x) (((x) >> S_TABLELATENCYDONE) & M_TABLELATENCYDONE)
28253 
28254 #define S_TABLELATENCYSTART    24
28255 #define M_TABLELATENCYSTART    0xfU
28256 #define V_TABLELATENCYSTART(x) ((x) << S_TABLELATENCYSTART)
28257 #define G_TABLELATENCYSTART(x) (((x) >> S_TABLELATENCYSTART) & M_TABLELATENCYSTART)
28258 
28259 #define S_ENGINELATENCYDELTA    16
28260 #define M_ENGINELATENCYDELTA    0xfU
28261 #define V_ENGINELATENCYDELTA(x) ((x) << S_ENGINELATENCYDELTA)
28262 #define G_ENGINELATENCYDELTA(x) (((x) >> S_ENGINELATENCYDELTA) & M_ENGINELATENCYDELTA)
28263 
28264 #define S_ENGINELATENCYMMGR    12
28265 #define M_ENGINELATENCYMMGR    0xfU
28266 #define V_ENGINELATENCYMMGR(x) ((x) << S_ENGINELATENCYMMGR)
28267 #define G_ENGINELATENCYMMGR(x) (((x) >> S_ENGINELATENCYMMGR) & M_ENGINELATENCYMMGR)
28268 
28269 #define S_ENGINELATENCYWIREIP6    8
28270 #define M_ENGINELATENCYWIREIP6    0xfU
28271 #define V_ENGINELATENCYWIREIP6(x) ((x) << S_ENGINELATENCYWIREIP6)
28272 #define G_ENGINELATENCYWIREIP6(x) (((x) >> S_ENGINELATENCYWIREIP6) & M_ENGINELATENCYWIREIP6)
28273 
28274 #define S_ENGINELATENCYWIRE    4
28275 #define M_ENGINELATENCYWIRE    0xfU
28276 #define V_ENGINELATENCYWIRE(x) ((x) << S_ENGINELATENCYWIRE)
28277 #define G_ENGINELATENCYWIRE(x) (((x) >> S_ENGINELATENCYWIRE) & M_ENGINELATENCYWIRE)
28278 
28279 #define S_ENGINELATENCYBASE    0
28280 #define M_ENGINELATENCYBASE    0xfU
28281 #define V_ENGINELATENCYBASE(x) ((x) << S_ENGINELATENCYBASE)
28282 #define G_ENGINELATENCYBASE(x) (((x) >> S_ENGINELATENCYBASE) & M_ENGINELATENCYBASE)
28283 
28284 #define A_TP_PARA_REG8 0x7d84
28285 
28286 #define S_ECNACKECT    2
28287 #define V_ECNACKECT(x) ((x) << S_ECNACKECT)
28288 #define F_ECNACKECT    V_ECNACKECT(1U)
28289 
28290 #define S_ECNFINECT    1
28291 #define V_ECNFINECT(x) ((x) << S_ECNFINECT)
28292 #define F_ECNFINECT    V_ECNFINECT(1U)
28293 
28294 #define S_ECNSYNECT    0
28295 #define V_ECNSYNECT(x) ((x) << S_ECNSYNECT)
28296 #define F_ECNSYNECT    V_ECNSYNECT(1U)
28297 
28298 #define A_TP_PARA_REG9 0x7d88
28299 
28300 #define S_PMMAXXFERLEN3    16
28301 #define M_PMMAXXFERLEN3    0xffffU
28302 #define V_PMMAXXFERLEN3(x) ((x) << S_PMMAXXFERLEN3)
28303 #define G_PMMAXXFERLEN3(x) (((x) >> S_PMMAXXFERLEN3) & M_PMMAXXFERLEN3)
28304 
28305 #define S_PMMAXXFERLEN2    0
28306 #define M_PMMAXXFERLEN2    0xffffU
28307 #define V_PMMAXXFERLEN2(x) ((x) << S_PMMAXXFERLEN2)
28308 #define G_PMMAXXFERLEN2(x) (((x) >> S_PMMAXXFERLEN2) & M_PMMAXXFERLEN2)
28309 
28310 #define A_TP_ERR_CONFIG 0x7d8c
28311 
28312 #define S_TNLERRORPING    30
28313 #define V_TNLERRORPING(x) ((x) << S_TNLERRORPING)
28314 #define F_TNLERRORPING    V_TNLERRORPING(1U)
28315 
28316 #define S_TNLERRORCSUM    29
28317 #define V_TNLERRORCSUM(x) ((x) << S_TNLERRORCSUM)
28318 #define F_TNLERRORCSUM    V_TNLERRORCSUM(1U)
28319 
28320 #define S_TNLERRORCSUMIP    28
28321 #define V_TNLERRORCSUMIP(x) ((x) << S_TNLERRORCSUMIP)
28322 #define F_TNLERRORCSUMIP    V_TNLERRORCSUMIP(1U)
28323 
28324 #define S_TNLERRORTCPOPT    25
28325 #define V_TNLERRORTCPOPT(x) ((x) << S_TNLERRORTCPOPT)
28326 #define F_TNLERRORTCPOPT    V_TNLERRORTCPOPT(1U)
28327 
28328 #define S_TNLERRORPKTLEN    24
28329 #define V_TNLERRORPKTLEN(x) ((x) << S_TNLERRORPKTLEN)
28330 #define F_TNLERRORPKTLEN    V_TNLERRORPKTLEN(1U)
28331 
28332 #define S_TNLERRORTCPHDRLEN    23
28333 #define V_TNLERRORTCPHDRLEN(x) ((x) << S_TNLERRORTCPHDRLEN)
28334 #define F_TNLERRORTCPHDRLEN    V_TNLERRORTCPHDRLEN(1U)
28335 
28336 #define S_TNLERRORIPHDRLEN    22
28337 #define V_TNLERRORIPHDRLEN(x) ((x) << S_TNLERRORIPHDRLEN)
28338 #define F_TNLERRORIPHDRLEN    V_TNLERRORIPHDRLEN(1U)
28339 
28340 #define S_TNLERRORETHHDRLEN    21
28341 #define V_TNLERRORETHHDRLEN(x) ((x) << S_TNLERRORETHHDRLEN)
28342 #define F_TNLERRORETHHDRLEN    V_TNLERRORETHHDRLEN(1U)
28343 
28344 #define S_TNLERRORATTACK    20
28345 #define V_TNLERRORATTACK(x) ((x) << S_TNLERRORATTACK)
28346 #define F_TNLERRORATTACK    V_TNLERRORATTACK(1U)
28347 
28348 #define S_TNLERRORFRAG    19
28349 #define V_TNLERRORFRAG(x) ((x) << S_TNLERRORFRAG)
28350 #define F_TNLERRORFRAG    V_TNLERRORFRAG(1U)
28351 
28352 #define S_TNLERRORIPVER    18
28353 #define V_TNLERRORIPVER(x) ((x) << S_TNLERRORIPVER)
28354 #define F_TNLERRORIPVER    V_TNLERRORIPVER(1U)
28355 
28356 #define S_TNLERRORMAC    17
28357 #define V_TNLERRORMAC(x) ((x) << S_TNLERRORMAC)
28358 #define F_TNLERRORMAC    V_TNLERRORMAC(1U)
28359 
28360 #define S_TNLERRORANY    16
28361 #define V_TNLERRORANY(x) ((x) << S_TNLERRORANY)
28362 #define F_TNLERRORANY    V_TNLERRORANY(1U)
28363 
28364 #define S_DROPERRORPING    14
28365 #define V_DROPERRORPING(x) ((x) << S_DROPERRORPING)
28366 #define F_DROPERRORPING    V_DROPERRORPING(1U)
28367 
28368 #define S_DROPERRORCSUM    13
28369 #define V_DROPERRORCSUM(x) ((x) << S_DROPERRORCSUM)
28370 #define F_DROPERRORCSUM    V_DROPERRORCSUM(1U)
28371 
28372 #define S_DROPERRORCSUMIP    12
28373 #define V_DROPERRORCSUMIP(x) ((x) << S_DROPERRORCSUMIP)
28374 #define F_DROPERRORCSUMIP    V_DROPERRORCSUMIP(1U)
28375 
28376 #define S_DROPERRORTCPOPT    9
28377 #define V_DROPERRORTCPOPT(x) ((x) << S_DROPERRORTCPOPT)
28378 #define F_DROPERRORTCPOPT    V_DROPERRORTCPOPT(1U)
28379 
28380 #define S_DROPERRORPKTLEN    8
28381 #define V_DROPERRORPKTLEN(x) ((x) << S_DROPERRORPKTLEN)
28382 #define F_DROPERRORPKTLEN    V_DROPERRORPKTLEN(1U)
28383 
28384 #define S_DROPERRORTCPHDRLEN    7
28385 #define V_DROPERRORTCPHDRLEN(x) ((x) << S_DROPERRORTCPHDRLEN)
28386 #define F_DROPERRORTCPHDRLEN    V_DROPERRORTCPHDRLEN(1U)
28387 
28388 #define S_DROPERRORIPHDRLEN    6
28389 #define V_DROPERRORIPHDRLEN(x) ((x) << S_DROPERRORIPHDRLEN)
28390 #define F_DROPERRORIPHDRLEN    V_DROPERRORIPHDRLEN(1U)
28391 
28392 #define S_DROPERRORETHHDRLEN    5
28393 #define V_DROPERRORETHHDRLEN(x) ((x) << S_DROPERRORETHHDRLEN)
28394 #define F_DROPERRORETHHDRLEN    V_DROPERRORETHHDRLEN(1U)
28395 
28396 #define S_DROPERRORATTACK    4
28397 #define V_DROPERRORATTACK(x) ((x) << S_DROPERRORATTACK)
28398 #define F_DROPERRORATTACK    V_DROPERRORATTACK(1U)
28399 
28400 #define S_DROPERRORFRAG    3
28401 #define V_DROPERRORFRAG(x) ((x) << S_DROPERRORFRAG)
28402 #define F_DROPERRORFRAG    V_DROPERRORFRAG(1U)
28403 
28404 #define S_DROPERRORIPVER    2
28405 #define V_DROPERRORIPVER(x) ((x) << S_DROPERRORIPVER)
28406 #define F_DROPERRORIPVER    V_DROPERRORIPVER(1U)
28407 
28408 #define S_DROPERRORMAC    1
28409 #define V_DROPERRORMAC(x) ((x) << S_DROPERRORMAC)
28410 #define F_DROPERRORMAC    V_DROPERRORMAC(1U)
28411 
28412 #define S_DROPERRORANY    0
28413 #define V_DROPERRORANY(x) ((x) << S_DROPERRORANY)
28414 #define F_DROPERRORANY    V_DROPERRORANY(1U)
28415 
28416 #define S_TNLERRORFPMA    31
28417 #define V_TNLERRORFPMA(x) ((x) << S_TNLERRORFPMA)
28418 #define F_TNLERRORFPMA    V_TNLERRORFPMA(1U)
28419 
28420 #define S_DROPERRORFPMA    15
28421 #define V_DROPERRORFPMA(x) ((x) << S_DROPERRORFPMA)
28422 #define F_DROPERRORFPMA    V_DROPERRORFPMA(1U)
28423 
28424 #define S_TNLERROROPAQUE    27
28425 #define V_TNLERROROPAQUE(x) ((x) << S_TNLERROROPAQUE)
28426 #define F_TNLERROROPAQUE    V_TNLERROROPAQUE(1U)
28427 
28428 #define S_TNLERRORIP6OPT    26
28429 #define V_TNLERRORIP6OPT(x) ((x) << S_TNLERRORIP6OPT)
28430 #define F_TNLERRORIP6OPT    V_TNLERRORIP6OPT(1U)
28431 
28432 #define S_DROPERROROPAQUE    11
28433 #define V_DROPERROROPAQUE(x) ((x) << S_DROPERROROPAQUE)
28434 #define F_DROPERROROPAQUE    V_DROPERROROPAQUE(1U)
28435 
28436 #define S_DROPERRORIP6OPT    10
28437 #define V_DROPERRORIP6OPT(x) ((x) << S_DROPERRORIP6OPT)
28438 #define F_DROPERRORIP6OPT    V_DROPERRORIP6OPT(1U)
28439 
28440 #define A_TP_TIMER_RESOLUTION 0x7d90
28441 
28442 #define S_TIMERRESOLUTION    16
28443 #define M_TIMERRESOLUTION    0xffU
28444 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
28445 #define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)
28446 
28447 #define S_TIMESTAMPRESOLUTION    8
28448 #define M_TIMESTAMPRESOLUTION    0xffU
28449 #define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
28450 #define G_TIMESTAMPRESOLUTION(x) (((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION)
28451 
28452 #define S_DELAYEDACKRESOLUTION    0
28453 #define M_DELAYEDACKRESOLUTION    0xffU
28454 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
28455 #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION)
28456 
28457 #define S_ROCETIMERRESOLUTION    24
28458 #define M_ROCETIMERRESOLUTION    0xffU
28459 #define V_ROCETIMERRESOLUTION(x) ((x) << S_ROCETIMERRESOLUTION)
28460 #define G_ROCETIMERRESOLUTION(x) (((x) >> S_ROCETIMERRESOLUTION) & M_ROCETIMERRESOLUTION)
28461 
28462 #define A_TP_MSL 0x7d94
28463 
28464 #define S_MSL    0
28465 #define M_MSL    0x3fffffffU
28466 #define V_MSL(x) ((x) << S_MSL)
28467 #define G_MSL(x) (((x) >> S_MSL) & M_MSL)
28468 
28469 #define A_TP_RXT_MIN 0x7d98
28470 
28471 #define S_RXTMIN    0
28472 #define M_RXTMIN    0x3fffffffU
28473 #define V_RXTMIN(x) ((x) << S_RXTMIN)
28474 #define G_RXTMIN(x) (((x) >> S_RXTMIN) & M_RXTMIN)
28475 
28476 #define A_TP_RXT_MAX 0x7d9c
28477 
28478 #define S_RXTMAX    0
28479 #define M_RXTMAX    0x3fffffffU
28480 #define V_RXTMAX(x) ((x) << S_RXTMAX)
28481 #define G_RXTMAX(x) (((x) >> S_RXTMAX) & M_RXTMAX)
28482 
28483 #define A_TP_PERS_MIN 0x7da0
28484 
28485 #define S_PERSMIN    0
28486 #define M_PERSMIN    0x3fffffffU
28487 #define V_PERSMIN(x) ((x) << S_PERSMIN)
28488 #define G_PERSMIN(x) (((x) >> S_PERSMIN) & M_PERSMIN)
28489 
28490 #define A_TP_PERS_MAX 0x7da4
28491 
28492 #define S_PERSMAX    0
28493 #define M_PERSMAX    0x3fffffffU
28494 #define V_PERSMAX(x) ((x) << S_PERSMAX)
28495 #define G_PERSMAX(x) (((x) >> S_PERSMAX) & M_PERSMAX)
28496 
28497 #define A_TP_KEEP_IDLE 0x7da8
28498 
28499 #define S_KEEPALIVEIDLE    0
28500 #define M_KEEPALIVEIDLE    0x3fffffffU
28501 #define V_KEEPALIVEIDLE(x) ((x) << S_KEEPALIVEIDLE)
28502 #define G_KEEPALIVEIDLE(x) (((x) >> S_KEEPALIVEIDLE) & M_KEEPALIVEIDLE)
28503 
28504 #define A_TP_KEEP_INTVL 0x7dac
28505 
28506 #define S_KEEPALIVEINTVL    0
28507 #define M_KEEPALIVEINTVL    0x3fffffffU
28508 #define V_KEEPALIVEINTVL(x) ((x) << S_KEEPALIVEINTVL)
28509 #define G_KEEPALIVEINTVL(x) (((x) >> S_KEEPALIVEINTVL) & M_KEEPALIVEINTVL)
28510 
28511 #define A_TP_INIT_SRTT 0x7db0
28512 
28513 #define S_MAXRTT    16
28514 #define M_MAXRTT    0xffffU
28515 #define V_MAXRTT(x) ((x) << S_MAXRTT)
28516 #define G_MAXRTT(x) (((x) >> S_MAXRTT) & M_MAXRTT)
28517 
28518 #define S_INITSRTT    0
28519 #define M_INITSRTT    0xffffU
28520 #define V_INITSRTT(x) ((x) << S_INITSRTT)
28521 #define G_INITSRTT(x) (((x) >> S_INITSRTT) & M_INITSRTT)
28522 
28523 #define A_TP_DACK_TIMER 0x7db4
28524 
28525 #define S_DACKTIME    0
28526 #define M_DACKTIME    0xfffU
28527 #define V_DACKTIME(x) ((x) << S_DACKTIME)
28528 #define G_DACKTIME(x) (((x) >> S_DACKTIME) & M_DACKTIME)
28529 
28530 #define A_TP_FINWAIT2_TIMER 0x7db8
28531 
28532 #define S_FINWAIT2TIME    0
28533 #define M_FINWAIT2TIME    0x3fffffffU
28534 #define V_FINWAIT2TIME(x) ((x) << S_FINWAIT2TIME)
28535 #define G_FINWAIT2TIME(x) (((x) >> S_FINWAIT2TIME) & M_FINWAIT2TIME)
28536 
28537 #define A_TP_FAST_FINWAIT2_TIMER 0x7dbc
28538 
28539 #define S_FASTFINWAIT2TIME    0
28540 #define M_FASTFINWAIT2TIME    0x3fffffffU
28541 #define V_FASTFINWAIT2TIME(x) ((x) << S_FASTFINWAIT2TIME)
28542 #define G_FASTFINWAIT2TIME(x) (((x) >> S_FASTFINWAIT2TIME) & M_FASTFINWAIT2TIME)
28543 
28544 #define A_TP_SHIFT_CNT 0x7dc0
28545 
28546 #define S_SYNSHIFTMAX    24
28547 #define M_SYNSHIFTMAX    0xffU
28548 #define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
28549 #define G_SYNSHIFTMAX(x) (((x) >> S_SYNSHIFTMAX) & M_SYNSHIFTMAX)
28550 
28551 #define S_RXTSHIFTMAXR1    20
28552 #define M_RXTSHIFTMAXR1    0xfU
28553 #define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
28554 #define G_RXTSHIFTMAXR1(x) (((x) >> S_RXTSHIFTMAXR1) & M_RXTSHIFTMAXR1)
28555 
28556 #define S_RXTSHIFTMAXR2    16
28557 #define M_RXTSHIFTMAXR2    0xfU
28558 #define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
28559 #define G_RXTSHIFTMAXR2(x) (((x) >> S_RXTSHIFTMAXR2) & M_RXTSHIFTMAXR2)
28560 
28561 #define S_PERSHIFTBACKOFFMAX    12
28562 #define M_PERSHIFTBACKOFFMAX    0xfU
28563 #define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
28564 #define G_PERSHIFTBACKOFFMAX(x) (((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX)
28565 
28566 #define S_PERSHIFTMAX    8
28567 #define M_PERSHIFTMAX    0xfU
28568 #define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
28569 #define G_PERSHIFTMAX(x) (((x) >> S_PERSHIFTMAX) & M_PERSHIFTMAX)
28570 
28571 #define S_KEEPALIVEMAXR1    4
28572 #define M_KEEPALIVEMAXR1    0xfU
28573 #define V_KEEPALIVEMAXR1(x) ((x) << S_KEEPALIVEMAXR1)
28574 #define G_KEEPALIVEMAXR1(x) (((x) >> S_KEEPALIVEMAXR1) & M_KEEPALIVEMAXR1)
28575 
28576 #define S_KEEPALIVEMAXR2    0
28577 #define M_KEEPALIVEMAXR2    0xfU
28578 #define V_KEEPALIVEMAXR2(x) ((x) << S_KEEPALIVEMAXR2)
28579 #define G_KEEPALIVEMAXR2(x) (((x) >> S_KEEPALIVEMAXR2) & M_KEEPALIVEMAXR2)
28580 
28581 #define S_T6_SYNSHIFTMAX    24
28582 #define M_T6_SYNSHIFTMAX    0xfU
28583 #define V_T6_SYNSHIFTMAX(x) ((x) << S_T6_SYNSHIFTMAX)
28584 #define G_T6_SYNSHIFTMAX(x) (((x) >> S_T6_SYNSHIFTMAX) & M_T6_SYNSHIFTMAX)
28585 
28586 #define A_TP_TM_CONFIG 0x7dc4
28587 
28588 #define S_CMTIMERMAXNUM    0
28589 #define M_CMTIMERMAXNUM    0x7U
28590 #define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM)
28591 #define G_CMTIMERMAXNUM(x) (((x) >> S_CMTIMERMAXNUM) & M_CMTIMERMAXNUM)
28592 
28593 #define A_TP_TIME_LO 0x7dc8
28594 #define A_TP_TIME_HI 0x7dcc
28595 #define A_TP_PORT_MTU_0 0x7dd0
28596 
28597 #define S_PORT1MTUVALUE    16
28598 #define M_PORT1MTUVALUE    0xffffU
28599 #define V_PORT1MTUVALUE(x) ((x) << S_PORT1MTUVALUE)
28600 #define G_PORT1MTUVALUE(x) (((x) >> S_PORT1MTUVALUE) & M_PORT1MTUVALUE)
28601 
28602 #define S_PORT0MTUVALUE    0
28603 #define M_PORT0MTUVALUE    0xffffU
28604 #define V_PORT0MTUVALUE(x) ((x) << S_PORT0MTUVALUE)
28605 #define G_PORT0MTUVALUE(x) (((x) >> S_PORT0MTUVALUE) & M_PORT0MTUVALUE)
28606 
28607 #define A_TP_PORT_MTU_1 0x7dd4
28608 
28609 #define S_PORT3MTUVALUE    16
28610 #define M_PORT3MTUVALUE    0xffffU
28611 #define V_PORT3MTUVALUE(x) ((x) << S_PORT3MTUVALUE)
28612 #define G_PORT3MTUVALUE(x) (((x) >> S_PORT3MTUVALUE) & M_PORT3MTUVALUE)
28613 
28614 #define S_PORT2MTUVALUE    0
28615 #define M_PORT2MTUVALUE    0xffffU
28616 #define V_PORT2MTUVALUE(x) ((x) << S_PORT2MTUVALUE)
28617 #define G_PORT2MTUVALUE(x) (((x) >> S_PORT2MTUVALUE) & M_PORT2MTUVALUE)
28618 
28619 #define A_TP_PACE_TABLE 0x7dd8
28620 #define A_TP_CCTRL_TABLE 0x7ddc
28621 
28622 #define S_ROWINDEX    16
28623 #define M_ROWINDEX    0xffffU
28624 #define V_ROWINDEX(x) ((x) << S_ROWINDEX)
28625 #define G_ROWINDEX(x) (((x) >> S_ROWINDEX) & M_ROWINDEX)
28626 
28627 #define S_ROWVALUE    0
28628 #define M_ROWVALUE    0xffffU
28629 #define V_ROWVALUE(x) ((x) << S_ROWVALUE)
28630 #define G_ROWVALUE(x) (((x) >> S_ROWVALUE) & M_ROWVALUE)
28631 
28632 #define A_TP_MTU_TABLE 0x7de4
28633 
28634 #define S_MTUINDEX    24
28635 #define M_MTUINDEX    0xffU
28636 #define V_MTUINDEX(x) ((x) << S_MTUINDEX)
28637 #define G_MTUINDEX(x) (((x) >> S_MTUINDEX) & M_MTUINDEX)
28638 
28639 #define S_MTUWIDTH    16
28640 #define M_MTUWIDTH    0xfU
28641 #define V_MTUWIDTH(x) ((x) << S_MTUWIDTH)
28642 #define G_MTUWIDTH(x) (((x) >> S_MTUWIDTH) & M_MTUWIDTH)
28643 
28644 #define S_MTUVALUE    0
28645 #define M_MTUVALUE    0x3fffU
28646 #define V_MTUVALUE(x) ((x) << S_MTUVALUE)
28647 #define G_MTUVALUE(x) (((x) >> S_MTUVALUE) & M_MTUVALUE)
28648 
28649 #define A_TP_ULP_TABLE 0x7de8
28650 
28651 #define S_ULPTYPE7FIELD    28
28652 #define M_ULPTYPE7FIELD    0xfU
28653 #define V_ULPTYPE7FIELD(x) ((x) << S_ULPTYPE7FIELD)
28654 #define G_ULPTYPE7FIELD(x) (((x) >> S_ULPTYPE7FIELD) & M_ULPTYPE7FIELD)
28655 
28656 #define S_ULPTYPE6FIELD    24
28657 #define M_ULPTYPE6FIELD    0xfU
28658 #define V_ULPTYPE6FIELD(x) ((x) << S_ULPTYPE6FIELD)
28659 #define G_ULPTYPE6FIELD(x) (((x) >> S_ULPTYPE6FIELD) & M_ULPTYPE6FIELD)
28660 
28661 #define S_ULPTYPE5FIELD    20
28662 #define M_ULPTYPE5FIELD    0xfU
28663 #define V_ULPTYPE5FIELD(x) ((x) << S_ULPTYPE5FIELD)
28664 #define G_ULPTYPE5FIELD(x) (((x) >> S_ULPTYPE5FIELD) & M_ULPTYPE5FIELD)
28665 
28666 #define S_ULPTYPE4FIELD    16
28667 #define M_ULPTYPE4FIELD    0xfU
28668 #define V_ULPTYPE4FIELD(x) ((x) << S_ULPTYPE4FIELD)
28669 #define G_ULPTYPE4FIELD(x) (((x) >> S_ULPTYPE4FIELD) & M_ULPTYPE4FIELD)
28670 
28671 #define S_ULPTYPE3FIELD    12
28672 #define M_ULPTYPE3FIELD    0xfU
28673 #define V_ULPTYPE3FIELD(x) ((x) << S_ULPTYPE3FIELD)
28674 #define G_ULPTYPE3FIELD(x) (((x) >> S_ULPTYPE3FIELD) & M_ULPTYPE3FIELD)
28675 
28676 #define S_ULPTYPE2FIELD    8
28677 #define M_ULPTYPE2FIELD    0xfU
28678 #define V_ULPTYPE2FIELD(x) ((x) << S_ULPTYPE2FIELD)
28679 #define G_ULPTYPE2FIELD(x) (((x) >> S_ULPTYPE2FIELD) & M_ULPTYPE2FIELD)
28680 
28681 #define S_ULPTYPE1FIELD    4
28682 #define M_ULPTYPE1FIELD    0xfU
28683 #define V_ULPTYPE1FIELD(x) ((x) << S_ULPTYPE1FIELD)
28684 #define G_ULPTYPE1FIELD(x) (((x) >> S_ULPTYPE1FIELD) & M_ULPTYPE1FIELD)
28685 
28686 #define S_ULPTYPE0FIELD    0
28687 #define M_ULPTYPE0FIELD    0xfU
28688 #define V_ULPTYPE0FIELD(x) ((x) << S_ULPTYPE0FIELD)
28689 #define G_ULPTYPE0FIELD(x) (((x) >> S_ULPTYPE0FIELD) & M_ULPTYPE0FIELD)
28690 
28691 #define S_ULPTYPE7LENGTH    31
28692 #define V_ULPTYPE7LENGTH(x) ((x) << S_ULPTYPE7LENGTH)
28693 #define F_ULPTYPE7LENGTH    V_ULPTYPE7LENGTH(1U)
28694 
28695 #define S_ULPTYPE7OFFSET    28
28696 #define M_ULPTYPE7OFFSET    0x7U
28697 #define V_ULPTYPE7OFFSET(x) ((x) << S_ULPTYPE7OFFSET)
28698 #define G_ULPTYPE7OFFSET(x) (((x) >> S_ULPTYPE7OFFSET) & M_ULPTYPE7OFFSET)
28699 
28700 #define S_ULPTYPE6LENGTH    27
28701 #define V_ULPTYPE6LENGTH(x) ((x) << S_ULPTYPE6LENGTH)
28702 #define F_ULPTYPE6LENGTH    V_ULPTYPE6LENGTH(1U)
28703 
28704 #define S_ULPTYPE6OFFSET    24
28705 #define M_ULPTYPE6OFFSET    0x7U
28706 #define V_ULPTYPE6OFFSET(x) ((x) << S_ULPTYPE6OFFSET)
28707 #define G_ULPTYPE6OFFSET(x) (((x) >> S_ULPTYPE6OFFSET) & M_ULPTYPE6OFFSET)
28708 
28709 #define S_ULPTYPE5LENGTH    23
28710 #define V_ULPTYPE5LENGTH(x) ((x) << S_ULPTYPE5LENGTH)
28711 #define F_ULPTYPE5LENGTH    V_ULPTYPE5LENGTH(1U)
28712 
28713 #define S_ULPTYPE5OFFSET    20
28714 #define M_ULPTYPE5OFFSET    0x7U
28715 #define V_ULPTYPE5OFFSET(x) ((x) << S_ULPTYPE5OFFSET)
28716 #define G_ULPTYPE5OFFSET(x) (((x) >> S_ULPTYPE5OFFSET) & M_ULPTYPE5OFFSET)
28717 
28718 #define S_ULPTYPE4LENGTH    19
28719 #define V_ULPTYPE4LENGTH(x) ((x) << S_ULPTYPE4LENGTH)
28720 #define F_ULPTYPE4LENGTH    V_ULPTYPE4LENGTH(1U)
28721 
28722 #define S_ULPTYPE4OFFSET    16
28723 #define M_ULPTYPE4OFFSET    0x7U
28724 #define V_ULPTYPE4OFFSET(x) ((x) << S_ULPTYPE4OFFSET)
28725 #define G_ULPTYPE4OFFSET(x) (((x) >> S_ULPTYPE4OFFSET) & M_ULPTYPE4OFFSET)
28726 
28727 #define S_ULPTYPE3LENGTH    15
28728 #define V_ULPTYPE3LENGTH(x) ((x) << S_ULPTYPE3LENGTH)
28729 #define F_ULPTYPE3LENGTH    V_ULPTYPE3LENGTH(1U)
28730 
28731 #define S_ULPTYPE3OFFSET    12
28732 #define M_ULPTYPE3OFFSET    0x7U
28733 #define V_ULPTYPE3OFFSET(x) ((x) << S_ULPTYPE3OFFSET)
28734 #define G_ULPTYPE3OFFSET(x) (((x) >> S_ULPTYPE3OFFSET) & M_ULPTYPE3OFFSET)
28735 
28736 #define S_ULPTYPE2LENGTH    11
28737 #define V_ULPTYPE2LENGTH(x) ((x) << S_ULPTYPE2LENGTH)
28738 #define F_ULPTYPE2LENGTH    V_ULPTYPE2LENGTH(1U)
28739 
28740 #define S_ULPTYPE2OFFSET    8
28741 #define M_ULPTYPE2OFFSET    0x7U
28742 #define V_ULPTYPE2OFFSET(x) ((x) << S_ULPTYPE2OFFSET)
28743 #define G_ULPTYPE2OFFSET(x) (((x) >> S_ULPTYPE2OFFSET) & M_ULPTYPE2OFFSET)
28744 
28745 #define S_ULPTYPE1LENGTH    7
28746 #define V_ULPTYPE1LENGTH(x) ((x) << S_ULPTYPE1LENGTH)
28747 #define F_ULPTYPE1LENGTH    V_ULPTYPE1LENGTH(1U)
28748 
28749 #define S_ULPTYPE1OFFSET    4
28750 #define M_ULPTYPE1OFFSET    0x7U
28751 #define V_ULPTYPE1OFFSET(x) ((x) << S_ULPTYPE1OFFSET)
28752 #define G_ULPTYPE1OFFSET(x) (((x) >> S_ULPTYPE1OFFSET) & M_ULPTYPE1OFFSET)
28753 
28754 #define S_ULPTYPE0LENGTH    3
28755 #define V_ULPTYPE0LENGTH(x) ((x) << S_ULPTYPE0LENGTH)
28756 #define F_ULPTYPE0LENGTH    V_ULPTYPE0LENGTH(1U)
28757 
28758 #define S_ULPTYPE0OFFSET    0
28759 #define M_ULPTYPE0OFFSET    0x7U
28760 #define V_ULPTYPE0OFFSET(x) ((x) << S_ULPTYPE0OFFSET)
28761 #define G_ULPTYPE0OFFSET(x) (((x) >> S_ULPTYPE0OFFSET) & M_ULPTYPE0OFFSET)
28762 
28763 #define A_TP_RSS_LKP_TABLE 0x7dec
28764 
28765 #define S_LKPTBLROWVLD    31
28766 #define V_LKPTBLROWVLD(x) ((x) << S_LKPTBLROWVLD)
28767 #define F_LKPTBLROWVLD    V_LKPTBLROWVLD(1U)
28768 
28769 #define S_LKPTBLROWIDX    20
28770 #define M_LKPTBLROWIDX    0x3ffU
28771 #define V_LKPTBLROWIDX(x) ((x) << S_LKPTBLROWIDX)
28772 #define G_LKPTBLROWIDX(x) (((x) >> S_LKPTBLROWIDX) & M_LKPTBLROWIDX)
28773 
28774 #define S_LKPTBLQUEUE1    10
28775 #define M_LKPTBLQUEUE1    0x3ffU
28776 #define V_LKPTBLQUEUE1(x) ((x) << S_LKPTBLQUEUE1)
28777 #define G_LKPTBLQUEUE1(x) (((x) >> S_LKPTBLQUEUE1) & M_LKPTBLQUEUE1)
28778 
28779 #define S_LKPTBLQUEUE0    0
28780 #define M_LKPTBLQUEUE0    0x3ffU
28781 #define V_LKPTBLQUEUE0(x) ((x) << S_LKPTBLQUEUE0)
28782 #define G_LKPTBLQUEUE0(x) (((x) >> S_LKPTBLQUEUE0) & M_LKPTBLQUEUE0)
28783 
28784 #define S_T6_LKPTBLROWIDX    20
28785 #define M_T6_LKPTBLROWIDX    0x7ffU
28786 #define V_T6_LKPTBLROWIDX(x) ((x) << S_T6_LKPTBLROWIDX)
28787 #define G_T6_LKPTBLROWIDX(x) (((x) >> S_T6_LKPTBLROWIDX) & M_T6_LKPTBLROWIDX)
28788 
28789 #define A_TP_RSS_CONFIG 0x7df0
28790 
28791 #define S_TNL4TUPENIPV6    31
28792 #define V_TNL4TUPENIPV6(x) ((x) << S_TNL4TUPENIPV6)
28793 #define F_TNL4TUPENIPV6    V_TNL4TUPENIPV6(1U)
28794 
28795 #define S_TNL2TUPENIPV6    30
28796 #define V_TNL2TUPENIPV6(x) ((x) << S_TNL2TUPENIPV6)
28797 #define F_TNL2TUPENIPV6    V_TNL2TUPENIPV6(1U)
28798 
28799 #define S_TNL4TUPENIPV4    29
28800 #define V_TNL4TUPENIPV4(x) ((x) << S_TNL4TUPENIPV4)
28801 #define F_TNL4TUPENIPV4    V_TNL4TUPENIPV4(1U)
28802 
28803 #define S_TNL2TUPENIPV4    28
28804 #define V_TNL2TUPENIPV4(x) ((x) << S_TNL2TUPENIPV4)
28805 #define F_TNL2TUPENIPV4    V_TNL2TUPENIPV4(1U)
28806 
28807 #define S_TNLTCPSEL    27
28808 #define V_TNLTCPSEL(x) ((x) << S_TNLTCPSEL)
28809 #define F_TNLTCPSEL    V_TNLTCPSEL(1U)
28810 
28811 #define S_TNLIP6SEL    26
28812 #define V_TNLIP6SEL(x) ((x) << S_TNLIP6SEL)
28813 #define F_TNLIP6SEL    V_TNLIP6SEL(1U)
28814 
28815 #define S_TNLVRTSEL    25
28816 #define V_TNLVRTSEL(x) ((x) << S_TNLVRTSEL)
28817 #define F_TNLVRTSEL    V_TNLVRTSEL(1U)
28818 
28819 #define S_TNLMAPEN    24
28820 #define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
28821 #define F_TNLMAPEN    V_TNLMAPEN(1U)
28822 
28823 #define S_OFDHASHSAVE    19
28824 #define V_OFDHASHSAVE(x) ((x) << S_OFDHASHSAVE)
28825 #define F_OFDHASHSAVE    V_OFDHASHSAVE(1U)
28826 
28827 #define S_OFDVRTSEL    18
28828 #define V_OFDVRTSEL(x) ((x) << S_OFDVRTSEL)
28829 #define F_OFDVRTSEL    V_OFDVRTSEL(1U)
28830 
28831 #define S_OFDMAPEN    17
28832 #define V_OFDMAPEN(x) ((x) << S_OFDMAPEN)
28833 #define F_OFDMAPEN    V_OFDMAPEN(1U)
28834 
28835 #define S_OFDLKPEN    16
28836 #define V_OFDLKPEN(x) ((x) << S_OFDLKPEN)
28837 #define F_OFDLKPEN    V_OFDLKPEN(1U)
28838 
28839 #define S_SYN4TUPENIPV6    15
28840 #define V_SYN4TUPENIPV6(x) ((x) << S_SYN4TUPENIPV6)
28841 #define F_SYN4TUPENIPV6    V_SYN4TUPENIPV6(1U)
28842 
28843 #define S_SYN2TUPENIPV6    14
28844 #define V_SYN2TUPENIPV6(x) ((x) << S_SYN2TUPENIPV6)
28845 #define F_SYN2TUPENIPV6    V_SYN2TUPENIPV6(1U)
28846 
28847 #define S_SYN4TUPENIPV4    13
28848 #define V_SYN4TUPENIPV4(x) ((x) << S_SYN4TUPENIPV4)
28849 #define F_SYN4TUPENIPV4    V_SYN4TUPENIPV4(1U)
28850 
28851 #define S_SYN2TUPENIPV4    12
28852 #define V_SYN2TUPENIPV4(x) ((x) << S_SYN2TUPENIPV4)
28853 #define F_SYN2TUPENIPV4    V_SYN2TUPENIPV4(1U)
28854 
28855 #define S_SYNIP6SEL    11
28856 #define V_SYNIP6SEL(x) ((x) << S_SYNIP6SEL)
28857 #define F_SYNIP6SEL    V_SYNIP6SEL(1U)
28858 
28859 #define S_SYNVRTSEL    10
28860 #define V_SYNVRTSEL(x) ((x) << S_SYNVRTSEL)
28861 #define F_SYNVRTSEL    V_SYNVRTSEL(1U)
28862 
28863 #define S_SYNMAPEN    9
28864 #define V_SYNMAPEN(x) ((x) << S_SYNMAPEN)
28865 #define F_SYNMAPEN    V_SYNMAPEN(1U)
28866 
28867 #define S_SYNLKPEN    8
28868 #define V_SYNLKPEN(x) ((x) << S_SYNLKPEN)
28869 #define F_SYNLKPEN    V_SYNLKPEN(1U)
28870 
28871 #define S_CHANNELENABLE    7
28872 #define V_CHANNELENABLE(x) ((x) << S_CHANNELENABLE)
28873 #define F_CHANNELENABLE    V_CHANNELENABLE(1U)
28874 
28875 #define S_PORTENABLE    6
28876 #define V_PORTENABLE(x) ((x) << S_PORTENABLE)
28877 #define F_PORTENABLE    V_PORTENABLE(1U)
28878 
28879 #define S_TNLALLLOOKUP    5
28880 #define V_TNLALLLOOKUP(x) ((x) << S_TNLALLLOOKUP)
28881 #define F_TNLALLLOOKUP    V_TNLALLLOOKUP(1U)
28882 
28883 #define S_VIRTENABLE    4
28884 #define V_VIRTENABLE(x) ((x) << S_VIRTENABLE)
28885 #define F_VIRTENABLE    V_VIRTENABLE(1U)
28886 
28887 #define S_CONGESTIONENABLE    3
28888 #define V_CONGESTIONENABLE(x) ((x) << S_CONGESTIONENABLE)
28889 #define F_CONGESTIONENABLE    V_CONGESTIONENABLE(1U)
28890 
28891 #define S_HASHTOEPLITZ    2
28892 #define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ)
28893 #define F_HASHTOEPLITZ    V_HASHTOEPLITZ(1U)
28894 
28895 #define S_UDPENABLE    1
28896 #define V_UDPENABLE(x) ((x) << S_UDPENABLE)
28897 #define F_UDPENABLE    V_UDPENABLE(1U)
28898 
28899 #define S_DISABLE    0
28900 #define V_DISABLE(x) ((x) << S_DISABLE)
28901 #define F_DISABLE    V_DISABLE(1U)
28902 
28903 #define S_TNLFCOEMODE    23
28904 #define V_TNLFCOEMODE(x) ((x) << S_TNLFCOEMODE)
28905 #define F_TNLFCOEMODE    V_TNLFCOEMODE(1U)
28906 
28907 #define S_TNLFCOEEN    21
28908 #define V_TNLFCOEEN(x) ((x) << S_TNLFCOEEN)
28909 #define F_TNLFCOEEN    V_TNLFCOEEN(1U)
28910 
28911 #define S_HASHXOR    20
28912 #define V_HASHXOR(x) ((x) << S_HASHXOR)
28913 #define F_HASHXOR    V_HASHXOR(1U)
28914 
28915 #define S_TNLFCOESID    22
28916 #define V_TNLFCOESID(x) ((x) << S_TNLFCOESID)
28917 #define F_TNLFCOESID    V_TNLFCOESID(1U)
28918 
28919 #define A_TP_RSS_CONFIG_TNL 0x7df4
28920 
28921 #define S_MASKSIZE    28
28922 #define M_MASKSIZE    0xfU
28923 #define V_MASKSIZE(x) ((x) << S_MASKSIZE)
28924 #define G_MASKSIZE(x) (((x) >> S_MASKSIZE) & M_MASKSIZE)
28925 
28926 #define S_MASKFILTER    16
28927 #define M_MASKFILTER    0x7ffU
28928 #define V_MASKFILTER(x) ((x) << S_MASKFILTER)
28929 #define G_MASKFILTER(x) (((x) >> S_MASKFILTER) & M_MASKFILTER)
28930 
28931 #define S_USEWIRECH    0
28932 #define V_USEWIRECH(x) ((x) << S_USEWIRECH)
28933 #define F_USEWIRECH    V_USEWIRECH(1U)
28934 
28935 #define S_HASHALL    2
28936 #define V_HASHALL(x) ((x) << S_HASHALL)
28937 #define F_HASHALL    V_HASHALL(1U)
28938 
28939 #define S_HASHETH    1
28940 #define V_HASHETH(x) ((x) << S_HASHETH)
28941 #define F_HASHETH    V_HASHETH(1U)
28942 
28943 #define A_TP_RSS_CONFIG_OFD 0x7df8
28944 
28945 #define S_RRCPLMAPEN    20
28946 #define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN)
28947 #define F_RRCPLMAPEN    V_RRCPLMAPEN(1U)
28948 
28949 #define S_RRCPLQUEWIDTH    16
28950 #define M_RRCPLQUEWIDTH    0xfU
28951 #define V_RRCPLQUEWIDTH(x) ((x) << S_RRCPLQUEWIDTH)
28952 #define G_RRCPLQUEWIDTH(x) (((x) >> S_RRCPLQUEWIDTH) & M_RRCPLQUEWIDTH)
28953 
28954 #define S_FRMWRQUEMASK    12
28955 #define M_FRMWRQUEMASK    0xfU
28956 #define V_FRMWRQUEMASK(x) ((x) << S_FRMWRQUEMASK)
28957 #define G_FRMWRQUEMASK(x) (((x) >> S_FRMWRQUEMASK) & M_FRMWRQUEMASK)
28958 
28959 #define S_RRCPLOPT1SMSELEN    11
28960 #define V_RRCPLOPT1SMSELEN(x) ((x) << S_RRCPLOPT1SMSELEN)
28961 #define F_RRCPLOPT1SMSELEN    V_RRCPLOPT1SMSELEN(1U)
28962 
28963 #define S_RRCPLOPT1BQEN    10
28964 #define V_RRCPLOPT1BQEN(x) ((x) << S_RRCPLOPT1BQEN)
28965 #define F_RRCPLOPT1BQEN    V_RRCPLOPT1BQEN(1U)
28966 
28967 #define A_TP_RSS_CONFIG_SYN 0x7dfc
28968 #define A_TP_RSS_CONFIG_VRT 0x7e00
28969 
28970 #define S_VFRDRG    25
28971 #define V_VFRDRG(x) ((x) << S_VFRDRG)
28972 #define F_VFRDRG    V_VFRDRG(1U)
28973 
28974 #define S_VFRDEN    24
28975 #define V_VFRDEN(x) ((x) << S_VFRDEN)
28976 #define F_VFRDEN    V_VFRDEN(1U)
28977 
28978 #define S_VFPERREN    23
28979 #define V_VFPERREN(x) ((x) << S_VFPERREN)
28980 #define F_VFPERREN    V_VFPERREN(1U)
28981 
28982 #define S_KEYPERREN    22
28983 #define V_KEYPERREN(x) ((x) << S_KEYPERREN)
28984 #define F_KEYPERREN    V_KEYPERREN(1U)
28985 
28986 #define S_DISABLEVLAN    21
28987 #define V_DISABLEVLAN(x) ((x) << S_DISABLEVLAN)
28988 #define F_DISABLEVLAN    V_DISABLEVLAN(1U)
28989 
28990 #define S_ENABLEUP0    20
28991 #define V_ENABLEUP0(x) ((x) << S_ENABLEUP0)
28992 #define F_ENABLEUP0    V_ENABLEUP0(1U)
28993 
28994 #define S_HASHDELAY    16
28995 #define M_HASHDELAY    0xfU
28996 #define V_HASHDELAY(x) ((x) << S_HASHDELAY)
28997 #define G_HASHDELAY(x) (((x) >> S_HASHDELAY) & M_HASHDELAY)
28998 
28999 #define S_VFWRADDR    8
29000 #define M_VFWRADDR    0x7fU
29001 #define V_VFWRADDR(x) ((x) << S_VFWRADDR)
29002 #define G_VFWRADDR(x) (((x) >> S_VFWRADDR) & M_VFWRADDR)
29003 
29004 #define S_KEYMODE    6
29005 #define M_KEYMODE    0x3U
29006 #define V_KEYMODE(x) ((x) << S_KEYMODE)
29007 #define G_KEYMODE(x) (((x) >> S_KEYMODE) & M_KEYMODE)
29008 
29009 #define S_VFWREN    5
29010 #define V_VFWREN(x) ((x) << S_VFWREN)
29011 #define F_VFWREN    V_VFWREN(1U)
29012 
29013 #define S_KEYWREN    4
29014 #define V_KEYWREN(x) ((x) << S_KEYWREN)
29015 #define F_KEYWREN    V_KEYWREN(1U)
29016 
29017 #define S_KEYWRADDR    0
29018 #define M_KEYWRADDR    0xfU
29019 #define V_KEYWRADDR(x) ((x) << S_KEYWRADDR)
29020 #define G_KEYWRADDR(x) (((x) >> S_KEYWRADDR) & M_KEYWRADDR)
29021 
29022 #define S_VFVLANEN    21
29023 #define V_VFVLANEN(x) ((x) << S_VFVLANEN)
29024 #define F_VFVLANEN    V_VFVLANEN(1U)
29025 
29026 #define S_VFFWEN    20
29027 #define V_VFFWEN(x) ((x) << S_VFFWEN)
29028 #define F_VFFWEN    V_VFFWEN(1U)
29029 
29030 #define S_KEYWRADDRX    30
29031 #define M_KEYWRADDRX    0x3U
29032 #define V_KEYWRADDRX(x) ((x) << S_KEYWRADDRX)
29033 #define G_KEYWRADDRX(x) (((x) >> S_KEYWRADDRX) & M_KEYWRADDRX)
29034 
29035 #define S_KEYEXTEND    26
29036 #define V_KEYEXTEND(x) ((x) << S_KEYEXTEND)
29037 #define F_KEYEXTEND    V_KEYEXTEND(1U)
29038 
29039 #define S_T6_VFWRADDR    8
29040 #define M_T6_VFWRADDR    0xffU
29041 #define V_T6_VFWRADDR(x) ((x) << S_T6_VFWRADDR)
29042 #define G_T6_VFWRADDR(x) (((x) >> S_T6_VFWRADDR) & M_T6_VFWRADDR)
29043 
29044 #define A_TP_RSS_CONFIG_CNG 0x7e04
29045 
29046 #define S_CHNCOUNT3    31
29047 #define V_CHNCOUNT3(x) ((x) << S_CHNCOUNT3)
29048 #define F_CHNCOUNT3    V_CHNCOUNT3(1U)
29049 
29050 #define S_CHNCOUNT2    30
29051 #define V_CHNCOUNT2(x) ((x) << S_CHNCOUNT2)
29052 #define F_CHNCOUNT2    V_CHNCOUNT2(1U)
29053 
29054 #define S_CHNCOUNT1    29
29055 #define V_CHNCOUNT1(x) ((x) << S_CHNCOUNT1)
29056 #define F_CHNCOUNT1    V_CHNCOUNT1(1U)
29057 
29058 #define S_CHNCOUNT0    28
29059 #define V_CHNCOUNT0(x) ((x) << S_CHNCOUNT0)
29060 #define F_CHNCOUNT0    V_CHNCOUNT0(1U)
29061 
29062 #define S_CHNUNDFLOW3    27
29063 #define V_CHNUNDFLOW3(x) ((x) << S_CHNUNDFLOW3)
29064 #define F_CHNUNDFLOW3    V_CHNUNDFLOW3(1U)
29065 
29066 #define S_CHNUNDFLOW2    26
29067 #define V_CHNUNDFLOW2(x) ((x) << S_CHNUNDFLOW2)
29068 #define F_CHNUNDFLOW2    V_CHNUNDFLOW2(1U)
29069 
29070 #define S_CHNUNDFLOW1    25
29071 #define V_CHNUNDFLOW1(x) ((x) << S_CHNUNDFLOW1)
29072 #define F_CHNUNDFLOW1    V_CHNUNDFLOW1(1U)
29073 
29074 #define S_CHNUNDFLOW0    24
29075 #define V_CHNUNDFLOW0(x) ((x) << S_CHNUNDFLOW0)
29076 #define F_CHNUNDFLOW0    V_CHNUNDFLOW0(1U)
29077 
29078 #define S_CHNOVRFLOW3    23
29079 #define V_CHNOVRFLOW3(x) ((x) << S_CHNOVRFLOW3)
29080 #define F_CHNOVRFLOW3    V_CHNOVRFLOW3(1U)
29081 
29082 #define S_CHNOVRFLOW2    22
29083 #define V_CHNOVRFLOW2(x) ((x) << S_CHNOVRFLOW2)
29084 #define F_CHNOVRFLOW2    V_CHNOVRFLOW2(1U)
29085 
29086 #define S_CHNOVRFLOW1    21
29087 #define V_CHNOVRFLOW1(x) ((x) << S_CHNOVRFLOW1)
29088 #define F_CHNOVRFLOW1    V_CHNOVRFLOW1(1U)
29089 
29090 #define S_CHNOVRFLOW0    20
29091 #define V_CHNOVRFLOW0(x) ((x) << S_CHNOVRFLOW0)
29092 #define F_CHNOVRFLOW0    V_CHNOVRFLOW0(1U)
29093 
29094 #define S_RSTCHN3    19
29095 #define V_RSTCHN3(x) ((x) << S_RSTCHN3)
29096 #define F_RSTCHN3    V_RSTCHN3(1U)
29097 
29098 #define S_RSTCHN2    18
29099 #define V_RSTCHN2(x) ((x) << S_RSTCHN2)
29100 #define F_RSTCHN2    V_RSTCHN2(1U)
29101 
29102 #define S_RSTCHN1    17
29103 #define V_RSTCHN1(x) ((x) << S_RSTCHN1)
29104 #define F_RSTCHN1    V_RSTCHN1(1U)
29105 
29106 #define S_RSTCHN0    16
29107 #define V_RSTCHN0(x) ((x) << S_RSTCHN0)
29108 #define F_RSTCHN0    V_RSTCHN0(1U)
29109 
29110 #define S_UPDVLD    15
29111 #define V_UPDVLD(x) ((x) << S_UPDVLD)
29112 #define F_UPDVLD    V_UPDVLD(1U)
29113 
29114 #define S_XOFF    14
29115 #define V_XOFF(x) ((x) << S_XOFF)
29116 #define F_XOFF    V_XOFF(1U)
29117 
29118 #define S_UPDCHN3    13
29119 #define V_UPDCHN3(x) ((x) << S_UPDCHN3)
29120 #define F_UPDCHN3    V_UPDCHN3(1U)
29121 
29122 #define S_UPDCHN2    12
29123 #define V_UPDCHN2(x) ((x) << S_UPDCHN2)
29124 #define F_UPDCHN2    V_UPDCHN2(1U)
29125 
29126 #define S_UPDCHN1    11
29127 #define V_UPDCHN1(x) ((x) << S_UPDCHN1)
29128 #define F_UPDCHN1    V_UPDCHN1(1U)
29129 
29130 #define S_UPDCHN0    10
29131 #define V_UPDCHN0(x) ((x) << S_UPDCHN0)
29132 #define F_UPDCHN0    V_UPDCHN0(1U)
29133 
29134 #define S_QUEUE    0
29135 #define M_QUEUE    0x3ffU
29136 #define V_QUEUE(x) ((x) << S_QUEUE)
29137 #define G_QUEUE(x) (((x) >> S_QUEUE) & M_QUEUE)
29138 
29139 #define S_T7_UPDVLD    19
29140 #define V_T7_UPDVLD(x) ((x) << S_T7_UPDVLD)
29141 #define F_T7_UPDVLD    V_T7_UPDVLD(1U)
29142 
29143 #define S_T7_XOFF    18
29144 #define V_T7_XOFF(x) ((x) << S_T7_XOFF)
29145 #define F_T7_XOFF    V_T7_XOFF(1U)
29146 
29147 #define S_T7_UPDCHN3    17
29148 #define V_T7_UPDCHN3(x) ((x) << S_T7_UPDCHN3)
29149 #define F_T7_UPDCHN3    V_T7_UPDCHN3(1U)
29150 
29151 #define S_T7_UPDCHN2    16
29152 #define V_T7_UPDCHN2(x) ((x) << S_T7_UPDCHN2)
29153 #define F_T7_UPDCHN2    V_T7_UPDCHN2(1U)
29154 
29155 #define S_T7_UPDCHN1    15
29156 #define V_T7_UPDCHN1(x) ((x) << S_T7_UPDCHN1)
29157 #define F_T7_UPDCHN1    V_T7_UPDCHN1(1U)
29158 
29159 #define S_T7_UPDCHN0    14
29160 #define V_T7_UPDCHN0(x) ((x) << S_T7_UPDCHN0)
29161 #define F_T7_UPDCHN0    V_T7_UPDCHN0(1U)
29162 
29163 #define S_T7_QUEUE    0
29164 #define M_T7_QUEUE    0x3fffU
29165 #define V_T7_QUEUE(x) ((x) << S_T7_QUEUE)
29166 #define G_T7_QUEUE(x) (((x) >> S_T7_QUEUE) & M_T7_QUEUE)
29167 
29168 #define A_TP_RSS_CONFIG_4CH 0x7e08
29169 
29170 #define S_BASEQIDEN    1
29171 #define V_BASEQIDEN(x) ((x) << S_BASEQIDEN)
29172 #define F_BASEQIDEN    V_BASEQIDEN(1U)
29173 
29174 #define S_200GMODE    0
29175 #define V_200GMODE(x) ((x) << S_200GMODE)
29176 #define F_200GMODE    V_200GMODE(1U)
29177 
29178 #define A_TP_RSS_CONFIG_SRAM 0x7e0c
29179 
29180 #define S_SRAMRDDIS    20
29181 #define V_SRAMRDDIS(x) ((x) << S_SRAMRDDIS)
29182 #define F_SRAMRDDIS    V_SRAMRDDIS(1U)
29183 
29184 #define S_SRAMSTART    19
29185 #define V_SRAMSTART(x) ((x) << S_SRAMSTART)
29186 #define F_SRAMSTART    V_SRAMSTART(1U)
29187 
29188 #define S_SRAMWRITE    18
29189 #define V_SRAMWRITE(x) ((x) << S_SRAMWRITE)
29190 #define F_SRAMWRITE    V_SRAMWRITE(1U)
29191 
29192 #define S_SRAMSEL    16
29193 #define M_SRAMSEL    0x3U
29194 #define V_SRAMSEL(x) ((x) << S_SRAMSEL)
29195 #define G_SRAMSEL(x) (((x) >> S_SRAMSEL) & M_SRAMSEL)
29196 
29197 #define S_SRAMADDR    0
29198 #define M_SRAMADDR    0x3fffU
29199 #define V_SRAMADDR(x) ((x) << S_SRAMADDR)
29200 #define G_SRAMADDR(x) (((x) >> S_SRAMADDR) & M_SRAMADDR)
29201 
29202 #define A_TP_LA_TABLE_0 0x7e10
29203 
29204 #define S_VIRTPORT1TABLE    16
29205 #define M_VIRTPORT1TABLE    0xffffU
29206 #define V_VIRTPORT1TABLE(x) ((x) << S_VIRTPORT1TABLE)
29207 #define G_VIRTPORT1TABLE(x) (((x) >> S_VIRTPORT1TABLE) & M_VIRTPORT1TABLE)
29208 
29209 #define S_VIRTPORT0TABLE    0
29210 #define M_VIRTPORT0TABLE    0xffffU
29211 #define V_VIRTPORT0TABLE(x) ((x) << S_VIRTPORT0TABLE)
29212 #define G_VIRTPORT0TABLE(x) (((x) >> S_VIRTPORT0TABLE) & M_VIRTPORT0TABLE)
29213 
29214 #define A_TP_LA_TABLE_1 0x7e14
29215 
29216 #define S_VIRTPORT3TABLE    16
29217 #define M_VIRTPORT3TABLE    0xffffU
29218 #define V_VIRTPORT3TABLE(x) ((x) << S_VIRTPORT3TABLE)
29219 #define G_VIRTPORT3TABLE(x) (((x) >> S_VIRTPORT3TABLE) & M_VIRTPORT3TABLE)
29220 
29221 #define S_VIRTPORT2TABLE    0
29222 #define M_VIRTPORT2TABLE    0xffffU
29223 #define V_VIRTPORT2TABLE(x) ((x) << S_VIRTPORT2TABLE)
29224 #define G_VIRTPORT2TABLE(x) (((x) >> S_VIRTPORT2TABLE) & M_VIRTPORT2TABLE)
29225 
29226 #define A_TP_TM_PIO_ADDR 0x7e18
29227 #define A_TP_TM_PIO_DATA 0x7e1c
29228 #define A_TP_RX_MOD_CONFIG_CH3_CH2 0x7e20
29229 
29230 #define S_RXCHANNELWEIGHT3    8
29231 #define M_RXCHANNELWEIGHT3    0xffU
29232 #define V_RXCHANNELWEIGHT3(x) ((x) << S_RXCHANNELWEIGHT3)
29233 #define G_RXCHANNELWEIGHT3(x) (((x) >> S_RXCHANNELWEIGHT3) & M_RXCHANNELWEIGHT3)
29234 
29235 #define S_RXCHANNELWEIGHT2    0
29236 #define M_RXCHANNELWEIGHT2    0xffU
29237 #define V_RXCHANNELWEIGHT2(x) ((x) << S_RXCHANNELWEIGHT2)
29238 #define G_RXCHANNELWEIGHT2(x) (((x) >> S_RXCHANNELWEIGHT2) & M_RXCHANNELWEIGHT2)
29239 
29240 #define A_TP_MOD_CONFIG 0x7e24
29241 
29242 #define S_RXCHANNELWEIGHT1    24
29243 #define M_RXCHANNELWEIGHT1    0xffU
29244 #define V_RXCHANNELWEIGHT1(x) ((x) << S_RXCHANNELWEIGHT1)
29245 #define G_RXCHANNELWEIGHT1(x) (((x) >> S_RXCHANNELWEIGHT1) & M_RXCHANNELWEIGHT1)
29246 
29247 #define S_RXCHANNELWEIGHT0    16
29248 #define M_RXCHANNELWEIGHT0    0xffU
29249 #define V_RXCHANNELWEIGHT0(x) ((x) << S_RXCHANNELWEIGHT0)
29250 #define G_RXCHANNELWEIGHT0(x) (((x) >> S_RXCHANNELWEIGHT0) & M_RXCHANNELWEIGHT0)
29251 
29252 #define S_TIMERMODE    8
29253 #define M_TIMERMODE    0xffU
29254 #define V_TIMERMODE(x) ((x) << S_TIMERMODE)
29255 #define G_TIMERMODE(x) (((x) >> S_TIMERMODE) & M_TIMERMODE)
29256 
29257 #define S_TXCHANNELXOFFEN    0
29258 #define M_TXCHANNELXOFFEN    0xfU
29259 #define V_TXCHANNELXOFFEN(x) ((x) << S_TXCHANNELXOFFEN)
29260 #define G_TXCHANNELXOFFEN(x) (((x) >> S_TXCHANNELXOFFEN) & M_TXCHANNELXOFFEN)
29261 
29262 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28
29263 
29264 #define S_RX_MOD_WEIGHT    24
29265 #define M_RX_MOD_WEIGHT    0xffU
29266 #define V_RX_MOD_WEIGHT(x) ((x) << S_RX_MOD_WEIGHT)
29267 #define G_RX_MOD_WEIGHT(x) (((x) >> S_RX_MOD_WEIGHT) & M_RX_MOD_WEIGHT)
29268 
29269 #define S_TX_MOD_WEIGHT    16
29270 #define M_TX_MOD_WEIGHT    0xffU
29271 #define V_TX_MOD_WEIGHT(x) ((x) << S_TX_MOD_WEIGHT)
29272 #define G_TX_MOD_WEIGHT(x) (((x) >> S_TX_MOD_WEIGHT) & M_TX_MOD_WEIGHT)
29273 
29274 #define S_TX_MOD_QUEUE_REQ_MAP    0
29275 #define M_TX_MOD_QUEUE_REQ_MAP    0xffffU
29276 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
29277 #define G_TX_MOD_QUEUE_REQ_MAP(x) (((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP)
29278 
29279 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x7e2c
29280 
29281 #define S_TX_MODQ_WEIGHT7    24
29282 #define M_TX_MODQ_WEIGHT7    0xffU
29283 #define V_TX_MODQ_WEIGHT7(x) ((x) << S_TX_MODQ_WEIGHT7)
29284 #define G_TX_MODQ_WEIGHT7(x) (((x) >> S_TX_MODQ_WEIGHT7) & M_TX_MODQ_WEIGHT7)
29285 
29286 #define S_TX_MODQ_WEIGHT6    16
29287 #define M_TX_MODQ_WEIGHT6    0xffU
29288 #define V_TX_MODQ_WEIGHT6(x) ((x) << S_TX_MODQ_WEIGHT6)
29289 #define G_TX_MODQ_WEIGHT6(x) (((x) >> S_TX_MODQ_WEIGHT6) & M_TX_MODQ_WEIGHT6)
29290 
29291 #define S_TX_MODQ_WEIGHT5    8
29292 #define M_TX_MODQ_WEIGHT5    0xffU
29293 #define V_TX_MODQ_WEIGHT5(x) ((x) << S_TX_MODQ_WEIGHT5)
29294 #define G_TX_MODQ_WEIGHT5(x) (((x) >> S_TX_MODQ_WEIGHT5) & M_TX_MODQ_WEIGHT5)
29295 
29296 #define S_TX_MODQ_WEIGHT4    0
29297 #define M_TX_MODQ_WEIGHT4    0xffU
29298 #define V_TX_MODQ_WEIGHT4(x) ((x) << S_TX_MODQ_WEIGHT4)
29299 #define G_TX_MODQ_WEIGHT4(x) (((x) >> S_TX_MODQ_WEIGHT4) & M_TX_MODQ_WEIGHT4)
29300 
29301 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30
29302 
29303 #define S_TX_MODQ_WEIGHT3    24
29304 #define M_TX_MODQ_WEIGHT3    0xffU
29305 #define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3)
29306 #define G_TX_MODQ_WEIGHT3(x) (((x) >> S_TX_MODQ_WEIGHT3) & M_TX_MODQ_WEIGHT3)
29307 
29308 #define S_TX_MODQ_WEIGHT2    16
29309 #define M_TX_MODQ_WEIGHT2    0xffU
29310 #define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2)
29311 #define G_TX_MODQ_WEIGHT2(x) (((x) >> S_TX_MODQ_WEIGHT2) & M_TX_MODQ_WEIGHT2)
29312 
29313 #define S_TX_MODQ_WEIGHT1    8
29314 #define M_TX_MODQ_WEIGHT1    0xffU
29315 #define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1)
29316 #define G_TX_MODQ_WEIGHT1(x) (((x) >> S_TX_MODQ_WEIGHT1) & M_TX_MODQ_WEIGHT1)
29317 
29318 #define S_TX_MODQ_WEIGHT0    0
29319 #define M_TX_MODQ_WEIGHT0    0xffU
29320 #define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0)
29321 #define G_TX_MODQ_WEIGHT0(x) (((x) >> S_TX_MODQ_WEIGHT0) & M_TX_MODQ_WEIGHT0)
29322 
29323 #define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34
29324 #define A_TP_MOD_RATE_LIMIT 0x7e38
29325 
29326 #define S_RX_MOD_RATE_LIMIT_INC    24
29327 #define M_RX_MOD_RATE_LIMIT_INC    0xffU
29328 #define V_RX_MOD_RATE_LIMIT_INC(x) ((x) << S_RX_MOD_RATE_LIMIT_INC)
29329 #define G_RX_MOD_RATE_LIMIT_INC(x) (((x) >> S_RX_MOD_RATE_LIMIT_INC) & M_RX_MOD_RATE_LIMIT_INC)
29330 
29331 #define S_RX_MOD_RATE_LIMIT_TICK    16
29332 #define M_RX_MOD_RATE_LIMIT_TICK    0xffU
29333 #define V_RX_MOD_RATE_LIMIT_TICK(x) ((x) << S_RX_MOD_RATE_LIMIT_TICK)
29334 #define G_RX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_RX_MOD_RATE_LIMIT_TICK) & M_RX_MOD_RATE_LIMIT_TICK)
29335 
29336 #define S_TX_MOD_RATE_LIMIT_INC    8
29337 #define M_TX_MOD_RATE_LIMIT_INC    0xffU
29338 #define V_TX_MOD_RATE_LIMIT_INC(x) ((x) << S_TX_MOD_RATE_LIMIT_INC)
29339 #define G_TX_MOD_RATE_LIMIT_INC(x) (((x) >> S_TX_MOD_RATE_LIMIT_INC) & M_TX_MOD_RATE_LIMIT_INC)
29340 
29341 #define S_TX_MOD_RATE_LIMIT_TICK    0
29342 #define M_TX_MOD_RATE_LIMIT_TICK    0xffU
29343 #define V_TX_MOD_RATE_LIMIT_TICK(x) ((x) << S_TX_MOD_RATE_LIMIT_TICK)
29344 #define G_TX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_TX_MOD_RATE_LIMIT_TICK) & M_TX_MOD_RATE_LIMIT_TICK)
29345 
29346 #define A_TP_PIO_ADDR 0x7e40
29347 #define A_TP_PIO_DATA 0x7e44
29348 #define A_TP_RESET 0x7e4c
29349 
29350 #define S_FLSTINITENABLE    1
29351 #define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE)
29352 #define F_FLSTINITENABLE    V_FLSTINITENABLE(1U)
29353 
29354 #define S_TPRESET    0
29355 #define V_TPRESET(x) ((x) << S_TPRESET)
29356 #define F_TPRESET    V_TPRESET(1U)
29357 
29358 #define A_TP_MIB_INDEX 0x7e50
29359 #define A_TP_MIB_DATA 0x7e54
29360 #define A_TP_SYNC_TIME_HI 0x7e58
29361 #define A_TP_SYNC_TIME_LO 0x7e5c
29362 #define A_TP_CMM_MM_RX_FLST_BASE 0x7e60
29363 #define A_TP_CMM_MM_TX_FLST_BASE 0x7e64
29364 #define A_TP_CMM_MM_PS_FLST_BASE 0x7e68
29365 #define A_TP_CMM_MM_MAX_PSTRUCT 0x7e6c
29366 
29367 #define S_CMMAXPSTRUCT    0
29368 #define M_CMMAXPSTRUCT    0x1fffffU
29369 #define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT)
29370 #define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT)
29371 
29372 #define A_TP_INT_ENABLE 0x7e70
29373 
29374 #define S_FLMTXFLSTEMPTY    30
29375 #define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY)
29376 #define F_FLMTXFLSTEMPTY    V_FLMTXFLSTEMPTY(1U)
29377 
29378 #define S_RSSLKPPERR    29
29379 #define V_RSSLKPPERR(x) ((x) << S_RSSLKPPERR)
29380 #define F_RSSLKPPERR    V_RSSLKPPERR(1U)
29381 
29382 #define S_FLMPERRSET    28
29383 #define V_FLMPERRSET(x) ((x) << S_FLMPERRSET)
29384 #define F_FLMPERRSET    V_FLMPERRSET(1U)
29385 
29386 #define S_PROTOCOLSRAMPERR    27
29387 #define V_PROTOCOLSRAMPERR(x) ((x) << S_PROTOCOLSRAMPERR)
29388 #define F_PROTOCOLSRAMPERR    V_PROTOCOLSRAMPERR(1U)
29389 
29390 #define S_ARPLUTPERR    26
29391 #define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR)
29392 #define F_ARPLUTPERR    V_ARPLUTPERR(1U)
29393 
29394 #define S_CMRCFOPPERR    25
29395 #define V_CMRCFOPPERR(x) ((x) << S_CMRCFOPPERR)
29396 #define F_CMRCFOPPERR    V_CMRCFOPPERR(1U)
29397 
29398 #define S_CMCACHEPERR    24
29399 #define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR)
29400 #define F_CMCACHEPERR    V_CMCACHEPERR(1U)
29401 
29402 #define S_CMRCFDATAPERR    23
29403 #define V_CMRCFDATAPERR(x) ((x) << S_CMRCFDATAPERR)
29404 #define F_CMRCFDATAPERR    V_CMRCFDATAPERR(1U)
29405 
29406 #define S_DBL2TLUTPERR    22
29407 #define V_DBL2TLUTPERR(x) ((x) << S_DBL2TLUTPERR)
29408 #define F_DBL2TLUTPERR    V_DBL2TLUTPERR(1U)
29409 
29410 #define S_DBTXTIDPERR    21
29411 #define V_DBTXTIDPERR(x) ((x) << S_DBTXTIDPERR)
29412 #define F_DBTXTIDPERR    V_DBTXTIDPERR(1U)
29413 
29414 #define S_DBEXTPERR    20
29415 #define V_DBEXTPERR(x) ((x) << S_DBEXTPERR)
29416 #define F_DBEXTPERR    V_DBEXTPERR(1U)
29417 
29418 #define S_DBOPPERR    19
29419 #define V_DBOPPERR(x) ((x) << S_DBOPPERR)
29420 #define F_DBOPPERR    V_DBOPPERR(1U)
29421 
29422 #define S_TMCACHEPERR    18
29423 #define V_TMCACHEPERR(x) ((x) << S_TMCACHEPERR)
29424 #define F_TMCACHEPERR    V_TMCACHEPERR(1U)
29425 
29426 #define S_ETPOUTCPLFIFOPERR    17
29427 #define V_ETPOUTCPLFIFOPERR(x) ((x) << S_ETPOUTCPLFIFOPERR)
29428 #define F_ETPOUTCPLFIFOPERR    V_ETPOUTCPLFIFOPERR(1U)
29429 
29430 #define S_ETPOUTTCPFIFOPERR    16
29431 #define V_ETPOUTTCPFIFOPERR(x) ((x) << S_ETPOUTTCPFIFOPERR)
29432 #define F_ETPOUTTCPFIFOPERR    V_ETPOUTTCPFIFOPERR(1U)
29433 
29434 #define S_ETPOUTIPFIFOPERR    15
29435 #define V_ETPOUTIPFIFOPERR(x) ((x) << S_ETPOUTIPFIFOPERR)
29436 #define F_ETPOUTIPFIFOPERR    V_ETPOUTIPFIFOPERR(1U)
29437 
29438 #define S_ETPOUTETHFIFOPERR    14
29439 #define V_ETPOUTETHFIFOPERR(x) ((x) << S_ETPOUTETHFIFOPERR)
29440 #define F_ETPOUTETHFIFOPERR    V_ETPOUTETHFIFOPERR(1U)
29441 
29442 #define S_ETPINCPLFIFOPERR    13
29443 #define V_ETPINCPLFIFOPERR(x) ((x) << S_ETPINCPLFIFOPERR)
29444 #define F_ETPINCPLFIFOPERR    V_ETPINCPLFIFOPERR(1U)
29445 
29446 #define S_ETPINTCPOPTFIFOPERR    12
29447 #define V_ETPINTCPOPTFIFOPERR(x) ((x) << S_ETPINTCPOPTFIFOPERR)
29448 #define F_ETPINTCPOPTFIFOPERR    V_ETPINTCPOPTFIFOPERR(1U)
29449 
29450 #define S_ETPINTCPFIFOPERR    11
29451 #define V_ETPINTCPFIFOPERR(x) ((x) << S_ETPINTCPFIFOPERR)
29452 #define F_ETPINTCPFIFOPERR    V_ETPINTCPFIFOPERR(1U)
29453 
29454 #define S_ETPINIPFIFOPERR    10
29455 #define V_ETPINIPFIFOPERR(x) ((x) << S_ETPINIPFIFOPERR)
29456 #define F_ETPINIPFIFOPERR    V_ETPINIPFIFOPERR(1U)
29457 
29458 #define S_ETPINETHFIFOPERR    9
29459 #define V_ETPINETHFIFOPERR(x) ((x) << S_ETPINETHFIFOPERR)
29460 #define F_ETPINETHFIFOPERR    V_ETPINETHFIFOPERR(1U)
29461 
29462 #define S_CTPOUTCPLFIFOPERR    8
29463 #define V_CTPOUTCPLFIFOPERR(x) ((x) << S_CTPOUTCPLFIFOPERR)
29464 #define F_CTPOUTCPLFIFOPERR    V_CTPOUTCPLFIFOPERR(1U)
29465 
29466 #define S_CTPOUTTCPFIFOPERR    7
29467 #define V_CTPOUTTCPFIFOPERR(x) ((x) << S_CTPOUTTCPFIFOPERR)
29468 #define F_CTPOUTTCPFIFOPERR    V_CTPOUTTCPFIFOPERR(1U)
29469 
29470 #define S_CTPOUTIPFIFOPERR    6
29471 #define V_CTPOUTIPFIFOPERR(x) ((x) << S_CTPOUTIPFIFOPERR)
29472 #define F_CTPOUTIPFIFOPERR    V_CTPOUTIPFIFOPERR(1U)
29473 
29474 #define S_CTPOUTETHFIFOPERR    5
29475 #define V_CTPOUTETHFIFOPERR(x) ((x) << S_CTPOUTETHFIFOPERR)
29476 #define F_CTPOUTETHFIFOPERR    V_CTPOUTETHFIFOPERR(1U)
29477 
29478 #define S_CTPINCPLFIFOPERR    4
29479 #define V_CTPINCPLFIFOPERR(x) ((x) << S_CTPINCPLFIFOPERR)
29480 #define F_CTPINCPLFIFOPERR    V_CTPINCPLFIFOPERR(1U)
29481 
29482 #define S_CTPINTCPOPFIFOPERR    3
29483 #define V_CTPINTCPOPFIFOPERR(x) ((x) << S_CTPINTCPOPFIFOPERR)
29484 #define F_CTPINTCPOPFIFOPERR    V_CTPINTCPOPFIFOPERR(1U)
29485 
29486 #define S_PDUFBKFIFOPERR    2
29487 #define V_PDUFBKFIFOPERR(x) ((x) << S_PDUFBKFIFOPERR)
29488 #define F_PDUFBKFIFOPERR    V_PDUFBKFIFOPERR(1U)
29489 
29490 #define S_CMOPEXTFIFOPERR    1
29491 #define V_CMOPEXTFIFOPERR(x) ((x) << S_CMOPEXTFIFOPERR)
29492 #define F_CMOPEXTFIFOPERR    V_CMOPEXTFIFOPERR(1U)
29493 
29494 #define S_DELINVFIFOPERR    0
29495 #define V_DELINVFIFOPERR(x) ((x) << S_DELINVFIFOPERR)
29496 #define F_DELINVFIFOPERR    V_DELINVFIFOPERR(1U)
29497 
29498 #define S_CTPOUTPLDFIFOPERR    7
29499 #define V_CTPOUTPLDFIFOPERR(x) ((x) << S_CTPOUTPLDFIFOPERR)
29500 #define F_CTPOUTPLDFIFOPERR    V_CTPOUTPLDFIFOPERR(1U)
29501 
29502 #define S_SRQTABLEPERR    1
29503 #define V_SRQTABLEPERR(x) ((x) << S_SRQTABLEPERR)
29504 #define F_SRQTABLEPERR    V_SRQTABLEPERR(1U)
29505 
29506 #define S_TPCERR    5
29507 #define V_TPCERR(x) ((x) << S_TPCERR)
29508 #define F_TPCERR    V_TPCERR(1U)
29509 
29510 #define S_OTHERPERR    4
29511 #define V_OTHERPERR(x) ((x) << S_OTHERPERR)
29512 #define F_OTHERPERR    V_OTHERPERR(1U)
29513 
29514 #define S_TPEING1PERR    3
29515 #define V_TPEING1PERR(x) ((x) << S_TPEING1PERR)
29516 #define F_TPEING1PERR    V_TPEING1PERR(1U)
29517 
29518 #define S_TPEING0PERR    2
29519 #define V_TPEING0PERR(x) ((x) << S_TPEING0PERR)
29520 #define F_TPEING0PERR    V_TPEING0PERR(1U)
29521 
29522 #define S_TPEEGPERR    1
29523 #define V_TPEEGPERR(x) ((x) << S_TPEEGPERR)
29524 #define F_TPEEGPERR    V_TPEEGPERR(1U)
29525 
29526 #define S_TPCPERR    0
29527 #define V_TPCPERR(x) ((x) << S_TPCPERR)
29528 #define F_TPCPERR    V_TPCPERR(1U)
29529 
29530 #define A_TP_INT_CAUSE 0x7e74
29531 #define A_TP_PER_ENABLE 0x7e78
29532 #define A_TP_FLM_FREE_PS_CNT 0x7e80
29533 
29534 #define S_FREEPSTRUCTCOUNT    0
29535 #define M_FREEPSTRUCTCOUNT    0x1fffffU
29536 #define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT)
29537 #define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT)
29538 
29539 #define A_TP_FLM_FREE_RX_CNT 0x7e84
29540 
29541 #define S_FREERXPAGECHN    28
29542 #define V_FREERXPAGECHN(x) ((x) << S_FREERXPAGECHN)
29543 #define F_FREERXPAGECHN    V_FREERXPAGECHN(1U)
29544 
29545 #define S_FREERXPAGECOUNT    0
29546 #define M_FREERXPAGECOUNT    0x1fffffU
29547 #define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT)
29548 #define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT)
29549 
29550 #define S_T7_FREERXPAGECHN    28
29551 #define M_T7_FREERXPAGECHN    0x7U
29552 #define V_T7_FREERXPAGECHN(x) ((x) << S_T7_FREERXPAGECHN)
29553 #define G_T7_FREERXPAGECHN(x) (((x) >> S_T7_FREERXPAGECHN) & M_T7_FREERXPAGECHN)
29554 
29555 #define A_TP_FLM_FREE_TX_CNT 0x7e88
29556 
29557 #define S_FREETXPAGECHN    28
29558 #define M_FREETXPAGECHN    0x3U
29559 #define V_FREETXPAGECHN(x) ((x) << S_FREETXPAGECHN)
29560 #define G_FREETXPAGECHN(x) (((x) >> S_FREETXPAGECHN) & M_FREETXPAGECHN)
29561 
29562 #define S_FREETXPAGECOUNT    0
29563 #define M_FREETXPAGECOUNT    0x1fffffU
29564 #define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT)
29565 #define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT)
29566 
29567 #define S_T7_FREETXPAGECHN    28
29568 #define M_T7_FREETXPAGECHN    0x7U
29569 #define V_T7_FREETXPAGECHN(x) ((x) << S_T7_FREETXPAGECHN)
29570 #define G_T7_FREETXPAGECHN(x) (((x) >> S_T7_FREETXPAGECHN) & M_T7_FREETXPAGECHN)
29571 
29572 #define A_TP_TM_HEAP_PUSH_CNT 0x7e8c
29573 #define A_TP_TM_HEAP_POP_CNT 0x7e90
29574 #define A_TP_TM_DACK_PUSH_CNT 0x7e94
29575 #define A_TP_TM_DACK_POP_CNT 0x7e98
29576 #define A_TP_TM_MOD_PUSH_CNT 0x7e9c
29577 #define A_TP_MOD_POP_CNT 0x7ea0
29578 #define A_TP_TIMER_SEPARATOR 0x7ea4
29579 
29580 #define S_TIMERSEPARATOR    16
29581 #define M_TIMERSEPARATOR    0xffffU
29582 #define V_TIMERSEPARATOR(x) ((x) << S_TIMERSEPARATOR)
29583 #define G_TIMERSEPARATOR(x) (((x) >> S_TIMERSEPARATOR) & M_TIMERSEPARATOR)
29584 
29585 #define S_DISABLETIMEFREEZE    0
29586 #define V_DISABLETIMEFREEZE(x) ((x) << S_DISABLETIMEFREEZE)
29587 #define F_DISABLETIMEFREEZE    V_DISABLETIMEFREEZE(1U)
29588 
29589 #define A_TP_STAMP_TIME 0x7ea8
29590 #define A_TP_DEBUG_FLAGS 0x7eac
29591 
29592 #define S_RXTIMERDACKFIRST    26
29593 #define V_RXTIMERDACKFIRST(x) ((x) << S_RXTIMERDACKFIRST)
29594 #define F_RXTIMERDACKFIRST    V_RXTIMERDACKFIRST(1U)
29595 
29596 #define S_RXTIMERDACK    25
29597 #define V_RXTIMERDACK(x) ((x) << S_RXTIMERDACK)
29598 #define F_RXTIMERDACK    V_RXTIMERDACK(1U)
29599 
29600 #define S_RXTIMERHEARTBEAT    24
29601 #define V_RXTIMERHEARTBEAT(x) ((x) << S_RXTIMERHEARTBEAT)
29602 #define F_RXTIMERHEARTBEAT    V_RXTIMERHEARTBEAT(1U)
29603 
29604 #define S_RXPAWSDROP    23
29605 #define V_RXPAWSDROP(x) ((x) << S_RXPAWSDROP)
29606 #define F_RXPAWSDROP    V_RXPAWSDROP(1U)
29607 
29608 #define S_RXURGDATADROP    22
29609 #define V_RXURGDATADROP(x) ((x) << S_RXURGDATADROP)
29610 #define F_RXURGDATADROP    V_RXURGDATADROP(1U)
29611 
29612 #define S_RXFUTUREDATA    21
29613 #define V_RXFUTUREDATA(x) ((x) << S_RXFUTUREDATA)
29614 #define F_RXFUTUREDATA    V_RXFUTUREDATA(1U)
29615 
29616 #define S_RXRCVRXMDATA    20
29617 #define V_RXRCVRXMDATA(x) ((x) << S_RXRCVRXMDATA)
29618 #define F_RXRCVRXMDATA    V_RXRCVRXMDATA(1U)
29619 
29620 #define S_RXRCVOOODATAFIN    19
29621 #define V_RXRCVOOODATAFIN(x) ((x) << S_RXRCVOOODATAFIN)
29622 #define F_RXRCVOOODATAFIN    V_RXRCVOOODATAFIN(1U)
29623 
29624 #define S_RXRCVOOODATA    18
29625 #define V_RXRCVOOODATA(x) ((x) << S_RXRCVOOODATA)
29626 #define F_RXRCVOOODATA    V_RXRCVOOODATA(1U)
29627 
29628 #define S_RXRCVWNDZERO    17
29629 #define V_RXRCVWNDZERO(x) ((x) << S_RXRCVWNDZERO)
29630 #define F_RXRCVWNDZERO    V_RXRCVWNDZERO(1U)
29631 
29632 #define S_RXRCVWNDLTMSS    16
29633 #define V_RXRCVWNDLTMSS(x) ((x) << S_RXRCVWNDLTMSS)
29634 #define F_RXRCVWNDLTMSS    V_RXRCVWNDLTMSS(1U)
29635 
29636 #define S_TXDUPACKINC    11
29637 #define V_TXDUPACKINC(x) ((x) << S_TXDUPACKINC)
29638 #define F_TXDUPACKINC    V_TXDUPACKINC(1U)
29639 
29640 #define S_TXRXMURG    10
29641 #define V_TXRXMURG(x) ((x) << S_TXRXMURG)
29642 #define F_TXRXMURG    V_TXRXMURG(1U)
29643 
29644 #define S_TXRXMFIN    9
29645 #define V_TXRXMFIN(x) ((x) << S_TXRXMFIN)
29646 #define F_TXRXMFIN    V_TXRXMFIN(1U)
29647 
29648 #define S_TXRXMSYN    8
29649 #define V_TXRXMSYN(x) ((x) << S_TXRXMSYN)
29650 #define F_TXRXMSYN    V_TXRXMSYN(1U)
29651 
29652 #define S_TXRXMNEWRENO    7
29653 #define V_TXRXMNEWRENO(x) ((x) << S_TXRXMNEWRENO)
29654 #define F_TXRXMNEWRENO    V_TXRXMNEWRENO(1U)
29655 
29656 #define S_TXRXMFAST    6
29657 #define V_TXRXMFAST(x) ((x) << S_TXRXMFAST)
29658 #define F_TXRXMFAST    V_TXRXMFAST(1U)
29659 
29660 #define S_TXRXMTIMER    5
29661 #define V_TXRXMTIMER(x) ((x) << S_TXRXMTIMER)
29662 #define F_TXRXMTIMER    V_TXRXMTIMER(1U)
29663 
29664 #define S_TXRXMTIMERKEEPALIVE    4
29665 #define V_TXRXMTIMERKEEPALIVE(x) ((x) << S_TXRXMTIMERKEEPALIVE)
29666 #define F_TXRXMTIMERKEEPALIVE    V_TXRXMTIMERKEEPALIVE(1U)
29667 
29668 #define S_TXRXMTIMERPERSIST    3
29669 #define V_TXRXMTIMERPERSIST(x) ((x) << S_TXRXMTIMERPERSIST)
29670 #define F_TXRXMTIMERPERSIST    V_TXRXMTIMERPERSIST(1U)
29671 
29672 #define S_TXRCVADVSHRUNK    2
29673 #define V_TXRCVADVSHRUNK(x) ((x) << S_TXRCVADVSHRUNK)
29674 #define F_TXRCVADVSHRUNK    V_TXRCVADVSHRUNK(1U)
29675 
29676 #define S_TXRCVADVZERO    1
29677 #define V_TXRCVADVZERO(x) ((x) << S_TXRCVADVZERO)
29678 #define F_TXRCVADVZERO    V_TXRCVADVZERO(1U)
29679 
29680 #define S_TXRCVADVLTMSS    0
29681 #define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS)
29682 #define F_TXRCVADVLTMSS    V_TXRCVADVLTMSS(1U)
29683 
29684 #define S_RXTIMERCOMPBUFFER    27
29685 #define V_RXTIMERCOMPBUFFER(x) ((x) << S_RXTIMERCOMPBUFFER)
29686 #define F_RXTIMERCOMPBUFFER    V_RXTIMERCOMPBUFFER(1U)
29687 
29688 #define S_TXDFRFAST    13
29689 #define V_TXDFRFAST(x) ((x) << S_TXDFRFAST)
29690 #define F_TXDFRFAST    V_TXDFRFAST(1U)
29691 
29692 #define S_TXRXMMISC    12
29693 #define V_TXRXMMISC(x) ((x) << S_TXRXMMISC)
29694 #define F_TXRXMMISC    V_TXRXMMISC(1U)
29695 
29696 #define A_TP_RX_SCHED 0x7eb0
29697 
29698 #define S_RXCOMMITRESET1    31
29699 #define V_RXCOMMITRESET1(x) ((x) << S_RXCOMMITRESET1)
29700 #define F_RXCOMMITRESET1    V_RXCOMMITRESET1(1U)
29701 
29702 #define S_RXCOMMITRESET0    30
29703 #define V_RXCOMMITRESET0(x) ((x) << S_RXCOMMITRESET0)
29704 #define F_RXCOMMITRESET0    V_RXCOMMITRESET0(1U)
29705 
29706 #define S_RXFORCECONG1    29
29707 #define V_RXFORCECONG1(x) ((x) << S_RXFORCECONG1)
29708 #define F_RXFORCECONG1    V_RXFORCECONG1(1U)
29709 
29710 #define S_RXFORCECONG0    28
29711 #define V_RXFORCECONG0(x) ((x) << S_RXFORCECONG0)
29712 #define F_RXFORCECONG0    V_RXFORCECONG0(1U)
29713 
29714 #define S_ENABLELPBKFULL1    26
29715 #define M_ENABLELPBKFULL1    0x3U
29716 #define V_ENABLELPBKFULL1(x) ((x) << S_ENABLELPBKFULL1)
29717 #define G_ENABLELPBKFULL1(x) (((x) >> S_ENABLELPBKFULL1) & M_ENABLELPBKFULL1)
29718 
29719 #define S_ENABLELPBKFULL0    24
29720 #define M_ENABLELPBKFULL0    0x3U
29721 #define V_ENABLELPBKFULL0(x) ((x) << S_ENABLELPBKFULL0)
29722 #define G_ENABLELPBKFULL0(x) (((x) >> S_ENABLELPBKFULL0) & M_ENABLELPBKFULL0)
29723 
29724 #define S_ENABLEFIFOFULL1    22
29725 #define M_ENABLEFIFOFULL1    0x3U
29726 #define V_ENABLEFIFOFULL1(x) ((x) << S_ENABLEFIFOFULL1)
29727 #define G_ENABLEFIFOFULL1(x) (((x) >> S_ENABLEFIFOFULL1) & M_ENABLEFIFOFULL1)
29728 
29729 #define S_ENABLEPCMDFULL1    20
29730 #define M_ENABLEPCMDFULL1    0x3U
29731 #define V_ENABLEPCMDFULL1(x) ((x) << S_ENABLEPCMDFULL1)
29732 #define G_ENABLEPCMDFULL1(x) (((x) >> S_ENABLEPCMDFULL1) & M_ENABLEPCMDFULL1)
29733 
29734 #define S_ENABLEHDRFULL1    18
29735 #define M_ENABLEHDRFULL1    0x3U
29736 #define V_ENABLEHDRFULL1(x) ((x) << S_ENABLEHDRFULL1)
29737 #define G_ENABLEHDRFULL1(x) (((x) >> S_ENABLEHDRFULL1) & M_ENABLEHDRFULL1)
29738 
29739 #define S_ENABLEFIFOFULL0    16
29740 #define M_ENABLEFIFOFULL0    0x3U
29741 #define V_ENABLEFIFOFULL0(x) ((x) << S_ENABLEFIFOFULL0)
29742 #define G_ENABLEFIFOFULL0(x) (((x) >> S_ENABLEFIFOFULL0) & M_ENABLEFIFOFULL0)
29743 
29744 #define S_ENABLEPCMDFULL0    14
29745 #define M_ENABLEPCMDFULL0    0x3U
29746 #define V_ENABLEPCMDFULL0(x) ((x) << S_ENABLEPCMDFULL0)
29747 #define G_ENABLEPCMDFULL0(x) (((x) >> S_ENABLEPCMDFULL0) & M_ENABLEPCMDFULL0)
29748 
29749 #define S_ENABLEHDRFULL0    12
29750 #define M_ENABLEHDRFULL0    0x3U
29751 #define V_ENABLEHDRFULL0(x) ((x) << S_ENABLEHDRFULL0)
29752 #define G_ENABLEHDRFULL0(x) (((x) >> S_ENABLEHDRFULL0) & M_ENABLEHDRFULL0)
29753 
29754 #define S_COMMITLIMIT1    6
29755 #define M_COMMITLIMIT1    0x3fU
29756 #define V_COMMITLIMIT1(x) ((x) << S_COMMITLIMIT1)
29757 #define G_COMMITLIMIT1(x) (((x) >> S_COMMITLIMIT1) & M_COMMITLIMIT1)
29758 
29759 #define S_COMMITLIMIT0    0
29760 #define M_COMMITLIMIT0    0x3fU
29761 #define V_COMMITLIMIT0(x) ((x) << S_COMMITLIMIT0)
29762 #define G_COMMITLIMIT0(x) (((x) >> S_COMMITLIMIT0) & M_COMMITLIMIT0)
29763 
29764 #define S_RXCOMMITRESET3    7
29765 #define V_RXCOMMITRESET3(x) ((x) << S_RXCOMMITRESET3)
29766 #define F_RXCOMMITRESET3    V_RXCOMMITRESET3(1U)
29767 
29768 #define S_RXCOMMITRESET2    6
29769 #define V_RXCOMMITRESET2(x) ((x) << S_RXCOMMITRESET2)
29770 #define F_RXCOMMITRESET2    V_RXCOMMITRESET2(1U)
29771 
29772 #define S_T7_RXCOMMITRESET1    5
29773 #define V_T7_RXCOMMITRESET1(x) ((x) << S_T7_RXCOMMITRESET1)
29774 #define F_T7_RXCOMMITRESET1    V_T7_RXCOMMITRESET1(1U)
29775 
29776 #define S_T7_RXCOMMITRESET0    4
29777 #define V_T7_RXCOMMITRESET0(x) ((x) << S_T7_RXCOMMITRESET0)
29778 #define F_T7_RXCOMMITRESET0    V_T7_RXCOMMITRESET0(1U)
29779 
29780 #define S_RXFORCECONG3    3
29781 #define V_RXFORCECONG3(x) ((x) << S_RXFORCECONG3)
29782 #define F_RXFORCECONG3    V_RXFORCECONG3(1U)
29783 
29784 #define S_RXFORCECONG2    2
29785 #define V_RXFORCECONG2(x) ((x) << S_RXFORCECONG2)
29786 #define F_RXFORCECONG2    V_RXFORCECONG2(1U)
29787 
29788 #define S_T7_RXFORCECONG1    1
29789 #define V_T7_RXFORCECONG1(x) ((x) << S_T7_RXFORCECONG1)
29790 #define F_T7_RXFORCECONG1    V_T7_RXFORCECONG1(1U)
29791 
29792 #define S_T7_RXFORCECONG0    0
29793 #define V_T7_RXFORCECONG0(x) ((x) << S_T7_RXFORCECONG0)
29794 #define F_T7_RXFORCECONG0    V_T7_RXFORCECONG0(1U)
29795 
29796 #define A_TP_TX_SCHED 0x7eb4
29797 
29798 #define S_COMMITRESET3    31
29799 #define V_COMMITRESET3(x) ((x) << S_COMMITRESET3)
29800 #define F_COMMITRESET3    V_COMMITRESET3(1U)
29801 
29802 #define S_COMMITRESET2    30
29803 #define V_COMMITRESET2(x) ((x) << S_COMMITRESET2)
29804 #define F_COMMITRESET2    V_COMMITRESET2(1U)
29805 
29806 #define S_COMMITRESET1    29
29807 #define V_COMMITRESET1(x) ((x) << S_COMMITRESET1)
29808 #define F_COMMITRESET1    V_COMMITRESET1(1U)
29809 
29810 #define S_COMMITRESET0    28
29811 #define V_COMMITRESET0(x) ((x) << S_COMMITRESET0)
29812 #define F_COMMITRESET0    V_COMMITRESET0(1U)
29813 
29814 #define S_FORCECONG3    27
29815 #define V_FORCECONG3(x) ((x) << S_FORCECONG3)
29816 #define F_FORCECONG3    V_FORCECONG3(1U)
29817 
29818 #define S_FORCECONG2    26
29819 #define V_FORCECONG2(x) ((x) << S_FORCECONG2)
29820 #define F_FORCECONG2    V_FORCECONG2(1U)
29821 
29822 #define S_FORCECONG1    25
29823 #define V_FORCECONG1(x) ((x) << S_FORCECONG1)
29824 #define F_FORCECONG1    V_FORCECONG1(1U)
29825 
29826 #define S_FORCECONG0    24
29827 #define V_FORCECONG0(x) ((x) << S_FORCECONG0)
29828 #define F_FORCECONG0    V_FORCECONG0(1U)
29829 
29830 #define S_COMMITLIMIT3    18
29831 #define M_COMMITLIMIT3    0x3fU
29832 #define V_COMMITLIMIT3(x) ((x) << S_COMMITLIMIT3)
29833 #define G_COMMITLIMIT3(x) (((x) >> S_COMMITLIMIT3) & M_COMMITLIMIT3)
29834 
29835 #define S_COMMITLIMIT2    12
29836 #define M_COMMITLIMIT2    0x3fU
29837 #define V_COMMITLIMIT2(x) ((x) << S_COMMITLIMIT2)
29838 #define G_COMMITLIMIT2(x) (((x) >> S_COMMITLIMIT2) & M_COMMITLIMIT2)
29839 
29840 #define A_TP_FX_SCHED 0x7eb8
29841 
29842 #define S_TXCHNXOFF3    19
29843 #define V_TXCHNXOFF3(x) ((x) << S_TXCHNXOFF3)
29844 #define F_TXCHNXOFF3    V_TXCHNXOFF3(1U)
29845 
29846 #define S_TXCHNXOFF2    18
29847 #define V_TXCHNXOFF2(x) ((x) << S_TXCHNXOFF2)
29848 #define F_TXCHNXOFF2    V_TXCHNXOFF2(1U)
29849 
29850 #define S_TXCHNXOFF1    17
29851 #define V_TXCHNXOFF1(x) ((x) << S_TXCHNXOFF1)
29852 #define F_TXCHNXOFF1    V_TXCHNXOFF1(1U)
29853 
29854 #define S_TXCHNXOFF0    16
29855 #define V_TXCHNXOFF0(x) ((x) << S_TXCHNXOFF0)
29856 #define F_TXCHNXOFF0    V_TXCHNXOFF0(1U)
29857 
29858 #define S_TXMODXOFF7    15
29859 #define V_TXMODXOFF7(x) ((x) << S_TXMODXOFF7)
29860 #define F_TXMODXOFF7    V_TXMODXOFF7(1U)
29861 
29862 #define S_TXMODXOFF6    14
29863 #define V_TXMODXOFF6(x) ((x) << S_TXMODXOFF6)
29864 #define F_TXMODXOFF6    V_TXMODXOFF6(1U)
29865 
29866 #define S_TXMODXOFF5    13
29867 #define V_TXMODXOFF5(x) ((x) << S_TXMODXOFF5)
29868 #define F_TXMODXOFF5    V_TXMODXOFF5(1U)
29869 
29870 #define S_TXMODXOFF4    12
29871 #define V_TXMODXOFF4(x) ((x) << S_TXMODXOFF4)
29872 #define F_TXMODXOFF4    V_TXMODXOFF4(1U)
29873 
29874 #define S_TXMODXOFF3    11
29875 #define V_TXMODXOFF3(x) ((x) << S_TXMODXOFF3)
29876 #define F_TXMODXOFF3    V_TXMODXOFF3(1U)
29877 
29878 #define S_TXMODXOFF2    10
29879 #define V_TXMODXOFF2(x) ((x) << S_TXMODXOFF2)
29880 #define F_TXMODXOFF2    V_TXMODXOFF2(1U)
29881 
29882 #define S_TXMODXOFF1    9
29883 #define V_TXMODXOFF1(x) ((x) << S_TXMODXOFF1)
29884 #define F_TXMODXOFF1    V_TXMODXOFF1(1U)
29885 
29886 #define S_TXMODXOFF0    8
29887 #define V_TXMODXOFF0(x) ((x) << S_TXMODXOFF0)
29888 #define F_TXMODXOFF0    V_TXMODXOFF0(1U)
29889 
29890 #define S_RXCHNXOFF3    7
29891 #define V_RXCHNXOFF3(x) ((x) << S_RXCHNXOFF3)
29892 #define F_RXCHNXOFF3    V_RXCHNXOFF3(1U)
29893 
29894 #define S_RXCHNXOFF2    6
29895 #define V_RXCHNXOFF2(x) ((x) << S_RXCHNXOFF2)
29896 #define F_RXCHNXOFF2    V_RXCHNXOFF2(1U)
29897 
29898 #define S_RXCHNXOFF1    5
29899 #define V_RXCHNXOFF1(x) ((x) << S_RXCHNXOFF1)
29900 #define F_RXCHNXOFF1    V_RXCHNXOFF1(1U)
29901 
29902 #define S_RXCHNXOFF0    4
29903 #define V_RXCHNXOFF0(x) ((x) << S_RXCHNXOFF0)
29904 #define F_RXCHNXOFF0    V_RXCHNXOFF0(1U)
29905 
29906 #define S_RXMODXOFF1    1
29907 #define V_RXMODXOFF1(x) ((x) << S_RXMODXOFF1)
29908 #define F_RXMODXOFF1    V_RXMODXOFF1(1U)
29909 
29910 #define S_RXMODXOFF0    0
29911 #define V_RXMODXOFF0(x) ((x) << S_RXMODXOFF0)
29912 #define F_RXMODXOFF0    V_RXMODXOFF0(1U)
29913 
29914 #define S_RXMODXOFF3    3
29915 #define V_RXMODXOFF3(x) ((x) << S_RXMODXOFF3)
29916 #define F_RXMODXOFF3    V_RXMODXOFF3(1U)
29917 
29918 #define S_RXMODXOFF2    2
29919 #define V_RXMODXOFF2(x) ((x) << S_RXMODXOFF2)
29920 #define F_RXMODXOFF2    V_RXMODXOFF2(1U)
29921 
29922 #define A_TP_TX_ORATE 0x7ebc
29923 
29924 #define S_OFDRATE3    24
29925 #define M_OFDRATE3    0xffU
29926 #define V_OFDRATE3(x) ((x) << S_OFDRATE3)
29927 #define G_OFDRATE3(x) (((x) >> S_OFDRATE3) & M_OFDRATE3)
29928 
29929 #define S_OFDRATE2    16
29930 #define M_OFDRATE2    0xffU
29931 #define V_OFDRATE2(x) ((x) << S_OFDRATE2)
29932 #define G_OFDRATE2(x) (((x) >> S_OFDRATE2) & M_OFDRATE2)
29933 
29934 #define S_OFDRATE1    8
29935 #define M_OFDRATE1    0xffU
29936 #define V_OFDRATE1(x) ((x) << S_OFDRATE1)
29937 #define G_OFDRATE1(x) (((x) >> S_OFDRATE1) & M_OFDRATE1)
29938 
29939 #define S_OFDRATE0    0
29940 #define M_OFDRATE0    0xffU
29941 #define V_OFDRATE0(x) ((x) << S_OFDRATE0)
29942 #define G_OFDRATE0(x) (((x) >> S_OFDRATE0) & M_OFDRATE0)
29943 
29944 #define A_TP_IX_SCHED0 0x7ec0
29945 #define A_TP_IX_SCHED1 0x7ec4
29946 #define A_TP_IX_SCHED2 0x7ec8
29947 #define A_TP_IX_SCHED3 0x7ecc
29948 #define A_TP_TX_TRATE 0x7ed0
29949 
29950 #define S_TNLRATE3    24
29951 #define M_TNLRATE3    0xffU
29952 #define V_TNLRATE3(x) ((x) << S_TNLRATE3)
29953 #define G_TNLRATE3(x) (((x) >> S_TNLRATE3) & M_TNLRATE3)
29954 
29955 #define S_TNLRATE2    16
29956 #define M_TNLRATE2    0xffU
29957 #define V_TNLRATE2(x) ((x) << S_TNLRATE2)
29958 #define G_TNLRATE2(x) (((x) >> S_TNLRATE2) & M_TNLRATE2)
29959 
29960 #define S_TNLRATE1    8
29961 #define M_TNLRATE1    0xffU
29962 #define V_TNLRATE1(x) ((x) << S_TNLRATE1)
29963 #define G_TNLRATE1(x) (((x) >> S_TNLRATE1) & M_TNLRATE1)
29964 
29965 #define S_TNLRATE0    0
29966 #define M_TNLRATE0    0xffU
29967 #define V_TNLRATE0(x) ((x) << S_TNLRATE0)
29968 #define G_TNLRATE0(x) (((x) >> S_TNLRATE0) & M_TNLRATE0)
29969 
29970 #define A_TP_DBG_LA_CONFIG 0x7ed4
29971 
29972 #define S_DBGLAOPCENABLE    24
29973 #define M_DBGLAOPCENABLE    0xffU
29974 #define V_DBGLAOPCENABLE(x) ((x) << S_DBGLAOPCENABLE)
29975 #define G_DBGLAOPCENABLE(x) (((x) >> S_DBGLAOPCENABLE) & M_DBGLAOPCENABLE)
29976 
29977 #define S_DBGLAWHLF    23
29978 #define V_DBGLAWHLF(x) ((x) << S_DBGLAWHLF)
29979 #define F_DBGLAWHLF    V_DBGLAWHLF(1U)
29980 
29981 #define S_DBGLAWPTR    16
29982 #define M_DBGLAWPTR    0x7fU
29983 #define V_DBGLAWPTR(x) ((x) << S_DBGLAWPTR)
29984 #define G_DBGLAWPTR(x) (((x) >> S_DBGLAWPTR) & M_DBGLAWPTR)
29985 
29986 #define S_DBGLAMODE    14
29987 #define M_DBGLAMODE    0x3U
29988 #define V_DBGLAMODE(x) ((x) << S_DBGLAMODE)
29989 #define G_DBGLAMODE(x) (((x) >> S_DBGLAMODE) & M_DBGLAMODE)
29990 
29991 #define S_DBGLAFATALFREEZE    13
29992 #define V_DBGLAFATALFREEZE(x) ((x) << S_DBGLAFATALFREEZE)
29993 #define F_DBGLAFATALFREEZE    V_DBGLAFATALFREEZE(1U)
29994 
29995 #define S_DBGLAENABLE    12
29996 #define V_DBGLAENABLE(x) ((x) << S_DBGLAENABLE)
29997 #define F_DBGLAENABLE    V_DBGLAENABLE(1U)
29998 
29999 #define S_DBGLARPTR    0
30000 #define M_DBGLARPTR    0x7fU
30001 #define V_DBGLARPTR(x) ((x) << S_DBGLARPTR)
30002 #define G_DBGLARPTR(x) (((x) >> S_DBGLARPTR) & M_DBGLARPTR)
30003 
30004 #define A_TP_DBG_LA_DATAL 0x7ed8
30005 #define A_TP_DBG_LA_DATAH 0x7edc
30006 #define A_TP_DBG_LA_FILTER 0x7ee0
30007 
30008 #define S_FILTERTID    12
30009 #define M_FILTERTID    0xfffffU
30010 #define V_FILTERTID(x) ((x) << S_FILTERTID)
30011 #define G_FILTERTID(x) (((x) >> S_FILTERTID) & M_FILTERTID)
30012 
30013 #define S_ENTIDFILTER    5
30014 #define V_ENTIDFILTER(x) ((x) << S_ENTIDFILTER)
30015 #define F_ENTIDFILTER    V_ENTIDFILTER(1U)
30016 
30017 #define S_ENOFFLOAD    4
30018 #define V_ENOFFLOAD(x) ((x) << S_ENOFFLOAD)
30019 #define F_ENOFFLOAD    V_ENOFFLOAD(1U)
30020 
30021 #define S_ENTUNNEL    3
30022 #define V_ENTUNNEL(x) ((x) << S_ENTUNNEL)
30023 #define F_ENTUNNEL    V_ENTUNNEL(1U)
30024 
30025 #define S_ENI    2
30026 #define V_ENI(x) ((x) << S_ENI)
30027 #define F_ENI    V_ENI(1U)
30028 
30029 #define S_ENC    1
30030 #define V_ENC(x) ((x) << S_ENC)
30031 #define F_ENC    V_ENC(1U)
30032 
30033 #define S_ENE    0
30034 #define V_ENE(x) ((x) << S_ENE)
30035 #define F_ENE    V_ENE(1U)
30036 
30037 #define A_TP_PROTOCOL_CNTRL 0x7ee8
30038 
30039 #define S_WRITEENABLE    31
30040 #define V_WRITEENABLE(x) ((x) << S_WRITEENABLE)
30041 #define F_WRITEENABLE    V_WRITEENABLE(1U)
30042 
30043 #define S_TCAMENABLE    10
30044 #define V_TCAMENABLE(x) ((x) << S_TCAMENABLE)
30045 #define F_TCAMENABLE    V_TCAMENABLE(1U)
30046 
30047 #define S_BLOCKSELECT    8
30048 #define M_BLOCKSELECT    0x3U
30049 #define V_BLOCKSELECT(x) ((x) << S_BLOCKSELECT)
30050 #define G_BLOCKSELECT(x) (((x) >> S_BLOCKSELECT) & M_BLOCKSELECT)
30051 
30052 #define S_LINEADDRESS    1
30053 #define M_LINEADDRESS    0x7fU
30054 #define V_LINEADDRESS(x) ((x) << S_LINEADDRESS)
30055 #define G_LINEADDRESS(x) (((x) >> S_LINEADDRESS) & M_LINEADDRESS)
30056 
30057 #define S_REQUESTDONE    0
30058 #define V_REQUESTDONE(x) ((x) << S_REQUESTDONE)
30059 #define F_REQUESTDONE    V_REQUESTDONE(1U)
30060 
30061 #define A_TP_PROTOCOL_DATA0 0x7eec
30062 #define A_TP_PROTOCOL_DATA1 0x7ef0
30063 #define A_TP_PROTOCOL_DATA2 0x7ef4
30064 #define A_TP_PROTOCOL_DATA3 0x7ef8
30065 #define A_TP_PROTOCOL_DATA4 0x7efc
30066 
30067 #define S_PROTOCOLDATAFIELD    0
30068 #define M_PROTOCOLDATAFIELD    0xfU
30069 #define V_PROTOCOLDATAFIELD(x) ((x) << S_PROTOCOLDATAFIELD)
30070 #define G_PROTOCOLDATAFIELD(x) (((x) >> S_PROTOCOLDATAFIELD) & M_PROTOCOLDATAFIELD)
30071 
30072 #define A_TP_INIC_CTRL0 0x7f00
30073 #define A_TP_INIC_DBG 0x7f04
30074 #define A_TP_INIC_PERR_ENABLE 0x7f08
30075 
30076 #define S_INICMAC1_ERR    16
30077 #define M_INICMAC1_ERR    0x3fU
30078 #define V_INICMAC1_ERR(x) ((x) << S_INICMAC1_ERR)
30079 #define G_INICMAC1_ERR(x) (((x) >> S_INICMAC1_ERR) & M_INICMAC1_ERR)
30080 
30081 #define S_INICMAC0_ERR    0
30082 #define M_INICMAC0_ERR    0x3fU
30083 #define V_INICMAC0_ERR(x) ((x) << S_INICMAC0_ERR)
30084 #define G_INICMAC0_ERR(x) (((x) >> S_INICMAC0_ERR) & M_INICMAC0_ERR)
30085 
30086 #define A_TP_INIC_PERR_CAUSE 0x7f0c
30087 #define A_TP_PARA_REG10 0x7f20
30088 
30089 #define S_DIS39320FIX    20
30090 #define V_DIS39320FIX(x) ((x) << S_DIS39320FIX)
30091 #define F_DIS39320FIX    V_DIS39320FIX(1U)
30092 
30093 #define S_IWARPMAXPDULEN    16
30094 #define M_IWARPMAXPDULEN    0xfU
30095 #define V_IWARPMAXPDULEN(x) ((x) << S_IWARPMAXPDULEN)
30096 #define G_IWARPMAXPDULEN(x) (((x) >> S_IWARPMAXPDULEN) & M_IWARPMAXPDULEN)
30097 
30098 #define S_TLSMAXRXDATA    0
30099 #define M_TLSMAXRXDATA    0xffffU
30100 #define V_TLSMAXRXDATA(x) ((x) << S_TLSMAXRXDATA)
30101 #define G_TLSMAXRXDATA(x) (((x) >> S_TLSMAXRXDATA) & M_TLSMAXRXDATA)
30102 
30103 #define A_TP_TCAM_BIST_CTRL 0x7f24
30104 #define A_TP_TCAM_BIST_CB_PASS 0x7f28
30105 #define A_TP_TCAM_BIST_CB_BUSY 0x7f2c
30106 #define A_TP_C_PERR_ENABLE 0x7f30
30107 
30108 #define S_DMXFIFOOVFL    26
30109 #define V_DMXFIFOOVFL(x) ((x) << S_DMXFIFOOVFL)
30110 #define F_DMXFIFOOVFL    V_DMXFIFOOVFL(1U)
30111 
30112 #define S_URX2TPCDDPINTF    25
30113 #define V_URX2TPCDDPINTF(x) ((x) << S_URX2TPCDDPINTF)
30114 #define F_URX2TPCDDPINTF    V_URX2TPCDDPINTF(1U)
30115 
30116 #define S_TPCDISPTOKENFIFO    24
30117 #define V_TPCDISPTOKENFIFO(x) ((x) << S_TPCDISPTOKENFIFO)
30118 #define F_TPCDISPTOKENFIFO    V_TPCDISPTOKENFIFO(1U)
30119 
30120 #define S_TPCDISPCPLFIFO3    23
30121 #define V_TPCDISPCPLFIFO3(x) ((x) << S_TPCDISPCPLFIFO3)
30122 #define F_TPCDISPCPLFIFO3    V_TPCDISPCPLFIFO3(1U)
30123 
30124 #define S_TPCDISPCPLFIFO2    22
30125 #define V_TPCDISPCPLFIFO2(x) ((x) << S_TPCDISPCPLFIFO2)
30126 #define F_TPCDISPCPLFIFO2    V_TPCDISPCPLFIFO2(1U)
30127 
30128 #define S_TPCDISPCPLFIFO1    21
30129 #define V_TPCDISPCPLFIFO1(x) ((x) << S_TPCDISPCPLFIFO1)
30130 #define F_TPCDISPCPLFIFO1    V_TPCDISPCPLFIFO1(1U)
30131 
30132 #define S_TPCDISPCPLFIFO0    20
30133 #define V_TPCDISPCPLFIFO0(x) ((x) << S_TPCDISPCPLFIFO0)
30134 #define F_TPCDISPCPLFIFO0    V_TPCDISPCPLFIFO0(1U)
30135 
30136 #define S_URXPLDINTFCRC3    19
30137 #define V_URXPLDINTFCRC3(x) ((x) << S_URXPLDINTFCRC3)
30138 #define F_URXPLDINTFCRC3    V_URXPLDINTFCRC3(1U)
30139 
30140 #define S_URXPLDINTFCRC2    18
30141 #define V_URXPLDINTFCRC2(x) ((x) << S_URXPLDINTFCRC2)
30142 #define F_URXPLDINTFCRC2    V_URXPLDINTFCRC2(1U)
30143 
30144 #define S_URXPLDINTFCRC1    17
30145 #define V_URXPLDINTFCRC1(x) ((x) << S_URXPLDINTFCRC1)
30146 #define F_URXPLDINTFCRC1    V_URXPLDINTFCRC1(1U)
30147 
30148 #define S_URXPLDINTFCRC0    16
30149 #define V_URXPLDINTFCRC0(x) ((x) << S_URXPLDINTFCRC0)
30150 #define F_URXPLDINTFCRC0    V_URXPLDINTFCRC0(1U)
30151 
30152 #define S_DMXDBFIFO    15
30153 #define V_DMXDBFIFO(x) ((x) << S_DMXDBFIFO)
30154 #define F_DMXDBFIFO    V_DMXDBFIFO(1U)
30155 
30156 #define S_DMXDBSRAM    14
30157 #define V_DMXDBSRAM(x) ((x) << S_DMXDBSRAM)
30158 #define F_DMXDBSRAM    V_DMXDBSRAM(1U)
30159 
30160 #define S_DMXCPLFIFO    13
30161 #define V_DMXCPLFIFO(x) ((x) << S_DMXCPLFIFO)
30162 #define F_DMXCPLFIFO    V_DMXCPLFIFO(1U)
30163 
30164 #define S_DMXCPLSRAM    12
30165 #define V_DMXCPLSRAM(x) ((x) << S_DMXCPLSRAM)
30166 #define F_DMXCPLSRAM    V_DMXCPLSRAM(1U)
30167 
30168 #define S_DMXCSUMFIFO    11
30169 #define V_DMXCSUMFIFO(x) ((x) << S_DMXCSUMFIFO)
30170 #define F_DMXCSUMFIFO    V_DMXCSUMFIFO(1U)
30171 
30172 #define S_DMXLENFIFO    10
30173 #define V_DMXLENFIFO(x) ((x) << S_DMXLENFIFO)
30174 #define F_DMXLENFIFO    V_DMXLENFIFO(1U)
30175 
30176 #define S_DMXCHECKFIFO    9
30177 #define V_DMXCHECKFIFO(x) ((x) << S_DMXCHECKFIFO)
30178 #define F_DMXCHECKFIFO    V_DMXCHECKFIFO(1U)
30179 
30180 #define S_DMXWINFIFO    8
30181 #define V_DMXWINFIFO(x) ((x) << S_DMXWINFIFO)
30182 #define F_DMXWINFIFO    V_DMXWINFIFO(1U)
30183 
30184 #define S_EGTOKENFIFO    7
30185 #define V_EGTOKENFIFO(x) ((x) << S_EGTOKENFIFO)
30186 #define F_EGTOKENFIFO    V_EGTOKENFIFO(1U)
30187 
30188 #define S_EGDATAFIFO    6
30189 #define V_EGDATAFIFO(x) ((x) << S_EGDATAFIFO)
30190 #define F_EGDATAFIFO    V_EGDATAFIFO(1U)
30191 
30192 #define S_UTX2TPCINTF3    5
30193 #define V_UTX2TPCINTF3(x) ((x) << S_UTX2TPCINTF3)
30194 #define F_UTX2TPCINTF3    V_UTX2TPCINTF3(1U)
30195 
30196 #define S_UTX2TPCINTF2    4
30197 #define V_UTX2TPCINTF2(x) ((x) << S_UTX2TPCINTF2)
30198 #define F_UTX2TPCINTF2    V_UTX2TPCINTF2(1U)
30199 
30200 #define S_UTX2TPCINTF1    3
30201 #define V_UTX2TPCINTF1(x) ((x) << S_UTX2TPCINTF1)
30202 #define F_UTX2TPCINTF1    V_UTX2TPCINTF1(1U)
30203 
30204 #define S_UTX2TPCINTF0    2
30205 #define V_UTX2TPCINTF0(x) ((x) << S_UTX2TPCINTF0)
30206 #define F_UTX2TPCINTF0    V_UTX2TPCINTF0(1U)
30207 
30208 #define S_LBKTOKENFIFO    1
30209 #define V_LBKTOKENFIFO(x) ((x) << S_LBKTOKENFIFO)
30210 #define F_LBKTOKENFIFO    V_LBKTOKENFIFO(1U)
30211 
30212 #define S_LBKDATAFIFO    0
30213 #define V_LBKDATAFIFO(x) ((x) << S_LBKDATAFIFO)
30214 #define F_LBKDATAFIFO    V_LBKDATAFIFO(1U)
30215 
30216 #define A_TP_C_PERR_CAUSE 0x7f34
30217 #define A_TP_E_EG_PERR_ENABLE 0x7f38
30218 
30219 #define S_MPSLPBKTOKENFIFO    25
30220 #define V_MPSLPBKTOKENFIFO(x) ((x) << S_MPSLPBKTOKENFIFO)
30221 #define F_MPSLPBKTOKENFIFO    V_MPSLPBKTOKENFIFO(1U)
30222 
30223 #define S_MPSMACTOKENFIFO    24
30224 #define V_MPSMACTOKENFIFO(x) ((x) << S_MPSMACTOKENFIFO)
30225 #define F_MPSMACTOKENFIFO    V_MPSMACTOKENFIFO(1U)
30226 
30227 #define S_DISPIPSECFIFO3    23
30228 #define V_DISPIPSECFIFO3(x) ((x) << S_DISPIPSECFIFO3)
30229 #define F_DISPIPSECFIFO3    V_DISPIPSECFIFO3(1U)
30230 
30231 #define S_DISPTCPFIFO3    22
30232 #define V_DISPTCPFIFO3(x) ((x) << S_DISPTCPFIFO3)
30233 #define F_DISPTCPFIFO3    V_DISPTCPFIFO3(1U)
30234 
30235 #define S_DISPIPFIFO3    21
30236 #define V_DISPIPFIFO3(x) ((x) << S_DISPIPFIFO3)
30237 #define F_DISPIPFIFO3    V_DISPIPFIFO3(1U)
30238 
30239 #define S_DISPETHFIFO3    20
30240 #define V_DISPETHFIFO3(x) ((x) << S_DISPETHFIFO3)
30241 #define F_DISPETHFIFO3    V_DISPETHFIFO3(1U)
30242 
30243 #define S_DISPGREFIFO3    19
30244 #define V_DISPGREFIFO3(x) ((x) << S_DISPGREFIFO3)
30245 #define F_DISPGREFIFO3    V_DISPGREFIFO3(1U)
30246 
30247 #define S_DISPCPL5FIFO3    18
30248 #define V_DISPCPL5FIFO3(x) ((x) << S_DISPCPL5FIFO3)
30249 #define F_DISPCPL5FIFO3    V_DISPCPL5FIFO3(1U)
30250 
30251 #define S_DISPIPSECFIFO2    17
30252 #define V_DISPIPSECFIFO2(x) ((x) << S_DISPIPSECFIFO2)
30253 #define F_DISPIPSECFIFO2    V_DISPIPSECFIFO2(1U)
30254 
30255 #define S_DISPTCPFIFO2    16
30256 #define V_DISPTCPFIFO2(x) ((x) << S_DISPTCPFIFO2)
30257 #define F_DISPTCPFIFO2    V_DISPTCPFIFO2(1U)
30258 
30259 #define S_DISPIPFIFO2    15
30260 #define V_DISPIPFIFO2(x) ((x) << S_DISPIPFIFO2)
30261 #define F_DISPIPFIFO2    V_DISPIPFIFO2(1U)
30262 
30263 #define S_DISPETHFIFO2    14
30264 #define V_DISPETHFIFO2(x) ((x) << S_DISPETHFIFO2)
30265 #define F_DISPETHFIFO2    V_DISPETHFIFO2(1U)
30266 
30267 #define S_DISPGREFIFO2    13
30268 #define V_DISPGREFIFO2(x) ((x) << S_DISPGREFIFO2)
30269 #define F_DISPGREFIFO2    V_DISPGREFIFO2(1U)
30270 
30271 #define S_DISPCPL5FIFO2    12
30272 #define V_DISPCPL5FIFO2(x) ((x) << S_DISPCPL5FIFO2)
30273 #define F_DISPCPL5FIFO2    V_DISPCPL5FIFO2(1U)
30274 
30275 #define S_DISPIPSECFIFO1    11
30276 #define V_DISPIPSECFIFO1(x) ((x) << S_DISPIPSECFIFO1)
30277 #define F_DISPIPSECFIFO1    V_DISPIPSECFIFO1(1U)
30278 
30279 #define S_DISPTCPFIFO1    10
30280 #define V_DISPTCPFIFO1(x) ((x) << S_DISPTCPFIFO1)
30281 #define F_DISPTCPFIFO1    V_DISPTCPFIFO1(1U)
30282 
30283 #define S_DISPIPFIFO1    9
30284 #define V_DISPIPFIFO1(x) ((x) << S_DISPIPFIFO1)
30285 #define F_DISPIPFIFO1    V_DISPIPFIFO1(1U)
30286 
30287 #define S_DISPETHFIFO1    8
30288 #define V_DISPETHFIFO1(x) ((x) << S_DISPETHFIFO1)
30289 #define F_DISPETHFIFO1    V_DISPETHFIFO1(1U)
30290 
30291 #define S_DISPGREFIFO1    7
30292 #define V_DISPGREFIFO1(x) ((x) << S_DISPGREFIFO1)
30293 #define F_DISPGREFIFO1    V_DISPGREFIFO1(1U)
30294 
30295 #define S_DISPCPL5FIFO1    6
30296 #define V_DISPCPL5FIFO1(x) ((x) << S_DISPCPL5FIFO1)
30297 #define F_DISPCPL5FIFO1    V_DISPCPL5FIFO1(1U)
30298 
30299 #define S_DISPIPSECFIFO0    5
30300 #define V_DISPIPSECFIFO0(x) ((x) << S_DISPIPSECFIFO0)
30301 #define F_DISPIPSECFIFO0    V_DISPIPSECFIFO0(1U)
30302 
30303 #define S_DISPTCPFIFO0    4
30304 #define V_DISPTCPFIFO0(x) ((x) << S_DISPTCPFIFO0)
30305 #define F_DISPTCPFIFO0    V_DISPTCPFIFO0(1U)
30306 
30307 #define S_DISPIPFIFO0    3
30308 #define V_DISPIPFIFO0(x) ((x) << S_DISPIPFIFO0)
30309 #define F_DISPIPFIFO0    V_DISPIPFIFO0(1U)
30310 
30311 #define S_DISPETHFIFO0    2
30312 #define V_DISPETHFIFO0(x) ((x) << S_DISPETHFIFO0)
30313 #define F_DISPETHFIFO0    V_DISPETHFIFO0(1U)
30314 
30315 #define S_DISPGREFIFO0    1
30316 #define V_DISPGREFIFO0(x) ((x) << S_DISPGREFIFO0)
30317 #define F_DISPGREFIFO0    V_DISPGREFIFO0(1U)
30318 
30319 #define S_DISPCPL5FIFO0    0
30320 #define V_DISPCPL5FIFO0(x) ((x) << S_DISPCPL5FIFO0)
30321 #define F_DISPCPL5FIFO0    V_DISPCPL5FIFO0(1U)
30322 
30323 #define A_TP_E_EG_PERR_CAUSE 0x7f3c
30324 #define A_TP_E_IN0_PERR_ENABLE 0x7f40
30325 
30326 #define S_DMXISSFIFO    30
30327 #define V_DMXISSFIFO(x) ((x) << S_DMXISSFIFO)
30328 #define F_DMXISSFIFO    V_DMXISSFIFO(1U)
30329 
30330 #define S_DMXERRFIFO    29
30331 #define V_DMXERRFIFO(x) ((x) << S_DMXERRFIFO)
30332 #define F_DMXERRFIFO    V_DMXERRFIFO(1U)
30333 
30334 #define S_DMXATTFIFO    28
30335 #define V_DMXATTFIFO(x) ((x) << S_DMXATTFIFO)
30336 #define F_DMXATTFIFO    V_DMXATTFIFO(1U)
30337 
30338 #define S_DMXTCPFIFO    27
30339 #define V_DMXTCPFIFO(x) ((x) << S_DMXTCPFIFO)
30340 #define F_DMXTCPFIFO    V_DMXTCPFIFO(1U)
30341 
30342 #define S_DMXMPAFIFO    26
30343 #define V_DMXMPAFIFO(x) ((x) << S_DMXMPAFIFO)
30344 #define F_DMXMPAFIFO    V_DMXMPAFIFO(1U)
30345 
30346 #define S_DMXOPTFIFO    25
30347 #define V_DMXOPTFIFO(x) ((x) << S_DMXOPTFIFO)
30348 #define F_DMXOPTFIFO    V_DMXOPTFIFO(1U)
30349 
30350 #define S_INGTOKENFIFO    24
30351 #define V_INGTOKENFIFO(x) ((x) << S_INGTOKENFIFO)
30352 #define F_INGTOKENFIFO    V_INGTOKENFIFO(1U)
30353 
30354 #define S_DMXPLDCHKOVFL1    21
30355 #define V_DMXPLDCHKOVFL1(x) ((x) << S_DMXPLDCHKOVFL1)
30356 #define F_DMXPLDCHKOVFL1    V_DMXPLDCHKOVFL1(1U)
30357 
30358 #define S_DMXPLDCHKFIFO1    20
30359 #define V_DMXPLDCHKFIFO1(x) ((x) << S_DMXPLDCHKFIFO1)
30360 #define F_DMXPLDCHKFIFO1    V_DMXPLDCHKFIFO1(1U)
30361 
30362 #define S_DMXOPTFIFO1    19
30363 #define V_DMXOPTFIFO1(x) ((x) << S_DMXOPTFIFO1)
30364 #define F_DMXOPTFIFO1    V_DMXOPTFIFO1(1U)
30365 
30366 #define S_DMXMPAFIFO1    18
30367 #define V_DMXMPAFIFO1(x) ((x) << S_DMXMPAFIFO1)
30368 #define F_DMXMPAFIFO1    V_DMXMPAFIFO1(1U)
30369 
30370 #define S_DMXDBFIFO1    17
30371 #define V_DMXDBFIFO1(x) ((x) << S_DMXDBFIFO1)
30372 #define F_DMXDBFIFO1    V_DMXDBFIFO1(1U)
30373 
30374 #define S_DMXATTFIFO1    16
30375 #define V_DMXATTFIFO1(x) ((x) << S_DMXATTFIFO1)
30376 #define F_DMXATTFIFO1    V_DMXATTFIFO1(1U)
30377 
30378 #define S_DMXISSFIFO1    15
30379 #define V_DMXISSFIFO1(x) ((x) << S_DMXISSFIFO1)
30380 #define F_DMXISSFIFO1    V_DMXISSFIFO1(1U)
30381 
30382 #define S_DMXTCPFIFO1    14
30383 #define V_DMXTCPFIFO1(x) ((x) << S_DMXTCPFIFO1)
30384 #define F_DMXTCPFIFO1    V_DMXTCPFIFO1(1U)
30385 
30386 #define S_DMXERRFIFO1    13
30387 #define V_DMXERRFIFO1(x) ((x) << S_DMXERRFIFO1)
30388 #define F_DMXERRFIFO1    V_DMXERRFIFO1(1U)
30389 
30390 #define S_MPS2TPINTF1    12
30391 #define V_MPS2TPINTF1(x) ((x) << S_MPS2TPINTF1)
30392 #define F_MPS2TPINTF1    V_MPS2TPINTF1(1U)
30393 
30394 #define S_DMXPLDCHKOVFL0    9
30395 #define V_DMXPLDCHKOVFL0(x) ((x) << S_DMXPLDCHKOVFL0)
30396 #define F_DMXPLDCHKOVFL0    V_DMXPLDCHKOVFL0(1U)
30397 
30398 #define S_DMXPLDCHKFIFO0    8
30399 #define V_DMXPLDCHKFIFO0(x) ((x) << S_DMXPLDCHKFIFO0)
30400 #define F_DMXPLDCHKFIFO0    V_DMXPLDCHKFIFO0(1U)
30401 
30402 #define S_DMXOPTFIFO0    7
30403 #define V_DMXOPTFIFO0(x) ((x) << S_DMXOPTFIFO0)
30404 #define F_DMXOPTFIFO0    V_DMXOPTFIFO0(1U)
30405 
30406 #define S_DMXMPAFIFO0    6
30407 #define V_DMXMPAFIFO0(x) ((x) << S_DMXMPAFIFO0)
30408 #define F_DMXMPAFIFO0    V_DMXMPAFIFO0(1U)
30409 
30410 #define S_DMXDBFIFO0    5
30411 #define V_DMXDBFIFO0(x) ((x) << S_DMXDBFIFO0)
30412 #define F_DMXDBFIFO0    V_DMXDBFIFO0(1U)
30413 
30414 #define S_DMXATTFIFO0    4
30415 #define V_DMXATTFIFO0(x) ((x) << S_DMXATTFIFO0)
30416 #define F_DMXATTFIFO0    V_DMXATTFIFO0(1U)
30417 
30418 #define S_DMXISSFIFO0    3
30419 #define V_DMXISSFIFO0(x) ((x) << S_DMXISSFIFO0)
30420 #define F_DMXISSFIFO0    V_DMXISSFIFO0(1U)
30421 
30422 #define S_DMXTCPFIFO0    2
30423 #define V_DMXTCPFIFO0(x) ((x) << S_DMXTCPFIFO0)
30424 #define F_DMXTCPFIFO0    V_DMXTCPFIFO0(1U)
30425 
30426 #define S_DMXERRFIFO0    1
30427 #define V_DMXERRFIFO0(x) ((x) << S_DMXERRFIFO0)
30428 #define F_DMXERRFIFO0    V_DMXERRFIFO0(1U)
30429 
30430 #define S_MPS2TPINTF0    0
30431 #define V_MPS2TPINTF0(x) ((x) << S_MPS2TPINTF0)
30432 #define F_MPS2TPINTF0    V_MPS2TPINTF0(1U)
30433 
30434 #define A_TP_E_IN0_PERR_CAUSE 0x7f44
30435 #define A_TP_E_IN1_PERR_ENABLE 0x7f48
30436 
30437 #define S_DMXPLDCHKOVFL3    21
30438 #define V_DMXPLDCHKOVFL3(x) ((x) << S_DMXPLDCHKOVFL3)
30439 #define F_DMXPLDCHKOVFL3    V_DMXPLDCHKOVFL3(1U)
30440 
30441 #define S_DMXPLDCHKFIFO3    20
30442 #define V_DMXPLDCHKFIFO3(x) ((x) << S_DMXPLDCHKFIFO3)
30443 #define F_DMXPLDCHKFIFO3    V_DMXPLDCHKFIFO3(1U)
30444 
30445 #define S_DMXOPTFIFO3    19
30446 #define V_DMXOPTFIFO3(x) ((x) << S_DMXOPTFIFO3)
30447 #define F_DMXOPTFIFO3    V_DMXOPTFIFO3(1U)
30448 
30449 #define S_DMXMPAFIFO3    18
30450 #define V_DMXMPAFIFO3(x) ((x) << S_DMXMPAFIFO3)
30451 #define F_DMXMPAFIFO3    V_DMXMPAFIFO3(1U)
30452 
30453 #define S_DMXDBFIFO3    17
30454 #define V_DMXDBFIFO3(x) ((x) << S_DMXDBFIFO3)
30455 #define F_DMXDBFIFO3    V_DMXDBFIFO3(1U)
30456 
30457 #define S_DMXATTFIFO3    16
30458 #define V_DMXATTFIFO3(x) ((x) << S_DMXATTFIFO3)
30459 #define F_DMXATTFIFO3    V_DMXATTFIFO3(1U)
30460 
30461 #define S_DMXISSFIFO3    15
30462 #define V_DMXISSFIFO3(x) ((x) << S_DMXISSFIFO3)
30463 #define F_DMXISSFIFO3    V_DMXISSFIFO3(1U)
30464 
30465 #define S_DMXTCPFIFO3    14
30466 #define V_DMXTCPFIFO3(x) ((x) << S_DMXTCPFIFO3)
30467 #define F_DMXTCPFIFO3    V_DMXTCPFIFO3(1U)
30468 
30469 #define S_DMXERRFIFO3    13
30470 #define V_DMXERRFIFO3(x) ((x) << S_DMXERRFIFO3)
30471 #define F_DMXERRFIFO3    V_DMXERRFIFO3(1U)
30472 
30473 #define S_MPS2TPINTF3    12
30474 #define V_MPS2TPINTF3(x) ((x) << S_MPS2TPINTF3)
30475 #define F_MPS2TPINTF3    V_MPS2TPINTF3(1U)
30476 
30477 #define S_DMXPLDCHKOVFL2    9
30478 #define V_DMXPLDCHKOVFL2(x) ((x) << S_DMXPLDCHKOVFL2)
30479 #define F_DMXPLDCHKOVFL2    V_DMXPLDCHKOVFL2(1U)
30480 
30481 #define S_DMXPLDCHKFIFO2    8
30482 #define V_DMXPLDCHKFIFO2(x) ((x) << S_DMXPLDCHKFIFO2)
30483 #define F_DMXPLDCHKFIFO2    V_DMXPLDCHKFIFO2(1U)
30484 
30485 #define S_DMXOPTFIFO2    7
30486 #define V_DMXOPTFIFO2(x) ((x) << S_DMXOPTFIFO2)
30487 #define F_DMXOPTFIFO2    V_DMXOPTFIFO2(1U)
30488 
30489 #define S_DMXMPAFIFO2    6
30490 #define V_DMXMPAFIFO2(x) ((x) << S_DMXMPAFIFO2)
30491 #define F_DMXMPAFIFO2    V_DMXMPAFIFO2(1U)
30492 
30493 #define S_DMXDBFIFO2    5
30494 #define V_DMXDBFIFO2(x) ((x) << S_DMXDBFIFO2)
30495 #define F_DMXDBFIFO2    V_DMXDBFIFO2(1U)
30496 
30497 #define S_DMXATTFIFO2    4
30498 #define V_DMXATTFIFO2(x) ((x) << S_DMXATTFIFO2)
30499 #define F_DMXATTFIFO2    V_DMXATTFIFO2(1U)
30500 
30501 #define S_DMXISSFIFO2    3
30502 #define V_DMXISSFIFO2(x) ((x) << S_DMXISSFIFO2)
30503 #define F_DMXISSFIFO2    V_DMXISSFIFO2(1U)
30504 
30505 #define S_DMXTCPFIFO2    2
30506 #define V_DMXTCPFIFO2(x) ((x) << S_DMXTCPFIFO2)
30507 #define F_DMXTCPFIFO2    V_DMXTCPFIFO2(1U)
30508 
30509 #define S_DMXERRFIFO2    1
30510 #define V_DMXERRFIFO2(x) ((x) << S_DMXERRFIFO2)
30511 #define F_DMXERRFIFO2    V_DMXERRFIFO2(1U)
30512 
30513 #define S_MPS2TPINTF2    0
30514 #define V_MPS2TPINTF2(x) ((x) << S_MPS2TPINTF2)
30515 #define F_MPS2TPINTF2    V_MPS2TPINTF2(1U)
30516 
30517 #define A_TP_E_IN1_PERR_CAUSE 0x7f4c
30518 #define A_TP_O_PERR_ENABLE 0x7f50
30519 
30520 #define S_DMARBTPERR    31
30521 #define V_DMARBTPERR(x) ((x) << S_DMARBTPERR)
30522 #define F_DMARBTPERR    V_DMARBTPERR(1U)
30523 
30524 #define S_MMGRCACHEDATASRAM    24
30525 #define V_MMGRCACHEDATASRAM(x) ((x) << S_MMGRCACHEDATASRAM)
30526 #define F_MMGRCACHEDATASRAM    V_MMGRCACHEDATASRAM(1U)
30527 
30528 #define S_MMGRCACHETAGFIFO    23
30529 #define V_MMGRCACHETAGFIFO(x) ((x) << S_MMGRCACHETAGFIFO)
30530 #define F_MMGRCACHETAGFIFO    V_MMGRCACHETAGFIFO(1U)
30531 
30532 #define S_TPPROTOSRAM    16
30533 #define V_TPPROTOSRAM(x) ((x) << S_TPPROTOSRAM)
30534 #define F_TPPROTOSRAM    V_TPPROTOSRAM(1U)
30535 
30536 #define S_HSPSRAM    15
30537 #define V_HSPSRAM(x) ((x) << S_HSPSRAM)
30538 #define F_HSPSRAM    V_HSPSRAM(1U)
30539 
30540 #define S_RATEGRPSRAM    14
30541 #define V_RATEGRPSRAM(x) ((x) << S_RATEGRPSRAM)
30542 #define F_RATEGRPSRAM    V_RATEGRPSRAM(1U)
30543 
30544 #define S_TXFBSEQFIFO    13
30545 #define V_TXFBSEQFIFO(x) ((x) << S_TXFBSEQFIFO)
30546 #define F_TXFBSEQFIFO    V_TXFBSEQFIFO(1U)
30547 
30548 #define S_CMDATASRAM    12
30549 #define V_CMDATASRAM(x) ((x) << S_CMDATASRAM)
30550 #define F_CMDATASRAM    V_CMDATASRAM(1U)
30551 
30552 #define S_CMTAGFIFO    11
30553 #define V_CMTAGFIFO(x) ((x) << S_CMTAGFIFO)
30554 #define F_CMTAGFIFO    V_CMTAGFIFO(1U)
30555 
30556 #define S_RFCOPFIFO    10
30557 #define V_RFCOPFIFO(x) ((x) << S_RFCOPFIFO)
30558 #define F_RFCOPFIFO    V_RFCOPFIFO(1U)
30559 
30560 #define S_DELINVFIFO    9
30561 #define V_DELINVFIFO(x) ((x) << S_DELINVFIFO)
30562 #define F_DELINVFIFO    V_DELINVFIFO(1U)
30563 
30564 #define S_RSSCFGSRAM    8
30565 #define V_RSSCFGSRAM(x) ((x) << S_RSSCFGSRAM)
30566 #define F_RSSCFGSRAM    V_RSSCFGSRAM(1U)
30567 
30568 #define S_RSSKEYSRAM    7
30569 #define V_RSSKEYSRAM(x) ((x) << S_RSSKEYSRAM)
30570 #define F_RSSKEYSRAM    V_RSSKEYSRAM(1U)
30571 
30572 #define S_RSSLKPSRAM    6
30573 #define V_RSSLKPSRAM(x) ((x) << S_RSSLKPSRAM)
30574 #define F_RSSLKPSRAM    V_RSSLKPSRAM(1U)
30575 
30576 #define S_SRQSRAM    5
30577 #define V_SRQSRAM(x) ((x) << S_SRQSRAM)
30578 #define F_SRQSRAM    V_SRQSRAM(1U)
30579 
30580 #define S_ARPDASRAM    4
30581 #define V_ARPDASRAM(x) ((x) << S_ARPDASRAM)
30582 #define F_ARPDASRAM    V_ARPDASRAM(1U)
30583 
30584 #define S_ARPSASRAM    3
30585 #define V_ARPSASRAM(x) ((x) << S_ARPSASRAM)
30586 #define F_ARPSASRAM    V_ARPSASRAM(1U)
30587 
30588 #define S_ARPGRESRAM    2
30589 #define V_ARPGRESRAM(x) ((x) << S_ARPGRESRAM)
30590 #define F_ARPGRESRAM    V_ARPGRESRAM(1U)
30591 
30592 #define S_ARPIPSECSRAM1    1
30593 #define V_ARPIPSECSRAM1(x) ((x) << S_ARPIPSECSRAM1)
30594 #define F_ARPIPSECSRAM1    V_ARPIPSECSRAM1(1U)
30595 
30596 #define S_ARPIPSECSRAM0    0
30597 #define V_ARPIPSECSRAM0(x) ((x) << S_ARPIPSECSRAM0)
30598 #define F_ARPIPSECSRAM0    V_ARPIPSECSRAM0(1U)
30599 
30600 #define A_TP_O_PERR_CAUSE 0x7f54
30601 #define A_TP_CERR_ENABLE 0x7f58
30602 
30603 #define S_TPCEGDATAFIFO    8
30604 #define V_TPCEGDATAFIFO(x) ((x) << S_TPCEGDATAFIFO)
30605 #define F_TPCEGDATAFIFO    V_TPCEGDATAFIFO(1U)
30606 
30607 #define S_TPCLBKDATAFIFO    7
30608 #define V_TPCLBKDATAFIFO(x) ((x) << S_TPCLBKDATAFIFO)
30609 #define F_TPCLBKDATAFIFO    V_TPCLBKDATAFIFO(1U)
30610 
30611 #define A_TP_CERR_CAUSE 0x7f5c
30612 #define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0
30613 
30614 #define S_TXTIMERSEPQ7    16
30615 #define M_TXTIMERSEPQ7    0xffffU
30616 #define V_TXTIMERSEPQ7(x) ((x) << S_TXTIMERSEPQ7)
30617 #define G_TXTIMERSEPQ7(x) (((x) >> S_TXTIMERSEPQ7) & M_TXTIMERSEPQ7)
30618 
30619 #define S_TXTIMERSEPQ6    0
30620 #define M_TXTIMERSEPQ6    0xffffU
30621 #define V_TXTIMERSEPQ6(x) ((x) << S_TXTIMERSEPQ6)
30622 #define G_TXTIMERSEPQ6(x) (((x) >> S_TXTIMERSEPQ6) & M_TXTIMERSEPQ6)
30623 
30624 #define A_TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR 0x1
30625 
30626 #define S_TXTIMERSEPQ5    16
30627 #define M_TXTIMERSEPQ5    0xffffU
30628 #define V_TXTIMERSEPQ5(x) ((x) << S_TXTIMERSEPQ5)
30629 #define G_TXTIMERSEPQ5(x) (((x) >> S_TXTIMERSEPQ5) & M_TXTIMERSEPQ5)
30630 
30631 #define S_TXTIMERSEPQ4    0
30632 #define M_TXTIMERSEPQ4    0xffffU
30633 #define V_TXTIMERSEPQ4(x) ((x) << S_TXTIMERSEPQ4)
30634 #define G_TXTIMERSEPQ4(x) (((x) >> S_TXTIMERSEPQ4) & M_TXTIMERSEPQ4)
30635 
30636 #define A_TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR 0x2
30637 
30638 #define S_TXTIMERSEPQ3    16
30639 #define M_TXTIMERSEPQ3    0xffffU
30640 #define V_TXTIMERSEPQ3(x) ((x) << S_TXTIMERSEPQ3)
30641 #define G_TXTIMERSEPQ3(x) (((x) >> S_TXTIMERSEPQ3) & M_TXTIMERSEPQ3)
30642 
30643 #define S_TXTIMERSEPQ2    0
30644 #define M_TXTIMERSEPQ2    0xffffU
30645 #define V_TXTIMERSEPQ2(x) ((x) << S_TXTIMERSEPQ2)
30646 #define G_TXTIMERSEPQ2(x) (((x) >> S_TXTIMERSEPQ2) & M_TXTIMERSEPQ2)
30647 
30648 #define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3
30649 
30650 #define S_TXTIMERSEPQ1    16
30651 #define M_TXTIMERSEPQ1    0xffffU
30652 #define V_TXTIMERSEPQ1(x) ((x) << S_TXTIMERSEPQ1)
30653 #define G_TXTIMERSEPQ1(x) (((x) >> S_TXTIMERSEPQ1) & M_TXTIMERSEPQ1)
30654 
30655 #define S_TXTIMERSEPQ0    0
30656 #define M_TXTIMERSEPQ0    0xffffU
30657 #define V_TXTIMERSEPQ0(x) ((x) << S_TXTIMERSEPQ0)
30658 #define G_TXTIMERSEPQ0(x) (((x) >> S_TXTIMERSEPQ0) & M_TXTIMERSEPQ0)
30659 
30660 #define A_TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR 0x4
30661 
30662 #define S_RXTIMERSEPQ1    16
30663 #define M_RXTIMERSEPQ1    0xffffU
30664 #define V_RXTIMERSEPQ1(x) ((x) << S_RXTIMERSEPQ1)
30665 #define G_RXTIMERSEPQ1(x) (((x) >> S_RXTIMERSEPQ1) & M_RXTIMERSEPQ1)
30666 
30667 #define S_RXTIMERSEPQ0    0
30668 #define M_RXTIMERSEPQ0    0xffffU
30669 #define V_RXTIMERSEPQ0(x) ((x) << S_RXTIMERSEPQ0)
30670 #define G_RXTIMERSEPQ0(x) (((x) >> S_RXTIMERSEPQ0) & M_RXTIMERSEPQ0)
30671 
30672 #define A_TP_TX_MOD_Q7_Q6_RATE_LIMIT 0x5
30673 
30674 #define S_TXRATEINCQ7    24
30675 #define M_TXRATEINCQ7    0xffU
30676 #define V_TXRATEINCQ7(x) ((x) << S_TXRATEINCQ7)
30677 #define G_TXRATEINCQ7(x) (((x) >> S_TXRATEINCQ7) & M_TXRATEINCQ7)
30678 
30679 #define S_TXRATETCKQ7    16
30680 #define M_TXRATETCKQ7    0xffU
30681 #define V_TXRATETCKQ7(x) ((x) << S_TXRATETCKQ7)
30682 #define G_TXRATETCKQ7(x) (((x) >> S_TXRATETCKQ7) & M_TXRATETCKQ7)
30683 
30684 #define S_TXRATEINCQ6    8
30685 #define M_TXRATEINCQ6    0xffU
30686 #define V_TXRATEINCQ6(x) ((x) << S_TXRATEINCQ6)
30687 #define G_TXRATEINCQ6(x) (((x) >> S_TXRATEINCQ6) & M_TXRATEINCQ6)
30688 
30689 #define S_TXRATETCKQ6    0
30690 #define M_TXRATETCKQ6    0xffU
30691 #define V_TXRATETCKQ6(x) ((x) << S_TXRATETCKQ6)
30692 #define G_TXRATETCKQ6(x) (((x) >> S_TXRATETCKQ6) & M_TXRATETCKQ6)
30693 
30694 #define A_TP_TX_MOD_Q5_Q4_RATE_LIMIT 0x6
30695 
30696 #define S_TXRATEINCQ5    24
30697 #define M_TXRATEINCQ5    0xffU
30698 #define V_TXRATEINCQ5(x) ((x) << S_TXRATEINCQ5)
30699 #define G_TXRATEINCQ5(x) (((x) >> S_TXRATEINCQ5) & M_TXRATEINCQ5)
30700 
30701 #define S_TXRATETCKQ5    16
30702 #define M_TXRATETCKQ5    0xffU
30703 #define V_TXRATETCKQ5(x) ((x) << S_TXRATETCKQ5)
30704 #define G_TXRATETCKQ5(x) (((x) >> S_TXRATETCKQ5) & M_TXRATETCKQ5)
30705 
30706 #define S_TXRATEINCQ4    8
30707 #define M_TXRATEINCQ4    0xffU
30708 #define V_TXRATEINCQ4(x) ((x) << S_TXRATEINCQ4)
30709 #define G_TXRATEINCQ4(x) (((x) >> S_TXRATEINCQ4) & M_TXRATEINCQ4)
30710 
30711 #define S_TXRATETCKQ4    0
30712 #define M_TXRATETCKQ4    0xffU
30713 #define V_TXRATETCKQ4(x) ((x) << S_TXRATETCKQ4)
30714 #define G_TXRATETCKQ4(x) (((x) >> S_TXRATETCKQ4) & M_TXRATETCKQ4)
30715 
30716 #define A_TP_TX_MOD_Q3_Q2_RATE_LIMIT 0x7
30717 
30718 #define S_TXRATEINCQ3    24
30719 #define M_TXRATEINCQ3    0xffU
30720 #define V_TXRATEINCQ3(x) ((x) << S_TXRATEINCQ3)
30721 #define G_TXRATEINCQ3(x) (((x) >> S_TXRATEINCQ3) & M_TXRATEINCQ3)
30722 
30723 #define S_TXRATETCKQ3    16
30724 #define M_TXRATETCKQ3    0xffU
30725 #define V_TXRATETCKQ3(x) ((x) << S_TXRATETCKQ3)
30726 #define G_TXRATETCKQ3(x) (((x) >> S_TXRATETCKQ3) & M_TXRATETCKQ3)
30727 
30728 #define S_TXRATEINCQ2    8
30729 #define M_TXRATEINCQ2    0xffU
30730 #define V_TXRATEINCQ2(x) ((x) << S_TXRATEINCQ2)
30731 #define G_TXRATEINCQ2(x) (((x) >> S_TXRATEINCQ2) & M_TXRATEINCQ2)
30732 
30733 #define S_TXRATETCKQ2    0
30734 #define M_TXRATETCKQ2    0xffU
30735 #define V_TXRATETCKQ2(x) ((x) << S_TXRATETCKQ2)
30736 #define G_TXRATETCKQ2(x) (((x) >> S_TXRATETCKQ2) & M_TXRATETCKQ2)
30737 
30738 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
30739 
30740 #define S_TXRATEINCQ1    24
30741 #define M_TXRATEINCQ1    0xffU
30742 #define V_TXRATEINCQ1(x) ((x) << S_TXRATEINCQ1)
30743 #define G_TXRATEINCQ1(x) (((x) >> S_TXRATEINCQ1) & M_TXRATEINCQ1)
30744 
30745 #define S_TXRATETCKQ1    16
30746 #define M_TXRATETCKQ1    0xffU
30747 #define V_TXRATETCKQ1(x) ((x) << S_TXRATETCKQ1)
30748 #define G_TXRATETCKQ1(x) (((x) >> S_TXRATETCKQ1) & M_TXRATETCKQ1)
30749 
30750 #define S_TXRATEINCQ0    8
30751 #define M_TXRATEINCQ0    0xffU
30752 #define V_TXRATEINCQ0(x) ((x) << S_TXRATEINCQ0)
30753 #define G_TXRATEINCQ0(x) (((x) >> S_TXRATEINCQ0) & M_TXRATEINCQ0)
30754 
30755 #define S_TXRATETCKQ0    0
30756 #define M_TXRATETCKQ0    0xffU
30757 #define V_TXRATETCKQ0(x) ((x) << S_TXRATETCKQ0)
30758 #define G_TXRATETCKQ0(x) (((x) >> S_TXRATETCKQ0) & M_TXRATETCKQ0)
30759 
30760 #define A_TP_RX_MOD_Q1_Q0_RATE_LIMIT 0x9
30761 
30762 #define S_RXRATEINCQ1    24
30763 #define M_RXRATEINCQ1    0xffU
30764 #define V_RXRATEINCQ1(x) ((x) << S_RXRATEINCQ1)
30765 #define G_RXRATEINCQ1(x) (((x) >> S_RXRATEINCQ1) & M_RXRATEINCQ1)
30766 
30767 #define S_RXRATETCKQ1    16
30768 #define M_RXRATETCKQ1    0xffU
30769 #define V_RXRATETCKQ1(x) ((x) << S_RXRATETCKQ1)
30770 #define G_RXRATETCKQ1(x) (((x) >> S_RXRATETCKQ1) & M_RXRATETCKQ1)
30771 
30772 #define S_RXRATEINCQ0    8
30773 #define M_RXRATEINCQ0    0xffU
30774 #define V_RXRATEINCQ0(x) ((x) << S_RXRATEINCQ0)
30775 #define G_RXRATEINCQ0(x) (((x) >> S_RXRATEINCQ0) & M_RXRATEINCQ0)
30776 
30777 #define S_RXRATETCKQ0    0
30778 #define M_RXRATETCKQ0    0xffU
30779 #define V_RXRATETCKQ0(x) ((x) << S_RXRATETCKQ0)
30780 #define G_RXRATETCKQ0(x) (((x) >> S_RXRATETCKQ0) & M_RXRATETCKQ0)
30781 
30782 #define A_TP_TX_MOD_C3_C2_RATE_LIMIT 0xa
30783 #define A_TP_TX_MOD_C1_C0_RATE_LIMIT 0xb
30784 #define A_TP_RX_MOD_Q3_Q2_TIMER_SEPARATOR 0xc
30785 
30786 #define S_RXTIMERSEPQ3    16
30787 #define M_RXTIMERSEPQ3    0xffffU
30788 #define V_RXTIMERSEPQ3(x) ((x) << S_RXTIMERSEPQ3)
30789 #define G_RXTIMERSEPQ3(x) (((x) >> S_RXTIMERSEPQ3) & M_RXTIMERSEPQ3)
30790 
30791 #define S_RXTIMERSEPQ2    0
30792 #define M_RXTIMERSEPQ2    0xffffU
30793 #define V_RXTIMERSEPQ2(x) ((x) << S_RXTIMERSEPQ2)
30794 #define G_RXTIMERSEPQ2(x) (((x) >> S_RXTIMERSEPQ2) & M_RXTIMERSEPQ2)
30795 
30796 #define A_TP_RX_MOD_Q3_Q2_RATE_LIMIT 0xd
30797 
30798 #define S_RXRATEINCQ3    24
30799 #define M_RXRATEINCQ3    0xffU
30800 #define V_RXRATEINCQ3(x) ((x) << S_RXRATEINCQ3)
30801 #define G_RXRATEINCQ3(x) (((x) >> S_RXRATEINCQ3) & M_RXRATEINCQ3)
30802 
30803 #define S_RXRATETCKQ3    16
30804 #define M_RXRATETCKQ3    0xffU
30805 #define V_RXRATETCKQ3(x) ((x) << S_RXRATETCKQ3)
30806 #define G_RXRATETCKQ3(x) (((x) >> S_RXRATETCKQ3) & M_RXRATETCKQ3)
30807 
30808 #define S_RXRATEINCQ2    8
30809 #define M_RXRATEINCQ2    0xffU
30810 #define V_RXRATEINCQ2(x) ((x) << S_RXRATEINCQ2)
30811 #define G_RXRATEINCQ2(x) (((x) >> S_RXRATEINCQ2) & M_RXRATEINCQ2)
30812 
30813 #define S_RXRATETCKQ2    0
30814 #define M_RXRATETCKQ2    0xffU
30815 #define V_RXRATETCKQ2(x) ((x) << S_RXRATETCKQ2)
30816 #define G_RXRATETCKQ2(x) (((x) >> S_RXRATETCKQ2) & M_RXRATETCKQ2)
30817 
30818 #define A_TP_RX_LPBK_CONG 0x1c
30819 #define A_TP_RX_SCHED_MOD 0x1d
30820 
30821 #define S_T7_ENABLELPBKFULL1    28
30822 #define M_T7_ENABLELPBKFULL1    0xfU
30823 #define V_T7_ENABLELPBKFULL1(x) ((x) << S_T7_ENABLELPBKFULL1)
30824 #define G_T7_ENABLELPBKFULL1(x) (((x) >> S_T7_ENABLELPBKFULL1) & M_T7_ENABLELPBKFULL1)
30825 
30826 #define S_T7_ENABLEFIFOFULL1    24
30827 #define M_T7_ENABLEFIFOFULL1    0xfU
30828 #define V_T7_ENABLEFIFOFULL1(x) ((x) << S_T7_ENABLEFIFOFULL1)
30829 #define G_T7_ENABLEFIFOFULL1(x) (((x) >> S_T7_ENABLEFIFOFULL1) & M_T7_ENABLEFIFOFULL1)
30830 
30831 #define S_T7_ENABLEPCMDFULL1    20
30832 #define M_T7_ENABLEPCMDFULL1    0xfU
30833 #define V_T7_ENABLEPCMDFULL1(x) ((x) << S_T7_ENABLEPCMDFULL1)
30834 #define G_T7_ENABLEPCMDFULL1(x) (((x) >> S_T7_ENABLEPCMDFULL1) & M_T7_ENABLEPCMDFULL1)
30835 
30836 #define S_T7_ENABLEHDRFULL1    16
30837 #define M_T7_ENABLEHDRFULL1    0xfU
30838 #define V_T7_ENABLEHDRFULL1(x) ((x) << S_T7_ENABLEHDRFULL1)
30839 #define G_T7_ENABLEHDRFULL1(x) (((x) >> S_T7_ENABLEHDRFULL1) & M_T7_ENABLEHDRFULL1)
30840 
30841 #define S_T7_ENABLELPBKFULL0    12
30842 #define M_T7_ENABLELPBKFULL0    0xfU
30843 #define V_T7_ENABLELPBKFULL0(x) ((x) << S_T7_ENABLELPBKFULL0)
30844 #define G_T7_ENABLELPBKFULL0(x) (((x) >> S_T7_ENABLELPBKFULL0) & M_T7_ENABLELPBKFULL0)
30845 
30846 #define S_T7_ENABLEFIFOFULL0    8
30847 #define M_T7_ENABLEFIFOFULL0    0xfU
30848 #define V_T7_ENABLEFIFOFULL0(x) ((x) << S_T7_ENABLEFIFOFULL0)
30849 #define G_T7_ENABLEFIFOFULL0(x) (((x) >> S_T7_ENABLEFIFOFULL0) & M_T7_ENABLEFIFOFULL0)
30850 
30851 #define S_T7_ENABLEPCMDFULL0    4
30852 #define M_T7_ENABLEPCMDFULL0    0xfU
30853 #define V_T7_ENABLEPCMDFULL0(x) ((x) << S_T7_ENABLEPCMDFULL0)
30854 #define G_T7_ENABLEPCMDFULL0(x) (((x) >> S_T7_ENABLEPCMDFULL0) & M_T7_ENABLEPCMDFULL0)
30855 
30856 #define S_T7_ENABLEHDRFULL0    0
30857 #define M_T7_ENABLEHDRFULL0    0xfU
30858 #define V_T7_ENABLEHDRFULL0(x) ((x) << S_T7_ENABLEHDRFULL0)
30859 #define G_T7_ENABLEHDRFULL0(x) (((x) >> S_T7_ENABLEHDRFULL0) & M_T7_ENABLEHDRFULL0)
30860 
30861 #define A_TP_RX_SCHED_MOD_CH3_CH2 0x1e
30862 
30863 #define S_ENABLELPBKFULL3    28
30864 #define M_ENABLELPBKFULL3    0xfU
30865 #define V_ENABLELPBKFULL3(x) ((x) << S_ENABLELPBKFULL3)
30866 #define G_ENABLELPBKFULL3(x) (((x) >> S_ENABLELPBKFULL3) & M_ENABLELPBKFULL3)
30867 
30868 #define S_ENABLEFIFOFULL3    24
30869 #define M_ENABLEFIFOFULL3    0xfU
30870 #define V_ENABLEFIFOFULL3(x) ((x) << S_ENABLEFIFOFULL3)
30871 #define G_ENABLEFIFOFULL3(x) (((x) >> S_ENABLEFIFOFULL3) & M_ENABLEFIFOFULL3)
30872 
30873 #define S_ENABLEPCMDFULL3    20
30874 #define M_ENABLEPCMDFULL3    0xfU
30875 #define V_ENABLEPCMDFULL3(x) ((x) << S_ENABLEPCMDFULL3)
30876 #define G_ENABLEPCMDFULL3(x) (((x) >> S_ENABLEPCMDFULL3) & M_ENABLEPCMDFULL3)
30877 
30878 #define S_ENABLEHDRFULL3    16
30879 #define M_ENABLEHDRFULL3    0xfU
30880 #define V_ENABLEHDRFULL3(x) ((x) << S_ENABLEHDRFULL3)
30881 #define G_ENABLEHDRFULL3(x) (((x) >> S_ENABLEHDRFULL3) & M_ENABLEHDRFULL3)
30882 
30883 #define S_ENABLELPBKFULL2    12
30884 #define M_ENABLELPBKFULL2    0xfU
30885 #define V_ENABLELPBKFULL2(x) ((x) << S_ENABLELPBKFULL2)
30886 #define G_ENABLELPBKFULL2(x) (((x) >> S_ENABLELPBKFULL2) & M_ENABLELPBKFULL2)
30887 
30888 #define S_ENABLEFIFOFULL2    8
30889 #define M_ENABLEFIFOFULL2    0xfU
30890 #define V_ENABLEFIFOFULL2(x) ((x) << S_ENABLEFIFOFULL2)
30891 #define G_ENABLEFIFOFULL2(x) (((x) >> S_ENABLEFIFOFULL2) & M_ENABLEFIFOFULL2)
30892 
30893 #define S_ENABLEPCMDFULL2    4
30894 #define M_ENABLEPCMDFULL2    0xfU
30895 #define V_ENABLEPCMDFULL2(x) ((x) << S_ENABLEPCMDFULL2)
30896 #define G_ENABLEPCMDFULL2(x) (((x) >> S_ENABLEPCMDFULL2) & M_ENABLEPCMDFULL2)
30897 
30898 #define S_ENABLEHDRFULL2    0
30899 #define M_ENABLEHDRFULL2    0xfU
30900 #define V_ENABLEHDRFULL2(x) ((x) << S_ENABLEHDRFULL2)
30901 #define G_ENABLEHDRFULL2(x) (((x) >> S_ENABLEHDRFULL2) & M_ENABLEHDRFULL2)
30902 
30903 #define A_TP_RX_SCHED_MAP_CH3_CH2 0x1f
30904 
30905 #define S_T7_RXMAPCHANNEL3    16
30906 #define M_T7_RXMAPCHANNEL3    0xffffU
30907 #define V_T7_RXMAPCHANNEL3(x) ((x) << S_T7_RXMAPCHANNEL3)
30908 #define G_T7_RXMAPCHANNEL3(x) (((x) >> S_T7_RXMAPCHANNEL3) & M_T7_RXMAPCHANNEL3)
30909 
30910 #define S_T7_RXMAPCHANNEL2    0
30911 #define M_T7_RXMAPCHANNEL2    0xffffU
30912 #define V_T7_RXMAPCHANNEL2(x) ((x) << S_T7_RXMAPCHANNEL2)
30913 #define G_T7_RXMAPCHANNEL2(x) (((x) >> S_T7_RXMAPCHANNEL2) & M_T7_RXMAPCHANNEL2)
30914 
30915 #define A_TP_RX_SCHED_MAP 0x20
30916 
30917 #define S_RXMAPCHANNEL3    24
30918 #define M_RXMAPCHANNEL3    0xffU
30919 #define V_RXMAPCHANNEL3(x) ((x) << S_RXMAPCHANNEL3)
30920 #define G_RXMAPCHANNEL3(x) (((x) >> S_RXMAPCHANNEL3) & M_RXMAPCHANNEL3)
30921 
30922 #define S_RXMAPCHANNEL2    16
30923 #define M_RXMAPCHANNEL2    0xffU
30924 #define V_RXMAPCHANNEL2(x) ((x) << S_RXMAPCHANNEL2)
30925 #define G_RXMAPCHANNEL2(x) (((x) >> S_RXMAPCHANNEL2) & M_RXMAPCHANNEL2)
30926 
30927 #define S_RXMAPCHANNEL1    8
30928 #define M_RXMAPCHANNEL1    0xffU
30929 #define V_RXMAPCHANNEL1(x) ((x) << S_RXMAPCHANNEL1)
30930 #define G_RXMAPCHANNEL1(x) (((x) >> S_RXMAPCHANNEL1) & M_RXMAPCHANNEL1)
30931 
30932 #define S_RXMAPCHANNEL0    0
30933 #define M_RXMAPCHANNEL0    0xffU
30934 #define V_RXMAPCHANNEL0(x) ((x) << S_RXMAPCHANNEL0)
30935 #define G_RXMAPCHANNEL0(x) (((x) >> S_RXMAPCHANNEL0) & M_RXMAPCHANNEL0)
30936 
30937 #define S_T7_RXMAPCHANNEL1    16
30938 #define M_T7_RXMAPCHANNEL1    0xffffU
30939 #define V_T7_RXMAPCHANNEL1(x) ((x) << S_T7_RXMAPCHANNEL1)
30940 #define G_T7_RXMAPCHANNEL1(x) (((x) >> S_T7_RXMAPCHANNEL1) & M_T7_RXMAPCHANNEL1)
30941 
30942 #define S_T7_RXMAPCHANNEL0    0
30943 #define M_T7_RXMAPCHANNEL0    0xffffU
30944 #define V_T7_RXMAPCHANNEL0(x) ((x) << S_T7_RXMAPCHANNEL0)
30945 #define G_T7_RXMAPCHANNEL0(x) (((x) >> S_T7_RXMAPCHANNEL0) & M_T7_RXMAPCHANNEL0)
30946 
30947 #define A_TP_RX_SCHED_SGE 0x21
30948 
30949 #define S_RXSGEMOD1    12
30950 #define M_RXSGEMOD1    0xfU
30951 #define V_RXSGEMOD1(x) ((x) << S_RXSGEMOD1)
30952 #define G_RXSGEMOD1(x) (((x) >> S_RXSGEMOD1) & M_RXSGEMOD1)
30953 
30954 #define S_RXSGEMOD0    8
30955 #define M_RXSGEMOD0    0xfU
30956 #define V_RXSGEMOD0(x) ((x) << S_RXSGEMOD0)
30957 #define G_RXSGEMOD0(x) (((x) >> S_RXSGEMOD0) & M_RXSGEMOD0)
30958 
30959 #define S_RXSGECHANNEL3    3
30960 #define V_RXSGECHANNEL3(x) ((x) << S_RXSGECHANNEL3)
30961 #define F_RXSGECHANNEL3    V_RXSGECHANNEL3(1U)
30962 
30963 #define S_RXSGECHANNEL2    2
30964 #define V_RXSGECHANNEL2(x) ((x) << S_RXSGECHANNEL2)
30965 #define F_RXSGECHANNEL2    V_RXSGECHANNEL2(1U)
30966 
30967 #define S_RXSGECHANNEL1    1
30968 #define V_RXSGECHANNEL1(x) ((x) << S_RXSGECHANNEL1)
30969 #define F_RXSGECHANNEL1    V_RXSGECHANNEL1(1U)
30970 
30971 #define S_RXSGECHANNEL0    0
30972 #define V_RXSGECHANNEL0(x) ((x) << S_RXSGECHANNEL0)
30973 #define F_RXSGECHANNEL0    V_RXSGECHANNEL0(1U)
30974 
30975 #define S_RXSGEMOD3    20
30976 #define M_RXSGEMOD3    0xfU
30977 #define V_RXSGEMOD3(x) ((x) << S_RXSGEMOD3)
30978 #define G_RXSGEMOD3(x) (((x) >> S_RXSGEMOD3) & M_RXSGEMOD3)
30979 
30980 #define S_RXSGEMOD2    16
30981 #define M_RXSGEMOD2    0xfU
30982 #define V_RXSGEMOD2(x) ((x) << S_RXSGEMOD2)
30983 #define G_RXSGEMOD2(x) (((x) >> S_RXSGEMOD2) & M_RXSGEMOD2)
30984 
30985 #define A_TP_TX_SCHED_MAP 0x22
30986 
30987 #define S_TXMAPCHANNEL3    12
30988 #define M_TXMAPCHANNEL3    0xfU
30989 #define V_TXMAPCHANNEL3(x) ((x) << S_TXMAPCHANNEL3)
30990 #define G_TXMAPCHANNEL3(x) (((x) >> S_TXMAPCHANNEL3) & M_TXMAPCHANNEL3)
30991 
30992 #define S_TXMAPCHANNEL2    8
30993 #define M_TXMAPCHANNEL2    0xfU
30994 #define V_TXMAPCHANNEL2(x) ((x) << S_TXMAPCHANNEL2)
30995 #define G_TXMAPCHANNEL2(x) (((x) >> S_TXMAPCHANNEL2) & M_TXMAPCHANNEL2)
30996 
30997 #define S_TXMAPCHANNEL1    4
30998 #define M_TXMAPCHANNEL1    0xfU
30999 #define V_TXMAPCHANNEL1(x) ((x) << S_TXMAPCHANNEL1)
31000 #define G_TXMAPCHANNEL1(x) (((x) >> S_TXMAPCHANNEL1) & M_TXMAPCHANNEL1)
31001 
31002 #define S_TXMAPCHANNEL0    0
31003 #define M_TXMAPCHANNEL0    0xfU
31004 #define V_TXMAPCHANNEL0(x) ((x) << S_TXMAPCHANNEL0)
31005 #define G_TXMAPCHANNEL0(x) (((x) >> S_TXMAPCHANNEL0) & M_TXMAPCHANNEL0)
31006 
31007 #define S_TXLPKCHANNEL1    17
31008 #define V_TXLPKCHANNEL1(x) ((x) << S_TXLPKCHANNEL1)
31009 #define F_TXLPKCHANNEL1    V_TXLPKCHANNEL1(1U)
31010 
31011 #define S_TXLPKCHANNEL0    16
31012 #define V_TXLPKCHANNEL0(x) ((x) << S_TXLPKCHANNEL0)
31013 #define F_TXLPKCHANNEL0    V_TXLPKCHANNEL0(1U)
31014 
31015 #define S_TXLPKCHANNEL3    19
31016 #define V_TXLPKCHANNEL3(x) ((x) << S_TXLPKCHANNEL3)
31017 #define F_TXLPKCHANNEL3    V_TXLPKCHANNEL3(1U)
31018 
31019 #define S_TXLPKCHANNEL2    18
31020 #define V_TXLPKCHANNEL2(x) ((x) << S_TXLPKCHANNEL2)
31021 #define F_TXLPKCHANNEL2    V_TXLPKCHANNEL2(1U)
31022 
31023 #define A_TP_TX_SCHED_HDR 0x23
31024 
31025 #define S_TXMAPHDRCHANNEL7    28
31026 #define M_TXMAPHDRCHANNEL7    0xfU
31027 #define V_TXMAPHDRCHANNEL7(x) ((x) << S_TXMAPHDRCHANNEL7)
31028 #define G_TXMAPHDRCHANNEL7(x) (((x) >> S_TXMAPHDRCHANNEL7) & M_TXMAPHDRCHANNEL7)
31029 
31030 #define S_TXMAPHDRCHANNEL6    24
31031 #define M_TXMAPHDRCHANNEL6    0xfU
31032 #define V_TXMAPHDRCHANNEL6(x) ((x) << S_TXMAPHDRCHANNEL6)
31033 #define G_TXMAPHDRCHANNEL6(x) (((x) >> S_TXMAPHDRCHANNEL6) & M_TXMAPHDRCHANNEL6)
31034 
31035 #define S_TXMAPHDRCHANNEL5    20
31036 #define M_TXMAPHDRCHANNEL5    0xfU
31037 #define V_TXMAPHDRCHANNEL5(x) ((x) << S_TXMAPHDRCHANNEL5)
31038 #define G_TXMAPHDRCHANNEL5(x) (((x) >> S_TXMAPHDRCHANNEL5) & M_TXMAPHDRCHANNEL5)
31039 
31040 #define S_TXMAPHDRCHANNEL4    16
31041 #define M_TXMAPHDRCHANNEL4    0xfU
31042 #define V_TXMAPHDRCHANNEL4(x) ((x) << S_TXMAPHDRCHANNEL4)
31043 #define G_TXMAPHDRCHANNEL4(x) (((x) >> S_TXMAPHDRCHANNEL4) & M_TXMAPHDRCHANNEL4)
31044 
31045 #define S_TXMAPHDRCHANNEL3    12
31046 #define M_TXMAPHDRCHANNEL3    0xfU
31047 #define V_TXMAPHDRCHANNEL3(x) ((x) << S_TXMAPHDRCHANNEL3)
31048 #define G_TXMAPHDRCHANNEL3(x) (((x) >> S_TXMAPHDRCHANNEL3) & M_TXMAPHDRCHANNEL3)
31049 
31050 #define S_TXMAPHDRCHANNEL2    8
31051 #define M_TXMAPHDRCHANNEL2    0xfU
31052 #define V_TXMAPHDRCHANNEL2(x) ((x) << S_TXMAPHDRCHANNEL2)
31053 #define G_TXMAPHDRCHANNEL2(x) (((x) >> S_TXMAPHDRCHANNEL2) & M_TXMAPHDRCHANNEL2)
31054 
31055 #define S_TXMAPHDRCHANNEL1    4
31056 #define M_TXMAPHDRCHANNEL1    0xfU
31057 #define V_TXMAPHDRCHANNEL1(x) ((x) << S_TXMAPHDRCHANNEL1)
31058 #define G_TXMAPHDRCHANNEL1(x) (((x) >> S_TXMAPHDRCHANNEL1) & M_TXMAPHDRCHANNEL1)
31059 
31060 #define S_TXMAPHDRCHANNEL0    0
31061 #define M_TXMAPHDRCHANNEL0    0xfU
31062 #define V_TXMAPHDRCHANNEL0(x) ((x) << S_TXMAPHDRCHANNEL0)
31063 #define G_TXMAPHDRCHANNEL0(x) (((x) >> S_TXMAPHDRCHANNEL0) & M_TXMAPHDRCHANNEL0)
31064 
31065 #define A_TP_TX_SCHED_FIFO 0x24
31066 
31067 #define S_TXMAPFIFOCHANNEL7    28
31068 #define M_TXMAPFIFOCHANNEL7    0xfU
31069 #define V_TXMAPFIFOCHANNEL7(x) ((x) << S_TXMAPFIFOCHANNEL7)
31070 #define G_TXMAPFIFOCHANNEL7(x) (((x) >> S_TXMAPFIFOCHANNEL7) & M_TXMAPFIFOCHANNEL7)
31071 
31072 #define S_TXMAPFIFOCHANNEL6    24
31073 #define M_TXMAPFIFOCHANNEL6    0xfU
31074 #define V_TXMAPFIFOCHANNEL6(x) ((x) << S_TXMAPFIFOCHANNEL6)
31075 #define G_TXMAPFIFOCHANNEL6(x) (((x) >> S_TXMAPFIFOCHANNEL6) & M_TXMAPFIFOCHANNEL6)
31076 
31077 #define S_TXMAPFIFOCHANNEL5    20
31078 #define M_TXMAPFIFOCHANNEL5    0xfU
31079 #define V_TXMAPFIFOCHANNEL5(x) ((x) << S_TXMAPFIFOCHANNEL5)
31080 #define G_TXMAPFIFOCHANNEL5(x) (((x) >> S_TXMAPFIFOCHANNEL5) & M_TXMAPFIFOCHANNEL5)
31081 
31082 #define S_TXMAPFIFOCHANNEL4    16
31083 #define M_TXMAPFIFOCHANNEL4    0xfU
31084 #define V_TXMAPFIFOCHANNEL4(x) ((x) << S_TXMAPFIFOCHANNEL4)
31085 #define G_TXMAPFIFOCHANNEL4(x) (((x) >> S_TXMAPFIFOCHANNEL4) & M_TXMAPFIFOCHANNEL4)
31086 
31087 #define S_TXMAPFIFOCHANNEL3    12
31088 #define M_TXMAPFIFOCHANNEL3    0xfU
31089 #define V_TXMAPFIFOCHANNEL3(x) ((x) << S_TXMAPFIFOCHANNEL3)
31090 #define G_TXMAPFIFOCHANNEL3(x) (((x) >> S_TXMAPFIFOCHANNEL3) & M_TXMAPFIFOCHANNEL3)
31091 
31092 #define S_TXMAPFIFOCHANNEL2    8
31093 #define M_TXMAPFIFOCHANNEL2    0xfU
31094 #define V_TXMAPFIFOCHANNEL2(x) ((x) << S_TXMAPFIFOCHANNEL2)
31095 #define G_TXMAPFIFOCHANNEL2(x) (((x) >> S_TXMAPFIFOCHANNEL2) & M_TXMAPFIFOCHANNEL2)
31096 
31097 #define S_TXMAPFIFOCHANNEL1    4
31098 #define M_TXMAPFIFOCHANNEL1    0xfU
31099 #define V_TXMAPFIFOCHANNEL1(x) ((x) << S_TXMAPFIFOCHANNEL1)
31100 #define G_TXMAPFIFOCHANNEL1(x) (((x) >> S_TXMAPFIFOCHANNEL1) & M_TXMAPFIFOCHANNEL1)
31101 
31102 #define S_TXMAPFIFOCHANNEL0    0
31103 #define M_TXMAPFIFOCHANNEL0    0xfU
31104 #define V_TXMAPFIFOCHANNEL0(x) ((x) << S_TXMAPFIFOCHANNEL0)
31105 #define G_TXMAPFIFOCHANNEL0(x) (((x) >> S_TXMAPFIFOCHANNEL0) & M_TXMAPFIFOCHANNEL0)
31106 
31107 #define A_TP_TX_SCHED_PCMD 0x25
31108 
31109 #define S_TXMAPPCMDCHANNEL7    28
31110 #define M_TXMAPPCMDCHANNEL7    0xfU
31111 #define V_TXMAPPCMDCHANNEL7(x) ((x) << S_TXMAPPCMDCHANNEL7)
31112 #define G_TXMAPPCMDCHANNEL7(x) (((x) >> S_TXMAPPCMDCHANNEL7) & M_TXMAPPCMDCHANNEL7)
31113 
31114 #define S_TXMAPPCMDCHANNEL6    24
31115 #define M_TXMAPPCMDCHANNEL6    0xfU
31116 #define V_TXMAPPCMDCHANNEL6(x) ((x) << S_TXMAPPCMDCHANNEL6)
31117 #define G_TXMAPPCMDCHANNEL6(x) (((x) >> S_TXMAPPCMDCHANNEL6) & M_TXMAPPCMDCHANNEL6)
31118 
31119 #define S_TXMAPPCMDCHANNEL5    20
31120 #define M_TXMAPPCMDCHANNEL5    0xfU
31121 #define V_TXMAPPCMDCHANNEL5(x) ((x) << S_TXMAPPCMDCHANNEL5)
31122 #define G_TXMAPPCMDCHANNEL5(x) (((x) >> S_TXMAPPCMDCHANNEL5) & M_TXMAPPCMDCHANNEL5)
31123 
31124 #define S_TXMAPPCMDCHANNEL4    16
31125 #define M_TXMAPPCMDCHANNEL4    0xfU
31126 #define V_TXMAPPCMDCHANNEL4(x) ((x) << S_TXMAPPCMDCHANNEL4)
31127 #define G_TXMAPPCMDCHANNEL4(x) (((x) >> S_TXMAPPCMDCHANNEL4) & M_TXMAPPCMDCHANNEL4)
31128 
31129 #define S_TXMAPPCMDCHANNEL3    12
31130 #define M_TXMAPPCMDCHANNEL3    0xfU
31131 #define V_TXMAPPCMDCHANNEL3(x) ((x) << S_TXMAPPCMDCHANNEL3)
31132 #define G_TXMAPPCMDCHANNEL3(x) (((x) >> S_TXMAPPCMDCHANNEL3) & M_TXMAPPCMDCHANNEL3)
31133 
31134 #define S_TXMAPPCMDCHANNEL2    8
31135 #define M_TXMAPPCMDCHANNEL2    0xfU
31136 #define V_TXMAPPCMDCHANNEL2(x) ((x) << S_TXMAPPCMDCHANNEL2)
31137 #define G_TXMAPPCMDCHANNEL2(x) (((x) >> S_TXMAPPCMDCHANNEL2) & M_TXMAPPCMDCHANNEL2)
31138 
31139 #define S_TXMAPPCMDCHANNEL1    4
31140 #define M_TXMAPPCMDCHANNEL1    0xfU
31141 #define V_TXMAPPCMDCHANNEL1(x) ((x) << S_TXMAPPCMDCHANNEL1)
31142 #define G_TXMAPPCMDCHANNEL1(x) (((x) >> S_TXMAPPCMDCHANNEL1) & M_TXMAPPCMDCHANNEL1)
31143 
31144 #define S_TXMAPPCMDCHANNEL0    0
31145 #define M_TXMAPPCMDCHANNEL0    0xfU
31146 #define V_TXMAPPCMDCHANNEL0(x) ((x) << S_TXMAPPCMDCHANNEL0)
31147 #define G_TXMAPPCMDCHANNEL0(x) (((x) >> S_TXMAPPCMDCHANNEL0) & M_TXMAPPCMDCHANNEL0)
31148 
31149 #define A_TP_TX_SCHED_LPBK 0x26
31150 
31151 #define S_TXMAPLPBKCHANNEL7    28
31152 #define M_TXMAPLPBKCHANNEL7    0xfU
31153 #define V_TXMAPLPBKCHANNEL7(x) ((x) << S_TXMAPLPBKCHANNEL7)
31154 #define G_TXMAPLPBKCHANNEL7(x) (((x) >> S_TXMAPLPBKCHANNEL7) & M_TXMAPLPBKCHANNEL7)
31155 
31156 #define S_TXMAPLPBKCHANNEL6    24
31157 #define M_TXMAPLPBKCHANNEL6    0xfU
31158 #define V_TXMAPLPBKCHANNEL6(x) ((x) << S_TXMAPLPBKCHANNEL6)
31159 #define G_TXMAPLPBKCHANNEL6(x) (((x) >> S_TXMAPLPBKCHANNEL6) & M_TXMAPLPBKCHANNEL6)
31160 
31161 #define S_TXMAPLPBKCHANNEL5    20
31162 #define M_TXMAPLPBKCHANNEL5    0xfU
31163 #define V_TXMAPLPBKCHANNEL5(x) ((x) << S_TXMAPLPBKCHANNEL5)
31164 #define G_TXMAPLPBKCHANNEL5(x) (((x) >> S_TXMAPLPBKCHANNEL5) & M_TXMAPLPBKCHANNEL5)
31165 
31166 #define S_TXMAPLPBKCHANNEL4    16
31167 #define M_TXMAPLPBKCHANNEL4    0xfU
31168 #define V_TXMAPLPBKCHANNEL4(x) ((x) << S_TXMAPLPBKCHANNEL4)
31169 #define G_TXMAPLPBKCHANNEL4(x) (((x) >> S_TXMAPLPBKCHANNEL4) & M_TXMAPLPBKCHANNEL4)
31170 
31171 #define S_TXMAPLPBKCHANNEL3    12
31172 #define M_TXMAPLPBKCHANNEL3    0xfU
31173 #define V_TXMAPLPBKCHANNEL3(x) ((x) << S_TXMAPLPBKCHANNEL3)
31174 #define G_TXMAPLPBKCHANNEL3(x) (((x) >> S_TXMAPLPBKCHANNEL3) & M_TXMAPLPBKCHANNEL3)
31175 
31176 #define S_TXMAPLPBKCHANNEL2    8
31177 #define M_TXMAPLPBKCHANNEL2    0xfU
31178 #define V_TXMAPLPBKCHANNEL2(x) ((x) << S_TXMAPLPBKCHANNEL2)
31179 #define G_TXMAPLPBKCHANNEL2(x) (((x) >> S_TXMAPLPBKCHANNEL2) & M_TXMAPLPBKCHANNEL2)
31180 
31181 #define S_TXMAPLPBKCHANNEL1    4
31182 #define M_TXMAPLPBKCHANNEL1    0xfU
31183 #define V_TXMAPLPBKCHANNEL1(x) ((x) << S_TXMAPLPBKCHANNEL1)
31184 #define G_TXMAPLPBKCHANNEL1(x) (((x) >> S_TXMAPLPBKCHANNEL1) & M_TXMAPLPBKCHANNEL1)
31185 
31186 #define S_TXMAPLPBKCHANNEL0    0
31187 #define M_TXMAPLPBKCHANNEL0    0xfU
31188 #define V_TXMAPLPBKCHANNEL0(x) ((x) << S_TXMAPLPBKCHANNEL0)
31189 #define G_TXMAPLPBKCHANNEL0(x) (((x) >> S_TXMAPLPBKCHANNEL0) & M_TXMAPLPBKCHANNEL0)
31190 
31191 #define A_TP_CHANNEL_MAP 0x27
31192 
31193 #define S_RXMAPCHANNELELN    16
31194 #define M_RXMAPCHANNELELN    0xfU
31195 #define V_RXMAPCHANNELELN(x) ((x) << S_RXMAPCHANNELELN)
31196 #define G_RXMAPCHANNELELN(x) (((x) >> S_RXMAPCHANNELELN) & M_RXMAPCHANNELELN)
31197 
31198 #define S_RXMAPE2LCHANNEL3    14
31199 #define M_RXMAPE2LCHANNEL3    0x3U
31200 #define V_RXMAPE2LCHANNEL3(x) ((x) << S_RXMAPE2LCHANNEL3)
31201 #define G_RXMAPE2LCHANNEL3(x) (((x) >> S_RXMAPE2LCHANNEL3) & M_RXMAPE2LCHANNEL3)
31202 
31203 #define S_RXMAPE2LCHANNEL2    12
31204 #define M_RXMAPE2LCHANNEL2    0x3U
31205 #define V_RXMAPE2LCHANNEL2(x) ((x) << S_RXMAPE2LCHANNEL2)
31206 #define G_RXMAPE2LCHANNEL2(x) (((x) >> S_RXMAPE2LCHANNEL2) & M_RXMAPE2LCHANNEL2)
31207 
31208 #define S_RXMAPE2LCHANNEL1    10
31209 #define M_RXMAPE2LCHANNEL1    0x3U
31210 #define V_RXMAPE2LCHANNEL1(x) ((x) << S_RXMAPE2LCHANNEL1)
31211 #define G_RXMAPE2LCHANNEL1(x) (((x) >> S_RXMAPE2LCHANNEL1) & M_RXMAPE2LCHANNEL1)
31212 
31213 #define S_RXMAPE2LCHANNEL0    8
31214 #define M_RXMAPE2LCHANNEL0    0x3U
31215 #define V_RXMAPE2LCHANNEL0(x) ((x) << S_RXMAPE2LCHANNEL0)
31216 #define G_RXMAPE2LCHANNEL0(x) (((x) >> S_RXMAPE2LCHANNEL0) & M_RXMAPE2LCHANNEL0)
31217 
31218 #define S_RXMAPC2CCHANNEL3    7
31219 #define V_RXMAPC2CCHANNEL3(x) ((x) << S_RXMAPC2CCHANNEL3)
31220 #define F_RXMAPC2CCHANNEL3    V_RXMAPC2CCHANNEL3(1U)
31221 
31222 #define S_RXMAPC2CCHANNEL2    6
31223 #define V_RXMAPC2CCHANNEL2(x) ((x) << S_RXMAPC2CCHANNEL2)
31224 #define F_RXMAPC2CCHANNEL2    V_RXMAPC2CCHANNEL2(1U)
31225 
31226 #define S_RXMAPC2CCHANNEL1    5
31227 #define V_RXMAPC2CCHANNEL1(x) ((x) << S_RXMAPC2CCHANNEL1)
31228 #define F_RXMAPC2CCHANNEL1    V_RXMAPC2CCHANNEL1(1U)
31229 
31230 #define S_RXMAPC2CCHANNEL0    4
31231 #define V_RXMAPC2CCHANNEL0(x) ((x) << S_RXMAPC2CCHANNEL0)
31232 #define F_RXMAPC2CCHANNEL0    V_RXMAPC2CCHANNEL0(1U)
31233 
31234 #define S_RXMAPE2CCHANNEL3    3
31235 #define V_RXMAPE2CCHANNEL3(x) ((x) << S_RXMAPE2CCHANNEL3)
31236 #define F_RXMAPE2CCHANNEL3    V_RXMAPE2CCHANNEL3(1U)
31237 
31238 #define S_RXMAPE2CCHANNEL2    2
31239 #define V_RXMAPE2CCHANNEL2(x) ((x) << S_RXMAPE2CCHANNEL2)
31240 #define F_RXMAPE2CCHANNEL2    V_RXMAPE2CCHANNEL2(1U)
31241 
31242 #define S_RXMAPE2CCHANNEL1    1
31243 #define V_RXMAPE2CCHANNEL1(x) ((x) << S_RXMAPE2CCHANNEL1)
31244 #define F_RXMAPE2CCHANNEL1    V_RXMAPE2CCHANNEL1(1U)
31245 
31246 #define S_RXMAPE2CCHANNEL0    0
31247 #define V_RXMAPE2CCHANNEL0(x) ((x) << S_RXMAPE2CCHANNEL0)
31248 #define F_RXMAPE2CCHANNEL0    V_RXMAPE2CCHANNEL0(1U)
31249 
31250 #define S_T7_LB_MODE    30
31251 #define M_T7_LB_MODE    0x3U
31252 #define V_T7_LB_MODE(x) ((x) << S_T7_LB_MODE)
31253 #define G_T7_LB_MODE(x) (((x) >> S_T7_LB_MODE) & M_T7_LB_MODE)
31254 
31255 #define S_ING_LB_MODE    28
31256 #define M_ING_LB_MODE    0x3U
31257 #define V_ING_LB_MODE(x) ((x) << S_ING_LB_MODE)
31258 #define G_ING_LB_MODE(x) (((x) >> S_ING_LB_MODE) & M_ING_LB_MODE)
31259 
31260 #define S_RXC_LB_MODE    26
31261 #define M_RXC_LB_MODE    0x3U
31262 #define V_RXC_LB_MODE(x) ((x) << S_RXC_LB_MODE)
31263 #define G_RXC_LB_MODE(x) (((x) >> S_RXC_LB_MODE) & M_RXC_LB_MODE)
31264 
31265 #define S_SINGLERXCHANNEL    25
31266 #define V_SINGLERXCHANNEL(x) ((x) << S_SINGLERXCHANNEL)
31267 #define F_SINGLERXCHANNEL    V_SINGLERXCHANNEL(1U)
31268 
31269 #define S_RXCHANNELCHECK    24
31270 #define V_RXCHANNELCHECK(x) ((x) << S_RXCHANNELCHECK)
31271 #define F_RXCHANNELCHECK    V_RXCHANNELCHECK(1U)
31272 
31273 #define S_T7_RXMAPC2CCHANNEL3    21
31274 #define M_T7_RXMAPC2CCHANNEL3    0x7U
31275 #define V_T7_RXMAPC2CCHANNEL3(x) ((x) << S_T7_RXMAPC2CCHANNEL3)
31276 #define G_T7_RXMAPC2CCHANNEL3(x) (((x) >> S_T7_RXMAPC2CCHANNEL3) & M_T7_RXMAPC2CCHANNEL3)
31277 
31278 #define S_T7_RXMAPC2CCHANNEL2    18
31279 #define M_T7_RXMAPC2CCHANNEL2    0x7U
31280 #define V_T7_RXMAPC2CCHANNEL2(x) ((x) << S_T7_RXMAPC2CCHANNEL2)
31281 #define G_T7_RXMAPC2CCHANNEL2(x) (((x) >> S_T7_RXMAPC2CCHANNEL2) & M_T7_RXMAPC2CCHANNEL2)
31282 
31283 #define S_T7_RXMAPC2CCHANNEL1    15
31284 #define M_T7_RXMAPC2CCHANNEL1    0x7U
31285 #define V_T7_RXMAPC2CCHANNEL1(x) ((x) << S_T7_RXMAPC2CCHANNEL1)
31286 #define G_T7_RXMAPC2CCHANNEL1(x) (((x) >> S_T7_RXMAPC2CCHANNEL1) & M_T7_RXMAPC2CCHANNEL1)
31287 
31288 #define S_T7_RXMAPC2CCHANNEL0    12
31289 #define M_T7_RXMAPC2CCHANNEL0    0x7U
31290 #define V_T7_RXMAPC2CCHANNEL0(x) ((x) << S_T7_RXMAPC2CCHANNEL0)
31291 #define G_T7_RXMAPC2CCHANNEL0(x) (((x) >> S_T7_RXMAPC2CCHANNEL0) & M_T7_RXMAPC2CCHANNEL0)
31292 
31293 #define S_T7_RXMAPE2CCHANNEL3    9
31294 #define M_T7_RXMAPE2CCHANNEL3    0x7U
31295 #define V_T7_RXMAPE2CCHANNEL3(x) ((x) << S_T7_RXMAPE2CCHANNEL3)
31296 #define G_T7_RXMAPE2CCHANNEL3(x) (((x) >> S_T7_RXMAPE2CCHANNEL3) & M_T7_RXMAPE2CCHANNEL3)
31297 
31298 #define S_T7_RXMAPE2CCHANNEL2    6
31299 #define M_T7_RXMAPE2CCHANNEL2    0x7U
31300 #define V_T7_RXMAPE2CCHANNEL2(x) ((x) << S_T7_RXMAPE2CCHANNEL2)
31301 #define G_T7_RXMAPE2CCHANNEL2(x) (((x) >> S_T7_RXMAPE2CCHANNEL2) & M_T7_RXMAPE2CCHANNEL2)
31302 
31303 #define S_T7_RXMAPE2CCHANNEL1    3
31304 #define M_T7_RXMAPE2CCHANNEL1    0x7U
31305 #define V_T7_RXMAPE2CCHANNEL1(x) ((x) << S_T7_RXMAPE2CCHANNEL1)
31306 #define G_T7_RXMAPE2CCHANNEL1(x) (((x) >> S_T7_RXMAPE2CCHANNEL1) & M_T7_RXMAPE2CCHANNEL1)
31307 
31308 #define S_T7_RXMAPE2CCHANNEL0    0
31309 #define M_T7_RXMAPE2CCHANNEL0    0x7U
31310 #define V_T7_RXMAPE2CCHANNEL0(x) ((x) << S_T7_RXMAPE2CCHANNEL0)
31311 #define G_T7_RXMAPE2CCHANNEL0(x) (((x) >> S_T7_RXMAPE2CCHANNEL0) & M_T7_RXMAPE2CCHANNEL0)
31312 
31313 #define A_TP_RX_LPBK 0x28
31314 #define A_TP_TX_LPBK 0x29
31315 #define A_TP_TX_SCHED_PPP 0x2a
31316 
31317 #define S_TXPPPENPORT3    24
31318 #define M_TXPPPENPORT3    0xffU
31319 #define V_TXPPPENPORT3(x) ((x) << S_TXPPPENPORT3)
31320 #define G_TXPPPENPORT3(x) (((x) >> S_TXPPPENPORT3) & M_TXPPPENPORT3)
31321 
31322 #define S_TXPPPENPORT2    16
31323 #define M_TXPPPENPORT2    0xffU
31324 #define V_TXPPPENPORT2(x) ((x) << S_TXPPPENPORT2)
31325 #define G_TXPPPENPORT2(x) (((x) >> S_TXPPPENPORT2) & M_TXPPPENPORT2)
31326 
31327 #define S_TXPPPENPORT1    8
31328 #define M_TXPPPENPORT1    0xffU
31329 #define V_TXPPPENPORT1(x) ((x) << S_TXPPPENPORT1)
31330 #define G_TXPPPENPORT1(x) (((x) >> S_TXPPPENPORT1) & M_TXPPPENPORT1)
31331 
31332 #define S_TXPPPENPORT0    0
31333 #define M_TXPPPENPORT0    0xffU
31334 #define V_TXPPPENPORT0(x) ((x) << S_TXPPPENPORT0)
31335 #define G_TXPPPENPORT0(x) (((x) >> S_TXPPPENPORT0) & M_TXPPPENPORT0)
31336 
31337 #define A_TP_RX_SCHED_FIFO 0x2b
31338 
31339 #define S_COMMITLIMIT1H    24
31340 #define M_COMMITLIMIT1H    0xffU
31341 #define V_COMMITLIMIT1H(x) ((x) << S_COMMITLIMIT1H)
31342 #define G_COMMITLIMIT1H(x) (((x) >> S_COMMITLIMIT1H) & M_COMMITLIMIT1H)
31343 
31344 #define S_COMMITLIMIT1L    16
31345 #define M_COMMITLIMIT1L    0xffU
31346 #define V_COMMITLIMIT1L(x) ((x) << S_COMMITLIMIT1L)
31347 #define G_COMMITLIMIT1L(x) (((x) >> S_COMMITLIMIT1L) & M_COMMITLIMIT1L)
31348 
31349 #define S_COMMITLIMIT0H    8
31350 #define M_COMMITLIMIT0H    0xffU
31351 #define V_COMMITLIMIT0H(x) ((x) << S_COMMITLIMIT0H)
31352 #define G_COMMITLIMIT0H(x) (((x) >> S_COMMITLIMIT0H) & M_COMMITLIMIT0H)
31353 
31354 #define S_COMMITLIMIT0L    0
31355 #define M_COMMITLIMIT0L    0xffU
31356 #define V_COMMITLIMIT0L(x) ((x) << S_COMMITLIMIT0L)
31357 #define G_COMMITLIMIT0L(x) (((x) >> S_COMMITLIMIT0L) & M_COMMITLIMIT0L)
31358 
31359 #define A_TP_RX_SCHED_FIFO_CH3_CH2 0x2c
31360 
31361 #define S_COMMITLIMIT3H    24
31362 #define M_COMMITLIMIT3H    0xffU
31363 #define V_COMMITLIMIT3H(x) ((x) << S_COMMITLIMIT3H)
31364 #define G_COMMITLIMIT3H(x) (((x) >> S_COMMITLIMIT3H) & M_COMMITLIMIT3H)
31365 
31366 #define S_COMMITLIMIT3L    16
31367 #define M_COMMITLIMIT3L    0xffU
31368 #define V_COMMITLIMIT3L(x) ((x) << S_COMMITLIMIT3L)
31369 #define G_COMMITLIMIT3L(x) (((x) >> S_COMMITLIMIT3L) & M_COMMITLIMIT3L)
31370 
31371 #define S_COMMITLIMIT2H    8
31372 #define M_COMMITLIMIT2H    0xffU
31373 #define V_COMMITLIMIT2H(x) ((x) << S_COMMITLIMIT2H)
31374 #define G_COMMITLIMIT2H(x) (((x) >> S_COMMITLIMIT2H) & M_COMMITLIMIT2H)
31375 
31376 #define S_COMMITLIMIT2L    0
31377 #define M_COMMITLIMIT2L    0xffU
31378 #define V_COMMITLIMIT2L(x) ((x) << S_COMMITLIMIT2L)
31379 #define G_COMMITLIMIT2L(x) (((x) >> S_COMMITLIMIT2L) & M_COMMITLIMIT2L)
31380 
31381 #define A_TP_CHANNEL_MAP_LPBK 0x2d
31382 
31383 #define S_T7_RXMAPCHANNELELN    12
31384 #define M_T7_RXMAPCHANNELELN    0xfU
31385 #define V_T7_RXMAPCHANNELELN(x) ((x) << S_T7_RXMAPCHANNELELN)
31386 #define G_T7_RXMAPCHANNELELN(x) (((x) >> S_T7_RXMAPCHANNELELN) & M_T7_RXMAPCHANNELELN)
31387 
31388 #define S_T7_RXMAPE2LCHANNEL3    9
31389 #define M_T7_RXMAPE2LCHANNEL3    0x7U
31390 #define V_T7_RXMAPE2LCHANNEL3(x) ((x) << S_T7_RXMAPE2LCHANNEL3)
31391 #define G_T7_RXMAPE2LCHANNEL3(x) (((x) >> S_T7_RXMAPE2LCHANNEL3) & M_T7_RXMAPE2LCHANNEL3)
31392 
31393 #define S_T7_RXMAPE2LCHANNEL2    6
31394 #define M_T7_RXMAPE2LCHANNEL2    0x7U
31395 #define V_T7_RXMAPE2LCHANNEL2(x) ((x) << S_T7_RXMAPE2LCHANNEL2)
31396 #define G_T7_RXMAPE2LCHANNEL2(x) (((x) >> S_T7_RXMAPE2LCHANNEL2) & M_T7_RXMAPE2LCHANNEL2)
31397 
31398 #define S_T7_RXMAPE2LCHANNEL1    3
31399 #define M_T7_RXMAPE2LCHANNEL1    0x7U
31400 #define V_T7_RXMAPE2LCHANNEL1(x) ((x) << S_T7_RXMAPE2LCHANNEL1)
31401 #define G_T7_RXMAPE2LCHANNEL1(x) (((x) >> S_T7_RXMAPE2LCHANNEL1) & M_T7_RXMAPE2LCHANNEL1)
31402 
31403 #define S_T7_RXMAPE2LCHANNEL0    0
31404 #define M_T7_RXMAPE2LCHANNEL0    0x7U
31405 #define V_T7_RXMAPE2LCHANNEL0(x) ((x) << S_T7_RXMAPE2LCHANNEL0)
31406 #define G_T7_RXMAPE2LCHANNEL0(x) (((x) >> S_T7_RXMAPE2LCHANNEL0) & M_T7_RXMAPE2LCHANNEL0)
31407 
31408 #define A_TP_IPMI_CFG1 0x2e
31409 
31410 #define S_VLANENABLE    31
31411 #define V_VLANENABLE(x) ((x) << S_VLANENABLE)
31412 #define F_VLANENABLE    V_VLANENABLE(1U)
31413 
31414 #define S_PRIMARYPORTENABLE    30
31415 #define V_PRIMARYPORTENABLE(x) ((x) << S_PRIMARYPORTENABLE)
31416 #define F_PRIMARYPORTENABLE    V_PRIMARYPORTENABLE(1U)
31417 
31418 #define S_SECUREPORTENABLE    29
31419 #define V_SECUREPORTENABLE(x) ((x) << S_SECUREPORTENABLE)
31420 #define F_SECUREPORTENABLE    V_SECUREPORTENABLE(1U)
31421 
31422 #define S_ARPENABLE    28
31423 #define V_ARPENABLE(x) ((x) << S_ARPENABLE)
31424 #define F_ARPENABLE    V_ARPENABLE(1U)
31425 
31426 #define S_IPMI_VLAN    0
31427 #define M_IPMI_VLAN    0xffffU
31428 #define V_IPMI_VLAN(x) ((x) << S_IPMI_VLAN)
31429 #define G_IPMI_VLAN(x) (((x) >> S_IPMI_VLAN) & M_IPMI_VLAN)
31430 
31431 #define A_TP_IPMI_CFG2 0x2f
31432 
31433 #define S_SECUREPORT    16
31434 #define M_SECUREPORT    0xffffU
31435 #define V_SECUREPORT(x) ((x) << S_SECUREPORT)
31436 #define G_SECUREPORT(x) (((x) >> S_SECUREPORT) & M_SECUREPORT)
31437 
31438 #define S_PRIMARYPORT    0
31439 #define M_PRIMARYPORT    0xffffU
31440 #define V_PRIMARYPORT(x) ((x) << S_PRIMARYPORT)
31441 #define G_PRIMARYPORT(x) (((x) >> S_PRIMARYPORT) & M_PRIMARYPORT)
31442 
31443 #define A_TP_RSS_PF0_CONFIG 0x30
31444 
31445 #define S_MAPENABLE    31
31446 #define V_MAPENABLE(x) ((x) << S_MAPENABLE)
31447 #define F_MAPENABLE    V_MAPENABLE(1U)
31448 
31449 #define S_CHNENABLE    30
31450 #define V_CHNENABLE(x) ((x) << S_CHNENABLE)
31451 #define F_CHNENABLE    V_CHNENABLE(1U)
31452 
31453 #define S_PRTENABLE    29
31454 #define V_PRTENABLE(x) ((x) << S_PRTENABLE)
31455 #define F_PRTENABLE    V_PRTENABLE(1U)
31456 
31457 #define S_UDPFOURTUPEN    28
31458 #define V_UDPFOURTUPEN(x) ((x) << S_UDPFOURTUPEN)
31459 #define F_UDPFOURTUPEN    V_UDPFOURTUPEN(1U)
31460 
31461 #define S_IP6FOURTUPEN    27
31462 #define V_IP6FOURTUPEN(x) ((x) << S_IP6FOURTUPEN)
31463 #define F_IP6FOURTUPEN    V_IP6FOURTUPEN(1U)
31464 
31465 #define S_IP6TWOTUPEN    26
31466 #define V_IP6TWOTUPEN(x) ((x) << S_IP6TWOTUPEN)
31467 #define F_IP6TWOTUPEN    V_IP6TWOTUPEN(1U)
31468 
31469 #define S_IP4FOURTUPEN    25
31470 #define V_IP4FOURTUPEN(x) ((x) << S_IP4FOURTUPEN)
31471 #define F_IP4FOURTUPEN    V_IP4FOURTUPEN(1U)
31472 
31473 #define S_IP4TWOTUPEN    24
31474 #define V_IP4TWOTUPEN(x) ((x) << S_IP4TWOTUPEN)
31475 #define F_IP4TWOTUPEN    V_IP4TWOTUPEN(1U)
31476 
31477 #define S_IVFWIDTH    20
31478 #define M_IVFWIDTH    0xfU
31479 #define V_IVFWIDTH(x) ((x) << S_IVFWIDTH)
31480 #define G_IVFWIDTH(x) (((x) >> S_IVFWIDTH) & M_IVFWIDTH)
31481 
31482 #define S_CH1DEFAULTQUEUE    10
31483 #define M_CH1DEFAULTQUEUE    0x3ffU
31484 #define V_CH1DEFAULTQUEUE(x) ((x) << S_CH1DEFAULTQUEUE)
31485 #define G_CH1DEFAULTQUEUE(x) (((x) >> S_CH1DEFAULTQUEUE) & M_CH1DEFAULTQUEUE)
31486 
31487 #define S_CH0DEFAULTQUEUE    0
31488 #define M_CH0DEFAULTQUEUE    0x3ffU
31489 #define V_CH0DEFAULTQUEUE(x) ((x) << S_CH0DEFAULTQUEUE)
31490 #define G_CH0DEFAULTQUEUE(x) (((x) >> S_CH0DEFAULTQUEUE) & M_CH0DEFAULTQUEUE)
31491 
31492 #define S_PRIENABLE    30
31493 #define V_PRIENABLE(x) ((x) << S_PRIENABLE)
31494 #define F_PRIENABLE    V_PRIENABLE(1U)
31495 
31496 #define S_T6_CHNENABLE    29
31497 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
31498 #define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
31499 
31500 #define A_TP_RSS_PF1_CONFIG 0x31
31501 #define A_TP_RSS_PF2_CONFIG 0x32
31502 #define A_TP_RSS_PF3_CONFIG 0x33
31503 #define A_TP_RSS_PF4_CONFIG 0x34
31504 #define A_TP_RSS_PF5_CONFIG 0x35
31505 #define A_TP_RSS_PF6_CONFIG 0x36
31506 #define A_TP_RSS_PF7_CONFIG 0x37
31507 #define A_TP_RSS_PF_MAP 0x38
31508 
31509 #define S_LKPIDXSIZE    24
31510 #define M_LKPIDXSIZE    0x3U
31511 #define V_LKPIDXSIZE(x) ((x) << S_LKPIDXSIZE)
31512 #define G_LKPIDXSIZE(x) (((x) >> S_LKPIDXSIZE) & M_LKPIDXSIZE)
31513 
31514 #define S_PF7LKPIDX    21
31515 #define M_PF7LKPIDX    0x7U
31516 #define V_PF7LKPIDX(x) ((x) << S_PF7LKPIDX)
31517 #define G_PF7LKPIDX(x) (((x) >> S_PF7LKPIDX) & M_PF7LKPIDX)
31518 
31519 #define S_PF6LKPIDX    18
31520 #define M_PF6LKPIDX    0x7U
31521 #define V_PF6LKPIDX(x) ((x) << S_PF6LKPIDX)
31522 #define G_PF6LKPIDX(x) (((x) >> S_PF6LKPIDX) & M_PF6LKPIDX)
31523 
31524 #define S_PF5LKPIDX    15
31525 #define M_PF5LKPIDX    0x7U
31526 #define V_PF5LKPIDX(x) ((x) << S_PF5LKPIDX)
31527 #define G_PF5LKPIDX(x) (((x) >> S_PF5LKPIDX) & M_PF5LKPIDX)
31528 
31529 #define S_PF4LKPIDX    12
31530 #define M_PF4LKPIDX    0x7U
31531 #define V_PF4LKPIDX(x) ((x) << S_PF4LKPIDX)
31532 #define G_PF4LKPIDX(x) (((x) >> S_PF4LKPIDX) & M_PF4LKPIDX)
31533 
31534 #define S_PF3LKPIDX    9
31535 #define M_PF3LKPIDX    0x7U
31536 #define V_PF3LKPIDX(x) ((x) << S_PF3LKPIDX)
31537 #define G_PF3LKPIDX(x) (((x) >> S_PF3LKPIDX) & M_PF3LKPIDX)
31538 
31539 #define S_PF2LKPIDX    6
31540 #define M_PF2LKPIDX    0x7U
31541 #define V_PF2LKPIDX(x) ((x) << S_PF2LKPIDX)
31542 #define G_PF2LKPIDX(x) (((x) >> S_PF2LKPIDX) & M_PF2LKPIDX)
31543 
31544 #define S_PF1LKPIDX    3
31545 #define M_PF1LKPIDX    0x7U
31546 #define V_PF1LKPIDX(x) ((x) << S_PF1LKPIDX)
31547 #define G_PF1LKPIDX(x) (((x) >> S_PF1LKPIDX) & M_PF1LKPIDX)
31548 
31549 #define S_PF0LKPIDX    0
31550 #define M_PF0LKPIDX    0x7U
31551 #define V_PF0LKPIDX(x) ((x) << S_PF0LKPIDX)
31552 #define G_PF0LKPIDX(x) (((x) >> S_PF0LKPIDX) & M_PF0LKPIDX)
31553 
31554 #define A_TP_RSS_PF_MSK 0x39
31555 
31556 #define S_PF7MSKSIZE    28
31557 #define M_PF7MSKSIZE    0xfU
31558 #define V_PF7MSKSIZE(x) ((x) << S_PF7MSKSIZE)
31559 #define G_PF7MSKSIZE(x) (((x) >> S_PF7MSKSIZE) & M_PF7MSKSIZE)
31560 
31561 #define S_PF6MSKSIZE    24
31562 #define M_PF6MSKSIZE    0xfU
31563 #define V_PF6MSKSIZE(x) ((x) << S_PF6MSKSIZE)
31564 #define G_PF6MSKSIZE(x) (((x) >> S_PF6MSKSIZE) & M_PF6MSKSIZE)
31565 
31566 #define S_PF5MSKSIZE    20
31567 #define M_PF5MSKSIZE    0xfU
31568 #define V_PF5MSKSIZE(x) ((x) << S_PF5MSKSIZE)
31569 #define G_PF5MSKSIZE(x) (((x) >> S_PF5MSKSIZE) & M_PF5MSKSIZE)
31570 
31571 #define S_PF4MSKSIZE    16
31572 #define M_PF4MSKSIZE    0xfU
31573 #define V_PF4MSKSIZE(x) ((x) << S_PF4MSKSIZE)
31574 #define G_PF4MSKSIZE(x) (((x) >> S_PF4MSKSIZE) & M_PF4MSKSIZE)
31575 
31576 #define S_PF3MSKSIZE    12
31577 #define M_PF3MSKSIZE    0xfU
31578 #define V_PF3MSKSIZE(x) ((x) << S_PF3MSKSIZE)
31579 #define G_PF3MSKSIZE(x) (((x) >> S_PF3MSKSIZE) & M_PF3MSKSIZE)
31580 
31581 #define S_PF2MSKSIZE    8
31582 #define M_PF2MSKSIZE    0xfU
31583 #define V_PF2MSKSIZE(x) ((x) << S_PF2MSKSIZE)
31584 #define G_PF2MSKSIZE(x) (((x) >> S_PF2MSKSIZE) & M_PF2MSKSIZE)
31585 
31586 #define S_PF1MSKSIZE    4
31587 #define M_PF1MSKSIZE    0xfU
31588 #define V_PF1MSKSIZE(x) ((x) << S_PF1MSKSIZE)
31589 #define G_PF1MSKSIZE(x) (((x) >> S_PF1MSKSIZE) & M_PF1MSKSIZE)
31590 
31591 #define S_PF0MSKSIZE    0
31592 #define M_PF0MSKSIZE    0xfU
31593 #define V_PF0MSKSIZE(x) ((x) << S_PF0MSKSIZE)
31594 #define G_PF0MSKSIZE(x) (((x) >> S_PF0MSKSIZE) & M_PF0MSKSIZE)
31595 
31596 #define A_TP_RSS_VFL_CONFIG 0x3a
31597 
31598 #define S_BASEQID    16
31599 #define M_BASEQID    0xfffU
31600 #define V_BASEQID(x) ((x) << S_BASEQID)
31601 #define G_BASEQID(x) (((x) >> S_BASEQID) & M_BASEQID)
31602 
31603 #define S_MAXRRQID    8
31604 #define M_MAXRRQID    0xffU
31605 #define V_MAXRRQID(x) ((x) << S_MAXRRQID)
31606 #define G_MAXRRQID(x) (((x) >> S_MAXRRQID) & M_MAXRRQID)
31607 
31608 #define S_RRCOUNTER    0
31609 #define M_RRCOUNTER    0xffU
31610 #define V_RRCOUNTER(x) ((x) << S_RRCOUNTER)
31611 #define G_RRCOUNTER(x) (((x) >> S_RRCOUNTER) & M_RRCOUNTER)
31612 
31613 #define A_TP_RSS_VFH_CONFIG 0x3b
31614 
31615 #define S_ENABLEUDPHASH    31
31616 #define V_ENABLEUDPHASH(x) ((x) << S_ENABLEUDPHASH)
31617 #define F_ENABLEUDPHASH    V_ENABLEUDPHASH(1U)
31618 
31619 #define S_VFUPEN    30
31620 #define V_VFUPEN(x) ((x) << S_VFUPEN)
31621 #define F_VFUPEN    V_VFUPEN(1U)
31622 
31623 #define S_VFVLNEX    28
31624 #define V_VFVLNEX(x) ((x) << S_VFVLNEX)
31625 #define F_VFVLNEX    V_VFVLNEX(1U)
31626 
31627 #define S_VFPRTEN    27
31628 #define V_VFPRTEN(x) ((x) << S_VFPRTEN)
31629 #define F_VFPRTEN    V_VFPRTEN(1U)
31630 
31631 #define S_VFCHNEN    26
31632 #define V_VFCHNEN(x) ((x) << S_VFCHNEN)
31633 #define F_VFCHNEN    V_VFCHNEN(1U)
31634 
31635 #define S_DEFAULTQUEUE    16
31636 #define M_DEFAULTQUEUE    0x3ffU
31637 #define V_DEFAULTQUEUE(x) ((x) << S_DEFAULTQUEUE)
31638 #define G_DEFAULTQUEUE(x) (((x) >> S_DEFAULTQUEUE) & M_DEFAULTQUEUE)
31639 
31640 #define S_VFLKPIDX    8
31641 #define M_VFLKPIDX    0xffU
31642 #define V_VFLKPIDX(x) ((x) << S_VFLKPIDX)
31643 #define G_VFLKPIDX(x) (((x) >> S_VFLKPIDX) & M_VFLKPIDX)
31644 
31645 #define S_VFIP6FOURTUPEN    7
31646 #define V_VFIP6FOURTUPEN(x) ((x) << S_VFIP6FOURTUPEN)
31647 #define F_VFIP6FOURTUPEN    V_VFIP6FOURTUPEN(1U)
31648 
31649 #define S_VFIP6TWOTUPEN    6
31650 #define V_VFIP6TWOTUPEN(x) ((x) << S_VFIP6TWOTUPEN)
31651 #define F_VFIP6TWOTUPEN    V_VFIP6TWOTUPEN(1U)
31652 
31653 #define S_VFIP4FOURTUPEN    5
31654 #define V_VFIP4FOURTUPEN(x) ((x) << S_VFIP4FOURTUPEN)
31655 #define F_VFIP4FOURTUPEN    V_VFIP4FOURTUPEN(1U)
31656 
31657 #define S_VFIP4TWOTUPEN    4
31658 #define V_VFIP4TWOTUPEN(x) ((x) << S_VFIP4TWOTUPEN)
31659 #define F_VFIP4TWOTUPEN    V_VFIP4TWOTUPEN(1U)
31660 
31661 #define S_KEYINDEX    0
31662 #define M_KEYINDEX    0xfU
31663 #define V_KEYINDEX(x) ((x) << S_KEYINDEX)
31664 #define G_KEYINDEX(x) (((x) >> S_KEYINDEX) & M_KEYINDEX)
31665 
31666 #define S_ROUNDROBINEN    3
31667 #define V_ROUNDROBINEN(x) ((x) << S_ROUNDROBINEN)
31668 #define F_ROUNDROBINEN    V_ROUNDROBINEN(1U)
31669 
31670 #define A_TP_RSS_SECRET_KEY0 0x40
31671 #define A_TP_RSS_SECRET_KEY1 0x41
31672 #define A_TP_RSS_SECRET_KEY2 0x42
31673 #define A_TP_RSS_SECRET_KEY3 0x43
31674 #define A_TP_RSS_SECRET_KEY4 0x44
31675 #define A_TP_RSS_SECRET_KEY5 0x45
31676 #define A_TP_RSS_SECRET_KEY6 0x46
31677 #define A_TP_RSS_SECRET_KEY7 0x47
31678 #define A_TP_RSS_SECRET_KEY8 0x48
31679 #define A_TP_RSS_SECRET_KEY9 0x49
31680 #define A_TP_ETHER_TYPE_VL 0x50
31681 
31682 #define S_CQFCTYPE    16
31683 #define M_CQFCTYPE    0xffffU
31684 #define V_CQFCTYPE(x) ((x) << S_CQFCTYPE)
31685 #define G_CQFCTYPE(x) (((x) >> S_CQFCTYPE) & M_CQFCTYPE)
31686 
31687 #define S_VLANTYPE    0
31688 #define M_VLANTYPE    0xffffU
31689 #define V_VLANTYPE(x) ((x) << S_VLANTYPE)
31690 #define G_VLANTYPE(x) (((x) >> S_VLANTYPE) & M_VLANTYPE)
31691 
31692 #define A_TP_ETHER_TYPE_IP 0x51
31693 
31694 #define S_IPV6TYPE    16
31695 #define M_IPV6TYPE    0xffffU
31696 #define V_IPV6TYPE(x) ((x) << S_IPV6TYPE)
31697 #define G_IPV6TYPE(x) (((x) >> S_IPV6TYPE) & M_IPV6TYPE)
31698 
31699 #define S_IPV4TYPE    0
31700 #define M_IPV4TYPE    0xffffU
31701 #define V_IPV4TYPE(x) ((x) << S_IPV4TYPE)
31702 #define G_IPV4TYPE(x) (((x) >> S_IPV4TYPE) & M_IPV4TYPE)
31703 
31704 #define A_TP_ETHER_TYPE_FW 0x52
31705 
31706 #define S_ETHTYPE1    16
31707 #define M_ETHTYPE1    0xffffU
31708 #define V_ETHTYPE1(x) ((x) << S_ETHTYPE1)
31709 #define G_ETHTYPE1(x) (((x) >> S_ETHTYPE1) & M_ETHTYPE1)
31710 
31711 #define S_ETHTYPE0    0
31712 #define M_ETHTYPE0    0xffffU
31713 #define V_ETHTYPE0(x) ((x) << S_ETHTYPE0)
31714 #define G_ETHTYPE0(x) (((x) >> S_ETHTYPE0) & M_ETHTYPE0)
31715 
31716 #define A_TP_VXLAN_HEADER 0x53
31717 
31718 #define S_VXLANPORT    0
31719 #define M_VXLANPORT    0xffffU
31720 #define V_VXLANPORT(x) ((x) << S_VXLANPORT)
31721 #define G_VXLANPORT(x) (((x) >> S_VXLANPORT) & M_VXLANPORT)
31722 
31723 #define A_TP_CORE_POWER 0x54
31724 
31725 #define S_SLEEPRDYVNT    12
31726 #define V_SLEEPRDYVNT(x) ((x) << S_SLEEPRDYVNT)
31727 #define F_SLEEPRDYVNT    V_SLEEPRDYVNT(1U)
31728 
31729 #define S_SLEEPRDYTBL    11
31730 #define V_SLEEPRDYTBL(x) ((x) << S_SLEEPRDYTBL)
31731 #define F_SLEEPRDYTBL    V_SLEEPRDYTBL(1U)
31732 
31733 #define S_SLEEPRDYMIB    10
31734 #define V_SLEEPRDYMIB(x) ((x) << S_SLEEPRDYMIB)
31735 #define F_SLEEPRDYMIB    V_SLEEPRDYMIB(1U)
31736 
31737 #define S_SLEEPRDYARP    9
31738 #define V_SLEEPRDYARP(x) ((x) << S_SLEEPRDYARP)
31739 #define F_SLEEPRDYARP    V_SLEEPRDYARP(1U)
31740 
31741 #define S_SLEEPRDYRSS    8
31742 #define V_SLEEPRDYRSS(x) ((x) << S_SLEEPRDYRSS)
31743 #define F_SLEEPRDYRSS    V_SLEEPRDYRSS(1U)
31744 
31745 #define S_SLEEPREQVNT    4
31746 #define V_SLEEPREQVNT(x) ((x) << S_SLEEPREQVNT)
31747 #define F_SLEEPREQVNT    V_SLEEPREQVNT(1U)
31748 
31749 #define S_SLEEPREQTBL    3
31750 #define V_SLEEPREQTBL(x) ((x) << S_SLEEPREQTBL)
31751 #define F_SLEEPREQTBL    V_SLEEPREQTBL(1U)
31752 
31753 #define S_SLEEPREQMIB    2
31754 #define V_SLEEPREQMIB(x) ((x) << S_SLEEPREQMIB)
31755 #define F_SLEEPREQMIB    V_SLEEPREQMIB(1U)
31756 
31757 #define S_SLEEPREQARP    1
31758 #define V_SLEEPREQARP(x) ((x) << S_SLEEPREQARP)
31759 #define F_SLEEPREQARP    V_SLEEPREQARP(1U)
31760 
31761 #define S_SLEEPREQRSS    0
31762 #define V_SLEEPREQRSS(x) ((x) << S_SLEEPREQRSS)
31763 #define F_SLEEPREQRSS    V_SLEEPREQRSS(1U)
31764 
31765 #define A_TP_CORE_RDMA 0x55
31766 
31767 #define S_IMMEDIATEOP    20
31768 #define M_IMMEDIATEOP    0xfU
31769 #define V_IMMEDIATEOP(x) ((x) << S_IMMEDIATEOP)
31770 #define G_IMMEDIATEOP(x) (((x) >> S_IMMEDIATEOP) & M_IMMEDIATEOP)
31771 
31772 #define S_IMMEDIATESE    16
31773 #define M_IMMEDIATESE    0xfU
31774 #define V_IMMEDIATESE(x) ((x) << S_IMMEDIATESE)
31775 #define G_IMMEDIATESE(x) (((x) >> S_IMMEDIATESE) & M_IMMEDIATESE)
31776 
31777 #define S_ATOMICREQOP    12
31778 #define M_ATOMICREQOP    0xfU
31779 #define V_ATOMICREQOP(x) ((x) << S_ATOMICREQOP)
31780 #define G_ATOMICREQOP(x) (((x) >> S_ATOMICREQOP) & M_ATOMICREQOP)
31781 
31782 #define S_ATOMICRSPOP    8
31783 #define M_ATOMICRSPOP    0xfU
31784 #define V_ATOMICRSPOP(x) ((x) << S_ATOMICRSPOP)
31785 #define G_ATOMICRSPOP(x) (((x) >> S_ATOMICRSPOP) & M_ATOMICRSPOP)
31786 
31787 #define S_IMMEDIASEEN    1
31788 #define V_IMMEDIASEEN(x) ((x) << S_IMMEDIASEEN)
31789 #define F_IMMEDIASEEN    V_IMMEDIASEEN(1U)
31790 
31791 #define S_IMMEDIATEEN    0
31792 #define V_IMMEDIATEEN(x) ((x) << S_IMMEDIATEEN)
31793 #define F_IMMEDIATEEN    V_IMMEDIATEEN(1U)
31794 
31795 #define S_SHAREDRQEN    31
31796 #define V_SHAREDRQEN(x) ((x) << S_SHAREDRQEN)
31797 #define F_SHAREDRQEN    V_SHAREDRQEN(1U)
31798 
31799 #define S_SHAREDXRC    30
31800 #define V_SHAREDXRC(x) ((x) << S_SHAREDXRC)
31801 #define F_SHAREDXRC    V_SHAREDXRC(1U)
31802 
31803 #define S_VERIFYRSPOP    25
31804 #define M_VERIFYRSPOP    0x1fU
31805 #define V_VERIFYRSPOP(x) ((x) << S_VERIFYRSPOP)
31806 #define G_VERIFYRSPOP(x) (((x) >> S_VERIFYRSPOP) & M_VERIFYRSPOP)
31807 
31808 #define S_VERIFYREQOP    20
31809 #define M_VERIFYREQOP    0x1fU
31810 #define V_VERIFYREQOP(x) ((x) << S_VERIFYREQOP)
31811 #define G_VERIFYREQOP(x) (((x) >> S_VERIFYREQOP) & M_VERIFYREQOP)
31812 
31813 #define S_AWRITERSPOP    15
31814 #define M_AWRITERSPOP    0x1fU
31815 #define V_AWRITERSPOP(x) ((x) << S_AWRITERSPOP)
31816 #define G_AWRITERSPOP(x) (((x) >> S_AWRITERSPOP) & M_AWRITERSPOP)
31817 
31818 #define S_AWRITEREQOP    10
31819 #define M_AWRITEREQOP    0x1fU
31820 #define V_AWRITEREQOP(x) ((x) << S_AWRITEREQOP)
31821 #define G_AWRITEREQOP(x) (((x) >> S_AWRITEREQOP) & M_AWRITEREQOP)
31822 
31823 #define S_FLUSHRSPOP    5
31824 #define M_FLUSHRSPOP    0x1fU
31825 #define V_FLUSHRSPOP(x) ((x) << S_FLUSHRSPOP)
31826 #define G_FLUSHRSPOP(x) (((x) >> S_FLUSHRSPOP) & M_FLUSHRSPOP)
31827 
31828 #define S_FLUSHREQOP    0
31829 #define M_FLUSHREQOP    0x1fU
31830 #define V_FLUSHREQOP(x) ((x) << S_FLUSHREQOP)
31831 #define G_FLUSHREQOP(x) (((x) >> S_FLUSHREQOP) & M_FLUSHREQOP)
31832 
31833 #define A_TP_FRAG_CONFIG 0x56
31834 
31835 #define S_TLSMODE    16
31836 #define M_TLSMODE    0x3U
31837 #define V_TLSMODE(x) ((x) << S_TLSMODE)
31838 #define G_TLSMODE(x) (((x) >> S_TLSMODE) & M_TLSMODE)
31839 
31840 #define S_USERMODE    14
31841 #define M_USERMODE    0x3U
31842 #define V_USERMODE(x) ((x) << S_USERMODE)
31843 #define G_USERMODE(x) (((x) >> S_USERMODE) & M_USERMODE)
31844 
31845 #define S_FCOEMODE    12
31846 #define M_FCOEMODE    0x3U
31847 #define V_FCOEMODE(x) ((x) << S_FCOEMODE)
31848 #define G_FCOEMODE(x) (((x) >> S_FCOEMODE) & M_FCOEMODE)
31849 
31850 #define S_IANDPMODE    10
31851 #define M_IANDPMODE    0x3U
31852 #define V_IANDPMODE(x) ((x) << S_IANDPMODE)
31853 #define G_IANDPMODE(x) (((x) >> S_IANDPMODE) & M_IANDPMODE)
31854 
31855 #define S_RDDPMODE    8
31856 #define M_RDDPMODE    0x3U
31857 #define V_RDDPMODE(x) ((x) << S_RDDPMODE)
31858 #define G_RDDPMODE(x) (((x) >> S_RDDPMODE) & M_RDDPMODE)
31859 
31860 #define S_IWARPMODE    6
31861 #define M_IWARPMODE    0x3U
31862 #define V_IWARPMODE(x) ((x) << S_IWARPMODE)
31863 #define G_IWARPMODE(x) (((x) >> S_IWARPMODE) & M_IWARPMODE)
31864 
31865 #define S_ISCSIMODE    4
31866 #define M_ISCSIMODE    0x3U
31867 #define V_ISCSIMODE(x) ((x) << S_ISCSIMODE)
31868 #define G_ISCSIMODE(x) (((x) >> S_ISCSIMODE) & M_ISCSIMODE)
31869 
31870 #define S_DDPMODE    2
31871 #define M_DDPMODE    0x3U
31872 #define V_DDPMODE(x) ((x) << S_DDPMODE)
31873 #define G_DDPMODE(x) (((x) >> S_DDPMODE) & M_DDPMODE)
31874 
31875 #define S_PASSMODE    0
31876 #define M_PASSMODE    0x3U
31877 #define V_PASSMODE(x) ((x) << S_PASSMODE)
31878 #define G_PASSMODE(x) (((x) >> S_PASSMODE) & M_PASSMODE)
31879 
31880 #define S_NVMTMODE    22
31881 #define M_NVMTMODE    0x3U
31882 #define V_NVMTMODE(x) ((x) << S_NVMTMODE)
31883 #define G_NVMTMODE(x) (((x) >> S_NVMTMODE) & M_NVMTMODE)
31884 
31885 #define S_ROCEMODE    20
31886 #define M_ROCEMODE    0x3U
31887 #define V_ROCEMODE(x) ((x) << S_ROCEMODE)
31888 #define G_ROCEMODE(x) (((x) >> S_ROCEMODE) & M_ROCEMODE)
31889 
31890 #define S_DTLSMODE    18
31891 #define M_DTLSMODE    0x3U
31892 #define V_DTLSMODE(x) ((x) << S_DTLSMODE)
31893 #define G_DTLSMODE(x) (((x) >> S_DTLSMODE) & M_DTLSMODE)
31894 
31895 #define A_TP_CMM_CONFIG 0x57
31896 
31897 #define S_WRCNTIDLE    16
31898 #define M_WRCNTIDLE    0xffffU
31899 #define V_WRCNTIDLE(x) ((x) << S_WRCNTIDLE)
31900 #define G_WRCNTIDLE(x) (((x) >> S_WRCNTIDLE) & M_WRCNTIDLE)
31901 
31902 #define S_RDTHRESHOLD    8
31903 #define M_RDTHRESHOLD    0x3fU
31904 #define V_RDTHRESHOLD(x) ((x) << S_RDTHRESHOLD)
31905 #define G_RDTHRESHOLD(x) (((x) >> S_RDTHRESHOLD) & M_RDTHRESHOLD)
31906 
31907 #define S_WRTHRLEVEL2    7
31908 #define V_WRTHRLEVEL2(x) ((x) << S_WRTHRLEVEL2)
31909 #define F_WRTHRLEVEL2    V_WRTHRLEVEL2(1U)
31910 
31911 #define S_WRTHRLEVEL1    6
31912 #define V_WRTHRLEVEL1(x) ((x) << S_WRTHRLEVEL1)
31913 #define F_WRTHRLEVEL1    V_WRTHRLEVEL1(1U)
31914 
31915 #define S_WRTHRTHRESHEN    5
31916 #define V_WRTHRTHRESHEN(x) ((x) << S_WRTHRTHRESHEN)
31917 #define F_WRTHRTHRESHEN    V_WRTHRTHRESHEN(1U)
31918 
31919 #define S_WRTHRTHRESH    0
31920 #define M_WRTHRTHRESH    0x1fU
31921 #define V_WRTHRTHRESH(x) ((x) << S_WRTHRTHRESH)
31922 #define G_WRTHRTHRESH(x) (((x) >> S_WRTHRTHRESH) & M_WRTHRTHRESH)
31923 
31924 #define A_TP_VXLAN_CONFIG 0x58
31925 
31926 #define S_VXLANFLAGS    16
31927 #define M_VXLANFLAGS    0xffffU
31928 #define V_VXLANFLAGS(x) ((x) << S_VXLANFLAGS)
31929 #define G_VXLANFLAGS(x) (((x) >> S_VXLANFLAGS) & M_VXLANFLAGS)
31930 
31931 #define S_VXLANTYPE    0
31932 #define M_VXLANTYPE    0xffffU
31933 #define V_VXLANTYPE(x) ((x) << S_VXLANTYPE)
31934 #define G_VXLANTYPE(x) (((x) >> S_VXLANTYPE) & M_VXLANTYPE)
31935 
31936 #define A_TP_NVGRE_CONFIG 0x59
31937 
31938 #define S_GREFLAGS    16
31939 #define M_GREFLAGS    0xffffU
31940 #define V_GREFLAGS(x) ((x) << S_GREFLAGS)
31941 #define G_GREFLAGS(x) (((x) >> S_GREFLAGS) & M_GREFLAGS)
31942 
31943 #define S_GRETYPE    0
31944 #define M_GRETYPE    0xffffU
31945 #define V_GRETYPE(x) ((x) << S_GRETYPE)
31946 #define G_GRETYPE(x) (((x) >> S_GRETYPE) & M_GRETYPE)
31947 
31948 #define A_TP_MMGR_CMM_CONFIG 0x5a
31949 #define A_TP_DBG_CLEAR 0x60
31950 #define A_TP_DBG_CORE_HDR0 0x61
31951 
31952 #define S_E_TCP_OP_SRDY    16
31953 #define V_E_TCP_OP_SRDY(x) ((x) << S_E_TCP_OP_SRDY)
31954 #define F_E_TCP_OP_SRDY    V_E_TCP_OP_SRDY(1U)
31955 
31956 #define S_E_PLD_TXZEROP_SRDY    15
31957 #define V_E_PLD_TXZEROP_SRDY(x) ((x) << S_E_PLD_TXZEROP_SRDY)
31958 #define F_E_PLD_TXZEROP_SRDY    V_E_PLD_TXZEROP_SRDY(1U)
31959 
31960 #define S_E_PLD_RX_SRDY    14
31961 #define V_E_PLD_RX_SRDY(x) ((x) << S_E_PLD_RX_SRDY)
31962 #define F_E_PLD_RX_SRDY    V_E_PLD_RX_SRDY(1U)
31963 
31964 #define S_E_RX_ERROR_SRDY    13
31965 #define V_E_RX_ERROR_SRDY(x) ((x) << S_E_RX_ERROR_SRDY)
31966 #define F_E_RX_ERROR_SRDY    V_E_RX_ERROR_SRDY(1U)
31967 
31968 #define S_E_RX_ISS_SRDY    12
31969 #define V_E_RX_ISS_SRDY(x) ((x) << S_E_RX_ISS_SRDY)
31970 #define F_E_RX_ISS_SRDY    V_E_RX_ISS_SRDY(1U)
31971 
31972 #define S_C_TCP_OP_SRDY    11
31973 #define V_C_TCP_OP_SRDY(x) ((x) << S_C_TCP_OP_SRDY)
31974 #define F_C_TCP_OP_SRDY    V_C_TCP_OP_SRDY(1U)
31975 
31976 #define S_C_PLD_TXZEROP_SRDY    10
31977 #define V_C_PLD_TXZEROP_SRDY(x) ((x) << S_C_PLD_TXZEROP_SRDY)
31978 #define F_C_PLD_TXZEROP_SRDY    V_C_PLD_TXZEROP_SRDY(1U)
31979 
31980 #define S_C_PLD_RX_SRDY    9
31981 #define V_C_PLD_RX_SRDY(x) ((x) << S_C_PLD_RX_SRDY)
31982 #define F_C_PLD_RX_SRDY    V_C_PLD_RX_SRDY(1U)
31983 
31984 #define S_C_RX_ERROR_SRDY    8
31985 #define V_C_RX_ERROR_SRDY(x) ((x) << S_C_RX_ERROR_SRDY)
31986 #define F_C_RX_ERROR_SRDY    V_C_RX_ERROR_SRDY(1U)
31987 
31988 #define S_C_RX_ISS_SRDY    7
31989 #define V_C_RX_ISS_SRDY(x) ((x) << S_C_RX_ISS_SRDY)
31990 #define F_C_RX_ISS_SRDY    V_C_RX_ISS_SRDY(1U)
31991 
31992 #define S_E_CPL5_TXVALID    6
31993 #define V_E_CPL5_TXVALID(x) ((x) << S_E_CPL5_TXVALID)
31994 #define F_E_CPL5_TXVALID    V_E_CPL5_TXVALID(1U)
31995 
31996 #define S_E_ETH_TXVALID    5
31997 #define V_E_ETH_TXVALID(x) ((x) << S_E_ETH_TXVALID)
31998 #define F_E_ETH_TXVALID    V_E_ETH_TXVALID(1U)
31999 
32000 #define S_E_IP_TXVALID    4
32001 #define V_E_IP_TXVALID(x) ((x) << S_E_IP_TXVALID)
32002 #define F_E_IP_TXVALID    V_E_IP_TXVALID(1U)
32003 
32004 #define S_E_TCP_TXVALID    3
32005 #define V_E_TCP_TXVALID(x) ((x) << S_E_TCP_TXVALID)
32006 #define F_E_TCP_TXVALID    V_E_TCP_TXVALID(1U)
32007 
32008 #define S_C_CPL5_RXVALID    2
32009 #define V_C_CPL5_RXVALID(x) ((x) << S_C_CPL5_RXVALID)
32010 #define F_C_CPL5_RXVALID    V_C_CPL5_RXVALID(1U)
32011 
32012 #define S_C_CPL5_TXVALID    1
32013 #define V_C_CPL5_TXVALID(x) ((x) << S_C_CPL5_TXVALID)
32014 #define F_C_CPL5_TXVALID    V_C_CPL5_TXVALID(1U)
32015 
32016 #define S_E_TCP_OPT_RXVALID    0
32017 #define V_E_TCP_OPT_RXVALID(x) ((x) << S_E_TCP_OPT_RXVALID)
32018 #define F_E_TCP_OPT_RXVALID    V_E_TCP_OPT_RXVALID(1U)
32019 
32020 #define A_TP_DBG_CORE_HDR1 0x62
32021 
32022 #define S_E_CPL5_TXFULL    6
32023 #define V_E_CPL5_TXFULL(x) ((x) << S_E_CPL5_TXFULL)
32024 #define F_E_CPL5_TXFULL    V_E_CPL5_TXFULL(1U)
32025 
32026 #define S_E_ETH_TXFULL    5
32027 #define V_E_ETH_TXFULL(x) ((x) << S_E_ETH_TXFULL)
32028 #define F_E_ETH_TXFULL    V_E_ETH_TXFULL(1U)
32029 
32030 #define S_E_IP_TXFULL    4
32031 #define V_E_IP_TXFULL(x) ((x) << S_E_IP_TXFULL)
32032 #define F_E_IP_TXFULL    V_E_IP_TXFULL(1U)
32033 
32034 #define S_E_TCP_TXFULL    3
32035 #define V_E_TCP_TXFULL(x) ((x) << S_E_TCP_TXFULL)
32036 #define F_E_TCP_TXFULL    V_E_TCP_TXFULL(1U)
32037 
32038 #define S_C_CPL5_RXFULL    2
32039 #define V_C_CPL5_RXFULL(x) ((x) << S_C_CPL5_RXFULL)
32040 #define F_C_CPL5_RXFULL    V_C_CPL5_RXFULL(1U)
32041 
32042 #define S_C_CPL5_TXFULL    1
32043 #define V_C_CPL5_TXFULL(x) ((x) << S_C_CPL5_TXFULL)
32044 #define F_C_CPL5_TXFULL    V_C_CPL5_TXFULL(1U)
32045 
32046 #define S_E_TCP_OPT_RXFULL    0
32047 #define V_E_TCP_OPT_RXFULL(x) ((x) << S_E_TCP_OPT_RXFULL)
32048 #define F_E_TCP_OPT_RXFULL    V_E_TCP_OPT_RXFULL(1U)
32049 
32050 #define A_TP_DBG_CORE_FATAL 0x63
32051 
32052 #define S_EMSGFATAL    31
32053 #define V_EMSGFATAL(x) ((x) << S_EMSGFATAL)
32054 #define F_EMSGFATAL    V_EMSGFATAL(1U)
32055 
32056 #define S_CMSGFATAL    30
32057 #define V_CMSGFATAL(x) ((x) << S_CMSGFATAL)
32058 #define F_CMSGFATAL    V_CMSGFATAL(1U)
32059 
32060 #define S_PAWSFATAL    29
32061 #define V_PAWSFATAL(x) ((x) << S_PAWSFATAL)
32062 #define F_PAWSFATAL    V_PAWSFATAL(1U)
32063 
32064 #define S_SRAMFATAL    28
32065 #define V_SRAMFATAL(x) ((x) << S_SRAMFATAL)
32066 #define F_SRAMFATAL    V_SRAMFATAL(1U)
32067 
32068 #define S_CPCMDCONG    24
32069 #define M_CPCMDCONG    0xfU
32070 #define V_CPCMDCONG(x) ((x) << S_CPCMDCONG)
32071 #define G_CPCMDCONG(x) (((x) >> S_CPCMDCONG) & M_CPCMDCONG)
32072 
32073 #define S_EPCMDCONG    22
32074 #define M_EPCMDCONG    0x3U
32075 #define V_EPCMDCONG(x) ((x) << S_EPCMDCONG)
32076 #define G_EPCMDCONG(x) (((x) >> S_EPCMDCONG) & M_EPCMDCONG)
32077 
32078 #define S_CPCMDLENFATAL    21
32079 #define V_CPCMDLENFATAL(x) ((x) << S_CPCMDLENFATAL)
32080 #define F_CPCMDLENFATAL    V_CPCMDLENFATAL(1U)
32081 
32082 #define S_EPCMDLENFATAL    20
32083 #define V_EPCMDLENFATAL(x) ((x) << S_EPCMDLENFATAL)
32084 #define F_EPCMDLENFATAL    V_EPCMDLENFATAL(1U)
32085 
32086 #define S_CPCMDVALID    16
32087 #define M_CPCMDVALID    0xfU
32088 #define V_CPCMDVALID(x) ((x) << S_CPCMDVALID)
32089 #define G_CPCMDVALID(x) (((x) >> S_CPCMDVALID) & M_CPCMDVALID)
32090 
32091 #define S_CPCMDAFULL    12
32092 #define M_CPCMDAFULL    0xfU
32093 #define V_CPCMDAFULL(x) ((x) << S_CPCMDAFULL)
32094 #define G_CPCMDAFULL(x) (((x) >> S_CPCMDAFULL) & M_CPCMDAFULL)
32095 
32096 #define S_EPCMDVALID    10
32097 #define M_EPCMDVALID    0x3U
32098 #define V_EPCMDVALID(x) ((x) << S_EPCMDVALID)
32099 #define G_EPCMDVALID(x) (((x) >> S_EPCMDVALID) & M_EPCMDVALID)
32100 
32101 #define S_EPCMDAFULL    8
32102 #define M_EPCMDAFULL    0x3U
32103 #define V_EPCMDAFULL(x) ((x) << S_EPCMDAFULL)
32104 #define G_EPCMDAFULL(x) (((x) >> S_EPCMDAFULL) & M_EPCMDAFULL)
32105 
32106 #define S_CPCMDEOIFATAL    7
32107 #define V_CPCMDEOIFATAL(x) ((x) << S_CPCMDEOIFATAL)
32108 #define F_CPCMDEOIFATAL    V_CPCMDEOIFATAL(1U)
32109 
32110 #define S_CMDBRQFATAL    4
32111 #define V_CMDBRQFATAL(x) ((x) << S_CMDBRQFATAL)
32112 #define F_CMDBRQFATAL    V_CMDBRQFATAL(1U)
32113 
32114 #define S_CNONZEROPPOPCNT    2
32115 #define M_CNONZEROPPOPCNT    0x3U
32116 #define V_CNONZEROPPOPCNT(x) ((x) << S_CNONZEROPPOPCNT)
32117 #define G_CNONZEROPPOPCNT(x) (((x) >> S_CNONZEROPPOPCNT) & M_CNONZEROPPOPCNT)
32118 
32119 #define S_CPCMDEOICNT    0
32120 #define M_CPCMDEOICNT    0x3U
32121 #define V_CPCMDEOICNT(x) ((x) << S_CPCMDEOICNT)
32122 #define G_CPCMDEOICNT(x) (((x) >> S_CPCMDEOICNT) & M_CPCMDEOICNT)
32123 
32124 #define S_CPCMDTTLFATAL    6
32125 #define V_CPCMDTTLFATAL(x) ((x) << S_CPCMDTTLFATAL)
32126 #define F_CPCMDTTLFATAL    V_CPCMDTTLFATAL(1U)
32127 
32128 #define S_CDATACHNFATAL    5
32129 #define V_CDATACHNFATAL(x) ((x) << S_CDATACHNFATAL)
32130 #define F_CDATACHNFATAL    V_CDATACHNFATAL(1U)
32131 
32132 #define A_TP_DBG_CORE_OUT 0x64
32133 
32134 #define S_CCPLENC    26
32135 #define V_CCPLENC(x) ((x) << S_CCPLENC)
32136 #define F_CCPLENC    V_CCPLENC(1U)
32137 
32138 #define S_CWRCPLPKT    25
32139 #define V_CWRCPLPKT(x) ((x) << S_CWRCPLPKT)
32140 #define F_CWRCPLPKT    V_CWRCPLPKT(1U)
32141 
32142 #define S_CWRETHPKT    24
32143 #define V_CWRETHPKT(x) ((x) << S_CWRETHPKT)
32144 #define F_CWRETHPKT    V_CWRETHPKT(1U)
32145 
32146 #define S_CWRIPPKT    23
32147 #define V_CWRIPPKT(x) ((x) << S_CWRIPPKT)
32148 #define F_CWRIPPKT    V_CWRIPPKT(1U)
32149 
32150 #define S_CWRTCPPKT    22
32151 #define V_CWRTCPPKT(x) ((x) << S_CWRTCPPKT)
32152 #define F_CWRTCPPKT    V_CWRTCPPKT(1U)
32153 
32154 #define S_CWRZEROP    21
32155 #define V_CWRZEROP(x) ((x) << S_CWRZEROP)
32156 #define F_CWRZEROP    V_CWRZEROP(1U)
32157 
32158 #define S_CCPLTXFULL    20
32159 #define V_CCPLTXFULL(x) ((x) << S_CCPLTXFULL)
32160 #define F_CCPLTXFULL    V_CCPLTXFULL(1U)
32161 
32162 #define S_CETHTXFULL    19
32163 #define V_CETHTXFULL(x) ((x) << S_CETHTXFULL)
32164 #define F_CETHTXFULL    V_CETHTXFULL(1U)
32165 
32166 #define S_CIPTXFULL    18
32167 #define V_CIPTXFULL(x) ((x) << S_CIPTXFULL)
32168 #define F_CIPTXFULL    V_CIPTXFULL(1U)
32169 
32170 #define S_CTCPTXFULL    17
32171 #define V_CTCPTXFULL(x) ((x) << S_CTCPTXFULL)
32172 #define F_CTCPTXFULL    V_CTCPTXFULL(1U)
32173 
32174 #define S_CPLDTXZEROPDRDY    16
32175 #define V_CPLDTXZEROPDRDY(x) ((x) << S_CPLDTXZEROPDRDY)
32176 #define F_CPLDTXZEROPDRDY    V_CPLDTXZEROPDRDY(1U)
32177 
32178 #define S_ECPLENC    10
32179 #define V_ECPLENC(x) ((x) << S_ECPLENC)
32180 #define F_ECPLENC    V_ECPLENC(1U)
32181 
32182 #define S_EWRCPLPKT    9
32183 #define V_EWRCPLPKT(x) ((x) << S_EWRCPLPKT)
32184 #define F_EWRCPLPKT    V_EWRCPLPKT(1U)
32185 
32186 #define S_EWRETHPKT    8
32187 #define V_EWRETHPKT(x) ((x) << S_EWRETHPKT)
32188 #define F_EWRETHPKT    V_EWRETHPKT(1U)
32189 
32190 #define S_EWRIPPKT    7
32191 #define V_EWRIPPKT(x) ((x) << S_EWRIPPKT)
32192 #define F_EWRIPPKT    V_EWRIPPKT(1U)
32193 
32194 #define S_EWRTCPPKT    6
32195 #define V_EWRTCPPKT(x) ((x) << S_EWRTCPPKT)
32196 #define F_EWRTCPPKT    V_EWRTCPPKT(1U)
32197 
32198 #define S_EWRZEROP    5
32199 #define V_EWRZEROP(x) ((x) << S_EWRZEROP)
32200 #define F_EWRZEROP    V_EWRZEROP(1U)
32201 
32202 #define S_ECPLTXFULL    4
32203 #define V_ECPLTXFULL(x) ((x) << S_ECPLTXFULL)
32204 #define F_ECPLTXFULL    V_ECPLTXFULL(1U)
32205 
32206 #define S_EETHTXFULL    3
32207 #define V_EETHTXFULL(x) ((x) << S_EETHTXFULL)
32208 #define F_EETHTXFULL    V_EETHTXFULL(1U)
32209 
32210 #define S_EIPTXFULL    2
32211 #define V_EIPTXFULL(x) ((x) << S_EIPTXFULL)
32212 #define F_EIPTXFULL    V_EIPTXFULL(1U)
32213 
32214 #define S_ETCPTXFULL    1
32215 #define V_ETCPTXFULL(x) ((x) << S_ETCPTXFULL)
32216 #define F_ETCPTXFULL    V_ETCPTXFULL(1U)
32217 
32218 #define S_EPLDTXZEROPDRDY    0
32219 #define V_EPLDTXZEROPDRDY(x) ((x) << S_EPLDTXZEROPDRDY)
32220 #define F_EPLDTXZEROPDRDY    V_EPLDTXZEROPDRDY(1U)
32221 
32222 #define S_CRXBUSYOUT    31
32223 #define V_CRXBUSYOUT(x) ((x) << S_CRXBUSYOUT)
32224 #define F_CRXBUSYOUT    V_CRXBUSYOUT(1U)
32225 
32226 #define S_CTXBUSYOUT    30
32227 #define V_CTXBUSYOUT(x) ((x) << S_CTXBUSYOUT)
32228 #define F_CTXBUSYOUT    V_CTXBUSYOUT(1U)
32229 
32230 #define S_CRDCPLPKT    29
32231 #define V_CRDCPLPKT(x) ((x) << S_CRDCPLPKT)
32232 #define F_CRDCPLPKT    V_CRDCPLPKT(1U)
32233 
32234 #define S_CRDTCPPKT    28
32235 #define V_CRDTCPPKT(x) ((x) << S_CRDTCPPKT)
32236 #define F_CRDTCPPKT    V_CRDTCPPKT(1U)
32237 
32238 #define S_CNEWMSG    27
32239 #define V_CNEWMSG(x) ((x) << S_CNEWMSG)
32240 #define F_CNEWMSG    V_CNEWMSG(1U)
32241 
32242 #define S_ERXBUSYOUT    15
32243 #define V_ERXBUSYOUT(x) ((x) << S_ERXBUSYOUT)
32244 #define F_ERXBUSYOUT    V_ERXBUSYOUT(1U)
32245 
32246 #define S_ETXBUSYOUT    14
32247 #define V_ETXBUSYOUT(x) ((x) << S_ETXBUSYOUT)
32248 #define F_ETXBUSYOUT    V_ETXBUSYOUT(1U)
32249 
32250 #define S_ERDCPLPKT    13
32251 #define V_ERDCPLPKT(x) ((x) << S_ERDCPLPKT)
32252 #define F_ERDCPLPKT    V_ERDCPLPKT(1U)
32253 
32254 #define S_ERDTCPPKT    12
32255 #define V_ERDTCPPKT(x) ((x) << S_ERDTCPPKT)
32256 #define F_ERDTCPPKT    V_ERDTCPPKT(1U)
32257 
32258 #define S_ENEWMSG    11
32259 #define V_ENEWMSG(x) ((x) << S_ENEWMSG)
32260 #define F_ENEWMSG    V_ENEWMSG(1U)
32261 
32262 #define A_TP_DBG_CORE_TID 0x65
32263 
32264 #define S_LINENUMBER    24
32265 #define M_LINENUMBER    0x7fU
32266 #define V_LINENUMBER(x) ((x) << S_LINENUMBER)
32267 #define G_LINENUMBER(x) (((x) >> S_LINENUMBER) & M_LINENUMBER)
32268 
32269 #define S_SPURIOUSMSG    23
32270 #define V_SPURIOUSMSG(x) ((x) << S_SPURIOUSMSG)
32271 #define F_SPURIOUSMSG    V_SPURIOUSMSG(1U)
32272 
32273 #define S_SYNLEARNED    20
32274 #define V_SYNLEARNED(x) ((x) << S_SYNLEARNED)
32275 #define F_SYNLEARNED    V_SYNLEARNED(1U)
32276 
32277 #define S_TIDVALUE    0
32278 #define M_TIDVALUE    0xfffffU
32279 #define V_TIDVALUE(x) ((x) << S_TIDVALUE)
32280 #define G_TIDVALUE(x) (((x) >> S_TIDVALUE) & M_TIDVALUE)
32281 
32282 #define S_SRC    21
32283 #define M_SRC    0x3U
32284 #define V_SRC(x) ((x) << S_SRC)
32285 #define G_SRC(x) (((x) >> S_SRC) & M_SRC)
32286 
32287 #define A_TP_DBG_ENG_RES0 0x66
32288 
32289 #define S_RESOURCESREADY    31
32290 #define V_RESOURCESREADY(x) ((x) << S_RESOURCESREADY)
32291 #define F_RESOURCESREADY    V_RESOURCESREADY(1U)
32292 
32293 #define S_RCFOPCODEOUTSRDY    30
32294 #define V_RCFOPCODEOUTSRDY(x) ((x) << S_RCFOPCODEOUTSRDY)
32295 #define F_RCFOPCODEOUTSRDY    V_RCFOPCODEOUTSRDY(1U)
32296 
32297 #define S_RCFDATAOUTSRDY    29
32298 #define V_RCFDATAOUTSRDY(x) ((x) << S_RCFDATAOUTSRDY)
32299 #define F_RCFDATAOUTSRDY    V_RCFDATAOUTSRDY(1U)
32300 
32301 #define S_FLUSHINPUTMSG    28
32302 #define V_FLUSHINPUTMSG(x) ((x) << S_FLUSHINPUTMSG)
32303 #define F_FLUSHINPUTMSG    V_FLUSHINPUTMSG(1U)
32304 
32305 #define S_RCFOPSRCOUT    26
32306 #define M_RCFOPSRCOUT    0x3U
32307 #define V_RCFOPSRCOUT(x) ((x) << S_RCFOPSRCOUT)
32308 #define G_RCFOPSRCOUT(x) (((x) >> S_RCFOPSRCOUT) & M_RCFOPSRCOUT)
32309 
32310 #define S_C_MSG    25
32311 #define V_C_MSG(x) ((x) << S_C_MSG)
32312 #define F_C_MSG    V_C_MSG(1U)
32313 
32314 #define S_E_MSG    24
32315 #define V_E_MSG(x) ((x) << S_E_MSG)
32316 #define F_E_MSG    V_E_MSG(1U)
32317 
32318 #define S_RCFOPCODEOUT    20
32319 #define M_RCFOPCODEOUT    0xfU
32320 #define V_RCFOPCODEOUT(x) ((x) << S_RCFOPCODEOUT)
32321 #define G_RCFOPCODEOUT(x) (((x) >> S_RCFOPCODEOUT) & M_RCFOPCODEOUT)
32322 
32323 #define S_EFFRCFOPCODEOUT    16
32324 #define M_EFFRCFOPCODEOUT    0xfU
32325 #define V_EFFRCFOPCODEOUT(x) ((x) << S_EFFRCFOPCODEOUT)
32326 #define G_EFFRCFOPCODEOUT(x) (((x) >> S_EFFRCFOPCODEOUT) & M_EFFRCFOPCODEOUT)
32327 
32328 #define S_SEENRESOURCESREADY    15
32329 #define V_SEENRESOURCESREADY(x) ((x) << S_SEENRESOURCESREADY)
32330 #define F_SEENRESOURCESREADY    V_SEENRESOURCESREADY(1U)
32331 
32332 #define S_RESOURCESREADYCOPY    14
32333 #define V_RESOURCESREADYCOPY(x) ((x) << S_RESOURCESREADYCOPY)
32334 #define F_RESOURCESREADYCOPY    V_RESOURCESREADYCOPY(1U)
32335 
32336 #define S_OPCODEWAITSFORDATA    13
32337 #define V_OPCODEWAITSFORDATA(x) ((x) << S_OPCODEWAITSFORDATA)
32338 #define F_OPCODEWAITSFORDATA    V_OPCODEWAITSFORDATA(1U)
32339 
32340 #define S_CPLDRXSRDY    12
32341 #define V_CPLDRXSRDY(x) ((x) << S_CPLDRXSRDY)
32342 #define F_CPLDRXSRDY    V_CPLDRXSRDY(1U)
32343 
32344 #define S_CPLDRXZEROPSRDY    11
32345 #define V_CPLDRXZEROPSRDY(x) ((x) << S_CPLDRXZEROPSRDY)
32346 #define F_CPLDRXZEROPSRDY    V_CPLDRXZEROPSRDY(1U)
32347 
32348 #define S_EPLDRXZEROPSRDY    10
32349 #define V_EPLDRXZEROPSRDY(x) ((x) << S_EPLDRXZEROPSRDY)
32350 #define F_EPLDRXZEROPSRDY    V_EPLDRXZEROPSRDY(1U)
32351 
32352 #define S_ERXERRORSRDY    9
32353 #define V_ERXERRORSRDY(x) ((x) << S_ERXERRORSRDY)
32354 #define F_ERXERRORSRDY    V_ERXERRORSRDY(1U)
32355 
32356 #define S_EPLDRXSRDY    8
32357 #define V_EPLDRXSRDY(x) ((x) << S_EPLDRXSRDY)
32358 #define F_EPLDRXSRDY    V_EPLDRXSRDY(1U)
32359 
32360 #define S_CRXBUSY    7
32361 #define V_CRXBUSY(x) ((x) << S_CRXBUSY)
32362 #define F_CRXBUSY    V_CRXBUSY(1U)
32363 
32364 #define S_ERXBUSY    6
32365 #define V_ERXBUSY(x) ((x) << S_ERXBUSY)
32366 #define F_ERXBUSY    V_ERXBUSY(1U)
32367 
32368 #define S_TIMERINSERTBUSY    5
32369 #define V_TIMERINSERTBUSY(x) ((x) << S_TIMERINSERTBUSY)
32370 #define F_TIMERINSERTBUSY    V_TIMERINSERTBUSY(1U)
32371 
32372 #define S_WCFBUSY    4
32373 #define V_WCFBUSY(x) ((x) << S_WCFBUSY)
32374 #define F_WCFBUSY    V_WCFBUSY(1U)
32375 
32376 #define S_CTXBUSY    3
32377 #define V_CTXBUSY(x) ((x) << S_CTXBUSY)
32378 #define F_CTXBUSY    V_CTXBUSY(1U)
32379 
32380 #define S_CPCMDBUSY    2
32381 #define V_CPCMDBUSY(x) ((x) << S_CPCMDBUSY)
32382 #define F_CPCMDBUSY    V_CPCMDBUSY(1U)
32383 
32384 #define S_EPCMDBUSY    1
32385 #define V_EPCMDBUSY(x) ((x) << S_EPCMDBUSY)
32386 #define F_EPCMDBUSY    V_EPCMDBUSY(1U)
32387 
32388 #define S_ETXBUSY    0
32389 #define V_ETXBUSY(x) ((x) << S_ETXBUSY)
32390 #define F_ETXBUSY    V_ETXBUSY(1U)
32391 
32392 #define S_EFFOPCODEOUT    16
32393 #define M_EFFOPCODEOUT    0xfU
32394 #define V_EFFOPCODEOUT(x) ((x) << S_EFFOPCODEOUT)
32395 #define G_EFFOPCODEOUT(x) (((x) >> S_EFFOPCODEOUT) & M_EFFOPCODEOUT)
32396 
32397 #define S_DELDRDY    14
32398 #define V_DELDRDY(x) ((x) << S_DELDRDY)
32399 #define F_DELDRDY    V_DELDRDY(1U)
32400 
32401 #define S_T5_ETXBUSY    1
32402 #define V_T5_ETXBUSY(x) ((x) << S_T5_ETXBUSY)
32403 #define F_T5_ETXBUSY    V_T5_ETXBUSY(1U)
32404 
32405 #define S_T5_EPCMDBUSY    0
32406 #define V_T5_EPCMDBUSY(x) ((x) << S_T5_EPCMDBUSY)
32407 #define F_T5_EPCMDBUSY    V_T5_EPCMDBUSY(1U)
32408 
32409 #define A_TP_DBG_ENG_RES1 0x67
32410 
32411 #define S_RXCPLSRDY    31
32412 #define V_RXCPLSRDY(x) ((x) << S_RXCPLSRDY)
32413 #define F_RXCPLSRDY    V_RXCPLSRDY(1U)
32414 
32415 #define S_RXOPTSRDY    30
32416 #define V_RXOPTSRDY(x) ((x) << S_RXOPTSRDY)
32417 #define F_RXOPTSRDY    V_RXOPTSRDY(1U)
32418 
32419 #define S_RXPLDLENSRDY    29
32420 #define V_RXPLDLENSRDY(x) ((x) << S_RXPLDLENSRDY)
32421 #define F_RXPLDLENSRDY    V_RXPLDLENSRDY(1U)
32422 
32423 #define S_RXNOTBUSY    28
32424 #define V_RXNOTBUSY(x) ((x) << S_RXNOTBUSY)
32425 #define F_RXNOTBUSY    V_RXNOTBUSY(1U)
32426 
32427 #define S_CPLCMDIN    20
32428 #define M_CPLCMDIN    0xffU
32429 #define V_CPLCMDIN(x) ((x) << S_CPLCMDIN)
32430 #define G_CPLCMDIN(x) (((x) >> S_CPLCMDIN) & M_CPLCMDIN)
32431 
32432 #define S_RCFPTIDSRDY    19
32433 #define V_RCFPTIDSRDY(x) ((x) << S_RCFPTIDSRDY)
32434 #define F_RCFPTIDSRDY    V_RCFPTIDSRDY(1U)
32435 
32436 #define S_EPDUHDRSRDY    18
32437 #define V_EPDUHDRSRDY(x) ((x) << S_EPDUHDRSRDY)
32438 #define F_EPDUHDRSRDY    V_EPDUHDRSRDY(1U)
32439 
32440 #define S_TUNNELPKTREG    17
32441 #define V_TUNNELPKTREG(x) ((x) << S_TUNNELPKTREG)
32442 #define F_TUNNELPKTREG    V_TUNNELPKTREG(1U)
32443 
32444 #define S_TXPKTCSUMSRDY    16
32445 #define V_TXPKTCSUMSRDY(x) ((x) << S_TXPKTCSUMSRDY)
32446 #define F_TXPKTCSUMSRDY    V_TXPKTCSUMSRDY(1U)
32447 
32448 #define S_TABLEACCESSLATENCY    12
32449 #define M_TABLEACCESSLATENCY    0xfU
32450 #define V_TABLEACCESSLATENCY(x) ((x) << S_TABLEACCESSLATENCY)
32451 #define G_TABLEACCESSLATENCY(x) (((x) >> S_TABLEACCESSLATENCY) & M_TABLEACCESSLATENCY)
32452 
32453 #define S_MMGRDONE    11
32454 #define V_MMGRDONE(x) ((x) << S_MMGRDONE)
32455 #define F_MMGRDONE    V_MMGRDONE(1U)
32456 
32457 #define S_SEENMMGRDONE    10
32458 #define V_SEENMMGRDONE(x) ((x) << S_SEENMMGRDONE)
32459 #define F_SEENMMGRDONE    V_SEENMMGRDONE(1U)
32460 
32461 #define S_RXERRORSRDY    9
32462 #define V_RXERRORSRDY(x) ((x) << S_RXERRORSRDY)
32463 #define F_RXERRORSRDY    V_RXERRORSRDY(1U)
32464 
32465 #define S_RCFOPTIONSTCPSRDY    8
32466 #define V_RCFOPTIONSTCPSRDY(x) ((x) << S_RCFOPTIONSTCPSRDY)
32467 #define F_RCFOPTIONSTCPSRDY    V_RCFOPTIONSTCPSRDY(1U)
32468 
32469 #define S_ENGINESTATE    6
32470 #define M_ENGINESTATE    0x3U
32471 #define V_ENGINESTATE(x) ((x) << S_ENGINESTATE)
32472 #define G_ENGINESTATE(x) (((x) >> S_ENGINESTATE) & M_ENGINESTATE)
32473 
32474 #define S_TABLEACCESINCREMENT    5
32475 #define V_TABLEACCESINCREMENT(x) ((x) << S_TABLEACCESINCREMENT)
32476 #define F_TABLEACCESINCREMENT    V_TABLEACCESINCREMENT(1U)
32477 
32478 #define S_TABLEACCESCOMPLETE    4
32479 #define V_TABLEACCESCOMPLETE(x) ((x) << S_TABLEACCESCOMPLETE)
32480 #define F_TABLEACCESCOMPLETE    V_TABLEACCESCOMPLETE(1U)
32481 
32482 #define S_RCFOPCODEOUTUSABLE    3
32483 #define V_RCFOPCODEOUTUSABLE(x) ((x) << S_RCFOPCODEOUTUSABLE)
32484 #define F_RCFOPCODEOUTUSABLE    V_RCFOPCODEOUTUSABLE(1U)
32485 
32486 #define S_RCFDATAOUTUSABLE    2
32487 #define V_RCFDATAOUTUSABLE(x) ((x) << S_RCFDATAOUTUSABLE)
32488 #define F_RCFDATAOUTUSABLE    V_RCFDATAOUTUSABLE(1U)
32489 
32490 #define S_RCFDATAWAITAFTERRD    1
32491 #define V_RCFDATAWAITAFTERRD(x) ((x) << S_RCFDATAWAITAFTERRD)
32492 #define F_RCFDATAWAITAFTERRD    V_RCFDATAWAITAFTERRD(1U)
32493 
32494 #define S_RCFDATACMRDY    0
32495 #define V_RCFDATACMRDY(x) ((x) << S_RCFDATACMRDY)
32496 #define F_RCFDATACMRDY    V_RCFDATACMRDY(1U)
32497 
32498 #define S_RXISSSRDY    28
32499 #define V_RXISSSRDY(x) ((x) << S_RXISSSRDY)
32500 #define F_RXISSSRDY    V_RXISSSRDY(1U)
32501 
32502 #define A_TP_DBG_ENG_RES2 0x68
32503 
32504 #define S_CPLCMDRAW    24
32505 #define M_CPLCMDRAW    0xffU
32506 #define V_CPLCMDRAW(x) ((x) << S_CPLCMDRAW)
32507 #define G_CPLCMDRAW(x) (((x) >> S_CPLCMDRAW) & M_CPLCMDRAW)
32508 
32509 #define S_RXMACPORT    20
32510 #define M_RXMACPORT    0xfU
32511 #define V_RXMACPORT(x) ((x) << S_RXMACPORT)
32512 #define G_RXMACPORT(x) (((x) >> S_RXMACPORT) & M_RXMACPORT)
32513 
32514 #define S_TXECHANNEL    18
32515 #define M_TXECHANNEL    0x3U
32516 #define V_TXECHANNEL(x) ((x) << S_TXECHANNEL)
32517 #define G_TXECHANNEL(x) (((x) >> S_TXECHANNEL) & M_TXECHANNEL)
32518 
32519 #define S_RXECHANNEL    16
32520 #define M_RXECHANNEL    0x3U
32521 #define V_RXECHANNEL(x) ((x) << S_RXECHANNEL)
32522 #define G_RXECHANNEL(x) (((x) >> S_RXECHANNEL) & M_RXECHANNEL)
32523 
32524 #define S_CDATAOUT    15
32525 #define V_CDATAOUT(x) ((x) << S_CDATAOUT)
32526 #define F_CDATAOUT    V_CDATAOUT(1U)
32527 
32528 #define S_CREADPDU    14
32529 #define V_CREADPDU(x) ((x) << S_CREADPDU)
32530 #define F_CREADPDU    V_CREADPDU(1U)
32531 
32532 #define S_EDATAOUT    13
32533 #define V_EDATAOUT(x) ((x) << S_EDATAOUT)
32534 #define F_EDATAOUT    V_EDATAOUT(1U)
32535 
32536 #define S_EREADPDU    12
32537 #define V_EREADPDU(x) ((x) << S_EREADPDU)
32538 #define F_EREADPDU    V_EREADPDU(1U)
32539 
32540 #define S_ETCPOPSRDY    11
32541 #define V_ETCPOPSRDY(x) ((x) << S_ETCPOPSRDY)
32542 #define F_ETCPOPSRDY    V_ETCPOPSRDY(1U)
32543 
32544 #define S_CTCPOPSRDY    10
32545 #define V_CTCPOPSRDY(x) ((x) << S_CTCPOPSRDY)
32546 #define F_CTCPOPSRDY    V_CTCPOPSRDY(1U)
32547 
32548 #define S_CPKTOUT    9
32549 #define V_CPKTOUT(x) ((x) << S_CPKTOUT)
32550 #define F_CPKTOUT    V_CPKTOUT(1U)
32551 
32552 #define S_CMDBRSPSRDY    8
32553 #define V_CMDBRSPSRDY(x) ((x) << S_CMDBRSPSRDY)
32554 #define F_CMDBRSPSRDY    V_CMDBRSPSRDY(1U)
32555 
32556 #define S_RXPSTRUCTSFULL    6
32557 #define M_RXPSTRUCTSFULL    0x3U
32558 #define V_RXPSTRUCTSFULL(x) ((x) << S_RXPSTRUCTSFULL)
32559 #define G_RXPSTRUCTSFULL(x) (((x) >> S_RXPSTRUCTSFULL) & M_RXPSTRUCTSFULL)
32560 
32561 #define S_RXPAGEPOOLFULL    4
32562 #define M_RXPAGEPOOLFULL    0x3U
32563 #define V_RXPAGEPOOLFULL(x) ((x) << S_RXPAGEPOOLFULL)
32564 #define G_RXPAGEPOOLFULL(x) (((x) >> S_RXPAGEPOOLFULL) & M_RXPAGEPOOLFULL)
32565 
32566 #define S_RCFREASONOUT    0
32567 #define M_RCFREASONOUT    0xfU
32568 #define V_RCFREASONOUT(x) ((x) << S_RCFREASONOUT)
32569 #define G_RCFREASONOUT(x) (((x) >> S_RCFREASONOUT) & M_RCFREASONOUT)
32570 
32571 #define A_TP_DBG_CORE_PCMD 0x69
32572 
32573 #define S_CPCMDEOPCNT    30
32574 #define M_CPCMDEOPCNT    0x3U
32575 #define V_CPCMDEOPCNT(x) ((x) << S_CPCMDEOPCNT)
32576 #define G_CPCMDEOPCNT(x) (((x) >> S_CPCMDEOPCNT) & M_CPCMDEOPCNT)
32577 
32578 #define S_CPCMDLENSAVE    16
32579 #define M_CPCMDLENSAVE    0x3fffU
32580 #define V_CPCMDLENSAVE(x) ((x) << S_CPCMDLENSAVE)
32581 #define G_CPCMDLENSAVE(x) (((x) >> S_CPCMDLENSAVE) & M_CPCMDLENSAVE)
32582 
32583 #define S_EPCMDEOPCNT    14
32584 #define M_EPCMDEOPCNT    0x3U
32585 #define V_EPCMDEOPCNT(x) ((x) << S_EPCMDEOPCNT)
32586 #define G_EPCMDEOPCNT(x) (((x) >> S_EPCMDEOPCNT) & M_EPCMDEOPCNT)
32587 
32588 #define S_EPCMDLENSAVE    0
32589 #define M_EPCMDLENSAVE    0x3fffU
32590 #define V_EPCMDLENSAVE(x) ((x) << S_EPCMDLENSAVE)
32591 #define G_EPCMDLENSAVE(x) (((x) >> S_EPCMDLENSAVE) & M_EPCMDLENSAVE)
32592 
32593 #define A_TP_DBG_SCHED_TX 0x6a
32594 
32595 #define S_TXCHNXOFF    28
32596 #define M_TXCHNXOFF    0xfU
32597 #define V_TXCHNXOFF(x) ((x) << S_TXCHNXOFF)
32598 #define G_TXCHNXOFF(x) (((x) >> S_TXCHNXOFF) & M_TXCHNXOFF)
32599 
32600 #define S_TXFIFOCNG    24
32601 #define M_TXFIFOCNG    0xfU
32602 #define V_TXFIFOCNG(x) ((x) << S_TXFIFOCNG)
32603 #define G_TXFIFOCNG(x) (((x) >> S_TXFIFOCNG) & M_TXFIFOCNG)
32604 
32605 #define S_TXPCMDCNG    20
32606 #define M_TXPCMDCNG    0xfU
32607 #define V_TXPCMDCNG(x) ((x) << S_TXPCMDCNG)
32608 #define G_TXPCMDCNG(x) (((x) >> S_TXPCMDCNG) & M_TXPCMDCNG)
32609 
32610 #define S_TXLPBKCNG    16
32611 #define M_TXLPBKCNG    0xfU
32612 #define V_TXLPBKCNG(x) ((x) << S_TXLPBKCNG)
32613 #define G_TXLPBKCNG(x) (((x) >> S_TXLPBKCNG) & M_TXLPBKCNG)
32614 
32615 #define S_TXHDRCNG    8
32616 #define M_TXHDRCNG    0xffU
32617 #define V_TXHDRCNG(x) ((x) << S_TXHDRCNG)
32618 #define G_TXHDRCNG(x) (((x) >> S_TXHDRCNG) & M_TXHDRCNG)
32619 
32620 #define S_TXMODXOFF    0
32621 #define M_TXMODXOFF    0xffU
32622 #define V_TXMODXOFF(x) ((x) << S_TXMODXOFF)
32623 #define G_TXMODXOFF(x) (((x) >> S_TXMODXOFF) & M_TXMODXOFF)
32624 
32625 #define A_TP_DBG_SCHED_RX 0x6b
32626 
32627 #define S_RXCHNXOFF    28
32628 #define M_RXCHNXOFF    0xfU
32629 #define V_RXCHNXOFF(x) ((x) << S_RXCHNXOFF)
32630 #define G_RXCHNXOFF(x) (((x) >> S_RXCHNXOFF) & M_RXCHNXOFF)
32631 
32632 #define S_RXSGECNG    24
32633 #define M_RXSGECNG    0xfU
32634 #define V_RXSGECNG(x) ((x) << S_RXSGECNG)
32635 #define G_RXSGECNG(x) (((x) >> S_RXSGECNG) & M_RXSGECNG)
32636 
32637 #define S_RXFIFOCNG    22
32638 #define M_RXFIFOCNG    0x3U
32639 #define V_RXFIFOCNG(x) ((x) << S_RXFIFOCNG)
32640 #define G_RXFIFOCNG(x) (((x) >> S_RXFIFOCNG) & M_RXFIFOCNG)
32641 
32642 #define S_RXPCMDCNG    20
32643 #define M_RXPCMDCNG    0x3U
32644 #define V_RXPCMDCNG(x) ((x) << S_RXPCMDCNG)
32645 #define G_RXPCMDCNG(x) (((x) >> S_RXPCMDCNG) & M_RXPCMDCNG)
32646 
32647 #define S_RXLPBKCNG    16
32648 #define M_RXLPBKCNG    0xfU
32649 #define V_RXLPBKCNG(x) ((x) << S_RXLPBKCNG)
32650 #define G_RXLPBKCNG(x) (((x) >> S_RXLPBKCNG) & M_RXLPBKCNG)
32651 
32652 #define S_RXHDRCNG    8
32653 #define M_RXHDRCNG    0xfU
32654 #define V_RXHDRCNG(x) ((x) << S_RXHDRCNG)
32655 #define G_RXHDRCNG(x) (((x) >> S_RXHDRCNG) & M_RXHDRCNG)
32656 
32657 #define S_RXMODXOFF    0
32658 #define M_RXMODXOFF    0x3U
32659 #define V_RXMODXOFF(x) ((x) << S_RXMODXOFF)
32660 #define G_RXMODXOFF(x) (((x) >> S_RXMODXOFF) & M_RXMODXOFF)
32661 
32662 #define S_T5_RXFIFOCNG    20
32663 #define M_T5_RXFIFOCNG    0xfU
32664 #define V_T5_RXFIFOCNG(x) ((x) << S_T5_RXFIFOCNG)
32665 #define G_T5_RXFIFOCNG(x) (((x) >> S_T5_RXFIFOCNG) & M_T5_RXFIFOCNG)
32666 
32667 #define S_T5_RXPCMDCNG    14
32668 #define M_T5_RXPCMDCNG    0x3U
32669 #define V_T5_RXPCMDCNG(x) ((x) << S_T5_RXPCMDCNG)
32670 #define G_T5_RXPCMDCNG(x) (((x) >> S_T5_RXPCMDCNG) & M_T5_RXPCMDCNG)
32671 
32672 #define A_TP_DBG_ERROR_CNT 0x6c
32673 #define A_TP_DBG_CORE_CPL 0x6d
32674 
32675 #define S_CPLCMDOUT3    24
32676 #define M_CPLCMDOUT3    0xffU
32677 #define V_CPLCMDOUT3(x) ((x) << S_CPLCMDOUT3)
32678 #define G_CPLCMDOUT3(x) (((x) >> S_CPLCMDOUT3) & M_CPLCMDOUT3)
32679 
32680 #define S_CPLCMDOUT2    16
32681 #define M_CPLCMDOUT2    0xffU
32682 #define V_CPLCMDOUT2(x) ((x) << S_CPLCMDOUT2)
32683 #define G_CPLCMDOUT2(x) (((x) >> S_CPLCMDOUT2) & M_CPLCMDOUT2)
32684 
32685 #define S_CPLCMDOUT1    8
32686 #define M_CPLCMDOUT1    0xffU
32687 #define V_CPLCMDOUT1(x) ((x) << S_CPLCMDOUT1)
32688 #define G_CPLCMDOUT1(x) (((x) >> S_CPLCMDOUT1) & M_CPLCMDOUT1)
32689 
32690 #define S_CPLCMDOUT0    0
32691 #define M_CPLCMDOUT0    0xffU
32692 #define V_CPLCMDOUT0(x) ((x) << S_CPLCMDOUT0)
32693 #define G_CPLCMDOUT0(x) (((x) >> S_CPLCMDOUT0) & M_CPLCMDOUT0)
32694 
32695 #define A_TP_MIB_DEBUG 0x6f
32696 
32697 #define S_SRC3    31
32698 #define V_SRC3(x) ((x) << S_SRC3)
32699 #define F_SRC3    V_SRC3(1U)
32700 
32701 #define S_LINENUM3    24
32702 #define M_LINENUM3    0x7fU
32703 #define V_LINENUM3(x) ((x) << S_LINENUM3)
32704 #define G_LINENUM3(x) (((x) >> S_LINENUM3) & M_LINENUM3)
32705 
32706 #define S_SRC2    23
32707 #define V_SRC2(x) ((x) << S_SRC2)
32708 #define F_SRC2    V_SRC2(1U)
32709 
32710 #define S_LINENUM2    16
32711 #define M_LINENUM2    0x7fU
32712 #define V_LINENUM2(x) ((x) << S_LINENUM2)
32713 #define G_LINENUM2(x) (((x) >> S_LINENUM2) & M_LINENUM2)
32714 
32715 #define S_SRC1    15
32716 #define V_SRC1(x) ((x) << S_SRC1)
32717 #define F_SRC1    V_SRC1(1U)
32718 
32719 #define S_LINENUM1    8
32720 #define M_LINENUM1    0x7fU
32721 #define V_LINENUM1(x) ((x) << S_LINENUM1)
32722 #define G_LINENUM1(x) (((x) >> S_LINENUM1) & M_LINENUM1)
32723 
32724 #define S_SRC0    7
32725 #define V_SRC0(x) ((x) << S_SRC0)
32726 #define F_SRC0    V_SRC0(1U)
32727 
32728 #define S_LINENUM0    0
32729 #define M_LINENUM0    0x7fU
32730 #define V_LINENUM0(x) ((x) << S_LINENUM0)
32731 #define G_LINENUM0(x) (((x) >> S_LINENUM0) & M_LINENUM0)
32732 
32733 #define A_TP_DBG_CACHE_WR_ALL 0x70
32734 #define A_TP_DBG_CACHE_WR_HIT 0x71
32735 #define A_TP_DBG_CACHE_RD_ALL 0x72
32736 #define A_TP_DBG_CACHE_RD_HIT 0x73
32737 #define A_TP_DBG_CACHE_MC_REQ 0x74
32738 #define A_TP_DBG_CACHE_MC_RSP 0x75
32739 #define A_TP_RSS_PF0_CONFIG_CH3_CH2 0x80
32740 
32741 #define S_PFMAPALWAYS    22
32742 #define V_PFMAPALWAYS(x) ((x) << S_PFMAPALWAYS)
32743 #define F_PFMAPALWAYS    V_PFMAPALWAYS(1U)
32744 
32745 #define S_PFROUNDROBINEN    21
32746 #define V_PFROUNDROBINEN(x) ((x) << S_PFROUNDROBINEN)
32747 #define F_PFROUNDROBINEN    V_PFROUNDROBINEN(1U)
32748 
32749 #define S_FOURCHNEN    20
32750 #define V_FOURCHNEN(x) ((x) << S_FOURCHNEN)
32751 #define F_FOURCHNEN    V_FOURCHNEN(1U)
32752 
32753 #define S_CH3DEFAULTQUEUE    10
32754 #define M_CH3DEFAULTQUEUE    0x3ffU
32755 #define V_CH3DEFAULTQUEUE(x) ((x) << S_CH3DEFAULTQUEUE)
32756 #define G_CH3DEFAULTQUEUE(x) (((x) >> S_CH3DEFAULTQUEUE) & M_CH3DEFAULTQUEUE)
32757 
32758 #define S_CH2DEFAULTQUEUE    0
32759 #define M_CH2DEFAULTQUEUE    0x3ffU
32760 #define V_CH2DEFAULTQUEUE(x) ((x) << S_CH2DEFAULTQUEUE)
32761 #define G_CH2DEFAULTQUEUE(x) (((x) >> S_CH2DEFAULTQUEUE) & M_CH2DEFAULTQUEUE)
32762 
32763 #define A_TP_RSS_PF1_CONFIG_CH3_CH2 0x81
32764 #define A_TP_RSS_PF2_CONFIG_CH3_CH2 0x82
32765 #define A_TP_RSS_PF3_CONFIG_CH3_CH2 0x83
32766 #define A_TP_RSS_PF4_CONFIG_CH3_CH2 0x84
32767 #define A_TP_RSS_PF5_CONFIG_CH3_CH2 0x85
32768 #define A_TP_RSS_PF6_CONFIG_CH3_CH2 0x86
32769 #define A_TP_RSS_PF7_CONFIG_CH3_CH2 0x87
32770 #define A_TP_RSS_PF0_EXT_CONFIG 0x88
32771 #define A_TP_RSS_PF1_EXT_CONFIG 0x89
32772 #define A_TP_RSS_PF2_EXT_CONFIG 0x8a
32773 #define A_TP_RSS_PF3_EXT_CONFIG 0x8b
32774 #define A_TP_RSS_PF4_EXT_CONFIG 0x8c
32775 #define A_TP_RSS_PF5_EXT_CONFIG 0x8d
32776 #define A_TP_RSS_PF6_EXT_CONFIG 0x8e
32777 #define A_TP_RSS_PF7_EXT_CONFIG 0x8f
32778 #define A_TP_ROCE_CONFIG 0x90
32779 
32780 #define S_IGNAETHMSB    24
32781 #define V_IGNAETHMSB(x) ((x) << S_IGNAETHMSB)
32782 #define F_IGNAETHMSB    V_IGNAETHMSB(1U)
32783 
32784 #define S_XDIDMMCTL    23
32785 #define V_XDIDMMCTL(x) ((x) << S_XDIDMMCTL)
32786 #define F_XDIDMMCTL    V_XDIDMMCTL(1U)
32787 
32788 #define S_WRRETHDBGFWDEN    22
32789 #define V_WRRETHDBGFWDEN(x) ((x) << S_WRRETHDBGFWDEN)
32790 #define F_WRRETHDBGFWDEN    V_WRRETHDBGFWDEN(1U)
32791 
32792 #define S_ACKINTGENCTRL    20
32793 #define M_ACKINTGENCTRL    0x3U
32794 #define V_ACKINTGENCTRL(x) ((x) << S_ACKINTGENCTRL)
32795 #define G_ACKINTGENCTRL(x) (((x) >> S_ACKINTGENCTRL) & M_ACKINTGENCTRL)
32796 
32797 #define S_ATOMICALIGNCHKEN    19
32798 #define V_ATOMICALIGNCHKEN(x) ((x) << S_ATOMICALIGNCHKEN)
32799 #define F_ATOMICALIGNCHKEN    V_ATOMICALIGNCHKEN(1U)
32800 
32801 #define S_RDRETHLENCHKEN    18
32802 #define V_RDRETHLENCHKEN(x) ((x) << S_RDRETHLENCHKEN)
32803 #define F_RDRETHLENCHKEN    V_RDRETHLENCHKEN(1U)
32804 
32805 #define S_WRTOTALLENCHKEN    17
32806 #define V_WRTOTALLENCHKEN(x) ((x) << S_WRTOTALLENCHKEN)
32807 #define F_WRTOTALLENCHKEN    V_WRTOTALLENCHKEN(1U)
32808 
32809 #define S_WRRETHLENCHKEN    16
32810 #define V_WRRETHLENCHKEN(x) ((x) << S_WRRETHLENCHKEN)
32811 #define F_WRRETHLENCHKEN    V_WRRETHLENCHKEN(1U)
32812 
32813 #define S_TNLERRORUDPLEN    11
32814 #define V_TNLERRORUDPLEN(x) ((x) << S_TNLERRORUDPLEN)
32815 #define F_TNLERRORUDPLEN    V_TNLERRORUDPLEN(1U)
32816 
32817 #define S_TNLERRORPKEY    10
32818 #define V_TNLERRORPKEY(x) ((x) << S_TNLERRORPKEY)
32819 #define F_TNLERRORPKEY    V_TNLERRORPKEY(1U)
32820 
32821 #define S_TNLERROROPCODE    9
32822 #define V_TNLERROROPCODE(x) ((x) << S_TNLERROROPCODE)
32823 #define F_TNLERROROPCODE    V_TNLERROROPCODE(1U)
32824 
32825 #define S_TNLERRORTVER    8
32826 #define V_TNLERRORTVER(x) ((x) << S_TNLERRORTVER)
32827 #define F_TNLERRORTVER    V_TNLERRORTVER(1U)
32828 
32829 #define S_DROPERRORUDPLEN    3
32830 #define V_DROPERRORUDPLEN(x) ((x) << S_DROPERRORUDPLEN)
32831 #define F_DROPERRORUDPLEN    V_DROPERRORUDPLEN(1U)
32832 
32833 #define S_DROPERRORPKEY    2
32834 #define V_DROPERRORPKEY(x) ((x) << S_DROPERRORPKEY)
32835 #define F_DROPERRORPKEY    V_DROPERRORPKEY(1U)
32836 
32837 #define S_DROPERROROPCODE    1
32838 #define V_DROPERROROPCODE(x) ((x) << S_DROPERROROPCODE)
32839 #define F_DROPERROROPCODE    V_DROPERROROPCODE(1U)
32840 
32841 #define S_DROPERRORTVER    0
32842 #define V_DROPERRORTVER(x) ((x) << S_DROPERRORTVER)
32843 #define F_DROPERRORTVER    V_DROPERRORTVER(1U)
32844 
32845 #define A_TP_NVMT_CONFIG 0x91
32846 
32847 #define S_PDACHKEN    2
32848 #define V_PDACHKEN(x) ((x) << S_PDACHKEN)
32849 #define F_PDACHKEN    V_PDACHKEN(1U)
32850 
32851 #define S_FORCERQNONDDP    1
32852 #define V_FORCERQNONDDP(x) ((x) << S_FORCERQNONDDP)
32853 #define F_FORCERQNONDDP    V_FORCERQNONDDP(1U)
32854 
32855 #define S_STRIPHCRC    0
32856 #define V_STRIPHCRC(x) ((x) << S_STRIPHCRC)
32857 #define F_STRIPHCRC    V_STRIPHCRC(1U)
32858 
32859 #define A_TP_NVMT_MAXHDR 0x92
32860 
32861 #define S_MAXHDR3    24
32862 #define M_MAXHDR3    0xffU
32863 #define V_MAXHDR3(x) ((x) << S_MAXHDR3)
32864 #define G_MAXHDR3(x) (((x) >> S_MAXHDR3) & M_MAXHDR3)
32865 
32866 #define S_MAXHDR2    16
32867 #define M_MAXHDR2    0xffU
32868 #define V_MAXHDR2(x) ((x) << S_MAXHDR2)
32869 #define G_MAXHDR2(x) (((x) >> S_MAXHDR2) & M_MAXHDR2)
32870 
32871 #define S_MAXHDR1    8
32872 #define M_MAXHDR1    0xffU
32873 #define V_MAXHDR1(x) ((x) << S_MAXHDR1)
32874 #define G_MAXHDR1(x) (((x) >> S_MAXHDR1) & M_MAXHDR1)
32875 
32876 #define S_MAXHDR0    0
32877 #define M_MAXHDR0    0xffU
32878 #define V_MAXHDR0(x) ((x) << S_MAXHDR0)
32879 #define G_MAXHDR0(x) (((x) >> S_MAXHDR0) & M_MAXHDR0)
32880 
32881 #define A_TP_NVMT_PDORSVD 0x93
32882 
32883 #define S_PDORSVD3    24
32884 #define M_PDORSVD3    0xffU
32885 #define V_PDORSVD3(x) ((x) << S_PDORSVD3)
32886 #define G_PDORSVD3(x) (((x) >> S_PDORSVD3) & M_PDORSVD3)
32887 
32888 #define S_PDORSVD2    16
32889 #define M_PDORSVD2    0xffU
32890 #define V_PDORSVD2(x) ((x) << S_PDORSVD2)
32891 #define G_PDORSVD2(x) (((x) >> S_PDORSVD2) & M_PDORSVD2)
32892 
32893 #define S_PDORSVD1    8
32894 #define M_PDORSVD1    0xffU
32895 #define V_PDORSVD1(x) ((x) << S_PDORSVD1)
32896 #define G_PDORSVD1(x) (((x) >> S_PDORSVD1) & M_PDORSVD1)
32897 
32898 #define S_PDORSVD0    0
32899 #define M_PDORSVD0    0xffU
32900 #define V_PDORSVD0(x) ((x) << S_PDORSVD0)
32901 #define G_PDORSVD0(x) (((x) >> S_PDORSVD0) & M_PDORSVD0)
32902 
32903 #define A_TP_RDMA_CONFIG 0x94
32904 
32905 #define S_SRQLIMITEN    20
32906 #define V_SRQLIMITEN(x) ((x) << S_SRQLIMITEN)
32907 #define F_SRQLIMITEN    V_SRQLIMITEN(1U)
32908 
32909 #define S_SNDIMMSEOP    15
32910 #define M_SNDIMMSEOP    0x1fU
32911 #define V_SNDIMMSEOP(x) ((x) << S_SNDIMMSEOP)
32912 #define G_SNDIMMSEOP(x) (((x) >> S_SNDIMMSEOP) & M_SNDIMMSEOP)
32913 
32914 #define S_SNDIMMOP    10
32915 #define M_SNDIMMOP    0x1fU
32916 #define V_SNDIMMOP(x) ((x) << S_SNDIMMOP)
32917 #define G_SNDIMMOP(x) (((x) >> S_SNDIMMOP) & M_SNDIMMOP)
32918 
32919 #define S_IWARPXRCIDCHKEN    4
32920 #define V_IWARPXRCIDCHKEN(x) ((x) << S_IWARPXRCIDCHKEN)
32921 #define F_IWARPXRCIDCHKEN    V_IWARPXRCIDCHKEN(1U)
32922 
32923 #define S_IWARPEXTOPEN    3
32924 #define V_IWARPEXTOPEN(x) ((x) << S_IWARPEXTOPEN)
32925 #define F_IWARPEXTOPEN    V_IWARPEXTOPEN(1U)
32926 
32927 #define S_XRCIMPLTYPE    1
32928 #define V_XRCIMPLTYPE(x) ((x) << S_XRCIMPLTYPE)
32929 #define F_XRCIMPLTYPE    V_XRCIMPLTYPE(1U)
32930 
32931 #define S_XRCEN    0
32932 #define V_XRCEN(x) ((x) << S_XRCEN)
32933 #define F_XRCEN    V_XRCEN(1U)
32934 
32935 #define A_TP_ROCE_RRQ_BASE 0x95
32936 #define A_TP_FILTER_RATE_CFG 0x96
32937 
32938 #define S_GRP_CFG_RD    30
32939 #define V_GRP_CFG_RD(x) ((x) << S_GRP_CFG_RD)
32940 #define F_GRP_CFG_RD    V_GRP_CFG_RD(1U)
32941 
32942 #define S_GRP_CFG_INIT    29
32943 #define V_GRP_CFG_INIT(x) ((x) << S_GRP_CFG_INIT)
32944 #define F_GRP_CFG_INIT    V_GRP_CFG_INIT(1U)
32945 
32946 #define S_GRP_CFG_RST    28
32947 #define V_GRP_CFG_RST(x) ((x) << S_GRP_CFG_RST)
32948 #define F_GRP_CFG_RST    V_GRP_CFG_RST(1U)
32949 
32950 #define S_GRP_CFG_SEL    16
32951 #define M_GRP_CFG_SEL    0xfffU
32952 #define V_GRP_CFG_SEL(x) ((x) << S_GRP_CFG_SEL)
32953 #define G_GRP_CFG_SEL(x) (((x) >> S_GRP_CFG_SEL) & M_GRP_CFG_SEL)
32954 
32955 #define S_US_TIMER_TICK    0
32956 #define M_US_TIMER_TICK    0xffffU
32957 #define V_US_TIMER_TICK(x) ((x) << S_US_TIMER_TICK)
32958 #define G_US_TIMER_TICK(x) (((x) >> S_US_TIMER_TICK) & M_US_TIMER_TICK)
32959 
32960 #define A_TP_TLS_CONFIG 0x99
32961 
32962 #define S_QUIESCETYPE1    24
32963 #define M_QUIESCETYPE1    0xffU
32964 #define V_QUIESCETYPE1(x) ((x) << S_QUIESCETYPE1)
32965 #define G_QUIESCETYPE1(x) (((x) >> S_QUIESCETYPE1) & M_QUIESCETYPE1)
32966 
32967 #define S_QUIESCETYPE2    16
32968 #define M_QUIESCETYPE2    0xffU
32969 #define V_QUIESCETYPE2(x) ((x) << S_QUIESCETYPE2)
32970 #define G_QUIESCETYPE2(x) (((x) >> S_QUIESCETYPE2) & M_QUIESCETYPE2)
32971 
32972 #define S_QUIESCETYPE3    8
32973 #define M_QUIESCETYPE3    0xffU
32974 #define V_QUIESCETYPE3(x) ((x) << S_QUIESCETYPE3)
32975 #define G_QUIESCETYPE3(x) (((x) >> S_QUIESCETYPE3) & M_QUIESCETYPE3)
32976 
32977 #define A_TP_T5_TX_DROP_CNT_CH0 0x120
32978 #define A_TP_T5_TX_DROP_CNT_CH1 0x121
32979 #define A_TP_TX_DROP_CNT_CH2 0x122
32980 #define A_TP_TX_DROP_CNT_CH3 0x123
32981 #define A_TP_TX_DROP_CFG_CH0 0x12b
32982 
32983 #define S_TIMERENABLED    31
32984 #define V_TIMERENABLED(x) ((x) << S_TIMERENABLED)
32985 #define F_TIMERENABLED    V_TIMERENABLED(1U)
32986 
32987 #define S_TIMERERRORENABLE    30
32988 #define V_TIMERERRORENABLE(x) ((x) << S_TIMERERRORENABLE)
32989 #define F_TIMERERRORENABLE    V_TIMERERRORENABLE(1U)
32990 
32991 #define S_TIMERTHRESHOLD    4
32992 #define M_TIMERTHRESHOLD    0x3ffffffU
32993 #define V_TIMERTHRESHOLD(x) ((x) << S_TIMERTHRESHOLD)
32994 #define G_TIMERTHRESHOLD(x) (((x) >> S_TIMERTHRESHOLD) & M_TIMERTHRESHOLD)
32995 
32996 #define S_PACKETDROPS    0
32997 #define M_PACKETDROPS    0xfU
32998 #define V_PACKETDROPS(x) ((x) << S_PACKETDROPS)
32999 #define G_PACKETDROPS(x) (((x) >> S_PACKETDROPS) & M_PACKETDROPS)
33000 
33001 #define A_TP_TX_DROP_CFG_CH1 0x12c
33002 #define A_TP_TX_DROP_CNT_CH0 0x12d
33003 
33004 #define S_TXDROPCNTCH0SENT    16
33005 #define M_TXDROPCNTCH0SENT    0xffffU
33006 #define V_TXDROPCNTCH0SENT(x) ((x) << S_TXDROPCNTCH0SENT)
33007 #define G_TXDROPCNTCH0SENT(x) (((x) >> S_TXDROPCNTCH0SENT) & M_TXDROPCNTCH0SENT)
33008 
33009 #define S_TXDROPCNTCH0RCVD    0
33010 #define M_TXDROPCNTCH0RCVD    0xffffU
33011 #define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
33012 #define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & M_TXDROPCNTCH0RCVD)
33013 
33014 #define A_TP_TX_DROP_CNT_CH1 0x12e
33015 
33016 #define S_TXDROPCNTCH1SENT    16
33017 #define M_TXDROPCNTCH1SENT    0xffffU
33018 #define V_TXDROPCNTCH1SENT(x) ((x) << S_TXDROPCNTCH1SENT)
33019 #define G_TXDROPCNTCH1SENT(x) (((x) >> S_TXDROPCNTCH1SENT) & M_TXDROPCNTCH1SENT)
33020 
33021 #define S_TXDROPCNTCH1RCVD    0
33022 #define M_TXDROPCNTCH1RCVD    0xffffU
33023 #define V_TXDROPCNTCH1RCVD(x) ((x) << S_TXDROPCNTCH1RCVD)
33024 #define G_TXDROPCNTCH1RCVD(x) (((x) >> S_TXDROPCNTCH1RCVD) & M_TXDROPCNTCH1RCVD)
33025 
33026 #define A_TP_TX_DROP_MODE 0x12f
33027 
33028 #define S_TXDROPMODECH3    3
33029 #define V_TXDROPMODECH3(x) ((x) << S_TXDROPMODECH3)
33030 #define F_TXDROPMODECH3    V_TXDROPMODECH3(1U)
33031 
33032 #define S_TXDROPMODECH2    2
33033 #define V_TXDROPMODECH2(x) ((x) << S_TXDROPMODECH2)
33034 #define F_TXDROPMODECH2    V_TXDROPMODECH2(1U)
33035 
33036 #define S_TXDROPMODECH1    1
33037 #define V_TXDROPMODECH1(x) ((x) << S_TXDROPMODECH1)
33038 #define F_TXDROPMODECH1    V_TXDROPMODECH1(1U)
33039 
33040 #define S_TXDROPMODECH0    0
33041 #define V_TXDROPMODECH0(x) ((x) << S_TXDROPMODECH0)
33042 #define F_TXDROPMODECH0    V_TXDROPMODECH0(1U)
33043 
33044 #define A_TP_DBG_ESIDE_PKT0 0x130
33045 
33046 #define S_ETXSOPCNT    28
33047 #define M_ETXSOPCNT    0xfU
33048 #define V_ETXSOPCNT(x) ((x) << S_ETXSOPCNT)
33049 #define G_ETXSOPCNT(x) (((x) >> S_ETXSOPCNT) & M_ETXSOPCNT)
33050 
33051 #define S_ETXEOPCNT    24
33052 #define M_ETXEOPCNT    0xfU
33053 #define V_ETXEOPCNT(x) ((x) << S_ETXEOPCNT)
33054 #define G_ETXEOPCNT(x) (((x) >> S_ETXEOPCNT) & M_ETXEOPCNT)
33055 
33056 #define S_ETXPLDSOPCNT    20
33057 #define M_ETXPLDSOPCNT    0xfU
33058 #define V_ETXPLDSOPCNT(x) ((x) << S_ETXPLDSOPCNT)
33059 #define G_ETXPLDSOPCNT(x) (((x) >> S_ETXPLDSOPCNT) & M_ETXPLDSOPCNT)
33060 
33061 #define S_ETXPLDEOPCNT    16
33062 #define M_ETXPLDEOPCNT    0xfU
33063 #define V_ETXPLDEOPCNT(x) ((x) << S_ETXPLDEOPCNT)
33064 #define G_ETXPLDEOPCNT(x) (((x) >> S_ETXPLDEOPCNT) & M_ETXPLDEOPCNT)
33065 
33066 #define S_ERXSOPCNT    12
33067 #define M_ERXSOPCNT    0xfU
33068 #define V_ERXSOPCNT(x) ((x) << S_ERXSOPCNT)
33069 #define G_ERXSOPCNT(x) (((x) >> S_ERXSOPCNT) & M_ERXSOPCNT)
33070 
33071 #define S_ERXEOPCNT    8
33072 #define M_ERXEOPCNT    0xfU
33073 #define V_ERXEOPCNT(x) ((x) << S_ERXEOPCNT)
33074 #define G_ERXEOPCNT(x) (((x) >> S_ERXEOPCNT) & M_ERXEOPCNT)
33075 
33076 #define S_ERXPLDSOPCNT    4
33077 #define M_ERXPLDSOPCNT    0xfU
33078 #define V_ERXPLDSOPCNT(x) ((x) << S_ERXPLDSOPCNT)
33079 #define G_ERXPLDSOPCNT(x) (((x) >> S_ERXPLDSOPCNT) & M_ERXPLDSOPCNT)
33080 
33081 #define S_ERXPLDEOPCNT    0
33082 #define M_ERXPLDEOPCNT    0xfU
33083 #define V_ERXPLDEOPCNT(x) ((x) << S_ERXPLDEOPCNT)
33084 #define G_ERXPLDEOPCNT(x) (((x) >> S_ERXPLDEOPCNT) & M_ERXPLDEOPCNT)
33085 
33086 #define A_TP_DBG_ESIDE_PKT1 0x131
33087 #define A_TP_DBG_ESIDE_PKT2 0x132
33088 #define A_TP_DBG_ESIDE_PKT3 0x133
33089 #define A_TP_DBG_ESIDE_FIFO0 0x134
33090 
33091 #define S_PLDRXCSUMVALID1    31
33092 #define V_PLDRXCSUMVALID1(x) ((x) << S_PLDRXCSUMVALID1)
33093 #define F_PLDRXCSUMVALID1    V_PLDRXCSUMVALID1(1U)
33094 
33095 #define S_PLDRXZEROPSRDY1    30
33096 #define V_PLDRXZEROPSRDY1(x) ((x) << S_PLDRXZEROPSRDY1)
33097 #define F_PLDRXZEROPSRDY1    V_PLDRXZEROPSRDY1(1U)
33098 
33099 #define S_PLDRXVALID1    29
33100 #define V_PLDRXVALID1(x) ((x) << S_PLDRXVALID1)
33101 #define F_PLDRXVALID1    V_PLDRXVALID1(1U)
33102 
33103 #define S_TCPRXVALID1    28
33104 #define V_TCPRXVALID1(x) ((x) << S_TCPRXVALID1)
33105 #define F_TCPRXVALID1    V_TCPRXVALID1(1U)
33106 
33107 #define S_IPRXVALID1    27
33108 #define V_IPRXVALID1(x) ((x) << S_IPRXVALID1)
33109 #define F_IPRXVALID1    V_IPRXVALID1(1U)
33110 
33111 #define S_ETHRXVALID1    26
33112 #define V_ETHRXVALID1(x) ((x) << S_ETHRXVALID1)
33113 #define F_ETHRXVALID1    V_ETHRXVALID1(1U)
33114 
33115 #define S_CPLRXVALID1    25
33116 #define V_CPLRXVALID1(x) ((x) << S_CPLRXVALID1)
33117 #define F_CPLRXVALID1    V_CPLRXVALID1(1U)
33118 
33119 #define S_FSTATIC1    24
33120 #define V_FSTATIC1(x) ((x) << S_FSTATIC1)
33121 #define F_FSTATIC1    V_FSTATIC1(1U)
33122 
33123 #define S_ERRORSRDY1    23
33124 #define V_ERRORSRDY1(x) ((x) << S_ERRORSRDY1)
33125 #define F_ERRORSRDY1    V_ERRORSRDY1(1U)
33126 
33127 #define S_PLDTXSRDY1    22
33128 #define V_PLDTXSRDY1(x) ((x) << S_PLDTXSRDY1)
33129 #define F_PLDTXSRDY1    V_PLDTXSRDY1(1U)
33130 
33131 #define S_DBVLD1    21
33132 #define V_DBVLD1(x) ((x) << S_DBVLD1)
33133 #define F_DBVLD1    V_DBVLD1(1U)
33134 
33135 #define S_PLDTXVALID1    20
33136 #define V_PLDTXVALID1(x) ((x) << S_PLDTXVALID1)
33137 #define F_PLDTXVALID1    V_PLDTXVALID1(1U)
33138 
33139 #define S_ETXVALID1    19
33140 #define V_ETXVALID1(x) ((x) << S_ETXVALID1)
33141 #define F_ETXVALID1    V_ETXVALID1(1U)
33142 
33143 #define S_ETXFULL1    18
33144 #define V_ETXFULL1(x) ((x) << S_ETXFULL1)
33145 #define F_ETXFULL1    V_ETXFULL1(1U)
33146 
33147 #define S_ERXVALID1    17
33148 #define V_ERXVALID1(x) ((x) << S_ERXVALID1)
33149 #define F_ERXVALID1    V_ERXVALID1(1U)
33150 
33151 #define S_ERXFULL1    16
33152 #define V_ERXFULL1(x) ((x) << S_ERXFULL1)
33153 #define F_ERXFULL1    V_ERXFULL1(1U)
33154 
33155 #define S_PLDRXCSUMVALID0    15
33156 #define V_PLDRXCSUMVALID0(x) ((x) << S_PLDRXCSUMVALID0)
33157 #define F_PLDRXCSUMVALID0    V_PLDRXCSUMVALID0(1U)
33158 
33159 #define S_PLDRXZEROPSRDY0    14
33160 #define V_PLDRXZEROPSRDY0(x) ((x) << S_PLDRXZEROPSRDY0)
33161 #define F_PLDRXZEROPSRDY0    V_PLDRXZEROPSRDY0(1U)
33162 
33163 #define S_PLDRXVALID0    13
33164 #define V_PLDRXVALID0(x) ((x) << S_PLDRXVALID0)
33165 #define F_PLDRXVALID0    V_PLDRXVALID0(1U)
33166 
33167 #define S_TCPRXVALID0    12
33168 #define V_TCPRXVALID0(x) ((x) << S_TCPRXVALID0)
33169 #define F_TCPRXVALID0    V_TCPRXVALID0(1U)
33170 
33171 #define S_IPRXVALID0    11
33172 #define V_IPRXVALID0(x) ((x) << S_IPRXVALID0)
33173 #define F_IPRXVALID0    V_IPRXVALID0(1U)
33174 
33175 #define S_ETHRXVALID0    10
33176 #define V_ETHRXVALID0(x) ((x) << S_ETHRXVALID0)
33177 #define F_ETHRXVALID0    V_ETHRXVALID0(1U)
33178 
33179 #define S_CPLRXVALID0    9
33180 #define V_CPLRXVALID0(x) ((x) << S_CPLRXVALID0)
33181 #define F_CPLRXVALID0    V_CPLRXVALID0(1U)
33182 
33183 #define S_FSTATIC0    8
33184 #define V_FSTATIC0(x) ((x) << S_FSTATIC0)
33185 #define F_FSTATIC0    V_FSTATIC0(1U)
33186 
33187 #define S_ERRORSRDY0    7
33188 #define V_ERRORSRDY0(x) ((x) << S_ERRORSRDY0)
33189 #define F_ERRORSRDY0    V_ERRORSRDY0(1U)
33190 
33191 #define S_PLDTXSRDY0    6
33192 #define V_PLDTXSRDY0(x) ((x) << S_PLDTXSRDY0)
33193 #define F_PLDTXSRDY0    V_PLDTXSRDY0(1U)
33194 
33195 #define S_DBVLD0    5
33196 #define V_DBVLD0(x) ((x) << S_DBVLD0)
33197 #define F_DBVLD0    V_DBVLD0(1U)
33198 
33199 #define S_PLDTXVALID0    4
33200 #define V_PLDTXVALID0(x) ((x) << S_PLDTXVALID0)
33201 #define F_PLDTXVALID0    V_PLDTXVALID0(1U)
33202 
33203 #define S_ETXVALID0    3
33204 #define V_ETXVALID0(x) ((x) << S_ETXVALID0)
33205 #define F_ETXVALID0    V_ETXVALID0(1U)
33206 
33207 #define S_ETXFULL0    2
33208 #define V_ETXFULL0(x) ((x) << S_ETXFULL0)
33209 #define F_ETXFULL0    V_ETXFULL0(1U)
33210 
33211 #define S_ERXVALID0    1
33212 #define V_ERXVALID0(x) ((x) << S_ERXVALID0)
33213 #define F_ERXVALID0    V_ERXVALID0(1U)
33214 
33215 #define S_ERXFULL0    0
33216 #define V_ERXFULL0(x) ((x) << S_ERXFULL0)
33217 #define F_ERXFULL0    V_ERXFULL0(1U)
33218 
33219 #define A_TP_DBG_ESIDE_FIFO1 0x135
33220 
33221 #define S_PLDRXCSUMVALID3    31
33222 #define V_PLDRXCSUMVALID3(x) ((x) << S_PLDRXCSUMVALID3)
33223 #define F_PLDRXCSUMVALID3    V_PLDRXCSUMVALID3(1U)
33224 
33225 #define S_PLDRXZEROPSRDY3    30
33226 #define V_PLDRXZEROPSRDY3(x) ((x) << S_PLDRXZEROPSRDY3)
33227 #define F_PLDRXZEROPSRDY3    V_PLDRXZEROPSRDY3(1U)
33228 
33229 #define S_PLDRXVALID3    29
33230 #define V_PLDRXVALID3(x) ((x) << S_PLDRXVALID3)
33231 #define F_PLDRXVALID3    V_PLDRXVALID3(1U)
33232 
33233 #define S_TCPRXVALID3    28
33234 #define V_TCPRXVALID3(x) ((x) << S_TCPRXVALID3)
33235 #define F_TCPRXVALID3    V_TCPRXVALID3(1U)
33236 
33237 #define S_IPRXVALID3    27
33238 #define V_IPRXVALID3(x) ((x) << S_IPRXVALID3)
33239 #define F_IPRXVALID3    V_IPRXVALID3(1U)
33240 
33241 #define S_ETHRXVALID3    26
33242 #define V_ETHRXVALID3(x) ((x) << S_ETHRXVALID3)
33243 #define F_ETHRXVALID3    V_ETHRXVALID3(1U)
33244 
33245 #define S_CPLRXVALID3    25
33246 #define V_CPLRXVALID3(x) ((x) << S_CPLRXVALID3)
33247 #define F_CPLRXVALID3    V_CPLRXVALID3(1U)
33248 
33249 #define S_FSTATIC3    24
33250 #define V_FSTATIC3(x) ((x) << S_FSTATIC3)
33251 #define F_FSTATIC3    V_FSTATIC3(1U)
33252 
33253 #define S_ERRORSRDY3    23
33254 #define V_ERRORSRDY3(x) ((x) << S_ERRORSRDY3)
33255 #define F_ERRORSRDY3    V_ERRORSRDY3(1U)
33256 
33257 #define S_PLDTXSRDY3    22
33258 #define V_PLDTXSRDY3(x) ((x) << S_PLDTXSRDY3)
33259 #define F_PLDTXSRDY3    V_PLDTXSRDY3(1U)
33260 
33261 #define S_DBVLD3    21
33262 #define V_DBVLD3(x) ((x) << S_DBVLD3)
33263 #define F_DBVLD3    V_DBVLD3(1U)
33264 
33265 #define S_PLDTXVALID3    20
33266 #define V_PLDTXVALID3(x) ((x) << S_PLDTXVALID3)
33267 #define F_PLDTXVALID3    V_PLDTXVALID3(1U)
33268 
33269 #define S_ETXVALID3    19
33270 #define V_ETXVALID3(x) ((x) << S_ETXVALID3)
33271 #define F_ETXVALID3    V_ETXVALID3(1U)
33272 
33273 #define S_ETXFULL3    18
33274 #define V_ETXFULL3(x) ((x) << S_ETXFULL3)
33275 #define F_ETXFULL3    V_ETXFULL3(1U)
33276 
33277 #define S_ERXVALID3    17
33278 #define V_ERXVALID3(x) ((x) << S_ERXVALID3)
33279 #define F_ERXVALID3    V_ERXVALID3(1U)
33280 
33281 #define S_ERXFULL3    16
33282 #define V_ERXFULL3(x) ((x) << S_ERXFULL3)
33283 #define F_ERXFULL3    V_ERXFULL3(1U)
33284 
33285 #define S_PLDRXCSUMVALID2    15
33286 #define V_PLDRXCSUMVALID2(x) ((x) << S_PLDRXCSUMVALID2)
33287 #define F_PLDRXCSUMVALID2    V_PLDRXCSUMVALID2(1U)
33288 
33289 #define S_PLDRXZEROPSRDY2    14
33290 #define V_PLDRXZEROPSRDY2(x) ((x) << S_PLDRXZEROPSRDY2)
33291 #define F_PLDRXZEROPSRDY2    V_PLDRXZEROPSRDY2(1U)
33292 
33293 #define S_PLDRXVALID2    13
33294 #define V_PLDRXVALID2(x) ((x) << S_PLDRXVALID2)
33295 #define F_PLDRXVALID2    V_PLDRXVALID2(1U)
33296 
33297 #define S_TCPRXVALID2    12
33298 #define V_TCPRXVALID2(x) ((x) << S_TCPRXVALID2)
33299 #define F_TCPRXVALID2    V_TCPRXVALID2(1U)
33300 
33301 #define S_IPRXVALID2    11
33302 #define V_IPRXVALID2(x) ((x) << S_IPRXVALID2)
33303 #define F_IPRXVALID2    V_IPRXVALID2(1U)
33304 
33305 #define S_ETHRXVALID2    10
33306 #define V_ETHRXVALID2(x) ((x) << S_ETHRXVALID2)
33307 #define F_ETHRXVALID2    V_ETHRXVALID2(1U)
33308 
33309 #define S_CPLRXVALID2    9
33310 #define V_CPLRXVALID2(x) ((x) << S_CPLRXVALID2)
33311 #define F_CPLRXVALID2    V_CPLRXVALID2(1U)
33312 
33313 #define S_FSTATIC2    8
33314 #define V_FSTATIC2(x) ((x) << S_FSTATIC2)
33315 #define F_FSTATIC2    V_FSTATIC2(1U)
33316 
33317 #define S_ERRORSRDY2    7
33318 #define V_ERRORSRDY2(x) ((x) << S_ERRORSRDY2)
33319 #define F_ERRORSRDY2    V_ERRORSRDY2(1U)
33320 
33321 #define S_PLDTXSRDY2    6
33322 #define V_PLDTXSRDY2(x) ((x) << S_PLDTXSRDY2)
33323 #define F_PLDTXSRDY2    V_PLDTXSRDY2(1U)
33324 
33325 #define S_DBVLD2    5
33326 #define V_DBVLD2(x) ((x) << S_DBVLD2)
33327 #define F_DBVLD2    V_DBVLD2(1U)
33328 
33329 #define S_PLDTXVALID2    4
33330 #define V_PLDTXVALID2(x) ((x) << S_PLDTXVALID2)
33331 #define F_PLDTXVALID2    V_PLDTXVALID2(1U)
33332 
33333 #define S_ETXVALID2    3
33334 #define V_ETXVALID2(x) ((x) << S_ETXVALID2)
33335 #define F_ETXVALID2    V_ETXVALID2(1U)
33336 
33337 #define S_ETXFULL2    2
33338 #define V_ETXFULL2(x) ((x) << S_ETXFULL2)
33339 #define F_ETXFULL2    V_ETXFULL2(1U)
33340 
33341 #define S_ERXVALID2    1
33342 #define V_ERXVALID2(x) ((x) << S_ERXVALID2)
33343 #define F_ERXVALID2    V_ERXVALID2(1U)
33344 
33345 #define S_ERXFULL2    0
33346 #define V_ERXFULL2(x) ((x) << S_ERXFULL2)
33347 #define F_ERXFULL2    V_ERXFULL2(1U)
33348 
33349 #define A_TP_DBG_ESIDE_DISP0 0x136
33350 
33351 #define S_RESRDY    31
33352 #define V_RESRDY(x) ((x) << S_RESRDY)
33353 #define F_RESRDY    V_RESRDY(1U)
33354 
33355 #define S_STATE    28
33356 #define M_STATE    0x7U
33357 #define V_STATE(x) ((x) << S_STATE)
33358 #define G_STATE(x) (((x) >> S_STATE) & M_STATE)
33359 
33360 #define S_FIFOCPL5RXVALID    27
33361 #define V_FIFOCPL5RXVALID(x) ((x) << S_FIFOCPL5RXVALID)
33362 #define F_FIFOCPL5RXVALID    V_FIFOCPL5RXVALID(1U)
33363 
33364 #define S_FIFOETHRXVALID    26
33365 #define V_FIFOETHRXVALID(x) ((x) << S_FIFOETHRXVALID)
33366 #define F_FIFOETHRXVALID    V_FIFOETHRXVALID(1U)
33367 
33368 #define S_FIFOETHRXSOCP    25
33369 #define V_FIFOETHRXSOCP(x) ((x) << S_FIFOETHRXSOCP)
33370 #define F_FIFOETHRXSOCP    V_FIFOETHRXSOCP(1U)
33371 
33372 #define S_FIFOPLDRXZEROP    24
33373 #define V_FIFOPLDRXZEROP(x) ((x) << S_FIFOPLDRXZEROP)
33374 #define F_FIFOPLDRXZEROP    V_FIFOPLDRXZEROP(1U)
33375 
33376 #define S_PLDRXVALID    23
33377 #define V_PLDRXVALID(x) ((x) << S_PLDRXVALID)
33378 #define F_PLDRXVALID    V_PLDRXVALID(1U)
33379 
33380 #define S_FIFOPLDRXZEROP_SRDY    22
33381 #define V_FIFOPLDRXZEROP_SRDY(x) ((x) << S_FIFOPLDRXZEROP_SRDY)
33382 #define F_FIFOPLDRXZEROP_SRDY    V_FIFOPLDRXZEROP_SRDY(1U)
33383 
33384 #define S_FIFOIPRXVALID    21
33385 #define V_FIFOIPRXVALID(x) ((x) << S_FIFOIPRXVALID)
33386 #define F_FIFOIPRXVALID    V_FIFOIPRXVALID(1U)
33387 
33388 #define S_FIFOTCPRXVALID    20
33389 #define V_FIFOTCPRXVALID(x) ((x) << S_FIFOTCPRXVALID)
33390 #define F_FIFOTCPRXVALID    V_FIFOTCPRXVALID(1U)
33391 
33392 #define S_PLDRXCSUMVALID    19
33393 #define V_PLDRXCSUMVALID(x) ((x) << S_PLDRXCSUMVALID)
33394 #define F_PLDRXCSUMVALID    V_PLDRXCSUMVALID(1U)
33395 
33396 #define S_FIFOIPCSUMSRDY    18
33397 #define V_FIFOIPCSUMSRDY(x) ((x) << S_FIFOIPCSUMSRDY)
33398 #define F_FIFOIPCSUMSRDY    V_FIFOIPCSUMSRDY(1U)
33399 
33400 #define S_FIFOIPPSEUDOCSUMSRDY    17
33401 #define V_FIFOIPPSEUDOCSUMSRDY(x) ((x) << S_FIFOIPPSEUDOCSUMSRDY)
33402 #define F_FIFOIPPSEUDOCSUMSRDY    V_FIFOIPPSEUDOCSUMSRDY(1U)
33403 
33404 #define S_FIFOTCPCSUMSRDY    16
33405 #define V_FIFOTCPCSUMSRDY(x) ((x) << S_FIFOTCPCSUMSRDY)
33406 #define F_FIFOTCPCSUMSRDY    V_FIFOTCPCSUMSRDY(1U)
33407 
33408 #define S_ESTATIC4    12
33409 #define M_ESTATIC4    0xfU
33410 #define V_ESTATIC4(x) ((x) << S_ESTATIC4)
33411 #define G_ESTATIC4(x) (((x) >> S_ESTATIC4) & M_ESTATIC4)
33412 
33413 #define S_FIFOCPLSOCPCNT    10
33414 #define M_FIFOCPLSOCPCNT    0x3U
33415 #define V_FIFOCPLSOCPCNT(x) ((x) << S_FIFOCPLSOCPCNT)
33416 #define G_FIFOCPLSOCPCNT(x) (((x) >> S_FIFOCPLSOCPCNT) & M_FIFOCPLSOCPCNT)
33417 
33418 #define S_FIFOETHSOCPCNT    8
33419 #define M_FIFOETHSOCPCNT    0x3U
33420 #define V_FIFOETHSOCPCNT(x) ((x) << S_FIFOETHSOCPCNT)
33421 #define G_FIFOETHSOCPCNT(x) (((x) >> S_FIFOETHSOCPCNT) & M_FIFOETHSOCPCNT)
33422 
33423 #define S_FIFOIPSOCPCNT    6
33424 #define M_FIFOIPSOCPCNT    0x3U
33425 #define V_FIFOIPSOCPCNT(x) ((x) << S_FIFOIPSOCPCNT)
33426 #define G_FIFOIPSOCPCNT(x) (((x) >> S_FIFOIPSOCPCNT) & M_FIFOIPSOCPCNT)
33427 
33428 #define S_FIFOTCPSOCPCNT    4
33429 #define M_FIFOTCPSOCPCNT    0x3U
33430 #define V_FIFOTCPSOCPCNT(x) ((x) << S_FIFOTCPSOCPCNT)
33431 #define G_FIFOTCPSOCPCNT(x) (((x) >> S_FIFOTCPSOCPCNT) & M_FIFOTCPSOCPCNT)
33432 
33433 #define S_PLD_RXZEROP_CNT    2
33434 #define M_PLD_RXZEROP_CNT    0x3U
33435 #define V_PLD_RXZEROP_CNT(x) ((x) << S_PLD_RXZEROP_CNT)
33436 #define G_PLD_RXZEROP_CNT(x) (((x) >> S_PLD_RXZEROP_CNT) & M_PLD_RXZEROP_CNT)
33437 
33438 #define S_ESTATIC6    1
33439 #define V_ESTATIC6(x) ((x) << S_ESTATIC6)
33440 #define F_ESTATIC6    V_ESTATIC6(1U)
33441 
33442 #define S_TXFULL    0
33443 #define V_TXFULL(x) ((x) << S_TXFULL)
33444 #define F_TXFULL    V_TXFULL(1U)
33445 
33446 #define S_FIFOGRERXVALID    15
33447 #define V_FIFOGRERXVALID(x) ((x) << S_FIFOGRERXVALID)
33448 #define F_FIFOGRERXVALID    V_FIFOGRERXVALID(1U)
33449 
33450 #define S_FIFOGRERXREADY    14
33451 #define V_FIFOGRERXREADY(x) ((x) << S_FIFOGRERXREADY)
33452 #define F_FIFOGRERXREADY    V_FIFOGRERXREADY(1U)
33453 
33454 #define S_FIFOGRERXSOCP    13
33455 #define V_FIFOGRERXSOCP(x) ((x) << S_FIFOGRERXSOCP)
33456 #define F_FIFOGRERXSOCP    V_FIFOGRERXSOCP(1U)
33457 
33458 #define S_T6_ESTATIC4    12
33459 #define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4)
33460 #define F_T6_ESTATIC4    V_T6_ESTATIC4(1U)
33461 
33462 #define S_TXFULL_ESIDE0    0
33463 #define V_TXFULL_ESIDE0(x) ((x) << S_TXFULL_ESIDE0)
33464 #define F_TXFULL_ESIDE0    V_TXFULL_ESIDE0(1U)
33465 
33466 #define A_TP_DBG_ESIDE_DISP1 0x137
33467 
33468 #define S_TXFULL_ESIDE1    0
33469 #define V_TXFULL_ESIDE1(x) ((x) << S_TXFULL_ESIDE1)
33470 #define F_TXFULL_ESIDE1    V_TXFULL_ESIDE1(1U)
33471 
33472 #define A_TP_MAC_MATCH_MAP0 0x138
33473 
33474 #define S_MAPVALUEWR    16
33475 #define M_MAPVALUEWR    0xffU
33476 #define V_MAPVALUEWR(x) ((x) << S_MAPVALUEWR)
33477 #define G_MAPVALUEWR(x) (((x) >> S_MAPVALUEWR) & M_MAPVALUEWR)
33478 
33479 #define S_MAPINDEX    2
33480 #define M_MAPINDEX    0x1ffU
33481 #define V_MAPINDEX(x) ((x) << S_MAPINDEX)
33482 #define G_MAPINDEX(x) (((x) >> S_MAPINDEX) & M_MAPINDEX)
33483 
33484 #define S_MAPREAD    1
33485 #define V_MAPREAD(x) ((x) << S_MAPREAD)
33486 #define F_MAPREAD    V_MAPREAD(1U)
33487 
33488 #define S_MAPWRITE    0
33489 #define V_MAPWRITE(x) ((x) << S_MAPWRITE)
33490 #define F_MAPWRITE    V_MAPWRITE(1U)
33491 
33492 #define A_TP_MAC_MATCH_MAP1 0x139
33493 
33494 #define S_MAPVALUERD    0
33495 #define M_MAPVALUERD    0x1ffU
33496 #define V_MAPVALUERD(x) ((x) << S_MAPVALUERD)
33497 #define G_MAPVALUERD(x) (((x) >> S_MAPVALUERD) & M_MAPVALUERD)
33498 
33499 #define A_TP_DBG_ESIDE_DISP2 0x13a
33500 
33501 #define S_TXFULL_ESIDE2    0
33502 #define V_TXFULL_ESIDE2(x) ((x) << S_TXFULL_ESIDE2)
33503 #define F_TXFULL_ESIDE2    V_TXFULL_ESIDE2(1U)
33504 
33505 #define A_TP_DBG_ESIDE_DISP3 0x13b
33506 
33507 #define S_TXFULL_ESIDE3    0
33508 #define V_TXFULL_ESIDE3(x) ((x) << S_TXFULL_ESIDE3)
33509 #define F_TXFULL_ESIDE3    V_TXFULL_ESIDE3(1U)
33510 
33511 #define A_TP_DBG_ESIDE_HDR0 0x13c
33512 
33513 #define S_TCPSOPCNT    28
33514 #define M_TCPSOPCNT    0xfU
33515 #define V_TCPSOPCNT(x) ((x) << S_TCPSOPCNT)
33516 #define G_TCPSOPCNT(x) (((x) >> S_TCPSOPCNT) & M_TCPSOPCNT)
33517 
33518 #define S_TCPEOPCNT    24
33519 #define M_TCPEOPCNT    0xfU
33520 #define V_TCPEOPCNT(x) ((x) << S_TCPEOPCNT)
33521 #define G_TCPEOPCNT(x) (((x) >> S_TCPEOPCNT) & M_TCPEOPCNT)
33522 
33523 #define S_IPSOPCNT    20
33524 #define M_IPSOPCNT    0xfU
33525 #define V_IPSOPCNT(x) ((x) << S_IPSOPCNT)
33526 #define G_IPSOPCNT(x) (((x) >> S_IPSOPCNT) & M_IPSOPCNT)
33527 
33528 #define S_IPEOPCNT    16
33529 #define M_IPEOPCNT    0xfU
33530 #define V_IPEOPCNT(x) ((x) << S_IPEOPCNT)
33531 #define G_IPEOPCNT(x) (((x) >> S_IPEOPCNT) & M_IPEOPCNT)
33532 
33533 #define S_ETHSOPCNT    12
33534 #define M_ETHSOPCNT    0xfU
33535 #define V_ETHSOPCNT(x) ((x) << S_ETHSOPCNT)
33536 #define G_ETHSOPCNT(x) (((x) >> S_ETHSOPCNT) & M_ETHSOPCNT)
33537 
33538 #define S_ETHEOPCNT    8
33539 #define M_ETHEOPCNT    0xfU
33540 #define V_ETHEOPCNT(x) ((x) << S_ETHEOPCNT)
33541 #define G_ETHEOPCNT(x) (((x) >> S_ETHEOPCNT) & M_ETHEOPCNT)
33542 
33543 #define S_CPLSOPCNT    4
33544 #define M_CPLSOPCNT    0xfU
33545 #define V_CPLSOPCNT(x) ((x) << S_CPLSOPCNT)
33546 #define G_CPLSOPCNT(x) (((x) >> S_CPLSOPCNT) & M_CPLSOPCNT)
33547 
33548 #define S_CPLEOPCNT    0
33549 #define M_CPLEOPCNT    0xfU
33550 #define V_CPLEOPCNT(x) ((x) << S_CPLEOPCNT)
33551 #define G_CPLEOPCNT(x) (((x) >> S_CPLEOPCNT) & M_CPLEOPCNT)
33552 
33553 #define A_TP_DBG_ESIDE_HDR1 0x13d
33554 #define A_TP_DBG_ESIDE_HDR2 0x13e
33555 #define A_TP_DBG_ESIDE_HDR3 0x13f
33556 #define A_TP_VLAN_PRI_MAP 0x140
33557 
33558 #define S_FRAGMENTATION    9
33559 #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
33560 #define F_FRAGMENTATION    V_FRAGMENTATION(1U)
33561 
33562 #define S_MPSHITTYPE    8
33563 #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
33564 #define F_MPSHITTYPE    V_MPSHITTYPE(1U)
33565 
33566 #define S_MACMATCH    7
33567 #define V_MACMATCH(x) ((x) << S_MACMATCH)
33568 #define F_MACMATCH    V_MACMATCH(1U)
33569 
33570 #define S_ETHERTYPE    6
33571 #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
33572 #define F_ETHERTYPE    V_ETHERTYPE(1U)
33573 
33574 #define S_PROTOCOL    5
33575 #define V_PROTOCOL(x) ((x) << S_PROTOCOL)
33576 #define F_PROTOCOL    V_PROTOCOL(1U)
33577 
33578 #define S_TOS    4
33579 #define V_TOS(x) ((x) << S_TOS)
33580 #define F_TOS    V_TOS(1U)
33581 
33582 #define S_VLAN    3
33583 #define V_VLAN(x) ((x) << S_VLAN)
33584 #define F_VLAN    V_VLAN(1U)
33585 
33586 #define S_VNIC_ID    2
33587 #define V_VNIC_ID(x) ((x) << S_VNIC_ID)
33588 #define F_VNIC_ID    V_VNIC_ID(1U)
33589 
33590 #define S_PORT    1
33591 #define V_PORT(x) ((x) << S_PORT)
33592 #define F_PORT    V_PORT(1U)
33593 
33594 #define S_FCOE    0
33595 #define V_FCOE(x) ((x) << S_FCOE)
33596 #define F_FCOE    V_FCOE(1U)
33597 
33598 #define S_FILTERMODE    15
33599 #define V_FILTERMODE(x) ((x) << S_FILTERMODE)
33600 #define F_FILTERMODE    V_FILTERMODE(1U)
33601 
33602 #define S_FCOEMASK    14
33603 #define V_FCOEMASK(x) ((x) << S_FCOEMASK)
33604 #define F_FCOEMASK    V_FCOEMASK(1U)
33605 
33606 #define S_SRVRSRAM    13
33607 #define V_SRVRSRAM(x) ((x) << S_SRVRSRAM)
33608 #define F_SRVRSRAM    V_SRVRSRAM(1U)
33609 
33610 #define S_T7_FILTERMODE    31
33611 #define V_T7_FILTERMODE(x) ((x) << S_T7_FILTERMODE)
33612 #define F_T7_FILTERMODE    V_T7_FILTERMODE(1U)
33613 
33614 #define S_T7_FCOEMASK    30
33615 #define V_T7_FCOEMASK(x) ((x) << S_T7_FCOEMASK)
33616 #define F_T7_FCOEMASK    V_T7_FCOEMASK(1U)
33617 
33618 #define S_T7_SRVRSRAM    29
33619 #define V_T7_SRVRSRAM(x) ((x) << S_T7_SRVRSRAM)
33620 #define F_T7_SRVRSRAM    V_T7_SRVRSRAM(1U)
33621 
33622 #define S_ROCEUDFORCEIPV6    28
33623 #define V_ROCEUDFORCEIPV6(x) ((x) << S_ROCEUDFORCEIPV6)
33624 #define F_ROCEUDFORCEIPV6    V_ROCEUDFORCEIPV6(1U)
33625 
33626 #define S_TCPFLAGS8    27
33627 #define V_TCPFLAGS8(x) ((x) << S_TCPFLAGS8)
33628 #define F_TCPFLAGS8    V_TCPFLAGS8(1U)
33629 
33630 #define S_MACMATCH11    26
33631 #define V_MACMATCH11(x) ((x) << S_MACMATCH11)
33632 #define F_MACMATCH11    V_MACMATCH11(1U)
33633 
33634 #define S_SMACMATCH10    25
33635 #define V_SMACMATCH10(x) ((x) << S_SMACMATCH10)
33636 #define F_SMACMATCH10    V_SMACMATCH10(1U)
33637 
33638 #define S_SMACMATCH    14
33639 #define V_SMACMATCH(x) ((x) << S_SMACMATCH)
33640 #define F_SMACMATCH    V_SMACMATCH(1U)
33641 
33642 #define S_TCPFLAGS    13
33643 #define V_TCPFLAGS(x) ((x) << S_TCPFLAGS)
33644 #define F_TCPFLAGS    V_TCPFLAGS(1U)
33645 
33646 #define S_SYNONLY    12
33647 #define V_SYNONLY(x) ((x) << S_SYNONLY)
33648 #define F_SYNONLY    V_SYNONLY(1U)
33649 
33650 #define S_ROCE    11
33651 #define V_ROCE(x) ((x) << S_ROCE)
33652 #define F_ROCE    V_ROCE(1U)
33653 
33654 #define S_T7_FRAGMENTATION    10
33655 #define V_T7_FRAGMENTATION(x) ((x) << S_T7_FRAGMENTATION)
33656 #define F_T7_FRAGMENTATION    V_T7_FRAGMENTATION(1U)
33657 
33658 #define S_T7_MPSHITTYPE    9
33659 #define V_T7_MPSHITTYPE(x) ((x) << S_T7_MPSHITTYPE)
33660 #define F_T7_MPSHITTYPE    V_T7_MPSHITTYPE(1U)
33661 
33662 #define S_T7_MACMATCH    8
33663 #define V_T7_MACMATCH(x) ((x) << S_T7_MACMATCH)
33664 #define F_T7_MACMATCH    V_T7_MACMATCH(1U)
33665 
33666 #define S_T7_ETHERTYPE    7
33667 #define V_T7_ETHERTYPE(x) ((x) << S_T7_ETHERTYPE)
33668 #define F_T7_ETHERTYPE    V_T7_ETHERTYPE(1U)
33669 
33670 #define S_T7_PROTOCOL    6
33671 #define V_T7_PROTOCOL(x) ((x) << S_T7_PROTOCOL)
33672 #define F_T7_PROTOCOL    V_T7_PROTOCOL(1U)
33673 
33674 #define S_T7_TOS    5
33675 #define V_T7_TOS(x) ((x) << S_T7_TOS)
33676 #define F_T7_TOS    V_T7_TOS(1U)
33677 
33678 #define S_T7_VLAN    4
33679 #define V_T7_VLAN(x) ((x) << S_T7_VLAN)
33680 #define F_T7_VLAN    V_T7_VLAN(1U)
33681 
33682 #define S_T7_VNIC_ID    3
33683 #define V_T7_VNIC_ID(x) ((x) << S_T7_VNIC_ID)
33684 #define F_T7_VNIC_ID    V_T7_VNIC_ID(1U)
33685 
33686 #define S_T7_PORT    2
33687 #define V_T7_PORT(x) ((x) << S_T7_PORT)
33688 #define F_T7_PORT    V_T7_PORT(1U)
33689 
33690 #define S_T7_FCOE    1
33691 #define V_T7_FCOE(x) ((x) << S_T7_FCOE)
33692 #define F_T7_FCOE    V_T7_FCOE(1U)
33693 
33694 #define S_IPSECIDX    0
33695 #define V_IPSECIDX(x) ((x) << S_IPSECIDX)
33696 #define F_IPSECIDX    V_IPSECIDX(1U)
33697 
33698 #define A_TP_INGRESS_CONFIG 0x141
33699 
33700 #define S_OPAQUE_TYPE    16
33701 #define M_OPAQUE_TYPE    0xffffU
33702 #define V_OPAQUE_TYPE(x) ((x) << S_OPAQUE_TYPE)
33703 #define G_OPAQUE_TYPE(x) (((x) >> S_OPAQUE_TYPE) & M_OPAQUE_TYPE)
33704 
33705 #define S_OPAQUE_RM    15
33706 #define V_OPAQUE_RM(x) ((x) << S_OPAQUE_RM)
33707 #define F_OPAQUE_RM    V_OPAQUE_RM(1U)
33708 
33709 #define S_OPAQUE_HDR_SIZE    14
33710 #define V_OPAQUE_HDR_SIZE(x) ((x) << S_OPAQUE_HDR_SIZE)
33711 #define F_OPAQUE_HDR_SIZE    V_OPAQUE_HDR_SIZE(1U)
33712 
33713 #define S_OPAQUE_RM_MAC_IN_MAC    13
33714 #define V_OPAQUE_RM_MAC_IN_MAC(x) ((x) << S_OPAQUE_RM_MAC_IN_MAC)
33715 #define F_OPAQUE_RM_MAC_IN_MAC    V_OPAQUE_RM_MAC_IN_MAC(1U)
33716 
33717 #define S_FCOE_TARGET    12
33718 #define V_FCOE_TARGET(x) ((x) << S_FCOE_TARGET)
33719 #define F_FCOE_TARGET    V_FCOE_TARGET(1U)
33720 
33721 #define S_VNIC    11
33722 #define V_VNIC(x) ((x) << S_VNIC)
33723 #define F_VNIC    V_VNIC(1U)
33724 
33725 #define S_CSUM_HAS_PSEUDO_HDR    10
33726 #define V_CSUM_HAS_PSEUDO_HDR(x) ((x) << S_CSUM_HAS_PSEUDO_HDR)
33727 #define F_CSUM_HAS_PSEUDO_HDR    V_CSUM_HAS_PSEUDO_HDR(1U)
33728 
33729 #define S_RM_OVLAN    9
33730 #define V_RM_OVLAN(x) ((x) << S_RM_OVLAN)
33731 #define F_RM_OVLAN    V_RM_OVLAN(1U)
33732 
33733 #define S_LOOKUPEVERYPKT    8
33734 #define V_LOOKUPEVERYPKT(x) ((x) << S_LOOKUPEVERYPKT)
33735 #define F_LOOKUPEVERYPKT    V_LOOKUPEVERYPKT(1U)
33736 
33737 #define S_IPV6_EXT_HDR_SKIP    0
33738 #define M_IPV6_EXT_HDR_SKIP    0xffU
33739 #define V_IPV6_EXT_HDR_SKIP(x) ((x) << S_IPV6_EXT_HDR_SKIP)
33740 #define G_IPV6_EXT_HDR_SKIP(x) (((x) >> S_IPV6_EXT_HDR_SKIP) & M_IPV6_EXT_HDR_SKIP)
33741 
33742 #define S_FRAG_LEN_MOD8_COMPAT    12
33743 #define V_FRAG_LEN_MOD8_COMPAT(x) ((x) << S_FRAG_LEN_MOD8_COMPAT)
33744 #define F_FRAG_LEN_MOD8_COMPAT    V_FRAG_LEN_MOD8_COMPAT(1U)
33745 
33746 #define S_USE_ENC_IDX    13
33747 #define V_USE_ENC_IDX(x) ((x) << S_USE_ENC_IDX)
33748 #define F_USE_ENC_IDX    V_USE_ENC_IDX(1U)
33749 
33750 #define S_USE_MPS_ECN    15
33751 #define V_USE_MPS_ECN(x) ((x) << S_USE_MPS_ECN)
33752 #define F_USE_MPS_ECN    V_USE_MPS_ECN(1U)
33753 
33754 #define S_USE_MPS_CONG    14
33755 #define V_USE_MPS_CONG(x) ((x) << S_USE_MPS_CONG)
33756 #define F_USE_MPS_CONG    V_USE_MPS_CONG(1U)
33757 
33758 #define A_TP_TX_DROP_CFG_CH2 0x142
33759 #define A_TP_TX_DROP_CFG_CH3 0x143
33760 #define A_TP_EGRESS_CONFIG 0x145
33761 
33762 #define S_REWRITEFORCETOSIZE    0
33763 #define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE)
33764 #define F_REWRITEFORCETOSIZE    V_REWRITEFORCETOSIZE(1U)
33765 
33766 #define A_TP_INGRESS_CONFIG2 0x145
33767 
33768 #define S_IPV6_UDP_CSUM_COMPAT    31
33769 #define V_IPV6_UDP_CSUM_COMPAT(x) ((x) << S_IPV6_UDP_CSUM_COMPAT)
33770 #define F_IPV6_UDP_CSUM_COMPAT    V_IPV6_UDP_CSUM_COMPAT(1U)
33771 
33772 #define S_VNTAGPLDENABLE    30
33773 #define V_VNTAGPLDENABLE(x) ((x) << S_VNTAGPLDENABLE)
33774 #define F_VNTAGPLDENABLE    V_VNTAGPLDENABLE(1U)
33775 
33776 #define S_TCP_PLD_FILTER_OFFSET    20
33777 #define M_TCP_PLD_FILTER_OFFSET    0x3ffU
33778 #define V_TCP_PLD_FILTER_OFFSET(x) ((x) << S_TCP_PLD_FILTER_OFFSET)
33779 #define G_TCP_PLD_FILTER_OFFSET(x) (((x) >> S_TCP_PLD_FILTER_OFFSET) & M_TCP_PLD_FILTER_OFFSET)
33780 
33781 #define S_UDP_PLD_FILTER_OFFSET    10
33782 #define M_UDP_PLD_FILTER_OFFSET    0x3ffU
33783 #define V_UDP_PLD_FILTER_OFFSET(x) ((x) << S_UDP_PLD_FILTER_OFFSET)
33784 #define G_UDP_PLD_FILTER_OFFSET(x) (((x) >> S_UDP_PLD_FILTER_OFFSET) & M_UDP_PLD_FILTER_OFFSET)
33785 
33786 #define S_TNL_PLD_FILTER_OFFSET    0
33787 #define M_TNL_PLD_FILTER_OFFSET    0x3ffU
33788 #define V_TNL_PLD_FILTER_OFFSET(x) ((x) << S_TNL_PLD_FILTER_OFFSET)
33789 #define G_TNL_PLD_FILTER_OFFSET(x) (((x) >> S_TNL_PLD_FILTER_OFFSET) & M_TNL_PLD_FILTER_OFFSET)
33790 
33791 #define A_TP_EHDR_CONFIG_LO 0x146
33792 
33793 #define S_CPLLIMIT    24
33794 #define M_CPLLIMIT    0xffU
33795 #define V_CPLLIMIT(x) ((x) << S_CPLLIMIT)
33796 #define G_CPLLIMIT(x) (((x) >> S_CPLLIMIT) & M_CPLLIMIT)
33797 
33798 #define S_ETHLIMIT    16
33799 #define M_ETHLIMIT    0xffU
33800 #define V_ETHLIMIT(x) ((x) << S_ETHLIMIT)
33801 #define G_ETHLIMIT(x) (((x) >> S_ETHLIMIT) & M_ETHLIMIT)
33802 
33803 #define S_IPLIMIT    8
33804 #define M_IPLIMIT    0xffU
33805 #define V_IPLIMIT(x) ((x) << S_IPLIMIT)
33806 #define G_IPLIMIT(x) (((x) >> S_IPLIMIT) & M_IPLIMIT)
33807 
33808 #define S_TCPLIMIT    0
33809 #define M_TCPLIMIT    0xffU
33810 #define V_TCPLIMIT(x) ((x) << S_TCPLIMIT)
33811 #define G_TCPLIMIT(x) (((x) >> S_TCPLIMIT) & M_TCPLIMIT)
33812 
33813 #define A_TP_EHDR_CONFIG_HI 0x147
33814 #define A_TP_DBG_ESIDE_INT 0x148
33815 
33816 #define S_ERXSOP2X    28
33817 #define M_ERXSOP2X    0xfU
33818 #define V_ERXSOP2X(x) ((x) << S_ERXSOP2X)
33819 #define G_ERXSOP2X(x) (((x) >> S_ERXSOP2X) & M_ERXSOP2X)
33820 
33821 #define S_ERXEOP2X    24
33822 #define M_ERXEOP2X    0xfU
33823 #define V_ERXEOP2X(x) ((x) << S_ERXEOP2X)
33824 #define G_ERXEOP2X(x) (((x) >> S_ERXEOP2X) & M_ERXEOP2X)
33825 
33826 #define S_ERXVALID2X    20
33827 #define M_ERXVALID2X    0xfU
33828 #define V_ERXVALID2X(x) ((x) << S_ERXVALID2X)
33829 #define G_ERXVALID2X(x) (((x) >> S_ERXVALID2X) & M_ERXVALID2X)
33830 
33831 #define S_ERXAFULL2X    16
33832 #define M_ERXAFULL2X    0xfU
33833 #define V_ERXAFULL2X(x) ((x) << S_ERXAFULL2X)
33834 #define G_ERXAFULL2X(x) (((x) >> S_ERXAFULL2X) & M_ERXAFULL2X)
33835 
33836 #define S_PLD2XTXVALID    12
33837 #define M_PLD2XTXVALID    0xfU
33838 #define V_PLD2XTXVALID(x) ((x) << S_PLD2XTXVALID)
33839 #define G_PLD2XTXVALID(x) (((x) >> S_PLD2XTXVALID) & M_PLD2XTXVALID)
33840 
33841 #define S_PLD2XTXAFULL    8
33842 #define M_PLD2XTXAFULL    0xfU
33843 #define V_PLD2XTXAFULL(x) ((x) << S_PLD2XTXAFULL)
33844 #define G_PLD2XTXAFULL(x) (((x) >> S_PLD2XTXAFULL) & M_PLD2XTXAFULL)
33845 
33846 #define S_ERRORSRDY    7
33847 #define V_ERRORSRDY(x) ((x) << S_ERRORSRDY)
33848 #define F_ERRORSRDY    V_ERRORSRDY(1U)
33849 
33850 #define S_ERRORDRDY    6
33851 #define V_ERRORDRDY(x) ((x) << S_ERRORDRDY)
33852 #define F_ERRORDRDY    V_ERRORDRDY(1U)
33853 
33854 #define S_TCPOPSRDY    5
33855 #define V_TCPOPSRDY(x) ((x) << S_TCPOPSRDY)
33856 #define F_TCPOPSRDY    V_TCPOPSRDY(1U)
33857 
33858 #define S_TCPOPDRDY    4
33859 #define V_TCPOPDRDY(x) ((x) << S_TCPOPDRDY)
33860 #define F_TCPOPDRDY    V_TCPOPDRDY(1U)
33861 
33862 #define S_PLDTXSRDY    3
33863 #define V_PLDTXSRDY(x) ((x) << S_PLDTXSRDY)
33864 #define F_PLDTXSRDY    V_PLDTXSRDY(1U)
33865 
33866 #define S_PLDTXDRDY    2
33867 #define V_PLDTXDRDY(x) ((x) << S_PLDTXDRDY)
33868 #define F_PLDTXDRDY    V_PLDTXDRDY(1U)
33869 
33870 #define S_TCPOPTTXVALID    1
33871 #define V_TCPOPTTXVALID(x) ((x) << S_TCPOPTTXVALID)
33872 #define F_TCPOPTTXVALID    V_TCPOPTTXVALID(1U)
33873 
33874 #define S_TCPOPTTXFULL    0
33875 #define V_TCPOPTTXFULL(x) ((x) << S_TCPOPTTXFULL)
33876 #define F_TCPOPTTXFULL    V_TCPOPTTXFULL(1U)
33877 
33878 #define S_PKTATTRSRDY    3
33879 #define V_PKTATTRSRDY(x) ((x) << S_PKTATTRSRDY)
33880 #define F_PKTATTRSRDY    V_PKTATTRSRDY(1U)
33881 
33882 #define S_PKTATTRDRDY    2
33883 #define V_PKTATTRDRDY(x) ((x) << S_PKTATTRDRDY)
33884 #define F_PKTATTRDRDY    V_PKTATTRDRDY(1U)
33885 
33886 #define A_TP_DBG_ESIDE_DEMUX 0x149
33887 
33888 #define S_EALLDONE    28
33889 #define M_EALLDONE    0xfU
33890 #define V_EALLDONE(x) ((x) << S_EALLDONE)
33891 #define G_EALLDONE(x) (((x) >> S_EALLDONE) & M_EALLDONE)
33892 
33893 #define S_EFIFOPLDDONE    24
33894 #define M_EFIFOPLDDONE    0xfU
33895 #define V_EFIFOPLDDONE(x) ((x) << S_EFIFOPLDDONE)
33896 #define G_EFIFOPLDDONE(x) (((x) >> S_EFIFOPLDDONE) & M_EFIFOPLDDONE)
33897 
33898 #define S_EDBDONE    20
33899 #define M_EDBDONE    0xfU
33900 #define V_EDBDONE(x) ((x) << S_EDBDONE)
33901 #define G_EDBDONE(x) (((x) >> S_EDBDONE) & M_EDBDONE)
33902 
33903 #define S_EISSFIFODONE    16
33904 #define M_EISSFIFODONE    0xfU
33905 #define V_EISSFIFODONE(x) ((x) << S_EISSFIFODONE)
33906 #define G_EISSFIFODONE(x) (((x) >> S_EISSFIFODONE) & M_EISSFIFODONE)
33907 
33908 #define S_EACKERRFIFODONE    12
33909 #define M_EACKERRFIFODONE    0xfU
33910 #define V_EACKERRFIFODONE(x) ((x) << S_EACKERRFIFODONE)
33911 #define G_EACKERRFIFODONE(x) (((x) >> S_EACKERRFIFODONE) & M_EACKERRFIFODONE)
33912 
33913 #define S_EFIFOERRORDONE    8
33914 #define M_EFIFOERRORDONE    0xfU
33915 #define V_EFIFOERRORDONE(x) ((x) << S_EFIFOERRORDONE)
33916 #define G_EFIFOERRORDONE(x) (((x) >> S_EFIFOERRORDONE) & M_EFIFOERRORDONE)
33917 
33918 #define S_ERXPKTATTRFIFOFDONE    4
33919 #define M_ERXPKTATTRFIFOFDONE    0xfU
33920 #define V_ERXPKTATTRFIFOFDONE(x) ((x) << S_ERXPKTATTRFIFOFDONE)
33921 #define G_ERXPKTATTRFIFOFDONE(x) (((x) >> S_ERXPKTATTRFIFOFDONE) & M_ERXPKTATTRFIFOFDONE)
33922 
33923 #define S_ETCPOPDONE    0
33924 #define M_ETCPOPDONE    0xfU
33925 #define V_ETCPOPDONE(x) ((x) << S_ETCPOPDONE)
33926 #define G_ETCPOPDONE(x) (((x) >> S_ETCPOPDONE) & M_ETCPOPDONE)
33927 
33928 #define A_TP_DBG_ESIDE_IN0 0x14a
33929 
33930 #define S_RXVALID    31
33931 #define V_RXVALID(x) ((x) << S_RXVALID)
33932 #define F_RXVALID    V_RXVALID(1U)
33933 
33934 #define S_RXFULL    30
33935 #define V_RXFULL(x) ((x) << S_RXFULL)
33936 #define F_RXFULL    V_RXFULL(1U)
33937 
33938 #define S_RXSOCP    29
33939 #define V_RXSOCP(x) ((x) << S_RXSOCP)
33940 #define F_RXSOCP    V_RXSOCP(1U)
33941 
33942 #define S_RXEOP    28
33943 #define V_RXEOP(x) ((x) << S_RXEOP)
33944 #define F_RXEOP    V_RXEOP(1U)
33945 
33946 #define S_RXVALID_I    27
33947 #define V_RXVALID_I(x) ((x) << S_RXVALID_I)
33948 #define F_RXVALID_I    V_RXVALID_I(1U)
33949 
33950 #define S_RXFULL_I    26
33951 #define V_RXFULL_I(x) ((x) << S_RXFULL_I)
33952 #define F_RXFULL_I    V_RXFULL_I(1U)
33953 
33954 #define S_RXSOCP_I    25
33955 #define V_RXSOCP_I(x) ((x) << S_RXSOCP_I)
33956 #define F_RXSOCP_I    V_RXSOCP_I(1U)
33957 
33958 #define S_RXEOP_I    24
33959 #define V_RXEOP_I(x) ((x) << S_RXEOP_I)
33960 #define F_RXEOP_I    V_RXEOP_I(1U)
33961 
33962 #define S_RXVALID_I2    23
33963 #define V_RXVALID_I2(x) ((x) << S_RXVALID_I2)
33964 #define F_RXVALID_I2    V_RXVALID_I2(1U)
33965 
33966 #define S_RXFULL_I2    22
33967 #define V_RXFULL_I2(x) ((x) << S_RXFULL_I2)
33968 #define F_RXFULL_I2    V_RXFULL_I2(1U)
33969 
33970 #define S_RXSOCP_I2    21
33971 #define V_RXSOCP_I2(x) ((x) << S_RXSOCP_I2)
33972 #define F_RXSOCP_I2    V_RXSOCP_I2(1U)
33973 
33974 #define S_RXEOP_I2    20
33975 #define V_RXEOP_I2(x) ((x) << S_RXEOP_I2)
33976 #define F_RXEOP_I2    V_RXEOP_I2(1U)
33977 
33978 #define S_CT_MPA_TXVALID_FIFO    19
33979 #define V_CT_MPA_TXVALID_FIFO(x) ((x) << S_CT_MPA_TXVALID_FIFO)
33980 #define F_CT_MPA_TXVALID_FIFO    V_CT_MPA_TXVALID_FIFO(1U)
33981 
33982 #define S_CT_MPA_TXFULL_FIFO    18
33983 #define V_CT_MPA_TXFULL_FIFO(x) ((x) << S_CT_MPA_TXFULL_FIFO)
33984 #define F_CT_MPA_TXFULL_FIFO    V_CT_MPA_TXFULL_FIFO(1U)
33985 
33986 #define S_CT_MPA_TXVALID    17
33987 #define V_CT_MPA_TXVALID(x) ((x) << S_CT_MPA_TXVALID)
33988 #define F_CT_MPA_TXVALID    V_CT_MPA_TXVALID(1U)
33989 
33990 #define S_CT_MPA_TXFULL    16
33991 #define V_CT_MPA_TXFULL(x) ((x) << S_CT_MPA_TXFULL)
33992 #define F_CT_MPA_TXFULL    V_CT_MPA_TXFULL(1U)
33993 
33994 #define S_RXVALID_BUF    15
33995 #define V_RXVALID_BUF(x) ((x) << S_RXVALID_BUF)
33996 #define F_RXVALID_BUF    V_RXVALID_BUF(1U)
33997 
33998 #define S_RXFULL_BUF    14
33999 #define V_RXFULL_BUF(x) ((x) << S_RXFULL_BUF)
34000 #define F_RXFULL_BUF    V_RXFULL_BUF(1U)
34001 
34002 #define S_PLD_TXVALID    13
34003 #define V_PLD_TXVALID(x) ((x) << S_PLD_TXVALID)
34004 #define F_PLD_TXVALID    V_PLD_TXVALID(1U)
34005 
34006 #define S_PLD_TXFULL    12
34007 #define V_PLD_TXFULL(x) ((x) << S_PLD_TXFULL)
34008 #define F_PLD_TXFULL    V_PLD_TXFULL(1U)
34009 
34010 #define S_ISS_FIFO_SRDY    11
34011 #define V_ISS_FIFO_SRDY(x) ((x) << S_ISS_FIFO_SRDY)
34012 #define F_ISS_FIFO_SRDY    V_ISS_FIFO_SRDY(1U)
34013 
34014 #define S_ISS_FIFO_DRDY    10
34015 #define V_ISS_FIFO_DRDY(x) ((x) << S_ISS_FIFO_DRDY)
34016 #define F_ISS_FIFO_DRDY    V_ISS_FIFO_DRDY(1U)
34017 
34018 #define S_CT_TCP_OP_ISS_SRDY    9
34019 #define V_CT_TCP_OP_ISS_SRDY(x) ((x) << S_CT_TCP_OP_ISS_SRDY)
34020 #define F_CT_TCP_OP_ISS_SRDY    V_CT_TCP_OP_ISS_SRDY(1U)
34021 
34022 #define S_CT_TCP_OP_ISS_DRDY    8
34023 #define V_CT_TCP_OP_ISS_DRDY(x) ((x) << S_CT_TCP_OP_ISS_DRDY)
34024 #define F_CT_TCP_OP_ISS_DRDY    V_CT_TCP_OP_ISS_DRDY(1U)
34025 
34026 #define S_P2CSUMERROR_SRDY    7
34027 #define V_P2CSUMERROR_SRDY(x) ((x) << S_P2CSUMERROR_SRDY)
34028 #define F_P2CSUMERROR_SRDY    V_P2CSUMERROR_SRDY(1U)
34029 
34030 #define S_P2CSUMERROR_DRDY    6
34031 #define V_P2CSUMERROR_DRDY(x) ((x) << S_P2CSUMERROR_DRDY)
34032 #define F_P2CSUMERROR_DRDY    V_P2CSUMERROR_DRDY(1U)
34033 
34034 #define S_FIFO_ERROR_SRDY    5
34035 #define V_FIFO_ERROR_SRDY(x) ((x) << S_FIFO_ERROR_SRDY)
34036 #define F_FIFO_ERROR_SRDY    V_FIFO_ERROR_SRDY(1U)
34037 
34038 #define S_FIFO_ERROR_DRDY    4
34039 #define V_FIFO_ERROR_DRDY(x) ((x) << S_FIFO_ERROR_DRDY)
34040 #define F_FIFO_ERROR_DRDY    V_FIFO_ERROR_DRDY(1U)
34041 
34042 #define S_PLD_SRDY    3
34043 #define V_PLD_SRDY(x) ((x) << S_PLD_SRDY)
34044 #define F_PLD_SRDY    V_PLD_SRDY(1U)
34045 
34046 #define S_PLD_DRDY    2
34047 #define V_PLD_DRDY(x) ((x) << S_PLD_DRDY)
34048 #define F_PLD_DRDY    V_PLD_DRDY(1U)
34049 
34050 #define S_RX_PKT_ATTR_SRDY    1
34051 #define V_RX_PKT_ATTR_SRDY(x) ((x) << S_RX_PKT_ATTR_SRDY)
34052 #define F_RX_PKT_ATTR_SRDY    V_RX_PKT_ATTR_SRDY(1U)
34053 
34054 #define S_RX_PKT_ATTR_DRDY    0
34055 #define V_RX_PKT_ATTR_DRDY(x) ((x) << S_RX_PKT_ATTR_DRDY)
34056 #define F_RX_PKT_ATTR_DRDY    V_RX_PKT_ATTR_DRDY(1U)
34057 
34058 #define S_RXRUNT    25
34059 #define V_RXRUNT(x) ((x) << S_RXRUNT)
34060 #define F_RXRUNT    V_RXRUNT(1U)
34061 
34062 #define S_RXRUNTPARSER    24
34063 #define V_RXRUNTPARSER(x) ((x) << S_RXRUNTPARSER)
34064 #define F_RXRUNTPARSER    V_RXRUNTPARSER(1U)
34065 
34066 #define S_ERROR_SRDY    5
34067 #define V_ERROR_SRDY(x) ((x) << S_ERROR_SRDY)
34068 #define F_ERROR_SRDY    V_ERROR_SRDY(1U)
34069 
34070 #define S_ERROR_DRDY    4
34071 #define V_ERROR_DRDY(x) ((x) << S_ERROR_DRDY)
34072 #define F_ERROR_DRDY    V_ERROR_DRDY(1U)
34073 
34074 #define A_TP_DBG_ESIDE_IN1 0x14b
34075 #define A_TP_DBG_ESIDE_IN2 0x14c
34076 #define A_TP_DBG_ESIDE_IN3 0x14d
34077 #define A_TP_DBG_ESIDE_FRM 0x14e
34078 
34079 #define S_ERX2XERROR    28
34080 #define M_ERX2XERROR    0xfU
34081 #define V_ERX2XERROR(x) ((x) << S_ERX2XERROR)
34082 #define G_ERX2XERROR(x) (((x) >> S_ERX2XERROR) & M_ERX2XERROR)
34083 
34084 #define S_EPLDTX2XERROR    24
34085 #define M_EPLDTX2XERROR    0xfU
34086 #define V_EPLDTX2XERROR(x) ((x) << S_EPLDTX2XERROR)
34087 #define G_EPLDTX2XERROR(x) (((x) >> S_EPLDTX2XERROR) & M_EPLDTX2XERROR)
34088 
34089 #define S_ETXERROR    20
34090 #define M_ETXERROR    0xfU
34091 #define V_ETXERROR(x) ((x) << S_ETXERROR)
34092 #define G_ETXERROR(x) (((x) >> S_ETXERROR) & M_ETXERROR)
34093 
34094 #define S_EPLDRXERROR    16
34095 #define M_EPLDRXERROR    0xfU
34096 #define V_EPLDRXERROR(x) ((x) << S_EPLDRXERROR)
34097 #define G_EPLDRXERROR(x) (((x) >> S_EPLDRXERROR) & M_EPLDRXERROR)
34098 
34099 #define S_ERXSIZEERROR3    12
34100 #define M_ERXSIZEERROR3    0xfU
34101 #define V_ERXSIZEERROR3(x) ((x) << S_ERXSIZEERROR3)
34102 #define G_ERXSIZEERROR3(x) (((x) >> S_ERXSIZEERROR3) & M_ERXSIZEERROR3)
34103 
34104 #define S_ERXSIZEERROR2    8
34105 #define M_ERXSIZEERROR2    0xfU
34106 #define V_ERXSIZEERROR2(x) ((x) << S_ERXSIZEERROR2)
34107 #define G_ERXSIZEERROR2(x) (((x) >> S_ERXSIZEERROR2) & M_ERXSIZEERROR2)
34108 
34109 #define S_ERXSIZEERROR1    4
34110 #define M_ERXSIZEERROR1    0xfU
34111 #define V_ERXSIZEERROR1(x) ((x) << S_ERXSIZEERROR1)
34112 #define G_ERXSIZEERROR1(x) (((x) >> S_ERXSIZEERROR1) & M_ERXSIZEERROR1)
34113 
34114 #define S_ERXSIZEERROR0    0
34115 #define M_ERXSIZEERROR0    0xfU
34116 #define V_ERXSIZEERROR0(x) ((x) << S_ERXSIZEERROR0)
34117 #define G_ERXSIZEERROR0(x) (((x) >> S_ERXSIZEERROR0) & M_ERXSIZEERROR0)
34118 
34119 #define A_TP_DBG_ESIDE_DRP 0x14f
34120 
34121 #define S_RXDROP3    24
34122 #define M_RXDROP3    0xffU
34123 #define V_RXDROP3(x) ((x) << S_RXDROP3)
34124 #define G_RXDROP3(x) (((x) >> S_RXDROP3) & M_RXDROP3)
34125 
34126 #define S_RXDROP2    16
34127 #define M_RXDROP2    0xffU
34128 #define V_RXDROP2(x) ((x) << S_RXDROP2)
34129 #define G_RXDROP2(x) (((x) >> S_RXDROP2) & M_RXDROP2)
34130 
34131 #define S_RXDROP1    8
34132 #define M_RXDROP1    0xffU
34133 #define V_RXDROP1(x) ((x) << S_RXDROP1)
34134 #define G_RXDROP1(x) (((x) >> S_RXDROP1) & M_RXDROP1)
34135 
34136 #define S_RXDROP0    0
34137 #define M_RXDROP0    0xffU
34138 #define V_RXDROP0(x) ((x) << S_RXDROP0)
34139 #define G_RXDROP0(x) (((x) >> S_RXDROP0) & M_RXDROP0)
34140 
34141 #define A_TP_DBG_ESIDE_TX 0x150
34142 
34143 #define S_ETXVALID    4
34144 #define M_ETXVALID    0xfU
34145 #define V_ETXVALID(x) ((x) << S_ETXVALID)
34146 #define G_ETXVALID(x) (((x) >> S_ETXVALID) & M_ETXVALID)
34147 
34148 #define S_ETXFULL    0
34149 #define M_ETXFULL    0xfU
34150 #define V_ETXFULL(x) ((x) << S_ETXFULL)
34151 #define G_ETXFULL(x) (((x) >> S_ETXFULL) & M_ETXFULL)
34152 
34153 #define S_TXERRORCNT    8
34154 #define M_TXERRORCNT    0xffffffU
34155 #define V_TXERRORCNT(x) ((x) << S_TXERRORCNT)
34156 #define G_TXERRORCNT(x) (((x) >> S_TXERRORCNT) & M_TXERRORCNT)
34157 
34158 #define A_TP_ESIDE_SVID_MASK 0x151
34159 #define A_TP_ESIDE_DVID_MASK 0x152
34160 #define A_TP_ESIDE_ALIGN_MASK 0x153
34161 
34162 #define S_USE_LOOP_BIT    24
34163 #define V_USE_LOOP_BIT(x) ((x) << S_USE_LOOP_BIT)
34164 #define F_USE_LOOP_BIT    V_USE_LOOP_BIT(1U)
34165 
34166 #define S_LOOP_OFFSET    16
34167 #define M_LOOP_OFFSET    0xffU
34168 #define V_LOOP_OFFSET(x) ((x) << S_LOOP_OFFSET)
34169 #define G_LOOP_OFFSET(x) (((x) >> S_LOOP_OFFSET) & M_LOOP_OFFSET)
34170 
34171 #define S_DVID_ID_OFFSET    8
34172 #define M_DVID_ID_OFFSET    0xffU
34173 #define V_DVID_ID_OFFSET(x) ((x) << S_DVID_ID_OFFSET)
34174 #define G_DVID_ID_OFFSET(x) (((x) >> S_DVID_ID_OFFSET) & M_DVID_ID_OFFSET)
34175 
34176 #define S_SVID_ID_OFFSET    0
34177 #define M_SVID_ID_OFFSET    0xffU
34178 #define V_SVID_ID_OFFSET(x) ((x) << S_SVID_ID_OFFSET)
34179 #define G_SVID_ID_OFFSET(x) (((x) >> S_SVID_ID_OFFSET) & M_SVID_ID_OFFSET)
34180 
34181 #define A_TP_DBG_ESIDE_OP 0x154
34182 
34183 #define S_OPT_PARSER_FATAL_CHANNEL0    29
34184 #define V_OPT_PARSER_FATAL_CHANNEL0(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL0)
34185 #define F_OPT_PARSER_FATAL_CHANNEL0    V_OPT_PARSER_FATAL_CHANNEL0(1U)
34186 
34187 #define S_OPT_PARSER_BUSY_CHANNEL0    28
34188 #define V_OPT_PARSER_BUSY_CHANNEL0(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL0)
34189 #define F_OPT_PARSER_BUSY_CHANNEL0    V_OPT_PARSER_BUSY_CHANNEL0(1U)
34190 
34191 #define S_OPT_PARSER_ITCP_STATE_CHANNEL0    26
34192 #define M_OPT_PARSER_ITCP_STATE_CHANNEL0    0x3U
34193 #define V_OPT_PARSER_ITCP_STATE_CHANNEL0(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL0)
34194 #define G_OPT_PARSER_ITCP_STATE_CHANNEL0(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL0) & M_OPT_PARSER_ITCP_STATE_CHANNEL0)
34195 
34196 #define S_OPT_PARSER_OTK_STATE_CHANNEL0    24
34197 #define M_OPT_PARSER_OTK_STATE_CHANNEL0    0x3U
34198 #define V_OPT_PARSER_OTK_STATE_CHANNEL0(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL0)
34199 #define G_OPT_PARSER_OTK_STATE_CHANNEL0(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL0) & M_OPT_PARSER_OTK_STATE_CHANNEL0)
34200 
34201 #define S_OPT_PARSER_FATAL_CHANNEL1    21
34202 #define V_OPT_PARSER_FATAL_CHANNEL1(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL1)
34203 #define F_OPT_PARSER_FATAL_CHANNEL1    V_OPT_PARSER_FATAL_CHANNEL1(1U)
34204 
34205 #define S_OPT_PARSER_BUSY_CHANNEL1    20
34206 #define V_OPT_PARSER_BUSY_CHANNEL1(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL1)
34207 #define F_OPT_PARSER_BUSY_CHANNEL1    V_OPT_PARSER_BUSY_CHANNEL1(1U)
34208 
34209 #define S_OPT_PARSER_ITCP_STATE_CHANNEL1    18
34210 #define M_OPT_PARSER_ITCP_STATE_CHANNEL1    0x3U
34211 #define V_OPT_PARSER_ITCP_STATE_CHANNEL1(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL1)
34212 #define G_OPT_PARSER_ITCP_STATE_CHANNEL1(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL1) & M_OPT_PARSER_ITCP_STATE_CHANNEL1)
34213 
34214 #define S_OPT_PARSER_OTK_STATE_CHANNEL1    16
34215 #define M_OPT_PARSER_OTK_STATE_CHANNEL1    0x3U
34216 #define V_OPT_PARSER_OTK_STATE_CHANNEL1(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL1)
34217 #define G_OPT_PARSER_OTK_STATE_CHANNEL1(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL1) & M_OPT_PARSER_OTK_STATE_CHANNEL1)
34218 
34219 #define S_OPT_PARSER_FATAL_CHANNEL2    13
34220 #define V_OPT_PARSER_FATAL_CHANNEL2(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL2)
34221 #define F_OPT_PARSER_FATAL_CHANNEL2    V_OPT_PARSER_FATAL_CHANNEL2(1U)
34222 
34223 #define S_OPT_PARSER_BUSY_CHANNEL2    12
34224 #define V_OPT_PARSER_BUSY_CHANNEL2(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL2)
34225 #define F_OPT_PARSER_BUSY_CHANNEL2    V_OPT_PARSER_BUSY_CHANNEL2(1U)
34226 
34227 #define S_OPT_PARSER_ITCP_STATE_CHANNEL2    10
34228 #define M_OPT_PARSER_ITCP_STATE_CHANNEL2    0x3U
34229 #define V_OPT_PARSER_ITCP_STATE_CHANNEL2(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL2)
34230 #define G_OPT_PARSER_ITCP_STATE_CHANNEL2(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL2) & M_OPT_PARSER_ITCP_STATE_CHANNEL2)
34231 
34232 #define S_OPT_PARSER_OTK_STATE_CHANNEL2    8
34233 #define M_OPT_PARSER_OTK_STATE_CHANNEL2    0x3U
34234 #define V_OPT_PARSER_OTK_STATE_CHANNEL2(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL2)
34235 #define G_OPT_PARSER_OTK_STATE_CHANNEL2(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL2) & M_OPT_PARSER_OTK_STATE_CHANNEL2)
34236 
34237 #define S_OPT_PARSER_FATAL_CHANNEL3    5
34238 #define V_OPT_PARSER_FATAL_CHANNEL3(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL3)
34239 #define F_OPT_PARSER_FATAL_CHANNEL3    V_OPT_PARSER_FATAL_CHANNEL3(1U)
34240 
34241 #define S_OPT_PARSER_BUSY_CHANNEL3    4
34242 #define V_OPT_PARSER_BUSY_CHANNEL3(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL3)
34243 #define F_OPT_PARSER_BUSY_CHANNEL3    V_OPT_PARSER_BUSY_CHANNEL3(1U)
34244 
34245 #define S_OPT_PARSER_ITCP_STATE_CHANNEL3    2
34246 #define M_OPT_PARSER_ITCP_STATE_CHANNEL3    0x3U
34247 #define V_OPT_PARSER_ITCP_STATE_CHANNEL3(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL3)
34248 #define G_OPT_PARSER_ITCP_STATE_CHANNEL3(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL3) & M_OPT_PARSER_ITCP_STATE_CHANNEL3)
34249 
34250 #define S_OPT_PARSER_OTK_STATE_CHANNEL3    0
34251 #define M_OPT_PARSER_OTK_STATE_CHANNEL3    0x3U
34252 #define V_OPT_PARSER_OTK_STATE_CHANNEL3(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL3)
34253 #define G_OPT_PARSER_OTK_STATE_CHANNEL3(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL3) & M_OPT_PARSER_OTK_STATE_CHANNEL3)
34254 
34255 #define A_TP_DBG_ESIDE_OP_ALT 0x155
34256 
34257 #define S_OPT_PARSER_PSTATE_FATAL_CHANNEL0    29
34258 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL0)
34259 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL0    V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(1U)
34260 
34261 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0    24
34262 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0    0x1fU
34263 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0)
34264 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0)
34265 
34266 #define S_OPT_PARSER_PSTATE_FATAL_CHANNEL1    21
34267 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL1)
34268 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL1    V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(1U)
34269 
34270 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1    16
34271 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1    0x1fU
34272 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1)
34273 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1)
34274 
34275 #define S_OPT_PARSER_PSTATE_FATAL_CHANNEL2    13
34276 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL2)
34277 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL2    V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(1U)
34278 
34279 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2    8
34280 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2    0x1fU
34281 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2)
34282 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2)
34283 
34284 #define S_OPT_PARSER_PSTATE_FATAL_CHANNEL3    5
34285 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL3)
34286 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL3    V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(1U)
34287 
34288 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3    0
34289 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3    0x1fU
34290 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3)
34291 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3)
34292 
34293 #define A_TP_DBG_ESIDE_OP_BUSY 0x156
34294 
34295 #define S_OPT_PARSER_BUSY_VEC_CHANNEL3    24
34296 #define M_OPT_PARSER_BUSY_VEC_CHANNEL3    0xffU
34297 #define V_OPT_PARSER_BUSY_VEC_CHANNEL3(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL3)
34298 #define G_OPT_PARSER_BUSY_VEC_CHANNEL3(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL3) & M_OPT_PARSER_BUSY_VEC_CHANNEL3)
34299 
34300 #define S_OPT_PARSER_BUSY_VEC_CHANNEL2    16
34301 #define M_OPT_PARSER_BUSY_VEC_CHANNEL2    0xffU
34302 #define V_OPT_PARSER_BUSY_VEC_CHANNEL2(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL2)
34303 #define G_OPT_PARSER_BUSY_VEC_CHANNEL2(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL2) & M_OPT_PARSER_BUSY_VEC_CHANNEL2)
34304 
34305 #define S_OPT_PARSER_BUSY_VEC_CHANNEL1    8
34306 #define M_OPT_PARSER_BUSY_VEC_CHANNEL1    0xffU
34307 #define V_OPT_PARSER_BUSY_VEC_CHANNEL1(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL1)
34308 #define G_OPT_PARSER_BUSY_VEC_CHANNEL1(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL1) & M_OPT_PARSER_BUSY_VEC_CHANNEL1)
34309 
34310 #define S_OPT_PARSER_BUSY_VEC_CHANNEL0    0
34311 #define M_OPT_PARSER_BUSY_VEC_CHANNEL0    0xffU
34312 #define V_OPT_PARSER_BUSY_VEC_CHANNEL0(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL0)
34313 #define G_OPT_PARSER_BUSY_VEC_CHANNEL0(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL0) & M_OPT_PARSER_BUSY_VEC_CHANNEL0)
34314 
34315 #define A_TP_DBG_ESIDE_OP_COOKIE 0x157
34316 
34317 #define S_OPT_PARSER_COOKIE_CHANNEL3    24
34318 #define M_OPT_PARSER_COOKIE_CHANNEL3    0xffU
34319 #define V_OPT_PARSER_COOKIE_CHANNEL3(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL3)
34320 #define G_OPT_PARSER_COOKIE_CHANNEL3(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL3) & M_OPT_PARSER_COOKIE_CHANNEL3)
34321 
34322 #define S_OPT_PARSER_COOKIE_CHANNEL2    16
34323 #define M_OPT_PARSER_COOKIE_CHANNEL2    0xffU
34324 #define V_OPT_PARSER_COOKIE_CHANNEL2(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL2)
34325 #define G_OPT_PARSER_COOKIE_CHANNEL2(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL2) & M_OPT_PARSER_COOKIE_CHANNEL2)
34326 
34327 #define S_OPT_PARSER_COOKIE_CHANNEL1    8
34328 #define M_OPT_PARSER_COOKIE_CHANNEL1    0xffU
34329 #define V_OPT_PARSER_COOKIE_CHANNEL1(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL1)
34330 #define G_OPT_PARSER_COOKIE_CHANNEL1(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL1) & M_OPT_PARSER_COOKIE_CHANNEL1)
34331 
34332 #define S_OPT_PARSER_COOKIE_CHANNEL0    0
34333 #define M_OPT_PARSER_COOKIE_CHANNEL0    0xffU
34334 #define V_OPT_PARSER_COOKIE_CHANNEL0(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL0)
34335 #define G_OPT_PARSER_COOKIE_CHANNEL0(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL0) & M_OPT_PARSER_COOKIE_CHANNEL0)
34336 
34337 #define A_TP_DBG_ESIDE_DEMUX_WAIT0 0x158
34338 #define A_TP_DBG_ESIDE_DEMUX_WAIT1 0x159
34339 #define A_TP_DBG_ESIDE_DEMUX_CNT0 0x15a
34340 #define A_TP_DBG_ESIDE_DEMUX_CNT1 0x15b
34341 #define A_TP_ESIDE_CONFIG 0x160
34342 
34343 #define S_VNI_EN    26
34344 #define V_VNI_EN(x) ((x) << S_VNI_EN)
34345 #define F_VNI_EN    V_VNI_EN(1U)
34346 
34347 #define S_ENC_RX_EN    25
34348 #define V_ENC_RX_EN(x) ((x) << S_ENC_RX_EN)
34349 #define F_ENC_RX_EN    V_ENC_RX_EN(1U)
34350 
34351 #define S_TNL_LKP_INNER_SEL    24
34352 #define V_TNL_LKP_INNER_SEL(x) ((x) << S_TNL_LKP_INNER_SEL)
34353 #define F_TNL_LKP_INNER_SEL    V_TNL_LKP_INNER_SEL(1U)
34354 
34355 #define S_ROCEV2UDPPORT    0
34356 #define M_ROCEV2UDPPORT    0xffffU
34357 #define V_ROCEV2UDPPORT(x) ((x) << S_ROCEV2UDPPORT)
34358 #define G_ROCEV2UDPPORT(x) (((x) >> S_ROCEV2UDPPORT) & M_ROCEV2UDPPORT)
34359 
34360 #define S_IPSECTUNETHTRANSEN    29
34361 #define V_IPSECTUNETHTRANSEN(x) ((x) << S_IPSECTUNETHTRANSEN)
34362 #define F_IPSECTUNETHTRANSEN    V_IPSECTUNETHTRANSEN(1U)
34363 
34364 #define S_ROCEV2ZEROUDP6CSUM    28
34365 #define V_ROCEV2ZEROUDP6CSUM(x) ((x) << S_ROCEV2ZEROUDP6CSUM)
34366 #define F_ROCEV2ZEROUDP6CSUM    V_ROCEV2ZEROUDP6CSUM(1U)
34367 
34368 #define S_ROCEV2PROCEN    27
34369 #define V_ROCEV2PROCEN(x) ((x) << S_ROCEV2PROCEN)
34370 #define F_ROCEV2PROCEN    V_ROCEV2PROCEN(1U)
34371 
34372 #define A_TP_ESIDE_ROCE_PORT12 0x161
34373 
34374 #define S_ROCEV2UDPPORT2    16
34375 #define M_ROCEV2UDPPORT2    0xffffU
34376 #define V_ROCEV2UDPPORT2(x) ((x) << S_ROCEV2UDPPORT2)
34377 #define G_ROCEV2UDPPORT2(x) (((x) >> S_ROCEV2UDPPORT2) & M_ROCEV2UDPPORT2)
34378 
34379 #define S_ROCEV2UDPPORT1    0
34380 #define M_ROCEV2UDPPORT1    0xffffU
34381 #define V_ROCEV2UDPPORT1(x) ((x) << S_ROCEV2UDPPORT1)
34382 #define G_ROCEV2UDPPORT1(x) (((x) >> S_ROCEV2UDPPORT1) & M_ROCEV2UDPPORT1)
34383 
34384 #define A_TP_ESIDE_ROCE_PORT34 0x162
34385 
34386 #define S_ROCEV2UDPPORT4    16
34387 #define M_ROCEV2UDPPORT4    0xffffU
34388 #define V_ROCEV2UDPPORT4(x) ((x) << S_ROCEV2UDPPORT4)
34389 #define G_ROCEV2UDPPORT4(x) (((x) >> S_ROCEV2UDPPORT4) & M_ROCEV2UDPPORT4)
34390 
34391 #define S_ROCEV2UDPPORT3    0
34392 #define M_ROCEV2UDPPORT3    0xffffU
34393 #define V_ROCEV2UDPPORT3(x) ((x) << S_ROCEV2UDPPORT3)
34394 #define G_ROCEV2UDPPORT3(x) (((x) >> S_ROCEV2UDPPORT3) & M_ROCEV2UDPPORT3)
34395 
34396 #define A_TP_ESIDE_CONFIG1 0x163
34397 
34398 #define S_ROCEV2CRCIGN    0
34399 #define M_ROCEV2CRCIGN    0xfU
34400 #define V_ROCEV2CRCIGN(x) ((x) << S_ROCEV2CRCIGN)
34401 #define G_ROCEV2CRCIGN(x) (((x) >> S_ROCEV2CRCIGN) & M_ROCEV2CRCIGN)
34402 
34403 #define A_TP_ESIDE_DEBUG_CFG 0x16c
34404 #define A_TP_ESIDE_DEBUG_DATA 0x16d
34405 #define A_TP_DBG_CSIDE_RX0 0x230
34406 
34407 #define S_CRXSOPCNT    28
34408 #define M_CRXSOPCNT    0xfU
34409 #define V_CRXSOPCNT(x) ((x) << S_CRXSOPCNT)
34410 #define G_CRXSOPCNT(x) (((x) >> S_CRXSOPCNT) & M_CRXSOPCNT)
34411 
34412 #define S_CRXEOPCNT    24
34413 #define M_CRXEOPCNT    0xfU
34414 #define V_CRXEOPCNT(x) ((x) << S_CRXEOPCNT)
34415 #define G_CRXEOPCNT(x) (((x) >> S_CRXEOPCNT) & M_CRXEOPCNT)
34416 
34417 #define S_CRXPLDSOPCNT    20
34418 #define M_CRXPLDSOPCNT    0xfU
34419 #define V_CRXPLDSOPCNT(x) ((x) << S_CRXPLDSOPCNT)
34420 #define G_CRXPLDSOPCNT(x) (((x) >> S_CRXPLDSOPCNT) & M_CRXPLDSOPCNT)
34421 
34422 #define S_CRXPLDEOPCNT    16
34423 #define M_CRXPLDEOPCNT    0xfU
34424 #define V_CRXPLDEOPCNT(x) ((x) << S_CRXPLDEOPCNT)
34425 #define G_CRXPLDEOPCNT(x) (((x) >> S_CRXPLDEOPCNT) & M_CRXPLDEOPCNT)
34426 
34427 #define S_CRXARBSOPCNT    12
34428 #define M_CRXARBSOPCNT    0xfU
34429 #define V_CRXARBSOPCNT(x) ((x) << S_CRXARBSOPCNT)
34430 #define G_CRXARBSOPCNT(x) (((x) >> S_CRXARBSOPCNT) & M_CRXARBSOPCNT)
34431 
34432 #define S_CRXARBEOPCNT    8
34433 #define M_CRXARBEOPCNT    0xfU
34434 #define V_CRXARBEOPCNT(x) ((x) << S_CRXARBEOPCNT)
34435 #define G_CRXARBEOPCNT(x) (((x) >> S_CRXARBEOPCNT) & M_CRXARBEOPCNT)
34436 
34437 #define S_CRXCPLSOPCNT    4
34438 #define M_CRXCPLSOPCNT    0xfU
34439 #define V_CRXCPLSOPCNT(x) ((x) << S_CRXCPLSOPCNT)
34440 #define G_CRXCPLSOPCNT(x) (((x) >> S_CRXCPLSOPCNT) & M_CRXCPLSOPCNT)
34441 
34442 #define S_CRXCPLEOPCNT    0
34443 #define M_CRXCPLEOPCNT    0xfU
34444 #define V_CRXCPLEOPCNT(x) ((x) << S_CRXCPLEOPCNT)
34445 #define G_CRXCPLEOPCNT(x) (((x) >> S_CRXCPLEOPCNT) & M_CRXCPLEOPCNT)
34446 
34447 #define A_TP_DBG_CSIDE_RX1 0x231
34448 #define A_TP_DBG_CSIDE_RX2 0x232
34449 #define A_TP_DBG_CSIDE_RX3 0x233
34450 #define A_TP_DBG_CSIDE_TX0 0x234
34451 
34452 #define S_TXSOPCNT    28
34453 #define M_TXSOPCNT    0xfU
34454 #define V_TXSOPCNT(x) ((x) << S_TXSOPCNT)
34455 #define G_TXSOPCNT(x) (((x) >> S_TXSOPCNT) & M_TXSOPCNT)
34456 
34457 #define S_TXEOPCNT    24
34458 #define M_TXEOPCNT    0xfU
34459 #define V_TXEOPCNT(x) ((x) << S_TXEOPCNT)
34460 #define G_TXEOPCNT(x) (((x) >> S_TXEOPCNT) & M_TXEOPCNT)
34461 
34462 #define S_TXPLDSOPCNT    20
34463 #define M_TXPLDSOPCNT    0xfU
34464 #define V_TXPLDSOPCNT(x) ((x) << S_TXPLDSOPCNT)
34465 #define G_TXPLDSOPCNT(x) (((x) >> S_TXPLDSOPCNT) & M_TXPLDSOPCNT)
34466 
34467 #define S_TXPLDEOPCNT    16
34468 #define M_TXPLDEOPCNT    0xfU
34469 #define V_TXPLDEOPCNT(x) ((x) << S_TXPLDEOPCNT)
34470 #define G_TXPLDEOPCNT(x) (((x) >> S_TXPLDEOPCNT) & M_TXPLDEOPCNT)
34471 
34472 #define S_TXARBSOPCNT    12
34473 #define M_TXARBSOPCNT    0xfU
34474 #define V_TXARBSOPCNT(x) ((x) << S_TXARBSOPCNT)
34475 #define G_TXARBSOPCNT(x) (((x) >> S_TXARBSOPCNT) & M_TXARBSOPCNT)
34476 
34477 #define S_TXARBEOPCNT    8
34478 #define M_TXARBEOPCNT    0xfU
34479 #define V_TXARBEOPCNT(x) ((x) << S_TXARBEOPCNT)
34480 #define G_TXARBEOPCNT(x) (((x) >> S_TXARBEOPCNT) & M_TXARBEOPCNT)
34481 
34482 #define S_TXCPLSOPCNT    4
34483 #define M_TXCPLSOPCNT    0xfU
34484 #define V_TXCPLSOPCNT(x) ((x) << S_TXCPLSOPCNT)
34485 #define G_TXCPLSOPCNT(x) (((x) >> S_TXCPLSOPCNT) & M_TXCPLSOPCNT)
34486 
34487 #define S_TXCPLEOPCNT    0
34488 #define M_TXCPLEOPCNT    0xfU
34489 #define V_TXCPLEOPCNT(x) ((x) << S_TXCPLEOPCNT)
34490 #define G_TXCPLEOPCNT(x) (((x) >> S_TXCPLEOPCNT) & M_TXCPLEOPCNT)
34491 
34492 #define A_TP_DBG_CSIDE_TX1 0x235
34493 #define A_TP_DBG_CSIDE_TX2 0x236
34494 #define A_TP_DBG_CSIDE_TX3 0x237
34495 #define A_TP_DBG_CSIDE_FIFO0 0x238
34496 
34497 #define S_PLD_RXZEROP_SRDY1    31
34498 #define V_PLD_RXZEROP_SRDY1(x) ((x) << S_PLD_RXZEROP_SRDY1)
34499 #define F_PLD_RXZEROP_SRDY1    V_PLD_RXZEROP_SRDY1(1U)
34500 
34501 #define S_PLD_RXZEROP_DRDY1    30
34502 #define V_PLD_RXZEROP_DRDY1(x) ((x) << S_PLD_RXZEROP_DRDY1)
34503 #define F_PLD_RXZEROP_DRDY1    V_PLD_RXZEROP_DRDY1(1U)
34504 
34505 #define S_PLD_TXZEROP_SRDY1    29
34506 #define V_PLD_TXZEROP_SRDY1(x) ((x) << S_PLD_TXZEROP_SRDY1)
34507 #define F_PLD_TXZEROP_SRDY1    V_PLD_TXZEROP_SRDY1(1U)
34508 
34509 #define S_PLD_TXZEROP_DRDY1    28
34510 #define V_PLD_TXZEROP_DRDY1(x) ((x) << S_PLD_TXZEROP_DRDY1)
34511 #define F_PLD_TXZEROP_DRDY1    V_PLD_TXZEROP_DRDY1(1U)
34512 
34513 #define S_PLD_TX_SRDY1    27
34514 #define V_PLD_TX_SRDY1(x) ((x) << S_PLD_TX_SRDY1)
34515 #define F_PLD_TX_SRDY1    V_PLD_TX_SRDY1(1U)
34516 
34517 #define S_PLD_TX_DRDY1    26
34518 #define V_PLD_TX_DRDY1(x) ((x) << S_PLD_TX_DRDY1)
34519 #define F_PLD_TX_DRDY1    V_PLD_TX_DRDY1(1U)
34520 
34521 #define S_ERROR_SRDY1    25
34522 #define V_ERROR_SRDY1(x) ((x) << S_ERROR_SRDY1)
34523 #define F_ERROR_SRDY1    V_ERROR_SRDY1(1U)
34524 
34525 #define S_ERROR_DRDY1    24
34526 #define V_ERROR_DRDY1(x) ((x) << S_ERROR_DRDY1)
34527 #define F_ERROR_DRDY1    V_ERROR_DRDY1(1U)
34528 
34529 #define S_DB_VLD1    23
34530 #define V_DB_VLD1(x) ((x) << S_DB_VLD1)
34531 #define F_DB_VLD1    V_DB_VLD1(1U)
34532 
34533 #define S_DB_GT1    22
34534 #define V_DB_GT1(x) ((x) << S_DB_GT1)
34535 #define F_DB_GT1    V_DB_GT1(1U)
34536 
34537 #define S_TXVALID1    21
34538 #define V_TXVALID1(x) ((x) << S_TXVALID1)
34539 #define F_TXVALID1    V_TXVALID1(1U)
34540 
34541 #define S_TXFULL1    20
34542 #define V_TXFULL1(x) ((x) << S_TXFULL1)
34543 #define F_TXFULL1    V_TXFULL1(1U)
34544 
34545 #define S_PLD_TXVALID1    19
34546 #define V_PLD_TXVALID1(x) ((x) << S_PLD_TXVALID1)
34547 #define F_PLD_TXVALID1    V_PLD_TXVALID1(1U)
34548 
34549 #define S_PLD_TXFULL1    18
34550 #define V_PLD_TXFULL1(x) ((x) << S_PLD_TXFULL1)
34551 #define F_PLD_TXFULL1    V_PLD_TXFULL1(1U)
34552 
34553 #define S_CPL5_TXVALID1    17
34554 #define V_CPL5_TXVALID1(x) ((x) << S_CPL5_TXVALID1)
34555 #define F_CPL5_TXVALID1    V_CPL5_TXVALID1(1U)
34556 
34557 #define S_CPL5_TXFULL1    16
34558 #define V_CPL5_TXFULL1(x) ((x) << S_CPL5_TXFULL1)
34559 #define F_CPL5_TXFULL1    V_CPL5_TXFULL1(1U)
34560 
34561 #define S_PLD_RXZEROP_SRDY0    15
34562 #define V_PLD_RXZEROP_SRDY0(x) ((x) << S_PLD_RXZEROP_SRDY0)
34563 #define F_PLD_RXZEROP_SRDY0    V_PLD_RXZEROP_SRDY0(1U)
34564 
34565 #define S_PLD_RXZEROP_DRDY0    14
34566 #define V_PLD_RXZEROP_DRDY0(x) ((x) << S_PLD_RXZEROP_DRDY0)
34567 #define F_PLD_RXZEROP_DRDY0    V_PLD_RXZEROP_DRDY0(1U)
34568 
34569 #define S_PLD_TXZEROP_SRDY0    13
34570 #define V_PLD_TXZEROP_SRDY0(x) ((x) << S_PLD_TXZEROP_SRDY0)
34571 #define F_PLD_TXZEROP_SRDY0    V_PLD_TXZEROP_SRDY0(1U)
34572 
34573 #define S_PLD_TXZEROP_DRDY0    12
34574 #define V_PLD_TXZEROP_DRDY0(x) ((x) << S_PLD_TXZEROP_DRDY0)
34575 #define F_PLD_TXZEROP_DRDY0    V_PLD_TXZEROP_DRDY0(1U)
34576 
34577 #define S_PLD_TX_SRDY0    11
34578 #define V_PLD_TX_SRDY0(x) ((x) << S_PLD_TX_SRDY0)
34579 #define F_PLD_TX_SRDY0    V_PLD_TX_SRDY0(1U)
34580 
34581 #define S_PLD_TX_DRDY0    10
34582 #define V_PLD_TX_DRDY0(x) ((x) << S_PLD_TX_DRDY0)
34583 #define F_PLD_TX_DRDY0    V_PLD_TX_DRDY0(1U)
34584 
34585 #define S_ERROR_SRDY0    9
34586 #define V_ERROR_SRDY0(x) ((x) << S_ERROR_SRDY0)
34587 #define F_ERROR_SRDY0    V_ERROR_SRDY0(1U)
34588 
34589 #define S_ERROR_DRDY0    8
34590 #define V_ERROR_DRDY0(x) ((x) << S_ERROR_DRDY0)
34591 #define F_ERROR_DRDY0    V_ERROR_DRDY0(1U)
34592 
34593 #define S_DB_VLD0    7
34594 #define V_DB_VLD0(x) ((x) << S_DB_VLD0)
34595 #define F_DB_VLD0    V_DB_VLD0(1U)
34596 
34597 #define S_DB_GT0    6
34598 #define V_DB_GT0(x) ((x) << S_DB_GT0)
34599 #define F_DB_GT0    V_DB_GT0(1U)
34600 
34601 #define S_TXVALID0    5
34602 #define V_TXVALID0(x) ((x) << S_TXVALID0)
34603 #define F_TXVALID0    V_TXVALID0(1U)
34604 
34605 #define S_TXFULL0    4
34606 #define V_TXFULL0(x) ((x) << S_TXFULL0)
34607 #define F_TXFULL0    V_TXFULL0(1U)
34608 
34609 #define S_PLD_TXVALID0    3
34610 #define V_PLD_TXVALID0(x) ((x) << S_PLD_TXVALID0)
34611 #define F_PLD_TXVALID0    V_PLD_TXVALID0(1U)
34612 
34613 #define S_PLD_TXFULL0    2
34614 #define V_PLD_TXFULL0(x) ((x) << S_PLD_TXFULL0)
34615 #define F_PLD_TXFULL0    V_PLD_TXFULL0(1U)
34616 
34617 #define S_CPL5_TXVALID0    1
34618 #define V_CPL5_TXVALID0(x) ((x) << S_CPL5_TXVALID0)
34619 #define F_CPL5_TXVALID0    V_CPL5_TXVALID0(1U)
34620 
34621 #define S_CPL5_TXFULL0    0
34622 #define V_CPL5_TXFULL0(x) ((x) << S_CPL5_TXFULL0)
34623 #define F_CPL5_TXFULL0    V_CPL5_TXFULL0(1U)
34624 
34625 #define A_TP_DBG_CSIDE_FIFO1 0x239
34626 
34627 #define S_PLD_RXZEROP_SRDY3    31
34628 #define V_PLD_RXZEROP_SRDY3(x) ((x) << S_PLD_RXZEROP_SRDY3)
34629 #define F_PLD_RXZEROP_SRDY3    V_PLD_RXZEROP_SRDY3(1U)
34630 
34631 #define S_PLD_RXZEROP_DRDY3    30
34632 #define V_PLD_RXZEROP_DRDY3(x) ((x) << S_PLD_RXZEROP_DRDY3)
34633 #define F_PLD_RXZEROP_DRDY3    V_PLD_RXZEROP_DRDY3(1U)
34634 
34635 #define S_PLD_TXZEROP_SRDY3    29
34636 #define V_PLD_TXZEROP_SRDY3(x) ((x) << S_PLD_TXZEROP_SRDY3)
34637 #define F_PLD_TXZEROP_SRDY3    V_PLD_TXZEROP_SRDY3(1U)
34638 
34639 #define S_PLD_TXZEROP_DRDY3    28
34640 #define V_PLD_TXZEROP_DRDY3(x) ((x) << S_PLD_TXZEROP_DRDY3)
34641 #define F_PLD_TXZEROP_DRDY3    V_PLD_TXZEROP_DRDY3(1U)
34642 
34643 #define S_PLD_TX_SRDY3    27
34644 #define V_PLD_TX_SRDY3(x) ((x) << S_PLD_TX_SRDY3)
34645 #define F_PLD_TX_SRDY3    V_PLD_TX_SRDY3(1U)
34646 
34647 #define S_PLD_TX_DRDY3    26
34648 #define V_PLD_TX_DRDY3(x) ((x) << S_PLD_TX_DRDY3)
34649 #define F_PLD_TX_DRDY3    V_PLD_TX_DRDY3(1U)
34650 
34651 #define S_ERROR_SRDY3    25
34652 #define V_ERROR_SRDY3(x) ((x) << S_ERROR_SRDY3)
34653 #define F_ERROR_SRDY3    V_ERROR_SRDY3(1U)
34654 
34655 #define S_ERROR_DRDY3    24
34656 #define V_ERROR_DRDY3(x) ((x) << S_ERROR_DRDY3)
34657 #define F_ERROR_DRDY3    V_ERROR_DRDY3(1U)
34658 
34659 #define S_DB_VLD3    23
34660 #define V_DB_VLD3(x) ((x) << S_DB_VLD3)
34661 #define F_DB_VLD3    V_DB_VLD3(1U)
34662 
34663 #define S_DB_GT3    22
34664 #define V_DB_GT3(x) ((x) << S_DB_GT3)
34665 #define F_DB_GT3    V_DB_GT3(1U)
34666 
34667 #define S_TXVALID3    21
34668 #define V_TXVALID3(x) ((x) << S_TXVALID3)
34669 #define F_TXVALID3    V_TXVALID3(1U)
34670 
34671 #define S_TXFULL3    20
34672 #define V_TXFULL3(x) ((x) << S_TXFULL3)
34673 #define F_TXFULL3    V_TXFULL3(1U)
34674 
34675 #define S_PLD_TXVALID3    19
34676 #define V_PLD_TXVALID3(x) ((x) << S_PLD_TXVALID3)
34677 #define F_PLD_TXVALID3    V_PLD_TXVALID3(1U)
34678 
34679 #define S_PLD_TXFULL3    18
34680 #define V_PLD_TXFULL3(x) ((x) << S_PLD_TXFULL3)
34681 #define F_PLD_TXFULL3    V_PLD_TXFULL3(1U)
34682 
34683 #define S_CPL5_TXVALID3    17
34684 #define V_CPL5_TXVALID3(x) ((x) << S_CPL5_TXVALID3)
34685 #define F_CPL5_TXVALID3    V_CPL5_TXVALID3(1U)
34686 
34687 #define S_CPL5_TXFULL3    16
34688 #define V_CPL5_TXFULL3(x) ((x) << S_CPL5_TXFULL3)
34689 #define F_CPL5_TXFULL3    V_CPL5_TXFULL3(1U)
34690 
34691 #define S_PLD_RXZEROP_SRDY2    15
34692 #define V_PLD_RXZEROP_SRDY2(x) ((x) << S_PLD_RXZEROP_SRDY2)
34693 #define F_PLD_RXZEROP_SRDY2    V_PLD_RXZEROP_SRDY2(1U)
34694 
34695 #define S_PLD_RXZEROP_DRDY2    14
34696 #define V_PLD_RXZEROP_DRDY2(x) ((x) << S_PLD_RXZEROP_DRDY2)
34697 #define F_PLD_RXZEROP_DRDY2    V_PLD_RXZEROP_DRDY2(1U)
34698 
34699 #define S_PLD_TXZEROP_SRDY2    13
34700 #define V_PLD_TXZEROP_SRDY2(x) ((x) << S_PLD_TXZEROP_SRDY2)
34701 #define F_PLD_TXZEROP_SRDY2    V_PLD_TXZEROP_SRDY2(1U)
34702 
34703 #define S_PLD_TXZEROP_DRDY2    12
34704 #define V_PLD_TXZEROP_DRDY2(x) ((x) << S_PLD_TXZEROP_DRDY2)
34705 #define F_PLD_TXZEROP_DRDY2    V_PLD_TXZEROP_DRDY2(1U)
34706 
34707 #define S_PLD_TX_SRDY2    11
34708 #define V_PLD_TX_SRDY2(x) ((x) << S_PLD_TX_SRDY2)
34709 #define F_PLD_TX_SRDY2    V_PLD_TX_SRDY2(1U)
34710 
34711 #define S_PLD_TX_DRDY2    10
34712 #define V_PLD_TX_DRDY2(x) ((x) << S_PLD_TX_DRDY2)
34713 #define F_PLD_TX_DRDY2    V_PLD_TX_DRDY2(1U)
34714 
34715 #define S_ERROR_SRDY2    9
34716 #define V_ERROR_SRDY2(x) ((x) << S_ERROR_SRDY2)
34717 #define F_ERROR_SRDY2    V_ERROR_SRDY2(1U)
34718 
34719 #define S_ERROR_DRDY2    8
34720 #define V_ERROR_DRDY2(x) ((x) << S_ERROR_DRDY2)
34721 #define F_ERROR_DRDY2    V_ERROR_DRDY2(1U)
34722 
34723 #define S_DB_VLD2    7
34724 #define V_DB_VLD2(x) ((x) << S_DB_VLD2)
34725 #define F_DB_VLD2    V_DB_VLD2(1U)
34726 
34727 #define S_DB_GT2    6
34728 #define V_DB_GT2(x) ((x) << S_DB_GT2)
34729 #define F_DB_GT2    V_DB_GT2(1U)
34730 
34731 #define S_TXVALID2    5
34732 #define V_TXVALID2(x) ((x) << S_TXVALID2)
34733 #define F_TXVALID2    V_TXVALID2(1U)
34734 
34735 #define S_TXFULL2    4
34736 #define V_TXFULL2(x) ((x) << S_TXFULL2)
34737 #define F_TXFULL2    V_TXFULL2(1U)
34738 
34739 #define S_PLD_TXVALID2    3
34740 #define V_PLD_TXVALID2(x) ((x) << S_PLD_TXVALID2)
34741 #define F_PLD_TXVALID2    V_PLD_TXVALID2(1U)
34742 
34743 #define S_PLD_TXFULL2    2
34744 #define V_PLD_TXFULL2(x) ((x) << S_PLD_TXFULL2)
34745 #define F_PLD_TXFULL2    V_PLD_TXFULL2(1U)
34746 
34747 #define S_CPL5_TXVALID2    1
34748 #define V_CPL5_TXVALID2(x) ((x) << S_CPL5_TXVALID2)
34749 #define F_CPL5_TXVALID2    V_CPL5_TXVALID2(1U)
34750 
34751 #define S_CPL5_TXFULL2    0
34752 #define V_CPL5_TXFULL2(x) ((x) << S_CPL5_TXFULL2)
34753 #define F_CPL5_TXFULL2    V_CPL5_TXFULL2(1U)
34754 
34755 #define A_TP_DBG_CSIDE_DISP0 0x23a
34756 
34757 #define S_CPL5RXVALID    27
34758 #define V_CPL5RXVALID(x) ((x) << S_CPL5RXVALID)
34759 #define F_CPL5RXVALID    V_CPL5RXVALID(1U)
34760 
34761 #define S_CSTATIC1    26
34762 #define V_CSTATIC1(x) ((x) << S_CSTATIC1)
34763 #define F_CSTATIC1    V_CSTATIC1(1U)
34764 
34765 #define S_CSTATIC2    25
34766 #define V_CSTATIC2(x) ((x) << S_CSTATIC2)
34767 #define F_CSTATIC2    V_CSTATIC2(1U)
34768 
34769 #define S_PLD_RXZEROP    24
34770 #define V_PLD_RXZEROP(x) ((x) << S_PLD_RXZEROP)
34771 #define F_PLD_RXZEROP    V_PLD_RXZEROP(1U)
34772 
34773 #define S_DDP_IN_PROGRESS    23
34774 #define V_DDP_IN_PROGRESS(x) ((x) << S_DDP_IN_PROGRESS)
34775 #define F_DDP_IN_PROGRESS    V_DDP_IN_PROGRESS(1U)
34776 
34777 #define S_PLD_RXZEROP_SRDY    22
34778 #define V_PLD_RXZEROP_SRDY(x) ((x) << S_PLD_RXZEROP_SRDY)
34779 #define F_PLD_RXZEROP_SRDY    V_PLD_RXZEROP_SRDY(1U)
34780 
34781 #define S_CSTATIC3    21
34782 #define V_CSTATIC3(x) ((x) << S_CSTATIC3)
34783 #define F_CSTATIC3    V_CSTATIC3(1U)
34784 
34785 #define S_DDP_DRDY    20
34786 #define V_DDP_DRDY(x) ((x) << S_DDP_DRDY)
34787 #define F_DDP_DRDY    V_DDP_DRDY(1U)
34788 
34789 #define S_DDP_PRE_STATE    17
34790 #define M_DDP_PRE_STATE    0x7U
34791 #define V_DDP_PRE_STATE(x) ((x) << S_DDP_PRE_STATE)
34792 #define G_DDP_PRE_STATE(x) (((x) >> S_DDP_PRE_STATE) & M_DDP_PRE_STATE)
34793 
34794 #define S_DDP_SRDY    16
34795 #define V_DDP_SRDY(x) ((x) << S_DDP_SRDY)
34796 #define F_DDP_SRDY    V_DDP_SRDY(1U)
34797 
34798 #define S_DDP_MSG_CODE    12
34799 #define M_DDP_MSG_CODE    0xfU
34800 #define V_DDP_MSG_CODE(x) ((x) << S_DDP_MSG_CODE)
34801 #define G_DDP_MSG_CODE(x) (((x) >> S_DDP_MSG_CODE) & M_DDP_MSG_CODE)
34802 
34803 #define S_CPL5_SOCP_CNT    10
34804 #define M_CPL5_SOCP_CNT    0x3U
34805 #define V_CPL5_SOCP_CNT(x) ((x) << S_CPL5_SOCP_CNT)
34806 #define G_CPL5_SOCP_CNT(x) (((x) >> S_CPL5_SOCP_CNT) & M_CPL5_SOCP_CNT)
34807 
34808 #define S_CSTATIC4    4
34809 #define M_CSTATIC4    0x3fU
34810 #define V_CSTATIC4(x) ((x) << S_CSTATIC4)
34811 #define G_CSTATIC4(x) (((x) >> S_CSTATIC4) & M_CSTATIC4)
34812 
34813 #define S_CMD_SEL    1
34814 #define V_CMD_SEL(x) ((x) << S_CMD_SEL)
34815 #define F_CMD_SEL    V_CMD_SEL(1U)
34816 
34817 #define S_T5_TXFULL    31
34818 #define V_T5_TXFULL(x) ((x) << S_T5_TXFULL)
34819 #define F_T5_TXFULL    V_T5_TXFULL(1U)
34820 
34821 #define S_CPL5RXFULL    26
34822 #define V_CPL5RXFULL(x) ((x) << S_CPL5RXFULL)
34823 #define F_CPL5RXFULL    V_CPL5RXFULL(1U)
34824 
34825 #define S_T5_PLD_RXZEROP_SRDY    25
34826 #define V_T5_PLD_RXZEROP_SRDY(x) ((x) << S_T5_PLD_RXZEROP_SRDY)
34827 #define F_T5_PLD_RXZEROP_SRDY    V_T5_PLD_RXZEROP_SRDY(1U)
34828 
34829 #define S_PLD2XRXVALID    23
34830 #define V_PLD2XRXVALID(x) ((x) << S_PLD2XRXVALID)
34831 #define F_PLD2XRXVALID    V_PLD2XRXVALID(1U)
34832 
34833 #define S_T5_DDP_SRDY    22
34834 #define V_T5_DDP_SRDY(x) ((x) << S_T5_DDP_SRDY)
34835 #define F_T5_DDP_SRDY    V_T5_DDP_SRDY(1U)
34836 
34837 #define S_T5_DDP_DRDY    21
34838 #define V_T5_DDP_DRDY(x) ((x) << S_T5_DDP_DRDY)
34839 #define F_T5_DDP_DRDY    V_T5_DDP_DRDY(1U)
34840 
34841 #define S_DDPSTATE    16
34842 #define M_DDPSTATE    0x1fU
34843 #define V_DDPSTATE(x) ((x) << S_DDPSTATE)
34844 #define G_DDPSTATE(x) (((x) >> S_DDPSTATE) & M_DDPSTATE)
34845 
34846 #define S_DDPMSGCODE    12
34847 #define M_DDPMSGCODE    0xfU
34848 #define V_DDPMSGCODE(x) ((x) << S_DDPMSGCODE)
34849 #define G_DDPMSGCODE(x) (((x) >> S_DDPMSGCODE) & M_DDPMSGCODE)
34850 
34851 #define S_CPL5SOCPCNT    8
34852 #define M_CPL5SOCPCNT    0xfU
34853 #define V_CPL5SOCPCNT(x) ((x) << S_CPL5SOCPCNT)
34854 #define G_CPL5SOCPCNT(x) (((x) >> S_CPL5SOCPCNT) & M_CPL5SOCPCNT)
34855 
34856 #define S_PLDRXZEROPCNT    4
34857 #define M_PLDRXZEROPCNT    0xfU
34858 #define V_PLDRXZEROPCNT(x) ((x) << S_PLDRXZEROPCNT)
34859 #define G_PLDRXZEROPCNT(x) (((x) >> S_PLDRXZEROPCNT) & M_PLDRXZEROPCNT)
34860 
34861 #define S_TXFRMERR2    3
34862 #define V_TXFRMERR2(x) ((x) << S_TXFRMERR2)
34863 #define F_TXFRMERR2    V_TXFRMERR2(1U)
34864 
34865 #define S_TXFRMERR1    2
34866 #define V_TXFRMERR1(x) ((x) << S_TXFRMERR1)
34867 #define F_TXFRMERR1    V_TXFRMERR1(1U)
34868 
34869 #define S_TXVALID2X    1
34870 #define V_TXVALID2X(x) ((x) << S_TXVALID2X)
34871 #define F_TXVALID2X    V_TXVALID2X(1U)
34872 
34873 #define S_TXFULL2X    0
34874 #define V_TXFULL2X(x) ((x) << S_TXFULL2X)
34875 #define F_TXFULL2X    V_TXFULL2X(1U)
34876 
34877 #define A_TP_DBG_CSIDE_DISP1 0x23b
34878 #define A_TP_DBG_CSIDE_DDP0 0x23c
34879 
34880 #define S_DDPMSGLATEST7    28
34881 #define M_DDPMSGLATEST7    0xfU
34882 #define V_DDPMSGLATEST7(x) ((x) << S_DDPMSGLATEST7)
34883 #define G_DDPMSGLATEST7(x) (((x) >> S_DDPMSGLATEST7) & M_DDPMSGLATEST7)
34884 
34885 #define S_DDPMSGLATEST6    24
34886 #define M_DDPMSGLATEST6    0xfU
34887 #define V_DDPMSGLATEST6(x) ((x) << S_DDPMSGLATEST6)
34888 #define G_DDPMSGLATEST6(x) (((x) >> S_DDPMSGLATEST6) & M_DDPMSGLATEST6)
34889 
34890 #define S_DDPMSGLATEST5    20
34891 #define M_DDPMSGLATEST5    0xfU
34892 #define V_DDPMSGLATEST5(x) ((x) << S_DDPMSGLATEST5)
34893 #define G_DDPMSGLATEST5(x) (((x) >> S_DDPMSGLATEST5) & M_DDPMSGLATEST5)
34894 
34895 #define S_DDPMSGLATEST4    16
34896 #define M_DDPMSGLATEST4    0xfU
34897 #define V_DDPMSGLATEST4(x) ((x) << S_DDPMSGLATEST4)
34898 #define G_DDPMSGLATEST4(x) (((x) >> S_DDPMSGLATEST4) & M_DDPMSGLATEST4)
34899 
34900 #define S_DDPMSGLATEST3    12
34901 #define M_DDPMSGLATEST3    0xfU
34902 #define V_DDPMSGLATEST3(x) ((x) << S_DDPMSGLATEST3)
34903 #define G_DDPMSGLATEST3(x) (((x) >> S_DDPMSGLATEST3) & M_DDPMSGLATEST3)
34904 
34905 #define S_DDPMSGLATEST2    8
34906 #define M_DDPMSGLATEST2    0xfU
34907 #define V_DDPMSGLATEST2(x) ((x) << S_DDPMSGLATEST2)
34908 #define G_DDPMSGLATEST2(x) (((x) >> S_DDPMSGLATEST2) & M_DDPMSGLATEST2)
34909 
34910 #define S_DDPMSGLATEST1    4
34911 #define M_DDPMSGLATEST1    0xfU
34912 #define V_DDPMSGLATEST1(x) ((x) << S_DDPMSGLATEST1)
34913 #define G_DDPMSGLATEST1(x) (((x) >> S_DDPMSGLATEST1) & M_DDPMSGLATEST1)
34914 
34915 #define S_DDPMSGLATEST0    0
34916 #define M_DDPMSGLATEST0    0xfU
34917 #define V_DDPMSGLATEST0(x) ((x) << S_DDPMSGLATEST0)
34918 #define G_DDPMSGLATEST0(x) (((x) >> S_DDPMSGLATEST0) & M_DDPMSGLATEST0)
34919 
34920 #define A_TP_DBG_CSIDE_DDP1 0x23d
34921 #define A_TP_DBG_CSIDE_FRM 0x23e
34922 
34923 #define S_CRX2XERROR    28
34924 #define M_CRX2XERROR    0xfU
34925 #define V_CRX2XERROR(x) ((x) << S_CRX2XERROR)
34926 #define G_CRX2XERROR(x) (((x) >> S_CRX2XERROR) & M_CRX2XERROR)
34927 
34928 #define S_CPLDTX2XERROR    24
34929 #define M_CPLDTX2XERROR    0xfU
34930 #define V_CPLDTX2XERROR(x) ((x) << S_CPLDTX2XERROR)
34931 #define G_CPLDTX2XERROR(x) (((x) >> S_CPLDTX2XERROR) & M_CPLDTX2XERROR)
34932 
34933 #define S_CTXERROR    22
34934 #define M_CTXERROR    0x3U
34935 #define V_CTXERROR(x) ((x) << S_CTXERROR)
34936 #define G_CTXERROR(x) (((x) >> S_CTXERROR) & M_CTXERROR)
34937 
34938 #define S_CPLDRXERROR    20
34939 #define M_CPLDRXERROR    0x3U
34940 #define V_CPLDRXERROR(x) ((x) << S_CPLDRXERROR)
34941 #define G_CPLDRXERROR(x) (((x) >> S_CPLDRXERROR) & M_CPLDRXERROR)
34942 
34943 #define S_CPLRXERROR    18
34944 #define M_CPLRXERROR    0x3U
34945 #define V_CPLRXERROR(x) ((x) << S_CPLRXERROR)
34946 #define G_CPLRXERROR(x) (((x) >> S_CPLRXERROR) & M_CPLRXERROR)
34947 
34948 #define S_CPLTXERROR    16
34949 #define M_CPLTXERROR    0x3U
34950 #define V_CPLTXERROR(x) ((x) << S_CPLTXERROR)
34951 #define G_CPLTXERROR(x) (((x) >> S_CPLTXERROR) & M_CPLTXERROR)
34952 
34953 #define S_CPRSERROR    0
34954 #define M_CPRSERROR    0xfU
34955 #define V_CPRSERROR(x) ((x) << S_CPRSERROR)
34956 #define G_CPRSERROR(x) (((x) >> S_CPRSERROR) & M_CPRSERROR)
34957 
34958 #define A_TP_DBG_CSIDE_INT 0x23f
34959 
34960 #define S_CRXVALID2X    28
34961 #define M_CRXVALID2X    0xfU
34962 #define V_CRXVALID2X(x) ((x) << S_CRXVALID2X)
34963 #define G_CRXVALID2X(x) (((x) >> S_CRXVALID2X) & M_CRXVALID2X)
34964 
34965 #define S_CRXAFULL2X    24
34966 #define M_CRXAFULL2X    0xfU
34967 #define V_CRXAFULL2X(x) ((x) << S_CRXAFULL2X)
34968 #define G_CRXAFULL2X(x) (((x) >> S_CRXAFULL2X) & M_CRXAFULL2X)
34969 
34970 #define S_CTXVALID2X    22
34971 #define M_CTXVALID2X    0x3U
34972 #define V_CTXVALID2X(x) ((x) << S_CTXVALID2X)
34973 #define G_CTXVALID2X(x) (((x) >> S_CTXVALID2X) & M_CTXVALID2X)
34974 
34975 #define S_CTXAFULL2X    20
34976 #define M_CTXAFULL2X    0x3U
34977 #define V_CTXAFULL2X(x) ((x) << S_CTXAFULL2X)
34978 #define G_CTXAFULL2X(x) (((x) >> S_CTXAFULL2X) & M_CTXAFULL2X)
34979 
34980 #define S_PLD2X_RXVALID    18
34981 #define M_PLD2X_RXVALID    0x3U
34982 #define V_PLD2X_RXVALID(x) ((x) << S_PLD2X_RXVALID)
34983 #define G_PLD2X_RXVALID(x) (((x) >> S_PLD2X_RXVALID) & M_PLD2X_RXVALID)
34984 
34985 #define S_PLD2X_RXAFULL    16
34986 #define M_PLD2X_RXAFULL    0x3U
34987 #define V_PLD2X_RXAFULL(x) ((x) << S_PLD2X_RXAFULL)
34988 #define G_PLD2X_RXAFULL(x) (((x) >> S_PLD2X_RXAFULL) & M_PLD2X_RXAFULL)
34989 
34990 #define S_CSIDE_DDP_VALID    14
34991 #define M_CSIDE_DDP_VALID    0x3U
34992 #define V_CSIDE_DDP_VALID(x) ((x) << S_CSIDE_DDP_VALID)
34993 #define G_CSIDE_DDP_VALID(x) (((x) >> S_CSIDE_DDP_VALID) & M_CSIDE_DDP_VALID)
34994 
34995 #define S_DDP_AFULL    12
34996 #define M_DDP_AFULL    0x3U
34997 #define V_DDP_AFULL(x) ((x) << S_DDP_AFULL)
34998 #define G_DDP_AFULL(x) (((x) >> S_DDP_AFULL) & M_DDP_AFULL)
34999 
35000 #define S_TRC_RXVALID    11
35001 #define V_TRC_RXVALID(x) ((x) << S_TRC_RXVALID)
35002 #define F_TRC_RXVALID    V_TRC_RXVALID(1U)
35003 
35004 #define S_TRC_RXFULL    10
35005 #define V_TRC_RXFULL(x) ((x) << S_TRC_RXFULL)
35006 #define F_TRC_RXFULL    V_TRC_RXFULL(1U)
35007 
35008 #define S_CPL5_TXVALID    9
35009 #define V_CPL5_TXVALID(x) ((x) << S_CPL5_TXVALID)
35010 #define F_CPL5_TXVALID    V_CPL5_TXVALID(1U)
35011 
35012 #define S_CPL5_TXFULL    8
35013 #define V_CPL5_TXFULL(x) ((x) << S_CPL5_TXFULL)
35014 #define F_CPL5_TXFULL    V_CPL5_TXFULL(1U)
35015 
35016 #define S_PLD2X_TXVALID    4
35017 #define M_PLD2X_TXVALID    0xfU
35018 #define V_PLD2X_TXVALID(x) ((x) << S_PLD2X_TXVALID)
35019 #define G_PLD2X_TXVALID(x) (((x) >> S_PLD2X_TXVALID) & M_PLD2X_TXVALID)
35020 
35021 #define S_PLD2X_TXAFULL    0
35022 #define M_PLD2X_TXAFULL    0xfU
35023 #define V_PLD2X_TXAFULL(x) ((x) << S_PLD2X_TXAFULL)
35024 #define G_PLD2X_TXAFULL(x) (((x) >> S_PLD2X_TXAFULL) & M_PLD2X_TXAFULL)
35025 
35026 #define A_TP_CHDR_CONFIG 0x240
35027 
35028 #define S_CH1HIGH    24
35029 #define M_CH1HIGH    0xffU
35030 #define V_CH1HIGH(x) ((x) << S_CH1HIGH)
35031 #define G_CH1HIGH(x) (((x) >> S_CH1HIGH) & M_CH1HIGH)
35032 
35033 #define S_CH1LOW    16
35034 #define M_CH1LOW    0xffU
35035 #define V_CH1LOW(x) ((x) << S_CH1LOW)
35036 #define G_CH1LOW(x) (((x) >> S_CH1LOW) & M_CH1LOW)
35037 
35038 #define S_CH0HIGH    8
35039 #define M_CH0HIGH    0xffU
35040 #define V_CH0HIGH(x) ((x) << S_CH0HIGH)
35041 #define G_CH0HIGH(x) (((x) >> S_CH0HIGH) & M_CH0HIGH)
35042 
35043 #define S_CH0LOW    0
35044 #define M_CH0LOW    0xffU
35045 #define V_CH0LOW(x) ((x) << S_CH0LOW)
35046 #define G_CH0LOW(x) (((x) >> S_CH0LOW) & M_CH0LOW)
35047 
35048 #define A_TP_UTRN_CONFIG 0x241
35049 
35050 #define S_CH2FIFOLIMIT    16
35051 #define M_CH2FIFOLIMIT    0xffU
35052 #define V_CH2FIFOLIMIT(x) ((x) << S_CH2FIFOLIMIT)
35053 #define G_CH2FIFOLIMIT(x) (((x) >> S_CH2FIFOLIMIT) & M_CH2FIFOLIMIT)
35054 
35055 #define S_CH1FIFOLIMIT    8
35056 #define M_CH1FIFOLIMIT    0xffU
35057 #define V_CH1FIFOLIMIT(x) ((x) << S_CH1FIFOLIMIT)
35058 #define G_CH1FIFOLIMIT(x) (((x) >> S_CH1FIFOLIMIT) & M_CH1FIFOLIMIT)
35059 
35060 #define S_CH0FIFOLIMIT    0
35061 #define M_CH0FIFOLIMIT    0xffU
35062 #define V_CH0FIFOLIMIT(x) ((x) << S_CH0FIFOLIMIT)
35063 #define G_CH0FIFOLIMIT(x) (((x) >> S_CH0FIFOLIMIT) & M_CH0FIFOLIMIT)
35064 
35065 #define A_TP_CDSP_CONFIG 0x242
35066 
35067 #define S_WRITEZEROEN    4
35068 #define V_WRITEZEROEN(x) ((x) << S_WRITEZEROEN)
35069 #define F_WRITEZEROEN    V_WRITEZEROEN(1U)
35070 
35071 #define S_WRITEZEROOP    0
35072 #define M_WRITEZEROOP    0xfU
35073 #define V_WRITEZEROOP(x) ((x) << S_WRITEZEROOP)
35074 #define G_WRITEZEROOP(x) (((x) >> S_WRITEZEROOP) & M_WRITEZEROOP)
35075 
35076 #define S_STARTSKIPPLD    7
35077 #define V_STARTSKIPPLD(x) ((x) << S_STARTSKIPPLD)
35078 #define F_STARTSKIPPLD    V_STARTSKIPPLD(1U)
35079 
35080 #define S_ATOMICCMDEN    5
35081 #define V_ATOMICCMDEN(x) ((x) << S_ATOMICCMDEN)
35082 #define F_ATOMICCMDEN    V_ATOMICCMDEN(1U)
35083 
35084 #define S_ISCSICMDMODE    28
35085 #define V_ISCSICMDMODE(x) ((x) << S_ISCSICMDMODE)
35086 #define F_ISCSICMDMODE    V_ISCSICMDMODE(1U)
35087 
35088 #define S_NVMTOPUPDEN    30
35089 #define V_NVMTOPUPDEN(x) ((x) << S_NVMTOPUPDEN)
35090 #define F_NVMTOPUPDEN    V_NVMTOPUPDEN(1U)
35091 
35092 #define S_NOPDIS    29
35093 #define V_NOPDIS(x) ((x) << S_NOPDIS)
35094 #define F_NOPDIS    V_NOPDIS(1U)
35095 
35096 #define S_IWARPINVREQEN    27
35097 #define V_IWARPINVREQEN(x) ((x) << S_IWARPINVREQEN)
35098 #define F_IWARPINVREQEN    V_IWARPINVREQEN(1U)
35099 
35100 #define S_ROCEINVREQEN    26
35101 #define V_ROCEINVREQEN(x) ((x) << S_ROCEINVREQEN)
35102 #define F_ROCEINVREQEN    V_ROCEINVREQEN(1U)
35103 
35104 #define S_ROCESRQFWEN    25
35105 #define V_ROCESRQFWEN(x) ((x) << S_ROCESRQFWEN)
35106 #define F_ROCESRQFWEN    V_ROCESRQFWEN(1U)
35107 
35108 #define S_T7_WRITEZEROOP    20
35109 #define M_T7_WRITEZEROOP    0x1fU
35110 #define V_T7_WRITEZEROOP(x) ((x) << S_T7_WRITEZEROOP)
35111 #define G_T7_WRITEZEROOP(x) (((x) >> S_T7_WRITEZEROOP) & M_T7_WRITEZEROOP)
35112 
35113 #define S_IWARPEXTMODE    9
35114 #define V_IWARPEXTMODE(x) ((x) << S_IWARPEXTMODE)
35115 #define F_IWARPEXTMODE    V_IWARPEXTMODE(1U)
35116 
35117 #define S_IWARPINVFWEN    8
35118 #define V_IWARPINVFWEN(x) ((x) << S_IWARPINVFWEN)
35119 #define F_IWARPINVFWEN    V_IWARPINVFWEN(1U)
35120 
35121 #define S_IWARPSRQFWEN    7
35122 #define V_IWARPSRQFWEN(x) ((x) << S_IWARPSRQFWEN)
35123 #define F_IWARPSRQFWEN    V_IWARPSRQFWEN(1U)
35124 
35125 #define S_T7_STARTSKIPPLD    3
35126 #define V_T7_STARTSKIPPLD(x) ((x) << S_T7_STARTSKIPPLD)
35127 #define F_T7_STARTSKIPPLD    V_T7_STARTSKIPPLD(1U)
35128 
35129 #define S_NVMTFLIMMEN    2
35130 #define V_NVMTFLIMMEN(x) ((x) << S_NVMTFLIMMEN)
35131 #define F_NVMTFLIMMEN    V_NVMTFLIMMEN(1U)
35132 
35133 #define S_NVMTOPCTRLEN    1
35134 #define V_NVMTOPCTRLEN(x) ((x) << S_NVMTOPCTRLEN)
35135 #define F_NVMTOPCTRLEN    V_NVMTOPCTRLEN(1U)
35136 
35137 #define S_T7_WRITEZEROEN    0
35138 #define V_T7_WRITEZEROEN(x) ((x) << S_T7_WRITEZEROEN)
35139 #define F_T7_WRITEZEROEN    V_T7_WRITEZEROEN(1U)
35140 
35141 #define A_TP_CSPI_POWER 0x243
35142 
35143 #define S_GATECHNTX3    11
35144 #define V_GATECHNTX3(x) ((x) << S_GATECHNTX3)
35145 #define F_GATECHNTX3    V_GATECHNTX3(1U)
35146 
35147 #define S_GATECHNTX2    10
35148 #define V_GATECHNTX2(x) ((x) << S_GATECHNTX2)
35149 #define F_GATECHNTX2    V_GATECHNTX2(1U)
35150 
35151 #define S_GATECHNTX1    9
35152 #define V_GATECHNTX1(x) ((x) << S_GATECHNTX1)
35153 #define F_GATECHNTX1    V_GATECHNTX1(1U)
35154 
35155 #define S_GATECHNTX0    8
35156 #define V_GATECHNTX0(x) ((x) << S_GATECHNTX0)
35157 #define F_GATECHNTX0    V_GATECHNTX0(1U)
35158 
35159 #define S_GATECHNRX1    7
35160 #define V_GATECHNRX1(x) ((x) << S_GATECHNRX1)
35161 #define F_GATECHNRX1    V_GATECHNRX1(1U)
35162 
35163 #define S_GATECHNRX0    6
35164 #define V_GATECHNRX0(x) ((x) << S_GATECHNRX0)
35165 #define F_GATECHNRX0    V_GATECHNRX0(1U)
35166 
35167 #define S_SLEEPRDYUTRN    4
35168 #define V_SLEEPRDYUTRN(x) ((x) << S_SLEEPRDYUTRN)
35169 #define F_SLEEPRDYUTRN    V_SLEEPRDYUTRN(1U)
35170 
35171 #define S_SLEEPREQUTRN    0
35172 #define V_SLEEPREQUTRN(x) ((x) << S_SLEEPREQUTRN)
35173 #define F_SLEEPREQUTRN    V_SLEEPREQUTRN(1U)
35174 
35175 #define S_GATECHNRX3    7
35176 #define V_GATECHNRX3(x) ((x) << S_GATECHNRX3)
35177 #define F_GATECHNRX3    V_GATECHNRX3(1U)
35178 
35179 #define S_GATECHNRX2    6
35180 #define V_GATECHNRX2(x) ((x) << S_GATECHNRX2)
35181 #define F_GATECHNRX2    V_GATECHNRX2(1U)
35182 
35183 #define S_T7_GATECHNRX1    5
35184 #define V_T7_GATECHNRX1(x) ((x) << S_T7_GATECHNRX1)
35185 #define F_T7_GATECHNRX1    V_T7_GATECHNRX1(1U)
35186 
35187 #define S_T7_GATECHNRX0    4
35188 #define V_T7_GATECHNRX0(x) ((x) << S_T7_GATECHNRX0)
35189 #define F_T7_GATECHNRX0    V_T7_GATECHNRX0(1U)
35190 
35191 #define S_T7_SLEEPRDYUTRN    3
35192 #define V_T7_SLEEPRDYUTRN(x) ((x) << S_T7_SLEEPRDYUTRN)
35193 #define F_T7_SLEEPRDYUTRN    V_T7_SLEEPRDYUTRN(1U)
35194 
35195 #define A_TP_TRC_CONFIG 0x244
35196 
35197 #define S_TRCRR    1
35198 #define V_TRCRR(x) ((x) << S_TRCRR)
35199 #define F_TRCRR    V_TRCRR(1U)
35200 
35201 #define S_TRCCH    0
35202 #define V_TRCCH(x) ((x) << S_TRCCH)
35203 #define F_TRCCH    V_TRCCH(1U)
35204 
35205 #define S_DEBUGPG    3
35206 #define V_DEBUGPG(x) ((x) << S_DEBUGPG)
35207 #define F_DEBUGPG    V_DEBUGPG(1U)
35208 
35209 #define S_T7_TRCRR    2
35210 #define V_T7_TRCRR(x) ((x) << S_T7_TRCRR)
35211 #define F_T7_TRCRR    V_T7_TRCRR(1U)
35212 
35213 #define S_T7_TRCCH    0
35214 #define M_T7_TRCCH    0x3U
35215 #define V_T7_TRCCH(x) ((x) << S_T7_TRCCH)
35216 #define G_T7_TRCCH(x) (((x) >> S_T7_TRCCH) & M_T7_TRCCH)
35217 
35218 #define A_TP_TAG_CONFIG 0x245
35219 
35220 #define S_ETAGTYPE    16
35221 #define M_ETAGTYPE    0xffffU
35222 #define V_ETAGTYPE(x) ((x) << S_ETAGTYPE)
35223 #define G_ETAGTYPE(x) (((x) >> S_ETAGTYPE) & M_ETAGTYPE)
35224 
35225 #define A_TP_DBG_CSIDE_PRS 0x246
35226 
35227 #define S_CPRSSTATE3    24
35228 #define M_CPRSSTATE3    0x7U
35229 #define V_CPRSSTATE3(x) ((x) << S_CPRSSTATE3)
35230 #define G_CPRSSTATE3(x) (((x) >> S_CPRSSTATE3) & M_CPRSSTATE3)
35231 
35232 #define S_CPRSSTATE2    16
35233 #define M_CPRSSTATE2    0x7U
35234 #define V_CPRSSTATE2(x) ((x) << S_CPRSSTATE2)
35235 #define G_CPRSSTATE2(x) (((x) >> S_CPRSSTATE2) & M_CPRSSTATE2)
35236 
35237 #define S_CPRSSTATE1    8
35238 #define M_CPRSSTATE1    0x7U
35239 #define V_CPRSSTATE1(x) ((x) << S_CPRSSTATE1)
35240 #define G_CPRSSTATE1(x) (((x) >> S_CPRSSTATE1) & M_CPRSSTATE1)
35241 
35242 #define S_CPRSSTATE0    0
35243 #define M_CPRSSTATE0    0x7U
35244 #define V_CPRSSTATE0(x) ((x) << S_CPRSSTATE0)
35245 #define G_CPRSSTATE0(x) (((x) >> S_CPRSSTATE0) & M_CPRSSTATE0)
35246 
35247 #define S_C4TUPBUSY3    31
35248 #define V_C4TUPBUSY3(x) ((x) << S_C4TUPBUSY3)
35249 #define F_C4TUPBUSY3    V_C4TUPBUSY3(1U)
35250 
35251 #define S_CDBVALID3    30
35252 #define V_CDBVALID3(x) ((x) << S_CDBVALID3)
35253 #define F_CDBVALID3    V_CDBVALID3(1U)
35254 
35255 #define S_CRXVALID3    29
35256 #define V_CRXVALID3(x) ((x) << S_CRXVALID3)
35257 #define F_CRXVALID3    V_CRXVALID3(1U)
35258 
35259 #define S_CRXFULL3    28
35260 #define V_CRXFULL3(x) ((x) << S_CRXFULL3)
35261 #define F_CRXFULL3    V_CRXFULL3(1U)
35262 
35263 #define S_T5_CPRSSTATE3    24
35264 #define M_T5_CPRSSTATE3    0xfU
35265 #define V_T5_CPRSSTATE3(x) ((x) << S_T5_CPRSSTATE3)
35266 #define G_T5_CPRSSTATE3(x) (((x) >> S_T5_CPRSSTATE3) & M_T5_CPRSSTATE3)
35267 
35268 #define S_C4TUPBUSY2    23
35269 #define V_C4TUPBUSY2(x) ((x) << S_C4TUPBUSY2)
35270 #define F_C4TUPBUSY2    V_C4TUPBUSY2(1U)
35271 
35272 #define S_CDBVALID2    22
35273 #define V_CDBVALID2(x) ((x) << S_CDBVALID2)
35274 #define F_CDBVALID2    V_CDBVALID2(1U)
35275 
35276 #define S_CRXVALID2    21
35277 #define V_CRXVALID2(x) ((x) << S_CRXVALID2)
35278 #define F_CRXVALID2    V_CRXVALID2(1U)
35279 
35280 #define S_CRXFULL2    20
35281 #define V_CRXFULL2(x) ((x) << S_CRXFULL2)
35282 #define F_CRXFULL2    V_CRXFULL2(1U)
35283 
35284 #define S_T5_CPRSSTATE2    16
35285 #define M_T5_CPRSSTATE2    0xfU
35286 #define V_T5_CPRSSTATE2(x) ((x) << S_T5_CPRSSTATE2)
35287 #define G_T5_CPRSSTATE2(x) (((x) >> S_T5_CPRSSTATE2) & M_T5_CPRSSTATE2)
35288 
35289 #define S_C4TUPBUSY1    15
35290 #define V_C4TUPBUSY1(x) ((x) << S_C4TUPBUSY1)
35291 #define F_C4TUPBUSY1    V_C4TUPBUSY1(1U)
35292 
35293 #define S_CDBVALID1    14
35294 #define V_CDBVALID1(x) ((x) << S_CDBVALID1)
35295 #define F_CDBVALID1    V_CDBVALID1(1U)
35296 
35297 #define S_CRXVALID1    13
35298 #define V_CRXVALID1(x) ((x) << S_CRXVALID1)
35299 #define F_CRXVALID1    V_CRXVALID1(1U)
35300 
35301 #define S_CRXFULL1    12
35302 #define V_CRXFULL1(x) ((x) << S_CRXFULL1)
35303 #define F_CRXFULL1    V_CRXFULL1(1U)
35304 
35305 #define S_T5_CPRSSTATE1    8
35306 #define M_T5_CPRSSTATE1    0xfU
35307 #define V_T5_CPRSSTATE1(x) ((x) << S_T5_CPRSSTATE1)
35308 #define G_T5_CPRSSTATE1(x) (((x) >> S_T5_CPRSSTATE1) & M_T5_CPRSSTATE1)
35309 
35310 #define S_C4TUPBUSY0    7
35311 #define V_C4TUPBUSY0(x) ((x) << S_C4TUPBUSY0)
35312 #define F_C4TUPBUSY0    V_C4TUPBUSY0(1U)
35313 
35314 #define S_CDBVALID0    6
35315 #define V_CDBVALID0(x) ((x) << S_CDBVALID0)
35316 #define F_CDBVALID0    V_CDBVALID0(1U)
35317 
35318 #define S_CRXVALID0    5
35319 #define V_CRXVALID0(x) ((x) << S_CRXVALID0)
35320 #define F_CRXVALID0    V_CRXVALID0(1U)
35321 
35322 #define S_CRXFULL0    4
35323 #define V_CRXFULL0(x) ((x) << S_CRXFULL0)
35324 #define F_CRXFULL0    V_CRXFULL0(1U)
35325 
35326 #define S_T5_CPRSSTATE0    0
35327 #define M_T5_CPRSSTATE0    0xfU
35328 #define V_T5_CPRSSTATE0(x) ((x) << S_T5_CPRSSTATE0)
35329 #define G_T5_CPRSSTATE0(x) (((x) >> S_T5_CPRSSTATE0) & M_T5_CPRSSTATE0)
35330 
35331 #define A_TP_DBG_CSIDE_DEMUX 0x247
35332 
35333 #define S_CALLDONE    28
35334 #define M_CALLDONE    0xfU
35335 #define V_CALLDONE(x) ((x) << S_CALLDONE)
35336 #define G_CALLDONE(x) (((x) >> S_CALLDONE) & M_CALLDONE)
35337 
35338 #define S_CTCPL5DONE    24
35339 #define M_CTCPL5DONE    0xfU
35340 #define V_CTCPL5DONE(x) ((x) << S_CTCPL5DONE)
35341 #define G_CTCPL5DONE(x) (((x) >> S_CTCPL5DONE) & M_CTCPL5DONE)
35342 
35343 #define S_CTXZEROPDONE    20
35344 #define M_CTXZEROPDONE    0xfU
35345 #define V_CTXZEROPDONE(x) ((x) << S_CTXZEROPDONE)
35346 #define G_CTXZEROPDONE(x) (((x) >> S_CTXZEROPDONE) & M_CTXZEROPDONE)
35347 
35348 #define S_CPLDDONE    16
35349 #define M_CPLDDONE    0xfU
35350 #define V_CPLDDONE(x) ((x) << S_CPLDDONE)
35351 #define G_CPLDDONE(x) (((x) >> S_CPLDDONE) & M_CPLDDONE)
35352 
35353 #define S_CTTCPOPDONE    12
35354 #define M_CTTCPOPDONE    0xfU
35355 #define V_CTTCPOPDONE(x) ((x) << S_CTTCPOPDONE)
35356 #define G_CTTCPOPDONE(x) (((x) >> S_CTTCPOPDONE) & M_CTTCPOPDONE)
35357 
35358 #define S_CDBDONE    8
35359 #define M_CDBDONE    0xfU
35360 #define V_CDBDONE(x) ((x) << S_CDBDONE)
35361 #define G_CDBDONE(x) (((x) >> S_CDBDONE) & M_CDBDONE)
35362 
35363 #define S_CISSFIFODONE    4
35364 #define M_CISSFIFODONE    0xfU
35365 #define V_CISSFIFODONE(x) ((x) << S_CISSFIFODONE)
35366 #define G_CISSFIFODONE(x) (((x) >> S_CISSFIFODONE) & M_CISSFIFODONE)
35367 
35368 #define S_CTXPKTCSUMDONE    0
35369 #define M_CTXPKTCSUMDONE    0xfU
35370 #define V_CTXPKTCSUMDONE(x) ((x) << S_CTXPKTCSUMDONE)
35371 #define G_CTXPKTCSUMDONE(x) (((x) >> S_CTXPKTCSUMDONE) & M_CTXPKTCSUMDONE)
35372 
35373 #define S_CARBVALID    28
35374 #define M_CARBVALID    0xfU
35375 #define V_CARBVALID(x) ((x) << S_CARBVALID)
35376 #define G_CARBVALID(x) (((x) >> S_CARBVALID) & M_CARBVALID)
35377 
35378 #define S_CCPL5DONE    24
35379 #define M_CCPL5DONE    0xfU
35380 #define V_CCPL5DONE(x) ((x) << S_CCPL5DONE)
35381 #define G_CCPL5DONE(x) (((x) >> S_CCPL5DONE) & M_CCPL5DONE)
35382 
35383 #define S_CTCPOPDONE    12
35384 #define M_CTCPOPDONE    0xfU
35385 #define V_CTCPOPDONE(x) ((x) << S_CTCPOPDONE)
35386 #define G_CTCPOPDONE(x) (((x) >> S_CTCPOPDONE) & M_CTCPOPDONE)
35387 
35388 #define A_TP_DBG_CSIDE_ARBIT 0x248
35389 
35390 #define S_CPLVALID3    31
35391 #define V_CPLVALID3(x) ((x) << S_CPLVALID3)
35392 #define F_CPLVALID3    V_CPLVALID3(1U)
35393 
35394 #define S_PLDVALID3    30
35395 #define V_PLDVALID3(x) ((x) << S_PLDVALID3)
35396 #define F_PLDVALID3    V_PLDVALID3(1U)
35397 
35398 #define S_CRCVALID3    29
35399 #define V_CRCVALID3(x) ((x) << S_CRCVALID3)
35400 #define F_CRCVALID3    V_CRCVALID3(1U)
35401 
35402 #define S_ISSVALID3    28
35403 #define V_ISSVALID3(x) ((x) << S_ISSVALID3)
35404 #define F_ISSVALID3    V_ISSVALID3(1U)
35405 
35406 #define S_DBVALID3    27
35407 #define V_DBVALID3(x) ((x) << S_DBVALID3)
35408 #define F_DBVALID3    V_DBVALID3(1U)
35409 
35410 #define S_CHKVALID3    26
35411 #define V_CHKVALID3(x) ((x) << S_CHKVALID3)
35412 #define F_CHKVALID3    V_CHKVALID3(1U)
35413 
35414 #define S_ZRPVALID3    25
35415 #define V_ZRPVALID3(x) ((x) << S_ZRPVALID3)
35416 #define F_ZRPVALID3    V_ZRPVALID3(1U)
35417 
35418 #define S_ERRVALID3    24
35419 #define V_ERRVALID3(x) ((x) << S_ERRVALID3)
35420 #define F_ERRVALID3    V_ERRVALID3(1U)
35421 
35422 #define S_CPLVALID2    23
35423 #define V_CPLVALID2(x) ((x) << S_CPLVALID2)
35424 #define F_CPLVALID2    V_CPLVALID2(1U)
35425 
35426 #define S_PLDVALID2    22
35427 #define V_PLDVALID2(x) ((x) << S_PLDVALID2)
35428 #define F_PLDVALID2    V_PLDVALID2(1U)
35429 
35430 #define S_CRCVALID2    21
35431 #define V_CRCVALID2(x) ((x) << S_CRCVALID2)
35432 #define F_CRCVALID2    V_CRCVALID2(1U)
35433 
35434 #define S_ISSVALID2    20
35435 #define V_ISSVALID2(x) ((x) << S_ISSVALID2)
35436 #define F_ISSVALID2    V_ISSVALID2(1U)
35437 
35438 #define S_DBVALID2    19
35439 #define V_DBVALID2(x) ((x) << S_DBVALID2)
35440 #define F_DBVALID2    V_DBVALID2(1U)
35441 
35442 #define S_CHKVALID2    18
35443 #define V_CHKVALID2(x) ((x) << S_CHKVALID2)
35444 #define F_CHKVALID2    V_CHKVALID2(1U)
35445 
35446 #define S_ZRPVALID2    17
35447 #define V_ZRPVALID2(x) ((x) << S_ZRPVALID2)
35448 #define F_ZRPVALID2    V_ZRPVALID2(1U)
35449 
35450 #define S_ERRVALID2    16
35451 #define V_ERRVALID2(x) ((x) << S_ERRVALID2)
35452 #define F_ERRVALID2    V_ERRVALID2(1U)
35453 
35454 #define S_CPLVALID1    15
35455 #define V_CPLVALID1(x) ((x) << S_CPLVALID1)
35456 #define F_CPLVALID1    V_CPLVALID1(1U)
35457 
35458 #define S_PLDVALID1    14
35459 #define V_PLDVALID1(x) ((x) << S_PLDVALID1)
35460 #define F_PLDVALID1    V_PLDVALID1(1U)
35461 
35462 #define S_CRCVALID1    13
35463 #define V_CRCVALID1(x) ((x) << S_CRCVALID1)
35464 #define F_CRCVALID1    V_CRCVALID1(1U)
35465 
35466 #define S_ISSVALID1    12
35467 #define V_ISSVALID1(x) ((x) << S_ISSVALID1)
35468 #define F_ISSVALID1    V_ISSVALID1(1U)
35469 
35470 #define S_DBVALID1    11
35471 #define V_DBVALID1(x) ((x) << S_DBVALID1)
35472 #define F_DBVALID1    V_DBVALID1(1U)
35473 
35474 #define S_CHKVALID1    10
35475 #define V_CHKVALID1(x) ((x) << S_CHKVALID1)
35476 #define F_CHKVALID1    V_CHKVALID1(1U)
35477 
35478 #define S_ZRPVALID1    9
35479 #define V_ZRPVALID1(x) ((x) << S_ZRPVALID1)
35480 #define F_ZRPVALID1    V_ZRPVALID1(1U)
35481 
35482 #define S_ERRVALID1    8
35483 #define V_ERRVALID1(x) ((x) << S_ERRVALID1)
35484 #define F_ERRVALID1    V_ERRVALID1(1U)
35485 
35486 #define S_CPLVALID0    7
35487 #define V_CPLVALID0(x) ((x) << S_CPLVALID0)
35488 #define F_CPLVALID0    V_CPLVALID0(1U)
35489 
35490 #define S_PLDVALID0    6
35491 #define V_PLDVALID0(x) ((x) << S_PLDVALID0)
35492 #define F_PLDVALID0    V_PLDVALID0(1U)
35493 
35494 #define S_CRCVALID0    5
35495 #define V_CRCVALID0(x) ((x) << S_CRCVALID0)
35496 #define F_CRCVALID0    V_CRCVALID0(1U)
35497 
35498 #define S_ISSVALID0    4
35499 #define V_ISSVALID0(x) ((x) << S_ISSVALID0)
35500 #define F_ISSVALID0    V_ISSVALID0(1U)
35501 
35502 #define S_DBVALID0    3
35503 #define V_DBVALID0(x) ((x) << S_DBVALID0)
35504 #define F_DBVALID0    V_DBVALID0(1U)
35505 
35506 #define S_CHKVALID0    2
35507 #define V_CHKVALID0(x) ((x) << S_CHKVALID0)
35508 #define F_CHKVALID0    V_CHKVALID0(1U)
35509 
35510 #define S_ZRPVALID0    1
35511 #define V_ZRPVALID0(x) ((x) << S_ZRPVALID0)
35512 #define F_ZRPVALID0    V_ZRPVALID0(1U)
35513 
35514 #define S_ERRVALID0    0
35515 #define V_ERRVALID0(x) ((x) << S_ERRVALID0)
35516 #define F_ERRVALID0    V_ERRVALID0(1U)
35517 
35518 #define A_TP_DBG_CSIDE_TRACE_CNT 0x24a
35519 
35520 #define S_TRCSOPCNT    24
35521 #define M_TRCSOPCNT    0xffU
35522 #define V_TRCSOPCNT(x) ((x) << S_TRCSOPCNT)
35523 #define G_TRCSOPCNT(x) (((x) >> S_TRCSOPCNT) & M_TRCSOPCNT)
35524 
35525 #define S_TRCEOPCNT    16
35526 #define M_TRCEOPCNT    0xffU
35527 #define V_TRCEOPCNT(x) ((x) << S_TRCEOPCNT)
35528 #define G_TRCEOPCNT(x) (((x) >> S_TRCEOPCNT) & M_TRCEOPCNT)
35529 
35530 #define S_TRCFLTHIT    12
35531 #define M_TRCFLTHIT    0xfU
35532 #define V_TRCFLTHIT(x) ((x) << S_TRCFLTHIT)
35533 #define G_TRCFLTHIT(x) (((x) >> S_TRCFLTHIT) & M_TRCFLTHIT)
35534 
35535 #define S_TRCRNTPKT    8
35536 #define M_TRCRNTPKT    0xfU
35537 #define V_TRCRNTPKT(x) ((x) << S_TRCRNTPKT)
35538 #define G_TRCRNTPKT(x) (((x) >> S_TRCRNTPKT) & M_TRCRNTPKT)
35539 
35540 #define S_TRCPKTLEN    0
35541 #define M_TRCPKTLEN    0xffU
35542 #define V_TRCPKTLEN(x) ((x) << S_TRCPKTLEN)
35543 #define G_TRCPKTLEN(x) (((x) >> S_TRCPKTLEN) & M_TRCPKTLEN)
35544 
35545 #define A_TP_DBG_CSIDE_TRACE_RSS 0x24b
35546 #define A_TP_VLN_CONFIG 0x24c
35547 
35548 #define S_ETHTYPEQINQ    16
35549 #define M_ETHTYPEQINQ    0xffffU
35550 #define V_ETHTYPEQINQ(x) ((x) << S_ETHTYPEQINQ)
35551 #define G_ETHTYPEQINQ(x) (((x) >> S_ETHTYPEQINQ) & M_ETHTYPEQINQ)
35552 
35553 #define S_ETHTYPEVLAN    0
35554 #define M_ETHTYPEVLAN    0xffffU
35555 #define V_ETHTYPEVLAN(x) ((x) << S_ETHTYPEVLAN)
35556 #define G_ETHTYPEVLAN(x) (((x) >> S_ETHTYPEVLAN) & M_ETHTYPEVLAN)
35557 
35558 #define A_TP_DBG_CSIDE_ARBIT_WAIT0 0x24d
35559 #define A_TP_DBG_CSIDE_ARBIT_WAIT1 0x24e
35560 #define A_TP_DBG_CSIDE_ARBIT_CNT0 0x24f
35561 #define A_TP_DBG_CSIDE_ARBIT_CNT1 0x250
35562 #define A_TP_CHDR_CONFIG1 0x259
35563 
35564 #define S_CH3HIGH    24
35565 #define M_CH3HIGH    0xffU
35566 #define V_CH3HIGH(x) ((x) << S_CH3HIGH)
35567 #define G_CH3HIGH(x) (((x) >> S_CH3HIGH) & M_CH3HIGH)
35568 
35569 #define S_CH3LOW    16
35570 #define M_CH3LOW    0xffU
35571 #define V_CH3LOW(x) ((x) << S_CH3LOW)
35572 #define G_CH3LOW(x) (((x) >> S_CH3LOW) & M_CH3LOW)
35573 
35574 #define S_CH2HIGH    8
35575 #define M_CH2HIGH    0xffU
35576 #define V_CH2HIGH(x) ((x) << S_CH2HIGH)
35577 #define G_CH2HIGH(x) (((x) >> S_CH2HIGH) & M_CH2HIGH)
35578 
35579 #define S_CH2LOW    0
35580 #define M_CH2LOW    0xffU
35581 #define V_CH2LOW(x) ((x) << S_CH2LOW)
35582 #define G_CH2LOW(x) (((x) >> S_CH2LOW) & M_CH2LOW)
35583 
35584 #define A_TP_CDSP_RDMA_CONFIG 0x260
35585 #define A_TP_NVMT_OP_CTRL 0x268
35586 
35587 #define S_DEFOPCTRL    30
35588 #define M_DEFOPCTRL    0x3U
35589 #define V_DEFOPCTRL(x) ((x) << S_DEFOPCTRL)
35590 #define G_DEFOPCTRL(x) (((x) >> S_DEFOPCTRL) & M_DEFOPCTRL)
35591 
35592 #define S_NVMTOPCTRL    0
35593 #define M_NVMTOPCTRL    0x3fffffffU
35594 #define V_NVMTOPCTRL(x) ((x) << S_NVMTOPCTRL)
35595 #define G_NVMTOPCTRL(x) (((x) >> S_NVMTOPCTRL) & M_NVMTOPCTRL)
35596 
35597 #define A_TP_CSIDE_DEBUG_CFG 0x26c
35598 
35599 #define S_T7_OR_EN    13
35600 #define V_T7_OR_EN(x) ((x) << S_T7_OR_EN)
35601 #define F_T7_OR_EN    V_T7_OR_EN(1U)
35602 
35603 #define S_T7_HI    12
35604 #define V_T7_HI(x) ((x) << S_T7_HI)
35605 #define F_T7_HI    V_T7_HI(1U)
35606 
35607 #define S_T7_SELH    6
35608 #define M_T7_SELH    0x3fU
35609 #define V_T7_SELH(x) ((x) << S_T7_SELH)
35610 #define G_T7_SELH(x) (((x) >> S_T7_SELH) & M_T7_SELH)
35611 
35612 #define S_T7_SELL    0
35613 #define M_T7_SELL    0x3fU
35614 #define V_T7_SELL(x) ((x) << S_T7_SELL)
35615 #define G_T7_SELL(x) (((x) >> S_T7_SELL) & M_T7_SELL)
35616 
35617 #define A_TP_CSIDE_DEBUG_DATA 0x26d
35618 #define A_TP_FIFO_CONFIG 0x8c0
35619 
35620 #define S_CH1_OUTPUT    27
35621 #define M_CH1_OUTPUT    0x1fU
35622 #define V_CH1_OUTPUT(x) ((x) << S_CH1_OUTPUT)
35623 #define G_CH1_OUTPUT(x) (((x) >> S_CH1_OUTPUT) & M_CH1_OUTPUT)
35624 
35625 #define S_CH2_OUTPUT    22
35626 #define M_CH2_OUTPUT    0x1fU
35627 #define V_CH2_OUTPUT(x) ((x) << S_CH2_OUTPUT)
35628 #define G_CH2_OUTPUT(x) (((x) >> S_CH2_OUTPUT) & M_CH2_OUTPUT)
35629 
35630 #define S_STROBE1    16
35631 #define V_STROBE1(x) ((x) << S_STROBE1)
35632 #define F_STROBE1    V_STROBE1(1U)
35633 
35634 #define S_CH1_INPUT    11
35635 #define M_CH1_INPUT    0x1fU
35636 #define V_CH1_INPUT(x) ((x) << S_CH1_INPUT)
35637 #define G_CH1_INPUT(x) (((x) >> S_CH1_INPUT) & M_CH1_INPUT)
35638 
35639 #define S_CH2_INPUT    6
35640 #define M_CH2_INPUT    0x1fU
35641 #define V_CH2_INPUT(x) ((x) << S_CH2_INPUT)
35642 #define G_CH2_INPUT(x) (((x) >> S_CH2_INPUT) & M_CH2_INPUT)
35643 
35644 #define S_CH3_INPUT    1
35645 #define M_CH3_INPUT    0x1fU
35646 #define V_CH3_INPUT(x) ((x) << S_CH3_INPUT)
35647 #define G_CH3_INPUT(x) (((x) >> S_CH3_INPUT) & M_CH3_INPUT)
35648 
35649 #define S_STROBE0    0
35650 #define V_STROBE0(x) ((x) << S_STROBE0)
35651 #define F_STROBE0    V_STROBE0(1U)
35652 
35653 #define A_TP_MIB_MAC_IN_ERR_0 0x0
35654 #define A_TP_MIB_MAC_IN_ERR_1 0x1
35655 #define A_TP_MIB_MAC_IN_ERR_2 0x2
35656 #define A_TP_MIB_MAC_IN_ERR_3 0x3
35657 #define A_TP_MIB_HDR_IN_ERR_0 0x4
35658 #define A_TP_MIB_HDR_IN_ERR_1 0x5
35659 #define A_TP_MIB_HDR_IN_ERR_2 0x6
35660 #define A_TP_MIB_HDR_IN_ERR_3 0x7
35661 #define A_TP_MIB_TCP_IN_ERR_0 0x8
35662 #define A_TP_MIB_TCP_IN_ERR_1 0x9
35663 #define A_TP_MIB_TCP_IN_ERR_2 0xa
35664 #define A_TP_MIB_TCP_IN_ERR_3 0xb
35665 #define A_TP_MIB_TCP_OUT_RST 0xc
35666 #define A_TP_MIB_TCP_IN_SEG_HI 0x10
35667 #define A_TP_MIB_TCP_IN_SEG_LO 0x11
35668 #define A_TP_MIB_TCP_OUT_SEG_HI 0x12
35669 #define A_TP_MIB_TCP_OUT_SEG_LO 0x13
35670 #define A_TP_MIB_TCP_RXT_SEG_HI 0x14
35671 #define A_TP_MIB_TCP_RXT_SEG_LO 0x15
35672 #define A_TP_MIB_TNL_CNG_DROP_0 0x18
35673 #define A_TP_MIB_TNL_CNG_DROP_1 0x19
35674 #define A_TP_MIB_TNL_CNG_DROP_2 0x1a
35675 #define A_TP_MIB_TNL_CNG_DROP_3 0x1b
35676 #define A_TP_MIB_OFD_CHN_DROP_0 0x1c
35677 #define A_TP_MIB_OFD_CHN_DROP_1 0x1d
35678 #define A_TP_MIB_OFD_CHN_DROP_2 0x1e
35679 #define A_TP_MIB_OFD_CHN_DROP_3 0x1f
35680 #define A_TP_MIB_TNL_OUT_PKT_0 0x20
35681 #define A_TP_MIB_TNL_OUT_PKT_1 0x21
35682 #define A_TP_MIB_TNL_OUT_PKT_2 0x22
35683 #define A_TP_MIB_TNL_OUT_PKT_3 0x23
35684 #define A_TP_MIB_TNL_IN_PKT_0 0x24
35685 #define A_TP_MIB_TNL_IN_PKT_1 0x25
35686 #define A_TP_MIB_TNL_IN_PKT_2 0x26
35687 #define A_TP_MIB_TNL_IN_PKT_3 0x27
35688 #define A_TP_MIB_TCP_V6IN_ERR_0 0x28
35689 #define A_TP_MIB_TCP_V6IN_ERR_1 0x29
35690 #define A_TP_MIB_TCP_V6IN_ERR_2 0x2a
35691 #define A_TP_MIB_TCP_V6IN_ERR_3 0x2b
35692 #define A_TP_MIB_TCP_V6OUT_RST 0x2c
35693 #define A_TP_MIB_TCP_V6IN_SEG_HI 0x30
35694 #define A_TP_MIB_TCP_V6IN_SEG_LO 0x31
35695 #define A_TP_MIB_TCP_V6OUT_SEG_HI 0x32
35696 #define A_TP_MIB_TCP_V6OUT_SEG_LO 0x33
35697 #define A_TP_MIB_TCP_V6RXT_SEG_HI 0x34
35698 #define A_TP_MIB_TCP_V6RXT_SEG_LO 0x35
35699 #define A_TP_MIB_OFD_ARP_DROP 0x36
35700 #define A_TP_MIB_OFD_DFR_DROP 0x37
35701 #define A_TP_MIB_CPL_IN_REQ_0 0x38
35702 #define A_TP_MIB_CPL_IN_REQ_1 0x39
35703 #define A_TP_MIB_CPL_IN_REQ_2 0x3a
35704 #define A_TP_MIB_CPL_IN_REQ_3 0x3b
35705 #define A_TP_MIB_CPL_OUT_RSP_0 0x3c
35706 #define A_TP_MIB_CPL_OUT_RSP_1 0x3d
35707 #define A_TP_MIB_CPL_OUT_RSP_2 0x3e
35708 #define A_TP_MIB_CPL_OUT_RSP_3 0x3f
35709 #define A_TP_MIB_TNL_LPBK_0 0x40
35710 #define A_TP_MIB_TNL_LPBK_1 0x41
35711 #define A_TP_MIB_TNL_LPBK_2 0x42
35712 #define A_TP_MIB_TNL_LPBK_3 0x43
35713 #define A_TP_MIB_TNL_DROP_0 0x44
35714 #define A_TP_MIB_TNL_DROP_1 0x45
35715 #define A_TP_MIB_TNL_DROP_2 0x46
35716 #define A_TP_MIB_TNL_DROP_3 0x47
35717 #define A_TP_MIB_FCOE_DDP_0 0x48
35718 #define A_TP_MIB_FCOE_DDP_1 0x49
35719 #define A_TP_MIB_FCOE_DDP_2 0x4a
35720 #define A_TP_MIB_FCOE_DDP_3 0x4b
35721 #define A_TP_MIB_FCOE_DROP_0 0x4c
35722 #define A_TP_MIB_FCOE_DROP_1 0x4d
35723 #define A_TP_MIB_FCOE_DROP_2 0x4e
35724 #define A_TP_MIB_FCOE_DROP_3 0x4f
35725 #define A_TP_MIB_FCOE_BYTE_0_HI 0x50
35726 #define A_TP_MIB_FCOE_BYTE_0_LO 0x51
35727 #define A_TP_MIB_FCOE_BYTE_1_HI 0x52
35728 #define A_TP_MIB_FCOE_BYTE_1_LO 0x53
35729 #define A_TP_MIB_FCOE_BYTE_2_HI 0x54
35730 #define A_TP_MIB_FCOE_BYTE_2_LO 0x55
35731 #define A_TP_MIB_FCOE_BYTE_3_HI 0x56
35732 #define A_TP_MIB_FCOE_BYTE_3_LO 0x57
35733 #define A_TP_MIB_OFD_VLN_DROP_0 0x58
35734 #define A_TP_MIB_OFD_VLN_DROP_1 0x59
35735 #define A_TP_MIB_OFD_VLN_DROP_2 0x5a
35736 #define A_TP_MIB_OFD_VLN_DROP_3 0x5b
35737 #define A_TP_MIB_USM_PKTS 0x5c
35738 #define A_TP_MIB_USM_DROP 0x5d
35739 #define A_TP_MIB_USM_BYTES_HI 0x5e
35740 #define A_TP_MIB_USM_BYTES_LO 0x5f
35741 #define A_TP_MIB_TID_DEL 0x60
35742 #define A_TP_MIB_TID_INV 0x61
35743 #define A_TP_MIB_TID_ACT 0x62
35744 #define A_TP_MIB_TID_PAS 0x63
35745 #define A_TP_MIB_RQE_DFR_PKT 0x64
35746 #define A_TP_MIB_RQE_DFR_MOD 0x65
35747 #define A_TP_MIB_CPL_OUT_ERR_0 0x68
35748 #define A_TP_MIB_CPL_OUT_ERR_1 0x69
35749 #define A_TP_MIB_CPL_OUT_ERR_2 0x6a
35750 #define A_TP_MIB_CPL_OUT_ERR_3 0x6b
35751 #define A_TP_MIB_ENG_LINE_0 0x6c
35752 #define A_TP_MIB_ENG_LINE_1 0x6d
35753 #define A_TP_MIB_ENG_LINE_2 0x6e
35754 #define A_TP_MIB_ENG_LINE_3 0x6f
35755 #define A_TP_MIB_TNL_ERR_0 0x70
35756 #define A_TP_MIB_TNL_ERR_1 0x71
35757 #define A_TP_MIB_TNL_ERR_2 0x72
35758 #define A_TP_MIB_TNL_ERR_3 0x73
35759 #define A_TP_MIB_RDMA_IN_PKT_0 0x80
35760 #define A_TP_MIB_RDMA_IN_PKT_1 0x81
35761 #define A_TP_MIB_RDMA_IN_PKT_2 0x82
35762 #define A_TP_MIB_RDMA_IN_PKT_3 0x83
35763 #define A_TP_MIB_RDMA_IN_BYTE_HI_0 0x84
35764 #define A_TP_MIB_RDMA_IN_BYTE_LO_0 0x85
35765 #define A_TP_MIB_RDMA_IN_BYTE_HI_1 0x86
35766 #define A_TP_MIB_RDMA_IN_BYTE_LO_1 0x87
35767 #define A_TP_MIB_RDMA_IN_BYTE_HI_2 0x88
35768 #define A_TP_MIB_RDMA_IN_BYTE_LO_2 0x89
35769 #define A_TP_MIB_RDMA_IN_BYTE_HI_3 0x8a
35770 #define A_TP_MIB_RDMA_IN_BYTE_LO_3 0x8b
35771 #define A_TP_MIB_RDMA_OUT_PKT_0 0x90
35772 #define A_TP_MIB_RDMA_OUT_PKT_1 0x91
35773 #define A_TP_MIB_RDMA_OUT_PKT_2 0x92
35774 #define A_TP_MIB_RDMA_OUT_PKT_3 0x93
35775 #define A_TP_MIB_RDMA_OUT_BYTE_HI_0 0x94
35776 #define A_TP_MIB_RDMA_OUT_BYTE_LO_0 0x95
35777 #define A_TP_MIB_RDMA_OUT_BYTE_HI_1 0x96
35778 #define A_TP_MIB_RDMA_OUT_BYTE_LO_1 0x97
35779 #define A_TP_MIB_RDMA_OUT_BYTE_HI_2 0x98
35780 #define A_TP_MIB_RDMA_OUT_BYTE_LO_2 0x99
35781 #define A_TP_MIB_RDMA_OUT_BYTE_HI_3 0x9a
35782 #define A_TP_MIB_RDMA_OUT_BYTE_LO_3 0x9b
35783 #define A_TP_MIB_ISCSI_IN_PKT_0 0xa0
35784 #define A_TP_MIB_ISCSI_IN_PKT_1 0xa1
35785 #define A_TP_MIB_ISCSI_IN_PKT_2 0xa2
35786 #define A_TP_MIB_ISCSI_IN_PKT_3 0xa3
35787 #define A_TP_MIB_ISCSI_IN_BYTE_HI_0 0xa4
35788 #define A_TP_MIB_ISCSI_IN_BYTE_LO_0 0xa5
35789 #define A_TP_MIB_ISCSI_IN_BYTE_HI_1 0xa6
35790 #define A_TP_MIB_ISCSI_IN_BYTE_LO_1 0xa7
35791 #define A_TP_MIB_ISCSI_IN_BYTE_HI_2 0xa8
35792 #define A_TP_MIB_ISCSI_IN_BYTE_LO_2 0xa9
35793 #define A_TP_MIB_ISCSI_IN_BYTE_HI_3 0xaa
35794 #define A_TP_MIB_ISCSI_IN_BYTE_LO_3 0xab
35795 #define A_TP_MIB_ISCSI_OUT_PKT_0 0xb0
35796 #define A_TP_MIB_ISCSI_OUT_PKT_1 0xb1
35797 #define A_TP_MIB_ISCSI_OUT_PKT_2 0xb2
35798 #define A_TP_MIB_ISCSI_OUT_PKT_3 0xb3
35799 #define A_TP_MIB_ISCSI_OUT_BYTE_HI_0 0xb4
35800 #define A_TP_MIB_ISCSI_OUT_BYTE_LO_0 0xb5
35801 #define A_TP_MIB_ISCSI_OUT_BYTE_HI_1 0xb6
35802 #define A_TP_MIB_ISCSI_OUT_BYTE_LO_1 0xb7
35803 #define A_TP_MIB_ISCSI_OUT_BYTE_HI_2 0xb8
35804 #define A_TP_MIB_ISCSI_OUT_BYTE_LO_2 0xb9
35805 #define A_TP_MIB_ISCSI_OUT_BYTE_HI_3 0xba
35806 #define A_TP_MIB_ISCSI_OUT_BYTE_LO_3 0xbb
35807 #define A_TP_MIB_NVMT_IN_PKT_0 0xc0
35808 #define A_TP_MIB_NVMT_IN_PKT_1 0xc1
35809 #define A_TP_MIB_NVMT_IN_PKT_2 0xc2
35810 #define A_TP_MIB_NVMT_IN_PKT_3 0xc3
35811 #define A_TP_MIB_NVMT_IN_BYTE_HI_0 0xc4
35812 #define A_TP_MIB_NVMT_IN_BYTE_LO_0 0xc5
35813 #define A_TP_MIB_NVMT_IN_BYTE_HI_1 0xc6
35814 #define A_TP_MIB_NVMT_IN_BYTE_LO_1 0xc7
35815 #define A_TP_MIB_NVMT_IN_BYTE_HI_2 0xc8
35816 #define A_TP_MIB_NVMT_IN_BYTE_LO_2 0xc9
35817 #define A_TP_MIB_NVMT_IN_BYTE_HI_3 0xca
35818 #define A_TP_MIB_NVMT_IN_BYTE_LO_3 0xcb
35819 #define A_TP_MIB_NVMT_OUT_PKT_0 0xd0
35820 #define A_TP_MIB_NVMT_OUT_PKT_1 0xd1
35821 #define A_TP_MIB_NVMT_OUT_PKT_2 0xd2
35822 #define A_TP_MIB_NVMT_OUT_PKT_3 0xd3
35823 #define A_TP_MIB_NVMT_OUT_BYTE_HI_0 0xd4
35824 #define A_TP_MIB_NVMT_OUT_BYTE_LO_0 0xd5
35825 #define A_TP_MIB_NVMT_OUT_BYTE_HI_1 0xd6
35826 #define A_TP_MIB_NVMT_OUT_BYTE_LO_1 0xd7
35827 #define A_TP_MIB_NVMT_OUT_BYTE_HI_2 0xd8
35828 #define A_TP_MIB_NVMT_OUT_BYTE_LO_2 0xd9
35829 #define A_TP_MIB_NVMT_OUT_BYTE_HI_3 0xda
35830 #define A_TP_MIB_NVMT_OUT_BYTE_LO_3 0xdb
35831 #define A_TP_MIB_TLS_IN_PKT_0 0xe0
35832 #define A_TP_MIB_TLS_IN_PKT_1 0xe1
35833 #define A_TP_MIB_TLS_IN_PKT_2 0xe2
35834 #define A_TP_MIB_TLS_IN_PKT_3 0xe3
35835 #define A_TP_MIB_TLS_IN_BYTE_HI_0 0xe4
35836 #define A_TP_MIB_TLS_IN_BYTE_LO_0 0xe5
35837 #define A_TP_MIB_TLS_IN_BYTE_HI_1 0xe6
35838 #define A_TP_MIB_TLS_IN_BYTE_LO_1 0xe7
35839 #define A_TP_MIB_TLS_IN_BYTE_HI_2 0xe8
35840 #define A_TP_MIB_TLS_IN_BYTE_LO_2 0xe9
35841 #define A_TP_MIB_TLS_IN_BYTE_HI_3 0xea
35842 #define A_TP_MIB_TLS_IN_BYTE_LO_3 0xeb
35843 #define A_TP_MIB_TLS_OUT_PKT_0 0xf0
35844 #define A_TP_MIB_TLS_OUT_PKT_1 0xf1
35845 #define A_TP_MIB_TLS_OUT_PKT_2 0xf2
35846 #define A_TP_MIB_TLS_OUT_PKT_3 0xf3
35847 #define A_TP_MIB_TLS_OUT_BYTE_HI_0 0xf4
35848 #define A_TP_MIB_TLS_OUT_BYTE_LO_0 0xf5
35849 #define A_TP_MIB_TLS_OUT_BYTE_HI_1 0xf6
35850 #define A_TP_MIB_TLS_OUT_BYTE_LO_1 0xf7
35851 #define A_TP_MIB_TLS_OUT_BYTE_HI_2 0xf8
35852 #define A_TP_MIB_TLS_OUT_BYTE_LO_2 0xf9
35853 #define A_TP_MIB_TLS_OUT_BYTE_HI_3 0xfa
35854 #define A_TP_MIB_TLS_OUT_BYTE_LO_3 0xfb
35855 #define A_TP_MIB_ROCE_IN_PKT_0 0x100
35856 #define A_TP_MIB_ROCE_IN_PKT_1 0x101
35857 #define A_TP_MIB_ROCE_IN_PKT_2 0x102
35858 #define A_TP_MIB_ROCE_IN_PKT_3 0x103
35859 #define A_TP_MIB_ROCE_IN_BYTE_HI_0 0x104
35860 #define A_TP_MIB_ROCE_IN_BYTE_LO_0 0x105
35861 #define A_TP_MIB_ROCE_IN_BYTE_HI_1 0x106
35862 #define A_TP_MIB_ROCE_IN_BYTE_LO_1 0x107
35863 #define A_TP_MIB_ROCE_IN_BYTE_HI_2 0x108
35864 #define A_TP_MIB_ROCE_IN_BYTE_LO_2 0x109
35865 #define A_TP_MIB_ROCE_IN_BYTE_HI_3 0x10a
35866 #define A_TP_MIB_ROCE_IN_BYTE_LO_3 0x10b
35867 #define A_TP_MIB_ROCE_OUT_PKT_0 0x110
35868 #define A_TP_MIB_ROCE_OUT_PKT_1 0x111
35869 #define A_TP_MIB_ROCE_OUT_PKT_2 0x112
35870 #define A_TP_MIB_ROCE_OUT_PKT_3 0x113
35871 #define A_TP_MIB_ROCE_OUT_BYTE_HI_0 0x114
35872 #define A_TP_MIB_ROCE_OUT_BYTE_LO_0 0x115
35873 #define A_TP_MIB_ROCE_OUT_BYTE_HI_1 0x116
35874 #define A_TP_MIB_ROCE_OUT_BYTE_LO_1 0x117
35875 #define A_TP_MIB_ROCE_OUT_BYTE_HI_2 0x118
35876 #define A_TP_MIB_ROCE_OUT_BYTE_LO_2 0x119
35877 #define A_TP_MIB_ROCE_OUT_BYTE_HI_3 0x11a
35878 #define A_TP_MIB_ROCE_OUT_BYTE_LO_3 0x11b
35879 #define A_TP_MIB_IPSEC_TNL_IN_PKT_0 0x120
35880 #define A_TP_MIB_IPSEC_TNL_IN_PKT_1 0x121
35881 #define A_TP_MIB_IPSEC_TNL_IN_PKT_2 0x122
35882 #define A_TP_MIB_IPSEC_TNL_IN_PKT_3 0x123
35883 #define A_TP_MIB_IPSEC_TNL_IN_BYTE_HI_0 0x124
35884 #define A_TP_MIB_IPSEC_TNL_IN_BYTE_LO_0 0x125
35885 #define A_TP_MIB_IPSEC_TNL_IN_BYTE_HI_1 0x126
35886 #define A_TP_MIB_IPSEC_TNL_IN_BYTE_LO_1 0x127
35887 #define A_TP_MIB_IPSEC_TNL_IN_BYTE_HI_2 0x128
35888 #define A_TP_MIB_IPSEC_TNL_IN_BYTE_LO_2 0x129
35889 #define A_TP_MIB_IPSEC_TNL_IN_BYTE_HI_3 0x12a
35890 #define A_TP_MIB_IPSEC_TNL_IN_BYTE_LO_3 0x12b
35891 #define A_TP_MIB_IPSEC_TNL_OUT_PKT_0 0x130
35892 #define A_TP_MIB_IPSEC_TNL_OUT_PKT_1 0x131
35893 #define A_TP_MIB_IPSEC_TNL_OUT_PKT_2 0x132
35894 #define A_TP_MIB_IPSEC_TNL_OUT_PKT_3 0x133
35895 #define A_TP_MIB_IPSEC_TNL_OUT_BYTE_HI_0 0x134
35896 #define A_TP_MIB_IPSEC_TNL_OUT_BYTE_LO_0 0x135
35897 #define A_TP_MIB_IPSEC_TNL_OUT_BYTE_HI_1 0x136
35898 #define A_TP_MIB_IPSEC_TNL_OUT_BYTE_LO_1 0x137
35899 #define A_TP_MIB_IPSEC_TNL_OUT_BYTE_HI_2 0x138
35900 #define A_TP_MIB_IPSEC_TNL_OUT_BYTE_LO_2 0x139
35901 #define A_TP_MIB_IPSEC_TNL_OUT_BYTE_HI_3 0x13a
35902 #define A_TP_MIB_IPSEC_TNL_OUT_BYTE_LO_3 0x13b
35903 #define A_TP_MIB_IPSEC_OFD_IN_PKT_0 0x140
35904 #define A_TP_MIB_IPSEC_OFD_IN_PKT_1 0x141
35905 #define A_TP_MIB_IPSEC_OFD_IN_PKT_2 0x142
35906 #define A_TP_MIB_IPSEC_OFD_IN_PKT_3 0x143
35907 #define A_TP_MIB_IPSEC_OFD_IN_BYTE_HI_0 0x144
35908 #define A_TP_MIB_IPSEC_OFD_IN_BYTE_LO_0 0x145
35909 #define A_TP_MIB_IPSEC_OFD_IN_BYTE_HI_1 0x146
35910 #define A_TP_MIB_IPSEC_OFD_IN_BYTE_LO_1 0x147
35911 #define A_TP_MIB_IPSEC_OFD_IN_BYTE_HI_2 0x148
35912 #define A_TP_MIB_IPSEC_OFD_IN_BYTE_LO_2 0x149
35913 #define A_TP_MIB_IPSEC_OFD_IN_BYTE_HI_3 0x14a
35914 #define A_TP_MIB_IPSEC_OFD_IN_BYTE_LO_3 0x14b
35915 #define A_TP_MIB_IPSEC_OFD_OUT_PKT_0 0x150
35916 #define A_TP_MIB_IPSEC_OFD_OUT_PKT_1 0x151
35917 #define A_TP_MIB_IPSEC_OFD_OUT_PKT_2 0x152
35918 #define A_TP_MIB_IPSEC_OFD_OUT_PKT_3 0x153
35919 #define A_TP_MIB_IPSEC_OFD_OUT_BYTE_HI_0 0x154
35920 #define A_TP_MIB_IPSEC_OFD_OUT_BYTE_LO_0 0x155
35921 #define A_TP_MIB_IPSEC_OFD_OUT_BYTE_HI_1 0x156
35922 #define A_TP_MIB_IPSEC_OFD_OUT_BYTE_LO_1 0x157
35923 #define A_TP_MIB_IPSEC_OFD_OUT_BYTE_HI_2 0x158
35924 #define A_TP_MIB_IPSEC_OFD_OUT_BYTE_LO_2 0x159
35925 #define A_TP_MIB_IPSEC_OFD_OUT_BYTE_HI_3 0x15a
35926 #define A_TP_MIB_IPSEC_OFD_OUT_BYTE_LO_3 0x15b
35927 
35928 /* registers for module ULP_TX */
35929 #define ULP_TX_BASE_ADDR 0x8dc0
35930 
35931 #define A_ULP_TX_CONFIG 0x8dc0
35932 
35933 #define S_STAG_MIX_ENABLE    2
35934 #define V_STAG_MIX_ENABLE(x) ((x) << S_STAG_MIX_ENABLE)
35935 #define F_STAG_MIX_ENABLE    V_STAG_MIX_ENABLE(1U)
35936 
35937 #define S_STAGF_FIX_DISABLE    1
35938 #define V_STAGF_FIX_DISABLE(x) ((x) << S_STAGF_FIX_DISABLE)
35939 #define F_STAGF_FIX_DISABLE    V_STAGF_FIX_DISABLE(1U)
35940 
35941 #define S_EXTRA_TAG_INSERTION_ENABLE    0
35942 #define V_EXTRA_TAG_INSERTION_ENABLE(x) ((x) << S_EXTRA_TAG_INSERTION_ENABLE)
35943 #define F_EXTRA_TAG_INSERTION_ENABLE    V_EXTRA_TAG_INSERTION_ENABLE(1U)
35944 
35945 #define S_PHYS_ADDR_RESP_EN    6
35946 #define V_PHYS_ADDR_RESP_EN(x) ((x) << S_PHYS_ADDR_RESP_EN)
35947 #define F_PHYS_ADDR_RESP_EN    V_PHYS_ADDR_RESP_EN(1U)
35948 
35949 #define S_ENDIANESS_CHANGE    5
35950 #define V_ENDIANESS_CHANGE(x) ((x) << S_ENDIANESS_CHANGE)
35951 #define F_ENDIANESS_CHANGE    V_ENDIANESS_CHANGE(1U)
35952 
35953 #define S_ERR_RTAG_EN    4
35954 #define V_ERR_RTAG_EN(x) ((x) << S_ERR_RTAG_EN)
35955 #define F_ERR_RTAG_EN    V_ERR_RTAG_EN(1U)
35956 
35957 #define S_TSO_ETHLEN_EN    3
35958 #define V_TSO_ETHLEN_EN(x) ((x) << S_TSO_ETHLEN_EN)
35959 #define F_TSO_ETHLEN_EN    V_TSO_ETHLEN_EN(1U)
35960 
35961 #define S_EMSG_MORE_INFO    2
35962 #define V_EMSG_MORE_INFO(x) ((x) << S_EMSG_MORE_INFO)
35963 #define F_EMSG_MORE_INFO    V_EMSG_MORE_INFO(1U)
35964 
35965 #define S_LOSDR    1
35966 #define V_LOSDR(x) ((x) << S_LOSDR)
35967 #define F_LOSDR    V_LOSDR(1U)
35968 
35969 #define S_ULIMIT_EXCLUSIVE_FIX    16
35970 #define V_ULIMIT_EXCLUSIVE_FIX(x) ((x) << S_ULIMIT_EXCLUSIVE_FIX)
35971 #define F_ULIMIT_EXCLUSIVE_FIX    V_ULIMIT_EXCLUSIVE_FIX(1U)
35972 
35973 #define S_ISO_A_FLAG_EN    15
35974 #define V_ISO_A_FLAG_EN(x) ((x) << S_ISO_A_FLAG_EN)
35975 #define F_ISO_A_FLAG_EN    V_ISO_A_FLAG_EN(1U)
35976 
35977 #define S_IWARP_SEQ_FLIT_DIS    14
35978 #define V_IWARP_SEQ_FLIT_DIS(x) ((x) << S_IWARP_SEQ_FLIT_DIS)
35979 #define F_IWARP_SEQ_FLIT_DIS    V_IWARP_SEQ_FLIT_DIS(1U)
35980 
35981 #define S_MR_SIZE_FIX_EN    13
35982 #define V_MR_SIZE_FIX_EN(x) ((x) << S_MR_SIZE_FIX_EN)
35983 #define F_MR_SIZE_FIX_EN    V_MR_SIZE_FIX_EN(1U)
35984 
35985 #define S_T10_ISO_FIX_EN    12
35986 #define V_T10_ISO_FIX_EN(x) ((x) << S_T10_ISO_FIX_EN)
35987 #define F_T10_ISO_FIX_EN    V_T10_ISO_FIX_EN(1U)
35988 
35989 #define S_CPL_FLAGS_UPDATE_EN    11
35990 #define V_CPL_FLAGS_UPDATE_EN(x) ((x) << S_CPL_FLAGS_UPDATE_EN)
35991 #define F_CPL_FLAGS_UPDATE_EN    V_CPL_FLAGS_UPDATE_EN(1U)
35992 
35993 #define S_IWARP_SEQ_UPDATE_EN    10
35994 #define V_IWARP_SEQ_UPDATE_EN(x) ((x) << S_IWARP_SEQ_UPDATE_EN)
35995 #define F_IWARP_SEQ_UPDATE_EN    V_IWARP_SEQ_UPDATE_EN(1U)
35996 
35997 #define S_SEQ_UPDATE_EN    9
35998 #define V_SEQ_UPDATE_EN(x) ((x) << S_SEQ_UPDATE_EN)
35999 #define F_SEQ_UPDATE_EN    V_SEQ_UPDATE_EN(1U)
36000 
36001 #define S_ERR_ITT_EN    8
36002 #define V_ERR_ITT_EN(x) ((x) << S_ERR_ITT_EN)
36003 #define F_ERR_ITT_EN    V_ERR_ITT_EN(1U)
36004 
36005 #define S_ATOMIC_FIX_DIS    7
36006 #define V_ATOMIC_FIX_DIS(x) ((x) << S_ATOMIC_FIX_DIS)
36007 #define F_ATOMIC_FIX_DIS    V_ATOMIC_FIX_DIS(1U)
36008 
36009 #define S_LB_LEN_SEL    28
36010 #define V_LB_LEN_SEL(x) ((x) << S_LB_LEN_SEL)
36011 #define F_LB_LEN_SEL    V_LB_LEN_SEL(1U)
36012 
36013 #define S_DISABLE_TPT_CREDIT_CHK    27
36014 #define V_DISABLE_TPT_CREDIT_CHK(x) ((x) << S_DISABLE_TPT_CREDIT_CHK)
36015 #define F_DISABLE_TPT_CREDIT_CHK    V_DISABLE_TPT_CREDIT_CHK(1U)
36016 
36017 #define S_REQSRC    26
36018 #define V_REQSRC(x) ((x) << S_REQSRC)
36019 #define F_REQSRC    V_REQSRC(1U)
36020 
36021 #define S_ERR2UP    25
36022 #define V_ERR2UP(x) ((x) << S_ERR2UP)
36023 #define F_ERR2UP    V_ERR2UP(1U)
36024 
36025 #define S_SGE_INVALIDATE_DIS    24
36026 #define V_SGE_INVALIDATE_DIS(x) ((x) << S_SGE_INVALIDATE_DIS)
36027 #define F_SGE_INVALIDATE_DIS    V_SGE_INVALIDATE_DIS(1U)
36028 
36029 #define S_ROCE_ACKREQ_CTRL    23
36030 #define V_ROCE_ACKREQ_CTRL(x) ((x) << S_ROCE_ACKREQ_CTRL)
36031 #define F_ROCE_ACKREQ_CTRL    V_ROCE_ACKREQ_CTRL(1U)
36032 
36033 #define S_MEM_ADDR_CTRL    21
36034 #define M_MEM_ADDR_CTRL    0x3U
36035 #define V_MEM_ADDR_CTRL(x) ((x) << S_MEM_ADDR_CTRL)
36036 #define G_MEM_ADDR_CTRL(x) (((x) >> S_MEM_ADDR_CTRL) & M_MEM_ADDR_CTRL)
36037 
36038 #define S_TPT_EXTENSION_MODE    20
36039 #define V_TPT_EXTENSION_MODE(x) ((x) << S_TPT_EXTENSION_MODE)
36040 #define F_TPT_EXTENSION_MODE    V_TPT_EXTENSION_MODE(1U)
36041 
36042 #define S_XRC_INDICATION    19
36043 #define V_XRC_INDICATION(x) ((x) << S_XRC_INDICATION)
36044 #define F_XRC_INDICATION    V_XRC_INDICATION(1U)
36045 
36046 #define S_LSO_1SEG_LEN_UPD_EN    18
36047 #define V_LSO_1SEG_LEN_UPD_EN(x) ((x) << S_LSO_1SEG_LEN_UPD_EN)
36048 #define F_LSO_1SEG_LEN_UPD_EN    V_LSO_1SEG_LEN_UPD_EN(1U)
36049 
36050 #define S_PKT_ISGL_ERR_ST_EN    17
36051 #define V_PKT_ISGL_ERR_ST_EN(x) ((x) << S_PKT_ISGL_ERR_ST_EN)
36052 #define F_PKT_ISGL_ERR_ST_EN    V_PKT_ISGL_ERR_ST_EN(1U)
36053 
36054 #define A_ULP_TX_PERR_INJECT 0x8dc4
36055 
36056 #define S_T7_1_MEMSEL    1
36057 #define M_T7_1_MEMSEL    0x7fU
36058 #define V_T7_1_MEMSEL(x) ((x) << S_T7_1_MEMSEL)
36059 #define G_T7_1_MEMSEL(x) (((x) >> S_T7_1_MEMSEL) & M_T7_1_MEMSEL)
36060 
36061 #define A_ULP_TX_INT_ENABLE 0x8dc8
36062 
36063 #define S_PBL_BOUND_ERR_CH3    31
36064 #define V_PBL_BOUND_ERR_CH3(x) ((x) << S_PBL_BOUND_ERR_CH3)
36065 #define F_PBL_BOUND_ERR_CH3    V_PBL_BOUND_ERR_CH3(1U)
36066 
36067 #define S_PBL_BOUND_ERR_CH2    30
36068 #define V_PBL_BOUND_ERR_CH2(x) ((x) << S_PBL_BOUND_ERR_CH2)
36069 #define F_PBL_BOUND_ERR_CH2    V_PBL_BOUND_ERR_CH2(1U)
36070 
36071 #define S_PBL_BOUND_ERR_CH1    29
36072 #define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
36073 #define F_PBL_BOUND_ERR_CH1    V_PBL_BOUND_ERR_CH1(1U)
36074 
36075 #define S_PBL_BOUND_ERR_CH0    28
36076 #define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
36077 #define F_PBL_BOUND_ERR_CH0    V_PBL_BOUND_ERR_CH0(1U)
36078 
36079 #define S_SGE2ULP_FIFO_PERR_SET3    27
36080 #define V_SGE2ULP_FIFO_PERR_SET3(x) ((x) << S_SGE2ULP_FIFO_PERR_SET3)
36081 #define F_SGE2ULP_FIFO_PERR_SET3    V_SGE2ULP_FIFO_PERR_SET3(1U)
36082 
36083 #define S_SGE2ULP_FIFO_PERR_SET2    26
36084 #define V_SGE2ULP_FIFO_PERR_SET2(x) ((x) << S_SGE2ULP_FIFO_PERR_SET2)
36085 #define F_SGE2ULP_FIFO_PERR_SET2    V_SGE2ULP_FIFO_PERR_SET2(1U)
36086 
36087 #define S_SGE2ULP_FIFO_PERR_SET1    25
36088 #define V_SGE2ULP_FIFO_PERR_SET1(x) ((x) << S_SGE2ULP_FIFO_PERR_SET1)
36089 #define F_SGE2ULP_FIFO_PERR_SET1    V_SGE2ULP_FIFO_PERR_SET1(1U)
36090 
36091 #define S_SGE2ULP_FIFO_PERR_SET0    24
36092 #define V_SGE2ULP_FIFO_PERR_SET0(x) ((x) << S_SGE2ULP_FIFO_PERR_SET0)
36093 #define F_SGE2ULP_FIFO_PERR_SET0    V_SGE2ULP_FIFO_PERR_SET0(1U)
36094 
36095 #define S_CIM2ULP_FIFO_PERR_SET3    23
36096 #define V_CIM2ULP_FIFO_PERR_SET3(x) ((x) << S_CIM2ULP_FIFO_PERR_SET3)
36097 #define F_CIM2ULP_FIFO_PERR_SET3    V_CIM2ULP_FIFO_PERR_SET3(1U)
36098 
36099 #define S_CIM2ULP_FIFO_PERR_SET2    22
36100 #define V_CIM2ULP_FIFO_PERR_SET2(x) ((x) << S_CIM2ULP_FIFO_PERR_SET2)
36101 #define F_CIM2ULP_FIFO_PERR_SET2    V_CIM2ULP_FIFO_PERR_SET2(1U)
36102 
36103 #define S_CIM2ULP_FIFO_PERR_SET1    21
36104 #define V_CIM2ULP_FIFO_PERR_SET1(x) ((x) << S_CIM2ULP_FIFO_PERR_SET1)
36105 #define F_CIM2ULP_FIFO_PERR_SET1    V_CIM2ULP_FIFO_PERR_SET1(1U)
36106 
36107 #define S_CIM2ULP_FIFO_PERR_SET0    20
36108 #define V_CIM2ULP_FIFO_PERR_SET0(x) ((x) << S_CIM2ULP_FIFO_PERR_SET0)
36109 #define F_CIM2ULP_FIFO_PERR_SET0    V_CIM2ULP_FIFO_PERR_SET0(1U)
36110 
36111 #define S_CQE_FIFO_PERR_SET3    19
36112 #define V_CQE_FIFO_PERR_SET3(x) ((x) << S_CQE_FIFO_PERR_SET3)
36113 #define F_CQE_FIFO_PERR_SET3    V_CQE_FIFO_PERR_SET3(1U)
36114 
36115 #define S_CQE_FIFO_PERR_SET2    18
36116 #define V_CQE_FIFO_PERR_SET2(x) ((x) << S_CQE_FIFO_PERR_SET2)
36117 #define F_CQE_FIFO_PERR_SET2    V_CQE_FIFO_PERR_SET2(1U)
36118 
36119 #define S_CQE_FIFO_PERR_SET1    17
36120 #define V_CQE_FIFO_PERR_SET1(x) ((x) << S_CQE_FIFO_PERR_SET1)
36121 #define F_CQE_FIFO_PERR_SET1    V_CQE_FIFO_PERR_SET1(1U)
36122 
36123 #define S_CQE_FIFO_PERR_SET0    16
36124 #define V_CQE_FIFO_PERR_SET0(x) ((x) << S_CQE_FIFO_PERR_SET0)
36125 #define F_CQE_FIFO_PERR_SET0    V_CQE_FIFO_PERR_SET0(1U)
36126 
36127 #define S_PBL_FIFO_PERR_SET3    15
36128 #define V_PBL_FIFO_PERR_SET3(x) ((x) << S_PBL_FIFO_PERR_SET3)
36129 #define F_PBL_FIFO_PERR_SET3    V_PBL_FIFO_PERR_SET3(1U)
36130 
36131 #define S_PBL_FIFO_PERR_SET2    14
36132 #define V_PBL_FIFO_PERR_SET2(x) ((x) << S_PBL_FIFO_PERR_SET2)
36133 #define F_PBL_FIFO_PERR_SET2    V_PBL_FIFO_PERR_SET2(1U)
36134 
36135 #define S_PBL_FIFO_PERR_SET1    13
36136 #define V_PBL_FIFO_PERR_SET1(x) ((x) << S_PBL_FIFO_PERR_SET1)
36137 #define F_PBL_FIFO_PERR_SET1    V_PBL_FIFO_PERR_SET1(1U)
36138 
36139 #define S_PBL_FIFO_PERR_SET0    12
36140 #define V_PBL_FIFO_PERR_SET0(x) ((x) << S_PBL_FIFO_PERR_SET0)
36141 #define F_PBL_FIFO_PERR_SET0    V_PBL_FIFO_PERR_SET0(1U)
36142 
36143 #define S_CMD_FIFO_PERR_SET3    11
36144 #define V_CMD_FIFO_PERR_SET3(x) ((x) << S_CMD_FIFO_PERR_SET3)
36145 #define F_CMD_FIFO_PERR_SET3    V_CMD_FIFO_PERR_SET3(1U)
36146 
36147 #define S_CMD_FIFO_PERR_SET2    10
36148 #define V_CMD_FIFO_PERR_SET2(x) ((x) << S_CMD_FIFO_PERR_SET2)
36149 #define F_CMD_FIFO_PERR_SET2    V_CMD_FIFO_PERR_SET2(1U)
36150 
36151 #define S_CMD_FIFO_PERR_SET1    9
36152 #define V_CMD_FIFO_PERR_SET1(x) ((x) << S_CMD_FIFO_PERR_SET1)
36153 #define F_CMD_FIFO_PERR_SET1    V_CMD_FIFO_PERR_SET1(1U)
36154 
36155 #define S_CMD_FIFO_PERR_SET0    8
36156 #define V_CMD_FIFO_PERR_SET0(x) ((x) << S_CMD_FIFO_PERR_SET0)
36157 #define F_CMD_FIFO_PERR_SET0    V_CMD_FIFO_PERR_SET0(1U)
36158 
36159 #define S_LSO_HDR_SRAM_PERR_SET3    7
36160 #define V_LSO_HDR_SRAM_PERR_SET3(x) ((x) << S_LSO_HDR_SRAM_PERR_SET3)
36161 #define F_LSO_HDR_SRAM_PERR_SET3    V_LSO_HDR_SRAM_PERR_SET3(1U)
36162 
36163 #define S_LSO_HDR_SRAM_PERR_SET2    6
36164 #define V_LSO_HDR_SRAM_PERR_SET2(x) ((x) << S_LSO_HDR_SRAM_PERR_SET2)
36165 #define F_LSO_HDR_SRAM_PERR_SET2    V_LSO_HDR_SRAM_PERR_SET2(1U)
36166 
36167 #define S_LSO_HDR_SRAM_PERR_SET1    5
36168 #define V_LSO_HDR_SRAM_PERR_SET1(x) ((x) << S_LSO_HDR_SRAM_PERR_SET1)
36169 #define F_LSO_HDR_SRAM_PERR_SET1    V_LSO_HDR_SRAM_PERR_SET1(1U)
36170 
36171 #define S_LSO_HDR_SRAM_PERR_SET0    4
36172 #define V_LSO_HDR_SRAM_PERR_SET0(x) ((x) << S_LSO_HDR_SRAM_PERR_SET0)
36173 #define F_LSO_HDR_SRAM_PERR_SET0    V_LSO_HDR_SRAM_PERR_SET0(1U)
36174 
36175 #define S_IMM_DATA_PERR_SET_CH3    3
36176 #define V_IMM_DATA_PERR_SET_CH3(x) ((x) << S_IMM_DATA_PERR_SET_CH3)
36177 #define F_IMM_DATA_PERR_SET_CH3    V_IMM_DATA_PERR_SET_CH3(1U)
36178 
36179 #define S_IMM_DATA_PERR_SET_CH2    2
36180 #define V_IMM_DATA_PERR_SET_CH2(x) ((x) << S_IMM_DATA_PERR_SET_CH2)
36181 #define F_IMM_DATA_PERR_SET_CH2    V_IMM_DATA_PERR_SET_CH2(1U)
36182 
36183 #define S_IMM_DATA_PERR_SET_CH1    1
36184 #define V_IMM_DATA_PERR_SET_CH1(x) ((x) << S_IMM_DATA_PERR_SET_CH1)
36185 #define F_IMM_DATA_PERR_SET_CH1    V_IMM_DATA_PERR_SET_CH1(1U)
36186 
36187 #define S_IMM_DATA_PERR_SET_CH0    0
36188 #define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0)
36189 #define F_IMM_DATA_PERR_SET_CH0    V_IMM_DATA_PERR_SET_CH0(1U)
36190 
36191 #define A_ULP_TX_INT_ENABLE_1 0x8dc8
36192 
36193 #define S_TLS_DSGL_PARERR3    3
36194 #define V_TLS_DSGL_PARERR3(x) ((x) << S_TLS_DSGL_PARERR3)
36195 #define F_TLS_DSGL_PARERR3    V_TLS_DSGL_PARERR3(1U)
36196 
36197 #define S_TLS_DSGL_PARERR2    2
36198 #define V_TLS_DSGL_PARERR2(x) ((x) << S_TLS_DSGL_PARERR2)
36199 #define F_TLS_DSGL_PARERR2    V_TLS_DSGL_PARERR2(1U)
36200 
36201 #define S_TLS_DSGL_PARERR1    1
36202 #define V_TLS_DSGL_PARERR1(x) ((x) << S_TLS_DSGL_PARERR1)
36203 #define F_TLS_DSGL_PARERR1    V_TLS_DSGL_PARERR1(1U)
36204 
36205 #define S_TLS_DSGL_PARERR0    0
36206 #define V_TLS_DSGL_PARERR0(x) ((x) << S_TLS_DSGL_PARERR0)
36207 #define F_TLS_DSGL_PARERR0    V_TLS_DSGL_PARERR0(1U)
36208 
36209 #define A_ULP_TX_INT_CAUSE 0x8dcc
36210 #define A_ULP_TX_INT_CAUSE_1 0x8dcc
36211 #define A_ULP_TX_PERR_ENABLE 0x8dd0
36212 #define A_ULP_TX_PERR_ENABLE_1 0x8dd0
36213 #define A_ULP_TX_TPT_LLIMIT 0x8dd4
36214 #define A_ULP_TX_TPT_ULIMIT 0x8dd8
36215 #define A_ULP_TX_PBL_LLIMIT 0x8ddc
36216 #define A_ULP_TX_PBL_ULIMIT 0x8de0
36217 #define A_ULP_TX_CPL_ERR_OFFSET 0x8de4
36218 #define A_ULP_TX_TLS_CTL 0x8de4
36219 
36220 #define S_TLSPERREN    4
36221 #define V_TLSPERREN(x) ((x) << S_TLSPERREN)
36222 #define F_TLSPERREN    V_TLSPERREN(1U)
36223 
36224 #define S_TLSPATHCTL    3
36225 #define V_TLSPATHCTL(x) ((x) << S_TLSPATHCTL)
36226 #define F_TLSPATHCTL    V_TLSPATHCTL(1U)
36227 
36228 #define S_TLSDISABLEIFUSE    2
36229 #define V_TLSDISABLEIFUSE(x) ((x) << S_TLSDISABLEIFUSE)
36230 #define F_TLSDISABLEIFUSE    V_TLSDISABLEIFUSE(1U)
36231 
36232 #define S_TLSDISABLECFUSE    1
36233 #define V_TLSDISABLECFUSE(x) ((x) << S_TLSDISABLECFUSE)
36234 #define F_TLSDISABLECFUSE    V_TLSDISABLECFUSE(1U)
36235 
36236 #define S_TLSDISABLE    0
36237 #define V_TLSDISABLE(x) ((x) << S_TLSDISABLE)
36238 #define F_TLSDISABLE    V_TLSDISABLE(1U)
36239 
36240 #define A_ULP_TX_CPL_ERR_MASK_L 0x8de8
36241 #define A_ULP_TX_FID_1 0x8de8
36242 
36243 #define S_FID_1    0
36244 #define M_FID_1    0x7ffU
36245 #define V_FID_1(x) ((x) << S_FID_1)
36246 #define G_FID_1(x) (((x) >> S_FID_1) & M_FID_1)
36247 
36248 #define A_ULP_TX_CPL_ERR_MASK_H 0x8dec
36249 #define A_ULP_TX_CPL_ERR_VALUE_L 0x8df0
36250 #define A_ULP_TX_CPL_ERR_VALUE_H 0x8df4
36251 #define A_ULP_TX_CPL_PACK_SIZE1 0x8df8
36252 
36253 #define S_CH3SIZE1    24
36254 #define M_CH3SIZE1    0xffU
36255 #define V_CH3SIZE1(x) ((x) << S_CH3SIZE1)
36256 #define G_CH3SIZE1(x) (((x) >> S_CH3SIZE1) & M_CH3SIZE1)
36257 
36258 #define S_CH2SIZE1    16
36259 #define M_CH2SIZE1    0xffU
36260 #define V_CH2SIZE1(x) ((x) << S_CH2SIZE1)
36261 #define G_CH2SIZE1(x) (((x) >> S_CH2SIZE1) & M_CH2SIZE1)
36262 
36263 #define S_CH1SIZE1    8
36264 #define M_CH1SIZE1    0xffU
36265 #define V_CH1SIZE1(x) ((x) << S_CH1SIZE1)
36266 #define G_CH1SIZE1(x) (((x) >> S_CH1SIZE1) & M_CH1SIZE1)
36267 
36268 #define S_CH0SIZE1    0
36269 #define M_CH0SIZE1    0xffU
36270 #define V_CH0SIZE1(x) ((x) << S_CH0SIZE1)
36271 #define G_CH0SIZE1(x) (((x) >> S_CH0SIZE1) & M_CH0SIZE1)
36272 
36273 #define A_ULP_TX_CPL_PACK_SIZE2 0x8dfc
36274 
36275 #define S_CH3SIZE2    24
36276 #define M_CH3SIZE2    0xffU
36277 #define V_CH3SIZE2(x) ((x) << S_CH3SIZE2)
36278 #define G_CH3SIZE2(x) (((x) >> S_CH3SIZE2) & M_CH3SIZE2)
36279 
36280 #define S_CH2SIZE2    16
36281 #define M_CH2SIZE2    0xffU
36282 #define V_CH2SIZE2(x) ((x) << S_CH2SIZE2)
36283 #define G_CH2SIZE2(x) (((x) >> S_CH2SIZE2) & M_CH2SIZE2)
36284 
36285 #define S_CH1SIZE2    8
36286 #define M_CH1SIZE2    0xffU
36287 #define V_CH1SIZE2(x) ((x) << S_CH1SIZE2)
36288 #define G_CH1SIZE2(x) (((x) >> S_CH1SIZE2) & M_CH1SIZE2)
36289 
36290 #define S_CH0SIZE2    0
36291 #define M_CH0SIZE2    0xffU
36292 #define V_CH0SIZE2(x) ((x) << S_CH0SIZE2)
36293 #define G_CH0SIZE2(x) (((x) >> S_CH0SIZE2) & M_CH0SIZE2)
36294 
36295 #define A_ULP_TX_ERR_MSG2CIM 0x8e00
36296 #define A_ULP_TX_ERR_TABLE_BASE 0x8e04
36297 #define A_ULP_TX_ERR_CNT_CH0 0x8e10
36298 
36299 #define S_ERR_CNT0    0
36300 #define M_ERR_CNT0    0xfffffU
36301 #define V_ERR_CNT0(x) ((x) << S_ERR_CNT0)
36302 #define G_ERR_CNT0(x) (((x) >> S_ERR_CNT0) & M_ERR_CNT0)
36303 
36304 #define A_ULP_TX_ERR_CNT_CH1 0x8e14
36305 
36306 #define S_ERR_CNT1    0
36307 #define M_ERR_CNT1    0xfffffU
36308 #define V_ERR_CNT1(x) ((x) << S_ERR_CNT1)
36309 #define G_ERR_CNT1(x) (((x) >> S_ERR_CNT1) & M_ERR_CNT1)
36310 
36311 #define A_ULP_TX_ERR_CNT_CH2 0x8e18
36312 
36313 #define S_ERR_CNT2    0
36314 #define M_ERR_CNT2    0xfffffU
36315 #define V_ERR_CNT2(x) ((x) << S_ERR_CNT2)
36316 #define G_ERR_CNT2(x) (((x) >> S_ERR_CNT2) & M_ERR_CNT2)
36317 
36318 #define A_ULP_TX_ERR_CNT_CH3 0x8e1c
36319 
36320 #define S_ERR_CNT3    0
36321 #define M_ERR_CNT3    0xfffffU
36322 #define V_ERR_CNT3(x) ((x) << S_ERR_CNT3)
36323 #define G_ERR_CNT3(x) (((x) >> S_ERR_CNT3) & M_ERR_CNT3)
36324 
36325 #define A_ULP_TX_FC_SOF 0x8e20
36326 
36327 #define S_SOF_FS3    24
36328 #define M_SOF_FS3    0xffU
36329 #define V_SOF_FS3(x) ((x) << S_SOF_FS3)
36330 #define G_SOF_FS3(x) (((x) >> S_SOF_FS3) & M_SOF_FS3)
36331 
36332 #define S_SOF_FS2    16
36333 #define M_SOF_FS2    0xffU
36334 #define V_SOF_FS2(x) ((x) << S_SOF_FS2)
36335 #define G_SOF_FS2(x) (((x) >> S_SOF_FS2) & M_SOF_FS2)
36336 
36337 #define S_SOF_3    8
36338 #define M_SOF_3    0xffU
36339 #define V_SOF_3(x) ((x) << S_SOF_3)
36340 #define G_SOF_3(x) (((x) >> S_SOF_3) & M_SOF_3)
36341 
36342 #define S_SOF_2    0
36343 #define M_SOF_2    0xffU
36344 #define V_SOF_2(x) ((x) << S_SOF_2)
36345 #define G_SOF_2(x) (((x) >> S_SOF_2) & M_SOF_2)
36346 
36347 #define A_ULP_TX_FC_EOF 0x8e24
36348 
36349 #define S_EOF_LS3    24
36350 #define M_EOF_LS3    0xffU
36351 #define V_EOF_LS3(x) ((x) << S_EOF_LS3)
36352 #define G_EOF_LS3(x) (((x) >> S_EOF_LS3) & M_EOF_LS3)
36353 
36354 #define S_EOF_LS2    16
36355 #define M_EOF_LS2    0xffU
36356 #define V_EOF_LS2(x) ((x) << S_EOF_LS2)
36357 #define G_EOF_LS2(x) (((x) >> S_EOF_LS2) & M_EOF_LS2)
36358 
36359 #define S_EOF_3    8
36360 #define M_EOF_3    0xffU
36361 #define V_EOF_3(x) ((x) << S_EOF_3)
36362 #define G_EOF_3(x) (((x) >> S_EOF_3) & M_EOF_3)
36363 
36364 #define S_EOF_2    0
36365 #define M_EOF_2    0xffU
36366 #define V_EOF_2(x) ((x) << S_EOF_2)
36367 #define G_EOF_2(x) (((x) >> S_EOF_2) & M_EOF_2)
36368 
36369 #define A_ULP_TX_CGEN_GLOBAL 0x8e28
36370 
36371 #define S_ULP_TX_GLOBAL_CGEN    0
36372 #define V_ULP_TX_GLOBAL_CGEN(x) ((x) << S_ULP_TX_GLOBAL_CGEN)
36373 #define F_ULP_TX_GLOBAL_CGEN    V_ULP_TX_GLOBAL_CGEN(1U)
36374 
36375 #define A_ULP_TX_CGEN 0x8e2c
36376 
36377 #define S_ULP_TX_CGEN_STORAGE    8
36378 #define M_ULP_TX_CGEN_STORAGE    0xfU
36379 #define V_ULP_TX_CGEN_STORAGE(x) ((x) << S_ULP_TX_CGEN_STORAGE)
36380 #define G_ULP_TX_CGEN_STORAGE(x) (((x) >> S_ULP_TX_CGEN_STORAGE) & M_ULP_TX_CGEN_STORAGE)
36381 
36382 #define S_ULP_TX_CGEN_RDMA    4
36383 #define M_ULP_TX_CGEN_RDMA    0xfU
36384 #define V_ULP_TX_CGEN_RDMA(x) ((x) << S_ULP_TX_CGEN_RDMA)
36385 #define G_ULP_TX_CGEN_RDMA(x) (((x) >> S_ULP_TX_CGEN_RDMA) & M_ULP_TX_CGEN_RDMA)
36386 
36387 #define S_ULP_TX_CGEN_CHANNEL    0
36388 #define M_ULP_TX_CGEN_CHANNEL    0xfU
36389 #define V_ULP_TX_CGEN_CHANNEL(x) ((x) << S_ULP_TX_CGEN_CHANNEL)
36390 #define G_ULP_TX_CGEN_CHANNEL(x) (((x) >> S_ULP_TX_CGEN_CHANNEL) & M_ULP_TX_CGEN_CHANNEL)
36391 
36392 #define A_ULP_TX_ULP2TP_BIST_CMD 0x8e30
36393 #define A_ULP_TX_MEM_CFG 0x8e30
36394 
36395 #define S_WRREQ_SZ    0
36396 #define M_WRREQ_SZ    0x7U
36397 #define V_WRREQ_SZ(x) ((x) << S_WRREQ_SZ)
36398 #define G_WRREQ_SZ(x) (((x) >> S_WRREQ_SZ) & M_WRREQ_SZ)
36399 
36400 #define S_T7_GLOBALENABLE    31
36401 #define V_T7_GLOBALENABLE(x) ((x) << S_T7_GLOBALENABLE)
36402 #define F_T7_GLOBALENABLE    V_T7_GLOBALENABLE(1U)
36403 
36404 #define S_RDREQ_SZ    3
36405 #define M_RDREQ_SZ    0x7U
36406 #define V_RDREQ_SZ(x) ((x) << S_RDREQ_SZ)
36407 #define G_RDREQ_SZ(x) (((x) >> S_RDREQ_SZ) & M_RDREQ_SZ)
36408 
36409 #define A_ULP_TX_ULP2TP_BIST_ERROR_CNT 0x8e34
36410 #define A_ULP_TX_PERR_INJECT_2 0x8e34
36411 
36412 #define S_T5_MEMSEL    1
36413 #define M_T5_MEMSEL    0x7U
36414 #define V_T5_MEMSEL(x) ((x) << S_T5_MEMSEL)
36415 #define G_T5_MEMSEL(x) (((x) >> S_T5_MEMSEL) & M_T5_MEMSEL)
36416 
36417 #define S_MEMSEL_ULPTX    1
36418 #define M_MEMSEL_ULPTX    0x1fU
36419 #define V_MEMSEL_ULPTX(x) ((x) << S_MEMSEL_ULPTX)
36420 #define G_MEMSEL_ULPTX(x) (((x) >> S_MEMSEL_ULPTX) & M_MEMSEL_ULPTX)
36421 
36422 #define A_ULP_TX_FPGA_CMD_CTRL 0x8e38
36423 #define A_ULP_TX_T5_FPGA_CMD_CTRL 0x8e38
36424 
36425 #define S_CHANNEL_SEL    12
36426 #define M_CHANNEL_SEL    0x3U
36427 #define V_CHANNEL_SEL(x) ((x) << S_CHANNEL_SEL)
36428 #define G_CHANNEL_SEL(x) (((x) >> S_CHANNEL_SEL) & M_CHANNEL_SEL)
36429 
36430 #define S_INTF_SEL    4
36431 #define M_INTF_SEL    0xfU
36432 #define V_INTF_SEL(x) ((x) << S_INTF_SEL)
36433 #define G_INTF_SEL(x) (((x) >> S_INTF_SEL) & M_INTF_SEL)
36434 
36435 #define S_NUM_FLITS    1
36436 #define M_NUM_FLITS    0x7U
36437 #define V_NUM_FLITS(x) ((x) << S_NUM_FLITS)
36438 #define G_NUM_FLITS(x) (((x) >> S_NUM_FLITS) & M_NUM_FLITS)
36439 
36440 #define S_CMD_GEN_EN    0
36441 #define V_CMD_GEN_EN(x) ((x) << S_CMD_GEN_EN)
36442 #define F_CMD_GEN_EN    V_CMD_GEN_EN(1U)
36443 
36444 #define A_ULP_TX_FPGA_CMD_0 0x8e3c
36445 #define A_ULP_TX_T5_FPGA_CMD_0 0x8e3c
36446 #define A_ULP_TX_FPGA_CMD_1 0x8e40
36447 #define A_ULP_TX_T5_FPGA_CMD_1 0x8e40
36448 #define A_ULP_TX_FPGA_CMD_2 0x8e44
36449 #define A_ULP_TX_T5_FPGA_CMD_2 0x8e44
36450 #define A_ULP_TX_FPGA_CMD_3 0x8e48
36451 #define A_ULP_TX_T5_FPGA_CMD_3 0x8e48
36452 #define A_ULP_TX_FPGA_CMD_4 0x8e4c
36453 #define A_ULP_TX_T5_FPGA_CMD_4 0x8e4c
36454 #define A_ULP_TX_FPGA_CMD_5 0x8e50
36455 #define A_ULP_TX_T5_FPGA_CMD_5 0x8e50
36456 #define A_ULP_TX_FPGA_CMD_6 0x8e54
36457 #define A_ULP_TX_T5_FPGA_CMD_6 0x8e54
36458 #define A_ULP_TX_FPGA_CMD_7 0x8e58
36459 #define A_ULP_TX_T5_FPGA_CMD_7 0x8e58
36460 #define A_ULP_TX_FPGA_CMD_8 0x8e5c
36461 #define A_ULP_TX_T5_FPGA_CMD_8 0x8e5c
36462 #define A_ULP_TX_FPGA_CMD_9 0x8e60
36463 #define A_ULP_TX_T5_FPGA_CMD_9 0x8e60
36464 #define A_ULP_TX_FPGA_CMD_10 0x8e64
36465 #define A_ULP_TX_T5_FPGA_CMD_10 0x8e64
36466 #define A_ULP_TX_FPGA_CMD_11 0x8e68
36467 #define A_ULP_TX_T5_FPGA_CMD_11 0x8e68
36468 #define A_ULP_TX_FPGA_CMD_12 0x8e6c
36469 #define A_ULP_TX_T5_FPGA_CMD_12 0x8e6c
36470 #define A_ULP_TX_FPGA_CMD_13 0x8e70
36471 #define A_ULP_TX_T5_FPGA_CMD_13 0x8e70
36472 #define A_ULP_TX_FPGA_CMD_14 0x8e74
36473 #define A_ULP_TX_T5_FPGA_CMD_14 0x8e74
36474 #define A_ULP_TX_FPGA_CMD_15 0x8e78
36475 #define A_ULP_TX_T5_FPGA_CMD_15 0x8e78
36476 #define A_ULP_TX_INT_ENABLE_2 0x8e7c
36477 
36478 #define S_SMARBT2ULP_DATA_PERR_SET    12
36479 #define V_SMARBT2ULP_DATA_PERR_SET(x) ((x) << S_SMARBT2ULP_DATA_PERR_SET)
36480 #define F_SMARBT2ULP_DATA_PERR_SET    V_SMARBT2ULP_DATA_PERR_SET(1U)
36481 
36482 #define S_ULP2TP_DATA_PERR_SET    11
36483 #define V_ULP2TP_DATA_PERR_SET(x) ((x) << S_ULP2TP_DATA_PERR_SET)
36484 #define F_ULP2TP_DATA_PERR_SET    V_ULP2TP_DATA_PERR_SET(1U)
36485 
36486 #define S_MA2ULP_DATA_PERR_SET    10
36487 #define V_MA2ULP_DATA_PERR_SET(x) ((x) << S_MA2ULP_DATA_PERR_SET)
36488 #define F_MA2ULP_DATA_PERR_SET    V_MA2ULP_DATA_PERR_SET(1U)
36489 
36490 #define S_SGE2ULP_DATA_PERR_SET    9
36491 #define V_SGE2ULP_DATA_PERR_SET(x) ((x) << S_SGE2ULP_DATA_PERR_SET)
36492 #define F_SGE2ULP_DATA_PERR_SET    V_SGE2ULP_DATA_PERR_SET(1U)
36493 
36494 #define S_CIM2ULP_DATA_PERR_SET    8
36495 #define V_CIM2ULP_DATA_PERR_SET(x) ((x) << S_CIM2ULP_DATA_PERR_SET)
36496 #define F_CIM2ULP_DATA_PERR_SET    V_CIM2ULP_DATA_PERR_SET(1U)
36497 
36498 #define S_FSO_HDR_SRAM_PERR_SET3    7
36499 #define V_FSO_HDR_SRAM_PERR_SET3(x) ((x) << S_FSO_HDR_SRAM_PERR_SET3)
36500 #define F_FSO_HDR_SRAM_PERR_SET3    V_FSO_HDR_SRAM_PERR_SET3(1U)
36501 
36502 #define S_FSO_HDR_SRAM_PERR_SET2    6
36503 #define V_FSO_HDR_SRAM_PERR_SET2(x) ((x) << S_FSO_HDR_SRAM_PERR_SET2)
36504 #define F_FSO_HDR_SRAM_PERR_SET2    V_FSO_HDR_SRAM_PERR_SET2(1U)
36505 
36506 #define S_FSO_HDR_SRAM_PERR_SET1    5
36507 #define V_FSO_HDR_SRAM_PERR_SET1(x) ((x) << S_FSO_HDR_SRAM_PERR_SET1)
36508 #define F_FSO_HDR_SRAM_PERR_SET1    V_FSO_HDR_SRAM_PERR_SET1(1U)
36509 
36510 #define S_FSO_HDR_SRAM_PERR_SET0    4
36511 #define V_FSO_HDR_SRAM_PERR_SET0(x) ((x) << S_FSO_HDR_SRAM_PERR_SET0)
36512 #define F_FSO_HDR_SRAM_PERR_SET0    V_FSO_HDR_SRAM_PERR_SET0(1U)
36513 
36514 #define S_T10_PI_SRAM_PERR_SET3    3
36515 #define V_T10_PI_SRAM_PERR_SET3(x) ((x) << S_T10_PI_SRAM_PERR_SET3)
36516 #define F_T10_PI_SRAM_PERR_SET3    V_T10_PI_SRAM_PERR_SET3(1U)
36517 
36518 #define S_T10_PI_SRAM_PERR_SET2    2
36519 #define V_T10_PI_SRAM_PERR_SET2(x) ((x) << S_T10_PI_SRAM_PERR_SET2)
36520 #define F_T10_PI_SRAM_PERR_SET2    V_T10_PI_SRAM_PERR_SET2(1U)
36521 
36522 #define S_T10_PI_SRAM_PERR_SET1    1
36523 #define V_T10_PI_SRAM_PERR_SET1(x) ((x) << S_T10_PI_SRAM_PERR_SET1)
36524 #define F_T10_PI_SRAM_PERR_SET1    V_T10_PI_SRAM_PERR_SET1(1U)
36525 
36526 #define S_T10_PI_SRAM_PERR_SET0    0
36527 #define V_T10_PI_SRAM_PERR_SET0(x) ((x) << S_T10_PI_SRAM_PERR_SET0)
36528 #define F_T10_PI_SRAM_PERR_SET0    V_T10_PI_SRAM_PERR_SET0(1U)
36529 
36530 #define S_EDMA_IN_FIFO_PERR_SET3    31
36531 #define V_EDMA_IN_FIFO_PERR_SET3(x) ((x) << S_EDMA_IN_FIFO_PERR_SET3)
36532 #define F_EDMA_IN_FIFO_PERR_SET3    V_EDMA_IN_FIFO_PERR_SET3(1U)
36533 
36534 #define S_EDMA_IN_FIFO_PERR_SET2    30
36535 #define V_EDMA_IN_FIFO_PERR_SET2(x) ((x) << S_EDMA_IN_FIFO_PERR_SET2)
36536 #define F_EDMA_IN_FIFO_PERR_SET2    V_EDMA_IN_FIFO_PERR_SET2(1U)
36537 
36538 #define S_EDMA_IN_FIFO_PERR_SET1    29
36539 #define V_EDMA_IN_FIFO_PERR_SET1(x) ((x) << S_EDMA_IN_FIFO_PERR_SET1)
36540 #define F_EDMA_IN_FIFO_PERR_SET1    V_EDMA_IN_FIFO_PERR_SET1(1U)
36541 
36542 #define S_EDMA_IN_FIFO_PERR_SET0    28
36543 #define V_EDMA_IN_FIFO_PERR_SET0(x) ((x) << S_EDMA_IN_FIFO_PERR_SET0)
36544 #define F_EDMA_IN_FIFO_PERR_SET0    V_EDMA_IN_FIFO_PERR_SET0(1U)
36545 
36546 #define S_ALIGN_CTL_FIFO_PERR_SET3    27
36547 #define V_ALIGN_CTL_FIFO_PERR_SET3(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET3)
36548 #define F_ALIGN_CTL_FIFO_PERR_SET3    V_ALIGN_CTL_FIFO_PERR_SET3(1U)
36549 
36550 #define S_ALIGN_CTL_FIFO_PERR_SET2    26
36551 #define V_ALIGN_CTL_FIFO_PERR_SET2(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET2)
36552 #define F_ALIGN_CTL_FIFO_PERR_SET2    V_ALIGN_CTL_FIFO_PERR_SET2(1U)
36553 
36554 #define S_ALIGN_CTL_FIFO_PERR_SET1    25
36555 #define V_ALIGN_CTL_FIFO_PERR_SET1(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET1)
36556 #define F_ALIGN_CTL_FIFO_PERR_SET1    V_ALIGN_CTL_FIFO_PERR_SET1(1U)
36557 
36558 #define S_ALIGN_CTL_FIFO_PERR_SET0    24
36559 #define V_ALIGN_CTL_FIFO_PERR_SET0(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET0)
36560 #define F_ALIGN_CTL_FIFO_PERR_SET0    V_ALIGN_CTL_FIFO_PERR_SET0(1U)
36561 
36562 #define S_SGE_FIFO_PERR_SET3    23
36563 #define V_SGE_FIFO_PERR_SET3(x) ((x) << S_SGE_FIFO_PERR_SET3)
36564 #define F_SGE_FIFO_PERR_SET3    V_SGE_FIFO_PERR_SET3(1U)
36565 
36566 #define S_SGE_FIFO_PERR_SET2    22
36567 #define V_SGE_FIFO_PERR_SET2(x) ((x) << S_SGE_FIFO_PERR_SET2)
36568 #define F_SGE_FIFO_PERR_SET2    V_SGE_FIFO_PERR_SET2(1U)
36569 
36570 #define S_SGE_FIFO_PERR_SET1    21
36571 #define V_SGE_FIFO_PERR_SET1(x) ((x) << S_SGE_FIFO_PERR_SET1)
36572 #define F_SGE_FIFO_PERR_SET1    V_SGE_FIFO_PERR_SET1(1U)
36573 
36574 #define S_SGE_FIFO_PERR_SET0    20
36575 #define V_SGE_FIFO_PERR_SET0(x) ((x) << S_SGE_FIFO_PERR_SET0)
36576 #define F_SGE_FIFO_PERR_SET0    V_SGE_FIFO_PERR_SET0(1U)
36577 
36578 #define S_STAG_FIFO_PERR_SET3    19
36579 #define V_STAG_FIFO_PERR_SET3(x) ((x) << S_STAG_FIFO_PERR_SET3)
36580 #define F_STAG_FIFO_PERR_SET3    V_STAG_FIFO_PERR_SET3(1U)
36581 
36582 #define S_STAG_FIFO_PERR_SET2    18
36583 #define V_STAG_FIFO_PERR_SET2(x) ((x) << S_STAG_FIFO_PERR_SET2)
36584 #define F_STAG_FIFO_PERR_SET2    V_STAG_FIFO_PERR_SET2(1U)
36585 
36586 #define S_STAG_FIFO_PERR_SET1    17
36587 #define V_STAG_FIFO_PERR_SET1(x) ((x) << S_STAG_FIFO_PERR_SET1)
36588 #define F_STAG_FIFO_PERR_SET1    V_STAG_FIFO_PERR_SET1(1U)
36589 
36590 #define S_STAG_FIFO_PERR_SET0    16
36591 #define V_STAG_FIFO_PERR_SET0(x) ((x) << S_STAG_FIFO_PERR_SET0)
36592 #define F_STAG_FIFO_PERR_SET0    V_STAG_FIFO_PERR_SET0(1U)
36593 
36594 #define S_MAP_FIFO_PERR_SET3    15
36595 #define V_MAP_FIFO_PERR_SET3(x) ((x) << S_MAP_FIFO_PERR_SET3)
36596 #define F_MAP_FIFO_PERR_SET3    V_MAP_FIFO_PERR_SET3(1U)
36597 
36598 #define S_MAP_FIFO_PERR_SET2    14
36599 #define V_MAP_FIFO_PERR_SET2(x) ((x) << S_MAP_FIFO_PERR_SET2)
36600 #define F_MAP_FIFO_PERR_SET2    V_MAP_FIFO_PERR_SET2(1U)
36601 
36602 #define S_MAP_FIFO_PERR_SET1    13
36603 #define V_MAP_FIFO_PERR_SET1(x) ((x) << S_MAP_FIFO_PERR_SET1)
36604 #define F_MAP_FIFO_PERR_SET1    V_MAP_FIFO_PERR_SET1(1U)
36605 
36606 #define S_MAP_FIFO_PERR_SET0    12
36607 #define V_MAP_FIFO_PERR_SET0(x) ((x) << S_MAP_FIFO_PERR_SET0)
36608 #define F_MAP_FIFO_PERR_SET0    V_MAP_FIFO_PERR_SET0(1U)
36609 
36610 #define S_DMA_FIFO_PERR_SET3    11
36611 #define V_DMA_FIFO_PERR_SET3(x) ((x) << S_DMA_FIFO_PERR_SET3)
36612 #define F_DMA_FIFO_PERR_SET3    V_DMA_FIFO_PERR_SET3(1U)
36613 
36614 #define S_DMA_FIFO_PERR_SET2    10
36615 #define V_DMA_FIFO_PERR_SET2(x) ((x) << S_DMA_FIFO_PERR_SET2)
36616 #define F_DMA_FIFO_PERR_SET2    V_DMA_FIFO_PERR_SET2(1U)
36617 
36618 #define S_DMA_FIFO_PERR_SET1    9
36619 #define V_DMA_FIFO_PERR_SET1(x) ((x) << S_DMA_FIFO_PERR_SET1)
36620 #define F_DMA_FIFO_PERR_SET1    V_DMA_FIFO_PERR_SET1(1U)
36621 
36622 #define S_DMA_FIFO_PERR_SET0    8
36623 #define V_DMA_FIFO_PERR_SET0(x) ((x) << S_DMA_FIFO_PERR_SET0)
36624 #define F_DMA_FIFO_PERR_SET0    V_DMA_FIFO_PERR_SET0(1U)
36625 
36626 #define A_ULP_TX_INT_CAUSE_2 0x8e80
36627 #define A_ULP_TX_PERR_ENABLE_2 0x8e84
36628 #define A_ULP_TX_INT_ENABLE_3 0x8e88
36629 
36630 #define S_GF_SGE_FIFO_PARERR3    31
36631 #define V_GF_SGE_FIFO_PARERR3(x) ((x) << S_GF_SGE_FIFO_PARERR3)
36632 #define F_GF_SGE_FIFO_PARERR3    V_GF_SGE_FIFO_PARERR3(1U)
36633 
36634 #define S_GF_SGE_FIFO_PARERR2    30
36635 #define V_GF_SGE_FIFO_PARERR2(x) ((x) << S_GF_SGE_FIFO_PARERR2)
36636 #define F_GF_SGE_FIFO_PARERR2    V_GF_SGE_FIFO_PARERR2(1U)
36637 
36638 #define S_GF_SGE_FIFO_PARERR1    29
36639 #define V_GF_SGE_FIFO_PARERR1(x) ((x) << S_GF_SGE_FIFO_PARERR1)
36640 #define F_GF_SGE_FIFO_PARERR1    V_GF_SGE_FIFO_PARERR1(1U)
36641 
36642 #define S_GF_SGE_FIFO_PARERR0    28
36643 #define V_GF_SGE_FIFO_PARERR0(x) ((x) << S_GF_SGE_FIFO_PARERR0)
36644 #define F_GF_SGE_FIFO_PARERR0    V_GF_SGE_FIFO_PARERR0(1U)
36645 
36646 #define S_DEDUPE_SGE_FIFO_PARERR3    27
36647 #define V_DEDUPE_SGE_FIFO_PARERR3(x) ((x) << S_DEDUPE_SGE_FIFO_PARERR3)
36648 #define F_DEDUPE_SGE_FIFO_PARERR3    V_DEDUPE_SGE_FIFO_PARERR3(1U)
36649 
36650 #define S_DEDUPE_SGE_FIFO_PARERR2    26
36651 #define V_DEDUPE_SGE_FIFO_PARERR2(x) ((x) << S_DEDUPE_SGE_FIFO_PARERR2)
36652 #define F_DEDUPE_SGE_FIFO_PARERR2    V_DEDUPE_SGE_FIFO_PARERR2(1U)
36653 
36654 #define S_DEDUPE_SGE_FIFO_PARERR1    25
36655 #define V_DEDUPE_SGE_FIFO_PARERR1(x) ((x) << S_DEDUPE_SGE_FIFO_PARERR1)
36656 #define F_DEDUPE_SGE_FIFO_PARERR1    V_DEDUPE_SGE_FIFO_PARERR1(1U)
36657 
36658 #define S_DEDUPE_SGE_FIFO_PARERR0    24
36659 #define V_DEDUPE_SGE_FIFO_PARERR0(x) ((x) << S_DEDUPE_SGE_FIFO_PARERR0)
36660 #define F_DEDUPE_SGE_FIFO_PARERR0    V_DEDUPE_SGE_FIFO_PARERR0(1U)
36661 
36662 #define S_GF3_DSGL_FIFO_PARERR    23
36663 #define V_GF3_DSGL_FIFO_PARERR(x) ((x) << S_GF3_DSGL_FIFO_PARERR)
36664 #define F_GF3_DSGL_FIFO_PARERR    V_GF3_DSGL_FIFO_PARERR(1U)
36665 
36666 #define S_GF2_DSGL_FIFO_PARERR    22
36667 #define V_GF2_DSGL_FIFO_PARERR(x) ((x) << S_GF2_DSGL_FIFO_PARERR)
36668 #define F_GF2_DSGL_FIFO_PARERR    V_GF2_DSGL_FIFO_PARERR(1U)
36669 
36670 #define S_GF1_DSGL_FIFO_PARERR    21
36671 #define V_GF1_DSGL_FIFO_PARERR(x) ((x) << S_GF1_DSGL_FIFO_PARERR)
36672 #define F_GF1_DSGL_FIFO_PARERR    V_GF1_DSGL_FIFO_PARERR(1U)
36673 
36674 #define S_GF0_DSGL_FIFO_PARERR    20
36675 #define V_GF0_DSGL_FIFO_PARERR(x) ((x) << S_GF0_DSGL_FIFO_PARERR)
36676 #define F_GF0_DSGL_FIFO_PARERR    V_GF0_DSGL_FIFO_PARERR(1U)
36677 
36678 #define S_DEDUPE3_DSGL_FIFO_PARERR    19
36679 #define V_DEDUPE3_DSGL_FIFO_PARERR(x) ((x) << S_DEDUPE3_DSGL_FIFO_PARERR)
36680 #define F_DEDUPE3_DSGL_FIFO_PARERR    V_DEDUPE3_DSGL_FIFO_PARERR(1U)
36681 
36682 #define S_DEDUPE2_DSGL_FIFO_PARERR    18
36683 #define V_DEDUPE2_DSGL_FIFO_PARERR(x) ((x) << S_DEDUPE2_DSGL_FIFO_PARERR)
36684 #define F_DEDUPE2_DSGL_FIFO_PARERR    V_DEDUPE2_DSGL_FIFO_PARERR(1U)
36685 
36686 #define S_DEDUPE1_DSGL_FIFO_PARERR    17
36687 #define V_DEDUPE1_DSGL_FIFO_PARERR(x) ((x) << S_DEDUPE1_DSGL_FIFO_PARERR)
36688 #define F_DEDUPE1_DSGL_FIFO_PARERR    V_DEDUPE1_DSGL_FIFO_PARERR(1U)
36689 
36690 #define S_DEDUPE0_DSGL_FIFO_PARERR    16
36691 #define V_DEDUPE0_DSGL_FIFO_PARERR(x) ((x) << S_DEDUPE0_DSGL_FIFO_PARERR)
36692 #define F_DEDUPE0_DSGL_FIFO_PARERR    V_DEDUPE0_DSGL_FIFO_PARERR(1U)
36693 
36694 #define S_XP10_SGE_FIFO_PARERR    15
36695 #define V_XP10_SGE_FIFO_PARERR(x) ((x) << S_XP10_SGE_FIFO_PARERR)
36696 #define F_XP10_SGE_FIFO_PARERR    V_XP10_SGE_FIFO_PARERR(1U)
36697 
36698 #define S_DSGL_PAR_ERR    14
36699 #define V_DSGL_PAR_ERR(x) ((x) << S_DSGL_PAR_ERR)
36700 #define F_DSGL_PAR_ERR    V_DSGL_PAR_ERR(1U)
36701 
36702 #define S_CDDIP_INT    13
36703 #define V_CDDIP_INT(x) ((x) << S_CDDIP_INT)
36704 #define F_CDDIP_INT    V_CDDIP_INT(1U)
36705 
36706 #define S_CCEIP_INT    12
36707 #define V_CCEIP_INT(x) ((x) << S_CCEIP_INT)
36708 #define F_CCEIP_INT    V_CCEIP_INT(1U)
36709 
36710 #define S_TLS_SGE_FIFO_PARERR3    11
36711 #define V_TLS_SGE_FIFO_PARERR3(x) ((x) << S_TLS_SGE_FIFO_PARERR3)
36712 #define F_TLS_SGE_FIFO_PARERR3    V_TLS_SGE_FIFO_PARERR3(1U)
36713 
36714 #define S_TLS_SGE_FIFO_PARERR2    10
36715 #define V_TLS_SGE_FIFO_PARERR2(x) ((x) << S_TLS_SGE_FIFO_PARERR2)
36716 #define F_TLS_SGE_FIFO_PARERR2    V_TLS_SGE_FIFO_PARERR2(1U)
36717 
36718 #define S_TLS_SGE_FIFO_PARERR1    9
36719 #define V_TLS_SGE_FIFO_PARERR1(x) ((x) << S_TLS_SGE_FIFO_PARERR1)
36720 #define F_TLS_SGE_FIFO_PARERR1    V_TLS_SGE_FIFO_PARERR1(1U)
36721 
36722 #define S_TLS_SGE_FIFO_PARERR0    8
36723 #define V_TLS_SGE_FIFO_PARERR0(x) ((x) << S_TLS_SGE_FIFO_PARERR0)
36724 #define F_TLS_SGE_FIFO_PARERR0    V_TLS_SGE_FIFO_PARERR0(1U)
36725 
36726 #define S_ULP2SMARBT_RSP_PERR    6
36727 #define V_ULP2SMARBT_RSP_PERR(x) ((x) << S_ULP2SMARBT_RSP_PERR)
36728 #define F_ULP2SMARBT_RSP_PERR    V_ULP2SMARBT_RSP_PERR(1U)
36729 
36730 #define S_ULPTX2MA_RSP_PERR    5
36731 #define V_ULPTX2MA_RSP_PERR(x) ((x) << S_ULPTX2MA_RSP_PERR)
36732 #define F_ULPTX2MA_RSP_PERR    V_ULPTX2MA_RSP_PERR(1U)
36733 
36734 #define S_PCIE2ULP_PERR3    4
36735 #define V_PCIE2ULP_PERR3(x) ((x) << S_PCIE2ULP_PERR3)
36736 #define F_PCIE2ULP_PERR3    V_PCIE2ULP_PERR3(1U)
36737 
36738 #define S_PCIE2ULP_PERR2    3
36739 #define V_PCIE2ULP_PERR2(x) ((x) << S_PCIE2ULP_PERR2)
36740 #define F_PCIE2ULP_PERR2    V_PCIE2ULP_PERR2(1U)
36741 
36742 #define S_PCIE2ULP_PERR1    2
36743 #define V_PCIE2ULP_PERR1(x) ((x) << S_PCIE2ULP_PERR1)
36744 #define F_PCIE2ULP_PERR1    V_PCIE2ULP_PERR1(1U)
36745 
36746 #define S_PCIE2ULP_PERR0    1
36747 #define V_PCIE2ULP_PERR0(x) ((x) << S_PCIE2ULP_PERR0)
36748 #define F_PCIE2ULP_PERR0    V_PCIE2ULP_PERR0(1U)
36749 
36750 #define S_CIM2ULP_PERR    0
36751 #define V_CIM2ULP_PERR(x) ((x) << S_CIM2ULP_PERR)
36752 #define F_CIM2ULP_PERR    V_CIM2ULP_PERR(1U)
36753 
36754 #define A_ULP_TX_INT_CAUSE_3 0x8e8c
36755 #define A_ULP_TX_PERR_ENABLE_3 0x8e90
36756 #define A_ULP_TX_INT_ENABLE_4 0x8e94
36757 
36758 #define S_DMA_PAR_ERR3    28
36759 #define M_DMA_PAR_ERR3    0xfU
36760 #define V_DMA_PAR_ERR3(x) ((x) << S_DMA_PAR_ERR3)
36761 #define G_DMA_PAR_ERR3(x) (((x) >> S_DMA_PAR_ERR3) & M_DMA_PAR_ERR3)
36762 
36763 #define S_DMA_PAR_ERR2    24
36764 #define M_DMA_PAR_ERR2    0xfU
36765 #define V_DMA_PAR_ERR2(x) ((x) << S_DMA_PAR_ERR2)
36766 #define G_DMA_PAR_ERR2(x) (((x) >> S_DMA_PAR_ERR2) & M_DMA_PAR_ERR2)
36767 
36768 #define S_DMA_PAR_ERR1    20
36769 #define M_DMA_PAR_ERR1    0xfU
36770 #define V_DMA_PAR_ERR1(x) ((x) << S_DMA_PAR_ERR1)
36771 #define G_DMA_PAR_ERR1(x) (((x) >> S_DMA_PAR_ERR1) & M_DMA_PAR_ERR1)
36772 
36773 #define S_DMA_PAR_ERR0    16
36774 #define M_DMA_PAR_ERR0    0xfU
36775 #define V_DMA_PAR_ERR0(x) ((x) << S_DMA_PAR_ERR0)
36776 #define G_DMA_PAR_ERR0(x) (((x) >> S_DMA_PAR_ERR0) & M_DMA_PAR_ERR0)
36777 
36778 #define S_CORE_CMD_FIFO_LB1    12
36779 #define M_CORE_CMD_FIFO_LB1    0xfU
36780 #define V_CORE_CMD_FIFO_LB1(x) ((x) << S_CORE_CMD_FIFO_LB1)
36781 #define G_CORE_CMD_FIFO_LB1(x) (((x) >> S_CORE_CMD_FIFO_LB1) & M_CORE_CMD_FIFO_LB1)
36782 
36783 #define S_CORE_CMD_FIFO_LB0    8
36784 #define M_CORE_CMD_FIFO_LB0    0xfU
36785 #define V_CORE_CMD_FIFO_LB0(x) ((x) << S_CORE_CMD_FIFO_LB0)
36786 #define G_CORE_CMD_FIFO_LB0(x) (((x) >> S_CORE_CMD_FIFO_LB0) & M_CORE_CMD_FIFO_LB0)
36787 
36788 #define S_XP10_2_ULP_PERR    7
36789 #define V_XP10_2_ULP_PERR(x) ((x) << S_XP10_2_ULP_PERR)
36790 #define F_XP10_2_ULP_PERR    V_XP10_2_ULP_PERR(1U)
36791 
36792 #define S_ULP_2_XP10_PERR    6
36793 #define V_ULP_2_XP10_PERR(x) ((x) << S_ULP_2_XP10_PERR)
36794 #define F_ULP_2_XP10_PERR    V_ULP_2_XP10_PERR(1U)
36795 
36796 #define S_CMD_FIFO_LB1    5
36797 #define V_CMD_FIFO_LB1(x) ((x) << S_CMD_FIFO_LB1)
36798 #define F_CMD_FIFO_LB1    V_CMD_FIFO_LB1(1U)
36799 
36800 #define S_CMD_FIFO_LB0    4
36801 #define V_CMD_FIFO_LB0(x) ((x) << S_CMD_FIFO_LB0)
36802 #define F_CMD_FIFO_LB0    V_CMD_FIFO_LB0(1U)
36803 
36804 #define S_TF_TP_PERR    3
36805 #define V_TF_TP_PERR(x) ((x) << S_TF_TP_PERR)
36806 #define F_TF_TP_PERR    V_TF_TP_PERR(1U)
36807 
36808 #define S_TF_SGE_PERR    2
36809 #define V_TF_SGE_PERR(x) ((x) << S_TF_SGE_PERR)
36810 #define F_TF_SGE_PERR    V_TF_SGE_PERR(1U)
36811 
36812 #define S_TF_MEM_PERR    1
36813 #define V_TF_MEM_PERR(x) ((x) << S_TF_MEM_PERR)
36814 #define F_TF_MEM_PERR    V_TF_MEM_PERR(1U)
36815 
36816 #define S_TF_MP_PERR    0
36817 #define V_TF_MP_PERR(x) ((x) << S_TF_MP_PERR)
36818 #define F_TF_MP_PERR    V_TF_MP_PERR(1U)
36819 
36820 #define A_ULP_TX_INT_CAUSE_4 0x8e98
36821 #define A_ULP_TX_PERR_ENABLE_4 0x8e9c
36822 #define A_ULP_TX_SE_CNT_ERR 0x8ea0
36823 
36824 #define S_ERR_CH3    12
36825 #define M_ERR_CH3    0xfU
36826 #define V_ERR_CH3(x) ((x) << S_ERR_CH3)
36827 #define G_ERR_CH3(x) (((x) >> S_ERR_CH3) & M_ERR_CH3)
36828 
36829 #define S_ERR_CH2    8
36830 #define M_ERR_CH2    0xfU
36831 #define V_ERR_CH2(x) ((x) << S_ERR_CH2)
36832 #define G_ERR_CH2(x) (((x) >> S_ERR_CH2) & M_ERR_CH2)
36833 
36834 #define S_ERR_CH1    4
36835 #define M_ERR_CH1    0xfU
36836 #define V_ERR_CH1(x) ((x) << S_ERR_CH1)
36837 #define G_ERR_CH1(x) (((x) >> S_ERR_CH1) & M_ERR_CH1)
36838 
36839 #define S_ERR_CH0    0
36840 #define M_ERR_CH0    0xfU
36841 #define V_ERR_CH0(x) ((x) << S_ERR_CH0)
36842 #define G_ERR_CH0(x) (((x) >> S_ERR_CH0) & M_ERR_CH0)
36843 
36844 #define A_ULP_TX_T5_SE_CNT_ERR 0x8ea0
36845 #define A_ULP_TX_SE_CNT_CLR 0x8ea4
36846 
36847 #define S_CLR_DROP    16
36848 #define M_CLR_DROP    0xfU
36849 #define V_CLR_DROP(x) ((x) << S_CLR_DROP)
36850 #define G_CLR_DROP(x) (((x) >> S_CLR_DROP) & M_CLR_DROP)
36851 
36852 #define S_CLR_CH3    12
36853 #define M_CLR_CH3    0xfU
36854 #define V_CLR_CH3(x) ((x) << S_CLR_CH3)
36855 #define G_CLR_CH3(x) (((x) >> S_CLR_CH3) & M_CLR_CH3)
36856 
36857 #define S_CLR_CH2    8
36858 #define M_CLR_CH2    0xfU
36859 #define V_CLR_CH2(x) ((x) << S_CLR_CH2)
36860 #define G_CLR_CH2(x) (((x) >> S_CLR_CH2) & M_CLR_CH2)
36861 
36862 #define S_CLR_CH1    4
36863 #define M_CLR_CH1    0xfU
36864 #define V_CLR_CH1(x) ((x) << S_CLR_CH1)
36865 #define G_CLR_CH1(x) (((x) >> S_CLR_CH1) & M_CLR_CH1)
36866 
36867 #define S_CLR_CH0    0
36868 #define M_CLR_CH0    0xfU
36869 #define V_CLR_CH0(x) ((x) << S_CLR_CH0)
36870 #define G_CLR_CH0(x) (((x) >> S_CLR_CH0) & M_CLR_CH0)
36871 
36872 #define A_ULP_TX_T5_SE_CNT_CLR 0x8ea4
36873 #define A_ULP_TX_SE_CNT_CH0 0x8ea8
36874 
36875 #define S_SOP_CNT_ULP2TP    28
36876 #define M_SOP_CNT_ULP2TP    0xfU
36877 #define V_SOP_CNT_ULP2TP(x) ((x) << S_SOP_CNT_ULP2TP)
36878 #define G_SOP_CNT_ULP2TP(x) (((x) >> S_SOP_CNT_ULP2TP) & M_SOP_CNT_ULP2TP)
36879 
36880 #define S_EOP_CNT_ULP2TP    24
36881 #define M_EOP_CNT_ULP2TP    0xfU
36882 #define V_EOP_CNT_ULP2TP(x) ((x) << S_EOP_CNT_ULP2TP)
36883 #define G_EOP_CNT_ULP2TP(x) (((x) >> S_EOP_CNT_ULP2TP) & M_EOP_CNT_ULP2TP)
36884 
36885 #define S_SOP_CNT_LSO_IN    20
36886 #define M_SOP_CNT_LSO_IN    0xfU
36887 #define V_SOP_CNT_LSO_IN(x) ((x) << S_SOP_CNT_LSO_IN)
36888 #define G_SOP_CNT_LSO_IN(x) (((x) >> S_SOP_CNT_LSO_IN) & M_SOP_CNT_LSO_IN)
36889 
36890 #define S_EOP_CNT_LSO_IN    16
36891 #define M_EOP_CNT_LSO_IN    0xfU
36892 #define V_EOP_CNT_LSO_IN(x) ((x) << S_EOP_CNT_LSO_IN)
36893 #define G_EOP_CNT_LSO_IN(x) (((x) >> S_EOP_CNT_LSO_IN) & M_EOP_CNT_LSO_IN)
36894 
36895 #define S_SOP_CNT_ALG_IN    12
36896 #define M_SOP_CNT_ALG_IN    0xfU
36897 #define V_SOP_CNT_ALG_IN(x) ((x) << S_SOP_CNT_ALG_IN)
36898 #define G_SOP_CNT_ALG_IN(x) (((x) >> S_SOP_CNT_ALG_IN) & M_SOP_CNT_ALG_IN)
36899 
36900 #define S_EOP_CNT_ALG_IN    8
36901 #define M_EOP_CNT_ALG_IN    0xfU
36902 #define V_EOP_CNT_ALG_IN(x) ((x) << S_EOP_CNT_ALG_IN)
36903 #define G_EOP_CNT_ALG_IN(x) (((x) >> S_EOP_CNT_ALG_IN) & M_EOP_CNT_ALG_IN)
36904 
36905 #define S_SOP_CNT_CIM2ULP    4
36906 #define M_SOP_CNT_CIM2ULP    0xfU
36907 #define V_SOP_CNT_CIM2ULP(x) ((x) << S_SOP_CNT_CIM2ULP)
36908 #define G_SOP_CNT_CIM2ULP(x) (((x) >> S_SOP_CNT_CIM2ULP) & M_SOP_CNT_CIM2ULP)
36909 
36910 #define S_EOP_CNT_CIM2ULP    0
36911 #define M_EOP_CNT_CIM2ULP    0xfU
36912 #define V_EOP_CNT_CIM2ULP(x) ((x) << S_EOP_CNT_CIM2ULP)
36913 #define G_EOP_CNT_CIM2ULP(x) (((x) >> S_EOP_CNT_CIM2ULP) & M_EOP_CNT_CIM2ULP)
36914 
36915 #define A_ULP_TX_T5_SE_CNT_CH0 0x8ea8
36916 #define A_ULP_TX_SE_CNT_CH1 0x8eac
36917 #define A_ULP_TX_T5_SE_CNT_CH1 0x8eac
36918 #define A_ULP_TX_SE_CNT_CH2 0x8eb0
36919 #define A_ULP_TX_T5_SE_CNT_CH2 0x8eb0
36920 #define A_ULP_TX_SE_CNT_CH3 0x8eb4
36921 #define A_ULP_TX_T5_SE_CNT_CH3 0x8eb4
36922 #define A_ULP_TX_DROP_CNT 0x8eb8
36923 
36924 #define S_DROP_CH3    12
36925 #define M_DROP_CH3    0xfU
36926 #define V_DROP_CH3(x) ((x) << S_DROP_CH3)
36927 #define G_DROP_CH3(x) (((x) >> S_DROP_CH3) & M_DROP_CH3)
36928 
36929 #define S_DROP_CH2    8
36930 #define M_DROP_CH2    0xfU
36931 #define V_DROP_CH2(x) ((x) << S_DROP_CH2)
36932 #define G_DROP_CH2(x) (((x) >> S_DROP_CH2) & M_DROP_CH2)
36933 
36934 #define S_DROP_CH1    4
36935 #define M_DROP_CH1    0xfU
36936 #define V_DROP_CH1(x) ((x) << S_DROP_CH1)
36937 #define G_DROP_CH1(x) (((x) >> S_DROP_CH1) & M_DROP_CH1)
36938 
36939 #define S_DROP_CH0    0
36940 #define M_DROP_CH0    0xfU
36941 #define V_DROP_CH0(x) ((x) << S_DROP_CH0)
36942 #define G_DROP_CH0(x) (((x) >> S_DROP_CH0) & M_DROP_CH0)
36943 
36944 #define A_ULP_TX_T5_DROP_CNT 0x8eb8
36945 
36946 #define S_DROP_INVLD_MC_CH3    28
36947 #define M_DROP_INVLD_MC_CH3    0xfU
36948 #define V_DROP_INVLD_MC_CH3(x) ((x) << S_DROP_INVLD_MC_CH3)
36949 #define G_DROP_INVLD_MC_CH3(x) (((x) >> S_DROP_INVLD_MC_CH3) & M_DROP_INVLD_MC_CH3)
36950 
36951 #define S_DROP_INVLD_MC_CH2    24
36952 #define M_DROP_INVLD_MC_CH2    0xfU
36953 #define V_DROP_INVLD_MC_CH2(x) ((x) << S_DROP_INVLD_MC_CH2)
36954 #define G_DROP_INVLD_MC_CH2(x) (((x) >> S_DROP_INVLD_MC_CH2) & M_DROP_INVLD_MC_CH2)
36955 
36956 #define S_DROP_INVLD_MC_CH1    20
36957 #define M_DROP_INVLD_MC_CH1    0xfU
36958 #define V_DROP_INVLD_MC_CH1(x) ((x) << S_DROP_INVLD_MC_CH1)
36959 #define G_DROP_INVLD_MC_CH1(x) (((x) >> S_DROP_INVLD_MC_CH1) & M_DROP_INVLD_MC_CH1)
36960 
36961 #define S_DROP_INVLD_MC_CH0    16
36962 #define M_DROP_INVLD_MC_CH0    0xfU
36963 #define V_DROP_INVLD_MC_CH0(x) ((x) << S_DROP_INVLD_MC_CH0)
36964 #define G_DROP_INVLD_MC_CH0(x) (((x) >> S_DROP_INVLD_MC_CH0) & M_DROP_INVLD_MC_CH0)
36965 
36966 #define A_ULP_TX_CSU_REVISION 0x8ebc
36967 #define A_ULP_TX_LA_RDPTR_0 0x8ec0
36968 #define A_ULP_TX_PL2APB_INFO 0x8ec0
36969 
36970 #define S_PL2APB_BRIDGE_HUNG    27
36971 #define V_PL2APB_BRIDGE_HUNG(x) ((x) << S_PL2APB_BRIDGE_HUNG)
36972 #define F_PL2APB_BRIDGE_HUNG    V_PL2APB_BRIDGE_HUNG(1U)
36973 
36974 #define S_PL2APB_BRIDGE_STATE    26
36975 #define V_PL2APB_BRIDGE_STATE(x) ((x) << S_PL2APB_BRIDGE_STATE)
36976 #define F_PL2APB_BRIDGE_STATE    V_PL2APB_BRIDGE_STATE(1U)
36977 
36978 #define S_PL2APB_BRIDGE_HUNG_TYPE    25
36979 #define V_PL2APB_BRIDGE_HUNG_TYPE(x) ((x) << S_PL2APB_BRIDGE_HUNG_TYPE)
36980 #define F_PL2APB_BRIDGE_HUNG_TYPE    V_PL2APB_BRIDGE_HUNG_TYPE(1U)
36981 
36982 #define S_PL2APB_BRIDGE_HUNG_ID    24
36983 #define V_PL2APB_BRIDGE_HUNG_ID(x) ((x) << S_PL2APB_BRIDGE_HUNG_ID)
36984 #define F_PL2APB_BRIDGE_HUNG_ID    V_PL2APB_BRIDGE_HUNG_ID(1U)
36985 
36986 #define S_PL2APB_BRIDGE_HUNG_ADDR    0
36987 #define M_PL2APB_BRIDGE_HUNG_ADDR    0xfffffU
36988 #define V_PL2APB_BRIDGE_HUNG_ADDR(x) ((x) << S_PL2APB_BRIDGE_HUNG_ADDR)
36989 #define G_PL2APB_BRIDGE_HUNG_ADDR(x) (((x) >> S_PL2APB_BRIDGE_HUNG_ADDR) & M_PL2APB_BRIDGE_HUNG_ADDR)
36990 
36991 #define A_ULP_TX_LA_RDDATA_0 0x8ec4
36992 #define A_ULP_TX_INT_ENABLE_5 0x8ec4
36993 
36994 #define S_DEDUPE_PERR3    23
36995 #define V_DEDUPE_PERR3(x) ((x) << S_DEDUPE_PERR3)
36996 #define F_DEDUPE_PERR3    V_DEDUPE_PERR3(1U)
36997 
36998 #define S_DEDUPE_PERR2    22
36999 #define V_DEDUPE_PERR2(x) ((x) << S_DEDUPE_PERR2)
37000 #define F_DEDUPE_PERR2    V_DEDUPE_PERR2(1U)
37001 
37002 #define S_DEDUPE_PERR1    21
37003 #define V_DEDUPE_PERR1(x) ((x) << S_DEDUPE_PERR1)
37004 #define F_DEDUPE_PERR1    V_DEDUPE_PERR1(1U)
37005 
37006 #define S_DEDUPE_PERR0    20
37007 #define V_DEDUPE_PERR0(x) ((x) << S_DEDUPE_PERR0)
37008 #define F_DEDUPE_PERR0    V_DEDUPE_PERR0(1U)
37009 
37010 #define S_GF_PERR3    19
37011 #define V_GF_PERR3(x) ((x) << S_GF_PERR3)
37012 #define F_GF_PERR3    V_GF_PERR3(1U)
37013 
37014 #define S_GF_PERR2    18
37015 #define V_GF_PERR2(x) ((x) << S_GF_PERR2)
37016 #define F_GF_PERR2    V_GF_PERR2(1U)
37017 
37018 #define S_GF_PERR1    17
37019 #define V_GF_PERR1(x) ((x) << S_GF_PERR1)
37020 #define F_GF_PERR1    V_GF_PERR1(1U)
37021 
37022 #define S_GF_PERR0    16
37023 #define V_GF_PERR0(x) ((x) << S_GF_PERR0)
37024 #define F_GF_PERR0    V_GF_PERR0(1U)
37025 
37026 #define S_SGE2ULP_INV_PERR    13
37027 #define V_SGE2ULP_INV_PERR(x) ((x) << S_SGE2ULP_INV_PERR)
37028 #define F_SGE2ULP_INV_PERR    V_SGE2ULP_INV_PERR(1U)
37029 
37030 #define S_T7_PL_BUSPERR    12
37031 #define V_T7_PL_BUSPERR(x) ((x) << S_T7_PL_BUSPERR)
37032 #define F_T7_PL_BUSPERR    V_T7_PL_BUSPERR(1U)
37033 
37034 #define S_TLSTX2ULPTX_PERR3    11
37035 #define V_TLSTX2ULPTX_PERR3(x) ((x) << S_TLSTX2ULPTX_PERR3)
37036 #define F_TLSTX2ULPTX_PERR3    V_TLSTX2ULPTX_PERR3(1U)
37037 
37038 #define S_TLSTX2ULPTX_PERR2    10
37039 #define V_TLSTX2ULPTX_PERR2(x) ((x) << S_TLSTX2ULPTX_PERR2)
37040 #define F_TLSTX2ULPTX_PERR2    V_TLSTX2ULPTX_PERR2(1U)
37041 
37042 #define S_TLSTX2ULPTX_PERR1    9
37043 #define V_TLSTX2ULPTX_PERR1(x) ((x) << S_TLSTX2ULPTX_PERR1)
37044 #define F_TLSTX2ULPTX_PERR1    V_TLSTX2ULPTX_PERR1(1U)
37045 
37046 #define S_TLSTX2ULPTX_PERR0    8
37047 #define V_TLSTX2ULPTX_PERR0(x) ((x) << S_TLSTX2ULPTX_PERR0)
37048 #define F_TLSTX2ULPTX_PERR0    V_TLSTX2ULPTX_PERR0(1U)
37049 
37050 #define S_XP10_2_ULP_PL_PERR    1
37051 #define V_XP10_2_ULP_PL_PERR(x) ((x) << S_XP10_2_ULP_PL_PERR)
37052 #define F_XP10_2_ULP_PL_PERR    V_XP10_2_ULP_PL_PERR(1U)
37053 
37054 #define S_ULP_2_XP10_PL_PERR    0
37055 #define V_ULP_2_XP10_PL_PERR(x) ((x) << S_ULP_2_XP10_PL_PERR)
37056 #define F_ULP_2_XP10_PL_PERR    V_ULP_2_XP10_PL_PERR(1U)
37057 
37058 #define A_ULP_TX_LA_WRPTR_0 0x8ec8
37059 #define A_ULP_TX_INT_CAUSE_5 0x8ec8
37060 #define A_ULP_TX_LA_RESERVED_0 0x8ecc
37061 #define A_ULP_TX_PERR_ENABLE_5 0x8ecc
37062 #define A_ULP_TX_LA_RDPTR_1 0x8ed0
37063 #define A_ULP_TX_INT_CAUSE_6 0x8ed0
37064 
37065 #define S_DDR_HDR_FIFO_PERR_SET3    12
37066 #define V_DDR_HDR_FIFO_PERR_SET3(x) ((x) << S_DDR_HDR_FIFO_PERR_SET3)
37067 #define F_DDR_HDR_FIFO_PERR_SET3    V_DDR_HDR_FIFO_PERR_SET3(1U)
37068 
37069 #define S_DDR_HDR_FIFO_PERR_SET2    11
37070 #define V_DDR_HDR_FIFO_PERR_SET2(x) ((x) << S_DDR_HDR_FIFO_PERR_SET2)
37071 #define F_DDR_HDR_FIFO_PERR_SET2    V_DDR_HDR_FIFO_PERR_SET2(1U)
37072 
37073 #define S_DDR_HDR_FIFO_PERR_SET1    10
37074 #define V_DDR_HDR_FIFO_PERR_SET1(x) ((x) << S_DDR_HDR_FIFO_PERR_SET1)
37075 #define F_DDR_HDR_FIFO_PERR_SET1    V_DDR_HDR_FIFO_PERR_SET1(1U)
37076 
37077 #define S_DDR_HDR_FIFO_PERR_SET0    9
37078 #define V_DDR_HDR_FIFO_PERR_SET0(x) ((x) << S_DDR_HDR_FIFO_PERR_SET0)
37079 #define F_DDR_HDR_FIFO_PERR_SET0    V_DDR_HDR_FIFO_PERR_SET0(1U)
37080 
37081 #define S_PRE_MP_RSP_PERR_SET3    8
37082 #define V_PRE_MP_RSP_PERR_SET3(x) ((x) << S_PRE_MP_RSP_PERR_SET3)
37083 #define F_PRE_MP_RSP_PERR_SET3    V_PRE_MP_RSP_PERR_SET3(1U)
37084 
37085 #define S_PRE_MP_RSP_PERR_SET2    7
37086 #define V_PRE_MP_RSP_PERR_SET2(x) ((x) << S_PRE_MP_RSP_PERR_SET2)
37087 #define F_PRE_MP_RSP_PERR_SET2    V_PRE_MP_RSP_PERR_SET2(1U)
37088 
37089 #define S_PRE_MP_RSP_PERR_SET1    6
37090 #define V_PRE_MP_RSP_PERR_SET1(x) ((x) << S_PRE_MP_RSP_PERR_SET1)
37091 #define F_PRE_MP_RSP_PERR_SET1    V_PRE_MP_RSP_PERR_SET1(1U)
37092 
37093 #define S_PRE_MP_RSP_PERR_SET0    5
37094 #define V_PRE_MP_RSP_PERR_SET0(x) ((x) << S_PRE_MP_RSP_PERR_SET0)
37095 #define F_PRE_MP_RSP_PERR_SET0    V_PRE_MP_RSP_PERR_SET0(1U)
37096 
37097 #define S_PRE_CQE_FIFO_PERR_SET3    4
37098 #define V_PRE_CQE_FIFO_PERR_SET3(x) ((x) << S_PRE_CQE_FIFO_PERR_SET3)
37099 #define F_PRE_CQE_FIFO_PERR_SET3    V_PRE_CQE_FIFO_PERR_SET3(1U)
37100 
37101 #define S_PRE_CQE_FIFO_PERR_SET2    3
37102 #define V_PRE_CQE_FIFO_PERR_SET2(x) ((x) << S_PRE_CQE_FIFO_PERR_SET2)
37103 #define F_PRE_CQE_FIFO_PERR_SET2    V_PRE_CQE_FIFO_PERR_SET2(1U)
37104 
37105 #define S_PRE_CQE_FIFO_PERR_SET1    2
37106 #define V_PRE_CQE_FIFO_PERR_SET1(x) ((x) << S_PRE_CQE_FIFO_PERR_SET1)
37107 #define F_PRE_CQE_FIFO_PERR_SET1    V_PRE_CQE_FIFO_PERR_SET1(1U)
37108 
37109 #define S_PRE_CQE_FIFO_PERR_SET0    1
37110 #define V_PRE_CQE_FIFO_PERR_SET0(x) ((x) << S_PRE_CQE_FIFO_PERR_SET0)
37111 #define F_PRE_CQE_FIFO_PERR_SET0    V_PRE_CQE_FIFO_PERR_SET0(1U)
37112 
37113 #define S_RSP_FIFO_PERR_SET    0
37114 #define V_RSP_FIFO_PERR_SET(x) ((x) << S_RSP_FIFO_PERR_SET)
37115 #define F_RSP_FIFO_PERR_SET    V_RSP_FIFO_PERR_SET(1U)
37116 
37117 #define A_ULP_TX_LA_RDDATA_1 0x8ed4
37118 #define A_ULP_TX_INT_ENABLE_6 0x8ed4
37119 #define A_ULP_TX_LA_WRPTR_1 0x8ed8
37120 #define A_ULP_TX_PERR_ENABLE_6 0x8ed8
37121 #define A_ULP_TX_LA_RESERVED_1 0x8edc
37122 #define A_ULP_TX_INT_CAUSE_7 0x8edc
37123 
37124 #define S_TLS_SGE_FIFO_CORERR3    23
37125 #define V_TLS_SGE_FIFO_CORERR3(x) ((x) << S_TLS_SGE_FIFO_CORERR3)
37126 #define F_TLS_SGE_FIFO_CORERR3    V_TLS_SGE_FIFO_CORERR3(1U)
37127 
37128 #define S_TLS_SGE_FIFO_CORERR2    22
37129 #define V_TLS_SGE_FIFO_CORERR2(x) ((x) << S_TLS_SGE_FIFO_CORERR2)
37130 #define F_TLS_SGE_FIFO_CORERR2    V_TLS_SGE_FIFO_CORERR2(1U)
37131 
37132 #define S_TLS_SGE_FIFO_CORERR1    21
37133 #define V_TLS_SGE_FIFO_CORERR1(x) ((x) << S_TLS_SGE_FIFO_CORERR1)
37134 #define F_TLS_SGE_FIFO_CORERR1    V_TLS_SGE_FIFO_CORERR1(1U)
37135 
37136 #define S_TLS_SGE_FIFO_CORERR0    20
37137 #define V_TLS_SGE_FIFO_CORERR0(x) ((x) << S_TLS_SGE_FIFO_CORERR0)
37138 #define F_TLS_SGE_FIFO_CORERR0    V_TLS_SGE_FIFO_CORERR0(1U)
37139 
37140 #define S_LSO_HDR_SRAM_CERR_SET3    19
37141 #define V_LSO_HDR_SRAM_CERR_SET3(x) ((x) << S_LSO_HDR_SRAM_CERR_SET3)
37142 #define F_LSO_HDR_SRAM_CERR_SET3    V_LSO_HDR_SRAM_CERR_SET3(1U)
37143 
37144 #define S_LSO_HDR_SRAM_CERR_SET2    18
37145 #define V_LSO_HDR_SRAM_CERR_SET2(x) ((x) << S_LSO_HDR_SRAM_CERR_SET2)
37146 #define F_LSO_HDR_SRAM_CERR_SET2    V_LSO_HDR_SRAM_CERR_SET2(1U)
37147 
37148 #define S_LSO_HDR_SRAM_CERR_SET1    17
37149 #define V_LSO_HDR_SRAM_CERR_SET1(x) ((x) << S_LSO_HDR_SRAM_CERR_SET1)
37150 #define F_LSO_HDR_SRAM_CERR_SET1    V_LSO_HDR_SRAM_CERR_SET1(1U)
37151 
37152 #define S_LSO_HDR_SRAM_CERR_SET0    16
37153 #define V_LSO_HDR_SRAM_CERR_SET0(x) ((x) << S_LSO_HDR_SRAM_CERR_SET0)
37154 #define F_LSO_HDR_SRAM_CERR_SET0    V_LSO_HDR_SRAM_CERR_SET0(1U)
37155 
37156 #define S_CORE_CMD_FIFO_CERR_SET_CH3_LB1    15
37157 #define V_CORE_CMD_FIFO_CERR_SET_CH3_LB1(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH3_LB1)
37158 #define F_CORE_CMD_FIFO_CERR_SET_CH3_LB1    V_CORE_CMD_FIFO_CERR_SET_CH3_LB1(1U)
37159 
37160 #define S_CORE_CMD_FIFO_CERR_SET_CH2_LB1    14
37161 #define V_CORE_CMD_FIFO_CERR_SET_CH2_LB1(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH2_LB1)
37162 #define F_CORE_CMD_FIFO_CERR_SET_CH2_LB1    V_CORE_CMD_FIFO_CERR_SET_CH2_LB1(1U)
37163 
37164 #define S_CORE_CMD_FIFO_CERR_SET_CH1_LB1    13
37165 #define V_CORE_CMD_FIFO_CERR_SET_CH1_LB1(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH1_LB1)
37166 #define F_CORE_CMD_FIFO_CERR_SET_CH1_LB1    V_CORE_CMD_FIFO_CERR_SET_CH1_LB1(1U)
37167 
37168 #define S_CORE_CMD_FIFO_CERR_SET_CH0_LB1    12
37169 #define V_CORE_CMD_FIFO_CERR_SET_CH0_LB1(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH0_LB1)
37170 #define F_CORE_CMD_FIFO_CERR_SET_CH0_LB1    V_CORE_CMD_FIFO_CERR_SET_CH0_LB1(1U)
37171 
37172 #define S_CORE_CMD_FIFO_CERR_SET_CH3_LB0    11
37173 #define V_CORE_CMD_FIFO_CERR_SET_CH3_LB0(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH3_LB0)
37174 #define F_CORE_CMD_FIFO_CERR_SET_CH3_LB0    V_CORE_CMD_FIFO_CERR_SET_CH3_LB0(1U)
37175 
37176 #define S_CORE_CMD_FIFO_CERR_SET_CH2_LB0    10
37177 #define V_CORE_CMD_FIFO_CERR_SET_CH2_LB0(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH2_LB0)
37178 #define F_CORE_CMD_FIFO_CERR_SET_CH2_LB0    V_CORE_CMD_FIFO_CERR_SET_CH2_LB0(1U)
37179 
37180 #define S_CORE_CMD_FIFO_CERR_SET_CH1_LB0    9
37181 #define V_CORE_CMD_FIFO_CERR_SET_CH1_LB0(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH1_LB0)
37182 #define F_CORE_CMD_FIFO_CERR_SET_CH1_LB0    V_CORE_CMD_FIFO_CERR_SET_CH1_LB0(1U)
37183 
37184 #define S_CORE_CMD_FIFO_CERR_SET_CH0_LB0    8
37185 #define V_CORE_CMD_FIFO_CERR_SET_CH0_LB0(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH0_LB0)
37186 #define F_CORE_CMD_FIFO_CERR_SET_CH0_LB0    V_CORE_CMD_FIFO_CERR_SET_CH0_LB0(1U)
37187 
37188 #define S_CQE_FIFO_CERR_SET3    7
37189 #define V_CQE_FIFO_CERR_SET3(x) ((x) << S_CQE_FIFO_CERR_SET3)
37190 #define F_CQE_FIFO_CERR_SET3    V_CQE_FIFO_CERR_SET3(1U)
37191 
37192 #define S_CQE_FIFO_CERR_SET2    6
37193 #define V_CQE_FIFO_CERR_SET2(x) ((x) << S_CQE_FIFO_CERR_SET2)
37194 #define F_CQE_FIFO_CERR_SET2    V_CQE_FIFO_CERR_SET2(1U)
37195 
37196 #define S_CQE_FIFO_CERR_SET1    5
37197 #define V_CQE_FIFO_CERR_SET1(x) ((x) << S_CQE_FIFO_CERR_SET1)
37198 #define F_CQE_FIFO_CERR_SET1    V_CQE_FIFO_CERR_SET1(1U)
37199 
37200 #define S_CQE_FIFO_CERR_SET0    4
37201 #define V_CQE_FIFO_CERR_SET0(x) ((x) << S_CQE_FIFO_CERR_SET0)
37202 #define F_CQE_FIFO_CERR_SET0    V_CQE_FIFO_CERR_SET0(1U)
37203 
37204 #define S_PRE_CQE_FIFO_CERR_SET3    3
37205 #define V_PRE_CQE_FIFO_CERR_SET3(x) ((x) << S_PRE_CQE_FIFO_CERR_SET3)
37206 #define F_PRE_CQE_FIFO_CERR_SET3    V_PRE_CQE_FIFO_CERR_SET3(1U)
37207 
37208 #define S_PRE_CQE_FIFO_CERR_SET2    2
37209 #define V_PRE_CQE_FIFO_CERR_SET2(x) ((x) << S_PRE_CQE_FIFO_CERR_SET2)
37210 #define F_PRE_CQE_FIFO_CERR_SET2    V_PRE_CQE_FIFO_CERR_SET2(1U)
37211 
37212 #define S_PRE_CQE_FIFO_CERR_SET1    1
37213 #define V_PRE_CQE_FIFO_CERR_SET1(x) ((x) << S_PRE_CQE_FIFO_CERR_SET1)
37214 #define F_PRE_CQE_FIFO_CERR_SET1    V_PRE_CQE_FIFO_CERR_SET1(1U)
37215 
37216 #define S_PRE_CQE_FIFO_CERR_SET0    0
37217 #define V_PRE_CQE_FIFO_CERR_SET0(x) ((x) << S_PRE_CQE_FIFO_CERR_SET0)
37218 #define F_PRE_CQE_FIFO_CERR_SET0    V_PRE_CQE_FIFO_CERR_SET0(1U)
37219 
37220 #define A_ULP_TX_LA_RDPTR_2 0x8ee0
37221 #define A_ULP_TX_INT_ENABLE_7 0x8ee0
37222 #define A_ULP_TX_LA_RDDATA_2 0x8ee4
37223 #define A_ULP_TX_INT_CAUSE_8 0x8ee4
37224 
37225 #define S_MEM_RSP_FIFO_CERR_SET3    28
37226 #define V_MEM_RSP_FIFO_CERR_SET3(x) ((x) << S_MEM_RSP_FIFO_CERR_SET3)
37227 #define F_MEM_RSP_FIFO_CERR_SET3    V_MEM_RSP_FIFO_CERR_SET3(1U)
37228 
37229 #define S_MEM_RSP_FIFO_CERR_SET2    27
37230 #define V_MEM_RSP_FIFO_CERR_SET2(x) ((x) << S_MEM_RSP_FIFO_CERR_SET2)
37231 #define F_MEM_RSP_FIFO_CERR_SET2    V_MEM_RSP_FIFO_CERR_SET2(1U)
37232 
37233 #define S_MEM_RSP_FIFO_CERR_SET1    26
37234 #define V_MEM_RSP_FIFO_CERR_SET1(x) ((x) << S_MEM_RSP_FIFO_CERR_SET1)
37235 #define F_MEM_RSP_FIFO_CERR_SET1    V_MEM_RSP_FIFO_CERR_SET1(1U)
37236 
37237 #define S_MEM_RSP_FIFO_CERR_SET0    25
37238 #define V_MEM_RSP_FIFO_CERR_SET0(x) ((x) << S_MEM_RSP_FIFO_CERR_SET0)
37239 #define F_MEM_RSP_FIFO_CERR_SET0    V_MEM_RSP_FIFO_CERR_SET0(1U)
37240 
37241 #define S_PI_SRAM_CERR_SET3    24
37242 #define V_PI_SRAM_CERR_SET3(x) ((x) << S_PI_SRAM_CERR_SET3)
37243 #define F_PI_SRAM_CERR_SET3    V_PI_SRAM_CERR_SET3(1U)
37244 
37245 #define S_PI_SRAM_CERR_SET2    23
37246 #define V_PI_SRAM_CERR_SET2(x) ((x) << S_PI_SRAM_CERR_SET2)
37247 #define F_PI_SRAM_CERR_SET2    V_PI_SRAM_CERR_SET2(1U)
37248 
37249 #define S_PI_SRAM_CERR_SET1    22
37250 #define V_PI_SRAM_CERR_SET1(x) ((x) << S_PI_SRAM_CERR_SET1)
37251 #define F_PI_SRAM_CERR_SET1    V_PI_SRAM_CERR_SET1(1U)
37252 
37253 #define S_PI_SRAM_CERR_SET0    21
37254 #define V_PI_SRAM_CERR_SET0(x) ((x) << S_PI_SRAM_CERR_SET0)
37255 #define F_PI_SRAM_CERR_SET0    V_PI_SRAM_CERR_SET0(1U)
37256 
37257 #define S_PRE_MP_RSP_CERR_SET3    20
37258 #define V_PRE_MP_RSP_CERR_SET3(x) ((x) << S_PRE_MP_RSP_CERR_SET3)
37259 #define F_PRE_MP_RSP_CERR_SET3    V_PRE_MP_RSP_CERR_SET3(1U)
37260 
37261 #define S_PRE_MP_RSP_CERR_SET2    19
37262 #define V_PRE_MP_RSP_CERR_SET2(x) ((x) << S_PRE_MP_RSP_CERR_SET2)
37263 #define F_PRE_MP_RSP_CERR_SET2    V_PRE_MP_RSP_CERR_SET2(1U)
37264 
37265 #define S_PRE_MP_RSP_CERR_SET1    18
37266 #define V_PRE_MP_RSP_CERR_SET1(x) ((x) << S_PRE_MP_RSP_CERR_SET1)
37267 #define F_PRE_MP_RSP_CERR_SET1    V_PRE_MP_RSP_CERR_SET1(1U)
37268 
37269 #define S_PRE_MP_RSP_CERR_SET0    17
37270 #define V_PRE_MP_RSP_CERR_SET0(x) ((x) << S_PRE_MP_RSP_CERR_SET0)
37271 #define F_PRE_MP_RSP_CERR_SET0    V_PRE_MP_RSP_CERR_SET0(1U)
37272 
37273 #define S_DDR_HDR_FIFO_CERR_SET3    16
37274 #define V_DDR_HDR_FIFO_CERR_SET3(x) ((x) << S_DDR_HDR_FIFO_CERR_SET3)
37275 #define F_DDR_HDR_FIFO_CERR_SET3    V_DDR_HDR_FIFO_CERR_SET3(1U)
37276 
37277 #define S_DDR_HDR_FIFO_CERR_SET2    15
37278 #define V_DDR_HDR_FIFO_CERR_SET2(x) ((x) << S_DDR_HDR_FIFO_CERR_SET2)
37279 #define F_DDR_HDR_FIFO_CERR_SET2    V_DDR_HDR_FIFO_CERR_SET2(1U)
37280 
37281 #define S_DDR_HDR_FIFO_CERR_SET1    14
37282 #define V_DDR_HDR_FIFO_CERR_SET1(x) ((x) << S_DDR_HDR_FIFO_CERR_SET1)
37283 #define F_DDR_HDR_FIFO_CERR_SET1    V_DDR_HDR_FIFO_CERR_SET1(1U)
37284 
37285 #define S_DDR_HDR_FIFO_CERR_SET0    13
37286 #define V_DDR_HDR_FIFO_CERR_SET0(x) ((x) << S_DDR_HDR_FIFO_CERR_SET0)
37287 #define F_DDR_HDR_FIFO_CERR_SET0    V_DDR_HDR_FIFO_CERR_SET0(1U)
37288 
37289 #define S_CMD_FIFO_CERR_SET3    12
37290 #define V_CMD_FIFO_CERR_SET3(x) ((x) << S_CMD_FIFO_CERR_SET3)
37291 #define F_CMD_FIFO_CERR_SET3    V_CMD_FIFO_CERR_SET3(1U)
37292 
37293 #define S_CMD_FIFO_CERR_SET2    11
37294 #define V_CMD_FIFO_CERR_SET2(x) ((x) << S_CMD_FIFO_CERR_SET2)
37295 #define F_CMD_FIFO_CERR_SET2    V_CMD_FIFO_CERR_SET2(1U)
37296 
37297 #define S_CMD_FIFO_CERR_SET1    10
37298 #define V_CMD_FIFO_CERR_SET1(x) ((x) << S_CMD_FIFO_CERR_SET1)
37299 #define F_CMD_FIFO_CERR_SET1    V_CMD_FIFO_CERR_SET1(1U)
37300 
37301 #define S_CMD_FIFO_CERR_SET0    9
37302 #define V_CMD_FIFO_CERR_SET0(x) ((x) << S_CMD_FIFO_CERR_SET0)
37303 #define F_CMD_FIFO_CERR_SET0    V_CMD_FIFO_CERR_SET0(1U)
37304 
37305 #define S_GF_SGE_FIFO_CORERR3    8
37306 #define V_GF_SGE_FIFO_CORERR3(x) ((x) << S_GF_SGE_FIFO_CORERR3)
37307 #define F_GF_SGE_FIFO_CORERR3    V_GF_SGE_FIFO_CORERR3(1U)
37308 
37309 #define S_GF_SGE_FIFO_CORERR2    7
37310 #define V_GF_SGE_FIFO_CORERR2(x) ((x) << S_GF_SGE_FIFO_CORERR2)
37311 #define F_GF_SGE_FIFO_CORERR2    V_GF_SGE_FIFO_CORERR2(1U)
37312 
37313 #define S_GF_SGE_FIFO_CORERR1    6
37314 #define V_GF_SGE_FIFO_CORERR1(x) ((x) << S_GF_SGE_FIFO_CORERR1)
37315 #define F_GF_SGE_FIFO_CORERR1    V_GF_SGE_FIFO_CORERR1(1U)
37316 
37317 #define S_GF_SGE_FIFO_CORERR0    5
37318 #define V_GF_SGE_FIFO_CORERR0(x) ((x) << S_GF_SGE_FIFO_CORERR0)
37319 #define F_GF_SGE_FIFO_CORERR0    V_GF_SGE_FIFO_CORERR0(1U)
37320 
37321 #define S_DEDUPE_SGE_FIFO_CORERR3    4
37322 #define V_DEDUPE_SGE_FIFO_CORERR3(x) ((x) << S_DEDUPE_SGE_FIFO_CORERR3)
37323 #define F_DEDUPE_SGE_FIFO_CORERR3    V_DEDUPE_SGE_FIFO_CORERR3(1U)
37324 
37325 #define S_DEDUPE_SGE_FIFO_CORERR2    3
37326 #define V_DEDUPE_SGE_FIFO_CORERR2(x) ((x) << S_DEDUPE_SGE_FIFO_CORERR2)
37327 #define F_DEDUPE_SGE_FIFO_CORERR2    V_DEDUPE_SGE_FIFO_CORERR2(1U)
37328 
37329 #define S_DEDUPE_SGE_FIFO_CORERR1    2
37330 #define V_DEDUPE_SGE_FIFO_CORERR1(x) ((x) << S_DEDUPE_SGE_FIFO_CORERR1)
37331 #define F_DEDUPE_SGE_FIFO_CORERR1    V_DEDUPE_SGE_FIFO_CORERR1(1U)
37332 
37333 #define S_DEDUPE_SGE_FIFO_CORERR0    1
37334 #define V_DEDUPE_SGE_FIFO_CORERR0(x) ((x) << S_DEDUPE_SGE_FIFO_CORERR0)
37335 #define F_DEDUPE_SGE_FIFO_CORERR0    V_DEDUPE_SGE_FIFO_CORERR0(1U)
37336 
37337 #define S_RSP_FIFO_CERR_SET    0
37338 #define V_RSP_FIFO_CERR_SET(x) ((x) << S_RSP_FIFO_CERR_SET)
37339 #define F_RSP_FIFO_CERR_SET    V_RSP_FIFO_CERR_SET(1U)
37340 
37341 #define A_ULP_TX_LA_WRPTR_2 0x8ee8
37342 #define A_ULP_TX_INT_ENABLE_8 0x8ee8
37343 #define A_ULP_TX_LA_RESERVED_2 0x8eec
37344 #define A_ULP_TX_LA_RDPTR_3 0x8ef0
37345 #define A_ULP_TX_LA_RDDATA_3 0x8ef4
37346 #define A_ULP_TX_LA_WRPTR_3 0x8ef8
37347 #define A_ULP_TX_LA_RESERVED_3 0x8efc
37348 #define A_ULP_TX_LA_RDPTR_4 0x8f00
37349 #define A_ULP_TX_LA_RDDATA_4 0x8f04
37350 #define A_ULP_TX_LA_WRPTR_4 0x8f08
37351 #define A_ULP_TX_LA_RESERVED_4 0x8f0c
37352 #define A_ULP_TX_LA_RDPTR_5 0x8f10
37353 #define A_ULP_TX_LA_RDDATA_5 0x8f14
37354 #define A_ULP_TX_LA_WRPTR_5 0x8f18
37355 #define A_ULP_TX_LA_RESERVED_5 0x8f1c
37356 #define A_ULP_TX_LA_RDPTR_6 0x8f20
37357 #define A_ULP_TX_LA_RDDATA_6 0x8f24
37358 #define A_ULP_TX_LA_WRPTR_6 0x8f28
37359 #define A_ULP_TX_LA_RESERVED_6 0x8f2c
37360 #define A_ULP_TX_LA_RDPTR_7 0x8f30
37361 #define A_ULP_TX_LA_RDDATA_7 0x8f34
37362 #define A_ULP_TX_LA_WRPTR_7 0x8f38
37363 #define A_ULP_TX_LA_RESERVED_7 0x8f3c
37364 #define A_ULP_TX_LA_RDPTR_8 0x8f40
37365 #define A_ULP_TX_LA_RDDATA_8 0x8f44
37366 #define A_ULP_TX_LA_WRPTR_8 0x8f48
37367 #define A_ULP_TX_LA_RESERVED_8 0x8f4c
37368 #define A_ULP_TX_LA_RDPTR_9 0x8f50
37369 #define A_ULP_TX_LA_RDDATA_9 0x8f54
37370 #define A_ULP_TX_LA_WRPTR_9 0x8f58
37371 #define A_ULP_TX_LA_RESERVED_9 0x8f5c
37372 #define A_ULP_TX_LA_RDPTR_10 0x8f60
37373 #define A_ULP_TX_LA_RDDATA_10 0x8f64
37374 #define A_ULP_TX_LA_WRPTR_10 0x8f68
37375 #define A_ULP_TX_LA_RESERVED_10 0x8f6c
37376 #define A_ULP_TX_ASIC_DEBUG_CTRL 0x8f70
37377 
37378 #define S_LA_WR0    0
37379 #define V_LA_WR0(x) ((x) << S_LA_WR0)
37380 #define F_LA_WR0    V_LA_WR0(1U)
37381 
37382 #define A_ULP_TX_ASIC_DEBUG_0 0x8f74
37383 #define A_ULP_TX_ASIC_DEBUG_1 0x8f78
37384 #define A_ULP_TX_ASIC_DEBUG_2 0x8f7c
37385 #define A_ULP_TX_ASIC_DEBUG_3 0x8f80
37386 #define A_ULP_TX_ASIC_DEBUG_4 0x8f84
37387 #define A_ULP_TX_CPL_TX_DATA_FLAGS_MASK 0x8f88
37388 
37389 #define S_BYPASS_FIRST    26
37390 #define V_BYPASS_FIRST(x) ((x) << S_BYPASS_FIRST)
37391 #define F_BYPASS_FIRST    V_BYPASS_FIRST(1U)
37392 
37393 #define S_BYPASS_MIDDLE    25
37394 #define V_BYPASS_MIDDLE(x) ((x) << S_BYPASS_MIDDLE)
37395 #define F_BYPASS_MIDDLE    V_BYPASS_MIDDLE(1U)
37396 
37397 #define S_BYPASS_LAST    24
37398 #define V_BYPASS_LAST(x) ((x) << S_BYPASS_LAST)
37399 #define F_BYPASS_LAST    V_BYPASS_LAST(1U)
37400 
37401 #define S_PUSH_FIRST    22
37402 #define V_PUSH_FIRST(x) ((x) << S_PUSH_FIRST)
37403 #define F_PUSH_FIRST    V_PUSH_FIRST(1U)
37404 
37405 #define S_PUSH_MIDDLE    21
37406 #define V_PUSH_MIDDLE(x) ((x) << S_PUSH_MIDDLE)
37407 #define F_PUSH_MIDDLE    V_PUSH_MIDDLE(1U)
37408 
37409 #define S_PUSH_LAST    20
37410 #define V_PUSH_LAST(x) ((x) << S_PUSH_LAST)
37411 #define F_PUSH_LAST    V_PUSH_LAST(1U)
37412 
37413 #define S_SAVE_FIRST    18
37414 #define V_SAVE_FIRST(x) ((x) << S_SAVE_FIRST)
37415 #define F_SAVE_FIRST    V_SAVE_FIRST(1U)
37416 
37417 #define S_SAVE_MIDDLE    17
37418 #define V_SAVE_MIDDLE(x) ((x) << S_SAVE_MIDDLE)
37419 #define F_SAVE_MIDDLE    V_SAVE_MIDDLE(1U)
37420 
37421 #define S_SAVE_LAST    16
37422 #define V_SAVE_LAST(x) ((x) << S_SAVE_LAST)
37423 #define F_SAVE_LAST    V_SAVE_LAST(1U)
37424 
37425 #define S_FLUSH_FIRST    14
37426 #define V_FLUSH_FIRST(x) ((x) << S_FLUSH_FIRST)
37427 #define F_FLUSH_FIRST    V_FLUSH_FIRST(1U)
37428 
37429 #define S_FLUSH_MIDDLE    13
37430 #define V_FLUSH_MIDDLE(x) ((x) << S_FLUSH_MIDDLE)
37431 #define F_FLUSH_MIDDLE    V_FLUSH_MIDDLE(1U)
37432 
37433 #define S_FLUSH_LAST    12
37434 #define V_FLUSH_LAST(x) ((x) << S_FLUSH_LAST)
37435 #define F_FLUSH_LAST    V_FLUSH_LAST(1U)
37436 
37437 #define S_URGENT_FIRST    10
37438 #define V_URGENT_FIRST(x) ((x) << S_URGENT_FIRST)
37439 #define F_URGENT_FIRST    V_URGENT_FIRST(1U)
37440 
37441 #define S_URGENT_MIDDLE    9
37442 #define V_URGENT_MIDDLE(x) ((x) << S_URGENT_MIDDLE)
37443 #define F_URGENT_MIDDLE    V_URGENT_MIDDLE(1U)
37444 
37445 #define S_URGENT_LAST    8
37446 #define V_URGENT_LAST(x) ((x) << S_URGENT_LAST)
37447 #define F_URGENT_LAST    V_URGENT_LAST(1U)
37448 
37449 #define S_MORE_FIRST    6
37450 #define V_MORE_FIRST(x) ((x) << S_MORE_FIRST)
37451 #define F_MORE_FIRST    V_MORE_FIRST(1U)
37452 
37453 #define S_MORE_MIDDLE    5
37454 #define V_MORE_MIDDLE(x) ((x) << S_MORE_MIDDLE)
37455 #define F_MORE_MIDDLE    V_MORE_MIDDLE(1U)
37456 
37457 #define S_MORE_LAST    4
37458 #define V_MORE_LAST(x) ((x) << S_MORE_LAST)
37459 #define F_MORE_LAST    V_MORE_LAST(1U)
37460 
37461 #define S_SHOVE_FIRST    2
37462 #define V_SHOVE_FIRST(x) ((x) << S_SHOVE_FIRST)
37463 #define F_SHOVE_FIRST    V_SHOVE_FIRST(1U)
37464 
37465 #define S_SHOVE_MIDDLE    1
37466 #define V_SHOVE_MIDDLE(x) ((x) << S_SHOVE_MIDDLE)
37467 #define F_SHOVE_MIDDLE    V_SHOVE_MIDDLE(1U)
37468 
37469 #define S_SHOVE_LAST    0
37470 #define V_SHOVE_LAST(x) ((x) << S_SHOVE_LAST)
37471 #define F_SHOVE_LAST    V_SHOVE_LAST(1U)
37472 
37473 #define A_ULP_TX_ACCELERATOR_CTL 0x8f90
37474 
37475 #define S_FIFO_THRESHOLD    8
37476 #define M_FIFO_THRESHOLD    0x1fU
37477 #define V_FIFO_THRESHOLD(x) ((x) << S_FIFO_THRESHOLD)
37478 #define G_FIFO_THRESHOLD(x) (((x) >> S_FIFO_THRESHOLD) & M_FIFO_THRESHOLD)
37479 
37480 #define S_COMPRESSION_XP10DISABLECFUSE    5
37481 #define V_COMPRESSION_XP10DISABLECFUSE(x) ((x) << S_COMPRESSION_XP10DISABLECFUSE)
37482 #define F_COMPRESSION_XP10DISABLECFUSE    V_COMPRESSION_XP10DISABLECFUSE(1U)
37483 
37484 #define S_COMPRESSION_XP10DISABLE    4
37485 #define V_COMPRESSION_XP10DISABLE(x) ((x) << S_COMPRESSION_XP10DISABLE)
37486 #define F_COMPRESSION_XP10DISABLE    V_COMPRESSION_XP10DISABLE(1U)
37487 
37488 #define S_DEDUPEDISABLECFUSE    3
37489 #define V_DEDUPEDISABLECFUSE(x) ((x) << S_DEDUPEDISABLECFUSE)
37490 #define F_DEDUPEDISABLECFUSE    V_DEDUPEDISABLECFUSE(1U)
37491 
37492 #define S_DEDUPEDISABLE    2
37493 #define V_DEDUPEDISABLE(x) ((x) << S_DEDUPEDISABLE)
37494 #define F_DEDUPEDISABLE    V_DEDUPEDISABLE(1U)
37495 
37496 #define S_GFDISABLECFUSE    1
37497 #define V_GFDISABLECFUSE(x) ((x) << S_GFDISABLECFUSE)
37498 #define F_GFDISABLECFUSE    V_GFDISABLECFUSE(1U)
37499 
37500 #define S_GFDISABLE    0
37501 #define V_GFDISABLE(x) ((x) << S_GFDISABLE)
37502 #define F_GFDISABLE    V_GFDISABLE(1U)
37503 
37504 #define A_ULP_TX_XP10_IND_ADDR 0x8f94
37505 
37506 #define S_XP10_CONTROL    31
37507 #define V_XP10_CONTROL(x) ((x) << S_XP10_CONTROL)
37508 #define F_XP10_CONTROL    V_XP10_CONTROL(1U)
37509 
37510 #define S_XP10_ADDR    0
37511 #define M_XP10_ADDR    0xfffffU
37512 #define V_XP10_ADDR(x) ((x) << S_XP10_ADDR)
37513 #define G_XP10_ADDR(x) (((x) >> S_XP10_ADDR) & M_XP10_ADDR)
37514 
37515 #define A_ULP_TX_XP10_IND_DATA 0x8f98
37516 #define A_ULP_TX_IWARP_PMOF_OPCODES_1 0x8f9c
37517 
37518 #define S_RDMA_VERIFY_RESPONSE    24
37519 #define M_RDMA_VERIFY_RESPONSE    0x1fU
37520 #define V_RDMA_VERIFY_RESPONSE(x) ((x) << S_RDMA_VERIFY_RESPONSE)
37521 #define G_RDMA_VERIFY_RESPONSE(x) (((x) >> S_RDMA_VERIFY_RESPONSE) & M_RDMA_VERIFY_RESPONSE)
37522 
37523 #define S_RDMA_VERIFY_REQUEST    16
37524 #define M_RDMA_VERIFY_REQUEST    0x1fU
37525 #define V_RDMA_VERIFY_REQUEST(x) ((x) << S_RDMA_VERIFY_REQUEST)
37526 #define G_RDMA_VERIFY_REQUEST(x) (((x) >> S_RDMA_VERIFY_REQUEST) & M_RDMA_VERIFY_REQUEST)
37527 
37528 #define S_RDMA_FLUSH_RESPONSE    8
37529 #define M_RDMA_FLUSH_RESPONSE    0x1fU
37530 #define V_RDMA_FLUSH_RESPONSE(x) ((x) << S_RDMA_FLUSH_RESPONSE)
37531 #define G_RDMA_FLUSH_RESPONSE(x) (((x) >> S_RDMA_FLUSH_RESPONSE) & M_RDMA_FLUSH_RESPONSE)
37532 
37533 #define S_RDMA_FLUSH_REQUEST    0
37534 #define M_RDMA_FLUSH_REQUEST    0x1fU
37535 #define V_RDMA_FLUSH_REQUEST(x) ((x) << S_RDMA_FLUSH_REQUEST)
37536 #define G_RDMA_FLUSH_REQUEST(x) (((x) >> S_RDMA_FLUSH_REQUEST) & M_RDMA_FLUSH_REQUEST)
37537 
37538 #define A_ULP_TX_IWARP_PMOF_OPCODES_2 0x8fa0
37539 
37540 #define S_RDMA_SEND_WITH_SE_IMMEDIATE    24
37541 #define M_RDMA_SEND_WITH_SE_IMMEDIATE    0x1fU
37542 #define V_RDMA_SEND_WITH_SE_IMMEDIATE(x) ((x) << S_RDMA_SEND_WITH_SE_IMMEDIATE)
37543 #define G_RDMA_SEND_WITH_SE_IMMEDIATE(x) (((x) >> S_RDMA_SEND_WITH_SE_IMMEDIATE) & M_RDMA_SEND_WITH_SE_IMMEDIATE)
37544 
37545 #define S_RDMA_SEND_WITH_IMMEDIATE    16
37546 #define M_RDMA_SEND_WITH_IMMEDIATE    0x1fU
37547 #define V_RDMA_SEND_WITH_IMMEDIATE(x) ((x) << S_RDMA_SEND_WITH_IMMEDIATE)
37548 #define G_RDMA_SEND_WITH_IMMEDIATE(x) (((x) >> S_RDMA_SEND_WITH_IMMEDIATE) & M_RDMA_SEND_WITH_IMMEDIATE)
37549 
37550 #define S_RDMA_ATOMIC_WRITE_RESPONSE    8
37551 #define M_RDMA_ATOMIC_WRITE_RESPONSE    0x1fU
37552 #define V_RDMA_ATOMIC_WRITE_RESPONSE(x) ((x) << S_RDMA_ATOMIC_WRITE_RESPONSE)
37553 #define G_RDMA_ATOMIC_WRITE_RESPONSE(x) (((x) >> S_RDMA_ATOMIC_WRITE_RESPONSE) & M_RDMA_ATOMIC_WRITE_RESPONSE)
37554 
37555 #define S_RDMA_ATOMIC_WRITE_REQUEST    0
37556 #define M_RDMA_ATOMIC_WRITE_REQUEST    0x1fU
37557 #define V_RDMA_ATOMIC_WRITE_REQUEST(x) ((x) << S_RDMA_ATOMIC_WRITE_REQUEST)
37558 #define G_RDMA_ATOMIC_WRITE_REQUEST(x) (((x) >> S_RDMA_ATOMIC_WRITE_REQUEST) & M_RDMA_ATOMIC_WRITE_REQUEST)
37559 
37560 #define A_ULP_TX_NVME_TCP_TPT_LLIMIT 0x8fa4
37561 #define A_ULP_TX_NVME_TCP_TPT_ULIMIT 0x8fa8
37562 #define A_ULP_TX_NVME_TCP_PBL_LLIMIT 0x8fac
37563 #define A_ULP_TX_NVME_TCP_PBL_ULIMIT 0x8fb0
37564 #define A_ULP_TX_TLS_IND_CMD 0x8fb8
37565 
37566 #define S_TLS_TX_REG_OFF_ADDR    0
37567 #define M_TLS_TX_REG_OFF_ADDR    0x3ffU
37568 #define V_TLS_TX_REG_OFF_ADDR(x) ((x) << S_TLS_TX_REG_OFF_ADDR)
37569 #define G_TLS_TX_REG_OFF_ADDR(x) (((x) >> S_TLS_TX_REG_OFF_ADDR) & M_TLS_TX_REG_OFF_ADDR)
37570 
37571 #define A_ULP_TX_DBG_CTL 0x8fb8
37572 #define A_ULP_TX_TLS_IND_DATA 0x8fbc
37573 #define A_ULP_TX_DBG_DATA 0x8fbc
37574 #define A_ULP_TX_TLS_CH0_PERR_CAUSE 0xc
37575 
37576 #define S_GLUE_PERR    3
37577 #define V_GLUE_PERR(x) ((x) << S_GLUE_PERR)
37578 #define F_GLUE_PERR    V_GLUE_PERR(1U)
37579 
37580 #define S_DSGL_PERR    2
37581 #define V_DSGL_PERR(x) ((x) << S_DSGL_PERR)
37582 #define F_DSGL_PERR    V_DSGL_PERR(1U)
37583 
37584 #define S_SGE_PERR    1
37585 #define V_SGE_PERR(x) ((x) << S_SGE_PERR)
37586 #define F_SGE_PERR    V_SGE_PERR(1U)
37587 
37588 #define S_KEX_PERR    0
37589 #define V_KEX_PERR(x) ((x) << S_KEX_PERR)
37590 #define F_KEX_PERR    V_KEX_PERR(1U)
37591 
37592 #define A_ULP_TX_TLS_CH0_PERR_ENABLE 0x10
37593 #define A_ULP_TX_TLS_CH0_HMACCTRL_CFG 0x20
37594 
37595 #define S_HMAC_CFG6    12
37596 #define M_HMAC_CFG6    0x3fU
37597 #define V_HMAC_CFG6(x) ((x) << S_HMAC_CFG6)
37598 #define G_HMAC_CFG6(x) (((x) >> S_HMAC_CFG6) & M_HMAC_CFG6)
37599 
37600 #define S_HMAC_CFG5    6
37601 #define M_HMAC_CFG5    0x3fU
37602 #define V_HMAC_CFG5(x) ((x) << S_HMAC_CFG5)
37603 #define G_HMAC_CFG5(x) (((x) >> S_HMAC_CFG5) & M_HMAC_CFG5)
37604 
37605 #define S_HMAC_CFG4    0
37606 #define M_HMAC_CFG4    0x3fU
37607 #define V_HMAC_CFG4(x) ((x) << S_HMAC_CFG4)
37608 #define G_HMAC_CFG4(x) (((x) >> S_HMAC_CFG4) & M_HMAC_CFG4)
37609 
37610 #define A_ULP_TX_TLS_CH1_PERR_CAUSE 0x4c
37611 #define A_ULP_TX_TLS_CH1_PERR_ENABLE 0x50
37612 #define A_ULP_TX_TLS_CH1_HMACCTRL_CFG 0x60
37613 
37614 /* registers for module PM_RX */
37615 #define PM_RX_BASE_ADDR 0x8fc0
37616 
37617 #define A_PM_RX_CFG 0x8fc0
37618 #define A_PM_RX_MODE 0x8fc4
37619 
37620 #define S_RX_USE_BUNDLE_LEN    4
37621 #define V_RX_USE_BUNDLE_LEN(x) ((x) << S_RX_USE_BUNDLE_LEN)
37622 #define F_RX_USE_BUNDLE_LEN    V_RX_USE_BUNDLE_LEN(1U)
37623 
37624 #define S_STAT_TO_CH    3
37625 #define V_STAT_TO_CH(x) ((x) << S_STAT_TO_CH)
37626 #define F_STAT_TO_CH    V_STAT_TO_CH(1U)
37627 
37628 #define S_STAT_FROM_CH    1
37629 #define M_STAT_FROM_CH    0x3U
37630 #define V_STAT_FROM_CH(x) ((x) << S_STAT_FROM_CH)
37631 #define G_STAT_FROM_CH(x) (((x) >> S_STAT_FROM_CH) & M_STAT_FROM_CH)
37632 
37633 #define S_PREFETCH_ENABLE    0
37634 #define V_PREFETCH_ENABLE(x) ((x) << S_PREFETCH_ENABLE)
37635 #define F_PREFETCH_ENABLE    V_PREFETCH_ENABLE(1U)
37636 
37637 #define S_CACHE_HOLD    13
37638 #define V_CACHE_HOLD(x) ((x) << S_CACHE_HOLD)
37639 #define F_CACHE_HOLD    V_CACHE_HOLD(1U)
37640 
37641 #define S_CACHE_INIT_DONE    12
37642 #define V_CACHE_INIT_DONE(x) ((x) << S_CACHE_INIT_DONE)
37643 #define F_CACHE_INIT_DONE    V_CACHE_INIT_DONE(1U)
37644 
37645 #define S_CACHE_DEPTH    8
37646 #define M_CACHE_DEPTH    0xfU
37647 #define V_CACHE_DEPTH(x) ((x) << S_CACHE_DEPTH)
37648 #define G_CACHE_DEPTH(x) (((x) >> S_CACHE_DEPTH) & M_CACHE_DEPTH)
37649 
37650 #define S_CACHE_INIT    7
37651 #define V_CACHE_INIT(x) ((x) << S_CACHE_INIT)
37652 #define F_CACHE_INIT    V_CACHE_INIT(1U)
37653 
37654 #define S_CACHE_SLEEP    6
37655 #define V_CACHE_SLEEP(x) ((x) << S_CACHE_SLEEP)
37656 #define F_CACHE_SLEEP    V_CACHE_SLEEP(1U)
37657 
37658 #define S_CACHE_BYPASS    5
37659 #define V_CACHE_BYPASS(x) ((x) << S_CACHE_BYPASS)
37660 #define F_CACHE_BYPASS    V_CACHE_BYPASS(1U)
37661 
37662 #define A_PM_RX_STAT_CONFIG 0x8fc8
37663 #define A_PM_RX_STAT_COUNT 0x8fcc
37664 #define A_PM_RX_STAT_LSB 0x8fd0
37665 #define A_PM_RX_DBG_CTRL 0x8fd0
37666 
37667 #define S_OSPIWRBUSY_T5    21
37668 #define M_OSPIWRBUSY_T5    0x3U
37669 #define V_OSPIWRBUSY_T5(x) ((x) << S_OSPIWRBUSY_T5)
37670 #define G_OSPIWRBUSY_T5(x) (((x) >> S_OSPIWRBUSY_T5) & M_OSPIWRBUSY_T5)
37671 
37672 #define S_ISPIWRBUSY    17
37673 #define M_ISPIWRBUSY    0xfU
37674 #define V_ISPIWRBUSY(x) ((x) << S_ISPIWRBUSY)
37675 #define G_ISPIWRBUSY(x) (((x) >> S_ISPIWRBUSY) & M_ISPIWRBUSY)
37676 
37677 #define S_PMDBGADDR    0
37678 #define M_PMDBGADDR    0x1ffffU
37679 #define V_PMDBGADDR(x) ((x) << S_PMDBGADDR)
37680 #define G_PMDBGADDR(x) (((x) >> S_PMDBGADDR) & M_PMDBGADDR)
37681 
37682 #define S_T7_OSPIWRBUSY_T5    21
37683 #define M_T7_OSPIWRBUSY_T5    0xfU
37684 #define V_T7_OSPIWRBUSY_T5(x) ((x) << S_T7_OSPIWRBUSY_T5)
37685 #define G_T7_OSPIWRBUSY_T5(x) (((x) >> S_T7_OSPIWRBUSY_T5) & M_T7_OSPIWRBUSY_T5)
37686 
37687 #define A_PM_RX_STAT_MSB 0x8fd4
37688 #define A_PM_RX_DBG_DATA 0x8fd4
37689 #define A_PM_RX_INT_ENABLE 0x8fd8
37690 
37691 #define S_ZERO_E_CMD_ERROR    22
37692 #define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
37693 #define F_ZERO_E_CMD_ERROR    V_ZERO_E_CMD_ERROR(1U)
37694 
37695 #define S_IESPI0_FIFO2X_RX_FRAMING_ERROR    21
37696 #define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
37697 #define F_IESPI0_FIFO2X_RX_FRAMING_ERROR    V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)
37698 
37699 #define S_IESPI1_FIFO2X_RX_FRAMING_ERROR    20
37700 #define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
37701 #define F_IESPI1_FIFO2X_RX_FRAMING_ERROR    V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)
37702 
37703 #define S_IESPI2_FIFO2X_RX_FRAMING_ERROR    19
37704 #define V_IESPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_FIFO2X_RX_FRAMING_ERROR)
37705 #define F_IESPI2_FIFO2X_RX_FRAMING_ERROR    V_IESPI2_FIFO2X_RX_FRAMING_ERROR(1U)
37706 
37707 #define S_IESPI3_FIFO2X_RX_FRAMING_ERROR    18
37708 #define V_IESPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_FIFO2X_RX_FRAMING_ERROR)
37709 #define F_IESPI3_FIFO2X_RX_FRAMING_ERROR    V_IESPI3_FIFO2X_RX_FRAMING_ERROR(1U)
37710 
37711 #define S_IESPI0_RX_FRAMING_ERROR    17
37712 #define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
37713 #define F_IESPI0_RX_FRAMING_ERROR    V_IESPI0_RX_FRAMING_ERROR(1U)
37714 
37715 #define S_IESPI1_RX_FRAMING_ERROR    16
37716 #define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
37717 #define F_IESPI1_RX_FRAMING_ERROR    V_IESPI1_RX_FRAMING_ERROR(1U)
37718 
37719 #define S_IESPI2_RX_FRAMING_ERROR    15
37720 #define V_IESPI2_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_RX_FRAMING_ERROR)
37721 #define F_IESPI2_RX_FRAMING_ERROR    V_IESPI2_RX_FRAMING_ERROR(1U)
37722 
37723 #define S_IESPI3_RX_FRAMING_ERROR    14
37724 #define V_IESPI3_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_RX_FRAMING_ERROR)
37725 #define F_IESPI3_RX_FRAMING_ERROR    V_IESPI3_RX_FRAMING_ERROR(1U)
37726 
37727 #define S_IESPI0_TX_FRAMING_ERROR    13
37728 #define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
37729 #define F_IESPI0_TX_FRAMING_ERROR    V_IESPI0_TX_FRAMING_ERROR(1U)
37730 
37731 #define S_IESPI1_TX_FRAMING_ERROR    12
37732 #define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
37733 #define F_IESPI1_TX_FRAMING_ERROR    V_IESPI1_TX_FRAMING_ERROR(1U)
37734 
37735 #define S_IESPI2_TX_FRAMING_ERROR    11
37736 #define V_IESPI2_TX_FRAMING_ERROR(x) ((x) << S_IESPI2_TX_FRAMING_ERROR)
37737 #define F_IESPI2_TX_FRAMING_ERROR    V_IESPI2_TX_FRAMING_ERROR(1U)
37738 
37739 #define S_IESPI3_TX_FRAMING_ERROR    10
37740 #define V_IESPI3_TX_FRAMING_ERROR(x) ((x) << S_IESPI3_TX_FRAMING_ERROR)
37741 #define F_IESPI3_TX_FRAMING_ERROR    V_IESPI3_TX_FRAMING_ERROR(1U)
37742 
37743 #define S_OCSPI0_RX_FRAMING_ERROR    9
37744 #define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
37745 #define F_OCSPI0_RX_FRAMING_ERROR    V_OCSPI0_RX_FRAMING_ERROR(1U)
37746 
37747 #define S_OCSPI1_RX_FRAMING_ERROR    8
37748 #define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
37749 #define F_OCSPI1_RX_FRAMING_ERROR    V_OCSPI1_RX_FRAMING_ERROR(1U)
37750 
37751 #define S_OCSPI0_TX_FRAMING_ERROR    7
37752 #define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
37753 #define F_OCSPI0_TX_FRAMING_ERROR    V_OCSPI0_TX_FRAMING_ERROR(1U)
37754 
37755 #define S_OCSPI1_TX_FRAMING_ERROR    6
37756 #define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
37757 #define F_OCSPI1_TX_FRAMING_ERROR    V_OCSPI1_TX_FRAMING_ERROR(1U)
37758 
37759 #define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    5
37760 #define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
37761 #define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
37762 
37763 #define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    4
37764 #define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
37765 #define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
37766 
37767 #define S_OCSPI_PAR_ERROR    3
37768 #define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
37769 #define F_OCSPI_PAR_ERROR    V_OCSPI_PAR_ERROR(1U)
37770 
37771 #define S_DB_OPTIONS_PAR_ERROR    2
37772 #define V_DB_OPTIONS_PAR_ERROR(x) ((x) << S_DB_OPTIONS_PAR_ERROR)
37773 #define F_DB_OPTIONS_PAR_ERROR    V_DB_OPTIONS_PAR_ERROR(1U)
37774 
37775 #define S_IESPI_PAR_ERROR    1
37776 #define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
37777 #define F_IESPI_PAR_ERROR    V_IESPI_PAR_ERROR(1U)
37778 
37779 #define S_E_PCMD_PAR_ERROR    0
37780 #define V_E_PCMD_PAR_ERROR(x) ((x) << S_E_PCMD_PAR_ERROR)
37781 #define F_E_PCMD_PAR_ERROR    V_E_PCMD_PAR_ERROR(1U)
37782 
37783 #define S_OSPI_OVERFLOW1    28
37784 #define V_OSPI_OVERFLOW1(x) ((x) << S_OSPI_OVERFLOW1)
37785 #define F_OSPI_OVERFLOW1    V_OSPI_OVERFLOW1(1U)
37786 
37787 #define S_OSPI_OVERFLOW0    27
37788 #define V_OSPI_OVERFLOW0(x) ((x) << S_OSPI_OVERFLOW0)
37789 #define F_OSPI_OVERFLOW0    V_OSPI_OVERFLOW0(1U)
37790 
37791 #define S_MA_INTF_SDC_ERR    26
37792 #define V_MA_INTF_SDC_ERR(x) ((x) << S_MA_INTF_SDC_ERR)
37793 #define F_MA_INTF_SDC_ERR    V_MA_INTF_SDC_ERR(1U)
37794 
37795 #define S_BUNDLE_LEN_PARERR    25
37796 #define V_BUNDLE_LEN_PARERR(x) ((x) << S_BUNDLE_LEN_PARERR)
37797 #define F_BUNDLE_LEN_PARERR    V_BUNDLE_LEN_PARERR(1U)
37798 
37799 #define S_BUNDLE_LEN_OVFL    24
37800 #define V_BUNDLE_LEN_OVFL(x) ((x) << S_BUNDLE_LEN_OVFL)
37801 #define F_BUNDLE_LEN_OVFL    V_BUNDLE_LEN_OVFL(1U)
37802 
37803 #define S_SDC_ERR    23
37804 #define V_SDC_ERR(x) ((x) << S_SDC_ERR)
37805 #define F_SDC_ERR    V_SDC_ERR(1U)
37806 
37807 #define S_MASTER_PERR    31
37808 #define V_MASTER_PERR(x) ((x) << S_MASTER_PERR)
37809 #define F_MASTER_PERR    V_MASTER_PERR(1U)
37810 
37811 #define S_T7_OSPI_OVERFLOW3    30
37812 #define V_T7_OSPI_OVERFLOW3(x) ((x) << S_T7_OSPI_OVERFLOW3)
37813 #define F_T7_OSPI_OVERFLOW3    V_T7_OSPI_OVERFLOW3(1U)
37814 
37815 #define S_T7_OSPI_OVERFLOW2    29
37816 #define V_T7_OSPI_OVERFLOW2(x) ((x) << S_T7_OSPI_OVERFLOW2)
37817 #define F_T7_OSPI_OVERFLOW2    V_T7_OSPI_OVERFLOW2(1U)
37818 
37819 #define A_PM_RX_INT_CAUSE 0x8fdc
37820 
37821 #define S_CACHE_SRAM_ERROR    3
37822 #define V_CACHE_SRAM_ERROR(x) ((x) << S_CACHE_SRAM_ERROR)
37823 #define F_CACHE_SRAM_ERROR    V_CACHE_SRAM_ERROR(1U)
37824 
37825 #define S_CACHE_LRU_ERROR    2
37826 #define V_CACHE_LRU_ERROR(x) ((x) << S_CACHE_LRU_ERROR)
37827 #define F_CACHE_LRU_ERROR    V_CACHE_LRU_ERROR(1U)
37828 
37829 #define S_CACHE_ISLAND_ERROR    1
37830 #define V_CACHE_ISLAND_ERROR(x) ((x) << S_CACHE_ISLAND_ERROR)
37831 #define F_CACHE_ISLAND_ERROR    V_CACHE_ISLAND_ERROR(1U)
37832 
37833 #define S_CACHE_CTRL_ERROR    0
37834 #define V_CACHE_CTRL_ERROR(x) ((x) << S_CACHE_CTRL_ERROR)
37835 #define F_CACHE_CTRL_ERROR    V_CACHE_CTRL_ERROR(1U)
37836 
37837 #define A_PM_RX_ISPI_DBG_4B_DATA0 0x10000
37838 #define A_PM_RX_ISPI_DBG_4B_DATA1 0x10001
37839 #define A_PM_RX_ISPI_DBG_4B_DATA2 0x10002
37840 #define A_PM_RX_ISPI_DBG_4B_DATA3 0x10003
37841 #define A_PM_RX_ISPI_DBG_4B_DATA4 0x10004
37842 #define A_PM_RX_ISPI_DBG_4B_DATA5 0x10005
37843 #define A_PM_RX_ISPI_DBG_4B_DATA6 0x10006
37844 #define A_PM_RX_ISPI_DBG_4B_DATA7 0x10007
37845 #define A_PM_RX_ISPI_DBG_4B_DATA8 0x10008
37846 #define A_PM_RX_OSPI_DBG_4B_DATA0 0x10009
37847 #define A_PM_RX_OSPI_DBG_4B_DATA1 0x1000a
37848 #define A_PM_RX_OSPI_DBG_4B_DATA2 0x1000b
37849 #define A_PM_RX_OSPI_DBG_4B_DATA3 0x1000c
37850 #define A_PM_RX_OSPI_DBG_4B_DATA4 0x1000d
37851 #define A_PM_RX_OSPI_DBG_4B_DATA5 0x1000e
37852 #define A_PM_RX_OSPI_DBG_4B_DATA6 0x1000f
37853 #define A_PM_RX_OSPI_DBG_4B_DATA7 0x10010
37854 #define A_PM_RX_OSPI_DBG_4B_DATA8 0x10011
37855 #define A_PM_RX_OSPI_DBG_4B_DATA9 0x10012
37856 #define A_PM_RX_DBG_STAT_MSB 0x10013
37857 #define A_PM_RX_DBG_STAT_LSB 0x10014
37858 #define A_PM_RX_DBG_RSVD_FLIT_CNT 0x10015
37859 
37860 #define S_I_TO_O_PATH_RSVD_FLIT_BACKUP    12
37861 #define M_I_TO_O_PATH_RSVD_FLIT_BACKUP    0xfU
37862 #define V_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT_BACKUP)
37863 #define G_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT_BACKUP) & M_I_TO_O_PATH_RSVD_FLIT_BACKUP)
37864 
37865 #define S_I_TO_O_PATH_RSVD_FLIT    8
37866 #define M_I_TO_O_PATH_RSVD_FLIT    0xfU
37867 #define V_I_TO_O_PATH_RSVD_FLIT(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT)
37868 #define G_I_TO_O_PATH_RSVD_FLIT(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT) & M_I_TO_O_PATH_RSVD_FLIT)
37869 
37870 #define S_PRFCH_RSVD_FLIT    4
37871 #define M_PRFCH_RSVD_FLIT    0xfU
37872 #define V_PRFCH_RSVD_FLIT(x) ((x) << S_PRFCH_RSVD_FLIT)
37873 #define G_PRFCH_RSVD_FLIT(x) (((x) >> S_PRFCH_RSVD_FLIT) & M_PRFCH_RSVD_FLIT)
37874 
37875 #define S_OSPI_RSVD_FLIT    0
37876 #define M_OSPI_RSVD_FLIT    0xfU
37877 #define V_OSPI_RSVD_FLIT(x) ((x) << S_OSPI_RSVD_FLIT)
37878 #define G_OSPI_RSVD_FLIT(x) (((x) >> S_OSPI_RSVD_FLIT) & M_OSPI_RSVD_FLIT)
37879 
37880 #define A_PM_RX_SDC_EN 0x10016
37881 
37882 #define S_SDC_EN    0
37883 #define V_SDC_EN(x) ((x) << S_SDC_EN)
37884 #define F_SDC_EN    V_SDC_EN(1U)
37885 
37886 #define A_PM_RX_INOUT_FIFO_DBG_CHNL_SEL 0x10017
37887 
37888 #define S_CHNL_3_SEL    3
37889 #define V_CHNL_3_SEL(x) ((x) << S_CHNL_3_SEL)
37890 #define F_CHNL_3_SEL    V_CHNL_3_SEL(1U)
37891 
37892 #define S_CHNL_2_SEL    2
37893 #define V_CHNL_2_SEL(x) ((x) << S_CHNL_2_SEL)
37894 #define F_CHNL_2_SEL    V_CHNL_2_SEL(1U)
37895 
37896 #define S_CHNL_1_SEL    1
37897 #define V_CHNL_1_SEL(x) ((x) << S_CHNL_1_SEL)
37898 #define F_CHNL_1_SEL    V_CHNL_1_SEL(1U)
37899 
37900 #define S_CHNL_0_SEL    0
37901 #define V_CHNL_0_SEL(x) ((x) << S_CHNL_0_SEL)
37902 #define F_CHNL_0_SEL    V_CHNL_0_SEL(1U)
37903 
37904 #define A_PM_RX_INOUT_FIFO_DBG_WR 0x10018
37905 
37906 #define S_O_FIFO_WRITE    3
37907 #define V_O_FIFO_WRITE(x) ((x) << S_O_FIFO_WRITE)
37908 #define F_O_FIFO_WRITE    V_O_FIFO_WRITE(1U)
37909 
37910 #define S_I_FIFO_WRITE    2
37911 #define V_I_FIFO_WRITE(x) ((x) << S_I_FIFO_WRITE)
37912 #define F_I_FIFO_WRITE    V_I_FIFO_WRITE(1U)
37913 
37914 #define S_O_FIFO_READ    1
37915 #define V_O_FIFO_READ(x) ((x) << S_O_FIFO_READ)
37916 #define F_O_FIFO_READ    V_O_FIFO_READ(1U)
37917 
37918 #define S_I_FIFO_READ    0
37919 #define V_I_FIFO_READ(x) ((x) << S_I_FIFO_READ)
37920 #define F_I_FIFO_READ    V_I_FIFO_READ(1U)
37921 
37922 #define A_PM_RX_INPUT_FIFO_STR_FWD_EN 0x10019
37923 
37924 #define S_ISPI_STR_FWD_EN    0
37925 #define V_ISPI_STR_FWD_EN(x) ((x) << S_ISPI_STR_FWD_EN)
37926 #define F_ISPI_STR_FWD_EN    V_ISPI_STR_FWD_EN(1U)
37927 
37928 #define A_PM_RX_PRFTCH_ACROSS_BNDLE_EN 0x1001a
37929 
37930 #define S_PRFTCH_ACROSS_BNDLE_EN    0
37931 #define V_PRFTCH_ACROSS_BNDLE_EN(x) ((x) << S_PRFTCH_ACROSS_BNDLE_EN)
37932 #define F_PRFTCH_ACROSS_BNDLE_EN    V_PRFTCH_ACROSS_BNDLE_EN(1U)
37933 
37934 #define A_PM_RX_PRFTCH_WRR_ENABLE 0x1001b
37935 
37936 #define S_PRFTCH_WRR_ENABLE    0
37937 #define V_PRFTCH_WRR_ENABLE(x) ((x) << S_PRFTCH_WRR_ENABLE)
37938 #define F_PRFTCH_WRR_ENABLE    V_PRFTCH_WRR_ENABLE(1U)
37939 
37940 #define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT 0x1001c
37941 
37942 #define S_CHNL1_MAX_DEFICIT_CNT    16
37943 #define M_CHNL1_MAX_DEFICIT_CNT    0xffffU
37944 #define V_CHNL1_MAX_DEFICIT_CNT(x) ((x) << S_CHNL1_MAX_DEFICIT_CNT)
37945 #define G_CHNL1_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL1_MAX_DEFICIT_CNT) & M_CHNL1_MAX_DEFICIT_CNT)
37946 
37947 #define S_CHNL0_MAX_DEFICIT_CNT    0
37948 #define M_CHNL0_MAX_DEFICIT_CNT    0xffffU
37949 #define V_CHNL0_MAX_DEFICIT_CNT(x) ((x) << S_CHNL0_MAX_DEFICIT_CNT)
37950 #define G_CHNL0_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL0_MAX_DEFICIT_CNT) & M_CHNL0_MAX_DEFICIT_CNT)
37951 
37952 #define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT0 0x1001c
37953 #define A_PM_RX_FEATURE_EN 0x1001d
37954 
37955 #define S_PIO_CH_DEFICIT_CTL_EN_RX    0
37956 #define V_PIO_CH_DEFICIT_CTL_EN_RX(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN_RX)
37957 #define F_PIO_CH_DEFICIT_CTL_EN_RX    V_PIO_CH_DEFICIT_CTL_EN_RX(1U)
37958 
37959 #define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT1 0x1001d
37960 
37961 #define S_CHNL3_MAX_DEFICIT_CNT    16
37962 #define M_CHNL3_MAX_DEFICIT_CNT    0xffffU
37963 #define V_CHNL3_MAX_DEFICIT_CNT(x) ((x) << S_CHNL3_MAX_DEFICIT_CNT)
37964 #define G_CHNL3_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL3_MAX_DEFICIT_CNT) & M_CHNL3_MAX_DEFICIT_CNT)
37965 
37966 #define S_CHNL2_MAX_DEFICIT_CNT    0
37967 #define M_CHNL2_MAX_DEFICIT_CNT    0xffffU
37968 #define V_CHNL2_MAX_DEFICIT_CNT(x) ((x) << S_CHNL2_MAX_DEFICIT_CNT)
37969 #define G_CHNL2_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL2_MAX_DEFICIT_CNT) & M_CHNL2_MAX_DEFICIT_CNT)
37970 
37971 #define A_PM_RX_CH0_OSPI_DEFICIT_THRSHLD 0x1001e
37972 
37973 #define S_CH0_OSPI_DEFICIT_THRSHLD    0
37974 #define M_CH0_OSPI_DEFICIT_THRSHLD    0xfffU
37975 #define V_CH0_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH0_OSPI_DEFICIT_THRSHLD)
37976 #define G_CH0_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH0_OSPI_DEFICIT_THRSHLD) & M_CH0_OSPI_DEFICIT_THRSHLD)
37977 
37978 #define A_PM_RX_CH1_OSPI_DEFICIT_THRSHLD 0x1001f
37979 
37980 #define S_CH1_OSPI_DEFICIT_THRSHLD    0
37981 #define M_CH1_OSPI_DEFICIT_THRSHLD    0xfffU
37982 #define V_CH1_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH1_OSPI_DEFICIT_THRSHLD)
37983 #define G_CH1_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH1_OSPI_DEFICIT_THRSHLD) & M_CH1_OSPI_DEFICIT_THRSHLD)
37984 
37985 #define A_PM_RX_INT_CAUSE_MASK_HALT 0x10020
37986 #define A_PM_RX_DBG_STAT0 0x10021
37987 
37988 #define S_RX_RD_I_BUSY    29
37989 #define V_RX_RD_I_BUSY(x) ((x) << S_RX_RD_I_BUSY)
37990 #define F_RX_RD_I_BUSY    V_RX_RD_I_BUSY(1U)
37991 
37992 #define S_RX_WR_TO_O_BUSY    28
37993 #define V_RX_WR_TO_O_BUSY(x) ((x) << S_RX_WR_TO_O_BUSY)
37994 #define F_RX_WR_TO_O_BUSY    V_RX_WR_TO_O_BUSY(1U)
37995 
37996 #define S_RX_M_TO_O_BUSY    27
37997 #define V_RX_M_TO_O_BUSY(x) ((x) << S_RX_M_TO_O_BUSY)
37998 #define F_RX_M_TO_O_BUSY    V_RX_M_TO_O_BUSY(1U)
37999 
38000 #define S_RX_I_TO_M_BUSY    26
38001 #define V_RX_I_TO_M_BUSY(x) ((x) << S_RX_I_TO_M_BUSY)
38002 #define F_RX_I_TO_M_BUSY    V_RX_I_TO_M_BUSY(1U)
38003 
38004 #define S_RX_PCMD_FB_ONLY    25
38005 #define V_RX_PCMD_FB_ONLY(x) ((x) << S_RX_PCMD_FB_ONLY)
38006 #define F_RX_PCMD_FB_ONLY    V_RX_PCMD_FB_ONLY(1U)
38007 
38008 #define S_RX_PCMD_MEM    24
38009 #define V_RX_PCMD_MEM(x) ((x) << S_RX_PCMD_MEM)
38010 #define F_RX_PCMD_MEM    V_RX_PCMD_MEM(1U)
38011 
38012 #define S_RX_PCMD_BYPASS    23
38013 #define V_RX_PCMD_BYPASS(x) ((x) << S_RX_PCMD_BYPASS)
38014 #define F_RX_PCMD_BYPASS    V_RX_PCMD_BYPASS(1U)
38015 
38016 #define S_RX_PCMD_EOP    22
38017 #define V_RX_PCMD_EOP(x) ((x) << S_RX_PCMD_EOP)
38018 #define F_RX_PCMD_EOP    V_RX_PCMD_EOP(1U)
38019 
38020 #define S_RX_DUMPLICATE_PCMD_EOP    21
38021 #define V_RX_DUMPLICATE_PCMD_EOP(x) ((x) << S_RX_DUMPLICATE_PCMD_EOP)
38022 #define F_RX_DUMPLICATE_PCMD_EOP    V_RX_DUMPLICATE_PCMD_EOP(1U)
38023 
38024 #define S_RX_PCMD_EOB    20
38025 #define V_RX_PCMD_EOB(x) ((x) << S_RX_PCMD_EOB)
38026 #define F_RX_PCMD_EOB    V_RX_PCMD_EOB(1U)
38027 
38028 #define S_RX_PCMD_FB    16
38029 #define M_RX_PCMD_FB    0xfU
38030 #define V_RX_PCMD_FB(x) ((x) << S_RX_PCMD_FB)
38031 #define G_RX_PCMD_FB(x) (((x) >> S_RX_PCMD_FB) & M_RX_PCMD_FB)
38032 
38033 #define S_RX_PCMD_LEN    0
38034 #define M_RX_PCMD_LEN    0xffffU
38035 #define V_RX_PCMD_LEN(x) ((x) << S_RX_PCMD_LEN)
38036 #define G_RX_PCMD_LEN(x) (((x) >> S_RX_PCMD_LEN) & M_RX_PCMD_LEN)
38037 
38038 #define A_PM_RX_DBG_STAT1 0x10022
38039 
38040 #define S_RX_PCMD0_MEM    30
38041 #define V_RX_PCMD0_MEM(x) ((x) << S_RX_PCMD0_MEM)
38042 #define F_RX_PCMD0_MEM    V_RX_PCMD0_MEM(1U)
38043 
38044 #define S_RX_FREE_OSPI_CNT0    18
38045 #define M_RX_FREE_OSPI_CNT0    0xfffU
38046 #define V_RX_FREE_OSPI_CNT0(x) ((x) << S_RX_FREE_OSPI_CNT0)
38047 #define G_RX_FREE_OSPI_CNT0(x) (((x) >> S_RX_FREE_OSPI_CNT0) & M_RX_FREE_OSPI_CNT0)
38048 
38049 #define S_RX_PCMD0_FLIT_LEN    6
38050 #define M_RX_PCMD0_FLIT_LEN    0xfffU
38051 #define V_RX_PCMD0_FLIT_LEN(x) ((x) << S_RX_PCMD0_FLIT_LEN)
38052 #define G_RX_PCMD0_FLIT_LEN(x) (((x) >> S_RX_PCMD0_FLIT_LEN) & M_RX_PCMD0_FLIT_LEN)
38053 
38054 #define S_RX_PCMD0_CMD    2
38055 #define M_RX_PCMD0_CMD    0xfU
38056 #define V_RX_PCMD0_CMD(x) ((x) << S_RX_PCMD0_CMD)
38057 #define G_RX_PCMD0_CMD(x) (((x) >> S_RX_PCMD0_CMD) & M_RX_PCMD0_CMD)
38058 
38059 #define S_RX_OFIFO_FULL0    1
38060 #define V_RX_OFIFO_FULL0(x) ((x) << S_RX_OFIFO_FULL0)
38061 #define F_RX_OFIFO_FULL0    V_RX_OFIFO_FULL0(1U)
38062 
38063 #define S_RX_PCMD0_BYPASS    0
38064 #define V_RX_PCMD0_BYPASS(x) ((x) << S_RX_PCMD0_BYPASS)
38065 #define F_RX_PCMD0_BYPASS    V_RX_PCMD0_BYPASS(1U)
38066 
38067 #define A_PM_RX_DBG_STAT2 0x10023
38068 
38069 #define S_RX_PCMD1_MEM    30
38070 #define V_RX_PCMD1_MEM(x) ((x) << S_RX_PCMD1_MEM)
38071 #define F_RX_PCMD1_MEM    V_RX_PCMD1_MEM(1U)
38072 
38073 #define S_RX_FREE_OSPI_CNT1    18
38074 #define M_RX_FREE_OSPI_CNT1    0xfffU
38075 #define V_RX_FREE_OSPI_CNT1(x) ((x) << S_RX_FREE_OSPI_CNT1)
38076 #define G_RX_FREE_OSPI_CNT1(x) (((x) >> S_RX_FREE_OSPI_CNT1) & M_RX_FREE_OSPI_CNT1)
38077 
38078 #define S_RX_PCMD1_FLIT_LEN    6
38079 #define M_RX_PCMD1_FLIT_LEN    0xfffU
38080 #define V_RX_PCMD1_FLIT_LEN(x) ((x) << S_RX_PCMD1_FLIT_LEN)
38081 #define G_RX_PCMD1_FLIT_LEN(x) (((x) >> S_RX_PCMD1_FLIT_LEN) & M_RX_PCMD1_FLIT_LEN)
38082 
38083 #define S_RX_PCMD1_CMD    2
38084 #define M_RX_PCMD1_CMD    0xfU
38085 #define V_RX_PCMD1_CMD(x) ((x) << S_RX_PCMD1_CMD)
38086 #define G_RX_PCMD1_CMD(x) (((x) >> S_RX_PCMD1_CMD) & M_RX_PCMD1_CMD)
38087 
38088 #define S_RX_OFIFO_FULL1    1
38089 #define V_RX_OFIFO_FULL1(x) ((x) << S_RX_OFIFO_FULL1)
38090 #define F_RX_OFIFO_FULL1    V_RX_OFIFO_FULL1(1U)
38091 
38092 #define S_RX_PCMD1_BYPASS    0
38093 #define V_RX_PCMD1_BYPASS(x) ((x) << S_RX_PCMD1_BYPASS)
38094 #define F_RX_PCMD1_BYPASS    V_RX_PCMD1_BYPASS(1U)
38095 
38096 #define A_PM_RX_DBG_STAT3 0x10024
38097 
38098 #define S_RX_SET_PCMD_RES_RDY_RD    10
38099 #define M_RX_SET_PCMD_RES_RDY_RD    0x3U
38100 #define V_RX_SET_PCMD_RES_RDY_RD(x) ((x) << S_RX_SET_PCMD_RES_RDY_RD)
38101 #define G_RX_SET_PCMD_RES_RDY_RD(x) (((x) >> S_RX_SET_PCMD_RES_RDY_RD) & M_RX_SET_PCMD_RES_RDY_RD)
38102 
38103 #define S_RX_ISSUED_PREFETCH_RD_E_CLR    8
38104 #define M_RX_ISSUED_PREFETCH_RD_E_CLR    0x3U
38105 #define V_RX_ISSUED_PREFETCH_RD_E_CLR(x) ((x) << S_RX_ISSUED_PREFETCH_RD_E_CLR)
38106 #define G_RX_ISSUED_PREFETCH_RD_E_CLR(x) (((x) >> S_RX_ISSUED_PREFETCH_RD_E_CLR) & M_RX_ISSUED_PREFETCH_RD_E_CLR)
38107 
38108 #define S_RX_ISSUED_PREFETCH_RD    6
38109 #define M_RX_ISSUED_PREFETCH_RD    0x3U
38110 #define V_RX_ISSUED_PREFETCH_RD(x) ((x) << S_RX_ISSUED_PREFETCH_RD)
38111 #define G_RX_ISSUED_PREFETCH_RD(x) (((x) >> S_RX_ISSUED_PREFETCH_RD) & M_RX_ISSUED_PREFETCH_RD)
38112 
38113 #define S_RX_PCMD_RES_RDY    4
38114 #define M_RX_PCMD_RES_RDY    0x3U
38115 #define V_RX_PCMD_RES_RDY(x) ((x) << S_RX_PCMD_RES_RDY)
38116 #define G_RX_PCMD_RES_RDY(x) (((x) >> S_RX_PCMD_RES_RDY) & M_RX_PCMD_RES_RDY)
38117 
38118 #define S_RX_DB_VLD    3
38119 #define V_RX_DB_VLD(x) ((x) << S_RX_DB_VLD)
38120 #define F_RX_DB_VLD    V_RX_DB_VLD(1U)
38121 
38122 #define S_RX_FIRST_BUNDLE    1
38123 #define M_RX_FIRST_BUNDLE    0x3U
38124 #define V_RX_FIRST_BUNDLE(x) ((x) << S_RX_FIRST_BUNDLE)
38125 #define G_RX_FIRST_BUNDLE(x) (((x) >> S_RX_FIRST_BUNDLE) & M_RX_FIRST_BUNDLE)
38126 
38127 #define S_RX_SDC_DRDY    0
38128 #define V_RX_SDC_DRDY(x) ((x) << S_RX_SDC_DRDY)
38129 #define F_RX_SDC_DRDY    V_RX_SDC_DRDY(1U)
38130 
38131 #define A_PM_RX_DBG_STAT4 0x10025
38132 
38133 #define S_RX_PCMD_VLD    26
38134 #define V_RX_PCMD_VLD(x) ((x) << S_RX_PCMD_VLD)
38135 #define F_RX_PCMD_VLD    V_RX_PCMD_VLD(1U)
38136 
38137 #define S_RX_PCMD_TO_CH    25
38138 #define V_RX_PCMD_TO_CH(x) ((x) << S_RX_PCMD_TO_CH)
38139 #define F_RX_PCMD_TO_CH    V_RX_PCMD_TO_CH(1U)
38140 
38141 #define S_RX_PCMD_FROM_CH    23
38142 #define M_RX_PCMD_FROM_CH    0x3U
38143 #define V_RX_PCMD_FROM_CH(x) ((x) << S_RX_PCMD_FROM_CH)
38144 #define G_RX_PCMD_FROM_CH(x) (((x) >> S_RX_PCMD_FROM_CH) & M_RX_PCMD_FROM_CH)
38145 
38146 #define S_RX_LINE    18
38147 #define M_RX_LINE    0x1fU
38148 #define V_RX_LINE(x) ((x) << S_RX_LINE)
38149 #define G_RX_LINE(x) (((x) >> S_RX_LINE) & M_RX_LINE)
38150 
38151 #define S_RX_IESPI_TXVALID    14
38152 #define M_RX_IESPI_TXVALID    0xfU
38153 #define V_RX_IESPI_TXVALID(x) ((x) << S_RX_IESPI_TXVALID)
38154 #define G_RX_IESPI_TXVALID(x) (((x) >> S_RX_IESPI_TXVALID) & M_RX_IESPI_TXVALID)
38155 
38156 #define S_RX_IESPI_TXFULL    10
38157 #define M_RX_IESPI_TXFULL    0xfU
38158 #define V_RX_IESPI_TXFULL(x) ((x) << S_RX_IESPI_TXFULL)
38159 #define G_RX_IESPI_TXFULL(x) (((x) >> S_RX_IESPI_TXFULL) & M_RX_IESPI_TXFULL)
38160 
38161 #define S_RX_PCMD_SRDY    8
38162 #define M_RX_PCMD_SRDY    0x3U
38163 #define V_RX_PCMD_SRDY(x) ((x) << S_RX_PCMD_SRDY)
38164 #define G_RX_PCMD_SRDY(x) (((x) >> S_RX_PCMD_SRDY) & M_RX_PCMD_SRDY)
38165 
38166 #define S_RX_PCMD_DRDY    6
38167 #define M_RX_PCMD_DRDY    0x3U
38168 #define V_RX_PCMD_DRDY(x) ((x) << S_RX_PCMD_DRDY)
38169 #define G_RX_PCMD_DRDY(x) (((x) >> S_RX_PCMD_DRDY) & M_RX_PCMD_DRDY)
38170 
38171 #define S_RX_PCMD_CMD    2
38172 #define M_RX_PCMD_CMD    0xfU
38173 #define V_RX_PCMD_CMD(x) ((x) << S_RX_PCMD_CMD)
38174 #define G_RX_PCMD_CMD(x) (((x) >> S_RX_PCMD_CMD) & M_RX_PCMD_CMD)
38175 
38176 #define S_DUPLICATE    0
38177 #define M_DUPLICATE    0x3U
38178 #define V_DUPLICATE(x) ((x) << S_DUPLICATE)
38179 #define G_DUPLICATE(x) (((x) >> S_DUPLICATE) & M_DUPLICATE)
38180 
38181 #define S_RX_PCMD_SRDY_STAT4    8
38182 #define M_RX_PCMD_SRDY_STAT4    0x3U
38183 #define V_RX_PCMD_SRDY_STAT4(x) ((x) << S_RX_PCMD_SRDY_STAT4)
38184 #define G_RX_PCMD_SRDY_STAT4(x) (((x) >> S_RX_PCMD_SRDY_STAT4) & M_RX_PCMD_SRDY_STAT4)
38185 
38186 #define S_RX_PCMD_DRDY_STAT4    6
38187 #define M_RX_PCMD_DRDY_STAT4    0x3U
38188 #define V_RX_PCMD_DRDY_STAT4(x) ((x) << S_RX_PCMD_DRDY_STAT4)
38189 #define G_RX_PCMD_DRDY_STAT4(x) (((x) >> S_RX_PCMD_DRDY_STAT4) & M_RX_PCMD_DRDY_STAT4)
38190 
38191 #define A_PM_RX_DBG_STAT5 0x10026
38192 
38193 #define S_RX_ATLST_1_PCMD_CH1    29
38194 #define V_RX_ATLST_1_PCMD_CH1(x) ((x) << S_RX_ATLST_1_PCMD_CH1)
38195 #define F_RX_ATLST_1_PCMD_CH1    V_RX_ATLST_1_PCMD_CH1(1U)
38196 
38197 #define S_RX_ATLST_1_PCMD_CH0    28
38198 #define V_RX_ATLST_1_PCMD_CH0(x) ((x) << S_RX_ATLST_1_PCMD_CH0)
38199 #define F_RX_ATLST_1_PCMD_CH0    V_RX_ATLST_1_PCMD_CH0(1U)
38200 
38201 #define S_T5_RX_PCMD_DRDY    26
38202 #define M_T5_RX_PCMD_DRDY    0x3U
38203 #define V_T5_RX_PCMD_DRDY(x) ((x) << S_T5_RX_PCMD_DRDY)
38204 #define G_T5_RX_PCMD_DRDY(x) (((x) >> S_T5_RX_PCMD_DRDY) & M_T5_RX_PCMD_DRDY)
38205 
38206 #define S_T5_RX_PCMD_SRDY    24
38207 #define M_T5_RX_PCMD_SRDY    0x3U
38208 #define V_T5_RX_PCMD_SRDY(x) ((x) << S_T5_RX_PCMD_SRDY)
38209 #define G_T5_RX_PCMD_SRDY(x) (((x) >> S_T5_RX_PCMD_SRDY) & M_T5_RX_PCMD_SRDY)
38210 
38211 #define S_RX_ISPI_TXVALID    20
38212 #define M_RX_ISPI_TXVALID    0xfU
38213 #define V_RX_ISPI_TXVALID(x) ((x) << S_RX_ISPI_TXVALID)
38214 #define G_RX_ISPI_TXVALID(x) (((x) >> S_RX_ISPI_TXVALID) & M_RX_ISPI_TXVALID)
38215 
38216 #define S_RX_ISPI_FULL    16
38217 #define M_RX_ISPI_FULL    0xfU
38218 #define V_RX_ISPI_FULL(x) ((x) << S_RX_ISPI_FULL)
38219 #define G_RX_ISPI_FULL(x) (((x) >> S_RX_ISPI_FULL) & M_RX_ISPI_FULL)
38220 
38221 #define S_RX_OSPI_TXVALID    14
38222 #define M_RX_OSPI_TXVALID    0x3U
38223 #define V_RX_OSPI_TXVALID(x) ((x) << S_RX_OSPI_TXVALID)
38224 #define G_RX_OSPI_TXVALID(x) (((x) >> S_RX_OSPI_TXVALID) & M_RX_OSPI_TXVALID)
38225 
38226 #define S_RX_OSPI_FULL    12
38227 #define M_RX_OSPI_FULL    0x3U
38228 #define V_RX_OSPI_FULL(x) ((x) << S_RX_OSPI_FULL)
38229 #define G_RX_OSPI_FULL(x) (((x) >> S_RX_OSPI_FULL) & M_RX_OSPI_FULL)
38230 
38231 #define S_RX_E_RXVALID    8
38232 #define M_RX_E_RXVALID    0xfU
38233 #define V_RX_E_RXVALID(x) ((x) << S_RX_E_RXVALID)
38234 #define G_RX_E_RXVALID(x) (((x) >> S_RX_E_RXVALID) & M_RX_E_RXVALID)
38235 
38236 #define S_RX_E_RXAFULL    4
38237 #define M_RX_E_RXAFULL    0xfU
38238 #define V_RX_E_RXAFULL(x) ((x) << S_RX_E_RXAFULL)
38239 #define G_RX_E_RXAFULL(x) (((x) >> S_RX_E_RXAFULL) & M_RX_E_RXAFULL)
38240 
38241 #define S_RX_C_TXVALID    2
38242 #define M_RX_C_TXVALID    0x3U
38243 #define V_RX_C_TXVALID(x) ((x) << S_RX_C_TXVALID)
38244 #define G_RX_C_TXVALID(x) (((x) >> S_RX_C_TXVALID) & M_RX_C_TXVALID)
38245 
38246 #define S_RX_C_TXAFULL    0
38247 #define M_RX_C_TXAFULL    0x3U
38248 #define V_RX_C_TXAFULL(x) ((x) << S_RX_C_TXAFULL)
38249 #define G_RX_C_TXAFULL(x) (((x) >> S_RX_C_TXAFULL) & M_RX_C_TXAFULL)
38250 
38251 #define A_PM_RX_DBG_STAT6 0x10027
38252 
38253 #define S_RX_M_INTRNL_FIFO_CNT    4
38254 #define M_RX_M_INTRNL_FIFO_CNT    0x3U
38255 #define V_RX_M_INTRNL_FIFO_CNT(x) ((x) << S_RX_M_INTRNL_FIFO_CNT)
38256 #define G_RX_M_INTRNL_FIFO_CNT(x) (((x) >> S_RX_M_INTRNL_FIFO_CNT) & M_RX_M_INTRNL_FIFO_CNT)
38257 
38258 #define S_RX_M_REQADDRRDY    3
38259 #define V_RX_M_REQADDRRDY(x) ((x) << S_RX_M_REQADDRRDY)
38260 #define F_RX_M_REQADDRRDY    V_RX_M_REQADDRRDY(1U)
38261 
38262 #define S_RX_M_REQWRITE    2
38263 #define V_RX_M_REQWRITE(x) ((x) << S_RX_M_REQWRITE)
38264 #define F_RX_M_REQWRITE    V_RX_M_REQWRITE(1U)
38265 
38266 #define S_RX_M_REQDATAVLD    1
38267 #define V_RX_M_REQDATAVLD(x) ((x) << S_RX_M_REQDATAVLD)
38268 #define F_RX_M_REQDATAVLD    V_RX_M_REQDATAVLD(1U)
38269 
38270 #define S_RX_M_REQDATARDY    0
38271 #define V_RX_M_REQDATARDY(x) ((x) << S_RX_M_REQDATARDY)
38272 #define F_RX_M_REQDATARDY    V_RX_M_REQDATARDY(1U)
38273 
38274 #define S_T6_RX_M_INTRNL_FIFO_CNT    7
38275 #define M_T6_RX_M_INTRNL_FIFO_CNT    0x3U
38276 #define V_T6_RX_M_INTRNL_FIFO_CNT(x) ((x) << S_T6_RX_M_INTRNL_FIFO_CNT)
38277 #define G_T6_RX_M_INTRNL_FIFO_CNT(x) (((x) >> S_T6_RX_M_INTRNL_FIFO_CNT) & M_T6_RX_M_INTRNL_FIFO_CNT)
38278 
38279 #define S_RX_M_RSPVLD    6
38280 #define V_RX_M_RSPVLD(x) ((x) << S_RX_M_RSPVLD)
38281 #define F_RX_M_RSPVLD    V_RX_M_RSPVLD(1U)
38282 
38283 #define S_RX_M_RSPRDY    5
38284 #define V_RX_M_RSPRDY(x) ((x) << S_RX_M_RSPRDY)
38285 #define F_RX_M_RSPRDY    V_RX_M_RSPRDY(1U)
38286 
38287 #define S_RX_M_REQADDRVLD    4
38288 #define V_RX_M_REQADDRVLD(x) ((x) << S_RX_M_REQADDRVLD)
38289 #define F_RX_M_REQADDRVLD    V_RX_M_REQADDRVLD(1U)
38290 
38291 #define A_PM_RX_DBG_STAT7 0x10028
38292 
38293 #define S_RX_PCMD1_FREE_CNT    7
38294 #define M_RX_PCMD1_FREE_CNT    0x7fU
38295 #define V_RX_PCMD1_FREE_CNT(x) ((x) << S_RX_PCMD1_FREE_CNT)
38296 #define G_RX_PCMD1_FREE_CNT(x) (((x) >> S_RX_PCMD1_FREE_CNT) & M_RX_PCMD1_FREE_CNT)
38297 
38298 #define S_RX_PCMD0_FREE_CNT    0
38299 #define M_RX_PCMD0_FREE_CNT    0x7fU
38300 #define V_RX_PCMD0_FREE_CNT(x) ((x) << S_RX_PCMD0_FREE_CNT)
38301 #define G_RX_PCMD0_FREE_CNT(x) (((x) >> S_RX_PCMD0_FREE_CNT) & M_RX_PCMD0_FREE_CNT)
38302 
38303 #define A_PM_RX_DBG_STAT8 0x10029
38304 
38305 #define S_RX_IN_EOP_CNT3    28
38306 #define M_RX_IN_EOP_CNT3    0xfU
38307 #define V_RX_IN_EOP_CNT3(x) ((x) << S_RX_IN_EOP_CNT3)
38308 #define G_RX_IN_EOP_CNT3(x) (((x) >> S_RX_IN_EOP_CNT3) & M_RX_IN_EOP_CNT3)
38309 
38310 #define S_RX_IN_EOP_CNT2    24
38311 #define M_RX_IN_EOP_CNT2    0xfU
38312 #define V_RX_IN_EOP_CNT2(x) ((x) << S_RX_IN_EOP_CNT2)
38313 #define G_RX_IN_EOP_CNT2(x) (((x) >> S_RX_IN_EOP_CNT2) & M_RX_IN_EOP_CNT2)
38314 
38315 #define S_RX_IN_EOP_CNT1    20
38316 #define M_RX_IN_EOP_CNT1    0xfU
38317 #define V_RX_IN_EOP_CNT1(x) ((x) << S_RX_IN_EOP_CNT1)
38318 #define G_RX_IN_EOP_CNT1(x) (((x) >> S_RX_IN_EOP_CNT1) & M_RX_IN_EOP_CNT1)
38319 
38320 #define S_RX_IN_EOP_CNT0    16
38321 #define M_RX_IN_EOP_CNT0    0xfU
38322 #define V_RX_IN_EOP_CNT0(x) ((x) << S_RX_IN_EOP_CNT0)
38323 #define G_RX_IN_EOP_CNT0(x) (((x) >> S_RX_IN_EOP_CNT0) & M_RX_IN_EOP_CNT0)
38324 
38325 #define S_RX_IN_SOP_CNT3    12
38326 #define M_RX_IN_SOP_CNT3    0xfU
38327 #define V_RX_IN_SOP_CNT3(x) ((x) << S_RX_IN_SOP_CNT3)
38328 #define G_RX_IN_SOP_CNT3(x) (((x) >> S_RX_IN_SOP_CNT3) & M_RX_IN_SOP_CNT3)
38329 
38330 #define S_RX_IN_SOP_CNT2    8
38331 #define M_RX_IN_SOP_CNT2    0xfU
38332 #define V_RX_IN_SOP_CNT2(x) ((x) << S_RX_IN_SOP_CNT2)
38333 #define G_RX_IN_SOP_CNT2(x) (((x) >> S_RX_IN_SOP_CNT2) & M_RX_IN_SOP_CNT2)
38334 
38335 #define S_RX_IN_SOP_CNT1    4
38336 #define M_RX_IN_SOP_CNT1    0xfU
38337 #define V_RX_IN_SOP_CNT1(x) ((x) << S_RX_IN_SOP_CNT1)
38338 #define G_RX_IN_SOP_CNT1(x) (((x) >> S_RX_IN_SOP_CNT1) & M_RX_IN_SOP_CNT1)
38339 
38340 #define S_RX_IN_SOP_CNT0    0
38341 #define M_RX_IN_SOP_CNT0    0xfU
38342 #define V_RX_IN_SOP_CNT0(x) ((x) << S_RX_IN_SOP_CNT0)
38343 #define G_RX_IN_SOP_CNT0(x) (((x) >> S_RX_IN_SOP_CNT0) & M_RX_IN_SOP_CNT0)
38344 
38345 #define A_PM_RX_DBG_STAT9 0x1002a
38346 
38347 #define S_RX_RSVD0    28
38348 #define M_RX_RSVD0    0xfU
38349 #define V_RX_RSVD0(x) ((x) << S_RX_RSVD0)
38350 #define G_RX_RSVD0(x) (((x) >> S_RX_RSVD0) & M_RX_RSVD0)
38351 
38352 #define S_RX_RSVD1    24
38353 #define M_RX_RSVD1    0xfU
38354 #define V_RX_RSVD1(x) ((x) << S_RX_RSVD1)
38355 #define G_RX_RSVD1(x) (((x) >> S_RX_RSVD1) & M_RX_RSVD1)
38356 
38357 #define S_RX_OUT_EOP_CNT1    20
38358 #define M_RX_OUT_EOP_CNT1    0xfU
38359 #define V_RX_OUT_EOP_CNT1(x) ((x) << S_RX_OUT_EOP_CNT1)
38360 #define G_RX_OUT_EOP_CNT1(x) (((x) >> S_RX_OUT_EOP_CNT1) & M_RX_OUT_EOP_CNT1)
38361 
38362 #define S_RX_OUT_EOP_CNT0    16
38363 #define M_RX_OUT_EOP_CNT0    0xfU
38364 #define V_RX_OUT_EOP_CNT0(x) ((x) << S_RX_OUT_EOP_CNT0)
38365 #define G_RX_OUT_EOP_CNT0(x) (((x) >> S_RX_OUT_EOP_CNT0) & M_RX_OUT_EOP_CNT0)
38366 
38367 #define S_RX_RSVD2    12
38368 #define M_RX_RSVD2    0xfU
38369 #define V_RX_RSVD2(x) ((x) << S_RX_RSVD2)
38370 #define G_RX_RSVD2(x) (((x) >> S_RX_RSVD2) & M_RX_RSVD2)
38371 
38372 #define S_RX_RSVD3    8
38373 #define M_RX_RSVD3    0xfU
38374 #define V_RX_RSVD3(x) ((x) << S_RX_RSVD3)
38375 #define G_RX_RSVD3(x) (((x) >> S_RX_RSVD3) & M_RX_RSVD3)
38376 
38377 #define S_RX_OUT_SOP_CNT1    4
38378 #define M_RX_OUT_SOP_CNT1    0xfU
38379 #define V_RX_OUT_SOP_CNT1(x) ((x) << S_RX_OUT_SOP_CNT1)
38380 #define G_RX_OUT_SOP_CNT1(x) (((x) >> S_RX_OUT_SOP_CNT1) & M_RX_OUT_SOP_CNT1)
38381 
38382 #define S_RX_OUT_SOP_CNT0    0
38383 #define M_RX_OUT_SOP_CNT0    0xfU
38384 #define V_RX_OUT_SOP_CNT0(x) ((x) << S_RX_OUT_SOP_CNT0)
38385 #define G_RX_OUT_SOP_CNT0(x) (((x) >> S_RX_OUT_SOP_CNT0) & M_RX_OUT_SOP_CNT0)
38386 
38387 #define A_PM_RX_DBG_STAT10 0x1002b
38388 
38389 #define S_RX_CH_DEFICIT_BLOWED    24
38390 #define V_RX_CH_DEFICIT_BLOWED(x) ((x) << S_RX_CH_DEFICIT_BLOWED)
38391 #define F_RX_CH_DEFICIT_BLOWED    V_RX_CH_DEFICIT_BLOWED(1U)
38392 
38393 #define S_RX_CH1_DEFICIT    12
38394 #define M_RX_CH1_DEFICIT    0xfffU
38395 #define V_RX_CH1_DEFICIT(x) ((x) << S_RX_CH1_DEFICIT)
38396 #define G_RX_CH1_DEFICIT(x) (((x) >> S_RX_CH1_DEFICIT) & M_RX_CH1_DEFICIT)
38397 
38398 #define S_RX_CH0_DEFICIT    0
38399 #define M_RX_CH0_DEFICIT    0xfffU
38400 #define V_RX_CH0_DEFICIT(x) ((x) << S_RX_CH0_DEFICIT)
38401 #define G_RX_CH0_DEFICIT(x) (((x) >> S_RX_CH0_DEFICIT) & M_RX_CH0_DEFICIT)
38402 
38403 #define A_PM_RX_DBG_STAT11 0x1002c
38404 
38405 #define S_RX_BUNDLE_LEN_SRDY    30
38406 #define M_RX_BUNDLE_LEN_SRDY    0x3U
38407 #define V_RX_BUNDLE_LEN_SRDY(x) ((x) << S_RX_BUNDLE_LEN_SRDY)
38408 #define G_RX_BUNDLE_LEN_SRDY(x) (((x) >> S_RX_BUNDLE_LEN_SRDY) & M_RX_BUNDLE_LEN_SRDY)
38409 
38410 #define S_RX_RSVD11_1    28
38411 #define M_RX_RSVD11_1    0x3U
38412 #define V_RX_RSVD11_1(x) ((x) << S_RX_RSVD11_1)
38413 #define G_RX_RSVD11_1(x) (((x) >> S_RX_RSVD11_1) & M_RX_RSVD11_1)
38414 
38415 #define S_RX_BUNDLE_LEN1    16
38416 #define M_RX_BUNDLE_LEN1    0xfffU
38417 #define V_RX_BUNDLE_LEN1(x) ((x) << S_RX_BUNDLE_LEN1)
38418 #define G_RX_BUNDLE_LEN1(x) (((x) >> S_RX_BUNDLE_LEN1) & M_RX_BUNDLE_LEN1)
38419 
38420 #define S_RX_RSVD11    12
38421 #define M_RX_RSVD11    0xfU
38422 #define V_RX_RSVD11(x) ((x) << S_RX_RSVD11)
38423 #define G_RX_RSVD11(x) (((x) >> S_RX_RSVD11) & M_RX_RSVD11)
38424 
38425 #define S_RX_BUNDLE_LEN0    0
38426 #define M_RX_BUNDLE_LEN0    0xfffU
38427 #define V_RX_BUNDLE_LEN0(x) ((x) << S_RX_BUNDLE_LEN0)
38428 #define G_RX_BUNDLE_LEN0(x) (((x) >> S_RX_BUNDLE_LEN0) & M_RX_BUNDLE_LEN0)
38429 
38430 #define A_PM_RX_INT_CAUSE_MASK_HALT_2 0x10049
38431 #define A_PM_RX_INT_ENABLE_2 0x10060
38432 
38433 #define S_CACHE_SRAM_ODD_CERR    12
38434 #define V_CACHE_SRAM_ODD_CERR(x) ((x) << S_CACHE_SRAM_ODD_CERR)
38435 #define F_CACHE_SRAM_ODD_CERR    V_CACHE_SRAM_ODD_CERR(1U)
38436 
38437 #define S_CACHE_SRAM_EVEN_CERR    11
38438 #define V_CACHE_SRAM_EVEN_CERR(x) ((x) << S_CACHE_SRAM_EVEN_CERR)
38439 #define F_CACHE_SRAM_EVEN_CERR    V_CACHE_SRAM_EVEN_CERR(1U)
38440 
38441 #define S_CACHE_LRU_LEFT_CERR    10
38442 #define V_CACHE_LRU_LEFT_CERR(x) ((x) << S_CACHE_LRU_LEFT_CERR)
38443 #define F_CACHE_LRU_LEFT_CERR    V_CACHE_LRU_LEFT_CERR(1U)
38444 
38445 #define S_CACHE_LRU_RIGHT_CERR    9
38446 #define V_CACHE_LRU_RIGHT_CERR(x) ((x) << S_CACHE_LRU_RIGHT_CERR)
38447 #define F_CACHE_LRU_RIGHT_CERR    V_CACHE_LRU_RIGHT_CERR(1U)
38448 
38449 #define S_CACHE_ISLAND_CERR    8
38450 #define V_CACHE_ISLAND_CERR(x) ((x) << S_CACHE_ISLAND_CERR)
38451 #define F_CACHE_ISLAND_CERR    V_CACHE_ISLAND_CERR(1U)
38452 
38453 #define S_OCSPI_CERR    7
38454 #define V_OCSPI_CERR(x) ((x) << S_OCSPI_CERR)
38455 #define F_OCSPI_CERR    V_OCSPI_CERR(1U)
38456 
38457 #define S_IESPI_CERR    6
38458 #define V_IESPI_CERR(x) ((x) << S_IESPI_CERR)
38459 #define F_IESPI_CERR    V_IESPI_CERR(1U)
38460 
38461 #define S_OCSPI2_RX_FRAMING_ERROR    5
38462 #define V_OCSPI2_RX_FRAMING_ERROR(x) ((x) << S_OCSPI2_RX_FRAMING_ERROR)
38463 #define F_OCSPI2_RX_FRAMING_ERROR    V_OCSPI2_RX_FRAMING_ERROR(1U)
38464 
38465 #define S_OCSPI3_RX_FRAMING_ERROR    4
38466 #define V_OCSPI3_RX_FRAMING_ERROR(x) ((x) << S_OCSPI3_RX_FRAMING_ERROR)
38467 #define F_OCSPI3_RX_FRAMING_ERROR    V_OCSPI3_RX_FRAMING_ERROR(1U)
38468 
38469 #define S_OCSPI2_TX_FRAMING_ERROR    3
38470 #define V_OCSPI2_TX_FRAMING_ERROR(x) ((x) << S_OCSPI2_TX_FRAMING_ERROR)
38471 #define F_OCSPI2_TX_FRAMING_ERROR    V_OCSPI2_TX_FRAMING_ERROR(1U)
38472 
38473 #define S_OCSPI3_TX_FRAMING_ERROR    2
38474 #define V_OCSPI3_TX_FRAMING_ERROR(x) ((x) << S_OCSPI3_TX_FRAMING_ERROR)
38475 #define F_OCSPI3_TX_FRAMING_ERROR    V_OCSPI3_TX_FRAMING_ERROR(1U)
38476 
38477 #define S_OCSPI2_OFIFO2X_TX_FRAMING_ERROR    1
38478 #define V_OCSPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI2_OFIFO2X_TX_FRAMING_ERROR)
38479 #define F_OCSPI2_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI2_OFIFO2X_TX_FRAMING_ERROR(1U)
38480 
38481 #define S_OCSPI3_OFIFO2X_TX_FRAMING_ERROR    0
38482 #define V_OCSPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI3_OFIFO2X_TX_FRAMING_ERROR)
38483 #define F_OCSPI3_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI3_OFIFO2X_TX_FRAMING_ERROR(1U)
38484 
38485 #define A_PM_RX_INT_CAUSE_2 0x10061
38486 #define A_PM_RX_PERR_ENABLE 0x10062
38487 
38488 #define S_T7_SDC_ERR    31
38489 #define V_T7_SDC_ERR(x) ((x) << S_T7_SDC_ERR)
38490 #define F_T7_SDC_ERR    V_T7_SDC_ERR(1U)
38491 
38492 #define S_T7_MA_INTF_SDC_ERR    30
38493 #define V_T7_MA_INTF_SDC_ERR(x) ((x) << S_T7_MA_INTF_SDC_ERR)
38494 #define F_T7_MA_INTF_SDC_ERR    V_T7_MA_INTF_SDC_ERR(1U)
38495 
38496 #define S_E_PCMD_PERR    21
38497 #define V_E_PCMD_PERR(x) ((x) << S_E_PCMD_PERR)
38498 #define F_E_PCMD_PERR    V_E_PCMD_PERR(1U)
38499 
38500 #define S_CACHE_RSP_DFIFO_PERR    20
38501 #define V_CACHE_RSP_DFIFO_PERR(x) ((x) << S_CACHE_RSP_DFIFO_PERR)
38502 #define F_CACHE_RSP_DFIFO_PERR    V_CACHE_RSP_DFIFO_PERR(1U)
38503 
38504 #define S_CACHE_SRAM_ODD_PERR    19
38505 #define V_CACHE_SRAM_ODD_PERR(x) ((x) << S_CACHE_SRAM_ODD_PERR)
38506 #define F_CACHE_SRAM_ODD_PERR    V_CACHE_SRAM_ODD_PERR(1U)
38507 
38508 #define S_CACHE_SRAM_EVEN_PERR    18
38509 #define V_CACHE_SRAM_EVEN_PERR(x) ((x) << S_CACHE_SRAM_EVEN_PERR)
38510 #define F_CACHE_SRAM_EVEN_PERR    V_CACHE_SRAM_EVEN_PERR(1U)
38511 
38512 #define S_CACHE_RSVD_PERR    17
38513 #define V_CACHE_RSVD_PERR(x) ((x) << S_CACHE_RSVD_PERR)
38514 #define F_CACHE_RSVD_PERR    V_CACHE_RSVD_PERR(1U)
38515 
38516 #define S_CACHE_LRU_LEFT_PERR    16
38517 #define V_CACHE_LRU_LEFT_PERR(x) ((x) << S_CACHE_LRU_LEFT_PERR)
38518 #define F_CACHE_LRU_LEFT_PERR    V_CACHE_LRU_LEFT_PERR(1U)
38519 
38520 #define S_CACHE_LRU_RIGHT_PERR    15
38521 #define V_CACHE_LRU_RIGHT_PERR(x) ((x) << S_CACHE_LRU_RIGHT_PERR)
38522 #define F_CACHE_LRU_RIGHT_PERR    V_CACHE_LRU_RIGHT_PERR(1U)
38523 
38524 #define S_CACHE_RSP_CMD_PERR    14
38525 #define V_CACHE_RSP_CMD_PERR(x) ((x) << S_CACHE_RSP_CMD_PERR)
38526 #define F_CACHE_RSP_CMD_PERR    V_CACHE_RSP_CMD_PERR(1U)
38527 
38528 #define S_CACHE_SRAM_CMD_PERR    13
38529 #define V_CACHE_SRAM_CMD_PERR(x) ((x) << S_CACHE_SRAM_CMD_PERR)
38530 #define F_CACHE_SRAM_CMD_PERR    V_CACHE_SRAM_CMD_PERR(1U)
38531 
38532 #define S_CACHE_MA_CMD_PERR    12
38533 #define V_CACHE_MA_CMD_PERR(x) ((x) << S_CACHE_MA_CMD_PERR)
38534 #define F_CACHE_MA_CMD_PERR    V_CACHE_MA_CMD_PERR(1U)
38535 
38536 #define S_CACHE_TCAM_PERR    11
38537 #define V_CACHE_TCAM_PERR(x) ((x) << S_CACHE_TCAM_PERR)
38538 #define F_CACHE_TCAM_PERR    V_CACHE_TCAM_PERR(1U)
38539 
38540 #define S_CACHE_ISLAND_PERR    10
38541 #define V_CACHE_ISLAND_PERR(x) ((x) << S_CACHE_ISLAND_PERR)
38542 #define F_CACHE_ISLAND_PERR    V_CACHE_ISLAND_PERR(1U)
38543 
38544 #define S_MC_WCNT_FIFO_PERR    9
38545 #define V_MC_WCNT_FIFO_PERR(x) ((x) << S_MC_WCNT_FIFO_PERR)
38546 #define F_MC_WCNT_FIFO_PERR    V_MC_WCNT_FIFO_PERR(1U)
38547 
38548 #define S_MC_WDATA_FIFO_PERR    8
38549 #define V_MC_WDATA_FIFO_PERR(x) ((x) << S_MC_WDATA_FIFO_PERR)
38550 #define F_MC_WDATA_FIFO_PERR    V_MC_WDATA_FIFO_PERR(1U)
38551 
38552 #define S_MC_RCNT_FIFO_PERR    7
38553 #define V_MC_RCNT_FIFO_PERR(x) ((x) << S_MC_RCNT_FIFO_PERR)
38554 #define F_MC_RCNT_FIFO_PERR    V_MC_RCNT_FIFO_PERR(1U)
38555 
38556 #define S_MC_RDATA_FIFO_PERR    6
38557 #define V_MC_RDATA_FIFO_PERR(x) ((x) << S_MC_RDATA_FIFO_PERR)
38558 #define F_MC_RDATA_FIFO_PERR    V_MC_RDATA_FIFO_PERR(1U)
38559 
38560 #define S_TOKEN_FIFO_PERR    5
38561 #define V_TOKEN_FIFO_PERR(x) ((x) << S_TOKEN_FIFO_PERR)
38562 #define F_TOKEN_FIFO_PERR    V_TOKEN_FIFO_PERR(1U)
38563 
38564 #define S_T7_BUNDLE_LEN_PARERR    4
38565 #define V_T7_BUNDLE_LEN_PARERR(x) ((x) << S_T7_BUNDLE_LEN_PARERR)
38566 #define F_T7_BUNDLE_LEN_PARERR    V_T7_BUNDLE_LEN_PARERR(1U)
38567 
38568 #define A_PM_RX_PERR_CAUSE 0x10063
38569 #define A_PM_RX_EXT_CFIFO_CONFIG0 0x10070
38570 
38571 #define S_CH1_PTR_MAX    17
38572 #define M_CH1_PTR_MAX    0x7fffU
38573 #define V_CH1_PTR_MAX(x) ((x) << S_CH1_PTR_MAX)
38574 #define G_CH1_PTR_MAX(x) (((x) >> S_CH1_PTR_MAX) & M_CH1_PTR_MAX)
38575 
38576 #define S_CH0_PTR_MAX    1
38577 #define M_CH0_PTR_MAX    0x7fffU
38578 #define V_CH0_PTR_MAX(x) ((x) << S_CH0_PTR_MAX)
38579 #define G_CH0_PTR_MAX(x) (((x) >> S_CH0_PTR_MAX) & M_CH0_PTR_MAX)
38580 
38581 #define S_STROBE    0
38582 #define V_STROBE(x) ((x) << S_STROBE)
38583 #define F_STROBE    V_STROBE(1U)
38584 
38585 #define A_PM_RX_EXT_CFIFO_CONFIG1 0x10071
38586 
38587 #define S_CH2_PTR_MAX    1
38588 #define M_CH2_PTR_MAX    0x7fffU
38589 #define V_CH2_PTR_MAX(x) ((x) << S_CH2_PTR_MAX)
38590 #define G_CH2_PTR_MAX(x) (((x) >> S_CH2_PTR_MAX) & M_CH2_PTR_MAX)
38591 
38592 #define A_PM_RX_EXT_EFIFO_CONFIG0 0x10072
38593 #define A_PM_RX_EXT_EFIFO_CONFIG1 0x10073
38594 #define A_T7_PM_RX_CH0_OSPI_DEFICIT_THRSHLD 0x10074
38595 #define A_T7_PM_RX_CH1_OSPI_DEFICIT_THRSHLD 0x10075
38596 #define A_PM_RX_CH2_OSPI_DEFICIT_THRSHLD 0x10076
38597 #define A_PM_RX_CH3_OSPI_DEFICIT_THRSHLD 0x10077
38598 #define A_T7_PM_RX_FEATURE_EN 0x10078
38599 #define A_PM_RX_TCAM_BIST_CTRL 0x10080
38600 #define A_PM_RX_TCAM_BIST_CB_PASS 0x10081
38601 #define A_PM_RX_TCAM_BIST_CB_BUSY 0x10082
38602 
38603 /* registers for module PM_TX */
38604 #define PM_TX_BASE_ADDR 0x8fe0
38605 
38606 #define A_PM_TX_CFG 0x8fe0
38607 
38608 #define S_CH3_OUTPUT    17
38609 #define M_CH3_OUTPUT    0x1fU
38610 #define V_CH3_OUTPUT(x) ((x) << S_CH3_OUTPUT)
38611 #define G_CH3_OUTPUT(x) (((x) >> S_CH3_OUTPUT) & M_CH3_OUTPUT)
38612 
38613 #define A_PM_TX_MODE 0x8fe4
38614 
38615 #define S_CONG_THRESH3    25
38616 #define M_CONG_THRESH3    0x7fU
38617 #define V_CONG_THRESH3(x) ((x) << S_CONG_THRESH3)
38618 #define G_CONG_THRESH3(x) (((x) >> S_CONG_THRESH3) & M_CONG_THRESH3)
38619 
38620 #define S_CONG_THRESH2    18
38621 #define M_CONG_THRESH2    0x7fU
38622 #define V_CONG_THRESH2(x) ((x) << S_CONG_THRESH2)
38623 #define G_CONG_THRESH2(x) (((x) >> S_CONG_THRESH2) & M_CONG_THRESH2)
38624 
38625 #define S_CONG_THRESH1    11
38626 #define M_CONG_THRESH1    0x7fU
38627 #define V_CONG_THRESH1(x) ((x) << S_CONG_THRESH1)
38628 #define G_CONG_THRESH1(x) (((x) >> S_CONG_THRESH1) & M_CONG_THRESH1)
38629 
38630 #define S_CONG_THRESH0    4
38631 #define M_CONG_THRESH0    0x7fU
38632 #define V_CONG_THRESH0(x) ((x) << S_CONG_THRESH0)
38633 #define G_CONG_THRESH0(x) (((x) >> S_CONG_THRESH0) & M_CONG_THRESH0)
38634 
38635 #define S_TX_USE_BUNDLE_LEN    3
38636 #define V_TX_USE_BUNDLE_LEN(x) ((x) << S_TX_USE_BUNDLE_LEN)
38637 #define F_TX_USE_BUNDLE_LEN    V_TX_USE_BUNDLE_LEN(1U)
38638 
38639 #define S_STAT_CHANNEL    1
38640 #define M_STAT_CHANNEL    0x3U
38641 #define V_STAT_CHANNEL(x) ((x) << S_STAT_CHANNEL)
38642 #define G_STAT_CHANNEL(x) (((x) >> S_STAT_CHANNEL) & M_STAT_CHANNEL)
38643 
38644 #define A_PM_TX_STAT_CONFIG 0x8fe8
38645 #define A_PM_TX_STAT_COUNT 0x8fec
38646 #define A_PM_TX_STAT_LSB 0x8ff0
38647 #define A_PM_TX_DBG_CTRL 0x8ff0
38648 
38649 #define S_OSPIWRBUSY    21
38650 #define M_OSPIWRBUSY    0xfU
38651 #define V_OSPIWRBUSY(x) ((x) << S_OSPIWRBUSY)
38652 #define G_OSPIWRBUSY(x) (((x) >> S_OSPIWRBUSY) & M_OSPIWRBUSY)
38653 
38654 #define A_PM_TX_STAT_MSB 0x8ff4
38655 #define A_PM_TX_DBG_DATA 0x8ff4
38656 #define A_PM_TX_INT_ENABLE 0x8ff8
38657 
38658 #define S_PCMD_LEN_OVFL0    31
38659 #define V_PCMD_LEN_OVFL0(x) ((x) << S_PCMD_LEN_OVFL0)
38660 #define F_PCMD_LEN_OVFL0    V_PCMD_LEN_OVFL0(1U)
38661 
38662 #define S_PCMD_LEN_OVFL1    30
38663 #define V_PCMD_LEN_OVFL1(x) ((x) << S_PCMD_LEN_OVFL1)
38664 #define F_PCMD_LEN_OVFL1    V_PCMD_LEN_OVFL1(1U)
38665 
38666 #define S_PCMD_LEN_OVFL2    29
38667 #define V_PCMD_LEN_OVFL2(x) ((x) << S_PCMD_LEN_OVFL2)
38668 #define F_PCMD_LEN_OVFL2    V_PCMD_LEN_OVFL2(1U)
38669 
38670 #define S_ZERO_C_CMD_ERRO    28
38671 #define V_ZERO_C_CMD_ERRO(x) ((x) << S_ZERO_C_CMD_ERRO)
38672 #define F_ZERO_C_CMD_ERRO    V_ZERO_C_CMD_ERRO(1U)
38673 
38674 #define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR    27
38675 #define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
38676 #define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR    V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
38677 
38678 #define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR    26
38679 #define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
38680 #define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR    V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
38681 
38682 #define S_ICSPI2_FIFO2X_RX_FRAMING_ERROR    25
38683 #define V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_FIFO2X_RX_FRAMING_ERROR)
38684 #define F_ICSPI2_FIFO2X_RX_FRAMING_ERROR    V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(1U)
38685 
38686 #define S_ICSPI3_FIFO2X_RX_FRAMING_ERROR    24
38687 #define V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_FIFO2X_RX_FRAMING_ERROR)
38688 #define F_ICSPI3_FIFO2X_RX_FRAMING_ERROR    V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(1U)
38689 
38690 #define S_ICSPI0_RX_FRAMING_ERROR    23
38691 #define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
38692 #define F_ICSPI0_RX_FRAMING_ERROR    V_ICSPI0_RX_FRAMING_ERROR(1U)
38693 
38694 #define S_ICSPI1_RX_FRAMING_ERROR    22
38695 #define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
38696 #define F_ICSPI1_RX_FRAMING_ERROR    V_ICSPI1_RX_FRAMING_ERROR(1U)
38697 
38698 #define S_ICSPI2_RX_FRAMING_ERROR    21
38699 #define V_ICSPI2_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_RX_FRAMING_ERROR)
38700 #define F_ICSPI2_RX_FRAMING_ERROR    V_ICSPI2_RX_FRAMING_ERROR(1U)
38701 
38702 #define S_ICSPI3_RX_FRAMING_ERROR    20
38703 #define V_ICSPI3_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_RX_FRAMING_ERROR)
38704 #define F_ICSPI3_RX_FRAMING_ERROR    V_ICSPI3_RX_FRAMING_ERROR(1U)
38705 
38706 #define S_ICSPI0_TX_FRAMING_ERROR    19
38707 #define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
38708 #define F_ICSPI0_TX_FRAMING_ERROR    V_ICSPI0_TX_FRAMING_ERROR(1U)
38709 
38710 #define S_ICSPI1_TX_FRAMING_ERROR    18
38711 #define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
38712 #define F_ICSPI1_TX_FRAMING_ERROR    V_ICSPI1_TX_FRAMING_ERROR(1U)
38713 
38714 #define S_ICSPI2_TX_FRAMING_ERROR    17
38715 #define V_ICSPI2_TX_FRAMING_ERROR(x) ((x) << S_ICSPI2_TX_FRAMING_ERROR)
38716 #define F_ICSPI2_TX_FRAMING_ERROR    V_ICSPI2_TX_FRAMING_ERROR(1U)
38717 
38718 #define S_ICSPI3_TX_FRAMING_ERROR    16
38719 #define V_ICSPI3_TX_FRAMING_ERROR(x) ((x) << S_ICSPI3_TX_FRAMING_ERROR)
38720 #define F_ICSPI3_TX_FRAMING_ERROR    V_ICSPI3_TX_FRAMING_ERROR(1U)
38721 
38722 #define S_OESPI0_RX_FRAMING_ERROR    15
38723 #define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
38724 #define F_OESPI0_RX_FRAMING_ERROR    V_OESPI0_RX_FRAMING_ERROR(1U)
38725 
38726 #define S_OESPI1_RX_FRAMING_ERROR    14
38727 #define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
38728 #define F_OESPI1_RX_FRAMING_ERROR    V_OESPI1_RX_FRAMING_ERROR(1U)
38729 
38730 #define S_OESPI2_RX_FRAMING_ERROR    13
38731 #define V_OESPI2_RX_FRAMING_ERROR(x) ((x) << S_OESPI2_RX_FRAMING_ERROR)
38732 #define F_OESPI2_RX_FRAMING_ERROR    V_OESPI2_RX_FRAMING_ERROR(1U)
38733 
38734 #define S_OESPI3_RX_FRAMING_ERROR    12
38735 #define V_OESPI3_RX_FRAMING_ERROR(x) ((x) << S_OESPI3_RX_FRAMING_ERROR)
38736 #define F_OESPI3_RX_FRAMING_ERROR    V_OESPI3_RX_FRAMING_ERROR(1U)
38737 
38738 #define S_OESPI0_TX_FRAMING_ERROR    11
38739 #define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
38740 #define F_OESPI0_TX_FRAMING_ERROR    V_OESPI0_TX_FRAMING_ERROR(1U)
38741 
38742 #define S_OESPI1_TX_FRAMING_ERROR    10
38743 #define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
38744 #define F_OESPI1_TX_FRAMING_ERROR    V_OESPI1_TX_FRAMING_ERROR(1U)
38745 
38746 #define S_OESPI2_TX_FRAMING_ERROR    9
38747 #define V_OESPI2_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_TX_FRAMING_ERROR)
38748 #define F_OESPI2_TX_FRAMING_ERROR    V_OESPI2_TX_FRAMING_ERROR(1U)
38749 
38750 #define S_OESPI3_TX_FRAMING_ERROR    8
38751 #define V_OESPI3_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_TX_FRAMING_ERROR)
38752 #define F_OESPI3_TX_FRAMING_ERROR    V_OESPI3_TX_FRAMING_ERROR(1U)
38753 
38754 #define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR    7
38755 #define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
38756 #define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR    V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
38757 
38758 #define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR    6
38759 #define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
38760 #define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR    V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
38761 
38762 #define S_OESPI2_OFIFO2X_TX_FRAMING_ERROR    5
38763 #define V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_OFIFO2X_TX_FRAMING_ERROR)
38764 #define F_OESPI2_OFIFO2X_TX_FRAMING_ERROR    V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(1U)
38765 
38766 #define S_OESPI3_OFIFO2X_TX_FRAMING_ERROR    4
38767 #define V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_OFIFO2X_TX_FRAMING_ERROR)
38768 #define F_OESPI3_OFIFO2X_TX_FRAMING_ERROR    V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(1U)
38769 
38770 #define S_OESPI_PAR_ERROR    3
38771 #define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
38772 #define F_OESPI_PAR_ERROR    V_OESPI_PAR_ERROR(1U)
38773 
38774 #define S_ICSPI_PAR_ERROR    1
38775 #define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
38776 #define F_ICSPI_PAR_ERROR    V_ICSPI_PAR_ERROR(1U)
38777 
38778 #define S_C_PCMD_PAR_ERROR    0
38779 #define V_C_PCMD_PAR_ERROR(x) ((x) << S_C_PCMD_PAR_ERROR)
38780 #define F_C_PCMD_PAR_ERROR    V_C_PCMD_PAR_ERROR(1U)
38781 
38782 #define S_T7_ZERO_C_CMD_ERROR    30
38783 #define V_T7_ZERO_C_CMD_ERROR(x) ((x) << S_T7_ZERO_C_CMD_ERROR)
38784 #define F_T7_ZERO_C_CMD_ERROR    V_T7_ZERO_C_CMD_ERROR(1U)
38785 
38786 #define S_OESPI_COR_ERR    29
38787 #define V_OESPI_COR_ERR(x) ((x) << S_OESPI_COR_ERR)
38788 #define F_OESPI_COR_ERR    V_OESPI_COR_ERR(1U)
38789 
38790 #define S_ICSPI_COR_ERR    28
38791 #define V_ICSPI_COR_ERR(x) ((x) << S_ICSPI_COR_ERR)
38792 #define F_ICSPI_COR_ERR    V_ICSPI_COR_ERR(1U)
38793 
38794 #define S_ICSPI_OVFL    24
38795 #define V_ICSPI_OVFL(x) ((x) << S_ICSPI_OVFL)
38796 #define F_ICSPI_OVFL    V_ICSPI_OVFL(1U)
38797 
38798 #define S_PCMD_LEN_OVFL3    23
38799 #define V_PCMD_LEN_OVFL3(x) ((x) << S_PCMD_LEN_OVFL3)
38800 #define F_PCMD_LEN_OVFL3    V_PCMD_LEN_OVFL3(1U)
38801 
38802 #define S_T7_PCMD_LEN_OVFL2    22
38803 #define V_T7_PCMD_LEN_OVFL2(x) ((x) << S_T7_PCMD_LEN_OVFL2)
38804 #define F_T7_PCMD_LEN_OVFL2    V_T7_PCMD_LEN_OVFL2(1U)
38805 
38806 #define S_T7_PCMD_LEN_OVFL1    21
38807 #define V_T7_PCMD_LEN_OVFL1(x) ((x) << S_T7_PCMD_LEN_OVFL1)
38808 #define F_T7_PCMD_LEN_OVFL1    V_T7_PCMD_LEN_OVFL1(1U)
38809 
38810 #define S_T7_PCMD_LEN_OVFL0    20
38811 #define V_T7_PCMD_LEN_OVFL0(x) ((x) << S_T7_PCMD_LEN_OVFL0)
38812 #define F_T7_PCMD_LEN_OVFL0    V_T7_PCMD_LEN_OVFL0(1U)
38813 
38814 #define S_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR    19
38815 #define V_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
38816 #define F_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR    V_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
38817 
38818 #define S_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR    18
38819 #define V_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
38820 #define F_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR    V_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
38821 
38822 #define S_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR    17
38823 #define V_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR)
38824 #define F_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR    V_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR(1U)
38825 
38826 #define S_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR    16
38827 #define V_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR)
38828 #define F_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR    V_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR(1U)
38829 
38830 #define S_T7_ICSPI0_TX_FRAMING_ERROR    15
38831 #define V_T7_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI0_TX_FRAMING_ERROR)
38832 #define F_T7_ICSPI0_TX_FRAMING_ERROR    V_T7_ICSPI0_TX_FRAMING_ERROR(1U)
38833 
38834 #define S_T7_ICSPI1_TX_FRAMING_ERROR    14
38835 #define V_T7_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI1_TX_FRAMING_ERROR)
38836 #define F_T7_ICSPI1_TX_FRAMING_ERROR    V_T7_ICSPI1_TX_FRAMING_ERROR(1U)
38837 
38838 #define S_T7_ICSPI2_TX_FRAMING_ERROR    13
38839 #define V_T7_ICSPI2_TX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI2_TX_FRAMING_ERROR)
38840 #define F_T7_ICSPI2_TX_FRAMING_ERROR    V_T7_ICSPI2_TX_FRAMING_ERROR(1U)
38841 
38842 #define S_T7_ICSPI3_TX_FRAMING_ERROR    12
38843 #define V_T7_ICSPI3_TX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI3_TX_FRAMING_ERROR)
38844 #define F_T7_ICSPI3_TX_FRAMING_ERROR    V_T7_ICSPI3_TX_FRAMING_ERROR(1U)
38845 
38846 #define S_T7_OESPI0_RX_FRAMING_ERROR    11
38847 #define V_T7_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_T7_OESPI0_RX_FRAMING_ERROR)
38848 #define F_T7_OESPI0_RX_FRAMING_ERROR    V_T7_OESPI0_RX_FRAMING_ERROR(1U)
38849 
38850 #define S_T7_OESPI1_RX_FRAMING_ERROR    10
38851 #define V_T7_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_T7_OESPI1_RX_FRAMING_ERROR)
38852 #define F_T7_OESPI1_RX_FRAMING_ERROR    V_T7_OESPI1_RX_FRAMING_ERROR(1U)
38853 
38854 #define S_T7_OESPI2_RX_FRAMING_ERROR    9
38855 #define V_T7_OESPI2_RX_FRAMING_ERROR(x) ((x) << S_T7_OESPI2_RX_FRAMING_ERROR)
38856 #define F_T7_OESPI2_RX_FRAMING_ERROR    V_T7_OESPI2_RX_FRAMING_ERROR(1U)
38857 
38858 #define S_T7_OESPI3_RX_FRAMING_ERROR    8
38859 #define V_T7_OESPI3_RX_FRAMING_ERROR(x) ((x) << S_T7_OESPI3_RX_FRAMING_ERROR)
38860 #define F_T7_OESPI3_RX_FRAMING_ERROR    V_T7_OESPI3_RX_FRAMING_ERROR(1U)
38861 
38862 #define S_T7_OESPI0_TX_FRAMING_ERROR    7
38863 #define V_T7_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI0_TX_FRAMING_ERROR)
38864 #define F_T7_OESPI0_TX_FRAMING_ERROR    V_T7_OESPI0_TX_FRAMING_ERROR(1U)
38865 
38866 #define S_T7_OESPI1_TX_FRAMING_ERROR    6
38867 #define V_T7_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI1_TX_FRAMING_ERROR)
38868 #define F_T7_OESPI1_TX_FRAMING_ERROR    V_T7_OESPI1_TX_FRAMING_ERROR(1U)
38869 
38870 #define S_T7_OESPI2_TX_FRAMING_ERROR    5
38871 #define V_T7_OESPI2_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI2_TX_FRAMING_ERROR)
38872 #define F_T7_OESPI2_TX_FRAMING_ERROR    V_T7_OESPI2_TX_FRAMING_ERROR(1U)
38873 
38874 #define S_T7_OESPI3_TX_FRAMING_ERROR    4
38875 #define V_T7_OESPI3_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI3_TX_FRAMING_ERROR)
38876 #define F_T7_OESPI3_TX_FRAMING_ERROR    V_T7_OESPI3_TX_FRAMING_ERROR(1U)
38877 
38878 #define S_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR    3
38879 #define V_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
38880 #define F_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR    V_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
38881 
38882 #define S_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR    2
38883 #define V_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
38884 #define F_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR    V_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
38885 
38886 #define S_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR    1
38887 #define V_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR)
38888 #define F_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR    V_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR(1U)
38889 
38890 #define S_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR    0
38891 #define V_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR)
38892 #define F_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR    V_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR(1U)
38893 
38894 #define A_PM_TX_INT_CAUSE 0x8ffc
38895 
38896 #define S_ZERO_C_CMD_ERROR    28
38897 #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
38898 #define F_ZERO_C_CMD_ERROR    V_ZERO_C_CMD_ERROR(1U)
38899 
38900 #define S_OSPI_OR_BUNDLE_LEN_PAR_ERR    3
38901 #define V_OSPI_OR_BUNDLE_LEN_PAR_ERR(x) ((x) << S_OSPI_OR_BUNDLE_LEN_PAR_ERR)
38902 #define F_OSPI_OR_BUNDLE_LEN_PAR_ERR    V_OSPI_OR_BUNDLE_LEN_PAR_ERR(1U)
38903 
38904 #define A_PM_TX_ISPI_DBG_4B_DATA0 0x10000
38905 #define A_T7_PM_TX_DBG_STAT_MSB 0x10000
38906 #define A_PM_TX_ISPI_DBG_4B_DATA1 0x10001
38907 #define A_T7_PM_TX_DBG_STAT_LSB 0x10001
38908 #define A_PM_TX_ISPI_DBG_4B_DATA2 0x10002
38909 #define A_T7_PM_TX_DBG_RSVD_FLIT_CNT 0x10002
38910 #define A_PM_TX_ISPI_DBG_4B_DATA3 0x10003
38911 #define A_T7_PM_TX_SDC_EN 0x10003
38912 #define A_PM_TX_ISPI_DBG_4B_DATA4 0x10004
38913 #define A_T7_PM_TX_INOUT_FIFO_DBG_CHNL_SEL 0x10004
38914 #define A_PM_TX_ISPI_DBG_4B_DATA5 0x10005
38915 #define A_T7_PM_TX_INOUT_FIFO_DBG_WR 0x10005
38916 #define A_PM_TX_ISPI_DBG_4B_DATA6 0x10006
38917 #define A_T7_PM_TX_INPUT_FIFO_STR_FWD_EN 0x10006
38918 #define A_PM_TX_ISPI_DBG_4B_DATA7 0x10007
38919 #define A_T7_PM_TX_FEATURE_EN 0x10007
38920 
38921 #define S_IN_AFULL_TH    5
38922 #define M_IN_AFULL_TH    0x3U
38923 #define V_IN_AFULL_TH(x) ((x) << S_IN_AFULL_TH)
38924 #define G_IN_AFULL_TH(x) (((x) >> S_IN_AFULL_TH) & M_IN_AFULL_TH)
38925 
38926 #define S_PIO_FROM_CH_EN    4
38927 #define V_PIO_FROM_CH_EN(x) ((x) << S_PIO_FROM_CH_EN)
38928 #define F_PIO_FROM_CH_EN    V_PIO_FROM_CH_EN(1U)
38929 
38930 #define A_PM_TX_ISPI_DBG_4B_DATA8 0x10008
38931 #define A_T7_PM_TX_T5_PM_TX_INT_ENABLE 0x10008
38932 #define A_PM_TX_OSPI_DBG_4B_DATA0 0x10009
38933 #define A_T7_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0 0x10009
38934 #define A_PM_TX_OSPI_DBG_4B_DATA1 0x1000a
38935 #define A_T7_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1 0x1000a
38936 #define A_PM_TX_OSPI_DBG_4B_DATA2 0x1000b
38937 #define A_T7_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2 0x1000b
38938 #define A_PM_TX_OSPI_DBG_4B_DATA3 0x1000c
38939 #define A_T7_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3 0x1000c
38940 #define A_PM_TX_OSPI_DBG_4B_DATA4 0x1000d
38941 #define A_T7_PM_TX_CH0_OSPI_DEFICIT_THRSHLD 0x1000d
38942 #define A_PM_TX_OSPI_DBG_4B_DATA5 0x1000e
38943 #define A_T7_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x1000e
38944 #define A_PM_TX_OSPI_DBG_4B_DATA6 0x1000f
38945 #define A_T7_PM_TX_CH2_OSPI_DEFICIT_THRSHLD 0x1000f
38946 #define A_PM_TX_OSPI_DBG_4B_DATA7 0x10010
38947 #define A_T7_PM_TX_CH3_OSPI_DEFICIT_THRSHLD 0x10010
38948 #define A_PM_TX_OSPI_DBG_4B_DATA8 0x10011
38949 #define A_T7_PM_TX_INT_CAUSE_MASK_HALT 0x10011
38950 #define A_PM_TX_OSPI_DBG_4B_DATA9 0x10012
38951 #define A_PM_TX_OSPI_DBG_4B_DATA10 0x10013
38952 #define A_PM_TX_OSPI_DBG_4B_DATA11 0x10014
38953 #define A_PM_TX_OSPI_DBG_4B_DATA12 0x10015
38954 #define A_PM_TX_OSPI_DBG_4B_DATA13 0x10016
38955 #define A_PM_TX_OSPI_DBG_4B_DATA14 0x10017
38956 #define A_PM_TX_OSPI_DBG_4B_DATA15 0x10018
38957 #define A_PM_TX_OSPI_DBG_4B_DATA16 0x10019
38958 #define A_PM_TX_DBG_STAT_MSB 0x1001a
38959 #define A_PM_TX_DBG_STAT_LSB 0x1001b
38960 #define A_PM_TX_DBG_RSVD_FLIT_CNT 0x1001c
38961 #define A_PM_TX_SDC_EN 0x1001d
38962 #define A_PM_TX_INOUT_FIFO_DBG_CHNL_SEL 0x1001e
38963 #define A_PM_TX_INOUT_FIFO_DBG_WR 0x1001f
38964 #define A_PM_TX_INPUT_FIFO_STR_FWD_EN 0x10020
38965 #define A_PM_TX_FEATURE_EN 0x10021
38966 
38967 #define S_PIO_CH_DEFICIT_CTL_EN    2
38968 #define V_PIO_CH_DEFICIT_CTL_EN(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN)
38969 #define F_PIO_CH_DEFICIT_CTL_EN    V_PIO_CH_DEFICIT_CTL_EN(1U)
38970 
38971 #define S_PIO_WRR_BASED_PRFTCH_EN    1
38972 #define V_PIO_WRR_BASED_PRFTCH_EN(x) ((x) << S_PIO_WRR_BASED_PRFTCH_EN)
38973 #define F_PIO_WRR_BASED_PRFTCH_EN    V_PIO_WRR_BASED_PRFTCH_EN(1U)
38974 
38975 #define A_PM_TX_T5_PM_TX_INT_ENABLE 0x10022
38976 
38977 #define S_OSPI_OVERFLOW3    7
38978 #define V_OSPI_OVERFLOW3(x) ((x) << S_OSPI_OVERFLOW3)
38979 #define F_OSPI_OVERFLOW3    V_OSPI_OVERFLOW3(1U)
38980 
38981 #define S_OSPI_OVERFLOW2    6
38982 #define V_OSPI_OVERFLOW2(x) ((x) << S_OSPI_OVERFLOW2)
38983 #define F_OSPI_OVERFLOW2    V_OSPI_OVERFLOW2(1U)
38984 
38985 #define S_T5_OSPI_OVERFLOW1    5
38986 #define V_T5_OSPI_OVERFLOW1(x) ((x) << S_T5_OSPI_OVERFLOW1)
38987 #define F_T5_OSPI_OVERFLOW1    V_T5_OSPI_OVERFLOW1(1U)
38988 
38989 #define S_T5_OSPI_OVERFLOW0    4
38990 #define V_T5_OSPI_OVERFLOW0(x) ((x) << S_T5_OSPI_OVERFLOW0)
38991 #define F_T5_OSPI_OVERFLOW0    V_T5_OSPI_OVERFLOW0(1U)
38992 
38993 #define S_M_INTFPERREN    3
38994 #define V_M_INTFPERREN(x) ((x) << S_M_INTFPERREN)
38995 #define F_M_INTFPERREN    V_M_INTFPERREN(1U)
38996 
38997 #define S_BUNDLE_LEN_PARERR_EN    2
38998 #define V_BUNDLE_LEN_PARERR_EN(x) ((x) << S_BUNDLE_LEN_PARERR_EN)
38999 #define F_BUNDLE_LEN_PARERR_EN    V_BUNDLE_LEN_PARERR_EN(1U)
39000 
39001 #define S_BUNDLE_LEN_OVFL_EN    1
39002 #define V_BUNDLE_LEN_OVFL_EN(x) ((x) << S_BUNDLE_LEN_OVFL_EN)
39003 #define F_BUNDLE_LEN_OVFL_EN    V_BUNDLE_LEN_OVFL_EN(1U)
39004 
39005 #define S_SDC_ERR_EN    0
39006 #define V_SDC_ERR_EN(x) ((x) << S_SDC_ERR_EN)
39007 #define F_SDC_ERR_EN    V_SDC_ERR_EN(1U)
39008 
39009 #define S_OSPI_OVERFLOW3_T5    7
39010 #define V_OSPI_OVERFLOW3_T5(x) ((x) << S_OSPI_OVERFLOW3_T5)
39011 #define F_OSPI_OVERFLOW3_T5    V_OSPI_OVERFLOW3_T5(1U)
39012 
39013 #define S_OSPI_OVERFLOW2_T5    6
39014 #define V_OSPI_OVERFLOW2_T5(x) ((x) << S_OSPI_OVERFLOW2_T5)
39015 #define F_OSPI_OVERFLOW2_T5    V_OSPI_OVERFLOW2_T5(1U)
39016 
39017 #define S_OSPI_OVERFLOW1_T5    5
39018 #define V_OSPI_OVERFLOW1_T5(x) ((x) << S_OSPI_OVERFLOW1_T5)
39019 #define F_OSPI_OVERFLOW1_T5    V_OSPI_OVERFLOW1_T5(1U)
39020 
39021 #define S_OSPI_OVERFLOW0_T5    4
39022 #define V_OSPI_OVERFLOW0_T5(x) ((x) << S_OSPI_OVERFLOW0_T5)
39023 #define F_OSPI_OVERFLOW0_T5    V_OSPI_OVERFLOW0_T5(1U)
39024 
39025 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0 0x10023
39026 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1 0x10024
39027 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2 0x10025
39028 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3 0x10026
39029 #define A_PM_TX_CH0_OSPI_DEFICIT_THRSHLD 0x10027
39030 #define A_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x10028
39031 #define A_PM_TX_PERR_ENABLE 0x10028
39032 
39033 #define S_T7_1_OSPI_OVERFLOW3    23
39034 #define V_T7_1_OSPI_OVERFLOW3(x) ((x) << S_T7_1_OSPI_OVERFLOW3)
39035 #define F_T7_1_OSPI_OVERFLOW3    V_T7_1_OSPI_OVERFLOW3(1U)
39036 
39037 #define S_T7_1_OSPI_OVERFLOW2    22
39038 #define V_T7_1_OSPI_OVERFLOW2(x) ((x) << S_T7_1_OSPI_OVERFLOW2)
39039 #define F_T7_1_OSPI_OVERFLOW2    V_T7_1_OSPI_OVERFLOW2(1U)
39040 
39041 #define S_T7_1_OSPI_OVERFLOW1    21
39042 #define V_T7_1_OSPI_OVERFLOW1(x) ((x) << S_T7_1_OSPI_OVERFLOW1)
39043 #define F_T7_1_OSPI_OVERFLOW1    V_T7_1_OSPI_OVERFLOW1(1U)
39044 
39045 #define S_T7_1_OSPI_OVERFLOW0    20
39046 #define V_T7_1_OSPI_OVERFLOW0(x) ((x) << S_T7_1_OSPI_OVERFLOW0)
39047 #define F_T7_1_OSPI_OVERFLOW0    V_T7_1_OSPI_OVERFLOW0(1U)
39048 
39049 #define S_T7_BUNDLE_LEN_OVFL_EN    18
39050 #define V_T7_BUNDLE_LEN_OVFL_EN(x) ((x) << S_T7_BUNDLE_LEN_OVFL_EN)
39051 #define F_T7_BUNDLE_LEN_OVFL_EN    V_T7_BUNDLE_LEN_OVFL_EN(1U)
39052 
39053 #define S_T7_M_INTFPERREN    17
39054 #define V_T7_M_INTFPERREN(x) ((x) << S_T7_M_INTFPERREN)
39055 #define F_T7_M_INTFPERREN    V_T7_M_INTFPERREN(1U)
39056 
39057 #define S_T7_1_SDC_ERR    16
39058 #define V_T7_1_SDC_ERR(x) ((x) << S_T7_1_SDC_ERR)
39059 #define F_T7_1_SDC_ERR    V_T7_1_SDC_ERR(1U)
39060 
39061 #define S_TOKEN_PAR_ERROR    5
39062 #define V_TOKEN_PAR_ERROR(x) ((x) << S_TOKEN_PAR_ERROR)
39063 #define F_TOKEN_PAR_ERROR    V_TOKEN_PAR_ERROR(1U)
39064 
39065 #define S_BUNDLE_LEN_PAR_ERROR    4
39066 #define V_BUNDLE_LEN_PAR_ERROR(x) ((x) << S_BUNDLE_LEN_PAR_ERROR)
39067 #define F_BUNDLE_LEN_PAR_ERROR    V_BUNDLE_LEN_PAR_ERROR(1U)
39068 
39069 #define S_C_PCMD_TOKEN_PAR_ERROR    0
39070 #define V_C_PCMD_TOKEN_PAR_ERROR(x) ((x) << S_C_PCMD_TOKEN_PAR_ERROR)
39071 #define F_C_PCMD_TOKEN_PAR_ERROR    V_C_PCMD_TOKEN_PAR_ERROR(1U)
39072 
39073 #define A_PM_TX_CH2_OSPI_DEFICIT_THRSHLD 0x10029
39074 
39075 #define S_CH2_OSPI_DEFICIT_THRSHLD    0
39076 #define M_CH2_OSPI_DEFICIT_THRSHLD    0xfffU
39077 #define V_CH2_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH2_OSPI_DEFICIT_THRSHLD)
39078 #define G_CH2_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH2_OSPI_DEFICIT_THRSHLD) & M_CH2_OSPI_DEFICIT_THRSHLD)
39079 
39080 #define A_PM_TX_PERR_CAUSE 0x10029
39081 #define A_PM_TX_CH3_OSPI_DEFICIT_THRSHLD 0x1002a
39082 
39083 #define S_CH3_OSPI_DEFICIT_THRSHLD    0
39084 #define M_CH3_OSPI_DEFICIT_THRSHLD    0xfffU
39085 #define V_CH3_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH3_OSPI_DEFICIT_THRSHLD)
39086 #define G_CH3_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH3_OSPI_DEFICIT_THRSHLD) & M_CH3_OSPI_DEFICIT_THRSHLD)
39087 
39088 #define A_PM_TX_INT_CAUSE_MASK_HALT 0x1002b
39089 #define A_PM_TX_DBG_STAT0 0x1002c
39090 
39091 #define S_RD_I_BUSY    29
39092 #define V_RD_I_BUSY(x) ((x) << S_RD_I_BUSY)
39093 #define F_RD_I_BUSY    V_RD_I_BUSY(1U)
39094 
39095 #define S_WR_O_BUSY    28
39096 #define V_WR_O_BUSY(x) ((x) << S_WR_O_BUSY)
39097 #define F_WR_O_BUSY    V_WR_O_BUSY(1U)
39098 
39099 #define S_M_TO_O_BUSY    27
39100 #define V_M_TO_O_BUSY(x) ((x) << S_M_TO_O_BUSY)
39101 #define F_M_TO_O_BUSY    V_M_TO_O_BUSY(1U)
39102 
39103 #define S_I_TO_M_BUSY    26
39104 #define V_I_TO_M_BUSY(x) ((x) << S_I_TO_M_BUSY)
39105 #define F_I_TO_M_BUSY    V_I_TO_M_BUSY(1U)
39106 
39107 #define S_PCMD_FB_ONLY    25
39108 #define V_PCMD_FB_ONLY(x) ((x) << S_PCMD_FB_ONLY)
39109 #define F_PCMD_FB_ONLY    V_PCMD_FB_ONLY(1U)
39110 
39111 #define S_PCMD_MEM    24
39112 #define V_PCMD_MEM(x) ((x) << S_PCMD_MEM)
39113 #define F_PCMD_MEM    V_PCMD_MEM(1U)
39114 
39115 #define S_PCMD_BYPASS    23
39116 #define V_PCMD_BYPASS(x) ((x) << S_PCMD_BYPASS)
39117 #define F_PCMD_BYPASS    V_PCMD_BYPASS(1U)
39118 
39119 #define S_PCMD_EOP2    22
39120 #define V_PCMD_EOP2(x) ((x) << S_PCMD_EOP2)
39121 #define F_PCMD_EOP2    V_PCMD_EOP2(1U)
39122 
39123 #define S_PCMD_EOP    21
39124 #define V_PCMD_EOP(x) ((x) << S_PCMD_EOP)
39125 #define F_PCMD_EOP    V_PCMD_EOP(1U)
39126 
39127 #define S_PCMD_END_BUNDLE    20
39128 #define V_PCMD_END_BUNDLE(x) ((x) << S_PCMD_END_BUNDLE)
39129 #define F_PCMD_END_BUNDLE    V_PCMD_END_BUNDLE(1U)
39130 
39131 #define S_PCMD_FB_CMD    16
39132 #define M_PCMD_FB_CMD    0xfU
39133 #define V_PCMD_FB_CMD(x) ((x) << S_PCMD_FB_CMD)
39134 #define G_PCMD_FB_CMD(x) (((x) >> S_PCMD_FB_CMD) & M_PCMD_FB_CMD)
39135 
39136 #define S_CUR_PCMD_LEN    0
39137 #define M_CUR_PCMD_LEN    0xffffU
39138 #define V_CUR_PCMD_LEN(x) ((x) << S_CUR_PCMD_LEN)
39139 #define G_CUR_PCMD_LEN(x) (((x) >> S_CUR_PCMD_LEN) & M_CUR_PCMD_LEN)
39140 
39141 #define S_T6_RD_I_BUSY    28
39142 #define V_T6_RD_I_BUSY(x) ((x) << S_T6_RD_I_BUSY)
39143 #define F_T6_RD_I_BUSY    V_T6_RD_I_BUSY(1U)
39144 
39145 #define S_T6_WR_O_BUSY    27
39146 #define V_T6_WR_O_BUSY(x) ((x) << S_T6_WR_O_BUSY)
39147 #define F_T6_WR_O_BUSY    V_T6_WR_O_BUSY(1U)
39148 
39149 #define S_T6_M_TO_O_BUSY    26
39150 #define V_T6_M_TO_O_BUSY(x) ((x) << S_T6_M_TO_O_BUSY)
39151 #define F_T6_M_TO_O_BUSY    V_T6_M_TO_O_BUSY(1U)
39152 
39153 #define S_T6_I_TO_M_BUSY    25
39154 #define V_T6_I_TO_M_BUSY(x) ((x) << S_T6_I_TO_M_BUSY)
39155 #define F_T6_I_TO_M_BUSY    V_T6_I_TO_M_BUSY(1U)
39156 
39157 #define S_T6_PCMD_FB_ONLY    24
39158 #define V_T6_PCMD_FB_ONLY(x) ((x) << S_T6_PCMD_FB_ONLY)
39159 #define F_T6_PCMD_FB_ONLY    V_T6_PCMD_FB_ONLY(1U)
39160 
39161 #define S_T6_PCMD_MEM    23
39162 #define V_T6_PCMD_MEM(x) ((x) << S_T6_PCMD_MEM)
39163 #define F_T6_PCMD_MEM    V_T6_PCMD_MEM(1U)
39164 
39165 #define S_T6_PCMD_BYPASS    22
39166 #define V_T6_PCMD_BYPASS(x) ((x) << S_T6_PCMD_BYPASS)
39167 #define F_T6_PCMD_BYPASS    V_T6_PCMD_BYPASS(1U)
39168 
39169 #define A_PM_TX_DBG_STAT1 0x1002d
39170 
39171 #define S_PCMD_MEM0    31
39172 #define V_PCMD_MEM0(x) ((x) << S_PCMD_MEM0)
39173 #define F_PCMD_MEM0    V_PCMD_MEM0(1U)
39174 
39175 #define S_FREE_OESPI_CNT0    19
39176 #define M_FREE_OESPI_CNT0    0xfffU
39177 #define V_FREE_OESPI_CNT0(x) ((x) << S_FREE_OESPI_CNT0)
39178 #define G_FREE_OESPI_CNT0(x) (((x) >> S_FREE_OESPI_CNT0) & M_FREE_OESPI_CNT0)
39179 
39180 #define S_PCMD_FLIT_LEN0    7
39181 #define M_PCMD_FLIT_LEN0    0xfffU
39182 #define V_PCMD_FLIT_LEN0(x) ((x) << S_PCMD_FLIT_LEN0)
39183 #define G_PCMD_FLIT_LEN0(x) (((x) >> S_PCMD_FLIT_LEN0) & M_PCMD_FLIT_LEN0)
39184 
39185 #define S_PCMD_CMD0    3
39186 #define M_PCMD_CMD0    0xfU
39187 #define V_PCMD_CMD0(x) ((x) << S_PCMD_CMD0)
39188 #define G_PCMD_CMD0(x) (((x) >> S_PCMD_CMD0) & M_PCMD_CMD0)
39189 
39190 #define S_OFIFO_FULL0    2
39191 #define V_OFIFO_FULL0(x) ((x) << S_OFIFO_FULL0)
39192 #define F_OFIFO_FULL0    V_OFIFO_FULL0(1U)
39193 
39194 #define S_GCSUM_DRDY0    1
39195 #define V_GCSUM_DRDY0(x) ((x) << S_GCSUM_DRDY0)
39196 #define F_GCSUM_DRDY0    V_GCSUM_DRDY0(1U)
39197 
39198 #define S_BYPASS0    0
39199 #define V_BYPASS0(x) ((x) << S_BYPASS0)
39200 #define F_BYPASS0    V_BYPASS0(1U)
39201 
39202 #define A_PM_TX_DBG_STAT2 0x1002e
39203 
39204 #define S_PCMD_MEM1    31
39205 #define V_PCMD_MEM1(x) ((x) << S_PCMD_MEM1)
39206 #define F_PCMD_MEM1    V_PCMD_MEM1(1U)
39207 
39208 #define S_FREE_OESPI_CNT1    19
39209 #define M_FREE_OESPI_CNT1    0xfffU
39210 #define V_FREE_OESPI_CNT1(x) ((x) << S_FREE_OESPI_CNT1)
39211 #define G_FREE_OESPI_CNT1(x) (((x) >> S_FREE_OESPI_CNT1) & M_FREE_OESPI_CNT1)
39212 
39213 #define S_PCMD_FLIT_LEN1    7
39214 #define M_PCMD_FLIT_LEN1    0xfffU
39215 #define V_PCMD_FLIT_LEN1(x) ((x) << S_PCMD_FLIT_LEN1)
39216 #define G_PCMD_FLIT_LEN1(x) (((x) >> S_PCMD_FLIT_LEN1) & M_PCMD_FLIT_LEN1)
39217 
39218 #define S_PCMD_CMD1    3
39219 #define M_PCMD_CMD1    0xfU
39220 #define V_PCMD_CMD1(x) ((x) << S_PCMD_CMD1)
39221 #define G_PCMD_CMD1(x) (((x) >> S_PCMD_CMD1) & M_PCMD_CMD1)
39222 
39223 #define S_OFIFO_FULL1    2
39224 #define V_OFIFO_FULL1(x) ((x) << S_OFIFO_FULL1)
39225 #define F_OFIFO_FULL1    V_OFIFO_FULL1(1U)
39226 
39227 #define S_GCSUM_DRDY1    1
39228 #define V_GCSUM_DRDY1(x) ((x) << S_GCSUM_DRDY1)
39229 #define F_GCSUM_DRDY1    V_GCSUM_DRDY1(1U)
39230 
39231 #define S_BYPASS1    0
39232 #define V_BYPASS1(x) ((x) << S_BYPASS1)
39233 #define F_BYPASS1    V_BYPASS1(1U)
39234 
39235 #define A_PM_TX_DBG_STAT3 0x1002f
39236 
39237 #define S_PCMD_MEM2    31
39238 #define V_PCMD_MEM2(x) ((x) << S_PCMD_MEM2)
39239 #define F_PCMD_MEM2    V_PCMD_MEM2(1U)
39240 
39241 #define S_FREE_OESPI_CNT2    19
39242 #define M_FREE_OESPI_CNT2    0xfffU
39243 #define V_FREE_OESPI_CNT2(x) ((x) << S_FREE_OESPI_CNT2)
39244 #define G_FREE_OESPI_CNT2(x) (((x) >> S_FREE_OESPI_CNT2) & M_FREE_OESPI_CNT2)
39245 
39246 #define S_PCMD_FLIT_LEN2    7
39247 #define M_PCMD_FLIT_LEN2    0xfffU
39248 #define V_PCMD_FLIT_LEN2(x) ((x) << S_PCMD_FLIT_LEN2)
39249 #define G_PCMD_FLIT_LEN2(x) (((x) >> S_PCMD_FLIT_LEN2) & M_PCMD_FLIT_LEN2)
39250 
39251 #define S_PCMD_CMD2    3
39252 #define M_PCMD_CMD2    0xfU
39253 #define V_PCMD_CMD2(x) ((x) << S_PCMD_CMD2)
39254 #define G_PCMD_CMD2(x) (((x) >> S_PCMD_CMD2) & M_PCMD_CMD2)
39255 
39256 #define S_OFIFO_FULL2    2
39257 #define V_OFIFO_FULL2(x) ((x) << S_OFIFO_FULL2)
39258 #define F_OFIFO_FULL2    V_OFIFO_FULL2(1U)
39259 
39260 #define S_GCSUM_DRDY2    1
39261 #define V_GCSUM_DRDY2(x) ((x) << S_GCSUM_DRDY2)
39262 #define F_GCSUM_DRDY2    V_GCSUM_DRDY2(1U)
39263 
39264 #define S_BYPASS2    0
39265 #define V_BYPASS2(x) ((x) << S_BYPASS2)
39266 #define F_BYPASS2    V_BYPASS2(1U)
39267 
39268 #define A_PM_TX_DBG_STAT4 0x10030
39269 
39270 #define S_PCMD_MEM3    31
39271 #define V_PCMD_MEM3(x) ((x) << S_PCMD_MEM3)
39272 #define F_PCMD_MEM3    V_PCMD_MEM3(1U)
39273 
39274 #define S_FREE_OESPI_CNT3    19
39275 #define M_FREE_OESPI_CNT3    0xfffU
39276 #define V_FREE_OESPI_CNT3(x) ((x) << S_FREE_OESPI_CNT3)
39277 #define G_FREE_OESPI_CNT3(x) (((x) >> S_FREE_OESPI_CNT3) & M_FREE_OESPI_CNT3)
39278 
39279 #define S_PCMD_FLIT_LEN3    7
39280 #define M_PCMD_FLIT_LEN3    0xfffU
39281 #define V_PCMD_FLIT_LEN3(x) ((x) << S_PCMD_FLIT_LEN3)
39282 #define G_PCMD_FLIT_LEN3(x) (((x) >> S_PCMD_FLIT_LEN3) & M_PCMD_FLIT_LEN3)
39283 
39284 #define S_PCMD_CMD3    3
39285 #define M_PCMD_CMD3    0xfU
39286 #define V_PCMD_CMD3(x) ((x) << S_PCMD_CMD3)
39287 #define G_PCMD_CMD3(x) (((x) >> S_PCMD_CMD3) & M_PCMD_CMD3)
39288 
39289 #define S_OFIFO_FULL3    2
39290 #define V_OFIFO_FULL3(x) ((x) << S_OFIFO_FULL3)
39291 #define F_OFIFO_FULL3    V_OFIFO_FULL3(1U)
39292 
39293 #define S_GCSUM_DRDY3    1
39294 #define V_GCSUM_DRDY3(x) ((x) << S_GCSUM_DRDY3)
39295 #define F_GCSUM_DRDY3    V_GCSUM_DRDY3(1U)
39296 
39297 #define S_BYPASS3    0
39298 #define V_BYPASS3(x) ((x) << S_BYPASS3)
39299 #define F_BYPASS3    V_BYPASS3(1U)
39300 
39301 #define A_PM_TX_DBG_STAT5 0x10031
39302 
39303 #define S_SET_PCMD_RES_RDY_RD    24
39304 #define M_SET_PCMD_RES_RDY_RD    0xfU
39305 #define V_SET_PCMD_RES_RDY_RD(x) ((x) << S_SET_PCMD_RES_RDY_RD)
39306 #define G_SET_PCMD_RES_RDY_RD(x) (((x) >> S_SET_PCMD_RES_RDY_RD) & M_SET_PCMD_RES_RDY_RD)
39307 
39308 #define S_ISSUED_PREF_RD_ER_CLR    20
39309 #define M_ISSUED_PREF_RD_ER_CLR    0xfU
39310 #define V_ISSUED_PREF_RD_ER_CLR(x) ((x) << S_ISSUED_PREF_RD_ER_CLR)
39311 #define G_ISSUED_PREF_RD_ER_CLR(x) (((x) >> S_ISSUED_PREF_RD_ER_CLR) & M_ISSUED_PREF_RD_ER_CLR)
39312 
39313 #define S_ISSUED_PREF_RD    16
39314 #define M_ISSUED_PREF_RD    0xfU
39315 #define V_ISSUED_PREF_RD(x) ((x) << S_ISSUED_PREF_RD)
39316 #define G_ISSUED_PREF_RD(x) (((x) >> S_ISSUED_PREF_RD) & M_ISSUED_PREF_RD)
39317 
39318 #define S_PCMD_RES_RDY    12
39319 #define M_PCMD_RES_RDY    0xfU
39320 #define V_PCMD_RES_RDY(x) ((x) << S_PCMD_RES_RDY)
39321 #define G_PCMD_RES_RDY(x) (((x) >> S_PCMD_RES_RDY) & M_PCMD_RES_RDY)
39322 
39323 #define S_DB_VLD    11
39324 #define V_DB_VLD(x) ((x) << S_DB_VLD)
39325 #define F_DB_VLD    V_DB_VLD(1U)
39326 
39327 #define S_INJECT0_DRDY    10
39328 #define V_INJECT0_DRDY(x) ((x) << S_INJECT0_DRDY)
39329 #define F_INJECT0_DRDY    V_INJECT0_DRDY(1U)
39330 
39331 #define S_INJECT1_DRDY    9
39332 #define V_INJECT1_DRDY(x) ((x) << S_INJECT1_DRDY)
39333 #define F_INJECT1_DRDY    V_INJECT1_DRDY(1U)
39334 
39335 #define S_FIRST_BUNDLE    5
39336 #define M_FIRST_BUNDLE    0xfU
39337 #define V_FIRST_BUNDLE(x) ((x) << S_FIRST_BUNDLE)
39338 #define G_FIRST_BUNDLE(x) (((x) >> S_FIRST_BUNDLE) & M_FIRST_BUNDLE)
39339 
39340 #define S_GCSUM_MORE_THAN_2_LEFT    1
39341 #define M_GCSUM_MORE_THAN_2_LEFT    0xfU
39342 #define V_GCSUM_MORE_THAN_2_LEFT(x) ((x) << S_GCSUM_MORE_THAN_2_LEFT)
39343 #define G_GCSUM_MORE_THAN_2_LEFT(x) (((x) >> S_GCSUM_MORE_THAN_2_LEFT) & M_GCSUM_MORE_THAN_2_LEFT)
39344 
39345 #define S_SDC_DRDY    0
39346 #define V_SDC_DRDY(x) ((x) << S_SDC_DRDY)
39347 #define F_SDC_DRDY    V_SDC_DRDY(1U)
39348 
39349 #define A_PM_TX_DBG_STAT6 0x10032
39350 
39351 #define S_PCMD_VLD    31
39352 #define V_PCMD_VLD(x) ((x) << S_PCMD_VLD)
39353 #define F_PCMD_VLD    V_PCMD_VLD(1U)
39354 
39355 #define S_PCMD_CH    29
39356 #define M_PCMD_CH    0x3U
39357 #define V_PCMD_CH(x) ((x) << S_PCMD_CH)
39358 #define G_PCMD_CH(x) (((x) >> S_PCMD_CH) & M_PCMD_CH)
39359 
39360 #define S_STATE_MACHINE_LOC    24
39361 #define M_STATE_MACHINE_LOC    0x1fU
39362 #define V_STATE_MACHINE_LOC(x) ((x) << S_STATE_MACHINE_LOC)
39363 #define G_STATE_MACHINE_LOC(x) (((x) >> S_STATE_MACHINE_LOC) & M_STATE_MACHINE_LOC)
39364 
39365 #define S_ICSPI_TXVALID    20
39366 #define M_ICSPI_TXVALID    0xfU
39367 #define V_ICSPI_TXVALID(x) ((x) << S_ICSPI_TXVALID)
39368 #define G_ICSPI_TXVALID(x) (((x) >> S_ICSPI_TXVALID) & M_ICSPI_TXVALID)
39369 
39370 #define S_ICSPI_TXFULL    16
39371 #define M_ICSPI_TXFULL    0xfU
39372 #define V_ICSPI_TXFULL(x) ((x) << S_ICSPI_TXFULL)
39373 #define G_ICSPI_TXFULL(x) (((x) >> S_ICSPI_TXFULL) & M_ICSPI_TXFULL)
39374 
39375 #define S_PCMD_SRDY    12
39376 #define M_PCMD_SRDY    0xfU
39377 #define V_PCMD_SRDY(x) ((x) << S_PCMD_SRDY)
39378 #define G_PCMD_SRDY(x) (((x) >> S_PCMD_SRDY) & M_PCMD_SRDY)
39379 
39380 #define S_PCMD_DRDY    8
39381 #define M_PCMD_DRDY    0xfU
39382 #define V_PCMD_DRDY(x) ((x) << S_PCMD_DRDY)
39383 #define G_PCMD_DRDY(x) (((x) >> S_PCMD_DRDY) & M_PCMD_DRDY)
39384 
39385 #define S_PCMD_CMD    4
39386 #define M_PCMD_CMD    0xfU
39387 #define V_PCMD_CMD(x) ((x) << S_PCMD_CMD)
39388 #define G_PCMD_CMD(x) (((x) >> S_PCMD_CMD) & M_PCMD_CMD)
39389 
39390 #define S_OEFIFO_FULL3    3
39391 #define V_OEFIFO_FULL3(x) ((x) << S_OEFIFO_FULL3)
39392 #define F_OEFIFO_FULL3    V_OEFIFO_FULL3(1U)
39393 
39394 #define S_OEFIFO_FULL2    2
39395 #define V_OEFIFO_FULL2(x) ((x) << S_OEFIFO_FULL2)
39396 #define F_OEFIFO_FULL2    V_OEFIFO_FULL2(1U)
39397 
39398 #define S_OEFIFO_FULL1    1
39399 #define V_OEFIFO_FULL1(x) ((x) << S_OEFIFO_FULL1)
39400 #define F_OEFIFO_FULL1    V_OEFIFO_FULL1(1U)
39401 
39402 #define S_OEFIFO_FULL0    0
39403 #define V_OEFIFO_FULL0(x) ((x) << S_OEFIFO_FULL0)
39404 #define F_OEFIFO_FULL0    V_OEFIFO_FULL0(1U)
39405 
39406 #define A_PM_TX_DBG_STAT7 0x10033
39407 
39408 #define S_ICSPI_RXVALID    28
39409 #define M_ICSPI_RXVALID    0xfU
39410 #define V_ICSPI_RXVALID(x) ((x) << S_ICSPI_RXVALID)
39411 #define G_ICSPI_RXVALID(x) (((x) >> S_ICSPI_RXVALID) & M_ICSPI_RXVALID)
39412 
39413 #define S_ICSPI_RXFULL    24
39414 #define M_ICSPI_RXFULL    0xfU
39415 #define V_ICSPI_RXFULL(x) ((x) << S_ICSPI_RXFULL)
39416 #define G_ICSPI_RXFULL(x) (((x) >> S_ICSPI_RXFULL) & M_ICSPI_RXFULL)
39417 
39418 #define S_OESPI_VALID    20
39419 #define M_OESPI_VALID    0xfU
39420 #define V_OESPI_VALID(x) ((x) << S_OESPI_VALID)
39421 #define G_OESPI_VALID(x) (((x) >> S_OESPI_VALID) & M_OESPI_VALID)
39422 
39423 #define S_OESPI_FULL    16
39424 #define M_OESPI_FULL    0xfU
39425 #define V_OESPI_FULL(x) ((x) << S_OESPI_FULL)
39426 #define G_OESPI_FULL(x) (((x) >> S_OESPI_FULL) & M_OESPI_FULL)
39427 
39428 #define S_C_RXVALID    12
39429 #define M_C_RXVALID    0xfU
39430 #define V_C_RXVALID(x) ((x) << S_C_RXVALID)
39431 #define G_C_RXVALID(x) (((x) >> S_C_RXVALID) & M_C_RXVALID)
39432 
39433 #define S_C_RXAFULL    8
39434 #define M_C_RXAFULL    0xfU
39435 #define V_C_RXAFULL(x) ((x) << S_C_RXAFULL)
39436 #define G_C_RXAFULL(x) (((x) >> S_C_RXAFULL) & M_C_RXAFULL)
39437 
39438 #define S_E_TXVALID3    7
39439 #define V_E_TXVALID3(x) ((x) << S_E_TXVALID3)
39440 #define F_E_TXVALID3    V_E_TXVALID3(1U)
39441 
39442 #define S_E_TXVALID2    6
39443 #define V_E_TXVALID2(x) ((x) << S_E_TXVALID2)
39444 #define F_E_TXVALID2    V_E_TXVALID2(1U)
39445 
39446 #define S_E_TXVALID1    5
39447 #define V_E_TXVALID1(x) ((x) << S_E_TXVALID1)
39448 #define F_E_TXVALID1    V_E_TXVALID1(1U)
39449 
39450 #define S_E_TXVALID0    4
39451 #define V_E_TXVALID0(x) ((x) << S_E_TXVALID0)
39452 #define F_E_TXVALID0    V_E_TXVALID0(1U)
39453 
39454 #define S_E_TXFULL3    3
39455 #define V_E_TXFULL3(x) ((x) << S_E_TXFULL3)
39456 #define F_E_TXFULL3    V_E_TXFULL3(1U)
39457 
39458 #define S_E_TXFULL2    2
39459 #define V_E_TXFULL2(x) ((x) << S_E_TXFULL2)
39460 #define F_E_TXFULL2    V_E_TXFULL2(1U)
39461 
39462 #define S_E_TXFULL1    1
39463 #define V_E_TXFULL1(x) ((x) << S_E_TXFULL1)
39464 #define F_E_TXFULL1    V_E_TXFULL1(1U)
39465 
39466 #define S_E_TXFULL0    0
39467 #define V_E_TXFULL0(x) ((x) << S_E_TXFULL0)
39468 #define F_E_TXFULL0    V_E_TXFULL0(1U)
39469 
39470 #define A_PM_TX_DBG_STAT8 0x10034
39471 
39472 #define S_MC_RSP_FIFO_CNT    24
39473 #define M_MC_RSP_FIFO_CNT    0x3U
39474 #define V_MC_RSP_FIFO_CNT(x) ((x) << S_MC_RSP_FIFO_CNT)
39475 #define G_MC_RSP_FIFO_CNT(x) (((x) >> S_MC_RSP_FIFO_CNT) & M_MC_RSP_FIFO_CNT)
39476 
39477 #define S_PCMD_FREE_CNT0    14
39478 #define M_PCMD_FREE_CNT0    0x3ffU
39479 #define V_PCMD_FREE_CNT0(x) ((x) << S_PCMD_FREE_CNT0)
39480 #define G_PCMD_FREE_CNT0(x) (((x) >> S_PCMD_FREE_CNT0) & M_PCMD_FREE_CNT0)
39481 
39482 #define S_PCMD_FREE_CNT1    4
39483 #define M_PCMD_FREE_CNT1    0x3ffU
39484 #define V_PCMD_FREE_CNT1(x) ((x) << S_PCMD_FREE_CNT1)
39485 #define G_PCMD_FREE_CNT1(x) (((x) >> S_PCMD_FREE_CNT1) & M_PCMD_FREE_CNT1)
39486 
39487 #define S_M_REQADDRRDY    3
39488 #define V_M_REQADDRRDY(x) ((x) << S_M_REQADDRRDY)
39489 #define F_M_REQADDRRDY    V_M_REQADDRRDY(1U)
39490 
39491 #define S_M_REQWRITE    2
39492 #define V_M_REQWRITE(x) ((x) << S_M_REQWRITE)
39493 #define F_M_REQWRITE    V_M_REQWRITE(1U)
39494 
39495 #define S_M_REQDATAVLD    1
39496 #define V_M_REQDATAVLD(x) ((x) << S_M_REQDATAVLD)
39497 #define F_M_REQDATAVLD    V_M_REQDATAVLD(1U)
39498 
39499 #define S_M_REQDATARDY    0
39500 #define V_M_REQDATARDY(x) ((x) << S_M_REQDATARDY)
39501 #define F_M_REQDATARDY    V_M_REQDATARDY(1U)
39502 
39503 #define S_T6_MC_RSP_FIFO_CNT    27
39504 #define M_T6_MC_RSP_FIFO_CNT    0x3U
39505 #define V_T6_MC_RSP_FIFO_CNT(x) ((x) << S_T6_MC_RSP_FIFO_CNT)
39506 #define G_T6_MC_RSP_FIFO_CNT(x) (((x) >> S_T6_MC_RSP_FIFO_CNT) & M_T6_MC_RSP_FIFO_CNT)
39507 
39508 #define S_T6_PCMD_FREE_CNT0    17
39509 #define M_T6_PCMD_FREE_CNT0    0x3ffU
39510 #define V_T6_PCMD_FREE_CNT0(x) ((x) << S_T6_PCMD_FREE_CNT0)
39511 #define G_T6_PCMD_FREE_CNT0(x) (((x) >> S_T6_PCMD_FREE_CNT0) & M_T6_PCMD_FREE_CNT0)
39512 
39513 #define S_T6_PCMD_FREE_CNT1    7
39514 #define M_T6_PCMD_FREE_CNT1    0x3ffU
39515 #define V_T6_PCMD_FREE_CNT1(x) ((x) << S_T6_PCMD_FREE_CNT1)
39516 #define G_T6_PCMD_FREE_CNT1(x) (((x) >> S_T6_PCMD_FREE_CNT1) & M_T6_PCMD_FREE_CNT1)
39517 
39518 #define S_M_RSPVLD    6
39519 #define V_M_RSPVLD(x) ((x) << S_M_RSPVLD)
39520 #define F_M_RSPVLD    V_M_RSPVLD(1U)
39521 
39522 #define S_M_RSPRDY    5
39523 #define V_M_RSPRDY(x) ((x) << S_M_RSPRDY)
39524 #define F_M_RSPRDY    V_M_RSPRDY(1U)
39525 
39526 #define S_M_REQADDRVLD    4
39527 #define V_M_REQADDRVLD(x) ((x) << S_M_REQADDRVLD)
39528 #define F_M_REQADDRVLD    V_M_REQADDRVLD(1U)
39529 
39530 #define A_PM_TX_DBG_STAT9 0x10035
39531 
39532 #define S_PCMD_FREE_CNT2    10
39533 #define M_PCMD_FREE_CNT2    0x3ffU
39534 #define V_PCMD_FREE_CNT2(x) ((x) << S_PCMD_FREE_CNT2)
39535 #define G_PCMD_FREE_CNT2(x) (((x) >> S_PCMD_FREE_CNT2) & M_PCMD_FREE_CNT2)
39536 
39537 #define S_PCMD_FREE_CNT3    0
39538 #define M_PCMD_FREE_CNT3    0x3ffU
39539 #define V_PCMD_FREE_CNT3(x) ((x) << S_PCMD_FREE_CNT3)
39540 #define G_PCMD_FREE_CNT3(x) (((x) >> S_PCMD_FREE_CNT3) & M_PCMD_FREE_CNT3)
39541 
39542 #define A_PM_TX_DBG_STAT10 0x10036
39543 
39544 #define S_IN_EOP_CNT3    28
39545 #define M_IN_EOP_CNT3    0xfU
39546 #define V_IN_EOP_CNT3(x) ((x) << S_IN_EOP_CNT3)
39547 #define G_IN_EOP_CNT3(x) (((x) >> S_IN_EOP_CNT3) & M_IN_EOP_CNT3)
39548 
39549 #define S_IN_EOP_CNT2    24
39550 #define M_IN_EOP_CNT2    0xfU
39551 #define V_IN_EOP_CNT2(x) ((x) << S_IN_EOP_CNT2)
39552 #define G_IN_EOP_CNT2(x) (((x) >> S_IN_EOP_CNT2) & M_IN_EOP_CNT2)
39553 
39554 #define S_IN_EOP_CNT1    20
39555 #define M_IN_EOP_CNT1    0xfU
39556 #define V_IN_EOP_CNT1(x) ((x) << S_IN_EOP_CNT1)
39557 #define G_IN_EOP_CNT1(x) (((x) >> S_IN_EOP_CNT1) & M_IN_EOP_CNT1)
39558 
39559 #define S_IN_EOP_CNT0    16
39560 #define M_IN_EOP_CNT0    0xfU
39561 #define V_IN_EOP_CNT0(x) ((x) << S_IN_EOP_CNT0)
39562 #define G_IN_EOP_CNT0(x) (((x) >> S_IN_EOP_CNT0) & M_IN_EOP_CNT0)
39563 
39564 #define S_IN_SOP_CNT3    12
39565 #define M_IN_SOP_CNT3    0xfU
39566 #define V_IN_SOP_CNT3(x) ((x) << S_IN_SOP_CNT3)
39567 #define G_IN_SOP_CNT3(x) (((x) >> S_IN_SOP_CNT3) & M_IN_SOP_CNT3)
39568 
39569 #define S_IN_SOP_CNT2    8
39570 #define M_IN_SOP_CNT2    0xfU
39571 #define V_IN_SOP_CNT2(x) ((x) << S_IN_SOP_CNT2)
39572 #define G_IN_SOP_CNT2(x) (((x) >> S_IN_SOP_CNT2) & M_IN_SOP_CNT2)
39573 
39574 #define S_IN_SOP_CNT1    4
39575 #define M_IN_SOP_CNT1    0xfU
39576 #define V_IN_SOP_CNT1(x) ((x) << S_IN_SOP_CNT1)
39577 #define G_IN_SOP_CNT1(x) (((x) >> S_IN_SOP_CNT1) & M_IN_SOP_CNT1)
39578 
39579 #define S_IN_SOP_CNT0    0
39580 #define M_IN_SOP_CNT0    0xfU
39581 #define V_IN_SOP_CNT0(x) ((x) << S_IN_SOP_CNT0)
39582 #define G_IN_SOP_CNT0(x) (((x) >> S_IN_SOP_CNT0) & M_IN_SOP_CNT0)
39583 
39584 #define A_PM_TX_DBG_STAT11 0x10037
39585 
39586 #define S_OUT_EOP_CNT3    28
39587 #define M_OUT_EOP_CNT3    0xfU
39588 #define V_OUT_EOP_CNT3(x) ((x) << S_OUT_EOP_CNT3)
39589 #define G_OUT_EOP_CNT3(x) (((x) >> S_OUT_EOP_CNT3) & M_OUT_EOP_CNT3)
39590 
39591 #define S_OUT_EOP_CNT2    24
39592 #define M_OUT_EOP_CNT2    0xfU
39593 #define V_OUT_EOP_CNT2(x) ((x) << S_OUT_EOP_CNT2)
39594 #define G_OUT_EOP_CNT2(x) (((x) >> S_OUT_EOP_CNT2) & M_OUT_EOP_CNT2)
39595 
39596 #define S_OUT_EOP_CNT1    20
39597 #define M_OUT_EOP_CNT1    0xfU
39598 #define V_OUT_EOP_CNT1(x) ((x) << S_OUT_EOP_CNT1)
39599 #define G_OUT_EOP_CNT1(x) (((x) >> S_OUT_EOP_CNT1) & M_OUT_EOP_CNT1)
39600 
39601 #define S_OUT_EOP_CNT0    16
39602 #define M_OUT_EOP_CNT0    0xfU
39603 #define V_OUT_EOP_CNT0(x) ((x) << S_OUT_EOP_CNT0)
39604 #define G_OUT_EOP_CNT0(x) (((x) >> S_OUT_EOP_CNT0) & M_OUT_EOP_CNT0)
39605 
39606 #define S_OUT_SOP_CNT3    12
39607 #define M_OUT_SOP_CNT3    0xfU
39608 #define V_OUT_SOP_CNT3(x) ((x) << S_OUT_SOP_CNT3)
39609 #define G_OUT_SOP_CNT3(x) (((x) >> S_OUT_SOP_CNT3) & M_OUT_SOP_CNT3)
39610 
39611 #define S_OUT_SOP_CNT2    8
39612 #define M_OUT_SOP_CNT2    0xfU
39613 #define V_OUT_SOP_CNT2(x) ((x) << S_OUT_SOP_CNT2)
39614 #define G_OUT_SOP_CNT2(x) (((x) >> S_OUT_SOP_CNT2) & M_OUT_SOP_CNT2)
39615 
39616 #define S_OUT_SOP_CNT1    4
39617 #define M_OUT_SOP_CNT1    0xfU
39618 #define V_OUT_SOP_CNT1(x) ((x) << S_OUT_SOP_CNT1)
39619 #define G_OUT_SOP_CNT1(x) (((x) >> S_OUT_SOP_CNT1) & M_OUT_SOP_CNT1)
39620 
39621 #define S_OUT_SOP_CNT0    0
39622 #define M_OUT_SOP_CNT0    0xfU
39623 #define V_OUT_SOP_CNT0(x) ((x) << S_OUT_SOP_CNT0)
39624 #define G_OUT_SOP_CNT0(x) (((x) >> S_OUT_SOP_CNT0) & M_OUT_SOP_CNT0)
39625 
39626 #define A_PM_TX_DBG_STAT12 0x10038
39627 #define A_PM_TX_DBG_STAT13 0x10039
39628 
39629 #define S_CH_DEFICIT_BLOWED    31
39630 #define V_CH_DEFICIT_BLOWED(x) ((x) << S_CH_DEFICIT_BLOWED)
39631 #define F_CH_DEFICIT_BLOWED    V_CH_DEFICIT_BLOWED(1U)
39632 
39633 #define S_CH1_DEFICIT    16
39634 #define M_CH1_DEFICIT    0xfffU
39635 #define V_CH1_DEFICIT(x) ((x) << S_CH1_DEFICIT)
39636 #define G_CH1_DEFICIT(x) (((x) >> S_CH1_DEFICIT) & M_CH1_DEFICIT)
39637 
39638 #define S_CH0_DEFICIT    0
39639 #define M_CH0_DEFICIT    0xfffU
39640 #define V_CH0_DEFICIT(x) ((x) << S_CH0_DEFICIT)
39641 #define G_CH0_DEFICIT(x) (((x) >> S_CH0_DEFICIT) & M_CH0_DEFICIT)
39642 
39643 #define A_PM_TX_DBG_STAT14 0x1003a
39644 
39645 #define S_CH3_DEFICIT    16
39646 #define M_CH3_DEFICIT    0xfffU
39647 #define V_CH3_DEFICIT(x) ((x) << S_CH3_DEFICIT)
39648 #define G_CH3_DEFICIT(x) (((x) >> S_CH3_DEFICIT) & M_CH3_DEFICIT)
39649 
39650 #define S_CH2_DEFICIT    0
39651 #define M_CH2_DEFICIT    0xfffU
39652 #define V_CH2_DEFICIT(x) ((x) << S_CH2_DEFICIT)
39653 #define G_CH2_DEFICIT(x) (((x) >> S_CH2_DEFICIT) & M_CH2_DEFICIT)
39654 
39655 #define A_PM_TX_DBG_STAT15 0x1003b
39656 
39657 #define S_BUNDLE_LEN_SRDY    28
39658 #define M_BUNDLE_LEN_SRDY    0xfU
39659 #define V_BUNDLE_LEN_SRDY(x) ((x) << S_BUNDLE_LEN_SRDY)
39660 #define G_BUNDLE_LEN_SRDY(x) (((x) >> S_BUNDLE_LEN_SRDY) & M_BUNDLE_LEN_SRDY)
39661 
39662 #define S_BUNDLE_LEN1    16
39663 #define M_BUNDLE_LEN1    0xfffU
39664 #define V_BUNDLE_LEN1(x) ((x) << S_BUNDLE_LEN1)
39665 #define G_BUNDLE_LEN1(x) (((x) >> S_BUNDLE_LEN1) & M_BUNDLE_LEN1)
39666 
39667 #define S_BUNDLE_LEN0    0
39668 #define M_BUNDLE_LEN0    0xfffU
39669 #define V_BUNDLE_LEN0(x) ((x) << S_BUNDLE_LEN0)
39670 #define G_BUNDLE_LEN0(x) (((x) >> S_BUNDLE_LEN0) & M_BUNDLE_LEN0)
39671 
39672 #define S_T6_BUNDLE_LEN_SRDY    24
39673 #define M_T6_BUNDLE_LEN_SRDY    0x3U
39674 #define V_T6_BUNDLE_LEN_SRDY(x) ((x) << S_T6_BUNDLE_LEN_SRDY)
39675 #define G_T6_BUNDLE_LEN_SRDY(x) (((x) >> S_T6_BUNDLE_LEN_SRDY) & M_T6_BUNDLE_LEN_SRDY)
39676 
39677 #define S_T6_BUNDLE_LEN1    12
39678 #define M_T6_BUNDLE_LEN1    0xfffU
39679 #define V_T6_BUNDLE_LEN1(x) ((x) << S_T6_BUNDLE_LEN1)
39680 #define G_T6_BUNDLE_LEN1(x) (((x) >> S_T6_BUNDLE_LEN1) & M_T6_BUNDLE_LEN1)
39681 
39682 #define A_PM_TX_DBG_STAT16 0x1003c
39683 
39684 #define S_BUNDLE_LEN3    16
39685 #define M_BUNDLE_LEN3    0xfffU
39686 #define V_BUNDLE_LEN3(x) ((x) << S_BUNDLE_LEN3)
39687 #define G_BUNDLE_LEN3(x) (((x) >> S_BUNDLE_LEN3) & M_BUNDLE_LEN3)
39688 
39689 #define S_BUNDLE_LEN2    0
39690 #define M_BUNDLE_LEN2    0xfffU
39691 #define V_BUNDLE_LEN2(x) ((x) << S_BUNDLE_LEN2)
39692 #define G_BUNDLE_LEN2(x) (((x) >> S_BUNDLE_LEN2) & M_BUNDLE_LEN2)
39693 
39694 /* registers for module MPS */
39695 #define MPS_BASE_ADDR 0x9000
39696 
39697 #define A_MPS_PORT_CTL 0x0
39698 
39699 #define S_LPBKEN    31
39700 #define V_LPBKEN(x) ((x) << S_LPBKEN)
39701 #define F_LPBKEN    V_LPBKEN(1U)
39702 
39703 #define S_PORTTXEN    30
39704 #define V_PORTTXEN(x) ((x) << S_PORTTXEN)
39705 #define F_PORTTXEN    V_PORTTXEN(1U)
39706 
39707 #define S_PORTRXEN    29
39708 #define V_PORTRXEN(x) ((x) << S_PORTRXEN)
39709 #define F_PORTRXEN    V_PORTRXEN(1U)
39710 
39711 #define S_PPPEN    28
39712 #define V_PPPEN(x) ((x) << S_PPPEN)
39713 #define F_PPPEN    V_PPPEN(1U)
39714 
39715 #define S_FCSSTRIPEN    27
39716 #define V_FCSSTRIPEN(x) ((x) << S_FCSSTRIPEN)
39717 #define F_FCSSTRIPEN    V_FCSSTRIPEN(1U)
39718 
39719 #define S_PPPANDPAUSE    26
39720 #define V_PPPANDPAUSE(x) ((x) << S_PPPANDPAUSE)
39721 #define F_PPPANDPAUSE    V_PPPANDPAUSE(1U)
39722 
39723 #define S_PRIOPPPENMAP    16
39724 #define M_PRIOPPPENMAP    0xffU
39725 #define V_PRIOPPPENMAP(x) ((x) << S_PRIOPPPENMAP)
39726 #define G_PRIOPPPENMAP(x) (((x) >> S_PRIOPPPENMAP) & M_PRIOPPPENMAP)
39727 
39728 #define A_MPS_VF_CTL 0x0
39729 #define A_MPS_PORT_PAUSE_CTL 0x4
39730 
39731 #define S_TIMEUNIT    0
39732 #define M_TIMEUNIT    0xffffU
39733 #define V_TIMEUNIT(x) ((x) << S_TIMEUNIT)
39734 #define G_TIMEUNIT(x) (((x) >> S_TIMEUNIT) & M_TIMEUNIT)
39735 
39736 #define A_MPS_PORT_TX_PAUSE_CTL 0x8
39737 
39738 #define S_REGSENDOFF    24
39739 #define M_REGSENDOFF    0xffU
39740 #define V_REGSENDOFF(x) ((x) << S_REGSENDOFF)
39741 #define G_REGSENDOFF(x) (((x) >> S_REGSENDOFF) & M_REGSENDOFF)
39742 
39743 #define S_REGSENDON    16
39744 #define M_REGSENDON    0xffU
39745 #define V_REGSENDON(x) ((x) << S_REGSENDON)
39746 #define G_REGSENDON(x) (((x) >> S_REGSENDON) & M_REGSENDON)
39747 
39748 #define S_SGESENDEN    8
39749 #define M_SGESENDEN    0xffU
39750 #define V_SGESENDEN(x) ((x) << S_SGESENDEN)
39751 #define G_SGESENDEN(x) (((x) >> S_SGESENDEN) & M_SGESENDEN)
39752 
39753 #define S_RXSENDEN    0
39754 #define M_RXSENDEN    0xffU
39755 #define V_RXSENDEN(x) ((x) << S_RXSENDEN)
39756 #define G_RXSENDEN(x) (((x) >> S_RXSENDEN) & M_RXSENDEN)
39757 
39758 #define A_MPS_PORT_TX_PAUSE_CTL2 0xc
39759 
39760 #define S_XOFFDISABLE    0
39761 #define V_XOFFDISABLE(x) ((x) << S_XOFFDISABLE)
39762 #define F_XOFFDISABLE    V_XOFFDISABLE(1U)
39763 
39764 #define A_MPS_PORT_RX_PAUSE_CTL 0x10
39765 
39766 #define S_REGHALTON    8
39767 #define M_REGHALTON    0xffU
39768 #define V_REGHALTON(x) ((x) << S_REGHALTON)
39769 #define G_REGHALTON(x) (((x) >> S_REGHALTON) & M_REGHALTON)
39770 
39771 #define S_RXHALTEN    0
39772 #define M_RXHALTEN    0xffU
39773 #define V_RXHALTEN(x) ((x) << S_RXHALTEN)
39774 #define G_RXHALTEN(x) (((x) >> S_RXHALTEN) & M_RXHALTEN)
39775 
39776 #define A_MPS_PORT_TX_PAUSE_STATUS 0x14
39777 
39778 #define S_REGSENDING    16
39779 #define M_REGSENDING    0xffU
39780 #define V_REGSENDING(x) ((x) << S_REGSENDING)
39781 #define G_REGSENDING(x) (((x) >> S_REGSENDING) & M_REGSENDING)
39782 
39783 #define S_SGESENDING    8
39784 #define M_SGESENDING    0xffU
39785 #define V_SGESENDING(x) ((x) << S_SGESENDING)
39786 #define G_SGESENDING(x) (((x) >> S_SGESENDING) & M_SGESENDING)
39787 
39788 #define S_RXSENDING    0
39789 #define M_RXSENDING    0xffU
39790 #define V_RXSENDING(x) ((x) << S_RXSENDING)
39791 #define G_RXSENDING(x) (((x) >> S_RXSENDING) & M_RXSENDING)
39792 
39793 #define A_MPS_PORT_RX_PAUSE_STATUS 0x18
39794 
39795 #define S_REGHALTED    8
39796 #define M_REGHALTED    0xffU
39797 #define V_REGHALTED(x) ((x) << S_REGHALTED)
39798 #define G_REGHALTED(x) (((x) >> S_REGHALTED) & M_REGHALTED)
39799 
39800 #define S_RXHALTED    0
39801 #define M_RXHALTED    0xffU
39802 #define V_RXHALTED(x) ((x) << S_RXHALTED)
39803 #define G_RXHALTED(x) (((x) >> S_RXHALTED) & M_RXHALTED)
39804 
39805 #define A_MPS_PORT_TX_PAUSE_DEST_L 0x1c
39806 #define A_MPS_PORT_TX_PAUSE_DEST_H 0x20
39807 
39808 #define S_ADDR    0
39809 #define M_ADDR    0xffffU
39810 #define V_ADDR(x) ((x) << S_ADDR)
39811 #define G_ADDR(x) (((x) >> S_ADDR) & M_ADDR)
39812 
39813 #define A_MPS_PORT_TX_PAUSE_SOURCE_L 0x24
39814 #define A_MPS_VF_TX_MAC_DROP_PP 0x24
39815 #define A_MPS_PORT_TX_PAUSE_SOURCE_H 0x28
39816 #define A_MPS_PORT_PRTY_BUFFER_GROUP_MAP 0x2c
39817 
39818 #define S_PRTY7    14
39819 #define M_PRTY7    0x3U
39820 #define V_PRTY7(x) ((x) << S_PRTY7)
39821 #define G_PRTY7(x) (((x) >> S_PRTY7) & M_PRTY7)
39822 
39823 #define S_PRTY6    12
39824 #define M_PRTY6    0x3U
39825 #define V_PRTY6(x) ((x) << S_PRTY6)
39826 #define G_PRTY6(x) (((x) >> S_PRTY6) & M_PRTY6)
39827 
39828 #define S_PRTY5    10
39829 #define M_PRTY5    0x3U
39830 #define V_PRTY5(x) ((x) << S_PRTY5)
39831 #define G_PRTY5(x) (((x) >> S_PRTY5) & M_PRTY5)
39832 
39833 #define S_PRTY4    8
39834 #define M_PRTY4    0x3U
39835 #define V_PRTY4(x) ((x) << S_PRTY4)
39836 #define G_PRTY4(x) (((x) >> S_PRTY4) & M_PRTY4)
39837 
39838 #define S_PRTY3    6
39839 #define M_PRTY3    0x3U
39840 #define V_PRTY3(x) ((x) << S_PRTY3)
39841 #define G_PRTY3(x) (((x) >> S_PRTY3) & M_PRTY3)
39842 
39843 #define S_PRTY2    4
39844 #define M_PRTY2    0x3U
39845 #define V_PRTY2(x) ((x) << S_PRTY2)
39846 #define G_PRTY2(x) (((x) >> S_PRTY2) & M_PRTY2)
39847 
39848 #define S_PRTY1    2
39849 #define M_PRTY1    0x3U
39850 #define V_PRTY1(x) ((x) << S_PRTY1)
39851 #define G_PRTY1(x) (((x) >> S_PRTY1) & M_PRTY1)
39852 
39853 #define S_PRTY0    0
39854 #define M_PRTY0    0x3U
39855 #define V_PRTY0(x) ((x) << S_PRTY0)
39856 #define G_PRTY0(x) (((x) >> S_PRTY0) & M_PRTY0)
39857 
39858 #define A_MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP 0x30
39859 
39860 #define S_TXPRTY7    28
39861 #define M_TXPRTY7    0xfU
39862 #define V_TXPRTY7(x) ((x) << S_TXPRTY7)
39863 #define G_TXPRTY7(x) (((x) >> S_TXPRTY7) & M_TXPRTY7)
39864 
39865 #define S_TXPRTY6    24
39866 #define M_TXPRTY6    0xfU
39867 #define V_TXPRTY6(x) ((x) << S_TXPRTY6)
39868 #define G_TXPRTY6(x) (((x) >> S_TXPRTY6) & M_TXPRTY6)
39869 
39870 #define S_TXPRTY5    20
39871 #define M_TXPRTY5    0xfU
39872 #define V_TXPRTY5(x) ((x) << S_TXPRTY5)
39873 #define G_TXPRTY5(x) (((x) >> S_TXPRTY5) & M_TXPRTY5)
39874 
39875 #define S_TXPRTY4    16
39876 #define M_TXPRTY4    0xfU
39877 #define V_TXPRTY4(x) ((x) << S_TXPRTY4)
39878 #define G_TXPRTY4(x) (((x) >> S_TXPRTY4) & M_TXPRTY4)
39879 
39880 #define S_TXPRTY3    12
39881 #define M_TXPRTY3    0xfU
39882 #define V_TXPRTY3(x) ((x) << S_TXPRTY3)
39883 #define G_TXPRTY3(x) (((x) >> S_TXPRTY3) & M_TXPRTY3)
39884 
39885 #define S_TXPRTY2    8
39886 #define M_TXPRTY2    0xfU
39887 #define V_TXPRTY2(x) ((x) << S_TXPRTY2)
39888 #define G_TXPRTY2(x) (((x) >> S_TXPRTY2) & M_TXPRTY2)
39889 
39890 #define S_TXPRTY1    4
39891 #define M_TXPRTY1    0xfU
39892 #define V_TXPRTY1(x) ((x) << S_TXPRTY1)
39893 #define G_TXPRTY1(x) (((x) >> S_TXPRTY1) & M_TXPRTY1)
39894 
39895 #define S_TXPRTY0    0
39896 #define M_TXPRTY0    0xfU
39897 #define V_TXPRTY0(x) ((x) << S_TXPRTY0)
39898 #define G_TXPRTY0(x) (((x) >> S_TXPRTY0) & M_TXPRTY0)
39899 
39900 #define A_MPS_PORT_PRTY_GROUP_MAP 0x34
39901 #define A_MPS_PORT_TRACE_MAX_CAPTURE_SIZE 0x38
39902 
39903 #define S_TX2RX    6
39904 #define M_TX2RX    0x7U
39905 #define V_TX2RX(x) ((x) << S_TX2RX)
39906 #define G_TX2RX(x) (((x) >> S_TX2RX) & M_TX2RX)
39907 
39908 #define S_MAC2MPS    3
39909 #define M_MAC2MPS    0x7U
39910 #define V_MAC2MPS(x) ((x) << S_MAC2MPS)
39911 #define G_MAC2MPS(x) (((x) >> S_MAC2MPS) & M_MAC2MPS)
39912 
39913 #define S_MPS2MAC    0
39914 #define M_MPS2MAC    0x7U
39915 #define V_MPS2MAC(x) ((x) << S_MPS2MAC)
39916 #define G_MPS2MAC(x) (((x) >> S_MPS2MAC) & M_MPS2MAC)
39917 
39918 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L 0x80
39919 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_H 0x84
39920 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_L 0x88
39921 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_H 0x8c
39922 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_L 0x90
39923 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_H 0x94
39924 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_L 0x98
39925 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_H 0x9c
39926 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_L 0xa0
39927 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_H 0xa4
39928 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_L 0xa8
39929 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_H 0xac
39930 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_L 0xb0
39931 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_H 0xb4
39932 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_L 0xb8
39933 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_H 0xbc
39934 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_L 0xc0
39935 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_H 0xc4
39936 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_L 0xc8
39937 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_H 0xcc
39938 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_L 0xd0
39939 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_H 0xd4
39940 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_L 0xd8
39941 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_H 0xdc
39942 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_L 0xe0
39943 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_H 0xe4
39944 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_L 0xe8
39945 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_H 0xec
39946 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_L 0xf0
39947 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_H 0xf4
39948 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_L 0xf8
39949 #define A_MPS_VF_STAT_RX_VF_ERR_DROP_FRAMES_L 0xf8
39950 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H 0xfc
39951 #define A_MPS_VF_STAT_RX_VF_ERR_DROP_FRAMES_H 0xfc
39952 #define A_MPS_PORT_RX_CTL 0x100
39953 
39954 #define S_NO_RPLCT_M    20
39955 #define V_NO_RPLCT_M(x) ((x) << S_NO_RPLCT_M)
39956 #define F_NO_RPLCT_M    V_NO_RPLCT_M(1U)
39957 
39958 #define S_RPLCT_SEL_L    18
39959 #define M_RPLCT_SEL_L    0x3U
39960 #define V_RPLCT_SEL_L(x) ((x) << S_RPLCT_SEL_L)
39961 #define G_RPLCT_SEL_L(x) (((x) >> S_RPLCT_SEL_L) & M_RPLCT_SEL_L)
39962 
39963 #define S_FLTR_VLAN_SEL    17
39964 #define V_FLTR_VLAN_SEL(x) ((x) << S_FLTR_VLAN_SEL)
39965 #define F_FLTR_VLAN_SEL    V_FLTR_VLAN_SEL(1U)
39966 
39967 #define S_PRIO_VLAN_SEL    16
39968 #define V_PRIO_VLAN_SEL(x) ((x) << S_PRIO_VLAN_SEL)
39969 #define F_PRIO_VLAN_SEL    V_PRIO_VLAN_SEL(1U)
39970 
39971 #define S_CHK_8023_LEN_M    15
39972 #define V_CHK_8023_LEN_M(x) ((x) << S_CHK_8023_LEN_M)
39973 #define F_CHK_8023_LEN_M    V_CHK_8023_LEN_M(1U)
39974 
39975 #define S_CHK_8023_LEN_L    14
39976 #define V_CHK_8023_LEN_L(x) ((x) << S_CHK_8023_LEN_L)
39977 #define F_CHK_8023_LEN_L    V_CHK_8023_LEN_L(1U)
39978 
39979 #define S_NIV_DROP    13
39980 #define V_NIV_DROP(x) ((x) << S_NIV_DROP)
39981 #define F_NIV_DROP    V_NIV_DROP(1U)
39982 
39983 #define S_NOV_DROP    12
39984 #define V_NOV_DROP(x) ((x) << S_NOV_DROP)
39985 #define F_NOV_DROP    V_NOV_DROP(1U)
39986 
39987 #define S_CLS_PRT    11
39988 #define V_CLS_PRT(x) ((x) << S_CLS_PRT)
39989 #define F_CLS_PRT    V_CLS_PRT(1U)
39990 
39991 #define S_RX_QFC_EN    10
39992 #define V_RX_QFC_EN(x) ((x) << S_RX_QFC_EN)
39993 #define F_RX_QFC_EN    V_RX_QFC_EN(1U)
39994 
39995 #define S_QFC_FWD_UP    9
39996 #define V_QFC_FWD_UP(x) ((x) << S_QFC_FWD_UP)
39997 #define F_QFC_FWD_UP    V_QFC_FWD_UP(1U)
39998 
39999 #define S_PPP_FWD_UP    8
40000 #define V_PPP_FWD_UP(x) ((x) << S_PPP_FWD_UP)
40001 #define F_PPP_FWD_UP    V_PPP_FWD_UP(1U)
40002 
40003 #define S_PAUSE_FWD_UP    7
40004 #define V_PAUSE_FWD_UP(x) ((x) << S_PAUSE_FWD_UP)
40005 #define F_PAUSE_FWD_UP    V_PAUSE_FWD_UP(1U)
40006 
40007 #define S_LPBK_BP    6
40008 #define V_LPBK_BP(x) ((x) << S_LPBK_BP)
40009 #define F_LPBK_BP    V_LPBK_BP(1U)
40010 
40011 #define S_PASS_NO_MATCH    5
40012 #define V_PASS_NO_MATCH(x) ((x) << S_PASS_NO_MATCH)
40013 #define F_PASS_NO_MATCH    V_PASS_NO_MATCH(1U)
40014 
40015 #define S_IVLAN_EN    4
40016 #define V_IVLAN_EN(x) ((x) << S_IVLAN_EN)
40017 #define F_IVLAN_EN    V_IVLAN_EN(1U)
40018 
40019 #define S_OVLAN_EN3    3
40020 #define V_OVLAN_EN3(x) ((x) << S_OVLAN_EN3)
40021 #define F_OVLAN_EN3    V_OVLAN_EN3(1U)
40022 
40023 #define S_OVLAN_EN2    2
40024 #define V_OVLAN_EN2(x) ((x) << S_OVLAN_EN2)
40025 #define F_OVLAN_EN2    V_OVLAN_EN2(1U)
40026 
40027 #define S_OVLAN_EN1    1
40028 #define V_OVLAN_EN1(x) ((x) << S_OVLAN_EN1)
40029 #define F_OVLAN_EN1    V_OVLAN_EN1(1U)
40030 
40031 #define S_OVLAN_EN0    0
40032 #define V_OVLAN_EN0(x) ((x) << S_OVLAN_EN0)
40033 #define F_OVLAN_EN0    V_OVLAN_EN0(1U)
40034 
40035 #define S_PTP_FWD_UP    21
40036 #define V_PTP_FWD_UP(x) ((x) << S_PTP_FWD_UP)
40037 #define F_PTP_FWD_UP    V_PTP_FWD_UP(1U)
40038 
40039 #define S_HASH_PRIO_SEL_LPBK    25
40040 #define V_HASH_PRIO_SEL_LPBK(x) ((x) << S_HASH_PRIO_SEL_LPBK)
40041 #define F_HASH_PRIO_SEL_LPBK    V_HASH_PRIO_SEL_LPBK(1U)
40042 
40043 #define S_HASH_PRIO_SEL_MAC    24
40044 #define V_HASH_PRIO_SEL_MAC(x) ((x) << S_HASH_PRIO_SEL_MAC)
40045 #define F_HASH_PRIO_SEL_MAC    V_HASH_PRIO_SEL_MAC(1U)
40046 
40047 #define S_HASH_EN_LPBK    23
40048 #define V_HASH_EN_LPBK(x) ((x) << S_HASH_EN_LPBK)
40049 #define F_HASH_EN_LPBK    V_HASH_EN_LPBK(1U)
40050 
40051 #define S_HASH_EN_MAC    22
40052 #define V_HASH_EN_MAC(x) ((x) << S_HASH_EN_MAC)
40053 #define F_HASH_EN_MAC    V_HASH_EN_MAC(1U)
40054 
40055 #define S_TRANS_ENCAP_EN    30
40056 #define V_TRANS_ENCAP_EN(x) ((x) << S_TRANS_ENCAP_EN)
40057 #define F_TRANS_ENCAP_EN    V_TRANS_ENCAP_EN(1U)
40058 
40059 #define S_CRYPTO_DUMMY_PKT_CHK_EN    29
40060 #define V_CRYPTO_DUMMY_PKT_CHK_EN(x) ((x) << S_CRYPTO_DUMMY_PKT_CHK_EN)
40061 #define F_CRYPTO_DUMMY_PKT_CHK_EN    V_CRYPTO_DUMMY_PKT_CHK_EN(1U)
40062 
40063 #define S_PASS_HPROM    28
40064 #define V_PASS_HPROM(x) ((x) << S_PASS_HPROM)
40065 #define F_PASS_HPROM    V_PASS_HPROM(1U)
40066 
40067 #define S_PASS_PROM    27
40068 #define V_PASS_PROM(x) ((x) << S_PASS_PROM)
40069 #define F_PASS_PROM    V_PASS_PROM(1U)
40070 
40071 #define S_ENCAP_ONLY_IF_OUTER_HIT    26
40072 #define V_ENCAP_ONLY_IF_OUTER_HIT(x) ((x) << S_ENCAP_ONLY_IF_OUTER_HIT)
40073 #define F_ENCAP_ONLY_IF_OUTER_HIT    V_ENCAP_ONLY_IF_OUTER_HIT(1U)
40074 
40075 #define A_MPS_PORT_RX_MTU 0x104
40076 #define A_MPS_PORT_RX_PF_MAP 0x108
40077 #define A_MPS_PORT_RX_VF_MAP0 0x10c
40078 #define A_MPS_PORT_RX_VF_MAP1 0x110
40079 #define A_MPS_PORT_RX_VF_MAP2 0x114
40080 #define A_MPS_PORT_RX_VF_MAP3 0x118
40081 #define A_MPS_PORT_RX_IVLAN 0x11c
40082 
40083 #define S_IVLAN_ETYPE    0
40084 #define M_IVLAN_ETYPE    0xffffU
40085 #define V_IVLAN_ETYPE(x) ((x) << S_IVLAN_ETYPE)
40086 #define G_IVLAN_ETYPE(x) (((x) >> S_IVLAN_ETYPE) & M_IVLAN_ETYPE)
40087 
40088 #define A_MPS_PORT_RX_OVLAN0 0x120
40089 
40090 #define S_OVLAN_MASK    16
40091 #define M_OVLAN_MASK    0xffffU
40092 #define V_OVLAN_MASK(x) ((x) << S_OVLAN_MASK)
40093 #define G_OVLAN_MASK(x) (((x) >> S_OVLAN_MASK) & M_OVLAN_MASK)
40094 
40095 #define S_OVLAN_ETYPE    0
40096 #define M_OVLAN_ETYPE    0xffffU
40097 #define V_OVLAN_ETYPE(x) ((x) << S_OVLAN_ETYPE)
40098 #define G_OVLAN_ETYPE(x) (((x) >> S_OVLAN_ETYPE) & M_OVLAN_ETYPE)
40099 
40100 #define A_MPS_PORT_RX_OVLAN1 0x124
40101 #define A_MPS_PORT_RX_OVLAN2 0x128
40102 #define A_MPS_PORT_RX_OVLAN3 0x12c
40103 #define A_MPS_PORT_RX_RSS_HASH 0x130
40104 #define A_MPS_PORT_RX_RSS_CONTROL 0x134
40105 
40106 #define S_RSS_CTRL    16
40107 #define M_RSS_CTRL    0xffU
40108 #define V_RSS_CTRL(x) ((x) << S_RSS_CTRL)
40109 #define G_RSS_CTRL(x) (((x) >> S_RSS_CTRL) & M_RSS_CTRL)
40110 
40111 #define S_QUE_NUM    0
40112 #define M_QUE_NUM    0xffffU
40113 #define V_QUE_NUM(x) ((x) << S_QUE_NUM)
40114 #define G_QUE_NUM(x) (((x) >> S_QUE_NUM) & M_QUE_NUM)
40115 
40116 #define A_MPS_PORT_RX_CTL1 0x138
40117 
40118 #define S_FIXED_PFVF_MAC    13
40119 #define V_FIXED_PFVF_MAC(x) ((x) << S_FIXED_PFVF_MAC)
40120 #define F_FIXED_PFVF_MAC    V_FIXED_PFVF_MAC(1U)
40121 
40122 #define S_FIXED_PFVF_LPBK    12
40123 #define V_FIXED_PFVF_LPBK(x) ((x) << S_FIXED_PFVF_LPBK)
40124 #define F_FIXED_PFVF_LPBK    V_FIXED_PFVF_LPBK(1U)
40125 
40126 #define S_FIXED_PFVF_LPBK_OV    11
40127 #define V_FIXED_PFVF_LPBK_OV(x) ((x) << S_FIXED_PFVF_LPBK_OV)
40128 #define F_FIXED_PFVF_LPBK_OV    V_FIXED_PFVF_LPBK_OV(1U)
40129 
40130 #define S_FIXED_PF    8
40131 #define M_FIXED_PF    0x7U
40132 #define V_FIXED_PF(x) ((x) << S_FIXED_PF)
40133 #define G_FIXED_PF(x) (((x) >> S_FIXED_PF) & M_FIXED_PF)
40134 
40135 #define S_FIXED_VF_VLD    7
40136 #define V_FIXED_VF_VLD(x) ((x) << S_FIXED_VF_VLD)
40137 #define F_FIXED_VF_VLD    V_FIXED_VF_VLD(1U)
40138 
40139 #define S_FIXED_VF    0
40140 #define M_FIXED_VF    0x7fU
40141 #define V_FIXED_VF(x) ((x) << S_FIXED_VF)
40142 #define G_FIXED_VF(x) (((x) >> S_FIXED_VF) & M_FIXED_VF)
40143 
40144 #define S_T6_FIXED_PFVF_MAC    14
40145 #define V_T6_FIXED_PFVF_MAC(x) ((x) << S_T6_FIXED_PFVF_MAC)
40146 #define F_T6_FIXED_PFVF_MAC    V_T6_FIXED_PFVF_MAC(1U)
40147 
40148 #define S_T6_FIXED_PFVF_LPBK    13
40149 #define V_T6_FIXED_PFVF_LPBK(x) ((x) << S_T6_FIXED_PFVF_LPBK)
40150 #define F_T6_FIXED_PFVF_LPBK    V_T6_FIXED_PFVF_LPBK(1U)
40151 
40152 #define S_T6_FIXED_PFVF_LPBK_OV    12
40153 #define V_T6_FIXED_PFVF_LPBK_OV(x) ((x) << S_T6_FIXED_PFVF_LPBK_OV)
40154 #define F_T6_FIXED_PFVF_LPBK_OV    V_T6_FIXED_PFVF_LPBK_OV(1U)
40155 
40156 #define S_T6_FIXED_PF    9
40157 #define M_T6_FIXED_PF    0x7U
40158 #define V_T6_FIXED_PF(x) ((x) << S_T6_FIXED_PF)
40159 #define G_T6_FIXED_PF(x) (((x) >> S_T6_FIXED_PF) & M_T6_FIXED_PF)
40160 
40161 #define S_T6_FIXED_VF_VLD    8
40162 #define V_T6_FIXED_VF_VLD(x) ((x) << S_T6_FIXED_VF_VLD)
40163 #define F_T6_FIXED_VF_VLD    V_T6_FIXED_VF_VLD(1U)
40164 
40165 #define S_T6_FIXED_VF    0
40166 #define M_T6_FIXED_VF    0xffU
40167 #define V_T6_FIXED_VF(x) ((x) << S_T6_FIXED_VF)
40168 #define G_T6_FIXED_VF(x) (((x) >> S_T6_FIXED_VF) & M_T6_FIXED_VF)
40169 
40170 #define A_MPS_PORT_RX_SPARE 0x13c
40171 #define A_MPS_PORT_RX_PTP_RSS_HASH 0x140
40172 #define A_MPS_PORT_RX_PTP_RSS_CONTROL 0x144
40173 #define A_MPS_PORT_RX_TS_VLD 0x148
40174 
40175 #define S_TS_VLD    0
40176 #define M_TS_VLD    0x3U
40177 #define V_TS_VLD(x) ((x) << S_TS_VLD)
40178 #define G_TS_VLD(x) (((x) >> S_TS_VLD) & M_TS_VLD)
40179 
40180 #define A_MPS_PORT_RX_TNL_LKP_INNER_SEL 0x14c
40181 
40182 #define S_LKP_SEL    0
40183 #define V_LKP_SEL(x) ((x) << S_LKP_SEL)
40184 #define F_LKP_SEL    V_LKP_SEL(1U)
40185 
40186 #define A_MPS_PORT_RX_VF_MAP4 0x150
40187 #define A_MPS_PORT_RX_VF_MAP5 0x154
40188 #define A_MPS_PORT_RX_VF_MAP6 0x158
40189 #define A_MPS_PORT_RX_VF_MAP7 0x15c
40190 #define A_MPS_PORT_RX_PRS_DEBUG_FLAG_MAC 0x160
40191 
40192 #define S_OUTER_IPV4_N_INNER_IPV4    31
40193 #define V_OUTER_IPV4_N_INNER_IPV4(x) ((x) << S_OUTER_IPV4_N_INNER_IPV4)
40194 #define F_OUTER_IPV4_N_INNER_IPV4    V_OUTER_IPV4_N_INNER_IPV4(1U)
40195 
40196 #define S_OUTER_IPV4_N_INNER_IPV6    30
40197 #define V_OUTER_IPV4_N_INNER_IPV6(x) ((x) << S_OUTER_IPV4_N_INNER_IPV6)
40198 #define F_OUTER_IPV4_N_INNER_IPV6    V_OUTER_IPV4_N_INNER_IPV6(1U)
40199 
40200 #define S_OUTER_IPV6_N_INNER_IPV4    29
40201 #define V_OUTER_IPV6_N_INNER_IPV4(x) ((x) << S_OUTER_IPV6_N_INNER_IPV4)
40202 #define F_OUTER_IPV6_N_INNER_IPV4    V_OUTER_IPV6_N_INNER_IPV4(1U)
40203 
40204 #define S_OUTER_IPV6_N_INNER_IPV6    28
40205 #define V_OUTER_IPV6_N_INNER_IPV6(x) ((x) << S_OUTER_IPV6_N_INNER_IPV6)
40206 #define F_OUTER_IPV6_N_INNER_IPV6    V_OUTER_IPV6_N_INNER_IPV6(1U)
40207 
40208 #define S_OUTER_IPV4_N_VLAN_NVGRE    27
40209 #define V_OUTER_IPV4_N_VLAN_NVGRE(x) ((x) << S_OUTER_IPV4_N_VLAN_NVGRE)
40210 #define F_OUTER_IPV4_N_VLAN_NVGRE    V_OUTER_IPV4_N_VLAN_NVGRE(1U)
40211 
40212 #define S_OUTER_IPV6_N_VLAN_NVGRE    26
40213 #define V_OUTER_IPV6_N_VLAN_NVGRE(x) ((x) << S_OUTER_IPV6_N_VLAN_NVGRE)
40214 #define F_OUTER_IPV6_N_VLAN_NVGRE    V_OUTER_IPV6_N_VLAN_NVGRE(1U)
40215 
40216 #define S_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE    25
40217 #define V_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE)
40218 #define F_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE    V_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE(1U)
40219 
40220 #define S_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE    24
40221 #define V_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE)
40222 #define F_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE    V_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE(1U)
40223 
40224 #define S_OUTER_IPV4_N_VLAN_GRE    23
40225 #define V_OUTER_IPV4_N_VLAN_GRE(x) ((x) << S_OUTER_IPV4_N_VLAN_GRE)
40226 #define F_OUTER_IPV4_N_VLAN_GRE    V_OUTER_IPV4_N_VLAN_GRE(1U)
40227 
40228 #define S_OUTER_IPV6_N_VLAN_GRE    22
40229 #define V_OUTER_IPV6_N_VLAN_GRE(x) ((x) << S_OUTER_IPV6_N_VLAN_GRE)
40230 #define F_OUTER_IPV6_N_VLAN_GRE    V_OUTER_IPV6_N_VLAN_GRE(1U)
40231 
40232 #define S_OUTER_IPV4_N_DOUBLE_VLAN_GRE    21
40233 #define V_OUTER_IPV4_N_DOUBLE_VLAN_GRE(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_GRE)
40234 #define F_OUTER_IPV4_N_DOUBLE_VLAN_GRE    V_OUTER_IPV4_N_DOUBLE_VLAN_GRE(1U)
40235 
40236 #define S_OUTER_IPV6_N_DOUBLE_VLAN_GRE    20
40237 #define V_OUTER_IPV6_N_DOUBLE_VLAN_GRE(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_GRE)
40238 #define F_OUTER_IPV6_N_DOUBLE_VLAN_GRE    V_OUTER_IPV6_N_DOUBLE_VLAN_GRE(1U)
40239 
40240 #define S_OUTER_IPV4_N_VLAN_VXLAN    19
40241 #define V_OUTER_IPV4_N_VLAN_VXLAN(x) ((x) << S_OUTER_IPV4_N_VLAN_VXLAN)
40242 #define F_OUTER_IPV4_N_VLAN_VXLAN    V_OUTER_IPV4_N_VLAN_VXLAN(1U)
40243 
40244 #define S_OUTER_IPV6_N_VLAN_VXLAN    18
40245 #define V_OUTER_IPV6_N_VLAN_VXLAN(x) ((x) << S_OUTER_IPV6_N_VLAN_VXLAN)
40246 #define F_OUTER_IPV6_N_VLAN_VXLAN    V_OUTER_IPV6_N_VLAN_VXLAN(1U)
40247 
40248 #define S_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN    17
40249 #define V_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN)
40250 #define F_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN    V_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN(1U)
40251 
40252 #define S_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN    16
40253 #define V_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN)
40254 #define F_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN    V_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN(1U)
40255 
40256 #define S_OUTER_IPV4_N_VLAN_GENEVE    15
40257 #define V_OUTER_IPV4_N_VLAN_GENEVE(x) ((x) << S_OUTER_IPV4_N_VLAN_GENEVE)
40258 #define F_OUTER_IPV4_N_VLAN_GENEVE    V_OUTER_IPV4_N_VLAN_GENEVE(1U)
40259 
40260 #define S_OUTER_IPV6_N_VLAN_GENEVE    14
40261 #define V_OUTER_IPV6_N_VLAN_GENEVE(x) ((x) << S_OUTER_IPV6_N_VLAN_GENEVE)
40262 #define F_OUTER_IPV6_N_VLAN_GENEVE    V_OUTER_IPV6_N_VLAN_GENEVE(1U)
40263 
40264 #define S_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE    13
40265 #define V_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE)
40266 #define F_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE    V_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE(1U)
40267 
40268 #define S_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE    12
40269 #define V_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE)
40270 #define F_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE    V_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE(1U)
40271 
40272 #define S_ERR_TNL_HDR_LEN    11
40273 #define V_ERR_TNL_HDR_LEN(x) ((x) << S_ERR_TNL_HDR_LEN)
40274 #define F_ERR_TNL_HDR_LEN    V_ERR_TNL_HDR_LEN(1U)
40275 
40276 #define S_NON_RUNT_FRAME    10
40277 #define V_NON_RUNT_FRAME(x) ((x) << S_NON_RUNT_FRAME)
40278 #define F_NON_RUNT_FRAME    V_NON_RUNT_FRAME(1U)
40279 
40280 #define S_INNER_VLAN_VLD    9
40281 #define V_INNER_VLAN_VLD(x) ((x) << S_INNER_VLAN_VLD)
40282 #define F_INNER_VLAN_VLD    V_INNER_VLAN_VLD(1U)
40283 
40284 #define S_ERR_IP_PAYLOAD_LEN    8
40285 #define V_ERR_IP_PAYLOAD_LEN(x) ((x) << S_ERR_IP_PAYLOAD_LEN)
40286 #define F_ERR_IP_PAYLOAD_LEN    V_ERR_IP_PAYLOAD_LEN(1U)
40287 
40288 #define S_ERR_UDP_PAYLOAD_LEN    7
40289 #define V_ERR_UDP_PAYLOAD_LEN(x) ((x) << S_ERR_UDP_PAYLOAD_LEN)
40290 #define F_ERR_UDP_PAYLOAD_LEN    V_ERR_UDP_PAYLOAD_LEN(1U)
40291 
40292 #define A_MPS_PORT_RX_PRS_DEBUG_FLAG_LPBK 0x164
40293 
40294 #define S_T6_INNER_VLAN_VLD    10
40295 #define V_T6_INNER_VLAN_VLD(x) ((x) << S_T6_INNER_VLAN_VLD)
40296 #define F_T6_INNER_VLAN_VLD    V_T6_INNER_VLAN_VLD(1U)
40297 
40298 #define S_T6_ERR_IP_PAYLOAD_LEN    9
40299 #define V_T6_ERR_IP_PAYLOAD_LEN(x) ((x) << S_T6_ERR_IP_PAYLOAD_LEN)
40300 #define F_T6_ERR_IP_PAYLOAD_LEN    V_T6_ERR_IP_PAYLOAD_LEN(1U)
40301 
40302 #define S_T6_ERR_UDP_PAYLOAD_LEN    8
40303 #define V_T6_ERR_UDP_PAYLOAD_LEN(x) ((x) << S_T6_ERR_UDP_PAYLOAD_LEN)
40304 #define F_T6_ERR_UDP_PAYLOAD_LEN    V_T6_ERR_UDP_PAYLOAD_LEN(1U)
40305 
40306 #define A_MPS_PORT_RX_REPL_VECT_SEL 0x168
40307 
40308 #define S_DIS_REPL_VECT_SEL    4
40309 #define V_DIS_REPL_VECT_SEL(x) ((x) << S_DIS_REPL_VECT_SEL)
40310 #define F_DIS_REPL_VECT_SEL    V_DIS_REPL_VECT_SEL(1U)
40311 
40312 #define S_REPL_VECT_SEL    0
40313 #define M_REPL_VECT_SEL    0xfU
40314 #define V_REPL_VECT_SEL(x) ((x) << S_REPL_VECT_SEL)
40315 #define G_REPL_VECT_SEL(x) (((x) >> S_REPL_VECT_SEL) & M_REPL_VECT_SEL)
40316 
40317 #define A_MPS_PORT_MAC_RX_DROP_EN_PP 0x16c
40318 
40319 #define S_PRIO    0
40320 #define M_PRIO    0xffU
40321 #define V_PRIO(x) ((x) << S_PRIO)
40322 #define G_PRIO(x) (((x) >> S_PRIO) & M_PRIO)
40323 
40324 #define A_MPS_PORT_RX_INT_RSS_HASH 0x170
40325 #define A_MPS_PORT_RX_INT_RSS_CONTROL 0x174
40326 #define A_MPS_PORT_RX_CNT_DBG_CTL 0x178
40327 
40328 #define S_DBG_TYPE    0
40329 #define M_DBG_TYPE    0x1fU
40330 #define V_DBG_TYPE(x) ((x) << S_DBG_TYPE)
40331 #define G_DBG_TYPE(x) (((x) >> S_DBG_TYPE) & M_DBG_TYPE)
40332 
40333 #define A_MPS_PORT_RX_CNT_DBG 0x17c
40334 #define A_MPS_PORT_TX_MAC_RELOAD_CH0 0x190
40335 
40336 #define S_CREDIT    0
40337 #define M_CREDIT    0xffffU
40338 #define V_CREDIT(x) ((x) << S_CREDIT)
40339 #define G_CREDIT(x) (((x) >> S_CREDIT) & M_CREDIT)
40340 
40341 #define A_MPS_PORT_TX_MAC_RELOAD_CH1 0x194
40342 #define A_MPS_PORT_TX_MAC_RELOAD_CH2 0x198
40343 #define A_MPS_PORT_TX_MAC_RELOAD_CH3 0x19c
40344 #define A_MPS_PORT_TX_MAC_RELOAD_CH4 0x1a0
40345 #define A_MPS_PORT_TX_LPBK_RELOAD_CH0 0x1a8
40346 #define A_MPS_PORT_TX_LPBK_RELOAD_CH1 0x1ac
40347 #define A_MPS_PORT_TX_LPBK_RELOAD_CH2 0x1b0
40348 #define A_MPS_PORT_TX_LPBK_RELOAD_CH3 0x1b4
40349 #define A_MPS_PORT_TX_LPBK_RELOAD_CH4 0x1b8
40350 #define A_MPS_PORT_TX_FIFO_CTL 0x1c4
40351 
40352 #define S_FIFOTH    5
40353 #define M_FIFOTH    0x1ffU
40354 #define V_FIFOTH(x) ((x) << S_FIFOTH)
40355 #define G_FIFOTH(x) (((x) >> S_FIFOTH) & M_FIFOTH)
40356 
40357 #define S_FIFOEN    4
40358 #define V_FIFOEN(x) ((x) << S_FIFOEN)
40359 #define F_FIFOEN    V_FIFOEN(1U)
40360 
40361 #define S_MAXPKTCNT    0
40362 #define M_MAXPKTCNT    0xfU
40363 #define V_MAXPKTCNT(x) ((x) << S_MAXPKTCNT)
40364 #define G_MAXPKTCNT(x) (((x) >> S_MAXPKTCNT) & M_MAXPKTCNT)
40365 
40366 #define S_OUT_TH    22
40367 #define M_OUT_TH    0xffU
40368 #define V_OUT_TH(x) ((x) << S_OUT_TH)
40369 #define G_OUT_TH(x) (((x) >> S_OUT_TH) & M_OUT_TH)
40370 
40371 #define S_IN_TH    14
40372 #define M_IN_TH    0xffU
40373 #define V_IN_TH(x) ((x) << S_IN_TH)
40374 #define G_IN_TH(x) (((x) >> S_IN_TH) & M_IN_TH)
40375 
40376 #define A_MPS_PORT_FPGA_PAUSE_CTL 0x1c8
40377 
40378 #define S_FPGAPAUSEEN    0
40379 #define V_FPGAPAUSEEN(x) ((x) << S_FPGAPAUSEEN)
40380 #define F_FPGAPAUSEEN    V_FPGAPAUSEEN(1U)
40381 
40382 #define A_MPS_PORT_TX_PAUSE_PENDING_STATUS 0x1d0
40383 
40384 #define S_OFF_PENDING    8
40385 #define M_OFF_PENDING    0xffU
40386 #define V_OFF_PENDING(x) ((x) << S_OFF_PENDING)
40387 #define G_OFF_PENDING(x) (((x) >> S_OFF_PENDING) & M_OFF_PENDING)
40388 
40389 #define S_ON_PENDING    0
40390 #define M_ON_PENDING    0xffU
40391 #define V_ON_PENDING(x) ((x) << S_ON_PENDING)
40392 #define G_ON_PENDING(x) (((x) >> S_ON_PENDING) & M_ON_PENDING)
40393 
40394 #define A_MPS_PORT_TX_MAC_DROP_PP 0x1d4
40395 #define A_MPS_PORT_TX_LPBK_DROP_PP 0x1d8
40396 #define A_MPS_PORT_TX_MAC_DROP_CNT 0x1dc
40397 #define A_MPS_PORT_TX_LPBK_DROP_CNT 0x1e0
40398 #define A_MPS_PORT_CLS_HASH_SRAM 0x200
40399 
40400 #define S_VALID    20
40401 #define V_VALID(x) ((x) << S_VALID)
40402 #define F_VALID    V_VALID(1U)
40403 
40404 #define S_HASHPORTMAP    16
40405 #define M_HASHPORTMAP    0xfU
40406 #define V_HASHPORTMAP(x) ((x) << S_HASHPORTMAP)
40407 #define G_HASHPORTMAP(x) (((x) >> S_HASHPORTMAP) & M_HASHPORTMAP)
40408 
40409 #define S_MULTILISTEN    15
40410 #define V_MULTILISTEN(x) ((x) << S_MULTILISTEN)
40411 #define F_MULTILISTEN    V_MULTILISTEN(1U)
40412 
40413 #define S_PRIORITY    12
40414 #define M_PRIORITY    0x7U
40415 #define V_PRIORITY(x) ((x) << S_PRIORITY)
40416 #define G_PRIORITY(x) (((x) >> S_PRIORITY) & M_PRIORITY)
40417 
40418 #define S_REPLICATE    11
40419 #define V_REPLICATE(x) ((x) << S_REPLICATE)
40420 #define F_REPLICATE    V_REPLICATE(1U)
40421 
40422 #define S_PF    8
40423 #define M_PF    0x7U
40424 #define V_PF(x) ((x) << S_PF)
40425 #define G_PF(x) (((x) >> S_PF) & M_PF)
40426 
40427 #define S_VF_VALID    7
40428 #define V_VF_VALID(x) ((x) << S_VF_VALID)
40429 #define F_VF_VALID    V_VF_VALID(1U)
40430 
40431 #define S_VF    0
40432 #define M_VF    0x7fU
40433 #define V_VF(x) ((x) << S_VF)
40434 #define G_VF(x) (((x) >> S_VF) & M_VF)
40435 
40436 #define S_DISENCAPOUTERRPLCT    23
40437 #define V_DISENCAPOUTERRPLCT(x) ((x) << S_DISENCAPOUTERRPLCT)
40438 #define F_DISENCAPOUTERRPLCT    V_DISENCAPOUTERRPLCT(1U)
40439 
40440 #define S_DISENCAP    22
40441 #define V_DISENCAP(x) ((x) << S_DISENCAP)
40442 #define F_DISENCAP    V_DISENCAP(1U)
40443 
40444 #define S_T6_VALID    21
40445 #define V_T6_VALID(x) ((x) << S_T6_VALID)
40446 #define F_T6_VALID    V_T6_VALID(1U)
40447 
40448 #define S_T6_HASHPORTMAP    17
40449 #define M_T6_HASHPORTMAP    0xfU
40450 #define V_T6_HASHPORTMAP(x) ((x) << S_T6_HASHPORTMAP)
40451 #define G_T6_HASHPORTMAP(x) (((x) >> S_T6_HASHPORTMAP) & M_T6_HASHPORTMAP)
40452 
40453 #define S_T6_MULTILISTEN    16
40454 #define V_T6_MULTILISTEN(x) ((x) << S_T6_MULTILISTEN)
40455 #define F_T6_MULTILISTEN    V_T6_MULTILISTEN(1U)
40456 
40457 #define S_T6_PRIORITY    13
40458 #define M_T6_PRIORITY    0x7U
40459 #define V_T6_PRIORITY(x) ((x) << S_T6_PRIORITY)
40460 #define G_T6_PRIORITY(x) (((x) >> S_T6_PRIORITY) & M_T6_PRIORITY)
40461 
40462 #define S_T6_REPLICATE    12
40463 #define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE)
40464 #define F_T6_REPLICATE    V_T6_REPLICATE(1U)
40465 
40466 #define S_T6_PF    9
40467 #define M_T6_PF    0x7U
40468 #define V_T6_PF(x) ((x) << S_T6_PF)
40469 #define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF)
40470 
40471 #define S_T6_VF_VALID    8
40472 #define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID)
40473 #define F_T6_VF_VALID    V_T6_VF_VALID(1U)
40474 
40475 #define S_T6_VF    0
40476 #define M_T6_VF    0xffU
40477 #define V_T6_VF(x) ((x) << S_T6_VF)
40478 #define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF)
40479 
40480 #define A_MPS_PF_CTL 0x2c0
40481 
40482 #define S_TXEN    1
40483 #define V_TXEN(x) ((x) << S_TXEN)
40484 #define F_TXEN    V_TXEN(1U)
40485 
40486 #define S_RXEN    0
40487 #define V_RXEN(x) ((x) << S_RXEN)
40488 #define F_RXEN    V_RXEN(1U)
40489 
40490 #define A_MPS_PF_TX_QINQ_VLAN 0x2e0
40491 
40492 #define S_PROTOCOLID    16
40493 #define M_PROTOCOLID    0xffffU
40494 #define V_PROTOCOLID(x) ((x) << S_PROTOCOLID)
40495 #define G_PROTOCOLID(x) (((x) >> S_PROTOCOLID) & M_PROTOCOLID)
40496 
40497 #define S_VLAN_PRIO    13
40498 #define M_VLAN_PRIO    0x7U
40499 #define V_VLAN_PRIO(x) ((x) << S_VLAN_PRIO)
40500 #define G_VLAN_PRIO(x) (((x) >> S_VLAN_PRIO) & M_VLAN_PRIO)
40501 
40502 #define S_CFI    12
40503 #define V_CFI(x) ((x) << S_CFI)
40504 #define F_CFI    V_CFI(1U)
40505 
40506 #define S_TAG    0
40507 #define M_TAG    0xfffU
40508 #define V_TAG(x) ((x) << S_TAG)
40509 #define G_TAG(x) (((x) >> S_TAG) & M_TAG)
40510 
40511 #define A_MPS_PF_TX_MAC_DROP_PP 0x2e4
40512 
40513 #define S_T7_DROPEN    0
40514 #define M_T7_DROPEN    0xffU
40515 #define V_T7_DROPEN(x) ((x) << S_T7_DROPEN)
40516 #define G_T7_DROPEN(x) (((x) >> S_T7_DROPEN) & M_T7_DROPEN)
40517 
40518 #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_L 0x300
40519 #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_H 0x304
40520 #define A_MPS_PORT_CLS_HASH_CTL 0x304
40521 
40522 #define S_UNICASTENABLE    31
40523 #define V_UNICASTENABLE(x) ((x) << S_UNICASTENABLE)
40524 #define F_UNICASTENABLE    V_UNICASTENABLE(1U)
40525 
40526 #define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_L 0x308
40527 #define A_MPS_PORT_CLS_PROMISCUOUS_CTL 0x308
40528 
40529 #define S_PROMISCEN    31
40530 #define V_PROMISCEN(x) ((x) << S_PROMISCEN)
40531 #define F_PROMISCEN    V_PROMISCEN(1U)
40532 
40533 #define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_H 0x30c
40534 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_L 0x30c
40535 #define A_MPS_PORT_CLS_BMC_MAC0_ADDR_L 0x30c
40536 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_L 0x310
40537 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_H 0x310
40538 
40539 #define S_MATCHBOTH    17
40540 #define V_MATCHBOTH(x) ((x) << S_MATCHBOTH)
40541 #define F_MATCHBOTH    V_MATCHBOTH(1U)
40542 
40543 #define S_BMC_VLD    16
40544 #define V_BMC_VLD(x) ((x) << S_BMC_VLD)
40545 #define F_BMC_VLD    V_BMC_VLD(1U)
40546 
40547 #define S_MATCHALL    18
40548 #define V_MATCHALL(x) ((x) << S_MATCHALL)
40549 #define F_MATCHALL    V_MATCHALL(1U)
40550 
40551 #define A_MPS_PORT_CLS_BMC_MAC0_ADDR_H 0x310
40552 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_H 0x314
40553 #define A_MPS_PORT_CLS_BMC_VLAN 0x314
40554 
40555 #define S_BMC_VLAN_SEL    13
40556 #define V_BMC_VLAN_SEL(x) ((x) << S_BMC_VLAN_SEL)
40557 #define F_BMC_VLAN_SEL    V_BMC_VLAN_SEL(1U)
40558 
40559 #define S_VLAN_VLD    12
40560 #define V_VLAN_VLD(x) ((x) << S_VLAN_VLD)
40561 #define F_VLAN_VLD    V_VLAN_VLD(1U)
40562 
40563 #define A_MPS_PORT_CLS_BMC_VLAN0 0x314
40564 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_L 0x318
40565 #define A_MPS_PORT_CLS_CTL 0x318
40566 
40567 #define S_PF_VLAN_SEL    0
40568 #define V_PF_VLAN_SEL(x) ((x) << S_PF_VLAN_SEL)
40569 #define F_PF_VLAN_SEL    V_PF_VLAN_SEL(1U)
40570 
40571 #define S_LPBK_TCAM1_HIT_PRIORITY    14
40572 #define V_LPBK_TCAM1_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM1_HIT_PRIORITY)
40573 #define F_LPBK_TCAM1_HIT_PRIORITY    V_LPBK_TCAM1_HIT_PRIORITY(1U)
40574 
40575 #define S_LPBK_TCAM0_HIT_PRIORITY    13
40576 #define V_LPBK_TCAM0_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM0_HIT_PRIORITY)
40577 #define F_LPBK_TCAM0_HIT_PRIORITY    V_LPBK_TCAM0_HIT_PRIORITY(1U)
40578 
40579 #define S_LPBK_TCAM_PRIORITY    12
40580 #define V_LPBK_TCAM_PRIORITY(x) ((x) << S_LPBK_TCAM_PRIORITY)
40581 #define F_LPBK_TCAM_PRIORITY    V_LPBK_TCAM_PRIORITY(1U)
40582 
40583 #define S_LPBK_SMAC_TCAM_SEL    10
40584 #define M_LPBK_SMAC_TCAM_SEL    0x3U
40585 #define V_LPBK_SMAC_TCAM_SEL(x) ((x) << S_LPBK_SMAC_TCAM_SEL)
40586 #define G_LPBK_SMAC_TCAM_SEL(x) (((x) >> S_LPBK_SMAC_TCAM_SEL) & M_LPBK_SMAC_TCAM_SEL)
40587 
40588 #define S_LPBK_DMAC_TCAM_SEL    8
40589 #define M_LPBK_DMAC_TCAM_SEL    0x3U
40590 #define V_LPBK_DMAC_TCAM_SEL(x) ((x) << S_LPBK_DMAC_TCAM_SEL)
40591 #define G_LPBK_DMAC_TCAM_SEL(x) (((x) >> S_LPBK_DMAC_TCAM_SEL) & M_LPBK_DMAC_TCAM_SEL)
40592 
40593 #define S_TCAM1_HIT_PRIORITY    7
40594 #define V_TCAM1_HIT_PRIORITY(x) ((x) << S_TCAM1_HIT_PRIORITY)
40595 #define F_TCAM1_HIT_PRIORITY    V_TCAM1_HIT_PRIORITY(1U)
40596 
40597 #define S_TCAM0_HIT_PRIORITY    6
40598 #define V_TCAM0_HIT_PRIORITY(x) ((x) << S_TCAM0_HIT_PRIORITY)
40599 #define F_TCAM0_HIT_PRIORITY    V_TCAM0_HIT_PRIORITY(1U)
40600 
40601 #define S_TCAM_PRIORITY    5
40602 #define V_TCAM_PRIORITY(x) ((x) << S_TCAM_PRIORITY)
40603 #define F_TCAM_PRIORITY    V_TCAM_PRIORITY(1U)
40604 
40605 #define S_SMAC_TCAM_SEL    3
40606 #define M_SMAC_TCAM_SEL    0x3U
40607 #define V_SMAC_TCAM_SEL(x) ((x) << S_SMAC_TCAM_SEL)
40608 #define G_SMAC_TCAM_SEL(x) (((x) >> S_SMAC_TCAM_SEL) & M_SMAC_TCAM_SEL)
40609 
40610 #define S_DMAC_TCAM_SEL    1
40611 #define M_DMAC_TCAM_SEL    0x3U
40612 #define V_DMAC_TCAM_SEL(x) ((x) << S_DMAC_TCAM_SEL)
40613 #define G_DMAC_TCAM_SEL(x) (((x) >> S_DMAC_TCAM_SEL) & M_DMAC_TCAM_SEL)
40614 
40615 #define S_SMAC_INDEX_EN    17
40616 #define V_SMAC_INDEX_EN(x) ((x) << S_SMAC_INDEX_EN)
40617 #define F_SMAC_INDEX_EN    V_SMAC_INDEX_EN(1U)
40618 
40619 #define S_LPBK_TCAM2_HIT_PRIORITY    16
40620 #define V_LPBK_TCAM2_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM2_HIT_PRIORITY)
40621 #define F_LPBK_TCAM2_HIT_PRIORITY    V_LPBK_TCAM2_HIT_PRIORITY(1U)
40622 
40623 #define S_TCAM2_HIT_PRIORITY    15
40624 #define V_TCAM2_HIT_PRIORITY(x) ((x) << S_TCAM2_HIT_PRIORITY)
40625 #define F_TCAM2_HIT_PRIORITY    V_TCAM2_HIT_PRIORITY(1U)
40626 
40627 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_H 0x31c
40628 #define A_MPS_PORT_CLS_NCSI_ETH_TYPE 0x31c
40629 
40630 #define S_ETHTYPE2    0
40631 #define M_ETHTYPE2    0xffffU
40632 #define V_ETHTYPE2(x) ((x) << S_ETHTYPE2)
40633 #define G_ETHTYPE2(x) (((x) >> S_ETHTYPE2) & M_ETHTYPE2)
40634 
40635 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_L 0x320
40636 #define A_MPS_PORT_CLS_NCSI_ETH_TYPE_EN 0x320
40637 
40638 #define S_EN1    1
40639 #define V_EN1(x) ((x) << S_EN1)
40640 #define F_EN1    V_EN1(1U)
40641 
40642 #define S_EN2    0
40643 #define V_EN2(x) ((x) << S_EN2)
40644 #define F_EN2    V_EN2(1U)
40645 
40646 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_H 0x324
40647 #define A_MPS_PORT_CLS_BMC_MAC1_ADDR_L 0x324
40648 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_L 0x328
40649 #define A_MPS_PORT_CLS_BMC_MAC1_ADDR_H 0x328
40650 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_H 0x32c
40651 #define A_MPS_PORT_CLS_BMC_MAC2_ADDR_L 0x32c
40652 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L 0x330
40653 #define A_MPS_PORT_CLS_BMC_MAC2_ADDR_H 0x330
40654 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H 0x334
40655 #define A_MPS_PORT_CLS_BMC_MAC3_ADDR_L 0x334
40656 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L 0x338
40657 #define A_MPS_PORT_CLS_BMC_MAC3_ADDR_H 0x338
40658 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H 0x33c
40659 #define A_MPS_PORT_CLS_BMC_VLAN1 0x33c
40660 #define A_MPS_PF_STAT_RX_PF_BYTES_L 0x340
40661 #define A_MPS_PORT_CLS_BMC_VLAN2 0x340
40662 #define A_MPS_PF_STAT_RX_PF_BYTES_H 0x344
40663 #define A_MPS_PORT_CLS_BMC_VLAN3 0x344
40664 #define A_MPS_PF_STAT_RX_PF_FRAMES_L 0x348
40665 #define A_MPS_PF_STAT_RX_PF_FRAMES_H 0x34c
40666 #define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_L 0x350
40667 #define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_H 0x354
40668 #define A_MPS_PF_STAT_RX_PF_BCAST_FRAMES_L 0x358
40669 #define A_MPS_PF_STAT_RX_PF_BCAST_FRAMES_H 0x35c
40670 #define A_MPS_PF_STAT_RX_PF_MCAST_BYTES_L 0x360
40671 #define A_MPS_PF_STAT_RX_PF_MCAST_BYTES_H 0x364
40672 #define A_MPS_PF_STAT_RX_PF_MCAST_FRAMES_L 0x368
40673 #define A_MPS_PF_STAT_RX_PF_MCAST_FRAMES_H 0x36c
40674 #define A_MPS_PF_STAT_RX_PF_UCAST_BYTES_L 0x370
40675 #define A_MPS_PF_STAT_RX_PF_UCAST_BYTES_H 0x374
40676 #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_L 0x378
40677 #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_H 0x37c
40678 #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_L 0x380
40679 #define A_MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_L 0x380
40680 #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_H 0x384
40681 #define A_MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_H 0x384
40682 #define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
40683 #define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
40684 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
40685 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
40686 #define A_MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
40687 #define A_MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
40688 #define A_MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
40689 #define A_MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
40690 #define A_MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
40691 #define A_MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
40692 #define A_MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
40693 #define A_MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
40694 #define A_MPS_PORT_STAT_TX_PORT_64B_L 0x430
40695 #define A_MPS_PORT_STAT_TX_PORT_64B_H 0x434
40696 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
40697 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
40698 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
40699 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
40700 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
40701 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
40702 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
40703 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
40704 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
40705 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
40706 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
40707 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
40708 #define A_MPS_PORT_STAT_TX_PORT_DROP_L 0x468
40709 #define A_MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
40710 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
40711 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
40712 #define A_MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
40713 #define A_MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
40714 #define A_MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
40715 #define A_MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
40716 #define A_MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
40717 #define A_MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
40718 #define A_MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
40719 #define A_MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
40720 #define A_MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
40721 #define A_MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
40722 #define A_MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
40723 #define A_MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
40724 #define A_MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
40725 #define A_MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
40726 #define A_MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
40727 #define A_MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
40728 #define A_MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
40729 #define A_MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
40730 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
40731 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
40732 #define A_MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
40733 #define A_MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
40734 #define A_MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
40735 #define A_MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
40736 #define A_MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
40737 #define A_MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
40738 #define A_MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
40739 #define A_MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
40740 #define A_MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
40741 #define A_MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
40742 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
40743 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
40744 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
40745 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
40746 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
40747 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
40748 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
40749 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
40750 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
40751 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
40752 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
40753 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
40754 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
40755 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
40756 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c
40757 #define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
40758 #define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
40759 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
40760 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
40761 #define A_MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
40762 #define A_MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
40763 #define A_MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
40764 #define A_MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
40765 #define A_MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
40766 #define A_MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
40767 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
40768 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
40769 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
40770 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
40771 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
40772 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
40773 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
40774 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
40775 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
40776 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
40777 #define A_MPS_PORT_STAT_RX_PORT_64B_L 0x590
40778 #define A_MPS_PORT_STAT_RX_PORT_64B_H 0x594
40779 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
40780 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
40781 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
40782 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
40783 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
40784 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
40785 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
40786 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
40787 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
40788 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
40789 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
40790 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
40791 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
40792 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
40793 #define A_MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
40794 #define A_MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
40795 #define A_MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
40796 #define A_MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
40797 #define A_MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
40798 #define A_MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
40799 #define A_MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
40800 #define A_MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
40801 #define A_MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
40802 #define A_MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
40803 #define A_MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
40804 #define A_MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
40805 #define A_MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
40806 #define A_MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
40807 #define A_MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
40808 #define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
40809 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
40810 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
40811 #define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_L 0x618
40812 #define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_H 0x61c
40813 #define A_MPS_PORT_STAT_RX_PRIO_0_DROP_FRAME_L 0x620
40814 #define A_MPS_PORT_STAT_RX_PRIO_0_DROP_FRAME_H 0x624
40815 #define A_MPS_PORT_STAT_RX_PRIO_1_DROP_FRAME_L 0x628
40816 #define A_MPS_PORT_STAT_RX_PRIO_1_DROP_FRAME_H 0x62c
40817 #define A_MPS_PORT_STAT_RX_PRIO_2_DROP_FRAME_L 0x630
40818 #define A_MPS_PORT_STAT_RX_PRIO_2_DROP_FRAME_H 0x634
40819 #define A_MPS_PORT_STAT_RX_PRIO_3_DROP_FRAME_L 0x638
40820 #define A_MPS_PORT_STAT_RX_PRIO_3_DROP_FRAME_H 0x63c
40821 #define A_MPS_PORT_STAT_RX_PRIO_4_DROP_FRAME_L 0x640
40822 #define A_MPS_PORT_STAT_RX_PRIO_4_DROP_FRAME_H 0x644
40823 #define A_MPS_PORT_STAT_RX_PRIO_5_DROP_FRAME_L 0x648
40824 #define A_MPS_PORT_STAT_RX_PRIO_5_DROP_FRAME_H 0x64c
40825 #define A_MPS_PORT_STAT_RX_PRIO_6_DROP_FRAME_L 0x650
40826 #define A_MPS_PORT_STAT_RX_PRIO_6_DROP_FRAME_H 0x654
40827 #define A_MPS_PORT_STAT_RX_PRIO_7_DROP_FRAME_L 0x658
40828 #define A_MPS_PORT_STAT_RX_PRIO_7_DROP_FRAME_H 0x65c
40829 #define A_MPS_CMN_CTL 0x9000
40830 
40831 #define S_DETECT8023    3
40832 #define V_DETECT8023(x) ((x) << S_DETECT8023)
40833 #define F_DETECT8023    V_DETECT8023(1U)
40834 
40835 #define S_VFDIRECTACCESS    2
40836 #define V_VFDIRECTACCESS(x) ((x) << S_VFDIRECTACCESS)
40837 #define F_VFDIRECTACCESS    V_VFDIRECTACCESS(1U)
40838 
40839 #define S_NUMPORTS    0
40840 #define M_NUMPORTS    0x3U
40841 #define V_NUMPORTS(x) ((x) << S_NUMPORTS)
40842 #define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS)
40843 
40844 #define S_LPBKCRDTCTRL    4
40845 #define V_LPBKCRDTCTRL(x) ((x) << S_LPBKCRDTCTRL)
40846 #define F_LPBKCRDTCTRL    V_LPBKCRDTCTRL(1U)
40847 
40848 #define S_TX_PORT_STATS_MODE    8
40849 #define V_TX_PORT_STATS_MODE(x) ((x) << S_TX_PORT_STATS_MODE)
40850 #define F_TX_PORT_STATS_MODE    V_TX_PORT_STATS_MODE(1U)
40851 
40852 #define S_T5MODE    7
40853 #define V_T5MODE(x) ((x) << S_T5MODE)
40854 #define F_T5MODE    V_T5MODE(1U)
40855 
40856 #define S_SPEEDMODE    5
40857 #define M_SPEEDMODE    0x3U
40858 #define V_SPEEDMODE(x) ((x) << S_SPEEDMODE)
40859 #define G_SPEEDMODE(x) (((x) >> S_SPEEDMODE) & M_SPEEDMODE)
40860 
40861 #define S_PT1_SEL_CFG    21
40862 #define V_PT1_SEL_CFG(x) ((x) << S_PT1_SEL_CFG)
40863 #define F_PT1_SEL_CFG    V_PT1_SEL_CFG(1U)
40864 
40865 #define S_BUG_42938_EN    20
40866 #define V_BUG_42938_EN(x) ((x) << S_BUG_42938_EN)
40867 #define F_BUG_42938_EN    V_BUG_42938_EN(1U)
40868 
40869 #define S_NO_BYPASS_PAUSE    19
40870 #define V_NO_BYPASS_PAUSE(x) ((x) << S_NO_BYPASS_PAUSE)
40871 #define F_NO_BYPASS_PAUSE    V_NO_BYPASS_PAUSE(1U)
40872 
40873 #define S_BYPASS_PAUSE    18
40874 #define V_BYPASS_PAUSE(x) ((x) << S_BYPASS_PAUSE)
40875 #define F_BYPASS_PAUSE    V_BYPASS_PAUSE(1U)
40876 
40877 #define S_PBUS_EN    16
40878 #define M_PBUS_EN    0x3U
40879 #define V_PBUS_EN(x) ((x) << S_PBUS_EN)
40880 #define G_PBUS_EN(x) (((x) >> S_PBUS_EN) & M_PBUS_EN)
40881 
40882 #define S_INIC_EN    14
40883 #define M_INIC_EN    0x3U
40884 #define V_INIC_EN(x) ((x) << S_INIC_EN)
40885 #define G_INIC_EN(x) (((x) >> S_INIC_EN) & M_INIC_EN)
40886 
40887 #define S_SBA_EN    12
40888 #define M_SBA_EN    0x3U
40889 #define V_SBA_EN(x) ((x) << S_SBA_EN)
40890 #define G_SBA_EN(x) (((x) >> S_SBA_EN) & M_SBA_EN)
40891 
40892 #define S_BG2TP_MAP_MODE    11
40893 #define V_BG2TP_MAP_MODE(x) ((x) << S_BG2TP_MAP_MODE)
40894 #define F_BG2TP_MAP_MODE    V_BG2TP_MAP_MODE(1U)
40895 
40896 #define S_MPS_LB_MODE    9
40897 #define M_MPS_LB_MODE    0x3U
40898 #define V_MPS_LB_MODE(x) ((x) << S_MPS_LB_MODE)
40899 #define G_MPS_LB_MODE(x) (((x) >> S_MPS_LB_MODE) & M_MPS_LB_MODE)
40900 
40901 #define A_MPS_INT_ENABLE 0x9004
40902 
40903 #define S_STATINTENB    5
40904 #define V_STATINTENB(x) ((x) << S_STATINTENB)
40905 #define F_STATINTENB    V_STATINTENB(1U)
40906 
40907 #define S_TXINTENB    4
40908 #define V_TXINTENB(x) ((x) << S_TXINTENB)
40909 #define F_TXINTENB    V_TXINTENB(1U)
40910 
40911 #define S_RXINTENB    3
40912 #define V_RXINTENB(x) ((x) << S_RXINTENB)
40913 #define F_RXINTENB    V_RXINTENB(1U)
40914 
40915 #define S_TRCINTENB    2
40916 #define V_TRCINTENB(x) ((x) << S_TRCINTENB)
40917 #define F_TRCINTENB    V_TRCINTENB(1U)
40918 
40919 #define S_CLSINTENB    1
40920 #define V_CLSINTENB(x) ((x) << S_CLSINTENB)
40921 #define F_CLSINTENB    V_CLSINTENB(1U)
40922 
40923 #define S_PLINTENB    0
40924 #define V_PLINTENB(x) ((x) << S_PLINTENB)
40925 #define F_PLINTENB    V_PLINTENB(1U)
40926 
40927 #define A_MPS_INT_CAUSE 0x9008
40928 
40929 #define S_STATINT    5
40930 #define V_STATINT(x) ((x) << S_STATINT)
40931 #define F_STATINT    V_STATINT(1U)
40932 
40933 #define S_TXINT    4
40934 #define V_TXINT(x) ((x) << S_TXINT)
40935 #define F_TXINT    V_TXINT(1U)
40936 
40937 #define S_RXINT    3
40938 #define V_RXINT(x) ((x) << S_RXINT)
40939 #define F_RXINT    V_RXINT(1U)
40940 
40941 #define S_TRCINT    2
40942 #define V_TRCINT(x) ((x) << S_TRCINT)
40943 #define F_TRCINT    V_TRCINT(1U)
40944 
40945 #define S_CLSINT    1
40946 #define V_CLSINT(x) ((x) << S_CLSINT)
40947 #define F_CLSINT    V_CLSINT(1U)
40948 
40949 #define S_PLINT    0
40950 #define V_PLINT(x) ((x) << S_PLINT)
40951 #define F_PLINT    V_PLINT(1U)
40952 
40953 #define A_MPS_CGEN_GLOBAL 0x900c
40954 
40955 #define S_MPS_GLOBAL_CGEN    0
40956 #define V_MPS_GLOBAL_CGEN(x) ((x) << S_MPS_GLOBAL_CGEN)
40957 #define F_MPS_GLOBAL_CGEN    V_MPS_GLOBAL_CGEN(1U)
40958 
40959 #define A_MPS_VF_TX_CTL_31_0 0x9010
40960 #define A_MPS_VF_TX_CTL_63_32 0x9014
40961 #define A_MPS_VF_TX_CTL_95_64 0x9018
40962 #define A_MPS_VF_TX_CTL_127_96 0x901c
40963 #define A_MPS_VF_RX_CTL_31_0 0x9020
40964 #define A_MPS_VF_RX_CTL_63_32 0x9024
40965 #define A_MPS_VF_RX_CTL_95_64 0x9028
40966 #define A_MPS_VF_RX_CTL_127_96 0x902c
40967 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP0 0x9030
40968 
40969 #define S_VALUE    0
40970 #define M_VALUE    0xffffU
40971 #define V_VALUE(x) ((x) << S_VALUE)
40972 #define G_VALUE(x) (((x) >> S_VALUE) & M_VALUE)
40973 
40974 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP1 0x9034
40975 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP2 0x9038
40976 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP3 0x903c
40977 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP0 0x9040
40978 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP1 0x9044
40979 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP2 0x9048
40980 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP3 0x904c
40981 #define A_MPS_TP_CSIDE_MUX_CTL_P0 0x9050
40982 
40983 #define S_WEIGHT    0
40984 #define M_WEIGHT    0xfffU
40985 #define V_WEIGHT(x) ((x) << S_WEIGHT)
40986 #define G_WEIGHT(x) (((x) >> S_WEIGHT) & M_WEIGHT)
40987 
40988 #define A_MPS_TP_CSIDE_MUX_CTL_P1 0x9054
40989 #define A_MPS_WOL_CTL_MODE 0x9058
40990 
40991 #define S_WOL_MODE    0
40992 #define V_WOL_MODE(x) ((x) << S_WOL_MODE)
40993 #define F_WOL_MODE    V_WOL_MODE(1U)
40994 
40995 #define A_MPS_FPGA_DEBUG 0x9060
40996 
40997 #define S_LPBK_EN    8
40998 #define V_LPBK_EN(x) ((x) << S_LPBK_EN)
40999 #define F_LPBK_EN    V_LPBK_EN(1U)
41000 
41001 #define S_CH_MAP3    6
41002 #define M_CH_MAP3    0x3U
41003 #define V_CH_MAP3(x) ((x) << S_CH_MAP3)
41004 #define G_CH_MAP3(x) (((x) >> S_CH_MAP3) & M_CH_MAP3)
41005 
41006 #define S_CH_MAP2    4
41007 #define M_CH_MAP2    0x3U
41008 #define V_CH_MAP2(x) ((x) << S_CH_MAP2)
41009 #define G_CH_MAP2(x) (((x) >> S_CH_MAP2) & M_CH_MAP2)
41010 
41011 #define S_CH_MAP1    2
41012 #define M_CH_MAP1    0x3U
41013 #define V_CH_MAP1(x) ((x) << S_CH_MAP1)
41014 #define G_CH_MAP1(x) (((x) >> S_CH_MAP1) & M_CH_MAP1)
41015 
41016 #define S_CH_MAP0    0
41017 #define M_CH_MAP0    0x3U
41018 #define V_CH_MAP0(x) ((x) << S_CH_MAP0)
41019 #define G_CH_MAP0(x) (((x) >> S_CH_MAP0) & M_CH_MAP0)
41020 
41021 #define S_FPGA_PTP_PORT    9
41022 #define M_FPGA_PTP_PORT    0x3U
41023 #define V_FPGA_PTP_PORT(x) ((x) << S_FPGA_PTP_PORT)
41024 #define G_FPGA_PTP_PORT(x) (((x) >> S_FPGA_PTP_PORT) & M_FPGA_PTP_PORT)
41025 
41026 #define A_MPS_DEBUG_CTL 0x9068
41027 
41028 #define S_DBGMODECTL_H    11
41029 #define V_DBGMODECTL_H(x) ((x) << S_DBGMODECTL_H)
41030 #define F_DBGMODECTL_H    V_DBGMODECTL_H(1U)
41031 
41032 #define S_DBGSEL_H    6
41033 #define M_DBGSEL_H    0x1fU
41034 #define V_DBGSEL_H(x) ((x) << S_DBGSEL_H)
41035 #define G_DBGSEL_H(x) (((x) >> S_DBGSEL_H) & M_DBGSEL_H)
41036 
41037 #define S_DBGMODECTL_L    5
41038 #define V_DBGMODECTL_L(x) ((x) << S_DBGMODECTL_L)
41039 #define F_DBGMODECTL_L    V_DBGMODECTL_L(1U)
41040 
41041 #define S_DBGSEL_L    0
41042 #define M_DBGSEL_L    0x1fU
41043 #define V_DBGSEL_L(x) ((x) << S_DBGSEL_L)
41044 #define G_DBGSEL_L(x) (((x) >> S_DBGSEL_L) & M_DBGSEL_L)
41045 
41046 #define A_MPS_DEBUG_DATA_REG_L 0x906c
41047 #define A_MPS_DEBUG_DATA_REG_H 0x9070
41048 #define A_MPS_TOP_SPARE 0x9074
41049 
41050 #define S_TOPSPARE    8
41051 #define M_TOPSPARE    0xffffffU
41052 #define V_TOPSPARE(x) ((x) << S_TOPSPARE)
41053 #define G_TOPSPARE(x) (((x) >> S_TOPSPARE) & M_TOPSPARE)
41054 
41055 #define S_OVLANSELLPBK3    7
41056 #define V_OVLANSELLPBK3(x) ((x) << S_OVLANSELLPBK3)
41057 #define F_OVLANSELLPBK3    V_OVLANSELLPBK3(1U)
41058 
41059 #define S_OVLANSELLPBK2    6
41060 #define V_OVLANSELLPBK2(x) ((x) << S_OVLANSELLPBK2)
41061 #define F_OVLANSELLPBK2    V_OVLANSELLPBK2(1U)
41062 
41063 #define S_OVLANSELLPBK1    5
41064 #define V_OVLANSELLPBK1(x) ((x) << S_OVLANSELLPBK1)
41065 #define F_OVLANSELLPBK1    V_OVLANSELLPBK1(1U)
41066 
41067 #define S_OVLANSELLPBK0    4
41068 #define V_OVLANSELLPBK0(x) ((x) << S_OVLANSELLPBK0)
41069 #define F_OVLANSELLPBK0    V_OVLANSELLPBK0(1U)
41070 
41071 #define S_OVLANSELMAC3    3
41072 #define V_OVLANSELMAC3(x) ((x) << S_OVLANSELMAC3)
41073 #define F_OVLANSELMAC3    V_OVLANSELMAC3(1U)
41074 
41075 #define S_OVLANSELMAC2    2
41076 #define V_OVLANSELMAC2(x) ((x) << S_OVLANSELMAC2)
41077 #define F_OVLANSELMAC2    V_OVLANSELMAC2(1U)
41078 
41079 #define S_OVLANSELMAC1    1
41080 #define V_OVLANSELMAC1(x) ((x) << S_OVLANSELMAC1)
41081 #define F_OVLANSELMAC1    V_OVLANSELMAC1(1U)
41082 
41083 #define S_OVLANSELMAC0    0
41084 #define V_OVLANSELMAC0(x) ((x) << S_OVLANSELMAC0)
41085 #define F_OVLANSELMAC0    V_OVLANSELMAC0(1U)
41086 
41087 #define S_T5_TOPSPARE    8
41088 #define M_T5_TOPSPARE    0xffffffU
41089 #define V_T5_TOPSPARE(x) ((x) << S_T5_TOPSPARE)
41090 #define G_T5_TOPSPARE(x) (((x) >> S_T5_TOPSPARE) & M_T5_TOPSPARE)
41091 
41092 #define A_MPS_T5_BUILD_REVISION 0x9078
41093 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH0 0x907c
41094 
41095 #define S_VALUE_1    16
41096 #define M_VALUE_1    0xffffU
41097 #define V_VALUE_1(x) ((x) << S_VALUE_1)
41098 #define G_VALUE_1(x) (((x) >> S_VALUE_1) & M_VALUE_1)
41099 
41100 #define S_VALUE_0    0
41101 #define M_VALUE_0    0xffffU
41102 #define V_VALUE_0(x) ((x) << S_VALUE_0)
41103 #define G_VALUE_0(x) (((x) >> S_VALUE_0) & M_VALUE_0)
41104 
41105 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH1 0x9080
41106 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH2 0x9084
41107 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH3 0x9088
41108 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH4 0x908c
41109 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH5 0x9090
41110 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH6 0x9094
41111 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH7 0x9098
41112 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH8 0x909c
41113 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH9 0x90a0
41114 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH10 0x90a4
41115 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH11 0x90a8
41116 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH12 0x90ac
41117 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH13 0x90b0
41118 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH14 0x90b4
41119 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH15 0x90b8
41120 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0 0x90bc
41121 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1 0x90c0
41122 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2 0x90c4
41123 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3 0x90c8
41124 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4 0x90cc
41125 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5 0x90d0
41126 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6 0x90d4
41127 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7 0x90d8
41128 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8 0x90dc
41129 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9 0x90e0
41130 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10 0x90e4
41131 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11 0x90e8
41132 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12 0x90ec
41133 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13 0x90f0
41134 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14 0x90f4
41135 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15 0x90f8
41136 #define A_MPS_BUILD_REVISION 0x90fc
41137 #define A_MPS_VF_TX_CTL_159_128 0x9100
41138 #define A_MPS_VF_TX_CTL_191_160 0x9104
41139 #define A_MPS_VF_TX_CTL_223_192 0x9108
41140 #define A_MPS_VF_TX_CTL_255_224 0x910c
41141 #define A_MPS_VF_RX_CTL_159_128 0x9110
41142 #define A_MPS_VF_RX_CTL_191_160 0x9114
41143 #define A_MPS_VF_RX_CTL_223_192 0x9118
41144 #define A_MPS_VF_RX_CTL_255_224 0x911c
41145 #define A_MPS_FPGA_BIST_CFG_P0 0x9120
41146 
41147 #define S_ADDRMASK    16
41148 #define M_ADDRMASK    0xffffU
41149 #define V_ADDRMASK(x) ((x) << S_ADDRMASK)
41150 #define G_ADDRMASK(x) (((x) >> S_ADDRMASK) & M_ADDRMASK)
41151 
41152 #define S_T6_BASEADDR    0
41153 #define M_T6_BASEADDR    0xffffU
41154 #define V_T6_BASEADDR(x) ((x) << S_T6_BASEADDR)
41155 #define G_T6_BASEADDR(x) (((x) >> S_T6_BASEADDR) & M_T6_BASEADDR)
41156 
41157 #define A_MPS_FPGA_BIST_CFG_P1 0x9124
41158 #define A_MPS_FPGA_BIST_CFG_P2 0x9128
41159 #define A_MPS_FPGA_BIST_CFG_P3 0x912c
41160 #define A_MPS_INIC_CTL 0x9130
41161 
41162 #define S_T7_RD_WRN    16
41163 #define V_T7_RD_WRN(x) ((x) << S_T7_RD_WRN)
41164 #define F_T7_RD_WRN    V_T7_RD_WRN(1U)
41165 
41166 #define A_MPS_INIC_DATA 0x9134
41167 #define A_MPS_TP_CSIDE_MUX_CTL_P2 0x9138
41168 #define A_MPS_TP_CSIDE_MUX_CTL_P3 0x913c
41169 #define A_MPS_RED_CTL 0x9140
41170 
41171 #define S_LPBK_SHIFT_0    28
41172 #define M_LPBK_SHIFT_0    0xfU
41173 #define V_LPBK_SHIFT_0(x) ((x) << S_LPBK_SHIFT_0)
41174 #define G_LPBK_SHIFT_0(x) (((x) >> S_LPBK_SHIFT_0) & M_LPBK_SHIFT_0)
41175 
41176 #define S_LPBK_SHIFT_1    24
41177 #define M_LPBK_SHIFT_1    0xfU
41178 #define V_LPBK_SHIFT_1(x) ((x) << S_LPBK_SHIFT_1)
41179 #define G_LPBK_SHIFT_1(x) (((x) >> S_LPBK_SHIFT_1) & M_LPBK_SHIFT_1)
41180 
41181 #define S_LPBK_SHIFT_2    20
41182 #define M_LPBK_SHIFT_2    0xfU
41183 #define V_LPBK_SHIFT_2(x) ((x) << S_LPBK_SHIFT_2)
41184 #define G_LPBK_SHIFT_2(x) (((x) >> S_LPBK_SHIFT_2) & M_LPBK_SHIFT_2)
41185 
41186 #define S_LPBK_SHIFT_3    16
41187 #define M_LPBK_SHIFT_3    0xfU
41188 #define V_LPBK_SHIFT_3(x) ((x) << S_LPBK_SHIFT_3)
41189 #define G_LPBK_SHIFT_3(x) (((x) >> S_LPBK_SHIFT_3) & M_LPBK_SHIFT_3)
41190 
41191 #define S_MAC_SHIFT_0    12
41192 #define M_MAC_SHIFT_0    0xfU
41193 #define V_MAC_SHIFT_0(x) ((x) << S_MAC_SHIFT_0)
41194 #define G_MAC_SHIFT_0(x) (((x) >> S_MAC_SHIFT_0) & M_MAC_SHIFT_0)
41195 
41196 #define S_MAC_SHIFT_1    8
41197 #define M_MAC_SHIFT_1    0xfU
41198 #define V_MAC_SHIFT_1(x) ((x) << S_MAC_SHIFT_1)
41199 #define G_MAC_SHIFT_1(x) (((x) >> S_MAC_SHIFT_1) & M_MAC_SHIFT_1)
41200 
41201 #define S_MAC_SHIFT_2    4
41202 #define M_MAC_SHIFT_2    0xfU
41203 #define V_MAC_SHIFT_2(x) ((x) << S_MAC_SHIFT_2)
41204 #define G_MAC_SHIFT_2(x) (((x) >> S_MAC_SHIFT_2) & M_MAC_SHIFT_2)
41205 
41206 #define S_MAC_SHIFT_3    0
41207 #define M_MAC_SHIFT_3    0xfU
41208 #define V_MAC_SHIFT_3(x) ((x) << S_MAC_SHIFT_3)
41209 #define G_MAC_SHIFT_3(x) (((x) >> S_MAC_SHIFT_3) & M_MAC_SHIFT_3)
41210 
41211 #define A_MPS_RED_EN 0x9144
41212 
41213 #define S_LPBK_EN3    7
41214 #define V_LPBK_EN3(x) ((x) << S_LPBK_EN3)
41215 #define F_LPBK_EN3    V_LPBK_EN3(1U)
41216 
41217 #define S_LPBK_EN2    6
41218 #define V_LPBK_EN2(x) ((x) << S_LPBK_EN2)
41219 #define F_LPBK_EN2    V_LPBK_EN2(1U)
41220 
41221 #define S_LPBK_EN1    5
41222 #define V_LPBK_EN1(x) ((x) << S_LPBK_EN1)
41223 #define F_LPBK_EN1    V_LPBK_EN1(1U)
41224 
41225 #define S_LPBK_EN0    4
41226 #define V_LPBK_EN0(x) ((x) << S_LPBK_EN0)
41227 #define F_LPBK_EN0    V_LPBK_EN0(1U)
41228 
41229 #define S_MAC_EN3    3
41230 #define V_MAC_EN3(x) ((x) << S_MAC_EN3)
41231 #define F_MAC_EN3    V_MAC_EN3(1U)
41232 
41233 #define S_MAC_EN2    2
41234 #define V_MAC_EN2(x) ((x) << S_MAC_EN2)
41235 #define F_MAC_EN2    V_MAC_EN2(1U)
41236 
41237 #define S_MAC_EN1    1
41238 #define V_MAC_EN1(x) ((x) << S_MAC_EN1)
41239 #define F_MAC_EN1    V_MAC_EN1(1U)
41240 
41241 #define S_MAC_EN0    0
41242 #define V_MAC_EN0(x) ((x) << S_MAC_EN0)
41243 #define F_MAC_EN0    V_MAC_EN0(1U)
41244 
41245 #define A_MPS_MAC0_RED_DROP_CNT_H 0x9148
41246 #define A_MPS_MAC0_RED_DROP_CNT_L 0x914c
41247 #define A_MPS_MAC1_RED_DROP_CNT_H 0x9150
41248 #define A_MPS_MAC1_RED_DROP_CNT_L 0x9154
41249 #define A_MPS_MAC2_RED_DROP_CNT_H 0x9158
41250 #define A_MPS_MAC2_RED_DROP_CNT_L 0x915c
41251 #define A_MPS_MAC3_RED_DROP_CNT_H 0x9160
41252 #define A_MPS_MAC3_RED_DROP_CNT_L 0x9164
41253 #define A_MPS_LPBK0_RED_DROP_CNT_H 0x9168
41254 #define A_MPS_LPBK0_RED_DROP_CNT_L 0x916c
41255 #define A_MPS_LPBK1_RED_DROP_CNT_H 0x9170
41256 #define A_MPS_LPBK1_RED_DROP_CNT_L 0x9174
41257 #define A_MPS_LPBK2_RED_DROP_CNT_H 0x9178
41258 #define A_MPS_LPBK2_RED_DROP_CNT_L 0x917c
41259 #define A_MPS_LPBK3_RED_DROP_CNT_H 0x9180
41260 #define A_MPS_LPBK3_RED_DROP_CNT_L 0x9184
41261 #define A_MPS_MAC_RED_PP_DROP_EN 0x9188
41262 
41263 #define S_T7_MAC3    24
41264 #define M_T7_MAC3    0xffU
41265 #define V_T7_MAC3(x) ((x) << S_T7_MAC3)
41266 #define G_T7_MAC3(x) (((x) >> S_T7_MAC3) & M_T7_MAC3)
41267 
41268 #define S_T7_MAC2    16
41269 #define M_T7_MAC2    0xffU
41270 #define V_T7_MAC2(x) ((x) << S_T7_MAC2)
41271 #define G_T7_MAC2(x) (((x) >> S_T7_MAC2) & M_T7_MAC2)
41272 
41273 #define S_T7_MAC1    8
41274 #define M_T7_MAC1    0xffU
41275 #define V_T7_MAC1(x) ((x) << S_T7_MAC1)
41276 #define G_T7_MAC1(x) (((x) >> S_T7_MAC1) & M_T7_MAC1)
41277 
41278 #define S_T7_MAC0    0
41279 #define M_T7_MAC0    0xffU
41280 #define V_T7_MAC0(x) ((x) << S_T7_MAC0)
41281 #define G_T7_MAC0(x) (((x) >> S_T7_MAC0) & M_T7_MAC0)
41282 
41283 #define A_MPS_TX_PRTY_SEL 0x9400
41284 
41285 #define S_CH4_PRTY    20
41286 #define M_CH4_PRTY    0x7U
41287 #define V_CH4_PRTY(x) ((x) << S_CH4_PRTY)
41288 #define G_CH4_PRTY(x) (((x) >> S_CH4_PRTY) & M_CH4_PRTY)
41289 
41290 #define S_CH3_PRTY    16
41291 #define M_CH3_PRTY    0x7U
41292 #define V_CH3_PRTY(x) ((x) << S_CH3_PRTY)
41293 #define G_CH3_PRTY(x) (((x) >> S_CH3_PRTY) & M_CH3_PRTY)
41294 
41295 #define S_CH2_PRTY    12
41296 #define M_CH2_PRTY    0x7U
41297 #define V_CH2_PRTY(x) ((x) << S_CH2_PRTY)
41298 #define G_CH2_PRTY(x) (((x) >> S_CH2_PRTY) & M_CH2_PRTY)
41299 
41300 #define S_CH1_PRTY    8
41301 #define M_CH1_PRTY    0x7U
41302 #define V_CH1_PRTY(x) ((x) << S_CH1_PRTY)
41303 #define G_CH1_PRTY(x) (((x) >> S_CH1_PRTY) & M_CH1_PRTY)
41304 
41305 #define S_CH0_PRTY    4
41306 #define M_CH0_PRTY    0x7U
41307 #define V_CH0_PRTY(x) ((x) << S_CH0_PRTY)
41308 #define G_CH0_PRTY(x) (((x) >> S_CH0_PRTY) & M_CH0_PRTY)
41309 
41310 #define S_TP_SOURCE    2
41311 #define M_TP_SOURCE    0x3U
41312 #define V_TP_SOURCE(x) ((x) << S_TP_SOURCE)
41313 #define G_TP_SOURCE(x) (((x) >> S_TP_SOURCE) & M_TP_SOURCE)
41314 
41315 #define S_NCSI_SOURCE    0
41316 #define M_NCSI_SOURCE    0x3U
41317 #define V_NCSI_SOURCE(x) ((x) << S_NCSI_SOURCE)
41318 #define G_NCSI_SOURCE(x) (((x) >> S_NCSI_SOURCE) & M_NCSI_SOURCE)
41319 
41320 #define S_T7_CH4_PRTY    16
41321 #define M_T7_CH4_PRTY    0x7U
41322 #define V_T7_CH4_PRTY(x) ((x) << S_T7_CH4_PRTY)
41323 #define G_T7_CH4_PRTY(x) (((x) >> S_T7_CH4_PRTY) & M_T7_CH4_PRTY)
41324 
41325 #define S_T7_CH3_PRTY    13
41326 #define M_T7_CH3_PRTY    0x7U
41327 #define V_T7_CH3_PRTY(x) ((x) << S_T7_CH3_PRTY)
41328 #define G_T7_CH3_PRTY(x) (((x) >> S_T7_CH3_PRTY) & M_T7_CH3_PRTY)
41329 
41330 #define S_T7_CH2_PRTY    10
41331 #define M_T7_CH2_PRTY    0x7U
41332 #define V_T7_CH2_PRTY(x) ((x) << S_T7_CH2_PRTY)
41333 #define G_T7_CH2_PRTY(x) (((x) >> S_T7_CH2_PRTY) & M_T7_CH2_PRTY)
41334 
41335 #define S_T7_CH1_PRTY    7
41336 #define M_T7_CH1_PRTY    0x7U
41337 #define V_T7_CH1_PRTY(x) ((x) << S_T7_CH1_PRTY)
41338 #define G_T7_CH1_PRTY(x) (((x) >> S_T7_CH1_PRTY) & M_T7_CH1_PRTY)
41339 
41340 #define A_MPS_TX_INT_ENABLE 0x9404
41341 
41342 #define S_PORTERR    16
41343 #define V_PORTERR(x) ((x) << S_PORTERR)
41344 #define F_PORTERR    V_PORTERR(1U)
41345 
41346 #define S_FRMERR    15
41347 #define V_FRMERR(x) ((x) << S_FRMERR)
41348 #define F_FRMERR    V_FRMERR(1U)
41349 
41350 #define S_SECNTERR    14
41351 #define V_SECNTERR(x) ((x) << S_SECNTERR)
41352 #define F_SECNTERR    V_SECNTERR(1U)
41353 
41354 #define S_BUBBLE    13
41355 #define V_BUBBLE(x) ((x) << S_BUBBLE)
41356 #define F_BUBBLE    V_BUBBLE(1U)
41357 
41358 #define S_TXDESCFIFO    9
41359 #define M_TXDESCFIFO    0xfU
41360 #define V_TXDESCFIFO(x) ((x) << S_TXDESCFIFO)
41361 #define G_TXDESCFIFO(x) (((x) >> S_TXDESCFIFO) & M_TXDESCFIFO)
41362 
41363 #define S_TXDATAFIFO    5
41364 #define M_TXDATAFIFO    0xfU
41365 #define V_TXDATAFIFO(x) ((x) << S_TXDATAFIFO)
41366 #define G_TXDATAFIFO(x) (((x) >> S_TXDATAFIFO) & M_TXDATAFIFO)
41367 
41368 #define S_NCSIFIFO    4
41369 #define V_NCSIFIFO(x) ((x) << S_NCSIFIFO)
41370 #define F_NCSIFIFO    V_NCSIFIFO(1U)
41371 
41372 #define S_TPFIFO    0
41373 #define M_TPFIFO    0xfU
41374 #define V_TPFIFO(x) ((x) << S_TPFIFO)
41375 #define G_TPFIFO(x) (((x) >> S_TPFIFO) & M_TPFIFO)
41376 
41377 #define S_T7_PORTERR    28
41378 #define V_T7_PORTERR(x) ((x) << S_T7_PORTERR)
41379 #define F_T7_PORTERR    V_T7_PORTERR(1U)
41380 
41381 #define S_T7_FRMERR    27
41382 #define V_T7_FRMERR(x) ((x) << S_T7_FRMERR)
41383 #define F_T7_FRMERR    V_T7_FRMERR(1U)
41384 
41385 #define S_T7_SECNTERR    26
41386 #define V_T7_SECNTERR(x) ((x) << S_T7_SECNTERR)
41387 #define F_T7_SECNTERR    V_T7_SECNTERR(1U)
41388 
41389 #define S_T7_BUBBLE    25
41390 #define V_T7_BUBBLE(x) ((x) << S_T7_BUBBLE)
41391 #define F_T7_BUBBLE    V_T7_BUBBLE(1U)
41392 
41393 #define S_TXTOKENFIFO    15
41394 #define M_TXTOKENFIFO    0x3ffU
41395 #define V_TXTOKENFIFO(x) ((x) << S_TXTOKENFIFO)
41396 #define G_TXTOKENFIFO(x) (((x) >> S_TXTOKENFIFO) & M_TXTOKENFIFO)
41397 
41398 #define S_PERR_TP2MPS_TFIFO    13
41399 #define M_PERR_TP2MPS_TFIFO    0x3U
41400 #define V_PERR_TP2MPS_TFIFO(x) ((x) << S_PERR_TP2MPS_TFIFO)
41401 #define G_PERR_TP2MPS_TFIFO(x) (((x) >> S_PERR_TP2MPS_TFIFO) & M_PERR_TP2MPS_TFIFO)
41402 
41403 #define A_MPS_TX_INT_CAUSE 0x9408
41404 #define A_MPS_TX_NCSI2MPS_CNT 0x940c
41405 #define A_MPS_TX_PERR_ENABLE 0x9410
41406 
41407 #define S_PORTERRINT    28
41408 #define V_PORTERRINT(x) ((x) << S_PORTERRINT)
41409 #define F_PORTERRINT    V_PORTERRINT(1U)
41410 
41411 #define S_FRAMINGERRINT    27
41412 #define V_FRAMINGERRINT(x) ((x) << S_FRAMINGERRINT)
41413 #define F_FRAMINGERRINT    V_FRAMINGERRINT(1U)
41414 
41415 #define S_SECNTERRINT    26
41416 #define V_SECNTERRINT(x) ((x) << S_SECNTERRINT)
41417 #define F_SECNTERRINT    V_SECNTERRINT(1U)
41418 
41419 #define S_BUBBLEERRINT    25
41420 #define V_BUBBLEERRINT(x) ((x) << S_BUBBLEERRINT)
41421 #define F_BUBBLEERRINT    V_BUBBLEERRINT(1U)
41422 
41423 #define A_MPS_TX_PERR_INJECT 0x9414
41424 
41425 #define S_MPSTXMEMSEL    1
41426 #define M_MPSTXMEMSEL    0x1fU
41427 #define V_MPSTXMEMSEL(x) ((x) << S_MPSTXMEMSEL)
41428 #define G_MPSTXMEMSEL(x) (((x) >> S_MPSTXMEMSEL) & M_MPSTXMEMSEL)
41429 
41430 #define A_MPS_TX_SE_CNT_TP01 0x9418
41431 #define A_MPS_TX_SE_CNT_TP23 0x941c
41432 #define A_MPS_TX_SE_CNT_MAC01 0x9420
41433 #define A_MPS_TX_SE_CNT_MAC23 0x9424
41434 #define A_MPS_TX_SECNT_SPI_BUBBLE_ERR 0x9428
41435 
41436 #define S_BUBBLEERR    16
41437 #define M_BUBBLEERR    0xffU
41438 #define V_BUBBLEERR(x) ((x) << S_BUBBLEERR)
41439 #define G_BUBBLEERR(x) (((x) >> S_BUBBLEERR) & M_BUBBLEERR)
41440 
41441 #define S_SPI    8
41442 #define M_SPI    0xffU
41443 #define V_SPI(x) ((x) << S_SPI)
41444 #define G_SPI(x) (((x) >> S_SPI) & M_SPI)
41445 
41446 #define S_SECNT    0
41447 #define M_SECNT    0xffU
41448 #define V_SECNT(x) ((x) << S_SECNT)
41449 #define G_SECNT(x) (((x) >> S_SECNT) & M_SECNT)
41450 
41451 #define A_MPS_TX_SECNT_BUBBLE_CLR 0x942c
41452 
41453 #define S_BUBBLECLR    8
41454 #define M_BUBBLECLR    0xffU
41455 #define V_BUBBLECLR(x) ((x) << S_BUBBLECLR)
41456 #define G_BUBBLECLR(x) (((x) >> S_BUBBLECLR) & M_BUBBLECLR)
41457 
41458 #define S_NCSISECNT    20
41459 #define V_NCSISECNT(x) ((x) << S_NCSISECNT)
41460 #define F_NCSISECNT    V_NCSISECNT(1U)
41461 
41462 #define S_LPBKSECNT    16
41463 #define M_LPBKSECNT    0xfU
41464 #define V_LPBKSECNT(x) ((x) << S_LPBKSECNT)
41465 #define G_LPBKSECNT(x) (((x) >> S_LPBKSECNT) & M_LPBKSECNT)
41466 
41467 #define A_MPS_TX_PORT_ERR 0x9430
41468 
41469 #define S_LPBKPT3    7
41470 #define V_LPBKPT3(x) ((x) << S_LPBKPT3)
41471 #define F_LPBKPT3    V_LPBKPT3(1U)
41472 
41473 #define S_LPBKPT2    6
41474 #define V_LPBKPT2(x) ((x) << S_LPBKPT2)
41475 #define F_LPBKPT2    V_LPBKPT2(1U)
41476 
41477 #define S_LPBKPT1    5
41478 #define V_LPBKPT1(x) ((x) << S_LPBKPT1)
41479 #define F_LPBKPT1    V_LPBKPT1(1U)
41480 
41481 #define S_LPBKPT0    4
41482 #define V_LPBKPT0(x) ((x) << S_LPBKPT0)
41483 #define F_LPBKPT0    V_LPBKPT0(1U)
41484 
41485 #define S_PT3    3
41486 #define V_PT3(x) ((x) << S_PT3)
41487 #define F_PT3    V_PT3(1U)
41488 
41489 #define S_PT2    2
41490 #define V_PT2(x) ((x) << S_PT2)
41491 #define F_PT2    V_PT2(1U)
41492 
41493 #define S_PT1    1
41494 #define V_PT1(x) ((x) << S_PT1)
41495 #define F_PT1    V_PT1(1U)
41496 
41497 #define S_PT0    0
41498 #define V_PT0(x) ((x) << S_PT0)
41499 #define F_PT0    V_PT0(1U)
41500 
41501 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH0 0x9434
41502 
41503 #define S_BPEN    1
41504 #define V_BPEN(x) ((x) << S_BPEN)
41505 #define F_BPEN    V_BPEN(1U)
41506 
41507 #define S_DROPEN    0
41508 #define V_DROPEN(x) ((x) << S_DROPEN)
41509 #define F_DROPEN    V_DROPEN(1U)
41510 
41511 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH1 0x9438
41512 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH2 0x943c
41513 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH3 0x9440
41514 #define A_MPS_TX_DEBUG_REG_TP2TX_10 0x9444
41515 
41516 #define S_SOPCH1    31
41517 #define V_SOPCH1(x) ((x) << S_SOPCH1)
41518 #define F_SOPCH1    V_SOPCH1(1U)
41519 
41520 #define S_EOPCH1    30
41521 #define V_EOPCH1(x) ((x) << S_EOPCH1)
41522 #define F_EOPCH1    V_EOPCH1(1U)
41523 
41524 #define S_SIZECH1    27
41525 #define M_SIZECH1    0x7U
41526 #define V_SIZECH1(x) ((x) << S_SIZECH1)
41527 #define G_SIZECH1(x) (((x) >> S_SIZECH1) & M_SIZECH1)
41528 
41529 #define S_ERRCH1    26
41530 #define V_ERRCH1(x) ((x) << S_ERRCH1)
41531 #define F_ERRCH1    V_ERRCH1(1U)
41532 
41533 #define S_FULLCH1    25
41534 #define V_FULLCH1(x) ((x) << S_FULLCH1)
41535 #define F_FULLCH1    V_FULLCH1(1U)
41536 
41537 #define S_VALIDCH1    24
41538 #define V_VALIDCH1(x) ((x) << S_VALIDCH1)
41539 #define F_VALIDCH1    V_VALIDCH1(1U)
41540 
41541 #define S_DATACH1    16
41542 #define M_DATACH1    0xffU
41543 #define V_DATACH1(x) ((x) << S_DATACH1)
41544 #define G_DATACH1(x) (((x) >> S_DATACH1) & M_DATACH1)
41545 
41546 #define S_SOPCH0    15
41547 #define V_SOPCH0(x) ((x) << S_SOPCH0)
41548 #define F_SOPCH0    V_SOPCH0(1U)
41549 
41550 #define S_EOPCH0    14
41551 #define V_EOPCH0(x) ((x) << S_EOPCH0)
41552 #define F_EOPCH0    V_EOPCH0(1U)
41553 
41554 #define S_SIZECH0    11
41555 #define M_SIZECH0    0x7U
41556 #define V_SIZECH0(x) ((x) << S_SIZECH0)
41557 #define G_SIZECH0(x) (((x) >> S_SIZECH0) & M_SIZECH0)
41558 
41559 #define S_ERRCH0    10
41560 #define V_ERRCH0(x) ((x) << S_ERRCH0)
41561 #define F_ERRCH0    V_ERRCH0(1U)
41562 
41563 #define S_FULLCH0    9
41564 #define V_FULLCH0(x) ((x) << S_FULLCH0)
41565 #define F_FULLCH0    V_FULLCH0(1U)
41566 
41567 #define S_VALIDCH0    8
41568 #define V_VALIDCH0(x) ((x) << S_VALIDCH0)
41569 #define F_VALIDCH0    V_VALIDCH0(1U)
41570 
41571 #define S_DATACH0    0
41572 #define M_DATACH0    0xffU
41573 #define V_DATACH0(x) ((x) << S_DATACH0)
41574 #define G_DATACH0(x) (((x) >> S_DATACH0) & M_DATACH0)
41575 
41576 #define S_T5_SIZECH1    26
41577 #define M_T5_SIZECH1    0xfU
41578 #define V_T5_SIZECH1(x) ((x) << S_T5_SIZECH1)
41579 #define G_T5_SIZECH1(x) (((x) >> S_T5_SIZECH1) & M_T5_SIZECH1)
41580 
41581 #define S_T5_ERRCH1    25
41582 #define V_T5_ERRCH1(x) ((x) << S_T5_ERRCH1)
41583 #define F_T5_ERRCH1    V_T5_ERRCH1(1U)
41584 
41585 #define S_T5_FULLCH1    24
41586 #define V_T5_FULLCH1(x) ((x) << S_T5_FULLCH1)
41587 #define F_T5_FULLCH1    V_T5_FULLCH1(1U)
41588 
41589 #define S_T5_VALIDCH1    23
41590 #define V_T5_VALIDCH1(x) ((x) << S_T5_VALIDCH1)
41591 #define F_T5_VALIDCH1    V_T5_VALIDCH1(1U)
41592 
41593 #define S_T5_DATACH1    16
41594 #define M_T5_DATACH1    0x7fU
41595 #define V_T5_DATACH1(x) ((x) << S_T5_DATACH1)
41596 #define G_T5_DATACH1(x) (((x) >> S_T5_DATACH1) & M_T5_DATACH1)
41597 
41598 #define S_T5_SIZECH0    10
41599 #define M_T5_SIZECH0    0xfU
41600 #define V_T5_SIZECH0(x) ((x) << S_T5_SIZECH0)
41601 #define G_T5_SIZECH0(x) (((x) >> S_T5_SIZECH0) & M_T5_SIZECH0)
41602 
41603 #define S_T5_ERRCH0    9
41604 #define V_T5_ERRCH0(x) ((x) << S_T5_ERRCH0)
41605 #define F_T5_ERRCH0    V_T5_ERRCH0(1U)
41606 
41607 #define S_T5_FULLCH0    8
41608 #define V_T5_FULLCH0(x) ((x) << S_T5_FULLCH0)
41609 #define F_T5_FULLCH0    V_T5_FULLCH0(1U)
41610 
41611 #define S_T5_VALIDCH0    7
41612 #define V_T5_VALIDCH0(x) ((x) << S_T5_VALIDCH0)
41613 #define F_T5_VALIDCH0    V_T5_VALIDCH0(1U)
41614 
41615 #define S_T5_DATACH0    0
41616 #define M_T5_DATACH0    0x7fU
41617 #define V_T5_DATACH0(x) ((x) << S_T5_DATACH0)
41618 #define G_T5_DATACH0(x) (((x) >> S_T5_DATACH0) & M_T5_DATACH0)
41619 
41620 #define A_MPS_TX_DEBUG_REG_TP2TX_32 0x9448
41621 
41622 #define S_SOPCH3    31
41623 #define V_SOPCH3(x) ((x) << S_SOPCH3)
41624 #define F_SOPCH3    V_SOPCH3(1U)
41625 
41626 #define S_EOPCH3    30
41627 #define V_EOPCH3(x) ((x) << S_EOPCH3)
41628 #define F_EOPCH3    V_EOPCH3(1U)
41629 
41630 #define S_SIZECH3    27
41631 #define M_SIZECH3    0x7U
41632 #define V_SIZECH3(x) ((x) << S_SIZECH3)
41633 #define G_SIZECH3(x) (((x) >> S_SIZECH3) & M_SIZECH3)
41634 
41635 #define S_ERRCH3    26
41636 #define V_ERRCH3(x) ((x) << S_ERRCH3)
41637 #define F_ERRCH3    V_ERRCH3(1U)
41638 
41639 #define S_FULLCH3    25
41640 #define V_FULLCH3(x) ((x) << S_FULLCH3)
41641 #define F_FULLCH3    V_FULLCH3(1U)
41642 
41643 #define S_VALIDCH3    24
41644 #define V_VALIDCH3(x) ((x) << S_VALIDCH3)
41645 #define F_VALIDCH3    V_VALIDCH3(1U)
41646 
41647 #define S_DATACH3    16
41648 #define M_DATACH3    0xffU
41649 #define V_DATACH3(x) ((x) << S_DATACH3)
41650 #define G_DATACH3(x) (((x) >> S_DATACH3) & M_DATACH3)
41651 
41652 #define S_SOPCH2    15
41653 #define V_SOPCH2(x) ((x) << S_SOPCH2)
41654 #define F_SOPCH2    V_SOPCH2(1U)
41655 
41656 #define S_EOPCH2    14
41657 #define V_EOPCH2(x) ((x) << S_EOPCH2)
41658 #define F_EOPCH2    V_EOPCH2(1U)
41659 
41660 #define S_SIZECH2    11
41661 #define M_SIZECH2    0x7U
41662 #define V_SIZECH2(x) ((x) << S_SIZECH2)
41663 #define G_SIZECH2(x) (((x) >> S_SIZECH2) & M_SIZECH2)
41664 
41665 #define S_ERRCH2    10
41666 #define V_ERRCH2(x) ((x) << S_ERRCH2)
41667 #define F_ERRCH2    V_ERRCH2(1U)
41668 
41669 #define S_FULLCH2    9
41670 #define V_FULLCH2(x) ((x) << S_FULLCH2)
41671 #define F_FULLCH2    V_FULLCH2(1U)
41672 
41673 #define S_VALIDCH2    8
41674 #define V_VALIDCH2(x) ((x) << S_VALIDCH2)
41675 #define F_VALIDCH2    V_VALIDCH2(1U)
41676 
41677 #define S_DATACH2    0
41678 #define M_DATACH2    0xffU
41679 #define V_DATACH2(x) ((x) << S_DATACH2)
41680 #define G_DATACH2(x) (((x) >> S_DATACH2) & M_DATACH2)
41681 
41682 #define S_T5_SIZECH3    26
41683 #define M_T5_SIZECH3    0xfU
41684 #define V_T5_SIZECH3(x) ((x) << S_T5_SIZECH3)
41685 #define G_T5_SIZECH3(x) (((x) >> S_T5_SIZECH3) & M_T5_SIZECH3)
41686 
41687 #define S_T5_ERRCH3    25
41688 #define V_T5_ERRCH3(x) ((x) << S_T5_ERRCH3)
41689 #define F_T5_ERRCH3    V_T5_ERRCH3(1U)
41690 
41691 #define S_T5_FULLCH3    24
41692 #define V_T5_FULLCH3(x) ((x) << S_T5_FULLCH3)
41693 #define F_T5_FULLCH3    V_T5_FULLCH3(1U)
41694 
41695 #define S_T5_VALIDCH3    23
41696 #define V_T5_VALIDCH3(x) ((x) << S_T5_VALIDCH3)
41697 #define F_T5_VALIDCH3    V_T5_VALIDCH3(1U)
41698 
41699 #define S_T5_DATACH3    16
41700 #define M_T5_DATACH3    0x7fU
41701 #define V_T5_DATACH3(x) ((x) << S_T5_DATACH3)
41702 #define G_T5_DATACH3(x) (((x) >> S_T5_DATACH3) & M_T5_DATACH3)
41703 
41704 #define S_T5_SIZECH2    10
41705 #define M_T5_SIZECH2    0xfU
41706 #define V_T5_SIZECH2(x) ((x) << S_T5_SIZECH2)
41707 #define G_T5_SIZECH2(x) (((x) >> S_T5_SIZECH2) & M_T5_SIZECH2)
41708 
41709 #define S_T5_ERRCH2    9
41710 #define V_T5_ERRCH2(x) ((x) << S_T5_ERRCH2)
41711 #define F_T5_ERRCH2    V_T5_ERRCH2(1U)
41712 
41713 #define S_T5_FULLCH2    8
41714 #define V_T5_FULLCH2(x) ((x) << S_T5_FULLCH2)
41715 #define F_T5_FULLCH2    V_T5_FULLCH2(1U)
41716 
41717 #define S_T5_VALIDCH2    7
41718 #define V_T5_VALIDCH2(x) ((x) << S_T5_VALIDCH2)
41719 #define F_T5_VALIDCH2    V_T5_VALIDCH2(1U)
41720 
41721 #define S_T5_DATACH2    0
41722 #define M_T5_DATACH2    0x7fU
41723 #define V_T5_DATACH2(x) ((x) << S_T5_DATACH2)
41724 #define G_T5_DATACH2(x) (((x) >> S_T5_DATACH2) & M_T5_DATACH2)
41725 
41726 #define A_MPS_TX_DEBUG_REG_TX2MAC_10 0x944c
41727 
41728 #define S_SOPPT1    31
41729 #define V_SOPPT1(x) ((x) << S_SOPPT1)
41730 #define F_SOPPT1    V_SOPPT1(1U)
41731 
41732 #define S_EOPPT1    30
41733 #define V_EOPPT1(x) ((x) << S_EOPPT1)
41734 #define F_EOPPT1    V_EOPPT1(1U)
41735 
41736 #define S_SIZEPT1    27
41737 #define M_SIZEPT1    0x7U
41738 #define V_SIZEPT1(x) ((x) << S_SIZEPT1)
41739 #define G_SIZEPT1(x) (((x) >> S_SIZEPT1) & M_SIZEPT1)
41740 
41741 #define S_ERRPT1    26
41742 #define V_ERRPT1(x) ((x) << S_ERRPT1)
41743 #define F_ERRPT1    V_ERRPT1(1U)
41744 
41745 #define S_FULLPT1    25
41746 #define V_FULLPT1(x) ((x) << S_FULLPT1)
41747 #define F_FULLPT1    V_FULLPT1(1U)
41748 
41749 #define S_VALIDPT1    24
41750 #define V_VALIDPT1(x) ((x) << S_VALIDPT1)
41751 #define F_VALIDPT1    V_VALIDPT1(1U)
41752 
41753 #define S_DATAPT1    16
41754 #define M_DATAPT1    0xffU
41755 #define V_DATAPT1(x) ((x) << S_DATAPT1)
41756 #define G_DATAPT1(x) (((x) >> S_DATAPT1) & M_DATAPT1)
41757 
41758 #define S_SOPPT0    15
41759 #define V_SOPPT0(x) ((x) << S_SOPPT0)
41760 #define F_SOPPT0    V_SOPPT0(1U)
41761 
41762 #define S_EOPPT0    14
41763 #define V_EOPPT0(x) ((x) << S_EOPPT0)
41764 #define F_EOPPT0    V_EOPPT0(1U)
41765 
41766 #define S_SIZEPT0    11
41767 #define M_SIZEPT0    0x7U
41768 #define V_SIZEPT0(x) ((x) << S_SIZEPT0)
41769 #define G_SIZEPT0(x) (((x) >> S_SIZEPT0) & M_SIZEPT0)
41770 
41771 #define S_ERRPT0    10
41772 #define V_ERRPT0(x) ((x) << S_ERRPT0)
41773 #define F_ERRPT0    V_ERRPT0(1U)
41774 
41775 #define S_FULLPT0    9
41776 #define V_FULLPT0(x) ((x) << S_FULLPT0)
41777 #define F_FULLPT0    V_FULLPT0(1U)
41778 
41779 #define S_VALIDPT0    8
41780 #define V_VALIDPT0(x) ((x) << S_VALIDPT0)
41781 #define F_VALIDPT0    V_VALIDPT0(1U)
41782 
41783 #define S_DATAPT0    0
41784 #define M_DATAPT0    0xffU
41785 #define V_DATAPT0(x) ((x) << S_DATAPT0)
41786 #define G_DATAPT0(x) (((x) >> S_DATAPT0) & M_DATAPT0)
41787 
41788 #define S_T5_SIZEPT1    26
41789 #define M_T5_SIZEPT1    0xfU
41790 #define V_T5_SIZEPT1(x) ((x) << S_T5_SIZEPT1)
41791 #define G_T5_SIZEPT1(x) (((x) >> S_T5_SIZEPT1) & M_T5_SIZEPT1)
41792 
41793 #define S_T5_ERRPT1    25
41794 #define V_T5_ERRPT1(x) ((x) << S_T5_ERRPT1)
41795 #define F_T5_ERRPT1    V_T5_ERRPT1(1U)
41796 
41797 #define S_T5_FULLPT1    24
41798 #define V_T5_FULLPT1(x) ((x) << S_T5_FULLPT1)
41799 #define F_T5_FULLPT1    V_T5_FULLPT1(1U)
41800 
41801 #define S_T5_VALIDPT1    23
41802 #define V_T5_VALIDPT1(x) ((x) << S_T5_VALIDPT1)
41803 #define F_T5_VALIDPT1    V_T5_VALIDPT1(1U)
41804 
41805 #define S_T5_DATAPT1    16
41806 #define M_T5_DATAPT1    0x7fU
41807 #define V_T5_DATAPT1(x) ((x) << S_T5_DATAPT1)
41808 #define G_T5_DATAPT1(x) (((x) >> S_T5_DATAPT1) & M_T5_DATAPT1)
41809 
41810 #define S_T5_SIZEPT0    10
41811 #define M_T5_SIZEPT0    0xfU
41812 #define V_T5_SIZEPT0(x) ((x) << S_T5_SIZEPT0)
41813 #define G_T5_SIZEPT0(x) (((x) >> S_T5_SIZEPT0) & M_T5_SIZEPT0)
41814 
41815 #define S_T5_ERRPT0    9
41816 #define V_T5_ERRPT0(x) ((x) << S_T5_ERRPT0)
41817 #define F_T5_ERRPT0    V_T5_ERRPT0(1U)
41818 
41819 #define S_T5_FULLPT0    8
41820 #define V_T5_FULLPT0(x) ((x) << S_T5_FULLPT0)
41821 #define F_T5_FULLPT0    V_T5_FULLPT0(1U)
41822 
41823 #define S_T5_VALIDPT0    7
41824 #define V_T5_VALIDPT0(x) ((x) << S_T5_VALIDPT0)
41825 #define F_T5_VALIDPT0    V_T5_VALIDPT0(1U)
41826 
41827 #define S_T5_DATAPT0    0
41828 #define M_T5_DATAPT0    0x7fU
41829 #define V_T5_DATAPT0(x) ((x) << S_T5_DATAPT0)
41830 #define G_T5_DATAPT0(x) (((x) >> S_T5_DATAPT0) & M_T5_DATAPT0)
41831 
41832 #define A_MPS_TX_DEBUG_REG_TX2MAC_32 0x9450
41833 
41834 #define S_SOPPT3    31
41835 #define V_SOPPT3(x) ((x) << S_SOPPT3)
41836 #define F_SOPPT3    V_SOPPT3(1U)
41837 
41838 #define S_EOPPT3    30
41839 #define V_EOPPT3(x) ((x) << S_EOPPT3)
41840 #define F_EOPPT3    V_EOPPT3(1U)
41841 
41842 #define S_SIZEPT3    27
41843 #define M_SIZEPT3    0x7U
41844 #define V_SIZEPT3(x) ((x) << S_SIZEPT3)
41845 #define G_SIZEPT3(x) (((x) >> S_SIZEPT3) & M_SIZEPT3)
41846 
41847 #define S_ERRPT3    26
41848 #define V_ERRPT3(x) ((x) << S_ERRPT3)
41849 #define F_ERRPT3    V_ERRPT3(1U)
41850 
41851 #define S_FULLPT3    25
41852 #define V_FULLPT3(x) ((x) << S_FULLPT3)
41853 #define F_FULLPT3    V_FULLPT3(1U)
41854 
41855 #define S_VALIDPT3    24
41856 #define V_VALIDPT3(x) ((x) << S_VALIDPT3)
41857 #define F_VALIDPT3    V_VALIDPT3(1U)
41858 
41859 #define S_DATAPT3    16
41860 #define M_DATAPT3    0xffU
41861 #define V_DATAPT3(x) ((x) << S_DATAPT3)
41862 #define G_DATAPT3(x) (((x) >> S_DATAPT3) & M_DATAPT3)
41863 
41864 #define S_SOPPT2    15
41865 #define V_SOPPT2(x) ((x) << S_SOPPT2)
41866 #define F_SOPPT2    V_SOPPT2(1U)
41867 
41868 #define S_EOPPT2    14
41869 #define V_EOPPT2(x) ((x) << S_EOPPT2)
41870 #define F_EOPPT2    V_EOPPT2(1U)
41871 
41872 #define S_SIZEPT2    11
41873 #define M_SIZEPT2    0x7U
41874 #define V_SIZEPT2(x) ((x) << S_SIZEPT2)
41875 #define G_SIZEPT2(x) (((x) >> S_SIZEPT2) & M_SIZEPT2)
41876 
41877 #define S_ERRPT2    10
41878 #define V_ERRPT2(x) ((x) << S_ERRPT2)
41879 #define F_ERRPT2    V_ERRPT2(1U)
41880 
41881 #define S_FULLPT2    9
41882 #define V_FULLPT2(x) ((x) << S_FULLPT2)
41883 #define F_FULLPT2    V_FULLPT2(1U)
41884 
41885 #define S_VALIDPT2    8
41886 #define V_VALIDPT2(x) ((x) << S_VALIDPT2)
41887 #define F_VALIDPT2    V_VALIDPT2(1U)
41888 
41889 #define S_DATAPT2    0
41890 #define M_DATAPT2    0xffU
41891 #define V_DATAPT2(x) ((x) << S_DATAPT2)
41892 #define G_DATAPT2(x) (((x) >> S_DATAPT2) & M_DATAPT2)
41893 
41894 #define S_T5_SIZEPT3    26
41895 #define M_T5_SIZEPT3    0xfU
41896 #define V_T5_SIZEPT3(x) ((x) << S_T5_SIZEPT3)
41897 #define G_T5_SIZEPT3(x) (((x) >> S_T5_SIZEPT3) & M_T5_SIZEPT3)
41898 
41899 #define S_T5_ERRPT3    25
41900 #define V_T5_ERRPT3(x) ((x) << S_T5_ERRPT3)
41901 #define F_T5_ERRPT3    V_T5_ERRPT3(1U)
41902 
41903 #define S_T5_FULLPT3    24
41904 #define V_T5_FULLPT3(x) ((x) << S_T5_FULLPT3)
41905 #define F_T5_FULLPT3    V_T5_FULLPT3(1U)
41906 
41907 #define S_T5_VALIDPT3    23
41908 #define V_T5_VALIDPT3(x) ((x) << S_T5_VALIDPT3)
41909 #define F_T5_VALIDPT3    V_T5_VALIDPT3(1U)
41910 
41911 #define S_T5_DATAPT3    16
41912 #define M_T5_DATAPT3    0x7fU
41913 #define V_T5_DATAPT3(x) ((x) << S_T5_DATAPT3)
41914 #define G_T5_DATAPT3(x) (((x) >> S_T5_DATAPT3) & M_T5_DATAPT3)
41915 
41916 #define S_T5_SIZEPT2    10
41917 #define M_T5_SIZEPT2    0xfU
41918 #define V_T5_SIZEPT2(x) ((x) << S_T5_SIZEPT2)
41919 #define G_T5_SIZEPT2(x) (((x) >> S_T5_SIZEPT2) & M_T5_SIZEPT2)
41920 
41921 #define S_T5_ERRPT2    9
41922 #define V_T5_ERRPT2(x) ((x) << S_T5_ERRPT2)
41923 #define F_T5_ERRPT2    V_T5_ERRPT2(1U)
41924 
41925 #define S_T5_FULLPT2    8
41926 #define V_T5_FULLPT2(x) ((x) << S_T5_FULLPT2)
41927 #define F_T5_FULLPT2    V_T5_FULLPT2(1U)
41928 
41929 #define S_T5_VALIDPT2    7
41930 #define V_T5_VALIDPT2(x) ((x) << S_T5_VALIDPT2)
41931 #define F_T5_VALIDPT2    V_T5_VALIDPT2(1U)
41932 
41933 #define S_T5_DATAPT2    0
41934 #define M_T5_DATAPT2    0x7fU
41935 #define V_T5_DATAPT2(x) ((x) << S_T5_DATAPT2)
41936 #define G_T5_DATAPT2(x) (((x) >> S_T5_DATAPT2) & M_T5_DATAPT2)
41937 
41938 #define A_MPS_TX_SGE_CH_PAUSE_IGNR 0x9454
41939 
41940 #define S_SGEPAUSEIGNR    0
41941 #define M_SGEPAUSEIGNR    0xfU
41942 #define V_SGEPAUSEIGNR(x) ((x) << S_SGEPAUSEIGNR)
41943 #define G_SGEPAUSEIGNR(x) (((x) >> S_SGEPAUSEIGNR) & M_SGEPAUSEIGNR)
41944 
41945 #define A_MPS_T5_TX_SGE_CH_PAUSE_IGNR 0x9454
41946 
41947 #define S_T5SGEPAUSEIGNR    0
41948 #define M_T5SGEPAUSEIGNR    0xffffU
41949 #define V_T5SGEPAUSEIGNR(x) ((x) << S_T5SGEPAUSEIGNR)
41950 #define G_T5SGEPAUSEIGNR(x) (((x) >> S_T5SGEPAUSEIGNR) & M_T5SGEPAUSEIGNR)
41951 
41952 #define A_MPS_TX_DEBUG_SUBPART_SEL 0x9458
41953 
41954 #define S_SUBPRTH    11
41955 #define M_SUBPRTH    0x1fU
41956 #define V_SUBPRTH(x) ((x) << S_SUBPRTH)
41957 #define G_SUBPRTH(x) (((x) >> S_SUBPRTH) & M_SUBPRTH)
41958 
41959 #define S_PORTH    8
41960 #define M_PORTH    0x7U
41961 #define V_PORTH(x) ((x) << S_PORTH)
41962 #define G_PORTH(x) (((x) >> S_PORTH) & M_PORTH)
41963 
41964 #define S_SUBPRTL    3
41965 #define M_SUBPRTL    0x1fU
41966 #define V_SUBPRTL(x) ((x) << S_SUBPRTL)
41967 #define G_SUBPRTL(x) (((x) >> S_SUBPRTL) & M_SUBPRTL)
41968 
41969 #define S_PORTL    0
41970 #define M_PORTL    0x7U
41971 #define V_PORTL(x) ((x) << S_PORTL)
41972 #define G_PORTL(x) (((x) >> S_PORTL) & M_PORTL)
41973 
41974 #define A_MPS_TX_PAD_CTL 0x945c
41975 
41976 #define S_LPBKPADENPT3    7
41977 #define V_LPBKPADENPT3(x) ((x) << S_LPBKPADENPT3)
41978 #define F_LPBKPADENPT3    V_LPBKPADENPT3(1U)
41979 
41980 #define S_LPBKPADENPT2    6
41981 #define V_LPBKPADENPT2(x) ((x) << S_LPBKPADENPT2)
41982 #define F_LPBKPADENPT2    V_LPBKPADENPT2(1U)
41983 
41984 #define S_LPBKPADENPT1    5
41985 #define V_LPBKPADENPT1(x) ((x) << S_LPBKPADENPT1)
41986 #define F_LPBKPADENPT1    V_LPBKPADENPT1(1U)
41987 
41988 #define S_LPBKPADENPT0    4
41989 #define V_LPBKPADENPT0(x) ((x) << S_LPBKPADENPT0)
41990 #define F_LPBKPADENPT0    V_LPBKPADENPT0(1U)
41991 
41992 #define S_MACPADENPT3    3
41993 #define V_MACPADENPT3(x) ((x) << S_MACPADENPT3)
41994 #define F_MACPADENPT3    V_MACPADENPT3(1U)
41995 
41996 #define S_MACPADENPT2    2
41997 #define V_MACPADENPT2(x) ((x) << S_MACPADENPT2)
41998 #define F_MACPADENPT2    V_MACPADENPT2(1U)
41999 
42000 #define S_MACPADENPT1    1
42001 #define V_MACPADENPT1(x) ((x) << S_MACPADENPT1)
42002 #define F_MACPADENPT1    V_MACPADENPT1(1U)
42003 
42004 #define S_MACPADENPT0    0
42005 #define V_MACPADENPT0(x) ((x) << S_MACPADENPT0)
42006 #define F_MACPADENPT0    V_MACPADENPT0(1U)
42007 
42008 #define A_MPS_TX_PFVF_PORT_DROP_TP 0x9460
42009 
42010 #define S_TP2MPS_CH3    24
42011 #define M_TP2MPS_CH3    0xffU
42012 #define V_TP2MPS_CH3(x) ((x) << S_TP2MPS_CH3)
42013 #define G_TP2MPS_CH3(x) (((x) >> S_TP2MPS_CH3) & M_TP2MPS_CH3)
42014 
42015 #define S_TP2MPS_CH2    16
42016 #define M_TP2MPS_CH2    0xffU
42017 #define V_TP2MPS_CH2(x) ((x) << S_TP2MPS_CH2)
42018 #define G_TP2MPS_CH2(x) (((x) >> S_TP2MPS_CH2) & M_TP2MPS_CH2)
42019 
42020 #define S_TP2MPS_CH1    8
42021 #define M_TP2MPS_CH1    0xffU
42022 #define V_TP2MPS_CH1(x) ((x) << S_TP2MPS_CH1)
42023 #define G_TP2MPS_CH1(x) (((x) >> S_TP2MPS_CH1) & M_TP2MPS_CH1)
42024 
42025 #define S_TP2MPS_CH0    0
42026 #define M_TP2MPS_CH0    0xffU
42027 #define V_TP2MPS_CH0(x) ((x) << S_TP2MPS_CH0)
42028 #define G_TP2MPS_CH0(x) (((x) >> S_TP2MPS_CH0) & M_TP2MPS_CH0)
42029 
42030 #define A_MPS_TX_PFVF_PORT_DROP_NCSI 0x9464
42031 
42032 #define S_NCSI_CH4    0
42033 #define M_NCSI_CH4    0xffU
42034 #define V_NCSI_CH4(x) ((x) << S_NCSI_CH4)
42035 #define G_NCSI_CH4(x) (((x) >> S_NCSI_CH4) & M_NCSI_CH4)
42036 
42037 #define A_MPS_TX_PFVF_PORT_DROP_CTL 0x9468
42038 
42039 #define S_PFNOVFDROP    5
42040 #define V_PFNOVFDROP(x) ((x) << S_PFNOVFDROP)
42041 #define F_PFNOVFDROP    V_PFNOVFDROP(1U)
42042 
42043 #define S_NCSI_CH4_CLR    4
42044 #define V_NCSI_CH4_CLR(x) ((x) << S_NCSI_CH4_CLR)
42045 #define F_NCSI_CH4_CLR    V_NCSI_CH4_CLR(1U)
42046 
42047 #define S_TP2MPS_CH3_CLR    3
42048 #define V_TP2MPS_CH3_CLR(x) ((x) << S_TP2MPS_CH3_CLR)
42049 #define F_TP2MPS_CH3_CLR    V_TP2MPS_CH3_CLR(1U)
42050 
42051 #define S_TP2MPS_CH2_CLR    2
42052 #define V_TP2MPS_CH2_CLR(x) ((x) << S_TP2MPS_CH2_CLR)
42053 #define F_TP2MPS_CH2_CLR    V_TP2MPS_CH2_CLR(1U)
42054 
42055 #define S_TP2MPS_CH1_CLR    1
42056 #define V_TP2MPS_CH1_CLR(x) ((x) << S_TP2MPS_CH1_CLR)
42057 #define F_TP2MPS_CH1_CLR    V_TP2MPS_CH1_CLR(1U)
42058 
42059 #define S_TP2MPS_CH0_CLR    0
42060 #define V_TP2MPS_CH0_CLR(x) ((x) << S_TP2MPS_CH0_CLR)
42061 #define F_TP2MPS_CH0_CLR    V_TP2MPS_CH0_CLR(1U)
42062 
42063 #define A_MPS_TX_CGEN 0x946c
42064 
42065 #define S_TXOUTLPBK3_CGEN    31
42066 #define V_TXOUTLPBK3_CGEN(x) ((x) << S_TXOUTLPBK3_CGEN)
42067 #define F_TXOUTLPBK3_CGEN    V_TXOUTLPBK3_CGEN(1U)
42068 
42069 #define S_TXOUTLPBK2_CGEN    30
42070 #define V_TXOUTLPBK2_CGEN(x) ((x) << S_TXOUTLPBK2_CGEN)
42071 #define F_TXOUTLPBK2_CGEN    V_TXOUTLPBK2_CGEN(1U)
42072 
42073 #define S_TXOUTLPBK1_CGEN    29
42074 #define V_TXOUTLPBK1_CGEN(x) ((x) << S_TXOUTLPBK1_CGEN)
42075 #define F_TXOUTLPBK1_CGEN    V_TXOUTLPBK1_CGEN(1U)
42076 
42077 #define S_TXOUTLPBK0_CGEN    28
42078 #define V_TXOUTLPBK0_CGEN(x) ((x) << S_TXOUTLPBK0_CGEN)
42079 #define F_TXOUTLPBK0_CGEN    V_TXOUTLPBK0_CGEN(1U)
42080 
42081 #define S_TXOUTMAC3_CGEN    27
42082 #define V_TXOUTMAC3_CGEN(x) ((x) << S_TXOUTMAC3_CGEN)
42083 #define F_TXOUTMAC3_CGEN    V_TXOUTMAC3_CGEN(1U)
42084 
42085 #define S_TXOUTMAC2_CGEN    26
42086 #define V_TXOUTMAC2_CGEN(x) ((x) << S_TXOUTMAC2_CGEN)
42087 #define F_TXOUTMAC2_CGEN    V_TXOUTMAC2_CGEN(1U)
42088 
42089 #define S_TXOUTMAC1_CGEN    25
42090 #define V_TXOUTMAC1_CGEN(x) ((x) << S_TXOUTMAC1_CGEN)
42091 #define F_TXOUTMAC1_CGEN    V_TXOUTMAC1_CGEN(1U)
42092 
42093 #define S_TXOUTMAC0_CGEN    24
42094 #define V_TXOUTMAC0_CGEN(x) ((x) << S_TXOUTMAC0_CGEN)
42095 #define F_TXOUTMAC0_CGEN    V_TXOUTMAC0_CGEN(1U)
42096 
42097 #define S_TXSCHLPBK3_CGEN    23
42098 #define V_TXSCHLPBK3_CGEN(x) ((x) << S_TXSCHLPBK3_CGEN)
42099 #define F_TXSCHLPBK3_CGEN    V_TXSCHLPBK3_CGEN(1U)
42100 
42101 #define S_TXSCHLPBK2_CGEN    22
42102 #define V_TXSCHLPBK2_CGEN(x) ((x) << S_TXSCHLPBK2_CGEN)
42103 #define F_TXSCHLPBK2_CGEN    V_TXSCHLPBK2_CGEN(1U)
42104 
42105 #define S_TXSCHLPBK1_CGEN    21
42106 #define V_TXSCHLPBK1_CGEN(x) ((x) << S_TXSCHLPBK1_CGEN)
42107 #define F_TXSCHLPBK1_CGEN    V_TXSCHLPBK1_CGEN(1U)
42108 
42109 #define S_TXSCHLPBK0_CGEN    20
42110 #define V_TXSCHLPBK0_CGEN(x) ((x) << S_TXSCHLPBK0_CGEN)
42111 #define F_TXSCHLPBK0_CGEN    V_TXSCHLPBK0_CGEN(1U)
42112 
42113 #define S_TXSCHMAC3_CGEN    19
42114 #define V_TXSCHMAC3_CGEN(x) ((x) << S_TXSCHMAC3_CGEN)
42115 #define F_TXSCHMAC3_CGEN    V_TXSCHMAC3_CGEN(1U)
42116 
42117 #define S_TXSCHMAC2_CGEN    18
42118 #define V_TXSCHMAC2_CGEN(x) ((x) << S_TXSCHMAC2_CGEN)
42119 #define F_TXSCHMAC2_CGEN    V_TXSCHMAC2_CGEN(1U)
42120 
42121 #define S_TXSCHMAC1_CGEN    17
42122 #define V_TXSCHMAC1_CGEN(x) ((x) << S_TXSCHMAC1_CGEN)
42123 #define F_TXSCHMAC1_CGEN    V_TXSCHMAC1_CGEN(1U)
42124 
42125 #define S_TXSCHMAC0_CGEN    16
42126 #define V_TXSCHMAC0_CGEN(x) ((x) << S_TXSCHMAC0_CGEN)
42127 #define F_TXSCHMAC0_CGEN    V_TXSCHMAC0_CGEN(1U)
42128 
42129 #define S_TXINCH4_CGEN    15
42130 #define V_TXINCH4_CGEN(x) ((x) << S_TXINCH4_CGEN)
42131 #define F_TXINCH4_CGEN    V_TXINCH4_CGEN(1U)
42132 
42133 #define S_TXINCH3_CGEN    14
42134 #define V_TXINCH3_CGEN(x) ((x) << S_TXINCH3_CGEN)
42135 #define F_TXINCH3_CGEN    V_TXINCH3_CGEN(1U)
42136 
42137 #define S_TXINCH2_CGEN    13
42138 #define V_TXINCH2_CGEN(x) ((x) << S_TXINCH2_CGEN)
42139 #define F_TXINCH2_CGEN    V_TXINCH2_CGEN(1U)
42140 
42141 #define S_TXINCH1_CGEN    12
42142 #define V_TXINCH1_CGEN(x) ((x) << S_TXINCH1_CGEN)
42143 #define F_TXINCH1_CGEN    V_TXINCH1_CGEN(1U)
42144 
42145 #define S_TXINCH0_CGEN    11
42146 #define V_TXINCH0_CGEN(x) ((x) << S_TXINCH0_CGEN)
42147 #define F_TXINCH0_CGEN    V_TXINCH0_CGEN(1U)
42148 
42149 #define A_MPS_TX_CGEN_DYNAMIC 0x9470
42150 #define A_MPS_TX2RX_CH_MAP 0x9474
42151 
42152 #define S_ENABLELBK_CH3    3
42153 #define V_ENABLELBK_CH3(x) ((x) << S_ENABLELBK_CH3)
42154 #define F_ENABLELBK_CH3    V_ENABLELBK_CH3(1U)
42155 
42156 #define S_ENABLELBK_CH2    2
42157 #define V_ENABLELBK_CH2(x) ((x) << S_ENABLELBK_CH2)
42158 #define F_ENABLELBK_CH2    V_ENABLELBK_CH2(1U)
42159 
42160 #define S_ENABLELBK_CH1    1
42161 #define V_ENABLELBK_CH1(x) ((x) << S_ENABLELBK_CH1)
42162 #define F_ENABLELBK_CH1    V_ENABLELBK_CH1(1U)
42163 
42164 #define S_ENABLELBK_CH0    0
42165 #define V_ENABLELBK_CH0(x) ((x) << S_ENABLELBK_CH0)
42166 #define F_ENABLELBK_CH0    V_ENABLELBK_CH0(1U)
42167 
42168 #define A_MPS_TX_DBG_CNT_CTL 0x9478
42169 
42170 #define S_DBG_CNT_CTL    0
42171 #define M_DBG_CNT_CTL    0xffU
42172 #define V_DBG_CNT_CTL(x) ((x) << S_DBG_CNT_CTL)
42173 #define G_DBG_CNT_CTL(x) (((x) >> S_DBG_CNT_CTL) & M_DBG_CNT_CTL)
42174 
42175 #define A_MPS_TX_DBG_CNT 0x947c
42176 #define A_MPS_TX_INT2_ENABLE 0x9498
42177 #define A_MPS_TX_INT2_CAUSE 0x949c
42178 #define A_MPS_TX_PERR2_ENABLE 0x94a0
42179 #define A_MPS_TX_INT3_ENABLE 0x94a4
42180 #define A_MPS_TX_INT3_CAUSE 0x94a8
42181 #define A_MPS_TX_PERR3_ENABLE 0x94ac
42182 #define A_MPS_TX_INT4_ENABLE 0x94b0
42183 #define A_MPS_TX_INT4_CAUSE 0x94b4
42184 #define A_MPS_TX_PERR4_ENABLE 0x94b8
42185 #define A_MPS_STAT_CTL 0x9600
42186 
42187 #define S_COUNTVFINPF    1
42188 #define V_COUNTVFINPF(x) ((x) << S_COUNTVFINPF)
42189 #define F_COUNTVFINPF    V_COUNTVFINPF(1U)
42190 
42191 #define S_LPBKERRSTAT    0
42192 #define V_LPBKERRSTAT(x) ((x) << S_LPBKERRSTAT)
42193 #define F_LPBKERRSTAT    V_LPBKERRSTAT(1U)
42194 
42195 #define S_STATSTOPCTRL    10
42196 #define V_STATSTOPCTRL(x) ((x) << S_STATSTOPCTRL)
42197 #define F_STATSTOPCTRL    V_STATSTOPCTRL(1U)
42198 
42199 #define S_STOPSTAT    9
42200 #define V_STOPSTAT(x) ((x) << S_STOPSTAT)
42201 #define F_STOPSTAT    V_STOPSTAT(1U)
42202 
42203 #define S_STATWRITECTRL    8
42204 #define V_STATWRITECTRL(x) ((x) << S_STATWRITECTRL)
42205 #define F_STATWRITECTRL    V_STATWRITECTRL(1U)
42206 
42207 #define S_COUNTLBPF    7
42208 #define V_COUNTLBPF(x) ((x) << S_COUNTLBPF)
42209 #define F_COUNTLBPF    V_COUNTLBPF(1U)
42210 
42211 #define S_COUNTLBVF    6
42212 #define V_COUNTLBVF(x) ((x) << S_COUNTLBVF)
42213 #define F_COUNTLBVF    V_COUNTLBVF(1U)
42214 
42215 #define S_COUNTPAUSEMCRX    5
42216 #define V_COUNTPAUSEMCRX(x) ((x) << S_COUNTPAUSEMCRX)
42217 #define F_COUNTPAUSEMCRX    V_COUNTPAUSEMCRX(1U)
42218 
42219 #define S_COUNTPAUSESTATRX    4
42220 #define V_COUNTPAUSESTATRX(x) ((x) << S_COUNTPAUSESTATRX)
42221 #define F_COUNTPAUSESTATRX    V_COUNTPAUSESTATRX(1U)
42222 
42223 #define S_COUNTPAUSEMCTX    3
42224 #define V_COUNTPAUSEMCTX(x) ((x) << S_COUNTPAUSEMCTX)
42225 #define F_COUNTPAUSEMCTX    V_COUNTPAUSEMCTX(1U)
42226 
42227 #define S_COUNTPAUSESTATTX    2
42228 #define V_COUNTPAUSESTATTX(x) ((x) << S_COUNTPAUSESTATTX)
42229 #define F_COUNTPAUSESTATTX    V_COUNTPAUSESTATTX(1U)
42230 
42231 #define A_MPS_STAT_INT_ENABLE 0x9608
42232 
42233 #define S_PLREADSYNCERR    0
42234 #define V_PLREADSYNCERR(x) ((x) << S_PLREADSYNCERR)
42235 #define F_PLREADSYNCERR    V_PLREADSYNCERR(1U)
42236 
42237 #define A_MPS_STAT_INT_CAUSE 0x960c
42238 #define A_MPS_STAT_PERR_INT_ENABLE_SRAM 0x9610
42239 
42240 #define S_RXBG    20
42241 #define V_RXBG(x) ((x) << S_RXBG)
42242 #define F_RXBG    V_RXBG(1U)
42243 
42244 #define S_RXVF    18
42245 #define M_RXVF    0x3U
42246 #define V_RXVF(x) ((x) << S_RXVF)
42247 #define G_RXVF(x) (((x) >> S_RXVF) & M_RXVF)
42248 
42249 #define S_TXVF    16
42250 #define M_TXVF    0x3U
42251 #define V_TXVF(x) ((x) << S_TXVF)
42252 #define G_TXVF(x) (((x) >> S_TXVF) & M_TXVF)
42253 
42254 #define S_RXPF    13
42255 #define M_RXPF    0x7U
42256 #define V_RXPF(x) ((x) << S_RXPF)
42257 #define G_RXPF(x) (((x) >> S_RXPF) & M_RXPF)
42258 
42259 #define S_TXPF    11
42260 #define M_TXPF    0x3U
42261 #define V_TXPF(x) ((x) << S_TXPF)
42262 #define G_TXPF(x) (((x) >> S_TXPF) & M_TXPF)
42263 
42264 #define S_RXPORT    7
42265 #define M_RXPORT    0xfU
42266 #define V_RXPORT(x) ((x) << S_RXPORT)
42267 #define G_RXPORT(x) (((x) >> S_RXPORT) & M_RXPORT)
42268 
42269 #define S_LBPORT    4
42270 #define M_LBPORT    0x7U
42271 #define V_LBPORT(x) ((x) << S_LBPORT)
42272 #define G_LBPORT(x) (((x) >> S_LBPORT) & M_LBPORT)
42273 
42274 #define S_TXPORT    0
42275 #define M_TXPORT    0xfU
42276 #define V_TXPORT(x) ((x) << S_TXPORT)
42277 #define G_TXPORT(x) (((x) >> S_TXPORT) & M_TXPORT)
42278 
42279 #define S_T5_RXBG    27
42280 #define M_T5_RXBG    0x3U
42281 #define V_T5_RXBG(x) ((x) << S_T5_RXBG)
42282 #define G_T5_RXBG(x) (((x) >> S_T5_RXBG) & M_T5_RXBG)
42283 
42284 #define S_T5_RXPF    22
42285 #define M_T5_RXPF    0x1fU
42286 #define V_T5_RXPF(x) ((x) << S_T5_RXPF)
42287 #define G_T5_RXPF(x) (((x) >> S_T5_RXPF) & M_T5_RXPF)
42288 
42289 #define S_T5_TXPF    18
42290 #define M_T5_TXPF    0xfU
42291 #define V_T5_TXPF(x) ((x) << S_T5_TXPF)
42292 #define G_T5_TXPF(x) (((x) >> S_T5_TXPF) & M_T5_TXPF)
42293 
42294 #define S_T5_RXPORT    11
42295 #define M_T5_RXPORT    0x7fU
42296 #define V_T5_RXPORT(x) ((x) << S_T5_RXPORT)
42297 #define G_T5_RXPORT(x) (((x) >> S_T5_RXPORT) & M_T5_RXPORT)
42298 
42299 #define S_T5_LBPORT    6
42300 #define M_T5_LBPORT    0x1fU
42301 #define V_T5_LBPORT(x) ((x) << S_T5_LBPORT)
42302 #define G_T5_LBPORT(x) (((x) >> S_T5_LBPORT) & M_T5_LBPORT)
42303 
42304 #define S_T5_TXPORT    0
42305 #define M_T5_TXPORT    0x3fU
42306 #define V_T5_TXPORT(x) ((x) << S_T5_TXPORT)
42307 #define G_T5_TXPORT(x) (((x) >> S_T5_TXPORT) & M_T5_TXPORT)
42308 
42309 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
42310 #define A_MPS_STAT_PERR_ENABLE_SRAM 0x9618
42311 #define A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO 0x961c
42312 
42313 #define S_TX    12
42314 #define M_TX    0xffU
42315 #define V_TX(x) ((x) << S_TX)
42316 #define G_TX(x) (((x) >> S_TX) & M_TX)
42317 
42318 #define S_TXPAUSEFIFO    8
42319 #define M_TXPAUSEFIFO    0xfU
42320 #define V_TXPAUSEFIFO(x) ((x) << S_TXPAUSEFIFO)
42321 #define G_TXPAUSEFIFO(x) (((x) >> S_TXPAUSEFIFO) & M_TXPAUSEFIFO)
42322 
42323 #define S_DROP    0
42324 #define M_DROP    0xffU
42325 #define V_DROP(x) ((x) << S_DROP)
42326 #define G_DROP(x) (((x) >> S_DROP) & M_DROP)
42327 
42328 #define S_TXCH    20
42329 #define M_TXCH    0xfU
42330 #define V_TXCH(x) ((x) << S_TXCH)
42331 #define G_TXCH(x) (((x) >> S_TXCH) & M_TXCH)
42332 
42333 #define A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
42334 #define A_MPS_STAT_PERR_ENABLE_TX_FIFO 0x9624
42335 #define A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO 0x9628
42336 
42337 #define S_PAUSEFIFO    20
42338 #define M_PAUSEFIFO    0xfU
42339 #define V_PAUSEFIFO(x) ((x) << S_PAUSEFIFO)
42340 #define G_PAUSEFIFO(x) (((x) >> S_PAUSEFIFO) & M_PAUSEFIFO)
42341 
42342 #define S_LPBK    16
42343 #define M_LPBK    0xfU
42344 #define V_LPBK(x) ((x) << S_LPBK)
42345 #define G_LPBK(x) (((x) >> S_LPBK) & M_LPBK)
42346 
42347 #define S_NQ    8
42348 #define M_NQ    0xffU
42349 #define V_NQ(x) ((x) << S_NQ)
42350 #define G_NQ(x) (((x) >> S_NQ) & M_NQ)
42351 
42352 #define S_PV    4
42353 #define M_PV    0xfU
42354 #define V_PV(x) ((x) << S_PV)
42355 #define G_PV(x) (((x) >> S_PV) & M_PV)
42356 
42357 #define S_MAC    0
42358 #define M_MAC    0xfU
42359 #define V_MAC(x) ((x) << S_MAC)
42360 #define G_MAC(x) (((x) >> S_MAC) & M_MAC)
42361 
42362 #define A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c
42363 #define A_MPS_STAT_PERR_ENABLE_RX_FIFO 0x9630
42364 #define A_MPS_STAT_PERR_INJECT 0x9634
42365 
42366 #define S_STATMEMSEL    1
42367 #define M_STATMEMSEL    0x7fU
42368 #define V_STATMEMSEL(x) ((x) << S_STATMEMSEL)
42369 #define G_STATMEMSEL(x) (((x) >> S_STATMEMSEL) & M_STATMEMSEL)
42370 
42371 #define A_MPS_STAT_DEBUG_SUB_SEL 0x9638
42372 
42373 #define S_STATSSUBPRTH    5
42374 #define M_STATSSUBPRTH    0x1fU
42375 #define V_STATSSUBPRTH(x) ((x) << S_STATSSUBPRTH)
42376 #define G_STATSSUBPRTH(x) (((x) >> S_STATSSUBPRTH) & M_STATSSUBPRTH)
42377 
42378 #define S_STATSSUBPRTL    0
42379 #define M_STATSSUBPRTL    0x1fU
42380 #define V_STATSSUBPRTL(x) ((x) << S_STATSSUBPRTL)
42381 #define G_STATSSUBPRTL(x) (((x) >> S_STATSSUBPRTL) & M_STATSSUBPRTL)
42382 
42383 #define S_STATSUBPRTH    5
42384 #define M_STATSUBPRTH    0x1fU
42385 #define V_STATSUBPRTH(x) ((x) << S_STATSUBPRTH)
42386 #define G_STATSUBPRTH(x) (((x) >> S_STATSUBPRTH) & M_STATSUBPRTH)
42387 
42388 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
42389 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
42390 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
42391 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
42392 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
42393 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
42394 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
42395 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
42396 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
42397 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
42398 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
42399 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
42400 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
42401 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
42402 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
42403 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
42404 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
42405 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
42406 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
42407 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
42408 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
42409 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
42410 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
42411 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
42412 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
42413 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
42414 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
42415 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
42416 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
42417 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
42418 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
42419 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
42420 #define A_MPS_STAT_PERR_INT_ENABLE_SRAM1 0x96c0
42421 
42422 #define S_T5_RXVF    5
42423 #define M_T5_RXVF    0x7U
42424 #define V_T5_RXVF(x) ((x) << S_T5_RXVF)
42425 #define G_T5_RXVF(x) (((x) >> S_T5_RXVF) & M_T5_RXVF)
42426 
42427 #define S_T5_TXVF    0
42428 #define M_T5_TXVF    0x1fU
42429 #define V_T5_TXVF(x) ((x) << S_T5_TXVF)
42430 #define G_T5_TXVF(x) (((x) >> S_T5_TXVF) & M_T5_TXVF)
42431 
42432 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM1 0x96c4
42433 #define A_MPS_STAT_PERR_ENABLE_SRAM1 0x96c8
42434 #define A_MPS_STAT_STOP_UPD_BG 0x96cc
42435 
42436 #define S_BGRX    0
42437 #define M_BGRX    0xfU
42438 #define V_BGRX(x) ((x) << S_BGRX)
42439 #define G_BGRX(x) (((x) >> S_BGRX) & M_BGRX)
42440 
42441 #define A_MPS_STAT_STOP_UPD_PORT 0x96d0
42442 
42443 #define S_PTLPBK    8
42444 #define M_PTLPBK    0xfU
42445 #define V_PTLPBK(x) ((x) << S_PTLPBK)
42446 #define G_PTLPBK(x) (((x) >> S_PTLPBK) & M_PTLPBK)
42447 
42448 #define S_PTTX    4
42449 #define M_PTTX    0xfU
42450 #define V_PTTX(x) ((x) << S_PTTX)
42451 #define G_PTTX(x) (((x) >> S_PTTX) & M_PTTX)
42452 
42453 #define S_PTRX    0
42454 #define M_PTRX    0xfU
42455 #define V_PTRX(x) ((x) << S_PTRX)
42456 #define G_PTRX(x) (((x) >> S_PTRX) & M_PTRX)
42457 
42458 #define A_MPS_STAT_STOP_UPD_PF 0x96d4
42459 
42460 #define S_PFTX    8
42461 #define M_PFTX    0xffU
42462 #define V_PFTX(x) ((x) << S_PFTX)
42463 #define G_PFTX(x) (((x) >> S_PFTX) & M_PFTX)
42464 
42465 #define S_PFRX    0
42466 #define M_PFRX    0xffU
42467 #define V_PFRX(x) ((x) << S_PFRX)
42468 #define G_PFRX(x) (((x) >> S_PFRX) & M_PFRX)
42469 
42470 #define A_MPS_STAT_STOP_UPD_TX_VF_0_31 0x96d8
42471 #define A_MPS_STAT_STOP_UPD_TX_VF_32_63 0x96dc
42472 #define A_MPS_STAT_STOP_UPD_TX_VF_64_95 0x96e0
42473 #define A_MPS_STAT_STOP_UPD_TX_VF_96_127 0x96e4
42474 #define A_MPS_STAT_STOP_UPD_RX_VF_0_31 0x96e8
42475 #define A_MPS_STAT_STOP_UPD_RX_VF_32_63 0x96ec
42476 #define A_MPS_STAT_STOP_UPD_RX_VF_64_95 0x96f0
42477 #define A_MPS_STAT_STOP_UPD_RX_VF_96_127 0x96f4
42478 #define A_MPS_STAT_STOP_UPD_RX_VF_128_159 0x96f8
42479 #define A_MPS_STAT_STOP_UPD_RX_VF_160_191 0x96fc
42480 #define A_MPS_STAT_STOP_UPD_RX_VF_192_223 0x9700
42481 #define A_MPS_STAT_STOP_UPD_RX_VF_224_255 0x9704
42482 #define A_MPS_STAT_STOP_UPD_TX_VF_128_159 0x9710
42483 #define A_MPS_STAT_STOP_UPD_TX_VF_160_191 0x9714
42484 #define A_MPS_STAT_STOP_UPD_TX_VF_192_223 0x9718
42485 #define A_MPS_STAT_STOP_UPD_TX_VF_224_255 0x971c
42486 #define A_MPS_TRC_CFG 0x9800
42487 
42488 #define S_TRCFIFOEMPTY    4
42489 #define V_TRCFIFOEMPTY(x) ((x) << S_TRCFIFOEMPTY)
42490 #define F_TRCFIFOEMPTY    V_TRCFIFOEMPTY(1U)
42491 
42492 #define S_TRCIGNOREDROPINPUT    3
42493 #define V_TRCIGNOREDROPINPUT(x) ((x) << S_TRCIGNOREDROPINPUT)
42494 #define F_TRCIGNOREDROPINPUT    V_TRCIGNOREDROPINPUT(1U)
42495 
42496 #define S_TRCKEEPDUPLICATES    2
42497 #define V_TRCKEEPDUPLICATES(x) ((x) << S_TRCKEEPDUPLICATES)
42498 #define F_TRCKEEPDUPLICATES    V_TRCKEEPDUPLICATES(1U)
42499 
42500 #define S_TRCEN    1
42501 #define V_TRCEN(x) ((x) << S_TRCEN)
42502 #define F_TRCEN    V_TRCEN(1U)
42503 
42504 #define S_TRCMULTIFILTER    0
42505 #define V_TRCMULTIFILTER(x) ((x) << S_TRCMULTIFILTER)
42506 #define F_TRCMULTIFILTER    V_TRCMULTIFILTER(1U)
42507 
42508 #define S_TRCMULTIRSSFILTER    5
42509 #define V_TRCMULTIRSSFILTER(x) ((x) << S_TRCMULTIRSSFILTER)
42510 #define F_TRCMULTIRSSFILTER    V_TRCMULTIRSSFILTER(1U)
42511 
42512 #define A_MPS_TRC_RSS_HASH 0x9804
42513 #define A_MPS_TRC_FILTER0_RSS_HASH 0x9804
42514 #define A_T7_MPS_TRC_PERR_INJECT 0x9804
42515 #define A_MPS_TRC_RSS_CONTROL 0x9808
42516 
42517 #define S_RSSCONTROL    16
42518 #define M_RSSCONTROL    0xffU
42519 #define V_RSSCONTROL(x) ((x) << S_RSSCONTROL)
42520 #define G_RSSCONTROL(x) (((x) >> S_RSSCONTROL) & M_RSSCONTROL)
42521 
42522 #define S_QUEUENUMBER    0
42523 #define M_QUEUENUMBER    0xffffU
42524 #define V_QUEUENUMBER(x) ((x) << S_QUEUENUMBER)
42525 #define G_QUEUENUMBER(x) (((x) >> S_QUEUENUMBER) & M_QUEUENUMBER)
42526 
42527 #define A_MPS_TRC_FILTER0_RSS_CONTROL 0x9808
42528 #define A_MPS_TRC_FILTER_MATCH_CTL_A 0x9810
42529 
42530 #define S_TFINVERTMATCH    24
42531 #define V_TFINVERTMATCH(x) ((x) << S_TFINVERTMATCH)
42532 #define F_TFINVERTMATCH    V_TFINVERTMATCH(1U)
42533 
42534 #define S_TFPKTTOOLARGE    23
42535 #define V_TFPKTTOOLARGE(x) ((x) << S_TFPKTTOOLARGE)
42536 #define F_TFPKTTOOLARGE    V_TFPKTTOOLARGE(1U)
42537 
42538 #define S_TFEN    22
42539 #define V_TFEN(x) ((x) << S_TFEN)
42540 #define F_TFEN    V_TFEN(1U)
42541 
42542 #define S_TFPORT    18
42543 #define M_TFPORT    0xfU
42544 #define V_TFPORT(x) ((x) << S_TFPORT)
42545 #define G_TFPORT(x) (((x) >> S_TFPORT) & M_TFPORT)
42546 
42547 #define S_TFDROP    17
42548 #define V_TFDROP(x) ((x) << S_TFDROP)
42549 #define F_TFDROP    V_TFDROP(1U)
42550 
42551 #define S_TFSOPEOPERR    16
42552 #define V_TFSOPEOPERR(x) ((x) << S_TFSOPEOPERR)
42553 #define F_TFSOPEOPERR    V_TFSOPEOPERR(1U)
42554 
42555 #define S_TFLENGTH    8
42556 #define M_TFLENGTH    0x1fU
42557 #define V_TFLENGTH(x) ((x) << S_TFLENGTH)
42558 #define G_TFLENGTH(x) (((x) >> S_TFLENGTH) & M_TFLENGTH)
42559 
42560 #define S_TFOFFSET    0
42561 #define M_TFOFFSET    0x1fU
42562 #define V_TFOFFSET(x) ((x) << S_TFOFFSET)
42563 #define G_TFOFFSET(x) (((x) >> S_TFOFFSET) & M_TFOFFSET)
42564 
42565 #define S_TFINSERTACTLEN    27
42566 #define V_TFINSERTACTLEN(x) ((x) << S_TFINSERTACTLEN)
42567 #define F_TFINSERTACTLEN    V_TFINSERTACTLEN(1U)
42568 
42569 #define S_TFINSERTTIMER    26
42570 #define V_TFINSERTTIMER(x) ((x) << S_TFINSERTTIMER)
42571 #define F_TFINSERTTIMER    V_TFINSERTTIMER(1U)
42572 
42573 #define S_T5_TFINVERTMATCH    25
42574 #define V_T5_TFINVERTMATCH(x) ((x) << S_T5_TFINVERTMATCH)
42575 #define F_T5_TFINVERTMATCH    V_T5_TFINVERTMATCH(1U)
42576 
42577 #define S_T5_TFPKTTOOLARGE    24
42578 #define V_T5_TFPKTTOOLARGE(x) ((x) << S_T5_TFPKTTOOLARGE)
42579 #define F_T5_TFPKTTOOLARGE    V_T5_TFPKTTOOLARGE(1U)
42580 
42581 #define S_T5_TFEN    23
42582 #define V_T5_TFEN(x) ((x) << S_T5_TFEN)
42583 #define F_T5_TFEN    V_T5_TFEN(1U)
42584 
42585 #define S_T5_TFPORT    18
42586 #define M_T5_TFPORT    0x1fU
42587 #define V_T5_TFPORT(x) ((x) << S_T5_TFPORT)
42588 #define G_T5_TFPORT(x) (((x) >> S_T5_TFPORT) & M_T5_TFPORT)
42589 
42590 #define A_MPS_TRC_FILTER_MATCH_CTL_B 0x9820
42591 
42592 #define S_TFMINPKTSIZE    16
42593 #define M_TFMINPKTSIZE    0x1ffU
42594 #define V_TFMINPKTSIZE(x) ((x) << S_TFMINPKTSIZE)
42595 #define G_TFMINPKTSIZE(x) (((x) >> S_TFMINPKTSIZE) & M_TFMINPKTSIZE)
42596 
42597 #define S_TFCAPTUREMAX    0
42598 #define M_TFCAPTUREMAX    0x3fffU
42599 #define V_TFCAPTUREMAX(x) ((x) << S_TFCAPTUREMAX)
42600 #define G_TFCAPTUREMAX(x) (((x) >> S_TFCAPTUREMAX) & M_TFCAPTUREMAX)
42601 
42602 #define A_MPS_TRC_FILTER_RUNT_CTL 0x9830
42603 
42604 #define S_TFRUNTSIZE    0
42605 #define M_TFRUNTSIZE    0x3fU
42606 #define V_TFRUNTSIZE(x) ((x) << S_TFRUNTSIZE)
42607 #define G_TFRUNTSIZE(x) (((x) >> S_TFRUNTSIZE) & M_TFRUNTSIZE)
42608 
42609 #define A_MPS_TRC_FILTER_DROP 0x9840
42610 
42611 #define S_TFDROPINPCOUNT    16
42612 #define M_TFDROPINPCOUNT    0xffffU
42613 #define V_TFDROPINPCOUNT(x) ((x) << S_TFDROPINPCOUNT)
42614 #define G_TFDROPINPCOUNT(x) (((x) >> S_TFDROPINPCOUNT) & M_TFDROPINPCOUNT)
42615 
42616 #define S_TFDROPBUFFERCOUNT    0
42617 #define M_TFDROPBUFFERCOUNT    0xffffU
42618 #define V_TFDROPBUFFERCOUNT(x) ((x) << S_TFDROPBUFFERCOUNT)
42619 #define G_TFDROPBUFFERCOUNT(x) (((x) >> S_TFDROPBUFFERCOUNT) & M_TFDROPBUFFERCOUNT)
42620 
42621 #define A_MPS_TRC_PERR_INJECT 0x9850
42622 
42623 #define S_TRCMEMSEL    1
42624 #define M_TRCMEMSEL    0xfU
42625 #define V_TRCMEMSEL(x) ((x) << S_TRCMEMSEL)
42626 #define G_TRCMEMSEL(x) (((x) >> S_TRCMEMSEL) & M_TRCMEMSEL)
42627 
42628 #define A_MPS_TRC_PERR_ENABLE 0x9854
42629 
42630 #define S_MISCPERR    8
42631 #define V_MISCPERR(x) ((x) << S_MISCPERR)
42632 #define F_MISCPERR    V_MISCPERR(1U)
42633 
42634 #define S_PKTFIFO    4
42635 #define M_PKTFIFO    0xfU
42636 #define V_PKTFIFO(x) ((x) << S_PKTFIFO)
42637 #define G_PKTFIFO(x) (((x) >> S_PKTFIFO) & M_PKTFIFO)
42638 
42639 #define S_FILTMEM    0
42640 #define M_FILTMEM    0xfU
42641 #define V_FILTMEM(x) ((x) << S_FILTMEM)
42642 #define G_FILTMEM(x) (((x) >> S_FILTMEM) & M_FILTMEM)
42643 
42644 #define S_T7_MISCPERR    16
42645 #define V_T7_MISCPERR(x) ((x) << S_T7_MISCPERR)
42646 #define F_T7_MISCPERR    V_T7_MISCPERR(1U)
42647 
42648 #define S_T7_PKTFIFO    8
42649 #define M_T7_PKTFIFO    0xffU
42650 #define V_T7_PKTFIFO(x) ((x) << S_T7_PKTFIFO)
42651 #define G_T7_PKTFIFO(x) (((x) >> S_T7_PKTFIFO) & M_T7_PKTFIFO)
42652 
42653 #define S_T7_FILTMEM    0
42654 #define M_T7_FILTMEM    0xffU
42655 #define V_T7_FILTMEM(x) ((x) << S_T7_FILTMEM)
42656 #define G_T7_FILTMEM(x) (((x) >> S_T7_FILTMEM) & M_T7_FILTMEM)
42657 
42658 #define A_MPS_TRC_INT_ENABLE 0x9858
42659 
42660 #define S_TRCPLERRENB    9
42661 #define V_TRCPLERRENB(x) ((x) << S_TRCPLERRENB)
42662 #define F_TRCPLERRENB    V_TRCPLERRENB(1U)
42663 
42664 #define A_MPS_TRC_INT_CAUSE 0x985c
42665 #define A_MPS_TRC_TIMESTAMP_L 0x9860
42666 #define A_MPS_TRC_TIMESTAMP_H 0x9864
42667 #define A_MPS_TRC_FILTER0_MATCH 0x9c00
42668 #define A_MPS_TRC_FILTER0_DONT_CARE 0x9c80
42669 #define A_MPS_TRC_FILTER1_MATCH 0x9d00
42670 #define A_MPS_TRC_FILTER1_DONT_CARE 0x9d80
42671 #define A_MPS_TRC_FILTER2_MATCH 0x9e00
42672 #define A_MPS_TRC_FILTER2_DONT_CARE 0x9e80
42673 #define A_MPS_TRC_FILTER3_MATCH 0x9f00
42674 #define A_MPS_TRC_FILTER3_DONT_CARE 0x9f80
42675 #define A_MPS_TRC_FILTER1_RSS_HASH 0x9ff0
42676 #define A_MPS_TRC_FILTER1_RSS_CONTROL 0x9ff4
42677 #define A_MPS_TRC_FILTER2_RSS_HASH 0x9ff8
42678 #define A_MPS_TRC_FILTER2_RSS_CONTROL 0x9ffc
42679 #define A_MPS_TRC_FILTER3_RSS_HASH 0xa000
42680 #define A_MPS_TRC_FILTER4_MATCH 0xa000
42681 #define A_MPS_TRC_FILTER3_RSS_CONTROL 0xa004
42682 #define A_MPS_T5_TRC_RSS_HASH 0xa008
42683 #define A_MPS_T5_TRC_RSS_CONTROL 0xa00c
42684 #define A_MPS_TRC_VF_OFF_FILTER_0 0xa010
42685 
42686 #define S_TRCMPS2TP_MACONLY    20
42687 #define V_TRCMPS2TP_MACONLY(x) ((x) << S_TRCMPS2TP_MACONLY)
42688 #define F_TRCMPS2TP_MACONLY    V_TRCMPS2TP_MACONLY(1U)
42689 
42690 #define S_TRCALLMPS2TP    19
42691 #define V_TRCALLMPS2TP(x) ((x) << S_TRCALLMPS2TP)
42692 #define F_TRCALLMPS2TP    V_TRCALLMPS2TP(1U)
42693 
42694 #define S_TRCALLTP2MPS    18
42695 #define V_TRCALLTP2MPS(x) ((x) << S_TRCALLTP2MPS)
42696 #define F_TRCALLTP2MPS    V_TRCALLTP2MPS(1U)
42697 
42698 #define S_TRCALLVF    17
42699 #define V_TRCALLVF(x) ((x) << S_TRCALLVF)
42700 #define F_TRCALLVF    V_TRCALLVF(1U)
42701 
42702 #define S_TRC_OFLD_EN    16
42703 #define V_TRC_OFLD_EN(x) ((x) << S_TRC_OFLD_EN)
42704 #define F_TRC_OFLD_EN    V_TRC_OFLD_EN(1U)
42705 
42706 #define S_VFFILTEN    15
42707 #define V_VFFILTEN(x) ((x) << S_VFFILTEN)
42708 #define F_VFFILTEN    V_VFFILTEN(1U)
42709 
42710 #define S_VFFILTMASK    8
42711 #define M_VFFILTMASK    0x7fU
42712 #define V_VFFILTMASK(x) ((x) << S_VFFILTMASK)
42713 #define G_VFFILTMASK(x) (((x) >> S_VFFILTMASK) & M_VFFILTMASK)
42714 
42715 #define S_VFFILTVALID    7
42716 #define V_VFFILTVALID(x) ((x) << S_VFFILTVALID)
42717 #define F_VFFILTVALID    V_VFFILTVALID(1U)
42718 
42719 #define S_VFFILTDATA    0
42720 #define M_VFFILTDATA    0x7fU
42721 #define V_VFFILTDATA(x) ((x) << S_VFFILTDATA)
42722 #define G_VFFILTDATA(x) (((x) >> S_VFFILTDATA) & M_VFFILTDATA)
42723 
42724 #define S_T6_TRCMPS2TP_MACONLY    22
42725 #define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY)
42726 #define F_T6_TRCMPS2TP_MACONLY    V_T6_TRCMPS2TP_MACONLY(1U)
42727 
42728 #define S_T6_TRCALLMPS2TP    21
42729 #define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP)
42730 #define F_T6_TRCALLMPS2TP    V_T6_TRCALLMPS2TP(1U)
42731 
42732 #define S_T6_TRCALLTP2MPS    20
42733 #define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS)
42734 #define F_T6_TRCALLTP2MPS    V_T6_TRCALLTP2MPS(1U)
42735 
42736 #define S_T6_TRCALLVF    19
42737 #define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF)
42738 #define F_T6_TRCALLVF    V_T6_TRCALLVF(1U)
42739 
42740 #define S_T6_TRC_OFLD_EN    18
42741 #define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN)
42742 #define F_T6_TRC_OFLD_EN    V_T6_TRC_OFLD_EN(1U)
42743 
42744 #define S_T6_VFFILTEN    17
42745 #define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN)
42746 #define F_T6_VFFILTEN    V_T6_VFFILTEN(1U)
42747 
42748 #define S_T6_VFFILTMASK    9
42749 #define M_T6_VFFILTMASK    0xffU
42750 #define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK)
42751 #define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK)
42752 
42753 #define S_T6_VFFILTVALID    8
42754 #define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID)
42755 #define F_T6_VFFILTVALID    V_T6_VFFILTVALID(1U)
42756 
42757 #define S_T6_VFFILTDATA    0
42758 #define M_T6_VFFILTDATA    0xffU
42759 #define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA)
42760 #define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
42761 
42762 #define A_MPS_TRC_VF_OFF_FILTER_1 0xa014
42763 #define A_MPS_TRC_VF_OFF_FILTER_2 0xa018
42764 #define A_MPS_TRC_VF_OFF_FILTER_3 0xa01c
42765 #define A_MPS_TRC_CGEN 0xa020
42766 
42767 #define S_MPSTRCCGEN    0
42768 #define M_MPSTRCCGEN    0xfU
42769 #define V_MPSTRCCGEN(x) ((x) << S_MPSTRCCGEN)
42770 #define G_MPSTRCCGEN(x) (((x) >> S_MPSTRCCGEN) & M_MPSTRCCGEN)
42771 
42772 #define A_MPS_TRC_FILTER4_DONT_CARE 0xa080
42773 #define A_MPS_TRC_FILTER5_MATCH 0xa100
42774 #define A_MPS_TRC_FILTER5_DONT_CARE 0xa180
42775 #define A_MPS_TRC_FILTER6_MATCH 0xa200
42776 #define A_MPS_TRC_FILTER6_DONT_CARE 0xa280
42777 #define A_MPS_TRC_FILTER7_MATCH 0xa300
42778 #define A_MPS_TRC_FILTER7_DONT_CARE 0xa380
42779 #define A_T7_MPS_TRC_FILTER0_RSS_HASH 0xa3f0
42780 #define A_T7_MPS_TRC_FILTER0_RSS_CONTROL 0xa3f4
42781 #define A_T7_MPS_TRC_FILTER1_RSS_HASH 0xa3f8
42782 #define A_T7_MPS_TRC_FILTER1_RSS_CONTROL 0xa3fc
42783 #define A_T7_MPS_TRC_FILTER2_RSS_HASH 0xa400
42784 #define A_T7_MPS_TRC_FILTER2_RSS_CONTROL 0xa404
42785 #define A_T7_MPS_TRC_FILTER3_RSS_HASH 0xa408
42786 #define A_T7_MPS_TRC_FILTER3_RSS_CONTROL 0xa40c
42787 #define A_MPS_TRC_FILTER4_RSS_HASH 0xa410
42788 #define A_MPS_TRC_FILTER4_RSS_CONTROL 0xa414
42789 #define A_MPS_TRC_FILTER5_RSS_HASH 0xa418
42790 #define A_MPS_TRC_FILTER5_RSS_CONTROL 0xa41c
42791 #define A_MPS_TRC_FILTER6_RSS_HASH 0xa420
42792 #define A_MPS_TRC_FILTER6_RSS_CONTROL 0xa424
42793 #define A_MPS_TRC_FILTER7_RSS_HASH 0xa428
42794 #define A_MPS_TRC_FILTER7_RSS_CONTROL 0xa42c
42795 #define A_T7_MPS_T5_TRC_RSS_HASH 0xa430
42796 #define A_T7_MPS_T5_TRC_RSS_CONTROL 0xa434
42797 #define A_T7_MPS_TRC_VF_OFF_FILTER_0 0xa438
42798 #define A_T7_MPS_TRC_VF_OFF_FILTER_1 0xa43c
42799 #define A_T7_MPS_TRC_VF_OFF_FILTER_2 0xa440
42800 #define A_T7_MPS_TRC_VF_OFF_FILTER_3 0xa444
42801 #define A_MPS_TRC_VF_OFF_FILTER_4 0xa448
42802 #define A_MPS_TRC_VF_OFF_FILTER_5 0xa44c
42803 #define A_MPS_TRC_VF_OFF_FILTER_6 0xa450
42804 #define A_MPS_TRC_VF_OFF_FILTER_7 0xa454
42805 #define A_T7_MPS_TRC_CGEN 0xa458
42806 
42807 #define S_T7_MPSTRCCGEN    0
42808 #define M_T7_MPSTRCCGEN    0xffU
42809 #define V_T7_MPSTRCCGEN(x) ((x) << S_T7_MPSTRCCGEN)
42810 #define G_T7_MPSTRCCGEN(x) (((x) >> S_T7_MPSTRCCGEN) & M_T7_MPSTRCCGEN)
42811 
42812 #define A_T7_MPS_TRC_FILTER_MATCH_CTL_A 0xa460
42813 #define A_T7_MPS_TRC_FILTER_MATCH_CTL_B 0xa480
42814 #define A_T7_MPS_TRC_FILTER_RUNT_CTL 0xa4a0
42815 #define A_T7_MPS_TRC_FILTER_DROP 0xa4c0
42816 #define A_T7_MPS_TRC_INT_ENABLE 0xa4e0
42817 
42818 #define S_T7_TRCPLERRENB    17
42819 #define V_T7_TRCPLERRENB(x) ((x) << S_T7_TRCPLERRENB)
42820 #define F_T7_TRCPLERRENB    V_T7_TRCPLERRENB(1U)
42821 
42822 #define A_T7_MPS_TRC_INT_CAUSE 0xa4e4
42823 #define A_T7_MPS_TRC_TIMESTAMP_L 0xa4e8
42824 #define A_T7_MPS_TRC_TIMESTAMP_H 0xa4ec
42825 #define A_MPS_TRC_PERR_ENABLE2 0xa4f0
42826 
42827 #define S_TRC_TF_ECC    24
42828 #define M_TRC_TF_ECC    0xffU
42829 #define V_TRC_TF_ECC(x) ((x) << S_TRC_TF_ECC)
42830 #define G_TRC_TF_ECC(x) (((x) >> S_TRC_TF_ECC) & M_TRC_TF_ECC)
42831 
42832 #define S_MPS2MAC_CONV_TRC_CERR    22
42833 #define M_MPS2MAC_CONV_TRC_CERR    0x3U
42834 #define V_MPS2MAC_CONV_TRC_CERR(x) ((x) << S_MPS2MAC_CONV_TRC_CERR)
42835 #define G_MPS2MAC_CONV_TRC_CERR(x) (((x) >> S_MPS2MAC_CONV_TRC_CERR) & M_MPS2MAC_CONV_TRC_CERR)
42836 
42837 #define S_MPS2MAC_CONV_TRC    18
42838 #define M_MPS2MAC_CONV_TRC    0xfU
42839 #define V_MPS2MAC_CONV_TRC(x) ((x) << S_MPS2MAC_CONV_TRC)
42840 #define G_MPS2MAC_CONV_TRC(x) (((x) >> S_MPS2MAC_CONV_TRC) & M_MPS2MAC_CONV_TRC)
42841 
42842 #define S_TF0_PERR_1    17
42843 #define V_TF0_PERR_1(x) ((x) << S_TF0_PERR_1)
42844 #define F_TF0_PERR_1    V_TF0_PERR_1(1U)
42845 
42846 #define S_TF1_PERR_1    16
42847 #define V_TF1_PERR_1(x) ((x) << S_TF1_PERR_1)
42848 #define F_TF1_PERR_1    V_TF1_PERR_1(1U)
42849 
42850 #define S_TF2_PERR_1    15
42851 #define V_TF2_PERR_1(x) ((x) << S_TF2_PERR_1)
42852 #define F_TF2_PERR_1    V_TF2_PERR_1(1U)
42853 
42854 #define S_TF3_PERR_1    14
42855 #define V_TF3_PERR_1(x) ((x) << S_TF3_PERR_1)
42856 #define F_TF3_PERR_1    V_TF3_PERR_1(1U)
42857 
42858 #define S_TF4_PERR_1    13
42859 #define V_TF4_PERR_1(x) ((x) << S_TF4_PERR_1)
42860 #define F_TF4_PERR_1    V_TF4_PERR_1(1U)
42861 
42862 #define S_TF0_PERR_0    12
42863 #define V_TF0_PERR_0(x) ((x) << S_TF0_PERR_0)
42864 #define F_TF0_PERR_0    V_TF0_PERR_0(1U)
42865 
42866 #define S_TF1_PERR_0    11
42867 #define V_TF1_PERR_0(x) ((x) << S_TF1_PERR_0)
42868 #define F_TF1_PERR_0    V_TF1_PERR_0(1U)
42869 
42870 #define S_TF2_PERR_0    10
42871 #define V_TF2_PERR_0(x) ((x) << S_TF2_PERR_0)
42872 #define F_TF2_PERR_0    V_TF2_PERR_0(1U)
42873 
42874 #define S_TF3_PERR_0    9
42875 #define V_TF3_PERR_0(x) ((x) << S_TF3_PERR_0)
42876 #define F_TF3_PERR_0    V_TF3_PERR_0(1U)
42877 
42878 #define S_TF4_PERR_0    8
42879 #define V_TF4_PERR_0(x) ((x) << S_TF4_PERR_0)
42880 #define F_TF4_PERR_0    V_TF4_PERR_0(1U)
42881 
42882 #define S_PERR_TF_IN_CTL    0
42883 #define M_PERR_TF_IN_CTL    0xffU
42884 #define V_PERR_TF_IN_CTL(x) ((x) << S_PERR_TF_IN_CTL)
42885 #define G_PERR_TF_IN_CTL(x) (((x) >> S_PERR_TF_IN_CTL) & M_PERR_TF_IN_CTL)
42886 
42887 #define A_MPS_TRC_INT_ENABLE2 0xa4f4
42888 #define A_MPS_TRC_INT_CAUSE2 0xa4f8
42889 
42890 #define S_T7_TRC_TF_ECC    22
42891 #define M_T7_TRC_TF_ECC    0xffU
42892 #define V_T7_TRC_TF_ECC(x) ((x) << S_T7_TRC_TF_ECC)
42893 #define G_T7_TRC_TF_ECC(x) (((x) >> S_T7_TRC_TF_ECC) & M_T7_TRC_TF_ECC)
42894 
42895 #define A_MPS_CLS_CTL 0xd000
42896 
42897 #define S_MEMWRITEFAULT    4
42898 #define V_MEMWRITEFAULT(x) ((x) << S_MEMWRITEFAULT)
42899 #define F_MEMWRITEFAULT    V_MEMWRITEFAULT(1U)
42900 
42901 #define S_MEMWRITEWAITING    3
42902 #define V_MEMWRITEWAITING(x) ((x) << S_MEMWRITEWAITING)
42903 #define F_MEMWRITEWAITING    V_MEMWRITEWAITING(1U)
42904 
42905 #define S_CIMNOPROMISCUOUS    2
42906 #define V_CIMNOPROMISCUOUS(x) ((x) << S_CIMNOPROMISCUOUS)
42907 #define F_CIMNOPROMISCUOUS    V_CIMNOPROMISCUOUS(1U)
42908 
42909 #define S_HYPERVISORONLY    1
42910 #define V_HYPERVISORONLY(x) ((x) << S_HYPERVISORONLY)
42911 #define F_HYPERVISORONLY    V_HYPERVISORONLY(1U)
42912 
42913 #define S_VLANCLSEN    0
42914 #define V_VLANCLSEN(x) ((x) << S_VLANCLSEN)
42915 #define F_VLANCLSEN    V_VLANCLSEN(1U)
42916 
42917 #define S_VLANCLSEN_IN    7
42918 #define V_VLANCLSEN_IN(x) ((x) << S_VLANCLSEN_IN)
42919 #define F_VLANCLSEN_IN    V_VLANCLSEN_IN(1U)
42920 
42921 #define S_DISTCAMPARCHK    6
42922 #define V_DISTCAMPARCHK(x) ((x) << S_DISTCAMPARCHK)
42923 #define F_DISTCAMPARCHK    V_DISTCAMPARCHK(1U)
42924 
42925 #define S_VLANLKPEN    5
42926 #define V_VLANLKPEN(x) ((x) << S_VLANLKPEN)
42927 #define F_VLANLKPEN    V_VLANLKPEN(1U)
42928 
42929 #define A_MPS_CLS_ARB_WEIGHT 0xd004
42930 
42931 #define S_PLWEIGHT    16
42932 #define M_PLWEIGHT    0x1fU
42933 #define V_PLWEIGHT(x) ((x) << S_PLWEIGHT)
42934 #define G_PLWEIGHT(x) (((x) >> S_PLWEIGHT) & M_PLWEIGHT)
42935 
42936 #define S_CIMWEIGHT    8
42937 #define M_CIMWEIGHT    0x1fU
42938 #define V_CIMWEIGHT(x) ((x) << S_CIMWEIGHT)
42939 #define G_CIMWEIGHT(x) (((x) >> S_CIMWEIGHT) & M_CIMWEIGHT)
42940 
42941 #define S_LPBKWEIGHT    0
42942 #define M_LPBKWEIGHT    0x1fU
42943 #define V_LPBKWEIGHT(x) ((x) << S_LPBKWEIGHT)
42944 #define G_LPBKWEIGHT(x) (((x) >> S_LPBKWEIGHT) & M_LPBKWEIGHT)
42945 
42946 #define A_MPS_CLS_NCSI_ETH_TYPE 0xd008
42947 #define A_MPS_CLS_NCSI_ETH_TYPE_EN 0xd00c
42948 #define A_MPS_CLS_BMC_MAC_ADDR_L 0xd010
42949 #define A_MPS_CLS_BMC_MAC_ADDR_H 0xd014
42950 #define A_MPS_CLS_BMC_VLAN 0xd018
42951 #define A_MPS_CLS_PERR_INJECT 0xd01c
42952 
42953 #define S_CLS_MEMSEL    1
42954 #define M_CLS_MEMSEL    0x3U
42955 #define V_CLS_MEMSEL(x) ((x) << S_CLS_MEMSEL)
42956 #define G_CLS_MEMSEL(x) (((x) >> S_CLS_MEMSEL) & M_CLS_MEMSEL)
42957 
42958 #define A_MPS_CLS_PERR_ENABLE 0xd020
42959 
42960 #define S_HASHSRAM    2
42961 #define V_HASHSRAM(x) ((x) << S_HASHSRAM)
42962 #define F_HASHSRAM    V_HASHSRAM(1U)
42963 
42964 #define S_MATCHTCAM    1
42965 #define V_MATCHTCAM(x) ((x) << S_MATCHTCAM)
42966 #define F_MATCHTCAM    V_MATCHTCAM(1U)
42967 
42968 #define S_MATCHSRAM    0
42969 #define V_MATCHSRAM(x) ((x) << S_MATCHSRAM)
42970 #define F_MATCHSRAM    V_MATCHSRAM(1U)
42971 
42972 #define S_CIM2MPS_INTF_PAR    4
42973 #define V_CIM2MPS_INTF_PAR(x) ((x) << S_CIM2MPS_INTF_PAR)
42974 #define F_CIM2MPS_INTF_PAR    V_CIM2MPS_INTF_PAR(1U)
42975 
42976 #define S_TCAM_CRC_SRAM    3
42977 #define V_TCAM_CRC_SRAM(x) ((x) << S_TCAM_CRC_SRAM)
42978 #define F_TCAM_CRC_SRAM    V_TCAM_CRC_SRAM(1U)
42979 
42980 #define A_MPS_CLS_INT_ENABLE 0xd024
42981 
42982 #define S_PLERRENB    3
42983 #define V_PLERRENB(x) ((x) << S_PLERRENB)
42984 #define F_PLERRENB    V_PLERRENB(1U)
42985 
42986 #define S_T7_PLERRENB    5
42987 #define V_T7_PLERRENB(x) ((x) << S_T7_PLERRENB)
42988 #define F_T7_PLERRENB    V_T7_PLERRENB(1U)
42989 
42990 #define A_MPS_CLS_INT_CAUSE 0xd028
42991 #define A_MPS_CLS_PL_TEST_DATA_L 0xd02c
42992 #define A_MPS_CLS_PL_TEST_DATA_H 0xd030
42993 #define A_MPS_CLS_PL_TEST_RES_DATA 0xd034
42994 
42995 #define S_CLS_PRIORITY    24
42996 #define M_CLS_PRIORITY    0x7U
42997 #define V_CLS_PRIORITY(x) ((x) << S_CLS_PRIORITY)
42998 #define G_CLS_PRIORITY(x) (((x) >> S_CLS_PRIORITY) & M_CLS_PRIORITY)
42999 
43000 #define S_CLS_REPLICATE    23
43001 #define V_CLS_REPLICATE(x) ((x) << S_CLS_REPLICATE)
43002 #define F_CLS_REPLICATE    V_CLS_REPLICATE(1U)
43003 
43004 #define S_CLS_INDEX    14
43005 #define M_CLS_INDEX    0x1ffU
43006 #define V_CLS_INDEX(x) ((x) << S_CLS_INDEX)
43007 #define G_CLS_INDEX(x) (((x) >> S_CLS_INDEX) & M_CLS_INDEX)
43008 
43009 #define S_CLS_VF    7
43010 #define M_CLS_VF    0x7fU
43011 #define V_CLS_VF(x) ((x) << S_CLS_VF)
43012 #define G_CLS_VF(x) (((x) >> S_CLS_VF) & M_CLS_VF)
43013 
43014 #define S_CLS_VF_VLD    6
43015 #define V_CLS_VF_VLD(x) ((x) << S_CLS_VF_VLD)
43016 #define F_CLS_VF_VLD    V_CLS_VF_VLD(1U)
43017 
43018 #define S_CLS_PF    3
43019 #define M_CLS_PF    0x7U
43020 #define V_CLS_PF(x) ((x) << S_CLS_PF)
43021 #define G_CLS_PF(x) (((x) >> S_CLS_PF) & M_CLS_PF)
43022 
43023 #define S_CLS_MATCH    0
43024 #define M_CLS_MATCH    0x7U
43025 #define V_CLS_MATCH(x) ((x) << S_CLS_MATCH)
43026 #define G_CLS_MATCH(x) (((x) >> S_CLS_MATCH) & M_CLS_MATCH)
43027 
43028 #define S_CLS_SPARE    28
43029 #define M_CLS_SPARE    0xfU
43030 #define V_CLS_SPARE(x) ((x) << S_CLS_SPARE)
43031 #define G_CLS_SPARE(x) (((x) >> S_CLS_SPARE) & M_CLS_SPARE)
43032 
43033 #define S_T6_CLS_PRIORITY    25
43034 #define M_T6_CLS_PRIORITY    0x7U
43035 #define V_T6_CLS_PRIORITY(x) ((x) << S_T6_CLS_PRIORITY)
43036 #define G_T6_CLS_PRIORITY(x) (((x) >> S_T6_CLS_PRIORITY) & M_T6_CLS_PRIORITY)
43037 
43038 #define S_T6_CLS_REPLICATE    24
43039 #define V_T6_CLS_REPLICATE(x) ((x) << S_T6_CLS_REPLICATE)
43040 #define F_T6_CLS_REPLICATE    V_T6_CLS_REPLICATE(1U)
43041 
43042 #define S_T6_CLS_INDEX    15
43043 #define M_T6_CLS_INDEX    0x1ffU
43044 #define V_T6_CLS_INDEX(x) ((x) << S_T6_CLS_INDEX)
43045 #define G_T6_CLS_INDEX(x) (((x) >> S_T6_CLS_INDEX) & M_T6_CLS_INDEX)
43046 
43047 #define S_T6_CLS_VF    7
43048 #define M_T6_CLS_VF    0xffU
43049 #define V_T6_CLS_VF(x) ((x) << S_T6_CLS_VF)
43050 #define G_T6_CLS_VF(x) (((x) >> S_T6_CLS_VF) & M_T6_CLS_VF)
43051 
43052 #define S_T7_CLS_SPARE    30
43053 #define M_T7_CLS_SPARE    0x3U
43054 #define V_T7_CLS_SPARE(x) ((x) << S_T7_CLS_SPARE)
43055 #define G_T7_CLS_SPARE(x) (((x) >> S_T7_CLS_SPARE) & M_T7_CLS_SPARE)
43056 
43057 #define S_T7_1_CLS_PRIORITY    27
43058 #define M_T7_1_CLS_PRIORITY    0x7U
43059 #define V_T7_1_CLS_PRIORITY(x) ((x) << S_T7_1_CLS_PRIORITY)
43060 #define G_T7_1_CLS_PRIORITY(x) (((x) >> S_T7_1_CLS_PRIORITY) & M_T7_1_CLS_PRIORITY)
43061 
43062 #define S_T7_1_CLS_REPLICATE    26
43063 #define V_T7_1_CLS_REPLICATE(x) ((x) << S_T7_1_CLS_REPLICATE)
43064 #define F_T7_1_CLS_REPLICATE    V_T7_1_CLS_REPLICATE(1U)
43065 
43066 #define S_T7_1_CLS_INDEX    15
43067 #define M_T7_1_CLS_INDEX    0x7ffU
43068 #define V_T7_1_CLS_INDEX(x) ((x) << S_T7_1_CLS_INDEX)
43069 #define G_T7_1_CLS_INDEX(x) (((x) >> S_T7_1_CLS_INDEX) & M_T7_1_CLS_INDEX)
43070 
43071 #define A_MPS_CLS_PL_TEST_CTL 0xd038
43072 
43073 #define S_PLTESTCTL    0
43074 #define V_PLTESTCTL(x) ((x) << S_PLTESTCTL)
43075 #define F_PLTESTCTL    V_PLTESTCTL(1U)
43076 
43077 #define A_MPS_CLS_PORT_BMC_CTL 0xd03c
43078 
43079 #define S_PRTBMCCTL    0
43080 #define V_PRTBMCCTL(x) ((x) << S_PRTBMCCTL)
43081 #define F_PRTBMCCTL    V_PRTBMCCTL(1U)
43082 
43083 #define A_MPS_CLS_MATCH_CNT_TCAM 0xd100
43084 #define A_MPS_CLS0_MATCH_CNT_TCAM 0xd100
43085 #define A_MPS_CLS_MATCH_CNT_HASH 0xd104
43086 #define A_MPS_CLS0_MATCH_CNT_HASH 0xd104
43087 #define A_MPS_CLS_MATCH_CNT_BCAST 0xd108
43088 #define A_MPS_CLS0_MATCH_CNT_BCAST 0xd108
43089 #define A_MPS_CLS_MATCH_CNT_BMC 0xd10c
43090 #define A_MPS_CLS0_MATCH_CNT_BMC 0xd10c
43091 #define A_MPS_CLS_MATCH_CNT_PROM 0xd110
43092 #define A_MPS_CLS0_MATCH_CNT_PROM 0xd110
43093 #define A_MPS_CLS_MATCH_CNT_HPROM 0xd114
43094 #define A_MPS_CLS0_MATCH_CNT_HPROM 0xd114
43095 #define A_MPS_CLS_MISS_CNT 0xd118
43096 #define A_MPS_CLS0_MISS_CNT 0xd118
43097 #define A_MPS_CLS1_MATCH_CNT_TCAM 0xd11c
43098 #define A_MPS_CLS1_MATCH_CNT_HASH 0xd120
43099 #define A_MPS_CLS1_MATCH_CNT_BCAST 0xd124
43100 #define A_MPS_CLS1_MATCH_CNT_BMC 0xd128
43101 #define A_MPS_CLS1_MATCH_CNT_PROM 0xd12c
43102 #define A_MPS_CLS1_MATCH_CNT_HPROM 0xd130
43103 #define A_MPS_CLS1_MISS_CNT 0xd134
43104 #define A_MPS_CLS_REQUEST_TRACE_MAC_DA_L 0xd200
43105 #define A_MPS_CLS_REQUEST_TRACE_MAC_DA_H 0xd204
43106 
43107 #define S_CLSTRCMACDAHI    0
43108 #define M_CLSTRCMACDAHI    0xffffU
43109 #define V_CLSTRCMACDAHI(x) ((x) << S_CLSTRCMACDAHI)
43110 #define G_CLSTRCMACDAHI(x) (((x) >> S_CLSTRCMACDAHI) & M_CLSTRCMACDAHI)
43111 
43112 #define A_MPS_CLS_REQUEST_TRACE_MAC_SA_L 0xd208
43113 #define A_MPS_CLS_REQUEST_TRACE_MAC_SA_H 0xd20c
43114 
43115 #define S_CLSTRCMACSAHI    0
43116 #define M_CLSTRCMACSAHI    0xffffU
43117 #define V_CLSTRCMACSAHI(x) ((x) << S_CLSTRCMACSAHI)
43118 #define G_CLSTRCMACSAHI(x) (((x) >> S_CLSTRCMACSAHI) & M_CLSTRCMACSAHI)
43119 
43120 #define A_MPS_CLS_REQUEST_TRACE_PORT_VLAN 0xd210
43121 
43122 #define S_CLSTRCVLANVLD    31
43123 #define V_CLSTRCVLANVLD(x) ((x) << S_CLSTRCVLANVLD)
43124 #define F_CLSTRCVLANVLD    V_CLSTRCVLANVLD(1U)
43125 
43126 #define S_CLSTRCVLANID    16
43127 #define M_CLSTRCVLANID    0xfffU
43128 #define V_CLSTRCVLANID(x) ((x) << S_CLSTRCVLANID)
43129 #define G_CLSTRCVLANID(x) (((x) >> S_CLSTRCVLANID) & M_CLSTRCVLANID)
43130 
43131 #define S_CLSTRCREQPORT    0
43132 #define M_CLSTRCREQPORT    0xfU
43133 #define V_CLSTRCREQPORT(x) ((x) << S_CLSTRCREQPORT)
43134 #define G_CLSTRCREQPORT(x) (((x) >> S_CLSTRCREQPORT) & M_CLSTRCREQPORT)
43135 
43136 #define A_MPS_CLS_REQUEST_TRACE_ENCAP 0xd214
43137 
43138 #define S_CLSTRCLKPTYPE    31
43139 #define V_CLSTRCLKPTYPE(x) ((x) << S_CLSTRCLKPTYPE)
43140 #define F_CLSTRCLKPTYPE    V_CLSTRCLKPTYPE(1U)
43141 
43142 #define S_CLSTRCDIPHIT    30
43143 #define V_CLSTRCDIPHIT(x) ((x) << S_CLSTRCDIPHIT)
43144 #define F_CLSTRCDIPHIT    V_CLSTRCDIPHIT(1U)
43145 
43146 #define S_CLSTRCVNI    0
43147 #define M_CLSTRCVNI    0xffffffU
43148 #define V_CLSTRCVNI(x) ((x) << S_CLSTRCVNI)
43149 #define G_CLSTRCVNI(x) (((x) >> S_CLSTRCVNI) & M_CLSTRCVNI)
43150 
43151 #define A_MPS_CLS_RESULT_TRACE 0xd300
43152 
43153 #define S_CLSTRCPORTNUM    31
43154 #define V_CLSTRCPORTNUM(x) ((x) << S_CLSTRCPORTNUM)
43155 #define F_CLSTRCPORTNUM    V_CLSTRCPORTNUM(1U)
43156 
43157 #define S_CLSTRCPRIORITY    28
43158 #define M_CLSTRCPRIORITY    0x7U
43159 #define V_CLSTRCPRIORITY(x) ((x) << S_CLSTRCPRIORITY)
43160 #define G_CLSTRCPRIORITY(x) (((x) >> S_CLSTRCPRIORITY) & M_CLSTRCPRIORITY)
43161 
43162 #define S_CLSTRCMULTILISTEN    27
43163 #define V_CLSTRCMULTILISTEN(x) ((x) << S_CLSTRCMULTILISTEN)
43164 #define F_CLSTRCMULTILISTEN    V_CLSTRCMULTILISTEN(1U)
43165 
43166 #define S_CLSTRCREPLICATE    26
43167 #define V_CLSTRCREPLICATE(x) ((x) << S_CLSTRCREPLICATE)
43168 #define F_CLSTRCREPLICATE    V_CLSTRCREPLICATE(1U)
43169 
43170 #define S_CLSTRCPORTMAP    24
43171 #define M_CLSTRCPORTMAP    0x3U
43172 #define V_CLSTRCPORTMAP(x) ((x) << S_CLSTRCPORTMAP)
43173 #define G_CLSTRCPORTMAP(x) (((x) >> S_CLSTRCPORTMAP) & M_CLSTRCPORTMAP)
43174 
43175 #define S_CLSTRCMATCH    21
43176 #define M_CLSTRCMATCH    0x7U
43177 #define V_CLSTRCMATCH(x) ((x) << S_CLSTRCMATCH)
43178 #define G_CLSTRCMATCH(x) (((x) >> S_CLSTRCMATCH) & M_CLSTRCMATCH)
43179 
43180 #define S_CLSTRCINDEX    12
43181 #define M_CLSTRCINDEX    0x1ffU
43182 #define V_CLSTRCINDEX(x) ((x) << S_CLSTRCINDEX)
43183 #define G_CLSTRCINDEX(x) (((x) >> S_CLSTRCINDEX) & M_CLSTRCINDEX)
43184 
43185 #define S_CLSTRCVF_VLD    11
43186 #define V_CLSTRCVF_VLD(x) ((x) << S_CLSTRCVF_VLD)
43187 #define F_CLSTRCVF_VLD    V_CLSTRCVF_VLD(1U)
43188 
43189 #define S_CLSTRCPF    3
43190 #define M_CLSTRCPF    0xffU
43191 #define V_CLSTRCPF(x) ((x) << S_CLSTRCPF)
43192 #define G_CLSTRCPF(x) (((x) >> S_CLSTRCPF) & M_CLSTRCPF)
43193 
43194 #define S_CLSTRCVF    0
43195 #define M_CLSTRCVF    0x7U
43196 #define V_CLSTRCVF(x) ((x) << S_CLSTRCVF)
43197 #define G_CLSTRCVF(x) (((x) >> S_CLSTRCVF) & M_CLSTRCVF)
43198 
43199 #define S_T7_CLSTRCMATCH    23
43200 #define V_T7_CLSTRCMATCH(x) ((x) << S_T7_CLSTRCMATCH)
43201 #define F_T7_CLSTRCMATCH    V_T7_CLSTRCMATCH(1U)
43202 
43203 #define S_T7_CLSTRCINDEX    12
43204 #define M_T7_CLSTRCINDEX    0x7ffU
43205 #define V_T7_CLSTRCINDEX(x) ((x) << S_T7_CLSTRCINDEX)
43206 #define G_T7_CLSTRCINDEX(x) (((x) >> S_T7_CLSTRCINDEX) & M_T7_CLSTRCINDEX)
43207 
43208 #define A_MPS_CLS_VLAN_TABLE 0xdfc0
43209 
43210 #define S_VLAN_MASK    16
43211 #define M_VLAN_MASK    0xfffU
43212 #define V_VLAN_MASK(x) ((x) << S_VLAN_MASK)
43213 #define G_VLAN_MASK(x) (((x) >> S_VLAN_MASK) & M_VLAN_MASK)
43214 
43215 #define S_VLANPF    13
43216 #define M_VLANPF    0x7U
43217 #define V_VLANPF(x) ((x) << S_VLANPF)
43218 #define G_VLANPF(x) (((x) >> S_VLANPF) & M_VLANPF)
43219 
43220 #define S_VLAN_VALID    12
43221 #define V_VLAN_VALID(x) ((x) << S_VLAN_VALID)
43222 #define F_VLAN_VALID    V_VLAN_VALID(1U)
43223 
43224 #define A_MPS_CLS_SRAM_L 0xe000
43225 
43226 #define S_MULTILISTEN3    28
43227 #define V_MULTILISTEN3(x) ((x) << S_MULTILISTEN3)
43228 #define F_MULTILISTEN3    V_MULTILISTEN3(1U)
43229 
43230 #define S_MULTILISTEN2    27
43231 #define V_MULTILISTEN2(x) ((x) << S_MULTILISTEN2)
43232 #define F_MULTILISTEN2    V_MULTILISTEN2(1U)
43233 
43234 #define S_MULTILISTEN1    26
43235 #define V_MULTILISTEN1(x) ((x) << S_MULTILISTEN1)
43236 #define F_MULTILISTEN1    V_MULTILISTEN1(1U)
43237 
43238 #define S_MULTILISTEN0    25
43239 #define V_MULTILISTEN0(x) ((x) << S_MULTILISTEN0)
43240 #define F_MULTILISTEN0    V_MULTILISTEN0(1U)
43241 
43242 #define S_SRAM_PRIO3    22
43243 #define M_SRAM_PRIO3    0x7U
43244 #define V_SRAM_PRIO3(x) ((x) << S_SRAM_PRIO3)
43245 #define G_SRAM_PRIO3(x) (((x) >> S_SRAM_PRIO3) & M_SRAM_PRIO3)
43246 
43247 #define S_SRAM_PRIO2    19
43248 #define M_SRAM_PRIO2    0x7U
43249 #define V_SRAM_PRIO2(x) ((x) << S_SRAM_PRIO2)
43250 #define G_SRAM_PRIO2(x) (((x) >> S_SRAM_PRIO2) & M_SRAM_PRIO2)
43251 
43252 #define S_SRAM_PRIO1    16
43253 #define M_SRAM_PRIO1    0x7U
43254 #define V_SRAM_PRIO1(x) ((x) << S_SRAM_PRIO1)
43255 #define G_SRAM_PRIO1(x) (((x) >> S_SRAM_PRIO1) & M_SRAM_PRIO1)
43256 
43257 #define S_SRAM_PRIO0    13
43258 #define M_SRAM_PRIO0    0x7U
43259 #define V_SRAM_PRIO0(x) ((x) << S_SRAM_PRIO0)
43260 #define G_SRAM_PRIO0(x) (((x) >> S_SRAM_PRIO0) & M_SRAM_PRIO0)
43261 
43262 #define S_SRAM_VLD    12
43263 #define V_SRAM_VLD(x) ((x) << S_SRAM_VLD)
43264 #define F_SRAM_VLD    V_SRAM_VLD(1U)
43265 
43266 #define A_MPS_T5_CLS_SRAM_L 0xe000
43267 
43268 #define S_T6_DISENCAPOUTERRPLCT    31
43269 #define V_T6_DISENCAPOUTERRPLCT(x) ((x) << S_T6_DISENCAPOUTERRPLCT)
43270 #define F_T6_DISENCAPOUTERRPLCT    V_T6_DISENCAPOUTERRPLCT(1U)
43271 
43272 #define S_T6_DISENCAP    30
43273 #define V_T6_DISENCAP(x) ((x) << S_T6_DISENCAP)
43274 #define F_T6_DISENCAP    V_T6_DISENCAP(1U)
43275 
43276 #define S_T6_MULTILISTEN3    29
43277 #define V_T6_MULTILISTEN3(x) ((x) << S_T6_MULTILISTEN3)
43278 #define F_T6_MULTILISTEN3    V_T6_MULTILISTEN3(1U)
43279 
43280 #define S_T6_MULTILISTEN2    28
43281 #define V_T6_MULTILISTEN2(x) ((x) << S_T6_MULTILISTEN2)
43282 #define F_T6_MULTILISTEN2    V_T6_MULTILISTEN2(1U)
43283 
43284 #define S_T6_MULTILISTEN1    27
43285 #define V_T6_MULTILISTEN1(x) ((x) << S_T6_MULTILISTEN1)
43286 #define F_T6_MULTILISTEN1    V_T6_MULTILISTEN1(1U)
43287 
43288 #define S_T6_MULTILISTEN0    26
43289 #define V_T6_MULTILISTEN0(x) ((x) << S_T6_MULTILISTEN0)
43290 #define F_T6_MULTILISTEN0    V_T6_MULTILISTEN0(1U)
43291 
43292 #define S_T6_SRAM_PRIO3    23
43293 #define M_T6_SRAM_PRIO3    0x7U
43294 #define V_T6_SRAM_PRIO3(x) ((x) << S_T6_SRAM_PRIO3)
43295 #define G_T6_SRAM_PRIO3(x) (((x) >> S_T6_SRAM_PRIO3) & M_T6_SRAM_PRIO3)
43296 
43297 #define S_T6_SRAM_PRIO2    20
43298 #define M_T6_SRAM_PRIO2    0x7U
43299 #define V_T6_SRAM_PRIO2(x) ((x) << S_T6_SRAM_PRIO2)
43300 #define G_T6_SRAM_PRIO2(x) (((x) >> S_T6_SRAM_PRIO2) & M_T6_SRAM_PRIO2)
43301 
43302 #define S_T6_SRAM_PRIO1    17
43303 #define M_T6_SRAM_PRIO1    0x7U
43304 #define V_T6_SRAM_PRIO1(x) ((x) << S_T6_SRAM_PRIO1)
43305 #define G_T6_SRAM_PRIO1(x) (((x) >> S_T6_SRAM_PRIO1) & M_T6_SRAM_PRIO1)
43306 
43307 #define S_T6_SRAM_PRIO0    14
43308 #define M_T6_SRAM_PRIO0    0x7U
43309 #define V_T6_SRAM_PRIO0(x) ((x) << S_T6_SRAM_PRIO0)
43310 #define G_T6_SRAM_PRIO0(x) (((x) >> S_T6_SRAM_PRIO0) & M_T6_SRAM_PRIO0)
43311 
43312 #define S_T6_SRAM_VLD    13
43313 #define V_T6_SRAM_VLD(x) ((x) << S_T6_SRAM_VLD)
43314 #define F_T6_SRAM_VLD    V_T6_SRAM_VLD(1U)
43315 
43316 #define A_MPS_CLS_SRAM_H 0xe004
43317 
43318 #define S_MACPARITY1    9
43319 #define V_MACPARITY1(x) ((x) << S_MACPARITY1)
43320 #define F_MACPARITY1    V_MACPARITY1(1U)
43321 
43322 #define S_MACPARITY0    8
43323 #define V_MACPARITY0(x) ((x) << S_MACPARITY0)
43324 #define F_MACPARITY0    V_MACPARITY0(1U)
43325 
43326 #define S_MACPARITYMASKSIZE    4
43327 #define M_MACPARITYMASKSIZE    0xfU
43328 #define V_MACPARITYMASKSIZE(x) ((x) << S_MACPARITYMASKSIZE)
43329 #define G_MACPARITYMASKSIZE(x) (((x) >> S_MACPARITYMASKSIZE) & M_MACPARITYMASKSIZE)
43330 
43331 #define S_PORTMAP    0
43332 #define M_PORTMAP    0xfU
43333 #define V_PORTMAP(x) ((x) << S_PORTMAP)
43334 #define G_PORTMAP(x) (((x) >> S_PORTMAP) & M_PORTMAP)
43335 
43336 #define A_MPS_T5_CLS_SRAM_H 0xe004
43337 
43338 #define S_MACPARITY2    10
43339 #define V_MACPARITY2(x) ((x) << S_MACPARITY2)
43340 #define F_MACPARITY2    V_MACPARITY2(1U)
43341 
43342 #define S_SRAMWRN    31
43343 #define V_SRAMWRN(x) ((x) << S_SRAMWRN)
43344 #define F_SRAMWRN    V_SRAMWRN(1U)
43345 
43346 #define S_SRAMSPARE    27
43347 #define M_SRAMSPARE    0xfU
43348 #define V_SRAMSPARE(x) ((x) << S_SRAMSPARE)
43349 #define G_SRAMSPARE(x) (((x) >> S_SRAMSPARE) & M_SRAMSPARE)
43350 
43351 #define S_SRAMINDEX    16
43352 #define M_SRAMINDEX    0x7ffU
43353 #define V_SRAMINDEX(x) ((x) << S_SRAMINDEX)
43354 #define G_SRAMINDEX(x) (((x) >> S_SRAMINDEX) & M_SRAMINDEX)
43355 
43356 #define A_MPS_CLS_HASH_TCAM_CTL 0xe008
43357 
43358 #define S_T7_CTLCMDTYPE    15
43359 #define V_T7_CTLCMDTYPE(x) ((x) << S_T7_CTLCMDTYPE)
43360 #define F_T7_CTLCMDTYPE    V_T7_CTLCMDTYPE(1U)
43361 
43362 #define S_T7_CTLXYBITSEL    12
43363 #define V_T7_CTLXYBITSEL(x) ((x) << S_T7_CTLXYBITSEL)
43364 #define F_T7_CTLXYBITSEL    V_T7_CTLXYBITSEL(1U)
43365 
43366 #define S_T7_CTLTCAMINDEX    0
43367 #define M_T7_CTLTCAMINDEX    0x1ffU
43368 #define V_T7_CTLTCAMINDEX(x) ((x) << S_T7_CTLTCAMINDEX)
43369 #define G_T7_CTLTCAMINDEX(x) (((x) >> S_T7_CTLTCAMINDEX) & M_T7_CTLTCAMINDEX)
43370 
43371 #define A_MPS_CLS_HASH_TCAM_DATA 0xe00c
43372 
43373 #define S_LKPTYPE    24
43374 #define V_LKPTYPE(x) ((x) << S_LKPTYPE)
43375 #define F_LKPTYPE    V_LKPTYPE(1U)
43376 
43377 #define A_MPS_CLS_TCAM_Y_L 0xf000
43378 #define A_MPS_CLS_TCAM_DATA0 0xf000
43379 #define A_MPS_CLS_TCAM_Y_H 0xf004
43380 
43381 #define S_TCAMYH    0
43382 #define M_TCAMYH    0xffffU
43383 #define V_TCAMYH(x) ((x) << S_TCAMYH)
43384 #define G_TCAMYH(x) (((x) >> S_TCAMYH) & M_TCAMYH)
43385 
43386 #define A_MPS_CLS_TCAM_DATA1 0xf004
43387 
43388 #define S_VIDL    16
43389 #define M_VIDL    0xffffU
43390 #define V_VIDL(x) ((x) << S_VIDL)
43391 #define G_VIDL(x) (((x) >> S_VIDL) & M_VIDL)
43392 
43393 #define S_DMACH    0
43394 #define M_DMACH    0xffffU
43395 #define V_DMACH(x) ((x) << S_DMACH)
43396 #define G_DMACH(x) (((x) >> S_DMACH) & M_DMACH)
43397 
43398 #define A_MPS_CLS_TCAM_X_L 0xf008
43399 #define A_MPS_CLS_TCAM_DATA2_CTL 0xf008
43400 
43401 #define S_CTLCMDTYPE    31
43402 #define V_CTLCMDTYPE(x) ((x) << S_CTLCMDTYPE)
43403 #define F_CTLCMDTYPE    V_CTLCMDTYPE(1U)
43404 
43405 #define S_CTLREQID    30
43406 #define V_CTLREQID(x) ((x) << S_CTLREQID)
43407 #define F_CTLREQID    V_CTLREQID(1U)
43408 
43409 #define S_CTLTCAMSEL    25
43410 #define V_CTLTCAMSEL(x) ((x) << S_CTLTCAMSEL)
43411 #define F_CTLTCAMSEL    V_CTLTCAMSEL(1U)
43412 
43413 #define S_CTLTCAMINDEX    17
43414 #define M_CTLTCAMINDEX    0xffU
43415 #define V_CTLTCAMINDEX(x) ((x) << S_CTLTCAMINDEX)
43416 #define G_CTLTCAMINDEX(x) (((x) >> S_CTLTCAMINDEX) & M_CTLTCAMINDEX)
43417 
43418 #define S_CTLXYBITSEL    16
43419 #define V_CTLXYBITSEL(x) ((x) << S_CTLXYBITSEL)
43420 #define F_CTLXYBITSEL    V_CTLXYBITSEL(1U)
43421 
43422 #define S_DATAPORTNUM    12
43423 #define M_DATAPORTNUM    0xfU
43424 #define V_DATAPORTNUM(x) ((x) << S_DATAPORTNUM)
43425 #define G_DATAPORTNUM(x) (((x) >> S_DATAPORTNUM) & M_DATAPORTNUM)
43426 
43427 #define S_DATALKPTYPE    10
43428 #define M_DATALKPTYPE    0x3U
43429 #define V_DATALKPTYPE(x) ((x) << S_DATALKPTYPE)
43430 #define G_DATALKPTYPE(x) (((x) >> S_DATALKPTYPE) & M_DATALKPTYPE)
43431 
43432 #define S_DATADIPHIT    8
43433 #define V_DATADIPHIT(x) ((x) << S_DATADIPHIT)
43434 #define F_DATADIPHIT    V_DATADIPHIT(1U)
43435 
43436 #define S_DATAVIDH2    7
43437 #define V_DATAVIDH2(x) ((x) << S_DATAVIDH2)
43438 #define F_DATAVIDH2    V_DATAVIDH2(1U)
43439 
43440 #define S_DATAVIDH1    0
43441 #define M_DATAVIDH1    0x7fU
43442 #define V_DATAVIDH1(x) ((x) << S_DATAVIDH1)
43443 #define G_DATAVIDH1(x) (((x) >> S_DATAVIDH1) & M_DATAVIDH1)
43444 
43445 #define S_T7_CTLTCAMSEL    26
43446 #define M_T7_CTLTCAMSEL    0x3U
43447 #define V_T7_CTLTCAMSEL(x) ((x) << S_T7_CTLTCAMSEL)
43448 #define G_T7_CTLTCAMSEL(x) (((x) >> S_T7_CTLTCAMSEL) & M_T7_CTLTCAMSEL)
43449 
43450 #define S_T7_1_CTLTCAMINDEX    17
43451 #define M_T7_1_CTLTCAMINDEX    0x1ffU
43452 #define V_T7_1_CTLTCAMINDEX(x) ((x) << S_T7_1_CTLTCAMINDEX)
43453 #define G_T7_1_CTLTCAMINDEX(x) (((x) >> S_T7_1_CTLTCAMINDEX) & M_T7_1_CTLTCAMINDEX)
43454 
43455 #define A_MPS_CLS_TCAM_X_H 0xf00c
43456 
43457 #define S_TCAMXH    0
43458 #define M_TCAMXH    0xffffU
43459 #define V_TCAMXH(x) ((x) << S_TCAMXH)
43460 #define G_TCAMXH(x) (((x) >> S_TCAMXH) & M_TCAMXH)
43461 
43462 #define A_MPS_CLS_TCAM_RDATA0_REQ_ID0 0xf010
43463 #define A_MPS_CLS_TCAM0_RDATA0_REQ_ID0 0xf010
43464 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID0 0xf014
43465 #define A_MPS_CLS_TCAM0_RDATA1_REQ_ID0 0xf014
43466 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID0 0xf018
43467 #define A_MPS_CLS_TCAM0_RDATA2_REQ_ID0 0xf018
43468 #define A_MPS_CLS_TCAM0_RDATA0_REQ_ID1 0xf01c
43469 #define A_MPS_CLS_TCAM_RDATA0_REQ_ID1 0xf020
43470 #define A_MPS_CLS_TCAM0_RDATA1_REQ_ID1 0xf020
43471 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID1 0xf024
43472 #define A_MPS_CLS_TCAM0_RDATA2_REQ_ID1 0xf024
43473 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID1 0xf028
43474 #define A_MPS_CLS_TCAM1_RDATA0_REQ_ID0 0xf028
43475 #define A_MPS_CLS_TCAM1_RDATA1_REQ_ID0 0xf02c
43476 #define A_MPS_CLS_TCAM1_RDATA2_REQ_ID0 0xf030
43477 #define A_MPS_CLS_TCAM1_RDATA0_REQ_ID1 0xf034
43478 #define A_MPS_CLS_TCAM1_RDATA1_REQ_ID1 0xf038
43479 #define A_MPS_CLS_TCAM1_RDATA2_REQ_ID1 0xf03c
43480 #define A_MPS_CLS_TCAM0_MASK_REG0 0xf040
43481 #define A_MPS_CLS_TCAM0_MASK_REG1 0xf044
43482 #define A_MPS_CLS_TCAM0_MASK_REG2 0xf048
43483 
43484 #define S_MASK_0_2    0
43485 #define M_MASK_0_2    0xffffU
43486 #define V_MASK_0_2(x) ((x) << S_MASK_0_2)
43487 #define G_MASK_0_2(x) (((x) >> S_MASK_0_2) & M_MASK_0_2)
43488 
43489 #define A_MPS_CLS_TCAM1_MASK_REG0 0xf04c
43490 #define A_MPS_CLS_TCAM1_MASK_REG1 0xf050
43491 #define A_MPS_CLS_TCAM1_MASK_REG2 0xf054
43492 
43493 #define S_MASK_1_2    0
43494 #define M_MASK_1_2    0xffffU
43495 #define V_MASK_1_2(x) ((x) << S_MASK_1_2)
43496 #define G_MASK_1_2(x) (((x) >> S_MASK_1_2) & M_MASK_1_2)
43497 
43498 #define A_MPS_CLS_TCAM_BIST_CTRL 0xf058
43499 #define A_MPS_CLS_TCAM_BIST_CB_PASS 0xf05c
43500 #define A_MPS_CLS_TCAM_BIST_CB_BUSY 0xf060
43501 #define A_MPS_CLS_TCAM2_MASK_REG0 0xf064
43502 #define A_MPS_CLS_TCAM2_MASK_REG1 0xf068
43503 #define A_MPS_CLS_TCAM2_MASK_REG2 0xf06c
43504 #define A_MPS_RX_CTL 0x11000
43505 
43506 #define S_FILT_VLAN_SEL    17
43507 #define V_FILT_VLAN_SEL(x) ((x) << S_FILT_VLAN_SEL)
43508 #define F_FILT_VLAN_SEL    V_FILT_VLAN_SEL(1U)
43509 
43510 #define S_CBA_EN    16
43511 #define V_CBA_EN(x) ((x) << S_CBA_EN)
43512 #define F_CBA_EN    V_CBA_EN(1U)
43513 
43514 #define S_BLK_SNDR    12
43515 #define M_BLK_SNDR    0xfU
43516 #define V_BLK_SNDR(x) ((x) << S_BLK_SNDR)
43517 #define G_BLK_SNDR(x) (((x) >> S_BLK_SNDR) & M_BLK_SNDR)
43518 
43519 #define S_CMPRS    8
43520 #define M_CMPRS    0xfU
43521 #define V_CMPRS(x) ((x) << S_CMPRS)
43522 #define G_CMPRS(x) (((x) >> S_CMPRS) & M_CMPRS)
43523 
43524 #define S_SNF    0
43525 #define M_SNF    0xffU
43526 #define V_SNF(x) ((x) << S_SNF)
43527 #define G_SNF(x) (((x) >> S_SNF) & M_SNF)
43528 
43529 #define S_HASH_TCAM_EN    19
43530 #define V_HASH_TCAM_EN(x) ((x) << S_HASH_TCAM_EN)
43531 #define F_HASH_TCAM_EN    V_HASH_TCAM_EN(1U)
43532 
43533 #define S_SND_ORG_PFVF    18
43534 #define V_SND_ORG_PFVF(x) ((x) << S_SND_ORG_PFVF)
43535 #define F_SND_ORG_PFVF    V_SND_ORG_PFVF(1U)
43536 
43537 #define A_MPS_RX_PORT_MUX_CTL 0x11004
43538 
43539 #define S_CTL_P3    12
43540 #define M_CTL_P3    0xfU
43541 #define V_CTL_P3(x) ((x) << S_CTL_P3)
43542 #define G_CTL_P3(x) (((x) >> S_CTL_P3) & M_CTL_P3)
43543 
43544 #define S_CTL_P2    8
43545 #define M_CTL_P2    0xfU
43546 #define V_CTL_P2(x) ((x) << S_CTL_P2)
43547 #define G_CTL_P2(x) (((x) >> S_CTL_P2) & M_CTL_P2)
43548 
43549 #define S_CTL_P1    4
43550 #define M_CTL_P1    0xfU
43551 #define V_CTL_P1(x) ((x) << S_CTL_P1)
43552 #define G_CTL_P1(x) (((x) >> S_CTL_P1) & M_CTL_P1)
43553 
43554 #define S_CTL_P0    0
43555 #define M_CTL_P0    0xfU
43556 #define V_CTL_P0(x) ((x) << S_CTL_P0)
43557 #define G_CTL_P0(x) (((x) >> S_CTL_P0) & M_CTL_P0)
43558 
43559 #define A_MPS_RX_PG_FL 0x11008
43560 
43561 #define S_RST    16
43562 #define V_RST(x) ((x) << S_RST)
43563 #define F_RST    V_RST(1U)
43564 
43565 #define S_CNT    0
43566 #define M_CNT    0xffffU
43567 #define V_CNT(x) ((x) << S_CNT)
43568 #define G_CNT(x) (((x) >> S_CNT) & M_CNT)
43569 
43570 #define A_MPS_RX_FIFO_0_CTL 0x11008
43571 
43572 #define S_DEST_SELECT    0
43573 #define M_DEST_SELECT    0xfU
43574 #define V_DEST_SELECT(x) ((x) << S_DEST_SELECT)
43575 #define G_DEST_SELECT(x) (((x) >> S_DEST_SELECT) & M_DEST_SELECT)
43576 
43577 #define A_MPS_RX_PKT_FL 0x1100c
43578 #define A_MPS_RX_FIFO_1_CTL 0x1100c
43579 #define A_MPS_RX_PG_RSV0 0x11010
43580 
43581 #define S_CLR_INTR    31
43582 #define V_CLR_INTR(x) ((x) << S_CLR_INTR)
43583 #define F_CLR_INTR    V_CLR_INTR(1U)
43584 
43585 #define S_SET_INTR    30
43586 #define V_SET_INTR(x) ((x) << S_SET_INTR)
43587 #define F_SET_INTR    V_SET_INTR(1U)
43588 
43589 #define S_USED    16
43590 #define M_USED    0x7ffU
43591 #define V_USED(x) ((x) << S_USED)
43592 #define G_USED(x) (((x) >> S_USED) & M_USED)
43593 
43594 #define S_ALLOC    0
43595 #define M_ALLOC    0x7ffU
43596 #define V_ALLOC(x) ((x) << S_ALLOC)
43597 #define G_ALLOC(x) (((x) >> S_ALLOC) & M_ALLOC)
43598 
43599 #define S_T5_USED    16
43600 #define M_T5_USED    0xfffU
43601 #define V_T5_USED(x) ((x) << S_T5_USED)
43602 #define G_T5_USED(x) (((x) >> S_T5_USED) & M_T5_USED)
43603 
43604 #define S_T5_ALLOC    0
43605 #define M_T5_ALLOC    0xfffU
43606 #define V_T5_ALLOC(x) ((x) << S_T5_ALLOC)
43607 #define G_T5_ALLOC(x) (((x) >> S_T5_ALLOC) & M_T5_ALLOC)
43608 
43609 #define A_MPS_RX_FIFO_2_CTL 0x11010
43610 #define A_MPS_RX_PG_RSV1 0x11014
43611 #define A_MPS_RX_FIFO_3_CTL 0x11014
43612 #define A_MPS_RX_PG_RSV2 0x11018
43613 #define A_MPS_RX_PG_RSV3 0x1101c
43614 #define A_MPS_RX_PG_RSV4 0x11020
43615 #define A_MPS_RX_PG_RSV5 0x11024
43616 #define A_MPS_RX_PG_RSV6 0x11028
43617 #define A_MPS_RX_PG_RSV7 0x1102c
43618 #define A_MPS_RX_PG_SHR_BG0 0x11030
43619 
43620 #define S_EN    31
43621 #define V_EN(x) ((x) << S_EN)
43622 #define F_EN    V_EN(1U)
43623 
43624 #define S_SEL    30
43625 #define V_SEL(x) ((x) << S_SEL)
43626 #define F_SEL    V_SEL(1U)
43627 
43628 #define S_MAX    16
43629 #define M_MAX    0x7ffU
43630 #define V_MAX(x) ((x) << S_MAX)
43631 #define G_MAX(x) (((x) >> S_MAX) & M_MAX)
43632 
43633 #define S_BORW    0
43634 #define M_BORW    0x7ffU
43635 #define V_BORW(x) ((x) << S_BORW)
43636 #define G_BORW(x) (((x) >> S_BORW) & M_BORW)
43637 
43638 #define S_T5_MAX    16
43639 #define M_T5_MAX    0xfffU
43640 #define V_T5_MAX(x) ((x) << S_T5_MAX)
43641 #define G_T5_MAX(x) (((x) >> S_T5_MAX) & M_T5_MAX)
43642 
43643 #define S_T5_BORW    0
43644 #define M_T5_BORW    0xfffU
43645 #define V_T5_BORW(x) ((x) << S_T5_BORW)
43646 #define G_T5_BORW(x) (((x) >> S_T5_BORW) & M_T5_BORW)
43647 
43648 #define A_MPS_RX_PG_SHR_BG1 0x11034
43649 #define A_MPS_RX_PG_SHR_BG2 0x11038
43650 #define A_MPS_RX_PG_SHR_BG3 0x1103c
43651 #define A_MPS_RX_PG_SHR0 0x11040
43652 
43653 #define S_QUOTA    16
43654 #define M_QUOTA    0x7ffU
43655 #define V_QUOTA(x) ((x) << S_QUOTA)
43656 #define G_QUOTA(x) (((x) >> S_QUOTA) & M_QUOTA)
43657 
43658 #define S_SHR_USED    0
43659 #define M_SHR_USED    0x7ffU
43660 #define V_SHR_USED(x) ((x) << S_SHR_USED)
43661 #define G_SHR_USED(x) (((x) >> S_SHR_USED) & M_SHR_USED)
43662 
43663 #define S_T5_QUOTA    16
43664 #define M_T5_QUOTA    0xfffU
43665 #define V_T5_QUOTA(x) ((x) << S_T5_QUOTA)
43666 #define G_T5_QUOTA(x) (((x) >> S_T5_QUOTA) & M_T5_QUOTA)
43667 
43668 #define S_T5_SHR_USED    0
43669 #define M_T5_SHR_USED    0xfffU
43670 #define V_T5_SHR_USED(x) ((x) << S_T5_SHR_USED)
43671 #define G_T5_SHR_USED(x) (((x) >> S_T5_SHR_USED) & M_T5_SHR_USED)
43672 
43673 #define A_MPS_RX_PG_SHR1 0x11044
43674 #define A_MPS_RX_PG_HYST_BG0 0x11048
43675 
43676 #define S_TH    0
43677 #define M_TH    0x7ffU
43678 #define V_TH(x) ((x) << S_TH)
43679 #define G_TH(x) (((x) >> S_TH) & M_TH)
43680 
43681 #define S_T5_TH    0
43682 #define M_T5_TH    0xfffU
43683 #define V_T5_TH(x) ((x) << S_T5_TH)
43684 #define G_T5_TH(x) (((x) >> S_T5_TH) & M_T5_TH)
43685 
43686 #define S_T6_TH    0
43687 #define M_T6_TH    0x7ffU
43688 #define V_T6_TH(x) ((x) << S_T6_TH)
43689 #define G_T6_TH(x) (((x) >> S_T6_TH) & M_T6_TH)
43690 
43691 #define A_MPS_RX_PG_HYST_BG1 0x1104c
43692 #define A_MPS_RX_PG_HYST_BG2 0x11050
43693 #define A_MPS_RX_PG_HYST_BG3 0x11054
43694 #define A_MPS_RX_OCH_CTL 0x11058
43695 
43696 #define S_DROP_WT    27
43697 #define M_DROP_WT    0x1fU
43698 #define V_DROP_WT(x) ((x) << S_DROP_WT)
43699 #define G_DROP_WT(x) (((x) >> S_DROP_WT) & M_DROP_WT)
43700 
43701 #define S_TRUNC_WT    22
43702 #define M_TRUNC_WT    0x1fU
43703 #define V_TRUNC_WT(x) ((x) << S_TRUNC_WT)
43704 #define G_TRUNC_WT(x) (((x) >> S_TRUNC_WT) & M_TRUNC_WT)
43705 
43706 #define S_OCH_DRAIN    13
43707 #define M_OCH_DRAIN    0x1fU
43708 #define V_OCH_DRAIN(x) ((x) << S_OCH_DRAIN)
43709 #define G_OCH_DRAIN(x) (((x) >> S_OCH_DRAIN) & M_OCH_DRAIN)
43710 
43711 #define S_OCH_DROP    8
43712 #define M_OCH_DROP    0x1fU
43713 #define V_OCH_DROP(x) ((x) << S_OCH_DROP)
43714 #define G_OCH_DROP(x) (((x) >> S_OCH_DROP) & M_OCH_DROP)
43715 
43716 #define S_STOP    0
43717 #define M_STOP    0x1fU
43718 #define V_STOP(x) ((x) << S_STOP)
43719 #define G_STOP(x) (((x) >> S_STOP) & M_STOP)
43720 
43721 #define A_MPS_RX_LPBK_BP0 0x1105c
43722 
43723 #define S_THRESH    0
43724 #define M_THRESH    0x7ffU
43725 #define V_THRESH(x) ((x) << S_THRESH)
43726 #define G_THRESH(x) (((x) >> S_THRESH) & M_THRESH)
43727 
43728 #define S_T7_THRESH    0
43729 #define M_T7_THRESH    0xfffU
43730 #define V_T7_THRESH(x) ((x) << S_T7_THRESH)
43731 #define G_T7_THRESH(x) (((x) >> S_T7_THRESH) & M_T7_THRESH)
43732 
43733 #define A_MPS_RX_LPBK_BP1 0x11060
43734 #define A_MPS_RX_LPBK_BP2 0x11064
43735 #define A_MPS_RX_LPBK_BP3 0x11068
43736 #define A_MPS_RX_PORT_GAP 0x1106c
43737 
43738 #define S_GAP    0
43739 #define M_GAP    0xfffffU
43740 #define V_GAP(x) ((x) << S_GAP)
43741 #define G_GAP(x) (((x) >> S_GAP) & M_GAP)
43742 
43743 #define A_MPS_RX_CHMN_CNT 0x11070
43744 #define A_MPS_CTL_STAT 0x11070
43745 
43746 #define S_T7_CTL    0
43747 #define V_T7_CTL(x) ((x) << S_T7_CTL)
43748 #define F_T7_CTL    V_T7_CTL(1U)
43749 
43750 #define A_MPS_RX_PERR_INT_CAUSE 0x11074
43751 
43752 #define S_FF    23
43753 #define V_FF(x) ((x) << S_FF)
43754 #define F_FF    V_FF(1U)
43755 
43756 #define S_PGMO    22
43757 #define V_PGMO(x) ((x) << S_PGMO)
43758 #define F_PGMO    V_PGMO(1U)
43759 
43760 #define S_PGME    21
43761 #define V_PGME(x) ((x) << S_PGME)
43762 #define F_PGME    V_PGME(1U)
43763 
43764 #define S_CHMN    20
43765 #define V_CHMN(x) ((x) << S_CHMN)
43766 #define F_CHMN    V_CHMN(1U)
43767 
43768 #define S_RPLC    19
43769 #define V_RPLC(x) ((x) << S_RPLC)
43770 #define F_RPLC    V_RPLC(1U)
43771 
43772 #define S_ATRB    18
43773 #define V_ATRB(x) ((x) << S_ATRB)
43774 #define F_ATRB    V_ATRB(1U)
43775 
43776 #define S_PSMX    17
43777 #define V_PSMX(x) ((x) << S_PSMX)
43778 #define F_PSMX    V_PSMX(1U)
43779 
43780 #define S_PGLL    16
43781 #define V_PGLL(x) ((x) << S_PGLL)
43782 #define F_PGLL    V_PGLL(1U)
43783 
43784 #define S_PGFL    15
43785 #define V_PGFL(x) ((x) << S_PGFL)
43786 #define F_PGFL    V_PGFL(1U)
43787 
43788 #define S_PKTQ    14
43789 #define V_PKTQ(x) ((x) << S_PKTQ)
43790 #define F_PKTQ    V_PKTQ(1U)
43791 
43792 #define S_PKFL    13
43793 #define V_PKFL(x) ((x) << S_PKFL)
43794 #define F_PKFL    V_PKFL(1U)
43795 
43796 #define S_PPM3    12
43797 #define V_PPM3(x) ((x) << S_PPM3)
43798 #define F_PPM3    V_PPM3(1U)
43799 
43800 #define S_PPM2    11
43801 #define V_PPM2(x) ((x) << S_PPM2)
43802 #define F_PPM2    V_PPM2(1U)
43803 
43804 #define S_PPM1    10
43805 #define V_PPM1(x) ((x) << S_PPM1)
43806 #define F_PPM1    V_PPM1(1U)
43807 
43808 #define S_PPM0    9
43809 #define V_PPM0(x) ((x) << S_PPM0)
43810 #define F_PPM0    V_PPM0(1U)
43811 
43812 #define S_SPMX    8
43813 #define V_SPMX(x) ((x) << S_SPMX)
43814 #define F_SPMX    V_SPMX(1U)
43815 
43816 #define S_CDL3    7
43817 #define V_CDL3(x) ((x) << S_CDL3)
43818 #define F_CDL3    V_CDL3(1U)
43819 
43820 #define S_CDL2    6
43821 #define V_CDL2(x) ((x) << S_CDL2)
43822 #define F_CDL2    V_CDL2(1U)
43823 
43824 #define S_CDL1    5
43825 #define V_CDL1(x) ((x) << S_CDL1)
43826 #define F_CDL1    V_CDL1(1U)
43827 
43828 #define S_CDL0    4
43829 #define V_CDL0(x) ((x) << S_CDL0)
43830 #define F_CDL0    V_CDL0(1U)
43831 
43832 #define S_CDM3    3
43833 #define V_CDM3(x) ((x) << S_CDM3)
43834 #define F_CDM3    V_CDM3(1U)
43835 
43836 #define S_CDM2    2
43837 #define V_CDM2(x) ((x) << S_CDM2)
43838 #define F_CDM2    V_CDM2(1U)
43839 
43840 #define S_CDM1    1
43841 #define V_CDM1(x) ((x) << S_CDM1)
43842 #define F_CDM1    V_CDM1(1U)
43843 
43844 #define S_CDM0    0
43845 #define V_CDM0(x) ((x) << S_CDM0)
43846 #define F_CDM0    V_CDM0(1U)
43847 
43848 #define S_T6_INT_ERR_INT    24
43849 #define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT)
43850 #define F_T6_INT_ERR_INT    V_T6_INT_ERR_INT(1U)
43851 
43852 #define S_MAC_IN_FIFO_768B    30
43853 #define V_MAC_IN_FIFO_768B(x) ((x) << S_MAC_IN_FIFO_768B)
43854 #define F_MAC_IN_FIFO_768B    V_MAC_IN_FIFO_768B(1U)
43855 
43856 #define S_T7_1_INT_ERR_INT    29
43857 #define V_T7_1_INT_ERR_INT(x) ((x) << S_T7_1_INT_ERR_INT)
43858 #define F_T7_1_INT_ERR_INT    V_T7_1_INT_ERR_INT(1U)
43859 
43860 #define S_FLOP_PERR    28
43861 #define V_FLOP_PERR(x) ((x) << S_FLOP_PERR)
43862 #define F_FLOP_PERR    V_FLOP_PERR(1U)
43863 
43864 #define S_RPLC_MAP    13
43865 #define M_RPLC_MAP    0x1fU
43866 #define V_RPLC_MAP(x) ((x) << S_RPLC_MAP)
43867 #define G_RPLC_MAP(x) (((x) >> S_RPLC_MAP) & M_RPLC_MAP)
43868 
43869 #define S_TKN_RUNT_DROP_FIFO    12
43870 #define V_TKN_RUNT_DROP_FIFO(x) ((x) << S_TKN_RUNT_DROP_FIFO)
43871 #define F_TKN_RUNT_DROP_FIFO    V_TKN_RUNT_DROP_FIFO(1U)
43872 
43873 #define S_T7_PPM3    9
43874 #define M_T7_PPM3    0x7U
43875 #define V_T7_PPM3(x) ((x) << S_T7_PPM3)
43876 #define G_T7_PPM3(x) (((x) >> S_T7_PPM3) & M_T7_PPM3)
43877 
43878 #define S_T7_PPM2    6
43879 #define M_T7_PPM2    0x7U
43880 #define V_T7_PPM2(x) ((x) << S_T7_PPM2)
43881 #define G_T7_PPM2(x) (((x) >> S_T7_PPM2) & M_T7_PPM2)
43882 
43883 #define S_T7_PPM1    3
43884 #define M_T7_PPM1    0x7U
43885 #define V_T7_PPM1(x) ((x) << S_T7_PPM1)
43886 #define G_T7_PPM1(x) (((x) >> S_T7_PPM1) & M_T7_PPM1)
43887 
43888 #define S_T7_PPM0    0
43889 #define M_T7_PPM0    0x7U
43890 #define V_T7_PPM0(x) ((x) << S_T7_PPM0)
43891 #define G_T7_PPM0(x) (((x) >> S_T7_PPM0) & M_T7_PPM0)
43892 
43893 #define A_MPS_RX_PERR_INT_ENABLE 0x11078
43894 
43895 #define S_T7_2_INT_ERR_INT    30
43896 #define V_T7_2_INT_ERR_INT(x) ((x) << S_T7_2_INT_ERR_INT)
43897 #define F_T7_2_INT_ERR_INT    V_T7_2_INT_ERR_INT(1U)
43898 
43899 #define A_MPS_RX_PERR_ENABLE 0x1107c
43900 #define A_MPS_RX_PERR_INJECT 0x11080
43901 #define A_MPS_RX_FUNC_INT_CAUSE 0x11084
43902 
43903 #define S_INT_ERR_INT    8
43904 #define M_INT_ERR_INT    0x1fU
43905 #define V_INT_ERR_INT(x) ((x) << S_INT_ERR_INT)
43906 #define G_INT_ERR_INT(x) (((x) >> S_INT_ERR_INT) & M_INT_ERR_INT)
43907 
43908 #define S_PG_TH_INT7    7
43909 #define V_PG_TH_INT7(x) ((x) << S_PG_TH_INT7)
43910 #define F_PG_TH_INT7    V_PG_TH_INT7(1U)
43911 
43912 #define S_PG_TH_INT6    6
43913 #define V_PG_TH_INT6(x) ((x) << S_PG_TH_INT6)
43914 #define F_PG_TH_INT6    V_PG_TH_INT6(1U)
43915 
43916 #define S_PG_TH_INT5    5
43917 #define V_PG_TH_INT5(x) ((x) << S_PG_TH_INT5)
43918 #define F_PG_TH_INT5    V_PG_TH_INT5(1U)
43919 
43920 #define S_PG_TH_INT4    4
43921 #define V_PG_TH_INT4(x) ((x) << S_PG_TH_INT4)
43922 #define F_PG_TH_INT4    V_PG_TH_INT4(1U)
43923 
43924 #define S_PG_TH_INT3    3
43925 #define V_PG_TH_INT3(x) ((x) << S_PG_TH_INT3)
43926 #define F_PG_TH_INT3    V_PG_TH_INT3(1U)
43927 
43928 #define S_PG_TH_INT2    2
43929 #define V_PG_TH_INT2(x) ((x) << S_PG_TH_INT2)
43930 #define F_PG_TH_INT2    V_PG_TH_INT2(1U)
43931 
43932 #define S_PG_TH_INT1    1
43933 #define V_PG_TH_INT1(x) ((x) << S_PG_TH_INT1)
43934 #define F_PG_TH_INT1    V_PG_TH_INT1(1U)
43935 
43936 #define S_PG_TH_INT0    0
43937 #define V_PG_TH_INT0(x) ((x) << S_PG_TH_INT0)
43938 #define F_PG_TH_INT0    V_PG_TH_INT0(1U)
43939 
43940 #define S_MTU_ERR_INT3    19
43941 #define V_MTU_ERR_INT3(x) ((x) << S_MTU_ERR_INT3)
43942 #define F_MTU_ERR_INT3    V_MTU_ERR_INT3(1U)
43943 
43944 #define S_MTU_ERR_INT2    18
43945 #define V_MTU_ERR_INT2(x) ((x) << S_MTU_ERR_INT2)
43946 #define F_MTU_ERR_INT2    V_MTU_ERR_INT2(1U)
43947 
43948 #define S_MTU_ERR_INT1    17
43949 #define V_MTU_ERR_INT1(x) ((x) << S_MTU_ERR_INT1)
43950 #define F_MTU_ERR_INT1    V_MTU_ERR_INT1(1U)
43951 
43952 #define S_MTU_ERR_INT0    16
43953 #define V_MTU_ERR_INT0(x) ((x) << S_MTU_ERR_INT0)
43954 #define F_MTU_ERR_INT0    V_MTU_ERR_INT0(1U)
43955 
43956 #define S_SE_CNT_ERR_INT    15
43957 #define V_SE_CNT_ERR_INT(x) ((x) << S_SE_CNT_ERR_INT)
43958 #define F_SE_CNT_ERR_INT    V_SE_CNT_ERR_INT(1U)
43959 
43960 #define S_FRM_ERR_INT    14
43961 #define V_FRM_ERR_INT(x) ((x) << S_FRM_ERR_INT)
43962 #define F_FRM_ERR_INT    V_FRM_ERR_INT(1U)
43963 
43964 #define S_LEN_ERR_INT    13
43965 #define V_LEN_ERR_INT(x) ((x) << S_LEN_ERR_INT)
43966 #define F_LEN_ERR_INT    V_LEN_ERR_INT(1U)
43967 
43968 #define A_MPS_RX_FUNC_INT_ENABLE 0x11088
43969 #define A_MPS_RX_PAUSE_GEN_TH_0 0x1108c
43970 
43971 #define S_TH_HIGH    16
43972 #define M_TH_HIGH    0xffffU
43973 #define V_TH_HIGH(x) ((x) << S_TH_HIGH)
43974 #define G_TH_HIGH(x) (((x) >> S_TH_HIGH) & M_TH_HIGH)
43975 
43976 #define S_TH_LOW    0
43977 #define M_TH_LOW    0xffffU
43978 #define V_TH_LOW(x) ((x) << S_TH_LOW)
43979 #define G_TH_LOW(x) (((x) >> S_TH_LOW) & M_TH_LOW)
43980 
43981 #define A_MPS_RX_PERR_INT_CAUSE2 0x1108c
43982 
43983 #define S_CRYPT2MPS_RX_INTF_FIFO    28
43984 #define M_CRYPT2MPS_RX_INTF_FIFO    0xfU
43985 #define V_CRYPT2MPS_RX_INTF_FIFO(x) ((x) << S_CRYPT2MPS_RX_INTF_FIFO)
43986 #define G_CRYPT2MPS_RX_INTF_FIFO(x) (((x) >> S_CRYPT2MPS_RX_INTF_FIFO) & M_CRYPT2MPS_RX_INTF_FIFO)
43987 
43988 #define S_INIC2MPS_TX0_PERR    27
43989 #define V_INIC2MPS_TX0_PERR(x) ((x) << S_INIC2MPS_TX0_PERR)
43990 #define F_INIC2MPS_TX0_PERR    V_INIC2MPS_TX0_PERR(1U)
43991 
43992 #define S_INIC2MPS_TX1_PERR    26
43993 #define V_INIC2MPS_TX1_PERR(x) ((x) << S_INIC2MPS_TX1_PERR)
43994 #define F_INIC2MPS_TX1_PERR    V_INIC2MPS_TX1_PERR(1U)
43995 
43996 #define S_XGMAC2MPS_RX0_PERR    25
43997 #define V_XGMAC2MPS_RX0_PERR(x) ((x) << S_XGMAC2MPS_RX0_PERR)
43998 #define F_XGMAC2MPS_RX0_PERR    V_XGMAC2MPS_RX0_PERR(1U)
43999 
44000 #define S_XGMAC2MPS_RX1_PERR    24
44001 #define V_XGMAC2MPS_RX1_PERR(x) ((x) << S_XGMAC2MPS_RX1_PERR)
44002 #define F_XGMAC2MPS_RX1_PERR    V_XGMAC2MPS_RX1_PERR(1U)
44003 
44004 #define S_MPS2CRYPTO_RX_INTF_FIFO    20
44005 #define M_MPS2CRYPTO_RX_INTF_FIFO    0xfU
44006 #define V_MPS2CRYPTO_RX_INTF_FIFO(x) ((x) << S_MPS2CRYPTO_RX_INTF_FIFO)
44007 #define G_MPS2CRYPTO_RX_INTF_FIFO(x) (((x) >> S_MPS2CRYPTO_RX_INTF_FIFO) & M_MPS2CRYPTO_RX_INTF_FIFO)
44008 
44009 #define S_RX_PRE_PROC_PERR    9
44010 #define M_RX_PRE_PROC_PERR    0x7ffU
44011 #define V_RX_PRE_PROC_PERR(x) ((x) << S_RX_PRE_PROC_PERR)
44012 #define G_RX_PRE_PROC_PERR(x) (((x) >> S_RX_PRE_PROC_PERR) & M_RX_PRE_PROC_PERR)
44013 
44014 #define A_MPS_RX_PAUSE_GEN_TH_1 0x11090
44015 #define A_MPS_RX_PERR_INT_ENABLE2 0x11090
44016 #define A_MPS_RX_PAUSE_GEN_TH_2 0x11094
44017 #define A_MPS_RX_PERR_ENABLE2 0x11094
44018 #define A_MPS_RX_PAUSE_GEN_TH_3 0x11098
44019 #define A_MPS_RX_REPL_CTL 0x11098
44020 
44021 #define S_INDEX_SEL    0
44022 #define V_INDEX_SEL(x) ((x) << S_INDEX_SEL)
44023 #define F_INDEX_SEL    V_INDEX_SEL(1U)
44024 
44025 #define A_MPS_RX_PPP_ATRB 0x1109c
44026 
44027 #define S_ETYPE    16
44028 #define M_ETYPE    0xffffU
44029 #define V_ETYPE(x) ((x) << S_ETYPE)
44030 #define G_ETYPE(x) (((x) >> S_ETYPE) & M_ETYPE)
44031 
44032 #define S_OPCODE    0
44033 #define M_OPCODE    0xffffU
44034 #define V_OPCODE(x) ((x) << S_OPCODE)
44035 #define G_OPCODE(x) (((x) >> S_OPCODE) & M_OPCODE)
44036 
44037 #define A_MPS_RX_QFC0_ATRB 0x110a0
44038 
44039 #define S_DA    0
44040 #define M_DA    0xffffU
44041 #define V_DA(x) ((x) << S_DA)
44042 #define G_DA(x) (((x) >> S_DA) & M_DA)
44043 
44044 #define A_MPS_RX_QFC1_ATRB 0x110a4
44045 #define A_MPS_RX_PT_ARB0 0x110a8
44046 
44047 #define S_LPBK_WT    16
44048 #define M_LPBK_WT    0x3fffU
44049 #define V_LPBK_WT(x) ((x) << S_LPBK_WT)
44050 #define G_LPBK_WT(x) (((x) >> S_LPBK_WT) & M_LPBK_WT)
44051 
44052 #define S_MAC_WT    0
44053 #define M_MAC_WT    0x3fffU
44054 #define V_MAC_WT(x) ((x) << S_MAC_WT)
44055 #define G_MAC_WT(x) (((x) >> S_MAC_WT) & M_MAC_WT)
44056 
44057 #define A_MPS_RX_PT_ARB1 0x110ac
44058 #define A_MPS_RX_PT_ARB2 0x110b0
44059 #define A_T7_MPS_RX_PT_ARB4 0x110b0
44060 #define A_MPS_RX_PT_ARB3 0x110b4
44061 #define A_T6_MPS_PF_OUT_EN 0x110b4
44062 #define A_T7_MPS_PF_OUT_EN 0x110b4
44063 #define A_MPS_RX_PT_ARB4 0x110b8
44064 #define A_T6_MPS_BMC_MTU 0x110b8
44065 #define A_T7_MPS_BMC_MTU 0x110b8
44066 #define A_MPS_PF_OUT_EN 0x110bc
44067 
44068 #define S_OUTEN    0
44069 #define M_OUTEN    0xffU
44070 #define V_OUTEN(x) ((x) << S_OUTEN)
44071 #define G_OUTEN(x) (((x) >> S_OUTEN) & M_OUTEN)
44072 
44073 #define A_T6_MPS_BMC_PKT_CNT 0x110bc
44074 #define A_T7_MPS_BMC_PKT_CNT 0x110bc
44075 #define A_MPS_BMC_MTU 0x110c0
44076 
44077 #define S_MTU    0
44078 #define M_MTU    0x3fffU
44079 #define V_MTU(x) ((x) << S_MTU)
44080 #define G_MTU(x) (((x) >> S_MTU) & M_MTU)
44081 
44082 #define A_T6_MPS_BMC_BYTE_CNT 0x110c0
44083 #define A_T7_MPS_BMC_BYTE_CNT 0x110c0
44084 #define A_MPS_BMC_PKT_CNT 0x110c4
44085 #define A_T6_MPS_PFVF_ATRB_CTL 0x110c4
44086 
44087 #define S_T6_PFVF    0
44088 #define M_T6_PFVF    0x1ffU
44089 #define V_T6_PFVF(x) ((x) << S_T6_PFVF)
44090 #define G_T6_PFVF(x) (((x) >> S_T6_PFVF) & M_T6_PFVF)
44091 
44092 #define A_T7_MPS_PFVF_ATRB_CTL 0x110c4
44093 #define A_MPS_BMC_BYTE_CNT 0x110c8
44094 #define A_T6_MPS_PFVF_ATRB 0x110c8
44095 
44096 #define S_FULL_FRAME_MODE    14
44097 #define V_FULL_FRAME_MODE(x) ((x) << S_FULL_FRAME_MODE)
44098 #define F_FULL_FRAME_MODE    V_FULL_FRAME_MODE(1U)
44099 
44100 #define A_T7_MPS_PFVF_ATRB 0x110c8
44101 
44102 #define S_EXTRACT_DEL_VLAN    31
44103 #define V_EXTRACT_DEL_VLAN(x) ((x) << S_EXTRACT_DEL_VLAN)
44104 #define F_EXTRACT_DEL_VLAN    V_EXTRACT_DEL_VLAN(1U)
44105 
44106 #define A_MPS_PFVF_ATRB_CTL 0x110cc
44107 
44108 #define S_RD_WRN    31
44109 #define V_RD_WRN(x) ((x) << S_RD_WRN)
44110 #define F_RD_WRN    V_RD_WRN(1U)
44111 
44112 #define S_PFVF    0
44113 #define M_PFVF    0xffU
44114 #define V_PFVF(x) ((x) << S_PFVF)
44115 #define G_PFVF(x) (((x) >> S_PFVF) & M_PFVF)
44116 
44117 #define A_T6_MPS_PFVF_ATRB_FLTR0 0x110cc
44118 #define A_T7_MPS_PFVF_ATRB_FLTR0 0x110cc
44119 #define A_MPS_PFVF_ATRB 0x110d0
44120 
44121 #define S_ATTR_PF    28
44122 #define M_ATTR_PF    0x7U
44123 #define V_ATTR_PF(x) ((x) << S_ATTR_PF)
44124 #define G_ATTR_PF(x) (((x) >> S_ATTR_PF) & M_ATTR_PF)
44125 
44126 #define S_OFF    18
44127 #define V_OFF(x) ((x) << S_OFF)
44128 #define F_OFF    V_OFF(1U)
44129 
44130 #define S_NV_DROP    17
44131 #define V_NV_DROP(x) ((x) << S_NV_DROP)
44132 #define F_NV_DROP    V_NV_DROP(1U)
44133 
44134 #define S_ATTR_MODE    16
44135 #define V_ATTR_MODE(x) ((x) << S_ATTR_MODE)
44136 #define F_ATTR_MODE    V_ATTR_MODE(1U)
44137 
44138 #define A_T6_MPS_PFVF_ATRB_FLTR1 0x110d0
44139 #define A_T7_MPS_PFVF_ATRB_FLTR1 0x110d0
44140 #define A_MPS_PFVF_ATRB_FLTR0 0x110d4
44141 
44142 #define S_VLAN_EN    16
44143 #define V_VLAN_EN(x) ((x) << S_VLAN_EN)
44144 #define F_VLAN_EN    V_VLAN_EN(1U)
44145 
44146 #define S_VLAN_ID    0
44147 #define M_VLAN_ID    0xfffU
44148 #define V_VLAN_ID(x) ((x) << S_VLAN_ID)
44149 #define G_VLAN_ID(x) (((x) >> S_VLAN_ID) & M_VLAN_ID)
44150 
44151 #define A_T6_MPS_PFVF_ATRB_FLTR2 0x110d4
44152 #define A_T7_MPS_PFVF_ATRB_FLTR2 0x110d4
44153 #define A_MPS_PFVF_ATRB_FLTR1 0x110d8
44154 #define A_T6_MPS_PFVF_ATRB_FLTR3 0x110d8
44155 #define A_T7_MPS_PFVF_ATRB_FLTR3 0x110d8
44156 #define A_MPS_PFVF_ATRB_FLTR2 0x110dc
44157 #define A_T6_MPS_PFVF_ATRB_FLTR4 0x110dc
44158 #define A_T7_MPS_PFVF_ATRB_FLTR4 0x110dc
44159 #define A_MPS_PFVF_ATRB_FLTR3 0x110e0
44160 #define A_T6_MPS_PFVF_ATRB_FLTR5 0x110e0
44161 #define A_T7_MPS_PFVF_ATRB_FLTR5 0x110e0
44162 #define A_MPS_PFVF_ATRB_FLTR4 0x110e4
44163 #define A_T6_MPS_PFVF_ATRB_FLTR6 0x110e4
44164 #define A_T7_MPS_PFVF_ATRB_FLTR6 0x110e4
44165 #define A_MPS_PFVF_ATRB_FLTR5 0x110e8
44166 #define A_T6_MPS_PFVF_ATRB_FLTR7 0x110e8
44167 #define A_T7_MPS_PFVF_ATRB_FLTR7 0x110e8
44168 #define A_MPS_PFVF_ATRB_FLTR6 0x110ec
44169 #define A_T6_MPS_PFVF_ATRB_FLTR8 0x110ec
44170 #define A_T7_MPS_PFVF_ATRB_FLTR8 0x110ec
44171 #define A_MPS_PFVF_ATRB_FLTR7 0x110f0
44172 #define A_T6_MPS_PFVF_ATRB_FLTR9 0x110f0
44173 #define A_T7_MPS_PFVF_ATRB_FLTR9 0x110f0
44174 #define A_MPS_PFVF_ATRB_FLTR8 0x110f4
44175 #define A_T6_MPS_PFVF_ATRB_FLTR10 0x110f4
44176 #define A_T7_MPS_PFVF_ATRB_FLTR10 0x110f4
44177 #define A_MPS_PFVF_ATRB_FLTR9 0x110f8
44178 #define A_T6_MPS_PFVF_ATRB_FLTR11 0x110f8
44179 #define A_T7_MPS_PFVF_ATRB_FLTR11 0x110f8
44180 #define A_MPS_PFVF_ATRB_FLTR10 0x110fc
44181 #define A_T6_MPS_PFVF_ATRB_FLTR12 0x110fc
44182 #define A_T7_MPS_PFVF_ATRB_FLTR12 0x110fc
44183 #define A_MPS_PFVF_ATRB_FLTR11 0x11100
44184 #define A_T6_MPS_PFVF_ATRB_FLTR13 0x11100
44185 #define A_T7_MPS_PFVF_ATRB_FLTR13 0x11100
44186 #define A_MPS_PFVF_ATRB_FLTR12 0x11104
44187 #define A_T6_MPS_PFVF_ATRB_FLTR14 0x11104
44188 #define A_T7_MPS_PFVF_ATRB_FLTR14 0x11104
44189 #define A_MPS_PFVF_ATRB_FLTR13 0x11108
44190 #define A_T6_MPS_PFVF_ATRB_FLTR15 0x11108
44191 #define A_T7_MPS_PFVF_ATRB_FLTR15 0x11108
44192 #define A_MPS_PFVF_ATRB_FLTR14 0x1110c
44193 #define A_T6_MPS_RPLC_MAP_CTL 0x1110c
44194 #define A_T7_MPS_RPLC_MAP_CTL 0x1110c
44195 
44196 #define S_T7_RPLC_MAP_ADDR    0
44197 #define M_T7_RPLC_MAP_ADDR    0xfffU
44198 #define V_T7_RPLC_MAP_ADDR(x) ((x) << S_T7_RPLC_MAP_ADDR)
44199 #define G_T7_RPLC_MAP_ADDR(x) (((x) >> S_T7_RPLC_MAP_ADDR) & M_T7_RPLC_MAP_ADDR)
44200 
44201 #define A_MPS_PFVF_ATRB_FLTR15 0x11110
44202 #define A_T6_MPS_PF_RPLCT_MAP 0x11110
44203 #define A_T7_MPS_PF_RPLCT_MAP 0x11110
44204 #define A_MPS_RPLC_MAP_CTL 0x11114
44205 
44206 #define S_RPLC_MAP_ADDR    0
44207 #define M_RPLC_MAP_ADDR    0x3ffU
44208 #define V_RPLC_MAP_ADDR(x) ((x) << S_RPLC_MAP_ADDR)
44209 #define G_RPLC_MAP_ADDR(x) (((x) >> S_RPLC_MAP_ADDR) & M_RPLC_MAP_ADDR)
44210 
44211 #define A_T6_MPS_VF_RPLCT_MAP0 0x11114
44212 #define A_T7_MPS_VF_RPLCT_MAP0 0x11114
44213 #define A_MPS_PF_RPLCT_MAP 0x11118
44214 
44215 #define S_PF_EN    0
44216 #define M_PF_EN    0xffU
44217 #define V_PF_EN(x) ((x) << S_PF_EN)
44218 #define G_PF_EN(x) (((x) >> S_PF_EN) & M_PF_EN)
44219 
44220 #define A_T6_MPS_VF_RPLCT_MAP1 0x11118
44221 #define A_T7_MPS_VF_RPLCT_MAP1 0x11118
44222 #define A_MPS_VF_RPLCT_MAP0 0x1111c
44223 #define A_T6_MPS_VF_RPLCT_MAP2 0x1111c
44224 #define A_T7_MPS_VF_RPLCT_MAP2 0x1111c
44225 #define A_MPS_VF_RPLCT_MAP1 0x11120
44226 #define A_T6_MPS_VF_RPLCT_MAP3 0x11120
44227 #define A_T7_MPS_VF_RPLCT_MAP3 0x11120
44228 #define A_MPS_VF_RPLCT_MAP2 0x11124
44229 #define A_MPS_VF_RPLCT_MAP3 0x11128
44230 #define A_MPS_MEM_DBG_CTL 0x1112c
44231 
44232 #define S_PKD    17
44233 #define V_PKD(x) ((x) << S_PKD)
44234 #define F_PKD    V_PKD(1U)
44235 
44236 #define S_PGD    16
44237 #define V_PGD(x) ((x) << S_PGD)
44238 #define F_PGD    V_PGD(1U)
44239 
44240 #define A_MPS_PKD_MEM_DATA0 0x11130
44241 #define A_MPS_PKD_MEM_DATA1 0x11134
44242 #define A_MPS_PKD_MEM_DATA2 0x11138
44243 #define A_MPS_PGD_MEM_DATA 0x1113c
44244 #define A_MPS_RX_SE_CNT_ERR 0x11140
44245 
44246 #define S_RX_SE_ERRMAP    0
44247 #define M_RX_SE_ERRMAP    0xfffffU
44248 #define V_RX_SE_ERRMAP(x) ((x) << S_RX_SE_ERRMAP)
44249 #define G_RX_SE_ERRMAP(x) (((x) >> S_RX_SE_ERRMAP) & M_RX_SE_ERRMAP)
44250 
44251 #define A_MPS_RX_SE_CNT_CLR 0x11144
44252 #define A_MPS_RX_SE_CNT_IN0 0x11148
44253 
44254 #define S_SOP_CNT_PM    24
44255 #define M_SOP_CNT_PM    0xffU
44256 #define V_SOP_CNT_PM(x) ((x) << S_SOP_CNT_PM)
44257 #define G_SOP_CNT_PM(x) (((x) >> S_SOP_CNT_PM) & M_SOP_CNT_PM)
44258 
44259 #define S_EOP_CNT_PM    16
44260 #define M_EOP_CNT_PM    0xffU
44261 #define V_EOP_CNT_PM(x) ((x) << S_EOP_CNT_PM)
44262 #define G_EOP_CNT_PM(x) (((x) >> S_EOP_CNT_PM) & M_EOP_CNT_PM)
44263 
44264 #define S_SOP_CNT_IN    8
44265 #define M_SOP_CNT_IN    0xffU
44266 #define V_SOP_CNT_IN(x) ((x) << S_SOP_CNT_IN)
44267 #define G_SOP_CNT_IN(x) (((x) >> S_SOP_CNT_IN) & M_SOP_CNT_IN)
44268 
44269 #define S_EOP_CNT_IN    0
44270 #define M_EOP_CNT_IN    0xffU
44271 #define V_EOP_CNT_IN(x) ((x) << S_EOP_CNT_IN)
44272 #define G_EOP_CNT_IN(x) (((x) >> S_EOP_CNT_IN) & M_EOP_CNT_IN)
44273 
44274 #define A_MPS_RX_SE_CNT_IN1 0x1114c
44275 #define A_MPS_RX_SE_CNT_IN2 0x11150
44276 #define A_MPS_RX_SE_CNT_IN3 0x11154
44277 #define A_MPS_RX_SE_CNT_IN4 0x11158
44278 #define A_MPS_RX_SE_CNT_IN5 0x1115c
44279 #define A_MPS_RX_SE_CNT_IN6 0x11160
44280 #define A_MPS_RX_SE_CNT_IN7 0x11164
44281 #define A_MPS_RX_SE_CNT_OUT01 0x11168
44282 
44283 #define S_SOP_CNT_1    24
44284 #define M_SOP_CNT_1    0xffU
44285 #define V_SOP_CNT_1(x) ((x) << S_SOP_CNT_1)
44286 #define G_SOP_CNT_1(x) (((x) >> S_SOP_CNT_1) & M_SOP_CNT_1)
44287 
44288 #define S_EOP_CNT_1    16
44289 #define M_EOP_CNT_1    0xffU
44290 #define V_EOP_CNT_1(x) ((x) << S_EOP_CNT_1)
44291 #define G_EOP_CNT_1(x) (((x) >> S_EOP_CNT_1) & M_EOP_CNT_1)
44292 
44293 #define S_SOP_CNT_0    8
44294 #define M_SOP_CNT_0    0xffU
44295 #define V_SOP_CNT_0(x) ((x) << S_SOP_CNT_0)
44296 #define G_SOP_CNT_0(x) (((x) >> S_SOP_CNT_0) & M_SOP_CNT_0)
44297 
44298 #define S_EOP_CNT_0    0
44299 #define M_EOP_CNT_0    0xffU
44300 #define V_EOP_CNT_0(x) ((x) << S_EOP_CNT_0)
44301 #define G_EOP_CNT_0(x) (((x) >> S_EOP_CNT_0) & M_EOP_CNT_0)
44302 
44303 #define A_MPS_RX_SE_CNT_OUT23 0x1116c
44304 
44305 #define S_SOP_CNT_3    24
44306 #define M_SOP_CNT_3    0xffU
44307 #define V_SOP_CNT_3(x) ((x) << S_SOP_CNT_3)
44308 #define G_SOP_CNT_3(x) (((x) >> S_SOP_CNT_3) & M_SOP_CNT_3)
44309 
44310 #define S_EOP_CNT_3    16
44311 #define M_EOP_CNT_3    0xffU
44312 #define V_EOP_CNT_3(x) ((x) << S_EOP_CNT_3)
44313 #define G_EOP_CNT_3(x) (((x) >> S_EOP_CNT_3) & M_EOP_CNT_3)
44314 
44315 #define S_SOP_CNT_2    8
44316 #define M_SOP_CNT_2    0xffU
44317 #define V_SOP_CNT_2(x) ((x) << S_SOP_CNT_2)
44318 #define G_SOP_CNT_2(x) (((x) >> S_SOP_CNT_2) & M_SOP_CNT_2)
44319 
44320 #define S_EOP_CNT_2    0
44321 #define M_EOP_CNT_2    0xffU
44322 #define V_EOP_CNT_2(x) ((x) << S_EOP_CNT_2)
44323 #define G_EOP_CNT_2(x) (((x) >> S_EOP_CNT_2) & M_EOP_CNT_2)
44324 
44325 #define A_MPS_RX_SPI_ERR 0x11170
44326 
44327 #define S_LENERR    21
44328 #define M_LENERR    0xfU
44329 #define V_LENERR(x) ((x) << S_LENERR)
44330 #define G_LENERR(x) (((x) >> S_LENERR) & M_LENERR)
44331 
44332 #define S_SPIERR    0
44333 #define M_SPIERR    0x1fffffU
44334 #define V_SPIERR(x) ((x) << S_SPIERR)
44335 #define G_SPIERR(x) (((x) >> S_SPIERR) & M_SPIERR)
44336 
44337 #define A_MPS_RX_IN_BUS_STATE 0x11174
44338 
44339 #define S_ST3    24
44340 #define M_ST3    0xffU
44341 #define V_ST3(x) ((x) << S_ST3)
44342 #define G_ST3(x) (((x) >> S_ST3) & M_ST3)
44343 
44344 #define S_ST2    16
44345 #define M_ST2    0xffU
44346 #define V_ST2(x) ((x) << S_ST2)
44347 #define G_ST2(x) (((x) >> S_ST2) & M_ST2)
44348 
44349 #define S_ST1    8
44350 #define M_ST1    0xffU
44351 #define V_ST1(x) ((x) << S_ST1)
44352 #define G_ST1(x) (((x) >> S_ST1) & M_ST1)
44353 
44354 #define S_ST0    0
44355 #define M_ST0    0xffU
44356 #define V_ST0(x) ((x) << S_ST0)
44357 #define G_ST0(x) (((x) >> S_ST0) & M_ST0)
44358 
44359 #define A_MPS_RX_OUT_BUS_STATE 0x11178
44360 
44361 #define S_ST_NCSI    23
44362 #define M_ST_NCSI    0x1ffU
44363 #define V_ST_NCSI(x) ((x) << S_ST_NCSI)
44364 #define G_ST_NCSI(x) (((x) >> S_ST_NCSI) & M_ST_NCSI)
44365 
44366 #define S_ST_TP    0
44367 #define M_ST_TP    0x7fffffU
44368 #define V_ST_TP(x) ((x) << S_ST_TP)
44369 #define G_ST_TP(x) (((x) >> S_ST_TP) & M_ST_TP)
44370 
44371 #define A_MPS_RX_DBG_CTL 0x1117c
44372 
44373 #define S_OUT_DBG_CHNL    8
44374 #define M_OUT_DBG_CHNL    0x7U
44375 #define V_OUT_DBG_CHNL(x) ((x) << S_OUT_DBG_CHNL)
44376 #define G_OUT_DBG_CHNL(x) (((x) >> S_OUT_DBG_CHNL) & M_OUT_DBG_CHNL)
44377 
44378 #define S_DBG_PKD_QSEL    7
44379 #define V_DBG_PKD_QSEL(x) ((x) << S_DBG_PKD_QSEL)
44380 #define F_DBG_PKD_QSEL    V_DBG_PKD_QSEL(1U)
44381 
44382 #define S_DBG_CDS_INV    6
44383 #define V_DBG_CDS_INV(x) ((x) << S_DBG_CDS_INV)
44384 #define F_DBG_CDS_INV    V_DBG_CDS_INV(1U)
44385 
44386 #define S_IN_DBG_PORT    3
44387 #define M_IN_DBG_PORT    0x7U
44388 #define V_IN_DBG_PORT(x) ((x) << S_IN_DBG_PORT)
44389 #define G_IN_DBG_PORT(x) (((x) >> S_IN_DBG_PORT) & M_IN_DBG_PORT)
44390 
44391 #define S_IN_DBG_CHNL    0
44392 #define M_IN_DBG_CHNL    0x7U
44393 #define V_IN_DBG_CHNL(x) ((x) << S_IN_DBG_CHNL)
44394 #define G_IN_DBG_CHNL(x) (((x) >> S_IN_DBG_CHNL) & M_IN_DBG_CHNL)
44395 
44396 #define A_MPS_RX_CLS_DROP_CNT0 0x11180
44397 
44398 #define S_LPBK_CNT0    16
44399 #define M_LPBK_CNT0    0xffffU
44400 #define V_LPBK_CNT0(x) ((x) << S_LPBK_CNT0)
44401 #define G_LPBK_CNT0(x) (((x) >> S_LPBK_CNT0) & M_LPBK_CNT0)
44402 
44403 #define S_MAC_CNT0    0
44404 #define M_MAC_CNT0    0xffffU
44405 #define V_MAC_CNT0(x) ((x) << S_MAC_CNT0)
44406 #define G_MAC_CNT0(x) (((x) >> S_MAC_CNT0) & M_MAC_CNT0)
44407 
44408 #define A_MPS_RX_CLS_DROP_CNT1 0x11184
44409 
44410 #define S_LPBK_CNT1    16
44411 #define M_LPBK_CNT1    0xffffU
44412 #define V_LPBK_CNT1(x) ((x) << S_LPBK_CNT1)
44413 #define G_LPBK_CNT1(x) (((x) >> S_LPBK_CNT1) & M_LPBK_CNT1)
44414 
44415 #define S_MAC_CNT1    0
44416 #define M_MAC_CNT1    0xffffU
44417 #define V_MAC_CNT1(x) ((x) << S_MAC_CNT1)
44418 #define G_MAC_CNT1(x) (((x) >> S_MAC_CNT1) & M_MAC_CNT1)
44419 
44420 #define A_MPS_RX_CLS_DROP_CNT2 0x11188
44421 
44422 #define S_LPBK_CNT2    16
44423 #define M_LPBK_CNT2    0xffffU
44424 #define V_LPBK_CNT2(x) ((x) << S_LPBK_CNT2)
44425 #define G_LPBK_CNT2(x) (((x) >> S_LPBK_CNT2) & M_LPBK_CNT2)
44426 
44427 #define S_MAC_CNT2    0
44428 #define M_MAC_CNT2    0xffffU
44429 #define V_MAC_CNT2(x) ((x) << S_MAC_CNT2)
44430 #define G_MAC_CNT2(x) (((x) >> S_MAC_CNT2) & M_MAC_CNT2)
44431 
44432 #define A_MPS_RX_CLS_DROP_CNT3 0x1118c
44433 
44434 #define S_LPBK_CNT3    16
44435 #define M_LPBK_CNT3    0xffffU
44436 #define V_LPBK_CNT3(x) ((x) << S_LPBK_CNT3)
44437 #define G_LPBK_CNT3(x) (((x) >> S_LPBK_CNT3) & M_LPBK_CNT3)
44438 
44439 #define S_MAC_CNT3    0
44440 #define M_MAC_CNT3    0xffffU
44441 #define V_MAC_CNT3(x) ((x) << S_MAC_CNT3)
44442 #define G_MAC_CNT3(x) (((x) >> S_MAC_CNT3) & M_MAC_CNT3)
44443 
44444 #define A_MPS_RX_SPARE 0x11190
44445 #define A_MPS_RX_PTP_ETYPE 0x11194
44446 
44447 #define S_PETYPE2    16
44448 #define M_PETYPE2    0xffffU
44449 #define V_PETYPE2(x) ((x) << S_PETYPE2)
44450 #define G_PETYPE2(x) (((x) >> S_PETYPE2) & M_PETYPE2)
44451 
44452 #define S_PETYPE1    0
44453 #define M_PETYPE1    0xffffU
44454 #define V_PETYPE1(x) ((x) << S_PETYPE1)
44455 #define G_PETYPE1(x) (((x) >> S_PETYPE1) & M_PETYPE1)
44456 
44457 #define A_MPS_RX_PTP_TCP 0x11198
44458 
44459 #define S_PTCPORT2    16
44460 #define M_PTCPORT2    0xffffU
44461 #define V_PTCPORT2(x) ((x) << S_PTCPORT2)
44462 #define G_PTCPORT2(x) (((x) >> S_PTCPORT2) & M_PTCPORT2)
44463 
44464 #define S_PTCPORT1    0
44465 #define M_PTCPORT1    0xffffU
44466 #define V_PTCPORT1(x) ((x) << S_PTCPORT1)
44467 #define G_PTCPORT1(x) (((x) >> S_PTCPORT1) & M_PTCPORT1)
44468 
44469 #define A_MPS_RX_PTP_UDP 0x1119c
44470 
44471 #define S_PUDPORT2    16
44472 #define M_PUDPORT2    0xffffU
44473 #define V_PUDPORT2(x) ((x) << S_PUDPORT2)
44474 #define G_PUDPORT2(x) (((x) >> S_PUDPORT2) & M_PUDPORT2)
44475 
44476 #define S_PUDPORT1    0
44477 #define M_PUDPORT1    0xffffU
44478 #define V_PUDPORT1(x) ((x) << S_PUDPORT1)
44479 #define G_PUDPORT1(x) (((x) >> S_PUDPORT1) & M_PUDPORT1)
44480 
44481 #define A_MPS_RX_PTP_CTL 0x111a0
44482 
44483 #define S_MIN_PTP_SPACE    24
44484 #define M_MIN_PTP_SPACE    0x7fU
44485 #define V_MIN_PTP_SPACE(x) ((x) << S_MIN_PTP_SPACE)
44486 #define G_MIN_PTP_SPACE(x) (((x) >> S_MIN_PTP_SPACE) & M_MIN_PTP_SPACE)
44487 
44488 #define S_PUDP2EN    20
44489 #define M_PUDP2EN    0xfU
44490 #define V_PUDP2EN(x) ((x) << S_PUDP2EN)
44491 #define G_PUDP2EN(x) (((x) >> S_PUDP2EN) & M_PUDP2EN)
44492 
44493 #define S_PUDP1EN    16
44494 #define M_PUDP1EN    0xfU
44495 #define V_PUDP1EN(x) ((x) << S_PUDP1EN)
44496 #define G_PUDP1EN(x) (((x) >> S_PUDP1EN) & M_PUDP1EN)
44497 
44498 #define S_PTCP2EN    12
44499 #define M_PTCP2EN    0xfU
44500 #define V_PTCP2EN(x) ((x) << S_PTCP2EN)
44501 #define G_PTCP2EN(x) (((x) >> S_PTCP2EN) & M_PTCP2EN)
44502 
44503 #define S_PTCP1EN    8
44504 #define M_PTCP1EN    0xfU
44505 #define V_PTCP1EN(x) ((x) << S_PTCP1EN)
44506 #define G_PTCP1EN(x) (((x) >> S_PTCP1EN) & M_PTCP1EN)
44507 
44508 #define S_PETYPE2EN    4
44509 #define M_PETYPE2EN    0xfU
44510 #define V_PETYPE2EN(x) ((x) << S_PETYPE2EN)
44511 #define G_PETYPE2EN(x) (((x) >> S_PETYPE2EN) & M_PETYPE2EN)
44512 
44513 #define S_PETYPE1EN    0
44514 #define M_PETYPE1EN    0xfU
44515 #define V_PETYPE1EN(x) ((x) << S_PETYPE1EN)
44516 #define G_PETYPE1EN(x) (((x) >> S_PETYPE1EN) & M_PETYPE1EN)
44517 
44518 #define A_MPS_RX_PAUSE_GEN_TH_0_0 0x111a4
44519 #define A_MPS_RX_PAUSE_GEN_TH_0_1 0x111a8
44520 #define A_MPS_RX_PAUSE_GEN_TH_0_2 0x111ac
44521 #define A_MPS_RX_PAUSE_GEN_TH_0_3 0x111b0
44522 #define A_MPS_RX_PAUSE_GEN_TH_1_0 0x111b4
44523 #define A_MPS_RX_PAUSE_GEN_TH_1_1 0x111b8
44524 #define A_MPS_RX_PAUSE_GEN_TH_1_2 0x111bc
44525 #define A_MPS_RX_PAUSE_GEN_TH_1_3 0x111c0
44526 #define A_MPS_RX_PAUSE_GEN_TH_2_0 0x111c4
44527 #define A_MPS_RX_PAUSE_GEN_TH_2_1 0x111c8
44528 #define A_MPS_RX_PAUSE_GEN_TH_2_2 0x111cc
44529 #define A_MPS_RX_PAUSE_GEN_TH_2_3 0x111d0
44530 #define A_MPS_RX_PAUSE_GEN_TH_3_0 0x111d4
44531 #define A_MPS_RX_PAUSE_GEN_TH_3_1 0x111d8
44532 #define A_MPS_RX_PAUSE_GEN_TH_3_2 0x111dc
44533 #define A_MPS_RX_PAUSE_GEN_TH_3_3 0x111e0
44534 #define A_MPS_RX_MAC_CLS_DROP_CNT0 0x111e4
44535 #define A_MPS_RX_MAC_CLS_DROP_CNT1 0x111e8
44536 #define A_MPS_RX_MAC_CLS_DROP_CNT2 0x111ec
44537 #define A_MPS_RX_MAC_CLS_DROP_CNT3 0x111f0
44538 #define A_MPS_RX_LPBK_CLS_DROP_CNT0 0x111f4
44539 #define A_MPS_RX_LPBK_CLS_DROP_CNT1 0x111f8
44540 #define A_MPS_RX_LPBK_CLS_DROP_CNT2 0x111fc
44541 #define A_MPS_RX_LPBK_CLS_DROP_CNT3 0x11200
44542 #define A_MPS_RX_CGEN 0x11204
44543 
44544 #define S_MPS_RX_CGEN_NCSI    12
44545 #define V_MPS_RX_CGEN_NCSI(x) ((x) << S_MPS_RX_CGEN_NCSI)
44546 #define F_MPS_RX_CGEN_NCSI    V_MPS_RX_CGEN_NCSI(1U)
44547 
44548 #define S_MPS_RX_CGEN_OUT    8
44549 #define M_MPS_RX_CGEN_OUT    0xfU
44550 #define V_MPS_RX_CGEN_OUT(x) ((x) << S_MPS_RX_CGEN_OUT)
44551 #define G_MPS_RX_CGEN_OUT(x) (((x) >> S_MPS_RX_CGEN_OUT) & M_MPS_RX_CGEN_OUT)
44552 
44553 #define S_MPS_RX_CGEN_LPBK_IN    4
44554 #define M_MPS_RX_CGEN_LPBK_IN    0xfU
44555 #define V_MPS_RX_CGEN_LPBK_IN(x) ((x) << S_MPS_RX_CGEN_LPBK_IN)
44556 #define G_MPS_RX_CGEN_LPBK_IN(x) (((x) >> S_MPS_RX_CGEN_LPBK_IN) & M_MPS_RX_CGEN_LPBK_IN)
44557 
44558 #define S_MPS_RX_CGEN_MAC_IN    0
44559 #define M_MPS_RX_CGEN_MAC_IN    0xfU
44560 #define V_MPS_RX_CGEN_MAC_IN(x) ((x) << S_MPS_RX_CGEN_MAC_IN)
44561 #define G_MPS_RX_CGEN_MAC_IN(x) (((x) >> S_MPS_RX_CGEN_MAC_IN) & M_MPS_RX_CGEN_MAC_IN)
44562 
44563 #define A_MPS_RX_MAC_BG_PG_CNT0 0x11208
44564 
44565 #define S_MAC_USED    16
44566 #define M_MAC_USED    0x7ffU
44567 #define V_MAC_USED(x) ((x) << S_MAC_USED)
44568 #define G_MAC_USED(x) (((x) >> S_MAC_USED) & M_MAC_USED)
44569 
44570 #define S_MAC_ALLOC    0
44571 #define M_MAC_ALLOC    0x7ffU
44572 #define V_MAC_ALLOC(x) ((x) << S_MAC_ALLOC)
44573 #define G_MAC_ALLOC(x) (((x) >> S_MAC_ALLOC) & M_MAC_ALLOC)
44574 
44575 #define A_MPS_RX_MAC_BG_PG_CNT1 0x1120c
44576 #define A_MPS_RX_MAC_BG_PG_CNT2 0x11210
44577 #define A_MPS_RX_MAC_BG_PG_CNT3 0x11214
44578 #define A_MPS_RX_LPBK_BG_PG_CNT0 0x11218
44579 
44580 #define S_LPBK_USED    16
44581 #define M_LPBK_USED    0x7ffU
44582 #define V_LPBK_USED(x) ((x) << S_LPBK_USED)
44583 #define G_LPBK_USED(x) (((x) >> S_LPBK_USED) & M_LPBK_USED)
44584 
44585 #define S_LPBK_ALLOC    0
44586 #define M_LPBK_ALLOC    0x7ffU
44587 #define V_LPBK_ALLOC(x) ((x) << S_LPBK_ALLOC)
44588 #define G_LPBK_ALLOC(x) (((x) >> S_LPBK_ALLOC) & M_LPBK_ALLOC)
44589 
44590 #define A_MPS_RX_LPBK_BG_PG_CNT1 0x1121c
44591 #define A_MPS_RX_CONGESTION_THRESHOLD_BG0 0x11220
44592 
44593 #define S_CONG_EN    31
44594 #define V_CONG_EN(x) ((x) << S_CONG_EN)
44595 #define F_CONG_EN    V_CONG_EN(1U)
44596 
44597 #define S_CONG_TH    0
44598 #define M_CONG_TH    0xfffffU
44599 #define V_CONG_TH(x) ((x) << S_CONG_TH)
44600 #define G_CONG_TH(x) (((x) >> S_CONG_TH) & M_CONG_TH)
44601 
44602 #define A_MPS_RX_LPBK_BG_PG_CNT2 0x11220
44603 #define A_MPS_RX_CONGESTION_THRESHOLD_BG1 0x11224
44604 #define A_MPS_RX_LPBK_BG_PG_CNT3 0x11224
44605 #define A_MPS_RX_CONGESTION_THRESHOLD_BG2 0x11228
44606 #define A_T7_MPS_RX_CONGESTION_THRESHOLD_BG0 0x11228
44607 #define A_MPS_RX_CONGESTION_THRESHOLD_BG3 0x1122c
44608 #define A_T7_MPS_RX_CONGESTION_THRESHOLD_BG1 0x1122c
44609 #define A_MPS_RX_GRE_PROT_TYPE 0x11230
44610 
44611 #define S_NVGRE_EN    9
44612 #define V_NVGRE_EN(x) ((x) << S_NVGRE_EN)
44613 #define F_NVGRE_EN    V_NVGRE_EN(1U)
44614 
44615 #define S_GRE_EN    8
44616 #define V_GRE_EN(x) ((x) << S_GRE_EN)
44617 #define F_GRE_EN    V_GRE_EN(1U)
44618 
44619 #define S_GRE    0
44620 #define M_GRE    0xffU
44621 #define V_GRE(x) ((x) << S_GRE)
44622 #define G_GRE(x) (((x) >> S_GRE) & M_GRE)
44623 
44624 #define A_T7_MPS_RX_CONGESTION_THRESHOLD_BG2 0x11230
44625 #define A_MPS_RX_VXLAN_TYPE 0x11234
44626 
44627 #define S_VXLAN_EN    16
44628 #define V_VXLAN_EN(x) ((x) << S_VXLAN_EN)
44629 #define F_VXLAN_EN    V_VXLAN_EN(1U)
44630 
44631 #define S_VXLAN    0
44632 #define M_VXLAN    0xffffU
44633 #define V_VXLAN(x) ((x) << S_VXLAN)
44634 #define G_VXLAN(x) (((x) >> S_VXLAN) & M_VXLAN)
44635 
44636 #define A_T7_MPS_RX_CONGESTION_THRESHOLD_BG3 0x11234
44637 #define A_MPS_RX_GENEVE_TYPE 0x11238
44638 
44639 #define S_GENEVE_EN    16
44640 #define V_GENEVE_EN(x) ((x) << S_GENEVE_EN)
44641 #define F_GENEVE_EN    V_GENEVE_EN(1U)
44642 
44643 #define S_GENEVE    0
44644 #define M_GENEVE    0xffffU
44645 #define V_GENEVE(x) ((x) << S_GENEVE)
44646 #define G_GENEVE(x) (((x) >> S_GENEVE) & M_GENEVE)
44647 
44648 #define A_T7_MPS_RX_GRE_PROT_TYPE 0x11238
44649 #define A_MPS_RX_INNER_HDR_IVLAN 0x1123c
44650 
44651 #define S_T6_IVLAN_EN    16
44652 #define V_T6_IVLAN_EN(x) ((x) << S_T6_IVLAN_EN)
44653 #define F_T6_IVLAN_EN    V_T6_IVLAN_EN(1U)
44654 
44655 #define A_T7_MPS_RX_VXLAN_TYPE 0x1123c
44656 #define A_MPS_RX_ENCAP_NVGRE 0x11240
44657 
44658 #define S_ETYPE_EN    16
44659 #define V_ETYPE_EN(x) ((x) << S_ETYPE_EN)
44660 #define F_ETYPE_EN    V_ETYPE_EN(1U)
44661 
44662 #define S_T6_ETYPE    0
44663 #define M_T6_ETYPE    0xffffU
44664 #define V_T6_ETYPE(x) ((x) << S_T6_ETYPE)
44665 #define G_T6_ETYPE(x) (((x) >> S_T6_ETYPE) & M_T6_ETYPE)
44666 
44667 #define A_T7_MPS_RX_GENEVE_TYPE 0x11240
44668 #define A_MPS_RX_ENCAP_GENEVE 0x11244
44669 #define A_T7_MPS_RX_INNER_HDR_IVLAN 0x11244
44670 #define A_MPS_RX_TCP 0x11248
44671 
44672 #define S_PROT_TYPE_EN    8
44673 #define V_PROT_TYPE_EN(x) ((x) << S_PROT_TYPE_EN)
44674 #define F_PROT_TYPE_EN    V_PROT_TYPE_EN(1U)
44675 
44676 #define S_PROT_TYPE    0
44677 #define M_PROT_TYPE    0xffU
44678 #define V_PROT_TYPE(x) ((x) << S_PROT_TYPE)
44679 #define G_PROT_TYPE(x) (((x) >> S_PROT_TYPE) & M_PROT_TYPE)
44680 
44681 #define A_T7_MPS_RX_ENCAP_NVGRE 0x11248
44682 #define A_MPS_RX_UDP 0x1124c
44683 #define A_T7_MPS_RX_ENCAP_GENEVE 0x1124c
44684 #define A_MPS_RX_PAUSE 0x11250
44685 #define A_T7_MPS_RX_TCP 0x11250
44686 #define A_MPS_RX_LENGTH 0x11254
44687 
44688 #define S_SAP_VALUE    16
44689 #define M_SAP_VALUE    0xffffU
44690 #define V_SAP_VALUE(x) ((x) << S_SAP_VALUE)
44691 #define G_SAP_VALUE(x) (((x) >> S_SAP_VALUE) & M_SAP_VALUE)
44692 
44693 #define S_LENGTH_ETYPE    0
44694 #define M_LENGTH_ETYPE    0xffffU
44695 #define V_LENGTH_ETYPE(x) ((x) << S_LENGTH_ETYPE)
44696 #define G_LENGTH_ETYPE(x) (((x) >> S_LENGTH_ETYPE) & M_LENGTH_ETYPE)
44697 
44698 #define A_T7_MPS_RX_UDP 0x11254
44699 #define A_MPS_RX_CTL_ORG 0x11258
44700 
44701 #define S_CTL_VALUE    24
44702 #define M_CTL_VALUE    0xffU
44703 #define V_CTL_VALUE(x) ((x) << S_CTL_VALUE)
44704 #define G_CTL_VALUE(x) (((x) >> S_CTL_VALUE) & M_CTL_VALUE)
44705 
44706 #define S_ORG_VALUE    0
44707 #define M_ORG_VALUE    0xffffffU
44708 #define V_ORG_VALUE(x) ((x) << S_ORG_VALUE)
44709 #define G_ORG_VALUE(x) (((x) >> S_ORG_VALUE) & M_ORG_VALUE)
44710 
44711 #define A_T7_MPS_RX_PAUSE 0x11258
44712 #define A_MPS_RX_IPV4 0x1125c
44713 
44714 #define S_ETYPE_IPV4    0
44715 #define M_ETYPE_IPV4    0xffffU
44716 #define V_ETYPE_IPV4(x) ((x) << S_ETYPE_IPV4)
44717 #define G_ETYPE_IPV4(x) (((x) >> S_ETYPE_IPV4) & M_ETYPE_IPV4)
44718 
44719 #define A_T7_MPS_RX_LENGTH 0x1125c
44720 #define A_MPS_RX_IPV6 0x11260
44721 
44722 #define S_ETYPE_IPV6    0
44723 #define M_ETYPE_IPV6    0xffffU
44724 #define V_ETYPE_IPV6(x) ((x) << S_ETYPE_IPV6)
44725 #define G_ETYPE_IPV6(x) (((x) >> S_ETYPE_IPV6) & M_ETYPE_IPV6)
44726 
44727 #define A_T7_MPS_RX_CTL_ORG 0x11260
44728 #define A_MPS_RX_TTL 0x11264
44729 
44730 #define S_TTL_IPV4    10
44731 #define M_TTL_IPV4    0xffU
44732 #define V_TTL_IPV4(x) ((x) << S_TTL_IPV4)
44733 #define G_TTL_IPV4(x) (((x) >> S_TTL_IPV4) & M_TTL_IPV4)
44734 
44735 #define S_TTL_IPV6    2
44736 #define M_TTL_IPV6    0xffU
44737 #define V_TTL_IPV6(x) ((x) << S_TTL_IPV6)
44738 #define G_TTL_IPV6(x) (((x) >> S_TTL_IPV6) & M_TTL_IPV6)
44739 
44740 #define S_TTL_CHK_EN_IPV4    1
44741 #define V_TTL_CHK_EN_IPV4(x) ((x) << S_TTL_CHK_EN_IPV4)
44742 #define F_TTL_CHK_EN_IPV4    V_TTL_CHK_EN_IPV4(1U)
44743 
44744 #define S_TTL_CHK_EN_IPV6    0
44745 #define V_TTL_CHK_EN_IPV6(x) ((x) << S_TTL_CHK_EN_IPV6)
44746 #define F_TTL_CHK_EN_IPV6    V_TTL_CHK_EN_IPV6(1U)
44747 
44748 #define A_T7_MPS_RX_IPV4 0x11264
44749 #define A_MPS_RX_DEFAULT_VNI 0x11268
44750 
44751 #define S_VNI    0
44752 #define M_VNI    0xffffffU
44753 #define V_VNI(x) ((x) << S_VNI)
44754 #define G_VNI(x) (((x) >> S_VNI) & M_VNI)
44755 
44756 #define A_T7_MPS_RX_IPV6 0x11268
44757 #define A_MPS_RX_PRS_CTL 0x1126c
44758 
44759 #define S_CTL_CHK_EN    28
44760 #define V_CTL_CHK_EN(x) ((x) << S_CTL_CHK_EN)
44761 #define F_CTL_CHK_EN    V_CTL_CHK_EN(1U)
44762 
44763 #define S_ORG_CHK_EN    27
44764 #define V_ORG_CHK_EN(x) ((x) << S_ORG_CHK_EN)
44765 #define F_ORG_CHK_EN    V_ORG_CHK_EN(1U)
44766 
44767 #define S_SAP_CHK_EN    26
44768 #define V_SAP_CHK_EN(x) ((x) << S_SAP_CHK_EN)
44769 #define F_SAP_CHK_EN    V_SAP_CHK_EN(1U)
44770 
44771 #define S_VXLAN_FLAG_CHK_EN    25
44772 #define V_VXLAN_FLAG_CHK_EN(x) ((x) << S_VXLAN_FLAG_CHK_EN)
44773 #define F_VXLAN_FLAG_CHK_EN    V_VXLAN_FLAG_CHK_EN(1U)
44774 
44775 #define S_VXLAN_FLAG_MASK    17
44776 #define M_VXLAN_FLAG_MASK    0xffU
44777 #define V_VXLAN_FLAG_MASK(x) ((x) << S_VXLAN_FLAG_MASK)
44778 #define G_VXLAN_FLAG_MASK(x) (((x) >> S_VXLAN_FLAG_MASK) & M_VXLAN_FLAG_MASK)
44779 
44780 #define S_VXLAN_FLAG    9
44781 #define M_VXLAN_FLAG    0xffU
44782 #define V_VXLAN_FLAG(x) ((x) << S_VXLAN_FLAG)
44783 #define G_VXLAN_FLAG(x) (((x) >> S_VXLAN_FLAG) & M_VXLAN_FLAG)
44784 
44785 #define S_GRE_VER_CHK_EN    8
44786 #define V_GRE_VER_CHK_EN(x) ((x) << S_GRE_VER_CHK_EN)
44787 #define F_GRE_VER_CHK_EN    V_GRE_VER_CHK_EN(1U)
44788 
44789 #define S_GRE_VER    5
44790 #define M_GRE_VER    0x7U
44791 #define V_GRE_VER(x) ((x) << S_GRE_VER)
44792 #define G_GRE_VER(x) (((x) >> S_GRE_VER) & M_GRE_VER)
44793 
44794 #define S_GENEVE_VER_CHK_EN    4
44795 #define V_GENEVE_VER_CHK_EN(x) ((x) << S_GENEVE_VER_CHK_EN)
44796 #define F_GENEVE_VER_CHK_EN    V_GENEVE_VER_CHK_EN(1U)
44797 
44798 #define S_GENEVE_VER    2
44799 #define M_GENEVE_VER    0x3U
44800 #define V_GENEVE_VER(x) ((x) << S_GENEVE_VER)
44801 #define G_GENEVE_VER(x) (((x) >> S_GENEVE_VER) & M_GENEVE_VER)
44802 
44803 #define S_DIP_EN    1
44804 #define V_DIP_EN(x) ((x) << S_DIP_EN)
44805 #define F_DIP_EN    V_DIP_EN(1U)
44806 
44807 #define A_T7_MPS_RX_TTL 0x1126c
44808 #define A_MPS_RX_PRS_CTL_2 0x11270
44809 
44810 #define S_EN_UDP_CSUM_CHK    4
44811 #define V_EN_UDP_CSUM_CHK(x) ((x) << S_EN_UDP_CSUM_CHK)
44812 #define F_EN_UDP_CSUM_CHK    V_EN_UDP_CSUM_CHK(1U)
44813 
44814 #define S_EN_UDP_LEN_CHK    3
44815 #define V_EN_UDP_LEN_CHK(x) ((x) << S_EN_UDP_LEN_CHK)
44816 #define F_EN_UDP_LEN_CHK    V_EN_UDP_LEN_CHK(1U)
44817 
44818 #define S_EN_IP_CSUM_CHK    2
44819 #define V_EN_IP_CSUM_CHK(x) ((x) << S_EN_IP_CSUM_CHK)
44820 #define F_EN_IP_CSUM_CHK    V_EN_IP_CSUM_CHK(1U)
44821 
44822 #define S_EN_IP_PAYLOAD_LEN_CHK    1
44823 #define V_EN_IP_PAYLOAD_LEN_CHK(x) ((x) << S_EN_IP_PAYLOAD_LEN_CHK)
44824 #define F_EN_IP_PAYLOAD_LEN_CHK    V_EN_IP_PAYLOAD_LEN_CHK(1U)
44825 
44826 #define S_T6_IPV6_UDP_CSUM_COMPAT    0
44827 #define V_T6_IPV6_UDP_CSUM_COMPAT(x) ((x) << S_T6_IPV6_UDP_CSUM_COMPAT)
44828 #define F_T6_IPV6_UDP_CSUM_COMPAT    V_T6_IPV6_UDP_CSUM_COMPAT(1U)
44829 
44830 #define A_T7_MPS_RX_DEFAULT_VNI 0x11270
44831 #define A_MPS_RX_MPS2NCSI_CNT 0x11274
44832 #define A_T7_MPS_RX_PRS_CTL 0x11274
44833 #define A_MPS_RX_MAX_TNL_HDR_LEN 0x11278
44834 
44835 #define S_T6_LEN    0
44836 #define M_T6_LEN    0x1ffU
44837 #define V_T6_LEN(x) ((x) << S_T6_LEN)
44838 #define G_T6_LEN(x) (((x) >> S_T6_LEN) & M_T6_LEN)
44839 
44840 #define A_T7_MPS_RX_PRS_CTL_2 0x11278
44841 
44842 #define S_IP_EXT_HDR_EN    5
44843 #define V_IP_EXT_HDR_EN(x) ((x) << S_IP_EXT_HDR_EN)
44844 #define F_IP_EXT_HDR_EN    V_IP_EXT_HDR_EN(1U)
44845 
44846 #define A_MPS_RX_PAUSE_DA_H 0x1127c
44847 #define A_T7_MPS_RX_MPS2NCSI_CNT 0x1127c
44848 #define A_MPS_RX_PAUSE_DA_L 0x11280
44849 #define A_T7_MPS_RX_MAX_TNL_HDR_LEN 0x11280
44850 
44851 #define S_MPS_TNL_HDR_LEN_MODE    9
44852 #define V_MPS_TNL_HDR_LEN_MODE(x) ((x) << S_MPS_TNL_HDR_LEN_MODE)
44853 #define F_MPS_TNL_HDR_LEN_MODE    V_MPS_TNL_HDR_LEN_MODE(1U)
44854 
44855 #define S_MPS_MAX_TNL_HDR_LEN    0
44856 #define M_MPS_MAX_TNL_HDR_LEN    0x1ffU
44857 #define V_MPS_MAX_TNL_HDR_LEN(x) ((x) << S_MPS_MAX_TNL_HDR_LEN)
44858 #define G_MPS_MAX_TNL_HDR_LEN(x) (((x) >> S_MPS_MAX_TNL_HDR_LEN) & M_MPS_MAX_TNL_HDR_LEN)
44859 
44860 #define A_MPS_RX_CNT_NVGRE_PKT_MAC0 0x11284
44861 #define A_T7_MPS_RX_PAUSE_DA_H 0x11284
44862 #define A_MPS_RX_CNT_VXLAN_PKT_MAC0 0x11288
44863 #define A_T7_MPS_RX_PAUSE_DA_L 0x11288
44864 #define A_MPS_RX_CNT_GENEVE_PKT_MAC0 0x1128c
44865 #define A_T7_MPS_RX_CNT_NVGRE_PKT_MAC0 0x1128c
44866 #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC0 0x11290
44867 #define A_T7_MPS_RX_CNT_VXLAN_PKT_MAC0 0x11290
44868 #define A_MPS_RX_CNT_NVGRE_PKT_MAC1 0x11294
44869 #define A_T7_MPS_RX_CNT_GENEVE_PKT_MAC0 0x11294
44870 #define A_MPS_RX_CNT_VXLAN_PKT_MAC1 0x11298
44871 #define A_T7_MPS_RX_CNT_TNL_ERR_PKT_MAC0 0x11298
44872 #define A_MPS_RX_CNT_GENEVE_PKT_MAC1 0x1129c
44873 #define A_T7_MPS_RX_CNT_NVGRE_PKT_MAC1 0x1129c
44874 #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC1 0x112a0
44875 #define A_T7_MPS_RX_CNT_VXLAN_PKT_MAC1 0x112a0
44876 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK0 0x112a4
44877 #define A_T7_MPS_RX_CNT_GENEVE_PKT_MAC1 0x112a4
44878 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK0 0x112a8
44879 #define A_T7_MPS_RX_CNT_TNL_ERR_PKT_MAC1 0x112a8
44880 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK0 0x112ac
44881 #define A_T7_MPS_RX_CNT_NVGRE_PKT_LPBK0 0x112ac
44882 #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK0 0x112b0
44883 #define A_T7_MPS_RX_CNT_VXLAN_PKT_LPBK0 0x112b0
44884 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK1 0x112b4
44885 #define A_T7_MPS_RX_CNT_GENEVE_PKT_LPBK0 0x112b4
44886 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK1 0x112b8
44887 #define A_T7_MPS_RX_CNT_TNL_ERR_PKT_LPBK0 0x112b8
44888 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK1 0x112bc
44889 #define A_T7_MPS_RX_CNT_NVGRE_PKT_LPBK1 0x112bc
44890 #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK1 0x112c0
44891 #define A_T7_MPS_RX_CNT_VXLAN_PKT_LPBK1 0x112c0
44892 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP0 0x112c4
44893 #define A_T7_MPS_RX_CNT_GENEVE_PKT_LPBK1 0x112c4
44894 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP0 0x112c8
44895 #define A_T7_MPS_RX_CNT_TNL_ERR_PKT_LPBK1 0x112c8
44896 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP0 0x112cc
44897 #define A_T7_MPS_RX_CNT_NVGRE_PKT_TO_TP0 0x112cc
44898 #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP0 0x112d0
44899 #define A_T7_MPS_RX_CNT_VXLAN_PKT_TO_TP0 0x112d0
44900 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP1 0x112d4
44901 #define A_T7_MPS_RX_CNT_GENEVE_PKT_TO_TP0 0x112d4
44902 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP1 0x112d8
44903 #define A_T7_MPS_RX_CNT_TNL_ERR_PKT_TO_TP0 0x112d8
44904 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP1 0x112dc
44905 #define A_T7_MPS_RX_CNT_NVGRE_PKT_TO_TP1 0x112dc
44906 #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP1 0x112e0
44907 #define A_T7_MPS_RX_CNT_VXLAN_PKT_TO_TP1 0x112e0
44908 #define A_T7_MPS_RX_CNT_GENEVE_PKT_TO_TP1 0x112e4
44909 #define A_T7_MPS_RX_CNT_TNL_ERR_PKT_TO_TP1 0x112e8
44910 #define A_MPS_RX_ESP 0x112ec
44911 #define A_MPS_EN_LPBK_BLK_SNDR 0x112f0
44912 
44913 #define S_EN_CH3    3
44914 #define V_EN_CH3(x) ((x) << S_EN_CH3)
44915 #define F_EN_CH3    V_EN_CH3(1U)
44916 
44917 #define S_EN_CH2    2
44918 #define V_EN_CH2(x) ((x) << S_EN_CH2)
44919 #define F_EN_CH2    V_EN_CH2(1U)
44920 
44921 #define S_EN_CH1    1
44922 #define V_EN_CH1(x) ((x) << S_EN_CH1)
44923 #define F_EN_CH1    V_EN_CH1(1U)
44924 
44925 #define S_EN_CH0    0
44926 #define V_EN_CH0(x) ((x) << S_EN_CH0)
44927 #define F_EN_CH0    V_EN_CH0(1U)
44928 
44929 #define A_MPS_VF_RPLCT_MAP4 0x11300
44930 #define A_MPS_VF_RPLCT_MAP5 0x11304
44931 #define A_MPS_VF_RPLCT_MAP6 0x11308
44932 #define A_MPS_VF_RPLCT_MAP7 0x1130c
44933 #define A_MPS_RX_PERR_INT_CAUSE3 0x11310
44934 #define A_MPS_RX_PERR_INT_ENABLE3 0x11314
44935 #define A_MPS_RX_PERR_ENABLE3 0x11318
44936 #define A_MPS_RX_PERR_INT_CAUSE4 0x1131c
44937 
44938 #define S_CLS    20
44939 #define M_CLS    0x3fU
44940 #define V_CLS(x) ((x) << S_CLS)
44941 #define G_CLS(x) (((x) >> S_CLS) & M_CLS)
44942 
44943 #define S_RX_PRE_PROC    16
44944 #define M_RX_PRE_PROC    0xfU
44945 #define V_RX_PRE_PROC(x) ((x) << S_RX_PRE_PROC)
44946 #define G_RX_PRE_PROC(x) (((x) >> S_RX_PRE_PROC) & M_RX_PRE_PROC)
44947 
44948 #define S_PPROC3    12
44949 #define M_PPROC3    0xfU
44950 #define V_PPROC3(x) ((x) << S_PPROC3)
44951 #define G_PPROC3(x) (((x) >> S_PPROC3) & M_PPROC3)
44952 
44953 #define S_PPROC2    8
44954 #define M_PPROC2    0xfU
44955 #define V_PPROC2(x) ((x) << S_PPROC2)
44956 #define G_PPROC2(x) (((x) >> S_PPROC2) & M_PPROC2)
44957 
44958 #define S_PPROC1    4
44959 #define M_PPROC1    0xfU
44960 #define V_PPROC1(x) ((x) << S_PPROC1)
44961 #define G_PPROC1(x) (((x) >> S_PPROC1) & M_PPROC1)
44962 
44963 #define S_PPROC0    0
44964 #define M_PPROC0    0xfU
44965 #define V_PPROC0(x) ((x) << S_PPROC0)
44966 #define G_PPROC0(x) (((x) >> S_PPROC0) & M_PPROC0)
44967 
44968 #define A_MPS_RX_PERR_INT_ENABLE4 0x11320
44969 #define A_MPS_RX_PERR_ENABLE4 0x11324
44970 #define A_MPS_RX_PERR_INT_CAUSE5 0x11328
44971 
44972 #define S_MPS2CRYP_RX_FIFO    26
44973 #define M_MPS2CRYP_RX_FIFO    0xfU
44974 #define V_MPS2CRYP_RX_FIFO(x) ((x) << S_MPS2CRYP_RX_FIFO)
44975 #define G_MPS2CRYP_RX_FIFO(x) (((x) >> S_MPS2CRYP_RX_FIFO) & M_MPS2CRYP_RX_FIFO)
44976 
44977 #define S_RX_OUT    20
44978 #define M_RX_OUT    0x3fU
44979 #define V_RX_OUT(x) ((x) << S_RX_OUT)
44980 #define G_RX_OUT(x) (((x) >> S_RX_OUT) & M_RX_OUT)
44981 
44982 #define S_MEM_WRAP    0
44983 #define M_MEM_WRAP    0xfffffU
44984 #define V_MEM_WRAP(x) ((x) << S_MEM_WRAP)
44985 #define G_MEM_WRAP(x) (((x) >> S_MEM_WRAP) & M_MEM_WRAP)
44986 
44987 #define A_MPS_RX_PERR_INT_ENABLE5 0x1132c
44988 #define A_MPS_RX_PERR_ENABLE5 0x11330
44989 #define A_MPS_RX_PERR_INT_CAUSE6 0x11334
44990 
44991 #define S_MPS_RX_MEM_WRAP    0
44992 #define M_MPS_RX_MEM_WRAP    0x1ffffffU
44993 #define V_MPS_RX_MEM_WRAP(x) ((x) << S_MPS_RX_MEM_WRAP)
44994 #define G_MPS_RX_MEM_WRAP(x) (((x) >> S_MPS_RX_MEM_WRAP) & M_MPS_RX_MEM_WRAP)
44995 
44996 #define A_MPS_RX_PERR_INT_ENABLE6 0x11338
44997 #define A_MPS_RX_PERR_ENABLE6 0x1133c
44998 #define A_MPS_RX_CNT_NVGRE_PKT_MAC2 0x11408
44999 #define A_MPS_RX_CNT_VXLAN_PKT_MAC2 0x1140c
45000 #define A_MPS_RX_CNT_GENEVE_PKT_MAC2 0x11410
45001 #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC2 0x11414
45002 #define A_MPS_RX_CNT_NVGRE_PKT_MAC3 0x11418
45003 #define A_MPS_RX_CNT_VXLAN_PKT_MAC3 0x1141c
45004 #define A_MPS_RX_CNT_GENEVE_PKT_MAC3 0x11420
45005 #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC3 0x11424
45006 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK2 0x11428
45007 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK2 0x1142c
45008 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK2 0x11430
45009 #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK2 0x11434
45010 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK3 0x11438
45011 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK3 0x1143c
45012 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK3 0x11440
45013 #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK3 0x11444
45014 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP2 0x11448
45015 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP2 0x1144c
45016 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP2 0x11450
45017 #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP2 0x11454
45018 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP3 0x11458
45019 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP3 0x1145c
45020 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP3 0x11460
45021 #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP3 0x11464
45022 #define A_T7_MPS_RX_PT_ARB2 0x11468
45023 #define A_T7_MPS_RX_PT_ARB3 0x1146c
45024 #define A_MPS_CLS_DIPIPV4_ID_TABLE 0x12000
45025 #define A_MPS_CLS_DIP_ID_TABLE_CTL 0x12000
45026 
45027 #define S_DIP_VLD    12
45028 #define V_DIP_VLD(x) ((x) << S_DIP_VLD)
45029 #define F_DIP_VLD    V_DIP_VLD(1U)
45030 
45031 #define S_DIP_TYPE    11
45032 #define V_DIP_TYPE(x) ((x) << S_DIP_TYPE)
45033 #define F_DIP_TYPE    V_DIP_TYPE(1U)
45034 
45035 #define S_DIP_WRN    10
45036 #define V_DIP_WRN(x) ((x) << S_DIP_WRN)
45037 #define F_DIP_WRN    V_DIP_WRN(1U)
45038 
45039 #define S_DIP_SEG    8
45040 #define M_DIP_SEG    0x3U
45041 #define V_DIP_SEG(x) ((x) << S_DIP_SEG)
45042 #define G_DIP_SEG(x) (((x) >> S_DIP_SEG) & M_DIP_SEG)
45043 
45044 #define S_DIP_TBL_RSVD1    5
45045 #define M_DIP_TBL_RSVD1    0x7U
45046 #define V_DIP_TBL_RSVD1(x) ((x) << S_DIP_TBL_RSVD1)
45047 #define G_DIP_TBL_RSVD1(x) (((x) >> S_DIP_TBL_RSVD1) & M_DIP_TBL_RSVD1)
45048 
45049 #define S_DIP_TBL_ADDR    0
45050 #define M_DIP_TBL_ADDR    0x1fU
45051 #define V_DIP_TBL_ADDR(x) ((x) << S_DIP_TBL_ADDR)
45052 #define G_DIP_TBL_ADDR(x) (((x) >> S_DIP_TBL_ADDR) & M_DIP_TBL_ADDR)
45053 
45054 #define A_MPS_CLS_DIPIPV4_MASK_TABLE 0x12004
45055 #define A_MPS_CLS_DIP_ID_TABLE_DATA 0x12004
45056 #define A_MPS_CLS_DIPIPV6ID_0_TABLE 0x12020
45057 #define A_MPS_CLS_DIPIPV6ID_1_TABLE 0x12024
45058 #define A_MPS_CLS_DIPIPV6ID_2_TABLE 0x12028
45059 #define A_MPS_CLS_DIPIPV6ID_3_TABLE 0x1202c
45060 #define A_MPS_CLS_DIPIPV6MASK_0_TABLE 0x12030
45061 #define A_MPS_CLS_DIPIPV6MASK_1_TABLE 0x12034
45062 #define A_MPS_CLS_DIPIPV6MASK_2_TABLE 0x12038
45063 #define A_MPS_CLS_DIPIPV6MASK_3_TABLE 0x1203c
45064 #define A_MPS_RX_HASH_LKP_TABLE 0x12060
45065 #define A_MPS_CLS_DROP_DMAC0_L 0x12070
45066 #define A_MPS_CLS_DROP_DMAC0_H 0x12074
45067 
45068 #define S_DMAC    0
45069 #define M_DMAC    0xffffU
45070 #define V_DMAC(x) ((x) << S_DMAC)
45071 #define G_DMAC(x) (((x) >> S_DMAC) & M_DMAC)
45072 
45073 #define A_MPS_CLS_DROP_DMAC1_L 0x12078
45074 #define A_MPS_CLS_DROP_DMAC1_H 0x1207c
45075 #define A_MPS_CLS_DROP_DMAC2_L 0x12080
45076 #define A_MPS_CLS_DROP_DMAC2_H 0x12084
45077 #define A_MPS_CLS_DROP_DMAC3_L 0x12088
45078 #define A_MPS_CLS_DROP_DMAC3_H 0x1208c
45079 #define A_MPS_CLS_DROP_DMAC4_L 0x12090
45080 #define A_MPS_CLS_DROP_DMAC4_H 0x12094
45081 #define A_MPS_CLS_DROP_DMAC5_L 0x12098
45082 #define A_MPS_CLS_DROP_DMAC5_H 0x1209c
45083 #define A_MPS_CLS_DROP_DMAC6_L 0x120a0
45084 #define A_MPS_CLS_DROP_DMAC6_H 0x120a4
45085 #define A_MPS_CLS_DROP_DMAC7_L 0x120a8
45086 #define A_MPS_CLS_DROP_DMAC7_H 0x120ac
45087 #define A_MPS_CLS_DROP_DMAC8_L 0x120b0
45088 #define A_MPS_CLS_DROP_DMAC8_H 0x120b4
45089 #define A_MPS_CLS_DROP_DMAC9_L 0x120b8
45090 #define A_MPS_CLS_DROP_DMAC9_H 0x120bc
45091 #define A_MPS_CLS_DROP_DMAC10_L 0x120c0
45092 #define A_MPS_CLS_DROP_DMAC10_H 0x120c4
45093 #define A_MPS_CLS_DROP_DMAC11_L 0x120c8
45094 #define A_MPS_CLS_DROP_DMAC11_H 0x120cc
45095 #define A_MPS_CLS_DROP_DMAC12_L 0x120d0
45096 #define A_MPS_CLS_DROP_DMAC12_H 0x120d4
45097 #define A_MPS_CLS_DROP_DMAC13_L 0x120d8
45098 #define A_MPS_CLS_DROP_DMAC13_H 0x120dc
45099 #define A_MPS_CLS_DROP_DMAC14_L 0x120e0
45100 #define A_MPS_CLS_DROP_DMAC14_H 0x120e4
45101 #define A_MPS_CLS_DROP_DMAC15_L 0x120e8
45102 #define A_MPS_CLS_DROP_DMAC15_H 0x120ec
45103 #define A_MPS_RX_ENCAP_VXLAN 0x120f0
45104 #define A_MPS_RX_INT_VXLAN 0x120f4
45105 
45106 #define S_INT_TYPE_EN    16
45107 #define V_INT_TYPE_EN(x) ((x) << S_INT_TYPE_EN)
45108 #define F_INT_TYPE_EN    V_INT_TYPE_EN(1U)
45109 
45110 #define S_INT_TYPE    0
45111 #define M_INT_TYPE    0xffffU
45112 #define V_INT_TYPE(x) ((x) << S_INT_TYPE)
45113 #define G_INT_TYPE(x) (((x) >> S_INT_TYPE) & M_INT_TYPE)
45114 
45115 #define A_MPS_RX_INT_GENEVE 0x120f8
45116 #define A_MPS_PFVF_ATRB2 0x120fc
45117 
45118 #define S_EXTRACT_DEL_ENCAP    31
45119 #define V_EXTRACT_DEL_ENCAP(x) ((x) << S_EXTRACT_DEL_ENCAP)
45120 #define F_EXTRACT_DEL_ENCAP    V_EXTRACT_DEL_ENCAP(1U)
45121 
45122 #define A_MPS_RX_TRANS_ENCAP_FLTR_CTL 0x12100
45123 
45124 #define S_TIMEOUT_FLT_CLR_EN    8
45125 #define V_TIMEOUT_FLT_CLR_EN(x) ((x) << S_TIMEOUT_FLT_CLR_EN)
45126 #define F_TIMEOUT_FLT_CLR_EN    V_TIMEOUT_FLT_CLR_EN(1U)
45127 
45128 #define S_FLTR_TIMOUT_VAL    0
45129 #define M_FLTR_TIMOUT_VAL    0xffU
45130 #define V_FLTR_TIMOUT_VAL(x) ((x) << S_FLTR_TIMOUT_VAL)
45131 #define G_FLTR_TIMOUT_VAL(x) (((x) >> S_FLTR_TIMOUT_VAL) & M_FLTR_TIMOUT_VAL)
45132 
45133 #define A_T7_MPS_RX_PAUSE_GEN_TH_0_0 0x12104
45134 #define A_T7_MPS_RX_PAUSE_GEN_TH_0_1 0x12108
45135 #define A_T7_MPS_RX_PAUSE_GEN_TH_0_2 0x1210c
45136 #define A_T7_MPS_RX_PAUSE_GEN_TH_0_3 0x12110
45137 #define A_MPS_RX_PAUSE_GEN_TH_0_4 0x12114
45138 #define A_MPS_RX_PAUSE_GEN_TH_0_5 0x12118
45139 #define A_MPS_RX_PAUSE_GEN_TH_0_6 0x1211c
45140 #define A_MPS_RX_PAUSE_GEN_TH_0_7 0x12120
45141 #define A_T7_MPS_RX_PAUSE_GEN_TH_1_0 0x12124
45142 #define A_T7_MPS_RX_PAUSE_GEN_TH_1_1 0x12128
45143 #define A_T7_MPS_RX_PAUSE_GEN_TH_1_2 0x1212c
45144 #define A_T7_MPS_RX_PAUSE_GEN_TH_1_3 0x12130
45145 #define A_MPS_RX_PAUSE_GEN_TH_1_4 0x12134
45146 #define A_MPS_RX_PAUSE_GEN_TH_1_5 0x12138
45147 #define A_MPS_RX_PAUSE_GEN_TH_1_6 0x1213c
45148 #define A_MPS_RX_PAUSE_GEN_TH_1_7 0x12140
45149 #define A_T7_MPS_RX_PAUSE_GEN_TH_2_0 0x12144
45150 #define A_T7_MPS_RX_PAUSE_GEN_TH_2_1 0x12148
45151 #define A_T7_MPS_RX_PAUSE_GEN_TH_2_2 0x1214c
45152 #define A_T7_MPS_RX_PAUSE_GEN_TH_2_3 0x12150
45153 #define A_MPS_RX_PAUSE_GEN_TH_2_4 0x12154
45154 #define A_MPS_RX_PAUSE_GEN_TH_2_5 0x12158
45155 #define A_MPS_RX_PAUSE_GEN_TH_2_6 0x1215c
45156 #define A_MPS_RX_PAUSE_GEN_TH_2_7 0x12160
45157 #define A_T7_MPS_RX_PAUSE_GEN_TH_3_0 0x12164
45158 #define A_T7_MPS_RX_PAUSE_GEN_TH_3_1 0x12168
45159 #define A_T7_MPS_RX_PAUSE_GEN_TH_3_2 0x1216c
45160 #define A_T7_MPS_RX_PAUSE_GEN_TH_3_3 0x12170
45161 #define A_MPS_RX_PAUSE_GEN_TH_3_4 0x12174
45162 #define A_MPS_RX_PAUSE_GEN_TH_3_5 0x12178
45163 #define A_MPS_RX_PAUSE_GEN_TH_3_6 0x1217c
45164 #define A_MPS_RX_PAUSE_GEN_TH_3_7 0x12180
45165 #define A_MPS_RX_DROP_0_0 0x12184
45166 
45167 #define S_DROP_TH    0
45168 #define M_DROP_TH    0xffffU
45169 #define V_DROP_TH(x) ((x) << S_DROP_TH)
45170 #define G_DROP_TH(x) (((x) >> S_DROP_TH) & M_DROP_TH)
45171 
45172 #define A_MPS_RX_DROP_0_1 0x12188
45173 #define A_MPS_RX_DROP_0_2 0x1218c
45174 #define A_MPS_RX_DROP_0_3 0x12190
45175 #define A_MPS_RX_DROP_0_4 0x12194
45176 #define A_MPS_RX_DROP_0_5 0x12198
45177 #define A_MPS_RX_DROP_0_6 0x1219c
45178 #define A_MPS_RX_DROP_0_7 0x121a0
45179 #define A_MPS_RX_DROP_1_0 0x121a4
45180 #define A_MPS_RX_DROP_1_1 0x121a8
45181 #define A_MPS_RX_DROP_1_2 0x121ac
45182 #define A_MPS_RX_DROP_1_3 0x121b0
45183 #define A_MPS_RX_DROP_1_4 0x121b4
45184 #define A_MPS_RX_DROP_1_5 0x121b8
45185 #define A_MPS_RX_DROP_1_6 0x121bc
45186 #define A_MPS_RX_DROP_1_7 0x121c0
45187 #define A_MPS_RX_DROP_2_0 0x121c4
45188 #define A_MPS_RX_DROP_2_1 0x121c8
45189 #define A_MPS_RX_DROP_2_2 0x121cc
45190 #define A_MPS_RX_DROP_2_3 0x121d0
45191 #define A_MPS_RX_DROP_2_4 0x121d4
45192 #define A_MPS_RX_DROP_2_5 0x121d8
45193 #define A_MPS_RX_DROP_2_6 0x121dc
45194 #define A_MPS_RX_DROP_2_7 0x121e0
45195 #define A_MPS_RX_DROP_3_0 0x121e4
45196 #define A_MPS_RX_DROP_3_1 0x121e8
45197 #define A_MPS_RX_DROP_3_2 0x121ec
45198 #define A_MPS_RX_DROP_3_3 0x121f0
45199 #define A_MPS_RX_DROP_3_4 0x121f4
45200 #define A_MPS_RX_DROP_3_5 0x121f8
45201 #define A_MPS_RX_DROP_3_6 0x121fc
45202 #define A_MPS_RX_DROP_3_7 0x12200
45203 #define A_MPS_RX_MAC_BG_PG_CNT0_0 0x12204
45204 #define A_MPS_RX_MAC_BG_PG_CNT0_1 0x12208
45205 #define A_MPS_RX_MAC_BG_PG_CNT0_2 0x1220c
45206 #define A_MPS_RX_MAC_BG_PG_CNT0_3 0x12210
45207 #define A_MPS_RX_MAC_BG_PG_CNT0_4 0x12214
45208 #define A_MPS_RX_MAC_BG_PG_CNT0_5 0x12218
45209 #define A_MPS_RX_MAC_BG_PG_CNT0_6 0x1221c
45210 #define A_MPS_RX_MAC_BG_PG_CNT0_7 0x12220
45211 #define A_MPS_RX_MAC_BG_PG_CNT1_0 0x12224
45212 #define A_MPS_RX_MAC_BG_PG_CNT1_1 0x12228
45213 #define A_MPS_RX_MAC_BG_PG_CNT1_2 0x1222c
45214 #define A_MPS_RX_MAC_BG_PG_CNT1_3 0x12230
45215 #define A_MPS_RX_MAC_BG_PG_CNT1_4 0x12234
45216 #define A_MPS_RX_MAC_BG_PG_CNT1_5 0x12238
45217 #define A_MPS_RX_MAC_BG_PG_CNT1_6 0x1223c
45218 #define A_MPS_RX_MAC_BG_PG_CNT1_7 0x12240
45219 #define A_MPS_RX_MAC_BG_PG_CNT2_0 0x12244
45220 #define A_MPS_RX_MAC_BG_PG_CNT2_1 0x12248
45221 #define A_MPS_RX_MAC_BG_PG_CNT2_2 0x1224c
45222 #define A_MPS_RX_MAC_BG_PG_CNT2_3 0x12250
45223 #define A_MPS_RX_MAC_BG_PG_CNT2_4 0x12254
45224 #define A_MPS_RX_MAC_BG_PG_CNT2_5 0x12258
45225 #define A_MPS_RX_MAC_BG_PG_CNT2_6 0x1225c
45226 #define A_MPS_RX_MAC_BG_PG_CNT2_7 0x12260
45227 #define A_MPS_RX_MAC_BG_PG_CNT3_0 0x12264
45228 #define A_MPS_RX_MAC_BG_PG_CNT3_1 0x12268
45229 #define A_MPS_RX_MAC_BG_PG_CNT3_2 0x1226c
45230 #define A_MPS_RX_MAC_BG_PG_CNT3_3 0x12270
45231 #define A_MPS_RX_MAC_BG_PG_CNT3_4 0x12274
45232 #define A_MPS_RX_MAC_BG_PG_CNT3_5 0x12278
45233 #define A_MPS_RX_MAC_BG_PG_CNT3_6 0x1227c
45234 #define A_MPS_RX_MAC_BG_PG_CNT3_7 0x12280
45235 #define A_T7_MPS_RX_PAUSE_GEN_TH_0 0x12284
45236 #define A_T7_MPS_RX_PAUSE_GEN_TH_1 0x12288
45237 #define A_T7_MPS_RX_PAUSE_GEN_TH_2 0x1228c
45238 #define A_T7_MPS_RX_PAUSE_GEN_TH_3 0x12290
45239 #define A_MPS_RX_BG0_IPSEC_CNT 0x12294
45240 #define A_MPS_RX_BG1_IPSEC_CNT 0x12298
45241 #define A_MPS_RX_BG2_IPSEC_CNT 0x1229c
45242 #define A_MPS_RX_BG3_IPSEC_CNT 0x122a0
45243 #define A_MPS_RX_MEM_FIFO_CONFIG0 0x122a4
45244 
45245 #define S_FIFO_CONFIG2    16
45246 #define M_FIFO_CONFIG2    0xffffU
45247 #define V_FIFO_CONFIG2(x) ((x) << S_FIFO_CONFIG2)
45248 #define G_FIFO_CONFIG2(x) (((x) >> S_FIFO_CONFIG2) & M_FIFO_CONFIG2)
45249 
45250 #define S_FIFO_CONFIG1    0
45251 #define M_FIFO_CONFIG1    0xffffU
45252 #define V_FIFO_CONFIG1(x) ((x) << S_FIFO_CONFIG1)
45253 #define G_FIFO_CONFIG1(x) (((x) >> S_FIFO_CONFIG1) & M_FIFO_CONFIG1)
45254 
45255 #define A_MPS_RX_MEM_FIFO_CONFIG1 0x122a8
45256 
45257 #define S_FIFO_CONFIG3    0
45258 #define M_FIFO_CONFIG3    0xffffU
45259 #define V_FIFO_CONFIG3(x) ((x) << S_FIFO_CONFIG3)
45260 #define G_FIFO_CONFIG3(x) (((x) >> S_FIFO_CONFIG3) & M_FIFO_CONFIG3)
45261 
45262 #define A_MPS_LPBK_MEM_FIFO_CONFIG0 0x122ac
45263 #define A_MPS_LPBK_MEM_FIFO_CONFIG1 0x122b0
45264 #define A_MPS_RX_LPBK_CONGESTION_THRESHOLD_BG0 0x122b4
45265 #define A_MPS_RX_LPBK_CONGESTION_THRESHOLD_BG1 0x122b8
45266 #define A_MPS_RX_LPBK_CONGESTION_THRESHOLD_BG2 0x122bc
45267 #define A_MPS_RX_LPBK_CONGESTION_THRESHOLD_BG3 0x122c0
45268 #define A_MPS_BG_PAUSE_CTL 0x122c4
45269 
45270 #define S_BG0_PAUSE_EN    3
45271 #define V_BG0_PAUSE_EN(x) ((x) << S_BG0_PAUSE_EN)
45272 #define F_BG0_PAUSE_EN    V_BG0_PAUSE_EN(1U)
45273 
45274 #define S_BG1_PAUSE_EN    2
45275 #define V_BG1_PAUSE_EN(x) ((x) << S_BG1_PAUSE_EN)
45276 #define F_BG1_PAUSE_EN    V_BG1_PAUSE_EN(1U)
45277 
45278 #define S_BG2_PAUSE_EN    1
45279 #define V_BG2_PAUSE_EN(x) ((x) << S_BG2_PAUSE_EN)
45280 #define F_BG2_PAUSE_EN    V_BG2_PAUSE_EN(1U)
45281 
45282 #define S_BG3_PAUSE_EN    0
45283 #define V_BG3_PAUSE_EN(x) ((x) << S_BG3_PAUSE_EN)
45284 #define F_BG3_PAUSE_EN    V_BG3_PAUSE_EN(1U)
45285 
45286 /* registers for module CPL_SWITCH */
45287 #define CPL_SWITCH_BASE_ADDR 0x19040
45288 
45289 #define A_CPL_SWITCH_CNTRL 0x19040
45290 
45291 #define S_CPL_PKT_TID    8
45292 #define M_CPL_PKT_TID    0xffffffU
45293 #define V_CPL_PKT_TID(x) ((x) << S_CPL_PKT_TID)
45294 #define G_CPL_PKT_TID(x) (((x) >> S_CPL_PKT_TID) & M_CPL_PKT_TID)
45295 
45296 #define S_CIM_TRUNCATE_ENABLE    5
45297 #define V_CIM_TRUNCATE_ENABLE(x) ((x) << S_CIM_TRUNCATE_ENABLE)
45298 #define F_CIM_TRUNCATE_ENABLE    V_CIM_TRUNCATE_ENABLE(1U)
45299 
45300 #define S_CIM_TO_UP_FULL_SIZE    4
45301 #define V_CIM_TO_UP_FULL_SIZE(x) ((x) << S_CIM_TO_UP_FULL_SIZE)
45302 #define F_CIM_TO_UP_FULL_SIZE    V_CIM_TO_UP_FULL_SIZE(1U)
45303 
45304 #define S_CPU_NO_ENABLE    3
45305 #define V_CPU_NO_ENABLE(x) ((x) << S_CPU_NO_ENABLE)
45306 #define F_CPU_NO_ENABLE    V_CPU_NO_ENABLE(1U)
45307 
45308 #define S_SWITCH_TABLE_ENABLE    2
45309 #define V_SWITCH_TABLE_ENABLE(x) ((x) << S_SWITCH_TABLE_ENABLE)
45310 #define F_SWITCH_TABLE_ENABLE    V_SWITCH_TABLE_ENABLE(1U)
45311 
45312 #define S_SGE_ENABLE    1
45313 #define V_SGE_ENABLE(x) ((x) << S_SGE_ENABLE)
45314 #define F_SGE_ENABLE    V_SGE_ENABLE(1U)
45315 
45316 #define S_CIM_ENABLE    0
45317 #define V_CIM_ENABLE(x) ((x) << S_CIM_ENABLE)
45318 #define F_CIM_ENABLE    V_CIM_ENABLE(1U)
45319 
45320 #define S_CIM_SPLIT_ENABLE    6
45321 #define V_CIM_SPLIT_ENABLE(x) ((x) << S_CIM_SPLIT_ENABLE)
45322 #define F_CIM_SPLIT_ENABLE    V_CIM_SPLIT_ENABLE(1U)
45323 
45324 #define A_CNTRL 0x19040
45325 #define A_CPL_SWITCH_TBL_IDX 0x19044
45326 
45327 #define S_SWITCH_TBL_IDX    0
45328 #define M_SWITCH_TBL_IDX    0xfU
45329 #define V_SWITCH_TBL_IDX(x) ((x) << S_SWITCH_TBL_IDX)
45330 #define G_SWITCH_TBL_IDX(x) (((x) >> S_SWITCH_TBL_IDX) & M_SWITCH_TBL_IDX)
45331 
45332 #define A_TBL_IDX 0x19044
45333 #define A_CPL_SWITCH_TBL_DATA 0x19048
45334 #define A_TBL_DATA 0x19048
45335 #define A_CPL_SWITCH_ZERO_ERROR 0x1904c
45336 
45337 #define S_ZERO_CMD_CH1    8
45338 #define M_ZERO_CMD_CH1    0xffU
45339 #define V_ZERO_CMD_CH1(x) ((x) << S_ZERO_CMD_CH1)
45340 #define G_ZERO_CMD_CH1(x) (((x) >> S_ZERO_CMD_CH1) & M_ZERO_CMD_CH1)
45341 
45342 #define S_ZERO_CMD_CH0    0
45343 #define M_ZERO_CMD_CH0    0xffU
45344 #define V_ZERO_CMD_CH0(x) ((x) << S_ZERO_CMD_CH0)
45345 #define G_ZERO_CMD_CH0(x) (((x) >> S_ZERO_CMD_CH0) & M_ZERO_CMD_CH0)
45346 
45347 #define A_ZERO_ERROR 0x1904c
45348 
45349 #define S_ZERO_CMD_CH3    24
45350 #define M_ZERO_CMD_CH3    0xffU
45351 #define V_ZERO_CMD_CH3(x) ((x) << S_ZERO_CMD_CH3)
45352 #define G_ZERO_CMD_CH3(x) (((x) >> S_ZERO_CMD_CH3) & M_ZERO_CMD_CH3)
45353 
45354 #define S_ZERO_CMD_CH2    16
45355 #define M_ZERO_CMD_CH2    0xffU
45356 #define V_ZERO_CMD_CH2(x) ((x) << S_ZERO_CMD_CH2)
45357 #define G_ZERO_CMD_CH2(x) (((x) >> S_ZERO_CMD_CH2) & M_ZERO_CMD_CH2)
45358 
45359 #define A_CPL_INTR_ENABLE 0x19050
45360 
45361 #define S_CIM_OP_MAP_PERR    5
45362 #define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR)
45363 #define F_CIM_OP_MAP_PERR    V_CIM_OP_MAP_PERR(1U)
45364 
45365 #define S_CIM_OVFL_ERROR    4
45366 #define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
45367 #define F_CIM_OVFL_ERROR    V_CIM_OVFL_ERROR(1U)
45368 
45369 #define S_TP_FRAMING_ERROR    3
45370 #define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
45371 #define F_TP_FRAMING_ERROR    V_TP_FRAMING_ERROR(1U)
45372 
45373 #define S_SGE_FRAMING_ERROR    2
45374 #define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
45375 #define F_SGE_FRAMING_ERROR    V_SGE_FRAMING_ERROR(1U)
45376 
45377 #define S_CIM_FRAMING_ERROR    1
45378 #define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
45379 #define F_CIM_FRAMING_ERROR    V_CIM_FRAMING_ERROR(1U)
45380 
45381 #define S_ZERO_SWITCH_ERROR    0
45382 #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
45383 #define F_ZERO_SWITCH_ERROR    V_ZERO_SWITCH_ERROR(1U)
45384 
45385 #define S_PERR_CPL_128TO128_1    7
45386 #define V_PERR_CPL_128TO128_1(x) ((x) << S_PERR_CPL_128TO128_1)
45387 #define F_PERR_CPL_128TO128_1    V_PERR_CPL_128TO128_1(1U)
45388 
45389 #define S_PERR_CPL_128TO128_0    6
45390 #define V_PERR_CPL_128TO128_0(x) ((x) << S_PERR_CPL_128TO128_0)
45391 #define F_PERR_CPL_128TO128_0    V_PERR_CPL_128TO128_0(1U)
45392 
45393 #define A_INTR_ENABLE 0x19050
45394 
45395 #define S_PERR_CPL_128TO128_3    9
45396 #define V_PERR_CPL_128TO128_3(x) ((x) << S_PERR_CPL_128TO128_3)
45397 #define F_PERR_CPL_128TO128_3    V_PERR_CPL_128TO128_3(1U)
45398 
45399 #define S_PERR_CPL_128TO128_2    8
45400 #define V_PERR_CPL_128TO128_2(x) ((x) << S_PERR_CPL_128TO128_2)
45401 #define F_PERR_CPL_128TO128_2    V_PERR_CPL_128TO128_2(1U)
45402 
45403 #define A_CPL_INTR_CAUSE 0x19054
45404 #define A_INTR_CAUSE 0x19054
45405 #define A_CPL_MAP_TBL_IDX 0x19058
45406 
45407 #define S_MAP_TBL_IDX    0
45408 #define M_MAP_TBL_IDX    0xffU
45409 #define V_MAP_TBL_IDX(x) ((x) << S_MAP_TBL_IDX)
45410 #define G_MAP_TBL_IDX(x) (((x) >> S_MAP_TBL_IDX) & M_MAP_TBL_IDX)
45411 
45412 #define S_CIM_SPLIT_OPCODE_PROGRAM    8
45413 #define V_CIM_SPLIT_OPCODE_PROGRAM(x) ((x) << S_CIM_SPLIT_OPCODE_PROGRAM)
45414 #define F_CIM_SPLIT_OPCODE_PROGRAM    V_CIM_SPLIT_OPCODE_PROGRAM(1U)
45415 
45416 #define A_MAP_TBL_IDX 0x19058
45417 
45418 #define S_CPL_MAP_TBL_SEL    9
45419 #define M_CPL_MAP_TBL_SEL    0x3U
45420 #define V_CPL_MAP_TBL_SEL(x) ((x) << S_CPL_MAP_TBL_SEL)
45421 #define G_CPL_MAP_TBL_SEL(x) (((x) >> S_CPL_MAP_TBL_SEL) & M_CPL_MAP_TBL_SEL)
45422 
45423 #define A_CPL_MAP_TBL_DATA 0x1905c
45424 
45425 #define S_MAP_TBL_DATA    0
45426 #define M_MAP_TBL_DATA    0xffU
45427 #define V_MAP_TBL_DATA(x) ((x) << S_MAP_TBL_DATA)
45428 #define G_MAP_TBL_DATA(x) (((x) >> S_MAP_TBL_DATA) & M_MAP_TBL_DATA)
45429 
45430 #define A_MAP_TBL_DATA 0x1905c
45431 
45432 /* registers for module SMB */
45433 #define SMB_BASE_ADDR 0x19060
45434 
45435 #define A_SMB_GLOBAL_TIME_CFG 0x19060
45436 
45437 #define S_MACROCNTCFG    8
45438 #define M_MACROCNTCFG    0x1fU
45439 #define V_MACROCNTCFG(x) ((x) << S_MACROCNTCFG)
45440 #define G_MACROCNTCFG(x) (((x) >> S_MACROCNTCFG) & M_MACROCNTCFG)
45441 
45442 #define S_MICROCNTCFG    0
45443 #define M_MICROCNTCFG    0xffU
45444 #define V_MICROCNTCFG(x) ((x) << S_MICROCNTCFG)
45445 #define G_MICROCNTCFG(x) (((x) >> S_MICROCNTCFG) & M_MICROCNTCFG)
45446 
45447 #define S_T7_MACROCNTCFG    12
45448 #define M_T7_MACROCNTCFG    0x1fU
45449 #define V_T7_MACROCNTCFG(x) ((x) << S_T7_MACROCNTCFG)
45450 #define G_T7_MACROCNTCFG(x) (((x) >> S_T7_MACROCNTCFG) & M_T7_MACROCNTCFG)
45451 
45452 #define S_T7_MICROCNTCFG    0
45453 #define M_T7_MICROCNTCFG    0xfffU
45454 #define V_T7_MICROCNTCFG(x) ((x) << S_T7_MICROCNTCFG)
45455 #define G_T7_MICROCNTCFG(x) (((x) >> S_T7_MICROCNTCFG) & M_T7_MICROCNTCFG)
45456 
45457 #define A_SMB_MST_TIMEOUT_CFG 0x19064
45458 
45459 #define S_MSTTIMEOUTCFG    0
45460 #define M_MSTTIMEOUTCFG    0xffffffU
45461 #define V_MSTTIMEOUTCFG(x) ((x) << S_MSTTIMEOUTCFG)
45462 #define G_MSTTIMEOUTCFG(x) (((x) >> S_MSTTIMEOUTCFG) & M_MSTTIMEOUTCFG)
45463 
45464 #define A_SMB_MST_CTL_CFG 0x19068
45465 
45466 #define S_MSTFIFODBG    31
45467 #define V_MSTFIFODBG(x) ((x) << S_MSTFIFODBG)
45468 #define F_MSTFIFODBG    V_MSTFIFODBG(1U)
45469 
45470 #define S_MSTFIFODBGCLR    30
45471 #define V_MSTFIFODBGCLR(x) ((x) << S_MSTFIFODBGCLR)
45472 #define F_MSTFIFODBGCLR    V_MSTFIFODBGCLR(1U)
45473 
45474 #define S_MSTRXBYTECFG    12
45475 #define M_MSTRXBYTECFG    0x3fU
45476 #define V_MSTRXBYTECFG(x) ((x) << S_MSTRXBYTECFG)
45477 #define G_MSTRXBYTECFG(x) (((x) >> S_MSTRXBYTECFG) & M_MSTRXBYTECFG)
45478 
45479 #define S_MSTTXBYTECFG    6
45480 #define M_MSTTXBYTECFG    0x3fU
45481 #define V_MSTTXBYTECFG(x) ((x) << S_MSTTXBYTECFG)
45482 #define G_MSTTXBYTECFG(x) (((x) >> S_MSTTXBYTECFG) & M_MSTTXBYTECFG)
45483 
45484 #define S_MSTRESET    1
45485 #define V_MSTRESET(x) ((x) << S_MSTRESET)
45486 #define F_MSTRESET    V_MSTRESET(1U)
45487 
45488 #define S_MSTCTLEN    0
45489 #define V_MSTCTLEN(x) ((x) << S_MSTCTLEN)
45490 #define F_MSTCTLEN    V_MSTCTLEN(1U)
45491 
45492 #define A_SMB_MST_CTL_STS 0x1906c
45493 
45494 #define S_MSTRXBYTECNT    12
45495 #define M_MSTRXBYTECNT    0x3fU
45496 #define V_MSTRXBYTECNT(x) ((x) << S_MSTRXBYTECNT)
45497 #define G_MSTRXBYTECNT(x) (((x) >> S_MSTRXBYTECNT) & M_MSTRXBYTECNT)
45498 
45499 #define S_MSTTXBYTECNT    6
45500 #define M_MSTTXBYTECNT    0x3fU
45501 #define V_MSTTXBYTECNT(x) ((x) << S_MSTTXBYTECNT)
45502 #define G_MSTTXBYTECNT(x) (((x) >> S_MSTTXBYTECNT) & M_MSTTXBYTECNT)
45503 
45504 #define S_MSTBUSYSTS    0
45505 #define V_MSTBUSYSTS(x) ((x) << S_MSTBUSYSTS)
45506 #define F_MSTBUSYSTS    V_MSTBUSYSTS(1U)
45507 
45508 #define A_SMB_MST_TX_FIFO_RDWR 0x19070
45509 #define A_SMB_MST_RX_FIFO_RDWR 0x19074
45510 #define A_SMB_SLV_TIMEOUT_CFG 0x19078
45511 
45512 #define S_SLVTIMEOUTCFG    0
45513 #define M_SLVTIMEOUTCFG    0xffffffU
45514 #define V_SLVTIMEOUTCFG(x) ((x) << S_SLVTIMEOUTCFG)
45515 #define G_SLVTIMEOUTCFG(x) (((x) >> S_SLVTIMEOUTCFG) & M_SLVTIMEOUTCFG)
45516 
45517 #define A_SMB_SLV_CTL_CFG 0x1907c
45518 
45519 #define S_SLVFIFODBG    31
45520 #define V_SLVFIFODBG(x) ((x) << S_SLVFIFODBG)
45521 #define F_SLVFIFODBG    V_SLVFIFODBG(1U)
45522 
45523 #define S_SLVFIFODBGCLR    30
45524 #define V_SLVFIFODBGCLR(x) ((x) << S_SLVFIFODBGCLR)
45525 #define F_SLVFIFODBGCLR    V_SLVFIFODBGCLR(1U)
45526 
45527 #define S_SLVCRCOUTBITINV    21
45528 #define V_SLVCRCOUTBITINV(x) ((x) << S_SLVCRCOUTBITINV)
45529 #define F_SLVCRCOUTBITINV    V_SLVCRCOUTBITINV(1U)
45530 
45531 #define S_SLVCRCOUTBITREV    20
45532 #define V_SLVCRCOUTBITREV(x) ((x) << S_SLVCRCOUTBITREV)
45533 #define F_SLVCRCOUTBITREV    V_SLVCRCOUTBITREV(1U)
45534 
45535 #define S_SLVCRCINBITREV    19
45536 #define V_SLVCRCINBITREV(x) ((x) << S_SLVCRCINBITREV)
45537 #define F_SLVCRCINBITREV    V_SLVCRCINBITREV(1U)
45538 
45539 #define S_SLVCRCPRESET    11
45540 #define M_SLVCRCPRESET    0xffU
45541 #define V_SLVCRCPRESET(x) ((x) << S_SLVCRCPRESET)
45542 #define G_SLVCRCPRESET(x) (((x) >> S_SLVCRCPRESET) & M_SLVCRCPRESET)
45543 
45544 #define S_SLVADDRCFG    4
45545 #define M_SLVADDRCFG    0x7fU
45546 #define V_SLVADDRCFG(x) ((x) << S_SLVADDRCFG)
45547 #define G_SLVADDRCFG(x) (((x) >> S_SLVADDRCFG) & M_SLVADDRCFG)
45548 
45549 #define S_SLVALRTSET    2
45550 #define V_SLVALRTSET(x) ((x) << S_SLVALRTSET)
45551 #define F_SLVALRTSET    V_SLVALRTSET(1U)
45552 
45553 #define S_SLVRESET    1
45554 #define V_SLVRESET(x) ((x) << S_SLVRESET)
45555 #define F_SLVRESET    V_SLVRESET(1U)
45556 
45557 #define S_SLVCTLEN    0
45558 #define V_SLVCTLEN(x) ((x) << S_SLVCTLEN)
45559 #define F_SLVCTLEN    V_SLVCTLEN(1U)
45560 
45561 #define A_SMB_SLV_CTL_STS 0x19080
45562 
45563 #define S_SLVFIFOTXCNT    12
45564 #define M_SLVFIFOTXCNT    0x3fU
45565 #define V_SLVFIFOTXCNT(x) ((x) << S_SLVFIFOTXCNT)
45566 #define G_SLVFIFOTXCNT(x) (((x) >> S_SLVFIFOTXCNT) & M_SLVFIFOTXCNT)
45567 
45568 #define S_SLVFIFOCNT    6
45569 #define M_SLVFIFOCNT    0x3fU
45570 #define V_SLVFIFOCNT(x) ((x) << S_SLVFIFOCNT)
45571 #define G_SLVFIFOCNT(x) (((x) >> S_SLVFIFOCNT) & M_SLVFIFOCNT)
45572 
45573 #define S_SLVALRTSTS    2
45574 #define V_SLVALRTSTS(x) ((x) << S_SLVALRTSTS)
45575 #define F_SLVALRTSTS    V_SLVALRTSTS(1U)
45576 
45577 #define S_SLVBUSYSTS    0
45578 #define V_SLVBUSYSTS(x) ((x) << S_SLVBUSYSTS)
45579 #define F_SLVBUSYSTS    V_SLVBUSYSTS(1U)
45580 
45581 #define A_SMB_SLV_FIFO_RDWR 0x19084
45582 #define A_SMB_INT_ENABLE 0x1908c
45583 
45584 #define S_MSTTXFIFOPAREN    21
45585 #define V_MSTTXFIFOPAREN(x) ((x) << S_MSTTXFIFOPAREN)
45586 #define F_MSTTXFIFOPAREN    V_MSTTXFIFOPAREN(1U)
45587 
45588 #define S_MSTRXFIFOPAREN    20
45589 #define V_MSTRXFIFOPAREN(x) ((x) << S_MSTRXFIFOPAREN)
45590 #define F_MSTRXFIFOPAREN    V_MSTRXFIFOPAREN(1U)
45591 
45592 #define S_SLVFIFOPAREN    19
45593 #define V_SLVFIFOPAREN(x) ((x) << S_SLVFIFOPAREN)
45594 #define F_SLVFIFOPAREN    V_SLVFIFOPAREN(1U)
45595 
45596 #define S_SLVUNEXPBUSSTOPEN    18
45597 #define V_SLVUNEXPBUSSTOPEN(x) ((x) << S_SLVUNEXPBUSSTOPEN)
45598 #define F_SLVUNEXPBUSSTOPEN    V_SLVUNEXPBUSSTOPEN(1U)
45599 
45600 #define S_SLVUNEXPBUSSTARTEN    17
45601 #define V_SLVUNEXPBUSSTARTEN(x) ((x) << S_SLVUNEXPBUSSTARTEN)
45602 #define F_SLVUNEXPBUSSTARTEN    V_SLVUNEXPBUSSTARTEN(1U)
45603 
45604 #define S_SLVCOMMANDCODEINVEN    16
45605 #define V_SLVCOMMANDCODEINVEN(x) ((x) << S_SLVCOMMANDCODEINVEN)
45606 #define F_SLVCOMMANDCODEINVEN    V_SLVCOMMANDCODEINVEN(1U)
45607 
45608 #define S_SLVBYTECNTERREN    15
45609 #define V_SLVBYTECNTERREN(x) ((x) << S_SLVBYTECNTERREN)
45610 #define F_SLVBYTECNTERREN    V_SLVBYTECNTERREN(1U)
45611 
45612 #define S_SLVUNEXPACKMSTEN    14
45613 #define V_SLVUNEXPACKMSTEN(x) ((x) << S_SLVUNEXPACKMSTEN)
45614 #define F_SLVUNEXPACKMSTEN    V_SLVUNEXPACKMSTEN(1U)
45615 
45616 #define S_SLVUNEXPNACKMSTEN    13
45617 #define V_SLVUNEXPNACKMSTEN(x) ((x) << S_SLVUNEXPNACKMSTEN)
45618 #define F_SLVUNEXPNACKMSTEN    V_SLVUNEXPNACKMSTEN(1U)
45619 
45620 #define S_SLVNOBUSSTOPEN    12
45621 #define V_SLVNOBUSSTOPEN(x) ((x) << S_SLVNOBUSSTOPEN)
45622 #define F_SLVNOBUSSTOPEN    V_SLVNOBUSSTOPEN(1U)
45623 
45624 #define S_SLVNOREPSTARTEN    11
45625 #define V_SLVNOREPSTARTEN(x) ((x) << S_SLVNOREPSTARTEN)
45626 #define F_SLVNOREPSTARTEN    V_SLVNOREPSTARTEN(1U)
45627 
45628 #define S_SLVRXADDRINTEN    10
45629 #define V_SLVRXADDRINTEN(x) ((x) << S_SLVRXADDRINTEN)
45630 #define F_SLVRXADDRINTEN    V_SLVRXADDRINTEN(1U)
45631 
45632 #define S_SLVRXPECERRINTEN    9
45633 #define V_SLVRXPECERRINTEN(x) ((x) << S_SLVRXPECERRINTEN)
45634 #define F_SLVRXPECERRINTEN    V_SLVRXPECERRINTEN(1U)
45635 
45636 #define S_SLVPREPTOARPINTEN    8
45637 #define V_SLVPREPTOARPINTEN(x) ((x) << S_SLVPREPTOARPINTEN)
45638 #define F_SLVPREPTOARPINTEN    V_SLVPREPTOARPINTEN(1U)
45639 
45640 #define S_SLVTIMEOUTINTEN    7
45641 #define V_SLVTIMEOUTINTEN(x) ((x) << S_SLVTIMEOUTINTEN)
45642 #define F_SLVTIMEOUTINTEN    V_SLVTIMEOUTINTEN(1U)
45643 
45644 #define S_SLVERRINTEN    6
45645 #define V_SLVERRINTEN(x) ((x) << S_SLVERRINTEN)
45646 #define F_SLVERRINTEN    V_SLVERRINTEN(1U)
45647 
45648 #define S_SLVDONEINTEN    5
45649 #define V_SLVDONEINTEN(x) ((x) << S_SLVDONEINTEN)
45650 #define F_SLVDONEINTEN    V_SLVDONEINTEN(1U)
45651 
45652 #define S_SLVRXRDYINTEN    4
45653 #define V_SLVRXRDYINTEN(x) ((x) << S_SLVRXRDYINTEN)
45654 #define F_SLVRXRDYINTEN    V_SLVRXRDYINTEN(1U)
45655 
45656 #define S_MSTTIMEOUTINTEN    3
45657 #define V_MSTTIMEOUTINTEN(x) ((x) << S_MSTTIMEOUTINTEN)
45658 #define F_MSTTIMEOUTINTEN    V_MSTTIMEOUTINTEN(1U)
45659 
45660 #define S_MSTNACKINTEN    2
45661 #define V_MSTNACKINTEN(x) ((x) << S_MSTNACKINTEN)
45662 #define F_MSTNACKINTEN    V_MSTNACKINTEN(1U)
45663 
45664 #define S_MSTLOSTARBINTEN    1
45665 #define V_MSTLOSTARBINTEN(x) ((x) << S_MSTLOSTARBINTEN)
45666 #define F_MSTLOSTARBINTEN    V_MSTLOSTARBINTEN(1U)
45667 
45668 #define S_MSTDONEINTEN    0
45669 #define V_MSTDONEINTEN(x) ((x) << S_MSTDONEINTEN)
45670 #define F_MSTDONEINTEN    V_MSTDONEINTEN(1U)
45671 
45672 #define A_SMB_INT_CAUSE 0x19090
45673 
45674 #define S_MSTTXFIFOPARINT    21
45675 #define V_MSTTXFIFOPARINT(x) ((x) << S_MSTTXFIFOPARINT)
45676 #define F_MSTTXFIFOPARINT    V_MSTTXFIFOPARINT(1U)
45677 
45678 #define S_MSTRXFIFOPARINT    20
45679 #define V_MSTRXFIFOPARINT(x) ((x) << S_MSTRXFIFOPARINT)
45680 #define F_MSTRXFIFOPARINT    V_MSTRXFIFOPARINT(1U)
45681 
45682 #define S_SLVFIFOPARINT    19
45683 #define V_SLVFIFOPARINT(x) ((x) << S_SLVFIFOPARINT)
45684 #define F_SLVFIFOPARINT    V_SLVFIFOPARINT(1U)
45685 
45686 #define S_SLVUNEXPBUSSTOPINT    18
45687 #define V_SLVUNEXPBUSSTOPINT(x) ((x) << S_SLVUNEXPBUSSTOPINT)
45688 #define F_SLVUNEXPBUSSTOPINT    V_SLVUNEXPBUSSTOPINT(1U)
45689 
45690 #define S_SLVUNEXPBUSSTARTINT    17
45691 #define V_SLVUNEXPBUSSTARTINT(x) ((x) << S_SLVUNEXPBUSSTARTINT)
45692 #define F_SLVUNEXPBUSSTARTINT    V_SLVUNEXPBUSSTARTINT(1U)
45693 
45694 #define S_SLVCOMMANDCODEINVINT    16
45695 #define V_SLVCOMMANDCODEINVINT(x) ((x) << S_SLVCOMMANDCODEINVINT)
45696 #define F_SLVCOMMANDCODEINVINT    V_SLVCOMMANDCODEINVINT(1U)
45697 
45698 #define S_SLVBYTECNTERRINT    15
45699 #define V_SLVBYTECNTERRINT(x) ((x) << S_SLVBYTECNTERRINT)
45700 #define F_SLVBYTECNTERRINT    V_SLVBYTECNTERRINT(1U)
45701 
45702 #define S_SLVUNEXPACKMSTINT    14
45703 #define V_SLVUNEXPACKMSTINT(x) ((x) << S_SLVUNEXPACKMSTINT)
45704 #define F_SLVUNEXPACKMSTINT    V_SLVUNEXPACKMSTINT(1U)
45705 
45706 #define S_SLVUNEXPNACKMSTINT    13
45707 #define V_SLVUNEXPNACKMSTINT(x) ((x) << S_SLVUNEXPNACKMSTINT)
45708 #define F_SLVUNEXPNACKMSTINT    V_SLVUNEXPNACKMSTINT(1U)
45709 
45710 #define S_SLVNOBUSSTOPINT    12
45711 #define V_SLVNOBUSSTOPINT(x) ((x) << S_SLVNOBUSSTOPINT)
45712 #define F_SLVNOBUSSTOPINT    V_SLVNOBUSSTOPINT(1U)
45713 
45714 #define S_SLVNOREPSTARTINT    11
45715 #define V_SLVNOREPSTARTINT(x) ((x) << S_SLVNOREPSTARTINT)
45716 #define F_SLVNOREPSTARTINT    V_SLVNOREPSTARTINT(1U)
45717 
45718 #define S_SLVRXADDRINT    10
45719 #define V_SLVRXADDRINT(x) ((x) << S_SLVRXADDRINT)
45720 #define F_SLVRXADDRINT    V_SLVRXADDRINT(1U)
45721 
45722 #define S_SLVRXPECERRINT    9
45723 #define V_SLVRXPECERRINT(x) ((x) << S_SLVRXPECERRINT)
45724 #define F_SLVRXPECERRINT    V_SLVRXPECERRINT(1U)
45725 
45726 #define S_SLVPREPTOARPINT    8
45727 #define V_SLVPREPTOARPINT(x) ((x) << S_SLVPREPTOARPINT)
45728 #define F_SLVPREPTOARPINT    V_SLVPREPTOARPINT(1U)
45729 
45730 #define S_SLVTIMEOUTINT    7
45731 #define V_SLVTIMEOUTINT(x) ((x) << S_SLVTIMEOUTINT)
45732 #define F_SLVTIMEOUTINT    V_SLVTIMEOUTINT(1U)
45733 
45734 #define S_SLVERRINT    6
45735 #define V_SLVERRINT(x) ((x) << S_SLVERRINT)
45736 #define F_SLVERRINT    V_SLVERRINT(1U)
45737 
45738 #define S_SLVDONEINT    5
45739 #define V_SLVDONEINT(x) ((x) << S_SLVDONEINT)
45740 #define F_SLVDONEINT    V_SLVDONEINT(1U)
45741 
45742 #define S_SLVRXRDYINT    4
45743 #define V_SLVRXRDYINT(x) ((x) << S_SLVRXRDYINT)
45744 #define F_SLVRXRDYINT    V_SLVRXRDYINT(1U)
45745 
45746 #define S_MSTTIMEOUTINT    3
45747 #define V_MSTTIMEOUTINT(x) ((x) << S_MSTTIMEOUTINT)
45748 #define F_MSTTIMEOUTINT    V_MSTTIMEOUTINT(1U)
45749 
45750 #define S_MSTNACKINT    2
45751 #define V_MSTNACKINT(x) ((x) << S_MSTNACKINT)
45752 #define F_MSTNACKINT    V_MSTNACKINT(1U)
45753 
45754 #define S_MSTLOSTARBINT    1
45755 #define V_MSTLOSTARBINT(x) ((x) << S_MSTLOSTARBINT)
45756 #define F_MSTLOSTARBINT    V_MSTLOSTARBINT(1U)
45757 
45758 #define S_MSTDONEINT    0
45759 #define V_MSTDONEINT(x) ((x) << S_MSTDONEINT)
45760 #define F_MSTDONEINT    V_MSTDONEINT(1U)
45761 
45762 #define A_SMB_DEBUG_DATA 0x19094
45763 
45764 #define S_DEBUGDATAH    16
45765 #define M_DEBUGDATAH    0xffffU
45766 #define V_DEBUGDATAH(x) ((x) << S_DEBUGDATAH)
45767 #define G_DEBUGDATAH(x) (((x) >> S_DEBUGDATAH) & M_DEBUGDATAH)
45768 
45769 #define S_DEBUGDATAL    0
45770 #define M_DEBUGDATAL    0xffffU
45771 #define V_DEBUGDATAL(x) ((x) << S_DEBUGDATAL)
45772 #define G_DEBUGDATAL(x) (((x) >> S_DEBUGDATAL) & M_DEBUGDATAL)
45773 
45774 #define A_SMB_PERR_EN 0x19098
45775 
45776 #define S_MSTTXFIFOPERREN    2
45777 #define V_MSTTXFIFOPERREN(x) ((x) << S_MSTTXFIFOPERREN)
45778 #define F_MSTTXFIFOPERREN    V_MSTTXFIFOPERREN(1U)
45779 
45780 #define S_MSTRXFIFOPERREN    1
45781 #define V_MSTRXFIFOPERREN(x) ((x) << S_MSTRXFIFOPERREN)
45782 #define F_MSTRXFIFOPERREN    V_MSTRXFIFOPERREN(1U)
45783 
45784 #define S_SLVFIFOPERREN    0
45785 #define V_SLVFIFOPERREN(x) ((x) << S_SLVFIFOPERREN)
45786 #define F_SLVFIFOPERREN    V_SLVFIFOPERREN(1U)
45787 
45788 #define S_MSTTXFIFO    21
45789 #define V_MSTTXFIFO(x) ((x) << S_MSTTXFIFO)
45790 #define F_MSTTXFIFO    V_MSTTXFIFO(1U)
45791 
45792 #define S_MSTRXFIFO    19
45793 #define V_MSTRXFIFO(x) ((x) << S_MSTRXFIFO)
45794 #define F_MSTRXFIFO    V_MSTRXFIFO(1U)
45795 
45796 #define S_SLVFIFO    18
45797 #define V_SLVFIFO(x) ((x) << S_SLVFIFO)
45798 #define F_SLVFIFO    V_SLVFIFO(1U)
45799 
45800 #define A_SMB_PERR_INJ 0x1909c
45801 
45802 #define S_MSTTXINJDATAERR    3
45803 #define V_MSTTXINJDATAERR(x) ((x) << S_MSTTXINJDATAERR)
45804 #define F_MSTTXINJDATAERR    V_MSTTXINJDATAERR(1U)
45805 
45806 #define S_MSTRXINJDATAERR    2
45807 #define V_MSTRXINJDATAERR(x) ((x) << S_MSTRXINJDATAERR)
45808 #define F_MSTRXINJDATAERR    V_MSTRXINJDATAERR(1U)
45809 
45810 #define S_SLVINJDATAERR    1
45811 #define V_SLVINJDATAERR(x) ((x) << S_SLVINJDATAERR)
45812 #define F_SLVINJDATAERR    V_SLVINJDATAERR(1U)
45813 
45814 #define S_FIFOINJDATAERREN    0
45815 #define V_FIFOINJDATAERREN(x) ((x) << S_FIFOINJDATAERREN)
45816 #define F_FIFOINJDATAERREN    V_FIFOINJDATAERREN(1U)
45817 
45818 #define A_SMB_SLV_ARP_CTL 0x190a0
45819 
45820 #define S_ARPCOMMANDCODE    2
45821 #define M_ARPCOMMANDCODE    0xffU
45822 #define V_ARPCOMMANDCODE(x) ((x) << S_ARPCOMMANDCODE)
45823 #define G_ARPCOMMANDCODE(x) (((x) >> S_ARPCOMMANDCODE) & M_ARPCOMMANDCODE)
45824 
45825 #define S_ARPADDRRES    1
45826 #define V_ARPADDRRES(x) ((x) << S_ARPADDRRES)
45827 #define F_ARPADDRRES    V_ARPADDRRES(1U)
45828 
45829 #define S_ARPADDRVAL    0
45830 #define V_ARPADDRVAL(x) ((x) << S_ARPADDRVAL)
45831 #define F_ARPADDRVAL    V_ARPADDRVAL(1U)
45832 
45833 #define A_SMB_ARP_UDID0 0x190a4
45834 #define A_SMB_ARP_UDID1 0x190a8
45835 
45836 #define S_SUBSYSTEMVENDORID    16
45837 #define M_SUBSYSTEMVENDORID    0xffffU
45838 #define V_SUBSYSTEMVENDORID(x) ((x) << S_SUBSYSTEMVENDORID)
45839 #define G_SUBSYSTEMVENDORID(x) (((x) >> S_SUBSYSTEMVENDORID) & M_SUBSYSTEMVENDORID)
45840 
45841 #define S_SUBSYSTEMDEVICEID    0
45842 #define M_SUBSYSTEMDEVICEID    0xffffU
45843 #define V_SUBSYSTEMDEVICEID(x) ((x) << S_SUBSYSTEMDEVICEID)
45844 #define G_SUBSYSTEMDEVICEID(x) (((x) >> S_SUBSYSTEMDEVICEID) & M_SUBSYSTEMDEVICEID)
45845 
45846 #define A_SMB_ARP_UDID2 0x190ac
45847 
45848 #define S_DEVICEID    16
45849 #define M_DEVICEID    0xffffU
45850 #define V_DEVICEID(x) ((x) << S_DEVICEID)
45851 #define G_DEVICEID(x) (((x) >> S_DEVICEID) & M_DEVICEID)
45852 
45853 #define S_INTERFACE    0
45854 #define M_INTERFACE    0xffffU
45855 #define V_INTERFACE(x) ((x) << S_INTERFACE)
45856 #define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE)
45857 
45858 #define A_SMB_ARP_UDID3 0x190b0
45859 
45860 #define S_DEVICECAP    24
45861 #define M_DEVICECAP    0xffU
45862 #define V_DEVICECAP(x) ((x) << S_DEVICECAP)
45863 #define G_DEVICECAP(x) (((x) >> S_DEVICECAP) & M_DEVICECAP)
45864 
45865 #define S_VERSIONID    16
45866 #define M_VERSIONID    0xffU
45867 #define V_VERSIONID(x) ((x) << S_VERSIONID)
45868 #define G_VERSIONID(x) (((x) >> S_VERSIONID) & M_VERSIONID)
45869 
45870 #define S_VENDORID    0
45871 #define M_VENDORID    0xffffU
45872 #define V_VENDORID(x) ((x) << S_VENDORID)
45873 #define G_VENDORID(x) (((x) >> S_VENDORID) & M_VENDORID)
45874 
45875 #define A_SMB_SLV_AUX_ADDR0 0x190b4
45876 
45877 #define S_AUXADDR0VAL    6
45878 #define V_AUXADDR0VAL(x) ((x) << S_AUXADDR0VAL)
45879 #define F_AUXADDR0VAL    V_AUXADDR0VAL(1U)
45880 
45881 #define S_AUXADDR0    0
45882 #define M_AUXADDR0    0x3fU
45883 #define V_AUXADDR0(x) ((x) << S_AUXADDR0)
45884 #define G_AUXADDR0(x) (((x) >> S_AUXADDR0) & M_AUXADDR0)
45885 
45886 #define A_SMB_SLV_AUX_ADDR1 0x190b8
45887 
45888 #define S_AUXADDR1VAL    6
45889 #define V_AUXADDR1VAL(x) ((x) << S_AUXADDR1VAL)
45890 #define F_AUXADDR1VAL    V_AUXADDR1VAL(1U)
45891 
45892 #define S_AUXADDR1    0
45893 #define M_AUXADDR1    0x3fU
45894 #define V_AUXADDR1(x) ((x) << S_AUXADDR1)
45895 #define G_AUXADDR1(x) (((x) >> S_AUXADDR1) & M_AUXADDR1)
45896 
45897 #define A_SMB_SLV_AUX_ADDR2 0x190bc
45898 
45899 #define S_AUXADDR2VAL    6
45900 #define V_AUXADDR2VAL(x) ((x) << S_AUXADDR2VAL)
45901 #define F_AUXADDR2VAL    V_AUXADDR2VAL(1U)
45902 
45903 #define S_AUXADDR2    0
45904 #define M_AUXADDR2    0x3fU
45905 #define V_AUXADDR2(x) ((x) << S_AUXADDR2)
45906 #define G_AUXADDR2(x) (((x) >> S_AUXADDR2) & M_AUXADDR2)
45907 
45908 #define A_SMB_SLV_AUX_ADDR3 0x190c0
45909 
45910 #define S_AUXADDR3VAL    6
45911 #define V_AUXADDR3VAL(x) ((x) << S_AUXADDR3VAL)
45912 #define F_AUXADDR3VAL    V_AUXADDR3VAL(1U)
45913 
45914 #define S_AUXADDR3    0
45915 #define M_AUXADDR3    0x3fU
45916 #define V_AUXADDR3(x) ((x) << S_AUXADDR3)
45917 #define G_AUXADDR3(x) (((x) >> S_AUXADDR3) & M_AUXADDR3)
45918 
45919 #define A_SMB_COMMAND_CODE0 0x190c4
45920 
45921 #define S_SMBUSCOMMANDCODE0    0
45922 #define M_SMBUSCOMMANDCODE0    0xffU
45923 #define V_SMBUSCOMMANDCODE0(x) ((x) << S_SMBUSCOMMANDCODE0)
45924 #define G_SMBUSCOMMANDCODE0(x) (((x) >> S_SMBUSCOMMANDCODE0) & M_SMBUSCOMMANDCODE0)
45925 
45926 #define A_SMB_COMMAND_CODE1 0x190c8
45927 
45928 #define S_SMBUSCOMMANDCODE1    0
45929 #define M_SMBUSCOMMANDCODE1    0xffU
45930 #define V_SMBUSCOMMANDCODE1(x) ((x) << S_SMBUSCOMMANDCODE1)
45931 #define G_SMBUSCOMMANDCODE1(x) (((x) >> S_SMBUSCOMMANDCODE1) & M_SMBUSCOMMANDCODE1)
45932 
45933 #define A_SMB_COMMAND_CODE2 0x190cc
45934 
45935 #define S_SMBUSCOMMANDCODE2    0
45936 #define M_SMBUSCOMMANDCODE2    0xffU
45937 #define V_SMBUSCOMMANDCODE2(x) ((x) << S_SMBUSCOMMANDCODE2)
45938 #define G_SMBUSCOMMANDCODE2(x) (((x) >> S_SMBUSCOMMANDCODE2) & M_SMBUSCOMMANDCODE2)
45939 
45940 #define A_SMB_COMMAND_CODE3 0x190d0
45941 
45942 #define S_SMBUSCOMMANDCODE3    0
45943 #define M_SMBUSCOMMANDCODE3    0xffU
45944 #define V_SMBUSCOMMANDCODE3(x) ((x) << S_SMBUSCOMMANDCODE3)
45945 #define G_SMBUSCOMMANDCODE3(x) (((x) >> S_SMBUSCOMMANDCODE3) & M_SMBUSCOMMANDCODE3)
45946 
45947 #define A_SMB_COMMAND_CODE4 0x190d4
45948 
45949 #define S_SMBUSCOMMANDCODE4    0
45950 #define M_SMBUSCOMMANDCODE4    0xffU
45951 #define V_SMBUSCOMMANDCODE4(x) ((x) << S_SMBUSCOMMANDCODE4)
45952 #define G_SMBUSCOMMANDCODE4(x) (((x) >> S_SMBUSCOMMANDCODE4) & M_SMBUSCOMMANDCODE4)
45953 
45954 #define A_SMB_COMMAND_CODE5 0x190d8
45955 
45956 #define S_SMBUSCOMMANDCODE5    0
45957 #define M_SMBUSCOMMANDCODE5    0xffU
45958 #define V_SMBUSCOMMANDCODE5(x) ((x) << S_SMBUSCOMMANDCODE5)
45959 #define G_SMBUSCOMMANDCODE5(x) (((x) >> S_SMBUSCOMMANDCODE5) & M_SMBUSCOMMANDCODE5)
45960 
45961 #define A_SMB_COMMAND_CODE6 0x190dc
45962 
45963 #define S_SMBUSCOMMANDCODE6    0
45964 #define M_SMBUSCOMMANDCODE6    0xffU
45965 #define V_SMBUSCOMMANDCODE6(x) ((x) << S_SMBUSCOMMANDCODE6)
45966 #define G_SMBUSCOMMANDCODE6(x) (((x) >> S_SMBUSCOMMANDCODE6) & M_SMBUSCOMMANDCODE6)
45967 
45968 #define A_SMB_COMMAND_CODE7 0x190e0
45969 
45970 #define S_SMBUSCOMMANDCODE7    0
45971 #define M_SMBUSCOMMANDCODE7    0xffU
45972 #define V_SMBUSCOMMANDCODE7(x) ((x) << S_SMBUSCOMMANDCODE7)
45973 #define G_SMBUSCOMMANDCODE7(x) (((x) >> S_SMBUSCOMMANDCODE7) & M_SMBUSCOMMANDCODE7)
45974 
45975 #define A_SMB_MICRO_CNT_CLK_CFG 0x190e4
45976 
45977 #define S_MACROCNTCLKCFG    8
45978 #define M_MACROCNTCLKCFG    0x1fU
45979 #define V_MACROCNTCLKCFG(x) ((x) << S_MACROCNTCLKCFG)
45980 #define G_MACROCNTCLKCFG(x) (((x) >> S_MACROCNTCLKCFG) & M_MACROCNTCLKCFG)
45981 
45982 #define S_MICROCNTCLKCFG    0
45983 #define M_MICROCNTCLKCFG    0xffU
45984 #define V_MICROCNTCLKCFG(x) ((x) << S_MICROCNTCLKCFG)
45985 #define G_MICROCNTCLKCFG(x) (((x) >> S_MICROCNTCLKCFG) & M_MICROCNTCLKCFG)
45986 
45987 #define A_SMB_CTL_STATUS 0x190e8
45988 
45989 #define S_MSTBUSBUSY    2
45990 #define V_MSTBUSBUSY(x) ((x) << S_MSTBUSBUSY)
45991 #define F_MSTBUSBUSY    V_MSTBUSBUSY(1U)
45992 
45993 #define S_SLVBUSBUSY    1
45994 #define V_SLVBUSBUSY(x) ((x) << S_SLVBUSBUSY)
45995 #define F_SLVBUSBUSY    V_SLVBUSBUSY(1U)
45996 
45997 #define S_BUSBUSY    0
45998 #define V_BUSBUSY(x) ((x) << S_BUSBUSY)
45999 #define F_BUSBUSY    V_BUSBUSY(1U)
46000 
46001 /* registers for module I2CM */
46002 #define I2CM_BASE_ADDR 0x190f0
46003 
46004 #define A_I2CM_CFG 0x190f0
46005 
46006 #define S_I2C_CLKDIV    0
46007 #define M_I2C_CLKDIV    0xfffU
46008 #define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV)
46009 #define G_I2C_CLKDIV(x) (((x) >> S_I2C_CLKDIV) & M_I2C_CLKDIV)
46010 
46011 #define S_I2C_CLKDIV16B    0
46012 #define M_I2C_CLKDIV16B    0xffffU
46013 #define V_I2C_CLKDIV16B(x) ((x) << S_I2C_CLKDIV16B)
46014 #define G_I2C_CLKDIV16B(x) (((x) >> S_I2C_CLKDIV16B) & M_I2C_CLKDIV16B)
46015 
46016 #define A_I2CM_DATA 0x190f4
46017 
46018 #define S_I2C_DATA    0
46019 #define M_I2C_DATA    0xffU
46020 #define V_I2C_DATA(x) ((x) << S_I2C_DATA)
46021 #define G_I2C_DATA(x) (((x) >> S_I2C_DATA) & M_I2C_DATA)
46022 
46023 #define A_I2CM_OP 0x190f8
46024 
46025 #define S_I2C_ACK    30
46026 #define V_I2C_ACK(x) ((x) << S_I2C_ACK)
46027 #define F_I2C_ACK    V_I2C_ACK(1U)
46028 
46029 #define S_I2C_CONT    1
46030 #define V_I2C_CONT(x) ((x) << S_I2C_CONT)
46031 #define F_I2C_CONT    V_I2C_CONT(1U)
46032 
46033 #define S_OP    0
46034 #define V_OP(x) ((x) << S_OP)
46035 #define F_OP    V_OP(1U)
46036 
46037 /* registers for module MI */
46038 #define MI_BASE_ADDR 0x19100
46039 
46040 #define A_MI_CFG 0x19100
46041 
46042 #define S_T4_ST    14
46043 #define V_T4_ST(x) ((x) << S_T4_ST)
46044 #define F_T4_ST    V_T4_ST(1U)
46045 
46046 #define S_CLKDIV    5
46047 #define M_CLKDIV    0xffU
46048 #define V_CLKDIV(x) ((x) << S_CLKDIV)
46049 #define G_CLKDIV(x) (((x) >> S_CLKDIV) & M_CLKDIV)
46050 
46051 #define S_ST    3
46052 #define M_ST    0x3U
46053 #define V_ST(x) ((x) << S_ST)
46054 #define G_ST(x) (((x) >> S_ST) & M_ST)
46055 
46056 #define S_PREEN    2
46057 #define V_PREEN(x) ((x) << S_PREEN)
46058 #define F_PREEN    V_PREEN(1U)
46059 
46060 #define S_MDIINV    1
46061 #define V_MDIINV(x) ((x) << S_MDIINV)
46062 #define F_MDIINV    V_MDIINV(1U)
46063 
46064 #define S_MDIO_1P2V_SEL    0
46065 #define V_MDIO_1P2V_SEL(x) ((x) << S_MDIO_1P2V_SEL)
46066 #define F_MDIO_1P2V_SEL    V_MDIO_1P2V_SEL(1U)
46067 
46068 #define A_MI_ADDR 0x19104
46069 
46070 #define S_PHYADDR    5
46071 #define M_PHYADDR    0x1fU
46072 #define V_PHYADDR(x) ((x) << S_PHYADDR)
46073 #define G_PHYADDR(x) (((x) >> S_PHYADDR) & M_PHYADDR)
46074 
46075 #define S_REGADDR    0
46076 #define M_REGADDR    0x1fU
46077 #define V_REGADDR(x) ((x) << S_REGADDR)
46078 #define G_REGADDR(x) (((x) >> S_REGADDR) & M_REGADDR)
46079 
46080 #define A_MI_DATA 0x19108
46081 
46082 #define S_MDIDATA    0
46083 #define M_MDIDATA    0xffffU
46084 #define V_MDIDATA(x) ((x) << S_MDIDATA)
46085 #define G_MDIDATA(x) (((x) >> S_MDIDATA) & M_MDIDATA)
46086 
46087 #define A_MI_OP 0x1910c
46088 
46089 #define S_INC    2
46090 #define V_INC(x) ((x) << S_INC)
46091 #define F_INC    V_INC(1U)
46092 
46093 #define S_MDIOP    0
46094 #define M_MDIOP    0x3U
46095 #define V_MDIOP(x) ((x) << S_MDIOP)
46096 #define G_MDIOP(x) (((x) >> S_MDIOP) & M_MDIOP)
46097 
46098 /* registers for module UART */
46099 #define UART_BASE_ADDR 0x19110
46100 
46101 #define A_UART_CONFIG 0x19110
46102 
46103 #define S_STOPBITS    22
46104 #define M_STOPBITS    0x3U
46105 #define V_STOPBITS(x) ((x) << S_STOPBITS)
46106 #define G_STOPBITS(x) (((x) >> S_STOPBITS) & M_STOPBITS)
46107 
46108 #define S_PARITY    20
46109 #define M_PARITY    0x3U
46110 #define V_PARITY(x) ((x) << S_PARITY)
46111 #define G_PARITY(x) (((x) >> S_PARITY) & M_PARITY)
46112 
46113 #define S_DATABITS    16
46114 #define M_DATABITS    0xfU
46115 #define V_DATABITS(x) ((x) << S_DATABITS)
46116 #define G_DATABITS(x) (((x) >> S_DATABITS) & M_DATABITS)
46117 
46118 #define S_UART_CLKDIV    0
46119 #define M_UART_CLKDIV    0xfffU
46120 #define V_UART_CLKDIV(x) ((x) << S_UART_CLKDIV)
46121 #define G_UART_CLKDIV(x) (((x) >> S_UART_CLKDIV) & M_UART_CLKDIV)
46122 
46123 #define S_T7_STOPBITS    25
46124 #define M_T7_STOPBITS    0x3U
46125 #define V_T7_STOPBITS(x) ((x) << S_T7_STOPBITS)
46126 #define G_T7_STOPBITS(x) (((x) >> S_T7_STOPBITS) & M_T7_STOPBITS)
46127 
46128 #define S_T7_PARITY    23
46129 #define M_T7_PARITY    0x3U
46130 #define V_T7_PARITY(x) ((x) << S_T7_PARITY)
46131 #define G_T7_PARITY(x) (((x) >> S_T7_PARITY) & M_T7_PARITY)
46132 
46133 #define S_T7_DATABITS    19
46134 #define M_T7_DATABITS    0xfU
46135 #define V_T7_DATABITS(x) ((x) << S_T7_DATABITS)
46136 #define G_T7_DATABITS(x) (((x) >> S_T7_DATABITS) & M_T7_DATABITS)
46137 
46138 #define S_T7_UART_CLKDIV    0
46139 #define M_T7_UART_CLKDIV    0x3ffffU
46140 #define V_T7_UART_CLKDIV(x) ((x) << S_T7_UART_CLKDIV)
46141 #define G_T7_UART_CLKDIV(x) (((x) >> S_T7_UART_CLKDIV) & M_T7_UART_CLKDIV)
46142 
46143 /* registers for module PMU */
46144 #define PMU_BASE_ADDR 0x19120
46145 
46146 #define A_PMU_PART_CG_PWRMODE 0x19120
46147 
46148 #define S_TPPARTCGEN    14
46149 #define V_TPPARTCGEN(x) ((x) << S_TPPARTCGEN)
46150 #define F_TPPARTCGEN    V_TPPARTCGEN(1U)
46151 
46152 #define S_PDPPARTCGEN    13
46153 #define V_PDPPARTCGEN(x) ((x) << S_PDPPARTCGEN)
46154 #define F_PDPPARTCGEN    V_PDPPARTCGEN(1U)
46155 
46156 #define S_PCIEPARTCGEN    12
46157 #define V_PCIEPARTCGEN(x) ((x) << S_PCIEPARTCGEN)
46158 #define F_PCIEPARTCGEN    V_PCIEPARTCGEN(1U)
46159 
46160 #define S_EDC1PARTCGEN    11
46161 #define V_EDC1PARTCGEN(x) ((x) << S_EDC1PARTCGEN)
46162 #define F_EDC1PARTCGEN    V_EDC1PARTCGEN(1U)
46163 
46164 #define S_MCPARTCGEN    10
46165 #define V_MCPARTCGEN(x) ((x) << S_MCPARTCGEN)
46166 #define F_MCPARTCGEN    V_MCPARTCGEN(1U)
46167 
46168 #define S_EDC0PARTCGEN    9
46169 #define V_EDC0PARTCGEN(x) ((x) << S_EDC0PARTCGEN)
46170 #define F_EDC0PARTCGEN    V_EDC0PARTCGEN(1U)
46171 
46172 #define S_LEPARTCGEN    8
46173 #define V_LEPARTCGEN(x) ((x) << S_LEPARTCGEN)
46174 #define F_LEPARTCGEN    V_LEPARTCGEN(1U)
46175 
46176 #define S_INITPOWERMODE    0
46177 #define M_INITPOWERMODE    0x3U
46178 #define V_INITPOWERMODE(x) ((x) << S_INITPOWERMODE)
46179 #define G_INITPOWERMODE(x) (((x) >> S_INITPOWERMODE) & M_INITPOWERMODE)
46180 
46181 #define S_SGE_PART_CGEN    19
46182 #define V_SGE_PART_CGEN(x) ((x) << S_SGE_PART_CGEN)
46183 #define F_SGE_PART_CGEN    V_SGE_PART_CGEN(1U)
46184 
46185 #define S_PDP_PART_CGEN    18
46186 #define V_PDP_PART_CGEN(x) ((x) << S_PDP_PART_CGEN)
46187 #define F_PDP_PART_CGEN    V_PDP_PART_CGEN(1U)
46188 
46189 #define S_TP_PART_CGEN    17
46190 #define V_TP_PART_CGEN(x) ((x) << S_TP_PART_CGEN)
46191 #define F_TP_PART_CGEN    V_TP_PART_CGEN(1U)
46192 
46193 #define S_EDC0_PART_CGEN    16
46194 #define V_EDC0_PART_CGEN(x) ((x) << S_EDC0_PART_CGEN)
46195 #define F_EDC0_PART_CGEN    V_EDC0_PART_CGEN(1U)
46196 
46197 #define S_EDC1_PART_CGEN    15
46198 #define V_EDC1_PART_CGEN(x) ((x) << S_EDC1_PART_CGEN)
46199 #define F_EDC1_PART_CGEN    V_EDC1_PART_CGEN(1U)
46200 
46201 #define S_LE_PART_CGEN    14
46202 #define V_LE_PART_CGEN(x) ((x) << S_LE_PART_CGEN)
46203 #define F_LE_PART_CGEN    V_LE_PART_CGEN(1U)
46204 
46205 #define S_MA_PART_CGEN    13
46206 #define V_MA_PART_CGEN(x) ((x) << S_MA_PART_CGEN)
46207 #define F_MA_PART_CGEN    V_MA_PART_CGEN(1U)
46208 
46209 #define S_MC0_PART_CGEN    12
46210 #define V_MC0_PART_CGEN(x) ((x) << S_MC0_PART_CGEN)
46211 #define F_MC0_PART_CGEN    V_MC0_PART_CGEN(1U)
46212 
46213 #define S_MC1_PART_CGEN    11
46214 #define V_MC1_PART_CGEN(x) ((x) << S_MC1_PART_CGEN)
46215 #define F_MC1_PART_CGEN    V_MC1_PART_CGEN(1U)
46216 
46217 #define S_PCIE_PART_CGEN    10
46218 #define V_PCIE_PART_CGEN(x) ((x) << S_PCIE_PART_CGEN)
46219 #define F_PCIE_PART_CGEN    V_PCIE_PART_CGEN(1U)
46220 
46221 #define S_PL_DIS_PRTY_CHK    20
46222 #define V_PL_DIS_PRTY_CHK(x) ((x) << S_PL_DIS_PRTY_CHK)
46223 #define F_PL_DIS_PRTY_CHK    V_PL_DIS_PRTY_CHK(1U)
46224 
46225 #define S_ARM_PART_CGEN    19
46226 #define V_ARM_PART_CGEN(x) ((x) << S_ARM_PART_CGEN)
46227 #define F_ARM_PART_CGEN    V_ARM_PART_CGEN(1U)
46228 
46229 #define S_CRYPTO_PART_CGEN    14
46230 #define V_CRYPTO_PART_CGEN(x) ((x) << S_CRYPTO_PART_CGEN)
46231 #define F_CRYPTO_PART_CGEN    V_CRYPTO_PART_CGEN(1U)
46232 
46233 #define S_NVME_PART_CGEN    9
46234 #define V_NVME_PART_CGEN(x) ((x) << S_NVME_PART_CGEN)
46235 #define F_NVME_PART_CGEN    V_NVME_PART_CGEN(1U)
46236 
46237 #define S_XP10_PART_CGEN    8
46238 #define V_XP10_PART_CGEN(x) ((x) << S_XP10_PART_CGEN)
46239 #define F_XP10_PART_CGEN    V_XP10_PART_CGEN(1U)
46240 
46241 #define S_GPEX_PART_CGEN    7
46242 #define V_GPEX_PART_CGEN(x) ((x) << S_GPEX_PART_CGEN)
46243 #define F_GPEX_PART_CGEN    V_GPEX_PART_CGEN(1U)
46244 
46245 #define A_PMU_SLEEPMODE_WAKEUP 0x19124
46246 
46247 #define S_HWWAKEUPEN    5
46248 #define V_HWWAKEUPEN(x) ((x) << S_HWWAKEUPEN)
46249 #define F_HWWAKEUPEN    V_HWWAKEUPEN(1U)
46250 
46251 #define S_PORT3SLEEPMODE    4
46252 #define V_PORT3SLEEPMODE(x) ((x) << S_PORT3SLEEPMODE)
46253 #define F_PORT3SLEEPMODE    V_PORT3SLEEPMODE(1U)
46254 
46255 #define S_PORT2SLEEPMODE    3
46256 #define V_PORT2SLEEPMODE(x) ((x) << S_PORT2SLEEPMODE)
46257 #define F_PORT2SLEEPMODE    V_PORT2SLEEPMODE(1U)
46258 
46259 #define S_PORT1SLEEPMODE    2
46260 #define V_PORT1SLEEPMODE(x) ((x) << S_PORT1SLEEPMODE)
46261 #define F_PORT1SLEEPMODE    V_PORT1SLEEPMODE(1U)
46262 
46263 #define S_PORT0SLEEPMODE    1
46264 #define V_PORT0SLEEPMODE(x) ((x) << S_PORT0SLEEPMODE)
46265 #define F_PORT0SLEEPMODE    V_PORT0SLEEPMODE(1U)
46266 
46267 #define S_WAKEUP    0
46268 #define V_WAKEUP(x) ((x) << S_WAKEUP)
46269 #define F_WAKEUP    V_WAKEUP(1U)
46270 
46271 #define S_GLOBALDEEPSLEEPEN    6
46272 #define V_GLOBALDEEPSLEEPEN(x) ((x) << S_GLOBALDEEPSLEEPEN)
46273 #define F_GLOBALDEEPSLEEPEN    V_GLOBALDEEPSLEEPEN(1U)
46274 
46275 /* registers for module ULP_RX */
46276 #define ULP_RX_BASE_ADDR 0x19150
46277 
46278 #define A_ULP_RX_CTL 0x19150
46279 
46280 #define S_PCMD1THRESHOLD    24
46281 #define M_PCMD1THRESHOLD    0xffU
46282 #define V_PCMD1THRESHOLD(x) ((x) << S_PCMD1THRESHOLD)
46283 #define G_PCMD1THRESHOLD(x) (((x) >> S_PCMD1THRESHOLD) & M_PCMD1THRESHOLD)
46284 
46285 #define S_PCMD0THRESHOLD    16
46286 #define M_PCMD0THRESHOLD    0xffU
46287 #define V_PCMD0THRESHOLD(x) ((x) << S_PCMD0THRESHOLD)
46288 #define G_PCMD0THRESHOLD(x) (((x) >> S_PCMD0THRESHOLD) & M_PCMD0THRESHOLD)
46289 
46290 #define S_DISABLE_0B_STAG_ERR    14
46291 #define V_DISABLE_0B_STAG_ERR(x) ((x) << S_DISABLE_0B_STAG_ERR)
46292 #define F_DISABLE_0B_STAG_ERR    V_DISABLE_0B_STAG_ERR(1U)
46293 
46294 #define S_RDMA_0B_WR_OPCODE    10
46295 #define M_RDMA_0B_WR_OPCODE    0xfU
46296 #define V_RDMA_0B_WR_OPCODE(x) ((x) << S_RDMA_0B_WR_OPCODE)
46297 #define G_RDMA_0B_WR_OPCODE(x) (((x) >> S_RDMA_0B_WR_OPCODE) & M_RDMA_0B_WR_OPCODE)
46298 
46299 #define S_RDMA_0B_WR_PASS    9
46300 #define V_RDMA_0B_WR_PASS(x) ((x) << S_RDMA_0B_WR_PASS)
46301 #define F_RDMA_0B_WR_PASS    V_RDMA_0B_WR_PASS(1U)
46302 
46303 #define S_STAG_RQE    8
46304 #define V_STAG_RQE(x) ((x) << S_STAG_RQE)
46305 #define F_STAG_RQE    V_STAG_RQE(1U)
46306 
46307 #define S_RDMA_STATE_EN    7
46308 #define V_RDMA_STATE_EN(x) ((x) << S_RDMA_STATE_EN)
46309 #define F_RDMA_STATE_EN    V_RDMA_STATE_EN(1U)
46310 
46311 #define S_CRC1_EN    6
46312 #define V_CRC1_EN(x) ((x) << S_CRC1_EN)
46313 #define F_CRC1_EN    V_CRC1_EN(1U)
46314 
46315 #define S_RDMA_0B_WR_CQE    5
46316 #define V_RDMA_0B_WR_CQE(x) ((x) << S_RDMA_0B_WR_CQE)
46317 #define F_RDMA_0B_WR_CQE    V_RDMA_0B_WR_CQE(1U)
46318 
46319 #define S_PCIE_ATRB_EN    4
46320 #define V_PCIE_ATRB_EN(x) ((x) << S_PCIE_ATRB_EN)
46321 #define F_PCIE_ATRB_EN    V_PCIE_ATRB_EN(1U)
46322 
46323 #define S_RDMA_PERMISSIVE_MODE    3
46324 #define V_RDMA_PERMISSIVE_MODE(x) ((x) << S_RDMA_PERMISSIVE_MODE)
46325 #define F_RDMA_PERMISSIVE_MODE    V_RDMA_PERMISSIVE_MODE(1U)
46326 
46327 #define S_PAGEPODME    2
46328 #define V_PAGEPODME(x) ((x) << S_PAGEPODME)
46329 #define F_PAGEPODME    V_PAGEPODME(1U)
46330 
46331 #define S_ISCSITAGTCB    1
46332 #define V_ISCSITAGTCB(x) ((x) << S_ISCSITAGTCB)
46333 #define F_ISCSITAGTCB    V_ISCSITAGTCB(1U)
46334 
46335 #define S_TDDPTAGTCB    0
46336 #define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB)
46337 #define F_TDDPTAGTCB    V_TDDPTAGTCB(1U)
46338 
46339 #define S_ISCSI_PAGE_SIZE_CHK_ENB    31
46340 #define V_ISCSI_PAGE_SIZE_CHK_ENB(x) ((x) << S_ISCSI_PAGE_SIZE_CHK_ENB)
46341 #define F_ISCSI_PAGE_SIZE_CHK_ENB    V_ISCSI_PAGE_SIZE_CHK_ENB(1U)
46342 
46343 #define S_RDMA_0B_WR_OPCODE_HI    29
46344 #define V_RDMA_0B_WR_OPCODE_HI(x) ((x) << S_RDMA_0B_WR_OPCODE_HI)
46345 #define F_RDMA_0B_WR_OPCODE_HI    V_RDMA_0B_WR_OPCODE_HI(1U)
46346 
46347 #define S_RDMA_IMMEDIATE_CQE    28
46348 #define V_RDMA_IMMEDIATE_CQE(x) ((x) << S_RDMA_IMMEDIATE_CQE)
46349 #define F_RDMA_IMMEDIATE_CQE    V_RDMA_IMMEDIATE_CQE(1U)
46350 
46351 #define S_RDMA_ATOMIC_WR_RSP_CQE    27
46352 #define V_RDMA_ATOMIC_WR_RSP_CQE(x) ((x) << S_RDMA_ATOMIC_WR_RSP_CQE)
46353 #define F_RDMA_ATOMIC_WR_RSP_CQE    V_RDMA_ATOMIC_WR_RSP_CQE(1U)
46354 
46355 #define S_RDMA_VERIFY_RSP_FLUSH    26
46356 #define V_RDMA_VERIFY_RSP_FLUSH(x) ((x) << S_RDMA_VERIFY_RSP_FLUSH)
46357 #define F_RDMA_VERIFY_RSP_FLUSH    V_RDMA_VERIFY_RSP_FLUSH(1U)
46358 
46359 #define S_RDMA_VERIFY_RSP_CQE    25
46360 #define V_RDMA_VERIFY_RSP_CQE(x) ((x) << S_RDMA_VERIFY_RSP_CQE)
46361 #define F_RDMA_VERIFY_RSP_CQE    V_RDMA_VERIFY_RSP_CQE(1U)
46362 
46363 #define S_RDMA_FLUSH_RSP_CQE    24
46364 #define V_RDMA_FLUSH_RSP_CQE(x) ((x) << S_RDMA_FLUSH_RSP_CQE)
46365 #define F_RDMA_FLUSH_RSP_CQE    V_RDMA_FLUSH_RSP_CQE(1U)
46366 
46367 #define S_RDMA_ATOMIC_RSP_CQE    23
46368 #define V_RDMA_ATOMIC_RSP_CQE(x) ((x) << S_RDMA_ATOMIC_RSP_CQE)
46369 #define F_RDMA_ATOMIC_RSP_CQE    V_RDMA_ATOMIC_RSP_CQE(1U)
46370 
46371 #define S_T7_TPT_EXTENSION_MODE    22
46372 #define V_T7_TPT_EXTENSION_MODE(x) ((x) << S_T7_TPT_EXTENSION_MODE)
46373 #define F_T7_TPT_EXTENSION_MODE    V_T7_TPT_EXTENSION_MODE(1U)
46374 
46375 #define S_NVME_TCP_DDP_VAL_EN    21
46376 #define V_NVME_TCP_DDP_VAL_EN(x) ((x) << S_NVME_TCP_DDP_VAL_EN)
46377 #define F_NVME_TCP_DDP_VAL_EN    V_NVME_TCP_DDP_VAL_EN(1U)
46378 
46379 #define S_NVME_TCP_REMOVE_HDR_CRC    20
46380 #define V_NVME_TCP_REMOVE_HDR_CRC(x) ((x) << S_NVME_TCP_REMOVE_HDR_CRC)
46381 #define F_NVME_TCP_REMOVE_HDR_CRC    V_NVME_TCP_REMOVE_HDR_CRC(1U)
46382 
46383 #define S_NVME_TCP_LAST_PDU_CHECK_ENB    19
46384 #define V_NVME_TCP_LAST_PDU_CHECK_ENB(x) ((x) << S_NVME_TCP_LAST_PDU_CHECK_ENB)
46385 #define F_NVME_TCP_LAST_PDU_CHECK_ENB    V_NVME_TCP_LAST_PDU_CHECK_ENB(1U)
46386 
46387 #define S_NVME_TCP_OFFSET_SUBMODE    17
46388 #define M_NVME_TCP_OFFSET_SUBMODE    0x3U
46389 #define V_NVME_TCP_OFFSET_SUBMODE(x) ((x) << S_NVME_TCP_OFFSET_SUBMODE)
46390 #define G_NVME_TCP_OFFSET_SUBMODE(x) (((x) >> S_NVME_TCP_OFFSET_SUBMODE) & M_NVME_TCP_OFFSET_SUBMODE)
46391 
46392 #define S_NVME_TCP_OFFSET_MODE    16
46393 #define V_NVME_TCP_OFFSET_MODE(x) ((x) << S_NVME_TCP_OFFSET_MODE)
46394 #define F_NVME_TCP_OFFSET_MODE    V_NVME_TCP_OFFSET_MODE(1U)
46395 
46396 #define S_QPID_CHECK_DISABLE_FOR_SEND    15
46397 #define V_QPID_CHECK_DISABLE_FOR_SEND(x) ((x) << S_QPID_CHECK_DISABLE_FOR_SEND)
46398 #define F_QPID_CHECK_DISABLE_FOR_SEND    V_QPID_CHECK_DISABLE_FOR_SEND(1U)
46399 
46400 #define S_RDMA_0B_WR_OPCODE_LO    10
46401 #define M_RDMA_0B_WR_OPCODE_LO    0xfU
46402 #define V_RDMA_0B_WR_OPCODE_LO(x) ((x) << S_RDMA_0B_WR_OPCODE_LO)
46403 #define G_RDMA_0B_WR_OPCODE_LO(x) (((x) >> S_RDMA_0B_WR_OPCODE_LO) & M_RDMA_0B_WR_OPCODE_LO)
46404 
46405 #define A_ULP_RX_INT_ENABLE 0x19154
46406 
46407 #define S_ENABLE_CTX_1    24
46408 #define V_ENABLE_CTX_1(x) ((x) << S_ENABLE_CTX_1)
46409 #define F_ENABLE_CTX_1    V_ENABLE_CTX_1(1U)
46410 
46411 #define S_ENABLE_CTX_0    23
46412 #define V_ENABLE_CTX_0(x) ((x) << S_ENABLE_CTX_0)
46413 #define F_ENABLE_CTX_0    V_ENABLE_CTX_0(1U)
46414 
46415 #define S_ENABLE_FF    22
46416 #define V_ENABLE_FF(x) ((x) << S_ENABLE_FF)
46417 #define F_ENABLE_FF    V_ENABLE_FF(1U)
46418 
46419 #define S_ENABLE_APF_1    21
46420 #define V_ENABLE_APF_1(x) ((x) << S_ENABLE_APF_1)
46421 #define F_ENABLE_APF_1    V_ENABLE_APF_1(1U)
46422 
46423 #define S_ENABLE_APF_0    20
46424 #define V_ENABLE_APF_0(x) ((x) << S_ENABLE_APF_0)
46425 #define F_ENABLE_APF_0    V_ENABLE_APF_0(1U)
46426 
46427 #define S_ENABLE_AF_1    19
46428 #define V_ENABLE_AF_1(x) ((x) << S_ENABLE_AF_1)
46429 #define F_ENABLE_AF_1    V_ENABLE_AF_1(1U)
46430 
46431 #define S_ENABLE_AF_0    18
46432 #define V_ENABLE_AF_0(x) ((x) << S_ENABLE_AF_0)
46433 #define F_ENABLE_AF_0    V_ENABLE_AF_0(1U)
46434 
46435 #define S_ENABLE_DDPDF_1    17
46436 #define V_ENABLE_DDPDF_1(x) ((x) << S_ENABLE_DDPDF_1)
46437 #define F_ENABLE_DDPDF_1    V_ENABLE_DDPDF_1(1U)
46438 
46439 #define S_ENABLE_DDPMF_1    16
46440 #define V_ENABLE_DDPMF_1(x) ((x) << S_ENABLE_DDPMF_1)
46441 #define F_ENABLE_DDPMF_1    V_ENABLE_DDPMF_1(1U)
46442 
46443 #define S_ENABLE_MEMRF_1    15
46444 #define V_ENABLE_MEMRF_1(x) ((x) << S_ENABLE_MEMRF_1)
46445 #define F_ENABLE_MEMRF_1    V_ENABLE_MEMRF_1(1U)
46446 
46447 #define S_ENABLE_PRSDF_1    14
46448 #define V_ENABLE_PRSDF_1(x) ((x) << S_ENABLE_PRSDF_1)
46449 #define F_ENABLE_PRSDF_1    V_ENABLE_PRSDF_1(1U)
46450 
46451 #define S_ENABLE_DDPDF_0    13
46452 #define V_ENABLE_DDPDF_0(x) ((x) << S_ENABLE_DDPDF_0)
46453 #define F_ENABLE_DDPDF_0    V_ENABLE_DDPDF_0(1U)
46454 
46455 #define S_ENABLE_DDPMF_0    12
46456 #define V_ENABLE_DDPMF_0(x) ((x) << S_ENABLE_DDPMF_0)
46457 #define F_ENABLE_DDPMF_0    V_ENABLE_DDPMF_0(1U)
46458 
46459 #define S_ENABLE_MEMRF_0    11
46460 #define V_ENABLE_MEMRF_0(x) ((x) << S_ENABLE_MEMRF_0)
46461 #define F_ENABLE_MEMRF_0    V_ENABLE_MEMRF_0(1U)
46462 
46463 #define S_ENABLE_PRSDF_0    10
46464 #define V_ENABLE_PRSDF_0(x) ((x) << S_ENABLE_PRSDF_0)
46465 #define F_ENABLE_PRSDF_0    V_ENABLE_PRSDF_0(1U)
46466 
46467 #define S_ENABLE_PCMDF_1    9
46468 #define V_ENABLE_PCMDF_1(x) ((x) << S_ENABLE_PCMDF_1)
46469 #define F_ENABLE_PCMDF_1    V_ENABLE_PCMDF_1(1U)
46470 
46471 #define S_ENABLE_TPTCF_1    8
46472 #define V_ENABLE_TPTCF_1(x) ((x) << S_ENABLE_TPTCF_1)
46473 #define F_ENABLE_TPTCF_1    V_ENABLE_TPTCF_1(1U)
46474 
46475 #define S_ENABLE_DDPCF_1    7
46476 #define V_ENABLE_DDPCF_1(x) ((x) << S_ENABLE_DDPCF_1)
46477 #define F_ENABLE_DDPCF_1    V_ENABLE_DDPCF_1(1U)
46478 
46479 #define S_ENABLE_MPARF_1    6
46480 #define V_ENABLE_MPARF_1(x) ((x) << S_ENABLE_MPARF_1)
46481 #define F_ENABLE_MPARF_1    V_ENABLE_MPARF_1(1U)
46482 
46483 #define S_ENABLE_MPARC_1    5
46484 #define V_ENABLE_MPARC_1(x) ((x) << S_ENABLE_MPARC_1)
46485 #define F_ENABLE_MPARC_1    V_ENABLE_MPARC_1(1U)
46486 
46487 #define S_ENABLE_PCMDF_0    4
46488 #define V_ENABLE_PCMDF_0(x) ((x) << S_ENABLE_PCMDF_0)
46489 #define F_ENABLE_PCMDF_0    V_ENABLE_PCMDF_0(1U)
46490 
46491 #define S_ENABLE_TPTCF_0    3
46492 #define V_ENABLE_TPTCF_0(x) ((x) << S_ENABLE_TPTCF_0)
46493 #define F_ENABLE_TPTCF_0    V_ENABLE_TPTCF_0(1U)
46494 
46495 #define S_ENABLE_DDPCF_0    2
46496 #define V_ENABLE_DDPCF_0(x) ((x) << S_ENABLE_DDPCF_0)
46497 #define F_ENABLE_DDPCF_0    V_ENABLE_DDPCF_0(1U)
46498 
46499 #define S_ENABLE_MPARF_0    1
46500 #define V_ENABLE_MPARF_0(x) ((x) << S_ENABLE_MPARF_0)
46501 #define F_ENABLE_MPARF_0    V_ENABLE_MPARF_0(1U)
46502 
46503 #define S_ENABLE_MPARC_0    0
46504 #define V_ENABLE_MPARC_0(x) ((x) << S_ENABLE_MPARC_0)
46505 #define F_ENABLE_MPARC_0    V_ENABLE_MPARC_0(1U)
46506 
46507 #define S_SE_CNT_MISMATCH_1    26
46508 #define V_SE_CNT_MISMATCH_1(x) ((x) << S_SE_CNT_MISMATCH_1)
46509 #define F_SE_CNT_MISMATCH_1    V_SE_CNT_MISMATCH_1(1U)
46510 
46511 #define S_SE_CNT_MISMATCH_0    25
46512 #define V_SE_CNT_MISMATCH_0(x) ((x) << S_SE_CNT_MISMATCH_0)
46513 #define F_SE_CNT_MISMATCH_0    V_SE_CNT_MISMATCH_0(1U)
46514 
46515 #define S_CERR_PCMD_FIFO_3    19
46516 #define V_CERR_PCMD_FIFO_3(x) ((x) << S_CERR_PCMD_FIFO_3)
46517 #define F_CERR_PCMD_FIFO_3    V_CERR_PCMD_FIFO_3(1U)
46518 
46519 #define S_CERR_PCMD_FIFO_2    18
46520 #define V_CERR_PCMD_FIFO_2(x) ((x) << S_CERR_PCMD_FIFO_2)
46521 #define F_CERR_PCMD_FIFO_2    V_CERR_PCMD_FIFO_2(1U)
46522 
46523 #define S_CERR_PCMD_FIFO_1    17
46524 #define V_CERR_PCMD_FIFO_1(x) ((x) << S_CERR_PCMD_FIFO_1)
46525 #define F_CERR_PCMD_FIFO_1    V_CERR_PCMD_FIFO_1(1U)
46526 
46527 #define S_CERR_PCMD_FIFO_0    16
46528 #define V_CERR_PCMD_FIFO_0(x) ((x) << S_CERR_PCMD_FIFO_0)
46529 #define F_CERR_PCMD_FIFO_0    V_CERR_PCMD_FIFO_0(1U)
46530 
46531 #define S_CERR_DATA_FIFO_3    15
46532 #define V_CERR_DATA_FIFO_3(x) ((x) << S_CERR_DATA_FIFO_3)
46533 #define F_CERR_DATA_FIFO_3    V_CERR_DATA_FIFO_3(1U)
46534 
46535 #define S_CERR_DATA_FIFO_2    14
46536 #define V_CERR_DATA_FIFO_2(x) ((x) << S_CERR_DATA_FIFO_2)
46537 #define F_CERR_DATA_FIFO_2    V_CERR_DATA_FIFO_2(1U)
46538 
46539 #define S_CERR_DATA_FIFO_1    13
46540 #define V_CERR_DATA_FIFO_1(x) ((x) << S_CERR_DATA_FIFO_1)
46541 #define F_CERR_DATA_FIFO_1    V_CERR_DATA_FIFO_1(1U)
46542 
46543 #define S_CERR_DATA_FIFO_0    12
46544 #define V_CERR_DATA_FIFO_0(x) ((x) << S_CERR_DATA_FIFO_0)
46545 #define F_CERR_DATA_FIFO_0    V_CERR_DATA_FIFO_0(1U)
46546 
46547 #define S_SE_CNT_MISMATCH_3    11
46548 #define V_SE_CNT_MISMATCH_3(x) ((x) << S_SE_CNT_MISMATCH_3)
46549 #define F_SE_CNT_MISMATCH_3    V_SE_CNT_MISMATCH_3(1U)
46550 
46551 #define S_SE_CNT_MISMATCH_2    10
46552 #define V_SE_CNT_MISMATCH_2(x) ((x) << S_SE_CNT_MISMATCH_2)
46553 #define F_SE_CNT_MISMATCH_2    V_SE_CNT_MISMATCH_2(1U)
46554 
46555 #define S_T7_SE_CNT_MISMATCH_1    9
46556 #define V_T7_SE_CNT_MISMATCH_1(x) ((x) << S_T7_SE_CNT_MISMATCH_1)
46557 #define F_T7_SE_CNT_MISMATCH_1    V_T7_SE_CNT_MISMATCH_1(1U)
46558 
46559 #define S_T7_SE_CNT_MISMATCH_0    8
46560 #define V_T7_SE_CNT_MISMATCH_0(x) ((x) << S_T7_SE_CNT_MISMATCH_0)
46561 #define F_T7_SE_CNT_MISMATCH_0    V_T7_SE_CNT_MISMATCH_0(1U)
46562 
46563 #define S_ENABLE_CTX_3    7
46564 #define V_ENABLE_CTX_3(x) ((x) << S_ENABLE_CTX_3)
46565 #define F_ENABLE_CTX_3    V_ENABLE_CTX_3(1U)
46566 
46567 #define S_ENABLE_CTX_2    6
46568 #define V_ENABLE_CTX_2(x) ((x) << S_ENABLE_CTX_2)
46569 #define F_ENABLE_CTX_2    V_ENABLE_CTX_2(1U)
46570 
46571 #define S_T7_ENABLE_CTX_1    5
46572 #define V_T7_ENABLE_CTX_1(x) ((x) << S_T7_ENABLE_CTX_1)
46573 #define F_T7_ENABLE_CTX_1    V_T7_ENABLE_CTX_1(1U)
46574 
46575 #define S_T7_ENABLE_CTX_0    4
46576 #define V_T7_ENABLE_CTX_0(x) ((x) << S_T7_ENABLE_CTX_0)
46577 #define F_T7_ENABLE_CTX_0    V_T7_ENABLE_CTX_0(1U)
46578 
46579 #define S_ENABLE_ALN_SDC_ERR_3    3
46580 #define V_ENABLE_ALN_SDC_ERR_3(x) ((x) << S_ENABLE_ALN_SDC_ERR_3)
46581 #define F_ENABLE_ALN_SDC_ERR_3    V_ENABLE_ALN_SDC_ERR_3(1U)
46582 
46583 #define S_ENABLE_ALN_SDC_ERR_2    2
46584 #define V_ENABLE_ALN_SDC_ERR_2(x) ((x) << S_ENABLE_ALN_SDC_ERR_2)
46585 #define F_ENABLE_ALN_SDC_ERR_2    V_ENABLE_ALN_SDC_ERR_2(1U)
46586 
46587 #define S_T7_ENABLE_ALN_SDC_ERR_1    1
46588 #define V_T7_ENABLE_ALN_SDC_ERR_1(x) ((x) << S_T7_ENABLE_ALN_SDC_ERR_1)
46589 #define F_T7_ENABLE_ALN_SDC_ERR_1    V_T7_ENABLE_ALN_SDC_ERR_1(1U)
46590 
46591 #define S_T7_ENABLE_ALN_SDC_ERR_0    0
46592 #define V_T7_ENABLE_ALN_SDC_ERR_0(x) ((x) << S_T7_ENABLE_ALN_SDC_ERR_0)
46593 #define F_T7_ENABLE_ALN_SDC_ERR_0    V_T7_ENABLE_ALN_SDC_ERR_0(1U)
46594 
46595 #define A_ULP_RX_INT_CAUSE 0x19158
46596 
46597 #define S_CAUSE_CTX_1    24
46598 #define V_CAUSE_CTX_1(x) ((x) << S_CAUSE_CTX_1)
46599 #define F_CAUSE_CTX_1    V_CAUSE_CTX_1(1U)
46600 
46601 #define S_CAUSE_CTX_0    23
46602 #define V_CAUSE_CTX_0(x) ((x) << S_CAUSE_CTX_0)
46603 #define F_CAUSE_CTX_0    V_CAUSE_CTX_0(1U)
46604 
46605 #define S_CAUSE_FF    22
46606 #define V_CAUSE_FF(x) ((x) << S_CAUSE_FF)
46607 #define F_CAUSE_FF    V_CAUSE_FF(1U)
46608 
46609 #define S_CAUSE_APF_1    21
46610 #define V_CAUSE_APF_1(x) ((x) << S_CAUSE_APF_1)
46611 #define F_CAUSE_APF_1    V_CAUSE_APF_1(1U)
46612 
46613 #define S_CAUSE_APF_0    20
46614 #define V_CAUSE_APF_0(x) ((x) << S_CAUSE_APF_0)
46615 #define F_CAUSE_APF_0    V_CAUSE_APF_0(1U)
46616 
46617 #define S_CAUSE_AF_1    19
46618 #define V_CAUSE_AF_1(x) ((x) << S_CAUSE_AF_1)
46619 #define F_CAUSE_AF_1    V_CAUSE_AF_1(1U)
46620 
46621 #define S_CAUSE_AF_0    18
46622 #define V_CAUSE_AF_0(x) ((x) << S_CAUSE_AF_0)
46623 #define F_CAUSE_AF_0    V_CAUSE_AF_0(1U)
46624 
46625 #define S_CAUSE_DDPDF_1    17
46626 #define V_CAUSE_DDPDF_1(x) ((x) << S_CAUSE_DDPDF_1)
46627 #define F_CAUSE_DDPDF_1    V_CAUSE_DDPDF_1(1U)
46628 
46629 #define S_CAUSE_DDPMF_1    16
46630 #define V_CAUSE_DDPMF_1(x) ((x) << S_CAUSE_DDPMF_1)
46631 #define F_CAUSE_DDPMF_1    V_CAUSE_DDPMF_1(1U)
46632 
46633 #define S_CAUSE_MEMRF_1    15
46634 #define V_CAUSE_MEMRF_1(x) ((x) << S_CAUSE_MEMRF_1)
46635 #define F_CAUSE_MEMRF_1    V_CAUSE_MEMRF_1(1U)
46636 
46637 #define S_CAUSE_PRSDF_1    14
46638 #define V_CAUSE_PRSDF_1(x) ((x) << S_CAUSE_PRSDF_1)
46639 #define F_CAUSE_PRSDF_1    V_CAUSE_PRSDF_1(1U)
46640 
46641 #define S_CAUSE_DDPDF_0    13
46642 #define V_CAUSE_DDPDF_0(x) ((x) << S_CAUSE_DDPDF_0)
46643 #define F_CAUSE_DDPDF_0    V_CAUSE_DDPDF_0(1U)
46644 
46645 #define S_CAUSE_DDPMF_0    12
46646 #define V_CAUSE_DDPMF_0(x) ((x) << S_CAUSE_DDPMF_0)
46647 #define F_CAUSE_DDPMF_0    V_CAUSE_DDPMF_0(1U)
46648 
46649 #define S_CAUSE_MEMRF_0    11
46650 #define V_CAUSE_MEMRF_0(x) ((x) << S_CAUSE_MEMRF_0)
46651 #define F_CAUSE_MEMRF_0    V_CAUSE_MEMRF_0(1U)
46652 
46653 #define S_CAUSE_PRSDF_0    10
46654 #define V_CAUSE_PRSDF_0(x) ((x) << S_CAUSE_PRSDF_0)
46655 #define F_CAUSE_PRSDF_0    V_CAUSE_PRSDF_0(1U)
46656 
46657 #define S_CAUSE_PCMDF_1    9
46658 #define V_CAUSE_PCMDF_1(x) ((x) << S_CAUSE_PCMDF_1)
46659 #define F_CAUSE_PCMDF_1    V_CAUSE_PCMDF_1(1U)
46660 
46661 #define S_CAUSE_TPTCF_1    8
46662 #define V_CAUSE_TPTCF_1(x) ((x) << S_CAUSE_TPTCF_1)
46663 #define F_CAUSE_TPTCF_1    V_CAUSE_TPTCF_1(1U)
46664 
46665 #define S_CAUSE_DDPCF_1    7
46666 #define V_CAUSE_DDPCF_1(x) ((x) << S_CAUSE_DDPCF_1)
46667 #define F_CAUSE_DDPCF_1    V_CAUSE_DDPCF_1(1U)
46668 
46669 #define S_CAUSE_MPARF_1    6
46670 #define V_CAUSE_MPARF_1(x) ((x) << S_CAUSE_MPARF_1)
46671 #define F_CAUSE_MPARF_1    V_CAUSE_MPARF_1(1U)
46672 
46673 #define S_CAUSE_MPARC_1    5
46674 #define V_CAUSE_MPARC_1(x) ((x) << S_CAUSE_MPARC_1)
46675 #define F_CAUSE_MPARC_1    V_CAUSE_MPARC_1(1U)
46676 
46677 #define S_CAUSE_PCMDF_0    4
46678 #define V_CAUSE_PCMDF_0(x) ((x) << S_CAUSE_PCMDF_0)
46679 #define F_CAUSE_PCMDF_0    V_CAUSE_PCMDF_0(1U)
46680 
46681 #define S_CAUSE_TPTCF_0    3
46682 #define V_CAUSE_TPTCF_0(x) ((x) << S_CAUSE_TPTCF_0)
46683 #define F_CAUSE_TPTCF_0    V_CAUSE_TPTCF_0(1U)
46684 
46685 #define S_CAUSE_DDPCF_0    2
46686 #define V_CAUSE_DDPCF_0(x) ((x) << S_CAUSE_DDPCF_0)
46687 #define F_CAUSE_DDPCF_0    V_CAUSE_DDPCF_0(1U)
46688 
46689 #define S_CAUSE_MPARF_0    1
46690 #define V_CAUSE_MPARF_0(x) ((x) << S_CAUSE_MPARF_0)
46691 #define F_CAUSE_MPARF_0    V_CAUSE_MPARF_0(1U)
46692 
46693 #define S_CAUSE_MPARC_0    0
46694 #define V_CAUSE_MPARC_0(x) ((x) << S_CAUSE_MPARC_0)
46695 #define F_CAUSE_MPARC_0    V_CAUSE_MPARC_0(1U)
46696 
46697 #define A_ULP_RX_ISCSI_LLIMIT 0x1915c
46698 
46699 #define S_ISCSILLIMIT    6
46700 #define M_ISCSILLIMIT    0x3ffffffU
46701 #define V_ISCSILLIMIT(x) ((x) << S_ISCSILLIMIT)
46702 #define G_ISCSILLIMIT(x) (((x) >> S_ISCSILLIMIT) & M_ISCSILLIMIT)
46703 
46704 #define A_ULP_RX_ISCSI_ULIMIT 0x19160
46705 
46706 #define S_ISCSIULIMIT    6
46707 #define M_ISCSIULIMIT    0x3ffffffU
46708 #define V_ISCSIULIMIT(x) ((x) << S_ISCSIULIMIT)
46709 #define G_ISCSIULIMIT(x) (((x) >> S_ISCSIULIMIT) & M_ISCSIULIMIT)
46710 
46711 #define A_ULP_RX_ISCSI_TAGMASK 0x19164
46712 
46713 #define S_ISCSITAGMASK    6
46714 #define M_ISCSITAGMASK    0x3ffffffU
46715 #define V_ISCSITAGMASK(x) ((x) << S_ISCSITAGMASK)
46716 #define G_ISCSITAGMASK(x) (((x) >> S_ISCSITAGMASK) & M_ISCSITAGMASK)
46717 
46718 #define A_ULP_RX_ISCSI_PSZ 0x19168
46719 
46720 #define S_HPZ3    24
46721 #define M_HPZ3    0xfU
46722 #define V_HPZ3(x) ((x) << S_HPZ3)
46723 #define G_HPZ3(x) (((x) >> S_HPZ3) & M_HPZ3)
46724 
46725 #define S_HPZ2    16
46726 #define M_HPZ2    0xfU
46727 #define V_HPZ2(x) ((x) << S_HPZ2)
46728 #define G_HPZ2(x) (((x) >> S_HPZ2) & M_HPZ2)
46729 
46730 #define S_HPZ1    8
46731 #define M_HPZ1    0xfU
46732 #define V_HPZ1(x) ((x) << S_HPZ1)
46733 #define G_HPZ1(x) (((x) >> S_HPZ1) & M_HPZ1)
46734 
46735 #define S_HPZ0    0
46736 #define M_HPZ0    0xfU
46737 #define V_HPZ0(x) ((x) << S_HPZ0)
46738 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
46739 
46740 #define A_ULP_RX_TDDP_LLIMIT 0x1916c
46741 
46742 #define S_TDDPLLIMIT    6
46743 #define M_TDDPLLIMIT    0x3ffffffU
46744 #define V_TDDPLLIMIT(x) ((x) << S_TDDPLLIMIT)
46745 #define G_TDDPLLIMIT(x) (((x) >> S_TDDPLLIMIT) & M_TDDPLLIMIT)
46746 
46747 #define A_ULP_RX_TDDP_ULIMIT 0x19170
46748 
46749 #define S_TDDPULIMIT    6
46750 #define M_TDDPULIMIT    0x3ffffffU
46751 #define V_TDDPULIMIT(x) ((x) << S_TDDPULIMIT)
46752 #define G_TDDPULIMIT(x) (((x) >> S_TDDPULIMIT) & M_TDDPULIMIT)
46753 
46754 #define A_ULP_RX_TDDP_TAGMASK 0x19174
46755 
46756 #define S_TDDPTAGMASK    6
46757 #define M_TDDPTAGMASK    0x3ffffffU
46758 #define V_TDDPTAGMASK(x) ((x) << S_TDDPTAGMASK)
46759 #define G_TDDPTAGMASK(x) (((x) >> S_TDDPTAGMASK) & M_TDDPTAGMASK)
46760 
46761 #define A_ULP_RX_TDDP_PSZ 0x19178
46762 #define A_ULP_RX_STAG_LLIMIT 0x1917c
46763 #define A_ULP_RX_STAG_ULIMIT 0x19180
46764 #define A_ULP_RX_RQ_LLIMIT 0x19184
46765 #define A_ULP_RX_RQ_ULIMIT 0x19188
46766 #define A_ULP_RX_PBL_LLIMIT 0x1918c
46767 #define A_ULP_RX_PBL_ULIMIT 0x19190
46768 #define A_ULP_RX_CTX_BASE 0x19194
46769 #define A_ULP_RX_PERR_ENABLE 0x1919c
46770 
46771 #define S_PERR_ENABLE_FF    22
46772 #define V_PERR_ENABLE_FF(x) ((x) << S_PERR_ENABLE_FF)
46773 #define F_PERR_ENABLE_FF    V_PERR_ENABLE_FF(1U)
46774 
46775 #define S_PERR_ENABLE_APF_1    21
46776 #define V_PERR_ENABLE_APF_1(x) ((x) << S_PERR_ENABLE_APF_1)
46777 #define F_PERR_ENABLE_APF_1    V_PERR_ENABLE_APF_1(1U)
46778 
46779 #define S_PERR_ENABLE_APF_0    20
46780 #define V_PERR_ENABLE_APF_0(x) ((x) << S_PERR_ENABLE_APF_0)
46781 #define F_PERR_ENABLE_APF_0    V_PERR_ENABLE_APF_0(1U)
46782 
46783 #define S_PERR_ENABLE_AF_1    19
46784 #define V_PERR_ENABLE_AF_1(x) ((x) << S_PERR_ENABLE_AF_1)
46785 #define F_PERR_ENABLE_AF_1    V_PERR_ENABLE_AF_1(1U)
46786 
46787 #define S_PERR_ENABLE_AF_0    18
46788 #define V_PERR_ENABLE_AF_0(x) ((x) << S_PERR_ENABLE_AF_0)
46789 #define F_PERR_ENABLE_AF_0    V_PERR_ENABLE_AF_0(1U)
46790 
46791 #define S_PERR_ENABLE_DDPDF_1    17
46792 #define V_PERR_ENABLE_DDPDF_1(x) ((x) << S_PERR_ENABLE_DDPDF_1)
46793 #define F_PERR_ENABLE_DDPDF_1    V_PERR_ENABLE_DDPDF_1(1U)
46794 
46795 #define S_PERR_ENABLE_DDPMF_1    16
46796 #define V_PERR_ENABLE_DDPMF_1(x) ((x) << S_PERR_ENABLE_DDPMF_1)
46797 #define F_PERR_ENABLE_DDPMF_1    V_PERR_ENABLE_DDPMF_1(1U)
46798 
46799 #define S_PERR_ENABLE_MEMRF_1    15
46800 #define V_PERR_ENABLE_MEMRF_1(x) ((x) << S_PERR_ENABLE_MEMRF_1)
46801 #define F_PERR_ENABLE_MEMRF_1    V_PERR_ENABLE_MEMRF_1(1U)
46802 
46803 #define S_PERR_ENABLE_PRSDF_1    14
46804 #define V_PERR_ENABLE_PRSDF_1(x) ((x) << S_PERR_ENABLE_PRSDF_1)
46805 #define F_PERR_ENABLE_PRSDF_1    V_PERR_ENABLE_PRSDF_1(1U)
46806 
46807 #define S_PERR_ENABLE_DDPDF_0    13
46808 #define V_PERR_ENABLE_DDPDF_0(x) ((x) << S_PERR_ENABLE_DDPDF_0)
46809 #define F_PERR_ENABLE_DDPDF_0    V_PERR_ENABLE_DDPDF_0(1U)
46810 
46811 #define S_PERR_ENABLE_DDPMF_0    12
46812 #define V_PERR_ENABLE_DDPMF_0(x) ((x) << S_PERR_ENABLE_DDPMF_0)
46813 #define F_PERR_ENABLE_DDPMF_0    V_PERR_ENABLE_DDPMF_0(1U)
46814 
46815 #define S_PERR_ENABLE_MEMRF_0    11
46816 #define V_PERR_ENABLE_MEMRF_0(x) ((x) << S_PERR_ENABLE_MEMRF_0)
46817 #define F_PERR_ENABLE_MEMRF_0    V_PERR_ENABLE_MEMRF_0(1U)
46818 
46819 #define S_PERR_ENABLE_PRSDF_0    10
46820 #define V_PERR_ENABLE_PRSDF_0(x) ((x) << S_PERR_ENABLE_PRSDF_0)
46821 #define F_PERR_ENABLE_PRSDF_0    V_PERR_ENABLE_PRSDF_0(1U)
46822 
46823 #define S_PERR_ENABLE_PCMDF_1    9
46824 #define V_PERR_ENABLE_PCMDF_1(x) ((x) << S_PERR_ENABLE_PCMDF_1)
46825 #define F_PERR_ENABLE_PCMDF_1    V_PERR_ENABLE_PCMDF_1(1U)
46826 
46827 #define S_PERR_ENABLE_TPTCF_1    8
46828 #define V_PERR_ENABLE_TPTCF_1(x) ((x) << S_PERR_ENABLE_TPTCF_1)
46829 #define F_PERR_ENABLE_TPTCF_1    V_PERR_ENABLE_TPTCF_1(1U)
46830 
46831 #define S_PERR_ENABLE_DDPCF_1    7
46832 #define V_PERR_ENABLE_DDPCF_1(x) ((x) << S_PERR_ENABLE_DDPCF_1)
46833 #define F_PERR_ENABLE_DDPCF_1    V_PERR_ENABLE_DDPCF_1(1U)
46834 
46835 #define S_PERR_ENABLE_MPARF_1    6
46836 #define V_PERR_ENABLE_MPARF_1(x) ((x) << S_PERR_ENABLE_MPARF_1)
46837 #define F_PERR_ENABLE_MPARF_1    V_PERR_ENABLE_MPARF_1(1U)
46838 
46839 #define S_PERR_ENABLE_MPARC_1    5
46840 #define V_PERR_ENABLE_MPARC_1(x) ((x) << S_PERR_ENABLE_MPARC_1)
46841 #define F_PERR_ENABLE_MPARC_1    V_PERR_ENABLE_MPARC_1(1U)
46842 
46843 #define S_PERR_ENABLE_PCMDF_0    4
46844 #define V_PERR_ENABLE_PCMDF_0(x) ((x) << S_PERR_ENABLE_PCMDF_0)
46845 #define F_PERR_ENABLE_PCMDF_0    V_PERR_ENABLE_PCMDF_0(1U)
46846 
46847 #define S_PERR_ENABLE_TPTCF_0    3
46848 #define V_PERR_ENABLE_TPTCF_0(x) ((x) << S_PERR_ENABLE_TPTCF_0)
46849 #define F_PERR_ENABLE_TPTCF_0    V_PERR_ENABLE_TPTCF_0(1U)
46850 
46851 #define S_PERR_ENABLE_DDPCF_0    2
46852 #define V_PERR_ENABLE_DDPCF_0(x) ((x) << S_PERR_ENABLE_DDPCF_0)
46853 #define F_PERR_ENABLE_DDPCF_0    V_PERR_ENABLE_DDPCF_0(1U)
46854 
46855 #define S_PERR_ENABLE_MPARF_0    1
46856 #define V_PERR_ENABLE_MPARF_0(x) ((x) << S_PERR_ENABLE_MPARF_0)
46857 #define F_PERR_ENABLE_MPARF_0    V_PERR_ENABLE_MPARF_0(1U)
46858 
46859 #define S_PERR_ENABLE_MPARC_0    0
46860 #define V_PERR_ENABLE_MPARC_0(x) ((x) << S_PERR_ENABLE_MPARC_0)
46861 #define F_PERR_ENABLE_MPARC_0    V_PERR_ENABLE_MPARC_0(1U)
46862 
46863 #define S_PERR_SE_CNT_MISMATCH_1    26
46864 #define V_PERR_SE_CNT_MISMATCH_1(x) ((x) << S_PERR_SE_CNT_MISMATCH_1)
46865 #define F_PERR_SE_CNT_MISMATCH_1    V_PERR_SE_CNT_MISMATCH_1(1U)
46866 
46867 #define S_PERR_SE_CNT_MISMATCH_0    25
46868 #define V_PERR_SE_CNT_MISMATCH_0(x) ((x) << S_PERR_SE_CNT_MISMATCH_0)
46869 #define F_PERR_SE_CNT_MISMATCH_0    V_PERR_SE_CNT_MISMATCH_0(1U)
46870 
46871 #define S_PERR_RSVD0    24
46872 #define V_PERR_RSVD0(x) ((x) << S_PERR_RSVD0)
46873 #define F_PERR_RSVD0    V_PERR_RSVD0(1U)
46874 
46875 #define S_PERR_RSVD1    23
46876 #define V_PERR_RSVD1(x) ((x) << S_PERR_RSVD1)
46877 #define F_PERR_RSVD1    V_PERR_RSVD1(1U)
46878 
46879 #define S_PERR_ENABLE_CTX_1    24
46880 #define V_PERR_ENABLE_CTX_1(x) ((x) << S_PERR_ENABLE_CTX_1)
46881 #define F_PERR_ENABLE_CTX_1    V_PERR_ENABLE_CTX_1(1U)
46882 
46883 #define S_PERR_ENABLE_CTX_0    23
46884 #define V_PERR_ENABLE_CTX_0(x) ((x) << S_PERR_ENABLE_CTX_0)
46885 #define F_PERR_ENABLE_CTX_0    V_PERR_ENABLE_CTX_0(1U)
46886 
46887 #define A_ULP_RX_PERR_INJECT 0x191a0
46888 #define A_ULP_RX_RQUDP_LLIMIT 0x191a4
46889 #define A_ULP_RX_RQUDP_ULIMIT 0x191a8
46890 #define A_ULP_RX_CTX_ACC_CH0 0x191ac
46891 
46892 #define S_REQ    21
46893 #define V_REQ(x) ((x) << S_REQ)
46894 #define F_REQ    V_REQ(1U)
46895 
46896 #define S_WB    20
46897 #define V_WB(x) ((x) << S_WB)
46898 #define F_WB    V_WB(1U)
46899 
46900 #define S_ULPRX_TID    0
46901 #define M_ULPRX_TID    0xfffffU
46902 #define V_ULPRX_TID(x) ((x) << S_ULPRX_TID)
46903 #define G_ULPRX_TID(x) (((x) >> S_ULPRX_TID) & M_ULPRX_TID)
46904 
46905 #define A_ULP_RX_CTX_ACC_CH1 0x191b0
46906 #define A_ULP_RX_CTX_ACC_CH2 0x191b4
46907 #define A_ULP_RX_CTX_ACC_CH3 0x191b8
46908 #define A_ULP_RX_CTL2 0x191bc
46909 
46910 #define S_PCMD3THRESHOLD    24
46911 #define M_PCMD3THRESHOLD    0xffU
46912 #define V_PCMD3THRESHOLD(x) ((x) << S_PCMD3THRESHOLD)
46913 #define G_PCMD3THRESHOLD(x) (((x) >> S_PCMD3THRESHOLD) & M_PCMD3THRESHOLD)
46914 
46915 #define S_PCMD2THRESHOLD    16
46916 #define M_PCMD2THRESHOLD    0xffU
46917 #define V_PCMD2THRESHOLD(x) ((x) << S_PCMD2THRESHOLD)
46918 #define G_PCMD2THRESHOLD(x) (((x) >> S_PCMD2THRESHOLD) & M_PCMD2THRESHOLD)
46919 
46920 #define S_T7_PCMD1THRESHOLD    8
46921 #define M_T7_PCMD1THRESHOLD    0xffU
46922 #define V_T7_PCMD1THRESHOLD(x) ((x) << S_T7_PCMD1THRESHOLD)
46923 #define G_T7_PCMD1THRESHOLD(x) (((x) >> S_T7_PCMD1THRESHOLD) & M_T7_PCMD1THRESHOLD)
46924 
46925 #define S_T7_PCMD0THRESHOLD    0
46926 #define M_T7_PCMD0THRESHOLD    0xffU
46927 #define V_T7_PCMD0THRESHOLD(x) ((x) << S_T7_PCMD0THRESHOLD)
46928 #define G_T7_PCMD0THRESHOLD(x) (((x) >> S_T7_PCMD0THRESHOLD) & M_T7_PCMD0THRESHOLD)
46929 
46930 #define A_ULP_RX_INT_ENABLE_INTERFACE 0x191c0
46931 
46932 #define S_ENABLE_ULPRX2SBT_RSPPERR    31
46933 #define V_ENABLE_ULPRX2SBT_RSPPERR(x) ((x) << S_ENABLE_ULPRX2SBT_RSPPERR)
46934 #define F_ENABLE_ULPRX2SBT_RSPPERR    V_ENABLE_ULPRX2SBT_RSPPERR(1U)
46935 
46936 #define S_ENABLE_ULPRX2MA_RSPPERR    30
46937 #define V_ENABLE_ULPRX2MA_RSPPERR(x) ((x) << S_ENABLE_ULPRX2MA_RSPPERR)
46938 #define F_ENABLE_ULPRX2MA_RSPPERR    V_ENABLE_ULPRX2MA_RSPPERR(1U)
46939 
46940 #define S_ENABME_PIO_BUS_PERR    29
46941 #define V_ENABME_PIO_BUS_PERR(x) ((x) << S_ENABME_PIO_BUS_PERR)
46942 #define F_ENABME_PIO_BUS_PERR    V_ENABME_PIO_BUS_PERR(1U)
46943 
46944 #define S_ENABLE_PM2ULP_SNOOPDATA_3    19
46945 #define V_ENABLE_PM2ULP_SNOOPDATA_3(x) ((x) << S_ENABLE_PM2ULP_SNOOPDATA_3)
46946 #define F_ENABLE_PM2ULP_SNOOPDATA_3    V_ENABLE_PM2ULP_SNOOPDATA_3(1U)
46947 
46948 #define S_ENABLE_PM2ULP_SNOOPDATA_2    18
46949 #define V_ENABLE_PM2ULP_SNOOPDATA_2(x) ((x) << S_ENABLE_PM2ULP_SNOOPDATA_2)
46950 #define F_ENABLE_PM2ULP_SNOOPDATA_2    V_ENABLE_PM2ULP_SNOOPDATA_2(1U)
46951 
46952 #define S_ENABLE_PM2ULP_SNOOPDATA_1    17
46953 #define V_ENABLE_PM2ULP_SNOOPDATA_1(x) ((x) << S_ENABLE_PM2ULP_SNOOPDATA_1)
46954 #define F_ENABLE_PM2ULP_SNOOPDATA_1    V_ENABLE_PM2ULP_SNOOPDATA_1(1U)
46955 
46956 #define S_ENABLE_PM2ULP_SNOOPDATA_0    16
46957 #define V_ENABLE_PM2ULP_SNOOPDATA_0(x) ((x) << S_ENABLE_PM2ULP_SNOOPDATA_0)
46958 #define F_ENABLE_PM2ULP_SNOOPDATA_0    V_ENABLE_PM2ULP_SNOOPDATA_0(1U)
46959 
46960 #define S_ENABLE_TLS2ULP_DATA_3    15
46961 #define V_ENABLE_TLS2ULP_DATA_3(x) ((x) << S_ENABLE_TLS2ULP_DATA_3)
46962 #define F_ENABLE_TLS2ULP_DATA_3    V_ENABLE_TLS2ULP_DATA_3(1U)
46963 
46964 #define S_ENABLE_TLS2ULP_DATA_2    14
46965 #define V_ENABLE_TLS2ULP_DATA_2(x) ((x) << S_ENABLE_TLS2ULP_DATA_2)
46966 #define F_ENABLE_TLS2ULP_DATA_2    V_ENABLE_TLS2ULP_DATA_2(1U)
46967 
46968 #define S_ENABLE_TLS2ULP_DATA_1    13
46969 #define V_ENABLE_TLS2ULP_DATA_1(x) ((x) << S_ENABLE_TLS2ULP_DATA_1)
46970 #define F_ENABLE_TLS2ULP_DATA_1    V_ENABLE_TLS2ULP_DATA_1(1U)
46971 
46972 #define S_ENABLE_TLS2ULP_DATA_0    12
46973 #define V_ENABLE_TLS2ULP_DATA_0(x) ((x) << S_ENABLE_TLS2ULP_DATA_0)
46974 #define F_ENABLE_TLS2ULP_DATA_0    V_ENABLE_TLS2ULP_DATA_0(1U)
46975 
46976 #define S_ENABLE_TLS2ULP_PLENDATA_3    11
46977 #define V_ENABLE_TLS2ULP_PLENDATA_3(x) ((x) << S_ENABLE_TLS2ULP_PLENDATA_3)
46978 #define F_ENABLE_TLS2ULP_PLENDATA_3    V_ENABLE_TLS2ULP_PLENDATA_3(1U)
46979 
46980 #define S_ENABLE_TLS2ULP_PLENDATA_2    10
46981 #define V_ENABLE_TLS2ULP_PLENDATA_2(x) ((x) << S_ENABLE_TLS2ULP_PLENDATA_2)
46982 #define F_ENABLE_TLS2ULP_PLENDATA_2    V_ENABLE_TLS2ULP_PLENDATA_2(1U)
46983 
46984 #define S_ENABLE_TLS2ULP_PLENDATA_1    9
46985 #define V_ENABLE_TLS2ULP_PLENDATA_1(x) ((x) << S_ENABLE_TLS2ULP_PLENDATA_1)
46986 #define F_ENABLE_TLS2ULP_PLENDATA_1    V_ENABLE_TLS2ULP_PLENDATA_1(1U)
46987 
46988 #define S_ENABLE_TLS2ULP_PLENDATA_0    8
46989 #define V_ENABLE_TLS2ULP_PLENDATA_0(x) ((x) << S_ENABLE_TLS2ULP_PLENDATA_0)
46990 #define F_ENABLE_TLS2ULP_PLENDATA_0    V_ENABLE_TLS2ULP_PLENDATA_0(1U)
46991 
46992 #define S_ENABLE_PM2ULP_DATA_3    7
46993 #define V_ENABLE_PM2ULP_DATA_3(x) ((x) << S_ENABLE_PM2ULP_DATA_3)
46994 #define F_ENABLE_PM2ULP_DATA_3    V_ENABLE_PM2ULP_DATA_3(1U)
46995 
46996 #define S_ENABLE_PM2ULP_DATA_2    6
46997 #define V_ENABLE_PM2ULP_DATA_2(x) ((x) << S_ENABLE_PM2ULP_DATA_2)
46998 #define F_ENABLE_PM2ULP_DATA_2    V_ENABLE_PM2ULP_DATA_2(1U)
46999 
47000 #define S_ENABLE_PM2ULP_DATA_1    5
47001 #define V_ENABLE_PM2ULP_DATA_1(x) ((x) << S_ENABLE_PM2ULP_DATA_1)
47002 #define F_ENABLE_PM2ULP_DATA_1    V_ENABLE_PM2ULP_DATA_1(1U)
47003 
47004 #define S_ENABLE_PM2ULP_DATA_0    4
47005 #define V_ENABLE_PM2ULP_DATA_0(x) ((x) << S_ENABLE_PM2ULP_DATA_0)
47006 #define F_ENABLE_PM2ULP_DATA_0    V_ENABLE_PM2ULP_DATA_0(1U)
47007 
47008 #define S_ENABLE_TP2ULP_PCMD_3    3
47009 #define V_ENABLE_TP2ULP_PCMD_3(x) ((x) << S_ENABLE_TP2ULP_PCMD_3)
47010 #define F_ENABLE_TP2ULP_PCMD_3    V_ENABLE_TP2ULP_PCMD_3(1U)
47011 
47012 #define S_ENABLE_TP2ULP_PCMD_2    2
47013 #define V_ENABLE_TP2ULP_PCMD_2(x) ((x) << S_ENABLE_TP2ULP_PCMD_2)
47014 #define F_ENABLE_TP2ULP_PCMD_2    V_ENABLE_TP2ULP_PCMD_2(1U)
47015 
47016 #define S_ENABLE_TP2ULP_PCMD_1    1
47017 #define V_ENABLE_TP2ULP_PCMD_1(x) ((x) << S_ENABLE_TP2ULP_PCMD_1)
47018 #define F_ENABLE_TP2ULP_PCMD_1    V_ENABLE_TP2ULP_PCMD_1(1U)
47019 
47020 #define S_ENABLE_TP2ULP_PCMD_0    0
47021 #define V_ENABLE_TP2ULP_PCMD_0(x) ((x) << S_ENABLE_TP2ULP_PCMD_0)
47022 #define F_ENABLE_TP2ULP_PCMD_0    V_ENABLE_TP2ULP_PCMD_0(1U)
47023 
47024 #define A_ULP_RX_INT_CAUSE_INTERFACE 0x191c4
47025 
47026 #define S_CAUSE_ULPRX2SBT_RSPPERR    31
47027 #define V_CAUSE_ULPRX2SBT_RSPPERR(x) ((x) << S_CAUSE_ULPRX2SBT_RSPPERR)
47028 #define F_CAUSE_ULPRX2SBT_RSPPERR    V_CAUSE_ULPRX2SBT_RSPPERR(1U)
47029 
47030 #define S_CAUSE_ULPRX2MA_RSPPERR    30
47031 #define V_CAUSE_ULPRX2MA_RSPPERR(x) ((x) << S_CAUSE_ULPRX2MA_RSPPERR)
47032 #define F_CAUSE_ULPRX2MA_RSPPERR    V_CAUSE_ULPRX2MA_RSPPERR(1U)
47033 
47034 #define S_CAUSE_PIO_BUS_PERR    29
47035 #define V_CAUSE_PIO_BUS_PERR(x) ((x) << S_CAUSE_PIO_BUS_PERR)
47036 #define F_CAUSE_PIO_BUS_PERR    V_CAUSE_PIO_BUS_PERR(1U)
47037 
47038 #define S_CAUSE_PM2ULP_SNOOPDATA_3    19
47039 #define V_CAUSE_PM2ULP_SNOOPDATA_3(x) ((x) << S_CAUSE_PM2ULP_SNOOPDATA_3)
47040 #define F_CAUSE_PM2ULP_SNOOPDATA_3    V_CAUSE_PM2ULP_SNOOPDATA_3(1U)
47041 
47042 #define S_CAUSE_PM2ULP_SNOOPDATA_2    18
47043 #define V_CAUSE_PM2ULP_SNOOPDATA_2(x) ((x) << S_CAUSE_PM2ULP_SNOOPDATA_2)
47044 #define F_CAUSE_PM2ULP_SNOOPDATA_2    V_CAUSE_PM2ULP_SNOOPDATA_2(1U)
47045 
47046 #define S_CAUSE_PM2ULP_SNOOPDATA_1    17
47047 #define V_CAUSE_PM2ULP_SNOOPDATA_1(x) ((x) << S_CAUSE_PM2ULP_SNOOPDATA_1)
47048 #define F_CAUSE_PM2ULP_SNOOPDATA_1    V_CAUSE_PM2ULP_SNOOPDATA_1(1U)
47049 
47050 #define S_CAUSE_PM2ULP_SNOOPDATA_0    16
47051 #define V_CAUSE_PM2ULP_SNOOPDATA_0(x) ((x) << S_CAUSE_PM2ULP_SNOOPDATA_0)
47052 #define F_CAUSE_PM2ULP_SNOOPDATA_0    V_CAUSE_PM2ULP_SNOOPDATA_0(1U)
47053 
47054 #define S_CAUSE_TLS2ULP_DATA_3    15
47055 #define V_CAUSE_TLS2ULP_DATA_3(x) ((x) << S_CAUSE_TLS2ULP_DATA_3)
47056 #define F_CAUSE_TLS2ULP_DATA_3    V_CAUSE_TLS2ULP_DATA_3(1U)
47057 
47058 #define S_CAUSE_TLS2ULP_DATA_2    14
47059 #define V_CAUSE_TLS2ULP_DATA_2(x) ((x) << S_CAUSE_TLS2ULP_DATA_2)
47060 #define F_CAUSE_TLS2ULP_DATA_2    V_CAUSE_TLS2ULP_DATA_2(1U)
47061 
47062 #define S_CAUSE_TLS2ULP_DATA_1    13
47063 #define V_CAUSE_TLS2ULP_DATA_1(x) ((x) << S_CAUSE_TLS2ULP_DATA_1)
47064 #define F_CAUSE_TLS2ULP_DATA_1    V_CAUSE_TLS2ULP_DATA_1(1U)
47065 
47066 #define S_CAUSE_TLS2ULP_DATA_0    12
47067 #define V_CAUSE_TLS2ULP_DATA_0(x) ((x) << S_CAUSE_TLS2ULP_DATA_0)
47068 #define F_CAUSE_TLS2ULP_DATA_0    V_CAUSE_TLS2ULP_DATA_0(1U)
47069 
47070 #define S_CAUSE_TLS2ULP_PLENDATA_3    11
47071 #define V_CAUSE_TLS2ULP_PLENDATA_3(x) ((x) << S_CAUSE_TLS2ULP_PLENDATA_3)
47072 #define F_CAUSE_TLS2ULP_PLENDATA_3    V_CAUSE_TLS2ULP_PLENDATA_3(1U)
47073 
47074 #define S_CAUSE_TLS2ULP_PLENDATA_2    10
47075 #define V_CAUSE_TLS2ULP_PLENDATA_2(x) ((x) << S_CAUSE_TLS2ULP_PLENDATA_2)
47076 #define F_CAUSE_TLS2ULP_PLENDATA_2    V_CAUSE_TLS2ULP_PLENDATA_2(1U)
47077 
47078 #define S_CAUSE_TLS2ULP_PLENDATA_1    9
47079 #define V_CAUSE_TLS2ULP_PLENDATA_1(x) ((x) << S_CAUSE_TLS2ULP_PLENDATA_1)
47080 #define F_CAUSE_TLS2ULP_PLENDATA_1    V_CAUSE_TLS2ULP_PLENDATA_1(1U)
47081 
47082 #define S_CAUSE_TLS2ULP_PLENDATA_0    8
47083 #define V_CAUSE_TLS2ULP_PLENDATA_0(x) ((x) << S_CAUSE_TLS2ULP_PLENDATA_0)
47084 #define F_CAUSE_TLS2ULP_PLENDATA_0    V_CAUSE_TLS2ULP_PLENDATA_0(1U)
47085 
47086 #define S_CAUSE_PM2ULP_DATA_3    7
47087 #define V_CAUSE_PM2ULP_DATA_3(x) ((x) << S_CAUSE_PM2ULP_DATA_3)
47088 #define F_CAUSE_PM2ULP_DATA_3    V_CAUSE_PM2ULP_DATA_3(1U)
47089 
47090 #define S_CAUSE_PM2ULP_DATA_2    6
47091 #define V_CAUSE_PM2ULP_DATA_2(x) ((x) << S_CAUSE_PM2ULP_DATA_2)
47092 #define F_CAUSE_PM2ULP_DATA_2    V_CAUSE_PM2ULP_DATA_2(1U)
47093 
47094 #define S_CAUSE_PM2ULP_DATA_1    5
47095 #define V_CAUSE_PM2ULP_DATA_1(x) ((x) << S_CAUSE_PM2ULP_DATA_1)
47096 #define F_CAUSE_PM2ULP_DATA_1    V_CAUSE_PM2ULP_DATA_1(1U)
47097 
47098 #define S_CAUSE_PM2ULP_DATA_0    4
47099 #define V_CAUSE_PM2ULP_DATA_0(x) ((x) << S_CAUSE_PM2ULP_DATA_0)
47100 #define F_CAUSE_PM2ULP_DATA_0    V_CAUSE_PM2ULP_DATA_0(1U)
47101 
47102 #define S_CAUSE_TP2ULP_PCMD_3    3
47103 #define V_CAUSE_TP2ULP_PCMD_3(x) ((x) << S_CAUSE_TP2ULP_PCMD_3)
47104 #define F_CAUSE_TP2ULP_PCMD_3    V_CAUSE_TP2ULP_PCMD_3(1U)
47105 
47106 #define S_CAUSE_TP2ULP_PCMD_2    2
47107 #define V_CAUSE_TP2ULP_PCMD_2(x) ((x) << S_CAUSE_TP2ULP_PCMD_2)
47108 #define F_CAUSE_TP2ULP_PCMD_2    V_CAUSE_TP2ULP_PCMD_2(1U)
47109 
47110 #define S_CAUSE_TP2ULP_PCMD_1    1
47111 #define V_CAUSE_TP2ULP_PCMD_1(x) ((x) << S_CAUSE_TP2ULP_PCMD_1)
47112 #define F_CAUSE_TP2ULP_PCMD_1    V_CAUSE_TP2ULP_PCMD_1(1U)
47113 
47114 #define S_CAUSE_TP2ULP_PCMD_0    0
47115 #define V_CAUSE_TP2ULP_PCMD_0(x) ((x) << S_CAUSE_TP2ULP_PCMD_0)
47116 #define F_CAUSE_TP2ULP_PCMD_0    V_CAUSE_TP2ULP_PCMD_0(1U)
47117 
47118 #define A_ULP_RX_PERR_ENABLE_INTERFACE 0x191c8
47119 
47120 #define S_PERR_ULPRX2SBT_RSPPERR    31
47121 #define V_PERR_ULPRX2SBT_RSPPERR(x) ((x) << S_PERR_ULPRX2SBT_RSPPERR)
47122 #define F_PERR_ULPRX2SBT_RSPPERR    V_PERR_ULPRX2SBT_RSPPERR(1U)
47123 
47124 #define S_PERR_ULPRX2MA_RSPPERR    30
47125 #define V_PERR_ULPRX2MA_RSPPERR(x) ((x) << S_PERR_ULPRX2MA_RSPPERR)
47126 #define F_PERR_ULPRX2MA_RSPPERR    V_PERR_ULPRX2MA_RSPPERR(1U)
47127 
47128 #define S_PERR_PIO_BUS_PERR    29
47129 #define V_PERR_PIO_BUS_PERR(x) ((x) << S_PERR_PIO_BUS_PERR)
47130 #define F_PERR_PIO_BUS_PERR    V_PERR_PIO_BUS_PERR(1U)
47131 
47132 #define S_PERR_PM2ULP_SNOOPDATA_3    19
47133 #define V_PERR_PM2ULP_SNOOPDATA_3(x) ((x) << S_PERR_PM2ULP_SNOOPDATA_3)
47134 #define F_PERR_PM2ULP_SNOOPDATA_3    V_PERR_PM2ULP_SNOOPDATA_3(1U)
47135 
47136 #define S_PERR_PM2ULP_SNOOPDATA_2    18
47137 #define V_PERR_PM2ULP_SNOOPDATA_2(x) ((x) << S_PERR_PM2ULP_SNOOPDATA_2)
47138 #define F_PERR_PM2ULP_SNOOPDATA_2    V_PERR_PM2ULP_SNOOPDATA_2(1U)
47139 
47140 #define S_PERR_PM2ULP_SNOOPDATA_1    17
47141 #define V_PERR_PM2ULP_SNOOPDATA_1(x) ((x) << S_PERR_PM2ULP_SNOOPDATA_1)
47142 #define F_PERR_PM2ULP_SNOOPDATA_1    V_PERR_PM2ULP_SNOOPDATA_1(1U)
47143 
47144 #define S_PERR_PM2ULP_SNOOPDATA_0    16
47145 #define V_PERR_PM2ULP_SNOOPDATA_0(x) ((x) << S_PERR_PM2ULP_SNOOPDATA_0)
47146 #define F_PERR_PM2ULP_SNOOPDATA_0    V_PERR_PM2ULP_SNOOPDATA_0(1U)
47147 
47148 #define S_PERR_TLS2ULP_DATA_3    15
47149 #define V_PERR_TLS2ULP_DATA_3(x) ((x) << S_PERR_TLS2ULP_DATA_3)
47150 #define F_PERR_TLS2ULP_DATA_3    V_PERR_TLS2ULP_DATA_3(1U)
47151 
47152 #define S_PERR_TLS2ULP_DATA_2    14
47153 #define V_PERR_TLS2ULP_DATA_2(x) ((x) << S_PERR_TLS2ULP_DATA_2)
47154 #define F_PERR_TLS2ULP_DATA_2    V_PERR_TLS2ULP_DATA_2(1U)
47155 
47156 #define S_PERR_TLS2ULP_DATA_1    13
47157 #define V_PERR_TLS2ULP_DATA_1(x) ((x) << S_PERR_TLS2ULP_DATA_1)
47158 #define F_PERR_TLS2ULP_DATA_1    V_PERR_TLS2ULP_DATA_1(1U)
47159 
47160 #define S_PERR_TLS2ULP_DATA_0    12
47161 #define V_PERR_TLS2ULP_DATA_0(x) ((x) << S_PERR_TLS2ULP_DATA_0)
47162 #define F_PERR_TLS2ULP_DATA_0    V_PERR_TLS2ULP_DATA_0(1U)
47163 
47164 #define S_PERR_TLS2ULP_PLENDATA_3    11
47165 #define V_PERR_TLS2ULP_PLENDATA_3(x) ((x) << S_PERR_TLS2ULP_PLENDATA_3)
47166 #define F_PERR_TLS2ULP_PLENDATA_3    V_PERR_TLS2ULP_PLENDATA_3(1U)
47167 
47168 #define S_PERR_TLS2ULP_PLENDATA_2    10
47169 #define V_PERR_TLS2ULP_PLENDATA_2(x) ((x) << S_PERR_TLS2ULP_PLENDATA_2)
47170 #define F_PERR_TLS2ULP_PLENDATA_2    V_PERR_TLS2ULP_PLENDATA_2(1U)
47171 
47172 #define S_PERR_TLS2ULP_PLENDATA_1    9
47173 #define V_PERR_TLS2ULP_PLENDATA_1(x) ((x) << S_PERR_TLS2ULP_PLENDATA_1)
47174 #define F_PERR_TLS2ULP_PLENDATA_1    V_PERR_TLS2ULP_PLENDATA_1(1U)
47175 
47176 #define S_PERR_TLS2ULP_PLENDATA_0    8
47177 #define V_PERR_TLS2ULP_PLENDATA_0(x) ((x) << S_PERR_TLS2ULP_PLENDATA_0)
47178 #define F_PERR_TLS2ULP_PLENDATA_0    V_PERR_TLS2ULP_PLENDATA_0(1U)
47179 
47180 #define S_PERR_PM2ULP_DATA_3    7
47181 #define V_PERR_PM2ULP_DATA_3(x) ((x) << S_PERR_PM2ULP_DATA_3)
47182 #define F_PERR_PM2ULP_DATA_3    V_PERR_PM2ULP_DATA_3(1U)
47183 
47184 #define S_PERR_PM2ULP_DATA_2    6
47185 #define V_PERR_PM2ULP_DATA_2(x) ((x) << S_PERR_PM2ULP_DATA_2)
47186 #define F_PERR_PM2ULP_DATA_2    V_PERR_PM2ULP_DATA_2(1U)
47187 
47188 #define S_PERR_PM2ULP_DATA_1    5
47189 #define V_PERR_PM2ULP_DATA_1(x) ((x) << S_PERR_PM2ULP_DATA_1)
47190 #define F_PERR_PM2ULP_DATA_1    V_PERR_PM2ULP_DATA_1(1U)
47191 
47192 #define S_PERR_PM2ULP_DATA_0    4
47193 #define V_PERR_PM2ULP_DATA_0(x) ((x) << S_PERR_PM2ULP_DATA_0)
47194 #define F_PERR_PM2ULP_DATA_0    V_PERR_PM2ULP_DATA_0(1U)
47195 
47196 #define S_PERR_TP2ULP_PCMD_3    3
47197 #define V_PERR_TP2ULP_PCMD_3(x) ((x) << S_PERR_TP2ULP_PCMD_3)
47198 #define F_PERR_TP2ULP_PCMD_3    V_PERR_TP2ULP_PCMD_3(1U)
47199 
47200 #define S_PERR_TP2ULP_PCMD_2    2
47201 #define V_PERR_TP2ULP_PCMD_2(x) ((x) << S_PERR_TP2ULP_PCMD_2)
47202 #define F_PERR_TP2ULP_PCMD_2    V_PERR_TP2ULP_PCMD_2(1U)
47203 
47204 #define S_PERR_TP2ULP_PCMD_1    1
47205 #define V_PERR_TP2ULP_PCMD_1(x) ((x) << S_PERR_TP2ULP_PCMD_1)
47206 #define F_PERR_TP2ULP_PCMD_1    V_PERR_TP2ULP_PCMD_1(1U)
47207 
47208 #define S_PERR_TP2ULP_PCMD_0    0
47209 #define V_PERR_TP2ULP_PCMD_0(x) ((x) << S_PERR_TP2ULP_PCMD_0)
47210 #define F_PERR_TP2ULP_PCMD_0    V_PERR_TP2ULP_PCMD_0(1U)
47211 
47212 #define A_ULP_RX_SE_CNT_ERR 0x191d0
47213 #define A_ULP_RX_SE_CNT_CLR 0x191d4
47214 
47215 #define S_CLRCHAN0    4
47216 #define M_CLRCHAN0    0xfU
47217 #define V_CLRCHAN0(x) ((x) << S_CLRCHAN0)
47218 #define G_CLRCHAN0(x) (((x) >> S_CLRCHAN0) & M_CLRCHAN0)
47219 
47220 #define S_CLRCHAN1    0
47221 #define M_CLRCHAN1    0xfU
47222 #define V_CLRCHAN1(x) ((x) << S_CLRCHAN1)
47223 #define G_CLRCHAN1(x) (((x) >> S_CLRCHAN1) & M_CLRCHAN1)
47224 
47225 #define S_CLRCHAN3    12
47226 #define M_CLRCHAN3    0xfU
47227 #define V_CLRCHAN3(x) ((x) << S_CLRCHAN3)
47228 #define G_CLRCHAN3(x) (((x) >> S_CLRCHAN3) & M_CLRCHAN3)
47229 
47230 #define S_CLRCHAN2    8
47231 #define M_CLRCHAN2    0xfU
47232 #define V_CLRCHAN2(x) ((x) << S_CLRCHAN2)
47233 #define G_CLRCHAN2(x) (((x) >> S_CLRCHAN2) & M_CLRCHAN2)
47234 
47235 #define S_T7_CLRCHAN1    4
47236 #define M_T7_CLRCHAN1    0xfU
47237 #define V_T7_CLRCHAN1(x) ((x) << S_T7_CLRCHAN1)
47238 #define G_T7_CLRCHAN1(x) (((x) >> S_T7_CLRCHAN1) & M_T7_CLRCHAN1)
47239 
47240 #define S_T7_CLRCHAN0    0
47241 #define M_T7_CLRCHAN0    0xfU
47242 #define V_T7_CLRCHAN0(x) ((x) << S_T7_CLRCHAN0)
47243 #define G_T7_CLRCHAN0(x) (((x) >> S_T7_CLRCHAN0) & M_T7_CLRCHAN0)
47244 
47245 #define A_ULP_RX_SE_CNT_CH0 0x191d8
47246 
47247 #define S_SOP_CNT_OUT0    28
47248 #define M_SOP_CNT_OUT0    0xfU
47249 #define V_SOP_CNT_OUT0(x) ((x) << S_SOP_CNT_OUT0)
47250 #define G_SOP_CNT_OUT0(x) (((x) >> S_SOP_CNT_OUT0) & M_SOP_CNT_OUT0)
47251 
47252 #define S_EOP_CNT_OUT0    24
47253 #define M_EOP_CNT_OUT0    0xfU
47254 #define V_EOP_CNT_OUT0(x) ((x) << S_EOP_CNT_OUT0)
47255 #define G_EOP_CNT_OUT0(x) (((x) >> S_EOP_CNT_OUT0) & M_EOP_CNT_OUT0)
47256 
47257 #define S_SOP_CNT_AL0    20
47258 #define M_SOP_CNT_AL0    0xfU
47259 #define V_SOP_CNT_AL0(x) ((x) << S_SOP_CNT_AL0)
47260 #define G_SOP_CNT_AL0(x) (((x) >> S_SOP_CNT_AL0) & M_SOP_CNT_AL0)
47261 
47262 #define S_EOP_CNT_AL0    16
47263 #define M_EOP_CNT_AL0    0xfU
47264 #define V_EOP_CNT_AL0(x) ((x) << S_EOP_CNT_AL0)
47265 #define G_EOP_CNT_AL0(x) (((x) >> S_EOP_CNT_AL0) & M_EOP_CNT_AL0)
47266 
47267 #define S_SOP_CNT_MR0    12
47268 #define M_SOP_CNT_MR0    0xfU
47269 #define V_SOP_CNT_MR0(x) ((x) << S_SOP_CNT_MR0)
47270 #define G_SOP_CNT_MR0(x) (((x) >> S_SOP_CNT_MR0) & M_SOP_CNT_MR0)
47271 
47272 #define S_EOP_CNT_MR0    8
47273 #define M_EOP_CNT_MR0    0xfU
47274 #define V_EOP_CNT_MR0(x) ((x) << S_EOP_CNT_MR0)
47275 #define G_EOP_CNT_MR0(x) (((x) >> S_EOP_CNT_MR0) & M_EOP_CNT_MR0)
47276 
47277 #define S_SOP_CNT_IN0    4
47278 #define M_SOP_CNT_IN0    0xfU
47279 #define V_SOP_CNT_IN0(x) ((x) << S_SOP_CNT_IN0)
47280 #define G_SOP_CNT_IN0(x) (((x) >> S_SOP_CNT_IN0) & M_SOP_CNT_IN0)
47281 
47282 #define S_EOP_CNT_IN0    0
47283 #define M_EOP_CNT_IN0    0xfU
47284 #define V_EOP_CNT_IN0(x) ((x) << S_EOP_CNT_IN0)
47285 #define G_EOP_CNT_IN0(x) (((x) >> S_EOP_CNT_IN0) & M_EOP_CNT_IN0)
47286 
47287 #define A_ULP_RX_SE_CNT_CH1 0x191dc
47288 
47289 #define S_SOP_CNT_OUT1    28
47290 #define M_SOP_CNT_OUT1    0xfU
47291 #define V_SOP_CNT_OUT1(x) ((x) << S_SOP_CNT_OUT1)
47292 #define G_SOP_CNT_OUT1(x) (((x) >> S_SOP_CNT_OUT1) & M_SOP_CNT_OUT1)
47293 
47294 #define S_EOP_CNT_OUT1    24
47295 #define M_EOP_CNT_OUT1    0xfU
47296 #define V_EOP_CNT_OUT1(x) ((x) << S_EOP_CNT_OUT1)
47297 #define G_EOP_CNT_OUT1(x) (((x) >> S_EOP_CNT_OUT1) & M_EOP_CNT_OUT1)
47298 
47299 #define S_SOP_CNT_AL1    20
47300 #define M_SOP_CNT_AL1    0xfU
47301 #define V_SOP_CNT_AL1(x) ((x) << S_SOP_CNT_AL1)
47302 #define G_SOP_CNT_AL1(x) (((x) >> S_SOP_CNT_AL1) & M_SOP_CNT_AL1)
47303 
47304 #define S_EOP_CNT_AL1    16
47305 #define M_EOP_CNT_AL1    0xfU
47306 #define V_EOP_CNT_AL1(x) ((x) << S_EOP_CNT_AL1)
47307 #define G_EOP_CNT_AL1(x) (((x) >> S_EOP_CNT_AL1) & M_EOP_CNT_AL1)
47308 
47309 #define S_SOP_CNT_MR1    12
47310 #define M_SOP_CNT_MR1    0xfU
47311 #define V_SOP_CNT_MR1(x) ((x) << S_SOP_CNT_MR1)
47312 #define G_SOP_CNT_MR1(x) (((x) >> S_SOP_CNT_MR1) & M_SOP_CNT_MR1)
47313 
47314 #define S_EOP_CNT_MR1    8
47315 #define M_EOP_CNT_MR1    0xfU
47316 #define V_EOP_CNT_MR1(x) ((x) << S_EOP_CNT_MR1)
47317 #define G_EOP_CNT_MR1(x) (((x) >> S_EOP_CNT_MR1) & M_EOP_CNT_MR1)
47318 
47319 #define S_SOP_CNT_IN1    4
47320 #define M_SOP_CNT_IN1    0xfU
47321 #define V_SOP_CNT_IN1(x) ((x) << S_SOP_CNT_IN1)
47322 #define G_SOP_CNT_IN1(x) (((x) >> S_SOP_CNT_IN1) & M_SOP_CNT_IN1)
47323 
47324 #define S_EOP_CNT_IN1    0
47325 #define M_EOP_CNT_IN1    0xfU
47326 #define V_EOP_CNT_IN1(x) ((x) << S_EOP_CNT_IN1)
47327 #define G_EOP_CNT_IN1(x) (((x) >> S_EOP_CNT_IN1) & M_EOP_CNT_IN1)
47328 
47329 #define A_ULP_RX_DBG_CTL 0x191e0
47330 
47331 #define S_EN_DBG_H    17
47332 #define V_EN_DBG_H(x) ((x) << S_EN_DBG_H)
47333 #define F_EN_DBG_H    V_EN_DBG_H(1U)
47334 
47335 #define S_EN_DBG_L    16
47336 #define V_EN_DBG_L(x) ((x) << S_EN_DBG_L)
47337 #define F_EN_DBG_L    V_EN_DBG_L(1U)
47338 
47339 #define S_SEL_H    8
47340 #define M_SEL_H    0xffU
47341 #define V_SEL_H(x) ((x) << S_SEL_H)
47342 #define G_SEL_H(x) (((x) >> S_SEL_H) & M_SEL_H)
47343 
47344 #define S_SEL_L    0
47345 #define M_SEL_L    0xffU
47346 #define V_SEL_L(x) ((x) << S_SEL_L)
47347 #define G_SEL_L(x) (((x) >> S_SEL_L) & M_SEL_L)
47348 
47349 #define A_ULP_RX_DBG_DATAH 0x191e4
47350 #define A_ULP_RX_DBG_DATA 0x191e4
47351 #define A_ULP_RX_DBG_DATAL 0x191e8
47352 #define A_ULP_RX_LA_CHNL 0x19238
47353 
47354 #define S_CHNL_SEL    0
47355 #define V_CHNL_SEL(x) ((x) << S_CHNL_SEL)
47356 #define F_CHNL_SEL    V_CHNL_SEL(1U)
47357 
47358 #define A_ULP_RX_LA_CTL 0x1923c
47359 
47360 #define S_TRC_SEL    0
47361 #define V_TRC_SEL(x) ((x) << S_TRC_SEL)
47362 #define F_TRC_SEL    V_TRC_SEL(1U)
47363 
47364 #define A_ULP_RX_LA_RDPTR 0x19240
47365 
47366 #define S_RD_PTR    0
47367 #define M_RD_PTR    0x1ffU
47368 #define V_RD_PTR(x) ((x) << S_RD_PTR)
47369 #define G_RD_PTR(x) (((x) >> S_RD_PTR) & M_RD_PTR)
47370 
47371 #define A_ULP_RX_LA_RDDATA 0x19244
47372 #define A_ULP_RX_LA_WRPTR 0x19248
47373 
47374 #define S_WR_PTR    0
47375 #define M_WR_PTR    0x1ffU
47376 #define V_WR_PTR(x) ((x) << S_WR_PTR)
47377 #define G_WR_PTR(x) (((x) >> S_WR_PTR) & M_WR_PTR)
47378 
47379 #define A_ULP_RX_LA_RESERVED 0x1924c
47380 #define A_ULP_RX_CQE_GEN_EN 0x19250
47381 
47382 #define S_TERMIMATE_MSG    1
47383 #define V_TERMIMATE_MSG(x) ((x) << S_TERMIMATE_MSG)
47384 #define F_TERMIMATE_MSG    V_TERMIMATE_MSG(1U)
47385 
47386 #define S_TERMINATE_WITH_ERR    0
47387 #define V_TERMINATE_WITH_ERR(x) ((x) << S_TERMINATE_WITH_ERR)
47388 #define F_TERMINATE_WITH_ERR    V_TERMINATE_WITH_ERR(1U)
47389 
47390 #define A_ULP_RX_ATOMIC_OPCODES 0x19254
47391 
47392 #define S_ATOMIC_REQ_QNO    22
47393 #define M_ATOMIC_REQ_QNO    0x3U
47394 #define V_ATOMIC_REQ_QNO(x) ((x) << S_ATOMIC_REQ_QNO)
47395 #define G_ATOMIC_REQ_QNO(x) (((x) >> S_ATOMIC_REQ_QNO) & M_ATOMIC_REQ_QNO)
47396 
47397 #define S_ATOMIC_RSP_QNO    20
47398 #define M_ATOMIC_RSP_QNO    0x3U
47399 #define V_ATOMIC_RSP_QNO(x) ((x) << S_ATOMIC_RSP_QNO)
47400 #define G_ATOMIC_RSP_QNO(x) (((x) >> S_ATOMIC_RSP_QNO) & M_ATOMIC_RSP_QNO)
47401 
47402 #define S_IMMEDIATE_QNO    18
47403 #define M_IMMEDIATE_QNO    0x3U
47404 #define V_IMMEDIATE_QNO(x) ((x) << S_IMMEDIATE_QNO)
47405 #define G_IMMEDIATE_QNO(x) (((x) >> S_IMMEDIATE_QNO) & M_IMMEDIATE_QNO)
47406 
47407 #define S_IMMEDIATE_WITH_SE_QNO    16
47408 #define M_IMMEDIATE_WITH_SE_QNO    0x3U
47409 #define V_IMMEDIATE_WITH_SE_QNO(x) ((x) << S_IMMEDIATE_WITH_SE_QNO)
47410 #define G_IMMEDIATE_WITH_SE_QNO(x) (((x) >> S_IMMEDIATE_WITH_SE_QNO) & M_IMMEDIATE_WITH_SE_QNO)
47411 
47412 #define S_ATOMIC_WR_OPCODE    12
47413 #define M_ATOMIC_WR_OPCODE    0xfU
47414 #define V_ATOMIC_WR_OPCODE(x) ((x) << S_ATOMIC_WR_OPCODE)
47415 #define G_ATOMIC_WR_OPCODE(x) (((x) >> S_ATOMIC_WR_OPCODE) & M_ATOMIC_WR_OPCODE)
47416 
47417 #define S_ATOMIC_RD_OPCODE    8
47418 #define M_ATOMIC_RD_OPCODE    0xfU
47419 #define V_ATOMIC_RD_OPCODE(x) ((x) << S_ATOMIC_RD_OPCODE)
47420 #define G_ATOMIC_RD_OPCODE(x) (((x) >> S_ATOMIC_RD_OPCODE) & M_ATOMIC_RD_OPCODE)
47421 
47422 #define S_IMMEDIATE_OPCODE    4
47423 #define M_IMMEDIATE_OPCODE    0xfU
47424 #define V_IMMEDIATE_OPCODE(x) ((x) << S_IMMEDIATE_OPCODE)
47425 #define G_IMMEDIATE_OPCODE(x) (((x) >> S_IMMEDIATE_OPCODE) & M_IMMEDIATE_OPCODE)
47426 
47427 #define S_IMMEDIATE_WITH_SE_OPCODE    0
47428 #define M_IMMEDIATE_WITH_SE_OPCODE    0xfU
47429 #define V_IMMEDIATE_WITH_SE_OPCODE(x) ((x) << S_IMMEDIATE_WITH_SE_OPCODE)
47430 #define G_IMMEDIATE_WITH_SE_OPCODE(x) (((x) >> S_IMMEDIATE_WITH_SE_OPCODE) & M_IMMEDIATE_WITH_SE_OPCODE)
47431 
47432 #define A_ULP_RX_T10_CRC_ENDIAN_SWITCHING 0x19258
47433 
47434 #define S_EN_ORIG_DATA    0
47435 #define V_EN_ORIG_DATA(x) ((x) << S_EN_ORIG_DATA)
47436 #define F_EN_ORIG_DATA    V_EN_ORIG_DATA(1U)
47437 
47438 #define A_ULP_RX_MISC_FEATURE_ENABLE 0x1925c
47439 
47440 #define S_TERMINATE_STATUS_EN    4
47441 #define V_TERMINATE_STATUS_EN(x) ((x) << S_TERMINATE_STATUS_EN)
47442 #define F_TERMINATE_STATUS_EN    V_TERMINATE_STATUS_EN(1U)
47443 
47444 #define S_MULTIPLE_PREF_ENABLE    3
47445 #define V_MULTIPLE_PREF_ENABLE(x) ((x) << S_MULTIPLE_PREF_ENABLE)
47446 #define F_MULTIPLE_PREF_ENABLE    V_MULTIPLE_PREF_ENABLE(1U)
47447 
47448 #define S_UMUDP_PBL_PREF_ENABLE    2
47449 #define V_UMUDP_PBL_PREF_ENABLE(x) ((x) << S_UMUDP_PBL_PREF_ENABLE)
47450 #define F_UMUDP_PBL_PREF_ENABLE    V_UMUDP_PBL_PREF_ENABLE(1U)
47451 
47452 #define S_RDMA_PBL_PREF_EN    1
47453 #define V_RDMA_PBL_PREF_EN(x) ((x) << S_RDMA_PBL_PREF_EN)
47454 #define F_RDMA_PBL_PREF_EN    V_RDMA_PBL_PREF_EN(1U)
47455 
47456 #define S_SDC_CRC_PROT_EN    0
47457 #define V_SDC_CRC_PROT_EN(x) ((x) << S_SDC_CRC_PROT_EN)
47458 #define F_SDC_CRC_PROT_EN    V_SDC_CRC_PROT_EN(1U)
47459 
47460 #define S_ISCSI_DCRC_ERROR_CMP_EN    25
47461 #define V_ISCSI_DCRC_ERROR_CMP_EN(x) ((x) << S_ISCSI_DCRC_ERROR_CMP_EN)
47462 #define F_ISCSI_DCRC_ERROR_CMP_EN    V_ISCSI_DCRC_ERROR_CMP_EN(1U)
47463 
47464 #define S_ISCSITAGPI    24
47465 #define V_ISCSITAGPI(x) ((x) << S_ISCSITAGPI)
47466 #define F_ISCSITAGPI    V_ISCSITAGPI(1U)
47467 
47468 #define S_DDP_VERSION_1    22
47469 #define M_DDP_VERSION_1    0x3U
47470 #define V_DDP_VERSION_1(x) ((x) << S_DDP_VERSION_1)
47471 #define G_DDP_VERSION_1(x) (((x) >> S_DDP_VERSION_1) & M_DDP_VERSION_1)
47472 
47473 #define S_DDP_VERSION_0    20
47474 #define M_DDP_VERSION_0    0x3U
47475 #define V_DDP_VERSION_0(x) ((x) << S_DDP_VERSION_0)
47476 #define G_DDP_VERSION_0(x) (((x) >> S_DDP_VERSION_0) & M_DDP_VERSION_0)
47477 
47478 #define S_RDMA_VERSION_1    18
47479 #define M_RDMA_VERSION_1    0x3U
47480 #define V_RDMA_VERSION_1(x) ((x) << S_RDMA_VERSION_1)
47481 #define G_RDMA_VERSION_1(x) (((x) >> S_RDMA_VERSION_1) & M_RDMA_VERSION_1)
47482 
47483 #define S_RDMA_VERSION_0    16
47484 #define M_RDMA_VERSION_0    0x3U
47485 #define V_RDMA_VERSION_0(x) ((x) << S_RDMA_VERSION_0)
47486 #define G_RDMA_VERSION_0(x) (((x) >> S_RDMA_VERSION_0) & M_RDMA_VERSION_0)
47487 
47488 #define S_PBL_BOUND_CHECK_W_PGLEN    15
47489 #define V_PBL_BOUND_CHECK_W_PGLEN(x) ((x) << S_PBL_BOUND_CHECK_W_PGLEN)
47490 #define F_PBL_BOUND_CHECK_W_PGLEN    V_PBL_BOUND_CHECK_W_PGLEN(1U)
47491 
47492 #define S_ZBYTE_FIX_DISABLE    14
47493 #define V_ZBYTE_FIX_DISABLE(x) ((x) << S_ZBYTE_FIX_DISABLE)
47494 #define F_ZBYTE_FIX_DISABLE    V_ZBYTE_FIX_DISABLE(1U)
47495 
47496 #define S_T10_OFFSET_UPDATE_EN    13
47497 #define V_T10_OFFSET_UPDATE_EN(x) ((x) << S_T10_OFFSET_UPDATE_EN)
47498 #define F_T10_OFFSET_UPDATE_EN    V_T10_OFFSET_UPDATE_EN(1U)
47499 
47500 #define S_ULP_INSERT_PI    12
47501 #define V_ULP_INSERT_PI(x) ((x) << S_ULP_INSERT_PI)
47502 #define F_ULP_INSERT_PI    V_ULP_INSERT_PI(1U)
47503 
47504 #define S_PDU_DPI    11
47505 #define V_PDU_DPI(x) ((x) << S_PDU_DPI)
47506 #define F_PDU_DPI    V_PDU_DPI(1U)
47507 
47508 #define S_ISCSI_EFF_OFFSET_EN    10
47509 #define V_ISCSI_EFF_OFFSET_EN(x) ((x) << S_ISCSI_EFF_OFFSET_EN)
47510 #define F_ISCSI_EFF_OFFSET_EN    V_ISCSI_EFF_OFFSET_EN(1U)
47511 
47512 #define S_ISCSI_ALL_CMP_MODE    9
47513 #define V_ISCSI_ALL_CMP_MODE(x) ((x) << S_ISCSI_ALL_CMP_MODE)
47514 #define F_ISCSI_ALL_CMP_MODE    V_ISCSI_ALL_CMP_MODE(1U)
47515 
47516 #define S_ISCSI_ENABLE_HDR_CMD    8
47517 #define V_ISCSI_ENABLE_HDR_CMD(x) ((x) << S_ISCSI_ENABLE_HDR_CMD)
47518 #define F_ISCSI_ENABLE_HDR_CMD    V_ISCSI_ENABLE_HDR_CMD(1U)
47519 
47520 #define S_ISCSI_FORCE_CMP_MODE    7
47521 #define V_ISCSI_FORCE_CMP_MODE(x) ((x) << S_ISCSI_FORCE_CMP_MODE)
47522 #define F_ISCSI_FORCE_CMP_MODE    V_ISCSI_FORCE_CMP_MODE(1U)
47523 
47524 #define S_ISCSI_ENABLE_CMP_MODE    6
47525 #define V_ISCSI_ENABLE_CMP_MODE(x) ((x) << S_ISCSI_ENABLE_CMP_MODE)
47526 #define F_ISCSI_ENABLE_CMP_MODE    V_ISCSI_ENABLE_CMP_MODE(1U)
47527 
47528 #define S_PIO_RDMA_SEND_RQE    5
47529 #define V_PIO_RDMA_SEND_RQE(x) ((x) << S_PIO_RDMA_SEND_RQE)
47530 #define F_PIO_RDMA_SEND_RQE    V_PIO_RDMA_SEND_RQE(1U)
47531 
47532 #define S_TLS_KEYSIZECONF    26
47533 #define M_TLS_KEYSIZECONF    0x3U
47534 #define V_TLS_KEYSIZECONF(x) ((x) << S_TLS_KEYSIZECONF)
47535 #define G_TLS_KEYSIZECONF(x) (((x) >> S_TLS_KEYSIZECONF) & M_TLS_KEYSIZECONF)
47536 
47537 #define A_ULP_RX_CH0_CGEN 0x19260
47538 
47539 #define S_BYPASS_CGEN    7
47540 #define V_BYPASS_CGEN(x) ((x) << S_BYPASS_CGEN)
47541 #define F_BYPASS_CGEN    V_BYPASS_CGEN(1U)
47542 
47543 #define S_TDDP_CGEN    6
47544 #define V_TDDP_CGEN(x) ((x) << S_TDDP_CGEN)
47545 #define F_TDDP_CGEN    V_TDDP_CGEN(1U)
47546 
47547 #define S_ISCSI_CGEN    5
47548 #define V_ISCSI_CGEN(x) ((x) << S_ISCSI_CGEN)
47549 #define F_ISCSI_CGEN    V_ISCSI_CGEN(1U)
47550 
47551 #define S_RDMA_CGEN    4
47552 #define V_RDMA_CGEN(x) ((x) << S_RDMA_CGEN)
47553 #define F_RDMA_CGEN    V_RDMA_CGEN(1U)
47554 
47555 #define S_CHANNEL_CGEN    3
47556 #define V_CHANNEL_CGEN(x) ((x) << S_CHANNEL_CGEN)
47557 #define F_CHANNEL_CGEN    V_CHANNEL_CGEN(1U)
47558 
47559 #define S_ALL_DATAPATH_CGEN    2
47560 #define V_ALL_DATAPATH_CGEN(x) ((x) << S_ALL_DATAPATH_CGEN)
47561 #define F_ALL_DATAPATH_CGEN    V_ALL_DATAPATH_CGEN(1U)
47562 
47563 #define S_T10DIFF_DATAPATH_CGEN    1
47564 #define V_T10DIFF_DATAPATH_CGEN(x) ((x) << S_T10DIFF_DATAPATH_CGEN)
47565 #define F_T10DIFF_DATAPATH_CGEN    V_T10DIFF_DATAPATH_CGEN(1U)
47566 
47567 #define S_RDMA_DATAPATH_CGEN    0
47568 #define V_RDMA_DATAPATH_CGEN(x) ((x) << S_RDMA_DATAPATH_CGEN)
47569 #define F_RDMA_DATAPATH_CGEN    V_RDMA_DATAPATH_CGEN(1U)
47570 
47571 #define A_ULP_RX_CH_CGEN 0x19260
47572 
47573 #define S_T7_BYPASS_CGEN    28
47574 #define M_T7_BYPASS_CGEN    0xfU
47575 #define V_T7_BYPASS_CGEN(x) ((x) << S_T7_BYPASS_CGEN)
47576 #define G_T7_BYPASS_CGEN(x) (((x) >> S_T7_BYPASS_CGEN) & M_T7_BYPASS_CGEN)
47577 
47578 #define S_T7_TDDP_CGEN    24
47579 #define M_T7_TDDP_CGEN    0xfU
47580 #define V_T7_TDDP_CGEN(x) ((x) << S_T7_TDDP_CGEN)
47581 #define G_T7_TDDP_CGEN(x) (((x) >> S_T7_TDDP_CGEN) & M_T7_TDDP_CGEN)
47582 
47583 #define S_T7_ISCSI_CGEN    20
47584 #define M_T7_ISCSI_CGEN    0xfU
47585 #define V_T7_ISCSI_CGEN(x) ((x) << S_T7_ISCSI_CGEN)
47586 #define G_T7_ISCSI_CGEN(x) (((x) >> S_T7_ISCSI_CGEN) & M_T7_ISCSI_CGEN)
47587 
47588 #define S_T7_RDMA_CGEN    16
47589 #define M_T7_RDMA_CGEN    0xfU
47590 #define V_T7_RDMA_CGEN(x) ((x) << S_T7_RDMA_CGEN)
47591 #define G_T7_RDMA_CGEN(x) (((x) >> S_T7_RDMA_CGEN) & M_T7_RDMA_CGEN)
47592 
47593 #define S_T7_CHANNEL_CGEN    12
47594 #define M_T7_CHANNEL_CGEN    0xfU
47595 #define V_T7_CHANNEL_CGEN(x) ((x) << S_T7_CHANNEL_CGEN)
47596 #define G_T7_CHANNEL_CGEN(x) (((x) >> S_T7_CHANNEL_CGEN) & M_T7_CHANNEL_CGEN)
47597 
47598 #define S_T7_ALL_DATAPATH_CGEN    8
47599 #define M_T7_ALL_DATAPATH_CGEN    0xfU
47600 #define V_T7_ALL_DATAPATH_CGEN(x) ((x) << S_T7_ALL_DATAPATH_CGEN)
47601 #define G_T7_ALL_DATAPATH_CGEN(x) (((x) >> S_T7_ALL_DATAPATH_CGEN) & M_T7_ALL_DATAPATH_CGEN)
47602 
47603 #define S_T7_T10DIFF_DATAPATH_CGEN    4
47604 #define M_T7_T10DIFF_DATAPATH_CGEN    0xfU
47605 #define V_T7_T10DIFF_DATAPATH_CGEN(x) ((x) << S_T7_T10DIFF_DATAPATH_CGEN)
47606 #define G_T7_T10DIFF_DATAPATH_CGEN(x) (((x) >> S_T7_T10DIFF_DATAPATH_CGEN) & M_T7_T10DIFF_DATAPATH_CGEN)
47607 
47608 #define S_T7_RDMA_DATAPATH_CGEN    0
47609 #define M_T7_RDMA_DATAPATH_CGEN    0xfU
47610 #define V_T7_RDMA_DATAPATH_CGEN(x) ((x) << S_T7_RDMA_DATAPATH_CGEN)
47611 #define G_T7_RDMA_DATAPATH_CGEN(x) (((x) >> S_T7_RDMA_DATAPATH_CGEN) & M_T7_RDMA_DATAPATH_CGEN)
47612 
47613 #define A_ULP_RX_CH1_CGEN 0x19264
47614 #define A_ULP_RX_CH_CGEN_1 0x19264
47615 
47616 #define S_NVME_TCP_CGEN    4
47617 #define M_NVME_TCP_CGEN    0xfU
47618 #define V_NVME_TCP_CGEN(x) ((x) << S_NVME_TCP_CGEN)
47619 #define G_NVME_TCP_CGEN(x) (((x) >> S_NVME_TCP_CGEN) & M_NVME_TCP_CGEN)
47620 
47621 #define S_ROCE_CGEN    0
47622 #define M_ROCE_CGEN    0xfU
47623 #define V_ROCE_CGEN(x) ((x) << S_ROCE_CGEN)
47624 #define G_ROCE_CGEN(x) (((x) >> S_ROCE_CGEN) & M_ROCE_CGEN)
47625 
47626 #define A_ULP_RX_RFE_DISABLE 0x19268
47627 
47628 #define S_RQE_LIM_CHECK_RFE_DISABLE    0
47629 #define V_RQE_LIM_CHECK_RFE_DISABLE(x) ((x) << S_RQE_LIM_CHECK_RFE_DISABLE)
47630 #define F_RQE_LIM_CHECK_RFE_DISABLE    V_RQE_LIM_CHECK_RFE_DISABLE(1U)
47631 
47632 #define A_ULP_RX_INT_ENABLE_2 0x1926c
47633 
47634 #define S_ULPRX2MA_INTFPERR    8
47635 #define V_ULPRX2MA_INTFPERR(x) ((x) << S_ULPRX2MA_INTFPERR)
47636 #define F_ULPRX2MA_INTFPERR    V_ULPRX2MA_INTFPERR(1U)
47637 
47638 #define S_ALN_SDC_ERR_1    7
47639 #define V_ALN_SDC_ERR_1(x) ((x) << S_ALN_SDC_ERR_1)
47640 #define F_ALN_SDC_ERR_1    V_ALN_SDC_ERR_1(1U)
47641 
47642 #define S_ALN_SDC_ERR_0    6
47643 #define V_ALN_SDC_ERR_0(x) ((x) << S_ALN_SDC_ERR_0)
47644 #define F_ALN_SDC_ERR_0    V_ALN_SDC_ERR_0(1U)
47645 
47646 #define S_PF_UNTAGGED_TPT_1    5
47647 #define V_PF_UNTAGGED_TPT_1(x) ((x) << S_PF_UNTAGGED_TPT_1)
47648 #define F_PF_UNTAGGED_TPT_1    V_PF_UNTAGGED_TPT_1(1U)
47649 
47650 #define S_PF_UNTAGGED_TPT_0    4
47651 #define V_PF_UNTAGGED_TPT_0(x) ((x) << S_PF_UNTAGGED_TPT_0)
47652 #define F_PF_UNTAGGED_TPT_0    V_PF_UNTAGGED_TPT_0(1U)
47653 
47654 #define S_PF_PBL_1    3
47655 #define V_PF_PBL_1(x) ((x) << S_PF_PBL_1)
47656 #define F_PF_PBL_1    V_PF_PBL_1(1U)
47657 
47658 #define S_PF_PBL_0    2
47659 #define V_PF_PBL_0(x) ((x) << S_PF_PBL_0)
47660 #define F_PF_PBL_0    V_PF_PBL_0(1U)
47661 
47662 #define S_DDP_HINT_1    1
47663 #define V_DDP_HINT_1(x) ((x) << S_DDP_HINT_1)
47664 #define F_DDP_HINT_1    V_DDP_HINT_1(1U)
47665 
47666 #define S_DDP_HINT_0    0
47667 #define V_DDP_HINT_0(x) ((x) << S_DDP_HINT_0)
47668 #define F_DDP_HINT_0    V_DDP_HINT_0(1U)
47669 
47670 #define A_ULP_RX_INT_CAUSE_2 0x19270
47671 #define A_ULP_RX_PERR_ENABLE_2 0x19274
47672 
47673 #define S_ENABLE_ULPRX2MA_INTFPERR    8
47674 #define V_ENABLE_ULPRX2MA_INTFPERR(x) ((x) << S_ENABLE_ULPRX2MA_INTFPERR)
47675 #define F_ENABLE_ULPRX2MA_INTFPERR    V_ENABLE_ULPRX2MA_INTFPERR(1U)
47676 
47677 #define S_ENABLE_ALN_SDC_ERR_1    7
47678 #define V_ENABLE_ALN_SDC_ERR_1(x) ((x) << S_ENABLE_ALN_SDC_ERR_1)
47679 #define F_ENABLE_ALN_SDC_ERR_1    V_ENABLE_ALN_SDC_ERR_1(1U)
47680 
47681 #define S_ENABLE_ALN_SDC_ERR_0    6
47682 #define V_ENABLE_ALN_SDC_ERR_0(x) ((x) << S_ENABLE_ALN_SDC_ERR_0)
47683 #define F_ENABLE_ALN_SDC_ERR_0    V_ENABLE_ALN_SDC_ERR_0(1U)
47684 
47685 #define S_ENABLE_PF_UNTAGGED_TPT_1    5
47686 #define V_ENABLE_PF_UNTAGGED_TPT_1(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_1)
47687 #define F_ENABLE_PF_UNTAGGED_TPT_1    V_ENABLE_PF_UNTAGGED_TPT_1(1U)
47688 
47689 #define S_ENABLE_PF_UNTAGGED_TPT_0    4
47690 #define V_ENABLE_PF_UNTAGGED_TPT_0(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_0)
47691 #define F_ENABLE_PF_UNTAGGED_TPT_0    V_ENABLE_PF_UNTAGGED_TPT_0(1U)
47692 
47693 #define S_ENABLE_PF_PBL_1    3
47694 #define V_ENABLE_PF_PBL_1(x) ((x) << S_ENABLE_PF_PBL_1)
47695 #define F_ENABLE_PF_PBL_1    V_ENABLE_PF_PBL_1(1U)
47696 
47697 #define S_ENABLE_PF_PBL_0    2
47698 #define V_ENABLE_PF_PBL_0(x) ((x) << S_ENABLE_PF_PBL_0)
47699 #define F_ENABLE_PF_PBL_0    V_ENABLE_PF_PBL_0(1U)
47700 
47701 #define S_ENABLE_DDP_HINT_1    1
47702 #define V_ENABLE_DDP_HINT_1(x) ((x) << S_ENABLE_DDP_HINT_1)
47703 #define F_ENABLE_DDP_HINT_1    V_ENABLE_DDP_HINT_1(1U)
47704 
47705 #define S_ENABLE_DDP_HINT_0    0
47706 #define V_ENABLE_DDP_HINT_0(x) ((x) << S_ENABLE_DDP_HINT_0)
47707 #define F_ENABLE_DDP_HINT_0    V_ENABLE_DDP_HINT_0(1U)
47708 
47709 #define A_ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT 0x19278
47710 
47711 #define S_PIO_RQE_PBL_MULTIPLE_CNT    0
47712 #define M_PIO_RQE_PBL_MULTIPLE_CNT    0xfU
47713 #define V_PIO_RQE_PBL_MULTIPLE_CNT(x) ((x) << S_PIO_RQE_PBL_MULTIPLE_CNT)
47714 #define G_PIO_RQE_PBL_MULTIPLE_CNT(x) (((x) >> S_PIO_RQE_PBL_MULTIPLE_CNT) & M_PIO_RQE_PBL_MULTIPLE_CNT)
47715 
47716 #define A_ULP_RX_ATOMIC_LEN 0x1927c
47717 
47718 #define S_ATOMIC_RPL_LEN    16
47719 #define M_ATOMIC_RPL_LEN    0xffU
47720 #define V_ATOMIC_RPL_LEN(x) ((x) << S_ATOMIC_RPL_LEN)
47721 #define G_ATOMIC_RPL_LEN(x) (((x) >> S_ATOMIC_RPL_LEN) & M_ATOMIC_RPL_LEN)
47722 
47723 #define S_ATOMIC_REQ_LEN    8
47724 #define M_ATOMIC_REQ_LEN    0xffU
47725 #define V_ATOMIC_REQ_LEN(x) ((x) << S_ATOMIC_REQ_LEN)
47726 #define G_ATOMIC_REQ_LEN(x) (((x) >> S_ATOMIC_REQ_LEN) & M_ATOMIC_REQ_LEN)
47727 
47728 #define S_ATOMIC_IMMEDIATE_LEN    0
47729 #define M_ATOMIC_IMMEDIATE_LEN    0xffU
47730 #define V_ATOMIC_IMMEDIATE_LEN(x) ((x) << S_ATOMIC_IMMEDIATE_LEN)
47731 #define G_ATOMIC_IMMEDIATE_LEN(x) (((x) >> S_ATOMIC_IMMEDIATE_LEN) & M_ATOMIC_IMMEDIATE_LEN)
47732 
47733 #define A_ULP_RX_CGEN_GLOBAL 0x19280
47734 #define A_ULP_RX_CTX_SKIP_MA_REQ 0x19284
47735 
47736 #define S_CLEAR_CTX_ERR_CNT1    3
47737 #define V_CLEAR_CTX_ERR_CNT1(x) ((x) << S_CLEAR_CTX_ERR_CNT1)
47738 #define F_CLEAR_CTX_ERR_CNT1    V_CLEAR_CTX_ERR_CNT1(1U)
47739 
47740 #define S_CLEAR_CTX_ERR_CNT0    2
47741 #define V_CLEAR_CTX_ERR_CNT0(x) ((x) << S_CLEAR_CTX_ERR_CNT0)
47742 #define F_CLEAR_CTX_ERR_CNT0    V_CLEAR_CTX_ERR_CNT0(1U)
47743 
47744 #define S_SKIP_MA_REQ_EN1    1
47745 #define V_SKIP_MA_REQ_EN1(x) ((x) << S_SKIP_MA_REQ_EN1)
47746 #define F_SKIP_MA_REQ_EN1    V_SKIP_MA_REQ_EN1(1U)
47747 
47748 #define S_SKIP_MA_REQ_EN0    0
47749 #define V_SKIP_MA_REQ_EN0(x) ((x) << S_SKIP_MA_REQ_EN0)
47750 #define F_SKIP_MA_REQ_EN0    V_SKIP_MA_REQ_EN0(1U)
47751 
47752 #define S_CLEAR_CTX_ERR_CNT3    7
47753 #define V_CLEAR_CTX_ERR_CNT3(x) ((x) << S_CLEAR_CTX_ERR_CNT3)
47754 #define F_CLEAR_CTX_ERR_CNT3    V_CLEAR_CTX_ERR_CNT3(1U)
47755 
47756 #define S_CLEAR_CTX_ERR_CNT2    6
47757 #define V_CLEAR_CTX_ERR_CNT2(x) ((x) << S_CLEAR_CTX_ERR_CNT2)
47758 #define F_CLEAR_CTX_ERR_CNT2    V_CLEAR_CTX_ERR_CNT2(1U)
47759 
47760 #define S_T7_CLEAR_CTX_ERR_CNT1    5
47761 #define V_T7_CLEAR_CTX_ERR_CNT1(x) ((x) << S_T7_CLEAR_CTX_ERR_CNT1)
47762 #define F_T7_CLEAR_CTX_ERR_CNT1    V_T7_CLEAR_CTX_ERR_CNT1(1U)
47763 
47764 #define S_T7_CLEAR_CTX_ERR_CNT0    4
47765 #define V_T7_CLEAR_CTX_ERR_CNT0(x) ((x) << S_T7_CLEAR_CTX_ERR_CNT0)
47766 #define F_T7_CLEAR_CTX_ERR_CNT0    V_T7_CLEAR_CTX_ERR_CNT0(1U)
47767 
47768 #define S_SKIP_MA_REQ_EN3    3
47769 #define V_SKIP_MA_REQ_EN3(x) ((x) << S_SKIP_MA_REQ_EN3)
47770 #define F_SKIP_MA_REQ_EN3    V_SKIP_MA_REQ_EN3(1U)
47771 
47772 #define S_SKIP_MA_REQ_EN2    2
47773 #define V_SKIP_MA_REQ_EN2(x) ((x) << S_SKIP_MA_REQ_EN2)
47774 #define F_SKIP_MA_REQ_EN2    V_SKIP_MA_REQ_EN2(1U)
47775 
47776 #define A_ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID 0x19288
47777 #define A_ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID 0x1928c
47778 #define A_ULP_RX_MSN_CHECK_ENABLE 0x19290
47779 
47780 #define S_RD_OR_TERM_MSN_CHECK_ENABLE    2
47781 #define V_RD_OR_TERM_MSN_CHECK_ENABLE(x) ((x) << S_RD_OR_TERM_MSN_CHECK_ENABLE)
47782 #define F_RD_OR_TERM_MSN_CHECK_ENABLE    V_RD_OR_TERM_MSN_CHECK_ENABLE(1U)
47783 
47784 #define S_ATOMIC_OP_MSN_CHECK_ENABLE    1
47785 #define V_ATOMIC_OP_MSN_CHECK_ENABLE(x) ((x) << S_ATOMIC_OP_MSN_CHECK_ENABLE)
47786 #define F_ATOMIC_OP_MSN_CHECK_ENABLE    V_ATOMIC_OP_MSN_CHECK_ENABLE(1U)
47787 
47788 #define S_SEND_MSN_CHECK_ENABLE    0
47789 #define V_SEND_MSN_CHECK_ENABLE(x) ((x) << S_SEND_MSN_CHECK_ENABLE)
47790 #define F_SEND_MSN_CHECK_ENABLE    V_SEND_MSN_CHECK_ENABLE(1U)
47791 
47792 #define A_ULP_RX_SE_CNT_CH2 0x19294
47793 
47794 #define S_SOP_CNT_OUT2    28
47795 #define M_SOP_CNT_OUT2    0xfU
47796 #define V_SOP_CNT_OUT2(x) ((x) << S_SOP_CNT_OUT2)
47797 #define G_SOP_CNT_OUT2(x) (((x) >> S_SOP_CNT_OUT2) & M_SOP_CNT_OUT2)
47798 
47799 #define S_EOP_CNT_OUT2    24
47800 #define M_EOP_CNT_OUT2    0xfU
47801 #define V_EOP_CNT_OUT2(x) ((x) << S_EOP_CNT_OUT2)
47802 #define G_EOP_CNT_OUT2(x) (((x) >> S_EOP_CNT_OUT2) & M_EOP_CNT_OUT2)
47803 
47804 #define S_SOP_CNT_AL2    20
47805 #define M_SOP_CNT_AL2    0xfU
47806 #define V_SOP_CNT_AL2(x) ((x) << S_SOP_CNT_AL2)
47807 #define G_SOP_CNT_AL2(x) (((x) >> S_SOP_CNT_AL2) & M_SOP_CNT_AL2)
47808 
47809 #define S_EOP_CNT_AL2    16
47810 #define M_EOP_CNT_AL2    0xfU
47811 #define V_EOP_CNT_AL2(x) ((x) << S_EOP_CNT_AL2)
47812 #define G_EOP_CNT_AL2(x) (((x) >> S_EOP_CNT_AL2) & M_EOP_CNT_AL2)
47813 
47814 #define S_SOP_CNT_MR2    12
47815 #define M_SOP_CNT_MR2    0xfU
47816 #define V_SOP_CNT_MR2(x) ((x) << S_SOP_CNT_MR2)
47817 #define G_SOP_CNT_MR2(x) (((x) >> S_SOP_CNT_MR2) & M_SOP_CNT_MR2)
47818 
47819 #define S_EOP_CNT_MR2    8
47820 #define M_EOP_CNT_MR2    0xfU
47821 #define V_EOP_CNT_MR2(x) ((x) << S_EOP_CNT_MR2)
47822 #define G_EOP_CNT_MR2(x) (((x) >> S_EOP_CNT_MR2) & M_EOP_CNT_MR2)
47823 
47824 #define S_SOP_CNT_IN2    4
47825 #define M_SOP_CNT_IN2    0xfU
47826 #define V_SOP_CNT_IN2(x) ((x) << S_SOP_CNT_IN2)
47827 #define G_SOP_CNT_IN2(x) (((x) >> S_SOP_CNT_IN2) & M_SOP_CNT_IN2)
47828 
47829 #define S_EOP_CNT_IN2    0
47830 #define M_EOP_CNT_IN2    0xfU
47831 #define V_EOP_CNT_IN2(x) ((x) << S_EOP_CNT_IN2)
47832 #define G_EOP_CNT_IN2(x) (((x) >> S_EOP_CNT_IN2) & M_EOP_CNT_IN2)
47833 
47834 #define A_ULP_RX_SE_CNT_CH3 0x19298
47835 
47836 #define S_SOP_CNT_OUT3    28
47837 #define M_SOP_CNT_OUT3    0xfU
47838 #define V_SOP_CNT_OUT3(x) ((x) << S_SOP_CNT_OUT3)
47839 #define G_SOP_CNT_OUT3(x) (((x) >> S_SOP_CNT_OUT3) & M_SOP_CNT_OUT3)
47840 
47841 #define S_EOP_CNT_OUT3    24
47842 #define M_EOP_CNT_OUT3    0xfU
47843 #define V_EOP_CNT_OUT3(x) ((x) << S_EOP_CNT_OUT3)
47844 #define G_EOP_CNT_OUT3(x) (((x) >> S_EOP_CNT_OUT3) & M_EOP_CNT_OUT3)
47845 
47846 #define S_SOP_CNT_AL3    20
47847 #define M_SOP_CNT_AL3    0xfU
47848 #define V_SOP_CNT_AL3(x) ((x) << S_SOP_CNT_AL3)
47849 #define G_SOP_CNT_AL3(x) (((x) >> S_SOP_CNT_AL3) & M_SOP_CNT_AL3)
47850 
47851 #define S_EOP_CNT_AL3    16
47852 #define M_EOP_CNT_AL3    0xfU
47853 #define V_EOP_CNT_AL3(x) ((x) << S_EOP_CNT_AL3)
47854 #define G_EOP_CNT_AL3(x) (((x) >> S_EOP_CNT_AL3) & M_EOP_CNT_AL3)
47855 
47856 #define S_SOP_CNT_MR3    12
47857 #define M_SOP_CNT_MR3    0xfU
47858 #define V_SOP_CNT_MR3(x) ((x) << S_SOP_CNT_MR3)
47859 #define G_SOP_CNT_MR3(x) (((x) >> S_SOP_CNT_MR3) & M_SOP_CNT_MR3)
47860 
47861 #define S_EOP_CNT_MR3    8
47862 #define M_EOP_CNT_MR3    0xfU
47863 #define V_EOP_CNT_MR3(x) ((x) << S_EOP_CNT_MR3)
47864 #define G_EOP_CNT_MR3(x) (((x) >> S_EOP_CNT_MR3) & M_EOP_CNT_MR3)
47865 
47866 #define S_SOP_CNT_IN3    4
47867 #define M_SOP_CNT_IN3    0xfU
47868 #define V_SOP_CNT_IN3(x) ((x) << S_SOP_CNT_IN3)
47869 #define G_SOP_CNT_IN3(x) (((x) >> S_SOP_CNT_IN3) & M_SOP_CNT_IN3)
47870 
47871 #define S_EOP_CNT_IN3    0
47872 #define M_EOP_CNT_IN3    0xfU
47873 #define V_EOP_CNT_IN3(x) ((x) << S_EOP_CNT_IN3)
47874 #define G_EOP_CNT_IN3(x) (((x) >> S_EOP_CNT_IN3) & M_EOP_CNT_IN3)
47875 
47876 #define A_ULP_RX_CHNL2_CTX_ERROR_COUNT_PER_TID 0x1929c
47877 #define A_ULP_RX_CHNL3_CTX_ERROR_COUNT_PER_TID 0x192a0
47878 #define A_ULP_RX_TLS_PP_LLIMIT 0x192a4
47879 
47880 #define S_TLSPPLLIMIT    6
47881 #define M_TLSPPLLIMIT    0x3ffffffU
47882 #define V_TLSPPLLIMIT(x) ((x) << S_TLSPPLLIMIT)
47883 #define G_TLSPPLLIMIT(x) (((x) >> S_TLSPPLLIMIT) & M_TLSPPLLIMIT)
47884 
47885 #define A_ULP_RX_TLS_PP_ULIMIT 0x192a8
47886 
47887 #define S_TLSPPULIMIT    6
47888 #define M_TLSPPULIMIT    0x3ffffffU
47889 #define V_TLSPPULIMIT(x) ((x) << S_TLSPPULIMIT)
47890 #define G_TLSPPULIMIT(x) (((x) >> S_TLSPPULIMIT) & M_TLSPPULIMIT)
47891 
47892 #define A_ULP_RX_TLS_KEY_LLIMIT 0x192ac
47893 
47894 #define S_TLSKEYLLIMIT    8
47895 #define M_TLSKEYLLIMIT    0xffffffU
47896 #define V_TLSKEYLLIMIT(x) ((x) << S_TLSKEYLLIMIT)
47897 #define G_TLSKEYLLIMIT(x) (((x) >> S_TLSKEYLLIMIT) & M_TLSKEYLLIMIT)
47898 
47899 #define A_ULP_RX_TLS_KEY_ULIMIT 0x192b0
47900 
47901 #define S_TLSKEYULIMIT    8
47902 #define M_TLSKEYULIMIT    0xffffffU
47903 #define V_TLSKEYULIMIT(x) ((x) << S_TLSKEYULIMIT)
47904 #define G_TLSKEYULIMIT(x) (((x) >> S_TLSKEYULIMIT) & M_TLSKEYULIMIT)
47905 
47906 #define A_ULP_RX_TLS_CTL 0x192bc
47907 #define A_ULP_RX_RRQ_LLIMIT 0x192c0
47908 #define A_ULP_RX_RRQ_ULIMIT 0x192c4
47909 #define A_ULP_RX_NVME_TCP_STAG_LLIMIT 0x192c8
47910 #define A_ULP_RX_NVME_TCP_STAG_ULIMIT 0x192cc
47911 #define A_ULP_RX_NVME_TCP_RQ_LLIMIT 0x192d0
47912 #define A_ULP_RX_NVME_TCP_RQ_ULIMIT 0x192d4
47913 #define A_ULP_RX_NVME_TCP_PBL_LLIMIT 0x192d8
47914 #define A_ULP_RX_NVME_TCP_PBL_ULIMIT 0x192dc
47915 #define A_ULP_RX_NVME_TCP_MAX_LENGTH 0x192e0
47916 
47917 #define S_NVME_TCP_MAX_PLEN01    24
47918 #define M_NVME_TCP_MAX_PLEN01    0xffU
47919 #define V_NVME_TCP_MAX_PLEN01(x) ((x) << S_NVME_TCP_MAX_PLEN01)
47920 #define G_NVME_TCP_MAX_PLEN01(x) (((x) >> S_NVME_TCP_MAX_PLEN01) & M_NVME_TCP_MAX_PLEN01)
47921 
47922 #define S_NVME_TCP_MAX_PLEN23    16
47923 #define M_NVME_TCP_MAX_PLEN23    0xffU
47924 #define V_NVME_TCP_MAX_PLEN23(x) ((x) << S_NVME_TCP_MAX_PLEN23)
47925 #define G_NVME_TCP_MAX_PLEN23(x) (((x) >> S_NVME_TCP_MAX_PLEN23) & M_NVME_TCP_MAX_PLEN23)
47926 
47927 #define S_NVME_TCP_MAX_CMD_PDU_LENGTH    0
47928 #define M_NVME_TCP_MAX_CMD_PDU_LENGTH    0xffffU
47929 #define V_NVME_TCP_MAX_CMD_PDU_LENGTH(x) ((x) << S_NVME_TCP_MAX_CMD_PDU_LENGTH)
47930 #define G_NVME_TCP_MAX_CMD_PDU_LENGTH(x) (((x) >> S_NVME_TCP_MAX_CMD_PDU_LENGTH) & M_NVME_TCP_MAX_CMD_PDU_LENGTH)
47931 
47932 #define A_ULP_RX_NVME_TCP_IQE_SIZE 0x192e4
47933 #define A_ULP_RX_NVME_TCP_NEW_PDU_TYPES 0x192e8
47934 #define A_ULP_RX_IWARP_PMOF_OPCODES_1 0x192ec
47935 #define A_ULP_RX_IWARP_PMOF_OPCODES_2 0x192f0
47936 #define A_ULP_RX_INT_ENABLE_PCMD 0x19300
47937 
47938 #define S_ENABLE_PCMD_SFIFO_3    30
47939 #define V_ENABLE_PCMD_SFIFO_3(x) ((x) << S_ENABLE_PCMD_SFIFO_3)
47940 #define F_ENABLE_PCMD_SFIFO_3    V_ENABLE_PCMD_SFIFO_3(1U)
47941 
47942 #define S_ENABLE_PCMD_FIFO_3    29
47943 #define V_ENABLE_PCMD_FIFO_3(x) ((x) << S_ENABLE_PCMD_FIFO_3)
47944 #define F_ENABLE_PCMD_FIFO_3    V_ENABLE_PCMD_FIFO_3(1U)
47945 
47946 #define S_ENABLE_PCMD_DDP_HINT_3    28
47947 #define V_ENABLE_PCMD_DDP_HINT_3(x) ((x) << S_ENABLE_PCMD_DDP_HINT_3)
47948 #define F_ENABLE_PCMD_DDP_HINT_3    V_ENABLE_PCMD_DDP_HINT_3(1U)
47949 
47950 #define S_ENABLE_PCMD_TPT_3    27
47951 #define V_ENABLE_PCMD_TPT_3(x) ((x) << S_ENABLE_PCMD_TPT_3)
47952 #define F_ENABLE_PCMD_TPT_3    V_ENABLE_PCMD_TPT_3(1U)
47953 
47954 #define S_ENABLE_PCMD_DDP_3    26
47955 #define V_ENABLE_PCMD_DDP_3(x) ((x) << S_ENABLE_PCMD_DDP_3)
47956 #define F_ENABLE_PCMD_DDP_3    V_ENABLE_PCMD_DDP_3(1U)
47957 
47958 #define S_ENABLE_PCMD_MPAR_3    25
47959 #define V_ENABLE_PCMD_MPAR_3(x) ((x) << S_ENABLE_PCMD_MPAR_3)
47960 #define F_ENABLE_PCMD_MPAR_3    V_ENABLE_PCMD_MPAR_3(1U)
47961 
47962 #define S_ENABLE_PCMD_MPAC_3    24
47963 #define V_ENABLE_PCMD_MPAC_3(x) ((x) << S_ENABLE_PCMD_MPAC_3)
47964 #define F_ENABLE_PCMD_MPAC_3    V_ENABLE_PCMD_MPAC_3(1U)
47965 
47966 #define S_ENABLE_PCMD_SFIFO_2    22
47967 #define V_ENABLE_PCMD_SFIFO_2(x) ((x) << S_ENABLE_PCMD_SFIFO_2)
47968 #define F_ENABLE_PCMD_SFIFO_2    V_ENABLE_PCMD_SFIFO_2(1U)
47969 
47970 #define S_ENABLE_PCMD_FIFO_2    21
47971 #define V_ENABLE_PCMD_FIFO_2(x) ((x) << S_ENABLE_PCMD_FIFO_2)
47972 #define F_ENABLE_PCMD_FIFO_2    V_ENABLE_PCMD_FIFO_2(1U)
47973 
47974 #define S_ENABLE_PCMD_DDP_HINT_2    20
47975 #define V_ENABLE_PCMD_DDP_HINT_2(x) ((x) << S_ENABLE_PCMD_DDP_HINT_2)
47976 #define F_ENABLE_PCMD_DDP_HINT_2    V_ENABLE_PCMD_DDP_HINT_2(1U)
47977 
47978 #define S_ENABLE_PCMD_TPT_2    19
47979 #define V_ENABLE_PCMD_TPT_2(x) ((x) << S_ENABLE_PCMD_TPT_2)
47980 #define F_ENABLE_PCMD_TPT_2    V_ENABLE_PCMD_TPT_2(1U)
47981 
47982 #define S_ENABLE_PCMD_DDP_2    18
47983 #define V_ENABLE_PCMD_DDP_2(x) ((x) << S_ENABLE_PCMD_DDP_2)
47984 #define F_ENABLE_PCMD_DDP_2    V_ENABLE_PCMD_DDP_2(1U)
47985 
47986 #define S_ENABLE_PCMD_MPAR_2    17
47987 #define V_ENABLE_PCMD_MPAR_2(x) ((x) << S_ENABLE_PCMD_MPAR_2)
47988 #define F_ENABLE_PCMD_MPAR_2    V_ENABLE_PCMD_MPAR_2(1U)
47989 
47990 #define S_ENABLE_PCMD_MPAC_2    16
47991 #define V_ENABLE_PCMD_MPAC_2(x) ((x) << S_ENABLE_PCMD_MPAC_2)
47992 #define F_ENABLE_PCMD_MPAC_2    V_ENABLE_PCMD_MPAC_2(1U)
47993 
47994 #define S_ENABLE_PCMD_SFIFO_1    14
47995 #define V_ENABLE_PCMD_SFIFO_1(x) ((x) << S_ENABLE_PCMD_SFIFO_1)
47996 #define F_ENABLE_PCMD_SFIFO_1    V_ENABLE_PCMD_SFIFO_1(1U)
47997 
47998 #define S_ENABLE_PCMD_FIFO_1    13
47999 #define V_ENABLE_PCMD_FIFO_1(x) ((x) << S_ENABLE_PCMD_FIFO_1)
48000 #define F_ENABLE_PCMD_FIFO_1    V_ENABLE_PCMD_FIFO_1(1U)
48001 
48002 #define S_ENABLE_PCMD_DDP_HINT_1    12
48003 #define V_ENABLE_PCMD_DDP_HINT_1(x) ((x) << S_ENABLE_PCMD_DDP_HINT_1)
48004 #define F_ENABLE_PCMD_DDP_HINT_1    V_ENABLE_PCMD_DDP_HINT_1(1U)
48005 
48006 #define S_ENABLE_PCMD_TPT_1    11
48007 #define V_ENABLE_PCMD_TPT_1(x) ((x) << S_ENABLE_PCMD_TPT_1)
48008 #define F_ENABLE_PCMD_TPT_1    V_ENABLE_PCMD_TPT_1(1U)
48009 
48010 #define S_ENABLE_PCMD_DDP_1    10
48011 #define V_ENABLE_PCMD_DDP_1(x) ((x) << S_ENABLE_PCMD_DDP_1)
48012 #define F_ENABLE_PCMD_DDP_1    V_ENABLE_PCMD_DDP_1(1U)
48013 
48014 #define S_ENABLE_PCMD_MPAR_1    9
48015 #define V_ENABLE_PCMD_MPAR_1(x) ((x) << S_ENABLE_PCMD_MPAR_1)
48016 #define F_ENABLE_PCMD_MPAR_1    V_ENABLE_PCMD_MPAR_1(1U)
48017 
48018 #define S_ENABLE_PCMD_MPAC_1    8
48019 #define V_ENABLE_PCMD_MPAC_1(x) ((x) << S_ENABLE_PCMD_MPAC_1)
48020 #define F_ENABLE_PCMD_MPAC_1    V_ENABLE_PCMD_MPAC_1(1U)
48021 
48022 #define S_ENABLE_PCMD_SFIFO_0    6
48023 #define V_ENABLE_PCMD_SFIFO_0(x) ((x) << S_ENABLE_PCMD_SFIFO_0)
48024 #define F_ENABLE_PCMD_SFIFO_0    V_ENABLE_PCMD_SFIFO_0(1U)
48025 
48026 #define S_ENABLE_PCMD_FIFO_0    5
48027 #define V_ENABLE_PCMD_FIFO_0(x) ((x) << S_ENABLE_PCMD_FIFO_0)
48028 #define F_ENABLE_PCMD_FIFO_0    V_ENABLE_PCMD_FIFO_0(1U)
48029 
48030 #define S_ENABLE_PCMD_DDP_HINT_0    4
48031 #define V_ENABLE_PCMD_DDP_HINT_0(x) ((x) << S_ENABLE_PCMD_DDP_HINT_0)
48032 #define F_ENABLE_PCMD_DDP_HINT_0    V_ENABLE_PCMD_DDP_HINT_0(1U)
48033 
48034 #define S_ENABLE_PCMD_TPT_0    3
48035 #define V_ENABLE_PCMD_TPT_0(x) ((x) << S_ENABLE_PCMD_TPT_0)
48036 #define F_ENABLE_PCMD_TPT_0    V_ENABLE_PCMD_TPT_0(1U)
48037 
48038 #define S_ENABLE_PCMD_DDP_0    2
48039 #define V_ENABLE_PCMD_DDP_0(x) ((x) << S_ENABLE_PCMD_DDP_0)
48040 #define F_ENABLE_PCMD_DDP_0    V_ENABLE_PCMD_DDP_0(1U)
48041 
48042 #define S_ENABLE_PCMD_MPAR_0    1
48043 #define V_ENABLE_PCMD_MPAR_0(x) ((x) << S_ENABLE_PCMD_MPAR_0)
48044 #define F_ENABLE_PCMD_MPAR_0    V_ENABLE_PCMD_MPAR_0(1U)
48045 
48046 #define S_ENABLE_PCMD_MPAC_0    0
48047 #define V_ENABLE_PCMD_MPAC_0(x) ((x) << S_ENABLE_PCMD_MPAC_0)
48048 #define F_ENABLE_PCMD_MPAC_0    V_ENABLE_PCMD_MPAC_0(1U)
48049 
48050 #define A_ULP_RX_INT_CAUSE_PCMD 0x19304
48051 
48052 #define S_CAUSE_PCMD_SFIFO_3    30
48053 #define V_CAUSE_PCMD_SFIFO_3(x) ((x) << S_CAUSE_PCMD_SFIFO_3)
48054 #define F_CAUSE_PCMD_SFIFO_3    V_CAUSE_PCMD_SFIFO_3(1U)
48055 
48056 #define S_CAUSE_PCMD_FIFO_3    29
48057 #define V_CAUSE_PCMD_FIFO_3(x) ((x) << S_CAUSE_PCMD_FIFO_3)
48058 #define F_CAUSE_PCMD_FIFO_3    V_CAUSE_PCMD_FIFO_3(1U)
48059 
48060 #define S_CAUSE_PCMD_DDP_HINT_3    28
48061 #define V_CAUSE_PCMD_DDP_HINT_3(x) ((x) << S_CAUSE_PCMD_DDP_HINT_3)
48062 #define F_CAUSE_PCMD_DDP_HINT_3    V_CAUSE_PCMD_DDP_HINT_3(1U)
48063 
48064 #define S_CAUSE_PCMD_TPT_3    27
48065 #define V_CAUSE_PCMD_TPT_3(x) ((x) << S_CAUSE_PCMD_TPT_3)
48066 #define F_CAUSE_PCMD_TPT_3    V_CAUSE_PCMD_TPT_3(1U)
48067 
48068 #define S_CAUSE_PCMD_DDP_3    26
48069 #define V_CAUSE_PCMD_DDP_3(x) ((x) << S_CAUSE_PCMD_DDP_3)
48070 #define F_CAUSE_PCMD_DDP_3    V_CAUSE_PCMD_DDP_3(1U)
48071 
48072 #define S_CAUSE_PCMD_MPAR_3    25
48073 #define V_CAUSE_PCMD_MPAR_3(x) ((x) << S_CAUSE_PCMD_MPAR_3)
48074 #define F_CAUSE_PCMD_MPAR_3    V_CAUSE_PCMD_MPAR_3(1U)
48075 
48076 #define S_CAUSE_PCMD_MPAC_3    24
48077 #define V_CAUSE_PCMD_MPAC_3(x) ((x) << S_CAUSE_PCMD_MPAC_3)
48078 #define F_CAUSE_PCMD_MPAC_3    V_CAUSE_PCMD_MPAC_3(1U)
48079 
48080 #define S_CAUSE_PCMD_SFIFO_2    22
48081 #define V_CAUSE_PCMD_SFIFO_2(x) ((x) << S_CAUSE_PCMD_SFIFO_2)
48082 #define F_CAUSE_PCMD_SFIFO_2    V_CAUSE_PCMD_SFIFO_2(1U)
48083 
48084 #define S_CAUSE_PCMD_FIFO_2    21
48085 #define V_CAUSE_PCMD_FIFO_2(x) ((x) << S_CAUSE_PCMD_FIFO_2)
48086 #define F_CAUSE_PCMD_FIFO_2    V_CAUSE_PCMD_FIFO_2(1U)
48087 
48088 #define S_CAUSE_PCMD_DDP_HINT_2    20
48089 #define V_CAUSE_PCMD_DDP_HINT_2(x) ((x) << S_CAUSE_PCMD_DDP_HINT_2)
48090 #define F_CAUSE_PCMD_DDP_HINT_2    V_CAUSE_PCMD_DDP_HINT_2(1U)
48091 
48092 #define S_CAUSE_PCMD_TPT_2    19
48093 #define V_CAUSE_PCMD_TPT_2(x) ((x) << S_CAUSE_PCMD_TPT_2)
48094 #define F_CAUSE_PCMD_TPT_2    V_CAUSE_PCMD_TPT_2(1U)
48095 
48096 #define S_CAUSE_PCMD_DDP_2    18
48097 #define V_CAUSE_PCMD_DDP_2(x) ((x) << S_CAUSE_PCMD_DDP_2)
48098 #define F_CAUSE_PCMD_DDP_2    V_CAUSE_PCMD_DDP_2(1U)
48099 
48100 #define S_CAUSE_PCMD_MPAR_2    17
48101 #define V_CAUSE_PCMD_MPAR_2(x) ((x) << S_CAUSE_PCMD_MPAR_2)
48102 #define F_CAUSE_PCMD_MPAR_2    V_CAUSE_PCMD_MPAR_2(1U)
48103 
48104 #define S_CAUSE_PCMD_MPAC_2    16
48105 #define V_CAUSE_PCMD_MPAC_2(x) ((x) << S_CAUSE_PCMD_MPAC_2)
48106 #define F_CAUSE_PCMD_MPAC_2    V_CAUSE_PCMD_MPAC_2(1U)
48107 
48108 #define S_CAUSE_PCMD_SFIFO_1    14
48109 #define V_CAUSE_PCMD_SFIFO_1(x) ((x) << S_CAUSE_PCMD_SFIFO_1)
48110 #define F_CAUSE_PCMD_SFIFO_1    V_CAUSE_PCMD_SFIFO_1(1U)
48111 
48112 #define S_CAUSE_PCMD_FIFO_1    13
48113 #define V_CAUSE_PCMD_FIFO_1(x) ((x) << S_CAUSE_PCMD_FIFO_1)
48114 #define F_CAUSE_PCMD_FIFO_1    V_CAUSE_PCMD_FIFO_1(1U)
48115 
48116 #define S_CAUSE_PCMD_DDP_HINT_1    12
48117 #define V_CAUSE_PCMD_DDP_HINT_1(x) ((x) << S_CAUSE_PCMD_DDP_HINT_1)
48118 #define F_CAUSE_PCMD_DDP_HINT_1    V_CAUSE_PCMD_DDP_HINT_1(1U)
48119 
48120 #define S_CAUSE_PCMD_TPT_1    11
48121 #define V_CAUSE_PCMD_TPT_1(x) ((x) << S_CAUSE_PCMD_TPT_1)
48122 #define F_CAUSE_PCMD_TPT_1    V_CAUSE_PCMD_TPT_1(1U)
48123 
48124 #define S_CAUSE_PCMD_DDP_1    10
48125 #define V_CAUSE_PCMD_DDP_1(x) ((x) << S_CAUSE_PCMD_DDP_1)
48126 #define F_CAUSE_PCMD_DDP_1    V_CAUSE_PCMD_DDP_1(1U)
48127 
48128 #define S_CAUSE_PCMD_MPAR_1    9
48129 #define V_CAUSE_PCMD_MPAR_1(x) ((x) << S_CAUSE_PCMD_MPAR_1)
48130 #define F_CAUSE_PCMD_MPAR_1    V_CAUSE_PCMD_MPAR_1(1U)
48131 
48132 #define S_CAUSE_PCMD_MPAC_1    8
48133 #define V_CAUSE_PCMD_MPAC_1(x) ((x) << S_CAUSE_PCMD_MPAC_1)
48134 #define F_CAUSE_PCMD_MPAC_1    V_CAUSE_PCMD_MPAC_1(1U)
48135 
48136 #define S_CAUSE_PCMD_SFIFO_0    6
48137 #define V_CAUSE_PCMD_SFIFO_0(x) ((x) << S_CAUSE_PCMD_SFIFO_0)
48138 #define F_CAUSE_PCMD_SFIFO_0    V_CAUSE_PCMD_SFIFO_0(1U)
48139 
48140 #define S_CAUSE_PCMD_FIFO_0    5
48141 #define V_CAUSE_PCMD_FIFO_0(x) ((x) << S_CAUSE_PCMD_FIFO_0)
48142 #define F_CAUSE_PCMD_FIFO_0    V_CAUSE_PCMD_FIFO_0(1U)
48143 
48144 #define S_CAUSE_PCMD_DDP_HINT_0    4
48145 #define V_CAUSE_PCMD_DDP_HINT_0(x) ((x) << S_CAUSE_PCMD_DDP_HINT_0)
48146 #define F_CAUSE_PCMD_DDP_HINT_0    V_CAUSE_PCMD_DDP_HINT_0(1U)
48147 
48148 #define S_CAUSE_PCMD_TPT_0    3
48149 #define V_CAUSE_PCMD_TPT_0(x) ((x) << S_CAUSE_PCMD_TPT_0)
48150 #define F_CAUSE_PCMD_TPT_0    V_CAUSE_PCMD_TPT_0(1U)
48151 
48152 #define S_CAUSE_PCMD_DDP_0    2
48153 #define V_CAUSE_PCMD_DDP_0(x) ((x) << S_CAUSE_PCMD_DDP_0)
48154 #define F_CAUSE_PCMD_DDP_0    V_CAUSE_PCMD_DDP_0(1U)
48155 
48156 #define S_CAUSE_PCMD_MPAR_0    1
48157 #define V_CAUSE_PCMD_MPAR_0(x) ((x) << S_CAUSE_PCMD_MPAR_0)
48158 #define F_CAUSE_PCMD_MPAR_0    V_CAUSE_PCMD_MPAR_0(1U)
48159 
48160 #define S_CAUSE_PCMD_MPAC_0    0
48161 #define V_CAUSE_PCMD_MPAC_0(x) ((x) << S_CAUSE_PCMD_MPAC_0)
48162 #define F_CAUSE_PCMD_MPAC_0    V_CAUSE_PCMD_MPAC_0(1U)
48163 
48164 #define A_ULP_RX_PERR_ENABLE_PCMD 0x19308
48165 
48166 #define S_PERR_ENABLE_PCMD_SFIFO_3    30
48167 #define V_PERR_ENABLE_PCMD_SFIFO_3(x) ((x) << S_PERR_ENABLE_PCMD_SFIFO_3)
48168 #define F_PERR_ENABLE_PCMD_SFIFO_3    V_PERR_ENABLE_PCMD_SFIFO_3(1U)
48169 
48170 #define S_PERR_ENABLE_PCMD_FIFO_3    29
48171 #define V_PERR_ENABLE_PCMD_FIFO_3(x) ((x) << S_PERR_ENABLE_PCMD_FIFO_3)
48172 #define F_PERR_ENABLE_PCMD_FIFO_3    V_PERR_ENABLE_PCMD_FIFO_3(1U)
48173 
48174 #define S_PERR_ENABLE_PCMD_DDP_HINT_3    28
48175 #define V_PERR_ENABLE_PCMD_DDP_HINT_3(x) ((x) << S_PERR_ENABLE_PCMD_DDP_HINT_3)
48176 #define F_PERR_ENABLE_PCMD_DDP_HINT_3    V_PERR_ENABLE_PCMD_DDP_HINT_3(1U)
48177 
48178 #define S_PERR_ENABLE_PCMD_TPT_3    27
48179 #define V_PERR_ENABLE_PCMD_TPT_3(x) ((x) << S_PERR_ENABLE_PCMD_TPT_3)
48180 #define F_PERR_ENABLE_PCMD_TPT_3    V_PERR_ENABLE_PCMD_TPT_3(1U)
48181 
48182 #define S_PERR_ENABLE_PCMD_DDP_3    26
48183 #define V_PERR_ENABLE_PCMD_DDP_3(x) ((x) << S_PERR_ENABLE_PCMD_DDP_3)
48184 #define F_PERR_ENABLE_PCMD_DDP_3    V_PERR_ENABLE_PCMD_DDP_3(1U)
48185 
48186 #define S_PERR_ENABLE_PCMD_MPAR_3    25
48187 #define V_PERR_ENABLE_PCMD_MPAR_3(x) ((x) << S_PERR_ENABLE_PCMD_MPAR_3)
48188 #define F_PERR_ENABLE_PCMD_MPAR_3    V_PERR_ENABLE_PCMD_MPAR_3(1U)
48189 
48190 #define S_PERR_ENABLE_PCMD_MPAC_3    24
48191 #define V_PERR_ENABLE_PCMD_MPAC_3(x) ((x) << S_PERR_ENABLE_PCMD_MPAC_3)
48192 #define F_PERR_ENABLE_PCMD_MPAC_3    V_PERR_ENABLE_PCMD_MPAC_3(1U)
48193 
48194 #define S_PERR_ENABLE_PCMD_SFIFO_2    22
48195 #define V_PERR_ENABLE_PCMD_SFIFO_2(x) ((x) << S_PERR_ENABLE_PCMD_SFIFO_2)
48196 #define F_PERR_ENABLE_PCMD_SFIFO_2    V_PERR_ENABLE_PCMD_SFIFO_2(1U)
48197 
48198 #define S_PERR_ENABLE_PCMD_FIFO_2    21
48199 #define V_PERR_ENABLE_PCMD_FIFO_2(x) ((x) << S_PERR_ENABLE_PCMD_FIFO_2)
48200 #define F_PERR_ENABLE_PCMD_FIFO_2    V_PERR_ENABLE_PCMD_FIFO_2(1U)
48201 
48202 #define S_PERR_ENABLE_PCMD_DDP_HINT_2    20
48203 #define V_PERR_ENABLE_PCMD_DDP_HINT_2(x) ((x) << S_PERR_ENABLE_PCMD_DDP_HINT_2)
48204 #define F_PERR_ENABLE_PCMD_DDP_HINT_2    V_PERR_ENABLE_PCMD_DDP_HINT_2(1U)
48205 
48206 #define S_PERR_ENABLE_PCMD_TPT_2    19
48207 #define V_PERR_ENABLE_PCMD_TPT_2(x) ((x) << S_PERR_ENABLE_PCMD_TPT_2)
48208 #define F_PERR_ENABLE_PCMD_TPT_2    V_PERR_ENABLE_PCMD_TPT_2(1U)
48209 
48210 #define S_PERR_ENABLE_PCMD_DDP_2    18
48211 #define V_PERR_ENABLE_PCMD_DDP_2(x) ((x) << S_PERR_ENABLE_PCMD_DDP_2)
48212 #define F_PERR_ENABLE_PCMD_DDP_2    V_PERR_ENABLE_PCMD_DDP_2(1U)
48213 
48214 #define S_PERR_ENABLE_PCMD_MPAR_2    17
48215 #define V_PERR_ENABLE_PCMD_MPAR_2(x) ((x) << S_PERR_ENABLE_PCMD_MPAR_2)
48216 #define F_PERR_ENABLE_PCMD_MPAR_2    V_PERR_ENABLE_PCMD_MPAR_2(1U)
48217 
48218 #define S_PERR_ENABLE_PCMD_MPAC_2    16
48219 #define V_PERR_ENABLE_PCMD_MPAC_2(x) ((x) << S_PERR_ENABLE_PCMD_MPAC_2)
48220 #define F_PERR_ENABLE_PCMD_MPAC_2    V_PERR_ENABLE_PCMD_MPAC_2(1U)
48221 
48222 #define S_PERR_ENABLE_PCMD_SFIFO_1    14
48223 #define V_PERR_ENABLE_PCMD_SFIFO_1(x) ((x) << S_PERR_ENABLE_PCMD_SFIFO_1)
48224 #define F_PERR_ENABLE_PCMD_SFIFO_1    V_PERR_ENABLE_PCMD_SFIFO_1(1U)
48225 
48226 #define S_PERR_ENABLE_PCMD_FIFO_1    13
48227 #define V_PERR_ENABLE_PCMD_FIFO_1(x) ((x) << S_PERR_ENABLE_PCMD_FIFO_1)
48228 #define F_PERR_ENABLE_PCMD_FIFO_1    V_PERR_ENABLE_PCMD_FIFO_1(1U)
48229 
48230 #define S_PERR_ENABLE_PCMD_DDP_HINT_1    12
48231 #define V_PERR_ENABLE_PCMD_DDP_HINT_1(x) ((x) << S_PERR_ENABLE_PCMD_DDP_HINT_1)
48232 #define F_PERR_ENABLE_PCMD_DDP_HINT_1    V_PERR_ENABLE_PCMD_DDP_HINT_1(1U)
48233 
48234 #define S_PERR_ENABLE_PCMD_TPT_1    11
48235 #define V_PERR_ENABLE_PCMD_TPT_1(x) ((x) << S_PERR_ENABLE_PCMD_TPT_1)
48236 #define F_PERR_ENABLE_PCMD_TPT_1    V_PERR_ENABLE_PCMD_TPT_1(1U)
48237 
48238 #define S_PERR_ENABLE_PCMD_DDP_1    10
48239 #define V_PERR_ENABLE_PCMD_DDP_1(x) ((x) << S_PERR_ENABLE_PCMD_DDP_1)
48240 #define F_PERR_ENABLE_PCMD_DDP_1    V_PERR_ENABLE_PCMD_DDP_1(1U)
48241 
48242 #define S_PERR_ENABLE_PCMD_MPAR_1    9
48243 #define V_PERR_ENABLE_PCMD_MPAR_1(x) ((x) << S_PERR_ENABLE_PCMD_MPAR_1)
48244 #define F_PERR_ENABLE_PCMD_MPAR_1    V_PERR_ENABLE_PCMD_MPAR_1(1U)
48245 
48246 #define S_PERR_ENABLE_PCMD_MPAC_1    8
48247 #define V_PERR_ENABLE_PCMD_MPAC_1(x) ((x) << S_PERR_ENABLE_PCMD_MPAC_1)
48248 #define F_PERR_ENABLE_PCMD_MPAC_1    V_PERR_ENABLE_PCMD_MPAC_1(1U)
48249 
48250 #define S_PERR_ENABLE_PCMD_SFIFO_0    6
48251 #define V_PERR_ENABLE_PCMD_SFIFO_0(x) ((x) << S_PERR_ENABLE_PCMD_SFIFO_0)
48252 #define F_PERR_ENABLE_PCMD_SFIFO_0    V_PERR_ENABLE_PCMD_SFIFO_0(1U)
48253 
48254 #define S_PERR_ENABLE_PCMD_FIFO_0    5
48255 #define V_PERR_ENABLE_PCMD_FIFO_0(x) ((x) << S_PERR_ENABLE_PCMD_FIFO_0)
48256 #define F_PERR_ENABLE_PCMD_FIFO_0    V_PERR_ENABLE_PCMD_FIFO_0(1U)
48257 
48258 #define S_PERR_ENABLE_PCMD_DDP_HINT_0    4
48259 #define V_PERR_ENABLE_PCMD_DDP_HINT_0(x) ((x) << S_PERR_ENABLE_PCMD_DDP_HINT_0)
48260 #define F_PERR_ENABLE_PCMD_DDP_HINT_0    V_PERR_ENABLE_PCMD_DDP_HINT_0(1U)
48261 
48262 #define S_PERR_ENABLE_PCMD_TPT_0    3
48263 #define V_PERR_ENABLE_PCMD_TPT_0(x) ((x) << S_PERR_ENABLE_PCMD_TPT_0)
48264 #define F_PERR_ENABLE_PCMD_TPT_0    V_PERR_ENABLE_PCMD_TPT_0(1U)
48265 
48266 #define S_PERR_ENABLE_PCMD_DDP_0    2
48267 #define V_PERR_ENABLE_PCMD_DDP_0(x) ((x) << S_PERR_ENABLE_PCMD_DDP_0)
48268 #define F_PERR_ENABLE_PCMD_DDP_0    V_PERR_ENABLE_PCMD_DDP_0(1U)
48269 
48270 #define S_PERR_ENABLE_PCMD_MPAR_0    1
48271 #define V_PERR_ENABLE_PCMD_MPAR_0(x) ((x) << S_PERR_ENABLE_PCMD_MPAR_0)
48272 #define F_PERR_ENABLE_PCMD_MPAR_0    V_PERR_ENABLE_PCMD_MPAR_0(1U)
48273 
48274 #define S_PERR_ENABLE_PCMD_MPAC_0    0
48275 #define V_PERR_ENABLE_PCMD_MPAC_0(x) ((x) << S_PERR_ENABLE_PCMD_MPAC_0)
48276 #define F_PERR_ENABLE_PCMD_MPAC_0    V_PERR_ENABLE_PCMD_MPAC_0(1U)
48277 
48278 #define A_ULP_RX_INT_ENABLE_DATA 0x19310
48279 
48280 #define S_ENABLE_DATA_SNOOP_3    29
48281 #define V_ENABLE_DATA_SNOOP_3(x) ((x) << S_ENABLE_DATA_SNOOP_3)
48282 #define F_ENABLE_DATA_SNOOP_3    V_ENABLE_DATA_SNOOP_3(1U)
48283 
48284 #define S_ENABLE_DATA_SFIFO_3    28
48285 #define V_ENABLE_DATA_SFIFO_3(x) ((x) << S_ENABLE_DATA_SFIFO_3)
48286 #define F_ENABLE_DATA_SFIFO_3    V_ENABLE_DATA_SFIFO_3(1U)
48287 
48288 #define S_ENABLE_DATA_FIFO_3    27
48289 #define V_ENABLE_DATA_FIFO_3(x) ((x) << S_ENABLE_DATA_FIFO_3)
48290 #define F_ENABLE_DATA_FIFO_3    V_ENABLE_DATA_FIFO_3(1U)
48291 
48292 #define S_ENABLE_DATA_DDP_3    26
48293 #define V_ENABLE_DATA_DDP_3(x) ((x) << S_ENABLE_DATA_DDP_3)
48294 #define F_ENABLE_DATA_DDP_3    V_ENABLE_DATA_DDP_3(1U)
48295 
48296 #define S_ENABLE_DATA_CTX_3    25
48297 #define V_ENABLE_DATA_CTX_3(x) ((x) << S_ENABLE_DATA_CTX_3)
48298 #define F_ENABLE_DATA_CTX_3    V_ENABLE_DATA_CTX_3(1U)
48299 
48300 #define S_ENABLE_DATA_PARSER_3    24
48301 #define V_ENABLE_DATA_PARSER_3(x) ((x) << S_ENABLE_DATA_PARSER_3)
48302 #define F_ENABLE_DATA_PARSER_3    V_ENABLE_DATA_PARSER_3(1U)
48303 
48304 #define S_ENABLE_DATA_SNOOP_2    21
48305 #define V_ENABLE_DATA_SNOOP_2(x) ((x) << S_ENABLE_DATA_SNOOP_2)
48306 #define F_ENABLE_DATA_SNOOP_2    V_ENABLE_DATA_SNOOP_2(1U)
48307 
48308 #define S_ENABLE_DATA_SFIFO_2    20
48309 #define V_ENABLE_DATA_SFIFO_2(x) ((x) << S_ENABLE_DATA_SFIFO_2)
48310 #define F_ENABLE_DATA_SFIFO_2    V_ENABLE_DATA_SFIFO_2(1U)
48311 
48312 #define S_ENABLE_DATA_FIFO_2    19
48313 #define V_ENABLE_DATA_FIFO_2(x) ((x) << S_ENABLE_DATA_FIFO_2)
48314 #define F_ENABLE_DATA_FIFO_2    V_ENABLE_DATA_FIFO_2(1U)
48315 
48316 #define S_ENABLE_DATA_DDP_2    18
48317 #define V_ENABLE_DATA_DDP_2(x) ((x) << S_ENABLE_DATA_DDP_2)
48318 #define F_ENABLE_DATA_DDP_2    V_ENABLE_DATA_DDP_2(1U)
48319 
48320 #define S_ENABLE_DATA_CTX_2    17
48321 #define V_ENABLE_DATA_CTX_2(x) ((x) << S_ENABLE_DATA_CTX_2)
48322 #define F_ENABLE_DATA_CTX_2    V_ENABLE_DATA_CTX_2(1U)
48323 
48324 #define S_ENABLE_DATA_PARSER_2    16
48325 #define V_ENABLE_DATA_PARSER_2(x) ((x) << S_ENABLE_DATA_PARSER_2)
48326 #define F_ENABLE_DATA_PARSER_2    V_ENABLE_DATA_PARSER_2(1U)
48327 
48328 #define S_ENABLE_DATA_SNOOP_1    13
48329 #define V_ENABLE_DATA_SNOOP_1(x) ((x) << S_ENABLE_DATA_SNOOP_1)
48330 #define F_ENABLE_DATA_SNOOP_1    V_ENABLE_DATA_SNOOP_1(1U)
48331 
48332 #define S_ENABLE_DATA_SFIFO_1    12
48333 #define V_ENABLE_DATA_SFIFO_1(x) ((x) << S_ENABLE_DATA_SFIFO_1)
48334 #define F_ENABLE_DATA_SFIFO_1    V_ENABLE_DATA_SFIFO_1(1U)
48335 
48336 #define S_ENABLE_DATA_FIFO_1    11
48337 #define V_ENABLE_DATA_FIFO_1(x) ((x) << S_ENABLE_DATA_FIFO_1)
48338 #define F_ENABLE_DATA_FIFO_1    V_ENABLE_DATA_FIFO_1(1U)
48339 
48340 #define S_ENABLE_DATA_DDP_1    10
48341 #define V_ENABLE_DATA_DDP_1(x) ((x) << S_ENABLE_DATA_DDP_1)
48342 #define F_ENABLE_DATA_DDP_1    V_ENABLE_DATA_DDP_1(1U)
48343 
48344 #define S_ENABLE_DATA_CTX_1    9
48345 #define V_ENABLE_DATA_CTX_1(x) ((x) << S_ENABLE_DATA_CTX_1)
48346 #define F_ENABLE_DATA_CTX_1    V_ENABLE_DATA_CTX_1(1U)
48347 
48348 #define S_ENABLE_DATA_PARSER_1    8
48349 #define V_ENABLE_DATA_PARSER_1(x) ((x) << S_ENABLE_DATA_PARSER_1)
48350 #define F_ENABLE_DATA_PARSER_1    V_ENABLE_DATA_PARSER_1(1U)
48351 
48352 #define S_ENABLE_DATA_SNOOP_0    5
48353 #define V_ENABLE_DATA_SNOOP_0(x) ((x) << S_ENABLE_DATA_SNOOP_0)
48354 #define F_ENABLE_DATA_SNOOP_0    V_ENABLE_DATA_SNOOP_0(1U)
48355 
48356 #define S_ENABLE_DATA_SFIFO_0    4
48357 #define V_ENABLE_DATA_SFIFO_0(x) ((x) << S_ENABLE_DATA_SFIFO_0)
48358 #define F_ENABLE_DATA_SFIFO_0    V_ENABLE_DATA_SFIFO_0(1U)
48359 
48360 #define S_ENABLE_DATA_FIFO_0    3
48361 #define V_ENABLE_DATA_FIFO_0(x) ((x) << S_ENABLE_DATA_FIFO_0)
48362 #define F_ENABLE_DATA_FIFO_0    V_ENABLE_DATA_FIFO_0(1U)
48363 
48364 #define S_ENABLE_DATA_DDP_0    2
48365 #define V_ENABLE_DATA_DDP_0(x) ((x) << S_ENABLE_DATA_DDP_0)
48366 #define F_ENABLE_DATA_DDP_0    V_ENABLE_DATA_DDP_0(1U)
48367 
48368 #define S_ENABLE_DATA_CTX_0    1
48369 #define V_ENABLE_DATA_CTX_0(x) ((x) << S_ENABLE_DATA_CTX_0)
48370 #define F_ENABLE_DATA_CTX_0    V_ENABLE_DATA_CTX_0(1U)
48371 
48372 #define S_ENABLE_DATA_PARSER_0    0
48373 #define V_ENABLE_DATA_PARSER_0(x) ((x) << S_ENABLE_DATA_PARSER_0)
48374 #define F_ENABLE_DATA_PARSER_0    V_ENABLE_DATA_PARSER_0(1U)
48375 
48376 #define A_ULP_RX_INT_CAUSE_DATA 0x19314
48377 
48378 #define S_CAUSE_DATA_SNOOP_3    29
48379 #define V_CAUSE_DATA_SNOOP_3(x) ((x) << S_CAUSE_DATA_SNOOP_3)
48380 #define F_CAUSE_DATA_SNOOP_3    V_CAUSE_DATA_SNOOP_3(1U)
48381 
48382 #define S_CAUSE_DATA_SFIFO_3    28
48383 #define V_CAUSE_DATA_SFIFO_3(x) ((x) << S_CAUSE_DATA_SFIFO_3)
48384 #define F_CAUSE_DATA_SFIFO_3    V_CAUSE_DATA_SFIFO_3(1U)
48385 
48386 #define S_CAUSE_DATA_FIFO_3    27
48387 #define V_CAUSE_DATA_FIFO_3(x) ((x) << S_CAUSE_DATA_FIFO_3)
48388 #define F_CAUSE_DATA_FIFO_3    V_CAUSE_DATA_FIFO_3(1U)
48389 
48390 #define S_CAUSE_DATA_DDP_3    26
48391 #define V_CAUSE_DATA_DDP_3(x) ((x) << S_CAUSE_DATA_DDP_3)
48392 #define F_CAUSE_DATA_DDP_3    V_CAUSE_DATA_DDP_3(1U)
48393 
48394 #define S_CAUSE_DATA_CTX_3    25
48395 #define V_CAUSE_DATA_CTX_3(x) ((x) << S_CAUSE_DATA_CTX_3)
48396 #define F_CAUSE_DATA_CTX_3    V_CAUSE_DATA_CTX_3(1U)
48397 
48398 #define S_CAUSE_DATA_PARSER_3    24
48399 #define V_CAUSE_DATA_PARSER_3(x) ((x) << S_CAUSE_DATA_PARSER_3)
48400 #define F_CAUSE_DATA_PARSER_3    V_CAUSE_DATA_PARSER_3(1U)
48401 
48402 #define S_CAUSE_DATA_SNOOP_2    21
48403 #define V_CAUSE_DATA_SNOOP_2(x) ((x) << S_CAUSE_DATA_SNOOP_2)
48404 #define F_CAUSE_DATA_SNOOP_2    V_CAUSE_DATA_SNOOP_2(1U)
48405 
48406 #define S_CAUSE_DATA_SFIFO_2    20
48407 #define V_CAUSE_DATA_SFIFO_2(x) ((x) << S_CAUSE_DATA_SFIFO_2)
48408 #define F_CAUSE_DATA_SFIFO_2    V_CAUSE_DATA_SFIFO_2(1U)
48409 
48410 #define S_CAUSE_DATA_FIFO_2    19
48411 #define V_CAUSE_DATA_FIFO_2(x) ((x) << S_CAUSE_DATA_FIFO_2)
48412 #define F_CAUSE_DATA_FIFO_2    V_CAUSE_DATA_FIFO_2(1U)
48413 
48414 #define S_CAUSE_DATA_DDP_2    18
48415 #define V_CAUSE_DATA_DDP_2(x) ((x) << S_CAUSE_DATA_DDP_2)
48416 #define F_CAUSE_DATA_DDP_2    V_CAUSE_DATA_DDP_2(1U)
48417 
48418 #define S_CAUSE_DATA_CTX_2    17
48419 #define V_CAUSE_DATA_CTX_2(x) ((x) << S_CAUSE_DATA_CTX_2)
48420 #define F_CAUSE_DATA_CTX_2    V_CAUSE_DATA_CTX_2(1U)
48421 
48422 #define S_CAUSE_DATA_PARSER_2    16
48423 #define V_CAUSE_DATA_PARSER_2(x) ((x) << S_CAUSE_DATA_PARSER_2)
48424 #define F_CAUSE_DATA_PARSER_2    V_CAUSE_DATA_PARSER_2(1U)
48425 
48426 #define S_CAUSE_DATA_SNOOP_1    13
48427 #define V_CAUSE_DATA_SNOOP_1(x) ((x) << S_CAUSE_DATA_SNOOP_1)
48428 #define F_CAUSE_DATA_SNOOP_1    V_CAUSE_DATA_SNOOP_1(1U)
48429 
48430 #define S_CAUSE_DATA_SFIFO_1    12
48431 #define V_CAUSE_DATA_SFIFO_1(x) ((x) << S_CAUSE_DATA_SFIFO_1)
48432 #define F_CAUSE_DATA_SFIFO_1    V_CAUSE_DATA_SFIFO_1(1U)
48433 
48434 #define S_CAUSE_DATA_FIFO_1    11
48435 #define V_CAUSE_DATA_FIFO_1(x) ((x) << S_CAUSE_DATA_FIFO_1)
48436 #define F_CAUSE_DATA_FIFO_1    V_CAUSE_DATA_FIFO_1(1U)
48437 
48438 #define S_CAUSE_DATA_DDP_1    10
48439 #define V_CAUSE_DATA_DDP_1(x) ((x) << S_CAUSE_DATA_DDP_1)
48440 #define F_CAUSE_DATA_DDP_1    V_CAUSE_DATA_DDP_1(1U)
48441 
48442 #define S_CAUSE_DATA_CTX_1    9
48443 #define V_CAUSE_DATA_CTX_1(x) ((x) << S_CAUSE_DATA_CTX_1)
48444 #define F_CAUSE_DATA_CTX_1    V_CAUSE_DATA_CTX_1(1U)
48445 
48446 #define S_CAUSE_DATA_PARSER_1    8
48447 #define V_CAUSE_DATA_PARSER_1(x) ((x) << S_CAUSE_DATA_PARSER_1)
48448 #define F_CAUSE_DATA_PARSER_1    V_CAUSE_DATA_PARSER_1(1U)
48449 
48450 #define S_CAUSE_DATA_SNOOP_0    5
48451 #define V_CAUSE_DATA_SNOOP_0(x) ((x) << S_CAUSE_DATA_SNOOP_0)
48452 #define F_CAUSE_DATA_SNOOP_0    V_CAUSE_DATA_SNOOP_0(1U)
48453 
48454 #define S_CAUSE_DATA_SFIFO_0    4
48455 #define V_CAUSE_DATA_SFIFO_0(x) ((x) << S_CAUSE_DATA_SFIFO_0)
48456 #define F_CAUSE_DATA_SFIFO_0    V_CAUSE_DATA_SFIFO_0(1U)
48457 
48458 #define S_CAUSE_DATA_FIFO_0    3
48459 #define V_CAUSE_DATA_FIFO_0(x) ((x) << S_CAUSE_DATA_FIFO_0)
48460 #define F_CAUSE_DATA_FIFO_0    V_CAUSE_DATA_FIFO_0(1U)
48461 
48462 #define S_CAUSE_DATA_DDP_0    2
48463 #define V_CAUSE_DATA_DDP_0(x) ((x) << S_CAUSE_DATA_DDP_0)
48464 #define F_CAUSE_DATA_DDP_0    V_CAUSE_DATA_DDP_0(1U)
48465 
48466 #define S_CAUSE_DATA_CTX_0    1
48467 #define V_CAUSE_DATA_CTX_0(x) ((x) << S_CAUSE_DATA_CTX_0)
48468 #define F_CAUSE_DATA_CTX_0    V_CAUSE_DATA_CTX_0(1U)
48469 
48470 #define S_CAUSE_DATA_PARSER_0    0
48471 #define V_CAUSE_DATA_PARSER_0(x) ((x) << S_CAUSE_DATA_PARSER_0)
48472 #define F_CAUSE_DATA_PARSER_0    V_CAUSE_DATA_PARSER_0(1U)
48473 
48474 #define A_ULP_RX_PERR_ENABLE_DATA 0x19318
48475 
48476 #define S_PERR_ENABLE_DATA_SNOOP_3    29
48477 #define V_PERR_ENABLE_DATA_SNOOP_3(x) ((x) << S_PERR_ENABLE_DATA_SNOOP_3)
48478 #define F_PERR_ENABLE_DATA_SNOOP_3    V_PERR_ENABLE_DATA_SNOOP_3(1U)
48479 
48480 #define S_PERR_ENABLE_DATA_SFIFO_3    28
48481 #define V_PERR_ENABLE_DATA_SFIFO_3(x) ((x) << S_PERR_ENABLE_DATA_SFIFO_3)
48482 #define F_PERR_ENABLE_DATA_SFIFO_3    V_PERR_ENABLE_DATA_SFIFO_3(1U)
48483 
48484 #define S_PERR_ENABLE_DATA_FIFO_3    27
48485 #define V_PERR_ENABLE_DATA_FIFO_3(x) ((x) << S_PERR_ENABLE_DATA_FIFO_3)
48486 #define F_PERR_ENABLE_DATA_FIFO_3    V_PERR_ENABLE_DATA_FIFO_3(1U)
48487 
48488 #define S_PERR_ENABLE_DATA_DDP_3    26
48489 #define V_PERR_ENABLE_DATA_DDP_3(x) ((x) << S_PERR_ENABLE_DATA_DDP_3)
48490 #define F_PERR_ENABLE_DATA_DDP_3    V_PERR_ENABLE_DATA_DDP_3(1U)
48491 
48492 #define S_PERR_ENABLE_DATA_CTX_3    25
48493 #define V_PERR_ENABLE_DATA_CTX_3(x) ((x) << S_PERR_ENABLE_DATA_CTX_3)
48494 #define F_PERR_ENABLE_DATA_CTX_3    V_PERR_ENABLE_DATA_CTX_3(1U)
48495 
48496 #define S_PERR_ENABLE_DATA_PARSER_3    24
48497 #define V_PERR_ENABLE_DATA_PARSER_3(x) ((x) << S_PERR_ENABLE_DATA_PARSER_3)
48498 #define F_PERR_ENABLE_DATA_PARSER_3    V_PERR_ENABLE_DATA_PARSER_3(1U)
48499 
48500 #define S_PERR_ENABLE_DATA_SNOOP_2    21
48501 #define V_PERR_ENABLE_DATA_SNOOP_2(x) ((x) << S_PERR_ENABLE_DATA_SNOOP_2)
48502 #define F_PERR_ENABLE_DATA_SNOOP_2    V_PERR_ENABLE_DATA_SNOOP_2(1U)
48503 
48504 #define S_PERR_ENABLE_DATA_SFIFO_2    20
48505 #define V_PERR_ENABLE_DATA_SFIFO_2(x) ((x) << S_PERR_ENABLE_DATA_SFIFO_2)
48506 #define F_PERR_ENABLE_DATA_SFIFO_2    V_PERR_ENABLE_DATA_SFIFO_2(1U)
48507 
48508 #define S_PERR_ENABLE_DATA_FIFO_2    19
48509 #define V_PERR_ENABLE_DATA_FIFO_2(x) ((x) << S_PERR_ENABLE_DATA_FIFO_2)
48510 #define F_PERR_ENABLE_DATA_FIFO_2    V_PERR_ENABLE_DATA_FIFO_2(1U)
48511 
48512 #define S_PERR_ENABLE_DATA_DDP_2    18
48513 #define V_PERR_ENABLE_DATA_DDP_2(x) ((x) << S_PERR_ENABLE_DATA_DDP_2)
48514 #define F_PERR_ENABLE_DATA_DDP_2    V_PERR_ENABLE_DATA_DDP_2(1U)
48515 
48516 #define S_PERR_ENABLE_DATA_CTX_2    17
48517 #define V_PERR_ENABLE_DATA_CTX_2(x) ((x) << S_PERR_ENABLE_DATA_CTX_2)
48518 #define F_PERR_ENABLE_DATA_CTX_2    V_PERR_ENABLE_DATA_CTX_2(1U)
48519 
48520 #define S_PERR_ENABLE_DATA_PARSER_2    16
48521 #define V_PERR_ENABLE_DATA_PARSER_2(x) ((x) << S_PERR_ENABLE_DATA_PARSER_2)
48522 #define F_PERR_ENABLE_DATA_PARSER_2    V_PERR_ENABLE_DATA_PARSER_2(1U)
48523 
48524 #define S_PERR_ENABLE_DATA_SNOOP_1    13
48525 #define V_PERR_ENABLE_DATA_SNOOP_1(x) ((x) << S_PERR_ENABLE_DATA_SNOOP_1)
48526 #define F_PERR_ENABLE_DATA_SNOOP_1    V_PERR_ENABLE_DATA_SNOOP_1(1U)
48527 
48528 #define S_PERR_ENABLE_DATA_SFIFO_1    12
48529 #define V_PERR_ENABLE_DATA_SFIFO_1(x) ((x) << S_PERR_ENABLE_DATA_SFIFO_1)
48530 #define F_PERR_ENABLE_DATA_SFIFO_1    V_PERR_ENABLE_DATA_SFIFO_1(1U)
48531 
48532 #define S_PERR_ENABLE_DATA_FIFO_1    11
48533 #define V_PERR_ENABLE_DATA_FIFO_1(x) ((x) << S_PERR_ENABLE_DATA_FIFO_1)
48534 #define F_PERR_ENABLE_DATA_FIFO_1    V_PERR_ENABLE_DATA_FIFO_1(1U)
48535 
48536 #define S_PERR_ENABLE_DATA_DDP_1    10
48537 #define V_PERR_ENABLE_DATA_DDP_1(x) ((x) << S_PERR_ENABLE_DATA_DDP_1)
48538 #define F_PERR_ENABLE_DATA_DDP_1    V_PERR_ENABLE_DATA_DDP_1(1U)
48539 
48540 #define S_PERR_ENABLE_DATA_CTX_1    9
48541 #define V_PERR_ENABLE_DATA_CTX_1(x) ((x) << S_PERR_ENABLE_DATA_CTX_1)
48542 #define F_PERR_ENABLE_DATA_CTX_1    V_PERR_ENABLE_DATA_CTX_1(1U)
48543 
48544 #define S_PERR_ENABLE_DATA_PARSER_1    8
48545 #define V_PERR_ENABLE_DATA_PARSER_1(x) ((x) << S_PERR_ENABLE_DATA_PARSER_1)
48546 #define F_PERR_ENABLE_DATA_PARSER_1    V_PERR_ENABLE_DATA_PARSER_1(1U)
48547 
48548 #define S_PERR_ENABLE_DATA_SNOOP_0    5
48549 #define V_PERR_ENABLE_DATA_SNOOP_0(x) ((x) << S_PERR_ENABLE_DATA_SNOOP_0)
48550 #define F_PERR_ENABLE_DATA_SNOOP_0    V_PERR_ENABLE_DATA_SNOOP_0(1U)
48551 
48552 #define S_PERR_ENABLE_DATA_SFIFO_0    4
48553 #define V_PERR_ENABLE_DATA_SFIFO_0(x) ((x) << S_PERR_ENABLE_DATA_SFIFO_0)
48554 #define F_PERR_ENABLE_DATA_SFIFO_0    V_PERR_ENABLE_DATA_SFIFO_0(1U)
48555 
48556 #define S_PERR_ENABLE_DATA_FIFO_0    3
48557 #define V_PERR_ENABLE_DATA_FIFO_0(x) ((x) << S_PERR_ENABLE_DATA_FIFO_0)
48558 #define F_PERR_ENABLE_DATA_FIFO_0    V_PERR_ENABLE_DATA_FIFO_0(1U)
48559 
48560 #define S_PERR_ENABLE_DATA_DDP_0    2
48561 #define V_PERR_ENABLE_DATA_DDP_0(x) ((x) << S_PERR_ENABLE_DATA_DDP_0)
48562 #define F_PERR_ENABLE_DATA_DDP_0    V_PERR_ENABLE_DATA_DDP_0(1U)
48563 
48564 #define S_PERR_ENABLE_DATA_CTX_0    1
48565 #define V_PERR_ENABLE_DATA_CTX_0(x) ((x) << S_PERR_ENABLE_DATA_CTX_0)
48566 #define F_PERR_ENABLE_DATA_CTX_0    V_PERR_ENABLE_DATA_CTX_0(1U)
48567 
48568 #define S_PERR_ENABLE_DATA_PARSER_0    0
48569 #define V_PERR_ENABLE_DATA_PARSER_0(x) ((x) << S_PERR_ENABLE_DATA_PARSER_0)
48570 #define F_PERR_ENABLE_DATA_PARSER_0    V_PERR_ENABLE_DATA_PARSER_0(1U)
48571 
48572 #define A_ULP_RX_INT_ENABLE_ARB 0x19320
48573 
48574 #define S_ENABLE_ARB_PBL_PF_3    27
48575 #define V_ENABLE_ARB_PBL_PF_3(x) ((x) << S_ENABLE_ARB_PBL_PF_3)
48576 #define F_ENABLE_ARB_PBL_PF_3    V_ENABLE_ARB_PBL_PF_3(1U)
48577 
48578 #define S_ENABLE_ARB_PF_3    26
48579 #define V_ENABLE_ARB_PF_3(x) ((x) << S_ENABLE_ARB_PF_3)
48580 #define F_ENABLE_ARB_PF_3    V_ENABLE_ARB_PF_3(1U)
48581 
48582 #define S_ENABLE_ARB_TPT_PF_3    25
48583 #define V_ENABLE_ARB_TPT_PF_3(x) ((x) << S_ENABLE_ARB_TPT_PF_3)
48584 #define F_ENABLE_ARB_TPT_PF_3    V_ENABLE_ARB_TPT_PF_3(1U)
48585 
48586 #define S_ENABLE_ARB_F_3    24
48587 #define V_ENABLE_ARB_F_3(x) ((x) << S_ENABLE_ARB_F_3)
48588 #define F_ENABLE_ARB_F_3    V_ENABLE_ARB_F_3(1U)
48589 
48590 #define S_ENABLE_ARB_PBL_PF_2    19
48591 #define V_ENABLE_ARB_PBL_PF_2(x) ((x) << S_ENABLE_ARB_PBL_PF_2)
48592 #define F_ENABLE_ARB_PBL_PF_2    V_ENABLE_ARB_PBL_PF_2(1U)
48593 
48594 #define S_ENABLE_ARB_PF_2    18
48595 #define V_ENABLE_ARB_PF_2(x) ((x) << S_ENABLE_ARB_PF_2)
48596 #define F_ENABLE_ARB_PF_2    V_ENABLE_ARB_PF_2(1U)
48597 
48598 #define S_ENABLE_ARB_TPT_PF_2    17
48599 #define V_ENABLE_ARB_TPT_PF_2(x) ((x) << S_ENABLE_ARB_TPT_PF_2)
48600 #define F_ENABLE_ARB_TPT_PF_2    V_ENABLE_ARB_TPT_PF_2(1U)
48601 
48602 #define S_ENABLE_ARB_F_2    16
48603 #define V_ENABLE_ARB_F_2(x) ((x) << S_ENABLE_ARB_F_2)
48604 #define F_ENABLE_ARB_F_2    V_ENABLE_ARB_F_2(1U)
48605 
48606 #define S_ENABLE_ARB_PBL_PF_1    11
48607 #define V_ENABLE_ARB_PBL_PF_1(x) ((x) << S_ENABLE_ARB_PBL_PF_1)
48608 #define F_ENABLE_ARB_PBL_PF_1    V_ENABLE_ARB_PBL_PF_1(1U)
48609 
48610 #define S_ENABLE_ARB_PF_1    10
48611 #define V_ENABLE_ARB_PF_1(x) ((x) << S_ENABLE_ARB_PF_1)
48612 #define F_ENABLE_ARB_PF_1    V_ENABLE_ARB_PF_1(1U)
48613 
48614 #define S_ENABLE_ARB_TPT_PF_1    9
48615 #define V_ENABLE_ARB_TPT_PF_1(x) ((x) << S_ENABLE_ARB_TPT_PF_1)
48616 #define F_ENABLE_ARB_TPT_PF_1    V_ENABLE_ARB_TPT_PF_1(1U)
48617 
48618 #define S_ENABLE_ARB_F_1    8
48619 #define V_ENABLE_ARB_F_1(x) ((x) << S_ENABLE_ARB_F_1)
48620 #define F_ENABLE_ARB_F_1    V_ENABLE_ARB_F_1(1U)
48621 
48622 #define S_ENABLE_ARB_PBL_PF_0    3
48623 #define V_ENABLE_ARB_PBL_PF_0(x) ((x) << S_ENABLE_ARB_PBL_PF_0)
48624 #define F_ENABLE_ARB_PBL_PF_0    V_ENABLE_ARB_PBL_PF_0(1U)
48625 
48626 #define S_ENABLE_ARB_PF_0    2
48627 #define V_ENABLE_ARB_PF_0(x) ((x) << S_ENABLE_ARB_PF_0)
48628 #define F_ENABLE_ARB_PF_0    V_ENABLE_ARB_PF_0(1U)
48629 
48630 #define S_ENABLE_ARB_TPT_PF_0    1
48631 #define V_ENABLE_ARB_TPT_PF_0(x) ((x) << S_ENABLE_ARB_TPT_PF_0)
48632 #define F_ENABLE_ARB_TPT_PF_0    V_ENABLE_ARB_TPT_PF_0(1U)
48633 
48634 #define S_ENABLE_ARB_F_0    0
48635 #define V_ENABLE_ARB_F_0(x) ((x) << S_ENABLE_ARB_F_0)
48636 #define F_ENABLE_ARB_F_0    V_ENABLE_ARB_F_0(1U)
48637 
48638 #define A_ULP_RX_INT_CAUSE_ARB 0x19324
48639 
48640 #define S_CAUSE_ARB_PBL_PF_3    27
48641 #define V_CAUSE_ARB_PBL_PF_3(x) ((x) << S_CAUSE_ARB_PBL_PF_3)
48642 #define F_CAUSE_ARB_PBL_PF_3    V_CAUSE_ARB_PBL_PF_3(1U)
48643 
48644 #define S_CAUSE_ARB_PF_3    26
48645 #define V_CAUSE_ARB_PF_3(x) ((x) << S_CAUSE_ARB_PF_3)
48646 #define F_CAUSE_ARB_PF_3    V_CAUSE_ARB_PF_3(1U)
48647 
48648 #define S_CAUSE_ARB_TPT_PF_3    25
48649 #define V_CAUSE_ARB_TPT_PF_3(x) ((x) << S_CAUSE_ARB_TPT_PF_3)
48650 #define F_CAUSE_ARB_TPT_PF_3    V_CAUSE_ARB_TPT_PF_3(1U)
48651 
48652 #define S_CAUSE_ARB_F_3    24
48653 #define V_CAUSE_ARB_F_3(x) ((x) << S_CAUSE_ARB_F_3)
48654 #define F_CAUSE_ARB_F_3    V_CAUSE_ARB_F_3(1U)
48655 
48656 #define S_CAUSE_ARB_PBL_PF_2    19
48657 #define V_CAUSE_ARB_PBL_PF_2(x) ((x) << S_CAUSE_ARB_PBL_PF_2)
48658 #define F_CAUSE_ARB_PBL_PF_2    V_CAUSE_ARB_PBL_PF_2(1U)
48659 
48660 #define S_CAUSE_ARB_PF_2    18
48661 #define V_CAUSE_ARB_PF_2(x) ((x) << S_CAUSE_ARB_PF_2)
48662 #define F_CAUSE_ARB_PF_2    V_CAUSE_ARB_PF_2(1U)
48663 
48664 #define S_CAUSE_ARB_TPT_PF_2    17
48665 #define V_CAUSE_ARB_TPT_PF_2(x) ((x) << S_CAUSE_ARB_TPT_PF_2)
48666 #define F_CAUSE_ARB_TPT_PF_2    V_CAUSE_ARB_TPT_PF_2(1U)
48667 
48668 #define S_CAUSE_ARB_F_2    16
48669 #define V_CAUSE_ARB_F_2(x) ((x) << S_CAUSE_ARB_F_2)
48670 #define F_CAUSE_ARB_F_2    V_CAUSE_ARB_F_2(1U)
48671 
48672 #define S_CAUSE_ARB_PBL_PF_1    11
48673 #define V_CAUSE_ARB_PBL_PF_1(x) ((x) << S_CAUSE_ARB_PBL_PF_1)
48674 #define F_CAUSE_ARB_PBL_PF_1    V_CAUSE_ARB_PBL_PF_1(1U)
48675 
48676 #define S_CAUSE_ARB_PF_1    10
48677 #define V_CAUSE_ARB_PF_1(x) ((x) << S_CAUSE_ARB_PF_1)
48678 #define F_CAUSE_ARB_PF_1    V_CAUSE_ARB_PF_1(1U)
48679 
48680 #define S_CAUSE_ARB_TPT_PF_1    9
48681 #define V_CAUSE_ARB_TPT_PF_1(x) ((x) << S_CAUSE_ARB_TPT_PF_1)
48682 #define F_CAUSE_ARB_TPT_PF_1    V_CAUSE_ARB_TPT_PF_1(1U)
48683 
48684 #define S_CAUSE_ARB_F_1    8
48685 #define V_CAUSE_ARB_F_1(x) ((x) << S_CAUSE_ARB_F_1)
48686 #define F_CAUSE_ARB_F_1    V_CAUSE_ARB_F_1(1U)
48687 
48688 #define S_CAUSE_ARB_PBL_PF_0    3
48689 #define V_CAUSE_ARB_PBL_PF_0(x) ((x) << S_CAUSE_ARB_PBL_PF_0)
48690 #define F_CAUSE_ARB_PBL_PF_0    V_CAUSE_ARB_PBL_PF_0(1U)
48691 
48692 #define S_CAUSE_ARB_PF_0    2
48693 #define V_CAUSE_ARB_PF_0(x) ((x) << S_CAUSE_ARB_PF_0)
48694 #define F_CAUSE_ARB_PF_0    V_CAUSE_ARB_PF_0(1U)
48695 
48696 #define S_CAUSE_ARB_TPT_PF_0    1
48697 #define V_CAUSE_ARB_TPT_PF_0(x) ((x) << S_CAUSE_ARB_TPT_PF_0)
48698 #define F_CAUSE_ARB_TPT_PF_0    V_CAUSE_ARB_TPT_PF_0(1U)
48699 
48700 #define S_CAUSE_ARB_F_0    0
48701 #define V_CAUSE_ARB_F_0(x) ((x) << S_CAUSE_ARB_F_0)
48702 #define F_CAUSE_ARB_F_0    V_CAUSE_ARB_F_0(1U)
48703 
48704 #define A_ULP_RX_PERR_ENABLE_ARB 0x19328
48705 
48706 #define S_PERR_ENABLE_ARB_PBL_PF_3    27
48707 #define V_PERR_ENABLE_ARB_PBL_PF_3(x) ((x) << S_PERR_ENABLE_ARB_PBL_PF_3)
48708 #define F_PERR_ENABLE_ARB_PBL_PF_3    V_PERR_ENABLE_ARB_PBL_PF_3(1U)
48709 
48710 #define S_PERR_ENABLE_ARB_PF_3    26
48711 #define V_PERR_ENABLE_ARB_PF_3(x) ((x) << S_PERR_ENABLE_ARB_PF_3)
48712 #define F_PERR_ENABLE_ARB_PF_3    V_PERR_ENABLE_ARB_PF_3(1U)
48713 
48714 #define S_PERR_ENABLE_ARB_TPT_PF_3    25
48715 #define V_PERR_ENABLE_ARB_TPT_PF_3(x) ((x) << S_PERR_ENABLE_ARB_TPT_PF_3)
48716 #define F_PERR_ENABLE_ARB_TPT_PF_3    V_PERR_ENABLE_ARB_TPT_PF_3(1U)
48717 
48718 #define S_PERR_ENABLE_ARB_F_3    24
48719 #define V_PERR_ENABLE_ARB_F_3(x) ((x) << S_PERR_ENABLE_ARB_F_3)
48720 #define F_PERR_ENABLE_ARB_F_3    V_PERR_ENABLE_ARB_F_3(1U)
48721 
48722 #define S_PERR_ENABLE_ARB_PBL_PF_2    19
48723 #define V_PERR_ENABLE_ARB_PBL_PF_2(x) ((x) << S_PERR_ENABLE_ARB_PBL_PF_2)
48724 #define F_PERR_ENABLE_ARB_PBL_PF_2    V_PERR_ENABLE_ARB_PBL_PF_2(1U)
48725 
48726 #define S_PERR_ENABLE_ARB_PF_2    18
48727 #define V_PERR_ENABLE_ARB_PF_2(x) ((x) << S_PERR_ENABLE_ARB_PF_2)
48728 #define F_PERR_ENABLE_ARB_PF_2    V_PERR_ENABLE_ARB_PF_2(1U)
48729 
48730 #define S_PERR_ENABLE_ARB_TPT_PF_2    17
48731 #define V_PERR_ENABLE_ARB_TPT_PF_2(x) ((x) << S_PERR_ENABLE_ARB_TPT_PF_2)
48732 #define F_PERR_ENABLE_ARB_TPT_PF_2    V_PERR_ENABLE_ARB_TPT_PF_2(1U)
48733 
48734 #define S_PERR_ENABLE_ARB_F_2    16
48735 #define V_PERR_ENABLE_ARB_F_2(x) ((x) << S_PERR_ENABLE_ARB_F_2)
48736 #define F_PERR_ENABLE_ARB_F_2    V_PERR_ENABLE_ARB_F_2(1U)
48737 
48738 #define S_PERR_ENABLE_ARB_PBL_PF_1    11
48739 #define V_PERR_ENABLE_ARB_PBL_PF_1(x) ((x) << S_PERR_ENABLE_ARB_PBL_PF_1)
48740 #define F_PERR_ENABLE_ARB_PBL_PF_1    V_PERR_ENABLE_ARB_PBL_PF_1(1U)
48741 
48742 #define S_PERR_ENABLE_ARB_PF_1    10
48743 #define V_PERR_ENABLE_ARB_PF_1(x) ((x) << S_PERR_ENABLE_ARB_PF_1)
48744 #define F_PERR_ENABLE_ARB_PF_1    V_PERR_ENABLE_ARB_PF_1(1U)
48745 
48746 #define S_PERR_ENABLE_ARB_TPT_PF_1    9
48747 #define V_PERR_ENABLE_ARB_TPT_PF_1(x) ((x) << S_PERR_ENABLE_ARB_TPT_PF_1)
48748 #define F_PERR_ENABLE_ARB_TPT_PF_1    V_PERR_ENABLE_ARB_TPT_PF_1(1U)
48749 
48750 #define S_PERR_ENABLE_ARB_F_1    8
48751 #define V_PERR_ENABLE_ARB_F_1(x) ((x) << S_PERR_ENABLE_ARB_F_1)
48752 #define F_PERR_ENABLE_ARB_F_1    V_PERR_ENABLE_ARB_F_1(1U)
48753 
48754 #define S_PERR_ENABLE_ARB_PBL_PF_0    3
48755 #define V_PERR_ENABLE_ARB_PBL_PF_0(x) ((x) << S_PERR_ENABLE_ARB_PBL_PF_0)
48756 #define F_PERR_ENABLE_ARB_PBL_PF_0    V_PERR_ENABLE_ARB_PBL_PF_0(1U)
48757 
48758 #define S_PERR_ENABLE_ARB_PF_0    2
48759 #define V_PERR_ENABLE_ARB_PF_0(x) ((x) << S_PERR_ENABLE_ARB_PF_0)
48760 #define F_PERR_ENABLE_ARB_PF_0    V_PERR_ENABLE_ARB_PF_0(1U)
48761 
48762 #define S_PERR_ENABLE_ARB_TPT_PF_0    1
48763 #define V_PERR_ENABLE_ARB_TPT_PF_0(x) ((x) << S_PERR_ENABLE_ARB_TPT_PF_0)
48764 #define F_PERR_ENABLE_ARB_TPT_PF_0    V_PERR_ENABLE_ARB_TPT_PF_0(1U)
48765 
48766 #define S_PERR_ENABLE_ARB_F_0    0
48767 #define V_PERR_ENABLE_ARB_F_0(x) ((x) << S_PERR_ENABLE_ARB_F_0)
48768 #define F_PERR_ENABLE_ARB_F_0    V_PERR_ENABLE_ARB_F_0(1U)
48769 
48770 #define A_ULP_RX_CTL1 0x19330
48771 
48772 #define S_ISCSI_CTL2    27
48773 #define V_ISCSI_CTL2(x) ((x) << S_ISCSI_CTL2)
48774 #define F_ISCSI_CTL2    V_ISCSI_CTL2(1U)
48775 
48776 #define S_ISCSI_CTL1    26
48777 #define V_ISCSI_CTL1(x) ((x) << S_ISCSI_CTL1)
48778 #define F_ISCSI_CTL1    V_ISCSI_CTL1(1U)
48779 
48780 #define S_ISCSI_CTL0    25
48781 #define V_ISCSI_CTL0(x) ((x) << S_ISCSI_CTL0)
48782 #define F_ISCSI_CTL0    V_ISCSI_CTL0(1U)
48783 
48784 #define S_NVME_TCP_DATA_ALIGNMENT    16
48785 #define M_NVME_TCP_DATA_ALIGNMENT    0x1ffU
48786 #define V_NVME_TCP_DATA_ALIGNMENT(x) ((x) << S_NVME_TCP_DATA_ALIGNMENT)
48787 #define G_NVME_TCP_DATA_ALIGNMENT(x) (((x) >> S_NVME_TCP_DATA_ALIGNMENT) & M_NVME_TCP_DATA_ALIGNMENT)
48788 
48789 #define S_NVME_TCP_INVLD_MSG_DIS    14
48790 #define M_NVME_TCP_INVLD_MSG_DIS    0x3U
48791 #define V_NVME_TCP_INVLD_MSG_DIS(x) ((x) << S_NVME_TCP_INVLD_MSG_DIS)
48792 #define G_NVME_TCP_INVLD_MSG_DIS(x) (((x) >> S_NVME_TCP_INVLD_MSG_DIS) & M_NVME_TCP_INVLD_MSG_DIS)
48793 
48794 #define S_NVME_TCP_DDP_PDU_CHK_TYPE    13
48795 #define V_NVME_TCP_DDP_PDU_CHK_TYPE(x) ((x) << S_NVME_TCP_DDP_PDU_CHK_TYPE)
48796 #define F_NVME_TCP_DDP_PDU_CHK_TYPE    V_NVME_TCP_DDP_PDU_CHK_TYPE(1U)
48797 
48798 #define S_T10_CONFIG_ENB    12
48799 #define V_T10_CONFIG_ENB(x) ((x) << S_T10_CONFIG_ENB)
48800 #define F_T10_CONFIG_ENB    V_T10_CONFIG_ENB(1U)
48801 
48802 #define S_NVME_TCP_COLOUR_ENB    10
48803 #define M_NVME_TCP_COLOUR_ENB    0x3U
48804 #define V_NVME_TCP_COLOUR_ENB(x) ((x) << S_NVME_TCP_COLOUR_ENB)
48805 #define G_NVME_TCP_COLOUR_ENB(x) (((x) >> S_NVME_TCP_COLOUR_ENB) & M_NVME_TCP_COLOUR_ENB)
48806 
48807 #define S_ROCE_SEND_RQE    8
48808 #define V_ROCE_SEND_RQE(x) ((x) << S_ROCE_SEND_RQE)
48809 #define F_ROCE_SEND_RQE    V_ROCE_SEND_RQE(1U)
48810 
48811 #define S_RDMA_INVLD_MSG_DIS    6
48812 #define M_RDMA_INVLD_MSG_DIS    0x3U
48813 #define V_RDMA_INVLD_MSG_DIS(x) ((x) << S_RDMA_INVLD_MSG_DIS)
48814 #define G_RDMA_INVLD_MSG_DIS(x) (((x) >> S_RDMA_INVLD_MSG_DIS) & M_RDMA_INVLD_MSG_DIS)
48815 
48816 #define S_ROCE_INVLD_MSG_DIS    4
48817 #define M_ROCE_INVLD_MSG_DIS    0x3U
48818 #define V_ROCE_INVLD_MSG_DIS(x) ((x) << S_ROCE_INVLD_MSG_DIS)
48819 #define G_ROCE_INVLD_MSG_DIS(x) (((x) >> S_ROCE_INVLD_MSG_DIS) & M_ROCE_INVLD_MSG_DIS)
48820 
48821 #define S_T7_MEM_ADDR_CTRL    2
48822 #define M_T7_MEM_ADDR_CTRL    0x3U
48823 #define V_T7_MEM_ADDR_CTRL(x) ((x) << S_T7_MEM_ADDR_CTRL)
48824 #define G_T7_MEM_ADDR_CTRL(x) (((x) >> S_T7_MEM_ADDR_CTRL) & M_T7_MEM_ADDR_CTRL)
48825 
48826 #define S_ENB_32K_PDU    1
48827 #define V_ENB_32K_PDU(x) ((x) << S_ENB_32K_PDU)
48828 #define F_ENB_32K_PDU    V_ENB_32K_PDU(1U)
48829 
48830 #define S_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS    0
48831 #define V_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS(x) ((x) << S_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS)
48832 #define F_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS    V_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS(1U)
48833 
48834 #define A_ULP_RX_TLS_IND_CMD 0x19348
48835 
48836 #define S_TLS_RX_REG_OFF_ADDR    0
48837 #define M_TLS_RX_REG_OFF_ADDR    0x3ffU
48838 #define V_TLS_RX_REG_OFF_ADDR(x) ((x) << S_TLS_RX_REG_OFF_ADDR)
48839 #define G_TLS_RX_REG_OFF_ADDR(x) (((x) >> S_TLS_RX_REG_OFF_ADDR) & M_TLS_RX_REG_OFF_ADDR)
48840 
48841 #define A_ULP_RX_TLS_IND_DATA 0x1934c
48842 #define A_ULP_RX_TLS_CH0_HMACCTRL_CFG 0x20
48843 #define A_ULP_RX_TLS_CH1_HMACCTRL_CFG 0x60
48844 
48845 /* registers for module SF */
48846 #define SF_BASE_ADDR 0x193f8
48847 
48848 #define A_SF_DATA 0x193f8
48849 #define A_SF_OP 0x193fc
48850 
48851 #define S_SF_LOCK    4
48852 #define V_SF_LOCK(x) ((x) << S_SF_LOCK)
48853 #define F_SF_LOCK    V_SF_LOCK(1U)
48854 
48855 #define S_CONT    3
48856 #define V_CONT(x) ((x) << S_CONT)
48857 #define F_CONT    V_CONT(1U)
48858 
48859 #define S_BYTECNT    1
48860 #define M_BYTECNT    0x3U
48861 #define V_BYTECNT(x) ((x) << S_BYTECNT)
48862 #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)
48863 
48864 #define S_EN32BADDR    30
48865 #define V_EN32BADDR(x) ((x) << S_EN32BADDR)
48866 #define F_EN32BADDR    V_EN32BADDR(1U)
48867 
48868 #define S_NUM_OF_BYTES    1
48869 #define M_NUM_OF_BYTES    0x3U
48870 #define V_NUM_OF_BYTES(x) ((x) << S_NUM_OF_BYTES)
48871 #define G_NUM_OF_BYTES(x) (((x) >> S_NUM_OF_BYTES) & M_NUM_OF_BYTES)
48872 
48873 #define S_QUADREADDISABLE    5
48874 #define V_QUADREADDISABLE(x) ((x) << S_QUADREADDISABLE)
48875 #define F_QUADREADDISABLE    V_QUADREADDISABLE(1U)
48876 
48877 #define S_EXIT4B    6
48878 #define V_EXIT4B(x) ((x) << S_EXIT4B)
48879 #define F_EXIT4B    V_EXIT4B(1U)
48880 
48881 #define S_ENTER4B    7
48882 #define V_ENTER4B(x) ((x) << S_ENTER4B)
48883 #define F_ENTER4B    V_ENTER4B(1U)
48884 
48885 #define S_QUADWRENABLE    8
48886 #define V_QUADWRENABLE(x) ((x) << S_QUADWRENABLE)
48887 #define F_QUADWRENABLE    V_QUADWRENABLE(1U)
48888 
48889 #define S_REGDBG_SEL    9
48890 #define V_REGDBG_SEL(x) ((x) << S_REGDBG_SEL)
48891 #define F_REGDBG_SEL    V_REGDBG_SEL(1U)
48892 
48893 #define S_REGDBG_MODE    10
48894 #define V_REGDBG_MODE(x) ((x) << S_REGDBG_MODE)
48895 #define F_REGDBG_MODE    V_REGDBG_MODE(1U)
48896 
48897 /* registers for module PL */
48898 #define PL_BASE_ADDR 0x19400
48899 
48900 #define A_PL_VF_WHOAMI 0x0
48901 
48902 #define S_PORTXMAP    24
48903 #define M_PORTXMAP    0x7U
48904 #define V_PORTXMAP(x) ((x) << S_PORTXMAP)
48905 #define G_PORTXMAP(x) (((x) >> S_PORTXMAP) & M_PORTXMAP)
48906 
48907 #define S_SOURCEBUS    16
48908 #define M_SOURCEBUS    0x3U
48909 #define V_SOURCEBUS(x) ((x) << S_SOURCEBUS)
48910 #define G_SOURCEBUS(x) (((x) >> S_SOURCEBUS) & M_SOURCEBUS)
48911 
48912 #define S_SOURCEPF    8
48913 #define M_SOURCEPF    0x7U
48914 #define V_SOURCEPF(x) ((x) << S_SOURCEPF)
48915 #define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF)
48916 
48917 #define S_ISVF    7
48918 #define V_ISVF(x) ((x) << S_ISVF)
48919 #define F_ISVF    V_ISVF(1U)
48920 
48921 #define S_VFID    0
48922 #define M_VFID    0x7fU
48923 #define V_VFID(x) ((x) << S_VFID)
48924 #define G_VFID(x) (((x) >> S_VFID) & M_VFID)
48925 
48926 #define S_T6_SOURCEPF    9
48927 #define M_T6_SOURCEPF    0x7U
48928 #define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF)
48929 #define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF)
48930 
48931 #define S_T6_ISVF    8
48932 #define V_T6_ISVF(x) ((x) << S_T6_ISVF)
48933 #define F_T6_ISVF    V_T6_ISVF(1U)
48934 
48935 #define S_T6_VFID    0
48936 #define M_T6_VFID    0xffU
48937 #define V_T6_VFID(x) ((x) << S_T6_VFID)
48938 #define G_T6_VFID(x) (((x) >> S_T6_VFID) & M_T6_VFID)
48939 
48940 #define A_PL_VF_REV 0x4
48941 
48942 #define S_CHIPID    4
48943 #define M_CHIPID    0xfU
48944 #define V_CHIPID(x) ((x) << S_CHIPID)
48945 #define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)
48946 
48947 #define A_PL_VF_REVISION 0x8
48948 #define A_PL_PF_INT_CAUSE 0x3c0
48949 
48950 #define S_PFSW    3
48951 #define V_PFSW(x) ((x) << S_PFSW)
48952 #define F_PFSW    V_PFSW(1U)
48953 
48954 #define S_PFSGE    2
48955 #define V_PFSGE(x) ((x) << S_PFSGE)
48956 #define F_PFSGE    V_PFSGE(1U)
48957 
48958 #define S_PFCIM    1
48959 #define V_PFCIM(x) ((x) << S_PFCIM)
48960 #define F_PFCIM    V_PFCIM(1U)
48961 
48962 #define S_PFMPS    0
48963 #define V_PFMPS(x) ((x) << S_PFMPS)
48964 #define F_PFMPS    V_PFMPS(1U)
48965 
48966 #define A_PL_PF_INT_ENABLE 0x3c4
48967 #define A_PL_PF_CTL 0x3c8
48968 
48969 #define S_SWINT    0
48970 #define V_SWINT(x) ((x) << S_SWINT)
48971 #define F_SWINT    V_SWINT(1U)
48972 
48973 #define A_PL_WHOAMI 0x19400
48974 #define A_PL_PERR_CAUSE 0x19404
48975 
48976 #define S_UART    28
48977 #define V_UART(x) ((x) << S_UART)
48978 #define F_UART    V_UART(1U)
48979 
48980 #define S_ULP_TX    27
48981 #define V_ULP_TX(x) ((x) << S_ULP_TX)
48982 #define F_ULP_TX    V_ULP_TX(1U)
48983 
48984 #define S_SGE    26
48985 #define V_SGE(x) ((x) << S_SGE)
48986 #define F_SGE    V_SGE(1U)
48987 
48988 #define S_HMA    25
48989 #define V_HMA(x) ((x) << S_HMA)
48990 #define F_HMA    V_HMA(1U)
48991 
48992 #define S_CPL_SWITCH    24
48993 #define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
48994 #define F_CPL_SWITCH    V_CPL_SWITCH(1U)
48995 
48996 #define S_ULP_RX    23
48997 #define V_ULP_RX(x) ((x) << S_ULP_RX)
48998 #define F_ULP_RX    V_ULP_RX(1U)
48999 
49000 #define S_PM_RX    22
49001 #define V_PM_RX(x) ((x) << S_PM_RX)
49002 #define F_PM_RX    V_PM_RX(1U)
49003 
49004 #define S_PM_TX    21
49005 #define V_PM_TX(x) ((x) << S_PM_TX)
49006 #define F_PM_TX    V_PM_TX(1U)
49007 
49008 #define S_MA    20
49009 #define V_MA(x) ((x) << S_MA)
49010 #define F_MA    V_MA(1U)
49011 
49012 #define S_TP    19
49013 #define V_TP(x) ((x) << S_TP)
49014 #define F_TP    V_TP(1U)
49015 
49016 #define S_LE    18
49017 #define V_LE(x) ((x) << S_LE)
49018 #define F_LE    V_LE(1U)
49019 
49020 #define S_EDC1    17
49021 #define V_EDC1(x) ((x) << S_EDC1)
49022 #define F_EDC1    V_EDC1(1U)
49023 
49024 #define S_EDC0    16
49025 #define V_EDC0(x) ((x) << S_EDC0)
49026 #define F_EDC0    V_EDC0(1U)
49027 
49028 #define S_MC    15
49029 #define V_MC(x) ((x) << S_MC)
49030 #define F_MC    V_MC(1U)
49031 
49032 #define S_PCIE    14
49033 #define V_PCIE(x) ((x) << S_PCIE)
49034 #define F_PCIE    V_PCIE(1U)
49035 
49036 #define S_PMU    13
49037 #define V_PMU(x) ((x) << S_PMU)
49038 #define F_PMU    V_PMU(1U)
49039 
49040 #define S_XGMAC_KR1    12
49041 #define V_XGMAC_KR1(x) ((x) << S_XGMAC_KR1)
49042 #define F_XGMAC_KR1    V_XGMAC_KR1(1U)
49043 
49044 #define S_XGMAC_KR0    11
49045 #define V_XGMAC_KR0(x) ((x) << S_XGMAC_KR0)
49046 #define F_XGMAC_KR0    V_XGMAC_KR0(1U)
49047 
49048 #define S_XGMAC1    10
49049 #define V_XGMAC1(x) ((x) << S_XGMAC1)
49050 #define F_XGMAC1    V_XGMAC1(1U)
49051 
49052 #define S_XGMAC0    9
49053 #define V_XGMAC0(x) ((x) << S_XGMAC0)
49054 #define F_XGMAC0    V_XGMAC0(1U)
49055 
49056 #define S_SMB    8
49057 #define V_SMB(x) ((x) << S_SMB)
49058 #define F_SMB    V_SMB(1U)
49059 
49060 #define S_SF    7
49061 #define V_SF(x) ((x) << S_SF)
49062 #define F_SF    V_SF(1U)
49063 
49064 #define S_PL    6
49065 #define V_PL(x) ((x) << S_PL)
49066 #define F_PL    V_PL(1U)
49067 
49068 #define S_NCSI    5
49069 #define V_NCSI(x) ((x) << S_NCSI)
49070 #define F_NCSI    V_NCSI(1U)
49071 
49072 #define S_MPS    4
49073 #define V_MPS(x) ((x) << S_MPS)
49074 #define F_MPS    V_MPS(1U)
49075 
49076 #define S_MI    3
49077 #define V_MI(x) ((x) << S_MI)
49078 #define F_MI    V_MI(1U)
49079 
49080 #define S_DBG    2
49081 #define V_DBG(x) ((x) << S_DBG)
49082 #define F_DBG    V_DBG(1U)
49083 
49084 #define S_I2CM    1
49085 #define V_I2CM(x) ((x) << S_I2CM)
49086 #define F_I2CM    V_I2CM(1U)
49087 
49088 #define S_CIM    0
49089 #define V_CIM(x) ((x) << S_CIM)
49090 #define F_CIM    V_CIM(1U)
49091 
49092 #define S_MC1    31
49093 #define V_MC1(x) ((x) << S_MC1)
49094 #define F_MC1    V_MC1(1U)
49095 
49096 #define S_MC0    15
49097 #define V_MC0(x) ((x) << S_MC0)
49098 #define F_MC0    V_MC0(1U)
49099 
49100 #define S_ANYMAC    9
49101 #define V_ANYMAC(x) ((x) << S_ANYMAC)
49102 #define F_ANYMAC    V_ANYMAC(1U)
49103 
49104 #define S_T7_PL_PERR_CRYPTO_KEY    31
49105 #define V_T7_PL_PERR_CRYPTO_KEY(x) ((x) << S_T7_PL_PERR_CRYPTO_KEY)
49106 #define F_T7_PL_PERR_CRYPTO_KEY    V_T7_PL_PERR_CRYPTO_KEY(1U)
49107 
49108 #define S_T7_PL_PERR_CRYPTO1    30
49109 #define V_T7_PL_PERR_CRYPTO1(x) ((x) << S_T7_PL_PERR_CRYPTO1)
49110 #define F_T7_PL_PERR_CRYPTO1    V_T7_PL_PERR_CRYPTO1(1U)
49111 
49112 #define S_T7_PL_PERR_CRYPTO0    29
49113 #define V_T7_PL_PERR_CRYPTO0(x) ((x) << S_T7_PL_PERR_CRYPTO0)
49114 #define F_T7_PL_PERR_CRYPTO0    V_T7_PL_PERR_CRYPTO0(1U)
49115 
49116 #define S_T7_PL_PERR_GCACHE    28
49117 #define V_T7_PL_PERR_GCACHE(x) ((x) << S_T7_PL_PERR_GCACHE)
49118 #define F_T7_PL_PERR_GCACHE    V_T7_PL_PERR_GCACHE(1U)
49119 
49120 #define S_T7_PL_PERR_ARM    27
49121 #define V_T7_PL_PERR_ARM(x) ((x) << S_T7_PL_PERR_ARM)
49122 #define F_T7_PL_PERR_ARM    V_T7_PL_PERR_ARM(1U)
49123 
49124 #define S_T7_PL_PERR_ULP_TX    26
49125 #define V_T7_PL_PERR_ULP_TX(x) ((x) << S_T7_PL_PERR_ULP_TX)
49126 #define F_T7_PL_PERR_ULP_TX    V_T7_PL_PERR_ULP_TX(1U)
49127 
49128 #define S_T7_PL_PERR_SGE    25
49129 #define V_T7_PL_PERR_SGE(x) ((x) << S_T7_PL_PERR_SGE)
49130 #define F_T7_PL_PERR_SGE    V_T7_PL_PERR_SGE(1U)
49131 
49132 #define S_T7_PL_PERR_HMA    24
49133 #define V_T7_PL_PERR_HMA(x) ((x) << S_T7_PL_PERR_HMA)
49134 #define F_T7_PL_PERR_HMA    V_T7_PL_PERR_HMA(1U)
49135 
49136 #define S_T7_PL_PERR_CPL_SWITCH    23
49137 #define V_T7_PL_PERR_CPL_SWITCH(x) ((x) << S_T7_PL_PERR_CPL_SWITCH)
49138 #define F_T7_PL_PERR_CPL_SWITCH    V_T7_PL_PERR_CPL_SWITCH(1U)
49139 
49140 #define S_T7_PL_PERR_ULP_RX    22
49141 #define V_T7_PL_PERR_ULP_RX(x) ((x) << S_T7_PL_PERR_ULP_RX)
49142 #define F_T7_PL_PERR_ULP_RX    V_T7_PL_PERR_ULP_RX(1U)
49143 
49144 #define S_T7_PL_PERR_PM_RX    21
49145 #define V_T7_PL_PERR_PM_RX(x) ((x) << S_T7_PL_PERR_PM_RX)
49146 #define F_T7_PL_PERR_PM_RX    V_T7_PL_PERR_PM_RX(1U)
49147 
49148 #define S_T7_PL_PERR_PM_TX    20
49149 #define V_T7_PL_PERR_PM_TX(x) ((x) << S_T7_PL_PERR_PM_TX)
49150 #define F_T7_PL_PERR_PM_TX    V_T7_PL_PERR_PM_TX(1U)
49151 
49152 #define S_T7_PL_PERR_MA    19
49153 #define V_T7_PL_PERR_MA(x) ((x) << S_T7_PL_PERR_MA)
49154 #define F_T7_PL_PERR_MA    V_T7_PL_PERR_MA(1U)
49155 
49156 #define S_T7_PL_PERR_TP    18
49157 #define V_T7_PL_PERR_TP(x) ((x) << S_T7_PL_PERR_TP)
49158 #define F_T7_PL_PERR_TP    V_T7_PL_PERR_TP(1U)
49159 
49160 #define S_T7_PL_PERR_LE    17
49161 #define V_T7_PL_PERR_LE(x) ((x) << S_T7_PL_PERR_LE)
49162 #define F_T7_PL_PERR_LE    V_T7_PL_PERR_LE(1U)
49163 
49164 #define S_T7_PL_PERR_EDC1    16
49165 #define V_T7_PL_PERR_EDC1(x) ((x) << S_T7_PL_PERR_EDC1)
49166 #define F_T7_PL_PERR_EDC1    V_T7_PL_PERR_EDC1(1U)
49167 
49168 #define S_T7_PL_PERR_EDC0    15
49169 #define V_T7_PL_PERR_EDC0(x) ((x) << S_T7_PL_PERR_EDC0)
49170 #define F_T7_PL_PERR_EDC0    V_T7_PL_PERR_EDC0(1U)
49171 
49172 #define S_T7_PL_PERR_MC1    14
49173 #define V_T7_PL_PERR_MC1(x) ((x) << S_T7_PL_PERR_MC1)
49174 #define F_T7_PL_PERR_MC1    V_T7_PL_PERR_MC1(1U)
49175 
49176 #define S_T7_PL_PERR_MC0    13
49177 #define V_T7_PL_PERR_MC0(x) ((x) << S_T7_PL_PERR_MC0)
49178 #define F_T7_PL_PERR_MC0    V_T7_PL_PERR_MC0(1U)
49179 
49180 #define S_T7_PL_PERR_PCIE    12
49181 #define V_T7_PL_PERR_PCIE(x) ((x) << S_T7_PL_PERR_PCIE)
49182 #define F_T7_PL_PERR_PCIE    V_T7_PL_PERR_PCIE(1U)
49183 
49184 #define S_T7_PL_PERR_UART    11
49185 #define V_T7_PL_PERR_UART(x) ((x) << S_T7_PL_PERR_UART)
49186 #define F_T7_PL_PERR_UART    V_T7_PL_PERR_UART(1U)
49187 
49188 #define S_T7_PL_PERR_PMU    10
49189 #define V_T7_PL_PERR_PMU(x) ((x) << S_T7_PL_PERR_PMU)
49190 #define F_T7_PL_PERR_PMU    V_T7_PL_PERR_PMU(1U)
49191 
49192 #define S_T7_PL_PERR_MAC    9
49193 #define V_T7_PL_PERR_MAC(x) ((x) << S_T7_PL_PERR_MAC)
49194 #define F_T7_PL_PERR_MAC    V_T7_PL_PERR_MAC(1U)
49195 
49196 #define S_T7_PL_PERR_SMB    8
49197 #define V_T7_PL_PERR_SMB(x) ((x) << S_T7_PL_PERR_SMB)
49198 #define F_T7_PL_PERR_SMB    V_T7_PL_PERR_SMB(1U)
49199 
49200 #define S_T7_PL_PERR_SF    7
49201 #define V_T7_PL_PERR_SF(x) ((x) << S_T7_PL_PERR_SF)
49202 #define F_T7_PL_PERR_SF    V_T7_PL_PERR_SF(1U)
49203 
49204 #define S_T7_PL_PERR_PL    6
49205 #define V_T7_PL_PERR_PL(x) ((x) << S_T7_PL_PERR_PL)
49206 #define F_T7_PL_PERR_PL    V_T7_PL_PERR_PL(1U)
49207 
49208 #define S_T7_PL_PERR_NCSI    5
49209 #define V_T7_PL_PERR_NCSI(x) ((x) << S_T7_PL_PERR_NCSI)
49210 #define F_T7_PL_PERR_NCSI    V_T7_PL_PERR_NCSI(1U)
49211 
49212 #define S_T7_PL_PERR_MPS    4
49213 #define V_T7_PL_PERR_MPS(x) ((x) << S_T7_PL_PERR_MPS)
49214 #define F_T7_PL_PERR_MPS    V_T7_PL_PERR_MPS(1U)
49215 
49216 #define S_T7_PL_PERR_MI    3
49217 #define V_T7_PL_PERR_MI(x) ((x) << S_T7_PL_PERR_MI)
49218 #define F_T7_PL_PERR_MI    V_T7_PL_PERR_MI(1U)
49219 
49220 #define S_T7_PL_PERR_DBG    2
49221 #define V_T7_PL_PERR_DBG(x) ((x) << S_T7_PL_PERR_DBG)
49222 #define F_T7_PL_PERR_DBG    V_T7_PL_PERR_DBG(1U)
49223 
49224 #define S_T7_PL_PERR_I2CM    1
49225 #define V_T7_PL_PERR_I2CM(x) ((x) << S_T7_PL_PERR_I2CM)
49226 #define F_T7_PL_PERR_I2CM    V_T7_PL_PERR_I2CM(1U)
49227 
49228 #define S_T7_PL_PERR_CIM    0
49229 #define V_T7_PL_PERR_CIM(x) ((x) << S_T7_PL_PERR_CIM)
49230 #define F_T7_PL_PERR_CIM    V_T7_PL_PERR_CIM(1U)
49231 
49232 #define A_PL_PERR_ENABLE 0x19408
49233 #define A_PL_INT_CAUSE 0x1940c
49234 
49235 #define S_FLR    30
49236 #define V_FLR(x) ((x) << S_FLR)
49237 #define F_FLR    V_FLR(1U)
49238 
49239 #define S_SW_CIM    29
49240 #define V_SW_CIM(x) ((x) << S_SW_CIM)
49241 #define F_SW_CIM    V_SW_CIM(1U)
49242 
49243 #define S_MAC3    12
49244 #define V_MAC3(x) ((x) << S_MAC3)
49245 #define F_MAC3    V_MAC3(1U)
49246 
49247 #define S_MAC2    11
49248 #define V_MAC2(x) ((x) << S_MAC2)
49249 #define F_MAC2    V_MAC2(1U)
49250 
49251 #define S_MAC1    10
49252 #define V_MAC1(x) ((x) << S_MAC1)
49253 #define F_MAC1    V_MAC1(1U)
49254 
49255 #define S_MAC0    9
49256 #define V_MAC0(x) ((x) << S_MAC0)
49257 #define F_MAC0    V_MAC0(1U)
49258 
49259 #define S_T7_FLR    31
49260 #define V_T7_FLR(x) ((x) << S_T7_FLR)
49261 #define F_T7_FLR    V_T7_FLR(1U)
49262 
49263 #define S_T7_SW_CIM    30
49264 #define V_T7_SW_CIM(x) ((x) << S_T7_SW_CIM)
49265 #define F_T7_SW_CIM    V_T7_SW_CIM(1U)
49266 
49267 #define S_T7_ULP_TX    29
49268 #define V_T7_ULP_TX(x) ((x) << S_T7_ULP_TX)
49269 #define F_T7_ULP_TX    V_T7_ULP_TX(1U)
49270 
49271 #define S_T7_SGE    28
49272 #define V_T7_SGE(x) ((x) << S_T7_SGE)
49273 #define F_T7_SGE    V_T7_SGE(1U)
49274 
49275 #define S_T7_HMA    27
49276 #define V_T7_HMA(x) ((x) << S_T7_HMA)
49277 #define F_T7_HMA    V_T7_HMA(1U)
49278 
49279 #define S_T7_CPL_SWITCH    26
49280 #define V_T7_CPL_SWITCH(x) ((x) << S_T7_CPL_SWITCH)
49281 #define F_T7_CPL_SWITCH    V_T7_CPL_SWITCH(1U)
49282 
49283 #define S_T7_ULP_RX    25
49284 #define V_T7_ULP_RX(x) ((x) << S_T7_ULP_RX)
49285 #define F_T7_ULP_RX    V_T7_ULP_RX(1U)
49286 
49287 #define S_T7_PM_RX    24
49288 #define V_T7_PM_RX(x) ((x) << S_T7_PM_RX)
49289 #define F_T7_PM_RX    V_T7_PM_RX(1U)
49290 
49291 #define S_T7_PM_TX    23
49292 #define V_T7_PM_TX(x) ((x) << S_T7_PM_TX)
49293 #define F_T7_PM_TX    V_T7_PM_TX(1U)
49294 
49295 #define S_T7_MA    22
49296 #define V_T7_MA(x) ((x) << S_T7_MA)
49297 #define F_T7_MA    V_T7_MA(1U)
49298 
49299 #define S_T7_TP    21
49300 #define V_T7_TP(x) ((x) << S_T7_TP)
49301 #define F_T7_TP    V_T7_TP(1U)
49302 
49303 #define S_T7_LE    20
49304 #define V_T7_LE(x) ((x) << S_T7_LE)
49305 #define F_T7_LE    V_T7_LE(1U)
49306 
49307 #define S_T7_EDC1    19
49308 #define V_T7_EDC1(x) ((x) << S_T7_EDC1)
49309 #define F_T7_EDC1    V_T7_EDC1(1U)
49310 
49311 #define S_T7_EDC0    18
49312 #define V_T7_EDC0(x) ((x) << S_T7_EDC0)
49313 #define F_T7_EDC0    V_T7_EDC0(1U)
49314 
49315 #define S_T7_MC1    17
49316 #define V_T7_MC1(x) ((x) << S_T7_MC1)
49317 #define F_T7_MC1    V_T7_MC1(1U)
49318 
49319 #define S_T7_MC0    16
49320 #define V_T7_MC0(x) ((x) << S_T7_MC0)
49321 #define F_T7_MC0    V_T7_MC0(1U)
49322 
49323 #define S_T7_PCIE    15
49324 #define V_T7_PCIE(x) ((x) << S_T7_PCIE)
49325 #define F_T7_PCIE    V_T7_PCIE(1U)
49326 
49327 #define S_T7_UART    14
49328 #define V_T7_UART(x) ((x) << S_T7_UART)
49329 #define F_T7_UART    V_T7_UART(1U)
49330 
49331 #define A_PL_INT_ENABLE 0x19410
49332 #define A_PL_INT_MAP0 0x19414
49333 
49334 #define S_MAPNCSI    16
49335 #define M_MAPNCSI    0x1ffU
49336 #define V_MAPNCSI(x) ((x) << S_MAPNCSI)
49337 #define G_MAPNCSI(x) (((x) >> S_MAPNCSI) & M_MAPNCSI)
49338 
49339 #define S_MAPDEFAULT    0
49340 #define M_MAPDEFAULT    0x1ffU
49341 #define V_MAPDEFAULT(x) ((x) << S_MAPDEFAULT)
49342 #define G_MAPDEFAULT(x) (((x) >> S_MAPDEFAULT) & M_MAPDEFAULT)
49343 
49344 #define A_PL_INT_MAP1 0x19418
49345 
49346 #define S_MAPXGMAC1    16
49347 #define M_MAPXGMAC1    0x1ffU
49348 #define V_MAPXGMAC1(x) ((x) << S_MAPXGMAC1)
49349 #define G_MAPXGMAC1(x) (((x) >> S_MAPXGMAC1) & M_MAPXGMAC1)
49350 
49351 #define S_MAPXGMAC0    0
49352 #define M_MAPXGMAC0    0x1ffU
49353 #define V_MAPXGMAC0(x) ((x) << S_MAPXGMAC0)
49354 #define G_MAPXGMAC0(x) (((x) >> S_MAPXGMAC0) & M_MAPXGMAC0)
49355 
49356 #define S_MAPMAC1    16
49357 #define M_MAPMAC1    0x1ffU
49358 #define V_MAPMAC1(x) ((x) << S_MAPMAC1)
49359 #define G_MAPMAC1(x) (((x) >> S_MAPMAC1) & M_MAPMAC1)
49360 
49361 #define S_MAPMAC0    0
49362 #define M_MAPMAC0    0x1ffU
49363 #define V_MAPMAC0(x) ((x) << S_MAPMAC0)
49364 #define G_MAPMAC0(x) (((x) >> S_MAPMAC0) & M_MAPMAC0)
49365 
49366 #define A_PL_INT_MAP2 0x1941c
49367 
49368 #define S_MAPXGMAC_KR1    16
49369 #define M_MAPXGMAC_KR1    0x1ffU
49370 #define V_MAPXGMAC_KR1(x) ((x) << S_MAPXGMAC_KR1)
49371 #define G_MAPXGMAC_KR1(x) (((x) >> S_MAPXGMAC_KR1) & M_MAPXGMAC_KR1)
49372 
49373 #define S_MAPXGMAC_KR0    0
49374 #define M_MAPXGMAC_KR0    0x1ffU
49375 #define V_MAPXGMAC_KR0(x) ((x) << S_MAPXGMAC_KR0)
49376 #define G_MAPXGMAC_KR0(x) (((x) >> S_MAPXGMAC_KR0) & M_MAPXGMAC_KR0)
49377 
49378 #define S_MAPMAC3    16
49379 #define M_MAPMAC3    0x1ffU
49380 #define V_MAPMAC3(x) ((x) << S_MAPMAC3)
49381 #define G_MAPMAC3(x) (((x) >> S_MAPMAC3) & M_MAPMAC3)
49382 
49383 #define S_MAPMAC2    0
49384 #define M_MAPMAC2    0x1ffU
49385 #define V_MAPMAC2(x) ((x) << S_MAPMAC2)
49386 #define G_MAPMAC2(x) (((x) >> S_MAPMAC2) & M_MAPMAC2)
49387 
49388 #define A_PL_INT_MAP3 0x19420
49389 
49390 #define S_MAPMI    16
49391 #define M_MAPMI    0x1ffU
49392 #define V_MAPMI(x) ((x) << S_MAPMI)
49393 #define G_MAPMI(x) (((x) >> S_MAPMI) & M_MAPMI)
49394 
49395 #define S_MAPSMB    0
49396 #define M_MAPSMB    0x1ffU
49397 #define V_MAPSMB(x) ((x) << S_MAPSMB)
49398 #define G_MAPSMB(x) (((x) >> S_MAPSMB) & M_MAPSMB)
49399 
49400 #define A_PL_INT_MAP4 0x19424
49401 
49402 #define S_MAPDBG    16
49403 #define M_MAPDBG    0x1ffU
49404 #define V_MAPDBG(x) ((x) << S_MAPDBG)
49405 #define G_MAPDBG(x) (((x) >> S_MAPDBG) & M_MAPDBG)
49406 
49407 #define S_MAPI2CM    0
49408 #define M_MAPI2CM    0x1ffU
49409 #define V_MAPI2CM(x) ((x) << S_MAPI2CM)
49410 #define G_MAPI2CM(x) (((x) >> S_MAPI2CM) & M_MAPI2CM)
49411 
49412 #define A_PL_RST 0x19428
49413 
49414 #define S_FATALPERREN    3
49415 #define V_FATALPERREN(x) ((x) << S_FATALPERREN)
49416 #define F_FATALPERREN    V_FATALPERREN(1U)
49417 
49418 #define S_SWINTCIM    2
49419 #define V_SWINTCIM(x) ((x) << S_SWINTCIM)
49420 #define F_SWINTCIM    V_SWINTCIM(1U)
49421 
49422 #define S_PIORST    1
49423 #define V_PIORST(x) ((x) << S_PIORST)
49424 #define F_PIORST    V_PIORST(1U)
49425 
49426 #define S_PIORSTMODE    0
49427 #define V_PIORSTMODE(x) ((x) << S_PIORSTMODE)
49428 #define F_PIORSTMODE    V_PIORSTMODE(1U)
49429 
49430 #define S_AUTOPCIEPAUSE    4
49431 #define V_AUTOPCIEPAUSE(x) ((x) << S_AUTOPCIEPAUSE)
49432 #define F_AUTOPCIEPAUSE    V_AUTOPCIEPAUSE(1U)
49433 
49434 #define A_PL_PL_PERR_INJECT 0x1942c
49435 
49436 #define S_PL_MEMSEL    1
49437 #define V_PL_MEMSEL(x) ((x) << S_PL_MEMSEL)
49438 #define F_PL_MEMSEL    V_PL_MEMSEL(1U)
49439 
49440 #define A_PL_PL_INT_CAUSE 0x19430
49441 
49442 #define S_PF_ENABLEERR    5
49443 #define V_PF_ENABLEERR(x) ((x) << S_PF_ENABLEERR)
49444 #define F_PF_ENABLEERR    V_PF_ENABLEERR(1U)
49445 
49446 #define S_FATALPERR    4
49447 #define V_FATALPERR(x) ((x) << S_FATALPERR)
49448 #define F_FATALPERR    V_FATALPERR(1U)
49449 
49450 #define S_INVALIDACCESS    3
49451 #define V_INVALIDACCESS(x) ((x) << S_INVALIDACCESS)
49452 #define F_INVALIDACCESS    V_INVALIDACCESS(1U)
49453 
49454 #define S_TIMEOUT    2
49455 #define V_TIMEOUT(x) ((x) << S_TIMEOUT)
49456 #define F_TIMEOUT    V_TIMEOUT(1U)
49457 
49458 #define S_PLERR    1
49459 #define V_PLERR(x) ((x) << S_PLERR)
49460 #define F_PLERR    V_PLERR(1U)
49461 
49462 #define S_PERRVFID    0
49463 #define V_PERRVFID(x) ((x) << S_PERRVFID)
49464 #define F_PERRVFID    V_PERRVFID(1U)
49465 
49466 #define S_PL_BUSPERR    6
49467 #define V_PL_BUSPERR(x) ((x) << S_PL_BUSPERR)
49468 #define F_PL_BUSPERR    V_PL_BUSPERR(1U)
49469 
49470 #define A_PL_PL_INT_ENABLE 0x19434
49471 #define A_PL_PL_PERR_ENABLE 0x19438
49472 #define A_PL_REV 0x1943c
49473 
49474 #define S_REV    0
49475 #define M_REV    0xfU
49476 #define V_REV(x) ((x) << S_REV)
49477 #define G_REV(x) (((x) >> S_REV) & M_REV)
49478 
49479 #define A_PL_PCIE_LINK 0x19440
49480 
49481 #define S_LN0_AESTAT    26
49482 #define M_LN0_AESTAT    0x7U
49483 #define V_LN0_AESTAT(x) ((x) << S_LN0_AESTAT)
49484 #define G_LN0_AESTAT(x) (((x) >> S_LN0_AESTAT) & M_LN0_AESTAT)
49485 
49486 #define S_LN0_AECMD    23
49487 #define M_LN0_AECMD    0x7U
49488 #define V_LN0_AECMD(x) ((x) << S_LN0_AECMD)
49489 #define G_LN0_AECMD(x) (((x) >> S_LN0_AECMD) & M_LN0_AECMD)
49490 
49491 #define S_T5_STATECFGINITF    16
49492 #define M_T5_STATECFGINITF    0x7fU
49493 #define V_T5_STATECFGINITF(x) ((x) << S_T5_STATECFGINITF)
49494 #define G_T5_STATECFGINITF(x) (((x) >> S_T5_STATECFGINITF) & M_T5_STATECFGINITF)
49495 
49496 #define S_T5_STATECFGINIT    12
49497 #define M_T5_STATECFGINIT    0xfU
49498 #define V_T5_STATECFGINIT(x) ((x) << S_T5_STATECFGINIT)
49499 #define G_T5_STATECFGINIT(x) (((x) >> S_T5_STATECFGINIT) & M_T5_STATECFGINIT)
49500 
49501 #define S_PCIE_SPEED    8
49502 #define M_PCIE_SPEED    0x3U
49503 #define V_PCIE_SPEED(x) ((x) << S_PCIE_SPEED)
49504 #define G_PCIE_SPEED(x) (((x) >> S_PCIE_SPEED) & M_PCIE_SPEED)
49505 
49506 #define S_T5_PERSTTIMEOUT    7
49507 #define V_T5_PERSTTIMEOUT(x) ((x) << S_T5_PERSTTIMEOUT)
49508 #define F_T5_PERSTTIMEOUT    V_T5_PERSTTIMEOUT(1U)
49509 
49510 #define S_T5_LTSSMENABLE    6
49511 #define V_T5_LTSSMENABLE(x) ((x) << S_T5_LTSSMENABLE)
49512 #define F_T5_LTSSMENABLE    V_T5_LTSSMENABLE(1U)
49513 
49514 #define S_LTSSM    0
49515 #define M_LTSSM    0x3fU
49516 #define V_LTSSM(x) ((x) << S_LTSSM)
49517 #define G_LTSSM(x) (((x) >> S_LTSSM) & M_LTSSM)
49518 
49519 #define S_T6_LN0_AESTAT    27
49520 #define M_T6_LN0_AESTAT    0x7U
49521 #define V_T6_LN0_AESTAT(x) ((x) << S_T6_LN0_AESTAT)
49522 #define G_T6_LN0_AESTAT(x) (((x) >> S_T6_LN0_AESTAT) & M_T6_LN0_AESTAT)
49523 
49524 #define S_T6_LN0_AECMD    24
49525 #define M_T6_LN0_AECMD    0x7U
49526 #define V_T6_LN0_AECMD(x) ((x) << S_T6_LN0_AECMD)
49527 #define G_T6_LN0_AECMD(x) (((x) >> S_T6_LN0_AECMD) & M_T6_LN0_AECMD)
49528 
49529 #define S_T6_1_STATECFGINITF    16
49530 #define M_T6_1_STATECFGINITF    0xffU
49531 #define V_T6_1_STATECFGINITF(x) ((x) << S_T6_1_STATECFGINITF)
49532 #define G_T6_1_STATECFGINITF(x) (((x) >> S_T6_1_STATECFGINITF) & M_T6_1_STATECFGINITF)
49533 
49534 #define S_PHY_STATUS    10
49535 #define V_PHY_STATUS(x) ((x) << S_PHY_STATUS)
49536 #define F_PHY_STATUS    V_PHY_STATUS(1U)
49537 
49538 #define S_SPEED_PL    8
49539 #define M_SPEED_PL    0x3U
49540 #define V_SPEED_PL(x) ((x) << S_SPEED_PL)
49541 #define G_SPEED_PL(x) (((x) >> S_SPEED_PL) & M_SPEED_PL)
49542 
49543 #define S_PERSTTIMEOUT_PL    7
49544 #define V_PERSTTIMEOUT_PL(x) ((x) << S_PERSTTIMEOUT_PL)
49545 #define F_PERSTTIMEOUT_PL    V_PERSTTIMEOUT_PL(1U)
49546 
49547 #define S_SPEEDMS    30
49548 #define V_SPEEDMS(x) ((x) << S_SPEEDMS)
49549 #define F_SPEEDMS    V_SPEEDMS(1U)
49550 
49551 #define A_PL_PCIE_CTL_STAT 0x19444
49552 
49553 #define S_PCIE_STATUS    16
49554 #define M_PCIE_STATUS    0xffffU
49555 #define V_PCIE_STATUS(x) ((x) << S_PCIE_STATUS)
49556 #define G_PCIE_STATUS(x) (((x) >> S_PCIE_STATUS) & M_PCIE_STATUS)
49557 
49558 #define S_PCIE_CONTROL    0
49559 #define M_PCIE_CONTROL    0xffffU
49560 #define V_PCIE_CONTROL(x) ((x) << S_PCIE_CONTROL)
49561 #define G_PCIE_CONTROL(x) (((x) >> S_PCIE_CONTROL) & M_PCIE_CONTROL)
49562 
49563 #define A_PL_SEMAPHORE_CTL 0x1944c
49564 
49565 #define S_LOCKSTATUS    16
49566 #define M_LOCKSTATUS    0xffU
49567 #define V_LOCKSTATUS(x) ((x) << S_LOCKSTATUS)
49568 #define G_LOCKSTATUS(x) (((x) >> S_LOCKSTATUS) & M_LOCKSTATUS)
49569 
49570 #define S_OWNEROVERRIDE    8
49571 #define V_OWNEROVERRIDE(x) ((x) << S_OWNEROVERRIDE)
49572 #define F_OWNEROVERRIDE    V_OWNEROVERRIDE(1U)
49573 
49574 #define S_ENABLEPF    0
49575 #define M_ENABLEPF    0xffU
49576 #define V_ENABLEPF(x) ((x) << S_ENABLEPF)
49577 #define G_ENABLEPF(x) (((x) >> S_ENABLEPF) & M_ENABLEPF)
49578 
49579 #define A_PL_SEMAPHORE_LOCK 0x19450
49580 
49581 #define S_SEMLOCK    31
49582 #define V_SEMLOCK(x) ((x) << S_SEMLOCK)
49583 #define F_SEMLOCK    V_SEMLOCK(1U)
49584 
49585 #define S_SEMSRCBUS    3
49586 #define M_SEMSRCBUS    0x3U
49587 #define V_SEMSRCBUS(x) ((x) << S_SEMSRCBUS)
49588 #define G_SEMSRCBUS(x) (((x) >> S_SEMSRCBUS) & M_SEMSRCBUS)
49589 
49590 #define S_SEMSRCPF    0
49591 #define M_SEMSRCPF    0x7U
49592 #define V_SEMSRCPF(x) ((x) << S_SEMSRCPF)
49593 #define G_SEMSRCPF(x) (((x) >> S_SEMSRCPF) & M_SEMSRCPF)
49594 
49595 #define A_PL_PF_ENABLE 0x19470
49596 
49597 #define S_PF_ENABLE    0
49598 #define M_PF_ENABLE    0xffU
49599 #define V_PF_ENABLE(x) ((x) << S_PF_ENABLE)
49600 #define G_PF_ENABLE(x) (((x) >> S_PF_ENABLE) & M_PF_ENABLE)
49601 
49602 #define A_PL_PORTX_MAP 0x19474
49603 
49604 #define S_MAP7    28
49605 #define M_MAP7    0x7U
49606 #define V_MAP7(x) ((x) << S_MAP7)
49607 #define G_MAP7(x) (((x) >> S_MAP7) & M_MAP7)
49608 
49609 #define S_MAP6    24
49610 #define M_MAP6    0x7U
49611 #define V_MAP6(x) ((x) << S_MAP6)
49612 #define G_MAP6(x) (((x) >> S_MAP6) & M_MAP6)
49613 
49614 #define S_MAP5    20
49615 #define M_MAP5    0x7U
49616 #define V_MAP5(x) ((x) << S_MAP5)
49617 #define G_MAP5(x) (((x) >> S_MAP5) & M_MAP5)
49618 
49619 #define S_MAP4    16
49620 #define M_MAP4    0x7U
49621 #define V_MAP4(x) ((x) << S_MAP4)
49622 #define G_MAP4(x) (((x) >> S_MAP4) & M_MAP4)
49623 
49624 #define S_MAP3    12
49625 #define M_MAP3    0x7U
49626 #define V_MAP3(x) ((x) << S_MAP3)
49627 #define G_MAP3(x) (((x) >> S_MAP3) & M_MAP3)
49628 
49629 #define S_MAP2    8
49630 #define M_MAP2    0x7U
49631 #define V_MAP2(x) ((x) << S_MAP2)
49632 #define G_MAP2(x) (((x) >> S_MAP2) & M_MAP2)
49633 
49634 #define S_MAP1    4
49635 #define M_MAP1    0x7U
49636 #define V_MAP1(x) ((x) << S_MAP1)
49637 #define G_MAP1(x) (((x) >> S_MAP1) & M_MAP1)
49638 
49639 #define S_MAP0    0
49640 #define M_MAP0    0x7U
49641 #define V_MAP0(x) ((x) << S_MAP0)
49642 #define G_MAP0(x) (((x) >> S_MAP0) & M_MAP0)
49643 
49644 #define A_PL_INT_CAUSE2 0x19478
49645 
49646 #define S_CRYPTO_KEY    4
49647 #define V_CRYPTO_KEY(x) ((x) << S_CRYPTO_KEY)
49648 #define F_CRYPTO_KEY    V_CRYPTO_KEY(1U)
49649 
49650 #define S_CRYPTO1    3
49651 #define V_CRYPTO1(x) ((x) << S_CRYPTO1)
49652 #define F_CRYPTO1    V_CRYPTO1(1U)
49653 
49654 #define S_CRYPTO0    2
49655 #define V_CRYPTO0(x) ((x) << S_CRYPTO0)
49656 #define F_CRYPTO0    V_CRYPTO0(1U)
49657 
49658 #define S_GCACHE    1
49659 #define V_GCACHE(x) ((x) << S_GCACHE)
49660 #define F_GCACHE    V_GCACHE(1U)
49661 
49662 #define S_ARM    0
49663 #define V_ARM(x) ((x) << S_ARM)
49664 #define F_ARM    V_ARM(1U)
49665 
49666 #define A_PL_INT_ENABLE2 0x1947c
49667 #define A_PL_ER_CMD 0x19488
49668 
49669 #define S_ER_ADDR    2
49670 #define M_ER_ADDR    0x3fffffffU
49671 #define V_ER_ADDR(x) ((x) << S_ER_ADDR)
49672 #define G_ER_ADDR(x) (((x) >> S_ER_ADDR) & M_ER_ADDR)
49673 
49674 #define A_PL_ER_DATA 0x1948c
49675 #define A_PL_VF_SLICE_L 0x19490
49676 
49677 #define S_LIMITADDR    16
49678 #define M_LIMITADDR    0x3ffU
49679 #define V_LIMITADDR(x) ((x) << S_LIMITADDR)
49680 #define G_LIMITADDR(x) (((x) >> S_LIMITADDR) & M_LIMITADDR)
49681 
49682 #define S_SLICEBASEADDR    0
49683 #define M_SLICEBASEADDR    0x3ffU
49684 #define V_SLICEBASEADDR(x) ((x) << S_SLICEBASEADDR)
49685 #define G_SLICEBASEADDR(x) (((x) >> S_SLICEBASEADDR) & M_SLICEBASEADDR)
49686 
49687 #define A_PL_VF_SLICE_H 0x19494
49688 
49689 #define S_MODINDX    16
49690 #define M_MODINDX    0x7U
49691 #define V_MODINDX(x) ((x) << S_MODINDX)
49692 #define G_MODINDX(x) (((x) >> S_MODINDX) & M_MODINDX)
49693 
49694 #define S_MODOFFSET    0
49695 #define M_MODOFFSET    0x3ffU
49696 #define V_MODOFFSET(x) ((x) << S_MODOFFSET)
49697 #define G_MODOFFSET(x) (((x) >> S_MODOFFSET) & M_MODOFFSET)
49698 
49699 #define A_PL_FLR_VF_STATUS 0x194d0
49700 #define A_PL_FLR_PF_STATUS 0x194e0
49701 
49702 #define S_FLR_PF    0
49703 #define M_FLR_PF    0xffU
49704 #define V_FLR_PF(x) ((x) << S_FLR_PF)
49705 #define G_FLR_PF(x) (((x) >> S_FLR_PF) & M_FLR_PF)
49706 
49707 #define A_PL_TIMEOUT_CTL 0x194f0
49708 
49709 #define S_PL_TIMEOUT    0
49710 #define M_PL_TIMEOUT    0xffffU
49711 #define V_PL_TIMEOUT(x) ((x) << S_PL_TIMEOUT)
49712 #define G_PL_TIMEOUT(x) (((x) >> S_PL_TIMEOUT) & M_PL_TIMEOUT)
49713 
49714 #define S_PERRCAPTURE    16
49715 #define V_PERRCAPTURE(x) ((x) << S_PERRCAPTURE)
49716 #define F_PERRCAPTURE    V_PERRCAPTURE(1U)
49717 
49718 #define A_PL_TIMEOUT_STATUS0 0x194f4
49719 
49720 #define S_PL_TOADDR    2
49721 #define M_PL_TOADDR    0xfffffffU
49722 #define V_PL_TOADDR(x) ((x) << S_PL_TOADDR)
49723 #define G_PL_TOADDR(x) (((x) >> S_PL_TOADDR) & M_PL_TOADDR)
49724 
49725 #define A_PL_TIMEOUT_STATUS1 0x194f8
49726 
49727 #define S_PL_TOVALID    31
49728 #define V_PL_TOVALID(x) ((x) << S_PL_TOVALID)
49729 #define F_PL_TOVALID    V_PL_TOVALID(1U)
49730 
49731 #define S_WRITE    22
49732 #define V_WRITE(x) ((x) << S_WRITE)
49733 #define F_WRITE    V_WRITE(1U)
49734 
49735 #define S_PL_TOBUS    20
49736 #define M_PL_TOBUS    0x3U
49737 #define V_PL_TOBUS(x) ((x) << S_PL_TOBUS)
49738 #define G_PL_TOBUS(x) (((x) >> S_PL_TOBUS) & M_PL_TOBUS)
49739 
49740 #define S_RGN    19
49741 #define V_RGN(x) ((x) << S_RGN)
49742 #define F_RGN    V_RGN(1U)
49743 
49744 #define S_PL_TOPF    16
49745 #define M_PL_TOPF    0x7U
49746 #define V_PL_TOPF(x) ((x) << S_PL_TOPF)
49747 #define G_PL_TOPF(x) (((x) >> S_PL_TOPF) & M_PL_TOPF)
49748 
49749 #define S_PL_TORID    0
49750 #define M_PL_TORID    0xffffU
49751 #define V_PL_TORID(x) ((x) << S_PL_TORID)
49752 #define G_PL_TORID(x) (((x) >> S_PL_TORID) & M_PL_TORID)
49753 
49754 #define S_VALIDPERR    30
49755 #define V_VALIDPERR(x) ((x) << S_VALIDPERR)
49756 #define F_VALIDPERR    V_VALIDPERR(1U)
49757 
49758 #define S_PL_TOVFID    0
49759 #define M_PL_TOVFID    0xffU
49760 #define V_PL_TOVFID(x) ((x) << S_PL_TOVFID)
49761 #define G_PL_TOVFID(x) (((x) >> S_PL_TOVFID) & M_PL_TOVFID)
49762 
49763 #define S_T6_PL_TOVFID    0
49764 #define M_T6_PL_TOVFID    0x1ffU
49765 #define V_T6_PL_TOVFID(x) ((x) << S_T6_PL_TOVFID)
49766 #define G_T6_PL_TOVFID(x) (((x) >> S_T6_PL_TOVFID) & M_T6_PL_TOVFID)
49767 
49768 #define A_PL_VFID_MAP 0x19800
49769 
49770 #define S_VFID_VLD    7
49771 #define V_VFID_VLD(x) ((x) << S_VFID_VLD)
49772 #define F_VFID_VLD    V_VFID_VLD(1U)
49773 
49774 /* registers for module LE */
49775 #define LE_BASE_ADDR 0x19c00
49776 
49777 #define A_LE_BUF_CONFIG 0x19c00
49778 #define A_LE_DB_ID 0x19c00
49779 #define A_LE_DB_CONFIG 0x19c04
49780 
49781 #define S_TCAMCMDOVLAPEN    21
49782 #define V_TCAMCMDOVLAPEN(x) ((x) << S_TCAMCMDOVLAPEN)
49783 #define F_TCAMCMDOVLAPEN    V_TCAMCMDOVLAPEN(1U)
49784 
49785 #define S_HASHEN    20
49786 #define V_HASHEN(x) ((x) << S_HASHEN)
49787 #define F_HASHEN    V_HASHEN(1U)
49788 
49789 #define S_ASBOTHSRCHEN    18
49790 #define V_ASBOTHSRCHEN(x) ((x) << S_ASBOTHSRCHEN)
49791 #define F_ASBOTHSRCHEN    V_ASBOTHSRCHEN(1U)
49792 
49793 #define S_ASLIPCOMPEN    17
49794 #define V_ASLIPCOMPEN(x) ((x) << S_ASLIPCOMPEN)
49795 #define F_ASLIPCOMPEN    V_ASLIPCOMPEN(1U)
49796 
49797 #define S_BUILD    16
49798 #define V_BUILD(x) ((x) << S_BUILD)
49799 #define F_BUILD    V_BUILD(1U)
49800 
49801 #define S_FILTEREN    11
49802 #define V_FILTEREN(x) ((x) << S_FILTEREN)
49803 #define F_FILTEREN    V_FILTEREN(1U)
49804 
49805 #define S_SYNMODE    7
49806 #define M_SYNMODE    0x3U
49807 #define V_SYNMODE(x) ((x) << S_SYNMODE)
49808 #define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE)
49809 
49810 #define S_LEBUSEN    5
49811 #define V_LEBUSEN(x) ((x) << S_LEBUSEN)
49812 #define F_LEBUSEN    V_LEBUSEN(1U)
49813 
49814 #define S_ELOOKDUMEN    4
49815 #define V_ELOOKDUMEN(x) ((x) << S_ELOOKDUMEN)
49816 #define F_ELOOKDUMEN    V_ELOOKDUMEN(1U)
49817 
49818 #define S_IPV4ONLYEN    3
49819 #define V_IPV4ONLYEN(x) ((x) << S_IPV4ONLYEN)
49820 #define F_IPV4ONLYEN    V_IPV4ONLYEN(1U)
49821 
49822 #define S_MOSTCMDOEN    2
49823 #define V_MOSTCMDOEN(x) ((x) << S_MOSTCMDOEN)
49824 #define F_MOSTCMDOEN    V_MOSTCMDOEN(1U)
49825 
49826 #define S_DELACTSYNOEN    1
49827 #define V_DELACTSYNOEN(x) ((x) << S_DELACTSYNOEN)
49828 #define F_DELACTSYNOEN    V_DELACTSYNOEN(1U)
49829 
49830 #define S_CMDOVERLAPDIS    0
49831 #define V_CMDOVERLAPDIS(x) ((x) << S_CMDOVERLAPDIS)
49832 #define F_CMDOVERLAPDIS    V_CMDOVERLAPDIS(1U)
49833 
49834 #define S_MASKCMDOLAPDIS    26
49835 #define V_MASKCMDOLAPDIS(x) ((x) << S_MASKCMDOLAPDIS)
49836 #define F_MASKCMDOLAPDIS    V_MASKCMDOLAPDIS(1U)
49837 
49838 #define S_IPV4HASHSIZEEN    25
49839 #define V_IPV4HASHSIZEEN(x) ((x) << S_IPV4HASHSIZEEN)
49840 #define F_IPV4HASHSIZEEN    V_IPV4HASHSIZEEN(1U)
49841 
49842 #define S_PROTOCOLMASKEN    24
49843 #define V_PROTOCOLMASKEN(x) ((x) << S_PROTOCOLMASKEN)
49844 #define F_PROTOCOLMASKEN    V_PROTOCOLMASKEN(1U)
49845 
49846 #define S_TUPLESIZEEN    23
49847 #define V_TUPLESIZEEN(x) ((x) << S_TUPLESIZEEN)
49848 #define F_TUPLESIZEEN    V_TUPLESIZEEN(1U)
49849 
49850 #define S_SRVRSRAMEN    22
49851 #define V_SRVRSRAMEN(x) ((x) << S_SRVRSRAMEN)
49852 #define F_SRVRSRAMEN    V_SRVRSRAMEN(1U)
49853 
49854 #define S_ASBOTHSRCHENPR    19
49855 #define V_ASBOTHSRCHENPR(x) ((x) << S_ASBOTHSRCHENPR)
49856 #define F_ASBOTHSRCHENPR    V_ASBOTHSRCHENPR(1U)
49857 
49858 #define S_POCLIPTID0    15
49859 #define V_POCLIPTID0(x) ((x) << S_POCLIPTID0)
49860 #define F_POCLIPTID0    V_POCLIPTID0(1U)
49861 
49862 #define S_TCAMARBOFF    14
49863 #define V_TCAMARBOFF(x) ((x) << S_TCAMARBOFF)
49864 #define F_TCAMARBOFF    V_TCAMARBOFF(1U)
49865 
49866 #define S_ACCNTFULLEN    13
49867 #define V_ACCNTFULLEN(x) ((x) << S_ACCNTFULLEN)
49868 #define F_ACCNTFULLEN    V_ACCNTFULLEN(1U)
49869 
49870 #define S_FILTERRWNOCLIP    12
49871 #define V_FILTERRWNOCLIP(x) ((x) << S_FILTERRWNOCLIP)
49872 #define F_FILTERRWNOCLIP    V_FILTERRWNOCLIP(1U)
49873 
49874 #define S_CRCHASH    10
49875 #define V_CRCHASH(x) ((x) << S_CRCHASH)
49876 #define F_CRCHASH    V_CRCHASH(1U)
49877 
49878 #define S_COMPTID    9
49879 #define V_COMPTID(x) ((x) << S_COMPTID)
49880 #define F_COMPTID    V_COMPTID(1U)
49881 
49882 #define S_SINGLETHREAD    6
49883 #define V_SINGLETHREAD(x) ((x) << S_SINGLETHREAD)
49884 #define F_SINGLETHREAD    V_SINGLETHREAD(1U)
49885 
49886 #define S_CHK_FUL_TUP_ZERO    27
49887 #define V_CHK_FUL_TUP_ZERO(x) ((x) << S_CHK_FUL_TUP_ZERO)
49888 #define F_CHK_FUL_TUP_ZERO    V_CHK_FUL_TUP_ZERO(1U)
49889 
49890 #define S_PRI_HASH    26
49891 #define V_PRI_HASH(x) ((x) << S_PRI_HASH)
49892 #define F_PRI_HASH    V_PRI_HASH(1U)
49893 
49894 #define S_EXTN_HASH_IPV4    25
49895 #define V_EXTN_HASH_IPV4(x) ((x) << S_EXTN_HASH_IPV4)
49896 #define F_EXTN_HASH_IPV4    V_EXTN_HASH_IPV4(1U)
49897 
49898 #define S_ASLIPCOMPEN_IPV4    18
49899 #define V_ASLIPCOMPEN_IPV4(x) ((x) << S_ASLIPCOMPEN_IPV4)
49900 #define F_ASLIPCOMPEN_IPV4    V_ASLIPCOMPEN_IPV4(1U)
49901 
49902 #define S_IGNR_TUP_ZERO    9
49903 #define V_IGNR_TUP_ZERO(x) ((x) << S_IGNR_TUP_ZERO)
49904 #define F_IGNR_TUP_ZERO    V_IGNR_TUP_ZERO(1U)
49905 
49906 #define S_IGNR_LIP_ZERO    8
49907 #define V_IGNR_LIP_ZERO(x) ((x) << S_IGNR_LIP_ZERO)
49908 #define F_IGNR_LIP_ZERO    V_IGNR_LIP_ZERO(1U)
49909 
49910 #define S_CLCAM_INIT_BUSY    7
49911 #define V_CLCAM_INIT_BUSY(x) ((x) << S_CLCAM_INIT_BUSY)
49912 #define F_CLCAM_INIT_BUSY    V_CLCAM_INIT_BUSY(1U)
49913 
49914 #define S_CLCAM_INIT    6
49915 #define V_CLCAM_INIT(x) ((x) << S_CLCAM_INIT)
49916 #define F_CLCAM_INIT    V_CLCAM_INIT(1U)
49917 
49918 #define S_MTCAM_INIT_BUSY    5
49919 #define V_MTCAM_INIT_BUSY(x) ((x) << S_MTCAM_INIT_BUSY)
49920 #define F_MTCAM_INIT_BUSY    V_MTCAM_INIT_BUSY(1U)
49921 
49922 #define S_MTCAM_INIT    4
49923 #define V_MTCAM_INIT(x) ((x) << S_MTCAM_INIT)
49924 #define F_MTCAM_INIT    V_MTCAM_INIT(1U)
49925 
49926 #define S_REGION_EN    0
49927 #define M_REGION_EN    0xfU
49928 #define V_REGION_EN(x) ((x) << S_REGION_EN)
49929 #define G_REGION_EN(x) (((x) >> S_REGION_EN) & M_REGION_EN)
49930 
49931 #define S_CACHEBYPASS    28
49932 #define V_CACHEBYPASS(x) ((x) << S_CACHEBYPASS)
49933 #define F_CACHEBYPASS    V_CACHEBYPASS(1U)
49934 
49935 #define A_LE_MISC 0x19c08
49936 
49937 #define S_CMPUNVAIL    0
49938 #define M_CMPUNVAIL    0xfU
49939 #define V_CMPUNVAIL(x) ((x) << S_CMPUNVAIL)
49940 #define G_CMPUNVAIL(x) (((x) >> S_CMPUNVAIL) & M_CMPUNVAIL)
49941 
49942 #define S_SRAMDEEPSLEEP_STAT    11
49943 #define V_SRAMDEEPSLEEP_STAT(x) ((x) << S_SRAMDEEPSLEEP_STAT)
49944 #define F_SRAMDEEPSLEEP_STAT    V_SRAMDEEPSLEEP_STAT(1U)
49945 
49946 #define S_TCAMDEEPSLEEP1_STAT    10
49947 #define V_TCAMDEEPSLEEP1_STAT(x) ((x) << S_TCAMDEEPSLEEP1_STAT)
49948 #define F_TCAMDEEPSLEEP1_STAT    V_TCAMDEEPSLEEP1_STAT(1U)
49949 
49950 #define S_TCAMDEEPSLEEP0_STAT    9
49951 #define V_TCAMDEEPSLEEP0_STAT(x) ((x) << S_TCAMDEEPSLEEP0_STAT)
49952 #define F_TCAMDEEPSLEEP0_STAT    V_TCAMDEEPSLEEP0_STAT(1U)
49953 
49954 #define S_SRAMDEEPSLEEP    8
49955 #define V_SRAMDEEPSLEEP(x) ((x) << S_SRAMDEEPSLEEP)
49956 #define F_SRAMDEEPSLEEP    V_SRAMDEEPSLEEP(1U)
49957 
49958 #define S_TCAMDEEPSLEEP1    7
49959 #define V_TCAMDEEPSLEEP1(x) ((x) << S_TCAMDEEPSLEEP1)
49960 #define F_TCAMDEEPSLEEP1    V_TCAMDEEPSLEEP1(1U)
49961 
49962 #define S_TCAMDEEPSLEEP0    6
49963 #define V_TCAMDEEPSLEEP0(x) ((x) << S_TCAMDEEPSLEEP0)
49964 #define F_TCAMDEEPSLEEP0    V_TCAMDEEPSLEEP0(1U)
49965 
49966 #define S_SRVRAMCLKOFF    5
49967 #define V_SRVRAMCLKOFF(x) ((x) << S_SRVRAMCLKOFF)
49968 #define F_SRVRAMCLKOFF    V_SRVRAMCLKOFF(1U)
49969 
49970 #define S_HASHCLKOFF    4
49971 #define V_HASHCLKOFF(x) ((x) << S_HASHCLKOFF)
49972 #define F_HASHCLKOFF    V_HASHCLKOFF(1U)
49973 
49974 #define A_LE_DB_EXEC_CTRL 0x19c08
49975 
49976 #define S_TPDB_IF_PAUSE_ACK    10
49977 #define V_TPDB_IF_PAUSE_ACK(x) ((x) << S_TPDB_IF_PAUSE_ACK)
49978 #define F_TPDB_IF_PAUSE_ACK    V_TPDB_IF_PAUSE_ACK(1U)
49979 
49980 #define S_TPDB_IF_PAUSE_REQ    9
49981 #define V_TPDB_IF_PAUSE_REQ(x) ((x) << S_TPDB_IF_PAUSE_REQ)
49982 #define F_TPDB_IF_PAUSE_REQ    V_TPDB_IF_PAUSE_REQ(1U)
49983 
49984 #define S_ERRSTOP_EN    8
49985 #define V_ERRSTOP_EN(x) ((x) << S_ERRSTOP_EN)
49986 #define F_ERRSTOP_EN    V_ERRSTOP_EN(1U)
49987 
49988 #define S_CMDLIMIT    0
49989 #define M_CMDLIMIT    0xffU
49990 #define V_CMDLIMIT(x) ((x) << S_CMDLIMIT)
49991 #define G_CMDLIMIT(x) (((x) >> S_CMDLIMIT) & M_CMDLIMIT)
49992 
49993 #define A_LE_DB_PS_CTRL 0x19c0c
49994 
49995 #define S_CLTCAMDEEPSLEEP_STAT    10
49996 #define V_CLTCAMDEEPSLEEP_STAT(x) ((x) << S_CLTCAMDEEPSLEEP_STAT)
49997 #define F_CLTCAMDEEPSLEEP_STAT    V_CLTCAMDEEPSLEEP_STAT(1U)
49998 
49999 #define S_TCAMDEEPSLEEP_STAT    9
50000 #define V_TCAMDEEPSLEEP_STAT(x) ((x) << S_TCAMDEEPSLEEP_STAT)
50001 #define F_TCAMDEEPSLEEP_STAT    V_TCAMDEEPSLEEP_STAT(1U)
50002 
50003 #define S_CLTCAMDEEPSLEEP    7
50004 #define V_CLTCAMDEEPSLEEP(x) ((x) << S_CLTCAMDEEPSLEEP)
50005 #define F_CLTCAMDEEPSLEEP    V_CLTCAMDEEPSLEEP(1U)
50006 
50007 #define S_TCAMDEEPSLEEP    6
50008 #define V_TCAMDEEPSLEEP(x) ((x) << S_TCAMDEEPSLEEP)
50009 #define F_TCAMDEEPSLEEP    V_TCAMDEEPSLEEP(1U)
50010 
50011 #define A_LE_DB_ROUTING_TABLE_INDEX 0x19c10
50012 
50013 #define S_RTINDX    7
50014 #define M_RTINDX    0x3fU
50015 #define V_RTINDX(x) ((x) << S_RTINDX)
50016 #define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX)
50017 
50018 #define A_LE_DB_ACTIVE_TABLE_START_INDEX 0x19c10
50019 
50020 #define S_ATINDX    0
50021 #define M_ATINDX    0xfffffU
50022 #define V_ATINDX(x) ((x) << S_ATINDX)
50023 #define G_ATINDX(x) (((x) >> S_ATINDX) & M_ATINDX)
50024 
50025 #define A_LE_DB_FILTER_TABLE_INDEX 0x19c14
50026 
50027 #define S_FTINDX    7
50028 #define M_FTINDX    0x3fU
50029 #define V_FTINDX(x) ((x) << S_FTINDX)
50030 #define G_FTINDX(x) (((x) >> S_FTINDX) & M_FTINDX)
50031 
50032 #define A_LE_DB_NORM_FILT_TABLE_START_INDEX 0x19c14
50033 
50034 #define S_NFTINDX    0
50035 #define M_NFTINDX    0xfffffU
50036 #define V_NFTINDX(x) ((x) << S_NFTINDX)
50037 #define G_NFTINDX(x) (((x) >> S_NFTINDX) & M_NFTINDX)
50038 
50039 #define A_LE_DB_SERVER_INDEX 0x19c18
50040 
50041 #define S_SRINDX    7
50042 #define M_SRINDX    0x3fU
50043 #define V_SRINDX(x) ((x) << S_SRINDX)
50044 #define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX)
50045 
50046 #define A_LE_DB_SRVR_START_INDEX 0x19c18
50047 
50048 #define S_T6_SRINDX    0
50049 #define M_T6_SRINDX    0xfffffU
50050 #define V_T6_SRINDX(x) ((x) << S_T6_SRINDX)
50051 #define G_T6_SRINDX(x) (((x) >> S_T6_SRINDX) & M_T6_SRINDX)
50052 
50053 #define A_LE_DB_CLIP_TABLE_INDEX 0x19c1c
50054 
50055 #define S_CLIPTINDX    7
50056 #define M_CLIPTINDX    0x3fU
50057 #define V_CLIPTINDX(x) ((x) << S_CLIPTINDX)
50058 #define G_CLIPTINDX(x) (((x) >> S_CLIPTINDX) & M_CLIPTINDX)
50059 
50060 #define A_LE_DB_HPRI_FILT_TABLE_START_INDEX 0x19c1c
50061 
50062 #define S_HFTINDX    0
50063 #define M_HFTINDX    0xfffffU
50064 #define V_HFTINDX(x) ((x) << S_HFTINDX)
50065 #define G_HFTINDX(x) (((x) >> S_HFTINDX) & M_HFTINDX)
50066 
50067 #define A_LE_DB_ACT_CNT_IPV4 0x19c20
50068 
50069 #define S_ACTCNTIPV4    0
50070 #define M_ACTCNTIPV4    0xfffffU
50071 #define V_ACTCNTIPV4(x) ((x) << S_ACTCNTIPV4)
50072 #define G_ACTCNTIPV4(x) (((x) >> S_ACTCNTIPV4) & M_ACTCNTIPV4)
50073 
50074 #define A_LE_DB_ACT_CNT_IPV6 0x19c24
50075 
50076 #define S_ACTCNTIPV6    0
50077 #define M_ACTCNTIPV6    0xfffffU
50078 #define V_ACTCNTIPV6(x) ((x) << S_ACTCNTIPV6)
50079 #define G_ACTCNTIPV6(x) (((x) >> S_ACTCNTIPV6) & M_ACTCNTIPV6)
50080 
50081 #define A_LE_DB_HASH_CONFIG 0x19c28
50082 
50083 #define S_HASHTIDSIZE    16
50084 #define M_HASHTIDSIZE    0x3fU
50085 #define V_HASHTIDSIZE(x) ((x) << S_HASHTIDSIZE)
50086 #define G_HASHTIDSIZE(x) (((x) >> S_HASHTIDSIZE) & M_HASHTIDSIZE)
50087 
50088 #define S_HASHSIZE    0
50089 #define M_HASHSIZE    0x3fU
50090 #define V_HASHSIZE(x) ((x) << S_HASHSIZE)
50091 #define G_HASHSIZE(x) (((x) >> S_HASHSIZE) & M_HASHSIZE)
50092 
50093 #define S_NUMHASHBKT    20
50094 #define M_NUMHASHBKT    0x1fU
50095 #define V_NUMHASHBKT(x) ((x) << S_NUMHASHBKT)
50096 #define G_NUMHASHBKT(x) (((x) >> S_NUMHASHBKT) & M_NUMHASHBKT)
50097 
50098 #define S_HASHTBLSIZE    3
50099 #define M_HASHTBLSIZE    0x1ffffU
50100 #define V_HASHTBLSIZE(x) ((x) << S_HASHTBLSIZE)
50101 #define G_HASHTBLSIZE(x) (((x) >> S_HASHTBLSIZE) & M_HASHTBLSIZE)
50102 
50103 #define A_LE_DB_HASH_TABLE_BASE 0x19c2c
50104 #define A_LE_DB_MIN_NUM_ACTV_TCAM_ENTRIES 0x19c2c
50105 
50106 #define S_MIN_ATCAM_ENTS    0
50107 #define M_MIN_ATCAM_ENTS    0xfffffU
50108 #define V_MIN_ATCAM_ENTS(x) ((x) << S_MIN_ATCAM_ENTS)
50109 #define G_MIN_ATCAM_ENTS(x) (((x) >> S_MIN_ATCAM_ENTS) & M_MIN_ATCAM_ENTS)
50110 
50111 #define A_LE_DB_HASH_TID_BASE 0x19c30
50112 #define A_LE_DB_HASH_TBL_BASE_ADDR 0x19c30
50113 
50114 #define S_HASHTBLADDR    4
50115 #define M_HASHTBLADDR    0xfffffffU
50116 #define V_HASHTBLADDR(x) ((x) << S_HASHTBLADDR)
50117 #define G_HASHTBLADDR(x) (((x) >> S_HASHTBLADDR) & M_HASHTBLADDR)
50118 
50119 #define A_LE_DB_SIZE 0x19c34
50120 #define A_LE_TCAM_SIZE 0x19c34
50121 
50122 #define S_TCAM_SIZE    0
50123 #define M_TCAM_SIZE    0x3U
50124 #define V_TCAM_SIZE(x) ((x) << S_TCAM_SIZE)
50125 #define G_TCAM_SIZE(x) (((x) >> S_TCAM_SIZE) & M_TCAM_SIZE)
50126 
50127 #define S_MLL_MASK    2
50128 #define V_MLL_MASK(x) ((x) << S_MLL_MASK)
50129 #define F_MLL_MASK    V_MLL_MASK(1U)
50130 
50131 #define A_LE_DB_INT_ENABLE 0x19c38
50132 
50133 #define S_MSGSEL    27
50134 #define M_MSGSEL    0x1fU
50135 #define V_MSGSEL(x) ((x) << S_MSGSEL)
50136 #define G_MSGSEL(x) (((x) >> S_MSGSEL) & M_MSGSEL)
50137 
50138 #define S_REQQPARERR    16
50139 #define V_REQQPARERR(x) ((x) << S_REQQPARERR)
50140 #define F_REQQPARERR    V_REQQPARERR(1U)
50141 
50142 #define S_UNKNOWNCMD    15
50143 #define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
50144 #define F_UNKNOWNCMD    V_UNKNOWNCMD(1U)
50145 
50146 #define S_DROPFILTERHIT    13
50147 #define V_DROPFILTERHIT(x) ((x) << S_DROPFILTERHIT)
50148 #define F_DROPFILTERHIT    V_DROPFILTERHIT(1U)
50149 
50150 #define S_FILTERHIT    12
50151 #define V_FILTERHIT(x) ((x) << S_FILTERHIT)
50152 #define F_FILTERHIT    V_FILTERHIT(1U)
50153 
50154 #define S_SYNCOOKIEOFF    11
50155 #define V_SYNCOOKIEOFF(x) ((x) << S_SYNCOOKIEOFF)
50156 #define F_SYNCOOKIEOFF    V_SYNCOOKIEOFF(1U)
50157 
50158 #define S_SYNCOOKIEBAD    10
50159 #define V_SYNCOOKIEBAD(x) ((x) << S_SYNCOOKIEBAD)
50160 #define F_SYNCOOKIEBAD    V_SYNCOOKIEBAD(1U)
50161 
50162 #define S_SYNCOOKIE    9
50163 #define V_SYNCOOKIE(x) ((x) << S_SYNCOOKIE)
50164 #define F_SYNCOOKIE    V_SYNCOOKIE(1U)
50165 
50166 #define S_NFASRCHFAIL    8
50167 #define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
50168 #define F_NFASRCHFAIL    V_NFASRCHFAIL(1U)
50169 
50170 #define S_ACTRGNFULL    7
50171 #define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
50172 #define F_ACTRGNFULL    V_ACTRGNFULL(1U)
50173 
50174 #define S_PARITYERR    6
50175 #define V_PARITYERR(x) ((x) << S_PARITYERR)
50176 #define F_PARITYERR    V_PARITYERR(1U)
50177 
50178 #define S_LIPMISS    5
50179 #define V_LIPMISS(x) ((x) << S_LIPMISS)
50180 #define F_LIPMISS    V_LIPMISS(1U)
50181 
50182 #define S_LIP0    4
50183 #define V_LIP0(x) ((x) << S_LIP0)
50184 #define F_LIP0    V_LIP0(1U)
50185 
50186 #define S_MISS    3
50187 #define V_MISS(x) ((x) << S_MISS)
50188 #define F_MISS    V_MISS(1U)
50189 
50190 #define S_ROUTINGHIT    2
50191 #define V_ROUTINGHIT(x) ((x) << S_ROUTINGHIT)
50192 #define F_ROUTINGHIT    V_ROUTINGHIT(1U)
50193 
50194 #define S_ACTIVEHIT    1
50195 #define V_ACTIVEHIT(x) ((x) << S_ACTIVEHIT)
50196 #define F_ACTIVEHIT    V_ACTIVEHIT(1U)
50197 
50198 #define S_SERVERHIT    0
50199 #define V_SERVERHIT(x) ((x) << S_SERVERHIT)
50200 #define F_SERVERHIT    V_SERVERHIT(1U)
50201 
50202 #define S_ACTCNTIPV6TZERO    21
50203 #define V_ACTCNTIPV6TZERO(x) ((x) << S_ACTCNTIPV6TZERO)
50204 #define F_ACTCNTIPV6TZERO    V_ACTCNTIPV6TZERO(1U)
50205 
50206 #define S_ACTCNTIPV4TZERO    20
50207 #define V_ACTCNTIPV4TZERO(x) ((x) << S_ACTCNTIPV4TZERO)
50208 #define F_ACTCNTIPV4TZERO    V_ACTCNTIPV4TZERO(1U)
50209 
50210 #define S_ACTCNTIPV6ZERO    19
50211 #define V_ACTCNTIPV6ZERO(x) ((x) << S_ACTCNTIPV6ZERO)
50212 #define F_ACTCNTIPV6ZERO    V_ACTCNTIPV6ZERO(1U)
50213 
50214 #define S_ACTCNTIPV4ZERO    18
50215 #define V_ACTCNTIPV4ZERO(x) ((x) << S_ACTCNTIPV4ZERO)
50216 #define F_ACTCNTIPV4ZERO    V_ACTCNTIPV4ZERO(1U)
50217 
50218 #define S_MARSPPARERR    17
50219 #define V_MARSPPARERR(x) ((x) << S_MARSPPARERR)
50220 #define F_MARSPPARERR    V_MARSPPARERR(1U)
50221 
50222 #define S_VFPARERR    14
50223 #define V_VFPARERR(x) ((x) << S_VFPARERR)
50224 #define F_VFPARERR    V_VFPARERR(1U)
50225 
50226 #define S_CLIPSUBERR    29
50227 #define V_CLIPSUBERR(x) ((x) << S_CLIPSUBERR)
50228 #define F_CLIPSUBERR    V_CLIPSUBERR(1U)
50229 
50230 #define S_CLCAMFIFOERR    28
50231 #define V_CLCAMFIFOERR(x) ((x) << S_CLCAMFIFOERR)
50232 #define F_CLCAMFIFOERR    V_CLCAMFIFOERR(1U)
50233 
50234 #define S_HASHTBLMEMCRCERR    27
50235 #define V_HASHTBLMEMCRCERR(x) ((x) << S_HASHTBLMEMCRCERR)
50236 #define F_HASHTBLMEMCRCERR    V_HASHTBLMEMCRCERR(1U)
50237 
50238 #define S_CTCAMINVLDENT    26
50239 #define V_CTCAMINVLDENT(x) ((x) << S_CTCAMINVLDENT)
50240 #define F_CTCAMINVLDENT    V_CTCAMINVLDENT(1U)
50241 
50242 #define S_TCAMINVLDENT    25
50243 #define V_TCAMINVLDENT(x) ((x) << S_TCAMINVLDENT)
50244 #define F_TCAMINVLDENT    V_TCAMINVLDENT(1U)
50245 
50246 #define S_TOTCNTERR    24
50247 #define V_TOTCNTERR(x) ((x) << S_TOTCNTERR)
50248 #define F_TOTCNTERR    V_TOTCNTERR(1U)
50249 
50250 #define S_CMDPRSRINTERR    23
50251 #define V_CMDPRSRINTERR(x) ((x) << S_CMDPRSRINTERR)
50252 #define F_CMDPRSRINTERR    V_CMDPRSRINTERR(1U)
50253 
50254 #define S_CMDTIDERR    22
50255 #define V_CMDTIDERR(x) ((x) << S_CMDTIDERR)
50256 #define F_CMDTIDERR    V_CMDTIDERR(1U)
50257 
50258 #define S_T6_ACTRGNFULL    21
50259 #define V_T6_ACTRGNFULL(x) ((x) << S_T6_ACTRGNFULL)
50260 #define F_T6_ACTRGNFULL    V_T6_ACTRGNFULL(1U)
50261 
50262 #define S_T6_ACTCNTIPV6TZERO    20
50263 #define V_T6_ACTCNTIPV6TZERO(x) ((x) << S_T6_ACTCNTIPV6TZERO)
50264 #define F_T6_ACTCNTIPV6TZERO    V_T6_ACTCNTIPV6TZERO(1U)
50265 
50266 #define S_T6_ACTCNTIPV4TZERO    19
50267 #define V_T6_ACTCNTIPV4TZERO(x) ((x) << S_T6_ACTCNTIPV4TZERO)
50268 #define F_T6_ACTCNTIPV4TZERO    V_T6_ACTCNTIPV4TZERO(1U)
50269 
50270 #define S_T6_ACTCNTIPV6ZERO    18
50271 #define V_T6_ACTCNTIPV6ZERO(x) ((x) << S_T6_ACTCNTIPV6ZERO)
50272 #define F_T6_ACTCNTIPV6ZERO    V_T6_ACTCNTIPV6ZERO(1U)
50273 
50274 #define S_T6_ACTCNTIPV4ZERO    17
50275 #define V_T6_ACTCNTIPV4ZERO(x) ((x) << S_T6_ACTCNTIPV4ZERO)
50276 #define F_T6_ACTCNTIPV4ZERO    V_T6_ACTCNTIPV4ZERO(1U)
50277 
50278 #define S_MAIFWRINTPERR    16
50279 #define V_MAIFWRINTPERR(x) ((x) << S_MAIFWRINTPERR)
50280 #define F_MAIFWRINTPERR    V_MAIFWRINTPERR(1U)
50281 
50282 #define S_HASHTBLMEMACCERR    15
50283 #define V_HASHTBLMEMACCERR(x) ((x) << S_HASHTBLMEMACCERR)
50284 #define F_HASHTBLMEMACCERR    V_HASHTBLMEMACCERR(1U)
50285 
50286 #define S_TCAMCRCERR    14
50287 #define V_TCAMCRCERR(x) ((x) << S_TCAMCRCERR)
50288 #define F_TCAMCRCERR    V_TCAMCRCERR(1U)
50289 
50290 #define S_TCAMINTPERR    13
50291 #define V_TCAMINTPERR(x) ((x) << S_TCAMINTPERR)
50292 #define F_TCAMINTPERR    V_TCAMINTPERR(1U)
50293 
50294 #define S_VFSRAMPERR    12
50295 #define V_VFSRAMPERR(x) ((x) << S_VFSRAMPERR)
50296 #define F_VFSRAMPERR    V_VFSRAMPERR(1U)
50297 
50298 #define S_SRVSRAMPERR    11
50299 #define V_SRVSRAMPERR(x) ((x) << S_SRVSRAMPERR)
50300 #define F_SRVSRAMPERR    V_SRVSRAMPERR(1U)
50301 
50302 #define S_SSRAMINTPERR    10
50303 #define V_SSRAMINTPERR(x) ((x) << S_SSRAMINTPERR)
50304 #define F_SSRAMINTPERR    V_SSRAMINTPERR(1U)
50305 
50306 #define S_CLCAMINTPERR    9
50307 #define V_CLCAMINTPERR(x) ((x) << S_CLCAMINTPERR)
50308 #define F_CLCAMINTPERR    V_CLCAMINTPERR(1U)
50309 
50310 #define S_CLCAMCRCPARERR    8
50311 #define V_CLCAMCRCPARERR(x) ((x) << S_CLCAMCRCPARERR)
50312 #define F_CLCAMCRCPARERR    V_CLCAMCRCPARERR(1U)
50313 
50314 #define S_HASHTBLACCFAIL    7
50315 #define V_HASHTBLACCFAIL(x) ((x) << S_HASHTBLACCFAIL)
50316 #define F_HASHTBLACCFAIL    V_HASHTBLACCFAIL(1U)
50317 
50318 #define S_TCAMACCFAIL    6
50319 #define V_TCAMACCFAIL(x) ((x) << S_TCAMACCFAIL)
50320 #define F_TCAMACCFAIL    V_TCAMACCFAIL(1U)
50321 
50322 #define S_SRVSRAMACCFAIL    5
50323 #define V_SRVSRAMACCFAIL(x) ((x) << S_SRVSRAMACCFAIL)
50324 #define F_SRVSRAMACCFAIL    V_SRVSRAMACCFAIL(1U)
50325 
50326 #define S_CLIPTCAMACCFAIL    4
50327 #define V_CLIPTCAMACCFAIL(x) ((x) << S_CLIPTCAMACCFAIL)
50328 #define F_CLIPTCAMACCFAIL    V_CLIPTCAMACCFAIL(1U)
50329 
50330 #define S_T6_UNKNOWNCMD    3
50331 #define V_T6_UNKNOWNCMD(x) ((x) << S_T6_UNKNOWNCMD)
50332 #define F_T6_UNKNOWNCMD    V_T6_UNKNOWNCMD(1U)
50333 
50334 #define S_T6_LIP0    2
50335 #define V_T6_LIP0(x) ((x) << S_T6_LIP0)
50336 #define F_T6_LIP0    V_T6_LIP0(1U)
50337 
50338 #define S_T6_LIPMISS    1
50339 #define V_T6_LIPMISS(x) ((x) << S_T6_LIPMISS)
50340 #define F_T6_LIPMISS    V_T6_LIPMISS(1U)
50341 
50342 #define S_PIPELINEERR    0
50343 #define V_PIPELINEERR(x) ((x) << S_PIPELINEERR)
50344 #define F_PIPELINEERR    V_PIPELINEERR(1U)
50345 
50346 #define S_CACHEINTPERR    31
50347 #define V_CACHEINTPERR(x) ((x) << S_CACHEINTPERR)
50348 #define F_CACHEINTPERR    V_CACHEINTPERR(1U)
50349 
50350 #define S_CACHESRAMPERR    30
50351 #define V_CACHESRAMPERR(x) ((x) << S_CACHESRAMPERR)
50352 #define F_CACHESRAMPERR    V_CACHESRAMPERR(1U)
50353 
50354 #define A_LE_DB_INT_CAUSE 0x19c3c
50355 #define A_LE_DB_INT_TID 0x19c40
50356 
50357 #define S_INTTID    0
50358 #define M_INTTID    0xfffffU
50359 #define V_INTTID(x) ((x) << S_INTTID)
50360 #define G_INTTID(x) (((x) >> S_INTTID) & M_INTTID)
50361 
50362 #define A_LE_DB_DBG_MATCH_CMD_IDX_MASK 0x19c40
50363 
50364 #define S_CMD_CMP_MASK    20
50365 #define M_CMD_CMP_MASK    0x1fU
50366 #define V_CMD_CMP_MASK(x) ((x) << S_CMD_CMP_MASK)
50367 #define G_CMD_CMP_MASK(x) (((x) >> S_CMD_CMP_MASK) & M_CMD_CMP_MASK)
50368 
50369 #define S_TID_CMP_MASK    0
50370 #define M_TID_CMP_MASK    0xfffffU
50371 #define V_TID_CMP_MASK(x) ((x) << S_TID_CMP_MASK)
50372 #define G_TID_CMP_MASK(x) (((x) >> S_TID_CMP_MASK) & M_TID_CMP_MASK)
50373 
50374 #define A_LE_DB_INT_PTID 0x19c44
50375 
50376 #define S_INTPTID    0
50377 #define M_INTPTID    0xfffffU
50378 #define V_INTPTID(x) ((x) << S_INTPTID)
50379 #define G_INTPTID(x) (((x) >> S_INTPTID) & M_INTPTID)
50380 
50381 #define A_LE_DB_DBG_MATCH_CMD_IDX_DATA 0x19c44
50382 
50383 #define S_CMD_CMP    20
50384 #define M_CMD_CMP    0x1fU
50385 #define V_CMD_CMP(x) ((x) << S_CMD_CMP)
50386 #define G_CMD_CMP(x) (((x) >> S_CMD_CMP) & M_CMD_CMP)
50387 
50388 #define S_TID_CMP    0
50389 #define M_TID_CMP    0xfffffU
50390 #define V_TID_CMP(x) ((x) << S_TID_CMP)
50391 #define G_TID_CMP(x) (((x) >> S_TID_CMP) & M_TID_CMP)
50392 
50393 #define A_LE_DB_INT_INDEX 0x19c48
50394 
50395 #define S_INTINDEX    0
50396 #define M_INTINDEX    0xfffffU
50397 #define V_INTINDEX(x) ((x) << S_INTINDEX)
50398 #define G_INTINDEX(x) (((x) >> S_INTINDEX) & M_INTINDEX)
50399 
50400 #define A_LE_DB_ERR_CMD_TID 0x19c48
50401 
50402 #define S_ERR_CID    22
50403 #define M_ERR_CID    0xffU
50404 #define V_ERR_CID(x) ((x) << S_ERR_CID)
50405 #define G_ERR_CID(x) (((x) >> S_ERR_CID) & M_ERR_CID)
50406 
50407 #define S_ERR_PROT    20
50408 #define M_ERR_PROT    0x3U
50409 #define V_ERR_PROT(x) ((x) << S_ERR_PROT)
50410 #define G_ERR_PROT(x) (((x) >> S_ERR_PROT) & M_ERR_PROT)
50411 
50412 #define S_ERR_TID    0
50413 #define M_ERR_TID    0xfffffU
50414 #define V_ERR_TID(x) ((x) << S_ERR_TID)
50415 #define G_ERR_TID(x) (((x) >> S_ERR_TID) & M_ERR_TID)
50416 
50417 #define A_LE_DB_INT_CMD 0x19c4c
50418 
50419 #define S_INTCMD    0
50420 #define M_INTCMD    0xfU
50421 #define V_INTCMD(x) ((x) << S_INTCMD)
50422 #define G_INTCMD(x) (((x) >> S_INTCMD) & M_INTCMD)
50423 
50424 #define A_LE_DB_MASK_IPV4 0x19c50
50425 #define A_LE_T5_DB_MASK_IPV4 0x19c50
50426 #define A_LE_DB_DBG_MATCH_DATA_MASK 0x19c50
50427 #define A_LE_DB_MAX_NUM_HASH_ENTRIES 0x19c70
50428 
50429 #define S_MAX_HASH_ENTS    0
50430 #define M_MAX_HASH_ENTS    0xfffffU
50431 #define V_MAX_HASH_ENTS(x) ((x) << S_MAX_HASH_ENTS)
50432 #define G_MAX_HASH_ENTS(x) (((x) >> S_MAX_HASH_ENTS) & M_MAX_HASH_ENTS)
50433 
50434 #define A_LE_DB_RSP_CODE_0 0x19c74
50435 
50436 #define S_SUCCESS    25
50437 #define M_SUCCESS    0x1fU
50438 #define V_SUCCESS(x) ((x) << S_SUCCESS)
50439 #define G_SUCCESS(x) (((x) >> S_SUCCESS) & M_SUCCESS)
50440 
50441 #define S_TCAM_ACTV_SUCC    20
50442 #define M_TCAM_ACTV_SUCC    0x1fU
50443 #define V_TCAM_ACTV_SUCC(x) ((x) << S_TCAM_ACTV_SUCC)
50444 #define G_TCAM_ACTV_SUCC(x) (((x) >> S_TCAM_ACTV_SUCC) & M_TCAM_ACTV_SUCC)
50445 
50446 #define S_HASH_ACTV_SUCC    15
50447 #define M_HASH_ACTV_SUCC    0x1fU
50448 #define V_HASH_ACTV_SUCC(x) ((x) << S_HASH_ACTV_SUCC)
50449 #define G_HASH_ACTV_SUCC(x) (((x) >> S_HASH_ACTV_SUCC) & M_HASH_ACTV_SUCC)
50450 
50451 #define S_TCAM_SRVR_HIT    10
50452 #define M_TCAM_SRVR_HIT    0x1fU
50453 #define V_TCAM_SRVR_HIT(x) ((x) << S_TCAM_SRVR_HIT)
50454 #define G_TCAM_SRVR_HIT(x) (((x) >> S_TCAM_SRVR_HIT) & M_TCAM_SRVR_HIT)
50455 
50456 #define S_SRAM_SRVR_HIT    5
50457 #define M_SRAM_SRVR_HIT    0x1fU
50458 #define V_SRAM_SRVR_HIT(x) ((x) << S_SRAM_SRVR_HIT)
50459 #define G_SRAM_SRVR_HIT(x) (((x) >> S_SRAM_SRVR_HIT) & M_SRAM_SRVR_HIT)
50460 
50461 #define S_TCAM_ACTV_HIT    0
50462 #define M_TCAM_ACTV_HIT    0x1fU
50463 #define V_TCAM_ACTV_HIT(x) ((x) << S_TCAM_ACTV_HIT)
50464 #define G_TCAM_ACTV_HIT(x) (((x) >> S_TCAM_ACTV_HIT) & M_TCAM_ACTV_HIT)
50465 
50466 #define A_LE_DB_RSP_CODE_1 0x19c78
50467 
50468 #define S_HASH_ACTV_HIT    25
50469 #define M_HASH_ACTV_HIT    0x1fU
50470 #define V_HASH_ACTV_HIT(x) ((x) << S_HASH_ACTV_HIT)
50471 #define G_HASH_ACTV_HIT(x) (((x) >> S_HASH_ACTV_HIT) & M_HASH_ACTV_HIT)
50472 
50473 #define S_T6_MISS    20
50474 #define M_T6_MISS    0x1fU
50475 #define V_T6_MISS(x) ((x) << S_T6_MISS)
50476 #define G_T6_MISS(x) (((x) >> S_T6_MISS) & M_T6_MISS)
50477 
50478 #define S_NORM_FILT_HIT    15
50479 #define M_NORM_FILT_HIT    0x1fU
50480 #define V_NORM_FILT_HIT(x) ((x) << S_NORM_FILT_HIT)
50481 #define G_NORM_FILT_HIT(x) (((x) >> S_NORM_FILT_HIT) & M_NORM_FILT_HIT)
50482 
50483 #define S_HPRI_FILT_HIT    10
50484 #define M_HPRI_FILT_HIT    0x1fU
50485 #define V_HPRI_FILT_HIT(x) ((x) << S_HPRI_FILT_HIT)
50486 #define G_HPRI_FILT_HIT(x) (((x) >> S_HPRI_FILT_HIT) & M_HPRI_FILT_HIT)
50487 
50488 #define S_ACTV_OPEN_ERR    5
50489 #define M_ACTV_OPEN_ERR    0x1fU
50490 #define V_ACTV_OPEN_ERR(x) ((x) << S_ACTV_OPEN_ERR)
50491 #define G_ACTV_OPEN_ERR(x) (((x) >> S_ACTV_OPEN_ERR) & M_ACTV_OPEN_ERR)
50492 
50493 #define S_ACTV_FULL_ERR    0
50494 #define M_ACTV_FULL_ERR    0x1fU
50495 #define V_ACTV_FULL_ERR(x) ((x) << S_ACTV_FULL_ERR)
50496 #define G_ACTV_FULL_ERR(x) (((x) >> S_ACTV_FULL_ERR) & M_ACTV_FULL_ERR)
50497 
50498 #define A_LE_DB_RSP_CODE_2 0x19c7c
50499 
50500 #define S_SRCH_RGN_HIT    25
50501 #define M_SRCH_RGN_HIT    0x1fU
50502 #define V_SRCH_RGN_HIT(x) ((x) << S_SRCH_RGN_HIT)
50503 #define G_SRCH_RGN_HIT(x) (((x) >> S_SRCH_RGN_HIT) & M_SRCH_RGN_HIT)
50504 
50505 #define S_CLIP_FAIL    20
50506 #define M_CLIP_FAIL    0x1fU
50507 #define V_CLIP_FAIL(x) ((x) << S_CLIP_FAIL)
50508 #define G_CLIP_FAIL(x) (((x) >> S_CLIP_FAIL) & M_CLIP_FAIL)
50509 
50510 #define S_LIP_ZERO_ERR    15
50511 #define M_LIP_ZERO_ERR    0x1fU
50512 #define V_LIP_ZERO_ERR(x) ((x) << S_LIP_ZERO_ERR)
50513 #define G_LIP_ZERO_ERR(x) (((x) >> S_LIP_ZERO_ERR) & M_LIP_ZERO_ERR)
50514 
50515 #define S_UNKNOWN_CMD    10
50516 #define M_UNKNOWN_CMD    0x1fU
50517 #define V_UNKNOWN_CMD(x) ((x) << S_UNKNOWN_CMD)
50518 #define G_UNKNOWN_CMD(x) (((x) >> S_UNKNOWN_CMD) & M_UNKNOWN_CMD)
50519 
50520 #define S_CMD_TID_ERR    5
50521 #define M_CMD_TID_ERR    0x1fU
50522 #define V_CMD_TID_ERR(x) ((x) << S_CMD_TID_ERR)
50523 #define G_CMD_TID_ERR(x) (((x) >> S_CMD_TID_ERR) & M_CMD_TID_ERR)
50524 
50525 #define S_INTERNAL_ERR    0
50526 #define M_INTERNAL_ERR    0x1fU
50527 #define V_INTERNAL_ERR(x) ((x) << S_INTERNAL_ERR)
50528 #define G_INTERNAL_ERR(x) (((x) >> S_INTERNAL_ERR) & M_INTERNAL_ERR)
50529 
50530 #define A_LE_DB_RSP_CODE_3 0x19c80
50531 
50532 #define S_SRAM_SRVR_HIT_ACTF    25
50533 #define M_SRAM_SRVR_HIT_ACTF    0x1fU
50534 #define V_SRAM_SRVR_HIT_ACTF(x) ((x) << S_SRAM_SRVR_HIT_ACTF)
50535 #define G_SRAM_SRVR_HIT_ACTF(x) (((x) >> S_SRAM_SRVR_HIT_ACTF) & M_SRAM_SRVR_HIT_ACTF)
50536 
50537 #define S_TCAM_SRVR_HIT_ACTF    20
50538 #define M_TCAM_SRVR_HIT_ACTF    0x1fU
50539 #define V_TCAM_SRVR_HIT_ACTF(x) ((x) << S_TCAM_SRVR_HIT_ACTF)
50540 #define G_TCAM_SRVR_HIT_ACTF(x) (((x) >> S_TCAM_SRVR_HIT_ACTF) & M_TCAM_SRVR_HIT_ACTF)
50541 
50542 #define S_INVLDRD    15
50543 #define M_INVLDRD    0x1fU
50544 #define V_INVLDRD(x) ((x) << S_INVLDRD)
50545 #define G_INVLDRD(x) (((x) >> S_INVLDRD) & M_INVLDRD)
50546 
50547 #define S_TUPLZERO    10
50548 #define M_TUPLZERO    0x1fU
50549 #define V_TUPLZERO(x) ((x) << S_TUPLZERO)
50550 #define G_TUPLZERO(x) (((x) >> S_TUPLZERO) & M_TUPLZERO)
50551 
50552 #define A_LE_DB_ACT_CNT_IPV4_TCAM 0x19c94
50553 #define A_LE_DB_ACT_CNT_IPV6_TCAM 0x19c98
50554 #define A_LE_ACT_CNT_THRSH 0x19c9c
50555 
50556 #define S_ACT_CNT_THRSH    0
50557 #define M_ACT_CNT_THRSH    0x1fffffU
50558 #define V_ACT_CNT_THRSH(x) ((x) << S_ACT_CNT_THRSH)
50559 #define G_ACT_CNT_THRSH(x) (((x) >> S_ACT_CNT_THRSH) & M_ACT_CNT_THRSH)
50560 
50561 #define A_LE_DB_MASK_IPV6 0x19ca0
50562 #define A_LE_DB_DBG_MATCH_DATA 0x19ca0
50563 #define A_LE_CMM_CONFIG 0x19cc0
50564 #define A_LE_CACHE_DBG 0x19cc4
50565 #define A_LE_CACHE_WR_ALL_CNT 0x19cc8
50566 #define A_LE_CACHE_WR_HIT_CNT 0x19ccc
50567 #define A_LE_CACHE_RD_ALL_CNT 0x19cd0
50568 #define A_LE_CACHE_RD_HIT_CNT 0x19cd4
50569 #define A_LE_CACHE_MC_WR_CNT 0x19cd8
50570 #define A_LE_CACHE_MC_RD_CNT 0x19cdc
50571 #define A_LE_DB_REQ_RSP_CNT 0x19ce4
50572 
50573 #define S_T4_RSPCNT    16
50574 #define M_T4_RSPCNT    0xffffU
50575 #define V_T4_RSPCNT(x) ((x) << S_T4_RSPCNT)
50576 #define G_T4_RSPCNT(x) (((x) >> S_T4_RSPCNT) & M_T4_RSPCNT)
50577 
50578 #define S_T4_REQCNT    0
50579 #define M_T4_REQCNT    0xffffU
50580 #define V_T4_REQCNT(x) ((x) << S_T4_REQCNT)
50581 #define G_T4_REQCNT(x) (((x) >> S_T4_REQCNT) & M_T4_REQCNT)
50582 
50583 #define S_RSPCNTLE    16
50584 #define M_RSPCNTLE    0xffffU
50585 #define V_RSPCNTLE(x) ((x) << S_RSPCNTLE)
50586 #define G_RSPCNTLE(x) (((x) >> S_RSPCNTLE) & M_RSPCNTLE)
50587 
50588 #define S_REQCNTLE    0
50589 #define M_REQCNTLE    0xffffU
50590 #define V_REQCNTLE(x) ((x) << S_REQCNTLE)
50591 #define G_REQCNTLE(x) (((x) >> S_REQCNTLE) & M_REQCNTLE)
50592 
50593 #define A_LE_IND_ADDR 0x19ce8
50594 
50595 #define S_T7_1_ADDR    0
50596 #define M_T7_1_ADDR    0xffU
50597 #define V_T7_1_ADDR(x) ((x) << S_T7_1_ADDR)
50598 #define G_T7_1_ADDR(x) (((x) >> S_T7_1_ADDR) & M_T7_1_ADDR)
50599 
50600 #define A_LE_IND_DATA 0x19cec
50601 #define A_LE_DB_DBGI_CONFIG 0x19cf0
50602 
50603 #define S_DBGICMDPERR    31
50604 #define V_DBGICMDPERR(x) ((x) << S_DBGICMDPERR)
50605 #define F_DBGICMDPERR    V_DBGICMDPERR(1U)
50606 
50607 #define S_DBGICMDRANGE    22
50608 #define M_DBGICMDRANGE    0x7U
50609 #define V_DBGICMDRANGE(x) ((x) << S_DBGICMDRANGE)
50610 #define G_DBGICMDRANGE(x) (((x) >> S_DBGICMDRANGE) & M_DBGICMDRANGE)
50611 
50612 #define S_DBGICMDMSKTYPE    21
50613 #define V_DBGICMDMSKTYPE(x) ((x) << S_DBGICMDMSKTYPE)
50614 #define F_DBGICMDMSKTYPE    V_DBGICMDMSKTYPE(1U)
50615 
50616 #define S_DBGICMDSEARCH    20
50617 #define V_DBGICMDSEARCH(x) ((x) << S_DBGICMDSEARCH)
50618 #define F_DBGICMDSEARCH    V_DBGICMDSEARCH(1U)
50619 
50620 #define S_DBGICMDREAD    19
50621 #define V_DBGICMDREAD(x) ((x) << S_DBGICMDREAD)
50622 #define F_DBGICMDREAD    V_DBGICMDREAD(1U)
50623 
50624 #define S_DBGICMDLEARN    18
50625 #define V_DBGICMDLEARN(x) ((x) << S_DBGICMDLEARN)
50626 #define F_DBGICMDLEARN    V_DBGICMDLEARN(1U)
50627 
50628 #define S_DBGICMDERASE    17
50629 #define V_DBGICMDERASE(x) ((x) << S_DBGICMDERASE)
50630 #define F_DBGICMDERASE    V_DBGICMDERASE(1U)
50631 
50632 #define S_DBGICMDIPV6    16
50633 #define V_DBGICMDIPV6(x) ((x) << S_DBGICMDIPV6)
50634 #define F_DBGICMDIPV6    V_DBGICMDIPV6(1U)
50635 
50636 #define S_DBGICMDTYPE    13
50637 #define M_DBGICMDTYPE    0x7U
50638 #define V_DBGICMDTYPE(x) ((x) << S_DBGICMDTYPE)
50639 #define G_DBGICMDTYPE(x) (((x) >> S_DBGICMDTYPE) & M_DBGICMDTYPE)
50640 
50641 #define S_DBGICMDACKERR    12
50642 #define V_DBGICMDACKERR(x) ((x) << S_DBGICMDACKERR)
50643 #define F_DBGICMDACKERR    V_DBGICMDACKERR(1U)
50644 
50645 #define S_DBGICMDBUSY    3
50646 #define V_DBGICMDBUSY(x) ((x) << S_DBGICMDBUSY)
50647 #define F_DBGICMDBUSY    V_DBGICMDBUSY(1U)
50648 
50649 #define S_DBGICMDSTRT    2
50650 #define V_DBGICMDSTRT(x) ((x) << S_DBGICMDSTRT)
50651 #define F_DBGICMDSTRT    V_DBGICMDSTRT(1U)
50652 
50653 #define S_DBGICMDMODE    0
50654 #define M_DBGICMDMODE    0x3U
50655 #define V_DBGICMDMODE(x) ((x) << S_DBGICMDMODE)
50656 #define G_DBGICMDMODE(x) (((x) >> S_DBGICMDMODE) & M_DBGICMDMODE)
50657 
50658 #define S_DBGICMDMSKREAD    21
50659 #define V_DBGICMDMSKREAD(x) ((x) << S_DBGICMDMSKREAD)
50660 #define F_DBGICMDMSKREAD    V_DBGICMDMSKREAD(1U)
50661 
50662 #define S_DBGICMDWRITE    17
50663 #define V_DBGICMDWRITE(x) ((x) << S_DBGICMDWRITE)
50664 #define F_DBGICMDWRITE    V_DBGICMDWRITE(1U)
50665 
50666 #define A_LE_DB_DBGI_REQ_TCAM_CMD 0x19cf4
50667 
50668 #define S_DBGICMD    20
50669 #define M_DBGICMD    0xfU
50670 #define V_DBGICMD(x) ((x) << S_DBGICMD)
50671 #define G_DBGICMD(x) (((x) >> S_DBGICMD) & M_DBGICMD)
50672 
50673 #define S_DBGITINDEX    0
50674 #define M_DBGITINDEX    0xfffffU
50675 #define V_DBGITINDEX(x) ((x) << S_DBGITINDEX)
50676 #define G_DBGITINDEX(x) (((x) >> S_DBGITINDEX) & M_DBGITINDEX)
50677 
50678 #define A_LE_DB_DBGI_REQ_CMD 0x19cf4
50679 
50680 #define S_DBGITID    0
50681 #define M_DBGITID    0xfffffU
50682 #define V_DBGITID(x) ((x) << S_DBGITID)
50683 #define G_DBGITID(x) (((x) >> S_DBGITID) & M_DBGITID)
50684 
50685 #define A_LE_PERR_ENABLE 0x19cf8
50686 
50687 #define S_REQQUEUE    1
50688 #define V_REQQUEUE(x) ((x) << S_REQQUEUE)
50689 #define F_REQQUEUE    V_REQQUEUE(1U)
50690 
50691 #define S_TCAM    0
50692 #define V_TCAM(x) ((x) << S_TCAM)
50693 #define F_TCAM    V_TCAM(1U)
50694 
50695 #define S_MARSPPARERRLE    17
50696 #define V_MARSPPARERRLE(x) ((x) << S_MARSPPARERRLE)
50697 #define F_MARSPPARERRLE    V_MARSPPARERRLE(1U)
50698 
50699 #define S_REQQUEUELE    16
50700 #define V_REQQUEUELE(x) ((x) << S_REQQUEUELE)
50701 #define F_REQQUEUELE    V_REQQUEUELE(1U)
50702 
50703 #define S_VFPARERRLE    14
50704 #define V_VFPARERRLE(x) ((x) << S_VFPARERRLE)
50705 #define F_VFPARERRLE    V_VFPARERRLE(1U)
50706 
50707 #define S_TCAMLE    6
50708 #define V_TCAMLE(x) ((x) << S_TCAMLE)
50709 #define F_TCAMLE    V_TCAMLE(1U)
50710 
50711 #define S_BKCHKPERIOD    22
50712 #define M_BKCHKPERIOD    0x3ffU
50713 #define V_BKCHKPERIOD(x) ((x) << S_BKCHKPERIOD)
50714 #define G_BKCHKPERIOD(x) (((x) >> S_BKCHKPERIOD) & M_BKCHKPERIOD)
50715 
50716 #define S_TCAMBKCHKEN    21
50717 #define V_TCAMBKCHKEN(x) ((x) << S_TCAMBKCHKEN)
50718 #define F_TCAMBKCHKEN    V_TCAMBKCHKEN(1U)
50719 
50720 #define S_T6_CLCAMFIFOERR    2
50721 #define V_T6_CLCAMFIFOERR(x) ((x) << S_T6_CLCAMFIFOERR)
50722 #define F_T6_CLCAMFIFOERR    V_T6_CLCAMFIFOERR(1U)
50723 
50724 #define S_T6_HASHTBLMEMCRCERR    1
50725 #define V_T6_HASHTBLMEMCRCERR(x) ((x) << S_T6_HASHTBLMEMCRCERR)
50726 #define F_T6_HASHTBLMEMCRCERR    V_T6_HASHTBLMEMCRCERR(1U)
50727 
50728 #define S_T7_BKCHKPERIOD    22
50729 #define M_T7_BKCHKPERIOD    0xffU
50730 #define V_T7_BKCHKPERIOD(x) ((x) << S_T7_BKCHKPERIOD)
50731 #define G_T7_BKCHKPERIOD(x) (((x) >> S_T7_BKCHKPERIOD) & M_T7_BKCHKPERIOD)
50732 
50733 #define A_LE_SPARE 0x19cfc
50734 #define A_LE_DB_DBGI_REQ_DATA 0x19d00
50735 #define A_LE_DB_DBGI_REQ_MASK 0x19d50
50736 #define A_LE_DB_DBGI_RSP_STATUS 0x19d94
50737 
50738 #define S_DBGIRSPINDEX    12
50739 #define M_DBGIRSPINDEX    0xfffffU
50740 #define V_DBGIRSPINDEX(x) ((x) << S_DBGIRSPINDEX)
50741 #define G_DBGIRSPINDEX(x) (((x) >> S_DBGIRSPINDEX) & M_DBGIRSPINDEX)
50742 
50743 #define S_DBGIRSPMSG    8
50744 #define M_DBGIRSPMSG    0xfU
50745 #define V_DBGIRSPMSG(x) ((x) << S_DBGIRSPMSG)
50746 #define G_DBGIRSPMSG(x) (((x) >> S_DBGIRSPMSG) & M_DBGIRSPMSG)
50747 
50748 #define S_DBGIRSPMSGVLD    7
50749 #define V_DBGIRSPMSGVLD(x) ((x) << S_DBGIRSPMSGVLD)
50750 #define F_DBGIRSPMSGVLD    V_DBGIRSPMSGVLD(1U)
50751 
50752 #define S_DBGIRSPMHIT    2
50753 #define V_DBGIRSPMHIT(x) ((x) << S_DBGIRSPMHIT)
50754 #define F_DBGIRSPMHIT    V_DBGIRSPMHIT(1U)
50755 
50756 #define S_DBGIRSPHIT    1
50757 #define V_DBGIRSPHIT(x) ((x) << S_DBGIRSPHIT)
50758 #define F_DBGIRSPHIT    V_DBGIRSPHIT(1U)
50759 
50760 #define S_DBGIRSPVALID    0
50761 #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
50762 #define F_DBGIRSPVALID    V_DBGIRSPVALID(1U)
50763 
50764 #define S_DBGIRSPTID    12
50765 #define M_DBGIRSPTID    0xfffffU
50766 #define V_DBGIRSPTID(x) ((x) << S_DBGIRSPTID)
50767 #define G_DBGIRSPTID(x) (((x) >> S_DBGIRSPTID) & M_DBGIRSPTID)
50768 
50769 #define S_DBGIRSPLEARN    2
50770 #define V_DBGIRSPLEARN(x) ((x) << S_DBGIRSPLEARN)
50771 #define F_DBGIRSPLEARN    V_DBGIRSPLEARN(1U)
50772 
50773 #define A_LE_DBG_SEL 0x19d98
50774 #define A_LE_DB_DBGI_RSP_DATA 0x19da0
50775 #define A_LE_DB_DBGI_RSP_LAST_CMD 0x19de4
50776 
50777 #define S_LASTCMDB    16
50778 #define M_LASTCMDB    0x7ffU
50779 #define V_LASTCMDB(x) ((x) << S_LASTCMDB)
50780 #define G_LASTCMDB(x) (((x) >> S_LASTCMDB) & M_LASTCMDB)
50781 
50782 #define S_LASTCMDA    0
50783 #define M_LASTCMDA    0x7ffU
50784 #define V_LASTCMDA(x) ((x) << S_LASTCMDA)
50785 #define G_LASTCMDA(x) (((x) >> S_LASTCMDA) & M_LASTCMDA)
50786 
50787 #define A_LE_DB_DROP_FILTER_ENTRY 0x19de8
50788 
50789 #define S_DROPFILTEREN    31
50790 #define V_DROPFILTEREN(x) ((x) << S_DROPFILTEREN)
50791 #define F_DROPFILTEREN    V_DROPFILTEREN(1U)
50792 
50793 #define S_DROPFILTERCLEAR    17
50794 #define V_DROPFILTERCLEAR(x) ((x) << S_DROPFILTERCLEAR)
50795 #define F_DROPFILTERCLEAR    V_DROPFILTERCLEAR(1U)
50796 
50797 #define S_DROPFILTERSET    16
50798 #define V_DROPFILTERSET(x) ((x) << S_DROPFILTERSET)
50799 #define F_DROPFILTERSET    V_DROPFILTERSET(1U)
50800 
50801 #define S_DROPFILTERFIDX    0
50802 #define M_DROPFILTERFIDX    0x1fffU
50803 #define V_DROPFILTERFIDX(x) ((x) << S_DROPFILTERFIDX)
50804 #define G_DROPFILTERFIDX(x) (((x) >> S_DROPFILTERFIDX) & M_DROPFILTERFIDX)
50805 
50806 #define A_LE_DB_PTID_SVRBASE 0x19df0
50807 
50808 #define S_SVRBASE_ADDR    2
50809 #define M_SVRBASE_ADDR    0x3ffffU
50810 #define V_SVRBASE_ADDR(x) ((x) << S_SVRBASE_ADDR)
50811 #define G_SVRBASE_ADDR(x) (((x) >> S_SVRBASE_ADDR) & M_SVRBASE_ADDR)
50812 
50813 #define A_LE_DB_TCAM_TID_BASE 0x19df0
50814 
50815 #define S_TCAM_TID_BASE    0
50816 #define M_TCAM_TID_BASE    0xfffffU
50817 #define V_TCAM_TID_BASE(x) ((x) << S_TCAM_TID_BASE)
50818 #define G_TCAM_TID_BASE(x) (((x) >> S_TCAM_TID_BASE) & M_TCAM_TID_BASE)
50819 
50820 #define A_LE_DB_FTID_FLTRBASE 0x19df4
50821 
50822 #define S_FLTRBASE_ADDR    2
50823 #define M_FLTRBASE_ADDR    0x3ffffU
50824 #define V_FLTRBASE_ADDR(x) ((x) << S_FLTRBASE_ADDR)
50825 #define G_FLTRBASE_ADDR(x) (((x) >> S_FLTRBASE_ADDR) & M_FLTRBASE_ADDR)
50826 
50827 #define A_LE_DB_CLCAM_TID_BASE 0x19df4
50828 
50829 #define S_CLCAM_TID_BASE    0
50830 #define M_CLCAM_TID_BASE    0xfffffU
50831 #define V_CLCAM_TID_BASE(x) ((x) << S_CLCAM_TID_BASE)
50832 #define G_CLCAM_TID_BASE(x) (((x) >> S_CLCAM_TID_BASE) & M_CLCAM_TID_BASE)
50833 
50834 #define A_LE_DB_TID_HASHBASE 0x19df8
50835 
50836 #define S_HASHBASE_ADDR    2
50837 #define M_HASHBASE_ADDR    0xfffffU
50838 #define V_HASHBASE_ADDR(x) ((x) << S_HASHBASE_ADDR)
50839 #define G_HASHBASE_ADDR(x) (((x) >> S_HASHBASE_ADDR) & M_HASHBASE_ADDR)
50840 
50841 #define A_T6_LE_DB_HASH_TID_BASE 0x19df8
50842 
50843 #define S_HASH_TID_BASE    0
50844 #define M_HASH_TID_BASE    0xfffffU
50845 #define V_HASH_TID_BASE(x) ((x) << S_HASH_TID_BASE)
50846 #define G_HASH_TID_BASE(x) (((x) >> S_HASH_TID_BASE) & M_HASH_TID_BASE)
50847 
50848 #define A_T7_LE_DB_HASH_TID_BASE 0x19df8
50849 #define A_LE_PERR_INJECT 0x19dfc
50850 
50851 #define S_LEMEMSEL    1
50852 #define M_LEMEMSEL    0x7U
50853 #define V_LEMEMSEL(x) ((x) << S_LEMEMSEL)
50854 #define G_LEMEMSEL(x) (((x) >> S_LEMEMSEL) & M_LEMEMSEL)
50855 
50856 #define A_LE_DB_SSRAM_TID_BASE 0x19dfc
50857 
50858 #define S_SSRAM_TID_BASE    0
50859 #define M_SSRAM_TID_BASE    0xfffffU
50860 #define V_SSRAM_TID_BASE(x) ((x) << S_SSRAM_TID_BASE)
50861 #define G_SSRAM_TID_BASE(x) (((x) >> S_SSRAM_TID_BASE) & M_SSRAM_TID_BASE)
50862 
50863 #define A_LE_DB_ACTIVE_MASK_IPV4 0x19e00
50864 #define A_LE_T5_DB_ACTIVE_MASK_IPV4 0x19e00
50865 #define A_LE_DB_ACTIVE_MASK_IPV6 0x19e50
50866 #define A_LE_HASH_MASK_GEN_IPV4 0x19ea0
50867 #define A_LE_HASH_MASK_GEN_IPV4T5 0x19ea0
50868 #define A_LE_HASH_MASK_GEN_IPV6 0x19eb0
50869 #define A_LE_HASH_MASK_GEN_IPV6T5 0x19eb4
50870 #define A_T6_LE_HASH_MASK_GEN_IPV6T5 0x19ec4
50871 #define A_T7_LE_HASH_MASK_GEN_IPV6T5 0x19ec4
50872 #define A_LE_HASH_MASK_CMP_IPV4 0x19ee0
50873 #define A_LE_HASH_MASK_CMP_IPV4T5 0x19ee4
50874 #define A_LE_DB_PSV_FILTER_MASK_TUP_IPV4 0x19ee4
50875 #define A_LE_HASH_MASK_CMP_IPV6 0x19ef0
50876 #define A_LE_DB_PSV_FILTER_MASK_FLT_IPV4 0x19ef0
50877 #define A_LE_HASH_MASK_CMP_IPV6T5 0x19ef8
50878 #define A_LE_DB_PSV_FILTER_MASK_TUP_IPV6 0x19f04
50879 #define A_LE_DEBUG_LA_CONFIG 0x19f20
50880 #define A_LE_REQ_DEBUG_LA_DATA 0x19f24
50881 #define A_LE_REQ_DEBUG_LA_WRPTR 0x19f28
50882 #define A_LE_DB_PSV_FILTER_MASK_FLT_IPV6 0x19f28
50883 #define A_LE_RSP_DEBUG_LA_DATA 0x19f2c
50884 #define A_LE_RSP_DEBUG_LA_WRPTR 0x19f30
50885 #define A_LE_DEBUG_LA_SELECTOR 0x19f34
50886 #define A_LE_SRVR_SRAM_INIT 0x19f34
50887 
50888 #define S_SRVRSRAMBASE    2
50889 #define M_SRVRSRAMBASE    0xfffffU
50890 #define V_SRVRSRAMBASE(x) ((x) << S_SRVRSRAMBASE)
50891 #define G_SRVRSRAMBASE(x) (((x) >> S_SRVRSRAMBASE) & M_SRVRSRAMBASE)
50892 
50893 #define S_SRVRINITBUSY    1
50894 #define V_SRVRINITBUSY(x) ((x) << S_SRVRINITBUSY)
50895 #define F_SRVRINITBUSY    V_SRVRINITBUSY(1U)
50896 
50897 #define S_SRVRINIT    0
50898 #define V_SRVRINIT(x) ((x) << S_SRVRINIT)
50899 #define F_SRVRINIT    V_SRVRINIT(1U)
50900 
50901 #define A_LE_DB_SRVR_SRAM_CONFIG 0x19f34
50902 
50903 #define S_PRI_HFILT    4
50904 #define V_PRI_HFILT(x) ((x) << S_PRI_HFILT)
50905 #define F_PRI_HFILT    V_PRI_HFILT(1U)
50906 
50907 #define S_PRI_SRVR    3
50908 #define V_PRI_SRVR(x) ((x) << S_PRI_SRVR)
50909 #define F_PRI_SRVR    V_PRI_SRVR(1U)
50910 
50911 #define S_PRI_FILT    2
50912 #define V_PRI_FILT(x) ((x) << S_PRI_FILT)
50913 #define F_PRI_FILT    V_PRI_FILT(1U)
50914 
50915 #define A_LE_DEBUG_LA_CAPTURED_DATA 0x19f38
50916 #define A_LE_SRVR_VF_SRCH_TABLE 0x19f38
50917 
50918 #define S_RDWR    21
50919 #define V_RDWR(x) ((x) << S_RDWR)
50920 #define F_RDWR    V_RDWR(1U)
50921 
50922 #define S_VFINDEX    14
50923 #define M_VFINDEX    0x7fU
50924 #define V_VFINDEX(x) ((x) << S_VFINDEX)
50925 #define G_VFINDEX(x) (((x) >> S_VFINDEX) & M_VFINDEX)
50926 
50927 #define S_SRCHHADDR    7
50928 #define M_SRCHHADDR    0x7fU
50929 #define V_SRCHHADDR(x) ((x) << S_SRCHHADDR)
50930 #define G_SRCHHADDR(x) (((x) >> S_SRCHHADDR) & M_SRCHHADDR)
50931 
50932 #define S_SRCHLADDR    0
50933 #define M_SRCHLADDR    0x7fU
50934 #define V_SRCHLADDR(x) ((x) << S_SRCHLADDR)
50935 #define G_SRCHLADDR(x) (((x) >> S_SRCHLADDR) & M_SRCHLADDR)
50936 
50937 #define A_LE_DB_SRVR_VF_SRCH_TABLE_CTRL 0x19f38
50938 
50939 #define S_VFLUTBUSY    10
50940 #define V_VFLUTBUSY(x) ((x) << S_VFLUTBUSY)
50941 #define F_VFLUTBUSY    V_VFLUTBUSY(1U)
50942 
50943 #define S_VFLUTSTART    9
50944 #define V_VFLUTSTART(x) ((x) << S_VFLUTSTART)
50945 #define F_VFLUTSTART    V_VFLUTSTART(1U)
50946 
50947 #define S_T6_RDWR    8
50948 #define V_T6_RDWR(x) ((x) << S_T6_RDWR)
50949 #define F_T6_RDWR    V_T6_RDWR(1U)
50950 
50951 #define S_T6_VFINDEX    0
50952 #define M_T6_VFINDEX    0xffU
50953 #define V_T6_VFINDEX(x) ((x) << S_T6_VFINDEX)
50954 #define G_T6_VFINDEX(x) (((x) >> S_T6_VFINDEX) & M_T6_VFINDEX)
50955 
50956 #define A_LE_MA_DEBUG_LA_DATA 0x19f3c
50957 #define A_LE_DB_SRVR_VF_SRCH_TABLE_DATA 0x19f3c
50958 
50959 #define S_T6_SRCHHADDR    12
50960 #define M_T6_SRCHHADDR    0xfffU
50961 #define V_T6_SRCHHADDR(x) ((x) << S_T6_SRCHHADDR)
50962 #define G_T6_SRCHHADDR(x) (((x) >> S_T6_SRCHHADDR) & M_T6_SRCHHADDR)
50963 
50964 #define S_T6_SRCHLADDR    0
50965 #define M_T6_SRCHLADDR    0xfffU
50966 #define V_T6_SRCHLADDR(x) ((x) << S_T6_SRCHLADDR)
50967 #define G_T6_SRCHLADDR(x) (((x) >> S_T6_SRCHLADDR) & M_T6_SRCHLADDR)
50968 
50969 #define A_LE_RSP_DEBUG_LA_HASH_WRPTR 0x19f40
50970 #define A_LE_DB_SECOND_ACTIVE_MASK_IPV4 0x19f40
50971 #define A_LE_HASH_DEBUG_LA_DATA 0x19f44
50972 #define A_LE_RSP_DEBUG_LA_TCAM_WRPTR 0x19f48
50973 #define A_LE_TCAM_DEBUG_LA_DATA 0x19f4c
50974 #define A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 0x19f90
50975 #define A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 0x19fa4
50976 #define A_LE_TCAM_BIST_CTRL 0x19fb0
50977 #define A_LE_TCAM_BIST_CB_PASS 0x19fb4
50978 #define A_LE_TCAM_BIST_CB_BUSY 0x19fbc
50979 #define A_LE_HASH_COLLISION 0x19fc4
50980 #define A_LE_GLOBAL_COLLISION 0x19fc8
50981 #define A_LE_FULL_CNT_COLLISION 0x19fcc
50982 #define A_LE_DEBUG_LA_CONFIGT5 0x19fd0
50983 #define A_LE_REQ_DEBUG_LA_DATAT5 0x19fd4
50984 #define A_LE_REQ_DEBUG_LA_WRPTRT5 0x19fd8
50985 #define A_LE_RSP_DEBUG_LA_DATAT5 0x19fdc
50986 #define A_LE_RSP_DEBUG_LA_WRPTRT5 0x19fe0
50987 #define A_LE_DEBUG_LA_SEL_DATA 0x19fe4
50988 #define A_LE_TCAM_NEG_CTRL0 0x0
50989 #define A_LE_TCAM_NEG_CTRL1 0x1
50990 #define A_LE_TCAM_NEG_CTRL2 0x2
50991 #define A_LE_TCAM_NEG_CTRL3 0x3
50992 #define A_LE_TCAM_NEG_CTRL4 0x4
50993 #define A_LE_TCAM_NEG_CTRL5 0x5
50994 #define A_LE_TCAM_NEG_CTRL6 0x6
50995 #define A_LE_TCAM_NEG_CTRL7 0x7
50996 #define A_LE_TCAM_NEG_CTRL8 0x8
50997 #define A_LE_TCAM_NEG_CTRL9 0x9
50998 #define A_LE_TCAM_NEG_CTRL10 0xa
50999 #define A_LE_TCAM_NEG_CTRL11 0xb
51000 #define A_LE_TCAM_NEG_CTRL12 0xc
51001 #define A_LE_TCAM_NEG_CTRL13 0xd
51002 #define A_LE_TCAM_NEG_CTRL14 0xe
51003 #define A_LE_TCAM_NEG_CTRL15 0xf
51004 #define A_LE_TCAM_NEG_CTRL16 0x10
51005 #define A_LE_TCAM_NEG_CTRL17 0x11
51006 #define A_LE_TCAM_NEG_CTRL18 0x12
51007 #define A_LE_TCAM_NEG_CTRL19 0x13
51008 #define A_LE_TCAM_NEG_CTRL20 0x14
51009 #define A_LE_TCAM_NEG_CTRL21 0x15
51010 #define A_LE_TCAM_NEG_CTRL22 0x16
51011 #define A_LE_TCAM_NEG_CTRL23 0x17
51012 #define A_LE_TCAM_NEG_CTRL24 0x18
51013 #define A_LE_TCAM_NEG_CTRL25 0x19
51014 #define A_LE_TCAM_NEG_CTRL26 0x1a
51015 #define A_LE_TCAM_NEG_CTRL27 0x1b
51016 #define A_LE_TCAM_NEG_CTRL28 0x1c
51017 #define A_LE_TCAM_NEG_CTRL29 0x1d
51018 #define A_LE_TCAM_NEG_CTRL30 0x1e
51019 #define A_LE_TCAM_NEG_CTRL31 0x1f
51020 
51021 /* registers for module NCSI */
51022 #define NCSI_BASE_ADDR 0x1a000
51023 
51024 #define A_NCSI_PORT_CFGREG 0x1a000
51025 
51026 #define S_WIREEN    28
51027 #define M_WIREEN    0xfU
51028 #define V_WIREEN(x) ((x) << S_WIREEN)
51029 #define G_WIREEN(x) (((x) >> S_WIREEN) & M_WIREEN)
51030 
51031 #define S_STRP_CRC    24
51032 #define M_STRP_CRC    0xfU
51033 #define V_STRP_CRC(x) ((x) << S_STRP_CRC)
51034 #define G_STRP_CRC(x) (((x) >> S_STRP_CRC) & M_STRP_CRC)
51035 
51036 #define S_RX_HALT    22
51037 #define V_RX_HALT(x) ((x) << S_RX_HALT)
51038 #define F_RX_HALT    V_RX_HALT(1U)
51039 
51040 #define S_FLUSH_RX_FIFO    21
51041 #define V_FLUSH_RX_FIFO(x) ((x) << S_FLUSH_RX_FIFO)
51042 #define F_FLUSH_RX_FIFO    V_FLUSH_RX_FIFO(1U)
51043 
51044 #define S_HW_ARB_EN    20
51045 #define V_HW_ARB_EN(x) ((x) << S_HW_ARB_EN)
51046 #define F_HW_ARB_EN    V_HW_ARB_EN(1U)
51047 
51048 #define S_SOFT_PKG_SEL    19
51049 #define V_SOFT_PKG_SEL(x) ((x) << S_SOFT_PKG_SEL)
51050 #define F_SOFT_PKG_SEL    V_SOFT_PKG_SEL(1U)
51051 
51052 #define S_ERR_DISCARD_EN    18
51053 #define V_ERR_DISCARD_EN(x) ((x) << S_ERR_DISCARD_EN)
51054 #define F_ERR_DISCARD_EN    V_ERR_DISCARD_EN(1U)
51055 
51056 #define S_MAX_PKT_SIZE    4
51057 #define M_MAX_PKT_SIZE    0x3fffU
51058 #define V_MAX_PKT_SIZE(x) ((x) << S_MAX_PKT_SIZE)
51059 #define G_MAX_PKT_SIZE(x) (((x) >> S_MAX_PKT_SIZE) & M_MAX_PKT_SIZE)
51060 
51061 #define S_RX_BYTE_SWAP    3
51062 #define V_RX_BYTE_SWAP(x) ((x) << S_RX_BYTE_SWAP)
51063 #define F_RX_BYTE_SWAP    V_RX_BYTE_SWAP(1U)
51064 
51065 #define S_TX_BYTE_SWAP    2
51066 #define V_TX_BYTE_SWAP(x) ((x) << S_TX_BYTE_SWAP)
51067 #define F_TX_BYTE_SWAP    V_TX_BYTE_SWAP(1U)
51068 
51069 #define S_XGMAC0_EN    0
51070 #define V_XGMAC0_EN(x) ((x) << S_XGMAC0_EN)
51071 #define F_XGMAC0_EN    V_XGMAC0_EN(1U)
51072 
51073 #define A_NCSI_RST_CTRL 0x1a004
51074 
51075 #define S_MAC_REF_RST    2
51076 #define V_MAC_REF_RST(x) ((x) << S_MAC_REF_RST)
51077 #define F_MAC_REF_RST    V_MAC_REF_RST(1U)
51078 
51079 #define S_MAC_RX_RST    1
51080 #define V_MAC_RX_RST(x) ((x) << S_MAC_RX_RST)
51081 #define F_MAC_RX_RST    V_MAC_RX_RST(1U)
51082 
51083 #define S_MAC_TX_RST    0
51084 #define V_MAC_TX_RST(x) ((x) << S_MAC_TX_RST)
51085 #define F_MAC_TX_RST    V_MAC_TX_RST(1U)
51086 
51087 #define A_NCSI_CH0_SADDR_LOW 0x1a010
51088 #define A_NCSI_CH0_SADDR_HIGH 0x1a014
51089 
51090 #define S_CHO_SADDR_EN    31
51091 #define V_CHO_SADDR_EN(x) ((x) << S_CHO_SADDR_EN)
51092 #define F_CHO_SADDR_EN    V_CHO_SADDR_EN(1U)
51093 
51094 #define S_CH0_SADDR_HIGH    0
51095 #define M_CH0_SADDR_HIGH    0xffffU
51096 #define V_CH0_SADDR_HIGH(x) ((x) << S_CH0_SADDR_HIGH)
51097 #define G_CH0_SADDR_HIGH(x) (((x) >> S_CH0_SADDR_HIGH) & M_CH0_SADDR_HIGH)
51098 
51099 #define A_NCSI_CH1_SADDR_LOW 0x1a018
51100 #define A_NCSI_CH1_SADDR_HIGH 0x1a01c
51101 
51102 #define S_CH1_SADDR_EN    31
51103 #define V_CH1_SADDR_EN(x) ((x) << S_CH1_SADDR_EN)
51104 #define F_CH1_SADDR_EN    V_CH1_SADDR_EN(1U)
51105 
51106 #define S_CH1_SADDR_HIGH    0
51107 #define M_CH1_SADDR_HIGH    0xffffU
51108 #define V_CH1_SADDR_HIGH(x) ((x) << S_CH1_SADDR_HIGH)
51109 #define G_CH1_SADDR_HIGH(x) (((x) >> S_CH1_SADDR_HIGH) & M_CH1_SADDR_HIGH)
51110 
51111 #define A_NCSI_CH2_SADDR_LOW 0x1a020
51112 #define A_NCSI_CH2_SADDR_HIGH 0x1a024
51113 
51114 #define S_CH2_SADDR_EN    31
51115 #define V_CH2_SADDR_EN(x) ((x) << S_CH2_SADDR_EN)
51116 #define F_CH2_SADDR_EN    V_CH2_SADDR_EN(1U)
51117 
51118 #define S_CH2_SADDR_HIGH    0
51119 #define M_CH2_SADDR_HIGH    0xffffU
51120 #define V_CH2_SADDR_HIGH(x) ((x) << S_CH2_SADDR_HIGH)
51121 #define G_CH2_SADDR_HIGH(x) (((x) >> S_CH2_SADDR_HIGH) & M_CH2_SADDR_HIGH)
51122 
51123 #define A_NCSI_CH3_SADDR_LOW 0x1a028
51124 #define A_NCSI_CH3_SADDR_HIGH 0x1a02c
51125 
51126 #define S_CH3_SADDR_EN    31
51127 #define V_CH3_SADDR_EN(x) ((x) << S_CH3_SADDR_EN)
51128 #define F_CH3_SADDR_EN    V_CH3_SADDR_EN(1U)
51129 
51130 #define S_CH3_SADDR_HIGH    0
51131 #define M_CH3_SADDR_HIGH    0xffffU
51132 #define V_CH3_SADDR_HIGH(x) ((x) << S_CH3_SADDR_HIGH)
51133 #define G_CH3_SADDR_HIGH(x) (((x) >> S_CH3_SADDR_HIGH) & M_CH3_SADDR_HIGH)
51134 
51135 #define A_NCSI_WORK_REQHDR_0 0x1a030
51136 #define A_NCSI_WORK_REQHDR_1 0x1a034
51137 #define A_NCSI_WORK_REQHDR_2 0x1a038
51138 #define A_NCSI_WORK_REQHDR_3 0x1a03c
51139 #define A_NCSI_MPS_HDR_LO 0x1a040
51140 #define A_NCSI_MPS_HDR_HI 0x1a044
51141 #define A_NCSI_CTL 0x1a048
51142 
51143 #define S_STRIP_OVLAN    3
51144 #define V_STRIP_OVLAN(x) ((x) << S_STRIP_OVLAN)
51145 #define F_STRIP_OVLAN    V_STRIP_OVLAN(1U)
51146 
51147 #define S_BMC_DROP_NON_BC    2
51148 #define V_BMC_DROP_NON_BC(x) ((x) << S_BMC_DROP_NON_BC)
51149 #define F_BMC_DROP_NON_BC    V_BMC_DROP_NON_BC(1U)
51150 
51151 #define S_BMC_RX_FWD_ALL    1
51152 #define V_BMC_RX_FWD_ALL(x) ((x) << S_BMC_RX_FWD_ALL)
51153 #define F_BMC_RX_FWD_ALL    V_BMC_RX_FWD_ALL(1U)
51154 
51155 #define S_FWD_BMC    0
51156 #define V_FWD_BMC(x) ((x) << S_FWD_BMC)
51157 #define F_FWD_BMC    V_FWD_BMC(1U)
51158 
51159 #define A_NCSI_NCSI_ETYPE 0x1a04c
51160 
51161 #define S_NCSI_ETHERTYPE    0
51162 #define M_NCSI_ETHERTYPE    0xffffU
51163 #define V_NCSI_ETHERTYPE(x) ((x) << S_NCSI_ETHERTYPE)
51164 #define G_NCSI_ETHERTYPE(x) (((x) >> S_NCSI_ETHERTYPE) & M_NCSI_ETHERTYPE)
51165 
51166 #define A_NCSI_RX_FIFO_CNT 0x1a050
51167 
51168 #define S_NCSI_RXFIFO_CNT    0
51169 #define M_NCSI_RXFIFO_CNT    0x7ffU
51170 #define V_NCSI_RXFIFO_CNT(x) ((x) << S_NCSI_RXFIFO_CNT)
51171 #define G_NCSI_RXFIFO_CNT(x) (((x) >> S_NCSI_RXFIFO_CNT) & M_NCSI_RXFIFO_CNT)
51172 
51173 #define A_NCSI_RX_ERR_CNT 0x1a054
51174 #define A_NCSI_RX_OF_CNT 0x1a058
51175 #define A_NCSI_RX_MS_CNT 0x1a05c
51176 #define A_NCSI_RX_IE_CNT 0x1a060
51177 #define A_NCSI_MPS_DEMUX_CNT 0x1a064
51178 
51179 #define S_MPS2CIM_CNT    16
51180 #define M_MPS2CIM_CNT    0x1ffU
51181 #define V_MPS2CIM_CNT(x) ((x) << S_MPS2CIM_CNT)
51182 #define G_MPS2CIM_CNT(x) (((x) >> S_MPS2CIM_CNT) & M_MPS2CIM_CNT)
51183 
51184 #define S_MPS2BMC_CNT    0
51185 #define M_MPS2BMC_CNT    0x1ffU
51186 #define V_MPS2BMC_CNT(x) ((x) << S_MPS2BMC_CNT)
51187 #define G_MPS2BMC_CNT(x) (((x) >> S_MPS2BMC_CNT) & M_MPS2BMC_CNT)
51188 
51189 #define A_NCSI_CIM_DEMUX_CNT 0x1a068
51190 
51191 #define S_CIM2MPS_CNT    16
51192 #define M_CIM2MPS_CNT    0x1ffU
51193 #define V_CIM2MPS_CNT(x) ((x) << S_CIM2MPS_CNT)
51194 #define G_CIM2MPS_CNT(x) (((x) >> S_CIM2MPS_CNT) & M_CIM2MPS_CNT)
51195 
51196 #define S_CIM2BMC_CNT    0
51197 #define M_CIM2BMC_CNT    0x1ffU
51198 #define V_CIM2BMC_CNT(x) ((x) << S_CIM2BMC_CNT)
51199 #define G_CIM2BMC_CNT(x) (((x) >> S_CIM2BMC_CNT) & M_CIM2BMC_CNT)
51200 
51201 #define A_NCSI_TX_FIFO_CNT 0x1a06c
51202 
51203 #define S_TX_FIFO_CNT    0
51204 #define M_TX_FIFO_CNT    0x3ffU
51205 #define V_TX_FIFO_CNT(x) ((x) << S_TX_FIFO_CNT)
51206 #define G_TX_FIFO_CNT(x) (((x) >> S_TX_FIFO_CNT) & M_TX_FIFO_CNT)
51207 
51208 #define A_NCSI_SE_CNT_CTL 0x1a0b0
51209 
51210 #define S_SE_CNT_CLR    0
51211 #define M_SE_CNT_CLR    0xfU
51212 #define V_SE_CNT_CLR(x) ((x) << S_SE_CNT_CLR)
51213 #define G_SE_CNT_CLR(x) (((x) >> S_SE_CNT_CLR) & M_SE_CNT_CLR)
51214 
51215 #define A_NCSI_SE_CNT_MPS 0x1a0b4
51216 
51217 #define S_NC2MPS_SOP_CNT    24
51218 #define M_NC2MPS_SOP_CNT    0xffU
51219 #define V_NC2MPS_SOP_CNT(x) ((x) << S_NC2MPS_SOP_CNT)
51220 #define G_NC2MPS_SOP_CNT(x) (((x) >> S_NC2MPS_SOP_CNT) & M_NC2MPS_SOP_CNT)
51221 
51222 #define S_NC2MPS_EOP_CNT    16
51223 #define M_NC2MPS_EOP_CNT    0x3fU
51224 #define V_NC2MPS_EOP_CNT(x) ((x) << S_NC2MPS_EOP_CNT)
51225 #define G_NC2MPS_EOP_CNT(x) (((x) >> S_NC2MPS_EOP_CNT) & M_NC2MPS_EOP_CNT)
51226 
51227 #define S_MPS2NC_SOP_CNT    8
51228 #define M_MPS2NC_SOP_CNT    0xffU
51229 #define V_MPS2NC_SOP_CNT(x) ((x) << S_MPS2NC_SOP_CNT)
51230 #define G_MPS2NC_SOP_CNT(x) (((x) >> S_MPS2NC_SOP_CNT) & M_MPS2NC_SOP_CNT)
51231 
51232 #define S_MPS2NC_EOP_CNT    0
51233 #define M_MPS2NC_EOP_CNT    0xffU
51234 #define V_MPS2NC_EOP_CNT(x) ((x) << S_MPS2NC_EOP_CNT)
51235 #define G_MPS2NC_EOP_CNT(x) (((x) >> S_MPS2NC_EOP_CNT) & M_MPS2NC_EOP_CNT)
51236 
51237 #define A_NCSI_SE_CNT_CIM 0x1a0b8
51238 
51239 #define S_NC2CIM_SOP_CNT    24
51240 #define M_NC2CIM_SOP_CNT    0xffU
51241 #define V_NC2CIM_SOP_CNT(x) ((x) << S_NC2CIM_SOP_CNT)
51242 #define G_NC2CIM_SOP_CNT(x) (((x) >> S_NC2CIM_SOP_CNT) & M_NC2CIM_SOP_CNT)
51243 
51244 #define S_NC2CIM_EOP_CNT    16
51245 #define M_NC2CIM_EOP_CNT    0x3fU
51246 #define V_NC2CIM_EOP_CNT(x) ((x) << S_NC2CIM_EOP_CNT)
51247 #define G_NC2CIM_EOP_CNT(x) (((x) >> S_NC2CIM_EOP_CNT) & M_NC2CIM_EOP_CNT)
51248 
51249 #define S_CIM2NC_SOP_CNT    8
51250 #define M_CIM2NC_SOP_CNT    0xffU
51251 #define V_CIM2NC_SOP_CNT(x) ((x) << S_CIM2NC_SOP_CNT)
51252 #define G_CIM2NC_SOP_CNT(x) (((x) >> S_CIM2NC_SOP_CNT) & M_CIM2NC_SOP_CNT)
51253 
51254 #define S_CIM2NC_EOP_CNT    0
51255 #define M_CIM2NC_EOP_CNT    0xffU
51256 #define V_CIM2NC_EOP_CNT(x) ((x) << S_CIM2NC_EOP_CNT)
51257 #define G_CIM2NC_EOP_CNT(x) (((x) >> S_CIM2NC_EOP_CNT) & M_CIM2NC_EOP_CNT)
51258 
51259 #define A_NCSI_BUS_DEBUG 0x1a0bc
51260 
51261 #define S_SOP_CNT_ERR    12
51262 #define M_SOP_CNT_ERR    0xfU
51263 #define V_SOP_CNT_ERR(x) ((x) << S_SOP_CNT_ERR)
51264 #define G_SOP_CNT_ERR(x) (((x) >> S_SOP_CNT_ERR) & M_SOP_CNT_ERR)
51265 
51266 #define S_BUS_STATE_MPS_OUT    6
51267 #define M_BUS_STATE_MPS_OUT    0x3U
51268 #define V_BUS_STATE_MPS_OUT(x) ((x) << S_BUS_STATE_MPS_OUT)
51269 #define G_BUS_STATE_MPS_OUT(x) (((x) >> S_BUS_STATE_MPS_OUT) & M_BUS_STATE_MPS_OUT)
51270 
51271 #define S_BUS_STATE_MPS_IN    4
51272 #define M_BUS_STATE_MPS_IN    0x3U
51273 #define V_BUS_STATE_MPS_IN(x) ((x) << S_BUS_STATE_MPS_IN)
51274 #define G_BUS_STATE_MPS_IN(x) (((x) >> S_BUS_STATE_MPS_IN) & M_BUS_STATE_MPS_IN)
51275 
51276 #define S_BUS_STATE_CIM_OUT    2
51277 #define M_BUS_STATE_CIM_OUT    0x3U
51278 #define V_BUS_STATE_CIM_OUT(x) ((x) << S_BUS_STATE_CIM_OUT)
51279 #define G_BUS_STATE_CIM_OUT(x) (((x) >> S_BUS_STATE_CIM_OUT) & M_BUS_STATE_CIM_OUT)
51280 
51281 #define S_BUS_STATE_CIM_IN    0
51282 #define M_BUS_STATE_CIM_IN    0x3U
51283 #define V_BUS_STATE_CIM_IN(x) ((x) << S_BUS_STATE_CIM_IN)
51284 #define G_BUS_STATE_CIM_IN(x) (((x) >> S_BUS_STATE_CIM_IN) & M_BUS_STATE_CIM_IN)
51285 
51286 #define A_NCSI_LA_RDPTR 0x1a0c0
51287 #define A_NCSI_LA_RDDATA 0x1a0c4
51288 #define A_NCSI_LA_WRPTR 0x1a0c8
51289 #define A_NCSI_LA_RESERVED 0x1a0cc
51290 #define A_NCSI_LA_CTL 0x1a0d0
51291 #define A_NCSI_INT_ENABLE 0x1a0d4
51292 
51293 #define S_CIM_DM_PRTY_ERR    8
51294 #define V_CIM_DM_PRTY_ERR(x) ((x) << S_CIM_DM_PRTY_ERR)
51295 #define F_CIM_DM_PRTY_ERR    V_CIM_DM_PRTY_ERR(1U)
51296 
51297 #define S_MPS_DM_PRTY_ERR    7
51298 #define V_MPS_DM_PRTY_ERR(x) ((x) << S_MPS_DM_PRTY_ERR)
51299 #define F_MPS_DM_PRTY_ERR    V_MPS_DM_PRTY_ERR(1U)
51300 
51301 #define S_TOKEN    6
51302 #define V_TOKEN(x) ((x) << S_TOKEN)
51303 #define F_TOKEN    V_TOKEN(1U)
51304 
51305 #define S_ARB_DONE    5
51306 #define V_ARB_DONE(x) ((x) << S_ARB_DONE)
51307 #define F_ARB_DONE    V_ARB_DONE(1U)
51308 
51309 #define S_ARB_STARTED    4
51310 #define V_ARB_STARTED(x) ((x) << S_ARB_STARTED)
51311 #define F_ARB_STARTED    V_ARB_STARTED(1U)
51312 
51313 #define S_WOL    3
51314 #define V_WOL(x) ((x) << S_WOL)
51315 #define F_WOL    V_WOL(1U)
51316 
51317 #define S_MACINT    2
51318 #define V_MACINT(x) ((x) << S_MACINT)
51319 #define F_MACINT    V_MACINT(1U)
51320 
51321 #define S_TXFIFO_PRTY_ERR    1
51322 #define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
51323 #define F_TXFIFO_PRTY_ERR    V_TXFIFO_PRTY_ERR(1U)
51324 
51325 #define S_RXFIFO_PRTY_ERR    0
51326 #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
51327 #define F_RXFIFO_PRTY_ERR    V_RXFIFO_PRTY_ERR(1U)
51328 
51329 #define S_CIM2NC_PERR    9
51330 #define V_CIM2NC_PERR(x) ((x) << S_CIM2NC_PERR)
51331 #define F_CIM2NC_PERR    V_CIM2NC_PERR(1U)
51332 
51333 #define A_NCSI_INT_CAUSE 0x1a0d8
51334 #define A_NCSI_STATUS 0x1a0dc
51335 
51336 #define S_MASTER    1
51337 #define V_MASTER(x) ((x) << S_MASTER)
51338 #define F_MASTER    V_MASTER(1U)
51339 
51340 #define S_ARB_STATUS    0
51341 #define V_ARB_STATUS(x) ((x) << S_ARB_STATUS)
51342 #define F_ARB_STATUS    V_ARB_STATUS(1U)
51343 
51344 #define A_NCSI_PAUSE_CTRL 0x1a0e0
51345 
51346 #define S_FORCEPAUSE    0
51347 #define V_FORCEPAUSE(x) ((x) << S_FORCEPAUSE)
51348 #define F_FORCEPAUSE    V_FORCEPAUSE(1U)
51349 
51350 #define A_NCSI_PAUSE_TIMEOUT 0x1a0e4
51351 #define A_NCSI_PAUSE_WM 0x1a0ec
51352 
51353 #define S_PAUSEHWM    16
51354 #define M_PAUSEHWM    0x7ffU
51355 #define V_PAUSEHWM(x) ((x) << S_PAUSEHWM)
51356 #define G_PAUSEHWM(x) (((x) >> S_PAUSEHWM) & M_PAUSEHWM)
51357 
51358 #define S_PAUSELWM    0
51359 #define M_PAUSELWM    0x7ffU
51360 #define V_PAUSELWM(x) ((x) << S_PAUSELWM)
51361 #define G_PAUSELWM(x) (((x) >> S_PAUSELWM) & M_PAUSELWM)
51362 
51363 #define A_NCSI_DEBUG 0x1a0f0
51364 
51365 #define S_DEBUGSEL    0
51366 #define M_DEBUGSEL    0x3fU
51367 #define V_DEBUGSEL(x) ((x) << S_DEBUGSEL)
51368 #define G_DEBUGSEL(x) (((x) >> S_DEBUGSEL) & M_DEBUGSEL)
51369 
51370 #define S_TXFIFO_EMPTY    4
51371 #define V_TXFIFO_EMPTY(x) ((x) << S_TXFIFO_EMPTY)
51372 #define F_TXFIFO_EMPTY    V_TXFIFO_EMPTY(1U)
51373 
51374 #define S_TXFIFO_FULL    3
51375 #define V_TXFIFO_FULL(x) ((x) << S_TXFIFO_FULL)
51376 #define F_TXFIFO_FULL    V_TXFIFO_FULL(1U)
51377 
51378 #define S_PKG_ID    0
51379 #define M_PKG_ID    0x7U
51380 #define V_PKG_ID(x) ((x) << S_PKG_ID)
51381 #define G_PKG_ID(x) (((x) >> S_PKG_ID) & M_PKG_ID)
51382 
51383 #define A_NCSI_PERR_INJECT 0x1a0f4
51384 
51385 #define S_MCSIMELSEL    1
51386 #define V_MCSIMELSEL(x) ((x) << S_MCSIMELSEL)
51387 #define F_MCSIMELSEL    V_MCSIMELSEL(1U)
51388 
51389 #define A_NCSI_PERR_ENABLE 0x1a0f8
51390 #define A_NCSI_MODE_SEL 0x1a0fc
51391 
51392 #define S_XGMAC_MODE    0
51393 #define V_XGMAC_MODE(x) ((x) << S_XGMAC_MODE)
51394 #define F_XGMAC_MODE    V_XGMAC_MODE(1U)
51395 
51396 #define A_NCSI_MACB_NETWORK_CTRL 0x1a100
51397 
51398 #define S_TXSNDZEROPAUSE    12
51399 #define V_TXSNDZEROPAUSE(x) ((x) << S_TXSNDZEROPAUSE)
51400 #define F_TXSNDZEROPAUSE    V_TXSNDZEROPAUSE(1U)
51401 
51402 #define S_TXSNDPAUSE    11
51403 #define V_TXSNDPAUSE(x) ((x) << S_TXSNDPAUSE)
51404 #define F_TXSNDPAUSE    V_TXSNDPAUSE(1U)
51405 
51406 #define S_TXSTOP    10
51407 #define V_TXSTOP(x) ((x) << S_TXSTOP)
51408 #define F_TXSTOP    V_TXSTOP(1U)
51409 
51410 #define S_TXSTART    9
51411 #define V_TXSTART(x) ((x) << S_TXSTART)
51412 #define F_TXSTART    V_TXSTART(1U)
51413 
51414 #define S_BACKPRESS    8
51415 #define V_BACKPRESS(x) ((x) << S_BACKPRESS)
51416 #define F_BACKPRESS    V_BACKPRESS(1U)
51417 
51418 #define S_STATWREN    7
51419 #define V_STATWREN(x) ((x) << S_STATWREN)
51420 #define F_STATWREN    V_STATWREN(1U)
51421 
51422 #define S_INCRSTAT    6
51423 #define V_INCRSTAT(x) ((x) << S_INCRSTAT)
51424 #define F_INCRSTAT    V_INCRSTAT(1U)
51425 
51426 #define S_CLEARSTAT    5
51427 #define V_CLEARSTAT(x) ((x) << S_CLEARSTAT)
51428 #define F_CLEARSTAT    V_CLEARSTAT(1U)
51429 
51430 #define S_ENMGMTPORT    4
51431 #define V_ENMGMTPORT(x) ((x) << S_ENMGMTPORT)
51432 #define F_ENMGMTPORT    V_ENMGMTPORT(1U)
51433 
51434 #define S_NCSITXEN    3
51435 #define V_NCSITXEN(x) ((x) << S_NCSITXEN)
51436 #define F_NCSITXEN    V_NCSITXEN(1U)
51437 
51438 #define S_NCSIRXEN    2
51439 #define V_NCSIRXEN(x) ((x) << S_NCSIRXEN)
51440 #define F_NCSIRXEN    V_NCSIRXEN(1U)
51441 
51442 #define S_LOOPLOCAL    1
51443 #define V_LOOPLOCAL(x) ((x) << S_LOOPLOCAL)
51444 #define F_LOOPLOCAL    V_LOOPLOCAL(1U)
51445 
51446 #define S_LOOPPHY    0
51447 #define V_LOOPPHY(x) ((x) << S_LOOPPHY)
51448 #define F_LOOPPHY    V_LOOPPHY(1U)
51449 
51450 #define A_NCSI_MACB_NETWORK_CFG 0x1a104
51451 
51452 #define S_PCLKDIV128    22
51453 #define V_PCLKDIV128(x) ((x) << S_PCLKDIV128)
51454 #define F_PCLKDIV128    V_PCLKDIV128(1U)
51455 
51456 #define S_COPYPAUSE    21
51457 #define V_COPYPAUSE(x) ((x) << S_COPYPAUSE)
51458 #define F_COPYPAUSE    V_COPYPAUSE(1U)
51459 
51460 #define S_NONSTDPREOK    20
51461 #define V_NONSTDPREOK(x) ((x) << S_NONSTDPREOK)
51462 #define F_NONSTDPREOK    V_NONSTDPREOK(1U)
51463 
51464 #define S_NOFCS    19
51465 #define V_NOFCS(x) ((x) << S_NOFCS)
51466 #define F_NOFCS    V_NOFCS(1U)
51467 
51468 #define S_RXENHALFDUP    18
51469 #define V_RXENHALFDUP(x) ((x) << S_RXENHALFDUP)
51470 #define F_RXENHALFDUP    V_RXENHALFDUP(1U)
51471 
51472 #define S_NOCOPYFCS    17
51473 #define V_NOCOPYFCS(x) ((x) << S_NOCOPYFCS)
51474 #define F_NOCOPYFCS    V_NOCOPYFCS(1U)
51475 
51476 #define S_LENCHKEN    16
51477 #define V_LENCHKEN(x) ((x) << S_LENCHKEN)
51478 #define F_LENCHKEN    V_LENCHKEN(1U)
51479 
51480 #define S_RXBUFOFFSET    14
51481 #define M_RXBUFOFFSET    0x3U
51482 #define V_RXBUFOFFSET(x) ((x) << S_RXBUFOFFSET)
51483 #define G_RXBUFOFFSET(x) (((x) >> S_RXBUFOFFSET) & M_RXBUFOFFSET)
51484 
51485 #define S_PAUSEEN    13
51486 #define V_PAUSEEN(x) ((x) << S_PAUSEEN)
51487 #define F_PAUSEEN    V_PAUSEEN(1U)
51488 
51489 #define S_RETRYTEST    12
51490 #define V_RETRYTEST(x) ((x) << S_RETRYTEST)
51491 #define F_RETRYTEST    V_RETRYTEST(1U)
51492 
51493 #define S_PCLKDIV    10
51494 #define M_PCLKDIV    0x3U
51495 #define V_PCLKDIV(x) ((x) << S_PCLKDIV)
51496 #define G_PCLKDIV(x) (((x) >> S_PCLKDIV) & M_PCLKDIV)
51497 
51498 #define S_EXTCLASS    9
51499 #define V_EXTCLASS(x) ((x) << S_EXTCLASS)
51500 #define F_EXTCLASS    V_EXTCLASS(1U)
51501 
51502 #define S_EN1536FRAME    8
51503 #define V_EN1536FRAME(x) ((x) << S_EN1536FRAME)
51504 #define F_EN1536FRAME    V_EN1536FRAME(1U)
51505 
51506 #define S_UCASTHASHEN    7
51507 #define V_UCASTHASHEN(x) ((x) << S_UCASTHASHEN)
51508 #define F_UCASTHASHEN    V_UCASTHASHEN(1U)
51509 
51510 #define S_MCASTHASHEN    6
51511 #define V_MCASTHASHEN(x) ((x) << S_MCASTHASHEN)
51512 #define F_MCASTHASHEN    V_MCASTHASHEN(1U)
51513 
51514 #define S_RXBCASTDIS    5
51515 #define V_RXBCASTDIS(x) ((x) << S_RXBCASTDIS)
51516 #define F_RXBCASTDIS    V_RXBCASTDIS(1U)
51517 
51518 #define S_NCSICOPYALLFRAMES    4
51519 #define V_NCSICOPYALLFRAMES(x) ((x) << S_NCSICOPYALLFRAMES)
51520 #define F_NCSICOPYALLFRAMES    V_NCSICOPYALLFRAMES(1U)
51521 
51522 #define S_JUMBOEN    3
51523 #define V_JUMBOEN(x) ((x) << S_JUMBOEN)
51524 #define F_JUMBOEN    V_JUMBOEN(1U)
51525 
51526 #define S_SEREN    2
51527 #define V_SEREN(x) ((x) << S_SEREN)
51528 #define F_SEREN    V_SEREN(1U)
51529 
51530 #define S_FULLDUPLEX    1
51531 #define V_FULLDUPLEX(x) ((x) << S_FULLDUPLEX)
51532 #define F_FULLDUPLEX    V_FULLDUPLEX(1U)
51533 
51534 #define S_SPEED    0
51535 #define V_SPEED(x) ((x) << S_SPEED)
51536 #define F_SPEED    V_SPEED(1U)
51537 
51538 #define A_NCSI_MACB_NETWORK_STATUS 0x1a108
51539 
51540 #define S_PHYMGMTSTATUS    2
51541 #define V_PHYMGMTSTATUS(x) ((x) << S_PHYMGMTSTATUS)
51542 #define F_PHYMGMTSTATUS    V_PHYMGMTSTATUS(1U)
51543 
51544 #define S_MDISTATUS    1
51545 #define V_MDISTATUS(x) ((x) << S_MDISTATUS)
51546 #define F_MDISTATUS    V_MDISTATUS(1U)
51547 
51548 #define S_LINKSTATUS    0
51549 #define V_LINKSTATUS(x) ((x) << S_LINKSTATUS)
51550 #define F_LINKSTATUS    V_LINKSTATUS(1U)
51551 
51552 #define A_NCSI_MACB_TX_STATUS 0x1a114
51553 
51554 #define S_UNDERRUNERR    6
51555 #define V_UNDERRUNERR(x) ((x) << S_UNDERRUNERR)
51556 #define F_UNDERRUNERR    V_UNDERRUNERR(1U)
51557 
51558 #define S_TXCOMPLETE    5
51559 #define V_TXCOMPLETE(x) ((x) << S_TXCOMPLETE)
51560 #define F_TXCOMPLETE    V_TXCOMPLETE(1U)
51561 
51562 #define S_BUFFEREXHAUSTED    4
51563 #define V_BUFFEREXHAUSTED(x) ((x) << S_BUFFEREXHAUSTED)
51564 #define F_BUFFEREXHAUSTED    V_BUFFEREXHAUSTED(1U)
51565 
51566 #define S_TXPROGRESS    3
51567 #define V_TXPROGRESS(x) ((x) << S_TXPROGRESS)
51568 #define F_TXPROGRESS    V_TXPROGRESS(1U)
51569 
51570 #define S_RETRYLIMIT    2
51571 #define V_RETRYLIMIT(x) ((x) << S_RETRYLIMIT)
51572 #define F_RETRYLIMIT    V_RETRYLIMIT(1U)
51573 
51574 #define S_COLEVENT    1
51575 #define V_COLEVENT(x) ((x) << S_COLEVENT)
51576 #define F_COLEVENT    V_COLEVENT(1U)
51577 
51578 #define S_USEDBITREAD    0
51579 #define V_USEDBITREAD(x) ((x) << S_USEDBITREAD)
51580 #define F_USEDBITREAD    V_USEDBITREAD(1U)
51581 
51582 #define A_NCSI_MACB_RX_BUF_QPTR 0x1a118
51583 
51584 #define S_RXBUFQPTR    2
51585 #define M_RXBUFQPTR    0x3fffffffU
51586 #define V_RXBUFQPTR(x) ((x) << S_RXBUFQPTR)
51587 #define G_RXBUFQPTR(x) (((x) >> S_RXBUFQPTR) & M_RXBUFQPTR)
51588 
51589 #define A_NCSI_MACB_TX_BUF_QPTR 0x1a11c
51590 
51591 #define S_TXBUFQPTR    2
51592 #define M_TXBUFQPTR    0x3fffffffU
51593 #define V_TXBUFQPTR(x) ((x) << S_TXBUFQPTR)
51594 #define G_TXBUFQPTR(x) (((x) >> S_TXBUFQPTR) & M_TXBUFQPTR)
51595 
51596 #define A_NCSI_MACB_RX_STATUS 0x1a120
51597 
51598 #define S_RXOVERRUNERR    2
51599 #define V_RXOVERRUNERR(x) ((x) << S_RXOVERRUNERR)
51600 #define F_RXOVERRUNERR    V_RXOVERRUNERR(1U)
51601 
51602 #define S_MACB_FRAMERCVD    1
51603 #define V_MACB_FRAMERCVD(x) ((x) << S_MACB_FRAMERCVD)
51604 #define F_MACB_FRAMERCVD    V_MACB_FRAMERCVD(1U)
51605 
51606 #define S_NORXBUF    0
51607 #define V_NORXBUF(x) ((x) << S_NORXBUF)
51608 #define F_NORXBUF    V_NORXBUF(1U)
51609 
51610 #define A_NCSI_MACB_INT_STATUS 0x1a124
51611 
51612 #define S_PAUSETIMEZERO    13
51613 #define V_PAUSETIMEZERO(x) ((x) << S_PAUSETIMEZERO)
51614 #define F_PAUSETIMEZERO    V_PAUSETIMEZERO(1U)
51615 
51616 #define S_PAUSERCVD    12
51617 #define V_PAUSERCVD(x) ((x) << S_PAUSERCVD)
51618 #define F_PAUSERCVD    V_PAUSERCVD(1U)
51619 
51620 #define S_HRESPNOTOK    11
51621 #define V_HRESPNOTOK(x) ((x) << S_HRESPNOTOK)
51622 #define F_HRESPNOTOK    V_HRESPNOTOK(1U)
51623 
51624 #define S_RXOVERRUN    10
51625 #define V_RXOVERRUN(x) ((x) << S_RXOVERRUN)
51626 #define F_RXOVERRUN    V_RXOVERRUN(1U)
51627 
51628 #define S_LINKCHANGE    9
51629 #define V_LINKCHANGE(x) ((x) << S_LINKCHANGE)
51630 #define F_LINKCHANGE    V_LINKCHANGE(1U)
51631 
51632 #define S_INT_TXCOMPLETE    7
51633 #define V_INT_TXCOMPLETE(x) ((x) << S_INT_TXCOMPLETE)
51634 #define F_INT_TXCOMPLETE    V_INT_TXCOMPLETE(1U)
51635 
51636 #define S_TXBUFERR    6
51637 #define V_TXBUFERR(x) ((x) << S_TXBUFERR)
51638 #define F_TXBUFERR    V_TXBUFERR(1U)
51639 
51640 #define S_RETRYLIMITERR    5
51641 #define V_RETRYLIMITERR(x) ((x) << S_RETRYLIMITERR)
51642 #define F_RETRYLIMITERR    V_RETRYLIMITERR(1U)
51643 
51644 #define S_TXBUFUNDERRUN    4
51645 #define V_TXBUFUNDERRUN(x) ((x) << S_TXBUFUNDERRUN)
51646 #define F_TXBUFUNDERRUN    V_TXBUFUNDERRUN(1U)
51647 
51648 #define S_TXUSEDBITREAD    3
51649 #define V_TXUSEDBITREAD(x) ((x) << S_TXUSEDBITREAD)
51650 #define F_TXUSEDBITREAD    V_TXUSEDBITREAD(1U)
51651 
51652 #define S_RXUSEDBITREAD    2
51653 #define V_RXUSEDBITREAD(x) ((x) << S_RXUSEDBITREAD)
51654 #define F_RXUSEDBITREAD    V_RXUSEDBITREAD(1U)
51655 
51656 #define S_RXCOMPLETE    1
51657 #define V_RXCOMPLETE(x) ((x) << S_RXCOMPLETE)
51658 #define F_RXCOMPLETE    V_RXCOMPLETE(1U)
51659 
51660 #define S_MGMTFRAMESENT    0
51661 #define V_MGMTFRAMESENT(x) ((x) << S_MGMTFRAMESENT)
51662 #define F_MGMTFRAMESENT    V_MGMTFRAMESENT(1U)
51663 
51664 #define A_NCSI_MACB_INT_EN 0x1a128
51665 #define A_NCSI_MACB_INT_DIS 0x1a12c
51666 #define A_NCSI_MACB_INT_MASK 0x1a130
51667 #define A_NCSI_MACB_PAUSE_TIME 0x1a138
51668 
51669 #define S_PAUSETIME    0
51670 #define M_PAUSETIME    0xffffU
51671 #define V_PAUSETIME(x) ((x) << S_PAUSETIME)
51672 #define G_PAUSETIME(x) (((x) >> S_PAUSETIME) & M_PAUSETIME)
51673 
51674 #define A_NCSI_MACB_PAUSE_FRAMES_RCVD 0x1a13c
51675 
51676 #define S_PAUSEFRRCVD    0
51677 #define M_PAUSEFRRCVD    0xffffU
51678 #define V_PAUSEFRRCVD(x) ((x) << S_PAUSEFRRCVD)
51679 #define G_PAUSEFRRCVD(x) (((x) >> S_PAUSEFRRCVD) & M_PAUSEFRRCVD)
51680 
51681 #define A_NCSI_MACB_TX_FRAMES_OK 0x1a140
51682 
51683 #define S_TXFRAMESOK    0
51684 #define M_TXFRAMESOK    0xffffffU
51685 #define V_TXFRAMESOK(x) ((x) << S_TXFRAMESOK)
51686 #define G_TXFRAMESOK(x) (((x) >> S_TXFRAMESOK) & M_TXFRAMESOK)
51687 
51688 #define A_NCSI_MACB_SINGLE_COL_FRAMES 0x1a144
51689 
51690 #define S_SINGLECOLTXFRAMES    0
51691 #define M_SINGLECOLTXFRAMES    0xffffU
51692 #define V_SINGLECOLTXFRAMES(x) ((x) << S_SINGLECOLTXFRAMES)
51693 #define G_SINGLECOLTXFRAMES(x) (((x) >> S_SINGLECOLTXFRAMES) & M_SINGLECOLTXFRAMES)
51694 
51695 #define A_NCSI_MACB_MUL_COL_FRAMES 0x1a148
51696 
51697 #define S_MULCOLTXFRAMES    0
51698 #define M_MULCOLTXFRAMES    0xffffU
51699 #define V_MULCOLTXFRAMES(x) ((x) << S_MULCOLTXFRAMES)
51700 #define G_MULCOLTXFRAMES(x) (((x) >> S_MULCOLTXFRAMES) & M_MULCOLTXFRAMES)
51701 
51702 #define A_NCSI_MACB_RX_FRAMES_OK 0x1a14c
51703 
51704 #define S_RXFRAMESOK    0
51705 #define M_RXFRAMESOK    0xffffffU
51706 #define V_RXFRAMESOK(x) ((x) << S_RXFRAMESOK)
51707 #define G_RXFRAMESOK(x) (((x) >> S_RXFRAMESOK) & M_RXFRAMESOK)
51708 
51709 #define A_NCSI_MACB_FCS_ERR 0x1a150
51710 
51711 #define S_RXFCSERR    0
51712 #define M_RXFCSERR    0xffU
51713 #define V_RXFCSERR(x) ((x) << S_RXFCSERR)
51714 #define G_RXFCSERR(x) (((x) >> S_RXFCSERR) & M_RXFCSERR)
51715 
51716 #define A_NCSI_MACB_ALIGN_ERR 0x1a154
51717 
51718 #define S_RXALIGNERR    0
51719 #define M_RXALIGNERR    0xffU
51720 #define V_RXALIGNERR(x) ((x) << S_RXALIGNERR)
51721 #define G_RXALIGNERR(x) (((x) >> S_RXALIGNERR) & M_RXALIGNERR)
51722 
51723 #define A_NCSI_MACB_DEF_TX_FRAMES 0x1a158
51724 
51725 #define S_TXDEFERREDFRAMES    0
51726 #define M_TXDEFERREDFRAMES    0xffffU
51727 #define V_TXDEFERREDFRAMES(x) ((x) << S_TXDEFERREDFRAMES)
51728 #define G_TXDEFERREDFRAMES(x) (((x) >> S_TXDEFERREDFRAMES) & M_TXDEFERREDFRAMES)
51729 
51730 #define A_NCSI_MACB_LATE_COL 0x1a15c
51731 
51732 #define S_LATECOLLISIONS    0
51733 #define M_LATECOLLISIONS    0xffffU
51734 #define V_LATECOLLISIONS(x) ((x) << S_LATECOLLISIONS)
51735 #define G_LATECOLLISIONS(x) (((x) >> S_LATECOLLISIONS) & M_LATECOLLISIONS)
51736 
51737 #define A_NCSI_MACB_EXCESSIVE_COL 0x1a160
51738 
51739 #define S_EXCESSIVECOLLISIONS    0
51740 #define M_EXCESSIVECOLLISIONS    0xffU
51741 #define V_EXCESSIVECOLLISIONS(x) ((x) << S_EXCESSIVECOLLISIONS)
51742 #define G_EXCESSIVECOLLISIONS(x) (((x) >> S_EXCESSIVECOLLISIONS) & M_EXCESSIVECOLLISIONS)
51743 
51744 #define A_NCSI_MACB_TX_UNDERRUN_ERR 0x1a164
51745 
51746 #define S_TXUNDERRUNERR    0
51747 #define M_TXUNDERRUNERR    0xffU
51748 #define V_TXUNDERRUNERR(x) ((x) << S_TXUNDERRUNERR)
51749 #define G_TXUNDERRUNERR(x) (((x) >> S_TXUNDERRUNERR) & M_TXUNDERRUNERR)
51750 
51751 #define A_NCSI_MACB_CARRIER_SENSE_ERR 0x1a168
51752 
51753 #define S_CARRIERSENSEERRS    0
51754 #define M_CARRIERSENSEERRS    0xffU
51755 #define V_CARRIERSENSEERRS(x) ((x) << S_CARRIERSENSEERRS)
51756 #define G_CARRIERSENSEERRS(x) (((x) >> S_CARRIERSENSEERRS) & M_CARRIERSENSEERRS)
51757 
51758 #define A_NCSI_MACB_RX_RESOURCE_ERR 0x1a16c
51759 
51760 #define S_RXRESOURCEERR    0
51761 #define M_RXRESOURCEERR    0xffffU
51762 #define V_RXRESOURCEERR(x) ((x) << S_RXRESOURCEERR)
51763 #define G_RXRESOURCEERR(x) (((x) >> S_RXRESOURCEERR) & M_RXRESOURCEERR)
51764 
51765 #define A_NCSI_MACB_RX_OVERRUN_ERR 0x1a170
51766 
51767 #define S_RXOVERRUNERRCNT    0
51768 #define M_RXOVERRUNERRCNT    0xffU
51769 #define V_RXOVERRUNERRCNT(x) ((x) << S_RXOVERRUNERRCNT)
51770 #define G_RXOVERRUNERRCNT(x) (((x) >> S_RXOVERRUNERRCNT) & M_RXOVERRUNERRCNT)
51771 
51772 #define A_NCSI_MACB_RX_SYMBOL_ERR 0x1a174
51773 
51774 #define S_RXSYMBOLERR    0
51775 #define M_RXSYMBOLERR    0xffU
51776 #define V_RXSYMBOLERR(x) ((x) << S_RXSYMBOLERR)
51777 #define G_RXSYMBOLERR(x) (((x) >> S_RXSYMBOLERR) & M_RXSYMBOLERR)
51778 
51779 #define A_NCSI_MACB_RX_OVERSIZE_FRAME 0x1a178
51780 
51781 #define S_RXOVERSIZEERR    0
51782 #define M_RXOVERSIZEERR    0xffU
51783 #define V_RXOVERSIZEERR(x) ((x) << S_RXOVERSIZEERR)
51784 #define G_RXOVERSIZEERR(x) (((x) >> S_RXOVERSIZEERR) & M_RXOVERSIZEERR)
51785 
51786 #define A_NCSI_MACB_RX_JABBER_ERR 0x1a17c
51787 
51788 #define S_RXJABBERERR    0
51789 #define M_RXJABBERERR    0xffU
51790 #define V_RXJABBERERR(x) ((x) << S_RXJABBERERR)
51791 #define G_RXJABBERERR(x) (((x) >> S_RXJABBERERR) & M_RXJABBERERR)
51792 
51793 #define A_NCSI_MACB_RX_UNDERSIZE_FRAME 0x1a180
51794 
51795 #define S_RXUNDERSIZEFR    0
51796 #define M_RXUNDERSIZEFR    0xffU
51797 #define V_RXUNDERSIZEFR(x) ((x) << S_RXUNDERSIZEFR)
51798 #define G_RXUNDERSIZEFR(x) (((x) >> S_RXUNDERSIZEFR) & M_RXUNDERSIZEFR)
51799 
51800 #define A_NCSI_MACB_SQE_TEST_ERR 0x1a184
51801 
51802 #define S_SQETESTERR    0
51803 #define M_SQETESTERR    0xffU
51804 #define V_SQETESTERR(x) ((x) << S_SQETESTERR)
51805 #define G_SQETESTERR(x) (((x) >> S_SQETESTERR) & M_SQETESTERR)
51806 
51807 #define A_NCSI_MACB_LENGTH_ERR 0x1a188
51808 
51809 #define S_LENGTHERR    0
51810 #define M_LENGTHERR    0xffU
51811 #define V_LENGTHERR(x) ((x) << S_LENGTHERR)
51812 #define G_LENGTHERR(x) (((x) >> S_LENGTHERR) & M_LENGTHERR)
51813 
51814 #define A_NCSI_MACB_TX_PAUSE_FRAMES 0x1a18c
51815 
51816 #define S_TXPAUSEFRAMES    0
51817 #define M_TXPAUSEFRAMES    0xffffU
51818 #define V_TXPAUSEFRAMES(x) ((x) << S_TXPAUSEFRAMES)
51819 #define G_TXPAUSEFRAMES(x) (((x) >> S_TXPAUSEFRAMES) & M_TXPAUSEFRAMES)
51820 
51821 #define A_NCSI_MACB_HASH_LOW 0x1a190
51822 #define A_NCSI_MACB_HASH_HIGH 0x1a194
51823 #define A_NCSI_MACB_SPECIFIC_1_LOW 0x1a198
51824 #define A_NCSI_MACB_SPECIFIC_1_HIGH 0x1a19c
51825 
51826 #define S_MATCHHIGH    0
51827 #define M_MATCHHIGH    0xffffU
51828 #define V_MATCHHIGH(x) ((x) << S_MATCHHIGH)
51829 #define G_MATCHHIGH(x) (((x) >> S_MATCHHIGH) & M_MATCHHIGH)
51830 
51831 #define A_NCSI_MACB_SPECIFIC_2_LOW 0x1a1a0
51832 #define A_NCSI_MACB_SPECIFIC_2_HIGH 0x1a1a4
51833 #define A_NCSI_MACB_SPECIFIC_3_LOW 0x1a1a8
51834 #define A_NCSI_MACB_SPECIFIC_3_HIGH 0x1a1ac
51835 #define A_NCSI_MACB_SPECIFIC_4_LOW 0x1a1b0
51836 #define A_NCSI_MACB_SPECIFIC_4_HIGH 0x1a1b4
51837 #define A_NCSI_MACB_TYPE_ID 0x1a1b8
51838 
51839 #define S_TYPEID    0
51840 #define M_TYPEID    0xffffU
51841 #define V_TYPEID(x) ((x) << S_TYPEID)
51842 #define G_TYPEID(x) (((x) >> S_TYPEID) & M_TYPEID)
51843 
51844 #define A_NCSI_MACB_TX_PAUSE_QUANTUM 0x1a1bc
51845 
51846 #define S_TXPAUSEQUANTUM    0
51847 #define M_TXPAUSEQUANTUM    0xffffU
51848 #define V_TXPAUSEQUANTUM(x) ((x) << S_TXPAUSEQUANTUM)
51849 #define G_TXPAUSEQUANTUM(x) (((x) >> S_TXPAUSEQUANTUM) & M_TXPAUSEQUANTUM)
51850 
51851 #define A_NCSI_MACB_USER_IO 0x1a1c0
51852 
51853 #define S_USERPROGINPUT    16
51854 #define M_USERPROGINPUT    0xffffU
51855 #define V_USERPROGINPUT(x) ((x) << S_USERPROGINPUT)
51856 #define G_USERPROGINPUT(x) (((x) >> S_USERPROGINPUT) & M_USERPROGINPUT)
51857 
51858 #define S_USERPROGOUTPUT    0
51859 #define M_USERPROGOUTPUT    0xffffU
51860 #define V_USERPROGOUTPUT(x) ((x) << S_USERPROGOUTPUT)
51861 #define G_USERPROGOUTPUT(x) (((x) >> S_USERPROGOUTPUT) & M_USERPROGOUTPUT)
51862 
51863 #define A_NCSI_MACB_WOL_CFG 0x1a1c4
51864 
51865 #define S_MCHASHEN    19
51866 #define V_MCHASHEN(x) ((x) << S_MCHASHEN)
51867 #define F_MCHASHEN    V_MCHASHEN(1U)
51868 
51869 #define S_SPECIFIC1EN    18
51870 #define V_SPECIFIC1EN(x) ((x) << S_SPECIFIC1EN)
51871 #define F_SPECIFIC1EN    V_SPECIFIC1EN(1U)
51872 
51873 #define S_ARPEN    17
51874 #define V_ARPEN(x) ((x) << S_ARPEN)
51875 #define F_ARPEN    V_ARPEN(1U)
51876 
51877 #define S_MAGICPKTEN    16
51878 #define V_MAGICPKTEN(x) ((x) << S_MAGICPKTEN)
51879 #define F_MAGICPKTEN    V_MAGICPKTEN(1U)
51880 
51881 #define S_ARPIPADDR    0
51882 #define M_ARPIPADDR    0xffffU
51883 #define V_ARPIPADDR(x) ((x) << S_ARPIPADDR)
51884 #define G_ARPIPADDR(x) (((x) >> S_ARPIPADDR) & M_ARPIPADDR)
51885 
51886 #define A_NCSI_MACB_REV_STATUS 0x1a1fc
51887 
51888 #define S_PARTREF    16
51889 #define M_PARTREF    0xffffU
51890 #define V_PARTREF(x) ((x) << S_PARTREF)
51891 #define G_PARTREF(x) (((x) >> S_PARTREF) & M_PARTREF)
51892 
51893 #define S_DESREV    0
51894 #define M_DESREV    0xffffU
51895 #define V_DESREV(x) ((x) << S_DESREV)
51896 #define G_DESREV(x) (((x) >> S_DESREV) & M_DESREV)
51897 
51898 #define A_NCSI_TX_CTRL 0x1a200
51899 
51900 #define S_T7_TXEN    0
51901 #define V_T7_TXEN(x) ((x) << S_T7_TXEN)
51902 #define F_T7_TXEN    V_T7_TXEN(1U)
51903 
51904 #define A_NCSI_TX_CFG 0x1a204
51905 #define A_NCSI_TX_PAUSE_QUANTA 0x1a208
51906 #define A_NCSI_RX_CTRL 0x1a20c
51907 #define A_NCSI_RX_CFG 0x1a210
51908 #define A_NCSI_RX_HASH_LOW 0x1a214
51909 #define A_NCSI_RX_HASH_HIGH 0x1a218
51910 #define A_NCSI_RX_EXACT_MATCH_LOW_1 0x1a21c
51911 #define A_NCSI_RX_EXACT_MATCH_HIGH_1 0x1a220
51912 #define A_NCSI_RX_EXACT_MATCH_LOW_2 0x1a224
51913 #define A_NCSI_RX_EXACT_MATCH_HIGH_2 0x1a228
51914 #define A_NCSI_RX_EXACT_MATCH_LOW_3 0x1a22c
51915 #define A_NCSI_RX_EXACT_MATCH_HIGH_3 0x1a230
51916 #define A_NCSI_RX_EXACT_MATCH_LOW_4 0x1a234
51917 #define A_NCSI_RX_EXACT_MATCH_HIGH_4 0x1a238
51918 #define A_NCSI_RX_EXACT_MATCH_LOW_5 0x1a23c
51919 #define A_NCSI_RX_EXACT_MATCH_HIGH_5 0x1a240
51920 #define A_NCSI_RX_EXACT_MATCH_LOW_6 0x1a244
51921 #define A_NCSI_RX_EXACT_MATCH_HIGH_6 0x1a248
51922 #define A_NCSI_RX_EXACT_MATCH_LOW_7 0x1a24c
51923 #define A_NCSI_RX_EXACT_MATCH_HIGH_7 0x1a250
51924 #define A_NCSI_RX_EXACT_MATCH_LOW_8 0x1a254
51925 #define A_NCSI_RX_EXACT_MATCH_HIGH_8 0x1a258
51926 #define A_NCSI_RX_TYPE_MATCH_1 0x1a25c
51927 #define A_NCSI_RX_TYPE_MATCH_2 0x1a260
51928 #define A_NCSI_RX_TYPE_MATCH_3 0x1a264
51929 #define A_NCSI_RX_TYPE_MATCH_4 0x1a268
51930 #define A_NCSI_INT_STATUS 0x1a26c
51931 #define A_NCSI_XGM_INT_MASK 0x1a270
51932 #define A_NCSI_XGM_INT_ENABLE 0x1a274
51933 #define A_NCSI_XGM_INT_DISABLE 0x1a278
51934 #define A_NCSI_TX_PAUSE_TIMER 0x1a27c
51935 #define A_NCSI_STAT_CTRL 0x1a280
51936 #define A_NCSI_RXFIFO_CFG 0x1a284
51937 
51938 #define S_RXFIFO_EMPTY    31
51939 #define V_RXFIFO_EMPTY(x) ((x) << S_RXFIFO_EMPTY)
51940 #define F_RXFIFO_EMPTY    V_RXFIFO_EMPTY(1U)
51941 
51942 #define S_RXFIFO_FULL    30
51943 #define V_RXFIFO_FULL(x) ((x) << S_RXFIFO_FULL)
51944 #define F_RXFIFO_FULL    V_RXFIFO_FULL(1U)
51945 
51946 #define S_RXFIFOPAUSEHWM    17
51947 #define M_RXFIFOPAUSEHWM    0xfffU
51948 #define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM)
51949 #define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM)
51950 
51951 #define S_RXFIFOPAUSELWM    5
51952 #define M_RXFIFOPAUSELWM    0xfffU
51953 #define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM)
51954 #define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM)
51955 
51956 #define S_FORCEDPAUSE    4
51957 #define V_FORCEDPAUSE(x) ((x) << S_FORCEDPAUSE)
51958 #define F_FORCEDPAUSE    V_FORCEDPAUSE(1U)
51959 
51960 #define S_EXTERNLOOPBACK    3
51961 #define V_EXTERNLOOPBACK(x) ((x) << S_EXTERNLOOPBACK)
51962 #define F_EXTERNLOOPBACK    V_EXTERNLOOPBACK(1U)
51963 
51964 #define S_RXBYTESWAP    2
51965 #define V_RXBYTESWAP(x) ((x) << S_RXBYTESWAP)
51966 #define F_RXBYTESWAP    V_RXBYTESWAP(1U)
51967 
51968 #define S_RXSTRFRWRD    1
51969 #define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD)
51970 #define F_RXSTRFRWRD    V_RXSTRFRWRD(1U)
51971 
51972 #define S_DISERRFRAMES    0
51973 #define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES)
51974 #define F_DISERRFRAMES    V_DISERRFRAMES(1U)
51975 
51976 #define A_NCSI_TXFIFO_CFG 0x1a288
51977 
51978 #define S_T7_TXFIFO_EMPTY    31
51979 #define V_T7_TXFIFO_EMPTY(x) ((x) << S_T7_TXFIFO_EMPTY)
51980 #define F_T7_TXFIFO_EMPTY    V_T7_TXFIFO_EMPTY(1U)
51981 
51982 #define S_T7_TXFIFO_FULL    30
51983 #define V_T7_TXFIFO_FULL(x) ((x) << S_T7_TXFIFO_FULL)
51984 #define F_T7_TXFIFO_FULL    V_T7_TXFIFO_FULL(1U)
51985 
51986 #define S_UNDERUNFIX    22
51987 #define V_UNDERUNFIX(x) ((x) << S_UNDERUNFIX)
51988 #define F_UNDERUNFIX    V_UNDERUNFIX(1U)
51989 
51990 #define S_ENDROPPKT    21
51991 #define V_ENDROPPKT(x) ((x) << S_ENDROPPKT)
51992 #define F_ENDROPPKT    V_ENDROPPKT(1U)
51993 
51994 #define S_TXIPG    13
51995 #define M_TXIPG    0xffU
51996 #define V_TXIPG(x) ((x) << S_TXIPG)
51997 #define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG)
51998 
51999 #define S_TXFIFOTHRESH    4
52000 #define M_TXFIFOTHRESH    0x1ffU
52001 #define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH)
52002 #define G_TXFIFOTHRESH(x) (((x) >> S_TXFIFOTHRESH) & M_TXFIFOTHRESH)
52003 
52004 #define S_INTERNLOOPBACK    3
52005 #define V_INTERNLOOPBACK(x) ((x) << S_INTERNLOOPBACK)
52006 #define F_INTERNLOOPBACK    V_INTERNLOOPBACK(1U)
52007 
52008 #define S_TXBYTESWAP    2
52009 #define V_TXBYTESWAP(x) ((x) << S_TXBYTESWAP)
52010 #define F_TXBYTESWAP    V_TXBYTESWAP(1U)
52011 
52012 #define S_DISCRC    1
52013 #define V_DISCRC(x) ((x) << S_DISCRC)
52014 #define F_DISCRC    V_DISCRC(1U)
52015 
52016 #define S_DISPREAMBLE    0
52017 #define V_DISPREAMBLE(x) ((x) << S_DISPREAMBLE)
52018 #define F_DISPREAMBLE    V_DISPREAMBLE(1U)
52019 
52020 #define A_NCSI_SLOW_TIMER 0x1a28c
52021 
52022 #define S_PAUSESLOWTIMEREN    31
52023 #define V_PAUSESLOWTIMEREN(x) ((x) << S_PAUSESLOWTIMEREN)
52024 #define F_PAUSESLOWTIMEREN    V_PAUSESLOWTIMEREN(1U)
52025 
52026 #define S_PAUSESLOWTIMER    0
52027 #define M_PAUSESLOWTIMER    0xfffffU
52028 #define V_PAUSESLOWTIMER(x) ((x) << S_PAUSESLOWTIMER)
52029 #define G_PAUSESLOWTIMER(x) (((x) >> S_PAUSESLOWTIMER) & M_PAUSESLOWTIMER)
52030 
52031 #define A_NCSI_PAUSE_TIMER 0x1a290
52032 
52033 #define S_PAUSETIMER    0
52034 #define M_PAUSETIMER    0xfffffU
52035 #define V_PAUSETIMER(x) ((x) << S_PAUSETIMER)
52036 #define G_PAUSETIMER(x) (((x) >> S_PAUSETIMER) & M_PAUSETIMER)
52037 
52038 #define A_NCSI_XAUI_PCS_TEST 0x1a294
52039 
52040 #define S_TESTPATTERN    1
52041 #define M_TESTPATTERN    0x3U
52042 #define V_TESTPATTERN(x) ((x) << S_TESTPATTERN)
52043 #define G_TESTPATTERN(x) (((x) >> S_TESTPATTERN) & M_TESTPATTERN)
52044 
52045 #define S_ENTEST    0
52046 #define V_ENTEST(x) ((x) << S_ENTEST)
52047 #define F_ENTEST    V_ENTEST(1U)
52048 
52049 #define A_NCSI_RGMII_CTRL 0x1a298
52050 
52051 #define S_PHALIGNFIFOTHRESH    1
52052 #define M_PHALIGNFIFOTHRESH    0x3U
52053 #define V_PHALIGNFIFOTHRESH(x) ((x) << S_PHALIGNFIFOTHRESH)
52054 #define G_PHALIGNFIFOTHRESH(x) (((x) >> S_PHALIGNFIFOTHRESH) & M_PHALIGNFIFOTHRESH)
52055 
52056 #define S_TXCLK90SHIFT    0
52057 #define V_TXCLK90SHIFT(x) ((x) << S_TXCLK90SHIFT)
52058 #define F_TXCLK90SHIFT    V_TXCLK90SHIFT(1U)
52059 
52060 #define A_NCSI_RGMII_IMP 0x1a29c
52061 
52062 #define S_CALRESET    8
52063 #define V_CALRESET(x) ((x) << S_CALRESET)
52064 #define F_CALRESET    V_CALRESET(1U)
52065 
52066 #define S_CALUPDATE    7
52067 #define V_CALUPDATE(x) ((x) << S_CALUPDATE)
52068 #define F_CALUPDATE    V_CALUPDATE(1U)
52069 
52070 #define S_IMPSETUPDATE    6
52071 #define V_IMPSETUPDATE(x) ((x) << S_IMPSETUPDATE)
52072 #define F_IMPSETUPDATE    V_IMPSETUPDATE(1U)
52073 
52074 #define S_RGMIIIMPPD    3
52075 #define M_RGMIIIMPPD    0x7U
52076 #define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD)
52077 #define G_RGMIIIMPPD(x) (((x) >> S_RGMIIIMPPD) & M_RGMIIIMPPD)
52078 
52079 #define S_RGMIIIMPPU    0
52080 #define M_RGMIIIMPPU    0x7U
52081 #define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU)
52082 #define G_RGMIIIMPPU(x) (((x) >> S_RGMIIIMPPU) & M_RGMIIIMPPU)
52083 
52084 #define A_NCSI_RX_MAX_PKT_SIZE 0x1a2a8
52085 
52086 #define S_RXMAXFRAMERSIZE    17
52087 #define M_RXMAXFRAMERSIZE    0x3fffU
52088 #define V_RXMAXFRAMERSIZE(x) ((x) << S_RXMAXFRAMERSIZE)
52089 #define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE)
52090 
52091 #define S_RXENERRORGATHER    16
52092 #define V_RXENERRORGATHER(x) ((x) << S_RXENERRORGATHER)
52093 #define F_RXENERRORGATHER    V_RXENERRORGATHER(1U)
52094 
52095 #define S_RXENSINGLEFLIT    15
52096 #define V_RXENSINGLEFLIT(x) ((x) << S_RXENSINGLEFLIT)
52097 #define F_RXENSINGLEFLIT    V_RXENSINGLEFLIT(1U)
52098 
52099 #define S_RXENFRAMER    14
52100 #define V_RXENFRAMER(x) ((x) << S_RXENFRAMER)
52101 #define F_RXENFRAMER    V_RXENFRAMER(1U)
52102 
52103 #define S_RXMAXPKTSIZE    0
52104 #define M_RXMAXPKTSIZE    0x3fffU
52105 #define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE)
52106 #define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE)
52107 
52108 #define A_NCSI_RESET_CTRL 0x1a2ac
52109 
52110 #define S_XGMAC_STOP_EN    4
52111 #define V_XGMAC_STOP_EN(x) ((x) << S_XGMAC_STOP_EN)
52112 #define F_XGMAC_STOP_EN    V_XGMAC_STOP_EN(1U)
52113 
52114 #define S_XG2G_RESET_    3
52115 #define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_)
52116 #define F_XG2G_RESET_    V_XG2G_RESET_(1U)
52117 
52118 #define S_RGMII_RESET_    2
52119 #define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_)
52120 #define F_RGMII_RESET_    V_RGMII_RESET_(1U)
52121 
52122 #define S_PCS_RESET_    1
52123 #define V_PCS_RESET_(x) ((x) << S_PCS_RESET_)
52124 #define F_PCS_RESET_    V_PCS_RESET_(1U)
52125 
52126 #define S_MAC_RESET_    0
52127 #define V_MAC_RESET_(x) ((x) << S_MAC_RESET_)
52128 #define F_MAC_RESET_    V_MAC_RESET_(1U)
52129 
52130 #define A_NCSI_XAUI1G_CTRL 0x1a2b0
52131 
52132 #define S_XAUI1GLINKID    0
52133 #define M_XAUI1GLINKID    0x3U
52134 #define V_XAUI1GLINKID(x) ((x) << S_XAUI1GLINKID)
52135 #define G_XAUI1GLINKID(x) (((x) >> S_XAUI1GLINKID) & M_XAUI1GLINKID)
52136 
52137 #define A_NCSI_SERDES_LANE_CTRL 0x1a2b4
52138 
52139 #define S_LANEREVERSAL    8
52140 #define V_LANEREVERSAL(x) ((x) << S_LANEREVERSAL)
52141 #define F_LANEREVERSAL    V_LANEREVERSAL(1U)
52142 
52143 #define S_TXPOLARITY    4
52144 #define M_TXPOLARITY    0xfU
52145 #define V_TXPOLARITY(x) ((x) << S_TXPOLARITY)
52146 #define G_TXPOLARITY(x) (((x) >> S_TXPOLARITY) & M_TXPOLARITY)
52147 
52148 #define S_RXPOLARITY    0
52149 #define M_RXPOLARITY    0xfU
52150 #define V_RXPOLARITY(x) ((x) << S_RXPOLARITY)
52151 #define G_RXPOLARITY(x) (((x) >> S_RXPOLARITY) & M_RXPOLARITY)
52152 
52153 #define A_NCSI_PORT_CFG 0x1a2b8
52154 
52155 #define S_NCSI_SAFESPEEDCHANGE    4
52156 #define V_NCSI_SAFESPEEDCHANGE(x) ((x) << S_NCSI_SAFESPEEDCHANGE)
52157 #define F_NCSI_SAFESPEEDCHANGE    V_NCSI_SAFESPEEDCHANGE(1U)
52158 
52159 #define S_NCSI_CLKDIVRESET_    3
52160 #define V_NCSI_CLKDIVRESET_(x) ((x) << S_NCSI_CLKDIVRESET_)
52161 #define F_NCSI_CLKDIVRESET_    V_NCSI_CLKDIVRESET_(1U)
52162 
52163 #define S_NCSI_PORTSPEED    1
52164 #define M_NCSI_PORTSPEED    0x3U
52165 #define V_NCSI_PORTSPEED(x) ((x) << S_NCSI_PORTSPEED)
52166 #define G_NCSI_PORTSPEED(x) (((x) >> S_NCSI_PORTSPEED) & M_NCSI_PORTSPEED)
52167 
52168 #define S_NCSI_ENRGMII    0
52169 #define V_NCSI_ENRGMII(x) ((x) << S_NCSI_ENRGMII)
52170 #define F_NCSI_ENRGMII    V_NCSI_ENRGMII(1U)
52171 
52172 #define A_NCSI_EPIO_DATA0 0x1a2c0
52173 #define A_NCSI_EPIO_DATA1 0x1a2c4
52174 #define A_NCSI_EPIO_DATA2 0x1a2c8
52175 #define A_NCSI_EPIO_DATA3 0x1a2cc
52176 #define A_NCSI_EPIO_OP 0x1a2d0
52177 
52178 #define S_PIO_READY    31
52179 #define V_PIO_READY(x) ((x) << S_PIO_READY)
52180 #define F_PIO_READY    V_PIO_READY(1U)
52181 
52182 #define S_PIO_WRRD    24
52183 #define V_PIO_WRRD(x) ((x) << S_PIO_WRRD)
52184 #define F_PIO_WRRD    V_PIO_WRRD(1U)
52185 
52186 #define S_PIO_ADDRESS    0
52187 #define M_PIO_ADDRESS    0xffU
52188 #define V_PIO_ADDRESS(x) ((x) << S_PIO_ADDRESS)
52189 #define G_PIO_ADDRESS(x) (((x) >> S_PIO_ADDRESS) & M_PIO_ADDRESS)
52190 
52191 #define A_NCSI_XGMAC0_INT_ENABLE 0x1a2d4
52192 
52193 #define S_XAUIPCSDECERR    24
52194 #define V_XAUIPCSDECERR(x) ((x) << S_XAUIPCSDECERR)
52195 #define F_XAUIPCSDECERR    V_XAUIPCSDECERR(1U)
52196 
52197 #define S_RGMIIRXFIFOOVERFLOW    23
52198 #define V_RGMIIRXFIFOOVERFLOW(x) ((x) << S_RGMIIRXFIFOOVERFLOW)
52199 #define F_RGMIIRXFIFOOVERFLOW    V_RGMIIRXFIFOOVERFLOW(1U)
52200 
52201 #define S_RGMIIRXFIFOUNDERFLOW    22
52202 #define V_RGMIIRXFIFOUNDERFLOW(x) ((x) << S_RGMIIRXFIFOUNDERFLOW)
52203 #define F_RGMIIRXFIFOUNDERFLOW    V_RGMIIRXFIFOUNDERFLOW(1U)
52204 
52205 #define S_RXPKTSIZEERROR    21
52206 #define V_RXPKTSIZEERROR(x) ((x) << S_RXPKTSIZEERROR)
52207 #define F_RXPKTSIZEERROR    V_RXPKTSIZEERROR(1U)
52208 
52209 #define S_WOLPATDETECTED    20
52210 #define V_WOLPATDETECTED(x) ((x) << S_WOLPATDETECTED)
52211 #define F_WOLPATDETECTED    V_WOLPATDETECTED(1U)
52212 
52213 #define S_T7_TXFIFO_PRTY_ERR    17
52214 #define M_T7_TXFIFO_PRTY_ERR    0x7U
52215 #define V_T7_TXFIFO_PRTY_ERR(x) ((x) << S_T7_TXFIFO_PRTY_ERR)
52216 #define G_T7_TXFIFO_PRTY_ERR(x) (((x) >> S_T7_TXFIFO_PRTY_ERR) & M_T7_TXFIFO_PRTY_ERR)
52217 
52218 #define S_T7_RXFIFO_PRTY_ERR    14
52219 #define M_T7_RXFIFO_PRTY_ERR    0x7U
52220 #define V_T7_RXFIFO_PRTY_ERR(x) ((x) << S_T7_RXFIFO_PRTY_ERR)
52221 #define G_T7_RXFIFO_PRTY_ERR(x) (((x) >> S_T7_RXFIFO_PRTY_ERR) & M_T7_RXFIFO_PRTY_ERR)
52222 
52223 #define S_TXFIFO_UNDERRUN    13
52224 #define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN)
52225 #define F_TXFIFO_UNDERRUN    V_TXFIFO_UNDERRUN(1U)
52226 
52227 #define S_RXFIFO_OVERFLOW    12
52228 #define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW)
52229 #define F_RXFIFO_OVERFLOW    V_RXFIFO_OVERFLOW(1U)
52230 
52231 #define S_SERDESBISTERR    8
52232 #define M_SERDESBISTERR    0xfU
52233 #define V_SERDESBISTERR(x) ((x) << S_SERDESBISTERR)
52234 #define G_SERDESBISTERR(x) (((x) >> S_SERDESBISTERR) & M_SERDESBISTERR)
52235 
52236 #define S_SERDESLOWSIGCHANGE    4
52237 #define M_SERDESLOWSIGCHANGE    0xfU
52238 #define V_SERDESLOWSIGCHANGE(x) ((x) << S_SERDESLOWSIGCHANGE)
52239 #define G_SERDESLOWSIGCHANGE(x) (((x) >> S_SERDESLOWSIGCHANGE) & M_SERDESLOWSIGCHANGE)
52240 
52241 #define S_XAUIPCSCTCERR    3
52242 #define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR)
52243 #define F_XAUIPCSCTCERR    V_XAUIPCSCTCERR(1U)
52244 
52245 #define S_XAUIPCSALIGNCHANGE    2
52246 #define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE)
52247 #define F_XAUIPCSALIGNCHANGE    V_XAUIPCSALIGNCHANGE(1U)
52248 
52249 #define S_RGMIILINKSTSCHANGE    1
52250 #define V_RGMIILINKSTSCHANGE(x) ((x) << S_RGMIILINKSTSCHANGE)
52251 #define F_RGMIILINKSTSCHANGE    V_RGMIILINKSTSCHANGE(1U)
52252 
52253 #define S_T7_XGM_INT    0
52254 #define V_T7_XGM_INT(x) ((x) << S_T7_XGM_INT)
52255 #define F_T7_XGM_INT    V_T7_XGM_INT(1U)
52256 
52257 #define A_NCSI_XGMAC0_INT_CAUSE 0x1a2d8
52258 #define A_NCSI_XAUI_ACT_CTRL 0x1a2dc
52259 #define A_NCSI_SERDES_CTRL0 0x1a2e0
52260 
52261 #define S_INTSERLPBK3    27
52262 #define V_INTSERLPBK3(x) ((x) << S_INTSERLPBK3)
52263 #define F_INTSERLPBK3    V_INTSERLPBK3(1U)
52264 
52265 #define S_INTSERLPBK2    26
52266 #define V_INTSERLPBK2(x) ((x) << S_INTSERLPBK2)
52267 #define F_INTSERLPBK2    V_INTSERLPBK2(1U)
52268 
52269 #define S_INTSERLPBK1    25
52270 #define V_INTSERLPBK1(x) ((x) << S_INTSERLPBK1)
52271 #define F_INTSERLPBK1    V_INTSERLPBK1(1U)
52272 
52273 #define S_INTSERLPBK0    24
52274 #define V_INTSERLPBK0(x) ((x) << S_INTSERLPBK0)
52275 #define F_INTSERLPBK0    V_INTSERLPBK0(1U)
52276 
52277 #define S_RESET3    23
52278 #define V_RESET3(x) ((x) << S_RESET3)
52279 #define F_RESET3    V_RESET3(1U)
52280 
52281 #define S_RESET2    22
52282 #define V_RESET2(x) ((x) << S_RESET2)
52283 #define F_RESET2    V_RESET2(1U)
52284 
52285 #define S_RESET1    21
52286 #define V_RESET1(x) ((x) << S_RESET1)
52287 #define F_RESET1    V_RESET1(1U)
52288 
52289 #define S_RESET0    20
52290 #define V_RESET0(x) ((x) << S_RESET0)
52291 #define F_RESET0    V_RESET0(1U)
52292 
52293 #define S_PWRDN3    19
52294 #define V_PWRDN3(x) ((x) << S_PWRDN3)
52295 #define F_PWRDN3    V_PWRDN3(1U)
52296 
52297 #define S_PWRDN2    18
52298 #define V_PWRDN2(x) ((x) << S_PWRDN2)
52299 #define F_PWRDN2    V_PWRDN2(1U)
52300 
52301 #define S_PWRDN1    17
52302 #define V_PWRDN1(x) ((x) << S_PWRDN1)
52303 #define F_PWRDN1    V_PWRDN1(1U)
52304 
52305 #define S_PWRDN0    16
52306 #define V_PWRDN0(x) ((x) << S_PWRDN0)
52307 #define F_PWRDN0    V_PWRDN0(1U)
52308 
52309 #define S_RESETPLL23    15
52310 #define V_RESETPLL23(x) ((x) << S_RESETPLL23)
52311 #define F_RESETPLL23    V_RESETPLL23(1U)
52312 
52313 #define S_RESETPLL01    14
52314 #define V_RESETPLL01(x) ((x) << S_RESETPLL01)
52315 #define F_RESETPLL01    V_RESETPLL01(1U)
52316 
52317 #define S_PW23    12
52318 #define M_PW23    0x3U
52319 #define V_PW23(x) ((x) << S_PW23)
52320 #define G_PW23(x) (((x) >> S_PW23) & M_PW23)
52321 
52322 #define S_PW01    10
52323 #define M_PW01    0x3U
52324 #define V_PW01(x) ((x) << S_PW01)
52325 #define G_PW01(x) (((x) >> S_PW01) & M_PW01)
52326 
52327 #define S_DEQ    6
52328 #define M_DEQ    0xfU
52329 #define V_DEQ(x) ((x) << S_DEQ)
52330 #define G_DEQ(x) (((x) >> S_DEQ) & M_DEQ)
52331 
52332 #define S_DTX    2
52333 #define M_DTX    0xfU
52334 #define V_DTX(x) ((x) << S_DTX)
52335 #define G_DTX(x) (((x) >> S_DTX) & M_DTX)
52336 
52337 #define S_LODRV    1
52338 #define V_LODRV(x) ((x) << S_LODRV)
52339 #define F_LODRV    V_LODRV(1U)
52340 
52341 #define S_HIDRV    0
52342 #define V_HIDRV(x) ((x) << S_HIDRV)
52343 #define F_HIDRV    V_HIDRV(1U)
52344 
52345 #define A_NCSI_SERDES_CTRL1 0x1a2e4
52346 
52347 #define S_FMOFFSET3    19
52348 #define M_FMOFFSET3    0x1fU
52349 #define V_FMOFFSET3(x) ((x) << S_FMOFFSET3)
52350 #define G_FMOFFSET3(x) (((x) >> S_FMOFFSET3) & M_FMOFFSET3)
52351 
52352 #define S_FMOFFSETEN3    18
52353 #define V_FMOFFSETEN3(x) ((x) << S_FMOFFSETEN3)
52354 #define F_FMOFFSETEN3    V_FMOFFSETEN3(1U)
52355 
52356 #define S_FMOFFSET2    13
52357 #define M_FMOFFSET2    0x1fU
52358 #define V_FMOFFSET2(x) ((x) << S_FMOFFSET2)
52359 #define G_FMOFFSET2(x) (((x) >> S_FMOFFSET2) & M_FMOFFSET2)
52360 
52361 #define S_FMOFFSETEN2    12
52362 #define V_FMOFFSETEN2(x) ((x) << S_FMOFFSETEN2)
52363 #define F_FMOFFSETEN2    V_FMOFFSETEN2(1U)
52364 
52365 #define S_FMOFFSET1    7
52366 #define M_FMOFFSET1    0x1fU
52367 #define V_FMOFFSET1(x) ((x) << S_FMOFFSET1)
52368 #define G_FMOFFSET1(x) (((x) >> S_FMOFFSET1) & M_FMOFFSET1)
52369 
52370 #define S_FMOFFSETEN1    6
52371 #define V_FMOFFSETEN1(x) ((x) << S_FMOFFSETEN1)
52372 #define F_FMOFFSETEN1    V_FMOFFSETEN1(1U)
52373 
52374 #define S_FMOFFSET0    1
52375 #define M_FMOFFSET0    0x1fU
52376 #define V_FMOFFSET0(x) ((x) << S_FMOFFSET0)
52377 #define G_FMOFFSET0(x) (((x) >> S_FMOFFSET0) & M_FMOFFSET0)
52378 
52379 #define S_FMOFFSETEN0    0
52380 #define V_FMOFFSETEN0(x) ((x) << S_FMOFFSETEN0)
52381 #define F_FMOFFSETEN0    V_FMOFFSETEN0(1U)
52382 
52383 #define A_NCSI_SERDES_CTRL2 0x1a2e8
52384 
52385 #define S_DNIN3    11
52386 #define V_DNIN3(x) ((x) << S_DNIN3)
52387 #define F_DNIN3    V_DNIN3(1U)
52388 
52389 #define S_UPIN3    10
52390 #define V_UPIN3(x) ((x) << S_UPIN3)
52391 #define F_UPIN3    V_UPIN3(1U)
52392 
52393 #define S_RXSLAVE3    9
52394 #define V_RXSLAVE3(x) ((x) << S_RXSLAVE3)
52395 #define F_RXSLAVE3    V_RXSLAVE3(1U)
52396 
52397 #define S_DNIN2    8
52398 #define V_DNIN2(x) ((x) << S_DNIN2)
52399 #define F_DNIN2    V_DNIN2(1U)
52400 
52401 #define S_UPIN2    7
52402 #define V_UPIN2(x) ((x) << S_UPIN2)
52403 #define F_UPIN2    V_UPIN2(1U)
52404 
52405 #define S_RXSLAVE2    6
52406 #define V_RXSLAVE2(x) ((x) << S_RXSLAVE2)
52407 #define F_RXSLAVE2    V_RXSLAVE2(1U)
52408 
52409 #define S_DNIN1    5
52410 #define V_DNIN1(x) ((x) << S_DNIN1)
52411 #define F_DNIN1    V_DNIN1(1U)
52412 
52413 #define S_UPIN1    4
52414 #define V_UPIN1(x) ((x) << S_UPIN1)
52415 #define F_UPIN1    V_UPIN1(1U)
52416 
52417 #define S_RXSLAVE1    3
52418 #define V_RXSLAVE1(x) ((x) << S_RXSLAVE1)
52419 #define F_RXSLAVE1    V_RXSLAVE1(1U)
52420 
52421 #define S_DNIN0    2
52422 #define V_DNIN0(x) ((x) << S_DNIN0)
52423 #define F_DNIN0    V_DNIN0(1U)
52424 
52425 #define S_UPIN0    1
52426 #define V_UPIN0(x) ((x) << S_UPIN0)
52427 #define F_UPIN0    V_UPIN0(1U)
52428 
52429 #define S_RXSLAVE0    0
52430 #define V_RXSLAVE0(x) ((x) << S_RXSLAVE0)
52431 #define F_RXSLAVE0    V_RXSLAVE0(1U)
52432 
52433 #define A_NCSI_SERDES_CTRL3 0x1a2ec
52434 
52435 #define S_EXTBISTCHKERRCLR3    31
52436 #define V_EXTBISTCHKERRCLR3(x) ((x) << S_EXTBISTCHKERRCLR3)
52437 #define F_EXTBISTCHKERRCLR3    V_EXTBISTCHKERRCLR3(1U)
52438 
52439 #define S_EXTBISTCHKEN3    30
52440 #define V_EXTBISTCHKEN3(x) ((x) << S_EXTBISTCHKEN3)
52441 #define F_EXTBISTCHKEN3    V_EXTBISTCHKEN3(1U)
52442 
52443 #define S_EXTBISTGENEN3    29
52444 #define V_EXTBISTGENEN3(x) ((x) << S_EXTBISTGENEN3)
52445 #define F_EXTBISTGENEN3    V_EXTBISTGENEN3(1U)
52446 
52447 #define S_EXTBISTPAT3    26
52448 #define M_EXTBISTPAT3    0x7U
52449 #define V_EXTBISTPAT3(x) ((x) << S_EXTBISTPAT3)
52450 #define G_EXTBISTPAT3(x) (((x) >> S_EXTBISTPAT3) & M_EXTBISTPAT3)
52451 
52452 #define S_EXTPARRESET3    25
52453 #define V_EXTPARRESET3(x) ((x) << S_EXTPARRESET3)
52454 #define F_EXTPARRESET3    V_EXTPARRESET3(1U)
52455 
52456 #define S_EXTPARLPBK3    24
52457 #define V_EXTPARLPBK3(x) ((x) << S_EXTPARLPBK3)
52458 #define F_EXTPARLPBK3    V_EXTPARLPBK3(1U)
52459 
52460 #define S_EXTBISTCHKERRCLR2    23
52461 #define V_EXTBISTCHKERRCLR2(x) ((x) << S_EXTBISTCHKERRCLR2)
52462 #define F_EXTBISTCHKERRCLR2    V_EXTBISTCHKERRCLR2(1U)
52463 
52464 #define S_EXTBISTCHKEN2    22
52465 #define V_EXTBISTCHKEN2(x) ((x) << S_EXTBISTCHKEN2)
52466 #define F_EXTBISTCHKEN2    V_EXTBISTCHKEN2(1U)
52467 
52468 #define S_EXTBISTGENEN2    21
52469 #define V_EXTBISTGENEN2(x) ((x) << S_EXTBISTGENEN2)
52470 #define F_EXTBISTGENEN2    V_EXTBISTGENEN2(1U)
52471 
52472 #define S_EXTBISTPAT2    18
52473 #define M_EXTBISTPAT2    0x7U
52474 #define V_EXTBISTPAT2(x) ((x) << S_EXTBISTPAT2)
52475 #define G_EXTBISTPAT2(x) (((x) >> S_EXTBISTPAT2) & M_EXTBISTPAT2)
52476 
52477 #define S_EXTPARRESET2    17
52478 #define V_EXTPARRESET2(x) ((x) << S_EXTPARRESET2)
52479 #define F_EXTPARRESET2    V_EXTPARRESET2(1U)
52480 
52481 #define S_EXTPARLPBK2    16
52482 #define V_EXTPARLPBK2(x) ((x) << S_EXTPARLPBK2)
52483 #define F_EXTPARLPBK2    V_EXTPARLPBK2(1U)
52484 
52485 #define S_EXTBISTCHKERRCLR1    15
52486 #define V_EXTBISTCHKERRCLR1(x) ((x) << S_EXTBISTCHKERRCLR1)
52487 #define F_EXTBISTCHKERRCLR1    V_EXTBISTCHKERRCLR1(1U)
52488 
52489 #define S_EXTBISTCHKEN1    14
52490 #define V_EXTBISTCHKEN1(x) ((x) << S_EXTBISTCHKEN1)
52491 #define F_EXTBISTCHKEN1    V_EXTBISTCHKEN1(1U)
52492 
52493 #define S_EXTBISTGENEN1    13
52494 #define V_EXTBISTGENEN1(x) ((x) << S_EXTBISTGENEN1)
52495 #define F_EXTBISTGENEN1    V_EXTBISTGENEN1(1U)
52496 
52497 #define S_EXTBISTPAT1    10
52498 #define M_EXTBISTPAT1    0x7U
52499 #define V_EXTBISTPAT1(x) ((x) << S_EXTBISTPAT1)
52500 #define G_EXTBISTPAT1(x) (((x) >> S_EXTBISTPAT1) & M_EXTBISTPAT1)
52501 
52502 #define S_EXTPARRESET1    9
52503 #define V_EXTPARRESET1(x) ((x) << S_EXTPARRESET1)
52504 #define F_EXTPARRESET1    V_EXTPARRESET1(1U)
52505 
52506 #define S_EXTPARLPBK1    8
52507 #define V_EXTPARLPBK1(x) ((x) << S_EXTPARLPBK1)
52508 #define F_EXTPARLPBK1    V_EXTPARLPBK1(1U)
52509 
52510 #define S_EXTBISTCHKERRCLR0    7
52511 #define V_EXTBISTCHKERRCLR0(x) ((x) << S_EXTBISTCHKERRCLR0)
52512 #define F_EXTBISTCHKERRCLR0    V_EXTBISTCHKERRCLR0(1U)
52513 
52514 #define S_EXTBISTCHKEN0    6
52515 #define V_EXTBISTCHKEN0(x) ((x) << S_EXTBISTCHKEN0)
52516 #define F_EXTBISTCHKEN0    V_EXTBISTCHKEN0(1U)
52517 
52518 #define S_EXTBISTGENEN0    5
52519 #define V_EXTBISTGENEN0(x) ((x) << S_EXTBISTGENEN0)
52520 #define F_EXTBISTGENEN0    V_EXTBISTGENEN0(1U)
52521 
52522 #define S_EXTBISTPAT0    2
52523 #define M_EXTBISTPAT0    0x7U
52524 #define V_EXTBISTPAT0(x) ((x) << S_EXTBISTPAT0)
52525 #define G_EXTBISTPAT0(x) (((x) >> S_EXTBISTPAT0) & M_EXTBISTPAT0)
52526 
52527 #define S_EXTPARRESET0    1
52528 #define V_EXTPARRESET0(x) ((x) << S_EXTPARRESET0)
52529 #define F_EXTPARRESET0    V_EXTPARRESET0(1U)
52530 
52531 #define S_EXTPARLPBK0    0
52532 #define V_EXTPARLPBK0(x) ((x) << S_EXTPARLPBK0)
52533 #define F_EXTPARLPBK0    V_EXTPARLPBK0(1U)
52534 
52535 #define A_NCSI_SERDES_STAT0 0x1a2f0
52536 
52537 #define S_EXTBISTCHKERRCNT0    4
52538 #define M_EXTBISTCHKERRCNT0    0xffffffU
52539 #define V_EXTBISTCHKERRCNT0(x) ((x) << S_EXTBISTCHKERRCNT0)
52540 #define G_EXTBISTCHKERRCNT0(x) (((x) >> S_EXTBISTCHKERRCNT0) & M_EXTBISTCHKERRCNT0)
52541 
52542 #define S_EXTBISTCHKFMD0    3
52543 #define V_EXTBISTCHKFMD0(x) ((x) << S_EXTBISTCHKFMD0)
52544 #define F_EXTBISTCHKFMD0    V_EXTBISTCHKFMD0(1U)
52545 
52546 #define S_LOWSIGFORCEEN0    2
52547 #define V_LOWSIGFORCEEN0(x) ((x) << S_LOWSIGFORCEEN0)
52548 #define F_LOWSIGFORCEEN0    V_LOWSIGFORCEEN0(1U)
52549 
52550 #define S_LOWSIGFORCEVALUE0    1
52551 #define V_LOWSIGFORCEVALUE0(x) ((x) << S_LOWSIGFORCEVALUE0)
52552 #define F_LOWSIGFORCEVALUE0    V_LOWSIGFORCEVALUE0(1U)
52553 
52554 #define S_LOWSIG0    0
52555 #define V_LOWSIG0(x) ((x) << S_LOWSIG0)
52556 #define F_LOWSIG0    V_LOWSIG0(1U)
52557 
52558 #define A_NCSI_SERDES_STAT1 0x1a2f4
52559 
52560 #define S_EXTBISTCHKERRCNT1    4
52561 #define M_EXTBISTCHKERRCNT1    0xffffffU
52562 #define V_EXTBISTCHKERRCNT1(x) ((x) << S_EXTBISTCHKERRCNT1)
52563 #define G_EXTBISTCHKERRCNT1(x) (((x) >> S_EXTBISTCHKERRCNT1) & M_EXTBISTCHKERRCNT1)
52564 
52565 #define S_EXTBISTCHKFMD1    3
52566 #define V_EXTBISTCHKFMD1(x) ((x) << S_EXTBISTCHKFMD1)
52567 #define F_EXTBISTCHKFMD1    V_EXTBISTCHKFMD1(1U)
52568 
52569 #define S_LOWSIGFORCEEN1    2
52570 #define V_LOWSIGFORCEEN1(x) ((x) << S_LOWSIGFORCEEN1)
52571 #define F_LOWSIGFORCEEN1    V_LOWSIGFORCEEN1(1U)
52572 
52573 #define S_LOWSIGFORCEVALUE1    1
52574 #define V_LOWSIGFORCEVALUE1(x) ((x) << S_LOWSIGFORCEVALUE1)
52575 #define F_LOWSIGFORCEVALUE1    V_LOWSIGFORCEVALUE1(1U)
52576 
52577 #define S_LOWSIG1    0
52578 #define V_LOWSIG1(x) ((x) << S_LOWSIG1)
52579 #define F_LOWSIG1    V_LOWSIG1(1U)
52580 
52581 #define A_NCSI_SERDES_STAT2 0x1a2f8
52582 
52583 #define S_EXTBISTCHKERRCNT2    4
52584 #define M_EXTBISTCHKERRCNT2    0xffffffU
52585 #define V_EXTBISTCHKERRCNT2(x) ((x) << S_EXTBISTCHKERRCNT2)
52586 #define G_EXTBISTCHKERRCNT2(x) (((x) >> S_EXTBISTCHKERRCNT2) & M_EXTBISTCHKERRCNT2)
52587 
52588 #define S_EXTBISTCHKFMD2    3
52589 #define V_EXTBISTCHKFMD2(x) ((x) << S_EXTBISTCHKFMD2)
52590 #define F_EXTBISTCHKFMD2    V_EXTBISTCHKFMD2(1U)
52591 
52592 #define S_LOWSIGFORCEEN2    2
52593 #define V_LOWSIGFORCEEN2(x) ((x) << S_LOWSIGFORCEEN2)
52594 #define F_LOWSIGFORCEEN2    V_LOWSIGFORCEEN2(1U)
52595 
52596 #define S_LOWSIGFORCEVALUE2    1
52597 #define V_LOWSIGFORCEVALUE2(x) ((x) << S_LOWSIGFORCEVALUE2)
52598 #define F_LOWSIGFORCEVALUE2    V_LOWSIGFORCEVALUE2(1U)
52599 
52600 #define S_LOWSIG2    0
52601 #define V_LOWSIG2(x) ((x) << S_LOWSIG2)
52602 #define F_LOWSIG2    V_LOWSIG2(1U)
52603 
52604 #define A_NCSI_SERDES_STAT3 0x1a2fc
52605 
52606 #define S_EXTBISTCHKERRCNT3    4
52607 #define M_EXTBISTCHKERRCNT3    0xffffffU
52608 #define V_EXTBISTCHKERRCNT3(x) ((x) << S_EXTBISTCHKERRCNT3)
52609 #define G_EXTBISTCHKERRCNT3(x) (((x) >> S_EXTBISTCHKERRCNT3) & M_EXTBISTCHKERRCNT3)
52610 
52611 #define S_EXTBISTCHKFMD3    3
52612 #define V_EXTBISTCHKFMD3(x) ((x) << S_EXTBISTCHKFMD3)
52613 #define F_EXTBISTCHKFMD3    V_EXTBISTCHKFMD3(1U)
52614 
52615 #define S_LOWSIGFORCEEN3    2
52616 #define V_LOWSIGFORCEEN3(x) ((x) << S_LOWSIGFORCEEN3)
52617 #define F_LOWSIGFORCEEN3    V_LOWSIGFORCEEN3(1U)
52618 
52619 #define S_LOWSIGFORCEVALUE3    1
52620 #define V_LOWSIGFORCEVALUE3(x) ((x) << S_LOWSIGFORCEVALUE3)
52621 #define F_LOWSIGFORCEVALUE3    V_LOWSIGFORCEVALUE3(1U)
52622 
52623 #define S_LOWSIG3    0
52624 #define V_LOWSIG3(x) ((x) << S_LOWSIG3)
52625 #define F_LOWSIG3    V_LOWSIG3(1U)
52626 
52627 #define A_NCSI_STAT_TX_BYTE_LOW 0x1a300
52628 #define A_NCSI_STAT_TX_BYTE_HIGH 0x1a304
52629 #define A_NCSI_STAT_TX_FRAME_LOW 0x1a308
52630 #define A_NCSI_STAT_TX_FRAME_HIGH 0x1a30c
52631 #define A_NCSI_STAT_TX_BCAST 0x1a310
52632 #define A_NCSI_STAT_TX_MCAST 0x1a314
52633 #define A_NCSI_STAT_TX_PAUSE 0x1a318
52634 #define A_NCSI_STAT_TX_64B_FRAMES 0x1a31c
52635 #define A_NCSI_STAT_TX_65_127B_FRAMES 0x1a320
52636 #define A_NCSI_STAT_TX_128_255B_FRAMES 0x1a324
52637 #define A_NCSI_STAT_TX_256_511B_FRAMES 0x1a328
52638 #define A_NCSI_STAT_TX_512_1023B_FRAMES 0x1a32c
52639 #define A_NCSI_STAT_TX_1024_1518B_FRAMES 0x1a330
52640 #define A_NCSI_STAT_TX_1519_MAXB_FRAMES 0x1a334
52641 #define A_NCSI_STAT_TX_ERR_FRAMES 0x1a338
52642 #define A_NCSI_STAT_RX_BYTES_LOW 0x1a33c
52643 #define A_NCSI_STAT_RX_BYTES_HIGH 0x1a340
52644 #define A_NCSI_STAT_RX_FRAMES_LOW 0x1a344
52645 #define A_NCSI_STAT_RX_FRAMES_HIGH 0x1a348
52646 #define A_NCSI_STAT_RX_BCAST_FRAMES 0x1a34c
52647 #define A_NCSI_STAT_RX_MCAST_FRAMES 0x1a350
52648 #define A_NCSI_STAT_RX_PAUSE_FRAMES 0x1a354
52649 #define A_NCSI_STAT_RX_64B_FRAMES 0x1a358
52650 #define A_NCSI_STAT_RX_65_127B_FRAMES 0x1a35c
52651 #define A_NCSI_STAT_RX_128_255B_FRAMES 0x1a360
52652 #define A_NCSI_STAT_RX_256_511B_FRAMES 0x1a364
52653 #define A_NCSI_STAT_RX_512_1023B_FRAMES 0x1a368
52654 #define A_NCSI_STAT_RX_1024_1518B_FRAMES 0x1a36c
52655 #define A_NCSI_STAT_RX_1519_MAXB_FRAMES 0x1a370
52656 #define A_NCSI_STAT_RX_SHORT_FRAMES 0x1a374
52657 #define A_NCSI_STAT_RX_OVERSIZE_FRAMES 0x1a378
52658 #define A_NCSI_STAT_RX_JABBER_FRAMES 0x1a37c
52659 #define A_NCSI_STAT_RX_CRC_ERR_FRAMES 0x1a380
52660 #define A_NCSI_STAT_RX_LENGTH_ERR_FRAMES 0x1a384
52661 #define A_NCSI_STAT_RX_SYM_CODE_ERR_FRAMES 0x1a388
52662 #define A_NCSI_XAUI_PCS_ERR 0x1a398
52663 
52664 #define S_PCS_SYNCSTATUS    5
52665 #define M_PCS_SYNCSTATUS    0xfU
52666 #define V_PCS_SYNCSTATUS(x) ((x) << S_PCS_SYNCSTATUS)
52667 #define G_PCS_SYNCSTATUS(x) (((x) >> S_PCS_SYNCSTATUS) & M_PCS_SYNCSTATUS)
52668 
52669 #define S_PCS_CTCFIFOERR    1
52670 #define M_PCS_CTCFIFOERR    0xfU
52671 #define V_PCS_CTCFIFOERR(x) ((x) << S_PCS_CTCFIFOERR)
52672 #define G_PCS_CTCFIFOERR(x) (((x) >> S_PCS_CTCFIFOERR) & M_PCS_CTCFIFOERR)
52673 
52674 #define S_PCS_NOTALIGNED    0
52675 #define V_PCS_NOTALIGNED(x) ((x) << S_PCS_NOTALIGNED)
52676 #define F_PCS_NOTALIGNED    V_PCS_NOTALIGNED(1U)
52677 
52678 #define A_NCSI_RGMII_STATUS 0x1a39c
52679 
52680 #define S_GMIIDUPLEX    3
52681 #define V_GMIIDUPLEX(x) ((x) << S_GMIIDUPLEX)
52682 #define F_GMIIDUPLEX    V_GMIIDUPLEX(1U)
52683 
52684 #define S_GMIISPEED    1
52685 #define M_GMIISPEED    0x3U
52686 #define V_GMIISPEED(x) ((x) << S_GMIISPEED)
52687 #define G_GMIISPEED(x) (((x) >> S_GMIISPEED) & M_GMIISPEED)
52688 
52689 #define S_GMIILINKSTATUS    0
52690 #define V_GMIILINKSTATUS(x) ((x) << S_GMIILINKSTATUS)
52691 #define F_GMIILINKSTATUS    V_GMIILINKSTATUS(1U)
52692 
52693 #define A_NCSI_WOL_STATUS 0x1a3a0
52694 
52695 #define S_T7_PATDETECTED    31
52696 #define V_T7_PATDETECTED(x) ((x) << S_T7_PATDETECTED)
52697 #define F_T7_PATDETECTED    V_T7_PATDETECTED(1U)
52698 
52699 #define A_NCSI_RX_MAX_PKT_SIZE_ERR_CNT 0x1a3a4
52700 #define A_NCSI_TX_SPI4_SOP_EOP_CNT 0x1a3a8
52701 
52702 #define S_TXSPI4SOPCNT    16
52703 #define M_TXSPI4SOPCNT    0xffffU
52704 #define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT)
52705 #define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT)
52706 
52707 #define S_TXSPI4EOPCNT    0
52708 #define M_TXSPI4EOPCNT    0xffffU
52709 #define V_TXSPI4EOPCNT(x) ((x) << S_TXSPI4EOPCNT)
52710 #define G_TXSPI4EOPCNT(x) (((x) >> S_TXSPI4EOPCNT) & M_TXSPI4EOPCNT)
52711 
52712 #define A_NCSI_RX_SPI4_SOP_EOP_CNT 0x1a3ac
52713 
52714 #define S_RXSPI4SOPCNT    16
52715 #define M_RXSPI4SOPCNT    0xffffU
52716 #define V_RXSPI4SOPCNT(x) ((x) << S_RXSPI4SOPCNT)
52717 #define G_RXSPI4SOPCNT(x) (((x) >> S_RXSPI4SOPCNT) & M_RXSPI4SOPCNT)
52718 
52719 #define S_RXSPI4EOPCNT    0
52720 #define M_RXSPI4EOPCNT    0xffffU
52721 #define V_RXSPI4EOPCNT(x) ((x) << S_RXSPI4EOPCNT)
52722 #define G_RXSPI4EOPCNT(x) (((x) >> S_RXSPI4EOPCNT) & M_RXSPI4EOPCNT)
52723 
52724 /* registers for module XGMAC */
52725 #define XGMAC_BASE_ADDR 0x0
52726 
52727 #define A_XGMAC_PORT_CFG 0x1000
52728 
52729 #define S_XGMII_CLK_SEL    29
52730 #define M_XGMII_CLK_SEL    0x7U
52731 #define V_XGMII_CLK_SEL(x) ((x) << S_XGMII_CLK_SEL)
52732 #define G_XGMII_CLK_SEL(x) (((x) >> S_XGMII_CLK_SEL) & M_XGMII_CLK_SEL)
52733 
52734 #define S_SINKTX    27
52735 #define V_SINKTX(x) ((x) << S_SINKTX)
52736 #define F_SINKTX    V_SINKTX(1U)
52737 
52738 #define S_SINKTXONLINKDOWN    26
52739 #define V_SINKTXONLINKDOWN(x) ((x) << S_SINKTXONLINKDOWN)
52740 #define F_SINKTXONLINKDOWN    V_SINKTXONLINKDOWN(1U)
52741 
52742 #define S_XG2G_SPEED_MODE    25
52743 #define V_XG2G_SPEED_MODE(x) ((x) << S_XG2G_SPEED_MODE)
52744 #define F_XG2G_SPEED_MODE    V_XG2G_SPEED_MODE(1U)
52745 
52746 #define S_LOOPNOFWD    24
52747 #define V_LOOPNOFWD(x) ((x) << S_LOOPNOFWD)
52748 #define F_LOOPNOFWD    V_LOOPNOFWD(1U)
52749 
52750 #define S_XGM_TX_PAUSE_SIZE    23
52751 #define V_XGM_TX_PAUSE_SIZE(x) ((x) << S_XGM_TX_PAUSE_SIZE)
52752 #define F_XGM_TX_PAUSE_SIZE    V_XGM_TX_PAUSE_SIZE(1U)
52753 
52754 #define S_XGM_TX_PAUSE_FRAME    22
52755 #define V_XGM_TX_PAUSE_FRAME(x) ((x) << S_XGM_TX_PAUSE_FRAME)
52756 #define F_XGM_TX_PAUSE_FRAME    V_XGM_TX_PAUSE_FRAME(1U)
52757 
52758 #define S_XGM_TX_DISABLE_PRE    21
52759 #define V_XGM_TX_DISABLE_PRE(x) ((x) << S_XGM_TX_DISABLE_PRE)
52760 #define F_XGM_TX_DISABLE_PRE    V_XGM_TX_DISABLE_PRE(1U)
52761 
52762 #define S_XGM_TX_DISABLE_CRC    20
52763 #define V_XGM_TX_DISABLE_CRC(x) ((x) << S_XGM_TX_DISABLE_CRC)
52764 #define F_XGM_TX_DISABLE_CRC    V_XGM_TX_DISABLE_CRC(1U)
52765 
52766 #define S_SMUX_RX_LOOP    19
52767 #define V_SMUX_RX_LOOP(x) ((x) << S_SMUX_RX_LOOP)
52768 #define F_SMUX_RX_LOOP    V_SMUX_RX_LOOP(1U)
52769 
52770 #define S_RX_LANE_SWAP    18
52771 #define V_RX_LANE_SWAP(x) ((x) << S_RX_LANE_SWAP)
52772 #define F_RX_LANE_SWAP    V_RX_LANE_SWAP(1U)
52773 
52774 #define S_TX_LANE_SWAP    17
52775 #define V_TX_LANE_SWAP(x) ((x) << S_TX_LANE_SWAP)
52776 #define F_TX_LANE_SWAP    V_TX_LANE_SWAP(1U)
52777 
52778 #define S_SIGNAL_DET    14
52779 #define V_SIGNAL_DET(x) ((x) << S_SIGNAL_DET)
52780 #define F_SIGNAL_DET    V_SIGNAL_DET(1U)
52781 
52782 #define S_PMUX_RX_LOOP    13
52783 #define V_PMUX_RX_LOOP(x) ((x) << S_PMUX_RX_LOOP)
52784 #define F_PMUX_RX_LOOP    V_PMUX_RX_LOOP(1U)
52785 
52786 #define S_PMUX_TX_LOOP    12
52787 #define V_PMUX_TX_LOOP(x) ((x) << S_PMUX_TX_LOOP)
52788 #define F_PMUX_TX_LOOP    V_PMUX_TX_LOOP(1U)
52789 
52790 #define S_XGM_RX_SEL    10
52791 #define M_XGM_RX_SEL    0x3U
52792 #define V_XGM_RX_SEL(x) ((x) << S_XGM_RX_SEL)
52793 #define G_XGM_RX_SEL(x) (((x) >> S_XGM_RX_SEL) & M_XGM_RX_SEL)
52794 
52795 #define S_PCS_TX_SEL    8
52796 #define M_PCS_TX_SEL    0x3U
52797 #define V_PCS_TX_SEL(x) ((x) << S_PCS_TX_SEL)
52798 #define G_PCS_TX_SEL(x) (((x) >> S_PCS_TX_SEL) & M_PCS_TX_SEL)
52799 
52800 #define S_XAUI20_REM_PRE    5
52801 #define V_XAUI20_REM_PRE(x) ((x) << S_XAUI20_REM_PRE)
52802 #define F_XAUI20_REM_PRE    V_XAUI20_REM_PRE(1U)
52803 
52804 #define S_XAUI20_XGMII_SEL    4
52805 #define V_XAUI20_XGMII_SEL(x) ((x) << S_XAUI20_XGMII_SEL)
52806 #define F_XAUI20_XGMII_SEL    V_XAUI20_XGMII_SEL(1U)
52807 
52808 #define S_PORT_SEL    0
52809 #define V_PORT_SEL(x) ((x) << S_PORT_SEL)
52810 #define F_PORT_SEL    V_PORT_SEL(1U)
52811 
52812 #define A_XGMAC_PORT_RESET_CTRL 0x1004
52813 
52814 #define S_AUXEXT_RESET    10
52815 #define V_AUXEXT_RESET(x) ((x) << S_AUXEXT_RESET)
52816 #define F_AUXEXT_RESET    V_AUXEXT_RESET(1U)
52817 
52818 #define S_TXFIFO_RESET    9
52819 #define V_TXFIFO_RESET(x) ((x) << S_TXFIFO_RESET)
52820 #define F_TXFIFO_RESET    V_TXFIFO_RESET(1U)
52821 
52822 #define S_RXFIFO_RESET    8
52823 #define V_RXFIFO_RESET(x) ((x) << S_RXFIFO_RESET)
52824 #define F_RXFIFO_RESET    V_RXFIFO_RESET(1U)
52825 
52826 #define S_BEAN_RESET    7
52827 #define V_BEAN_RESET(x) ((x) << S_BEAN_RESET)
52828 #define F_BEAN_RESET    V_BEAN_RESET(1U)
52829 
52830 #define S_XAUI_RESET    6
52831 #define V_XAUI_RESET(x) ((x) << S_XAUI_RESET)
52832 #define F_XAUI_RESET    V_XAUI_RESET(1U)
52833 
52834 #define S_AE_RESET    5
52835 #define V_AE_RESET(x) ((x) << S_AE_RESET)
52836 #define F_AE_RESET    V_AE_RESET(1U)
52837 
52838 #define S_XGM_RESET    4
52839 #define V_XGM_RESET(x) ((x) << S_XGM_RESET)
52840 #define F_XGM_RESET    V_XGM_RESET(1U)
52841 
52842 #define S_XG2G_RESET    3
52843 #define V_XG2G_RESET(x) ((x) << S_XG2G_RESET)
52844 #define F_XG2G_RESET    V_XG2G_RESET(1U)
52845 
52846 #define S_WOL_RESET    2
52847 #define V_WOL_RESET(x) ((x) << S_WOL_RESET)
52848 #define F_WOL_RESET    V_WOL_RESET(1U)
52849 
52850 #define S_XFI_PCS_RESET    1
52851 #define V_XFI_PCS_RESET(x) ((x) << S_XFI_PCS_RESET)
52852 #define F_XFI_PCS_RESET    V_XFI_PCS_RESET(1U)
52853 
52854 #define S_HSS_RESET    0
52855 #define V_HSS_RESET(x) ((x) << S_HSS_RESET)
52856 #define F_HSS_RESET    V_HSS_RESET(1U)
52857 
52858 #define A_XGMAC_PORT_LED_CFG 0x1008
52859 
52860 #define S_LED1_CFG    5
52861 #define M_LED1_CFG    0x7U
52862 #define V_LED1_CFG(x) ((x) << S_LED1_CFG)
52863 #define G_LED1_CFG(x) (((x) >> S_LED1_CFG) & M_LED1_CFG)
52864 
52865 #define S_LED1_POLARITY_INV    4
52866 #define V_LED1_POLARITY_INV(x) ((x) << S_LED1_POLARITY_INV)
52867 #define F_LED1_POLARITY_INV    V_LED1_POLARITY_INV(1U)
52868 
52869 #define S_LED0_CFG    1
52870 #define M_LED0_CFG    0x7U
52871 #define V_LED0_CFG(x) ((x) << S_LED0_CFG)
52872 #define G_LED0_CFG(x) (((x) >> S_LED0_CFG) & M_LED0_CFG)
52873 
52874 #define S_LED0_POLARITY_INV    0
52875 #define V_LED0_POLARITY_INV(x) ((x) << S_LED0_POLARITY_INV)
52876 #define F_LED0_POLARITY_INV    V_LED0_POLARITY_INV(1U)
52877 
52878 #define A_XGMAC_PORT_LED_COUNTHI 0x100c
52879 
52880 #define S_LED_COUNT_HI    0
52881 #define M_LED_COUNT_HI    0x1ffffffU
52882 #define V_LED_COUNT_HI(x) ((x) << S_LED_COUNT_HI)
52883 #define G_LED_COUNT_HI(x) (((x) >> S_LED_COUNT_HI) & M_LED_COUNT_HI)
52884 
52885 #define A_XGMAC_PORT_LED_COUNTLO 0x1010
52886 
52887 #define S_LED_COUNT_LO    0
52888 #define M_LED_COUNT_LO    0x1ffffffU
52889 #define V_LED_COUNT_LO(x) ((x) << S_LED_COUNT_LO)
52890 #define G_LED_COUNT_LO(x) (((x) >> S_LED_COUNT_LO) & M_LED_COUNT_LO)
52891 
52892 #define A_XGMAC_PORT_DEBUG_CFG 0x1014
52893 
52894 #define S_TESTCLK_SEL    0
52895 #define M_TESTCLK_SEL    0xfU
52896 #define V_TESTCLK_SEL(x) ((x) << S_TESTCLK_SEL)
52897 #define G_TESTCLK_SEL(x) (((x) >> S_TESTCLK_SEL) & M_TESTCLK_SEL)
52898 
52899 #define A_XGMAC_PORT_CFG2 0x1018
52900 
52901 #define S_RX_POLARITY_INV    28
52902 #define M_RX_POLARITY_INV    0xfU
52903 #define V_RX_POLARITY_INV(x) ((x) << S_RX_POLARITY_INV)
52904 #define G_RX_POLARITY_INV(x) (((x) >> S_RX_POLARITY_INV) & M_RX_POLARITY_INV)
52905 
52906 #define S_TX_POLARITY_INV    24
52907 #define M_TX_POLARITY_INV    0xfU
52908 #define V_TX_POLARITY_INV(x) ((x) << S_TX_POLARITY_INV)
52909 #define G_TX_POLARITY_INV(x) (((x) >> S_TX_POLARITY_INV) & M_TX_POLARITY_INV)
52910 
52911 #define S_INSTANCENUM    22
52912 #define M_INSTANCENUM    0x3U
52913 #define V_INSTANCENUM(x) ((x) << S_INSTANCENUM)
52914 #define G_INSTANCENUM(x) (((x) >> S_INSTANCENUM) & M_INSTANCENUM)
52915 
52916 #define S_STOPONPERR    21
52917 #define V_STOPONPERR(x) ((x) << S_STOPONPERR)
52918 #define F_STOPONPERR    V_STOPONPERR(1U)
52919 
52920 #define S_MACTXEN    20
52921 #define V_MACTXEN(x) ((x) << S_MACTXEN)
52922 #define F_MACTXEN    V_MACTXEN(1U)
52923 
52924 #define S_MACRXEN    19
52925 #define V_MACRXEN(x) ((x) << S_MACRXEN)
52926 #define F_MACRXEN    V_MACRXEN(1U)
52927 
52928 #define S_PATEN    18
52929 #define V_PATEN(x) ((x) << S_PATEN)
52930 #define F_PATEN    V_PATEN(1U)
52931 
52932 #define S_MAGICEN    17
52933 #define V_MAGICEN(x) ((x) << S_MAGICEN)
52934 #define F_MAGICEN    V_MAGICEN(1U)
52935 
52936 #define S_TX_IPG    4
52937 #define M_TX_IPG    0x1fffU
52938 #define V_TX_IPG(x) ((x) << S_TX_IPG)
52939 #define G_TX_IPG(x) (((x) >> S_TX_IPG) & M_TX_IPG)
52940 
52941 #define S_AEC_PMA_TX_READY    1
52942 #define V_AEC_PMA_TX_READY(x) ((x) << S_AEC_PMA_TX_READY)
52943 #define F_AEC_PMA_TX_READY    V_AEC_PMA_TX_READY(1U)
52944 
52945 #define S_AEC_PMA_RX_READY    0
52946 #define V_AEC_PMA_RX_READY(x) ((x) << S_AEC_PMA_RX_READY)
52947 #define F_AEC_PMA_RX_READY    V_AEC_PMA_RX_READY(1U)
52948 
52949 #define A_XGMAC_PORT_PKT_COUNT 0x101c
52950 
52951 #define S_TX_SOP_COUNT    24
52952 #define M_TX_SOP_COUNT    0xffU
52953 #define V_TX_SOP_COUNT(x) ((x) << S_TX_SOP_COUNT)
52954 #define G_TX_SOP_COUNT(x) (((x) >> S_TX_SOP_COUNT) & M_TX_SOP_COUNT)
52955 
52956 #define S_TX_EOP_COUNT    16
52957 #define M_TX_EOP_COUNT    0xffU
52958 #define V_TX_EOP_COUNT(x) ((x) << S_TX_EOP_COUNT)
52959 #define G_TX_EOP_COUNT(x) (((x) >> S_TX_EOP_COUNT) & M_TX_EOP_COUNT)
52960 
52961 #define S_RX_SOP_COUNT    8
52962 #define M_RX_SOP_COUNT    0xffU
52963 #define V_RX_SOP_COUNT(x) ((x) << S_RX_SOP_COUNT)
52964 #define G_RX_SOP_COUNT(x) (((x) >> S_RX_SOP_COUNT) & M_RX_SOP_COUNT)
52965 
52966 #define S_RX_EOP_COUNT    0
52967 #define M_RX_EOP_COUNT    0xffU
52968 #define V_RX_EOP_COUNT(x) ((x) << S_RX_EOP_COUNT)
52969 #define G_RX_EOP_COUNT(x) (((x) >> S_RX_EOP_COUNT) & M_RX_EOP_COUNT)
52970 
52971 #define A_XGMAC_PORT_PERR_INJECT 0x1020
52972 
52973 #define S_XGMMEMSEL    1
52974 #define V_XGMMEMSEL(x) ((x) << S_XGMMEMSEL)
52975 #define F_XGMMEMSEL    V_XGMMEMSEL(1U)
52976 
52977 #define A_XGMAC_PORT_MAGIC_MACID_LO 0x1024
52978 #define A_XGMAC_PORT_MAGIC_MACID_HI 0x1028
52979 
52980 #define S_MAC_WOL_DA    0
52981 #define M_MAC_WOL_DA    0xffffU
52982 #define V_MAC_WOL_DA(x) ((x) << S_MAC_WOL_DA)
52983 #define G_MAC_WOL_DA(x) (((x) >> S_MAC_WOL_DA) & M_MAC_WOL_DA)
52984 
52985 #define A_XGMAC_PORT_BUILD_REVISION 0x102c
52986 #define A_XGMAC_PORT_XGMII_SE_COUNT 0x1030
52987 
52988 #define S_TXSOP    24
52989 #define M_TXSOP    0xffU
52990 #define V_TXSOP(x) ((x) << S_TXSOP)
52991 #define G_TXSOP(x) (((x) >> S_TXSOP) & M_TXSOP)
52992 
52993 #define S_TXEOP    16
52994 #define M_TXEOP    0xffU
52995 #define V_TXEOP(x) ((x) << S_TXEOP)
52996 #define G_TXEOP(x) (((x) >> S_TXEOP) & M_TXEOP)
52997 
52998 #define S_RXSOP    8
52999 #define M_RXSOP    0xffU
53000 #define V_RXSOP(x) ((x) << S_RXSOP)
53001 #define G_RXSOP(x) (((x) >> S_RXSOP) & M_RXSOP)
53002 
53003 #define S_T4_RXEOP    0
53004 #define M_T4_RXEOP    0xffU
53005 #define V_T4_RXEOP(x) ((x) << S_T4_RXEOP)
53006 #define G_T4_RXEOP(x) (((x) >> S_T4_RXEOP) & M_T4_RXEOP)
53007 
53008 #define A_XGMAC_PORT_LINK_STATUS 0x1034
53009 
53010 #define S_REMFLT    3
53011 #define V_REMFLT(x) ((x) << S_REMFLT)
53012 #define F_REMFLT    V_REMFLT(1U)
53013 
53014 #define S_LOCFLT    2
53015 #define V_LOCFLT(x) ((x) << S_LOCFLT)
53016 #define F_LOCFLT    V_LOCFLT(1U)
53017 
53018 #define S_LINKUP    1
53019 #define V_LINKUP(x) ((x) << S_LINKUP)
53020 #define F_LINKUP    V_LINKUP(1U)
53021 
53022 #define S_LINKDN    0
53023 #define V_LINKDN(x) ((x) << S_LINKDN)
53024 #define F_LINKDN    V_LINKDN(1U)
53025 
53026 #define A_XGMAC_PORT_CHECKIN 0x1038
53027 
53028 #define S_PREAMBLE    1
53029 #define V_PREAMBLE(x) ((x) << S_PREAMBLE)
53030 #define F_PREAMBLE    V_PREAMBLE(1U)
53031 
53032 #define S_CHECKIN    0
53033 #define V_CHECKIN(x) ((x) << S_CHECKIN)
53034 #define F_CHECKIN    V_CHECKIN(1U)
53035 
53036 #define A_XGMAC_PORT_FAULT_TEST 0x103c
53037 
53038 #define S_FLTTYPE    1
53039 #define V_FLTTYPE(x) ((x) << S_FLTTYPE)
53040 #define F_FLTTYPE    V_FLTTYPE(1U)
53041 
53042 #define S_FLTCTRL    0
53043 #define V_FLTCTRL(x) ((x) << S_FLTCTRL)
53044 #define F_FLTCTRL    V_FLTCTRL(1U)
53045 
53046 #define A_XGMAC_PORT_SPARE 0x1040
53047 #define A_XGMAC_PORT_HSS_SIGDET_STATUS 0x1044
53048 
53049 #define S_SIGNALDETECT    0
53050 #define M_SIGNALDETECT    0xfU
53051 #define V_SIGNALDETECT(x) ((x) << S_SIGNALDETECT)
53052 #define G_SIGNALDETECT(x) (((x) >> S_SIGNALDETECT) & M_SIGNALDETECT)
53053 
53054 #define A_XGMAC_PORT_EXT_LOS_STATUS 0x1048
53055 #define A_XGMAC_PORT_EXT_LOS_CTRL 0x104c
53056 
53057 #define S_CTRL    0
53058 #define M_CTRL    0xfU
53059 #define V_CTRL(x) ((x) << S_CTRL)
53060 #define G_CTRL(x) (((x) >> S_CTRL) & M_CTRL)
53061 
53062 #define A_XGMAC_PORT_FPGA_PAUSE_CTL 0x1050
53063 
53064 #define S_CTL    31
53065 #define V_CTL(x) ((x) << S_CTL)
53066 #define F_CTL    V_CTL(1U)
53067 
53068 #define S_HWM    13
53069 #define M_HWM    0x1fffU
53070 #define V_HWM(x) ((x) << S_HWM)
53071 #define G_HWM(x) (((x) >> S_HWM) & M_HWM)
53072 
53073 #define S_LWM    0
53074 #define M_LWM    0x1fffU
53075 #define V_LWM(x) ((x) << S_LWM)
53076 #define G_LWM(x) (((x) >> S_LWM) & M_LWM)
53077 
53078 #define A_XGMAC_PORT_FPGA_ERRPKT_CNT 0x1054
53079 #define A_XGMAC_PORT_LA_TX_0 0x1058
53080 #define A_XGMAC_PORT_LA_RX_0 0x105c
53081 #define A_XGMAC_PORT_FPGA_LA_CTL 0x1060
53082 
53083 #define S_RXRST    5
53084 #define V_RXRST(x) ((x) << S_RXRST)
53085 #define F_RXRST    V_RXRST(1U)
53086 
53087 #define S_TXRST    4
53088 #define V_TXRST(x) ((x) << S_TXRST)
53089 #define F_TXRST    V_TXRST(1U)
53090 
53091 #define S_XGMII    3
53092 #define V_XGMII(x) ((x) << S_XGMII)
53093 #define F_XGMII    V_XGMII(1U)
53094 
53095 #define S_LAPAUSE    2
53096 #define V_LAPAUSE(x) ((x) << S_LAPAUSE)
53097 #define F_LAPAUSE    V_LAPAUSE(1U)
53098 
53099 #define S_STOPERR    1
53100 #define V_STOPERR(x) ((x) << S_STOPERR)
53101 #define F_STOPERR    V_STOPERR(1U)
53102 
53103 #define S_LASTOP    0
53104 #define V_LASTOP(x) ((x) << S_LASTOP)
53105 #define F_LASTOP    V_LASTOP(1U)
53106 
53107 #define A_XGMAC_PORT_EPIO_DATA0 0x10c0
53108 #define A_XGMAC_PORT_EPIO_DATA1 0x10c4
53109 #define A_XGMAC_PORT_EPIO_DATA2 0x10c8
53110 #define A_XGMAC_PORT_EPIO_DATA3 0x10cc
53111 #define A_XGMAC_PORT_EPIO_OP 0x10d0
53112 
53113 #define S_EPIOWR    8
53114 #define V_EPIOWR(x) ((x) << S_EPIOWR)
53115 #define F_EPIOWR    V_EPIOWR(1U)
53116 
53117 #define S_ADDRESS    0
53118 #define M_ADDRESS    0xffU
53119 #define V_ADDRESS(x) ((x) << S_ADDRESS)
53120 #define G_ADDRESS(x) (((x) >> S_ADDRESS) & M_ADDRESS)
53121 
53122 #define A_XGMAC_PORT_WOL_STATUS 0x10d4
53123 
53124 #define S_MAGICDETECTED    31
53125 #define V_MAGICDETECTED(x) ((x) << S_MAGICDETECTED)
53126 #define F_MAGICDETECTED    V_MAGICDETECTED(1U)
53127 
53128 #define S_PATDETECTED    30
53129 #define V_PATDETECTED(x) ((x) << S_PATDETECTED)
53130 #define F_PATDETECTED    V_PATDETECTED(1U)
53131 
53132 #define S_CLEARMAGIC    4
53133 #define V_CLEARMAGIC(x) ((x) << S_CLEARMAGIC)
53134 #define F_CLEARMAGIC    V_CLEARMAGIC(1U)
53135 
53136 #define S_CLEARMATCH    3
53137 #define V_CLEARMATCH(x) ((x) << S_CLEARMATCH)
53138 #define F_CLEARMATCH    V_CLEARMATCH(1U)
53139 
53140 #define S_MATCHEDFILTER    0
53141 #define M_MATCHEDFILTER    0x7U
53142 #define V_MATCHEDFILTER(x) ((x) << S_MATCHEDFILTER)
53143 #define G_MATCHEDFILTER(x) (((x) >> S_MATCHEDFILTER) & M_MATCHEDFILTER)
53144 
53145 #define A_XGMAC_PORT_INT_EN 0x10d8
53146 
53147 #define S_EXT_LOS    28
53148 #define V_EXT_LOS(x) ((x) << S_EXT_LOS)
53149 #define F_EXT_LOS    V_EXT_LOS(1U)
53150 
53151 #define S_INCMPTBL_LINK    27
53152 #define V_INCMPTBL_LINK(x) ((x) << S_INCMPTBL_LINK)
53153 #define F_INCMPTBL_LINK    V_INCMPTBL_LINK(1U)
53154 
53155 #define S_PATDETWAKE    26
53156 #define V_PATDETWAKE(x) ((x) << S_PATDETWAKE)
53157 #define F_PATDETWAKE    V_PATDETWAKE(1U)
53158 
53159 #define S_MAGICWAKE    25
53160 #define V_MAGICWAKE(x) ((x) << S_MAGICWAKE)
53161 #define F_MAGICWAKE    V_MAGICWAKE(1U)
53162 
53163 #define S_SIGDETCHG    24
53164 #define V_SIGDETCHG(x) ((x) << S_SIGDETCHG)
53165 #define F_SIGDETCHG    V_SIGDETCHG(1U)
53166 
53167 #define S_PCSR_FEC_CORR    23
53168 #define V_PCSR_FEC_CORR(x) ((x) << S_PCSR_FEC_CORR)
53169 #define F_PCSR_FEC_CORR    V_PCSR_FEC_CORR(1U)
53170 
53171 #define S_AE_TRAIN_LOCAL    22
53172 #define V_AE_TRAIN_LOCAL(x) ((x) << S_AE_TRAIN_LOCAL)
53173 #define F_AE_TRAIN_LOCAL    V_AE_TRAIN_LOCAL(1U)
53174 
53175 #define S_HSSPLL_LOCK    21
53176 #define V_HSSPLL_LOCK(x) ((x) << S_HSSPLL_LOCK)
53177 #define F_HSSPLL_LOCK    V_HSSPLL_LOCK(1U)
53178 
53179 #define S_HSSPRT_READY    20
53180 #define V_HSSPRT_READY(x) ((x) << S_HSSPRT_READY)
53181 #define F_HSSPRT_READY    V_HSSPRT_READY(1U)
53182 
53183 #define S_AUTONEG_DONE    19
53184 #define V_AUTONEG_DONE(x) ((x) << S_AUTONEG_DONE)
53185 #define F_AUTONEG_DONE    V_AUTONEG_DONE(1U)
53186 
53187 #define S_PCSR_HI_BER    18
53188 #define V_PCSR_HI_BER(x) ((x) << S_PCSR_HI_BER)
53189 #define F_PCSR_HI_BER    V_PCSR_HI_BER(1U)
53190 
53191 #define S_PCSR_FEC_ERROR    17
53192 #define V_PCSR_FEC_ERROR(x) ((x) << S_PCSR_FEC_ERROR)
53193 #define F_PCSR_FEC_ERROR    V_PCSR_FEC_ERROR(1U)
53194 
53195 #define S_PCSR_LINK_FAIL    16
53196 #define V_PCSR_LINK_FAIL(x) ((x) << S_PCSR_LINK_FAIL)
53197 #define F_PCSR_LINK_FAIL    V_PCSR_LINK_FAIL(1U)
53198 
53199 #define S_XAUI_DEC_ERROR    15
53200 #define V_XAUI_DEC_ERROR(x) ((x) << S_XAUI_DEC_ERROR)
53201 #define F_XAUI_DEC_ERROR    V_XAUI_DEC_ERROR(1U)
53202 
53203 #define S_XAUI_LINK_FAIL    14
53204 #define V_XAUI_LINK_FAIL(x) ((x) << S_XAUI_LINK_FAIL)
53205 #define F_XAUI_LINK_FAIL    V_XAUI_LINK_FAIL(1U)
53206 
53207 #define S_PCS_CTC_ERROR    13
53208 #define V_PCS_CTC_ERROR(x) ((x) << S_PCS_CTC_ERROR)
53209 #define F_PCS_CTC_ERROR    V_PCS_CTC_ERROR(1U)
53210 
53211 #define S_PCS_LINK_GOOD    12
53212 #define V_PCS_LINK_GOOD(x) ((x) << S_PCS_LINK_GOOD)
53213 #define F_PCS_LINK_GOOD    V_PCS_LINK_GOOD(1U)
53214 
53215 #define S_PCS_LINK_FAIL    11
53216 #define V_PCS_LINK_FAIL(x) ((x) << S_PCS_LINK_FAIL)
53217 #define F_PCS_LINK_FAIL    V_PCS_LINK_FAIL(1U)
53218 
53219 #define S_RXFIFOOVERFLOW    10
53220 #define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW)
53221 #define F_RXFIFOOVERFLOW    V_RXFIFOOVERFLOW(1U)
53222 
53223 #define S_HSSPRBSERR    9
53224 #define V_HSSPRBSERR(x) ((x) << S_HSSPRBSERR)
53225 #define F_HSSPRBSERR    V_HSSPRBSERR(1U)
53226 
53227 #define S_HSSEYEQUAL    8
53228 #define V_HSSEYEQUAL(x) ((x) << S_HSSEYEQUAL)
53229 #define F_HSSEYEQUAL    V_HSSEYEQUAL(1U)
53230 
53231 #define S_REMOTEFAULT    7
53232 #define V_REMOTEFAULT(x) ((x) << S_REMOTEFAULT)
53233 #define F_REMOTEFAULT    V_REMOTEFAULT(1U)
53234 
53235 #define S_LOCALFAULT    6
53236 #define V_LOCALFAULT(x) ((x) << S_LOCALFAULT)
53237 #define F_LOCALFAULT    V_LOCALFAULT(1U)
53238 
53239 #define S_MAC_LINK_DOWN    5
53240 #define V_MAC_LINK_DOWN(x) ((x) << S_MAC_LINK_DOWN)
53241 #define F_MAC_LINK_DOWN    V_MAC_LINK_DOWN(1U)
53242 
53243 #define S_MAC_LINK_UP    4
53244 #define V_MAC_LINK_UP(x) ((x) << S_MAC_LINK_UP)
53245 #define F_MAC_LINK_UP    V_MAC_LINK_UP(1U)
53246 
53247 #define S_BEAN_INT    3
53248 #define V_BEAN_INT(x) ((x) << S_BEAN_INT)
53249 #define F_BEAN_INT    V_BEAN_INT(1U)
53250 
53251 #define S_XGM_INT    2
53252 #define V_XGM_INT(x) ((x) << S_XGM_INT)
53253 #define F_XGM_INT    V_XGM_INT(1U)
53254 
53255 #define A_XGMAC_PORT_INT_CAUSE 0x10dc
53256 #define A_XGMAC_PORT_HSS_CFG0 0x10e0
53257 
53258 #define S_TXDTS    31
53259 #define V_TXDTS(x) ((x) << S_TXDTS)
53260 #define F_TXDTS    V_TXDTS(1U)
53261 
53262 #define S_TXCTS    30
53263 #define V_TXCTS(x) ((x) << S_TXCTS)
53264 #define F_TXCTS    V_TXCTS(1U)
53265 
53266 #define S_TXBTS    29
53267 #define V_TXBTS(x) ((x) << S_TXBTS)
53268 #define F_TXBTS    V_TXBTS(1U)
53269 
53270 #define S_TXATS    28
53271 #define V_TXATS(x) ((x) << S_TXATS)
53272 #define F_TXATS    V_TXATS(1U)
53273 
53274 #define S_TXDOBS    27
53275 #define V_TXDOBS(x) ((x) << S_TXDOBS)
53276 #define F_TXDOBS    V_TXDOBS(1U)
53277 
53278 #define S_TXCOBS    26
53279 #define V_TXCOBS(x) ((x) << S_TXCOBS)
53280 #define F_TXCOBS    V_TXCOBS(1U)
53281 
53282 #define S_TXBOBS    25
53283 #define V_TXBOBS(x) ((x) << S_TXBOBS)
53284 #define F_TXBOBS    V_TXBOBS(1U)
53285 
53286 #define S_TXAOBS    24
53287 #define V_TXAOBS(x) ((x) << S_TXAOBS)
53288 #define F_TXAOBS    V_TXAOBS(1U)
53289 
53290 #define S_HSSREFCLKSEL    20
53291 #define V_HSSREFCLKSEL(x) ((x) << S_HSSREFCLKSEL)
53292 #define F_HSSREFCLKSEL    V_HSSREFCLKSEL(1U)
53293 
53294 #define S_HSSAVDHI    17
53295 #define V_HSSAVDHI(x) ((x) << S_HSSAVDHI)
53296 #define F_HSSAVDHI    V_HSSAVDHI(1U)
53297 
53298 #define S_HSSRXTS    16
53299 #define V_HSSRXTS(x) ((x) << S_HSSRXTS)
53300 #define F_HSSRXTS    V_HSSRXTS(1U)
53301 
53302 #define S_HSSTXACMODE    15
53303 #define V_HSSTXACMODE(x) ((x) << S_HSSTXACMODE)
53304 #define F_HSSTXACMODE    V_HSSTXACMODE(1U)
53305 
53306 #define S_HSSRXACMODE    14
53307 #define V_HSSRXACMODE(x) ((x) << S_HSSRXACMODE)
53308 #define F_HSSRXACMODE    V_HSSRXACMODE(1U)
53309 
53310 #define S_HSSRESYNC    13
53311 #define V_HSSRESYNC(x) ((x) << S_HSSRESYNC)
53312 #define F_HSSRESYNC    V_HSSRESYNC(1U)
53313 
53314 #define S_HSSRECCAL    12
53315 #define V_HSSRECCAL(x) ((x) << S_HSSRECCAL)
53316 #define F_HSSRECCAL    V_HSSRECCAL(1U)
53317 
53318 #define S_HSSPDWNPLL    11
53319 #define V_HSSPDWNPLL(x) ((x) << S_HSSPDWNPLL)
53320 #define F_HSSPDWNPLL    V_HSSPDWNPLL(1U)
53321 
53322 #define S_HSSDIVSEL    9
53323 #define M_HSSDIVSEL    0x3U
53324 #define V_HSSDIVSEL(x) ((x) << S_HSSDIVSEL)
53325 #define G_HSSDIVSEL(x) (((x) >> S_HSSDIVSEL) & M_HSSDIVSEL)
53326 
53327 #define S_HSSREFDIV    8
53328 #define V_HSSREFDIV(x) ((x) << S_HSSREFDIV)
53329 #define F_HSSREFDIV    V_HSSREFDIV(1U)
53330 
53331 #define S_HSSPLLBYP    7
53332 #define V_HSSPLLBYP(x) ((x) << S_HSSPLLBYP)
53333 #define F_HSSPLLBYP    V_HSSPLLBYP(1U)
53334 
53335 #define S_HSSLOFREQPLL    6
53336 #define V_HSSLOFREQPLL(x) ((x) << S_HSSLOFREQPLL)
53337 #define F_HSSLOFREQPLL    V_HSSLOFREQPLL(1U)
53338 
53339 #define S_HSSLOFREQ2PLL    5
53340 #define V_HSSLOFREQ2PLL(x) ((x) << S_HSSLOFREQ2PLL)
53341 #define F_HSSLOFREQ2PLL    V_HSSLOFREQ2PLL(1U)
53342 
53343 #define S_HSSEXTC16SEL    4
53344 #define V_HSSEXTC16SEL(x) ((x) << S_HSSEXTC16SEL)
53345 #define F_HSSEXTC16SEL    V_HSSEXTC16SEL(1U)
53346 
53347 #define S_HSSRSTCONFIG    1
53348 #define M_HSSRSTCONFIG    0x7U
53349 #define V_HSSRSTCONFIG(x) ((x) << S_HSSRSTCONFIG)
53350 #define G_HSSRSTCONFIG(x) (((x) >> S_HSSRSTCONFIG) & M_HSSRSTCONFIG)
53351 
53352 #define S_HSSPRBSEN    0
53353 #define V_HSSPRBSEN(x) ((x) << S_HSSPRBSEN)
53354 #define F_HSSPRBSEN    V_HSSPRBSEN(1U)
53355 
53356 #define A_XGMAC_PORT_HSS_CFG1 0x10e4
53357 
53358 #define S_RXDPRBSRST    28
53359 #define V_RXDPRBSRST(x) ((x) << S_RXDPRBSRST)
53360 #define F_RXDPRBSRST    V_RXDPRBSRST(1U)
53361 
53362 #define S_RXDPRBSEN    27
53363 #define V_RXDPRBSEN(x) ((x) << S_RXDPRBSEN)
53364 #define F_RXDPRBSEN    V_RXDPRBSEN(1U)
53365 
53366 #define S_RXDPRBSFRCERR    26
53367 #define V_RXDPRBSFRCERR(x) ((x) << S_RXDPRBSFRCERR)
53368 #define F_RXDPRBSFRCERR    V_RXDPRBSFRCERR(1U)
53369 
53370 #define S_TXDPRBSRST    25
53371 #define V_TXDPRBSRST(x) ((x) << S_TXDPRBSRST)
53372 #define F_TXDPRBSRST    V_TXDPRBSRST(1U)
53373 
53374 #define S_TXDPRBSEN    24
53375 #define V_TXDPRBSEN(x) ((x) << S_TXDPRBSEN)
53376 #define F_TXDPRBSEN    V_TXDPRBSEN(1U)
53377 
53378 #define S_RXCPRBSRST    20
53379 #define V_RXCPRBSRST(x) ((x) << S_RXCPRBSRST)
53380 #define F_RXCPRBSRST    V_RXCPRBSRST(1U)
53381 
53382 #define S_RXCPRBSEN    19
53383 #define V_RXCPRBSEN(x) ((x) << S_RXCPRBSEN)
53384 #define F_RXCPRBSEN    V_RXCPRBSEN(1U)
53385 
53386 #define S_RXCPRBSFRCERR    18
53387 #define V_RXCPRBSFRCERR(x) ((x) << S_RXCPRBSFRCERR)
53388 #define F_RXCPRBSFRCERR    V_RXCPRBSFRCERR(1U)
53389 
53390 #define S_TXCPRBSRST    17
53391 #define V_TXCPRBSRST(x) ((x) << S_TXCPRBSRST)
53392 #define F_TXCPRBSRST    V_TXCPRBSRST(1U)
53393 
53394 #define S_TXCPRBSEN    16
53395 #define V_TXCPRBSEN(x) ((x) << S_TXCPRBSEN)
53396 #define F_TXCPRBSEN    V_TXCPRBSEN(1U)
53397 
53398 #define S_RXBPRBSRST    12
53399 #define V_RXBPRBSRST(x) ((x) << S_RXBPRBSRST)
53400 #define F_RXBPRBSRST    V_RXBPRBSRST(1U)
53401 
53402 #define S_RXBPRBSEN    11
53403 #define V_RXBPRBSEN(x) ((x) << S_RXBPRBSEN)
53404 #define F_RXBPRBSEN    V_RXBPRBSEN(1U)
53405 
53406 #define S_RXBPRBSFRCERR    10
53407 #define V_RXBPRBSFRCERR(x) ((x) << S_RXBPRBSFRCERR)
53408 #define F_RXBPRBSFRCERR    V_RXBPRBSFRCERR(1U)
53409 
53410 #define S_TXBPRBSRST    9
53411 #define V_TXBPRBSRST(x) ((x) << S_TXBPRBSRST)
53412 #define F_TXBPRBSRST    V_TXBPRBSRST(1U)
53413 
53414 #define S_TXBPRBSEN    8
53415 #define V_TXBPRBSEN(x) ((x) << S_TXBPRBSEN)
53416 #define F_TXBPRBSEN    V_TXBPRBSEN(1U)
53417 
53418 #define S_RXAPRBSRST    4
53419 #define V_RXAPRBSRST(x) ((x) << S_RXAPRBSRST)
53420 #define F_RXAPRBSRST    V_RXAPRBSRST(1U)
53421 
53422 #define S_RXAPRBSEN    3
53423 #define V_RXAPRBSEN(x) ((x) << S_RXAPRBSEN)
53424 #define F_RXAPRBSEN    V_RXAPRBSEN(1U)
53425 
53426 #define S_RXAPRBSFRCERR    2
53427 #define V_RXAPRBSFRCERR(x) ((x) << S_RXAPRBSFRCERR)
53428 #define F_RXAPRBSFRCERR    V_RXAPRBSFRCERR(1U)
53429 
53430 #define S_TXAPRBSRST    1
53431 #define V_TXAPRBSRST(x) ((x) << S_TXAPRBSRST)
53432 #define F_TXAPRBSRST    V_TXAPRBSRST(1U)
53433 
53434 #define S_TXAPRBSEN    0
53435 #define V_TXAPRBSEN(x) ((x) << S_TXAPRBSEN)
53436 #define F_TXAPRBSEN    V_TXAPRBSEN(1U)
53437 
53438 #define A_XGMAC_PORT_HSS_CFG2 0x10e8
53439 
53440 #define S_RXDDATASYNC    23
53441 #define V_RXDDATASYNC(x) ((x) << S_RXDDATASYNC)
53442 #define F_RXDDATASYNC    V_RXDDATASYNC(1U)
53443 
53444 #define S_RXCDATASYNC    22
53445 #define V_RXCDATASYNC(x) ((x) << S_RXCDATASYNC)
53446 #define F_RXCDATASYNC    V_RXCDATASYNC(1U)
53447 
53448 #define S_RXBDATASYNC    21
53449 #define V_RXBDATASYNC(x) ((x) << S_RXBDATASYNC)
53450 #define F_RXBDATASYNC    V_RXBDATASYNC(1U)
53451 
53452 #define S_RXADATASYNC    20
53453 #define V_RXADATASYNC(x) ((x) << S_RXADATASYNC)
53454 #define F_RXADATASYNC    V_RXADATASYNC(1U)
53455 
53456 #define S_RXDEARLYIN    19
53457 #define V_RXDEARLYIN(x) ((x) << S_RXDEARLYIN)
53458 #define F_RXDEARLYIN    V_RXDEARLYIN(1U)
53459 
53460 #define S_RXDLATEIN    18
53461 #define V_RXDLATEIN(x) ((x) << S_RXDLATEIN)
53462 #define F_RXDLATEIN    V_RXDLATEIN(1U)
53463 
53464 #define S_RXDPHSLOCK    17
53465 #define V_RXDPHSLOCK(x) ((x) << S_RXDPHSLOCK)
53466 #define F_RXDPHSLOCK    V_RXDPHSLOCK(1U)
53467 
53468 #define S_RXDPHSDNIN    16
53469 #define V_RXDPHSDNIN(x) ((x) << S_RXDPHSDNIN)
53470 #define F_RXDPHSDNIN    V_RXDPHSDNIN(1U)
53471 
53472 #define S_RXDPHSUPIN    15
53473 #define V_RXDPHSUPIN(x) ((x) << S_RXDPHSUPIN)
53474 #define F_RXDPHSUPIN    V_RXDPHSUPIN(1U)
53475 
53476 #define S_RXCEARLYIN    14
53477 #define V_RXCEARLYIN(x) ((x) << S_RXCEARLYIN)
53478 #define F_RXCEARLYIN    V_RXCEARLYIN(1U)
53479 
53480 #define S_RXCLATEIN    13
53481 #define V_RXCLATEIN(x) ((x) << S_RXCLATEIN)
53482 #define F_RXCLATEIN    V_RXCLATEIN(1U)
53483 
53484 #define S_RXCPHSLOCK    12
53485 #define V_RXCPHSLOCK(x) ((x) << S_RXCPHSLOCK)
53486 #define F_RXCPHSLOCK    V_RXCPHSLOCK(1U)
53487 
53488 #define S_RXCPHSDNIN    11
53489 #define V_RXCPHSDNIN(x) ((x) << S_RXCPHSDNIN)
53490 #define F_RXCPHSDNIN    V_RXCPHSDNIN(1U)
53491 
53492 #define S_RXCPHSUPIN    10
53493 #define V_RXCPHSUPIN(x) ((x) << S_RXCPHSUPIN)
53494 #define F_RXCPHSUPIN    V_RXCPHSUPIN(1U)
53495 
53496 #define S_RXBEARLYIN    9
53497 #define V_RXBEARLYIN(x) ((x) << S_RXBEARLYIN)
53498 #define F_RXBEARLYIN    V_RXBEARLYIN(1U)
53499 
53500 #define S_RXBLATEIN    8
53501 #define V_RXBLATEIN(x) ((x) << S_RXBLATEIN)
53502 #define F_RXBLATEIN    V_RXBLATEIN(1U)
53503 
53504 #define S_RXBPHSLOCK    7
53505 #define V_RXBPHSLOCK(x) ((x) << S_RXBPHSLOCK)
53506 #define F_RXBPHSLOCK    V_RXBPHSLOCK(1U)
53507 
53508 #define S_RXBPHSDNIN    6
53509 #define V_RXBPHSDNIN(x) ((x) << S_RXBPHSDNIN)
53510 #define F_RXBPHSDNIN    V_RXBPHSDNIN(1U)
53511 
53512 #define S_RXBPHSUPIN    5
53513 #define V_RXBPHSUPIN(x) ((x) << S_RXBPHSUPIN)
53514 #define F_RXBPHSUPIN    V_RXBPHSUPIN(1U)
53515 
53516 #define S_RXAEARLYIN    4
53517 #define V_RXAEARLYIN(x) ((x) << S_RXAEARLYIN)
53518 #define F_RXAEARLYIN    V_RXAEARLYIN(1U)
53519 
53520 #define S_RXALATEIN    3
53521 #define V_RXALATEIN(x) ((x) << S_RXALATEIN)
53522 #define F_RXALATEIN    V_RXALATEIN(1U)
53523 
53524 #define S_RXAPHSLOCK    2
53525 #define V_RXAPHSLOCK(x) ((x) << S_RXAPHSLOCK)
53526 #define F_RXAPHSLOCK    V_RXAPHSLOCK(1U)
53527 
53528 #define S_RXAPHSDNIN    1
53529 #define V_RXAPHSDNIN(x) ((x) << S_RXAPHSDNIN)
53530 #define F_RXAPHSDNIN    V_RXAPHSDNIN(1U)
53531 
53532 #define S_RXAPHSUPIN    0
53533 #define V_RXAPHSUPIN(x) ((x) << S_RXAPHSUPIN)
53534 #define F_RXAPHSUPIN    V_RXAPHSUPIN(1U)
53535 
53536 #define A_XGMAC_PORT_HSS_STATUS 0x10ec
53537 
53538 #define S_RXDPRBSSYNC    15
53539 #define V_RXDPRBSSYNC(x) ((x) << S_RXDPRBSSYNC)
53540 #define F_RXDPRBSSYNC    V_RXDPRBSSYNC(1U)
53541 
53542 #define S_RXCPRBSSYNC    14
53543 #define V_RXCPRBSSYNC(x) ((x) << S_RXCPRBSSYNC)
53544 #define F_RXCPRBSSYNC    V_RXCPRBSSYNC(1U)
53545 
53546 #define S_RXBPRBSSYNC    13
53547 #define V_RXBPRBSSYNC(x) ((x) << S_RXBPRBSSYNC)
53548 #define F_RXBPRBSSYNC    V_RXBPRBSSYNC(1U)
53549 
53550 #define S_RXAPRBSSYNC    12
53551 #define V_RXAPRBSSYNC(x) ((x) << S_RXAPRBSSYNC)
53552 #define F_RXAPRBSSYNC    V_RXAPRBSSYNC(1U)
53553 
53554 #define S_RXDPRBSERR    11
53555 #define V_RXDPRBSERR(x) ((x) << S_RXDPRBSERR)
53556 #define F_RXDPRBSERR    V_RXDPRBSERR(1U)
53557 
53558 #define S_RXCPRBSERR    10
53559 #define V_RXCPRBSERR(x) ((x) << S_RXCPRBSERR)
53560 #define F_RXCPRBSERR    V_RXCPRBSERR(1U)
53561 
53562 #define S_RXBPRBSERR    9
53563 #define V_RXBPRBSERR(x) ((x) << S_RXBPRBSERR)
53564 #define F_RXBPRBSERR    V_RXBPRBSERR(1U)
53565 
53566 #define S_RXAPRBSERR    8
53567 #define V_RXAPRBSERR(x) ((x) << S_RXAPRBSERR)
53568 #define F_RXAPRBSERR    V_RXAPRBSERR(1U)
53569 
53570 #define S_RXDSIGDET    7
53571 #define V_RXDSIGDET(x) ((x) << S_RXDSIGDET)
53572 #define F_RXDSIGDET    V_RXDSIGDET(1U)
53573 
53574 #define S_RXCSIGDET    6
53575 #define V_RXCSIGDET(x) ((x) << S_RXCSIGDET)
53576 #define F_RXCSIGDET    V_RXCSIGDET(1U)
53577 
53578 #define S_RXBSIGDET    5
53579 #define V_RXBSIGDET(x) ((x) << S_RXBSIGDET)
53580 #define F_RXBSIGDET    V_RXBSIGDET(1U)
53581 
53582 #define S_RXASIGDET    4
53583 #define V_RXASIGDET(x) ((x) << S_RXASIGDET)
53584 #define F_RXASIGDET    V_RXASIGDET(1U)
53585 
53586 #define S_HSSPLLLOCK    1
53587 #define V_HSSPLLLOCK(x) ((x) << S_HSSPLLLOCK)
53588 #define F_HSSPLLLOCK    V_HSSPLLLOCK(1U)
53589 
53590 #define S_HSSPRTREADY    0
53591 #define V_HSSPRTREADY(x) ((x) << S_HSSPRTREADY)
53592 #define F_HSSPRTREADY    V_HSSPRTREADY(1U)
53593 
53594 #define A_XGMAC_PORT_XGM_TX_CTRL 0x1200
53595 
53596 #define S_SENDPAUSE    2
53597 #define V_SENDPAUSE(x) ((x) << S_SENDPAUSE)
53598 #define F_SENDPAUSE    V_SENDPAUSE(1U)
53599 
53600 #define S_SENDZEROPAUSE    1
53601 #define V_SENDZEROPAUSE(x) ((x) << S_SENDZEROPAUSE)
53602 #define F_SENDZEROPAUSE    V_SENDZEROPAUSE(1U)
53603 
53604 #define S_XGM_TXEN    0
53605 #define V_XGM_TXEN(x) ((x) << S_XGM_TXEN)
53606 #define F_XGM_TXEN    V_XGM_TXEN(1U)
53607 
53608 #define A_XGMAC_PORT_XGM_TX_CFG 0x1204
53609 
53610 #define S_CRCCAL    8
53611 #define M_CRCCAL    0x3U
53612 #define V_CRCCAL(x) ((x) << S_CRCCAL)
53613 #define G_CRCCAL(x) (((x) >> S_CRCCAL) & M_CRCCAL)
53614 
53615 #define S_DISDEFIDLECNT    7
53616 #define V_DISDEFIDLECNT(x) ((x) << S_DISDEFIDLECNT)
53617 #define F_DISDEFIDLECNT    V_DISDEFIDLECNT(1U)
53618 
53619 #define S_DECAVGTXIPG    6
53620 #define V_DECAVGTXIPG(x) ((x) << S_DECAVGTXIPG)
53621 #define F_DECAVGTXIPG    V_DECAVGTXIPG(1U)
53622 
53623 #define S_UNIDIRTXEN    5
53624 #define V_UNIDIRTXEN(x) ((x) << S_UNIDIRTXEN)
53625 #define F_UNIDIRTXEN    V_UNIDIRTXEN(1U)
53626 
53627 #define S_CFGCLKSPEED    2
53628 #define M_CFGCLKSPEED    0x7U
53629 #define V_CFGCLKSPEED(x) ((x) << S_CFGCLKSPEED)
53630 #define G_CFGCLKSPEED(x) (((x) >> S_CFGCLKSPEED) & M_CFGCLKSPEED)
53631 
53632 #define S_STRETCHMODE    1
53633 #define V_STRETCHMODE(x) ((x) << S_STRETCHMODE)
53634 #define F_STRETCHMODE    V_STRETCHMODE(1U)
53635 
53636 #define S_TXPAUSEEN    0
53637 #define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
53638 #define F_TXPAUSEEN    V_TXPAUSEEN(1U)
53639 
53640 #define A_XGMAC_PORT_XGM_TX_PAUSE_QUANTA 0x1208
53641 
53642 #define S_TXPAUSEQUANTA    0
53643 #define M_TXPAUSEQUANTA    0xffffU
53644 #define V_TXPAUSEQUANTA(x) ((x) << S_TXPAUSEQUANTA)
53645 #define G_TXPAUSEQUANTA(x) (((x) >> S_TXPAUSEQUANTA) & M_TXPAUSEQUANTA)
53646 
53647 #define A_XGMAC_PORT_XGM_RX_CTRL 0x120c
53648 #define A_XGMAC_PORT_XGM_RX_CFG 0x1210
53649 
53650 #define S_RXCRCCAL    16
53651 #define M_RXCRCCAL    0x3U
53652 #define V_RXCRCCAL(x) ((x) << S_RXCRCCAL)
53653 #define G_RXCRCCAL(x) (((x) >> S_RXCRCCAL) & M_RXCRCCAL)
53654 
53655 #define S_STATLOCALFAULT    15
53656 #define V_STATLOCALFAULT(x) ((x) << S_STATLOCALFAULT)
53657 #define F_STATLOCALFAULT    V_STATLOCALFAULT(1U)
53658 
53659 #define S_STATREMOTEFAULT    14
53660 #define V_STATREMOTEFAULT(x) ((x) << S_STATREMOTEFAULT)
53661 #define F_STATREMOTEFAULT    V_STATREMOTEFAULT(1U)
53662 
53663 #define S_LENERRFRAMEDIS    13
53664 #define V_LENERRFRAMEDIS(x) ((x) << S_LENERRFRAMEDIS)
53665 #define F_LENERRFRAMEDIS    V_LENERRFRAMEDIS(1U)
53666 
53667 #define S_CON802_3PREAMBLE    12
53668 #define V_CON802_3PREAMBLE(x) ((x) << S_CON802_3PREAMBLE)
53669 #define F_CON802_3PREAMBLE    V_CON802_3PREAMBLE(1U)
53670 
53671 #define S_ENNON802_3PREAMBLE    11
53672 #define V_ENNON802_3PREAMBLE(x) ((x) << S_ENNON802_3PREAMBLE)
53673 #define F_ENNON802_3PREAMBLE    V_ENNON802_3PREAMBLE(1U)
53674 
53675 #define S_COPYPREAMBLE    10
53676 #define V_COPYPREAMBLE(x) ((x) << S_COPYPREAMBLE)
53677 #define F_COPYPREAMBLE    V_COPYPREAMBLE(1U)
53678 
53679 #define S_DISPAUSEFRAMES    9
53680 #define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES)
53681 #define F_DISPAUSEFRAMES    V_DISPAUSEFRAMES(1U)
53682 
53683 #define S_EN1536BFRAMES    8
53684 #define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES)
53685 #define F_EN1536BFRAMES    V_EN1536BFRAMES(1U)
53686 
53687 #define S_ENJUMBO    7
53688 #define V_ENJUMBO(x) ((x) << S_ENJUMBO)
53689 #define F_ENJUMBO    V_ENJUMBO(1U)
53690 
53691 #define S_RMFCS    6
53692 #define V_RMFCS(x) ((x) << S_RMFCS)
53693 #define F_RMFCS    V_RMFCS(1U)
53694 
53695 #define S_DISNONVLAN    5
53696 #define V_DISNONVLAN(x) ((x) << S_DISNONVLAN)
53697 #define F_DISNONVLAN    V_DISNONVLAN(1U)
53698 
53699 #define S_ENEXTMATCH    4
53700 #define V_ENEXTMATCH(x) ((x) << S_ENEXTMATCH)
53701 #define F_ENEXTMATCH    V_ENEXTMATCH(1U)
53702 
53703 #define S_ENHASHUCAST    3
53704 #define V_ENHASHUCAST(x) ((x) << S_ENHASHUCAST)
53705 #define F_ENHASHUCAST    V_ENHASHUCAST(1U)
53706 
53707 #define S_ENHASHMCAST    2
53708 #define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST)
53709 #define F_ENHASHMCAST    V_ENHASHMCAST(1U)
53710 
53711 #define S_DISBCAST    1
53712 #define V_DISBCAST(x) ((x) << S_DISBCAST)
53713 #define F_DISBCAST    V_DISBCAST(1U)
53714 
53715 #define S_COPYALLFRAMES    0
53716 #define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES)
53717 #define F_COPYALLFRAMES    V_COPYALLFRAMES(1U)
53718 
53719 #define A_XGMAC_PORT_XGM_RX_HASH_LOW 0x1214
53720 #define A_XGMAC_PORT_XGM_RX_HASH_HIGH 0x1218
53721 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_1 0x121c
53722 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_1 0x1220
53723 
53724 #define S_ADDRESS_HIGH    0
53725 #define M_ADDRESS_HIGH    0xffffU
53726 #define V_ADDRESS_HIGH(x) ((x) << S_ADDRESS_HIGH)
53727 #define G_ADDRESS_HIGH(x) (((x) >> S_ADDRESS_HIGH) & M_ADDRESS_HIGH)
53728 
53729 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_2 0x1224
53730 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_2 0x1228
53731 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_3 0x122c
53732 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_3 0x1230
53733 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_4 0x1234
53734 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_4 0x1238
53735 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_5 0x123c
53736 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_5 0x1240
53737 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_6 0x1244
53738 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_6 0x1248
53739 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_7 0x124c
53740 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_7 0x1250
53741 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_8 0x1254
53742 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_8 0x1258
53743 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_1 0x125c
53744 
53745 #define S_ENTYPEMATCH    31
53746 #define V_ENTYPEMATCH(x) ((x) << S_ENTYPEMATCH)
53747 #define F_ENTYPEMATCH    V_ENTYPEMATCH(1U)
53748 
53749 #define S_TYPE    0
53750 #define M_TYPE    0xffffU
53751 #define V_TYPE(x) ((x) << S_TYPE)
53752 #define G_TYPE(x) (((x) >> S_TYPE) & M_TYPE)
53753 
53754 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_2 0x1260
53755 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_3 0x1264
53756 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_4 0x1268
53757 #define A_XGMAC_PORT_XGM_INT_STATUS 0x126c
53758 
53759 #define S_XGMIIEXTINT    10
53760 #define V_XGMIIEXTINT(x) ((x) << S_XGMIIEXTINT)
53761 #define F_XGMIIEXTINT    V_XGMIIEXTINT(1U)
53762 
53763 #define S_LINKFAULTCHANGE    9
53764 #define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE)
53765 #define F_LINKFAULTCHANGE    V_LINKFAULTCHANGE(1U)
53766 
53767 #define S_PHYFRAMECOMPLETE    8
53768 #define V_PHYFRAMECOMPLETE(x) ((x) << S_PHYFRAMECOMPLETE)
53769 #define F_PHYFRAMECOMPLETE    V_PHYFRAMECOMPLETE(1U)
53770 
53771 #define S_PAUSEFRAMETXMT    7
53772 #define V_PAUSEFRAMETXMT(x) ((x) << S_PAUSEFRAMETXMT)
53773 #define F_PAUSEFRAMETXMT    V_PAUSEFRAMETXMT(1U)
53774 
53775 #define S_PAUSECNTRTIMEOUT    6
53776 #define V_PAUSECNTRTIMEOUT(x) ((x) << S_PAUSECNTRTIMEOUT)
53777 #define F_PAUSECNTRTIMEOUT    V_PAUSECNTRTIMEOUT(1U)
53778 
53779 #define S_NON0PAUSERCVD    5
53780 #define V_NON0PAUSERCVD(x) ((x) << S_NON0PAUSERCVD)
53781 #define F_NON0PAUSERCVD    V_NON0PAUSERCVD(1U)
53782 
53783 #define S_STATOFLOW    4
53784 #define V_STATOFLOW(x) ((x) << S_STATOFLOW)
53785 #define F_STATOFLOW    V_STATOFLOW(1U)
53786 
53787 #define S_TXERRFIFO    3
53788 #define V_TXERRFIFO(x) ((x) << S_TXERRFIFO)
53789 #define F_TXERRFIFO    V_TXERRFIFO(1U)
53790 
53791 #define S_TXUFLOW    2
53792 #define V_TXUFLOW(x) ((x) << S_TXUFLOW)
53793 #define F_TXUFLOW    V_TXUFLOW(1U)
53794 
53795 #define S_FRAMETXMT    1
53796 #define V_FRAMETXMT(x) ((x) << S_FRAMETXMT)
53797 #define F_FRAMETXMT    V_FRAMETXMT(1U)
53798 
53799 #define S_FRAMERCVD    0
53800 #define V_FRAMERCVD(x) ((x) << S_FRAMERCVD)
53801 #define F_FRAMERCVD    V_FRAMERCVD(1U)
53802 
53803 #define A_XGMAC_PORT_XGM_INT_MASK 0x1270
53804 #define A_XGMAC_PORT_XGM_INT_EN 0x1274
53805 #define A_XGMAC_PORT_XGM_INT_DISABLE 0x1278
53806 #define A_XGMAC_PORT_XGM_TX_PAUSE_TIMER 0x127c
53807 
53808 #define S_CURPAUSETIMER    0
53809 #define M_CURPAUSETIMER    0xffffU
53810 #define V_CURPAUSETIMER(x) ((x) << S_CURPAUSETIMER)
53811 #define G_CURPAUSETIMER(x) (((x) >> S_CURPAUSETIMER) & M_CURPAUSETIMER)
53812 
53813 #define A_XGMAC_PORT_XGM_STAT_CTRL 0x1280
53814 
53815 #define S_READSNPSHOT    4
53816 #define V_READSNPSHOT(x) ((x) << S_READSNPSHOT)
53817 #define F_READSNPSHOT    V_READSNPSHOT(1U)
53818 
53819 #define S_TAKESNPSHOT    3
53820 #define V_TAKESNPSHOT(x) ((x) << S_TAKESNPSHOT)
53821 #define F_TAKESNPSHOT    V_TAKESNPSHOT(1U)
53822 
53823 #define S_CLRSTATS    2
53824 #define V_CLRSTATS(x) ((x) << S_CLRSTATS)
53825 #define F_CLRSTATS    V_CLRSTATS(1U)
53826 
53827 #define S_INCRSTATS    1
53828 #define V_INCRSTATS(x) ((x) << S_INCRSTATS)
53829 #define F_INCRSTATS    V_INCRSTATS(1U)
53830 
53831 #define S_ENTESTMODEWR    0
53832 #define V_ENTESTMODEWR(x) ((x) << S_ENTESTMODEWR)
53833 #define F_ENTESTMODEWR    V_ENTESTMODEWR(1U)
53834 
53835 #define A_XGMAC_PORT_XGM_MDIO_CTRL 0x1284
53836 
53837 #define S_FRAMETYPE    30
53838 #define M_FRAMETYPE    0x3U
53839 #define V_FRAMETYPE(x) ((x) << S_FRAMETYPE)
53840 #define G_FRAMETYPE(x) (((x) >> S_FRAMETYPE) & M_FRAMETYPE)
53841 
53842 #define S_OPERATION    28
53843 #define M_OPERATION    0x3U
53844 #define V_OPERATION(x) ((x) << S_OPERATION)
53845 #define G_OPERATION(x) (((x) >> S_OPERATION) & M_OPERATION)
53846 
53847 #define S_PORTADDR    23
53848 #define M_PORTADDR    0x1fU
53849 #define V_PORTADDR(x) ((x) << S_PORTADDR)
53850 #define G_PORTADDR(x) (((x) >> S_PORTADDR) & M_PORTADDR)
53851 
53852 #define S_DEVADDR    18
53853 #define M_DEVADDR    0x1fU
53854 #define V_DEVADDR(x) ((x) << S_DEVADDR)
53855 #define G_DEVADDR(x) (((x) >> S_DEVADDR) & M_DEVADDR)
53856 
53857 #define S_RESRV    16
53858 #define M_RESRV    0x3U
53859 #define V_RESRV(x) ((x) << S_RESRV)
53860 #define G_RESRV(x) (((x) >> S_RESRV) & M_RESRV)
53861 
53862 #define S_DATA    0
53863 #define M_DATA    0xffffU
53864 #define V_DATA(x) ((x) << S_DATA)
53865 #define G_DATA(x) (((x) >> S_DATA) & M_DATA)
53866 
53867 #define A_XGMAC_PORT_XGM_MODULE_ID 0x12fc
53868 
53869 #define S_MODULEID    16
53870 #define M_MODULEID    0xffffU
53871 #define V_MODULEID(x) ((x) << S_MODULEID)
53872 #define G_MODULEID(x) (((x) >> S_MODULEID) & M_MODULEID)
53873 
53874 #define S_MODULEREV    0
53875 #define M_MODULEREV    0xffffU
53876 #define V_MODULEREV(x) ((x) << S_MODULEREV)
53877 #define G_MODULEREV(x) (((x) >> S_MODULEREV) & M_MODULEREV)
53878 
53879 #define A_XGMAC_PORT_XGM_STAT_TX_BYTE_LOW 0x1300
53880 #define A_XGMAC_PORT_XGM_STAT_TX_BYTE_HIGH 0x1304
53881 
53882 #define S_TXBYTES_HIGH    0
53883 #define M_TXBYTES_HIGH    0x1fffU
53884 #define V_TXBYTES_HIGH(x) ((x) << S_TXBYTES_HIGH)
53885 #define G_TXBYTES_HIGH(x) (((x) >> S_TXBYTES_HIGH) & M_TXBYTES_HIGH)
53886 
53887 #define A_XGMAC_PORT_XGM_STAT_TX_FRAME_LOW 0x1308
53888 #define A_XGMAC_PORT_XGM_STAT_TX_FRAME_HIGH 0x130c
53889 
53890 #define S_TXFRAMES_HIGH    0
53891 #define M_TXFRAMES_HIGH    0xfU
53892 #define V_TXFRAMES_HIGH(x) ((x) << S_TXFRAMES_HIGH)
53893 #define G_TXFRAMES_HIGH(x) (((x) >> S_TXFRAMES_HIGH) & M_TXFRAMES_HIGH)
53894 
53895 #define A_XGMAC_PORT_XGM_STAT_TX_BCAST 0x1310
53896 #define A_XGMAC_PORT_XGM_STAT_TX_MCAST 0x1314
53897 #define A_XGMAC_PORT_XGM_STAT_TX_PAUSE 0x1318
53898 #define A_XGMAC_PORT_XGM_STAT_TX_64B_FRAMES 0x131c
53899 #define A_XGMAC_PORT_XGM_STAT_TX_65_127B_FRAMES 0x1320
53900 #define A_XGMAC_PORT_XGM_STAT_TX_128_255B_FRAMES 0x1324
53901 #define A_XGMAC_PORT_XGM_STAT_TX_256_511B_FRAMES 0x1328
53902 #define A_XGMAC_PORT_XGM_STAT_TX_512_1023B_FRAMES 0x132c
53903 #define A_XGMAC_PORT_XGM_STAT_TX_1024_1518B_FRAMES 0x1330
53904 #define A_XGMAC_PORT_XGM_STAT_TX_1519_MAXB_FRAMES 0x1334
53905 #define A_XGMAC_PORT_XGM_STAT_TX_ERR_FRAMES 0x1338
53906 #define A_XGMAC_PORT_XGM_STAT_RX_BYTES_LOW 0x133c
53907 #define A_XGMAC_PORT_XGM_STAT_RX_BYTES_HIGH 0x1340
53908 
53909 #define S_RXBYTES_HIGH    0
53910 #define M_RXBYTES_HIGH    0x1fffU
53911 #define V_RXBYTES_HIGH(x) ((x) << S_RXBYTES_HIGH)
53912 #define G_RXBYTES_HIGH(x) (((x) >> S_RXBYTES_HIGH) & M_RXBYTES_HIGH)
53913 
53914 #define A_XGMAC_PORT_XGM_STAT_RX_FRAMES_LOW 0x1344
53915 #define A_XGMAC_PORT_XGM_STAT_RX_FRAMES_HIGH 0x1348
53916 
53917 #define S_RXFRAMES_HIGH    0
53918 #define M_RXFRAMES_HIGH    0xfU
53919 #define V_RXFRAMES_HIGH(x) ((x) << S_RXFRAMES_HIGH)
53920 #define G_RXFRAMES_HIGH(x) (((x) >> S_RXFRAMES_HIGH) & M_RXFRAMES_HIGH)
53921 
53922 #define A_XGMAC_PORT_XGM_STAT_RX_BCAST_FRAMES 0x134c
53923 #define A_XGMAC_PORT_XGM_STAT_RX_MCAST_FRAMES 0x1350
53924 #define A_XGMAC_PORT_XGM_STAT_RX_PAUSE_FRAMES 0x1354
53925 
53926 #define S_RXPAUSEFRAMES    0
53927 #define M_RXPAUSEFRAMES    0xffffU
53928 #define V_RXPAUSEFRAMES(x) ((x) << S_RXPAUSEFRAMES)
53929 #define G_RXPAUSEFRAMES(x) (((x) >> S_RXPAUSEFRAMES) & M_RXPAUSEFRAMES)
53930 
53931 #define A_XGMAC_PORT_XGM_STAT_RX_64B_FRAMES 0x1358
53932 #define A_XGMAC_PORT_XGM_STAT_RX_65_127B_FRAMES 0x135c
53933 #define A_XGMAC_PORT_XGM_STAT_RX_128_255B_FRAMES 0x1360
53934 #define A_XGMAC_PORT_XGM_STAT_RX_256_511B_FRAMES 0x1364
53935 #define A_XGMAC_PORT_XGM_STAT_RX_512_1023B_FRAMES 0x1368
53936 #define A_XGMAC_PORT_XGM_STAT_RX_1024_1518B_FRAMES 0x136c
53937 #define A_XGMAC_PORT_XGM_STAT_RX_1519_MAXB_FRAMES 0x1370
53938 #define A_XGMAC_PORT_XGM_STAT_RX_SHORT_FRAMES 0x1374
53939 
53940 #define S_RXSHORTFRAMES    0
53941 #define M_RXSHORTFRAMES    0xffffU
53942 #define V_RXSHORTFRAMES(x) ((x) << S_RXSHORTFRAMES)
53943 #define G_RXSHORTFRAMES(x) (((x) >> S_RXSHORTFRAMES) & M_RXSHORTFRAMES)
53944 
53945 #define A_XGMAC_PORT_XGM_STAT_RX_OVERSIZE_FRAMES 0x1378
53946 
53947 #define S_RXOVERSIZEFRAMES    0
53948 #define M_RXOVERSIZEFRAMES    0xffffU
53949 #define V_RXOVERSIZEFRAMES(x) ((x) << S_RXOVERSIZEFRAMES)
53950 #define G_RXOVERSIZEFRAMES(x) (((x) >> S_RXOVERSIZEFRAMES) & M_RXOVERSIZEFRAMES)
53951 
53952 #define A_XGMAC_PORT_XGM_STAT_RX_JABBER_FRAMES 0x137c
53953 
53954 #define S_RXJABBERFRAMES    0
53955 #define M_RXJABBERFRAMES    0xffffU
53956 #define V_RXJABBERFRAMES(x) ((x) << S_RXJABBERFRAMES)
53957 #define G_RXJABBERFRAMES(x) (((x) >> S_RXJABBERFRAMES) & M_RXJABBERFRAMES)
53958 
53959 #define A_XGMAC_PORT_XGM_STAT_RX_CRC_ERR_FRAMES 0x1380
53960 
53961 #define S_RXCRCERRFRAMES    0
53962 #define M_RXCRCERRFRAMES    0xffffU
53963 #define V_RXCRCERRFRAMES(x) ((x) << S_RXCRCERRFRAMES)
53964 #define G_RXCRCERRFRAMES(x) (((x) >> S_RXCRCERRFRAMES) & M_RXCRCERRFRAMES)
53965 
53966 #define A_XGMAC_PORT_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x1384
53967 
53968 #define S_RXLENGTHERRFRAMES    0
53969 #define M_RXLENGTHERRFRAMES    0xffffU
53970 #define V_RXLENGTHERRFRAMES(x) ((x) << S_RXLENGTHERRFRAMES)
53971 #define G_RXLENGTHERRFRAMES(x) (((x) >> S_RXLENGTHERRFRAMES) & M_RXLENGTHERRFRAMES)
53972 
53973 #define A_XGMAC_PORT_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x1388
53974 
53975 #define S_RXSYMCODEERRFRAMES    0
53976 #define M_RXSYMCODEERRFRAMES    0xffffU
53977 #define V_RXSYMCODEERRFRAMES(x) ((x) << S_RXSYMCODEERRFRAMES)
53978 #define G_RXSYMCODEERRFRAMES(x) (((x) >> S_RXSYMCODEERRFRAMES) & M_RXSYMCODEERRFRAMES)
53979 
53980 #define A_XGMAC_PORT_XAUI_CTRL 0x1400
53981 
53982 #define S_POLARITY_INV_RX    8
53983 #define M_POLARITY_INV_RX    0xfU
53984 #define V_POLARITY_INV_RX(x) ((x) << S_POLARITY_INV_RX)
53985 #define G_POLARITY_INV_RX(x) (((x) >> S_POLARITY_INV_RX) & M_POLARITY_INV_RX)
53986 
53987 #define S_POLARITY_INV_TX    4
53988 #define M_POLARITY_INV_TX    0xfU
53989 #define V_POLARITY_INV_TX(x) ((x) << S_POLARITY_INV_TX)
53990 #define G_POLARITY_INV_TX(x) (((x) >> S_POLARITY_INV_TX) & M_POLARITY_INV_TX)
53991 
53992 #define S_TEST_SEL    2
53993 #define M_TEST_SEL    0x3U
53994 #define V_TEST_SEL(x) ((x) << S_TEST_SEL)
53995 #define G_TEST_SEL(x) (((x) >> S_TEST_SEL) & M_TEST_SEL)
53996 
53997 #define S_TEST_EN    0
53998 #define V_TEST_EN(x) ((x) << S_TEST_EN)
53999 #define F_TEST_EN    V_TEST_EN(1U)
54000 
54001 #define A_XGMAC_PORT_XAUI_STATUS 0x1404
54002 
54003 #define S_DECODE_ERROR    12
54004 #define M_DECODE_ERROR    0xffU
54005 #define V_DECODE_ERROR(x) ((x) << S_DECODE_ERROR)
54006 #define G_DECODE_ERROR(x) (((x) >> S_DECODE_ERROR) & M_DECODE_ERROR)
54007 
54008 #define S_LANE3_CTC_STATUS    11
54009 #define V_LANE3_CTC_STATUS(x) ((x) << S_LANE3_CTC_STATUS)
54010 #define F_LANE3_CTC_STATUS    V_LANE3_CTC_STATUS(1U)
54011 
54012 #define S_LANE2_CTC_STATUS    10
54013 #define V_LANE2_CTC_STATUS(x) ((x) << S_LANE2_CTC_STATUS)
54014 #define F_LANE2_CTC_STATUS    V_LANE2_CTC_STATUS(1U)
54015 
54016 #define S_LANE1_CTC_STATUS    9
54017 #define V_LANE1_CTC_STATUS(x) ((x) << S_LANE1_CTC_STATUS)
54018 #define F_LANE1_CTC_STATUS    V_LANE1_CTC_STATUS(1U)
54019 
54020 #define S_LANE0_CTC_STATUS    8
54021 #define V_LANE0_CTC_STATUS(x) ((x) << S_LANE0_CTC_STATUS)
54022 #define F_LANE0_CTC_STATUS    V_LANE0_CTC_STATUS(1U)
54023 
54024 #define S_ALIGN_STATUS    4
54025 #define V_ALIGN_STATUS(x) ((x) << S_ALIGN_STATUS)
54026 #define F_ALIGN_STATUS    V_ALIGN_STATUS(1U)
54027 
54028 #define S_LANE3_SYNC_STATUS    3
54029 #define V_LANE3_SYNC_STATUS(x) ((x) << S_LANE3_SYNC_STATUS)
54030 #define F_LANE3_SYNC_STATUS    V_LANE3_SYNC_STATUS(1U)
54031 
54032 #define S_LANE2_SYNC_STATUS    2
54033 #define V_LANE2_SYNC_STATUS(x) ((x) << S_LANE2_SYNC_STATUS)
54034 #define F_LANE2_SYNC_STATUS    V_LANE2_SYNC_STATUS(1U)
54035 
54036 #define S_LANE1_SYNC_STATUS    1
54037 #define V_LANE1_SYNC_STATUS(x) ((x) << S_LANE1_SYNC_STATUS)
54038 #define F_LANE1_SYNC_STATUS    V_LANE1_SYNC_STATUS(1U)
54039 
54040 #define S_LANE0_SYNC_STATUS    0
54041 #define V_LANE0_SYNC_STATUS(x) ((x) << S_LANE0_SYNC_STATUS)
54042 #define F_LANE0_SYNC_STATUS    V_LANE0_SYNC_STATUS(1U)
54043 
54044 #define A_XGMAC_PORT_PCSR_CTRL 0x1500
54045 
54046 #define S_RX_CLK_SPEED    7
54047 #define V_RX_CLK_SPEED(x) ((x) << S_RX_CLK_SPEED)
54048 #define F_RX_CLK_SPEED    V_RX_CLK_SPEED(1U)
54049 
54050 #define S_SCRBYPASS    6
54051 #define V_SCRBYPASS(x) ((x) << S_SCRBYPASS)
54052 #define F_SCRBYPASS    V_SCRBYPASS(1U)
54053 
54054 #define S_FECERRINDEN    5
54055 #define V_FECERRINDEN(x) ((x) << S_FECERRINDEN)
54056 #define F_FECERRINDEN    V_FECERRINDEN(1U)
54057 
54058 #define S_FECEN    4
54059 #define V_FECEN(x) ((x) << S_FECEN)
54060 #define F_FECEN    V_FECEN(1U)
54061 
54062 #define S_TESTSEL    2
54063 #define M_TESTSEL    0x3U
54064 #define V_TESTSEL(x) ((x) << S_TESTSEL)
54065 #define G_TESTSEL(x) (((x) >> S_TESTSEL) & M_TESTSEL)
54066 
54067 #define S_SCRLOOPEN    1
54068 #define V_SCRLOOPEN(x) ((x) << S_SCRLOOPEN)
54069 #define F_SCRLOOPEN    V_SCRLOOPEN(1U)
54070 
54071 #define S_XGMIILOOPEN    0
54072 #define V_XGMIILOOPEN(x) ((x) << S_XGMIILOOPEN)
54073 #define F_XGMIILOOPEN    V_XGMIILOOPEN(1U)
54074 
54075 #define A_XGMAC_PORT_PCSR_TXTEST_CTRL 0x1510
54076 
54077 #define S_TX_PRBS9_EN    4
54078 #define V_TX_PRBS9_EN(x) ((x) << S_TX_PRBS9_EN)
54079 #define F_TX_PRBS9_EN    V_TX_PRBS9_EN(1U)
54080 
54081 #define S_TX_PRBS31_EN    3
54082 #define V_TX_PRBS31_EN(x) ((x) << S_TX_PRBS31_EN)
54083 #define F_TX_PRBS31_EN    V_TX_PRBS31_EN(1U)
54084 
54085 #define S_TX_TST_DAT_SEL    2
54086 #define V_TX_TST_DAT_SEL(x) ((x) << S_TX_TST_DAT_SEL)
54087 #define F_TX_TST_DAT_SEL    V_TX_TST_DAT_SEL(1U)
54088 
54089 #define S_TX_TST_SEL    1
54090 #define V_TX_TST_SEL(x) ((x) << S_TX_TST_SEL)
54091 #define F_TX_TST_SEL    V_TX_TST_SEL(1U)
54092 
54093 #define S_TX_TST_EN    0
54094 #define V_TX_TST_EN(x) ((x) << S_TX_TST_EN)
54095 #define F_TX_TST_EN    V_TX_TST_EN(1U)
54096 
54097 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDA_LOWER 0x1514
54098 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDA_UPPER 0x1518
54099 
54100 #define S_SEEDA_UPPER    0
54101 #define M_SEEDA_UPPER    0x3ffffffU
54102 #define V_SEEDA_UPPER(x) ((x) << S_SEEDA_UPPER)
54103 #define G_SEEDA_UPPER(x) (((x) >> S_SEEDA_UPPER) & M_SEEDA_UPPER)
54104 
54105 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDB_LOWER 0x152c
54106 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDB_UPPER 0x1530
54107 
54108 #define S_SEEDB_UPPER    0
54109 #define M_SEEDB_UPPER    0x3ffffffU
54110 #define V_SEEDB_UPPER(x) ((x) << S_SEEDB_UPPER)
54111 #define G_SEEDB_UPPER(x) (((x) >> S_SEEDB_UPPER) & M_SEEDB_UPPER)
54112 
54113 #define A_XGMAC_PORT_PCSR_RXTEST_CTRL 0x153c
54114 
54115 #define S_TPTER_CNT_RST    7
54116 #define V_TPTER_CNT_RST(x) ((x) << S_TPTER_CNT_RST)
54117 #define F_TPTER_CNT_RST    V_TPTER_CNT_RST(1U)
54118 
54119 #define S_TEST_CNT_125US    6
54120 #define V_TEST_CNT_125US(x) ((x) << S_TEST_CNT_125US)
54121 #define F_TEST_CNT_125US    V_TEST_CNT_125US(1U)
54122 
54123 #define S_TEST_CNT_PRE    5
54124 #define V_TEST_CNT_PRE(x) ((x) << S_TEST_CNT_PRE)
54125 #define F_TEST_CNT_PRE    V_TEST_CNT_PRE(1U)
54126 
54127 #define S_BER_CNT_RST    4
54128 #define V_BER_CNT_RST(x) ((x) << S_BER_CNT_RST)
54129 #define F_BER_CNT_RST    V_BER_CNT_RST(1U)
54130 
54131 #define S_ERR_BLK_CNT_RST    3
54132 #define V_ERR_BLK_CNT_RST(x) ((x) << S_ERR_BLK_CNT_RST)
54133 #define F_ERR_BLK_CNT_RST    V_ERR_BLK_CNT_RST(1U)
54134 
54135 #define S_RX_PRBS31_EN    2
54136 #define V_RX_PRBS31_EN(x) ((x) << S_RX_PRBS31_EN)
54137 #define F_RX_PRBS31_EN    V_RX_PRBS31_EN(1U)
54138 
54139 #define S_RX_TST_DAT_SEL    1
54140 #define V_RX_TST_DAT_SEL(x) ((x) << S_RX_TST_DAT_SEL)
54141 #define F_RX_TST_DAT_SEL    V_RX_TST_DAT_SEL(1U)
54142 
54143 #define S_RX_TST_EN    0
54144 #define V_RX_TST_EN(x) ((x) << S_RX_TST_EN)
54145 #define F_RX_TST_EN    V_RX_TST_EN(1U)
54146 
54147 #define A_XGMAC_PORT_PCSR_STATUS 0x1550
54148 
54149 #define S_ERR_BLK_CNT    16
54150 #define M_ERR_BLK_CNT    0xffU
54151 #define V_ERR_BLK_CNT(x) ((x) << S_ERR_BLK_CNT)
54152 #define G_ERR_BLK_CNT(x) (((x) >> S_ERR_BLK_CNT) & M_ERR_BLK_CNT)
54153 
54154 #define S_BER_COUNT    8
54155 #define M_BER_COUNT    0x3fU
54156 #define V_BER_COUNT(x) ((x) << S_BER_COUNT)
54157 #define G_BER_COUNT(x) (((x) >> S_BER_COUNT) & M_BER_COUNT)
54158 
54159 #define S_HI_BER    2
54160 #define V_HI_BER(x) ((x) << S_HI_BER)
54161 #define F_HI_BER    V_HI_BER(1U)
54162 
54163 #define S_RX_FAULT    1
54164 #define V_RX_FAULT(x) ((x) << S_RX_FAULT)
54165 #define F_RX_FAULT    V_RX_FAULT(1U)
54166 
54167 #define S_TX_FAULT    0
54168 #define V_TX_FAULT(x) ((x) << S_TX_FAULT)
54169 #define F_TX_FAULT    V_TX_FAULT(1U)
54170 
54171 #define A_XGMAC_PORT_PCSR_TEST_STATUS 0x1554
54172 
54173 #define S_TPT_ERR_CNT    0
54174 #define M_TPT_ERR_CNT    0xffffU
54175 #define V_TPT_ERR_CNT(x) ((x) << S_TPT_ERR_CNT)
54176 #define G_TPT_ERR_CNT(x) (((x) >> S_TPT_ERR_CNT) & M_TPT_ERR_CNT)
54177 
54178 #define A_XGMAC_PORT_AN_CONTROL 0x1600
54179 
54180 #define S_SOFT_RESET    15
54181 #define V_SOFT_RESET(x) ((x) << S_SOFT_RESET)
54182 #define F_SOFT_RESET    V_SOFT_RESET(1U)
54183 
54184 #define S_AN_ENABLE    12
54185 #define V_AN_ENABLE(x) ((x) << S_AN_ENABLE)
54186 #define F_AN_ENABLE    V_AN_ENABLE(1U)
54187 
54188 #define S_RESTART_AN    9
54189 #define V_RESTART_AN(x) ((x) << S_RESTART_AN)
54190 #define F_RESTART_AN    V_RESTART_AN(1U)
54191 
54192 #define A_XGMAC_PORT_AN_STATUS 0x1604
54193 
54194 #define S_NONCER_MATCH    31
54195 #define V_NONCER_MATCH(x) ((x) << S_NONCER_MATCH)
54196 #define F_NONCER_MATCH    V_NONCER_MATCH(1U)
54197 
54198 #define S_PARALLEL_DET_FAULT    9
54199 #define V_PARALLEL_DET_FAULT(x) ((x) << S_PARALLEL_DET_FAULT)
54200 #define F_PARALLEL_DET_FAULT    V_PARALLEL_DET_FAULT(1U)
54201 
54202 #define S_PAGE_RECEIVED    6
54203 #define V_PAGE_RECEIVED(x) ((x) << S_PAGE_RECEIVED)
54204 #define F_PAGE_RECEIVED    V_PAGE_RECEIVED(1U)
54205 
54206 #define S_AN_COMPLETE    5
54207 #define V_AN_COMPLETE(x) ((x) << S_AN_COMPLETE)
54208 #define F_AN_COMPLETE    V_AN_COMPLETE(1U)
54209 
54210 #define S_STAT_REMFAULT    4
54211 #define V_STAT_REMFAULT(x) ((x) << S_STAT_REMFAULT)
54212 #define F_STAT_REMFAULT    V_STAT_REMFAULT(1U)
54213 
54214 #define S_AN_ABILITY    3
54215 #define V_AN_ABILITY(x) ((x) << S_AN_ABILITY)
54216 #define F_AN_ABILITY    V_AN_ABILITY(1U)
54217 
54218 #define S_LINK_STATUS    2
54219 #define V_LINK_STATUS(x) ((x) << S_LINK_STATUS)
54220 #define F_LINK_STATUS    V_LINK_STATUS(1U)
54221 
54222 #define S_PARTNER_AN_ABILITY    0
54223 #define V_PARTNER_AN_ABILITY(x) ((x) << S_PARTNER_AN_ABILITY)
54224 #define F_PARTNER_AN_ABILITY    V_PARTNER_AN_ABILITY(1U)
54225 
54226 #define A_XGMAC_PORT_AN_ADVERTISEMENT 0x1608
54227 
54228 #define S_FEC_ENABLE    31
54229 #define V_FEC_ENABLE(x) ((x) << S_FEC_ENABLE)
54230 #define F_FEC_ENABLE    V_FEC_ENABLE(1U)
54231 
54232 #define S_FEC_ABILITY    30
54233 #define V_FEC_ABILITY(x) ((x) << S_FEC_ABILITY)
54234 #define F_FEC_ABILITY    V_FEC_ABILITY(1U)
54235 
54236 #define S_10GBASE_KR_CAPABLE    23
54237 #define V_10GBASE_KR_CAPABLE(x) ((x) << S_10GBASE_KR_CAPABLE)
54238 #define F_10GBASE_KR_CAPABLE    V_10GBASE_KR_CAPABLE(1U)
54239 
54240 #define S_10GBASE_KX4_CAPABLE    22
54241 #define V_10GBASE_KX4_CAPABLE(x) ((x) << S_10GBASE_KX4_CAPABLE)
54242 #define F_10GBASE_KX4_CAPABLE    V_10GBASE_KX4_CAPABLE(1U)
54243 
54244 #define S_1000BASE_KX_CAPABLE    21
54245 #define V_1000BASE_KX_CAPABLE(x) ((x) << S_1000BASE_KX_CAPABLE)
54246 #define F_1000BASE_KX_CAPABLE    V_1000BASE_KX_CAPABLE(1U)
54247 
54248 #define S_TRANSMITTED_NONCE    16
54249 #define M_TRANSMITTED_NONCE    0x1fU
54250 #define V_TRANSMITTED_NONCE(x) ((x) << S_TRANSMITTED_NONCE)
54251 #define G_TRANSMITTED_NONCE(x) (((x) >> S_TRANSMITTED_NONCE) & M_TRANSMITTED_NONCE)
54252 
54253 #define S_NP    15
54254 #define V_NP(x) ((x) << S_NP)
54255 #define F_NP    V_NP(1U)
54256 
54257 #define S_ACK    14
54258 #define V_ACK(x) ((x) << S_ACK)
54259 #define F_ACK    V_ACK(1U)
54260 
54261 #define S_REMOTE_FAULT    13
54262 #define V_REMOTE_FAULT(x) ((x) << S_REMOTE_FAULT)
54263 #define F_REMOTE_FAULT    V_REMOTE_FAULT(1U)
54264 
54265 #define S_ASM_DIR    11
54266 #define V_ASM_DIR(x) ((x) << S_ASM_DIR)
54267 #define F_ASM_DIR    V_ASM_DIR(1U)
54268 
54269 #define S_PAUSE    10
54270 #define V_PAUSE(x) ((x) << S_PAUSE)
54271 #define F_PAUSE    V_PAUSE(1U)
54272 
54273 #define S_ECHOED_NONCE    5
54274 #define M_ECHOED_NONCE    0x1fU
54275 #define V_ECHOED_NONCE(x) ((x) << S_ECHOED_NONCE)
54276 #define G_ECHOED_NONCE(x) (((x) >> S_ECHOED_NONCE) & M_ECHOED_NONCE)
54277 
54278 #define A_XGMAC_PORT_AN_LINK_PARTNER_ABILITY 0x160c
54279 
54280 #define S_SELECTOR_FIELD    0
54281 #define M_SELECTOR_FIELD    0x1fU
54282 #define V_SELECTOR_FIELD(x) ((x) << S_SELECTOR_FIELD)
54283 #define G_SELECTOR_FIELD(x) (((x) >> S_SELECTOR_FIELD) & M_SELECTOR_FIELD)
54284 
54285 #define A_XGMAC_PORT_AN_NP_LOWER_TRANSMIT 0x1610
54286 
54287 #define S_NP_INFO    16
54288 #define M_NP_INFO    0xffffU
54289 #define V_NP_INFO(x) ((x) << S_NP_INFO)
54290 #define G_NP_INFO(x) (((x) >> S_NP_INFO) & M_NP_INFO)
54291 
54292 #define S_NP_INDICATION    15
54293 #define V_NP_INDICATION(x) ((x) << S_NP_INDICATION)
54294 #define F_NP_INDICATION    V_NP_INDICATION(1U)
54295 
54296 #define S_MESSAGE_PAGE    13
54297 #define V_MESSAGE_PAGE(x) ((x) << S_MESSAGE_PAGE)
54298 #define F_MESSAGE_PAGE    V_MESSAGE_PAGE(1U)
54299 
54300 #define S_ACK_2    12
54301 #define V_ACK_2(x) ((x) << S_ACK_2)
54302 #define F_ACK_2    V_ACK_2(1U)
54303 
54304 #define S_TOGGLE    11
54305 #define V_TOGGLE(x) ((x) << S_TOGGLE)
54306 #define F_TOGGLE    V_TOGGLE(1U)
54307 
54308 #define A_XGMAC_PORT_AN_NP_UPPER_TRANSMIT 0x1614
54309 
54310 #define S_NP_INFO_HI    0
54311 #define M_NP_INFO_HI    0xffffU
54312 #define V_NP_INFO_HI(x) ((x) << S_NP_INFO_HI)
54313 #define G_NP_INFO_HI(x) (((x) >> S_NP_INFO_HI) & M_NP_INFO_HI)
54314 
54315 #define A_XGMAC_PORT_AN_LP_NP_LOWER 0x1618
54316 #define A_XGMAC_PORT_AN_LP_NP_UPPER 0x161c
54317 #define A_XGMAC_PORT_AN_BACKPLANE_ETHERNET_STATUS 0x1624
54318 
54319 #define S_TX_PAUSE_OKAY    6
54320 #define V_TX_PAUSE_OKAY(x) ((x) << S_TX_PAUSE_OKAY)
54321 #define F_TX_PAUSE_OKAY    V_TX_PAUSE_OKAY(1U)
54322 
54323 #define S_RX_PAUSE_OKAY    5
54324 #define V_RX_PAUSE_OKAY(x) ((x) << S_RX_PAUSE_OKAY)
54325 #define F_RX_PAUSE_OKAY    V_RX_PAUSE_OKAY(1U)
54326 
54327 #define S_10GBASE_KR_FEC_NEG    4
54328 #define V_10GBASE_KR_FEC_NEG(x) ((x) << S_10GBASE_KR_FEC_NEG)
54329 #define F_10GBASE_KR_FEC_NEG    V_10GBASE_KR_FEC_NEG(1U)
54330 
54331 #define S_10GBASE_KR_NEG    3
54332 #define V_10GBASE_KR_NEG(x) ((x) << S_10GBASE_KR_NEG)
54333 #define F_10GBASE_KR_NEG    V_10GBASE_KR_NEG(1U)
54334 
54335 #define S_10GBASE_KX4_NEG    2
54336 #define V_10GBASE_KX4_NEG(x) ((x) << S_10GBASE_KX4_NEG)
54337 #define F_10GBASE_KX4_NEG    V_10GBASE_KX4_NEG(1U)
54338 
54339 #define S_1000BASE_KX_NEG    1
54340 #define V_1000BASE_KX_NEG(x) ((x) << S_1000BASE_KX_NEG)
54341 #define F_1000BASE_KX_NEG    V_1000BASE_KX_NEG(1U)
54342 
54343 #define S_BP_AN_ABILITY    0
54344 #define V_BP_AN_ABILITY(x) ((x) << S_BP_AN_ABILITY)
54345 #define F_BP_AN_ABILITY    V_BP_AN_ABILITY(1U)
54346 
54347 #define A_XGMAC_PORT_AN_TX_NONCE_CONTROL 0x1628
54348 
54349 #define S_BYPASS_LFSR    15
54350 #define V_BYPASS_LFSR(x) ((x) << S_BYPASS_LFSR)
54351 #define F_BYPASS_LFSR    V_BYPASS_LFSR(1U)
54352 
54353 #define S_LFSR_INIT    0
54354 #define M_LFSR_INIT    0x7fffU
54355 #define V_LFSR_INIT(x) ((x) << S_LFSR_INIT)
54356 #define G_LFSR_INIT(x) (((x) >> S_LFSR_INIT) & M_LFSR_INIT)
54357 
54358 #define A_XGMAC_PORT_AN_INTERRUPT_STATUS 0x162c
54359 
54360 #define S_NP_FROM_LP    3
54361 #define V_NP_FROM_LP(x) ((x) << S_NP_FROM_LP)
54362 #define F_NP_FROM_LP    V_NP_FROM_LP(1U)
54363 
54364 #define S_PARALLELDETFAULTINT    2
54365 #define V_PARALLELDETFAULTINT(x) ((x) << S_PARALLELDETFAULTINT)
54366 #define F_PARALLELDETFAULTINT    V_PARALLELDETFAULTINT(1U)
54367 
54368 #define S_BP_FROM_LP    1
54369 #define V_BP_FROM_LP(x) ((x) << S_BP_FROM_LP)
54370 #define F_BP_FROM_LP    V_BP_FROM_LP(1U)
54371 
54372 #define S_PCS_AN_COMPLETE    0
54373 #define V_PCS_AN_COMPLETE(x) ((x) << S_PCS_AN_COMPLETE)
54374 #define F_PCS_AN_COMPLETE    V_PCS_AN_COMPLETE(1U)
54375 
54376 #define A_XGMAC_PORT_AN_GENERIC_TIMER_TIMEOUT 0x1630
54377 
54378 #define S_GENERIC_TIMEOUT    0
54379 #define M_GENERIC_TIMEOUT    0x7fffffU
54380 #define V_GENERIC_TIMEOUT(x) ((x) << S_GENERIC_TIMEOUT)
54381 #define G_GENERIC_TIMEOUT(x) (((x) >> S_GENERIC_TIMEOUT) & M_GENERIC_TIMEOUT)
54382 
54383 #define A_XGMAC_PORT_AN_BREAK_LINK_TIMEOUT 0x1634
54384 
54385 #define S_BREAK_LINK_TIMEOUT    0
54386 #define M_BREAK_LINK_TIMEOUT    0xffffffU
54387 #define V_BREAK_LINK_TIMEOUT(x) ((x) << S_BREAK_LINK_TIMEOUT)
54388 #define G_BREAK_LINK_TIMEOUT(x) (((x) >> S_BREAK_LINK_TIMEOUT) & M_BREAK_LINK_TIMEOUT)
54389 
54390 #define A_XGMAC_PORT_AN_MODULE_ID 0x163c
54391 
54392 #define S_MODULE_ID    16
54393 #define M_MODULE_ID    0xffffU
54394 #define V_MODULE_ID(x) ((x) << S_MODULE_ID)
54395 #define G_MODULE_ID(x) (((x) >> S_MODULE_ID) & M_MODULE_ID)
54396 
54397 #define S_MODULE_REVISION    0
54398 #define M_MODULE_REVISION    0xffffU
54399 #define V_MODULE_REVISION(x) ((x) << S_MODULE_REVISION)
54400 #define G_MODULE_REVISION(x) (((x) >> S_MODULE_REVISION) & M_MODULE_REVISION)
54401 
54402 #define A_XGMAC_PORT_AE_RX_COEF_REQ 0x1700
54403 
54404 #define S_RXREQ_CPRE    13
54405 #define V_RXREQ_CPRE(x) ((x) << S_RXREQ_CPRE)
54406 #define F_RXREQ_CPRE    V_RXREQ_CPRE(1U)
54407 
54408 #define S_RXREQ_CINIT    12
54409 #define V_RXREQ_CINIT(x) ((x) << S_RXREQ_CINIT)
54410 #define F_RXREQ_CINIT    V_RXREQ_CINIT(1U)
54411 
54412 #define S_RXREQ_C0    4
54413 #define M_RXREQ_C0    0x3U
54414 #define V_RXREQ_C0(x) ((x) << S_RXREQ_C0)
54415 #define G_RXREQ_C0(x) (((x) >> S_RXREQ_C0) & M_RXREQ_C0)
54416 
54417 #define S_RXREQ_C1    2
54418 #define M_RXREQ_C1    0x3U
54419 #define V_RXREQ_C1(x) ((x) << S_RXREQ_C1)
54420 #define G_RXREQ_C1(x) (((x) >> S_RXREQ_C1) & M_RXREQ_C1)
54421 
54422 #define S_RXREQ_C2    0
54423 #define M_RXREQ_C2    0x3U
54424 #define V_RXREQ_C2(x) ((x) << S_RXREQ_C2)
54425 #define G_RXREQ_C2(x) (((x) >> S_RXREQ_C2) & M_RXREQ_C2)
54426 
54427 #define A_XGMAC_PORT_AE_RX_COEF_STAT 0x1704
54428 
54429 #define S_RXSTAT_RDY    15
54430 #define V_RXSTAT_RDY(x) ((x) << S_RXSTAT_RDY)
54431 #define F_RXSTAT_RDY    V_RXSTAT_RDY(1U)
54432 
54433 #define S_RXSTAT_C0    4
54434 #define M_RXSTAT_C0    0x3U
54435 #define V_RXSTAT_C0(x) ((x) << S_RXSTAT_C0)
54436 #define G_RXSTAT_C0(x) (((x) >> S_RXSTAT_C0) & M_RXSTAT_C0)
54437 
54438 #define S_RXSTAT_C1    2
54439 #define M_RXSTAT_C1    0x3U
54440 #define V_RXSTAT_C1(x) ((x) << S_RXSTAT_C1)
54441 #define G_RXSTAT_C1(x) (((x) >> S_RXSTAT_C1) & M_RXSTAT_C1)
54442 
54443 #define S_RXSTAT_C2    0
54444 #define M_RXSTAT_C2    0x3U
54445 #define V_RXSTAT_C2(x) ((x) << S_RXSTAT_C2)
54446 #define G_RXSTAT_C2(x) (((x) >> S_RXSTAT_C2) & M_RXSTAT_C2)
54447 
54448 #define A_XGMAC_PORT_AE_TX_COEF_REQ 0x1708
54449 
54450 #define S_TXREQ_CPRE    13
54451 #define V_TXREQ_CPRE(x) ((x) << S_TXREQ_CPRE)
54452 #define F_TXREQ_CPRE    V_TXREQ_CPRE(1U)
54453 
54454 #define S_TXREQ_CINIT    12
54455 #define V_TXREQ_CINIT(x) ((x) << S_TXREQ_CINIT)
54456 #define F_TXREQ_CINIT    V_TXREQ_CINIT(1U)
54457 
54458 #define S_TXREQ_C0    4
54459 #define M_TXREQ_C0    0x3U
54460 #define V_TXREQ_C0(x) ((x) << S_TXREQ_C0)
54461 #define G_TXREQ_C0(x) (((x) >> S_TXREQ_C0) & M_TXREQ_C0)
54462 
54463 #define S_TXREQ_C1    2
54464 #define M_TXREQ_C1    0x3U
54465 #define V_TXREQ_C1(x) ((x) << S_TXREQ_C1)
54466 #define G_TXREQ_C1(x) (((x) >> S_TXREQ_C1) & M_TXREQ_C1)
54467 
54468 #define S_TXREQ_C2    0
54469 #define M_TXREQ_C2    0x3U
54470 #define V_TXREQ_C2(x) ((x) << S_TXREQ_C2)
54471 #define G_TXREQ_C2(x) (((x) >> S_TXREQ_C2) & M_TXREQ_C2)
54472 
54473 #define A_XGMAC_PORT_AE_TX_COEF_STAT 0x170c
54474 
54475 #define S_TXSTAT_RDY    15
54476 #define V_TXSTAT_RDY(x) ((x) << S_TXSTAT_RDY)
54477 #define F_TXSTAT_RDY    V_TXSTAT_RDY(1U)
54478 
54479 #define S_TXSTAT_C0    4
54480 #define M_TXSTAT_C0    0x3U
54481 #define V_TXSTAT_C0(x) ((x) << S_TXSTAT_C0)
54482 #define G_TXSTAT_C0(x) (((x) >> S_TXSTAT_C0) & M_TXSTAT_C0)
54483 
54484 #define S_TXSTAT_C1    2
54485 #define M_TXSTAT_C1    0x3U
54486 #define V_TXSTAT_C1(x) ((x) << S_TXSTAT_C1)
54487 #define G_TXSTAT_C1(x) (((x) >> S_TXSTAT_C1) & M_TXSTAT_C1)
54488 
54489 #define S_TXSTAT_C2    0
54490 #define M_TXSTAT_C2    0x3U
54491 #define V_TXSTAT_C2(x) ((x) << S_TXSTAT_C2)
54492 #define G_TXSTAT_C2(x) (((x) >> S_TXSTAT_C2) & M_TXSTAT_C2)
54493 
54494 #define A_XGMAC_PORT_AE_REG_MODE 0x1710
54495 
54496 #define S_MAN_DEC    4
54497 #define M_MAN_DEC    0x3U
54498 #define V_MAN_DEC(x) ((x) << S_MAN_DEC)
54499 #define G_MAN_DEC(x) (((x) >> S_MAN_DEC) & M_MAN_DEC)
54500 
54501 #define S_MANUAL_RDY    3
54502 #define V_MANUAL_RDY(x) ((x) << S_MANUAL_RDY)
54503 #define F_MANUAL_RDY    V_MANUAL_RDY(1U)
54504 
54505 #define S_MWT_DISABLE    2
54506 #define V_MWT_DISABLE(x) ((x) << S_MWT_DISABLE)
54507 #define F_MWT_DISABLE    V_MWT_DISABLE(1U)
54508 
54509 #define S_MDIO_OVR    1
54510 #define V_MDIO_OVR(x) ((x) << S_MDIO_OVR)
54511 #define F_MDIO_OVR    V_MDIO_OVR(1U)
54512 
54513 #define S_STICKY_MODE    0
54514 #define V_STICKY_MODE(x) ((x) << S_STICKY_MODE)
54515 #define F_STICKY_MODE    V_STICKY_MODE(1U)
54516 
54517 #define A_XGMAC_PORT_AE_PRBS_CTL 0x1714
54518 
54519 #define S_PRBS_CHK_ERRCNT    8
54520 #define M_PRBS_CHK_ERRCNT    0xffU
54521 #define V_PRBS_CHK_ERRCNT(x) ((x) << S_PRBS_CHK_ERRCNT)
54522 #define G_PRBS_CHK_ERRCNT(x) (((x) >> S_PRBS_CHK_ERRCNT) & M_PRBS_CHK_ERRCNT)
54523 
54524 #define S_PRBS_SYNCCNT    5
54525 #define M_PRBS_SYNCCNT    0x7U
54526 #define V_PRBS_SYNCCNT(x) ((x) << S_PRBS_SYNCCNT)
54527 #define G_PRBS_SYNCCNT(x) (((x) >> S_PRBS_SYNCCNT) & M_PRBS_SYNCCNT)
54528 
54529 #define S_PRBS_CHK_SYNC    4
54530 #define V_PRBS_CHK_SYNC(x) ((x) << S_PRBS_CHK_SYNC)
54531 #define F_PRBS_CHK_SYNC    V_PRBS_CHK_SYNC(1U)
54532 
54533 #define S_PRBS_CHK_RST    3
54534 #define V_PRBS_CHK_RST(x) ((x) << S_PRBS_CHK_RST)
54535 #define F_PRBS_CHK_RST    V_PRBS_CHK_RST(1U)
54536 
54537 #define S_PRBS_CHK_OFF    2
54538 #define V_PRBS_CHK_OFF(x) ((x) << S_PRBS_CHK_OFF)
54539 #define F_PRBS_CHK_OFF    V_PRBS_CHK_OFF(1U)
54540 
54541 #define S_PRBS_GEN_FRCERR    1
54542 #define V_PRBS_GEN_FRCERR(x) ((x) << S_PRBS_GEN_FRCERR)
54543 #define F_PRBS_GEN_FRCERR    V_PRBS_GEN_FRCERR(1U)
54544 
54545 #define S_PRBS_GEN_OFF    0
54546 #define V_PRBS_GEN_OFF(x) ((x) << S_PRBS_GEN_OFF)
54547 #define F_PRBS_GEN_OFF    V_PRBS_GEN_OFF(1U)
54548 
54549 #define A_XGMAC_PORT_AE_FSM_CTL 0x1718
54550 
54551 #define S_FSM_TR_LCL    14
54552 #define V_FSM_TR_LCL(x) ((x) << S_FSM_TR_LCL)
54553 #define F_FSM_TR_LCL    V_FSM_TR_LCL(1U)
54554 
54555 #define S_FSM_GDMRK    11
54556 #define M_FSM_GDMRK    0x7U
54557 #define V_FSM_GDMRK(x) ((x) << S_FSM_GDMRK)
54558 #define G_FSM_GDMRK(x) (((x) >> S_FSM_GDMRK) & M_FSM_GDMRK)
54559 
54560 #define S_FSM_BADMRK    8
54561 #define M_FSM_BADMRK    0x7U
54562 #define V_FSM_BADMRK(x) ((x) << S_FSM_BADMRK)
54563 #define G_FSM_BADMRK(x) (((x) >> S_FSM_BADMRK) & M_FSM_BADMRK)
54564 
54565 #define S_FSM_TR_FAIL    7
54566 #define V_FSM_TR_FAIL(x) ((x) << S_FSM_TR_FAIL)
54567 #define F_FSM_TR_FAIL    V_FSM_TR_FAIL(1U)
54568 
54569 #define S_FSM_TR_ACT    6
54570 #define V_FSM_TR_ACT(x) ((x) << S_FSM_TR_ACT)
54571 #define F_FSM_TR_ACT    V_FSM_TR_ACT(1U)
54572 
54573 #define S_FSM_FRM_LCK    5
54574 #define V_FSM_FRM_LCK(x) ((x) << S_FSM_FRM_LCK)
54575 #define F_FSM_FRM_LCK    V_FSM_FRM_LCK(1U)
54576 
54577 #define S_FSM_TR_COMP    4
54578 #define V_FSM_TR_COMP(x) ((x) << S_FSM_TR_COMP)
54579 #define F_FSM_TR_COMP    V_FSM_TR_COMP(1U)
54580 
54581 #define S_MC_RX_RDY    3
54582 #define V_MC_RX_RDY(x) ((x) << S_MC_RX_RDY)
54583 #define F_MC_RX_RDY    V_MC_RX_RDY(1U)
54584 
54585 #define S_FSM_CU_DIS    2
54586 #define V_FSM_CU_DIS(x) ((x) << S_FSM_CU_DIS)
54587 #define F_FSM_CU_DIS    V_FSM_CU_DIS(1U)
54588 
54589 #define S_FSM_TR_RST    1
54590 #define V_FSM_TR_RST(x) ((x) << S_FSM_TR_RST)
54591 #define F_FSM_TR_RST    V_FSM_TR_RST(1U)
54592 
54593 #define S_FSM_TR_EN    0
54594 #define V_FSM_TR_EN(x) ((x) << S_FSM_TR_EN)
54595 #define F_FSM_TR_EN    V_FSM_TR_EN(1U)
54596 
54597 #define A_XGMAC_PORT_AE_FSM_STATE 0x171c
54598 
54599 #define S_CC2FSM_STATE    13
54600 #define M_CC2FSM_STATE    0x7U
54601 #define V_CC2FSM_STATE(x) ((x) << S_CC2FSM_STATE)
54602 #define G_CC2FSM_STATE(x) (((x) >> S_CC2FSM_STATE) & M_CC2FSM_STATE)
54603 
54604 #define S_CC1FSM_STATE    10
54605 #define M_CC1FSM_STATE    0x7U
54606 #define V_CC1FSM_STATE(x) ((x) << S_CC1FSM_STATE)
54607 #define G_CC1FSM_STATE(x) (((x) >> S_CC1FSM_STATE) & M_CC1FSM_STATE)
54608 
54609 #define S_CC0FSM_STATE    7
54610 #define M_CC0FSM_STATE    0x7U
54611 #define V_CC0FSM_STATE(x) ((x) << S_CC0FSM_STATE)
54612 #define G_CC0FSM_STATE(x) (((x) >> S_CC0FSM_STATE) & M_CC0FSM_STATE)
54613 
54614 #define S_FLFSM_STATE    4
54615 #define M_FLFSM_STATE    0x7U
54616 #define V_FLFSM_STATE(x) ((x) << S_FLFSM_STATE)
54617 #define G_FLFSM_STATE(x) (((x) >> S_FLFSM_STATE) & M_FLFSM_STATE)
54618 
54619 #define S_TFSM_STATE    0
54620 #define M_TFSM_STATE    0x7U
54621 #define V_TFSM_STATE(x) ((x) << S_TFSM_STATE)
54622 #define G_TFSM_STATE(x) (((x) >> S_TFSM_STATE) & M_TFSM_STATE)
54623 
54624 #define A_XGMAC_PORT_AE_TX_DIS 0x1780
54625 
54626 #define S_PMD_TX_DIS    0
54627 #define V_PMD_TX_DIS(x) ((x) << S_PMD_TX_DIS)
54628 #define F_PMD_TX_DIS    V_PMD_TX_DIS(1U)
54629 
54630 #define A_XGMAC_PORT_AE_KR_CTRL 0x1784
54631 
54632 #define S_TRAINING_ENABLE    1
54633 #define V_TRAINING_ENABLE(x) ((x) << S_TRAINING_ENABLE)
54634 #define F_TRAINING_ENABLE    V_TRAINING_ENABLE(1U)
54635 
54636 #define S_RESTART_TRAINING    0
54637 #define V_RESTART_TRAINING(x) ((x) << S_RESTART_TRAINING)
54638 #define F_RESTART_TRAINING    V_RESTART_TRAINING(1U)
54639 
54640 #define A_XGMAC_PORT_AE_RX_SIGDET 0x1788
54641 
54642 #define S_PMD_SIGDET    0
54643 #define V_PMD_SIGDET(x) ((x) << S_PMD_SIGDET)
54644 #define F_PMD_SIGDET    V_PMD_SIGDET(1U)
54645 
54646 #define A_XGMAC_PORT_AE_KR_STATUS 0x178c
54647 
54648 #define S_TRAINING_FAILURE    3
54649 #define V_TRAINING_FAILURE(x) ((x) << S_TRAINING_FAILURE)
54650 #define F_TRAINING_FAILURE    V_TRAINING_FAILURE(1U)
54651 
54652 #define S_TRAINING    2
54653 #define V_TRAINING(x) ((x) << S_TRAINING)
54654 #define F_TRAINING    V_TRAINING(1U)
54655 
54656 #define S_FRAME_LOCK    1
54657 #define V_FRAME_LOCK(x) ((x) << S_FRAME_LOCK)
54658 #define F_FRAME_LOCK    V_FRAME_LOCK(1U)
54659 
54660 #define S_RX_TRAINED    0
54661 #define V_RX_TRAINED(x) ((x) << S_RX_TRAINED)
54662 #define F_RX_TRAINED    V_RX_TRAINED(1U)
54663 
54664 #define A_XGMAC_PORT_HSS_TXA_MODE_CFG 0x1800
54665 
54666 #define S_BWSEL    2
54667 #define M_BWSEL    0x3U
54668 #define V_BWSEL(x) ((x) << S_BWSEL)
54669 #define G_BWSEL(x) (((x) >> S_BWSEL) & M_BWSEL)
54670 
54671 #define S_RTSEL    0
54672 #define M_RTSEL    0x3U
54673 #define V_RTSEL(x) ((x) << S_RTSEL)
54674 #define G_RTSEL(x) (((x) >> S_RTSEL) & M_RTSEL)
54675 
54676 #define A_XGMAC_PORT_HSS_TXA_TEST_CTRL 0x1804
54677 
54678 #define S_TWDP    5
54679 #define V_TWDP(x) ((x) << S_TWDP)
54680 #define F_TWDP    V_TWDP(1U)
54681 
54682 #define S_TPGRST    4
54683 #define V_TPGRST(x) ((x) << S_TPGRST)
54684 #define F_TPGRST    V_TPGRST(1U)
54685 
54686 #define S_TPGEN    3
54687 #define V_TPGEN(x) ((x) << S_TPGEN)
54688 #define F_TPGEN    V_TPGEN(1U)
54689 
54690 #define S_TPSEL    0
54691 #define M_TPSEL    0x7U
54692 #define V_TPSEL(x) ((x) << S_TPSEL)
54693 #define G_TPSEL(x) (((x) >> S_TPSEL) & M_TPSEL)
54694 
54695 #define A_XGMAC_PORT_HSS_TXA_COEFF_CTRL 0x1808
54696 
54697 #define S_AEINVPOL    6
54698 #define V_AEINVPOL(x) ((x) << S_AEINVPOL)
54699 #define F_AEINVPOL    V_AEINVPOL(1U)
54700 
54701 #define S_AESOURCE    5
54702 #define V_AESOURCE(x) ((x) << S_AESOURCE)
54703 #define F_AESOURCE    V_AESOURCE(1U)
54704 
54705 #define S_EQMODE    4
54706 #define V_EQMODE(x) ((x) << S_EQMODE)
54707 #define F_EQMODE    V_EQMODE(1U)
54708 
54709 #define S_OCOEF    3
54710 #define V_OCOEF(x) ((x) << S_OCOEF)
54711 #define F_OCOEF    V_OCOEF(1U)
54712 
54713 #define S_COEFRST    2
54714 #define V_COEFRST(x) ((x) << S_COEFRST)
54715 #define F_COEFRST    V_COEFRST(1U)
54716 
54717 #define S_SPEN    1
54718 #define V_SPEN(x) ((x) << S_SPEN)
54719 #define F_SPEN    V_SPEN(1U)
54720 
54721 #define S_ALOAD    0
54722 #define V_ALOAD(x) ((x) << S_ALOAD)
54723 #define F_ALOAD    V_ALOAD(1U)
54724 
54725 #define A_XGMAC_PORT_HSS_TXA_DRIVER_MODE 0x180c
54726 
54727 #define S_DRVOFFT    5
54728 #define V_DRVOFFT(x) ((x) << S_DRVOFFT)
54729 #define F_DRVOFFT    V_DRVOFFT(1U)
54730 
54731 #define S_SLEW    2
54732 #define M_SLEW    0x7U
54733 #define V_SLEW(x) ((x) << S_SLEW)
54734 #define G_SLEW(x) (((x) >> S_SLEW) & M_SLEW)
54735 
54736 #define S_FFE    0
54737 #define M_FFE    0x3U
54738 #define V_FFE(x) ((x) << S_FFE)
54739 #define G_FFE(x) (((x) >> S_FFE) & M_FFE)
54740 
54741 #define A_XGMAC_PORT_HSS_TXA_DRIVER_OVR_CTRL 0x1810
54742 
54743 #define S_VLINC    7
54744 #define V_VLINC(x) ((x) << S_VLINC)
54745 #define F_VLINC    V_VLINC(1U)
54746 
54747 #define S_VLDEC    6
54748 #define V_VLDEC(x) ((x) << S_VLDEC)
54749 #define F_VLDEC    V_VLDEC(1U)
54750 
54751 #define S_LOPWR    5
54752 #define V_LOPWR(x) ((x) << S_LOPWR)
54753 #define F_LOPWR    V_LOPWR(1U)
54754 
54755 #define S_TDMEN    4
54756 #define V_TDMEN(x) ((x) << S_TDMEN)
54757 #define F_TDMEN    V_TDMEN(1U)
54758 
54759 #define S_DCCEN    3
54760 #define V_DCCEN(x) ((x) << S_DCCEN)
54761 #define F_DCCEN    V_DCCEN(1U)
54762 
54763 #define S_VHSEL    2
54764 #define V_VHSEL(x) ((x) << S_VHSEL)
54765 #define F_VHSEL    V_VHSEL(1U)
54766 
54767 #define S_IDAC    0
54768 #define M_IDAC    0x3U
54769 #define V_IDAC(x) ((x) << S_IDAC)
54770 #define G_IDAC(x) (((x) >> S_IDAC) & M_IDAC)
54771 
54772 #define A_XGMAC_PORT_HSS_TXA_TDM_BIASGEN_STANDBY_TIMER 0x1814
54773 
54774 #define S_STBY    0
54775 #define M_STBY    0xffffU
54776 #define V_STBY(x) ((x) << S_STBY)
54777 #define G_STBY(x) (((x) >> S_STBY) & M_STBY)
54778 
54779 #define A_XGMAC_PORT_HSS_TXA_TDM_BIASGEN_PWRON_TIMER 0x1818
54780 
54781 #define S_PON    0
54782 #define M_PON    0xffffU
54783 #define V_PON(x) ((x) << S_PON)
54784 #define G_PON(x) (((x) >> S_PON) & M_PON)
54785 
54786 #define A_XGMAC_PORT_HSS_TXA_TAP0_COEFF 0x1820
54787 
54788 #define S_NXTT0    0
54789 #define M_NXTT0    0xfU
54790 #define V_NXTT0(x) ((x) << S_NXTT0)
54791 #define G_NXTT0(x) (((x) >> S_NXTT0) & M_NXTT0)
54792 
54793 #define A_XGMAC_PORT_HSS_TXA_TAP1_COEFF 0x1824
54794 
54795 #define S_NXTT1    0
54796 #define M_NXTT1    0x3fU
54797 #define V_NXTT1(x) ((x) << S_NXTT1)
54798 #define G_NXTT1(x) (((x) >> S_NXTT1) & M_NXTT1)
54799 
54800 #define A_XGMAC_PORT_HSS_TXA_TAP2_COEFF 0x1828
54801 
54802 #define S_NXTT2    0
54803 #define M_NXTT2    0x1fU
54804 #define V_NXTT2(x) ((x) << S_NXTT2)
54805 #define G_NXTT2(x) (((x) >> S_NXTT2) & M_NXTT2)
54806 
54807 #define A_XGMAC_PORT_HSS_TXA_PWR 0x1830
54808 
54809 #define S_TXPWR    0
54810 #define M_TXPWR    0x7fU
54811 #define V_TXPWR(x) ((x) << S_TXPWR)
54812 #define G_TXPWR(x) (((x) >> S_TXPWR) & M_TXPWR)
54813 
54814 #define A_XGMAC_PORT_HSS_TXA_POLARITY 0x1834
54815 
54816 #define S_TXPOL    4
54817 #define M_TXPOL    0x7U
54818 #define V_TXPOL(x) ((x) << S_TXPOL)
54819 #define G_TXPOL(x) (((x) >> S_TXPOL) & M_TXPOL)
54820 
54821 #define S_NTXPOL    0
54822 #define M_NTXPOL    0x7U
54823 #define V_NTXPOL(x) ((x) << S_NTXPOL)
54824 #define G_NTXPOL(x) (((x) >> S_NTXPOL) & M_NTXPOL)
54825 
54826 #define A_XGMAC_PORT_HSS_TXA_8023AP_AE_CMD 0x1838
54827 
54828 #define S_CXPRESET    13
54829 #define V_CXPRESET(x) ((x) << S_CXPRESET)
54830 #define F_CXPRESET    V_CXPRESET(1U)
54831 
54832 #define S_CXINIT    12
54833 #define V_CXINIT(x) ((x) << S_CXINIT)
54834 #define F_CXINIT    V_CXINIT(1U)
54835 
54836 #define S_C2UPDT    4
54837 #define M_C2UPDT    0x3U
54838 #define V_C2UPDT(x) ((x) << S_C2UPDT)
54839 #define G_C2UPDT(x) (((x) >> S_C2UPDT) & M_C2UPDT)
54840 
54841 #define S_C1UPDT    2
54842 #define M_C1UPDT    0x3U
54843 #define V_C1UPDT(x) ((x) << S_C1UPDT)
54844 #define G_C1UPDT(x) (((x) >> S_C1UPDT) & M_C1UPDT)
54845 
54846 #define S_C0UPDT    0
54847 #define M_C0UPDT    0x3U
54848 #define V_C0UPDT(x) ((x) << S_C0UPDT)
54849 #define G_C0UPDT(x) (((x) >> S_C0UPDT) & M_C0UPDT)
54850 
54851 #define A_XGMAC_PORT_HSS_TXA_8023AP_AE_STATUS 0x183c
54852 
54853 #define S_C2STAT    4
54854 #define M_C2STAT    0x3U
54855 #define V_C2STAT(x) ((x) << S_C2STAT)
54856 #define G_C2STAT(x) (((x) >> S_C2STAT) & M_C2STAT)
54857 
54858 #define S_C1STAT    2
54859 #define M_C1STAT    0x3U
54860 #define V_C1STAT(x) ((x) << S_C1STAT)
54861 #define G_C1STAT(x) (((x) >> S_C1STAT) & M_C1STAT)
54862 
54863 #define S_C0STAT    0
54864 #define M_C0STAT    0x3U
54865 #define V_C0STAT(x) ((x) << S_C0STAT)
54866 #define G_C0STAT(x) (((x) >> S_C0STAT) & M_C0STAT)
54867 
54868 #define A_XGMAC_PORT_HSS_TXA_TAP0_IDAC_OVR 0x1840
54869 
54870 #define S_NIDAC0    0
54871 #define M_NIDAC0    0x1fU
54872 #define V_NIDAC0(x) ((x) << S_NIDAC0)
54873 #define G_NIDAC0(x) (((x) >> S_NIDAC0) & M_NIDAC0)
54874 
54875 #define A_XGMAC_PORT_HSS_TXA_TAP1_IDAC_OVR 0x1844
54876 
54877 #define S_NIDAC1    0
54878 #define M_NIDAC1    0x7fU
54879 #define V_NIDAC1(x) ((x) << S_NIDAC1)
54880 #define G_NIDAC1(x) (((x) >> S_NIDAC1) & M_NIDAC1)
54881 
54882 #define A_XGMAC_PORT_HSS_TXA_TAP2_IDAC_OVR 0x1848
54883 
54884 #define S_NIDAC2    0
54885 #define M_NIDAC2    0x3fU
54886 #define V_NIDAC2(x) ((x) << S_NIDAC2)
54887 #define G_NIDAC2(x) (((x) >> S_NIDAC2) & M_NIDAC2)
54888 
54889 #define A_XGMAC_PORT_HSS_TXA_PWR_DAC_OVR 0x1850
54890 
54891 #define S_OPEN    7
54892 #define V_OPEN(x) ((x) << S_OPEN)
54893 #define F_OPEN    V_OPEN(1U)
54894 
54895 #define S_OPVAL    0
54896 #define M_OPVAL    0x1fU
54897 #define V_OPVAL(x) ((x) << S_OPVAL)
54898 #define G_OPVAL(x) (((x) >> S_OPVAL) & M_OPVAL)
54899 
54900 #define A_XGMAC_PORT_HSS_TXA_PWR_DAC 0x1854
54901 
54902 #define S_PDAC    0
54903 #define M_PDAC    0x1fU
54904 #define V_PDAC(x) ((x) << S_PDAC)
54905 #define G_PDAC(x) (((x) >> S_PDAC) & M_PDAC)
54906 
54907 #define A_XGMAC_PORT_HSS_TXA_TAP0_IDAC_APP 0x1860
54908 
54909 #define S_AIDAC0    0
54910 #define M_AIDAC0    0x1fU
54911 #define V_AIDAC0(x) ((x) << S_AIDAC0)
54912 #define G_AIDAC0(x) (((x) >> S_AIDAC0) & M_AIDAC0)
54913 
54914 #define A_XGMAC_PORT_HSS_TXA_TAP1_IDAC_APP 0x1864
54915 
54916 #define S_AIDAC1    0
54917 #define M_AIDAC1    0x1fU
54918 #define V_AIDAC1(x) ((x) << S_AIDAC1)
54919 #define G_AIDAC1(x) (((x) >> S_AIDAC1) & M_AIDAC1)
54920 
54921 #define A_XGMAC_PORT_HSS_TXA_TAP2_IDAC_APP 0x1868
54922 
54923 #define S_TXA_AIDAC2    0
54924 #define M_TXA_AIDAC2    0x1fU
54925 #define V_TXA_AIDAC2(x) ((x) << S_TXA_AIDAC2)
54926 #define G_TXA_AIDAC2(x) (((x) >> S_TXA_AIDAC2) & M_TXA_AIDAC2)
54927 
54928 #define A_XGMAC_PORT_HSS_TXA_SEG_DIS_APP 0x1870
54929 
54930 #define S_CURSD    0
54931 #define M_CURSD    0x7fU
54932 #define V_CURSD(x) ((x) << S_CURSD)
54933 #define G_CURSD(x) (((x) >> S_CURSD) & M_CURSD)
54934 
54935 #define A_XGMAC_PORT_HSS_TXA_EXT_ADDR_DATA 0x1878
54936 
54937 #define S_XDATA    0
54938 #define M_XDATA    0xffffU
54939 #define V_XDATA(x) ((x) << S_XDATA)
54940 #define G_XDATA(x) (((x) >> S_XDATA) & M_XDATA)
54941 
54942 #define A_XGMAC_PORT_HSS_TXA_EXT_ADDR 0x187c
54943 
54944 #define S_EXTADDR    1
54945 #define M_EXTADDR    0x1fU
54946 #define V_EXTADDR(x) ((x) << S_EXTADDR)
54947 #define G_EXTADDR(x) (((x) >> S_EXTADDR) & M_EXTADDR)
54948 
54949 #define S_XWR    0
54950 #define V_XWR(x) ((x) << S_XWR)
54951 #define F_XWR    V_XWR(1U)
54952 
54953 #define A_XGMAC_PORT_HSS_TXB_MODE_CFG 0x1880
54954 #define A_XGMAC_PORT_HSS_TXB_TEST_CTRL 0x1884
54955 #define A_XGMAC_PORT_HSS_TXB_COEFF_CTRL 0x1888
54956 #define A_XGMAC_PORT_HSS_TXB_DRIVER_MODE 0x188c
54957 #define A_XGMAC_PORT_HSS_TXB_DRIVER_OVR_CTRL 0x1890
54958 #define A_XGMAC_PORT_HSS_TXB_TDM_BIASGEN_STANDBY_TIMER 0x1894
54959 #define A_XGMAC_PORT_HSS_TXB_TDM_BIASGEN_PWRON_TIMER 0x1898
54960 #define A_XGMAC_PORT_HSS_TXB_TAP0_COEFF 0x18a0
54961 #define A_XGMAC_PORT_HSS_TXB_TAP1_COEFF 0x18a4
54962 #define A_XGMAC_PORT_HSS_TXB_TAP2_COEFF 0x18a8
54963 #define A_XGMAC_PORT_HSS_TXB_PWR 0x18b0
54964 #define A_XGMAC_PORT_HSS_TXB_POLARITY 0x18b4
54965 #define A_XGMAC_PORT_HSS_TXB_8023AP_AE_CMD 0x18b8
54966 #define A_XGMAC_PORT_HSS_TXB_8023AP_AE_STATUS 0x18bc
54967 #define A_XGMAC_PORT_HSS_TXB_TAP0_IDAC_OVR 0x18c0
54968 #define A_XGMAC_PORT_HSS_TXB_TAP1_IDAC_OVR 0x18c4
54969 #define A_XGMAC_PORT_HSS_TXB_TAP2_IDAC_OVR 0x18c8
54970 #define A_XGMAC_PORT_HSS_TXB_PWR_DAC_OVR 0x18d0
54971 #define A_XGMAC_PORT_HSS_TXB_PWR_DAC 0x18d4
54972 #define A_XGMAC_PORT_HSS_TXB_TAP0_IDAC_APP 0x18e0
54973 #define A_XGMAC_PORT_HSS_TXB_TAP1_IDAC_APP 0x18e4
54974 #define A_XGMAC_PORT_HSS_TXB_TAP2_IDAC_APP 0x18e8
54975 
54976 #define S_AIDAC2    0
54977 #define M_AIDAC2    0x3fU
54978 #define V_AIDAC2(x) ((x) << S_AIDAC2)
54979 #define G_AIDAC2(x) (((x) >> S_AIDAC2) & M_AIDAC2)
54980 
54981 #define A_XGMAC_PORT_HSS_TXB_SEG_DIS_APP 0x18f0
54982 #define A_XGMAC_PORT_HSS_TXB_EXT_ADDR_DATA 0x18f8
54983 #define A_XGMAC_PORT_HSS_TXB_EXT_ADDR 0x18fc
54984 
54985 #define S_XADDR    2
54986 #define M_XADDR    0xfU
54987 #define V_XADDR(x) ((x) << S_XADDR)
54988 #define G_XADDR(x) (((x) >> S_XADDR) & M_XADDR)
54989 
54990 #define A_XGMAC_PORT_HSS_RXA_CFG_MODE 0x1900
54991 
54992 #define S_BW810    8
54993 #define V_BW810(x) ((x) << S_BW810)
54994 #define F_BW810    V_BW810(1U)
54995 
54996 #define S_AUXCLK    7
54997 #define V_AUXCLK(x) ((x) << S_AUXCLK)
54998 #define F_AUXCLK    V_AUXCLK(1U)
54999 
55000 #define S_DMSEL    4
55001 #define M_DMSEL    0x7U
55002 #define V_DMSEL(x) ((x) << S_DMSEL)
55003 #define G_DMSEL(x) (((x) >> S_DMSEL) & M_DMSEL)
55004 
55005 #define A_XGMAC_PORT_HSS_RXA_TEST_CTRL 0x1904
55006 
55007 #define S_RCLKEN    15
55008 #define V_RCLKEN(x) ((x) << S_RCLKEN)
55009 #define F_RCLKEN    V_RCLKEN(1U)
55010 
55011 #define S_RRATE    13
55012 #define M_RRATE    0x3U
55013 #define V_RRATE(x) ((x) << S_RRATE)
55014 #define G_RRATE(x) (((x) >> S_RRATE) & M_RRATE)
55015 
55016 #define S_LBFRCERROR    10
55017 #define V_LBFRCERROR(x) ((x) << S_LBFRCERROR)
55018 #define F_LBFRCERROR    V_LBFRCERROR(1U)
55019 
55020 #define S_LBERROR    9
55021 #define V_LBERROR(x) ((x) << S_LBERROR)
55022 #define F_LBERROR    V_LBERROR(1U)
55023 
55024 #define S_LBSYNC    8
55025 #define V_LBSYNC(x) ((x) << S_LBSYNC)
55026 #define F_LBSYNC    V_LBSYNC(1U)
55027 
55028 #define S_FDWRAPCLK    7
55029 #define V_FDWRAPCLK(x) ((x) << S_FDWRAPCLK)
55030 #define F_FDWRAPCLK    V_FDWRAPCLK(1U)
55031 
55032 #define S_FDWRAP    6
55033 #define V_FDWRAP(x) ((x) << S_FDWRAP)
55034 #define F_FDWRAP    V_FDWRAP(1U)
55035 
55036 #define S_PRST    4
55037 #define V_PRST(x) ((x) << S_PRST)
55038 #define F_PRST    V_PRST(1U)
55039 
55040 #define S_PCHKEN    3
55041 #define V_PCHKEN(x) ((x) << S_PCHKEN)
55042 #define F_PCHKEN    V_PCHKEN(1U)
55043 
55044 #define S_PRBSSEL    0
55045 #define M_PRBSSEL    0x7U
55046 #define V_PRBSSEL(x) ((x) << S_PRBSSEL)
55047 #define G_PRBSSEL(x) (((x) >> S_PRBSSEL) & M_PRBSSEL)
55048 
55049 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_CTRL 0x1908
55050 
55051 #define S_FTHROT    12
55052 #define M_FTHROT    0xfU
55053 #define V_FTHROT(x) ((x) << S_FTHROT)
55054 #define G_FTHROT(x) (((x) >> S_FTHROT) & M_FTHROT)
55055 
55056 #define S_RTHROT    11
55057 #define V_RTHROT(x) ((x) << S_RTHROT)
55058 #define F_RTHROT    V_RTHROT(1U)
55059 
55060 #define S_FILTCTL    7
55061 #define M_FILTCTL    0xfU
55062 #define V_FILTCTL(x) ((x) << S_FILTCTL)
55063 #define G_FILTCTL(x) (((x) >> S_FILTCTL) & M_FILTCTL)
55064 
55065 #define S_RSRVO    5
55066 #define M_RSRVO    0x3U
55067 #define V_RSRVO(x) ((x) << S_RSRVO)
55068 #define G_RSRVO(x) (((x) >> S_RSRVO) & M_RSRVO)
55069 
55070 #define S_EXTEL    4
55071 #define V_EXTEL(x) ((x) << S_EXTEL)
55072 #define F_EXTEL    V_EXTEL(1U)
55073 
55074 #define S_RSTONSTUCK    3
55075 #define V_RSTONSTUCK(x) ((x) << S_RSTONSTUCK)
55076 #define F_RSTONSTUCK    V_RSTONSTUCK(1U)
55077 
55078 #define S_FREEZEFW    2
55079 #define V_FREEZEFW(x) ((x) << S_FREEZEFW)
55080 #define F_FREEZEFW    V_FREEZEFW(1U)
55081 
55082 #define S_RESETFW    1
55083 #define V_RESETFW(x) ((x) << S_RESETFW)
55084 #define F_RESETFW    V_RESETFW(1U)
55085 
55086 #define S_SSCENABLE    0
55087 #define V_SSCENABLE(x) ((x) << S_SSCENABLE)
55088 #define F_SSCENABLE    V_SSCENABLE(1U)
55089 
55090 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_OFFSET_CTRL 0x190c
55091 
55092 #define S_RSNP    11
55093 #define V_RSNP(x) ((x) << S_RSNP)
55094 #define F_RSNP    V_RSNP(1U)
55095 
55096 #define S_TSOEN    10
55097 #define V_TSOEN(x) ((x) << S_TSOEN)
55098 #define F_TSOEN    V_TSOEN(1U)
55099 
55100 #define S_OFFEN    9
55101 #define V_OFFEN(x) ((x) << S_OFFEN)
55102 #define F_OFFEN    V_OFFEN(1U)
55103 
55104 #define S_TMSCAL    7
55105 #define M_TMSCAL    0x3U
55106 #define V_TMSCAL(x) ((x) << S_TMSCAL)
55107 #define G_TMSCAL(x) (((x) >> S_TMSCAL) & M_TMSCAL)
55108 
55109 #define S_APADJ    6
55110 #define V_APADJ(x) ((x) << S_APADJ)
55111 #define F_APADJ    V_APADJ(1U)
55112 
55113 #define S_RSEL    5
55114 #define V_RSEL(x) ((x) << S_RSEL)
55115 #define F_RSEL    V_RSEL(1U)
55116 
55117 #define S_PHOFFS    0
55118 #define M_PHOFFS    0x1fU
55119 #define V_PHOFFS(x) ((x) << S_PHOFFS)
55120 #define G_PHOFFS(x) (((x) >> S_PHOFFS) & M_PHOFFS)
55121 
55122 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION1 0x1910
55123 
55124 #define S_ROT0A    8
55125 #define M_ROT0A    0x3fU
55126 #define V_ROT0A(x) ((x) << S_ROT0A)
55127 #define G_ROT0A(x) (((x) >> S_ROT0A) & M_ROT0A)
55128 
55129 #define S_RTSEL_SNAPSHOT    0
55130 #define M_RTSEL_SNAPSHOT    0x3fU
55131 #define V_RTSEL_SNAPSHOT(x) ((x) << S_RTSEL_SNAPSHOT)
55132 #define G_RTSEL_SNAPSHOT(x) (((x) >> S_RTSEL_SNAPSHOT) & M_RTSEL_SNAPSHOT)
55133 
55134 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION2 0x1914
55135 
55136 #define S_ROT90    0
55137 #define M_ROT90    0x3fU
55138 #define V_ROT90(x) ((x) << S_ROT90)
55139 #define G_ROT90(x) (((x) >> S_ROT90) & M_ROT90)
55140 
55141 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_STATIC_PH_OFFSET 0x1918
55142 
55143 #define S_RCALER    15
55144 #define V_RCALER(x) ((x) << S_RCALER)
55145 #define F_RCALER    V_RCALER(1U)
55146 
55147 #define S_RAOOFF    10
55148 #define M_RAOOFF    0x1fU
55149 #define V_RAOOFF(x) ((x) << S_RAOOFF)
55150 #define G_RAOOFF(x) (((x) >> S_RAOOFF) & M_RAOOFF)
55151 
55152 #define S_RAEOFF    5
55153 #define M_RAEOFF    0x1fU
55154 #define V_RAEOFF(x) ((x) << S_RAEOFF)
55155 #define G_RAEOFF(x) (((x) >> S_RAEOFF) & M_RAEOFF)
55156 
55157 #define S_RDOFF    0
55158 #define M_RDOFF    0x1fU
55159 #define V_RDOFF(x) ((x) << S_RDOFF)
55160 #define G_RDOFF(x) (((x) >> S_RDOFF) & M_RDOFF)
55161 
55162 #define A_XGMAC_PORT_HSS_RXA_SIGDET_CTRL 0x191c
55163 
55164 #define S_SIGNSD    13
55165 #define M_SIGNSD    0x3U
55166 #define V_SIGNSD(x) ((x) << S_SIGNSD)
55167 #define G_SIGNSD(x) (((x) >> S_SIGNSD) & M_SIGNSD)
55168 
55169 #define S_DACSD    8
55170 #define M_DACSD    0x1fU
55171 #define V_DACSD(x) ((x) << S_DACSD)
55172 #define G_DACSD(x) (((x) >> S_DACSD) & M_DACSD)
55173 
55174 #define S_SDPDN    6
55175 #define V_SDPDN(x) ((x) << S_SDPDN)
55176 #define F_SDPDN    V_SDPDN(1U)
55177 
55178 #define S_SIGDET    5
55179 #define V_SIGDET(x) ((x) << S_SIGDET)
55180 #define F_SIGDET    V_SIGDET(1U)
55181 
55182 #define S_SDLVL    0
55183 #define M_SDLVL    0x1fU
55184 #define V_SDLVL(x) ((x) << S_SDLVL)
55185 #define G_SDLVL(x) (((x) >> S_SDLVL) & M_SDLVL)
55186 
55187 #define A_XGMAC_PORT_HSS_RXA_DFE_CTRL 0x1920
55188 
55189 #define S_REQCMP    15
55190 #define V_REQCMP(x) ((x) << S_REQCMP)
55191 #define F_REQCMP    V_REQCMP(1U)
55192 
55193 #define S_DFEREQ    14
55194 #define V_DFEREQ(x) ((x) << S_DFEREQ)
55195 #define F_DFEREQ    V_DFEREQ(1U)
55196 
55197 #define S_SPCEN    13
55198 #define V_SPCEN(x) ((x) << S_SPCEN)
55199 #define F_SPCEN    V_SPCEN(1U)
55200 
55201 #define S_GATEEN    12
55202 #define V_GATEEN(x) ((x) << S_GATEEN)
55203 #define F_GATEEN    V_GATEEN(1U)
55204 
55205 #define S_SPIFMT    9
55206 #define M_SPIFMT    0x7U
55207 #define V_SPIFMT(x) ((x) << S_SPIFMT)
55208 #define G_SPIFMT(x) (((x) >> S_SPIFMT) & M_SPIFMT)
55209 
55210 #define S_DFEPWR    6
55211 #define M_DFEPWR    0x7U
55212 #define V_DFEPWR(x) ((x) << S_DFEPWR)
55213 #define G_DFEPWR(x) (((x) >> S_DFEPWR) & M_DFEPWR)
55214 
55215 #define S_STNDBY    5
55216 #define V_STNDBY(x) ((x) << S_STNDBY)
55217 #define F_STNDBY    V_STNDBY(1U)
55218 
55219 #define S_FRCH    4
55220 #define V_FRCH(x) ((x) << S_FRCH)
55221 #define F_FRCH    V_FRCH(1U)
55222 
55223 #define S_NONRND    3
55224 #define V_NONRND(x) ((x) << S_NONRND)
55225 #define F_NONRND    V_NONRND(1U)
55226 
55227 #define S_NONRNF    2
55228 #define V_NONRNF(x) ((x) << S_NONRNF)
55229 #define F_NONRNF    V_NONRNF(1U)
55230 
55231 #define S_FSTLCK    1
55232 #define V_FSTLCK(x) ((x) << S_FSTLCK)
55233 #define F_FSTLCK    V_FSTLCK(1U)
55234 
55235 #define S_DFERST    0
55236 #define V_DFERST(x) ((x) << S_DFERST)
55237 #define F_DFERST    V_DFERST(1U)
55238 
55239 #define A_XGMAC_PORT_HSS_RXA_DFE_DATA_EDGE_SAMPLE 0x1924
55240 
55241 #define S_ESAMP    8
55242 #define M_ESAMP    0xffU
55243 #define V_ESAMP(x) ((x) << S_ESAMP)
55244 #define G_ESAMP(x) (((x) >> S_ESAMP) & M_ESAMP)
55245 
55246 #define S_DSAMP    0
55247 #define M_DSAMP    0xffU
55248 #define V_DSAMP(x) ((x) << S_DSAMP)
55249 #define G_DSAMP(x) (((x) >> S_DSAMP) & M_DSAMP)
55250 
55251 #define A_XGMAC_PORT_HSS_RXA_DFE_AMP_SAMPLE 0x1928
55252 
55253 #define S_SMODE    8
55254 #define M_SMODE    0xfU
55255 #define V_SMODE(x) ((x) << S_SMODE)
55256 #define G_SMODE(x) (((x) >> S_SMODE) & M_SMODE)
55257 
55258 #define S_ADCORR    7
55259 #define V_ADCORR(x) ((x) << S_ADCORR)
55260 #define F_ADCORR    V_ADCORR(1U)
55261 
55262 #define S_TRAINEN    6
55263 #define V_TRAINEN(x) ((x) << S_TRAINEN)
55264 #define F_TRAINEN    V_TRAINEN(1U)
55265 
55266 #define S_ASAMPQ    3
55267 #define M_ASAMPQ    0x7U
55268 #define V_ASAMPQ(x) ((x) << S_ASAMPQ)
55269 #define G_ASAMPQ(x) (((x) >> S_ASAMPQ) & M_ASAMPQ)
55270 
55271 #define S_ASAMP    0
55272 #define M_ASAMP    0x7U
55273 #define V_ASAMP(x) ((x) << S_ASAMP)
55274 #define G_ASAMP(x) (((x) >> S_ASAMP) & M_ASAMP)
55275 
55276 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL1 0x192c
55277 
55278 #define S_POLE    12
55279 #define M_POLE    0x3U
55280 #define V_POLE(x) ((x) << S_POLE)
55281 #define G_POLE(x) (((x) >> S_POLE) & M_POLE)
55282 
55283 #define S_PEAK    8
55284 #define M_PEAK    0x7U
55285 #define V_PEAK(x) ((x) << S_PEAK)
55286 #define G_PEAK(x) (((x) >> S_PEAK) & M_PEAK)
55287 
55288 #define S_VOFFSN    6
55289 #define M_VOFFSN    0x3U
55290 #define V_VOFFSN(x) ((x) << S_VOFFSN)
55291 #define G_VOFFSN(x) (((x) >> S_VOFFSN) & M_VOFFSN)
55292 
55293 #define S_VOFFA    0
55294 #define M_VOFFA    0x3fU
55295 #define V_VOFFA(x) ((x) << S_VOFFA)
55296 #define G_VOFFA(x) (((x) >> S_VOFFA) & M_VOFFA)
55297 
55298 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL2 0x1930
55299 
55300 #define S_SHORTV    10
55301 #define V_SHORTV(x) ((x) << S_SHORTV)
55302 #define F_SHORTV    V_SHORTV(1U)
55303 
55304 #define S_VGAIN    0
55305 #define M_VGAIN    0xfU
55306 #define V_VGAIN(x) ((x) << S_VGAIN)
55307 #define G_VGAIN(x) (((x) >> S_VGAIN) & M_VGAIN)
55308 
55309 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL3 0x1934
55310 
55311 #define S_HBND1    10
55312 #define V_HBND1(x) ((x) << S_HBND1)
55313 #define F_HBND1    V_HBND1(1U)
55314 
55315 #define S_HBND0    9
55316 #define V_HBND0(x) ((x) << S_HBND0)
55317 #define F_HBND0    V_HBND0(1U)
55318 
55319 #define S_VLCKD    8
55320 #define V_VLCKD(x) ((x) << S_VLCKD)
55321 #define F_VLCKD    V_VLCKD(1U)
55322 
55323 #define S_VLCKDF    7
55324 #define V_VLCKDF(x) ((x) << S_VLCKDF)
55325 #define F_VLCKDF    V_VLCKDF(1U)
55326 
55327 #define S_AMAXT    0
55328 #define M_AMAXT    0x7fU
55329 #define V_AMAXT(x) ((x) << S_AMAXT)
55330 #define G_AMAXT(x) (((x) >> S_AMAXT) & M_AMAXT)
55331 
55332 #define A_XGMAC_PORT_HSS_RXA_DFE_D00_D01_OFFSET 0x1938
55333 
55334 #define S_D01SN    13
55335 #define M_D01SN    0x3U
55336 #define V_D01SN(x) ((x) << S_D01SN)
55337 #define G_D01SN(x) (((x) >> S_D01SN) & M_D01SN)
55338 
55339 #define S_D01AMP    8
55340 #define M_D01AMP    0x1fU
55341 #define V_D01AMP(x) ((x) << S_D01AMP)
55342 #define G_D01AMP(x) (((x) >> S_D01AMP) & M_D01AMP)
55343 
55344 #define S_D00SN    5
55345 #define M_D00SN    0x3U
55346 #define V_D00SN(x) ((x) << S_D00SN)
55347 #define G_D00SN(x) (((x) >> S_D00SN) & M_D00SN)
55348 
55349 #define S_D00AMP    0
55350 #define M_D00AMP    0x1fU
55351 #define V_D00AMP(x) ((x) << S_D00AMP)
55352 #define G_D00AMP(x) (((x) >> S_D00AMP) & M_D00AMP)
55353 
55354 #define A_XGMAC_PORT_HSS_RXA_DFE_D10_D11_OFFSET 0x193c
55355 
55356 #define S_D11SN    13
55357 #define M_D11SN    0x3U
55358 #define V_D11SN(x) ((x) << S_D11SN)
55359 #define G_D11SN(x) (((x) >> S_D11SN) & M_D11SN)
55360 
55361 #define S_D11AMP    8
55362 #define M_D11AMP    0x1fU
55363 #define V_D11AMP(x) ((x) << S_D11AMP)
55364 #define G_D11AMP(x) (((x) >> S_D11AMP) & M_D11AMP)
55365 
55366 #define S_D10SN    5
55367 #define M_D10SN    0x3U
55368 #define V_D10SN(x) ((x) << S_D10SN)
55369 #define G_D10SN(x) (((x) >> S_D10SN) & M_D10SN)
55370 
55371 #define S_D10AMP    0
55372 #define M_D10AMP    0x1fU
55373 #define V_D10AMP(x) ((x) << S_D10AMP)
55374 #define G_D10AMP(x) (((x) >> S_D10AMP) & M_D10AMP)
55375 
55376 #define A_XGMAC_PORT_HSS_RXA_DFE_E0_E1_OFFSET 0x1940
55377 
55378 #define S_E1SN    13
55379 #define M_E1SN    0x3U
55380 #define V_E1SN(x) ((x) << S_E1SN)
55381 #define G_E1SN(x) (((x) >> S_E1SN) & M_E1SN)
55382 
55383 #define S_E1AMP    8
55384 #define M_E1AMP    0x1fU
55385 #define V_E1AMP(x) ((x) << S_E1AMP)
55386 #define G_E1AMP(x) (((x) >> S_E1AMP) & M_E1AMP)
55387 
55388 #define S_E0SN    5
55389 #define M_E0SN    0x3U
55390 #define V_E0SN(x) ((x) << S_E0SN)
55391 #define G_E0SN(x) (((x) >> S_E0SN) & M_E0SN)
55392 
55393 #define S_E0AMP    0
55394 #define M_E0AMP    0x1fU
55395 #define V_E0AMP(x) ((x) << S_E0AMP)
55396 #define G_E0AMP(x) (((x) >> S_E0AMP) & M_E0AMP)
55397 
55398 #define A_XGMAC_PORT_HSS_RXA_DACA_OFFSET 0x1944
55399 
55400 #define S_AOFFO    8
55401 #define M_AOFFO    0x3fU
55402 #define V_AOFFO(x) ((x) << S_AOFFO)
55403 #define G_AOFFO(x) (((x) >> S_AOFFO) & M_AOFFO)
55404 
55405 #define S_AOFFE    0
55406 #define M_AOFFE    0x3fU
55407 #define V_AOFFE(x) ((x) << S_AOFFE)
55408 #define G_AOFFE(x) (((x) >> S_AOFFE) & M_AOFFE)
55409 
55410 #define A_XGMAC_PORT_HSS_RXA_DACAP_DAC_AN_OFFSET 0x1948
55411 
55412 #define S_DACAN    8
55413 #define M_DACAN    0xffU
55414 #define V_DACAN(x) ((x) << S_DACAN)
55415 #define G_DACAN(x) (((x) >> S_DACAN) & M_DACAN)
55416 
55417 #define S_DACAP    0
55418 #define M_DACAP    0xffU
55419 #define V_DACAP(x) ((x) << S_DACAP)
55420 #define G_DACAP(x) (((x) >> S_DACAP) & M_DACAP)
55421 
55422 #define A_XGMAC_PORT_HSS_RXA_DACA_MIN 0x194c
55423 
55424 #define S_DACAZ    8
55425 #define M_DACAZ    0xffU
55426 #define V_DACAZ(x) ((x) << S_DACAZ)
55427 #define G_DACAZ(x) (((x) >> S_DACAZ) & M_DACAZ)
55428 
55429 #define S_DACAM    0
55430 #define M_DACAM    0xffU
55431 #define V_DACAM(x) ((x) << S_DACAM)
55432 #define G_DACAM(x) (((x) >> S_DACAM) & M_DACAM)
55433 
55434 #define A_XGMAC_PORT_HSS_RXA_ADAC_CTRL 0x1950
55435 
55436 #define S_ADSN    7
55437 #define M_ADSN    0x3U
55438 #define V_ADSN(x) ((x) << S_ADSN)
55439 #define G_ADSN(x) (((x) >> S_ADSN) & M_ADSN)
55440 
55441 #define S_ADMAG    0
55442 #define M_ADMAG    0x7fU
55443 #define V_ADMAG(x) ((x) << S_ADMAG)
55444 #define G_ADMAG(x) (((x) >> S_ADMAG) & M_ADMAG)
55445 
55446 #define A_XGMAC_PORT_HSS_RXA_DIGITAL_EYE_CTRL 0x1954
55447 
55448 #define S_BLKAZ    15
55449 #define V_BLKAZ(x) ((x) << S_BLKAZ)
55450 #define F_BLKAZ    V_BLKAZ(1U)
55451 
55452 #define S_WIDTH    10
55453 #define M_WIDTH    0x1fU
55454 #define V_WIDTH(x) ((x) << S_WIDTH)
55455 #define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH)
55456 
55457 #define S_MINWIDTH    5
55458 #define M_MINWIDTH    0x1fU
55459 #define V_MINWIDTH(x) ((x) << S_MINWIDTH)
55460 #define G_MINWIDTH(x) (((x) >> S_MINWIDTH) & M_MINWIDTH)
55461 
55462 #define S_MINAMP    0
55463 #define M_MINAMP    0x1fU
55464 #define V_MINAMP(x) ((x) << S_MINAMP)
55465 #define G_MINAMP(x) (((x) >> S_MINAMP) & M_MINAMP)
55466 
55467 #define A_XGMAC_PORT_HSS_RXA_DIGITAL_EYE_METRICS 0x1958
55468 
55469 #define S_EMBRDY    10
55470 #define V_EMBRDY(x) ((x) << S_EMBRDY)
55471 #define F_EMBRDY    V_EMBRDY(1U)
55472 
55473 #define S_EMBUMP    7
55474 #define V_EMBUMP(x) ((x) << S_EMBUMP)
55475 #define F_EMBUMP    V_EMBUMP(1U)
55476 
55477 #define S_EMMD    5
55478 #define M_EMMD    0x3U
55479 #define V_EMMD(x) ((x) << S_EMMD)
55480 #define G_EMMD(x) (((x) >> S_EMMD) & M_EMMD)
55481 
55482 #define S_EMPAT    1
55483 #define V_EMPAT(x) ((x) << S_EMPAT)
55484 #define F_EMPAT    V_EMPAT(1U)
55485 
55486 #define S_EMEN    0
55487 #define V_EMEN(x) ((x) << S_EMEN)
55488 #define F_EMEN    V_EMEN(1U)
55489 
55490 #define A_XGMAC_PORT_HSS_RXA_DFE_H1 0x195c
55491 
55492 #define S_H1OSN    14
55493 #define M_H1OSN    0x3U
55494 #define V_H1OSN(x) ((x) << S_H1OSN)
55495 #define G_H1OSN(x) (((x) >> S_H1OSN) & M_H1OSN)
55496 
55497 #define S_H1OMAG    8
55498 #define M_H1OMAG    0x3fU
55499 #define V_H1OMAG(x) ((x) << S_H1OMAG)
55500 #define G_H1OMAG(x) (((x) >> S_H1OMAG) & M_H1OMAG)
55501 
55502 #define S_H1ESN    6
55503 #define M_H1ESN    0x3U
55504 #define V_H1ESN(x) ((x) << S_H1ESN)
55505 #define G_H1ESN(x) (((x) >> S_H1ESN) & M_H1ESN)
55506 
55507 #define S_H1EMAG    0
55508 #define M_H1EMAG    0x3fU
55509 #define V_H1EMAG(x) ((x) << S_H1EMAG)
55510 #define G_H1EMAG(x) (((x) >> S_H1EMAG) & M_H1EMAG)
55511 
55512 #define A_XGMAC_PORT_HSS_RXA_DFE_H2 0x1960
55513 
55514 #define S_H2OSN    13
55515 #define M_H2OSN    0x3U
55516 #define V_H2OSN(x) ((x) << S_H2OSN)
55517 #define G_H2OSN(x) (((x) >> S_H2OSN) & M_H2OSN)
55518 
55519 #define S_H2OMAG    8
55520 #define M_H2OMAG    0x1fU
55521 #define V_H2OMAG(x) ((x) << S_H2OMAG)
55522 #define G_H2OMAG(x) (((x) >> S_H2OMAG) & M_H2OMAG)
55523 
55524 #define S_H2ESN    5
55525 #define M_H2ESN    0x3U
55526 #define V_H2ESN(x) ((x) << S_H2ESN)
55527 #define G_H2ESN(x) (((x) >> S_H2ESN) & M_H2ESN)
55528 
55529 #define S_H2EMAG    0
55530 #define M_H2EMAG    0x1fU
55531 #define V_H2EMAG(x) ((x) << S_H2EMAG)
55532 #define G_H2EMAG(x) (((x) >> S_H2EMAG) & M_H2EMAG)
55533 
55534 #define A_XGMAC_PORT_HSS_RXA_DFE_H3 0x1964
55535 
55536 #define S_H3OSN    12
55537 #define M_H3OSN    0x3U
55538 #define V_H3OSN(x) ((x) << S_H3OSN)
55539 #define G_H3OSN(x) (((x) >> S_H3OSN) & M_H3OSN)
55540 
55541 #define S_H3OMAG    8
55542 #define M_H3OMAG    0xfU
55543 #define V_H3OMAG(x) ((x) << S_H3OMAG)
55544 #define G_H3OMAG(x) (((x) >> S_H3OMAG) & M_H3OMAG)
55545 
55546 #define S_H3ESN    4
55547 #define M_H3ESN    0x3U
55548 #define V_H3ESN(x) ((x) << S_H3ESN)
55549 #define G_H3ESN(x) (((x) >> S_H3ESN) & M_H3ESN)
55550 
55551 #define S_H3EMAG    0
55552 #define M_H3EMAG    0xfU
55553 #define V_H3EMAG(x) ((x) << S_H3EMAG)
55554 #define G_H3EMAG(x) (((x) >> S_H3EMAG) & M_H3EMAG)
55555 
55556 #define A_XGMAC_PORT_HSS_RXA_DFE_H4 0x1968
55557 
55558 #define S_H4OSN    12
55559 #define M_H4OSN    0x3U
55560 #define V_H4OSN(x) ((x) << S_H4OSN)
55561 #define G_H4OSN(x) (((x) >> S_H4OSN) & M_H4OSN)
55562 
55563 #define S_H4OMAG    8
55564 #define M_H4OMAG    0xfU
55565 #define V_H4OMAG(x) ((x) << S_H4OMAG)
55566 #define G_H4OMAG(x) (((x) >> S_H4OMAG) & M_H4OMAG)
55567 
55568 #define S_H4ESN    4
55569 #define M_H4ESN    0x3U
55570 #define V_H4ESN(x) ((x) << S_H4ESN)
55571 #define G_H4ESN(x) (((x) >> S_H4ESN) & M_H4ESN)
55572 
55573 #define S_H4EMAG    0
55574 #define M_H4EMAG    0xfU
55575 #define V_H4EMAG(x) ((x) << S_H4EMAG)
55576 #define G_H4EMAG(x) (((x) >> S_H4EMAG) & M_H4EMAG)
55577 
55578 #define A_XGMAC_PORT_HSS_RXA_DFE_H5 0x196c
55579 
55580 #define S_H5OSN    12
55581 #define M_H5OSN    0x3U
55582 #define V_H5OSN(x) ((x) << S_H5OSN)
55583 #define G_H5OSN(x) (((x) >> S_H5OSN) & M_H5OSN)
55584 
55585 #define S_H5OMAG    8
55586 #define M_H5OMAG    0xfU
55587 #define V_H5OMAG(x) ((x) << S_H5OMAG)
55588 #define G_H5OMAG(x) (((x) >> S_H5OMAG) & M_H5OMAG)
55589 
55590 #define S_H5ESN    4
55591 #define M_H5ESN    0x3U
55592 #define V_H5ESN(x) ((x) << S_H5ESN)
55593 #define G_H5ESN(x) (((x) >> S_H5ESN) & M_H5ESN)
55594 
55595 #define S_H5EMAG    0
55596 #define M_H5EMAG    0xfU
55597 #define V_H5EMAG(x) ((x) << S_H5EMAG)
55598 #define G_H5EMAG(x) (((x) >> S_H5EMAG) & M_H5EMAG)
55599 
55600 #define A_XGMAC_PORT_HSS_RXA_DAC_DPC 0x1970
55601 
55602 #define S_DPCCVG    13
55603 #define V_DPCCVG(x) ((x) << S_DPCCVG)
55604 #define F_DPCCVG    V_DPCCVG(1U)
55605 
55606 #define S_DACCVG    12
55607 #define V_DACCVG(x) ((x) << S_DACCVG)
55608 #define F_DACCVG    V_DACCVG(1U)
55609 
55610 #define S_DPCTGT    9
55611 #define M_DPCTGT    0x7U
55612 #define V_DPCTGT(x) ((x) << S_DPCTGT)
55613 #define G_DPCTGT(x) (((x) >> S_DPCTGT) & M_DPCTGT)
55614 
55615 #define S_BLKH1T    8
55616 #define V_BLKH1T(x) ((x) << S_BLKH1T)
55617 #define F_BLKH1T    V_BLKH1T(1U)
55618 
55619 #define S_BLKOAE    7
55620 #define V_BLKOAE(x) ((x) << S_BLKOAE)
55621 #define F_BLKOAE    V_BLKOAE(1U)
55622 
55623 #define S_H1TGT    4
55624 #define M_H1TGT    0x7U
55625 #define V_H1TGT(x) ((x) << S_H1TGT)
55626 #define G_H1TGT(x) (((x) >> S_H1TGT) & M_H1TGT)
55627 
55628 #define S_OAE    0
55629 #define M_OAE    0xfU
55630 #define V_OAE(x) ((x) << S_OAE)
55631 #define G_OAE(x) (((x) >> S_OAE) & M_OAE)
55632 
55633 #define A_XGMAC_PORT_HSS_RXA_DDC 0x1974
55634 
55635 #define S_OLS    11
55636 #define M_OLS    0x1fU
55637 #define V_OLS(x) ((x) << S_OLS)
55638 #define G_OLS(x) (((x) >> S_OLS) & M_OLS)
55639 
55640 #define S_OES    6
55641 #define M_OES    0x1fU
55642 #define V_OES(x) ((x) << S_OES)
55643 #define G_OES(x) (((x) >> S_OES) & M_OES)
55644 
55645 #define S_BLKODEC    5
55646 #define V_BLKODEC(x) ((x) << S_BLKODEC)
55647 #define F_BLKODEC    V_BLKODEC(1U)
55648 
55649 #define S_ODEC    0
55650 #define M_ODEC    0x1fU
55651 #define V_ODEC(x) ((x) << S_ODEC)
55652 #define G_ODEC(x) (((x) >> S_ODEC) & M_ODEC)
55653 
55654 #define A_XGMAC_PORT_HSS_RXA_INTERNAL_STATUS 0x1978
55655 
55656 #define S_BER6    15
55657 #define V_BER6(x) ((x) << S_BER6)
55658 #define F_BER6    V_BER6(1U)
55659 
55660 #define S_BER6VAL    14
55661 #define V_BER6VAL(x) ((x) << S_BER6VAL)
55662 #define F_BER6VAL    V_BER6VAL(1U)
55663 
55664 #define S_BER3VAL    13
55665 #define V_BER3VAL(x) ((x) << S_BER3VAL)
55666 #define F_BER3VAL    V_BER3VAL(1U)
55667 
55668 #define S_DPCCMP    9
55669 #define V_DPCCMP(x) ((x) << S_DPCCMP)
55670 #define F_DPCCMP    V_DPCCMP(1U)
55671 
55672 #define S_DACCMP    8
55673 #define V_DACCMP(x) ((x) << S_DACCMP)
55674 #define F_DACCMP    V_DACCMP(1U)
55675 
55676 #define S_DDCCMP    7
55677 #define V_DDCCMP(x) ((x) << S_DDCCMP)
55678 #define F_DDCCMP    V_DDCCMP(1U)
55679 
55680 #define S_AERRFLG    6
55681 #define V_AERRFLG(x) ((x) << S_AERRFLG)
55682 #define F_AERRFLG    V_AERRFLG(1U)
55683 
55684 #define S_WERRFLG    5
55685 #define V_WERRFLG(x) ((x) << S_WERRFLG)
55686 #define F_WERRFLG    V_WERRFLG(1U)
55687 
55688 #define S_TRCMP    4
55689 #define V_TRCMP(x) ((x) << S_TRCMP)
55690 #define F_TRCMP    V_TRCMP(1U)
55691 
55692 #define S_VLCKF    3
55693 #define V_VLCKF(x) ((x) << S_VLCKF)
55694 #define F_VLCKF    V_VLCKF(1U)
55695 
55696 #define S_ROCADJ    2
55697 #define V_ROCADJ(x) ((x) << S_ROCADJ)
55698 #define F_ROCADJ    V_ROCADJ(1U)
55699 
55700 #define S_ROCCMP    1
55701 #define V_ROCCMP(x) ((x) << S_ROCCMP)
55702 #define F_ROCCMP    V_ROCCMP(1U)
55703 
55704 #define S_OCCMP    0
55705 #define V_OCCMP(x) ((x) << S_OCCMP)
55706 #define F_OCCMP    V_OCCMP(1U)
55707 
55708 #define A_XGMAC_PORT_HSS_RXA_DFE_FUNC_CTRL 0x197c
55709 
55710 #define S_FDPC    15
55711 #define V_FDPC(x) ((x) << S_FDPC)
55712 #define F_FDPC    V_FDPC(1U)
55713 
55714 #define S_FDAC    14
55715 #define V_FDAC(x) ((x) << S_FDAC)
55716 #define F_FDAC    V_FDAC(1U)
55717 
55718 #define S_FDDC    13
55719 #define V_FDDC(x) ((x) << S_FDDC)
55720 #define F_FDDC    V_FDDC(1U)
55721 
55722 #define S_FNRND    12
55723 #define V_FNRND(x) ((x) << S_FNRND)
55724 #define F_FNRND    V_FNRND(1U)
55725 
55726 #define S_FVGAIN    11
55727 #define V_FVGAIN(x) ((x) << S_FVGAIN)
55728 #define F_FVGAIN    V_FVGAIN(1U)
55729 
55730 #define S_FVOFF    10
55731 #define V_FVOFF(x) ((x) << S_FVOFF)
55732 #define F_FVOFF    V_FVOFF(1U)
55733 
55734 #define S_FSDET    9
55735 #define V_FSDET(x) ((x) << S_FSDET)
55736 #define F_FSDET    V_FSDET(1U)
55737 
55738 #define S_FBER6    8
55739 #define V_FBER6(x) ((x) << S_FBER6)
55740 #define F_FBER6    V_FBER6(1U)
55741 
55742 #define S_FROTO    7
55743 #define V_FROTO(x) ((x) << S_FROTO)
55744 #define F_FROTO    V_FROTO(1U)
55745 
55746 #define S_FH4H5    6
55747 #define V_FH4H5(x) ((x) << S_FH4H5)
55748 #define F_FH4H5    V_FH4H5(1U)
55749 
55750 #define S_FH2H3    5
55751 #define V_FH2H3(x) ((x) << S_FH2H3)
55752 #define F_FH2H3    V_FH2H3(1U)
55753 
55754 #define S_FH1    4
55755 #define V_FH1(x) ((x) << S_FH1)
55756 #define F_FH1    V_FH1(1U)
55757 
55758 #define S_FH1SN    3
55759 #define V_FH1SN(x) ((x) << S_FH1SN)
55760 #define F_FH1SN    V_FH1SN(1U)
55761 
55762 #define S_FNRDF    2
55763 #define V_FNRDF(x) ((x) << S_FNRDF)
55764 #define F_FNRDF    V_FNRDF(1U)
55765 
55766 #define S_FADAC    0
55767 #define V_FADAC(x) ((x) << S_FADAC)
55768 #define F_FADAC    V_FADAC(1U)
55769 
55770 #define A_XGMAC_PORT_HSS_RXB_CFG_MODE 0x1980
55771 #define A_XGMAC_PORT_HSS_RXB_TEST_CTRL 0x1984
55772 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_CTRL 0x1988
55773 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_OFFSET_CTRL 0x198c
55774 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION1 0x1990
55775 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION2 0x1994
55776 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_STATIC_PH_OFFSET 0x1998
55777 #define A_XGMAC_PORT_HSS_RXB_SIGDET_CTRL 0x199c
55778 #define A_XGMAC_PORT_HSS_RXB_DFE_CTRL 0x19a0
55779 #define A_XGMAC_PORT_HSS_RXB_DFE_DATA_EDGE_SAMPLE 0x19a4
55780 #define A_XGMAC_PORT_HSS_RXB_DFE_AMP_SAMPLE 0x19a8
55781 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL1 0x19ac
55782 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL2 0x19b0
55783 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL3 0x19b4
55784 #define A_XGMAC_PORT_HSS_RXB_DFE_D00_D01_OFFSET 0x19b8
55785 #define A_XGMAC_PORT_HSS_RXB_DFE_D10_D11_OFFSET 0x19bc
55786 #define A_XGMAC_PORT_HSS_RXB_DFE_E0_E1_OFFSET 0x19c0
55787 #define A_XGMAC_PORT_HSS_RXB_DACA_OFFSET 0x19c4
55788 #define A_XGMAC_PORT_HSS_RXB_DACAP_DAC_AN_OFFSET 0x19c8
55789 #define A_XGMAC_PORT_HSS_RXB_DACA_MIN 0x19cc
55790 #define A_XGMAC_PORT_HSS_RXB_ADAC_CTRL 0x19d0
55791 #define A_XGMAC_PORT_HSS_RXB_DIGITAL_EYE_CTRL 0x19d4
55792 #define A_XGMAC_PORT_HSS_RXB_DIGITAL_EYE_METRICS 0x19d8
55793 #define A_XGMAC_PORT_HSS_RXB_DFE_H1 0x19dc
55794 #define A_XGMAC_PORT_HSS_RXB_DFE_H2 0x19e0
55795 #define A_XGMAC_PORT_HSS_RXB_DFE_H3 0x19e4
55796 #define A_XGMAC_PORT_HSS_RXB_DFE_H4 0x19e8
55797 #define A_XGMAC_PORT_HSS_RXB_DFE_H5 0x19ec
55798 #define A_XGMAC_PORT_HSS_RXB_DAC_DPC 0x19f0
55799 #define A_XGMAC_PORT_HSS_RXB_DDC 0x19f4
55800 #define A_XGMAC_PORT_HSS_RXB_INTERNAL_STATUS 0x19f8
55801 #define A_XGMAC_PORT_HSS_RXB_DFE_FUNC_CTRL 0x19fc
55802 #define A_XGMAC_PORT_HSS_TXC_MODE_CFG 0x1a00
55803 #define A_XGMAC_PORT_HSS_TXC_TEST_CTRL 0x1a04
55804 #define A_XGMAC_PORT_HSS_TXC_COEFF_CTRL 0x1a08
55805 #define A_XGMAC_PORT_HSS_TXC_DRIVER_MODE 0x1a0c
55806 #define A_XGMAC_PORT_HSS_TXC_DRIVER_OVR_CTRL 0x1a10
55807 #define A_XGMAC_PORT_HSS_TXC_TDM_BIASGEN_STANDBY_TIMER 0x1a14
55808 #define A_XGMAC_PORT_HSS_TXC_TDM_BIASGEN_PWRON_TIMER 0x1a18
55809 #define A_XGMAC_PORT_HSS_TXC_TAP0_COEFF 0x1a20
55810 #define A_XGMAC_PORT_HSS_TXC_TAP1_COEFF 0x1a24
55811 #define A_XGMAC_PORT_HSS_TXC_TAP2_COEFF 0x1a28
55812 #define A_XGMAC_PORT_HSS_TXC_PWR 0x1a30
55813 #define A_XGMAC_PORT_HSS_TXC_POLARITY 0x1a34
55814 #define A_XGMAC_PORT_HSS_TXC_8023AP_AE_CMD 0x1a38
55815 #define A_XGMAC_PORT_HSS_TXC_8023AP_AE_STATUS 0x1a3c
55816 #define A_XGMAC_PORT_HSS_TXC_TAP0_IDAC_OVR 0x1a40
55817 #define A_XGMAC_PORT_HSS_TXC_TAP1_IDAC_OVR 0x1a44
55818 #define A_XGMAC_PORT_HSS_TXC_TAP2_IDAC_OVR 0x1a48
55819 #define A_XGMAC_PORT_HSS_TXC_PWR_DAC_OVR 0x1a50
55820 #define A_XGMAC_PORT_HSS_TXC_PWR_DAC 0x1a54
55821 #define A_XGMAC_PORT_HSS_TXC_TAP0_IDAC_APP 0x1a60
55822 #define A_XGMAC_PORT_HSS_TXC_TAP1_IDAC_APP 0x1a64
55823 #define A_XGMAC_PORT_HSS_TXC_TAP2_IDAC_APP 0x1a68
55824 #define A_XGMAC_PORT_HSS_TXC_SEG_DIS_APP 0x1a70
55825 #define A_XGMAC_PORT_HSS_TXC_EXT_ADDR_DATA 0x1a78
55826 #define A_XGMAC_PORT_HSS_TXC_EXT_ADDR 0x1a7c
55827 #define A_XGMAC_PORT_HSS_TXD_MODE_CFG 0x1a80
55828 #define A_XGMAC_PORT_HSS_TXD_TEST_CTRL 0x1a84
55829 #define A_XGMAC_PORT_HSS_TXD_COEFF_CTRL 0x1a88
55830 #define A_XGMAC_PORT_HSS_TXD_DRIVER_MODE 0x1a8c
55831 #define A_XGMAC_PORT_HSS_TXD_DRIVER_OVR_CTRL 0x1a90
55832 #define A_XGMAC_PORT_HSS_TXD_TDM_BIASGEN_STANDBY_TIMER 0x1a94
55833 #define A_XGMAC_PORT_HSS_TXD_TDM_BIASGEN_PWRON_TIMER 0x1a98
55834 #define A_XGMAC_PORT_HSS_TXD_TAP0_COEFF 0x1aa0
55835 #define A_XGMAC_PORT_HSS_TXD_TAP1_COEFF 0x1aa4
55836 #define A_XGMAC_PORT_HSS_TXD_TAP2_COEFF 0x1aa8
55837 #define A_XGMAC_PORT_HSS_TXD_PWR 0x1ab0
55838 #define A_XGMAC_PORT_HSS_TXD_POLARITY 0x1ab4
55839 #define A_XGMAC_PORT_HSS_TXD_8023AP_AE_CMD 0x1ab8
55840 #define A_XGMAC_PORT_HSS_TXD_8023AP_AE_STATUS 0x1abc
55841 #define A_XGMAC_PORT_HSS_TXD_TAP0_IDAC_OVR 0x1ac0
55842 #define A_XGMAC_PORT_HSS_TXD_TAP1_IDAC_OVR 0x1ac4
55843 #define A_XGMAC_PORT_HSS_TXD_TAP2_IDAC_OVR 0x1ac8
55844 #define A_XGMAC_PORT_HSS_TXD_PWR_DAC_OVR 0x1ad0
55845 #define A_XGMAC_PORT_HSS_TXD_PWR_DAC 0x1ad4
55846 #define A_XGMAC_PORT_HSS_TXD_TAP0_IDAC_APP 0x1ae0
55847 #define A_XGMAC_PORT_HSS_TXD_TAP1_IDAC_APP 0x1ae4
55848 #define A_XGMAC_PORT_HSS_TXD_TAP2_IDAC_APP 0x1ae8
55849 #define A_XGMAC_PORT_HSS_TXD_SEG_DIS_APP 0x1af0
55850 #define A_XGMAC_PORT_HSS_TXD_EXT_ADDR_DATA 0x1af8
55851 #define A_XGMAC_PORT_HSS_TXD_EXT_ADDR 0x1afc
55852 #define A_XGMAC_PORT_HSS_RXC_CFG_MODE 0x1b00
55853 #define A_XGMAC_PORT_HSS_RXC_TEST_CTRL 0x1b04
55854 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_CTRL 0x1b08
55855 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_OFFSET_CTRL 0x1b0c
55856 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION1 0x1b10
55857 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION2 0x1b14
55858 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_STATIC_PH_OFFSET 0x1b18
55859 #define A_XGMAC_PORT_HSS_RXC_SIGDET_CTRL 0x1b1c
55860 #define A_XGMAC_PORT_HSS_RXC_DFE_CTRL 0x1b20
55861 #define A_XGMAC_PORT_HSS_RXC_DFE_DATA_EDGE_SAMPLE 0x1b24
55862 #define A_XGMAC_PORT_HSS_RXC_DFE_AMP_SAMPLE 0x1b28
55863 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL1 0x1b2c
55864 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL2 0x1b30
55865 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL3 0x1b34
55866 #define A_XGMAC_PORT_HSS_RXC_DFE_D00_D01_OFFSET 0x1b38
55867 #define A_XGMAC_PORT_HSS_RXC_DFE_D10_D11_OFFSET 0x1b3c
55868 #define A_XGMAC_PORT_HSS_RXC_DFE_E0_E1_OFFSET 0x1b40
55869 #define A_XGMAC_PORT_HSS_RXC_DACA_OFFSET 0x1b44
55870 #define A_XGMAC_PORT_HSS_RXC_DACAP_DAC_AN_OFFSET 0x1b48
55871 #define A_XGMAC_PORT_HSS_RXC_DACA_MIN 0x1b4c
55872 #define A_XGMAC_PORT_HSS_RXC_ADAC_CTRL 0x1b50
55873 #define A_XGMAC_PORT_HSS_RXC_DIGITAL_EYE_CTRL 0x1b54
55874 #define A_XGMAC_PORT_HSS_RXC_DIGITAL_EYE_METRICS 0x1b58
55875 #define A_XGMAC_PORT_HSS_RXC_DFE_H1 0x1b5c
55876 #define A_XGMAC_PORT_HSS_RXC_DFE_H2 0x1b60
55877 #define A_XGMAC_PORT_HSS_RXC_DFE_H3 0x1b64
55878 #define A_XGMAC_PORT_HSS_RXC_DFE_H4 0x1b68
55879 #define A_XGMAC_PORT_HSS_RXC_DFE_H5 0x1b6c
55880 #define A_XGMAC_PORT_HSS_RXC_DAC_DPC 0x1b70
55881 #define A_XGMAC_PORT_HSS_RXC_DDC 0x1b74
55882 #define A_XGMAC_PORT_HSS_RXC_INTERNAL_STATUS 0x1b78
55883 #define A_XGMAC_PORT_HSS_RXC_DFE_FUNC_CTRL 0x1b7c
55884 #define A_XGMAC_PORT_HSS_RXD_CFG_MODE 0x1b80
55885 #define A_XGMAC_PORT_HSS_RXD_TEST_CTRL 0x1b84
55886 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_CTRL 0x1b88
55887 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_OFFSET_CTRL 0x1b8c
55888 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION1 0x1b90
55889 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION2 0x1b94
55890 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_STATIC_PH_OFFSET 0x1b98
55891 #define A_XGMAC_PORT_HSS_RXD_SIGDET_CTRL 0x1b9c
55892 #define A_XGMAC_PORT_HSS_RXD_DFE_CTRL 0x1ba0
55893 #define A_XGMAC_PORT_HSS_RXD_DFE_DATA_EDGE_SAMPLE 0x1ba4
55894 #define A_XGMAC_PORT_HSS_RXD_DFE_AMP_SAMPLE 0x1ba8
55895 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL1 0x1bac
55896 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL2 0x1bb0
55897 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL3 0x1bb4
55898 #define A_XGMAC_PORT_HSS_RXD_DFE_D00_D01_OFFSET 0x1bb8
55899 #define A_XGMAC_PORT_HSS_RXD_DFE_D10_D11_OFFSET 0x1bbc
55900 #define A_XGMAC_PORT_HSS_RXD_DFE_E0_E1_OFFSET 0x1bc0
55901 #define A_XGMAC_PORT_HSS_RXD_DACA_OFFSET 0x1bc4
55902 #define A_XGMAC_PORT_HSS_RXD_DACAP_DAC_AN_OFFSET 0x1bc8
55903 #define A_XGMAC_PORT_HSS_RXD_DACA_MIN 0x1bcc
55904 #define A_XGMAC_PORT_HSS_RXD_ADAC_CTRL 0x1bd0
55905 #define A_XGMAC_PORT_HSS_RXD_DIGITAL_EYE_CTRL 0x1bd4
55906 #define A_XGMAC_PORT_HSS_RXD_DIGITAL_EYE_METRICS 0x1bd8
55907 #define A_XGMAC_PORT_HSS_RXD_DFE_H1 0x1bdc
55908 #define A_XGMAC_PORT_HSS_RXD_DFE_H2 0x1be0
55909 #define A_XGMAC_PORT_HSS_RXD_DFE_H3 0x1be4
55910 #define A_XGMAC_PORT_HSS_RXD_DFE_H4 0x1be8
55911 #define A_XGMAC_PORT_HSS_RXD_DFE_H5 0x1bec
55912 #define A_XGMAC_PORT_HSS_RXD_DAC_DPC 0x1bf0
55913 #define A_XGMAC_PORT_HSS_RXD_DDC 0x1bf4
55914 #define A_XGMAC_PORT_HSS_RXD_INTERNAL_STATUS 0x1bf8
55915 #define A_XGMAC_PORT_HSS_RXD_DFE_FUNC_CTRL 0x1bfc
55916 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_0 0x1c00
55917 
55918 #define S_BSELO    0
55919 #define M_BSELO    0xfU
55920 #define V_BSELO(x) ((x) << S_BSELO)
55921 #define G_BSELO(x) (((x) >> S_BSELO) & M_BSELO)
55922 
55923 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_1 0x1c04
55924 
55925 #define S_LDET    4
55926 #define V_LDET(x) ((x) << S_LDET)
55927 #define F_LDET    V_LDET(1U)
55928 
55929 #define S_CCERR    3
55930 #define V_CCERR(x) ((x) << S_CCERR)
55931 #define F_CCERR    V_CCERR(1U)
55932 
55933 #define S_CCCMP    2
55934 #define V_CCCMP(x) ((x) << S_CCCMP)
55935 #define F_CCCMP    V_CCCMP(1U)
55936 
55937 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_2 0x1c08
55938 
55939 #define S_BSELI    0
55940 #define M_BSELI    0xfU
55941 #define V_BSELI(x) ((x) << S_BSELI)
55942 #define G_BSELI(x) (((x) >> S_BSELI) & M_BSELI)
55943 
55944 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_3 0x1c0c
55945 
55946 #define S_VISEL    4
55947 #define V_VISEL(x) ((x) << S_VISEL)
55948 #define F_VISEL    V_VISEL(1U)
55949 
55950 #define S_FMIN    3
55951 #define V_FMIN(x) ((x) << S_FMIN)
55952 #define F_FMIN    V_FMIN(1U)
55953 
55954 #define S_FMAX    2
55955 #define V_FMAX(x) ((x) << S_FMAX)
55956 #define F_FMAX    V_FMAX(1U)
55957 
55958 #define S_CVHOLD    1
55959 #define V_CVHOLD(x) ((x) << S_CVHOLD)
55960 #define F_CVHOLD    V_CVHOLD(1U)
55961 
55962 #define S_TCDIS    0
55963 #define V_TCDIS(x) ((x) << S_TCDIS)
55964 #define F_TCDIS    V_TCDIS(1U)
55965 
55966 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_4 0x1c10
55967 
55968 #define S_CMETH    2
55969 #define V_CMETH(x) ((x) << S_CMETH)
55970 #define F_CMETH    V_CMETH(1U)
55971 
55972 #define S_RECAL    1
55973 #define V_RECAL(x) ((x) << S_RECAL)
55974 #define F_RECAL    V_RECAL(1U)
55975 
55976 #define S_CCLD    0
55977 #define V_CCLD(x) ((x) << S_CCLD)
55978 #define F_CCLD    V_CCLD(1U)
55979 
55980 #define A_XGMAC_PORT_HSS_ANALOG_TEST_MUX 0x1c14
55981 
55982 #define S_ATST    0
55983 #define M_ATST    0x1fU
55984 #define V_ATST(x) ((x) << S_ATST)
55985 #define G_ATST(x) (((x) >> S_ATST) & M_ATST)
55986 
55987 #define A_XGMAC_PORT_HSS_PORT_EN_0 0x1c18
55988 
55989 #define S_RXDEN    7
55990 #define V_RXDEN(x) ((x) << S_RXDEN)
55991 #define F_RXDEN    V_RXDEN(1U)
55992 
55993 #define S_RXCEN    6
55994 #define V_RXCEN(x) ((x) << S_RXCEN)
55995 #define F_RXCEN    V_RXCEN(1U)
55996 
55997 #define S_TXDEN    5
55998 #define V_TXDEN(x) ((x) << S_TXDEN)
55999 #define F_TXDEN    V_TXDEN(1U)
56000 
56001 #define S_TXCEN    4
56002 #define V_TXCEN(x) ((x) << S_TXCEN)
56003 #define F_TXCEN    V_TXCEN(1U)
56004 
56005 #define S_RXBEN    3
56006 #define V_RXBEN(x) ((x) << S_RXBEN)
56007 #define F_RXBEN    V_RXBEN(1U)
56008 
56009 #define S_RXAEN    2
56010 #define V_RXAEN(x) ((x) << S_RXAEN)
56011 #define F_RXAEN    V_RXAEN(1U)
56012 
56013 #define S_TXBEN    1
56014 #define V_TXBEN(x) ((x) << S_TXBEN)
56015 #define F_TXBEN    V_TXBEN(1U)
56016 
56017 #define S_TXAEN    0
56018 #define V_TXAEN(x) ((x) << S_TXAEN)
56019 #define F_TXAEN    V_TXAEN(1U)
56020 
56021 #define A_XGMAC_PORT_HSS_PORT_RESET_0 0x1c20
56022 
56023 #define S_RXDRST    7
56024 #define V_RXDRST(x) ((x) << S_RXDRST)
56025 #define F_RXDRST    V_RXDRST(1U)
56026 
56027 #define S_RXCRST    6
56028 #define V_RXCRST(x) ((x) << S_RXCRST)
56029 #define F_RXCRST    V_RXCRST(1U)
56030 
56031 #define S_TXDRST    5
56032 #define V_TXDRST(x) ((x) << S_TXDRST)
56033 #define F_TXDRST    V_TXDRST(1U)
56034 
56035 #define S_TXCRST    4
56036 #define V_TXCRST(x) ((x) << S_TXCRST)
56037 #define F_TXCRST    V_TXCRST(1U)
56038 
56039 #define S_RXBRST    3
56040 #define V_RXBRST(x) ((x) << S_RXBRST)
56041 #define F_RXBRST    V_RXBRST(1U)
56042 
56043 #define S_RXARST    2
56044 #define V_RXARST(x) ((x) << S_RXARST)
56045 #define F_RXARST    V_RXARST(1U)
56046 
56047 #define S_TXBRST    1
56048 #define V_TXBRST(x) ((x) << S_TXBRST)
56049 #define F_TXBRST    V_TXBRST(1U)
56050 
56051 #define S_TXARST    0
56052 #define V_TXARST(x) ((x) << S_TXARST)
56053 #define F_TXARST    V_TXARST(1U)
56054 
56055 #define A_XGMAC_PORT_HSS_CHARGE_PUMP_CTRL 0x1c28
56056 
56057 #define S_ENCPIS    2
56058 #define V_ENCPIS(x) ((x) << S_ENCPIS)
56059 #define F_ENCPIS    V_ENCPIS(1U)
56060 
56061 #define S_CPISEL    0
56062 #define M_CPISEL    0x3U
56063 #define V_CPISEL(x) ((x) << S_CPISEL)
56064 #define G_CPISEL(x) (((x) >> S_CPISEL) & M_CPISEL)
56065 
56066 #define A_XGMAC_PORT_HSS_BAND_GAP_CTRL 0x1c2c
56067 
56068 #define S_BGCTL    0
56069 #define M_BGCTL    0x1fU
56070 #define V_BGCTL(x) ((x) << S_BGCTL)
56071 #define G_BGCTL(x) (((x) >> S_BGCTL) & M_BGCTL)
56072 
56073 #define A_XGMAC_PORT_HSS_LOFREQ_OVR 0x1c30
56074 
56075 #define S_LFREQ2    3
56076 #define V_LFREQ2(x) ((x) << S_LFREQ2)
56077 #define F_LFREQ2    V_LFREQ2(1U)
56078 
56079 #define S_LFREQ1    2
56080 #define V_LFREQ1(x) ((x) << S_LFREQ1)
56081 #define F_LFREQ1    V_LFREQ1(1U)
56082 
56083 #define S_LFREQO    1
56084 #define V_LFREQO(x) ((x) << S_LFREQO)
56085 #define F_LFREQO    V_LFREQO(1U)
56086 
56087 #define S_LFSEL    0
56088 #define V_LFSEL(x) ((x) << S_LFSEL)
56089 #define F_LFSEL    V_LFSEL(1U)
56090 
56091 #define A_XGMAC_PORT_HSS_VOLTAGE_BOOST_CTRL 0x1c38
56092 
56093 #define S_PFVAL    2
56094 #define V_PFVAL(x) ((x) << S_PFVAL)
56095 #define F_PFVAL    V_PFVAL(1U)
56096 
56097 #define S_PFEN    1
56098 #define V_PFEN(x) ((x) << S_PFEN)
56099 #define F_PFEN    V_PFEN(1U)
56100 
56101 #define S_VBADJ    0
56102 #define V_VBADJ(x) ((x) << S_VBADJ)
56103 #define F_VBADJ    V_VBADJ(1U)
56104 
56105 #define A_XGMAC_PORT_HSS_TX_MODE_CFG 0x1c80
56106 #define A_XGMAC_PORT_HSS_TXTEST_CTRL 0x1c84
56107 #define A_XGMAC_PORT_HSS_TX_COEFF_CTRL 0x1c88
56108 #define A_XGMAC_PORT_HSS_TX_DRIVER_MODE 0x1c8c
56109 #define A_XGMAC_PORT_HSS_TX_DRIVER_OVR_CTRL 0x1c90
56110 #define A_XGMAC_PORT_HSS_TX_TDM_BIASGEN_STANDBY_TIMER 0x1c94
56111 #define A_XGMAC_PORT_HSS_TX_TDM_BIASGEN_PWRON_TIMER 0x1c98
56112 #define A_XGMAC_PORT_HSS_TX_TAP0_COEFF 0x1ca0
56113 #define A_XGMAC_PORT_HSS_TX_TAP1_COEFF 0x1ca4
56114 #define A_XGMAC_PORT_HSS_TX_TAP2_COEFF 0x1ca8
56115 #define A_XGMAC_PORT_HSS_TX_PWR 0x1cb0
56116 #define A_XGMAC_PORT_HSS_TX_POLARITY 0x1cb4
56117 #define A_XGMAC_PORT_HSS_TX_8023AP_AE_CMD 0x1cb8
56118 #define A_XGMAC_PORT_HSS_TX_8023AP_AE_STATUS 0x1cbc
56119 #define A_XGMAC_PORT_HSS_TX_TAP0_IDAC_OVR 0x1cc0
56120 #define A_XGMAC_PORT_HSS_TX_TAP1_IDAC_OVR 0x1cc4
56121 #define A_XGMAC_PORT_HSS_TX_TAP2_IDAC_OVR 0x1cc8
56122 #define A_XGMAC_PORT_HSS_TX_PWR_DAC_OVR 0x1cd0
56123 #define A_XGMAC_PORT_HSS_TX_PWR_DAC 0x1cd4
56124 #define A_XGMAC_PORT_HSS_TX_TAP0_IDAC_APP 0x1ce0
56125 #define A_XGMAC_PORT_HSS_TX_TAP1_IDAC_APP 0x1ce4
56126 #define A_XGMAC_PORT_HSS_TX_TAP2_IDAC_APP 0x1ce8
56127 #define A_XGMAC_PORT_HSS_TX_SEG_DIS_APP 0x1cf0
56128 #define A_XGMAC_PORT_HSS_TX_EXT_ADDR_DATA 0x1cf8
56129 #define A_XGMAC_PORT_HSS_TX_EXT_ADDR 0x1cfc
56130 #define A_XGMAC_PORT_HSS_RX_CFG_MODE 0x1d00
56131 #define A_XGMAC_PORT_HSS_RXTEST_CTRL 0x1d04
56132 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_CTRL 0x1d08
56133 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_OFFSET_CTRL 0x1d0c
56134 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION1 0x1d10
56135 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION2 0x1d14
56136 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_STATIC_PH_OFFSET 0x1d18
56137 #define A_XGMAC_PORT_HSS_RX_SIGDET_CTRL 0x1d1c
56138 #define A_XGMAC_PORT_HSS_RX_DFE_CTRL 0x1d20
56139 #define A_XGMAC_PORT_HSS_RX_DFE_DATA_EDGE_SAMPLE 0x1d24
56140 #define A_XGMAC_PORT_HSS_RX_DFE_AMP_SAMPLE 0x1d28
56141 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL1 0x1d2c
56142 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL2 0x1d30
56143 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL3 0x1d34
56144 #define A_XGMAC_PORT_HSS_RX_DFE_D00_D01_OFFSET 0x1d38
56145 #define A_XGMAC_PORT_HSS_RX_DFE_D10_D11_OFFSET 0x1d3c
56146 #define A_XGMAC_PORT_HSS_RX_DFE_E0_E1_OFFSET 0x1d40
56147 #define A_XGMAC_PORT_HSS_RX_DACA_OFFSET 0x1d44
56148 #define A_XGMAC_PORT_HSS_RX_DACAP_DAC_AN_OFFSET 0x1d48
56149 #define A_XGMAC_PORT_HSS_RX_DACA_MIN 0x1d4c
56150 #define A_XGMAC_PORT_HSS_RX_ADAC_CTRL 0x1d50
56151 #define A_XGMAC_PORT_HSS_RX_DIGITAL_EYE_CTRL 0x1d54
56152 #define A_XGMAC_PORT_HSS_RX_DIGITAL_EYE_METRICS 0x1d58
56153 #define A_XGMAC_PORT_HSS_RX_DFE_H1 0x1d5c
56154 #define A_XGMAC_PORT_HSS_RX_DFE_H2 0x1d60
56155 #define A_XGMAC_PORT_HSS_RX_DFE_H3 0x1d64
56156 #define A_XGMAC_PORT_HSS_RX_DFE_H4 0x1d68
56157 #define A_XGMAC_PORT_HSS_RX_DFE_H5 0x1d6c
56158 #define A_XGMAC_PORT_HSS_RX_DAC_DPC 0x1d70
56159 #define A_XGMAC_PORT_HSS_RX_DDC 0x1d74
56160 #define A_XGMAC_PORT_HSS_RX_INTERNAL_STATUS 0x1d78
56161 #define A_XGMAC_PORT_HSS_RX_DFE_FUNC_CTRL 0x1d7c
56162 #define A_XGMAC_PORT_HSS_TXRX_CFG_MODE 0x1e00
56163 #define A_XGMAC_PORT_HSS_TXRXTEST_CTRL 0x1e04
56164 
56165 /* registers for module UP */
56166 #define UP_BASE_ADDR 0x0
56167 
56168 #define A_UP_IBQ_CONFIG 0x0
56169 
56170 #define S_IBQGEN2    2
56171 #define M_IBQGEN2    0x3fffffffU
56172 #define V_IBQGEN2(x) ((x) << S_IBQGEN2)
56173 #define G_IBQGEN2(x) (((x) >> S_IBQGEN2) & M_IBQGEN2)
56174 
56175 #define S_IBQBUSY    1
56176 #define V_IBQBUSY(x) ((x) << S_IBQBUSY)
56177 #define F_IBQBUSY    V_IBQBUSY(1U)
56178 
56179 #define S_IBQEN    0
56180 #define V_IBQEN(x) ((x) << S_IBQEN)
56181 #define F_IBQEN    V_IBQEN(1U)
56182 
56183 #define A_UP_OBQ_CONFIG 0x4
56184 
56185 #define S_OBQGEN2    2
56186 #define M_OBQGEN2    0x3fffffffU
56187 #define V_OBQGEN2(x) ((x) << S_OBQGEN2)
56188 #define G_OBQGEN2(x) (((x) >> S_OBQGEN2) & M_OBQGEN2)
56189 
56190 #define S_OBQBUSY    1
56191 #define V_OBQBUSY(x) ((x) << S_OBQBUSY)
56192 #define F_OBQBUSY    V_OBQBUSY(1U)
56193 
56194 #define S_OBQEN    0
56195 #define V_OBQEN(x) ((x) << S_OBQEN)
56196 #define F_OBQEN    V_OBQEN(1U)
56197 
56198 #define A_UP_IBQ_GEN 0x8
56199 
56200 #define S_IBQGEN0    22
56201 #define M_IBQGEN0    0x3ffU
56202 #define V_IBQGEN0(x) ((x) << S_IBQGEN0)
56203 #define G_IBQGEN0(x) (((x) >> S_IBQGEN0) & M_IBQGEN0)
56204 
56205 #define S_IBQTSCHCHNLRDY    18
56206 #define M_IBQTSCHCHNLRDY    0xfU
56207 #define V_IBQTSCHCHNLRDY(x) ((x) << S_IBQTSCHCHNLRDY)
56208 #define G_IBQTSCHCHNLRDY(x) (((x) >> S_IBQTSCHCHNLRDY) & M_IBQTSCHCHNLRDY)
56209 
56210 #define S_IBQMBVFSTATUS    17
56211 #define V_IBQMBVFSTATUS(x) ((x) << S_IBQMBVFSTATUS)
56212 #define F_IBQMBVFSTATUS    V_IBQMBVFSTATUS(1U)
56213 
56214 #define S_IBQMBSTATUS    16
56215 #define V_IBQMBSTATUS(x) ((x) << S_IBQMBSTATUS)
56216 #define F_IBQMBSTATUS    V_IBQMBSTATUS(1U)
56217 
56218 #define S_IBQGEN1    6
56219 #define M_IBQGEN1    0x3ffU
56220 #define V_IBQGEN1(x) ((x) << S_IBQGEN1)
56221 #define G_IBQGEN1(x) (((x) >> S_IBQGEN1) & M_IBQGEN1)
56222 
56223 #define S_IBQEMPTY    0
56224 #define M_IBQEMPTY    0x3fU
56225 #define V_IBQEMPTY(x) ((x) << S_IBQEMPTY)
56226 #define G_IBQEMPTY(x) (((x) >> S_IBQEMPTY) & M_IBQEMPTY)
56227 
56228 #define S_T7_IBQGEN1    10
56229 #define M_T7_IBQGEN1    0x3fU
56230 #define V_T7_IBQGEN1(x) ((x) << S_T7_IBQGEN1)
56231 #define G_T7_IBQGEN1(x) (((x) >> S_T7_IBQGEN1) & M_T7_IBQGEN1)
56232 
56233 #define S_T7_IBQEMPTY    0
56234 #define M_T7_IBQEMPTY    0x3ffU
56235 #define V_T7_IBQEMPTY(x) ((x) << S_T7_IBQEMPTY)
56236 #define G_T7_IBQEMPTY(x) (((x) >> S_T7_IBQEMPTY) & M_T7_IBQEMPTY)
56237 
56238 #define A_UP_OBQ_GEN 0xc
56239 
56240 #define S_OBQGEN    6
56241 #define M_OBQGEN    0x3ffffffU
56242 #define V_OBQGEN(x) ((x) << S_OBQGEN)
56243 #define G_OBQGEN(x) (((x) >> S_OBQGEN) & M_OBQGEN)
56244 
56245 #define S_OBQFULL    0
56246 #define M_OBQFULL    0x3fU
56247 #define V_OBQFULL(x) ((x) << S_OBQFULL)
56248 #define G_OBQFULL(x) (((x) >> S_OBQFULL) & M_OBQFULL)
56249 
56250 #define S_T5_OBQGEN    8
56251 #define M_T5_OBQGEN    0xffffffU
56252 #define V_T5_OBQGEN(x) ((x) << S_T5_OBQGEN)
56253 #define G_T5_OBQGEN(x) (((x) >> S_T5_OBQGEN) & M_T5_OBQGEN)
56254 
56255 #define S_T5_OBQFULL    0
56256 #define M_T5_OBQFULL    0xffU
56257 #define V_T5_OBQFULL(x) ((x) << S_T5_OBQFULL)
56258 #define G_T5_OBQFULL(x) (((x) >> S_T5_OBQFULL) & M_T5_OBQFULL)
56259 
56260 #define S_T7_T5_OBQGEN    16
56261 #define M_T7_T5_OBQGEN    0xffffU
56262 #define V_T7_T5_OBQGEN(x) ((x) << S_T7_T5_OBQGEN)
56263 #define G_T7_T5_OBQGEN(x) (((x) >> S_T7_T5_OBQGEN) & M_T7_T5_OBQGEN)
56264 
56265 #define S_T7_T5_OBQFULL    0
56266 #define M_T7_T5_OBQFULL    0xffffU
56267 #define V_T7_T5_OBQFULL(x) ((x) << S_T7_T5_OBQFULL)
56268 #define G_T7_T5_OBQFULL(x) (((x) >> S_T7_T5_OBQFULL) & M_T7_T5_OBQFULL)
56269 
56270 #define A_UP_IBQ_0_RDADDR 0x10
56271 
56272 #define S_QUEID    13
56273 #define M_QUEID    0x7ffffU
56274 #define V_QUEID(x) ((x) << S_QUEID)
56275 #define G_QUEID(x) (((x) >> S_QUEID) & M_QUEID)
56276 
56277 #define S_IBQRDADDR    0
56278 #define M_IBQRDADDR    0x1fffU
56279 #define V_IBQRDADDR(x) ((x) << S_IBQRDADDR)
56280 #define G_IBQRDADDR(x) (((x) >> S_IBQRDADDR) & M_IBQRDADDR)
56281 
56282 #define A_UP_IBQ_GEN_IPC 0x10
56283 
56284 #define S_IPCEMPTY    0
56285 #define M_IPCEMPTY    0x7fU
56286 #define V_IPCEMPTY(x) ((x) << S_IPCEMPTY)
56287 #define G_IPCEMPTY(x) (((x) >> S_IPCEMPTY) & M_IPCEMPTY)
56288 
56289 #define A_UP_IBQ_0_WRADDR 0x14
56290 
56291 #define S_IBQWRADDR    0
56292 #define M_IBQWRADDR    0x1fffU
56293 #define V_IBQWRADDR(x) ((x) << S_IBQWRADDR)
56294 #define G_IBQWRADDR(x) (((x) >> S_IBQWRADDR) & M_IBQWRADDR)
56295 
56296 #define A_UP_IBQ_0_STATUS 0x18
56297 
56298 #define S_QUEERRFRAME    31
56299 #define V_QUEERRFRAME(x) ((x) << S_QUEERRFRAME)
56300 #define F_QUEERRFRAME    V_QUEERRFRAME(1U)
56301 
56302 #define S_QUEREMFLITS    0
56303 #define M_QUEREMFLITS    0x7ffU
56304 #define V_QUEREMFLITS(x) ((x) << S_QUEREMFLITS)
56305 #define G_QUEREMFLITS(x) (((x) >> S_QUEREMFLITS) & M_QUEREMFLITS)
56306 
56307 #define A_UP_IBQ_0_PKTCNT 0x1c
56308 
56309 #define S_QUEEOPCNT    16
56310 #define M_QUEEOPCNT    0xfffU
56311 #define V_QUEEOPCNT(x) ((x) << S_QUEEOPCNT)
56312 #define G_QUEEOPCNT(x) (((x) >> S_QUEEOPCNT) & M_QUEEOPCNT)
56313 
56314 #define S_QUESOPCNT    0
56315 #define M_QUESOPCNT    0xfffU
56316 #define V_QUESOPCNT(x) ((x) << S_QUESOPCNT)
56317 #define G_QUESOPCNT(x) (((x) >> S_QUESOPCNT) & M_QUESOPCNT)
56318 
56319 #define A_UP_IBQ_1_RDADDR 0x20
56320 #define A_UP_IBQ_1_WRADDR 0x24
56321 #define A_UP_IBQ_1_STATUS 0x28
56322 #define A_UP_IBQ_1_PKTCNT 0x2c
56323 #define A_UP_IBQ_2_RDADDR 0x30
56324 #define A_UP_IBQ_2_WRADDR 0x34
56325 #define A_UP_IBQ_2_STATUS 0x38
56326 #define A_UP_IBQ_2_PKTCNT 0x3c
56327 #define A_UP_IBQ_3_RDADDR 0x40
56328 #define A_UP_IBQ_3_WRADDR 0x44
56329 #define A_UP_IBQ_3_STATUS 0x48
56330 #define A_UP_IBQ_3_PKTCNT 0x4c
56331 #define A_UP_IBQ_4_RDADDR 0x50
56332 #define A_UP_IBQ_4_WRADDR 0x54
56333 #define A_UP_IBQ_4_STATUS 0x58
56334 #define A_UP_IBQ_4_PKTCNT 0x5c
56335 #define A_UP_IBQ_5_RDADDR 0x60
56336 #define A_UP_IBQ_5_WRADDR 0x64
56337 #define A_UP_IBQ_5_STATUS 0x68
56338 #define A_UP_IBQ_5_PKTCNT 0x6c
56339 #define A_UP_OBQ_0_RDADDR 0x70
56340 
56341 #define S_OBQID    15
56342 #define M_OBQID    0x1ffffU
56343 #define V_OBQID(x) ((x) << S_OBQID)
56344 #define G_OBQID(x) (((x) >> S_OBQID) & M_OBQID)
56345 
56346 #define S_QUERDADDR    0
56347 #define M_QUERDADDR    0x7fffU
56348 #define V_QUERDADDR(x) ((x) << S_QUERDADDR)
56349 #define G_QUERDADDR(x) (((x) >> S_QUERDADDR) & M_QUERDADDR)
56350 
56351 #define A_UP_OBQ_0_WRADDR 0x74
56352 
56353 #define S_QUEWRADDR    0
56354 #define M_QUEWRADDR    0x7fffU
56355 #define V_QUEWRADDR(x) ((x) << S_QUEWRADDR)
56356 #define G_QUEWRADDR(x) (((x) >> S_QUEWRADDR) & M_QUEWRADDR)
56357 
56358 #define A_UP_OBQ_0_STATUS 0x78
56359 #define A_UP_OBQ_0_PKTCNT 0x7c
56360 #define A_UP_OBQ_1_RDADDR 0x80
56361 #define A_UP_NXT_FLOWADDR0 0x80
56362 #define A_UP_OBQ_1_WRADDR 0x84
56363 #define A_UP_NXT_FLOWADDR1 0x84
56364 #define A_UP_OBQ_1_STATUS 0x88
56365 #define A_UP_NXT_FLOWADDR2 0x88
56366 #define A_UP_OBQ_1_PKTCNT 0x8c
56367 #define A_UP_NXT_FLOWADDR3 0x8c
56368 #define A_UP_OBQ_2_RDADDR 0x90
56369 #define A_UP_DFT_FLOWADDR 0x90
56370 #define A_UP_OBQ_2_WRADDR 0x94
56371 #define A_UP_OBQ_2_STATUS 0x98
56372 #define A_UP_OBQ_2_PKTCNT 0x9c
56373 #define A_UP_OBQ_3_RDADDR 0xa0
56374 #define A_UP_OBQ_3_WRADDR 0xa4
56375 #define A_UP_OBQ_3_STATUS 0xa8
56376 #define A_UP_OBQ_3_PKTCNT 0xac
56377 #define A_UP_OBQ_4_RDADDR 0xb0
56378 #define A_UP_OBQ_4_WRADDR 0xb4
56379 #define A_UP_OBQ_4_STATUS 0xb8
56380 #define A_UP_OBQ_4_PKTCNT 0xbc
56381 #define A_UP_OBQ_5_RDADDR 0xc0
56382 #define A_UP_MAX_SEQ_NUM 0xc0
56383 #define A_UP_OBQ_5_WRADDR 0xc4
56384 #define A_UP_UNACK_SEQ_NUM 0xc4
56385 #define A_UP_OBQ_5_STATUS 0xc8
56386 #define A_UP_SEARCH_SEQ_NUM 0xc8
56387 #define A_UP_OBQ_5_PKTCNT 0xcc
56388 #define A_UP_SEQ_SEARCH_CTRL 0xcc
56389 
56390 #define S_FIFO_SIZE    29
56391 #define M_FIFO_SIZE    0x7U
56392 #define V_FIFO_SIZE(x) ((x) << S_FIFO_SIZE)
56393 #define G_FIFO_SIZE(x) (((x) >> S_FIFO_SIZE) & M_FIFO_SIZE)
56394 
56395 #define S_ROCE_MODE    28
56396 #define V_ROCE_MODE(x) ((x) << S_ROCE_MODE)
56397 #define F_ROCE_MODE    V_ROCE_MODE(1U)
56398 
56399 #define S_SEQ_WR_PTR    16
56400 #define M_SEQ_WR_PTR    0xfffU
56401 #define V_SEQ_WR_PTR(x) ((x) << S_SEQ_WR_PTR)
56402 #define G_SEQ_WR_PTR(x) (((x) >> S_SEQ_WR_PTR) & M_SEQ_WR_PTR)
56403 
56404 #define S_SEQ_RD_PTR    0
56405 #define M_SEQ_RD_PTR    0xfffU
56406 #define V_SEQ_RD_PTR(x) ((x) << S_SEQ_RD_PTR)
56407 #define G_SEQ_RD_PTR(x) (((x) >> S_SEQ_RD_PTR) & M_SEQ_RD_PTR)
56408 
56409 #define A_UP_IBQ_0_CONFIG 0xd0
56410 
56411 #define S_QUESIZE    26
56412 #define M_QUESIZE    0x3fU
56413 #define V_QUESIZE(x) ((x) << S_QUESIZE)
56414 #define G_QUESIZE(x) (((x) >> S_QUESIZE) & M_QUESIZE)
56415 
56416 #define S_QUEBASE    8
56417 #define M_QUEBASE    0x3fU
56418 #define V_QUEBASE(x) ((x) << S_QUEBASE)
56419 #define G_QUEBASE(x) (((x) >> S_QUEBASE) & M_QUEBASE)
56420 
56421 #define S_QUEDBG8BEN    7
56422 #define V_QUEDBG8BEN(x) ((x) << S_QUEDBG8BEN)
56423 #define F_QUEDBG8BEN    V_QUEDBG8BEN(1U)
56424 
56425 #define S_QUEBAREADDR    0
56426 #define V_QUEBAREADDR(x) ((x) << S_QUEBAREADDR)
56427 #define F_QUEBAREADDR    V_QUEBAREADDR(1U)
56428 
56429 #define S_QUE1KEN    6
56430 #define V_QUE1KEN(x) ((x) << S_QUE1KEN)
56431 #define F_QUE1KEN    V_QUE1KEN(1U)
56432 
56433 #define A_UP_SEQ_SEARCH_RES0 0xd0
56434 
56435 #define S_INV_SEQ    18
56436 #define V_INV_SEQ(x) ((x) << S_INV_SEQ)
56437 #define F_INV_SEQ    V_INV_SEQ(1U)
56438 
56439 #define S_DUP_SEQ    17
56440 #define V_DUP_SEQ(x) ((x) << S_DUP_SEQ)
56441 #define F_DUP_SEQ    V_DUP_SEQ(1U)
56442 
56443 #define S_MATCH_VLD    16
56444 #define V_MATCH_VLD(x) ((x) << S_MATCH_VLD)
56445 #define F_MATCH_VLD    V_MATCH_VLD(1U)
56446 
56447 #define S_MATCH_INDEX    0
56448 #define M_MATCH_INDEX    0xffffU
56449 #define V_MATCH_INDEX(x) ((x) << S_MATCH_INDEX)
56450 #define G_MATCH_INDEX(x) (((x) >> S_MATCH_INDEX) & M_MATCH_INDEX)
56451 
56452 #define A_UP_IBQ_0_REALADDR 0xd4
56453 
56454 #define S_QUERDADDRWRAP    31
56455 #define V_QUERDADDRWRAP(x) ((x) << S_QUERDADDRWRAP)
56456 #define F_QUERDADDRWRAP    V_QUERDADDRWRAP(1U)
56457 
56458 #define S_QUEWRADDRWRAP    30
56459 #define V_QUEWRADDRWRAP(x) ((x) << S_QUEWRADDRWRAP)
56460 #define F_QUEWRADDRWRAP    V_QUEWRADDRWRAP(1U)
56461 
56462 #define S_QUEMEMADDR    3
56463 #define M_QUEMEMADDR    0x7ffU
56464 #define V_QUEMEMADDR(x) ((x) << S_QUEMEMADDR)
56465 #define G_QUEMEMADDR(x) (((x) >> S_QUEMEMADDR) & M_QUEMEMADDR)
56466 
56467 #define A_UP_SEQ_SEARCH_RES1 0xd4
56468 #define A_UP_IBQ_1_CONFIG 0xd8
56469 #define A_UP_IBQ_1_REALADDR 0xdc
56470 #define A_UP_IBQ_2_CONFIG 0xe0
56471 #define A_UP_IBQ_2_REALADDR 0xe4
56472 #define A_UP_IBQ_3_CONFIG 0xe8
56473 #define A_UP_IBQ_3_REALADDR 0xec
56474 #define A_UP_IBQ_4_CONFIG 0xf0
56475 #define A_UP_IBQ_4_REALADDR 0xf4
56476 #define A_UP_IBQ_5_CONFIG 0xf8
56477 #define A_UP_IBQ_5_REALADDR 0xfc
56478 #define A_UP_OBQ_0_CONFIG 0x100
56479 #define A_UP_PEER_HALT_STAT0 0x100
56480 
56481 #define S_HALTINFO    1
56482 #define M_HALTINFO    0x7fffffffU
56483 #define V_HALTINFO(x) ((x) << S_HALTINFO)
56484 #define G_HALTINFO(x) (((x) >> S_HALTINFO) & M_HALTINFO)
56485 
56486 #define A_UP_OBQ_0_REALADDR 0x104
56487 #define A_UP_PEER_HALT_STAT1 0x104
56488 #define A_UP_OBQ_1_CONFIG 0x108
56489 #define A_UP_PEER_HALT_STAT2 0x108
56490 #define A_UP_OBQ_1_REALADDR 0x10c
56491 #define A_UP_PEER_HALT_STAT3 0x10c
56492 #define A_UP_OBQ_2_CONFIG 0x110
56493 #define A_UP_PEER_HALT_STAT4 0x110
56494 #define A_UP_OBQ_2_REALADDR 0x114
56495 #define A_UP_PEER_HALT_STAT5 0x114
56496 #define A_UP_OBQ_3_CONFIG 0x118
56497 #define A_UP_PEER_HALT_STAT6 0x118
56498 #define A_UP_OBQ_3_REALADDR 0x11c
56499 #define A_UP_PEER_HALT_STAT7 0x11c
56500 #define A_UP_OBQ_4_CONFIG 0x120
56501 #define A_UP_PEER_HALT_CTL 0x120
56502 
56503 #define S_HALTREQ    0
56504 #define V_HALTREQ(x) ((x) << S_HALTREQ)
56505 #define F_HALTREQ    V_HALTREQ(1U)
56506 
56507 #define A_UP_OBQ_4_REALADDR 0x124
56508 #define A_UP_OBQ_5_CONFIG 0x128
56509 #define A_UP_OBQ_5_REALADDR 0x12c
56510 #define A_UP_MAILBOX_STATUS 0x130
56511 
56512 #define S_MBGEN0    20
56513 #define M_MBGEN0    0xfffU
56514 #define V_MBGEN0(x) ((x) << S_MBGEN0)
56515 #define G_MBGEN0(x) (((x) >> S_MBGEN0) & M_MBGEN0)
56516 
56517 #define S_GENTIMERTRIGGER    16
56518 #define M_GENTIMERTRIGGER    0xfU
56519 #define V_GENTIMERTRIGGER(x) ((x) << S_GENTIMERTRIGGER)
56520 #define G_GENTIMERTRIGGER(x) (((x) >> S_GENTIMERTRIGGER) & M_GENTIMERTRIGGER)
56521 
56522 #define S_MBGEN1    8
56523 #define M_MBGEN1    0xffU
56524 #define V_MBGEN1(x) ((x) << S_MBGEN1)
56525 #define G_MBGEN1(x) (((x) >> S_MBGEN1) & M_MBGEN1)
56526 
56527 #define S_MBPFINT    0
56528 #define M_MBPFINT    0xffU
56529 #define V_MBPFINT(x) ((x) << S_MBPFINT)
56530 #define G_MBPFINT(x) (((x) >> S_MBPFINT) & M_MBPFINT)
56531 
56532 #define A_UP_UP_DBG_LA_CFG 0x140
56533 
56534 #define S_UPDBGLACAPTBUB    31
56535 #define V_UPDBGLACAPTBUB(x) ((x) << S_UPDBGLACAPTBUB)
56536 #define F_UPDBGLACAPTBUB    V_UPDBGLACAPTBUB(1U)
56537 
56538 #define S_UPDBGLACAPTPCONLY    30
56539 #define V_UPDBGLACAPTPCONLY(x) ((x) << S_UPDBGLACAPTPCONLY)
56540 #define F_UPDBGLACAPTPCONLY    V_UPDBGLACAPTPCONLY(1U)
56541 
56542 #define S_UPDBGLAMASKSTOP    29
56543 #define V_UPDBGLAMASKSTOP(x) ((x) << S_UPDBGLAMASKSTOP)
56544 #define F_UPDBGLAMASKSTOP    V_UPDBGLAMASKSTOP(1U)
56545 
56546 #define S_UPDBGLAMASKTRIG    28
56547 #define V_UPDBGLAMASKTRIG(x) ((x) << S_UPDBGLAMASKTRIG)
56548 #define F_UPDBGLAMASKTRIG    V_UPDBGLAMASKTRIG(1U)
56549 
56550 #define S_UPDBGLAWRPTR    16
56551 #define M_UPDBGLAWRPTR    0xfffU
56552 #define V_UPDBGLAWRPTR(x) ((x) << S_UPDBGLAWRPTR)
56553 #define G_UPDBGLAWRPTR(x) (((x) >> S_UPDBGLAWRPTR) & M_UPDBGLAWRPTR)
56554 
56555 #define S_UPDBGLARDPTR    2
56556 #define M_UPDBGLARDPTR    0xfffU
56557 #define V_UPDBGLARDPTR(x) ((x) << S_UPDBGLARDPTR)
56558 #define G_UPDBGLARDPTR(x) (((x) >> S_UPDBGLARDPTR) & M_UPDBGLARDPTR)
56559 
56560 #define S_UPDBGLARDEN    1
56561 #define V_UPDBGLARDEN(x) ((x) << S_UPDBGLARDEN)
56562 #define F_UPDBGLARDEN    V_UPDBGLARDEN(1U)
56563 
56564 #define S_UPDBGLAEN    0
56565 #define V_UPDBGLAEN(x) ((x) << S_UPDBGLAEN)
56566 #define F_UPDBGLAEN    V_UPDBGLAEN(1U)
56567 
56568 #define S_UPDBGLABUSY    14
56569 #define V_UPDBGLABUSY(x) ((x) << S_UPDBGLABUSY)
56570 #define F_UPDBGLABUSY    V_UPDBGLABUSY(1U)
56571 
56572 #define A_UP_UP_DBG_LA_DATA 0x144
56573 #define A_UP_PIO_MST_CONFIG 0x148
56574 
56575 #define S_FLSRC    24
56576 #define M_FLSRC    0x7U
56577 #define V_FLSRC(x) ((x) << S_FLSRC)
56578 #define G_FLSRC(x) (((x) >> S_FLSRC) & M_FLSRC)
56579 
56580 #define S_SEPROT    23
56581 #define V_SEPROT(x) ((x) << S_SEPROT)
56582 #define F_SEPROT    V_SEPROT(1U)
56583 
56584 #define S_SESRC    20
56585 #define M_SESRC    0x7U
56586 #define V_SESRC(x) ((x) << S_SESRC)
56587 #define G_SESRC(x) (((x) >> S_SESRC) & M_SESRC)
56588 
56589 #define S_UPRGN    19
56590 #define V_UPRGN(x) ((x) << S_UPRGN)
56591 #define F_UPRGN    V_UPRGN(1U)
56592 
56593 #define S_UPPF    16
56594 #define M_UPPF    0x7U
56595 #define V_UPPF(x) ((x) << S_UPPF)
56596 #define G_UPPF(x) (((x) >> S_UPPF) & M_UPPF)
56597 
56598 #define S_UPRID    0
56599 #define M_UPRID    0xffffU
56600 #define V_UPRID(x) ((x) << S_UPRID)
56601 #define G_UPRID(x) (((x) >> S_UPRID) & M_UPRID)
56602 
56603 #define S_REQVFVLD    27
56604 #define V_REQVFVLD(x) ((x) << S_REQVFVLD)
56605 #define F_REQVFVLD    V_REQVFVLD(1U)
56606 
56607 #define S_T5_UPRID    0
56608 #define M_T5_UPRID    0xffU
56609 #define V_T5_UPRID(x) ((x) << S_T5_UPRID)
56610 #define G_T5_UPRID(x) (((x) >> S_T5_UPRID) & M_T5_UPRID)
56611 
56612 #define S_T6_UPRID    0
56613 #define M_T6_UPRID    0x1ffU
56614 #define V_T6_UPRID(x) ((x) << S_T6_UPRID)
56615 #define G_T6_UPRID(x) (((x) >> S_T6_UPRID) & M_T6_UPRID)
56616 
56617 #define A_UP_UP_SELF_CONTROL 0x14c
56618 
56619 #define S_UPSELFRESET    0
56620 #define V_UPSELFRESET(x) ((x) << S_UPSELFRESET)
56621 #define F_UPSELFRESET    V_UPSELFRESET(1U)
56622 
56623 #define A_UP_MAILBOX_PF0_CTL 0x180
56624 #define A_UP_MAILBOX_PF1_CTL 0x190
56625 #define A_UP_MAILBOX_PF2_CTL 0x1a0
56626 #define A_UP_MAILBOX_PF3_CTL 0x1b0
56627 #define A_UP_MAILBOX_PF4_CTL 0x1c0
56628 #define A_UP_MAILBOX_PF5_CTL 0x1d0
56629 #define A_UP_MAILBOX_PF6_CTL 0x1e0
56630 #define A_UP_MAILBOX_PF7_CTL 0x1f0
56631 #define A_UP_TSCH_CHNLN_CLASS_RDY 0x200
56632 
56633 #define S_ECO_15444_SGE_DB_BUSY    31
56634 #define V_ECO_15444_SGE_DB_BUSY(x) ((x) << S_ECO_15444_SGE_DB_BUSY)
56635 #define F_ECO_15444_SGE_DB_BUSY    V_ECO_15444_SGE_DB_BUSY(1U)
56636 
56637 #define S_ECO_15444_PL_INTF_BUSY    30
56638 #define V_ECO_15444_PL_INTF_BUSY(x) ((x) << S_ECO_15444_PL_INTF_BUSY)
56639 #define F_ECO_15444_PL_INTF_BUSY    V_ECO_15444_PL_INTF_BUSY(1U)
56640 
56641 #define S_TSCHCHNLCRDY    0
56642 #define M_TSCHCHNLCRDY    0x3fffffffU
56643 #define V_TSCHCHNLCRDY(x) ((x) << S_TSCHCHNLCRDY)
56644 #define G_TSCHCHNLCRDY(x) (((x) >> S_TSCHCHNLCRDY) & M_TSCHCHNLCRDY)
56645 
56646 #define A_UP_TSCH_CHNLN_CLASS_WATCH_RDY 0x204
56647 
56648 #define S_TSCHWRRLIMIT    16
56649 #define M_TSCHWRRLIMIT    0xffffU
56650 #define V_TSCHWRRLIMIT(x) ((x) << S_TSCHWRRLIMIT)
56651 #define G_TSCHWRRLIMIT(x) (((x) >> S_TSCHWRRLIMIT) & M_TSCHWRRLIMIT)
56652 
56653 #define S_TSCHCHNLCWRDY    0
56654 #define M_TSCHCHNLCWRDY    0xffffU
56655 #define V_TSCHCHNLCWRDY(x) ((x) << S_TSCHCHNLCWRDY)
56656 #define G_TSCHCHNLCWRDY(x) (((x) >> S_TSCHCHNLCWRDY) & M_TSCHCHNLCWRDY)
56657 
56658 #define A_UP_TSCH_CHNLN_CLASS_WATCH_LIST 0x208
56659 
56660 #define S_TSCHWRRRELOAD    16
56661 #define M_TSCHWRRRELOAD    0xffffU
56662 #define V_TSCHWRRRELOAD(x) ((x) << S_TSCHWRRRELOAD)
56663 #define G_TSCHWRRRELOAD(x) (((x) >> S_TSCHWRRRELOAD) & M_TSCHWRRRELOAD)
56664 
56665 #define S_TSCHCHNLCWATCH    0
56666 #define M_TSCHCHNLCWATCH    0xffffU
56667 #define V_TSCHCHNLCWATCH(x) ((x) << S_TSCHCHNLCWATCH)
56668 #define G_TSCHCHNLCWATCH(x) (((x) >> S_TSCHCHNLCWATCH) & M_TSCHCHNLCWATCH)
56669 
56670 #define A_UP_TSCH_CHNLN_CLASS_TAKE 0x20c
56671 
56672 #define S_TSCHCHNLCNUM    24
56673 #define M_TSCHCHNLCNUM    0x1fU
56674 #define V_TSCHCHNLCNUM(x) ((x) << S_TSCHCHNLCNUM)
56675 #define G_TSCHCHNLCNUM(x) (((x) >> S_TSCHCHNLCNUM) & M_TSCHCHNLCNUM)
56676 
56677 #define S_TSCHCHNLCCNT    0
56678 #define M_TSCHCHNLCCNT    0xffffffU
56679 #define V_TSCHCHNLCCNT(x) ((x) << S_TSCHCHNLCCNT)
56680 #define G_TSCHCHNLCCNT(x) (((x) >> S_TSCHCHNLCCNT) & M_TSCHCHNLCCNT)
56681 
56682 #define S_TSCHCHNLCHDIS    31
56683 #define V_TSCHCHNLCHDIS(x) ((x) << S_TSCHCHNLCHDIS)
56684 #define F_TSCHCHNLCHDIS    V_TSCHCHNLCHDIS(1U)
56685 
56686 #define S_TSCHCHNLWDIS    30
56687 #define V_TSCHCHNLWDIS(x) ((x) << S_TSCHCHNLWDIS)
56688 #define F_TSCHCHNLWDIS    V_TSCHCHNLWDIS(1U)
56689 
56690 #define S_TSCHCHNLCLDIS    29
56691 #define V_TSCHCHNLCLDIS(x) ((x) << S_TSCHCHNLCLDIS)
56692 #define F_TSCHCHNLCLDIS    V_TSCHCHNLCLDIS(1U)
56693 
56694 #define A_UP_UPLADBGPCCHKDATA_0 0x240
56695 #define A_UP_UPLADBGPCCHKMASK_0 0x244
56696 #define A_UP_UPLADBGPCCHKDATA_1 0x250
56697 #define A_UP_UPLADBGPCCHKMASK_1 0x254
56698 #define A_UP_UPLADBGPCCHKDATA_2 0x260
56699 #define A_UP_UPLADBGPCCHKMASK_2 0x264
56700 #define A_UP_UPLADBGPCCHKDATA_3 0x270
56701 #define A_UP_UPLADBGPCCHKMASK_3 0x274
56702 #define A_UP_IBQ_0_SHADOW_RDADDR 0x280
56703 #define A_UP_IBQ_0_SHADOW_WRADDR 0x284
56704 #define A_UP_IBQ_0_SHADOW_STATUS 0x288
56705 #define A_UP_IBQ_0_SHADOW_PKTCNT 0x28c
56706 #define A_UP_IBQ_1_SHADOW_RDADDR 0x290
56707 #define A_UP_IBQ_1_SHADOW_WRADDR 0x294
56708 #define A_UP_IBQ_1_SHADOW_STATUS 0x298
56709 #define A_UP_IBQ_1_SHADOW_PKTCNT 0x29c
56710 #define A_UP_IBQ_2_SHADOW_RDADDR 0x2a0
56711 #define A_UP_IBQ_2_SHADOW_WRADDR 0x2a4
56712 #define A_UP_IBQ_2_SHADOW_STATUS 0x2a8
56713 #define A_UP_IBQ_2_SHADOW_PKTCNT 0x2ac
56714 #define A_UP_IBQ_3_SHADOW_RDADDR 0x2b0
56715 #define A_UP_IBQ_3_SHADOW_WRADDR 0x2b4
56716 #define A_UP_IBQ_3_SHADOW_STATUS 0x2b8
56717 #define A_UP_IBQ_3_SHADOW_PKTCNT 0x2bc
56718 #define A_UP_IBQ_4_SHADOW_RDADDR 0x2c0
56719 #define A_UP_IBQ_4_SHADOW_WRADDR 0x2c4
56720 #define A_UP_IBQ_4_SHADOW_STATUS 0x2c8
56721 #define A_UP_IBQ_4_SHADOW_PKTCNT 0x2cc
56722 #define A_UP_IBQ_5_SHADOW_RDADDR 0x2d0
56723 #define A_UP_IBQ_5_SHADOW_WRADDR 0x2d4
56724 #define A_UP_IBQ_5_SHADOW_STATUS 0x2d8
56725 #define A_UP_IBQ_5_SHADOW_PKTCNT 0x2dc
56726 #define A_UP_OBQ_0_SHADOW_RDADDR 0x2e0
56727 #define A_UP_OBQ_0_SHADOW_WRADDR 0x2e4
56728 #define A_UP_OBQ_0_SHADOW_STATUS 0x2e8
56729 #define A_UP_OBQ_0_SHADOW_PKTCNT 0x2ec
56730 #define A_UP_OBQ_1_SHADOW_RDADDR 0x2f0
56731 #define A_UP_OBQ_1_SHADOW_WRADDR 0x2f4
56732 #define A_UP_OBQ_1_SHADOW_STATUS 0x2f8
56733 #define A_UP_OBQ_1_SHADOW_PKTCNT 0x2fc
56734 #define A_UP_OBQ_2_SHADOW_RDADDR 0x300
56735 #define A_UP_OBQ_2_SHADOW_WRADDR 0x304
56736 #define A_UP_OBQ_2_SHADOW_STATUS 0x308
56737 #define A_UP_OBQ_2_SHADOW_PKTCNT 0x30c
56738 #define A_UP_OBQ_3_SHADOW_RDADDR 0x310
56739 #define A_UP_OBQ_3_SHADOW_WRADDR 0x314
56740 #define A_UP_OBQ_3_SHADOW_STATUS 0x318
56741 #define A_UP_OBQ_3_SHADOW_PKTCNT 0x31c
56742 #define A_UP_OBQ_4_SHADOW_RDADDR 0x320
56743 #define A_UP_OBQ_4_SHADOW_WRADDR 0x324
56744 #define A_UP_OBQ_4_SHADOW_STATUS 0x328
56745 #define A_UP_OBQ_4_SHADOW_PKTCNT 0x32c
56746 #define A_UP_OBQ_5_SHADOW_RDADDR 0x330
56747 #define A_UP_OBQ_5_SHADOW_WRADDR 0x334
56748 #define A_UP_OBQ_5_SHADOW_STATUS 0x338
56749 #define A_UP_OBQ_5_SHADOW_PKTCNT 0x33c
56750 #define A_UP_OBQ_6_SHADOW_RDADDR 0x340
56751 #define A_UP_OBQ_6_SHADOW_WRADDR 0x344
56752 #define A_UP_OBQ_6_SHADOW_STATUS 0x348
56753 #define A_UP_OBQ_6_SHADOW_PKTCNT 0x34c
56754 #define A_UP_OBQ_7_SHADOW_RDADDR 0x350
56755 #define A_UP_OBQ_7_SHADOW_WRADDR 0x354
56756 #define A_UP_OBQ_7_SHADOW_STATUS 0x358
56757 #define A_UP_OBQ_7_SHADOW_PKTCNT 0x35c
56758 #define A_UP_IBQ_0_SHADOW_CONFIG 0x360
56759 #define A_UP_IBQ_0_SHADOW_REALADDR 0x364
56760 #define A_UP_IBQ_1_SHADOW_CONFIG 0x368
56761 #define A_UP_IBQ_1_SHADOW_REALADDR 0x36c
56762 #define A_UP_IBQ_2_SHADOW_CONFIG 0x370
56763 #define A_UP_IBQ_2_SHADOW_REALADDR 0x374
56764 #define A_UP_IBQ_3_SHADOW_CONFIG 0x378
56765 #define A_UP_IBQ_3_SHADOW_REALADDR 0x37c
56766 #define A_UP_IBQ_4_SHADOW_CONFIG 0x380
56767 #define A_UP_IBQ_4_SHADOW_REALADDR 0x384
56768 #define A_UP_IBQ_5_SHADOW_CONFIG 0x388
56769 #define A_UP_IBQ_5_SHADOW_REALADDR 0x38c
56770 #define A_UP_OBQ_0_SHADOW_CONFIG 0x390
56771 #define A_UP_OBQ_0_SHADOW_REALADDR 0x394
56772 #define A_UP_OBQ_1_SHADOW_CONFIG 0x398
56773 #define A_UP_OBQ_1_SHADOW_REALADDR 0x39c
56774 #define A_UP_OBQ_2_SHADOW_CONFIG 0x3a0
56775 #define A_UP_OBQ_2_SHADOW_REALADDR 0x3a4
56776 #define A_UP_OBQ_3_SHADOW_CONFIG 0x3a8
56777 #define A_UP_OBQ_3_SHADOW_REALADDR 0x3ac
56778 #define A_UP_OBQ_4_SHADOW_CONFIG 0x3b0
56779 #define A_UP_OBQ_4_SHADOW_REALADDR 0x3b4
56780 #define A_UP_OBQ_5_SHADOW_CONFIG 0x3b8
56781 #define A_UP_OBQ_5_SHADOW_REALADDR 0x3bc
56782 #define A_UP_OBQ_6_SHADOW_CONFIG 0x3c0
56783 #define A_UP_OBQ_6_SHADOW_REALADDR 0x3c4
56784 #define A_UP_OBQ_7_SHADOW_CONFIG 0x3c8
56785 #define A_UP_OBQ_7_SHADOW_REALADDR 0x3cc
56786 #define A_T7_UP_IBQ_0_SHADOW_RDADDR 0x400
56787 #define A_T7_UP_IBQ_0_SHADOW_WRADDR 0x404
56788 #define A_T7_UP_IBQ_0_SHADOW_STATUS 0x408
56789 
56790 #define S_T7_QUEREMFLITS    0
56791 #define M_T7_QUEREMFLITS    0xfffU
56792 #define V_T7_QUEREMFLITS(x) ((x) << S_T7_QUEREMFLITS)
56793 #define G_T7_QUEREMFLITS(x) (((x) >> S_T7_QUEREMFLITS) & M_T7_QUEREMFLITS)
56794 
56795 #define A_T7_UP_IBQ_0_SHADOW_PKTCNT 0x40c
56796 #define A_T7_UP_IBQ_1_SHADOW_RDADDR 0x410
56797 #define A_T7_UP_IBQ_1_SHADOW_WRADDR 0x414
56798 #define A_T7_UP_IBQ_1_SHADOW_STATUS 0x418
56799 #define A_T7_UP_IBQ_1_SHADOW_PKTCNT 0x41c
56800 #define A_T7_UP_IBQ_2_SHADOW_RDADDR 0x420
56801 #define A_T7_UP_IBQ_2_SHADOW_WRADDR 0x424
56802 #define A_T7_UP_IBQ_2_SHADOW_STATUS 0x428
56803 #define A_T7_UP_IBQ_2_SHADOW_PKTCNT 0x42c
56804 #define A_T7_UP_IBQ_3_SHADOW_RDADDR 0x430
56805 #define A_T7_UP_IBQ_3_SHADOW_WRADDR 0x434
56806 #define A_T7_UP_IBQ_3_SHADOW_STATUS 0x438
56807 #define A_T7_UP_IBQ_3_SHADOW_PKTCNT 0x43c
56808 #define A_T7_UP_IBQ_4_SHADOW_RDADDR 0x440
56809 #define A_T7_UP_IBQ_4_SHADOW_WRADDR 0x444
56810 #define A_T7_UP_IBQ_4_SHADOW_STATUS 0x448
56811 #define A_T7_UP_IBQ_4_SHADOW_PKTCNT 0x44c
56812 #define A_T7_UP_IBQ_5_SHADOW_RDADDR 0x450
56813 #define A_T7_UP_IBQ_5_SHADOW_WRADDR 0x454
56814 #define A_T7_UP_IBQ_5_SHADOW_STATUS 0x458
56815 #define A_T7_UP_IBQ_5_SHADOW_PKTCNT 0x45c
56816 #define A_UP_IBQ_6_SHADOW_RDADDR 0x460
56817 #define A_UP_IBQ_6_SHADOW_WRADDR 0x464
56818 #define A_UP_IBQ_6_SHADOW_STATUS 0x468
56819 #define A_UP_IBQ_6_SHADOW_PKTCNT 0x46c
56820 #define A_UP_IBQ_7_SHADOW_RDADDR 0x470
56821 #define A_UP_IBQ_7_SHADOW_WRADDR 0x474
56822 #define A_UP_IBQ_7_SHADOW_STATUS 0x478
56823 #define A_UP_IBQ_7_SHADOW_PKTCNT 0x47c
56824 #define A_UP_IBQ_8_SHADOW_RDADDR 0x480
56825 #define A_UP_IBQ_8_SHADOW_WRADDR 0x484
56826 #define A_UP_IBQ_8_SHADOW_STATUS 0x488
56827 #define A_UP_IBQ_8_SHADOW_PKTCNT 0x48c
56828 #define A_UP_IBQ_9_SHADOW_RDADDR 0x490
56829 #define A_UP_IBQ_9_SHADOW_WRADDR 0x494
56830 #define A_UP_IBQ_9_SHADOW_STATUS 0x498
56831 #define A_UP_IBQ_9_SHADOW_PKTCNT 0x49c
56832 #define A_UP_IBQ_10_SHADOW_RDADDR 0x4a0
56833 #define A_UP_IBQ_10_SHADOW_WRADDR 0x4a4
56834 #define A_UP_IBQ_10_SHADOW_STATUS 0x4a8
56835 #define A_UP_IBQ_10_SHADOW_PKTCNT 0x4ac
56836 #define A_UP_IBQ_11_SHADOW_RDADDR 0x4b0
56837 #define A_UP_IBQ_11_SHADOW_WRADDR 0x4b4
56838 #define A_UP_IBQ_11_SHADOW_STATUS 0x4b8
56839 #define A_UP_IBQ_11_SHADOW_PKTCNT 0x4bc
56840 #define A_UP_IBQ_12_SHADOW_RDADDR 0x4c0
56841 #define A_UP_IBQ_12_SHADOW_WRADDR 0x4c4
56842 #define A_UP_IBQ_12_SHADOW_STATUS 0x4c8
56843 #define A_UP_IBQ_12_SHADOW_PKTCNT 0x4cc
56844 #define A_UP_IBQ_13_SHADOW_RDADDR 0x4d0
56845 #define A_UP_IBQ_13_SHADOW_WRADDR 0x4d4
56846 #define A_UP_IBQ_13_SHADOW_STATUS 0x4d8
56847 #define A_UP_IBQ_13_SHADOW_PKTCNT 0x4dc
56848 #define A_UP_IBQ_14_SHADOW_RDADDR 0x4e0
56849 #define A_UP_IBQ_14_SHADOW_WRADDR 0x4e4
56850 #define A_UP_IBQ_14_SHADOW_STATUS 0x4e8
56851 #define A_UP_IBQ_14_SHADOW_PKTCNT 0x4ec
56852 #define A_UP_IBQ_15_SHADOW_RDADDR 0x4f0
56853 #define A_UP_IBQ_15_SHADOW_WRADDR 0x4f4
56854 #define A_UP_IBQ_15_SHADOW_STATUS 0x4f8
56855 #define A_UP_IBQ_15_SHADOW_PKTCNT 0x4fc
56856 #define A_T7_UP_IBQ_0_SHADOW_CONFIG 0x500
56857 #define A_T7_UP_IBQ_0_SHADOW_REALADDR 0x504
56858 #define A_T7_UP_IBQ_1_SHADOW_CONFIG 0x510
56859 #define A_T7_UP_IBQ_1_SHADOW_REALADDR 0x514
56860 #define A_T7_UP_IBQ_2_SHADOW_CONFIG 0x520
56861 #define A_T7_UP_IBQ_2_SHADOW_REALADDR 0x524
56862 #define A_T7_UP_IBQ_3_SHADOW_CONFIG 0x530
56863 #define A_T7_UP_IBQ_3_SHADOW_REALADDR 0x534
56864 #define A_T7_UP_IBQ_4_SHADOW_CONFIG 0x540
56865 #define A_T7_UP_IBQ_4_SHADOW_REALADDR 0x544
56866 #define A_T7_UP_IBQ_5_SHADOW_CONFIG 0x550
56867 #define A_T7_UP_IBQ_5_SHADOW_REALADDR 0x554
56868 #define A_UP_IBQ_6_SHADOW_CONFIG 0x560
56869 #define A_UP_IBQ_6_SHADOW_REALADDR 0x564
56870 #define A_UP_IBQ_7_SHADOW_CONFIG 0x570
56871 #define A_UP_IBQ_7_SHADOW_REALADDR 0x574
56872 #define A_UP_IBQ_8_SHADOW_CONFIG 0x580
56873 #define A_UP_IBQ_8_SHADOW_REALADDR 0x584
56874 #define A_UP_IBQ_9_SHADOW_CONFIG 0x590
56875 #define A_UP_IBQ_9_SHADOW_REALADDR 0x594
56876 #define A_UP_IBQ_10_SHADOW_CONFIG 0x5a0
56877 #define A_UP_IBQ_10_SHADOW_REALADDR 0x5a4
56878 #define A_UP_IBQ_11_SHADOW_CONFIG 0x5b0
56879 #define A_UP_IBQ_11_SHADOW_REALADDR 0x5b4
56880 #define A_UP_IBQ_12_SHADOW_CONFIG 0x5c0
56881 #define A_UP_IBQ_12_SHADOW_REALADDR 0x5c4
56882 #define A_UP_IBQ_13_SHADOW_CONFIG 0x5d0
56883 #define A_UP_IBQ_13_SHADOW_REALADDR 0x5d4
56884 #define A_UP_IBQ_14_SHADOW_CONFIG 0x5e0
56885 #define A_UP_IBQ_14_SHADOW_REALADDR 0x5e4
56886 #define A_UP_IBQ_15_SHADOW_CONFIG 0x5f0
56887 #define A_UP_IBQ_15_SHADOW_REALADDR 0x5f4
56888 #define A_T7_UP_OBQ_0_SHADOW_RDADDR 0x600
56889 #define A_T7_UP_OBQ_0_SHADOW_WRADDR 0x604
56890 #define A_T7_UP_OBQ_0_SHADOW_STATUS 0x608
56891 #define A_T7_UP_OBQ_0_SHADOW_PKTCNT 0x60c
56892 #define A_T7_UP_OBQ_1_SHADOW_RDADDR 0x610
56893 #define A_T7_UP_OBQ_1_SHADOW_WRADDR 0x614
56894 #define A_T7_UP_OBQ_1_SHADOW_STATUS 0x618
56895 #define A_T7_UP_OBQ_1_SHADOW_PKTCNT 0x61c
56896 #define A_T7_UP_OBQ_2_SHADOW_RDADDR 0x620
56897 #define A_T7_UP_OBQ_2_SHADOW_WRADDR 0x624
56898 #define A_T7_UP_OBQ_2_SHADOW_STATUS 0x628
56899 #define A_T7_UP_OBQ_2_SHADOW_PKTCNT 0x62c
56900 #define A_T7_UP_OBQ_3_SHADOW_RDADDR 0x630
56901 #define A_T7_UP_OBQ_3_SHADOW_WRADDR 0x634
56902 #define A_T7_UP_OBQ_3_SHADOW_STATUS 0x638
56903 #define A_T7_UP_OBQ_3_SHADOW_PKTCNT 0x63c
56904 #define A_T7_UP_OBQ_4_SHADOW_RDADDR 0x640
56905 #define A_T7_UP_OBQ_4_SHADOW_WRADDR 0x644
56906 #define A_T7_UP_OBQ_4_SHADOW_STATUS 0x648
56907 #define A_T7_UP_OBQ_4_SHADOW_PKTCNT 0x64c
56908 #define A_T7_UP_OBQ_5_SHADOW_RDADDR 0x650
56909 #define A_T7_UP_OBQ_5_SHADOW_WRADDR 0x654
56910 #define A_T7_UP_OBQ_5_SHADOW_STATUS 0x658
56911 #define A_T7_UP_OBQ_5_SHADOW_PKTCNT 0x65c
56912 #define A_T7_UP_OBQ_6_SHADOW_RDADDR 0x660
56913 #define A_T7_UP_OBQ_6_SHADOW_WRADDR 0x664
56914 #define A_T7_UP_OBQ_6_SHADOW_STATUS 0x668
56915 #define A_T7_UP_OBQ_6_SHADOW_PKTCNT 0x66c
56916 #define A_T7_UP_OBQ_7_SHADOW_RDADDR 0x670
56917 #define A_T7_UP_OBQ_7_SHADOW_WRADDR 0x674
56918 #define A_T7_UP_OBQ_7_SHADOW_STATUS 0x678
56919 #define A_T7_UP_OBQ_7_SHADOW_PKTCNT 0x67c
56920 #define A_UP_OBQ_8_SHADOW_RDADDR 0x680
56921 #define A_UP_OBQ_8_SHADOW_WRADDR 0x684
56922 #define A_UP_OBQ_8_SHADOW_STATUS 0x688
56923 #define A_UP_OBQ_8_SHADOW_PKTCNT 0x68c
56924 #define A_UP_OBQ_9_SHADOW_RDADDR 0x690
56925 #define A_UP_OBQ_9_SHADOW_WRADDR 0x694
56926 #define A_UP_OBQ_9_SHADOW_STATUS 0x698
56927 #define A_UP_OBQ_9_SHADOW_PKTCNT 0x69c
56928 #define A_UP_OBQ_10_SHADOW_RDADDR 0x6a0
56929 #define A_UP_OBQ_10_SHADOW_WRADDR 0x6a4
56930 #define A_UP_OBQ_10_SHADOW_STATUS 0x6a8
56931 #define A_UP_OBQ_10_SHADOW_PKTCNT 0x6ac
56932 #define A_UP_OBQ_11_SHADOW_RDADDR 0x6b0
56933 #define A_UP_OBQ_11_SHADOW_WRADDR 0x6b4
56934 #define A_UP_OBQ_11_SHADOW_STATUS 0x6b8
56935 #define A_UP_OBQ_11_SHADOW_PKTCNT 0x6bc
56936 #define A_UP_OBQ_12_SHADOW_RDADDR 0x6c0
56937 #define A_UP_OBQ_12_SHADOW_WRADDR 0x6c4
56938 #define A_UP_OBQ_12_SHADOW_STATUS 0x6c8
56939 #define A_UP_OBQ_12_SHADOW_PKTCNT 0x6cc
56940 #define A_UP_OBQ_13_SHADOW_RDADDR 0x6d0
56941 #define A_UP_OBQ_13_SHADOW_WRADDR 0x6d4
56942 #define A_UP_OBQ_13_SHADOW_STATUS 0x6d8
56943 #define A_UP_OBQ_13_SHADOW_PKTCNT 0x6dc
56944 #define A_UP_OBQ_14_SHADOW_RDADDR 0x6e0
56945 #define A_UP_OBQ_14_SHADOW_WRADDR 0x6e4
56946 #define A_UP_OBQ_14_SHADOW_STATUS 0x6e8
56947 #define A_UP_OBQ_14_SHADOW_PKTCNT 0x6ec
56948 #define A_UP_OBQ_15_SHADOW_RDADDR 0x6f0
56949 #define A_UP_OBQ_15_SHADOW_WRADDR 0x6f4
56950 #define A_UP_OBQ_15_SHADOW_STATUS 0x6f8
56951 #define A_UP_OBQ_15_SHADOW_PKTCNT 0x6fc
56952 #define A_T7_UP_OBQ_0_SHADOW_CONFIG 0x700
56953 #define A_T7_UP_OBQ_0_SHADOW_REALADDR 0x704
56954 #define A_T7_UP_OBQ_1_SHADOW_CONFIG 0x710
56955 #define A_T7_UP_OBQ_1_SHADOW_REALADDR 0x714
56956 #define A_T7_UP_OBQ_2_SHADOW_CONFIG 0x720
56957 #define A_T7_UP_OBQ_2_SHADOW_REALADDR 0x724
56958 #define A_T7_UP_OBQ_3_SHADOW_CONFIG 0x730
56959 #define A_T7_UP_OBQ_3_SHADOW_REALADDR 0x734
56960 #define A_T7_UP_OBQ_4_SHADOW_CONFIG 0x740
56961 #define A_T7_UP_OBQ_4_SHADOW_REALADDR 0x744
56962 #define A_T7_UP_OBQ_5_SHADOW_CONFIG 0x750
56963 #define A_T7_UP_OBQ_5_SHADOW_REALADDR 0x754
56964 #define A_T7_UP_OBQ_6_SHADOW_CONFIG 0x760
56965 #define A_T7_UP_OBQ_6_SHADOW_REALADDR 0x764
56966 #define A_T7_UP_OBQ_7_SHADOW_CONFIG 0x770
56967 #define A_T7_UP_OBQ_7_SHADOW_REALADDR 0x774
56968 #define A_UP_OBQ_8_SHADOW_CONFIG 0x780
56969 #define A_UP_OBQ_8_SHADOW_REALADDR 0x784
56970 #define A_UP_OBQ_9_SHADOW_CONFIG 0x790
56971 #define A_UP_OBQ_9_SHADOW_REALADDR 0x794
56972 #define A_UP_OBQ_10_SHADOW_CONFIG 0x7a0
56973 #define A_UP_OBQ_10_SHADOW_REALADDR 0x7a4
56974 #define A_UP_OBQ_11_SHADOW_CONFIG 0x7b0
56975 #define A_UP_OBQ_11_SHADOW_REALADDR 0x7b4
56976 #define A_UP_OBQ_12_SHADOW_CONFIG 0x7c0
56977 #define A_UP_OBQ_12_SHADOW_REALADDR 0x7c4
56978 #define A_UP_OBQ_13_SHADOW_CONFIG 0x7d0
56979 #define A_UP_OBQ_13_SHADOW_REALADDR 0x7d4
56980 #define A_UP_OBQ_14_SHADOW_CONFIG 0x7e0
56981 #define A_UP_OBQ_14_SHADOW_REALADDR 0x7e4
56982 #define A_UP_OBQ_15_SHADOW_CONFIG 0x7f0
56983 #define A_UP_OBQ_15_SHADOW_REALADDR 0x7f4
56984 
56985 /* registers for module CIM_CTL */
56986 #define CIM_CTL_BASE_ADDR 0x0
56987 
56988 #define A_CIM_CTL_CONFIG 0x0
56989 
56990 #define S_AUTOPREFLOC    17
56991 #define M_AUTOPREFLOC    0x1fU
56992 #define V_AUTOPREFLOC(x) ((x) << S_AUTOPREFLOC)
56993 #define G_AUTOPREFLOC(x) (((x) >> S_AUTOPREFLOC) & M_AUTOPREFLOC)
56994 
56995 #define S_AUTOPREFEN    16
56996 #define V_AUTOPREFEN(x) ((x) << S_AUTOPREFEN)
56997 #define F_AUTOPREFEN    V_AUTOPREFEN(1U)
56998 
56999 #define S_DISMATIMEOUT    15
57000 #define V_DISMATIMEOUT(x) ((x) << S_DISMATIMEOUT)
57001 #define F_DISMATIMEOUT    V_DISMATIMEOUT(1U)
57002 
57003 #define S_PIFMULTICMD    8
57004 #define V_PIFMULTICMD(x) ((x) << S_PIFMULTICMD)
57005 #define F_PIFMULTICMD    V_PIFMULTICMD(1U)
57006 
57007 #define S_UPSELFRESETTOUT    7
57008 #define V_UPSELFRESETTOUT(x) ((x) << S_UPSELFRESETTOUT)
57009 #define F_UPSELFRESETTOUT    V_UPSELFRESETTOUT(1U)
57010 
57011 #define S_PLSWAPDISWR    6
57012 #define V_PLSWAPDISWR(x) ((x) << S_PLSWAPDISWR)
57013 #define F_PLSWAPDISWR    V_PLSWAPDISWR(1U)
57014 
57015 #define S_PLSWAPDISRD    5
57016 #define V_PLSWAPDISRD(x) ((x) << S_PLSWAPDISRD)
57017 #define F_PLSWAPDISRD    V_PLSWAPDISRD(1U)
57018 
57019 #define S_PREFEN    0
57020 #define V_PREFEN(x) ((x) << S_PREFEN)
57021 #define F_PREFEN    V_PREFEN(1U)
57022 
57023 #define S_DISSLOWTIMEOUT    14
57024 #define V_DISSLOWTIMEOUT(x) ((x) << S_DISSLOWTIMEOUT)
57025 #define F_DISSLOWTIMEOUT    V_DISSLOWTIMEOUT(1U)
57026 
57027 #define S_INTLRSPEN    9
57028 #define V_INTLRSPEN(x) ((x) << S_INTLRSPEN)
57029 #define F_INTLRSPEN    V_INTLRSPEN(1U)
57030 
57031 #define A_CIM_CTL_PREFADDR 0x4
57032 #define A_CIM_CTL_ALLOCADDR 0x8
57033 #define A_CIM_CTL_INVLDTADDR 0xc
57034 #define A_CIM_CTL_STATIC_PREFADDR0 0x10
57035 #define A_CIM_CTL_STATIC_PREFADDR1 0x14
57036 #define A_CIM_CTL_STATIC_PREFADDR2 0x18
57037 #define A_CIM_CTL_STATIC_PREFADDR3 0x1c
57038 #define A_CIM_CTL_STATIC_PREFADDR4 0x20
57039 #define A_CIM_CTL_STATIC_PREFADDR5 0x24
57040 #define A_CIM_CTL_STATIC_PREFADDR6 0x28
57041 #define A_CIM_CTL_STATIC_PREFADDR7 0x2c
57042 #define A_CIM_CTL_STATIC_PREFADDR8 0x30
57043 #define A_CIM_CTL_STATIC_PREFADDR9 0x34
57044 #define A_CIM_CTL_STATIC_PREFADDR10 0x38
57045 #define A_CIM_CTL_STATIC_PREFADDR11 0x3c
57046 #define A_CIM_CTL_STATIC_PREFADDR12 0x40
57047 #define A_CIM_CTL_SEM_CFG 0x40
57048 
57049 #define S_SEMINIT    31
57050 #define V_SEMINIT(x) ((x) << S_SEMINIT)
57051 #define F_SEMINIT    V_SEMINIT(1U)
57052 
57053 #define S_NUMSEM    0
57054 #define M_NUMSEM    0x3ffffU
57055 #define V_NUMSEM(x) ((x) << S_NUMSEM)
57056 #define G_NUMSEM(x) (((x) >> S_NUMSEM) & M_NUMSEM)
57057 
57058 #define A_CIM_CTL_STATIC_PREFADDR13 0x44
57059 #define A_CIM_CTL_SEM_MA_CFG 0x44
57060 
57061 #define S_SEMMABASE    4
57062 #define M_SEMMABASE    0xfffffffU
57063 #define V_SEMMABASE(x) ((x) << S_SEMMABASE)
57064 #define G_SEMMABASE(x) (((x) >> S_SEMMABASE) & M_SEMMABASE)
57065 
57066 #define S_SEMMATHREADID    0
57067 #define M_SEMMATHREADID    0x7U
57068 #define V_SEMMATHREADID(x) ((x) << S_SEMMATHREADID)
57069 #define G_SEMMATHREADID(x) (((x) >> S_SEMMATHREADID) & M_SEMMATHREADID)
57070 
57071 #define A_CIM_CTL_STATIC_PREFADDR14 0x48
57072 #define A_CIM_CTL_STATIC_PREFADDR15 0x4c
57073 #define A_CIM_CTL_STATIC_ALLOCADDR0 0x50
57074 #define A_CIM_CTL_LOCK_CFG 0x50
57075 
57076 #define S_NUMLOCK    0
57077 #define M_NUMLOCK    0x3ffffU
57078 #define V_NUMLOCK(x) ((x) << S_NUMLOCK)
57079 #define G_NUMLOCK(x) (((x) >> S_NUMLOCK) & M_NUMLOCK)
57080 
57081 #define A_CIM_CTL_STATIC_ALLOCADDR1 0x54
57082 #define A_CIM_CTL_LOCK_MA_CFG 0x54
57083 
57084 #define S_LOCKMABASE    4
57085 #define M_LOCKMABASE    0xfffffffU
57086 #define V_LOCKMABASE(x) ((x) << S_LOCKMABASE)
57087 #define G_LOCKMABASE(x) (((x) >> S_LOCKMABASE) & M_LOCKMABASE)
57088 
57089 #define S_LOCKMATHREADID    0
57090 #define M_LOCKMATHREADID    0x7U
57091 #define V_LOCKMATHREADID(x) ((x) << S_LOCKMATHREADID)
57092 #define G_LOCKMATHREADID(x) (((x) >> S_LOCKMATHREADID) & M_LOCKMATHREADID)
57093 
57094 #define A_CIM_CTL_STATIC_ALLOCADDR2 0x58
57095 #define A_CIM_CTL_STATIC_ALLOCADDR3 0x5c
57096 #define A_CIM_CTL_STATIC_ALLOCADDR4 0x60
57097 #define A_CIM_CTL_RSA_INT 0x60
57098 #define A_CIM_CTL_STATIC_ALLOCADDR5 0x64
57099 #define A_CIM_CTL_RSA_BUSY 0x64
57100 #define A_CIM_CTL_STATIC_ALLOCADDR6 0x68
57101 #define A_CIM_CTL_RSA_CPERR 0x68
57102 #define A_CIM_CTL_STATIC_ALLOCADDR7 0x6c
57103 #define A_CIM_CTL_RSA_DPERR 0x6c
57104 #define A_CIM_CTL_STATIC_ALLOCADDR8 0x70
57105 #define A_CIM_CTL_STATIC_ALLOCADDR9 0x74
57106 #define A_CIM_CTL_STATIC_ALLOCADDR10 0x78
57107 #define A_CIM_CTL_STATIC_ALLOCADDR11 0x7c
57108 #define A_CIM_CTL_STATIC_ALLOCADDR12 0x80
57109 #define A_CIM_CTL_STATIC_ALLOCADDR13 0x84
57110 #define A_CIM_CTL_STATIC_ALLOCADDR14 0x88
57111 #define A_CIM_CTL_STATIC_ALLOCADDR15 0x8c
57112 #define A_CIM_CTL_FIFO_CNT 0x90
57113 
57114 #define S_CTLFIFOCNT    0
57115 #define M_CTLFIFOCNT    0xfU
57116 #define V_CTLFIFOCNT(x) ((x) << S_CTLFIFOCNT)
57117 #define G_CTLFIFOCNT(x) (((x) >> S_CTLFIFOCNT) & M_CTLFIFOCNT)
57118 
57119 #define A_CIM_CTL_GLB_TIMER 0x94
57120 #define A_CIM_CTL_TIMER0 0x98
57121 #define A_CIM_CTL_TIMER1 0x9c
57122 #define A_CIM_CTL_GEN0 0xa0
57123 #define A_CIM_CTL_GEN1 0xa4
57124 #define A_CIM_CTL_GEN2 0xa8
57125 #define A_CIM_CTL_GEN3 0xac
57126 #define A_CIM_CTL_GLB_TIMER_TICK 0xb0
57127 #define A_CIM_CTL_GEN_TIMER0_CTL 0xb4
57128 
57129 #define S_GENTIMERRUN    7
57130 #define V_GENTIMERRUN(x) ((x) << S_GENTIMERRUN)
57131 #define F_GENTIMERRUN    V_GENTIMERRUN(1U)
57132 
57133 #define S_GENTIMERTRIG    6
57134 #define V_GENTIMERTRIG(x) ((x) << S_GENTIMERTRIG)
57135 #define F_GENTIMERTRIG    V_GENTIMERTRIG(1U)
57136 
57137 #define S_GENTIMERACT    4
57138 #define M_GENTIMERACT    0x3U
57139 #define V_GENTIMERACT(x) ((x) << S_GENTIMERACT)
57140 #define G_GENTIMERACT(x) (((x) >> S_GENTIMERACT) & M_GENTIMERACT)
57141 
57142 #define S_GENTIMERCFG    2
57143 #define M_GENTIMERCFG    0x3U
57144 #define V_GENTIMERCFG(x) ((x) << S_GENTIMERCFG)
57145 #define G_GENTIMERCFG(x) (((x) >> S_GENTIMERCFG) & M_GENTIMERCFG)
57146 
57147 #define S_GENTIMERSTOP    1
57148 #define V_GENTIMERSTOP(x) ((x) << S_GENTIMERSTOP)
57149 #define F_GENTIMERSTOP    V_GENTIMERSTOP(1U)
57150 
57151 #define S_GENTIMERSTRT    0
57152 #define V_GENTIMERSTRT(x) ((x) << S_GENTIMERSTRT)
57153 #define F_GENTIMERSTRT    V_GENTIMERSTRT(1U)
57154 
57155 #define A_CIM_CTL_GEN_TIMER0 0xb8
57156 #define A_CIM_CTL_GEN_TIMER1_CTL 0xbc
57157 #define A_CIM_CTL_GEN_TIMER1 0xc0
57158 #define A_CIM_CTL_GEN_TIMER2_CTL 0xc4
57159 #define A_CIM_CTL_GEN_TIMER2 0xc8
57160 #define A_CIM_CTL_GEN_TIMER3_CTL 0xcc
57161 #define A_CIM_CTL_GEN_TIMER3 0xd0
57162 #define A_CIM_CTL_MAILBOX_VF_STATUS 0xe0
57163 #define A_CIM_CTL_MAILBOX_VFN_CTL 0x100
57164 #define A_CIM_CTL_TID_MAP_EN 0x500
57165 #define A_CIM_CTL_TID_MAP_CORE 0x520
57166 #define A_CIM_CTL_TID_MAP_CONFIG 0x540
57167 
57168 #define S_TIDDEFCORE    4
57169 #define M_TIDDEFCORE    0xfU
57170 #define V_TIDDEFCORE(x) ((x) << S_TIDDEFCORE)
57171 #define G_TIDDEFCORE(x) (((x) >> S_TIDDEFCORE) & M_TIDDEFCORE)
57172 
57173 #define S_TIDVECBASE    0
57174 #define M_TIDVECBASE    0x7U
57175 #define V_TIDVECBASE(x) ((x) << S_TIDVECBASE)
57176 #define G_TIDVECBASE(x) (((x) >> S_TIDVECBASE) & M_TIDVECBASE)
57177 
57178 #define A_CIM_CTL_CRYPTO_KEY_DATA 0x600
57179 #define A_CIM_CTL_SECURE_CONFIG 0x6f8
57180 #define A_CIM_CTL_CRYPTO_KEY_CTRL 0x6fc
57181 
57182 #define S_CRYPTOKEYDATAREGNUM    8
57183 #define M_CRYPTOKEYDATAREGNUM    0xffU
57184 #define V_CRYPTOKEYDATAREGNUM(x) ((x) << S_CRYPTOKEYDATAREGNUM)
57185 #define G_CRYPTOKEYDATAREGNUM(x) (((x) >> S_CRYPTOKEYDATAREGNUM) & M_CRYPTOKEYDATAREGNUM)
57186 
57187 #define S_CRYPTOKEYSTARTBUSY    0
57188 #define V_CRYPTOKEYSTARTBUSY(x) ((x) << S_CRYPTOKEYSTARTBUSY)
57189 #define F_CRYPTOKEYSTARTBUSY    V_CRYPTOKEYSTARTBUSY(1U)
57190 
57191 #define A_CIM_CTL_FLOWID_OP_VALID 0x700
57192 #define A_CIM_CTL_FLOWID_CTL 0x720
57193 
57194 #define S_FLOWBASEADDR    8
57195 #define M_FLOWBASEADDR    0xffffffU
57196 #define V_FLOWBASEADDR(x) ((x) << S_FLOWBASEADDR)
57197 #define G_FLOWBASEADDR(x) (((x) >> S_FLOWBASEADDR) & M_FLOWBASEADDR)
57198 
57199 #define S_SEQSRCHALIGNCFG    4
57200 #define M_SEQSRCHALIGNCFG    0x3U
57201 #define V_SEQSRCHALIGNCFG(x) ((x) << S_SEQSRCHALIGNCFG)
57202 #define G_SEQSRCHALIGNCFG(x) (((x) >> S_SEQSRCHALIGNCFG) & M_SEQSRCHALIGNCFG)
57203 
57204 #define S_FLOWADDRSIZE    1
57205 #define M_FLOWADDRSIZE    0x3U
57206 #define V_FLOWADDRSIZE(x) ((x) << S_FLOWADDRSIZE)
57207 #define G_FLOWADDRSIZE(x) (((x) >> S_FLOWADDRSIZE) & M_FLOWADDRSIZE)
57208 
57209 #define S_FLOWIDEN    0
57210 #define V_FLOWIDEN(x) ((x) << S_FLOWIDEN)
57211 #define F_FLOWIDEN    V_FLOWIDEN(1U)
57212 
57213 #define A_CIM_CTL_FLOWID_MAX 0x724
57214 
57215 #define S_MAXFLOWID    0
57216 #define M_MAXFLOWID    0xffffffU
57217 #define V_MAXFLOWID(x) ((x) << S_MAXFLOWID)
57218 #define G_MAXFLOWID(x) (((x) >> S_MAXFLOWID) & M_MAXFLOWID)
57219 
57220 #define A_CIM_CTL_FLOWID_HINT0 0x728
57221 #define A_CIM_CTL_EFUSE_CTRL 0x780
57222 #define A_CIM_CTL_EFUSE_QOUT 0x784
57223 #define A_CIM_CTL_EFUSE_RFOUT 0x788
57224 #define A_CIM_CTL_TSCH_CHNLN_CTL 0x900
57225 
57226 #define S_TSCHNLEN    31
57227 #define V_TSCHNLEN(x) ((x) << S_TSCHNLEN)
57228 #define F_TSCHNLEN    V_TSCHNLEN(1U)
57229 
57230 #define S_TSCHNRESET    30
57231 #define V_TSCHNRESET(x) ((x) << S_TSCHNRESET)
57232 #define F_TSCHNRESET    V_TSCHNRESET(1U)
57233 
57234 #define S_T6_MIN_MAX_EN    29
57235 #define V_T6_MIN_MAX_EN(x) ((x) << S_T6_MIN_MAX_EN)
57236 #define F_T6_MIN_MAX_EN    V_T6_MIN_MAX_EN(1U)
57237 
57238 #define A_CIM_CTL_TSCH_CHNLN_TICK 0x904
57239 
57240 #define S_TSCHNLTICK    0
57241 #define M_TSCHNLTICK    0xffffU
57242 #define V_TSCHNLTICK(x) ((x) << S_TSCHNLTICK)
57243 #define G_TSCHNLTICK(x) (((x) >> S_TSCHNLTICK) & M_TSCHNLTICK)
57244 
57245 #define A_CIM_CTL_TSCH_CHNLN_CLASS_RATECTL 0x904
57246 
57247 #define S_TSC15RATECTL    15
57248 #define V_TSC15RATECTL(x) ((x) << S_TSC15RATECTL)
57249 #define F_TSC15RATECTL    V_TSC15RATECTL(1U)
57250 
57251 #define S_TSC14RATECTL    14
57252 #define V_TSC14RATECTL(x) ((x) << S_TSC14RATECTL)
57253 #define F_TSC14RATECTL    V_TSC14RATECTL(1U)
57254 
57255 #define S_TSC13RATECTL    13
57256 #define V_TSC13RATECTL(x) ((x) << S_TSC13RATECTL)
57257 #define F_TSC13RATECTL    V_TSC13RATECTL(1U)
57258 
57259 #define S_TSC12RATECTL    12
57260 #define V_TSC12RATECTL(x) ((x) << S_TSC12RATECTL)
57261 #define F_TSC12RATECTL    V_TSC12RATECTL(1U)
57262 
57263 #define S_TSC11RATECTL    11
57264 #define V_TSC11RATECTL(x) ((x) << S_TSC11RATECTL)
57265 #define F_TSC11RATECTL    V_TSC11RATECTL(1U)
57266 
57267 #define S_TSC10RATECTL    10
57268 #define V_TSC10RATECTL(x) ((x) << S_TSC10RATECTL)
57269 #define F_TSC10RATECTL    V_TSC10RATECTL(1U)
57270 
57271 #define S_TSC9RATECTL    9
57272 #define V_TSC9RATECTL(x) ((x) << S_TSC9RATECTL)
57273 #define F_TSC9RATECTL    V_TSC9RATECTL(1U)
57274 
57275 #define S_TSC8RATECTL    8
57276 #define V_TSC8RATECTL(x) ((x) << S_TSC8RATECTL)
57277 #define F_TSC8RATECTL    V_TSC8RATECTL(1U)
57278 
57279 #define S_TSC7RATECTL    7
57280 #define V_TSC7RATECTL(x) ((x) << S_TSC7RATECTL)
57281 #define F_TSC7RATECTL    V_TSC7RATECTL(1U)
57282 
57283 #define S_TSC6RATECTL    6
57284 #define V_TSC6RATECTL(x) ((x) << S_TSC6RATECTL)
57285 #define F_TSC6RATECTL    V_TSC6RATECTL(1U)
57286 
57287 #define S_TSC5RATECTL    5
57288 #define V_TSC5RATECTL(x) ((x) << S_TSC5RATECTL)
57289 #define F_TSC5RATECTL    V_TSC5RATECTL(1U)
57290 
57291 #define S_TSC4RATECTL    4
57292 #define V_TSC4RATECTL(x) ((x) << S_TSC4RATECTL)
57293 #define F_TSC4RATECTL    V_TSC4RATECTL(1U)
57294 
57295 #define S_TSC3RATECTL    3
57296 #define V_TSC3RATECTL(x) ((x) << S_TSC3RATECTL)
57297 #define F_TSC3RATECTL    V_TSC3RATECTL(1U)
57298 
57299 #define S_TSC2RATECTL    2
57300 #define V_TSC2RATECTL(x) ((x) << S_TSC2RATECTL)
57301 #define F_TSC2RATECTL    V_TSC2RATECTL(1U)
57302 
57303 #define S_TSC1RATECTL    1
57304 #define V_TSC1RATECTL(x) ((x) << S_TSC1RATECTL)
57305 #define F_TSC1RATECTL    V_TSC1RATECTL(1U)
57306 
57307 #define S_TSC0RATECTL    0
57308 #define V_TSC0RATECTL(x) ((x) << S_TSC0RATECTL)
57309 #define F_TSC0RATECTL    V_TSC0RATECTL(1U)
57310 
57311 #define A_CIM_CTL_TSCH_CHNLN_CLASS_ENABLE_A 0x908
57312 
57313 #define S_TSC15WRREN    31
57314 #define V_TSC15WRREN(x) ((x) << S_TSC15WRREN)
57315 #define F_TSC15WRREN    V_TSC15WRREN(1U)
57316 
57317 #define S_TSC15RATEEN    30
57318 #define V_TSC15RATEEN(x) ((x) << S_TSC15RATEEN)
57319 #define F_TSC15RATEEN    V_TSC15RATEEN(1U)
57320 
57321 #define S_TSC14WRREN    29
57322 #define V_TSC14WRREN(x) ((x) << S_TSC14WRREN)
57323 #define F_TSC14WRREN    V_TSC14WRREN(1U)
57324 
57325 #define S_TSC14RATEEN    28
57326 #define V_TSC14RATEEN(x) ((x) << S_TSC14RATEEN)
57327 #define F_TSC14RATEEN    V_TSC14RATEEN(1U)
57328 
57329 #define S_TSC13WRREN    27
57330 #define V_TSC13WRREN(x) ((x) << S_TSC13WRREN)
57331 #define F_TSC13WRREN    V_TSC13WRREN(1U)
57332 
57333 #define S_TSC13RATEEN    26
57334 #define V_TSC13RATEEN(x) ((x) << S_TSC13RATEEN)
57335 #define F_TSC13RATEEN    V_TSC13RATEEN(1U)
57336 
57337 #define S_TSC12WRREN    25
57338 #define V_TSC12WRREN(x) ((x) << S_TSC12WRREN)
57339 #define F_TSC12WRREN    V_TSC12WRREN(1U)
57340 
57341 #define S_TSC12RATEEN    24
57342 #define V_TSC12RATEEN(x) ((x) << S_TSC12RATEEN)
57343 #define F_TSC12RATEEN    V_TSC12RATEEN(1U)
57344 
57345 #define S_TSC11WRREN    23
57346 #define V_TSC11WRREN(x) ((x) << S_TSC11WRREN)
57347 #define F_TSC11WRREN    V_TSC11WRREN(1U)
57348 
57349 #define S_TSC11RATEEN    22
57350 #define V_TSC11RATEEN(x) ((x) << S_TSC11RATEEN)
57351 #define F_TSC11RATEEN    V_TSC11RATEEN(1U)
57352 
57353 #define S_TSC10WRREN    21
57354 #define V_TSC10WRREN(x) ((x) << S_TSC10WRREN)
57355 #define F_TSC10WRREN    V_TSC10WRREN(1U)
57356 
57357 #define S_TSC10RATEEN    20
57358 #define V_TSC10RATEEN(x) ((x) << S_TSC10RATEEN)
57359 #define F_TSC10RATEEN    V_TSC10RATEEN(1U)
57360 
57361 #define S_TSC9WRREN    19
57362 #define V_TSC9WRREN(x) ((x) << S_TSC9WRREN)
57363 #define F_TSC9WRREN    V_TSC9WRREN(1U)
57364 
57365 #define S_TSC9RATEEN    18
57366 #define V_TSC9RATEEN(x) ((x) << S_TSC9RATEEN)
57367 #define F_TSC9RATEEN    V_TSC9RATEEN(1U)
57368 
57369 #define S_TSC8WRREN    17
57370 #define V_TSC8WRREN(x) ((x) << S_TSC8WRREN)
57371 #define F_TSC8WRREN    V_TSC8WRREN(1U)
57372 
57373 #define S_TSC8RATEEN    16
57374 #define V_TSC8RATEEN(x) ((x) << S_TSC8RATEEN)
57375 #define F_TSC8RATEEN    V_TSC8RATEEN(1U)
57376 
57377 #define S_TSC7WRREN    15
57378 #define V_TSC7WRREN(x) ((x) << S_TSC7WRREN)
57379 #define F_TSC7WRREN    V_TSC7WRREN(1U)
57380 
57381 #define S_TSC7RATEEN    14
57382 #define V_TSC7RATEEN(x) ((x) << S_TSC7RATEEN)
57383 #define F_TSC7RATEEN    V_TSC7RATEEN(1U)
57384 
57385 #define S_TSC6WRREN    13
57386 #define V_TSC6WRREN(x) ((x) << S_TSC6WRREN)
57387 #define F_TSC6WRREN    V_TSC6WRREN(1U)
57388 
57389 #define S_TSC6RATEEN    12
57390 #define V_TSC6RATEEN(x) ((x) << S_TSC6RATEEN)
57391 #define F_TSC6RATEEN    V_TSC6RATEEN(1U)
57392 
57393 #define S_TSC5WRREN    11
57394 #define V_TSC5WRREN(x) ((x) << S_TSC5WRREN)
57395 #define F_TSC5WRREN    V_TSC5WRREN(1U)
57396 
57397 #define S_TSC5RATEEN    10
57398 #define V_TSC5RATEEN(x) ((x) << S_TSC5RATEEN)
57399 #define F_TSC5RATEEN    V_TSC5RATEEN(1U)
57400 
57401 #define S_TSC4WRREN    9
57402 #define V_TSC4WRREN(x) ((x) << S_TSC4WRREN)
57403 #define F_TSC4WRREN    V_TSC4WRREN(1U)
57404 
57405 #define S_TSC4RATEEN    8
57406 #define V_TSC4RATEEN(x) ((x) << S_TSC4RATEEN)
57407 #define F_TSC4RATEEN    V_TSC4RATEEN(1U)
57408 
57409 #define S_TSC3WRREN    7
57410 #define V_TSC3WRREN(x) ((x) << S_TSC3WRREN)
57411 #define F_TSC3WRREN    V_TSC3WRREN(1U)
57412 
57413 #define S_TSC3RATEEN    6
57414 #define V_TSC3RATEEN(x) ((x) << S_TSC3RATEEN)
57415 #define F_TSC3RATEEN    V_TSC3RATEEN(1U)
57416 
57417 #define S_TSC2WRREN    5
57418 #define V_TSC2WRREN(x) ((x) << S_TSC2WRREN)
57419 #define F_TSC2WRREN    V_TSC2WRREN(1U)
57420 
57421 #define S_TSC2RATEEN    4
57422 #define V_TSC2RATEEN(x) ((x) << S_TSC2RATEEN)
57423 #define F_TSC2RATEEN    V_TSC2RATEEN(1U)
57424 
57425 #define S_TSC1WRREN    3
57426 #define V_TSC1WRREN(x) ((x) << S_TSC1WRREN)
57427 #define F_TSC1WRREN    V_TSC1WRREN(1U)
57428 
57429 #define S_TSC1RATEEN    2
57430 #define V_TSC1RATEEN(x) ((x) << S_TSC1RATEEN)
57431 #define F_TSC1RATEEN    V_TSC1RATEEN(1U)
57432 
57433 #define S_TSC0WRREN    1
57434 #define V_TSC0WRREN(x) ((x) << S_TSC0WRREN)
57435 #define F_TSC0WRREN    V_TSC0WRREN(1U)
57436 
57437 #define S_TSC0RATEEN    0
57438 #define V_TSC0RATEEN(x) ((x) << S_TSC0RATEEN)
57439 #define F_TSC0RATEEN    V_TSC0RATEEN(1U)
57440 
57441 #define A_CIM_CTL_TSCH_MIN_MAX_EN 0x90c
57442 
57443 #define S_MIN_MAX_EN    0
57444 #define V_MIN_MAX_EN(x) ((x) << S_MIN_MAX_EN)
57445 #define F_MIN_MAX_EN    V_MIN_MAX_EN(1U)
57446 
57447 #define A_CIM_CTL_TSCH_CHNLN_RATE_LIMITER 0x910
57448 
57449 #define S_TSCHNLRATENEG    31
57450 #define V_TSCHNLRATENEG(x) ((x) << S_TSCHNLRATENEG)
57451 #define F_TSCHNLRATENEG    V_TSCHNLRATENEG(1U)
57452 
57453 #define S_TSCHNLRATEL    0
57454 #define M_TSCHNLRATEL    0x7fffffffU
57455 #define V_TSCHNLRATEL(x) ((x) << S_TSCHNLRATEL)
57456 #define G_TSCHNLRATEL(x) (((x) >> S_TSCHNLRATEL) & M_TSCHNLRATEL)
57457 
57458 #define S_TSCHNLRATEPROT    30
57459 #define V_TSCHNLRATEPROT(x) ((x) << S_TSCHNLRATEPROT)
57460 #define F_TSCHNLRATEPROT    V_TSCHNLRATEPROT(1U)
57461 
57462 #define S_T6_TSCHNLRATEL    0
57463 #define M_T6_TSCHNLRATEL    0x3fffffffU
57464 #define V_T6_TSCHNLRATEL(x) ((x) << S_T6_TSCHNLRATEL)
57465 #define G_T6_TSCHNLRATEL(x) (((x) >> S_T6_TSCHNLRATEL) & M_T6_TSCHNLRATEL)
57466 
57467 #define A_CIM_CTL_TSCH_CHNLN_RATE_PROPERTIES 0x914
57468 
57469 #define S_TSCHNLRMAX    16
57470 #define M_TSCHNLRMAX    0xffffU
57471 #define V_TSCHNLRMAX(x) ((x) << S_TSCHNLRMAX)
57472 #define G_TSCHNLRMAX(x) (((x) >> S_TSCHNLRMAX) & M_TSCHNLRMAX)
57473 
57474 #define S_TSCHNLRINCR    0
57475 #define M_TSCHNLRINCR    0xffffU
57476 #define V_TSCHNLRINCR(x) ((x) << S_TSCHNLRINCR)
57477 #define G_TSCHNLRINCR(x) (((x) >> S_TSCHNLRINCR) & M_TSCHNLRINCR)
57478 
57479 #define S_TSCHNLRTSEL    14
57480 #define M_TSCHNLRTSEL    0x3U
57481 #define V_TSCHNLRTSEL(x) ((x) << S_TSCHNLRTSEL)
57482 #define G_TSCHNLRTSEL(x) (((x) >> S_TSCHNLRTSEL) & M_TSCHNLRTSEL)
57483 
57484 #define S_T6_TSCHNLRINCR    0
57485 #define M_T6_TSCHNLRINCR    0x3fffU
57486 #define V_T6_TSCHNLRINCR(x) ((x) << S_T6_TSCHNLRINCR)
57487 #define G_T6_TSCHNLRINCR(x) (((x) >> S_T6_TSCHNLRINCR) & M_T6_TSCHNLRINCR)
57488 
57489 #define A_CIM_CTL_TSCH_CHNLN_WRR 0x918
57490 #define A_CIM_CTL_TSCH_CHNLN_WEIGHT 0x91c
57491 
57492 #define S_TSCHNLWEIGHT    0
57493 #define M_TSCHNLWEIGHT    0x3fffffU
57494 #define V_TSCHNLWEIGHT(x) ((x) << S_TSCHNLWEIGHT)
57495 #define G_TSCHNLWEIGHT(x) (((x) >> S_TSCHNLWEIGHT) & M_TSCHNLWEIGHT)
57496 
57497 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_LIMITER 0x920
57498 
57499 #define S_TSCCLRATENEG    31
57500 #define V_TSCCLRATENEG(x) ((x) << S_TSCCLRATENEG)
57501 #define F_TSCCLRATENEG    V_TSCCLRATENEG(1U)
57502 
57503 #define S_TSCCLRATEL    0
57504 #define M_TSCCLRATEL    0xffffffU
57505 #define V_TSCCLRATEL(x) ((x) << S_TSCCLRATEL)
57506 #define G_TSCCLRATEL(x) (((x) >> S_TSCCLRATEL) & M_TSCCLRATEL)
57507 
57508 #define S_TSCCLRATEPROT    30
57509 #define V_TSCCLRATEPROT(x) ((x) << S_TSCCLRATEPROT)
57510 #define F_TSCCLRATEPROT    V_TSCCLRATEPROT(1U)
57511 
57512 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_PROPERTIES 0x924
57513 
57514 #define S_TSCCLRMAX    16
57515 #define M_TSCCLRMAX    0xffffU
57516 #define V_TSCCLRMAX(x) ((x) << S_TSCCLRMAX)
57517 #define G_TSCCLRMAX(x) (((x) >> S_TSCCLRMAX) & M_TSCCLRMAX)
57518 
57519 #define S_TSCCLRINCR    0
57520 #define M_TSCCLRINCR    0xffffU
57521 #define V_TSCCLRINCR(x) ((x) << S_TSCCLRINCR)
57522 #define G_TSCCLRINCR(x) (((x) >> S_TSCCLRINCR) & M_TSCCLRINCR)
57523 
57524 #define S_TSCCLRTSEL    14
57525 #define M_TSCCLRTSEL    0x3U
57526 #define V_TSCCLRTSEL(x) ((x) << S_TSCCLRTSEL)
57527 #define G_TSCCLRTSEL(x) (((x) >> S_TSCCLRTSEL) & M_TSCCLRTSEL)
57528 
57529 #define S_T6_TSCCLRINCR    0
57530 #define M_T6_TSCCLRINCR    0x3fffU
57531 #define V_T6_TSCCLRINCR(x) ((x) << S_T6_TSCCLRINCR)
57532 #define G_T6_TSCCLRINCR(x) (((x) >> S_T6_TSCCLRINCR) & M_T6_TSCCLRINCR)
57533 
57534 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_WRR 0x928
57535 
57536 #define S_TSCCLWRRNEG    31
57537 #define V_TSCCLWRRNEG(x) ((x) << S_TSCCLWRRNEG)
57538 #define F_TSCCLWRRNEG    V_TSCCLWRRNEG(1U)
57539 
57540 #define S_TSCCLWRR    0
57541 #define M_TSCCLWRR    0x3ffffffU
57542 #define V_TSCCLWRR(x) ((x) << S_TSCCLWRR)
57543 #define G_TSCCLWRR(x) (((x) >> S_TSCCLWRR) & M_TSCCLWRR)
57544 
57545 #define S_TSCCLWRRPROT    30
57546 #define V_TSCCLWRRPROT(x) ((x) << S_TSCCLWRRPROT)
57547 #define F_TSCCLWRRPROT    V_TSCCLWRRPROT(1U)
57548 
57549 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_WEIGHT 0x92c
57550 
57551 #define S_TSCCLWEIGHT    0
57552 #define M_TSCCLWEIGHT    0xffffU
57553 #define V_TSCCLWEIGHT(x) ((x) << S_TSCCLWEIGHT)
57554 #define G_TSCCLWEIGHT(x) (((x) >> S_TSCCLWEIGHT) & M_TSCCLWEIGHT)
57555 
57556 #define S_PAUSEVECSEL    28
57557 #define M_PAUSEVECSEL    0x3U
57558 #define V_PAUSEVECSEL(x) ((x) << S_PAUSEVECSEL)
57559 #define G_PAUSEVECSEL(x) (((x) >> S_PAUSEVECSEL) & M_PAUSEVECSEL)
57560 
57561 #define S_MPSPAUSEMASK    20
57562 #define M_MPSPAUSEMASK    0xffU
57563 #define V_MPSPAUSEMASK(x) ((x) << S_MPSPAUSEMASK)
57564 #define G_MPSPAUSEMASK(x) (((x) >> S_MPSPAUSEMASK) & M_MPSPAUSEMASK)
57565 
57566 #define A_CIM_CTL_TSCH_TICK0 0xd80
57567 #define A_CIM_CTL_MAILBOX_PF0_CTL 0xd84
57568 #define A_CIM_CTL_TSCH_TICK1 0xd84
57569 #define A_CIM_CTL_MAILBOX_PF1_CTL 0xd88
57570 #define A_CIM_CTL_TSCH_TICK2 0xd88
57571 #define A_CIM_CTL_MAILBOX_PF2_CTL 0xd8c
57572 #define A_CIM_CTL_TSCH_TICK3 0xd8c
57573 #define A_CIM_CTL_MAILBOX_PF3_CTL 0xd90
57574 #define A_T6_CIM_CTL_MAILBOX_PF0_CTL 0xd90
57575 #define A_T7_CIM_CTL_MAILBOX_PF0_CTL 0xd90
57576 #define A_CIM_CTL_MAILBOX_PF4_CTL 0xd94
57577 #define A_T6_CIM_CTL_MAILBOX_PF1_CTL 0xd94
57578 #define A_T7_CIM_CTL_MAILBOX_PF1_CTL 0xd94
57579 #define A_CIM_CTL_MAILBOX_PF5_CTL 0xd98
57580 #define A_T6_CIM_CTL_MAILBOX_PF2_CTL 0xd98
57581 #define A_T7_CIM_CTL_MAILBOX_PF2_CTL 0xd98
57582 #define A_CIM_CTL_MAILBOX_PF6_CTL 0xd9c
57583 #define A_T6_CIM_CTL_MAILBOX_PF3_CTL 0xd9c
57584 #define A_T7_CIM_CTL_MAILBOX_PF3_CTL 0xd9c
57585 #define A_CIM_CTL_MAILBOX_PF7_CTL 0xda0
57586 #define A_T6_CIM_CTL_MAILBOX_PF4_CTL 0xda0
57587 #define A_T7_CIM_CTL_MAILBOX_PF4_CTL 0xda0
57588 #define A_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xda4
57589 
57590 #define S_PF7_OWNER_PL    15
57591 #define V_PF7_OWNER_PL(x) ((x) << S_PF7_OWNER_PL)
57592 #define F_PF7_OWNER_PL    V_PF7_OWNER_PL(1U)
57593 
57594 #define S_PF6_OWNER_PL    14
57595 #define V_PF6_OWNER_PL(x) ((x) << S_PF6_OWNER_PL)
57596 #define F_PF6_OWNER_PL    V_PF6_OWNER_PL(1U)
57597 
57598 #define S_PF5_OWNER_PL    13
57599 #define V_PF5_OWNER_PL(x) ((x) << S_PF5_OWNER_PL)
57600 #define F_PF5_OWNER_PL    V_PF5_OWNER_PL(1U)
57601 
57602 #define S_PF4_OWNER_PL    12
57603 #define V_PF4_OWNER_PL(x) ((x) << S_PF4_OWNER_PL)
57604 #define F_PF4_OWNER_PL    V_PF4_OWNER_PL(1U)
57605 
57606 #define S_PF3_OWNER_PL    11
57607 #define V_PF3_OWNER_PL(x) ((x) << S_PF3_OWNER_PL)
57608 #define F_PF3_OWNER_PL    V_PF3_OWNER_PL(1U)
57609 
57610 #define S_PF2_OWNER_PL    10
57611 #define V_PF2_OWNER_PL(x) ((x) << S_PF2_OWNER_PL)
57612 #define F_PF2_OWNER_PL    V_PF2_OWNER_PL(1U)
57613 
57614 #define S_PF1_OWNER_PL    9
57615 #define V_PF1_OWNER_PL(x) ((x) << S_PF1_OWNER_PL)
57616 #define F_PF1_OWNER_PL    V_PF1_OWNER_PL(1U)
57617 
57618 #define S_PF0_OWNER_PL    8
57619 #define V_PF0_OWNER_PL(x) ((x) << S_PF0_OWNER_PL)
57620 #define F_PF0_OWNER_PL    V_PF0_OWNER_PL(1U)
57621 
57622 #define S_PF7_OWNER_UP    7
57623 #define V_PF7_OWNER_UP(x) ((x) << S_PF7_OWNER_UP)
57624 #define F_PF7_OWNER_UP    V_PF7_OWNER_UP(1U)
57625 
57626 #define S_PF6_OWNER_UP    6
57627 #define V_PF6_OWNER_UP(x) ((x) << S_PF6_OWNER_UP)
57628 #define F_PF6_OWNER_UP    V_PF6_OWNER_UP(1U)
57629 
57630 #define S_PF5_OWNER_UP    5
57631 #define V_PF5_OWNER_UP(x) ((x) << S_PF5_OWNER_UP)
57632 #define F_PF5_OWNER_UP    V_PF5_OWNER_UP(1U)
57633 
57634 #define S_PF4_OWNER_UP    4
57635 #define V_PF4_OWNER_UP(x) ((x) << S_PF4_OWNER_UP)
57636 #define F_PF4_OWNER_UP    V_PF4_OWNER_UP(1U)
57637 
57638 #define S_PF3_OWNER_UP    3
57639 #define V_PF3_OWNER_UP(x) ((x) << S_PF3_OWNER_UP)
57640 #define F_PF3_OWNER_UP    V_PF3_OWNER_UP(1U)
57641 
57642 #define S_PF2_OWNER_UP    2
57643 #define V_PF2_OWNER_UP(x) ((x) << S_PF2_OWNER_UP)
57644 #define F_PF2_OWNER_UP    V_PF2_OWNER_UP(1U)
57645 
57646 #define S_PF1_OWNER_UP    1
57647 #define V_PF1_OWNER_UP(x) ((x) << S_PF1_OWNER_UP)
57648 #define F_PF1_OWNER_UP    V_PF1_OWNER_UP(1U)
57649 
57650 #define S_PF0_OWNER_UP    0
57651 #define V_PF0_OWNER_UP(x) ((x) << S_PF0_OWNER_UP)
57652 #define F_PF0_OWNER_UP    V_PF0_OWNER_UP(1U)
57653 
57654 #define A_T6_CIM_CTL_MAILBOX_PF5_CTL 0xda4
57655 #define A_T7_CIM_CTL_MAILBOX_PF5_CTL 0xda4
57656 #define A_CIM_CTL_PIO_MST_CONFIG 0xda8
57657 
57658 #define S_T5_CTLRID    0
57659 #define M_T5_CTLRID    0xffU
57660 #define V_T5_CTLRID(x) ((x) << S_T5_CTLRID)
57661 #define G_T5_CTLRID(x) (((x) >> S_T5_CTLRID) & M_T5_CTLRID)
57662 
57663 #define A_T6_CIM_CTL_MAILBOX_PF6_CTL 0xda8
57664 #define A_T7_CIM_CTL_MAILBOX_PF6_CTL 0xda8
57665 #define A_T6_CIM_CTL_MAILBOX_PF7_CTL 0xdac
57666 #define A_T7_CIM_CTL_MAILBOX_PF7_CTL 0xdac
57667 #define A_T6_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xdb0
57668 #define A_T7_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xdb0
57669 #define A_T6_CIM_CTL_PIO_MST_CONFIG 0xdb4
57670 #define A_T7_CIM_CTL_PIO_MST_CONFIG 0xdb4
57671 #define A_CIM_CTL_ULP_OBQ0_PAUSE_MASK 0xe00
57672 #define A_CIM_CTL_ULP_OBQ1_PAUSE_MASK 0xe04
57673 #define A_CIM_CTL_ULP_OBQ2_PAUSE_MASK 0xe08
57674 #define A_CIM_CTL_ULP_OBQ3_PAUSE_MASK 0xe0c
57675 #define A_CIM_CTL_ULP_OBQ_CONFIG 0xe10
57676 
57677 #define S_CH1_PRIO_EN    1
57678 #define V_CH1_PRIO_EN(x) ((x) << S_CH1_PRIO_EN)
57679 #define F_CH1_PRIO_EN    V_CH1_PRIO_EN(1U)
57680 
57681 #define S_CH0_PRIO_EN    0
57682 #define V_CH0_PRIO_EN(x) ((x) << S_CH0_PRIO_EN)
57683 #define F_CH0_PRIO_EN    V_CH0_PRIO_EN(1U)
57684 
57685 #define A_CIM_CTL_PIF_TIMEOUT 0xe40
57686 
57687 #define S_SLOW_TIMEOUT    16
57688 #define M_SLOW_TIMEOUT    0xffffU
57689 #define V_SLOW_TIMEOUT(x) ((x) << S_SLOW_TIMEOUT)
57690 #define G_SLOW_TIMEOUT(x) (((x) >> S_SLOW_TIMEOUT) & M_SLOW_TIMEOUT)
57691 
57692 #define S_MA_TIMEOUT    0
57693 #define M_MA_TIMEOUT    0xffffU
57694 #define V_MA_TIMEOUT(x) ((x) << S_MA_TIMEOUT)
57695 #define G_MA_TIMEOUT(x) (((x) >> S_MA_TIMEOUT) & M_MA_TIMEOUT)
57696 
57697 #define A_CIM_CTL_BREAK 0xf00
57698 
57699 #define S_XOCDMODE    8
57700 #define M_XOCDMODE    0xffU
57701 #define V_XOCDMODE(x) ((x) << S_XOCDMODE)
57702 #define G_XOCDMODE(x) (((x) >> S_XOCDMODE) & M_XOCDMODE)
57703 
57704 #define S_BREAKIN_CONTROL    0
57705 #define M_BREAKIN_CONTROL    0xffU
57706 #define V_BREAKIN_CONTROL(x) ((x) << S_BREAKIN_CONTROL)
57707 #define G_BREAKIN_CONTROL(x) (((x) >> S_BREAKIN_CONTROL) & M_BREAKIN_CONTROL)
57708 
57709 #define A_CIM_CTL_SLV_BOOT_CFG 0x4000
57710 
57711 #define S_T7_UPGEN    3
57712 #define M_T7_UPGEN    0x1fU
57713 #define V_T7_UPGEN(x) ((x) << S_T7_UPGEN)
57714 #define G_T7_UPGEN(x) (((x) >> S_T7_UPGEN) & M_T7_UPGEN)
57715 
57716 #define S_UPCLKEN    2
57717 #define V_UPCLKEN(x) ((x) << S_UPCLKEN)
57718 #define F_UPCLKEN    V_UPCLKEN(1U)
57719 
57720 #define A_CIM_CTL_SLV_BOOT_LEN 0x4004
57721 #define A_CIM_CTL_SLV_ACC_INT_ENABLE 0x4008
57722 #define A_CIM_CTL_SLV_ACC_INT_CAUSE 0x400c
57723 #define A_CIM_CTL_SLV_INT_ENABLE 0x4010
57724 #define A_CIM_CTL_SLV_INT_CAUSE 0x4014
57725 #define A_CIM_CTL_SLV_PERR_ENABLE 0x4018
57726 #define A_CIM_CTL_SLV_PERR_CAUSE 0x401c
57727 #define A_CIM_CTL_SLV_ADDR_TIMEOUT 0x4028
57728 #define A_CIM_CTL_SLV_ADDR_ILLEGAL 0x402c
57729 #define A_CIM_CTL_SLV_PIO_MST_CONFIG 0x4030
57730 #define A_CIM_CTL_SLV_MEM_ZONE0_VA 0x4040
57731 #define A_CIM_CTL_SLV_MEM_ZONE0_BA 0x4044
57732 #define A_CIM_CTL_SLV_MEM_ZONE0_LEN 0x4048
57733 #define A_CIM_CTL_SLV_MEM_ZONE1_VA 0x404c
57734 #define A_CIM_CTL_SLV_MEM_ZONE1_BA 0x4050
57735 #define A_CIM_CTL_SLV_MEM_ZONE1_LEN 0x4054
57736 #define A_CIM_CTL_SLV_MEM_ZONE2_VA 0x4058
57737 #define A_CIM_CTL_SLV_MEM_ZONE2_BA 0x405c
57738 #define A_CIM_CTL_SLV_MEM_ZONE2_LEN 0x4060
57739 #define A_CIM_CTL_SLV_MEM_ZONE3_VA 0x4064
57740 #define A_CIM_CTL_SLV_MEM_ZONE3_BA 0x4068
57741 #define A_CIM_CTL_SLV_MEM_ZONE3_LEN 0x406c
57742 #define A_CIM_CTL_SLV_MEM_ZONE4_VA 0x4070
57743 #define A_CIM_CTL_SLV_MEM_ZONE4_BA 0x4074
57744 #define A_CIM_CTL_SLV_MEM_ZONE4_LEN 0x4078
57745 #define A_CIM_CTL_SLV_MEM_ZONE5_VA 0x407c
57746 #define A_CIM_CTL_SLV_MEM_ZONE5_BA 0x4080
57747 #define A_CIM_CTL_SLV_MEM_ZONE5_LEN 0x4084
57748 #define A_CIM_CTL_SLV_MEM_ZONE6_VA 0x4088
57749 #define A_CIM_CTL_SLV_MEM_ZONE6_BA 0x408c
57750 #define A_CIM_CTL_SLV_MEM_ZONE6_LEN 0x4090
57751 #define A_CIM_CTL_SLV_MEM_ZONE7_VA 0x4094
57752 #define A_CIM_CTL_SLV_MEM_ZONE7_BA 0x4098
57753 #define A_CIM_CTL_SLV_MEM_ZONE7_LEN 0x409c
57754 
57755 /* registers for module MAC */
57756 #define MAC_BASE_ADDR 0x0
57757 
57758 #define A_MAC_PORT_CFG 0x800
57759 
57760 #define S_MAC_CLK_SEL    29
57761 #define M_MAC_CLK_SEL    0x7U
57762 #define V_MAC_CLK_SEL(x) ((x) << S_MAC_CLK_SEL)
57763 #define G_MAC_CLK_SEL(x) (((x) >> S_MAC_CLK_SEL) & M_MAC_CLK_SEL)
57764 
57765 #define S_SMUXTXSEL    9
57766 #define V_SMUXTXSEL(x) ((x) << S_SMUXTXSEL)
57767 #define F_SMUXTXSEL    V_SMUXTXSEL(1U)
57768 
57769 #define S_SMUXRXSEL    8
57770 #define V_SMUXRXSEL(x) ((x) << S_SMUXRXSEL)
57771 #define F_SMUXRXSEL    V_SMUXRXSEL(1U)
57772 
57773 #define S_PORTSPEED    4
57774 #define M_PORTSPEED    0x3U
57775 #define V_PORTSPEED(x) ((x) << S_PORTSPEED)
57776 #define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED)
57777 
57778 #define S_ENA_ERR_RSP    28
57779 #define V_ENA_ERR_RSP(x) ((x) << S_ENA_ERR_RSP)
57780 #define F_ENA_ERR_RSP    V_ENA_ERR_RSP(1U)
57781 
57782 #define S_DEBUG_CLR    25
57783 #define V_DEBUG_CLR(x) ((x) << S_DEBUG_CLR)
57784 #define F_DEBUG_CLR    V_DEBUG_CLR(1U)
57785 
57786 #define S_PLL_SEL    23
57787 #define V_PLL_SEL(x) ((x) << S_PLL_SEL)
57788 #define F_PLL_SEL    V_PLL_SEL(1U)
57789 
57790 #define S_PORT_MAP    20
57791 #define M_PORT_MAP    0x7U
57792 #define V_PORT_MAP(x) ((x) << S_PORT_MAP)
57793 #define G_PORT_MAP(x) (((x) >> S_PORT_MAP) & M_PORT_MAP)
57794 
57795 #define S_AEC_PAT_DATA    15
57796 #define V_AEC_PAT_DATA(x) ((x) << S_AEC_PAT_DATA)
57797 #define F_AEC_PAT_DATA    V_AEC_PAT_DATA(1U)
57798 
57799 #define S_MACCLK_SEL    13
57800 #define V_MACCLK_SEL(x) ((x) << S_MACCLK_SEL)
57801 #define F_MACCLK_SEL    V_MACCLK_SEL(1U)
57802 
57803 #define S_XGMII_SEL    12
57804 #define V_XGMII_SEL(x) ((x) << S_XGMII_SEL)
57805 #define F_XGMII_SEL    V_XGMII_SEL(1U)
57806 
57807 #define S_DEBUG_PORT_SEL    10
57808 #define M_DEBUG_PORT_SEL    0x3U
57809 #define V_DEBUG_PORT_SEL(x) ((x) << S_DEBUG_PORT_SEL)
57810 #define G_DEBUG_PORT_SEL(x) (((x) >> S_DEBUG_PORT_SEL) & M_DEBUG_PORT_SEL)
57811 
57812 #define S_ENABLE_25G    7
57813 #define V_ENABLE_25G(x) ((x) << S_ENABLE_25G)
57814 #define F_ENABLE_25G    V_ENABLE_25G(1U)
57815 
57816 #define S_ENABLE_50G    6
57817 #define V_ENABLE_50G(x) ((x) << S_ENABLE_50G)
57818 #define F_ENABLE_50G    V_ENABLE_50G(1U)
57819 
57820 #define S_DEBUG_TX_RX_SEL    1
57821 #define V_DEBUG_TX_RX_SEL(x) ((x) << S_DEBUG_TX_RX_SEL)
57822 #define F_DEBUG_TX_RX_SEL    V_DEBUG_TX_RX_SEL(1U)
57823 
57824 #define A_MAC_PORT_RESET_CTRL 0x804
57825 
57826 #define S_TWGDSK_HSSC16B    31
57827 #define V_TWGDSK_HSSC16B(x) ((x) << S_TWGDSK_HSSC16B)
57828 #define F_TWGDSK_HSSC16B    V_TWGDSK_HSSC16B(1U)
57829 
57830 #define S_EEE_RESET    30
57831 #define V_EEE_RESET(x) ((x) << S_EEE_RESET)
57832 #define F_EEE_RESET    V_EEE_RESET(1U)
57833 
57834 #define S_PTP_TIMER    29
57835 #define V_PTP_TIMER(x) ((x) << S_PTP_TIMER)
57836 #define F_PTP_TIMER    V_PTP_TIMER(1U)
57837 
57838 #define S_MTIPREFRESET    28
57839 #define V_MTIPREFRESET(x) ((x) << S_MTIPREFRESET)
57840 #define F_MTIPREFRESET    V_MTIPREFRESET(1U)
57841 
57842 #define S_MTIPTXFFRESET    27
57843 #define V_MTIPTXFFRESET(x) ((x) << S_MTIPTXFFRESET)
57844 #define F_MTIPTXFFRESET    V_MTIPTXFFRESET(1U)
57845 
57846 #define S_MTIPRXFFRESET    26
57847 #define V_MTIPRXFFRESET(x) ((x) << S_MTIPRXFFRESET)
57848 #define F_MTIPRXFFRESET    V_MTIPRXFFRESET(1U)
57849 
57850 #define S_MTIPREGRESET    25
57851 #define V_MTIPREGRESET(x) ((x) << S_MTIPREGRESET)
57852 #define F_MTIPREGRESET    V_MTIPREGRESET(1U)
57853 
57854 #define S_AEC3RESET    23
57855 #define V_AEC3RESET(x) ((x) << S_AEC3RESET)
57856 #define F_AEC3RESET    V_AEC3RESET(1U)
57857 
57858 #define S_AEC2RESET    22
57859 #define V_AEC2RESET(x) ((x) << S_AEC2RESET)
57860 #define F_AEC2RESET    V_AEC2RESET(1U)
57861 
57862 #define S_AEC1RESET    21
57863 #define V_AEC1RESET(x) ((x) << S_AEC1RESET)
57864 #define F_AEC1RESET    V_AEC1RESET(1U)
57865 
57866 #define S_AEC0RESET    20
57867 #define V_AEC0RESET(x) ((x) << S_AEC0RESET)
57868 #define F_AEC0RESET    V_AEC0RESET(1U)
57869 
57870 #define S_AET3RESET    19
57871 #define V_AET3RESET(x) ((x) << S_AET3RESET)
57872 #define F_AET3RESET    V_AET3RESET(1U)
57873 
57874 #define S_AET2RESET    18
57875 #define V_AET2RESET(x) ((x) << S_AET2RESET)
57876 #define F_AET2RESET    V_AET2RESET(1U)
57877 
57878 #define S_AET1RESET    17
57879 #define V_AET1RESET(x) ((x) << S_AET1RESET)
57880 #define F_AET1RESET    V_AET1RESET(1U)
57881 
57882 #define S_AET0RESET    16
57883 #define V_AET0RESET(x) ((x) << S_AET0RESET)
57884 #define F_AET0RESET    V_AET0RESET(1U)
57885 
57886 #define S_TXIF_RESET    12
57887 #define V_TXIF_RESET(x) ((x) << S_TXIF_RESET)
57888 #define F_TXIF_RESET    V_TXIF_RESET(1U)
57889 
57890 #define S_RXIF_RESET    11
57891 #define V_RXIF_RESET(x) ((x) << S_RXIF_RESET)
57892 #define F_RXIF_RESET    V_RXIF_RESET(1U)
57893 
57894 #define S_MTIPSD3TXRST    9
57895 #define V_MTIPSD3TXRST(x) ((x) << S_MTIPSD3TXRST)
57896 #define F_MTIPSD3TXRST    V_MTIPSD3TXRST(1U)
57897 
57898 #define S_MTIPSD2TXRST    8
57899 #define V_MTIPSD2TXRST(x) ((x) << S_MTIPSD2TXRST)
57900 #define F_MTIPSD2TXRST    V_MTIPSD2TXRST(1U)
57901 
57902 #define S_MTIPSD1TXRST    7
57903 #define V_MTIPSD1TXRST(x) ((x) << S_MTIPSD1TXRST)
57904 #define F_MTIPSD1TXRST    V_MTIPSD1TXRST(1U)
57905 
57906 #define S_MTIPSD0TXRST    6
57907 #define V_MTIPSD0TXRST(x) ((x) << S_MTIPSD0TXRST)
57908 #define F_MTIPSD0TXRST    V_MTIPSD0TXRST(1U)
57909 
57910 #define S_MTIPSD3RXRST    5
57911 #define V_MTIPSD3RXRST(x) ((x) << S_MTIPSD3RXRST)
57912 #define F_MTIPSD3RXRST    V_MTIPSD3RXRST(1U)
57913 
57914 #define S_MTIPSD2RXRST    4
57915 #define V_MTIPSD2RXRST(x) ((x) << S_MTIPSD2RXRST)
57916 #define F_MTIPSD2RXRST    V_MTIPSD2RXRST(1U)
57917 
57918 #define S_MTIPSD1RXRST    3
57919 #define V_MTIPSD1RXRST(x) ((x) << S_MTIPSD1RXRST)
57920 #define F_MTIPSD1RXRST    V_MTIPSD1RXRST(1U)
57921 
57922 #define S_MTIPSD0RXRST    1
57923 #define V_MTIPSD0RXRST(x) ((x) << S_MTIPSD0RXRST)
57924 #define F_MTIPSD0RXRST    V_MTIPSD0RXRST(1U)
57925 
57926 #define S_MAC100G40G_RESET    27
57927 #define V_MAC100G40G_RESET(x) ((x) << S_MAC100G40G_RESET)
57928 #define F_MAC100G40G_RESET    V_MAC100G40G_RESET(1U)
57929 
57930 #define S_MAC10G1G_RESET    26
57931 #define V_MAC10G1G_RESET(x) ((x) << S_MAC10G1G_RESET)
57932 #define F_MAC10G1G_RESET    V_MAC10G1G_RESET(1U)
57933 
57934 #define S_PCS1G_RESET    24
57935 #define V_PCS1G_RESET(x) ((x) << S_PCS1G_RESET)
57936 #define F_PCS1G_RESET    V_PCS1G_RESET(1U)
57937 
57938 #define S_PCS10G_RESET    15
57939 #define V_PCS10G_RESET(x) ((x) << S_PCS10G_RESET)
57940 #define F_PCS10G_RESET    V_PCS10G_RESET(1U)
57941 
57942 #define S_PCS40G_RESET    14
57943 #define V_PCS40G_RESET(x) ((x) << S_PCS40G_RESET)
57944 #define F_PCS40G_RESET    V_PCS40G_RESET(1U)
57945 
57946 #define S_PCS100G_RESET    13
57947 #define V_PCS100G_RESET(x) ((x) << S_PCS100G_RESET)
57948 #define F_PCS100G_RESET    V_PCS100G_RESET(1U)
57949 
57950 #define A_MAC_PORT_LED_CFG 0x808
57951 
57952 #define S_LED1_CFG1    14
57953 #define M_LED1_CFG1    0x3U
57954 #define V_LED1_CFG1(x) ((x) << S_LED1_CFG1)
57955 #define G_LED1_CFG1(x) (((x) >> S_LED1_CFG1) & M_LED1_CFG1)
57956 
57957 #define S_LED0_CFG1    12
57958 #define M_LED0_CFG1    0x3U
57959 #define V_LED0_CFG1(x) ((x) << S_LED0_CFG1)
57960 #define G_LED0_CFG1(x) (((x) >> S_LED0_CFG1) & M_LED0_CFG1)
57961 
57962 #define S_LED1_TLO    11
57963 #define V_LED1_TLO(x) ((x) << S_LED1_TLO)
57964 #define F_LED1_TLO    V_LED1_TLO(1U)
57965 
57966 #define S_LED1_THI    10
57967 #define V_LED1_THI(x) ((x) << S_LED1_THI)
57968 #define F_LED1_THI    V_LED1_THI(1U)
57969 
57970 #define S_LED0_TLO    9
57971 #define V_LED0_TLO(x) ((x) << S_LED0_TLO)
57972 #define F_LED0_TLO    V_LED0_TLO(1U)
57973 
57974 #define S_LED0_THI    8
57975 #define V_LED0_THI(x) ((x) << S_LED0_THI)
57976 #define F_LED0_THI    V_LED0_THI(1U)
57977 
57978 #define A_MAC_PORT_LED_COUNTHI 0x80c
57979 #define A_MAC_PORT_LED_COUNTLO 0x810
57980 #define A_MAC_PORT_CFG3 0x814
57981 
57982 #define S_T5_FPGA_PTP_PORT    26
57983 #define M_T5_FPGA_PTP_PORT    0x3U
57984 #define V_T5_FPGA_PTP_PORT(x) ((x) << S_T5_FPGA_PTP_PORT)
57985 #define G_T5_FPGA_PTP_PORT(x) (((x) >> S_T5_FPGA_PTP_PORT) & M_T5_FPGA_PTP_PORT)
57986 
57987 #define S_FCSDISCTRL    25
57988 #define V_FCSDISCTRL(x) ((x) << S_FCSDISCTRL)
57989 #define F_FCSDISCTRL    V_FCSDISCTRL(1U)
57990 
57991 #define S_SIGDETCTRL    24
57992 #define V_SIGDETCTRL(x) ((x) << S_SIGDETCTRL)
57993 #define F_SIGDETCTRL    V_SIGDETCTRL(1U)
57994 
57995 #define S_TX_LANE    23
57996 #define V_TX_LANE(x) ((x) << S_TX_LANE)
57997 #define F_TX_LANE    V_TX_LANE(1U)
57998 
57999 #define S_RX_LANE    22
58000 #define V_RX_LANE(x) ((x) << S_RX_LANE)
58001 #define F_RX_LANE    V_RX_LANE(1U)
58002 
58003 #define S_SE_CLR    21
58004 #define V_SE_CLR(x) ((x) << S_SE_CLR)
58005 #define F_SE_CLR    V_SE_CLR(1U)
58006 
58007 #define S_AN_ENA    17
58008 #define M_AN_ENA    0xfU
58009 #define V_AN_ENA(x) ((x) << S_AN_ENA)
58010 #define G_AN_ENA(x) (((x) >> S_AN_ENA) & M_AN_ENA)
58011 
58012 #define S_SD_RX_CLK_ENA    13
58013 #define M_SD_RX_CLK_ENA    0xfU
58014 #define V_SD_RX_CLK_ENA(x) ((x) << S_SD_RX_CLK_ENA)
58015 #define G_SD_RX_CLK_ENA(x) (((x) >> S_SD_RX_CLK_ENA) & M_SD_RX_CLK_ENA)
58016 
58017 #define S_SD_TX_CLK_ENA    9
58018 #define M_SD_TX_CLK_ENA    0xfU
58019 #define V_SD_TX_CLK_ENA(x) ((x) << S_SD_TX_CLK_ENA)
58020 #define G_SD_TX_CLK_ENA(x) (((x) >> S_SD_TX_CLK_ENA) & M_SD_TX_CLK_ENA)
58021 
58022 #define S_SGMIISEL    8
58023 #define V_SGMIISEL(x) ((x) << S_SGMIISEL)
58024 #define F_SGMIISEL    V_SGMIISEL(1U)
58025 
58026 #define S_HSSPLLSEL    4
58027 #define M_HSSPLLSEL    0xfU
58028 #define V_HSSPLLSEL(x) ((x) << S_HSSPLLSEL)
58029 #define G_HSSPLLSEL(x) (((x) >> S_HSSPLLSEL) & M_HSSPLLSEL)
58030 
58031 #define S_HSSC16C20SEL    0
58032 #define M_HSSC16C20SEL    0xfU
58033 #define V_HSSC16C20SEL(x) ((x) << S_HSSC16C20SEL)
58034 #define G_HSSC16C20SEL(x) (((x) >> S_HSSC16C20SEL) & M_HSSC16C20SEL)
58035 
58036 #define S_REF_CLK_SEL    30
58037 #define M_REF_CLK_SEL    0x3U
58038 #define V_REF_CLK_SEL(x) ((x) << S_REF_CLK_SEL)
58039 #define G_REF_CLK_SEL(x) (((x) >> S_REF_CLK_SEL) & M_REF_CLK_SEL)
58040 
58041 #define S_SGMII_SD_SIG_DET    29
58042 #define V_SGMII_SD_SIG_DET(x) ((x) << S_SGMII_SD_SIG_DET)
58043 #define F_SGMII_SD_SIG_DET    V_SGMII_SD_SIG_DET(1U)
58044 
58045 #define S_SGMII_SGPCS_ENA    28
58046 #define V_SGMII_SGPCS_ENA(x) ((x) << S_SGMII_SGPCS_ENA)
58047 #define F_SGMII_SGPCS_ENA    V_SGMII_SGPCS_ENA(1U)
58048 
58049 #define S_MAC_FPGA_PTP_PORT    26
58050 #define M_MAC_FPGA_PTP_PORT    0x3U
58051 #define V_MAC_FPGA_PTP_PORT(x) ((x) << S_MAC_FPGA_PTP_PORT)
58052 #define G_MAC_FPGA_PTP_PORT(x) (((x) >> S_MAC_FPGA_PTP_PORT) & M_MAC_FPGA_PTP_PORT)
58053 
58054 #define A_MAC_PORT_CFG2 0x818
58055 
58056 #define S_T5_AEC_PMA_TX_READY    4
58057 #define M_T5_AEC_PMA_TX_READY    0xfU
58058 #define V_T5_AEC_PMA_TX_READY(x) ((x) << S_T5_AEC_PMA_TX_READY)
58059 #define G_T5_AEC_PMA_TX_READY(x) (((x) >> S_T5_AEC_PMA_TX_READY) & M_T5_AEC_PMA_TX_READY)
58060 
58061 #define S_T5_AEC_PMA_RX_READY    0
58062 #define M_T5_AEC_PMA_RX_READY    0xfU
58063 #define V_T5_AEC_PMA_RX_READY(x) ((x) << S_T5_AEC_PMA_RX_READY)
58064 #define G_T5_AEC_PMA_RX_READY(x) (((x) >> S_T5_AEC_PMA_RX_READY) & M_T5_AEC_PMA_RX_READY)
58065 
58066 #define S_AN_DATA_CTL    19
58067 #define V_AN_DATA_CTL(x) ((x) << S_AN_DATA_CTL)
58068 #define F_AN_DATA_CTL    V_AN_DATA_CTL(1U)
58069 
58070 #define A_MAC_PORT_PKT_COUNT 0x81c
58071 #define A_MAC_PORT_CFG4 0x820
58072 
58073 #define S_AEC3_RX_WIDTH    14
58074 #define M_AEC3_RX_WIDTH    0x3U
58075 #define V_AEC3_RX_WIDTH(x) ((x) << S_AEC3_RX_WIDTH)
58076 #define G_AEC3_RX_WIDTH(x) (((x) >> S_AEC3_RX_WIDTH) & M_AEC3_RX_WIDTH)
58077 
58078 #define S_AEC2_RX_WIDTH    12
58079 #define M_AEC2_RX_WIDTH    0x3U
58080 #define V_AEC2_RX_WIDTH(x) ((x) << S_AEC2_RX_WIDTH)
58081 #define G_AEC2_RX_WIDTH(x) (((x) >> S_AEC2_RX_WIDTH) & M_AEC2_RX_WIDTH)
58082 
58083 #define S_AEC1_RX_WIDTH    10
58084 #define M_AEC1_RX_WIDTH    0x3U
58085 #define V_AEC1_RX_WIDTH(x) ((x) << S_AEC1_RX_WIDTH)
58086 #define G_AEC1_RX_WIDTH(x) (((x) >> S_AEC1_RX_WIDTH) & M_AEC1_RX_WIDTH)
58087 
58088 #define S_AEC0_RX_WIDTH    8
58089 #define M_AEC0_RX_WIDTH    0x3U
58090 #define V_AEC0_RX_WIDTH(x) ((x) << S_AEC0_RX_WIDTH)
58091 #define G_AEC0_RX_WIDTH(x) (((x) >> S_AEC0_RX_WIDTH) & M_AEC0_RX_WIDTH)
58092 
58093 #define S_AEC3_TX_WIDTH    6
58094 #define M_AEC3_TX_WIDTH    0x3U
58095 #define V_AEC3_TX_WIDTH(x) ((x) << S_AEC3_TX_WIDTH)
58096 #define G_AEC3_TX_WIDTH(x) (((x) >> S_AEC3_TX_WIDTH) & M_AEC3_TX_WIDTH)
58097 
58098 #define S_AEC2_TX_WIDTH    4
58099 #define M_AEC2_TX_WIDTH    0x3U
58100 #define V_AEC2_TX_WIDTH(x) ((x) << S_AEC2_TX_WIDTH)
58101 #define G_AEC2_TX_WIDTH(x) (((x) >> S_AEC2_TX_WIDTH) & M_AEC2_TX_WIDTH)
58102 
58103 #define S_AEC1_TX_WIDTH    2
58104 #define M_AEC1_TX_WIDTH    0x3U
58105 #define V_AEC1_TX_WIDTH(x) ((x) << S_AEC1_TX_WIDTH)
58106 #define G_AEC1_TX_WIDTH(x) (((x) >> S_AEC1_TX_WIDTH) & M_AEC1_TX_WIDTH)
58107 
58108 #define S_AEC0_TX_WIDTH    0
58109 #define M_AEC0_TX_WIDTH    0x3U
58110 #define V_AEC0_TX_WIDTH(x) ((x) << S_AEC0_TX_WIDTH)
58111 #define G_AEC0_TX_WIDTH(x) (((x) >> S_AEC0_TX_WIDTH) & M_AEC0_TX_WIDTH)
58112 
58113 #define A_MAC_PORT_MAGIC_MACID_LO 0x824
58114 #define A_MAC_PORT_MAGIC_MACID_HI 0x828
58115 #define A_MAC_PORT_MTIP_RESET_CTRL 0x82c
58116 
58117 #define S_AN_RESET_SD_TX_CLK    31
58118 #define V_AN_RESET_SD_TX_CLK(x) ((x) << S_AN_RESET_SD_TX_CLK)
58119 #define F_AN_RESET_SD_TX_CLK    V_AN_RESET_SD_TX_CLK(1U)
58120 
58121 #define S_AN_RESET_SD_RX_CLK    30
58122 #define V_AN_RESET_SD_RX_CLK(x) ((x) << S_AN_RESET_SD_RX_CLK)
58123 #define F_AN_RESET_SD_RX_CLK    V_AN_RESET_SD_RX_CLK(1U)
58124 
58125 #define S_SGMII_RESET_TX_CLK    29
58126 #define V_SGMII_RESET_TX_CLK(x) ((x) << S_SGMII_RESET_TX_CLK)
58127 #define F_SGMII_RESET_TX_CLK    V_SGMII_RESET_TX_CLK(1U)
58128 
58129 #define S_SGMII_RESET_RX_CLK    28
58130 #define V_SGMII_RESET_RX_CLK(x) ((x) << S_SGMII_RESET_RX_CLK)
58131 #define F_SGMII_RESET_RX_CLK    V_SGMII_RESET_RX_CLK(1U)
58132 
58133 #define S_SGMII_RESET_REF_CLK    27
58134 #define V_SGMII_RESET_REF_CLK(x) ((x) << S_SGMII_RESET_REF_CLK)
58135 #define F_SGMII_RESET_REF_CLK    V_SGMII_RESET_REF_CLK(1U)
58136 
58137 #define S_PCS10G_RESET_XFI_RXCLK    26
58138 #define V_PCS10G_RESET_XFI_RXCLK(x) ((x) << S_PCS10G_RESET_XFI_RXCLK)
58139 #define F_PCS10G_RESET_XFI_RXCLK    V_PCS10G_RESET_XFI_RXCLK(1U)
58140 
58141 #define S_PCS10G_RESET_XFI_TXCLK    25
58142 #define V_PCS10G_RESET_XFI_TXCLK(x) ((x) << S_PCS10G_RESET_XFI_TXCLK)
58143 #define F_PCS10G_RESET_XFI_TXCLK    V_PCS10G_RESET_XFI_TXCLK(1U)
58144 
58145 #define S_PCS10G_RESET_SD_TX_CLK    24
58146 #define V_PCS10G_RESET_SD_TX_CLK(x) ((x) << S_PCS10G_RESET_SD_TX_CLK)
58147 #define F_PCS10G_RESET_SD_TX_CLK    V_PCS10G_RESET_SD_TX_CLK(1U)
58148 
58149 #define S_PCS10G_RESET_SD_RX_CLK    23
58150 #define V_PCS10G_RESET_SD_RX_CLK(x) ((x) << S_PCS10G_RESET_SD_RX_CLK)
58151 #define F_PCS10G_RESET_SD_RX_CLK    V_PCS10G_RESET_SD_RX_CLK(1U)
58152 
58153 #define S_PCS40G_RESET_RXCLK    22
58154 #define V_PCS40G_RESET_RXCLK(x) ((x) << S_PCS40G_RESET_RXCLK)
58155 #define F_PCS40G_RESET_RXCLK    V_PCS40G_RESET_RXCLK(1U)
58156 
58157 #define S_PCS40G_RESET_SD_TX_CLK    21
58158 #define V_PCS40G_RESET_SD_TX_CLK(x) ((x) << S_PCS40G_RESET_SD_TX_CLK)
58159 #define F_PCS40G_RESET_SD_TX_CLK    V_PCS40G_RESET_SD_TX_CLK(1U)
58160 
58161 #define S_PCS40G_RESET_SD0_RX_CLK    20
58162 #define V_PCS40G_RESET_SD0_RX_CLK(x) ((x) << S_PCS40G_RESET_SD0_RX_CLK)
58163 #define F_PCS40G_RESET_SD0_RX_CLK    V_PCS40G_RESET_SD0_RX_CLK(1U)
58164 
58165 #define S_PCS40G_RESET_SD1_RX_CLK    19
58166 #define V_PCS40G_RESET_SD1_RX_CLK(x) ((x) << S_PCS40G_RESET_SD1_RX_CLK)
58167 #define F_PCS40G_RESET_SD1_RX_CLK    V_PCS40G_RESET_SD1_RX_CLK(1U)
58168 
58169 #define S_PCS40G_RESET_SD2_RX_CLK    18
58170 #define V_PCS40G_RESET_SD2_RX_CLK(x) ((x) << S_PCS40G_RESET_SD2_RX_CLK)
58171 #define F_PCS40G_RESET_SD2_RX_CLK    V_PCS40G_RESET_SD2_RX_CLK(1U)
58172 
58173 #define S_PCS40G_RESET_SD3_RX_CLK    17
58174 #define V_PCS40G_RESET_SD3_RX_CLK(x) ((x) << S_PCS40G_RESET_SD3_RX_CLK)
58175 #define F_PCS40G_RESET_SD3_RX_CLK    V_PCS40G_RESET_SD3_RX_CLK(1U)
58176 
58177 #define S_PCS100G_RESET_CGMII_RXCLK    16
58178 #define V_PCS100G_RESET_CGMII_RXCLK(x) ((x) << S_PCS100G_RESET_CGMII_RXCLK)
58179 #define F_PCS100G_RESET_CGMII_RXCLK    V_PCS100G_RESET_CGMII_RXCLK(1U)
58180 
58181 #define S_PCS100G_RESET_CGMII_TXCLK    15
58182 #define V_PCS100G_RESET_CGMII_TXCLK(x) ((x) << S_PCS100G_RESET_CGMII_TXCLK)
58183 #define F_PCS100G_RESET_CGMII_TXCLK    V_PCS100G_RESET_CGMII_TXCLK(1U)
58184 
58185 #define S_PCS100G_RESET_TX_CLK    14
58186 #define V_PCS100G_RESET_TX_CLK(x) ((x) << S_PCS100G_RESET_TX_CLK)
58187 #define F_PCS100G_RESET_TX_CLK    V_PCS100G_RESET_TX_CLK(1U)
58188 
58189 #define S_PCS100G_RESET_SD0_RX_CLK    13
58190 #define V_PCS100G_RESET_SD0_RX_CLK(x) ((x) << S_PCS100G_RESET_SD0_RX_CLK)
58191 #define F_PCS100G_RESET_SD0_RX_CLK    V_PCS100G_RESET_SD0_RX_CLK(1U)
58192 
58193 #define S_PCS100G_RESET_SD1_RX_CLK    12
58194 #define V_PCS100G_RESET_SD1_RX_CLK(x) ((x) << S_PCS100G_RESET_SD1_RX_CLK)
58195 #define F_PCS100G_RESET_SD1_RX_CLK    V_PCS100G_RESET_SD1_RX_CLK(1U)
58196 
58197 #define S_PCS100G_RESET_SD2_RX_CLK    11
58198 #define V_PCS100G_RESET_SD2_RX_CLK(x) ((x) << S_PCS100G_RESET_SD2_RX_CLK)
58199 #define F_PCS100G_RESET_SD2_RX_CLK    V_PCS100G_RESET_SD2_RX_CLK(1U)
58200 
58201 #define S_PCS100G_RESET_SD3_RX_CLK    10
58202 #define V_PCS100G_RESET_SD3_RX_CLK(x) ((x) << S_PCS100G_RESET_SD3_RX_CLK)
58203 #define F_PCS100G_RESET_SD3_RX_CLK    V_PCS100G_RESET_SD3_RX_CLK(1U)
58204 
58205 #define S_MAC40G100G_RESET_TXCLK    9
58206 #define V_MAC40G100G_RESET_TXCLK(x) ((x) << S_MAC40G100G_RESET_TXCLK)
58207 #define F_MAC40G100G_RESET_TXCLK    V_MAC40G100G_RESET_TXCLK(1U)
58208 
58209 #define S_MAC40G100G_RESET_RXCLK    8
58210 #define V_MAC40G100G_RESET_RXCLK(x) ((x) << S_MAC40G100G_RESET_RXCLK)
58211 #define F_MAC40G100G_RESET_RXCLK    V_MAC40G100G_RESET_RXCLK(1U)
58212 
58213 #define S_MAC40G100G_RESET_FF_TX_CLK    7
58214 #define V_MAC40G100G_RESET_FF_TX_CLK(x) ((x) << S_MAC40G100G_RESET_FF_TX_CLK)
58215 #define F_MAC40G100G_RESET_FF_TX_CLK    V_MAC40G100G_RESET_FF_TX_CLK(1U)
58216 
58217 #define S_MAC40G100G_RESET_FF_RX_CLK    6
58218 #define V_MAC40G100G_RESET_FF_RX_CLK(x) ((x) << S_MAC40G100G_RESET_FF_RX_CLK)
58219 #define F_MAC40G100G_RESET_FF_RX_CLK    V_MAC40G100G_RESET_FF_RX_CLK(1U)
58220 
58221 #define S_MAC40G100G_RESET_TS_CLK    5
58222 #define V_MAC40G100G_RESET_TS_CLK(x) ((x) << S_MAC40G100G_RESET_TS_CLK)
58223 #define F_MAC40G100G_RESET_TS_CLK    V_MAC40G100G_RESET_TS_CLK(1U)
58224 
58225 #define S_MAC1G10G_RESET_RXCLK    4
58226 #define V_MAC1G10G_RESET_RXCLK(x) ((x) << S_MAC1G10G_RESET_RXCLK)
58227 #define F_MAC1G10G_RESET_RXCLK    V_MAC1G10G_RESET_RXCLK(1U)
58228 
58229 #define S_MAC1G10G_RESET_TXCLK    3
58230 #define V_MAC1G10G_RESET_TXCLK(x) ((x) << S_MAC1G10G_RESET_TXCLK)
58231 #define F_MAC1G10G_RESET_TXCLK    V_MAC1G10G_RESET_TXCLK(1U)
58232 
58233 #define S_MAC1G10G_RESET_FF_RX_CLK    2
58234 #define V_MAC1G10G_RESET_FF_RX_CLK(x) ((x) << S_MAC1G10G_RESET_FF_RX_CLK)
58235 #define F_MAC1G10G_RESET_FF_RX_CLK    V_MAC1G10G_RESET_FF_RX_CLK(1U)
58236 
58237 #define S_MAC1G10G_RESET_FF_TX_CLK    1
58238 #define V_MAC1G10G_RESET_FF_TX_CLK(x) ((x) << S_MAC1G10G_RESET_FF_TX_CLK)
58239 #define F_MAC1G10G_RESET_FF_TX_CLK    V_MAC1G10G_RESET_FF_TX_CLK(1U)
58240 
58241 #define S_XGMII_CLK_RESET    0
58242 #define V_XGMII_CLK_RESET(x) ((x) << S_XGMII_CLK_RESET)
58243 #define F_XGMII_CLK_RESET    V_XGMII_CLK_RESET(1U)
58244 
58245 #define A_MAC_PORT_MTIP_GATE_CTRL 0x830
58246 
58247 #define S_AN_GATE_SD_TX_CLK    31
58248 #define V_AN_GATE_SD_TX_CLK(x) ((x) << S_AN_GATE_SD_TX_CLK)
58249 #define F_AN_GATE_SD_TX_CLK    V_AN_GATE_SD_TX_CLK(1U)
58250 
58251 #define S_AN_GATE_SD_RX_CLK    30
58252 #define V_AN_GATE_SD_RX_CLK(x) ((x) << S_AN_GATE_SD_RX_CLK)
58253 #define F_AN_GATE_SD_RX_CLK    V_AN_GATE_SD_RX_CLK(1U)
58254 
58255 #define S_SGMII_GATE_TX_CLK    29
58256 #define V_SGMII_GATE_TX_CLK(x) ((x) << S_SGMII_GATE_TX_CLK)
58257 #define F_SGMII_GATE_TX_CLK    V_SGMII_GATE_TX_CLK(1U)
58258 
58259 #define S_SGMII_GATE_RX_CLK    28
58260 #define V_SGMII_GATE_RX_CLK(x) ((x) << S_SGMII_GATE_RX_CLK)
58261 #define F_SGMII_GATE_RX_CLK    V_SGMII_GATE_RX_CLK(1U)
58262 
58263 #define S_SGMII_GATE_REF_CLK    27
58264 #define V_SGMII_GATE_REF_CLK(x) ((x) << S_SGMII_GATE_REF_CLK)
58265 #define F_SGMII_GATE_REF_CLK    V_SGMII_GATE_REF_CLK(1U)
58266 
58267 #define S_PCS10G_GATE_XFI_RXCLK    26
58268 #define V_PCS10G_GATE_XFI_RXCLK(x) ((x) << S_PCS10G_GATE_XFI_RXCLK)
58269 #define F_PCS10G_GATE_XFI_RXCLK    V_PCS10G_GATE_XFI_RXCLK(1U)
58270 
58271 #define S_PCS10G_GATE_XFI_TXCLK    25
58272 #define V_PCS10G_GATE_XFI_TXCLK(x) ((x) << S_PCS10G_GATE_XFI_TXCLK)
58273 #define F_PCS10G_GATE_XFI_TXCLK    V_PCS10G_GATE_XFI_TXCLK(1U)
58274 
58275 #define S_PCS10G_GATE_SD_TX_CLK    24
58276 #define V_PCS10G_GATE_SD_TX_CLK(x) ((x) << S_PCS10G_GATE_SD_TX_CLK)
58277 #define F_PCS10G_GATE_SD_TX_CLK    V_PCS10G_GATE_SD_TX_CLK(1U)
58278 
58279 #define S_PCS10G_GATE_SD_RX_CLK    23
58280 #define V_PCS10G_GATE_SD_RX_CLK(x) ((x) << S_PCS10G_GATE_SD_RX_CLK)
58281 #define F_PCS10G_GATE_SD_RX_CLK    V_PCS10G_GATE_SD_RX_CLK(1U)
58282 
58283 #define S_PCS40G_GATE_RXCLK    22
58284 #define V_PCS40G_GATE_RXCLK(x) ((x) << S_PCS40G_GATE_RXCLK)
58285 #define F_PCS40G_GATE_RXCLK    V_PCS40G_GATE_RXCLK(1U)
58286 
58287 #define S_PCS40G_GATE_SD_TX_CLK    21
58288 #define V_PCS40G_GATE_SD_TX_CLK(x) ((x) << S_PCS40G_GATE_SD_TX_CLK)
58289 #define F_PCS40G_GATE_SD_TX_CLK    V_PCS40G_GATE_SD_TX_CLK(1U)
58290 
58291 #define S_PCS40G_GATE_SD_RX_CLK    20
58292 #define V_PCS40G_GATE_SD_RX_CLK(x) ((x) << S_PCS40G_GATE_SD_RX_CLK)
58293 #define F_PCS40G_GATE_SD_RX_CLK    V_PCS40G_GATE_SD_RX_CLK(1U)
58294 
58295 #define S_PCS100G_GATE_CGMII_RXCLK    19
58296 #define V_PCS100G_GATE_CGMII_RXCLK(x) ((x) << S_PCS100G_GATE_CGMII_RXCLK)
58297 #define F_PCS100G_GATE_CGMII_RXCLK    V_PCS100G_GATE_CGMII_RXCLK(1U)
58298 
58299 #define S_PCS100G_GATE_CGMII_TXCLK    18
58300 #define V_PCS100G_GATE_CGMII_TXCLK(x) ((x) << S_PCS100G_GATE_CGMII_TXCLK)
58301 #define F_PCS100G_GATE_CGMII_TXCLK    V_PCS100G_GATE_CGMII_TXCLK(1U)
58302 
58303 #define S_PCS100G_GATE_TX_CLK    17
58304 #define V_PCS100G_GATE_TX_CLK(x) ((x) << S_PCS100G_GATE_TX_CLK)
58305 #define F_PCS100G_GATE_TX_CLK    V_PCS100G_GATE_TX_CLK(1U)
58306 
58307 #define S_PCS100G_GATE_SD_RX_CLK    16
58308 #define V_PCS100G_GATE_SD_RX_CLK(x) ((x) << S_PCS100G_GATE_SD_RX_CLK)
58309 #define F_PCS100G_GATE_SD_RX_CLK    V_PCS100G_GATE_SD_RX_CLK(1U)
58310 
58311 #define S_MAC40G100G_GATE_TXCLK    15
58312 #define V_MAC40G100G_GATE_TXCLK(x) ((x) << S_MAC40G100G_GATE_TXCLK)
58313 #define F_MAC40G100G_GATE_TXCLK    V_MAC40G100G_GATE_TXCLK(1U)
58314 
58315 #define S_MAC40G100G_GATE_RXCLK    14
58316 #define V_MAC40G100G_GATE_RXCLK(x) ((x) << S_MAC40G100G_GATE_RXCLK)
58317 #define F_MAC40G100G_GATE_RXCLK    V_MAC40G100G_GATE_RXCLK(1U)
58318 
58319 #define S_MAC40G100G_GATE_FF_TX_CLK    13
58320 #define V_MAC40G100G_GATE_FF_TX_CLK(x) ((x) << S_MAC40G100G_GATE_FF_TX_CLK)
58321 #define F_MAC40G100G_GATE_FF_TX_CLK    V_MAC40G100G_GATE_FF_TX_CLK(1U)
58322 
58323 #define S_MAC40G100G_GATE_FF_RX_CLK    12
58324 #define V_MAC40G100G_GATE_FF_RX_CLK(x) ((x) << S_MAC40G100G_GATE_FF_RX_CLK)
58325 #define F_MAC40G100G_GATE_FF_RX_CLK    V_MAC40G100G_GATE_FF_RX_CLK(1U)
58326 
58327 #define S_MAC40G100G_TS_CLK    11
58328 #define V_MAC40G100G_TS_CLK(x) ((x) << S_MAC40G100G_TS_CLK)
58329 #define F_MAC40G100G_TS_CLK    V_MAC40G100G_TS_CLK(1U)
58330 
58331 #define S_MAC1G10G_GATE_RXCLK    10
58332 #define V_MAC1G10G_GATE_RXCLK(x) ((x) << S_MAC1G10G_GATE_RXCLK)
58333 #define F_MAC1G10G_GATE_RXCLK    V_MAC1G10G_GATE_RXCLK(1U)
58334 
58335 #define S_MAC1G10G_GATE_TXCLK    9
58336 #define V_MAC1G10G_GATE_TXCLK(x) ((x) << S_MAC1G10G_GATE_TXCLK)
58337 #define F_MAC1G10G_GATE_TXCLK    V_MAC1G10G_GATE_TXCLK(1U)
58338 
58339 #define S_MAC1G10G_GATE_FF_RX_CLK    8
58340 #define V_MAC1G10G_GATE_FF_RX_CLK(x) ((x) << S_MAC1G10G_GATE_FF_RX_CLK)
58341 #define F_MAC1G10G_GATE_FF_RX_CLK    V_MAC1G10G_GATE_FF_RX_CLK(1U)
58342 
58343 #define S_MAC1G10G_GATE_FF_TX_CLK    7
58344 #define V_MAC1G10G_GATE_FF_TX_CLK(x) ((x) << S_MAC1G10G_GATE_FF_TX_CLK)
58345 #define F_MAC1G10G_GATE_FF_TX_CLK    V_MAC1G10G_GATE_FF_TX_CLK(1U)
58346 
58347 #define S_AEC_RX    6
58348 #define V_AEC_RX(x) ((x) << S_AEC_RX)
58349 #define F_AEC_RX    V_AEC_RX(1U)
58350 
58351 #define S_AEC_TX    5
58352 #define V_AEC_TX(x) ((x) << S_AEC_TX)
58353 #define F_AEC_TX    V_AEC_TX(1U)
58354 
58355 #define S_PCS100G_CLK_ENABLE    4
58356 #define V_PCS100G_CLK_ENABLE(x) ((x) << S_PCS100G_CLK_ENABLE)
58357 #define F_PCS100G_CLK_ENABLE    V_PCS100G_CLK_ENABLE(1U)
58358 
58359 #define S_PCS40G_CLK_ENABLE    3
58360 #define V_PCS40G_CLK_ENABLE(x) ((x) << S_PCS40G_CLK_ENABLE)
58361 #define F_PCS40G_CLK_ENABLE    V_PCS40G_CLK_ENABLE(1U)
58362 
58363 #define S_PCS10G_CLK_ENABLE    2
58364 #define V_PCS10G_CLK_ENABLE(x) ((x) << S_PCS10G_CLK_ENABLE)
58365 #define F_PCS10G_CLK_ENABLE    V_PCS10G_CLK_ENABLE(1U)
58366 
58367 #define S_PCS1G_CLK_ENABLE    1
58368 #define V_PCS1G_CLK_ENABLE(x) ((x) << S_PCS1G_CLK_ENABLE)
58369 #define F_PCS1G_CLK_ENABLE    V_PCS1G_CLK_ENABLE(1U)
58370 
58371 #define S_AN_CLK_ENABLE    0
58372 #define V_AN_CLK_ENABLE(x) ((x) << S_AN_CLK_ENABLE)
58373 #define F_AN_CLK_ENABLE    V_AN_CLK_ENABLE(1U)
58374 
58375 #define A_MAC_PORT_LINK_STATUS 0x834
58376 
58377 #define S_AN_DONE    6
58378 #define V_AN_DONE(x) ((x) << S_AN_DONE)
58379 #define F_AN_DONE    V_AN_DONE(1U)
58380 
58381 #define S_ALIGN_DONE    5
58382 #define V_ALIGN_DONE(x) ((x) << S_ALIGN_DONE)
58383 #define F_ALIGN_DONE    V_ALIGN_DONE(1U)
58384 
58385 #define S_BLOCK_LOCK    4
58386 #define V_BLOCK_LOCK(x) ((x) << S_BLOCK_LOCK)
58387 #define F_BLOCK_LOCK    V_BLOCK_LOCK(1U)
58388 
58389 #define S_HI_BER_ST    7
58390 #define V_HI_BER_ST(x) ((x) << S_HI_BER_ST)
58391 #define F_HI_BER_ST    V_HI_BER_ST(1U)
58392 
58393 #define S_AN_DONE_ST    6
58394 #define V_AN_DONE_ST(x) ((x) << S_AN_DONE_ST)
58395 #define F_AN_DONE_ST    V_AN_DONE_ST(1U)
58396 
58397 #define A_MAC_PORT_AEC_ADD_CTL_STAT_0 0x838
58398 
58399 #define S_AEC_SYS_LANE_TYPE_3    11
58400 #define V_AEC_SYS_LANE_TYPE_3(x) ((x) << S_AEC_SYS_LANE_TYPE_3)
58401 #define F_AEC_SYS_LANE_TYPE_3    V_AEC_SYS_LANE_TYPE_3(1U)
58402 
58403 #define S_AEC_SYS_LANE_TYPE_2    10
58404 #define V_AEC_SYS_LANE_TYPE_2(x) ((x) << S_AEC_SYS_LANE_TYPE_2)
58405 #define F_AEC_SYS_LANE_TYPE_2    V_AEC_SYS_LANE_TYPE_2(1U)
58406 
58407 #define S_AEC_SYS_LANE_TYPE_1    9
58408 #define V_AEC_SYS_LANE_TYPE_1(x) ((x) << S_AEC_SYS_LANE_TYPE_1)
58409 #define F_AEC_SYS_LANE_TYPE_1    V_AEC_SYS_LANE_TYPE_1(1U)
58410 
58411 #define S_AEC_SYS_LANE_TYPE_0    8
58412 #define V_AEC_SYS_LANE_TYPE_0(x) ((x) << S_AEC_SYS_LANE_TYPE_0)
58413 #define F_AEC_SYS_LANE_TYPE_0    V_AEC_SYS_LANE_TYPE_0(1U)
58414 
58415 #define S_AEC_SYS_LANE_SELECT_3    6
58416 #define M_AEC_SYS_LANE_SELECT_3    0x3U
58417 #define V_AEC_SYS_LANE_SELECT_3(x) ((x) << S_AEC_SYS_LANE_SELECT_3)
58418 #define G_AEC_SYS_LANE_SELECT_3(x) (((x) >> S_AEC_SYS_LANE_SELECT_3) & M_AEC_SYS_LANE_SELECT_3)
58419 
58420 #define S_AEC_SYS_LANE_SELECT_2    4
58421 #define M_AEC_SYS_LANE_SELECT_2    0x3U
58422 #define V_AEC_SYS_LANE_SELECT_2(x) ((x) << S_AEC_SYS_LANE_SELECT_2)
58423 #define G_AEC_SYS_LANE_SELECT_2(x) (((x) >> S_AEC_SYS_LANE_SELECT_2) & M_AEC_SYS_LANE_SELECT_2)
58424 
58425 #define S_AEC_SYS_LANE_SELECT_1    2
58426 #define M_AEC_SYS_LANE_SELECT_1    0x3U
58427 #define V_AEC_SYS_LANE_SELECT_1(x) ((x) << S_AEC_SYS_LANE_SELECT_1)
58428 #define G_AEC_SYS_LANE_SELECT_1(x) (((x) >> S_AEC_SYS_LANE_SELECT_1) & M_AEC_SYS_LANE_SELECT_1)
58429 
58430 #define S_AEC_SYS_LANE_SELECT_O    0
58431 #define M_AEC_SYS_LANE_SELECT_O    0x3U
58432 #define V_AEC_SYS_LANE_SELECT_O(x) ((x) << S_AEC_SYS_LANE_SELECT_O)
58433 #define G_AEC_SYS_LANE_SELECT_O(x) (((x) >> S_AEC_SYS_LANE_SELECT_O) & M_AEC_SYS_LANE_SELECT_O)
58434 
58435 #define A_MAC_PORT_AEC_ADD_CTL_STAT_1 0x83c
58436 
58437 #define S_AEC_RX_UNKNOWN_LANE_3    11
58438 #define V_AEC_RX_UNKNOWN_LANE_3(x) ((x) << S_AEC_RX_UNKNOWN_LANE_3)
58439 #define F_AEC_RX_UNKNOWN_LANE_3    V_AEC_RX_UNKNOWN_LANE_3(1U)
58440 
58441 #define S_AEC_RX_UNKNOWN_LANE_2    10
58442 #define V_AEC_RX_UNKNOWN_LANE_2(x) ((x) << S_AEC_RX_UNKNOWN_LANE_2)
58443 #define F_AEC_RX_UNKNOWN_LANE_2    V_AEC_RX_UNKNOWN_LANE_2(1U)
58444 
58445 #define S_AEC_RX_UNKNOWN_LANE_1    9
58446 #define V_AEC_RX_UNKNOWN_LANE_1(x) ((x) << S_AEC_RX_UNKNOWN_LANE_1)
58447 #define F_AEC_RX_UNKNOWN_LANE_1    V_AEC_RX_UNKNOWN_LANE_1(1U)
58448 
58449 #define S_AEC_RX_UNKNOWN_LANE_0    8
58450 #define V_AEC_RX_UNKNOWN_LANE_0(x) ((x) << S_AEC_RX_UNKNOWN_LANE_0)
58451 #define F_AEC_RX_UNKNOWN_LANE_0    V_AEC_RX_UNKNOWN_LANE_0(1U)
58452 
58453 #define S_AEC_RX_LANE_ID_3    6
58454 #define M_AEC_RX_LANE_ID_3    0x3U
58455 #define V_AEC_RX_LANE_ID_3(x) ((x) << S_AEC_RX_LANE_ID_3)
58456 #define G_AEC_RX_LANE_ID_3(x) (((x) >> S_AEC_RX_LANE_ID_3) & M_AEC_RX_LANE_ID_3)
58457 
58458 #define S_AEC_RX_LANE_ID_2    4
58459 #define M_AEC_RX_LANE_ID_2    0x3U
58460 #define V_AEC_RX_LANE_ID_2(x) ((x) << S_AEC_RX_LANE_ID_2)
58461 #define G_AEC_RX_LANE_ID_2(x) (((x) >> S_AEC_RX_LANE_ID_2) & M_AEC_RX_LANE_ID_2)
58462 
58463 #define S_AEC_RX_LANE_ID_1    2
58464 #define M_AEC_RX_LANE_ID_1    0x3U
58465 #define V_AEC_RX_LANE_ID_1(x) ((x) << S_AEC_RX_LANE_ID_1)
58466 #define G_AEC_RX_LANE_ID_1(x) (((x) >> S_AEC_RX_LANE_ID_1) & M_AEC_RX_LANE_ID_1)
58467 
58468 #define S_AEC_RX_LANE_ID_O    0
58469 #define M_AEC_RX_LANE_ID_O    0x3U
58470 #define V_AEC_RX_LANE_ID_O(x) ((x) << S_AEC_RX_LANE_ID_O)
58471 #define G_AEC_RX_LANE_ID_O(x) (((x) >> S_AEC_RX_LANE_ID_O) & M_AEC_RX_LANE_ID_O)
58472 
58473 #define A_MAC_PORT_AEC_XGMII_TIMER_LO_40G 0x840
58474 
58475 #define S_XGMII_CLK_IN_1MS_LO_40G    0
58476 #define M_XGMII_CLK_IN_1MS_LO_40G    0xffffU
58477 #define V_XGMII_CLK_IN_1MS_LO_40G(x) ((x) << S_XGMII_CLK_IN_1MS_LO_40G)
58478 #define G_XGMII_CLK_IN_1MS_LO_40G(x) (((x) >> S_XGMII_CLK_IN_1MS_LO_40G) & M_XGMII_CLK_IN_1MS_LO_40G)
58479 
58480 #define A_MAC_PORT_AEC_XGMII_TIMER_HI_40G 0x844
58481 
58482 #define S_XGMII_CLK_IN_1MS_HI_40G    0
58483 #define M_XGMII_CLK_IN_1MS_HI_40G    0xfU
58484 #define V_XGMII_CLK_IN_1MS_HI_40G(x) ((x) << S_XGMII_CLK_IN_1MS_HI_40G)
58485 #define G_XGMII_CLK_IN_1MS_HI_40G(x) (((x) >> S_XGMII_CLK_IN_1MS_HI_40G) & M_XGMII_CLK_IN_1MS_HI_40G)
58486 
58487 #define A_MAC_PORT_AEC_XGMII_TIMER_LO_100G 0x848
58488 
58489 #define S_XGMII_CLK_IN_1MS_LO_100G    0
58490 #define M_XGMII_CLK_IN_1MS_LO_100G    0xffffU
58491 #define V_XGMII_CLK_IN_1MS_LO_100G(x) ((x) << S_XGMII_CLK_IN_1MS_LO_100G)
58492 #define G_XGMII_CLK_IN_1MS_LO_100G(x) (((x) >> S_XGMII_CLK_IN_1MS_LO_100G) & M_XGMII_CLK_IN_1MS_LO_100G)
58493 
58494 #define A_MAC_PORT_AEC_XGMII_TIMER_HI_100G 0x84c
58495 
58496 #define S_XGMII_CLK_IN_1MS_HI_100G    0
58497 #define M_XGMII_CLK_IN_1MS_HI_100G    0xfU
58498 #define V_XGMII_CLK_IN_1MS_HI_100G(x) ((x) << S_XGMII_CLK_IN_1MS_HI_100G)
58499 #define G_XGMII_CLK_IN_1MS_HI_100G(x) (((x) >> S_XGMII_CLK_IN_1MS_HI_100G) & M_XGMII_CLK_IN_1MS_HI_100G)
58500 
58501 #define A_MAC_PORT_AEC_DEBUG_LO_0 0x850
58502 
58503 #define S_CTL_FSM_CUR_STATE    28
58504 #define M_CTL_FSM_CUR_STATE    0x7U
58505 #define V_CTL_FSM_CUR_STATE(x) ((x) << S_CTL_FSM_CUR_STATE)
58506 #define G_CTL_FSM_CUR_STATE(x) (((x) >> S_CTL_FSM_CUR_STATE) & M_CTL_FSM_CUR_STATE)
58507 
58508 #define S_CIN_FSM_CUR_STATE    26
58509 #define M_CIN_FSM_CUR_STATE    0x3U
58510 #define V_CIN_FSM_CUR_STATE(x) ((x) << S_CIN_FSM_CUR_STATE)
58511 #define G_CIN_FSM_CUR_STATE(x) (((x) >> S_CIN_FSM_CUR_STATE) & M_CIN_FSM_CUR_STATE)
58512 
58513 #define S_CRI_FSM_CUR_STATE    23
58514 #define M_CRI_FSM_CUR_STATE    0x7U
58515 #define V_CRI_FSM_CUR_STATE(x) ((x) << S_CRI_FSM_CUR_STATE)
58516 #define G_CRI_FSM_CUR_STATE(x) (((x) >> S_CRI_FSM_CUR_STATE) & M_CRI_FSM_CUR_STATE)
58517 
58518 #define S_CU_C3_ACK_VALUE    21
58519 #define M_CU_C3_ACK_VALUE    0x3U
58520 #define V_CU_C3_ACK_VALUE(x) ((x) << S_CU_C3_ACK_VALUE)
58521 #define G_CU_C3_ACK_VALUE(x) (((x) >> S_CU_C3_ACK_VALUE) & M_CU_C3_ACK_VALUE)
58522 
58523 #define S_CU_C2_ACK_VALUE    19
58524 #define M_CU_C2_ACK_VALUE    0x3U
58525 #define V_CU_C2_ACK_VALUE(x) ((x) << S_CU_C2_ACK_VALUE)
58526 #define G_CU_C2_ACK_VALUE(x) (((x) >> S_CU_C2_ACK_VALUE) & M_CU_C2_ACK_VALUE)
58527 
58528 #define S_CU_C1_ACK_VALUE    17
58529 #define M_CU_C1_ACK_VALUE    0x3U
58530 #define V_CU_C1_ACK_VALUE(x) ((x) << S_CU_C1_ACK_VALUE)
58531 #define G_CU_C1_ACK_VALUE(x) (((x) >> S_CU_C1_ACK_VALUE) & M_CU_C1_ACK_VALUE)
58532 
58533 #define S_CU_C0_ACK_VALUE    15
58534 #define M_CU_C0_ACK_VALUE    0x3U
58535 #define V_CU_C0_ACK_VALUE(x) ((x) << S_CU_C0_ACK_VALUE)
58536 #define G_CU_C0_ACK_VALUE(x) (((x) >> S_CU_C0_ACK_VALUE) & M_CU_C0_ACK_VALUE)
58537 
58538 #define S_CX_INIT    13
58539 #define V_CX_INIT(x) ((x) << S_CX_INIT)
58540 #define F_CX_INIT    V_CX_INIT(1U)
58541 
58542 #define S_CX_PRESET    12
58543 #define V_CX_PRESET(x) ((x) << S_CX_PRESET)
58544 #define F_CX_PRESET    V_CX_PRESET(1U)
58545 
58546 #define S_CUF_C3_UPDATE    9
58547 #define M_CUF_C3_UPDATE    0x3U
58548 #define V_CUF_C3_UPDATE(x) ((x) << S_CUF_C3_UPDATE)
58549 #define G_CUF_C3_UPDATE(x) (((x) >> S_CUF_C3_UPDATE) & M_CUF_C3_UPDATE)
58550 
58551 #define S_CUF_C2_UPDATE    7
58552 #define M_CUF_C2_UPDATE    0x3U
58553 #define V_CUF_C2_UPDATE(x) ((x) << S_CUF_C2_UPDATE)
58554 #define G_CUF_C2_UPDATE(x) (((x) >> S_CUF_C2_UPDATE) & M_CUF_C2_UPDATE)
58555 
58556 #define S_CUF_C1_UPDATE    5
58557 #define M_CUF_C1_UPDATE    0x3U
58558 #define V_CUF_C1_UPDATE(x) ((x) << S_CUF_C1_UPDATE)
58559 #define G_CUF_C1_UPDATE(x) (((x) >> S_CUF_C1_UPDATE) & M_CUF_C1_UPDATE)
58560 
58561 #define S_CUF_C0_UPDATE    3
58562 #define M_CUF_C0_UPDATE    0x3U
58563 #define V_CUF_C0_UPDATE(x) ((x) << S_CUF_C0_UPDATE)
58564 #define G_CUF_C0_UPDATE(x) (((x) >> S_CUF_C0_UPDATE) & M_CUF_C0_UPDATE)
58565 
58566 #define S_REG_FPH_ATTR_TXUPDAT_VALID    2
58567 #define V_REG_FPH_ATTR_TXUPDAT_VALID(x) ((x) << S_REG_FPH_ATTR_TXUPDAT_VALID)
58568 #define F_REG_FPH_ATTR_TXUPDAT_VALID    V_REG_FPH_ATTR_TXUPDAT_VALID(1U)
58569 
58570 #define S_REG_FPH_ATTR_TXSTAT_VALID    1
58571 #define V_REG_FPH_ATTR_TXSTAT_VALID(x) ((x) << S_REG_FPH_ATTR_TXSTAT_VALID)
58572 #define F_REG_FPH_ATTR_TXSTAT_VALID    V_REG_FPH_ATTR_TXSTAT_VALID(1U)
58573 
58574 #define S_REG_MAN_DEC_REQ    0
58575 #define V_REG_MAN_DEC_REQ(x) ((x) << S_REG_MAN_DEC_REQ)
58576 #define F_REG_MAN_DEC_REQ    V_REG_MAN_DEC_REQ(1U)
58577 
58578 #define A_MAC_PORT_AEC_DEBUG_HI_0 0x854
58579 
58580 #define S_FC_LSNA_    12
58581 #define V_FC_LSNA_(x) ((x) << S_FC_LSNA_)
58582 #define F_FC_LSNA_    V_FC_LSNA_(1U)
58583 
58584 #define S_CUF_C0_FSM_DEBUG    9
58585 #define M_CUF_C0_FSM_DEBUG    0x7U
58586 #define V_CUF_C0_FSM_DEBUG(x) ((x) << S_CUF_C0_FSM_DEBUG)
58587 #define G_CUF_C0_FSM_DEBUG(x) (((x) >> S_CUF_C0_FSM_DEBUG) & M_CUF_C0_FSM_DEBUG)
58588 
58589 #define S_CUF_C1_FSM_DEBUG    6
58590 #define M_CUF_C1_FSM_DEBUG    0x7U
58591 #define V_CUF_C1_FSM_DEBUG(x) ((x) << S_CUF_C1_FSM_DEBUG)
58592 #define G_CUF_C1_FSM_DEBUG(x) (((x) >> S_CUF_C1_FSM_DEBUG) & M_CUF_C1_FSM_DEBUG)
58593 
58594 #define S_CUF_C2_FSM_DEBUG    3
58595 #define M_CUF_C2_FSM_DEBUG    0x7U
58596 #define V_CUF_C2_FSM_DEBUG(x) ((x) << S_CUF_C2_FSM_DEBUG)
58597 #define G_CUF_C2_FSM_DEBUG(x) (((x) >> S_CUF_C2_FSM_DEBUG) & M_CUF_C2_FSM_DEBUG)
58598 
58599 #define S_LCK_FSM_CUR_STATE    0
58600 #define M_LCK_FSM_CUR_STATE    0x7U
58601 #define V_LCK_FSM_CUR_STATE(x) ((x) << S_LCK_FSM_CUR_STATE)
58602 #define G_LCK_FSM_CUR_STATE(x) (((x) >> S_LCK_FSM_CUR_STATE) & M_LCK_FSM_CUR_STATE)
58603 
58604 #define A_MAC_PORT_AEC_DEBUG_LO_1 0x858
58605 #define A_MAC_PORT_AEC_DEBUG_HI_1 0x85c
58606 #define A_MAC_PORT_AEC_DEBUG_LO_2 0x860
58607 #define A_MAC_PORT_AEC_DEBUG_HI_2 0x864
58608 #define A_MAC_PORT_AEC_DEBUG_LO_3 0x868
58609 #define A_MAC_PORT_AEC_DEBUG_HI_3 0x86c
58610 #define A_MAC_PORT_MAC_DEBUG_RO 0x870
58611 
58612 #define S_MAC40G100G_TX_UNDERFLOW    13
58613 #define V_MAC40G100G_TX_UNDERFLOW(x) ((x) << S_MAC40G100G_TX_UNDERFLOW)
58614 #define F_MAC40G100G_TX_UNDERFLOW    V_MAC40G100G_TX_UNDERFLOW(1U)
58615 
58616 #define S_MAC1G10G_MAGIC_IND    12
58617 #define V_MAC1G10G_MAGIC_IND(x) ((x) << S_MAC1G10G_MAGIC_IND)
58618 #define F_MAC1G10G_MAGIC_IND    V_MAC1G10G_MAGIC_IND(1U)
58619 
58620 #define S_MAC1G10G_FF_RX_EMPTY    11
58621 #define V_MAC1G10G_FF_RX_EMPTY(x) ((x) << S_MAC1G10G_FF_RX_EMPTY)
58622 #define F_MAC1G10G_FF_RX_EMPTY    V_MAC1G10G_FF_RX_EMPTY(1U)
58623 
58624 #define S_MAC1G10G_FF_TX_OVR_ERR    10
58625 #define V_MAC1G10G_FF_TX_OVR_ERR(x) ((x) << S_MAC1G10G_FF_TX_OVR_ERR)
58626 #define F_MAC1G10G_FF_TX_OVR_ERR    V_MAC1G10G_FF_TX_OVR_ERR(1U)
58627 
58628 #define S_MAC1G10G_IF_MODE_ENA    8
58629 #define M_MAC1G10G_IF_MODE_ENA    0x3U
58630 #define V_MAC1G10G_IF_MODE_ENA(x) ((x) << S_MAC1G10G_IF_MODE_ENA)
58631 #define G_MAC1G10G_IF_MODE_ENA(x) (((x) >> S_MAC1G10G_IF_MODE_ENA) & M_MAC1G10G_IF_MODE_ENA)
58632 
58633 #define S_MAC1G10G_MII_ENA_10    7
58634 #define V_MAC1G10G_MII_ENA_10(x) ((x) << S_MAC1G10G_MII_ENA_10)
58635 #define F_MAC1G10G_MII_ENA_10    V_MAC1G10G_MII_ENA_10(1U)
58636 
58637 #define S_MAC1G10G_PAUSE_ON    6
58638 #define V_MAC1G10G_PAUSE_ON(x) ((x) << S_MAC1G10G_PAUSE_ON)
58639 #define F_MAC1G10G_PAUSE_ON    V_MAC1G10G_PAUSE_ON(1U)
58640 
58641 #define S_MAC1G10G_PFC_MODE    5
58642 #define V_MAC1G10G_PFC_MODE(x) ((x) << S_MAC1G10G_PFC_MODE)
58643 #define F_MAC1G10G_PFC_MODE    V_MAC1G10G_PFC_MODE(1U)
58644 
58645 #define S_MAC1G10G_RX_SFD_O    4
58646 #define V_MAC1G10G_RX_SFD_O(x) ((x) << S_MAC1G10G_RX_SFD_O)
58647 #define F_MAC1G10G_RX_SFD_O    V_MAC1G10G_RX_SFD_O(1U)
58648 
58649 #define S_MAC1G10G_TX_EMPTY    3
58650 #define V_MAC1G10G_TX_EMPTY(x) ((x) << S_MAC1G10G_TX_EMPTY)
58651 #define F_MAC1G10G_TX_EMPTY    V_MAC1G10G_TX_EMPTY(1U)
58652 
58653 #define S_MAC1G10G_TX_SFD_O    2
58654 #define V_MAC1G10G_TX_SFD_O(x) ((x) << S_MAC1G10G_TX_SFD_O)
58655 #define F_MAC1G10G_TX_SFD_O    V_MAC1G10G_TX_SFD_O(1U)
58656 
58657 #define S_MAC1G10G_TX_TS_FRM_OUT    1
58658 #define V_MAC1G10G_TX_TS_FRM_OUT(x) ((x) << S_MAC1G10G_TX_TS_FRM_OUT)
58659 #define F_MAC1G10G_TX_TS_FRM_OUT    V_MAC1G10G_TX_TS_FRM_OUT(1U)
58660 
58661 #define S_MAC1G10G_TX_UNDERFLOW    0
58662 #define V_MAC1G10G_TX_UNDERFLOW(x) ((x) << S_MAC1G10G_TX_UNDERFLOW)
58663 #define F_MAC1G10G_TX_UNDERFLOW    V_MAC1G10G_TX_UNDERFLOW(1U)
58664 
58665 #define A_MAC_PORT_MAC_CTRL_RW 0x874
58666 
58667 #define S_MAC40G100G_FF_TX_PFC_XOFF    17
58668 #define M_MAC40G100G_FF_TX_PFC_XOFF    0xffU
58669 #define V_MAC40G100G_FF_TX_PFC_XOFF(x) ((x) << S_MAC40G100G_FF_TX_PFC_XOFF)
58670 #define G_MAC40G100G_FF_TX_PFC_XOFF(x) (((x) >> S_MAC40G100G_FF_TX_PFC_XOFF) & M_MAC40G100G_FF_TX_PFC_XOFF)
58671 
58672 #define S_MAC40G100G_TX_LOC_FAULT    16
58673 #define V_MAC40G100G_TX_LOC_FAULT(x) ((x) << S_MAC40G100G_TX_LOC_FAULT)
58674 #define F_MAC40G100G_TX_LOC_FAULT    V_MAC40G100G_TX_LOC_FAULT(1U)
58675 
58676 #define S_MAC40G100G_TX_REM_FAULT    15
58677 #define V_MAC40G100G_TX_REM_FAULT(x) ((x) << S_MAC40G100G_TX_REM_FAULT)
58678 #define F_MAC40G100G_TX_REM_FAULT    V_MAC40G100G_TX_REM_FAULT(1U)
58679 
58680 #define S_MAC40G_LOOP_BCK    14
58681 #define V_MAC40G_LOOP_BCK(x) ((x) << S_MAC40G_LOOP_BCK)
58682 #define F_MAC40G_LOOP_BCK    V_MAC40G_LOOP_BCK(1U)
58683 
58684 #define S_MAC1G10G_MAGIC_ENA    13
58685 #define V_MAC1G10G_MAGIC_ENA(x) ((x) << S_MAC1G10G_MAGIC_ENA)
58686 #define F_MAC1G10G_MAGIC_ENA    V_MAC1G10G_MAGIC_ENA(1U)
58687 
58688 #define S_MAC1G10G_IF_MODE_SET    11
58689 #define M_MAC1G10G_IF_MODE_SET    0x3U
58690 #define V_MAC1G10G_IF_MODE_SET(x) ((x) << S_MAC1G10G_IF_MODE_SET)
58691 #define G_MAC1G10G_IF_MODE_SET(x) (((x) >> S_MAC1G10G_IF_MODE_SET) & M_MAC1G10G_IF_MODE_SET)
58692 
58693 #define S_MAC1G10G_TX_LOC_FAULT    10
58694 #define V_MAC1G10G_TX_LOC_FAULT(x) ((x) << S_MAC1G10G_TX_LOC_FAULT)
58695 #define F_MAC1G10G_TX_LOC_FAULT    V_MAC1G10G_TX_LOC_FAULT(1U)
58696 
58697 #define S_MAC1G10G_TX_REM_FAULT    9
58698 #define V_MAC1G10G_TX_REM_FAULT(x) ((x) << S_MAC1G10G_TX_REM_FAULT)
58699 #define F_MAC1G10G_TX_REM_FAULT    V_MAC1G10G_TX_REM_FAULT(1U)
58700 
58701 #define S_MAC1G10G_XOFF_GEN    1
58702 #define M_MAC1G10G_XOFF_GEN    0xffU
58703 #define V_MAC1G10G_XOFF_GEN(x) ((x) << S_MAC1G10G_XOFF_GEN)
58704 #define G_MAC1G10G_XOFF_GEN(x) (((x) >> S_MAC1G10G_XOFF_GEN) & M_MAC1G10G_XOFF_GEN)
58705 
58706 #define S_MAC1G_LOOP_BCK    0
58707 #define V_MAC1G_LOOP_BCK(x) ((x) << S_MAC1G_LOOP_BCK)
58708 #define F_MAC1G_LOOP_BCK    V_MAC1G_LOOP_BCK(1U)
58709 
58710 #define A_MAC_PORT_PCS_DEBUG0_RO 0x878
58711 
58712 #define S_FPGA_LOCK    26
58713 #define M_FPGA_LOCK    0xfU
58714 #define V_FPGA_LOCK(x) ((x) << S_FPGA_LOCK)
58715 #define G_FPGA_LOCK(x) (((x) >> S_FPGA_LOCK) & M_FPGA_LOCK)
58716 
58717 #define S_T6_AN_DONE    25
58718 #define V_T6_AN_DONE(x) ((x) << S_T6_AN_DONE)
58719 #define F_T6_AN_DONE    V_T6_AN_DONE(1U)
58720 
58721 #define S_AN_INT    24
58722 #define V_AN_INT(x) ((x) << S_AN_INT)
58723 #define F_AN_INT    V_AN_INT(1U)
58724 
58725 #define S_AN_PCS_RX_CLK_ENA    23
58726 #define V_AN_PCS_RX_CLK_ENA(x) ((x) << S_AN_PCS_RX_CLK_ENA)
58727 #define F_AN_PCS_RX_CLK_ENA    V_AN_PCS_RX_CLK_ENA(1U)
58728 
58729 #define S_AN_PCS_TX_CLK_ENA    22
58730 #define V_AN_PCS_TX_CLK_ENA(x) ((x) << S_AN_PCS_TX_CLK_ENA)
58731 #define F_AN_PCS_TX_CLK_ENA    V_AN_PCS_TX_CLK_ENA(1U)
58732 
58733 #define S_AN_SELECT    17
58734 #define M_AN_SELECT    0x1fU
58735 #define V_AN_SELECT(x) ((x) << S_AN_SELECT)
58736 #define G_AN_SELECT(x) (((x) >> S_AN_SELECT) & M_AN_SELECT)
58737 
58738 #define S_AN_PROG    16
58739 #define V_AN_PROG(x) ((x) << S_AN_PROG)
58740 #define F_AN_PROG    V_AN_PROG(1U)
58741 
58742 #define S_PCS40G_BLOCK_LOCK    12
58743 #define M_PCS40G_BLOCK_LOCK    0xfU
58744 #define V_PCS40G_BLOCK_LOCK(x) ((x) << S_PCS40G_BLOCK_LOCK)
58745 #define G_PCS40G_BLOCK_LOCK(x) (((x) >> S_PCS40G_BLOCK_LOCK) & M_PCS40G_BLOCK_LOCK)
58746 
58747 #define S_PCS40G_BER_TIMER_DONE    11
58748 #define V_PCS40G_BER_TIMER_DONE(x) ((x) << S_PCS40G_BER_TIMER_DONE)
58749 #define F_PCS40G_BER_TIMER_DONE    V_PCS40G_BER_TIMER_DONE(1U)
58750 
58751 #define S_PCS10G_FEC_LOCKED    10
58752 #define V_PCS10G_FEC_LOCKED(x) ((x) << S_PCS10G_FEC_LOCKED)
58753 #define F_PCS10G_FEC_LOCKED    V_PCS10G_FEC_LOCKED(1U)
58754 
58755 #define S_PCS10G_BLOCK_LOCK    9
58756 #define V_PCS10G_BLOCK_LOCK(x) ((x) << S_PCS10G_BLOCK_LOCK)
58757 #define F_PCS10G_BLOCK_LOCK    V_PCS10G_BLOCK_LOCK(1U)
58758 
58759 #define S_SGMII_GMII_COL    8
58760 #define V_SGMII_GMII_COL(x) ((x) << S_SGMII_GMII_COL)
58761 #define F_SGMII_GMII_COL    V_SGMII_GMII_COL(1U)
58762 
58763 #define S_SGMII_GMII_CRS    7
58764 #define V_SGMII_GMII_CRS(x) ((x) << S_SGMII_GMII_CRS)
58765 #define F_SGMII_GMII_CRS    V_SGMII_GMII_CRS(1U)
58766 
58767 #define S_SGMII_SD_LOOPBACK    6
58768 #define V_SGMII_SD_LOOPBACK(x) ((x) << S_SGMII_SD_LOOPBACK)
58769 #define F_SGMII_SD_LOOPBACK    V_SGMII_SD_LOOPBACK(1U)
58770 
58771 #define S_SGMII_SG_AN_DONE    5
58772 #define V_SGMII_SG_AN_DONE(x) ((x) << S_SGMII_SG_AN_DONE)
58773 #define F_SGMII_SG_AN_DONE    V_SGMII_SG_AN_DONE(1U)
58774 
58775 #define S_SGMII_SG_HD    4
58776 #define V_SGMII_SG_HD(x) ((x) << S_SGMII_SG_HD)
58777 #define F_SGMII_SG_HD    V_SGMII_SG_HD(1U)
58778 
58779 #define S_SGMII_SG_PAGE_RX    3
58780 #define V_SGMII_SG_PAGE_RX(x) ((x) << S_SGMII_SG_PAGE_RX)
58781 #define F_SGMII_SG_PAGE_RX    V_SGMII_SG_PAGE_RX(1U)
58782 
58783 #define S_SGMII_SG_RX_SYNC    2
58784 #define V_SGMII_SG_RX_SYNC(x) ((x) << S_SGMII_SG_RX_SYNC)
58785 #define F_SGMII_SG_RX_SYNC    V_SGMII_SG_RX_SYNC(1U)
58786 
58787 #define S_SGMII_SG_SPEED    0
58788 #define M_SGMII_SG_SPEED    0x3U
58789 #define V_SGMII_SG_SPEED(x) ((x) << S_SGMII_SG_SPEED)
58790 #define G_SGMII_SG_SPEED(x) (((x) >> S_SGMII_SG_SPEED) & M_SGMII_SG_SPEED)
58791 
58792 #define A_MAC_PORT_PCS_CTRL_RW 0x87c
58793 
58794 #define S_TX_LI_FAULT    31
58795 #define V_TX_LI_FAULT(x) ((x) << S_TX_LI_FAULT)
58796 #define F_TX_LI_FAULT    V_TX_LI_FAULT(1U)
58797 
58798 #define S_T6_PAD    30
58799 #define V_T6_PAD(x) ((x) << S_T6_PAD)
58800 #define F_T6_PAD    V_T6_PAD(1U)
58801 
58802 #define S_BLK_STB_VAL    22
58803 #define M_BLK_STB_VAL    0xffU
58804 #define V_BLK_STB_VAL(x) ((x) << S_BLK_STB_VAL)
58805 #define G_BLK_STB_VAL(x) (((x) >> S_BLK_STB_VAL) & M_BLK_STB_VAL)
58806 
58807 #define S_DEBUG_SEL    18
58808 #define M_DEBUG_SEL    0xfU
58809 #define V_DEBUG_SEL(x) ((x) << S_DEBUG_SEL)
58810 #define G_DEBUG_SEL(x) (((x) >> S_DEBUG_SEL) & M_DEBUG_SEL)
58811 
58812 #define S_SGMII_LOOP    15
58813 #define M_SGMII_LOOP    0x7U
58814 #define V_SGMII_LOOP(x) ((x) << S_SGMII_LOOP)
58815 #define G_SGMII_LOOP(x) (((x) >> S_SGMII_LOOP) & M_SGMII_LOOP)
58816 
58817 #define S_AN_DIS_TIMER    14
58818 #define V_AN_DIS_TIMER(x) ((x) << S_AN_DIS_TIMER)
58819 #define F_AN_DIS_TIMER    V_AN_DIS_TIMER(1U)
58820 
58821 #define S_PCS100G_BER_TIMER_SHORT    13
58822 #define V_PCS100G_BER_TIMER_SHORT(x) ((x) << S_PCS100G_BER_TIMER_SHORT)
58823 #define F_PCS100G_BER_TIMER_SHORT    V_PCS100G_BER_TIMER_SHORT(1U)
58824 
58825 #define S_PCS100G_TX_LANE_THRESH    9
58826 #define M_PCS100G_TX_LANE_THRESH    0xfU
58827 #define V_PCS100G_TX_LANE_THRESH(x) ((x) << S_PCS100G_TX_LANE_THRESH)
58828 #define G_PCS100G_TX_LANE_THRESH(x) (((x) >> S_PCS100G_TX_LANE_THRESH) & M_PCS100G_TX_LANE_THRESH)
58829 
58830 #define S_PCS100G_VL_INTVL    8
58831 #define V_PCS100G_VL_INTVL(x) ((x) << S_PCS100G_VL_INTVL)
58832 #define F_PCS100G_VL_INTVL    V_PCS100G_VL_INTVL(1U)
58833 
58834 #define S_SGMII_TX_LANE_CKMULT    4
58835 #define M_SGMII_TX_LANE_CKMULT    0x7U
58836 #define V_SGMII_TX_LANE_CKMULT(x) ((x) << S_SGMII_TX_LANE_CKMULT)
58837 #define G_SGMII_TX_LANE_CKMULT(x) (((x) >> S_SGMII_TX_LANE_CKMULT) & M_SGMII_TX_LANE_CKMULT)
58838 
58839 #define S_SGMII_TX_LANE_THRESH    0
58840 #define M_SGMII_TX_LANE_THRESH    0xfU
58841 #define V_SGMII_TX_LANE_THRESH(x) ((x) << S_SGMII_TX_LANE_THRESH)
58842 #define G_SGMII_TX_LANE_THRESH(x) (((x) >> S_SGMII_TX_LANE_THRESH) & M_SGMII_TX_LANE_THRESH)
58843 
58844 #define A_MAC_PORT_PCS_DEBUG1_RO 0x880
58845 
58846 #define S_PCS100G_ALIGN_LOCK    21
58847 #define V_PCS100G_ALIGN_LOCK(x) ((x) << S_PCS100G_ALIGN_LOCK)
58848 #define F_PCS100G_ALIGN_LOCK    V_PCS100G_ALIGN_LOCK(1U)
58849 
58850 #define S_PCS100G_BER_TIMER_DONE    20
58851 #define V_PCS100G_BER_TIMER_DONE(x) ((x) << S_PCS100G_BER_TIMER_DONE)
58852 #define F_PCS100G_BER_TIMER_DONE    V_PCS100G_BER_TIMER_DONE(1U)
58853 
58854 #define S_PCS100G_BLOCK_LOCK    0
58855 #define M_PCS100G_BLOCK_LOCK    0xfffffU
58856 #define V_PCS100G_BLOCK_LOCK(x) ((x) << S_PCS100G_BLOCK_LOCK)
58857 #define G_PCS100G_BLOCK_LOCK(x) (((x) >> S_PCS100G_BLOCK_LOCK) & M_PCS100G_BLOCK_LOCK)
58858 
58859 #define A_MAC_PORT_PERR_INT_EN_100G 0x884
58860 
58861 #define S_PERR_RX_FEC100G_DLY    29
58862 #define V_PERR_RX_FEC100G_DLY(x) ((x) << S_PERR_RX_FEC100G_DLY)
58863 #define F_PERR_RX_FEC100G_DLY    V_PERR_RX_FEC100G_DLY(1U)
58864 
58865 #define S_PERR_RX_FEC100G    28
58866 #define V_PERR_RX_FEC100G(x) ((x) << S_PERR_RX_FEC100G)
58867 #define F_PERR_RX_FEC100G    V_PERR_RX_FEC100G(1U)
58868 
58869 #define S_PERR_RX3_FEC100G_DK    27
58870 #define V_PERR_RX3_FEC100G_DK(x) ((x) << S_PERR_RX3_FEC100G_DK)
58871 #define F_PERR_RX3_FEC100G_DK    V_PERR_RX3_FEC100G_DK(1U)
58872 
58873 #define S_PERR_RX2_FEC100G_DK    26
58874 #define V_PERR_RX2_FEC100G_DK(x) ((x) << S_PERR_RX2_FEC100G_DK)
58875 #define F_PERR_RX2_FEC100G_DK    V_PERR_RX2_FEC100G_DK(1U)
58876 
58877 #define S_PERR_RX1_FEC100G_DK    25
58878 #define V_PERR_RX1_FEC100G_DK(x) ((x) << S_PERR_RX1_FEC100G_DK)
58879 #define F_PERR_RX1_FEC100G_DK    V_PERR_RX1_FEC100G_DK(1U)
58880 
58881 #define S_PERR_RX0_FEC100G_DK    24
58882 #define V_PERR_RX0_FEC100G_DK(x) ((x) << S_PERR_RX0_FEC100G_DK)
58883 #define F_PERR_RX0_FEC100G_DK    V_PERR_RX0_FEC100G_DK(1U)
58884 
58885 #define S_PERR_TX3_PCS100G    23
58886 #define V_PERR_TX3_PCS100G(x) ((x) << S_PERR_TX3_PCS100G)
58887 #define F_PERR_TX3_PCS100G    V_PERR_TX3_PCS100G(1U)
58888 
58889 #define S_PERR_TX2_PCS100G    22
58890 #define V_PERR_TX2_PCS100G(x) ((x) << S_PERR_TX2_PCS100G)
58891 #define F_PERR_TX2_PCS100G    V_PERR_TX2_PCS100G(1U)
58892 
58893 #define S_PERR_TX1_PCS100G    21
58894 #define V_PERR_TX1_PCS100G(x) ((x) << S_PERR_TX1_PCS100G)
58895 #define F_PERR_TX1_PCS100G    V_PERR_TX1_PCS100G(1U)
58896 
58897 #define S_PERR_TX0_PCS100G    20
58898 #define V_PERR_TX0_PCS100G(x) ((x) << S_PERR_TX0_PCS100G)
58899 #define F_PERR_TX0_PCS100G    V_PERR_TX0_PCS100G(1U)
58900 
58901 #define S_PERR_RX19_PCS100G    19
58902 #define V_PERR_RX19_PCS100G(x) ((x) << S_PERR_RX19_PCS100G)
58903 #define F_PERR_RX19_PCS100G    V_PERR_RX19_PCS100G(1U)
58904 
58905 #define S_PERR_RX18_PCS100G    18
58906 #define V_PERR_RX18_PCS100G(x) ((x) << S_PERR_RX18_PCS100G)
58907 #define F_PERR_RX18_PCS100G    V_PERR_RX18_PCS100G(1U)
58908 
58909 #define S_PERR_RX17_PCS100G    17
58910 #define V_PERR_RX17_PCS100G(x) ((x) << S_PERR_RX17_PCS100G)
58911 #define F_PERR_RX17_PCS100G    V_PERR_RX17_PCS100G(1U)
58912 
58913 #define S_PERR_RX16_PCS100G    16
58914 #define V_PERR_RX16_PCS100G(x) ((x) << S_PERR_RX16_PCS100G)
58915 #define F_PERR_RX16_PCS100G    V_PERR_RX16_PCS100G(1U)
58916 
58917 #define S_PERR_RX15_PCS100G    15
58918 #define V_PERR_RX15_PCS100G(x) ((x) << S_PERR_RX15_PCS100G)
58919 #define F_PERR_RX15_PCS100G    V_PERR_RX15_PCS100G(1U)
58920 
58921 #define S_PERR_RX14_PCS100G    14
58922 #define V_PERR_RX14_PCS100G(x) ((x) << S_PERR_RX14_PCS100G)
58923 #define F_PERR_RX14_PCS100G    V_PERR_RX14_PCS100G(1U)
58924 
58925 #define S_PERR_RX13_PCS100G    13
58926 #define V_PERR_RX13_PCS100G(x) ((x) << S_PERR_RX13_PCS100G)
58927 #define F_PERR_RX13_PCS100G    V_PERR_RX13_PCS100G(1U)
58928 
58929 #define S_PERR_RX12_PCS100G    12
58930 #define V_PERR_RX12_PCS100G(x) ((x) << S_PERR_RX12_PCS100G)
58931 #define F_PERR_RX12_PCS100G    V_PERR_RX12_PCS100G(1U)
58932 
58933 #define S_PERR_RX11_PCS100G    11
58934 #define V_PERR_RX11_PCS100G(x) ((x) << S_PERR_RX11_PCS100G)
58935 #define F_PERR_RX11_PCS100G    V_PERR_RX11_PCS100G(1U)
58936 
58937 #define S_PERR_RX10_PCS100G    10
58938 #define V_PERR_RX10_PCS100G(x) ((x) << S_PERR_RX10_PCS100G)
58939 #define F_PERR_RX10_PCS100G    V_PERR_RX10_PCS100G(1U)
58940 
58941 #define S_PERR_RX9_PCS100G    9
58942 #define V_PERR_RX9_PCS100G(x) ((x) << S_PERR_RX9_PCS100G)
58943 #define F_PERR_RX9_PCS100G    V_PERR_RX9_PCS100G(1U)
58944 
58945 #define S_PERR_RX8_PCS100G    8
58946 #define V_PERR_RX8_PCS100G(x) ((x) << S_PERR_RX8_PCS100G)
58947 #define F_PERR_RX8_PCS100G    V_PERR_RX8_PCS100G(1U)
58948 
58949 #define S_PERR_RX7_PCS100G    7
58950 #define V_PERR_RX7_PCS100G(x) ((x) << S_PERR_RX7_PCS100G)
58951 #define F_PERR_RX7_PCS100G    V_PERR_RX7_PCS100G(1U)
58952 
58953 #define S_PERR_RX6_PCS100G    6
58954 #define V_PERR_RX6_PCS100G(x) ((x) << S_PERR_RX6_PCS100G)
58955 #define F_PERR_RX6_PCS100G    V_PERR_RX6_PCS100G(1U)
58956 
58957 #define S_PERR_RX5_PCS100G    5
58958 #define V_PERR_RX5_PCS100G(x) ((x) << S_PERR_RX5_PCS100G)
58959 #define F_PERR_RX5_PCS100G    V_PERR_RX5_PCS100G(1U)
58960 
58961 #define S_PERR_RX4_PCS100G    4
58962 #define V_PERR_RX4_PCS100G(x) ((x) << S_PERR_RX4_PCS100G)
58963 #define F_PERR_RX4_PCS100G    V_PERR_RX4_PCS100G(1U)
58964 
58965 #define S_PERR_RX3_PCS100G    3
58966 #define V_PERR_RX3_PCS100G(x) ((x) << S_PERR_RX3_PCS100G)
58967 #define F_PERR_RX3_PCS100G    V_PERR_RX3_PCS100G(1U)
58968 
58969 #define S_PERR_RX2_PCS100G    2
58970 #define V_PERR_RX2_PCS100G(x) ((x) << S_PERR_RX2_PCS100G)
58971 #define F_PERR_RX2_PCS100G    V_PERR_RX2_PCS100G(1U)
58972 
58973 #define S_PERR_RX1_PCS100G    1
58974 #define V_PERR_RX1_PCS100G(x) ((x) << S_PERR_RX1_PCS100G)
58975 #define F_PERR_RX1_PCS100G    V_PERR_RX1_PCS100G(1U)
58976 
58977 #define S_PERR_RX0_PCS100G    0
58978 #define V_PERR_RX0_PCS100G(x) ((x) << S_PERR_RX0_PCS100G)
58979 #define F_PERR_RX0_PCS100G    V_PERR_RX0_PCS100G(1U)
58980 
58981 #define A_MAC_PORT_PERR_INT_CAUSE_100G 0x888
58982 #define A_MAC_PORT_PERR_ENABLE_100G 0x88c
58983 #define A_MAC_PORT_MAC_STAT_DEBUG 0x890
58984 #define A_MAC_PORT_MAC_25G_50G_AM0 0x894
58985 #define A_MAC_PORT_MAC_25G_50G_AM1 0x898
58986 #define A_MAC_PORT_MAC_25G_50G_AM2 0x89c
58987 #define A_MAC_PORT_MAC_25G_50G_AM3 0x8a0
58988 #define A_MAC_PORT_MAC_AN_STATE_STATUS 0x8a4
58989 #define A_MAC_PORT_EPIO_DATA0 0x8c0
58990 #define A_MAC_PORT_EPIO_DATA1 0x8c4
58991 #define A_MAC_PORT_EPIO_DATA2 0x8c8
58992 #define A_MAC_PORT_EPIO_DATA3 0x8cc
58993 #define A_MAC_PORT_EPIO_OP 0x8d0
58994 #define A_MAC_PORT_WOL_STATUS 0x8d4
58995 #define A_MAC_PORT_INT_EN 0x8d8
58996 
58997 #define S_TX_TS_AVAIL    29
58998 #define V_TX_TS_AVAIL(x) ((x) << S_TX_TS_AVAIL)
58999 #define F_TX_TS_AVAIL    V_TX_TS_AVAIL(1U)
59000 
59001 #define S_AN_PAGE_RCVD    2
59002 #define V_AN_PAGE_RCVD(x) ((x) << S_AN_PAGE_RCVD)
59003 #define F_AN_PAGE_RCVD    V_AN_PAGE_RCVD(1U)
59004 
59005 #define S_PPS    30
59006 #define V_PPS(x) ((x) << S_PPS)
59007 #define F_PPS    V_PPS(1U)
59008 
59009 #define S_SINGLE_ALARM    28
59010 #define V_SINGLE_ALARM(x) ((x) << S_SINGLE_ALARM)
59011 #define F_SINGLE_ALARM    V_SINGLE_ALARM(1U)
59012 
59013 #define S_PERIODIC_ALARM    27
59014 #define V_PERIODIC_ALARM(x) ((x) << S_PERIODIC_ALARM)
59015 #define F_PERIODIC_ALARM    V_PERIODIC_ALARM(1U)
59016 
59017 #define A_MAC_PORT_INT_CAUSE 0x8dc
59018 #define A_MAC_PORT_PERR_INT_EN 0x8e0
59019 
59020 #define S_PERR_PKT_RAM    24
59021 #define V_PERR_PKT_RAM(x) ((x) << S_PERR_PKT_RAM)
59022 #define F_PERR_PKT_RAM    V_PERR_PKT_RAM(1U)
59023 
59024 #define S_PERR_MASK_RAM    23
59025 #define V_PERR_MASK_RAM(x) ((x) << S_PERR_MASK_RAM)
59026 #define F_PERR_MASK_RAM    V_PERR_MASK_RAM(1U)
59027 
59028 #define S_PERR_CRC_RAM    22
59029 #define V_PERR_CRC_RAM(x) ((x) << S_PERR_CRC_RAM)
59030 #define F_PERR_CRC_RAM    V_PERR_CRC_RAM(1U)
59031 
59032 #define S_RX_DFF_SEG0    21
59033 #define V_RX_DFF_SEG0(x) ((x) << S_RX_DFF_SEG0)
59034 #define F_RX_DFF_SEG0    V_RX_DFF_SEG0(1U)
59035 
59036 #define S_RX_SFF_SEG0    20
59037 #define V_RX_SFF_SEG0(x) ((x) << S_RX_SFF_SEG0)
59038 #define F_RX_SFF_SEG0    V_RX_SFF_SEG0(1U)
59039 
59040 #define S_RX_DFF_MAC10    19
59041 #define V_RX_DFF_MAC10(x) ((x) << S_RX_DFF_MAC10)
59042 #define F_RX_DFF_MAC10    V_RX_DFF_MAC10(1U)
59043 
59044 #define S_RX_SFF_MAC10    18
59045 #define V_RX_SFF_MAC10(x) ((x) << S_RX_SFF_MAC10)
59046 #define F_RX_SFF_MAC10    V_RX_SFF_MAC10(1U)
59047 
59048 #define S_TX_DFF_SEG0    17
59049 #define V_TX_DFF_SEG0(x) ((x) << S_TX_DFF_SEG0)
59050 #define F_TX_DFF_SEG0    V_TX_DFF_SEG0(1U)
59051 
59052 #define S_TX_SFF_SEG0    16
59053 #define V_TX_SFF_SEG0(x) ((x) << S_TX_SFF_SEG0)
59054 #define F_TX_SFF_SEG0    V_TX_SFF_SEG0(1U)
59055 
59056 #define S_TX_DFF_MAC10    15
59057 #define V_TX_DFF_MAC10(x) ((x) << S_TX_DFF_MAC10)
59058 #define F_TX_DFF_MAC10    V_TX_DFF_MAC10(1U)
59059 
59060 #define S_TX_SFF_MAC10    14
59061 #define V_TX_SFF_MAC10(x) ((x) << S_TX_SFF_MAC10)
59062 #define F_TX_SFF_MAC10    V_TX_SFF_MAC10(1U)
59063 
59064 #define S_RX_STATS    13
59065 #define V_RX_STATS(x) ((x) << S_RX_STATS)
59066 #define F_RX_STATS    V_RX_STATS(1U)
59067 
59068 #define S_TX_STATS    12
59069 #define V_TX_STATS(x) ((x) << S_TX_STATS)
59070 #define F_TX_STATS    V_TX_STATS(1U)
59071 
59072 #define S_PERR3_RX_MIX    11
59073 #define V_PERR3_RX_MIX(x) ((x) << S_PERR3_RX_MIX)
59074 #define F_PERR3_RX_MIX    V_PERR3_RX_MIX(1U)
59075 
59076 #define S_PERR3_RX_SD    10
59077 #define V_PERR3_RX_SD(x) ((x) << S_PERR3_RX_SD)
59078 #define F_PERR3_RX_SD    V_PERR3_RX_SD(1U)
59079 
59080 #define S_PERR3_TX    9
59081 #define V_PERR3_TX(x) ((x) << S_PERR3_TX)
59082 #define F_PERR3_TX    V_PERR3_TX(1U)
59083 
59084 #define S_PERR2_RX_MIX    8
59085 #define V_PERR2_RX_MIX(x) ((x) << S_PERR2_RX_MIX)
59086 #define F_PERR2_RX_MIX    V_PERR2_RX_MIX(1U)
59087 
59088 #define S_PERR2_RX_SD    7
59089 #define V_PERR2_RX_SD(x) ((x) << S_PERR2_RX_SD)
59090 #define F_PERR2_RX_SD    V_PERR2_RX_SD(1U)
59091 
59092 #define S_PERR2_TX    6
59093 #define V_PERR2_TX(x) ((x) << S_PERR2_TX)
59094 #define F_PERR2_TX    V_PERR2_TX(1U)
59095 
59096 #define S_PERR1_RX_MIX    5
59097 #define V_PERR1_RX_MIX(x) ((x) << S_PERR1_RX_MIX)
59098 #define F_PERR1_RX_MIX    V_PERR1_RX_MIX(1U)
59099 
59100 #define S_PERR1_RX_SD    4
59101 #define V_PERR1_RX_SD(x) ((x) << S_PERR1_RX_SD)
59102 #define F_PERR1_RX_SD    V_PERR1_RX_SD(1U)
59103 
59104 #define S_PERR1_TX    3
59105 #define V_PERR1_TX(x) ((x) << S_PERR1_TX)
59106 #define F_PERR1_TX    V_PERR1_TX(1U)
59107 
59108 #define S_PERR0_RX_MIX    2
59109 #define V_PERR0_RX_MIX(x) ((x) << S_PERR0_RX_MIX)
59110 #define F_PERR0_RX_MIX    V_PERR0_RX_MIX(1U)
59111 
59112 #define S_PERR0_RX_SD    1
59113 #define V_PERR0_RX_SD(x) ((x) << S_PERR0_RX_SD)
59114 #define F_PERR0_RX_SD    V_PERR0_RX_SD(1U)
59115 
59116 #define S_PERR0_TX    0
59117 #define V_PERR0_TX(x) ((x) << S_PERR0_TX)
59118 #define F_PERR0_TX    V_PERR0_TX(1U)
59119 
59120 #define S_T6_PERR_PKT_RAM    31
59121 #define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM)
59122 #define F_T6_PERR_PKT_RAM    V_T6_PERR_PKT_RAM(1U)
59123 
59124 #define S_T6_PERR_MASK_RAM    30
59125 #define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM)
59126 #define F_T6_PERR_MASK_RAM    V_T6_PERR_MASK_RAM(1U)
59127 
59128 #define S_T6_PERR_CRC_RAM    29
59129 #define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM)
59130 #define F_T6_PERR_CRC_RAM    V_T6_PERR_CRC_RAM(1U)
59131 
59132 #define S_RX_MAC40G    28
59133 #define V_RX_MAC40G(x) ((x) << S_RX_MAC40G)
59134 #define F_RX_MAC40G    V_RX_MAC40G(1U)
59135 
59136 #define S_TX_MAC40G    27
59137 #define V_TX_MAC40G(x) ((x) << S_TX_MAC40G)
59138 #define F_TX_MAC40G    V_TX_MAC40G(1U)
59139 
59140 #define S_RX_ST_MAC40G    26
59141 #define V_RX_ST_MAC40G(x) ((x) << S_RX_ST_MAC40G)
59142 #define F_RX_ST_MAC40G    V_RX_ST_MAC40G(1U)
59143 
59144 #define S_TX_ST_MAC40G    25
59145 #define V_TX_ST_MAC40G(x) ((x) << S_TX_ST_MAC40G)
59146 #define F_TX_ST_MAC40G    V_TX_ST_MAC40G(1U)
59147 
59148 #define S_TX_MAC1G10G    24
59149 #define V_TX_MAC1G10G(x) ((x) << S_TX_MAC1G10G)
59150 #define F_TX_MAC1G10G    V_TX_MAC1G10G(1U)
59151 
59152 #define S_RX_MAC1G10G    23
59153 #define V_RX_MAC1G10G(x) ((x) << S_RX_MAC1G10G)
59154 #define F_RX_MAC1G10G    V_RX_MAC1G10G(1U)
59155 
59156 #define S_RX_STATUS_MAC1G10G    22
59157 #define V_RX_STATUS_MAC1G10G(x) ((x) << S_RX_STATUS_MAC1G10G)
59158 #define F_RX_STATUS_MAC1G10G    V_RX_STATUS_MAC1G10G(1U)
59159 
59160 #define S_RX_ST_MAC1G10G    21
59161 #define V_RX_ST_MAC1G10G(x) ((x) << S_RX_ST_MAC1G10G)
59162 #define F_RX_ST_MAC1G10G    V_RX_ST_MAC1G10G(1U)
59163 
59164 #define S_TX_ST_MAC1G10G    20
59165 #define V_TX_ST_MAC1G10G(x) ((x) << S_TX_ST_MAC1G10G)
59166 #define F_TX_ST_MAC1G10G    V_TX_ST_MAC1G10G(1U)
59167 
59168 #define S_PERR_TX0_PCS40G    19
59169 #define V_PERR_TX0_PCS40G(x) ((x) << S_PERR_TX0_PCS40G)
59170 #define F_PERR_TX0_PCS40G    V_PERR_TX0_PCS40G(1U)
59171 
59172 #define S_PERR_TX1_PCS40G    18
59173 #define V_PERR_TX1_PCS40G(x) ((x) << S_PERR_TX1_PCS40G)
59174 #define F_PERR_TX1_PCS40G    V_PERR_TX1_PCS40G(1U)
59175 
59176 #define S_PERR_TX2_PCS40G    17
59177 #define V_PERR_TX2_PCS40G(x) ((x) << S_PERR_TX2_PCS40G)
59178 #define F_PERR_TX2_PCS40G    V_PERR_TX2_PCS40G(1U)
59179 
59180 #define S_PERR_TX3_PCS40G    16
59181 #define V_PERR_TX3_PCS40G(x) ((x) << S_PERR_TX3_PCS40G)
59182 #define F_PERR_TX3_PCS40G    V_PERR_TX3_PCS40G(1U)
59183 
59184 #define S_PERR_TX0_FEC40G    15
59185 #define V_PERR_TX0_FEC40G(x) ((x) << S_PERR_TX0_FEC40G)
59186 #define F_PERR_TX0_FEC40G    V_PERR_TX0_FEC40G(1U)
59187 
59188 #define S_PERR_TX1_FEC40G    14
59189 #define V_PERR_TX1_FEC40G(x) ((x) << S_PERR_TX1_FEC40G)
59190 #define F_PERR_TX1_FEC40G    V_PERR_TX1_FEC40G(1U)
59191 
59192 #define S_PERR_TX2_FEC40G    13
59193 #define V_PERR_TX2_FEC40G(x) ((x) << S_PERR_TX2_FEC40G)
59194 #define F_PERR_TX2_FEC40G    V_PERR_TX2_FEC40G(1U)
59195 
59196 #define S_PERR_TX3_FEC40G    12
59197 #define V_PERR_TX3_FEC40G(x) ((x) << S_PERR_TX3_FEC40G)
59198 #define F_PERR_TX3_FEC40G    V_PERR_TX3_FEC40G(1U)
59199 
59200 #define S_PERR_RX0_PCS40G    11
59201 #define V_PERR_RX0_PCS40G(x) ((x) << S_PERR_RX0_PCS40G)
59202 #define F_PERR_RX0_PCS40G    V_PERR_RX0_PCS40G(1U)
59203 
59204 #define S_PERR_RX1_PCS40G    10
59205 #define V_PERR_RX1_PCS40G(x) ((x) << S_PERR_RX1_PCS40G)
59206 #define F_PERR_RX1_PCS40G    V_PERR_RX1_PCS40G(1U)
59207 
59208 #define S_PERR_RX2_PCS40G    9
59209 #define V_PERR_RX2_PCS40G(x) ((x) << S_PERR_RX2_PCS40G)
59210 #define F_PERR_RX2_PCS40G    V_PERR_RX2_PCS40G(1U)
59211 
59212 #define S_PERR_RX3_PCS40G    8
59213 #define V_PERR_RX3_PCS40G(x) ((x) << S_PERR_RX3_PCS40G)
59214 #define F_PERR_RX3_PCS40G    V_PERR_RX3_PCS40G(1U)
59215 
59216 #define S_PERR_RX0_FEC40G    7
59217 #define V_PERR_RX0_FEC40G(x) ((x) << S_PERR_RX0_FEC40G)
59218 #define F_PERR_RX0_FEC40G    V_PERR_RX0_FEC40G(1U)
59219 
59220 #define S_PERR_RX1_FEC40G    6
59221 #define V_PERR_RX1_FEC40G(x) ((x) << S_PERR_RX1_FEC40G)
59222 #define F_PERR_RX1_FEC40G    V_PERR_RX1_FEC40G(1U)
59223 
59224 #define S_PERR_RX2_FEC40G    5
59225 #define V_PERR_RX2_FEC40G(x) ((x) << S_PERR_RX2_FEC40G)
59226 #define F_PERR_RX2_FEC40G    V_PERR_RX2_FEC40G(1U)
59227 
59228 #define S_PERR_RX3_FEC40G    4
59229 #define V_PERR_RX3_FEC40G(x) ((x) << S_PERR_RX3_FEC40G)
59230 #define F_PERR_RX3_FEC40G    V_PERR_RX3_FEC40G(1U)
59231 
59232 #define S_PERR_RX_PCS10G_LPBK    3
59233 #define V_PERR_RX_PCS10G_LPBK(x) ((x) << S_PERR_RX_PCS10G_LPBK)
59234 #define F_PERR_RX_PCS10G_LPBK    V_PERR_RX_PCS10G_LPBK(1U)
59235 
59236 #define S_PERR_RX_PCS10G    2
59237 #define V_PERR_RX_PCS10G(x) ((x) << S_PERR_RX_PCS10G)
59238 #define F_PERR_RX_PCS10G    V_PERR_RX_PCS10G(1U)
59239 
59240 #define S_PERR_RX_PCS1G    1
59241 #define V_PERR_RX_PCS1G(x) ((x) << S_PERR_RX_PCS1G)
59242 #define F_PERR_RX_PCS1G    V_PERR_RX_PCS1G(1U)
59243 
59244 #define S_PERR_TX_PCS1G    0
59245 #define V_PERR_TX_PCS1G(x) ((x) << S_PERR_TX_PCS1G)
59246 #define F_PERR_TX_PCS1G    V_PERR_TX_PCS1G(1U)
59247 
59248 #define A_MAC_PORT_PERR_INT_CAUSE 0x8e4
59249 #define A_MAC_PORT_PERR_ENABLE 0x8e8
59250 #define A_MAC_PORT_PERR_INJECT 0x8ec
59251 
59252 #define S_MEMSEL_PERR    1
59253 #define M_MEMSEL_PERR    0x3fU
59254 #define V_MEMSEL_PERR(x) ((x) << S_MEMSEL_PERR)
59255 #define G_MEMSEL_PERR(x) (((x) >> S_MEMSEL_PERR) & M_MEMSEL_PERR)
59256 
59257 #define A_MAC_PORT_HSS_CFG0 0x8f0
59258 
59259 #define S_HSSREFCLKVALIDA    20
59260 #define V_HSSREFCLKVALIDA(x) ((x) << S_HSSREFCLKVALIDA)
59261 #define F_HSSREFCLKVALIDA    V_HSSREFCLKVALIDA(1U)
59262 
59263 #define S_HSSREFCLKVALIDB    19
59264 #define V_HSSREFCLKVALIDB(x) ((x) << S_HSSREFCLKVALIDB)
59265 #define F_HSSREFCLKVALIDB    V_HSSREFCLKVALIDB(1U)
59266 
59267 #define S_HSSRESYNCA    18
59268 #define V_HSSRESYNCA(x) ((x) << S_HSSRESYNCA)
59269 #define F_HSSRESYNCA    V_HSSRESYNCA(1U)
59270 
59271 #define S_HSSRESYNCB    16
59272 #define V_HSSRESYNCB(x) ((x) << S_HSSRESYNCB)
59273 #define F_HSSRESYNCB    V_HSSRESYNCB(1U)
59274 
59275 #define S_HSSRECCALA    15
59276 #define V_HSSRECCALA(x) ((x) << S_HSSRECCALA)
59277 #define F_HSSRECCALA    V_HSSRECCALA(1U)
59278 
59279 #define S_HSSRECCALB    13
59280 #define V_HSSRECCALB(x) ((x) << S_HSSRECCALB)
59281 #define F_HSSRECCALB    V_HSSRECCALB(1U)
59282 
59283 #define S_HSSPLLBYPA    12
59284 #define V_HSSPLLBYPA(x) ((x) << S_HSSPLLBYPA)
59285 #define F_HSSPLLBYPA    V_HSSPLLBYPA(1U)
59286 
59287 #define S_HSSPLLBYPB    11
59288 #define V_HSSPLLBYPB(x) ((x) << S_HSSPLLBYPB)
59289 #define F_HSSPLLBYPB    V_HSSPLLBYPB(1U)
59290 
59291 #define S_HSSPDWNPLLA    10
59292 #define V_HSSPDWNPLLA(x) ((x) << S_HSSPDWNPLLA)
59293 #define F_HSSPDWNPLLA    V_HSSPDWNPLLA(1U)
59294 
59295 #define S_HSSPDWNPLLB    9
59296 #define V_HSSPDWNPLLB(x) ((x) << S_HSSPDWNPLLB)
59297 #define F_HSSPDWNPLLB    V_HSSPDWNPLLB(1U)
59298 
59299 #define S_HSSVCOSELA    8
59300 #define V_HSSVCOSELA(x) ((x) << S_HSSVCOSELA)
59301 #define F_HSSVCOSELA    V_HSSVCOSELA(1U)
59302 
59303 #define S_HSSVCOSELB    7
59304 #define V_HSSVCOSELB(x) ((x) << S_HSSVCOSELB)
59305 #define F_HSSVCOSELB    V_HSSVCOSELB(1U)
59306 
59307 #define S_HSSCALCOMP    6
59308 #define V_HSSCALCOMP(x) ((x) << S_HSSCALCOMP)
59309 #define F_HSSCALCOMP    V_HSSCALCOMP(1U)
59310 
59311 #define S_HSSCALENAB    5
59312 #define V_HSSCALENAB(x) ((x) << S_HSSCALENAB)
59313 #define F_HSSCALENAB    V_HSSCALENAB(1U)
59314 
59315 #define A_MAC_PORT_HSS_CFG1 0x8f4
59316 
59317 #define S_RXACONFIGSEL    30
59318 #define M_RXACONFIGSEL    0x3U
59319 #define V_RXACONFIGSEL(x) ((x) << S_RXACONFIGSEL)
59320 #define G_RXACONFIGSEL(x) (((x) >> S_RXACONFIGSEL) & M_RXACONFIGSEL)
59321 
59322 #define S_RXAQUIET    29
59323 #define V_RXAQUIET(x) ((x) << S_RXAQUIET)
59324 #define F_RXAQUIET    V_RXAQUIET(1U)
59325 
59326 #define S_RXAREFRESH    28
59327 #define V_RXAREFRESH(x) ((x) << S_RXAREFRESH)
59328 #define F_RXAREFRESH    V_RXAREFRESH(1U)
59329 
59330 #define S_RXBCONFIGSEL    26
59331 #define M_RXBCONFIGSEL    0x3U
59332 #define V_RXBCONFIGSEL(x) ((x) << S_RXBCONFIGSEL)
59333 #define G_RXBCONFIGSEL(x) (((x) >> S_RXBCONFIGSEL) & M_RXBCONFIGSEL)
59334 
59335 #define S_RXBQUIET    25
59336 #define V_RXBQUIET(x) ((x) << S_RXBQUIET)
59337 #define F_RXBQUIET    V_RXBQUIET(1U)
59338 
59339 #define S_RXBREFRESH    24
59340 #define V_RXBREFRESH(x) ((x) << S_RXBREFRESH)
59341 #define F_RXBREFRESH    V_RXBREFRESH(1U)
59342 
59343 #define S_RXCCONFIGSEL    22
59344 #define M_RXCCONFIGSEL    0x3U
59345 #define V_RXCCONFIGSEL(x) ((x) << S_RXCCONFIGSEL)
59346 #define G_RXCCONFIGSEL(x) (((x) >> S_RXCCONFIGSEL) & M_RXCCONFIGSEL)
59347 
59348 #define S_RXCQUIET    21
59349 #define V_RXCQUIET(x) ((x) << S_RXCQUIET)
59350 #define F_RXCQUIET    V_RXCQUIET(1U)
59351 
59352 #define S_RXCREFRESH    20
59353 #define V_RXCREFRESH(x) ((x) << S_RXCREFRESH)
59354 #define F_RXCREFRESH    V_RXCREFRESH(1U)
59355 
59356 #define S_RXDCONFIGSEL    18
59357 #define M_RXDCONFIGSEL    0x3U
59358 #define V_RXDCONFIGSEL(x) ((x) << S_RXDCONFIGSEL)
59359 #define G_RXDCONFIGSEL(x) (((x) >> S_RXDCONFIGSEL) & M_RXDCONFIGSEL)
59360 
59361 #define S_RXDQUIET    17
59362 #define V_RXDQUIET(x) ((x) << S_RXDQUIET)
59363 #define F_RXDQUIET    V_RXDQUIET(1U)
59364 
59365 #define S_RXDREFRESH    16
59366 #define V_RXDREFRESH(x) ((x) << S_RXDREFRESH)
59367 #define F_RXDREFRESH    V_RXDREFRESH(1U)
59368 
59369 #define S_TXACONFIGSEL    14
59370 #define M_TXACONFIGSEL    0x3U
59371 #define V_TXACONFIGSEL(x) ((x) << S_TXACONFIGSEL)
59372 #define G_TXACONFIGSEL(x) (((x) >> S_TXACONFIGSEL) & M_TXACONFIGSEL)
59373 
59374 #define S_TXAQUIET    13
59375 #define V_TXAQUIET(x) ((x) << S_TXAQUIET)
59376 #define F_TXAQUIET    V_TXAQUIET(1U)
59377 
59378 #define S_TXAREFRESH    12
59379 #define V_TXAREFRESH(x) ((x) << S_TXAREFRESH)
59380 #define F_TXAREFRESH    V_TXAREFRESH(1U)
59381 
59382 #define S_TXBCONFIGSEL    10
59383 #define M_TXBCONFIGSEL    0x3U
59384 #define V_TXBCONFIGSEL(x) ((x) << S_TXBCONFIGSEL)
59385 #define G_TXBCONFIGSEL(x) (((x) >> S_TXBCONFIGSEL) & M_TXBCONFIGSEL)
59386 
59387 #define S_TXBQUIET    9
59388 #define V_TXBQUIET(x) ((x) << S_TXBQUIET)
59389 #define F_TXBQUIET    V_TXBQUIET(1U)
59390 
59391 #define S_TXBREFRESH    8
59392 #define V_TXBREFRESH(x) ((x) << S_TXBREFRESH)
59393 #define F_TXBREFRESH    V_TXBREFRESH(1U)
59394 
59395 #define S_TXCCONFIGSEL    6
59396 #define M_TXCCONFIGSEL    0x3U
59397 #define V_TXCCONFIGSEL(x) ((x) << S_TXCCONFIGSEL)
59398 #define G_TXCCONFIGSEL(x) (((x) >> S_TXCCONFIGSEL) & M_TXCCONFIGSEL)
59399 
59400 #define S_TXCQUIET    5
59401 #define V_TXCQUIET(x) ((x) << S_TXCQUIET)
59402 #define F_TXCQUIET    V_TXCQUIET(1U)
59403 
59404 #define S_TXCREFRESH    4
59405 #define V_TXCREFRESH(x) ((x) << S_TXCREFRESH)
59406 #define F_TXCREFRESH    V_TXCREFRESH(1U)
59407 
59408 #define S_TXDCONFIGSEL    2
59409 #define M_TXDCONFIGSEL    0x3U
59410 #define V_TXDCONFIGSEL(x) ((x) << S_TXDCONFIGSEL)
59411 #define G_TXDCONFIGSEL(x) (((x) >> S_TXDCONFIGSEL) & M_TXDCONFIGSEL)
59412 
59413 #define S_TXDQUIET    1
59414 #define V_TXDQUIET(x) ((x) << S_TXDQUIET)
59415 #define F_TXDQUIET    V_TXDQUIET(1U)
59416 
59417 #define S_TXDREFRESH    0
59418 #define V_TXDREFRESH(x) ((x) << S_TXDREFRESH)
59419 #define F_TXDREFRESH    V_TXDREFRESH(1U)
59420 
59421 #define A_MAC_PORT_HSS_CFG2 0x8f8
59422 
59423 #define S_RXAASSTCLK    31
59424 #define V_RXAASSTCLK(x) ((x) << S_RXAASSTCLK)
59425 #define F_RXAASSTCLK    V_RXAASSTCLK(1U)
59426 
59427 #define S_T5RXAPRBSRST    30
59428 #define V_T5RXAPRBSRST(x) ((x) << S_T5RXAPRBSRST)
59429 #define F_T5RXAPRBSRST    V_T5RXAPRBSRST(1U)
59430 
59431 #define S_RXBASSTCLK    29
59432 #define V_RXBASSTCLK(x) ((x) << S_RXBASSTCLK)
59433 #define F_RXBASSTCLK    V_RXBASSTCLK(1U)
59434 
59435 #define S_T5RXBPRBSRST    28
59436 #define V_T5RXBPRBSRST(x) ((x) << S_T5RXBPRBSRST)
59437 #define F_T5RXBPRBSRST    V_T5RXBPRBSRST(1U)
59438 
59439 #define S_RXCASSTCLK    27
59440 #define V_RXCASSTCLK(x) ((x) << S_RXCASSTCLK)
59441 #define F_RXCASSTCLK    V_RXCASSTCLK(1U)
59442 
59443 #define S_T5RXCPRBSRST    26
59444 #define V_T5RXCPRBSRST(x) ((x) << S_T5RXCPRBSRST)
59445 #define F_T5RXCPRBSRST    V_T5RXCPRBSRST(1U)
59446 
59447 #define S_RXDASSTCLK    25
59448 #define V_RXDASSTCLK(x) ((x) << S_RXDASSTCLK)
59449 #define F_RXDASSTCLK    V_RXDASSTCLK(1U)
59450 
59451 #define S_T5RXDPRBSRST    24
59452 #define V_T5RXDPRBSRST(x) ((x) << S_T5RXDPRBSRST)
59453 #define F_T5RXDPRBSRST    V_T5RXDPRBSRST(1U)
59454 
59455 #define A_MAC_PORT_HSS_CFG3 0x8fc
59456 
59457 #define S_HSSCALSSTN    25
59458 #define M_HSSCALSSTN    0x7U
59459 #define V_HSSCALSSTN(x) ((x) << S_HSSCALSSTN)
59460 #define G_HSSCALSSTN(x) (((x) >> S_HSSCALSSTN) & M_HSSCALSSTN)
59461 
59462 #define S_HSSCALSSTP    22
59463 #define M_HSSCALSSTP    0x7U
59464 #define V_HSSCALSSTP(x) ((x) << S_HSSCALSSTP)
59465 #define G_HSSCALSSTP(x) (((x) >> S_HSSCALSSTP) & M_HSSCALSSTP)
59466 
59467 #define S_HSSVBOOSTDIVB    19
59468 #define M_HSSVBOOSTDIVB    0x7U
59469 #define V_HSSVBOOSTDIVB(x) ((x) << S_HSSVBOOSTDIVB)
59470 #define G_HSSVBOOSTDIVB(x) (((x) >> S_HSSVBOOSTDIVB) & M_HSSVBOOSTDIVB)
59471 
59472 #define S_HSSVBOOSTDIVA    16
59473 #define M_HSSVBOOSTDIVA    0x7U
59474 #define V_HSSVBOOSTDIVA(x) ((x) << S_HSSVBOOSTDIVA)
59475 #define G_HSSVBOOSTDIVA(x) (((x) >> S_HSSVBOOSTDIVA) & M_HSSVBOOSTDIVA)
59476 
59477 #define S_HSSPLLCONFIGB    8
59478 #define M_HSSPLLCONFIGB    0xffU
59479 #define V_HSSPLLCONFIGB(x) ((x) << S_HSSPLLCONFIGB)
59480 #define G_HSSPLLCONFIGB(x) (((x) >> S_HSSPLLCONFIGB) & M_HSSPLLCONFIGB)
59481 
59482 #define S_HSSPLLCONFIGA    0
59483 #define M_HSSPLLCONFIGA    0xffU
59484 #define V_HSSPLLCONFIGA(x) ((x) << S_HSSPLLCONFIGA)
59485 #define G_HSSPLLCONFIGA(x) (((x) >> S_HSSPLLCONFIGA) & M_HSSPLLCONFIGA)
59486 
59487 #define S_T6_HSSCALSSTN    22
59488 #define M_T6_HSSCALSSTN    0x3fU
59489 #define V_T6_HSSCALSSTN(x) ((x) << S_T6_HSSCALSSTN)
59490 #define G_T6_HSSCALSSTN(x) (((x) >> S_T6_HSSCALSSTN) & M_T6_HSSCALSSTN)
59491 
59492 #define S_T6_HSSCALSSTP    16
59493 #define M_T6_HSSCALSSTP    0x3fU
59494 #define V_T6_HSSCALSSTP(x) ((x) << S_T6_HSSCALSSTP)
59495 #define G_T6_HSSCALSSTP(x) (((x) >> S_T6_HSSCALSSTP) & M_T6_HSSCALSSTP)
59496 
59497 #define A_MAC_PORT_HSS_CFG4 0x900
59498 
59499 #define S_HSSDIVSELA    9
59500 #define M_HSSDIVSELA    0x1ffU
59501 #define V_HSSDIVSELA(x) ((x) << S_HSSDIVSELA)
59502 #define G_HSSDIVSELA(x) (((x) >> S_HSSDIVSELA) & M_HSSDIVSELA)
59503 
59504 #define S_HSSDIVSELB    0
59505 #define M_HSSDIVSELB    0x1ffU
59506 #define V_HSSDIVSELB(x) ((x) << S_HSSDIVSELB)
59507 #define G_HSSDIVSELB(x) (((x) >> S_HSSDIVSELB) & M_HSSDIVSELB)
59508 
59509 #define S_HSSREFDIVA    24
59510 #define M_HSSREFDIVA    0xfU
59511 #define V_HSSREFDIVA(x) ((x) << S_HSSREFDIVA)
59512 #define G_HSSREFDIVA(x) (((x) >> S_HSSREFDIVA) & M_HSSREFDIVA)
59513 
59514 #define S_HSSREFDIVB    20
59515 #define M_HSSREFDIVB    0xfU
59516 #define V_HSSREFDIVB(x) ((x) << S_HSSREFDIVB)
59517 #define G_HSSREFDIVB(x) (((x) >> S_HSSREFDIVB) & M_HSSREFDIVB)
59518 
59519 #define S_HSSPLLDIV2B    19
59520 #define V_HSSPLLDIV2B(x) ((x) << S_HSSPLLDIV2B)
59521 #define F_HSSPLLDIV2B    V_HSSPLLDIV2B(1U)
59522 
59523 #define S_HSSPLLDIV2A    18
59524 #define V_HSSPLLDIV2A(x) ((x) << S_HSSPLLDIV2A)
59525 #define F_HSSPLLDIV2A    V_HSSPLLDIV2A(1U)
59526 
59527 #define A_MAC_PORT_HSS_STATUS 0x904
59528 
59529 #define S_HSSPLLLOCKB    3
59530 #define V_HSSPLLLOCKB(x) ((x) << S_HSSPLLLOCKB)
59531 #define F_HSSPLLLOCKB    V_HSSPLLLOCKB(1U)
59532 
59533 #define S_HSSPLLLOCKA    2
59534 #define V_HSSPLLLOCKA(x) ((x) << S_HSSPLLLOCKA)
59535 #define F_HSSPLLLOCKA    V_HSSPLLLOCKA(1U)
59536 
59537 #define S_HSSPRTREADYB    1
59538 #define V_HSSPRTREADYB(x) ((x) << S_HSSPRTREADYB)
59539 #define F_HSSPRTREADYB    V_HSSPRTREADYB(1U)
59540 
59541 #define S_HSSPRTREADYA    0
59542 #define V_HSSPRTREADYA(x) ((x) << S_HSSPRTREADYA)
59543 #define F_HSSPRTREADYA    V_HSSPRTREADYA(1U)
59544 
59545 #define S_RXDERROFLOW    19
59546 #define V_RXDERROFLOW(x) ((x) << S_RXDERROFLOW)
59547 #define F_RXDERROFLOW    V_RXDERROFLOW(1U)
59548 
59549 #define S_RXCERROFLOW    18
59550 #define V_RXCERROFLOW(x) ((x) << S_RXCERROFLOW)
59551 #define F_RXCERROFLOW    V_RXCERROFLOW(1U)
59552 
59553 #define S_RXBERROFLOW    17
59554 #define V_RXBERROFLOW(x) ((x) << S_RXBERROFLOW)
59555 #define F_RXBERROFLOW    V_RXBERROFLOW(1U)
59556 
59557 #define S_RXAERROFLOW    16
59558 #define V_RXAERROFLOW(x) ((x) << S_RXAERROFLOW)
59559 #define F_RXAERROFLOW    V_RXAERROFLOW(1U)
59560 
59561 #define A_MAC_PORT_HSS_EEE_STATUS 0x908
59562 
59563 #define S_RXAQUIET_STATUS    15
59564 #define V_RXAQUIET_STATUS(x) ((x) << S_RXAQUIET_STATUS)
59565 #define F_RXAQUIET_STATUS    V_RXAQUIET_STATUS(1U)
59566 
59567 #define S_RXAREFRESH_STATUS    14
59568 #define V_RXAREFRESH_STATUS(x) ((x) << S_RXAREFRESH_STATUS)
59569 #define F_RXAREFRESH_STATUS    V_RXAREFRESH_STATUS(1U)
59570 
59571 #define S_RXBQUIET_STATUS    13
59572 #define V_RXBQUIET_STATUS(x) ((x) << S_RXBQUIET_STATUS)
59573 #define F_RXBQUIET_STATUS    V_RXBQUIET_STATUS(1U)
59574 
59575 #define S_RXBREFRESH_STATUS    12
59576 #define V_RXBREFRESH_STATUS(x) ((x) << S_RXBREFRESH_STATUS)
59577 #define F_RXBREFRESH_STATUS    V_RXBREFRESH_STATUS(1U)
59578 
59579 #define S_RXCQUIET_STATUS    11
59580 #define V_RXCQUIET_STATUS(x) ((x) << S_RXCQUIET_STATUS)
59581 #define F_RXCQUIET_STATUS    V_RXCQUIET_STATUS(1U)
59582 
59583 #define S_RXCREFRESH_STATUS    10
59584 #define V_RXCREFRESH_STATUS(x) ((x) << S_RXCREFRESH_STATUS)
59585 #define F_RXCREFRESH_STATUS    V_RXCREFRESH_STATUS(1U)
59586 
59587 #define S_RXDQUIET_STATUS    9
59588 #define V_RXDQUIET_STATUS(x) ((x) << S_RXDQUIET_STATUS)
59589 #define F_RXDQUIET_STATUS    V_RXDQUIET_STATUS(1U)
59590 
59591 #define S_RXDREFRESH_STATUS    8
59592 #define V_RXDREFRESH_STATUS(x) ((x) << S_RXDREFRESH_STATUS)
59593 #define F_RXDREFRESH_STATUS    V_RXDREFRESH_STATUS(1U)
59594 
59595 #define S_TXAQUIET_STATUS    7
59596 #define V_TXAQUIET_STATUS(x) ((x) << S_TXAQUIET_STATUS)
59597 #define F_TXAQUIET_STATUS    V_TXAQUIET_STATUS(1U)
59598 
59599 #define S_TXAREFRESH_STATUS    6
59600 #define V_TXAREFRESH_STATUS(x) ((x) << S_TXAREFRESH_STATUS)
59601 #define F_TXAREFRESH_STATUS    V_TXAREFRESH_STATUS(1U)
59602 
59603 #define S_TXBQUIET_STATUS    5
59604 #define V_TXBQUIET_STATUS(x) ((x) << S_TXBQUIET_STATUS)
59605 #define F_TXBQUIET_STATUS    V_TXBQUIET_STATUS(1U)
59606 
59607 #define S_TXBREFRESH_STATUS    4
59608 #define V_TXBREFRESH_STATUS(x) ((x) << S_TXBREFRESH_STATUS)
59609 #define F_TXBREFRESH_STATUS    V_TXBREFRESH_STATUS(1U)
59610 
59611 #define S_TXCQUIET_STATUS    3
59612 #define V_TXCQUIET_STATUS(x) ((x) << S_TXCQUIET_STATUS)
59613 #define F_TXCQUIET_STATUS    V_TXCQUIET_STATUS(1U)
59614 
59615 #define S_TXCREFRESH_STATUS    2
59616 #define V_TXCREFRESH_STATUS(x) ((x) << S_TXCREFRESH_STATUS)
59617 #define F_TXCREFRESH_STATUS    V_TXCREFRESH_STATUS(1U)
59618 
59619 #define S_TXDQUIET_STATUS    1
59620 #define V_TXDQUIET_STATUS(x) ((x) << S_TXDQUIET_STATUS)
59621 #define F_TXDQUIET_STATUS    V_TXDQUIET_STATUS(1U)
59622 
59623 #define S_TXDREFRESH_STATUS    0
59624 #define V_TXDREFRESH_STATUS(x) ((x) << S_TXDREFRESH_STATUS)
59625 #define F_TXDREFRESH_STATUS    V_TXDREFRESH_STATUS(1U)
59626 
59627 #define A_MAC_PORT_HSS_SIGDET_STATUS 0x90c
59628 #define A_MAC_PORT_HSS_PL_CTL 0x910
59629 
59630 #define S_TOV    16
59631 #define M_TOV    0xffU
59632 #define V_TOV(x) ((x) << S_TOV)
59633 #define G_TOV(x) (((x) >> S_TOV) & M_TOV)
59634 
59635 #define S_TSU    8
59636 #define M_TSU    0xffU
59637 #define V_TSU(x) ((x) << S_TSU)
59638 #define G_TSU(x) (((x) >> S_TSU) & M_TSU)
59639 
59640 #define S_IPW    0
59641 #define M_IPW    0xffU
59642 #define V_IPW(x) ((x) << S_IPW)
59643 #define G_IPW(x) (((x) >> S_IPW) & M_IPW)
59644 
59645 #define A_MAC_PORT_RUNT_FRAME 0x914
59646 
59647 #define S_RUNTCLEAR    16
59648 #define V_RUNTCLEAR(x) ((x) << S_RUNTCLEAR)
59649 #define F_RUNTCLEAR    V_RUNTCLEAR(1U)
59650 
59651 #define S_RUNT    0
59652 #define M_RUNT    0xffffU
59653 #define V_RUNT(x) ((x) << S_RUNT)
59654 #define G_RUNT(x) (((x) >> S_RUNT) & M_RUNT)
59655 
59656 #define A_MAC_PORT_EEE_STATUS 0x918
59657 
59658 #define S_EEE_TX_10G_STATE    10
59659 #define M_EEE_TX_10G_STATE    0x3U
59660 #define V_EEE_TX_10G_STATE(x) ((x) << S_EEE_TX_10G_STATE)
59661 #define G_EEE_TX_10G_STATE(x) (((x) >> S_EEE_TX_10G_STATE) & M_EEE_TX_10G_STATE)
59662 
59663 #define S_EEE_RX_10G_STATE    8
59664 #define M_EEE_RX_10G_STATE    0x3U
59665 #define V_EEE_RX_10G_STATE(x) ((x) << S_EEE_RX_10G_STATE)
59666 #define G_EEE_RX_10G_STATE(x) (((x) >> S_EEE_RX_10G_STATE) & M_EEE_RX_10G_STATE)
59667 
59668 #define S_EEE_TX_1G_STATE    6
59669 #define M_EEE_TX_1G_STATE    0x3U
59670 #define V_EEE_TX_1G_STATE(x) ((x) << S_EEE_TX_1G_STATE)
59671 #define G_EEE_TX_1G_STATE(x) (((x) >> S_EEE_TX_1G_STATE) & M_EEE_TX_1G_STATE)
59672 
59673 #define S_EEE_RX_1G_STATE    4
59674 #define M_EEE_RX_1G_STATE    0x3U
59675 #define V_EEE_RX_1G_STATE(x) ((x) << S_EEE_RX_1G_STATE)
59676 #define G_EEE_RX_1G_STATE(x) (((x) >> S_EEE_RX_1G_STATE) & M_EEE_RX_1G_STATE)
59677 
59678 #define S_PMA_RX_REFRESH    3
59679 #define V_PMA_RX_REFRESH(x) ((x) << S_PMA_RX_REFRESH)
59680 #define F_PMA_RX_REFRESH    V_PMA_RX_REFRESH(1U)
59681 
59682 #define S_PMA_RX_QUIET    2
59683 #define V_PMA_RX_QUIET(x) ((x) << S_PMA_RX_QUIET)
59684 #define F_PMA_RX_QUIET    V_PMA_RX_QUIET(1U)
59685 
59686 #define S_PMA_TX_REFRESH    1
59687 #define V_PMA_TX_REFRESH(x) ((x) << S_PMA_TX_REFRESH)
59688 #define F_PMA_TX_REFRESH    V_PMA_TX_REFRESH(1U)
59689 
59690 #define S_PMA_TX_QUIET    0
59691 #define V_PMA_TX_QUIET(x) ((x) << S_PMA_TX_QUIET)
59692 #define F_PMA_TX_QUIET    V_PMA_TX_QUIET(1U)
59693 
59694 #define A_MAC_PORT_CGEN 0x91c
59695 
59696 #define S_CGEN    8
59697 #define V_CGEN(x) ((x) << S_CGEN)
59698 #define F_CGEN    V_CGEN(1U)
59699 
59700 #define S_SD7_CGEN    7
59701 #define V_SD7_CGEN(x) ((x) << S_SD7_CGEN)
59702 #define F_SD7_CGEN    V_SD7_CGEN(1U)
59703 
59704 #define S_SD6_CGEN    6
59705 #define V_SD6_CGEN(x) ((x) << S_SD6_CGEN)
59706 #define F_SD6_CGEN    V_SD6_CGEN(1U)
59707 
59708 #define S_SD5_CGEN    5
59709 #define V_SD5_CGEN(x) ((x) << S_SD5_CGEN)
59710 #define F_SD5_CGEN    V_SD5_CGEN(1U)
59711 
59712 #define S_SD4_CGEN    4
59713 #define V_SD4_CGEN(x) ((x) << S_SD4_CGEN)
59714 #define F_SD4_CGEN    V_SD4_CGEN(1U)
59715 
59716 #define S_SD3_CGEN    3
59717 #define V_SD3_CGEN(x) ((x) << S_SD3_CGEN)
59718 #define F_SD3_CGEN    V_SD3_CGEN(1U)
59719 
59720 #define S_SD2_CGEN    2
59721 #define V_SD2_CGEN(x) ((x) << S_SD2_CGEN)
59722 #define F_SD2_CGEN    V_SD2_CGEN(1U)
59723 
59724 #define S_SD1_CGEN    1
59725 #define V_SD1_CGEN(x) ((x) << S_SD1_CGEN)
59726 #define F_SD1_CGEN    V_SD1_CGEN(1U)
59727 
59728 #define S_SD0_CGEN    0
59729 #define V_SD0_CGEN(x) ((x) << S_SD0_CGEN)
59730 #define F_SD0_CGEN    V_SD0_CGEN(1U)
59731 
59732 #define A_MAC_PORT_CGEN_MTIP 0x920
59733 
59734 #define S_MACSEG5_CGEN    11
59735 #define V_MACSEG5_CGEN(x) ((x) << S_MACSEG5_CGEN)
59736 #define F_MACSEG5_CGEN    V_MACSEG5_CGEN(1U)
59737 
59738 #define S_PCSSEG5_CGEN    10
59739 #define V_PCSSEG5_CGEN(x) ((x) << S_PCSSEG5_CGEN)
59740 #define F_PCSSEG5_CGEN    V_PCSSEG5_CGEN(1U)
59741 
59742 #define S_MACSEG4_CGEN    9
59743 #define V_MACSEG4_CGEN(x) ((x) << S_MACSEG4_CGEN)
59744 #define F_MACSEG4_CGEN    V_MACSEG4_CGEN(1U)
59745 
59746 #define S_PCSSEG4_CGEN    8
59747 #define V_PCSSEG4_CGEN(x) ((x) << S_PCSSEG4_CGEN)
59748 #define F_PCSSEG4_CGEN    V_PCSSEG4_CGEN(1U)
59749 
59750 #define S_MACSEG3_CGEN    7
59751 #define V_MACSEG3_CGEN(x) ((x) << S_MACSEG3_CGEN)
59752 #define F_MACSEG3_CGEN    V_MACSEG3_CGEN(1U)
59753 
59754 #define S_PCSSEG3_CGEN    6
59755 #define V_PCSSEG3_CGEN(x) ((x) << S_PCSSEG3_CGEN)
59756 #define F_PCSSEG3_CGEN    V_PCSSEG3_CGEN(1U)
59757 
59758 #define S_MACSEG2_CGEN    5
59759 #define V_MACSEG2_CGEN(x) ((x) << S_MACSEG2_CGEN)
59760 #define F_MACSEG2_CGEN    V_MACSEG2_CGEN(1U)
59761 
59762 #define S_PCSSEG2_CGEN    4
59763 #define V_PCSSEG2_CGEN(x) ((x) << S_PCSSEG2_CGEN)
59764 #define F_PCSSEG2_CGEN    V_PCSSEG2_CGEN(1U)
59765 
59766 #define S_MACSEG1_CGEN    3
59767 #define V_MACSEG1_CGEN(x) ((x) << S_MACSEG1_CGEN)
59768 #define F_MACSEG1_CGEN    V_MACSEG1_CGEN(1U)
59769 
59770 #define S_PCSSEG1_CGEN    2
59771 #define V_PCSSEG1_CGEN(x) ((x) << S_PCSSEG1_CGEN)
59772 #define F_PCSSEG1_CGEN    V_PCSSEG1_CGEN(1U)
59773 
59774 #define S_MACSEG0_CGEN    1
59775 #define V_MACSEG0_CGEN(x) ((x) << S_MACSEG0_CGEN)
59776 #define F_MACSEG0_CGEN    V_MACSEG0_CGEN(1U)
59777 
59778 #define S_PCSSEG0_CGEN    0
59779 #define V_PCSSEG0_CGEN(x) ((x) << S_PCSSEG0_CGEN)
59780 #define F_PCSSEG0_CGEN    V_PCSSEG0_CGEN(1U)
59781 
59782 #define A_MAC_PORT_TX_TS_ID 0x924
59783 
59784 #define S_TS_ID    0
59785 #define M_TS_ID    0x7U
59786 #define V_TS_ID(x) ((x) << S_TS_ID)
59787 #define G_TS_ID(x) (((x) >> S_TS_ID) & M_TS_ID)
59788 
59789 #define A_MAC_PORT_TX_TS_VAL_LO 0x928
59790 #define A_MAC_PORT_TX_TS_VAL_HI 0x92c
59791 #define A_MAC_PORT_EEE_CTL 0x930
59792 
59793 #define S_EEE_CTRL    2
59794 #define M_EEE_CTRL    0x3fffffffU
59795 #define V_EEE_CTRL(x) ((x) << S_EEE_CTRL)
59796 #define G_EEE_CTRL(x) (((x) >> S_EEE_CTRL) & M_EEE_CTRL)
59797 
59798 #define S_TICK_START    1
59799 #define V_TICK_START(x) ((x) << S_TICK_START)
59800 #define F_TICK_START    V_TICK_START(1U)
59801 
59802 #define S_EEE_ENABLE    0
59803 #define V_EEE_ENABLE(x) ((x) << S_EEE_ENABLE)
59804 #define F_EEE_ENABLE    V_EEE_ENABLE(1U)
59805 
59806 #define A_MAC_PORT_EEE_TX_CTL 0x934
59807 
59808 #define S_WAKE_TIMER    16
59809 #define M_WAKE_TIMER    0xffffU
59810 #define V_WAKE_TIMER(x) ((x) << S_WAKE_TIMER)
59811 #define G_WAKE_TIMER(x) (((x) >> S_WAKE_TIMER) & M_WAKE_TIMER)
59812 
59813 #define S_HSS_TIMER    5
59814 #define M_HSS_TIMER    0xfU
59815 #define V_HSS_TIMER(x) ((x) << S_HSS_TIMER)
59816 #define G_HSS_TIMER(x) (((x) >> S_HSS_TIMER) & M_HSS_TIMER)
59817 
59818 #define S_HSS_CTL    4
59819 #define V_HSS_CTL(x) ((x) << S_HSS_CTL)
59820 #define F_HSS_CTL    V_HSS_CTL(1U)
59821 
59822 #define S_LPI_ACTIVE    3
59823 #define V_LPI_ACTIVE(x) ((x) << S_LPI_ACTIVE)
59824 #define F_LPI_ACTIVE    V_LPI_ACTIVE(1U)
59825 
59826 #define S_LPI_TXHOLD    2
59827 #define V_LPI_TXHOLD(x) ((x) << S_LPI_TXHOLD)
59828 #define F_LPI_TXHOLD    V_LPI_TXHOLD(1U)
59829 
59830 #define S_LPI_REQ    1
59831 #define V_LPI_REQ(x) ((x) << S_LPI_REQ)
59832 #define F_LPI_REQ    V_LPI_REQ(1U)
59833 
59834 #define S_EEE_TX_RESET    0
59835 #define V_EEE_TX_RESET(x) ((x) << S_EEE_TX_RESET)
59836 #define F_EEE_TX_RESET    V_EEE_TX_RESET(1U)
59837 
59838 #define A_MAC_PORT_EEE_RX_CTL 0x938
59839 
59840 #define S_LPI_IND    1
59841 #define V_LPI_IND(x) ((x) << S_LPI_IND)
59842 #define F_LPI_IND    V_LPI_IND(1U)
59843 
59844 #define S_EEE_RX_RESET    0
59845 #define V_EEE_RX_RESET(x) ((x) << S_EEE_RX_RESET)
59846 #define F_EEE_RX_RESET    V_EEE_RX_RESET(1U)
59847 
59848 #define A_MAC_PORT_EEE_TX_10G_SLEEP_TIMER 0x93c
59849 #define A_MAC_PORT_EEE_TX_10G_QUIET_TIMER 0x940
59850 #define A_MAC_PORT_EEE_TX_10G_WAKE_TIMER 0x944
59851 #define A_MAC_PORT_EEE_TX_1G_SLEEP_TIMER 0x948
59852 #define A_MAC_PORT_EEE_TX_1G_QUIET_TIMER 0x94c
59853 #define A_MAC_PORT_EEE_TX_1G_REFRESH_TIMER 0x950
59854 #define A_MAC_PORT_EEE_RX_10G_QUIET_TIMER 0x954
59855 #define A_MAC_PORT_EEE_RX_10G_WAKE_TIMER 0x958
59856 #define A_MAC_PORT_EEE_RX_10G_WF_TIMER 0x95c
59857 #define A_MAC_PORT_EEE_RX_1G_QUIET_TIMER 0x960
59858 #define A_MAC_PORT_EEE_RX_1G_WAKE_TIMER 0x964
59859 #define A_MAC_PORT_EEE_WF_COUNT 0x968
59860 
59861 #define S_WAKE_CNT_CLR    16
59862 #define V_WAKE_CNT_CLR(x) ((x) << S_WAKE_CNT_CLR)
59863 #define F_WAKE_CNT_CLR    V_WAKE_CNT_CLR(1U)
59864 
59865 #define S_WAKE_CNT    0
59866 #define M_WAKE_CNT    0xffffU
59867 #define V_WAKE_CNT(x) ((x) << S_WAKE_CNT)
59868 #define G_WAKE_CNT(x) (((x) >> S_WAKE_CNT) & M_WAKE_CNT)
59869 
59870 #define A_MAC_PORT_PTP_TIMER_RD0_LO 0x96c
59871 #define A_MAC_PORT_PTP_TIMER_RD0_HI 0x970
59872 #define A_MAC_PORT_PTP_TIMER_RD1_LO 0x974
59873 #define A_MAC_PORT_PTP_TIMER_RD1_HI 0x978
59874 #define A_MAC_PORT_PTP_TIMER_WR_LO 0x97c
59875 #define A_MAC_PORT_PTP_TIMER_WR_HI 0x980
59876 #define A_MAC_PORT_PTP_TIMER_OFFSET_0 0x984
59877 #define A_MAC_PORT_PTP_TIMER_OFFSET_1 0x988
59878 #define A_MAC_PORT_PTP_TIMER_OFFSET_2 0x98c
59879 
59880 #define S_PTP_OFFSET    0
59881 #define M_PTP_OFFSET    0xffU
59882 #define V_PTP_OFFSET(x) ((x) << S_PTP_OFFSET)
59883 #define G_PTP_OFFSET(x) (((x) >> S_PTP_OFFSET) & M_PTP_OFFSET)
59884 
59885 #define A_MAC_PORT_PTP_SUM_LO 0x990
59886 #define A_MAC_PORT_PTP_SUM_HI 0x994
59887 #define A_MAC_PORT_PTP_TIMER_INCR0 0x998
59888 
59889 #define S_Y    16
59890 #define M_Y    0xffffU
59891 #define V_Y(x) ((x) << S_Y)
59892 #define G_Y(x) (((x) >> S_Y) & M_Y)
59893 
59894 #define S_X    0
59895 #define M_X    0xffffU
59896 #define V_X(x) ((x) << S_X)
59897 #define G_X(x) (((x) >> S_X) & M_X)
59898 
59899 #define A_MAC_PORT_PTP_TIMER_INCR1 0x99c
59900 
59901 #define S_Y_TICK    16
59902 #define M_Y_TICK    0xffffU
59903 #define V_Y_TICK(x) ((x) << S_Y_TICK)
59904 #define G_Y_TICK(x) (((x) >> S_Y_TICK) & M_Y_TICK)
59905 
59906 #define S_X_TICK    0
59907 #define M_X_TICK    0xffffU
59908 #define V_X_TICK(x) ((x) << S_X_TICK)
59909 #define G_X_TICK(x) (((x) >> S_X_TICK) & M_X_TICK)
59910 
59911 #define A_MAC_PORT_PTP_DRIFT_ADJUST_COUNT 0x9a0
59912 #define A_MAC_PORT_PTP_OFFSET_ADJUST_FINE 0x9a4
59913 
59914 #if 0
59915 #define S_B    16
59916 #define M_B    0xffffU
59917 #define V_B(x) ((x) << S_B)
59918 #define G_B(x) (((x) >> S_B) & M_B)
59919 #endif
59920 
59921 #define S_A    0
59922 #define M_A    0xffffU
59923 #define V_A(x) ((x) << S_A)
59924 #define G_A(x) (((x) >> S_A) & M_A)
59925 
59926 #define A_MAC_PORT_PTP_OFFSET_ADJUST_TOTAL 0x9a8
59927 #define A_MAC_PORT_PTP_CFG 0x9ac
59928 
59929 #define S_FRZ    18
59930 #define V_FRZ(x) ((x) << S_FRZ)
59931 #define F_FRZ    V_FRZ(1U)
59932 
59933 #define S_OFFSER_ADJUST_SIGN    17
59934 #define V_OFFSER_ADJUST_SIGN(x) ((x) << S_OFFSER_ADJUST_SIGN)
59935 #define F_OFFSER_ADJUST_SIGN    V_OFFSER_ADJUST_SIGN(1U)
59936 
59937 #define S_ADD_OFFSET    16
59938 #define V_ADD_OFFSET(x) ((x) << S_ADD_OFFSET)
59939 #define F_ADD_OFFSET    V_ADD_OFFSET(1U)
59940 
59941 #define S_CYCLE1    8
59942 #define M_CYCLE1    0xffU
59943 #define V_CYCLE1(x) ((x) << S_CYCLE1)
59944 #define G_CYCLE1(x) (((x) >> S_CYCLE1) & M_CYCLE1)
59945 
59946 #define S_Q    0
59947 #define M_Q    0xffU
59948 #define V_Q(x) ((x) << S_Q)
59949 #define G_Q(x) (((x) >> S_Q) & M_Q)
59950 
59951 #define S_ALARM_EN    21
59952 #define V_ALARM_EN(x) ((x) << S_ALARM_EN)
59953 #define F_ALARM_EN    V_ALARM_EN(1U)
59954 
59955 #define S_ALARM_START    20
59956 #define V_ALARM_START(x) ((x) << S_ALARM_START)
59957 #define F_ALARM_START    V_ALARM_START(1U)
59958 
59959 #define S_PPS_EN    19
59960 #define V_PPS_EN(x) ((x) << S_PPS_EN)
59961 #define F_PPS_EN    V_PPS_EN(1U)
59962 
59963 #define A_MAC_PORT_PTP_PPS 0x9b0
59964 #define A_MAC_PORT_PTP_SINGLE_ALARM 0x9b4
59965 #define A_MAC_PORT_PTP_PERIODIC_ALARM 0x9b8
59966 #define A_MAC_PORT_PTP_STATUS 0x9bc
59967 
59968 #define S_ALARM_DONE    0
59969 #define V_ALARM_DONE(x) ((x) << S_ALARM_DONE)
59970 #define F_ALARM_DONE    V_ALARM_DONE(1U)
59971 
59972 #define A_MAC_PORT_MTIP_REVISION 0xa00
59973 
59974 #define S_CUSTREV    16
59975 #define M_CUSTREV    0xffffU
59976 #define V_CUSTREV(x) ((x) << S_CUSTREV)
59977 #define G_CUSTREV(x) (((x) >> S_CUSTREV) & M_CUSTREV)
59978 
59979 #define S_VER    8
59980 #define M_VER    0xffU
59981 #define V_VER(x) ((x) << S_VER)
59982 #define G_VER(x) (((x) >> S_VER) & M_VER)
59983 
59984 #define S_MTIP_REV    0
59985 #define M_MTIP_REV    0xffU
59986 #define V_MTIP_REV(x) ((x) << S_MTIP_REV)
59987 #define G_MTIP_REV(x) (((x) >> S_MTIP_REV) & M_MTIP_REV)
59988 
59989 #define A_MAC_PORT_MTIP_SCRATCH 0xa04
59990 #define A_MAC_PORT_MTIP_COMMAND_CONFIG 0xa08
59991 
59992 #define S_TX_FLUSH_ENABLE    22
59993 #define V_TX_FLUSH_ENABLE(x) ((x) << S_TX_FLUSH_ENABLE)
59994 #define F_TX_FLUSH_ENABLE    V_TX_FLUSH_ENABLE(1U)
59995 
59996 #define S_RX_SFD_ANY    21
59997 #define V_RX_SFD_ANY(x) ((x) << S_RX_SFD_ANY)
59998 #define F_RX_SFD_ANY    V_RX_SFD_ANY(1U)
59999 
60000 #define S_PAUSE_PFC_COMP    20
60001 #define V_PAUSE_PFC_COMP(x) ((x) << S_PAUSE_PFC_COMP)
60002 #define F_PAUSE_PFC_COMP    V_PAUSE_PFC_COMP(1U)
60003 
60004 #define S_PFC_MODE    19
60005 #define V_PFC_MODE(x) ((x) << S_PFC_MODE)
60006 #define F_PFC_MODE    V_PFC_MODE(1U)
60007 
60008 #define S_RS_COL_CNT_EXT    18
60009 #define V_RS_COL_CNT_EXT(x) ((x) << S_RS_COL_CNT_EXT)
60010 #define F_RS_COL_CNT_EXT    V_RS_COL_CNT_EXT(1U)
60011 
60012 #define S_NO_LGTH_CHECK    17
60013 #define V_NO_LGTH_CHECK(x) ((x) << S_NO_LGTH_CHECK)
60014 #define F_NO_LGTH_CHECK    V_NO_LGTH_CHECK(1U)
60015 
60016 #define S_SEND_IDLE    16
60017 #define V_SEND_IDLE(x) ((x) << S_SEND_IDLE)
60018 #define F_SEND_IDLE    V_SEND_IDLE(1U)
60019 
60020 #define S_PHY_TXENA    15
60021 #define V_PHY_TXENA(x) ((x) << S_PHY_TXENA)
60022 #define F_PHY_TXENA    V_PHY_TXENA(1U)
60023 
60024 #define S_RX_ERR_DISC    14
60025 #define V_RX_ERR_DISC(x) ((x) << S_RX_ERR_DISC)
60026 #define F_RX_ERR_DISC    V_RX_ERR_DISC(1U)
60027 
60028 #define S_CMD_FRAME_ENA    13
60029 #define V_CMD_FRAME_ENA(x) ((x) << S_CMD_FRAME_ENA)
60030 #define F_CMD_FRAME_ENA    V_CMD_FRAME_ENA(1U)
60031 
60032 #define S_SW_RESET    12
60033 #define V_SW_RESET(x) ((x) << S_SW_RESET)
60034 #define F_SW_RESET    V_SW_RESET(1U)
60035 
60036 #define S_TX_PAD_EN    11
60037 #define V_TX_PAD_EN(x) ((x) << S_TX_PAD_EN)
60038 #define F_TX_PAD_EN    V_TX_PAD_EN(1U)
60039 
60040 #define S_PHY_LOOPBACK_EN    10
60041 #define V_PHY_LOOPBACK_EN(x) ((x) << S_PHY_LOOPBACK_EN)
60042 #define F_PHY_LOOPBACK_EN    V_PHY_LOOPBACK_EN(1U)
60043 
60044 #define S_TX_ADDR_INS    9
60045 #define V_TX_ADDR_INS(x) ((x) << S_TX_ADDR_INS)
60046 #define F_TX_ADDR_INS    V_TX_ADDR_INS(1U)
60047 
60048 #define S_PAUSE_IGNORE    8
60049 #define V_PAUSE_IGNORE(x) ((x) << S_PAUSE_IGNORE)
60050 #define F_PAUSE_IGNORE    V_PAUSE_IGNORE(1U)
60051 
60052 #define S_PAUSE_FWD    7
60053 #define V_PAUSE_FWD(x) ((x) << S_PAUSE_FWD)
60054 #define F_PAUSE_FWD    V_PAUSE_FWD(1U)
60055 
60056 #define S_CRC_FWD    6
60057 #define V_CRC_FWD(x) ((x) << S_CRC_FWD)
60058 #define F_CRC_FWD    V_CRC_FWD(1U)
60059 
60060 #define S_PAD_EN    5
60061 #define V_PAD_EN(x) ((x) << S_PAD_EN)
60062 #define F_PAD_EN    V_PAD_EN(1U)
60063 
60064 #define S_PROMIS_EN    4
60065 #define V_PROMIS_EN(x) ((x) << S_PROMIS_EN)
60066 #define F_PROMIS_EN    V_PROMIS_EN(1U)
60067 
60068 #define S_WAN_MODE    3
60069 #define V_WAN_MODE(x) ((x) << S_WAN_MODE)
60070 #define F_WAN_MODE    V_WAN_MODE(1U)
60071 
60072 #define S_RX_ENA    1
60073 #define V_RX_ENA(x) ((x) << S_RX_ENA)
60074 #define F_RX_ENA    V_RX_ENA(1U)
60075 
60076 #define S_TX_ENA    0
60077 #define V_TX_ENA(x) ((x) << S_TX_ENA)
60078 #define F_TX_ENA    V_TX_ENA(1U)
60079 
60080 #define A_MAC_PORT_MTIP_MAC_ADDR_0 0xa0c
60081 #define A_MAC_PORT_MTIP_MAC_ADDR_1 0xa10
60082 
60083 #define S_MACADDRHI    0
60084 #define M_MACADDRHI    0xffffU
60085 #define V_MACADDRHI(x) ((x) << S_MACADDRHI)
60086 #define G_MACADDRHI(x) (((x) >> S_MACADDRHI) & M_MACADDRHI)
60087 
60088 #define A_MAC_PORT_MTIP_FRM_LENGTH 0xa14
60089 
60090 #define S_LEN    0
60091 #define M_LEN    0xffffU
60092 #define V_LEN(x) ((x) << S_LEN)
60093 #define G_LEN(x) (((x) >> S_LEN) & M_LEN)
60094 
60095 #define A_MAC_PORT_MTIP_RX_FIFO_SECTIONS 0xa1c
60096 
60097 #define S_AVAIL    16
60098 #define M_AVAIL    0xffffU
60099 #define V_AVAIL(x) ((x) << S_AVAIL)
60100 #define G_AVAIL(x) (((x) >> S_AVAIL) & M_AVAIL)
60101 
60102 #define S_EMPTY    0
60103 #define M_EMPTY    0xffffU
60104 #define V_EMPTY(x) ((x) << S_EMPTY)
60105 #define G_EMPTY(x) (((x) >> S_EMPTY) & M_EMPTY)
60106 
60107 #define A_MAC_PORT_MTIP_TX_FIFO_SECTIONS 0xa20
60108 #define A_MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E 0xa24
60109 
60110 #define S_ALMSTFULL    16
60111 #define M_ALMSTFULL    0xffffU
60112 #define V_ALMSTFULL(x) ((x) << S_ALMSTFULL)
60113 #define G_ALMSTFULL(x) (((x) >> S_ALMSTFULL) & M_ALMSTFULL)
60114 
60115 #define S_ALMSTEMPTY    0
60116 #define M_ALMSTEMPTY    0xffffU
60117 #define V_ALMSTEMPTY(x) ((x) << S_ALMSTEMPTY)
60118 #define G_ALMSTEMPTY(x) (((x) >> S_ALMSTEMPTY) & M_ALMSTEMPTY)
60119 
60120 #define A_MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E 0xa28
60121 #define A_MAC_PORT_MTIP_HASHTABLE_LOAD 0xa2c
60122 
60123 #define S_ENABLE_MCAST_RX    8
60124 #define V_ENABLE_MCAST_RX(x) ((x) << S_ENABLE_MCAST_RX)
60125 #define F_ENABLE_MCAST_RX    V_ENABLE_MCAST_RX(1U)
60126 
60127 #define S_HASHTABLE_ADDR    0
60128 #define M_HASHTABLE_ADDR    0x3fU
60129 #define V_HASHTABLE_ADDR(x) ((x) << S_HASHTABLE_ADDR)
60130 #define G_HASHTABLE_ADDR(x) (((x) >> S_HASHTABLE_ADDR) & M_HASHTABLE_ADDR)
60131 
60132 #define A_MAC_PORT_MTIP_MAC_STATUS 0xa40
60133 
60134 #define S_TS_AVAIL    3
60135 #define V_TS_AVAIL(x) ((x) << S_TS_AVAIL)
60136 #define F_TS_AVAIL    V_TS_AVAIL(1U)
60137 
60138 #define S_PHY_LOS    2
60139 #define V_PHY_LOS(x) ((x) << S_PHY_LOS)
60140 #define F_PHY_LOS    V_PHY_LOS(1U)
60141 
60142 #define S_RX_REM_FAULT    1
60143 #define V_RX_REM_FAULT(x) ((x) << S_RX_REM_FAULT)
60144 #define F_RX_REM_FAULT    V_RX_REM_FAULT(1U)
60145 
60146 #define S_RX_LOC_FAULT    0
60147 #define V_RX_LOC_FAULT(x) ((x) << S_RX_LOC_FAULT)
60148 #define F_RX_LOC_FAULT    V_RX_LOC_FAULT(1U)
60149 
60150 #define A_MAC_PORT_MTIP_TX_IPG_LENGTH 0xa44
60151 
60152 #define S_IPG    0
60153 #define M_IPG    0x7fU
60154 #define V_IPG(x) ((x) << S_IPG)
60155 #define G_IPG(x) (((x) >> S_IPG) & M_IPG)
60156 
60157 #define A_MAC_PORT_MTIP_MAC_CREDIT_TRIGGER 0xa48
60158 
60159 #define S_RXFIFORST    0
60160 #define V_RXFIFORST(x) ((x) << S_RXFIFORST)
60161 #define F_RXFIFORST    V_RXFIFORST(1U)
60162 
60163 #define A_MAC_PORT_MTIP_INIT_CREDIT 0xa4c
60164 
60165 #define S_MACCRDRST    0
60166 #define M_MACCRDRST    0xffU
60167 #define V_MACCRDRST(x) ((x) << S_MACCRDRST)
60168 #define G_MACCRDRST(x) (((x) >> S_MACCRDRST) & M_MACCRDRST)
60169 
60170 #define A_MAC_PORT_MTIP_CURRENT_CREDIT 0xa50
60171 
60172 #define S_INITCREDIT    0
60173 #define M_INITCREDIT    0xffU
60174 #define V_INITCREDIT(x) ((x) << S_INITCREDIT)
60175 #define G_INITCREDIT(x) (((x) >> S_INITCREDIT) & M_INITCREDIT)
60176 
60177 #define A_MAC_PORT_RX_PAUSE_STATUS 0xa74
60178 
60179 #define S_STATUS    0
60180 #define M_STATUS    0xffU
60181 #define V_STATUS(x) ((x) << S_STATUS)
60182 #define G_STATUS(x) (((x) >> S_STATUS) & M_STATUS)
60183 
60184 #define A_MAC_PORT_MTIP_TS_TIMESTAMP 0xa7c
60185 #define A_MAC_PORT_AFRAMESTRANSMITTEDOK 0xa80
60186 #define A_MAC_PORT_AFRAMESTRANSMITTEDOKHI 0xa84
60187 #define A_MAC_PORT_AFRAMESRECEIVEDOK 0xa88
60188 #define A_MAC_PORT_AFRAMESRECEIVEDOKHI 0xa8c
60189 #define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS 0xa90
60190 #define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI 0xa94
60191 #define A_MAC_PORT_AALIGNMENTERRORS 0xa98
60192 #define A_MAC_PORT_AALIGNMENTERRORSHI 0xa9c
60193 #define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED 0xaa0
60194 #define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI 0xaa4
60195 #define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED 0xaa8
60196 #define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI 0xaac
60197 #define A_MAC_PORT_AFRAMETOOLONGERRORS 0xab0
60198 #define A_MAC_PORT_AFRAMETOOLONGERRORSHI 0xab4
60199 #define A_MAC_PORT_AINRANGELENGTHERRORS 0xab8
60200 #define A_MAC_PORT_AINRANGELENGTHERRORSHI 0xabc
60201 #define A_MAC_PORT_VLANTRANSMITTEDOK 0xac0
60202 #define A_MAC_PORT_VLANTRANSMITTEDOKHI 0xac4
60203 #define A_MAC_PORT_VLANRECEIVEDOK 0xac8
60204 #define A_MAC_PORT_VLANRECEIVEDOKHI 0xacc
60205 #define A_MAC_PORT_AOCTETSTRANSMITTEDOK 0xad0
60206 #define A_MAC_PORT_AOCTETSTRANSMITTEDOKHI 0xad4
60207 #define A_MAC_PORT_AOCTETSRECEIVEDOK 0xad8
60208 #define A_MAC_PORT_AOCTETSRECEIVEDOKHI 0xadc
60209 #define A_MAC_PORT_IFINUCASTPKTS 0xae0
60210 #define A_MAC_PORT_IFINUCASTPKTSHI 0xae4
60211 #define A_MAC_PORT_IFINMULTICASTPKTS 0xae8
60212 #define A_MAC_PORT_IFINMULTICASTPKTSHI 0xaec
60213 #define A_MAC_PORT_IFINBROADCASTPKTS 0xaf0
60214 #define A_MAC_PORT_IFINBROADCASTPKTSHI 0xaf4
60215 #define A_MAC_PORT_IFOUTERRORS 0xaf8
60216 #define A_MAC_PORT_IFOUTERRORSHI 0xafc
60217 #define A_MAC_PORT_IFOUTUCASTPKTS 0xb08
60218 #define A_MAC_PORT_IFOUTUCASTPKTSHI 0xb0c
60219 #define A_MAC_PORT_IFOUTMULTICASTPKTS 0xb10
60220 #define A_MAC_PORT_IFOUTMULTICASTPKTSHI 0xb14
60221 #define A_MAC_PORT_IFOUTBROADCASTPKTS 0xb18
60222 #define A_MAC_PORT_IFOUTBROADCASTPKTSHI 0xb1c
60223 #define A_MAC_PORT_ETHERSTATSDROPEVENTS 0xb20
60224 #define A_MAC_PORT_ETHERSTATSDROPEVENTSHI 0xb24
60225 #define A_MAC_PORT_ETHERSTATSOCTETS 0xb28
60226 #define A_MAC_PORT_ETHERSTATSOCTETSHI 0xb2c
60227 #define A_MAC_PORT_ETHERSTATSPKTS 0xb30
60228 #define A_MAC_PORT_ETHERSTATSPKTSHI 0xb34
60229 #define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTS 0xb38
60230 #define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI 0xb3c
60231 #define A_MAC_PORT_ETHERSTATSPKTS64OCTETS 0xb40
60232 #define A_MAC_PORT_ETHERSTATSPKTS64OCTETSHI 0xb44
60233 #define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETS 0xb48
60234 #define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI 0xb4c
60235 #define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETS 0xb50
60236 #define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI 0xb54
60237 #define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETS 0xb58
60238 #define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI 0xb5c
60239 #define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS 0xb60
60240 #define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI 0xb64
60241 #define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS 0xb68
60242 #define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI 0xb6c
60243 #define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS 0xb70
60244 #define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI 0xb74
60245 #define A_MAC_PORT_ETHERSTATSOVERSIZEPKTS 0xb78
60246 #define A_MAC_PORT_ETHERSTATSOVERSIZEPKTSHI 0xb7c
60247 #define A_MAC_PORT_ETHERSTATSJABBERS 0xb80
60248 #define A_MAC_PORT_ETHERSTATSJABBERSHI 0xb84
60249 #define A_MAC_PORT_ETHERSTATSFRAGMENTS 0xb88
60250 #define A_MAC_PORT_ETHERSTATSFRAGMENTSHI 0xb8c
60251 #define A_MAC_PORT_IFINERRORS 0xb90
60252 #define A_MAC_PORT_IFINERRORSHI 0xb94
60253 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0 0xb98
60254 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI 0xb9c
60255 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1 0xba0
60256 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI 0xba4
60257 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2 0xba8
60258 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI 0xbac
60259 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3 0xbb0
60260 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI 0xbb4
60261 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4 0xbb8
60262 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI 0xbbc
60263 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5 0xbc0
60264 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI 0xbc4
60265 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6 0xbc8
60266 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI 0xbcc
60267 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7 0xbd0
60268 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI 0xbd4
60269 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0 0xbd8
60270 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI 0xbdc
60271 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1 0xbe0
60272 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI 0xbe4
60273 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2 0xbe8
60274 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI 0xbec
60275 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3 0xbf0
60276 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI 0xbf4
60277 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4 0xbf8
60278 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI 0xbfc
60279 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5 0xc00
60280 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI 0xc04
60281 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6 0xc08
60282 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI 0xc0c
60283 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7 0xc10
60284 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI 0xc14
60285 #define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTED 0xc18
60286 #define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI 0xc1c
60287 #define A_MAC_PORT_AMACCONTROLFRAMESRECEIVED 0xc20
60288 #define A_MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI 0xc24
60289 #define A_MAC_PORT_MTIP_SGMII_CONTROL 0xd00
60290 
60291 #define S_RESET    15
60292 #define V_RESET(x) ((x) << S_RESET)
60293 #define F_RESET    V_RESET(1U)
60294 
60295 #define S_LOOPBACK    14
60296 #define V_LOOPBACK(x) ((x) << S_LOOPBACK)
60297 #define F_LOOPBACK    V_LOOPBACK(1U)
60298 
60299 #define S_SPPEDSEL1    13
60300 #define V_SPPEDSEL1(x) ((x) << S_SPPEDSEL1)
60301 #define F_SPPEDSEL1    V_SPPEDSEL1(1U)
60302 
60303 #define S_AN_EN    12
60304 #define V_AN_EN(x) ((x) << S_AN_EN)
60305 #define F_AN_EN    V_AN_EN(1U)
60306 
60307 #define S_PWRDWN    11
60308 #define V_PWRDWN(x) ((x) << S_PWRDWN)
60309 #define F_PWRDWN    V_PWRDWN(1U)
60310 
60311 #define S_ISOLATE    10
60312 #define V_ISOLATE(x) ((x) << S_ISOLATE)
60313 #define F_ISOLATE    V_ISOLATE(1U)
60314 
60315 #define S_AN_RESTART    9
60316 #define V_AN_RESTART(x) ((x) << S_AN_RESTART)
60317 #define F_AN_RESTART    V_AN_RESTART(1U)
60318 
60319 #define S_DPLX    8
60320 #define V_DPLX(x) ((x) << S_DPLX)
60321 #define F_DPLX    V_DPLX(1U)
60322 
60323 #define S_COLLISIONTEST    7
60324 #define V_COLLISIONTEST(x) ((x) << S_COLLISIONTEST)
60325 #define F_COLLISIONTEST    V_COLLISIONTEST(1U)
60326 
60327 #define S_SPEEDSEL0    6
60328 #define V_SPEEDSEL0(x) ((x) << S_SPEEDSEL0)
60329 #define F_SPEEDSEL0    V_SPEEDSEL0(1U)
60330 
60331 #define A_MAC_PORT_MTIP_1G10G_REVISION 0xd00
60332 
60333 #define S_VER_1G10G    8
60334 #define M_VER_1G10G    0xffU
60335 #define V_VER_1G10G(x) ((x) << S_VER_1G10G)
60336 #define G_VER_1G10G(x) (((x) >> S_VER_1G10G) & M_VER_1G10G)
60337 
60338 #define S_REV_1G10G    0
60339 #define M_REV_1G10G    0xffU
60340 #define V_REV_1G10G(x) ((x) << S_REV_1G10G)
60341 #define G_REV_1G10G(x) (((x) >> S_REV_1G10G) & M_REV_1G10G)
60342 
60343 #define A_MAC_PORT_MTIP_SGMII_STATUS 0xd04
60344 
60345 #define S_100BASET4    15
60346 #define V_100BASET4(x) ((x) << S_100BASET4)
60347 #define F_100BASET4    V_100BASET4(1U)
60348 
60349 #define S_100BASEXFULLDPLX    14
60350 #define V_100BASEXFULLDPLX(x) ((x) << S_100BASEXFULLDPLX)
60351 #define F_100BASEXFULLDPLX    V_100BASEXFULLDPLX(1U)
60352 
60353 #define S_100BASEXHALFDPLX    13
60354 #define V_100BASEXHALFDPLX(x) ((x) << S_100BASEXHALFDPLX)
60355 #define F_100BASEXHALFDPLX    V_100BASEXHALFDPLX(1U)
60356 
60357 #define S_10MBPSFULLDPLX    12
60358 #define V_10MBPSFULLDPLX(x) ((x) << S_10MBPSFULLDPLX)
60359 #define F_10MBPSFULLDPLX    V_10MBPSFULLDPLX(1U)
60360 
60361 #define S_10MBPSHALFDPLX    11
60362 #define V_10MBPSHALFDPLX(x) ((x) << S_10MBPSHALFDPLX)
60363 #define F_10MBPSHALFDPLX    V_10MBPSHALFDPLX(1U)
60364 
60365 #define S_100BASET2FULLDPLX    10
60366 #define V_100BASET2FULLDPLX(x) ((x) << S_100BASET2FULLDPLX)
60367 #define F_100BASET2FULLDPLX    V_100BASET2FULLDPLX(1U)
60368 
60369 #define S_100BASET2HALFDPLX    9
60370 #define V_100BASET2HALFDPLX(x) ((x) << S_100BASET2HALFDPLX)
60371 #define F_100BASET2HALFDPLX    V_100BASET2HALFDPLX(1U)
60372 
60373 #define S_EXTDSTATUS    8
60374 #define V_EXTDSTATUS(x) ((x) << S_EXTDSTATUS)
60375 #define F_EXTDSTATUS    V_EXTDSTATUS(1U)
60376 
60377 #define S_SGMII_REM_FAULT    4
60378 #define V_SGMII_REM_FAULT(x) ((x) << S_SGMII_REM_FAULT)
60379 #define F_SGMII_REM_FAULT    V_SGMII_REM_FAULT(1U)
60380 
60381 #define S_JABBERDETECT    1
60382 #define V_JABBERDETECT(x) ((x) << S_JABBERDETECT)
60383 #define F_JABBERDETECT    V_JABBERDETECT(1U)
60384 
60385 #define S_EXTDCAPABILITY    0
60386 #define V_EXTDCAPABILITY(x) ((x) << S_EXTDCAPABILITY)
60387 #define F_EXTDCAPABILITY    V_EXTDCAPABILITY(1U)
60388 
60389 #define A_MAC_PORT_MTIP_1G10G_SCRATCH 0xd04
60390 #define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 0xd08
60391 #define A_MAC_PORT_MTIP_1G10G_COMMAND_CONFIG 0xd08
60392 
60393 #define S_SHORT_DISCARD    25
60394 #define V_SHORT_DISCARD(x) ((x) << S_SHORT_DISCARD)
60395 #define F_SHORT_DISCARD    V_SHORT_DISCARD(1U)
60396 
60397 #define S_REG_LOWP_RXEMPTY    24
60398 #define V_REG_LOWP_RXEMPTY(x) ((x) << S_REG_LOWP_RXEMPTY)
60399 #define F_REG_LOWP_RXEMPTY    V_REG_LOWP_RXEMPTY(1U)
60400 
60401 #define S_TX_LOWP_ENA    23
60402 #define V_TX_LOWP_ENA(x) ((x) << S_TX_LOWP_ENA)
60403 #define F_TX_LOWP_ENA    V_TX_LOWP_ENA(1U)
60404 
60405 #define S_TX_FLUSH_EN    22
60406 #define V_TX_FLUSH_EN(x) ((x) << S_TX_FLUSH_EN)
60407 #define F_TX_FLUSH_EN    V_TX_FLUSH_EN(1U)
60408 
60409 #define S_SFD_ANY    21
60410 #define V_SFD_ANY(x) ((x) << S_SFD_ANY)
60411 #define F_SFD_ANY    V_SFD_ANY(1U)
60412 
60413 #define S_COL_CNT_EXT    18
60414 #define V_COL_CNT_EXT(x) ((x) << S_COL_CNT_EXT)
60415 #define F_COL_CNT_EXT    V_COL_CNT_EXT(1U)
60416 
60417 #define S_FORCE_SEND_IDLE    16
60418 #define V_FORCE_SEND_IDLE(x) ((x) << S_FORCE_SEND_IDLE)
60419 #define F_FORCE_SEND_IDLE    V_FORCE_SEND_IDLE(1U)
60420 
60421 #define S_CNTL_FRM_ENA    13
60422 #define V_CNTL_FRM_ENA(x) ((x) << S_CNTL_FRM_ENA)
60423 #define F_CNTL_FRM_ENA    V_CNTL_FRM_ENA(1U)
60424 
60425 #define S_RX_ENAMAC    1
60426 #define V_RX_ENAMAC(x) ((x) << S_RX_ENAMAC)
60427 #define F_RX_ENAMAC    V_RX_ENAMAC(1U)
60428 
60429 #define S_TX_ENAMAC    0
60430 #define V_TX_ENAMAC(x) ((x) << S_TX_ENAMAC)
60431 #define F_TX_ENAMAC    V_TX_ENAMAC(1U)
60432 
60433 #define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 0xd0c
60434 #define A_MAC_PORT_MTIP_1G10G_MAC_ADDR_0 0xd0c
60435 #define A_MAC_PORT_MTIP_SGMII_DEV_ABILITY 0xd10
60436 
60437 #define S_RF2    13
60438 #define V_RF2(x) ((x) << S_RF2)
60439 #define F_RF2    V_RF2(1U)
60440 
60441 #define S_RF1    12
60442 #define V_RF1(x) ((x) << S_RF1)
60443 #define F_RF1    V_RF1(1U)
60444 
60445 #define S_PS2    8
60446 #define V_PS2(x) ((x) << S_PS2)
60447 #define F_PS2    V_PS2(1U)
60448 
60449 #define S_PS1    7
60450 #define V_PS1(x) ((x) << S_PS1)
60451 #define F_PS1    V_PS1(1U)
60452 
60453 #define S_HD    6
60454 #define V_HD(x) ((x) << S_HD)
60455 #define F_HD    V_HD(1U)
60456 
60457 #define S_FD    5
60458 #define V_FD(x) ((x) << S_FD)
60459 #define F_FD    V_FD(1U)
60460 
60461 #define A_MAC_PORT_MTIP_1G10G_MAC_ADDR_1 0xd10
60462 #define A_MAC_PORT_MTIP_SGMII_PARTNER_ABILITY 0xd14
60463 
60464 #define S_CULINKSTATUS    15
60465 #define V_CULINKSTATUS(x) ((x) << S_CULINKSTATUS)
60466 #define F_CULINKSTATUS    V_CULINKSTATUS(1U)
60467 
60468 #define S_CUDPLXSTATUS    12
60469 #define V_CUDPLXSTATUS(x) ((x) << S_CUDPLXSTATUS)
60470 #define F_CUDPLXSTATUS    V_CUDPLXSTATUS(1U)
60471 
60472 #define S_CUSPEED    10
60473 #define M_CUSPEED    0x3U
60474 #define V_CUSPEED(x) ((x) << S_CUSPEED)
60475 #define G_CUSPEED(x) (((x) >> S_CUSPEED) & M_CUSPEED)
60476 
60477 #define A_MAC_PORT_MTIP_1G10G_FRM_LENGTH_TX_MTU 0xd14
60478 
60479 #define S_SET_LEN    16
60480 #define M_SET_LEN    0xffffU
60481 #define V_SET_LEN(x) ((x) << S_SET_LEN)
60482 #define G_SET_LEN(x) (((x) >> S_SET_LEN) & M_SET_LEN)
60483 
60484 #define S_FRM_LEN_SET    0
60485 #define M_FRM_LEN_SET    0xffffU
60486 #define V_FRM_LEN_SET(x) ((x) << S_FRM_LEN_SET)
60487 #define G_FRM_LEN_SET(x) (((x) >> S_FRM_LEN_SET) & M_FRM_LEN_SET)
60488 
60489 #define A_MAC_PORT_MTIP_SGMII_AN_EXPANSION 0xd18
60490 
60491 #define S_PGRCVD    1
60492 #define V_PGRCVD(x) ((x) << S_PGRCVD)
60493 #define F_PGRCVD    V_PGRCVD(1U)
60494 
60495 #define S_REALTIMEPGRCVD    0
60496 #define V_REALTIMEPGRCVD(x) ((x) << S_REALTIMEPGRCVD)
60497 #define F_REALTIMEPGRCVD    V_REALTIMEPGRCVD(1U)
60498 
60499 #define A_MAC_PORT_MTIP_SGMII_DEVICE_NP 0xd1c
60500 #define A_MAC_PORT_MTIP_1G10G_RX_FIFO_SECTIONS 0xd1c
60501 
60502 #define S_RX1G10G_EMPTY    16
60503 #define M_RX1G10G_EMPTY    0xffffU
60504 #define V_RX1G10G_EMPTY(x) ((x) << S_RX1G10G_EMPTY)
60505 #define G_RX1G10G_EMPTY(x) (((x) >> S_RX1G10G_EMPTY) & M_RX1G10G_EMPTY)
60506 
60507 #define S_RX1G10G_AVAIL    0
60508 #define M_RX1G10G_AVAIL    0xffffU
60509 #define V_RX1G10G_AVAIL(x) ((x) << S_RX1G10G_AVAIL)
60510 #define G_RX1G10G_AVAIL(x) (((x) >> S_RX1G10G_AVAIL) & M_RX1G10G_AVAIL)
60511 
60512 #define A_MAC_PORT_MTIP_SGMII_PARTNER_NP 0xd20
60513 #define A_MAC_PORT_MTIP_1G10G_TX_FIFO_SECTIONS 0xd20
60514 
60515 #define S_TX1G10G_EMPTY    16
60516 #define M_TX1G10G_EMPTY    0xffffU
60517 #define V_TX1G10G_EMPTY(x) ((x) << S_TX1G10G_EMPTY)
60518 #define G_TX1G10G_EMPTY(x) (((x) >> S_TX1G10G_EMPTY) & M_TX1G10G_EMPTY)
60519 
60520 #define S_TX1G10G_AVAIL    0
60521 #define M_TX1G10G_AVAIL    0xffffU
60522 #define V_TX1G10G_AVAIL(x) ((x) << S_TX1G10G_AVAIL)
60523 #define G_TX1G10G_AVAIL(x) (((x) >> S_TX1G10G_AVAIL) & M_TX1G10G_AVAIL)
60524 
60525 #define A_MAC_PORT_MTIP_1G10G_RX_FIFO_ALMOST_F_E 0xd24
60526 
60527 #define S_ALMOSTFULL    16
60528 #define M_ALMOSTFULL    0xffffU
60529 #define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL)
60530 #define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL)
60531 
60532 #define S_ALMOSTEMPTY    0
60533 #define M_ALMOSTEMPTY    0xffffU
60534 #define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY)
60535 #define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY)
60536 
60537 #define A_MAC_PORT_MTIP_1G10G_TX_FIFO_ALMOST_F_E 0xd28
60538 #define A_MAC_PORT_MTIP_1G10G_HASHTABLE_LOAD 0xd2c
60539 #define A_MAC_PORT_MTIP_1G10G_MDIO_CFG_STATUS 0xd30
60540 
60541 #define S_CLK_DIVISOR    7
60542 #define M_CLK_DIVISOR    0x1ffU
60543 #define V_CLK_DIVISOR(x) ((x) << S_CLK_DIVISOR)
60544 #define G_CLK_DIVISOR(x) (((x) >> S_CLK_DIVISOR) & M_CLK_DIVISOR)
60545 
60546 #define S_ENA_CLAUSE    6
60547 #define V_ENA_CLAUSE(x) ((x) << S_ENA_CLAUSE)
60548 #define F_ENA_CLAUSE    V_ENA_CLAUSE(1U)
60549 
60550 #define S_PREAMBLE_DISABLE    5
60551 #define V_PREAMBLE_DISABLE(x) ((x) << S_PREAMBLE_DISABLE)
60552 #define F_PREAMBLE_DISABLE    V_PREAMBLE_DISABLE(1U)
60553 
60554 #define S_HOLD_TIME_SETTING    2
60555 #define M_HOLD_TIME_SETTING    0x7U
60556 #define V_HOLD_TIME_SETTING(x) ((x) << S_HOLD_TIME_SETTING)
60557 #define G_HOLD_TIME_SETTING(x) (((x) >> S_HOLD_TIME_SETTING) & M_HOLD_TIME_SETTING)
60558 
60559 #define S_MDIO_READ_ERROR    1
60560 #define V_MDIO_READ_ERROR(x) ((x) << S_MDIO_READ_ERROR)
60561 #define F_MDIO_READ_ERROR    V_MDIO_READ_ERROR(1U)
60562 
60563 #define A_MAC_PORT_MTIP_1G10G_MDIO_COMMAND 0xd34
60564 
60565 #define S_READ_MODE    15
60566 #define V_READ_MODE(x) ((x) << S_READ_MODE)
60567 #define F_READ_MODE    V_READ_MODE(1U)
60568 
60569 #define S_POST_INCR_READ    14
60570 #define V_POST_INCR_READ(x) ((x) << S_POST_INCR_READ)
60571 #define F_POST_INCR_READ    V_POST_INCR_READ(1U)
60572 
60573 #define S_PORT_PHY_ADDR    5
60574 #define M_PORT_PHY_ADDR    0x1fU
60575 #define V_PORT_PHY_ADDR(x) ((x) << S_PORT_PHY_ADDR)
60576 #define G_PORT_PHY_ADDR(x) (((x) >> S_PORT_PHY_ADDR) & M_PORT_PHY_ADDR)
60577 
60578 #define S_DEVICE_REG_ADDR    0
60579 #define M_DEVICE_REG_ADDR    0x1fU
60580 #define V_DEVICE_REG_ADDR(x) ((x) << S_DEVICE_REG_ADDR)
60581 #define G_DEVICE_REG_ADDR(x) (((x) >> S_DEVICE_REG_ADDR) & M_DEVICE_REG_ADDR)
60582 
60583 #define A_MAC_PORT_MTIP_1G10G_MDIO_DATA 0xd38
60584 
60585 #define S_MDIO_DATA    0
60586 #define M_MDIO_DATA    0xffffU
60587 #define V_MDIO_DATA(x) ((x) << S_MDIO_DATA)
60588 #define G_MDIO_DATA(x) (((x) >> S_MDIO_DATA) & M_MDIO_DATA)
60589 
60590 #define A_MAC_PORT_MTIP_SGMII_EXTENDED_STATUS 0xd3c
60591 #define A_MAC_PORT_MTIP_1G10G_MDIO_REGADDR 0xd3c
60592 #define A_MAC_PORT_MTIP_1G10G_STATUS 0xd40
60593 
60594 #define S_RX_LINT_FAULT    7
60595 #define V_RX_LINT_FAULT(x) ((x) << S_RX_LINT_FAULT)
60596 #define F_RX_LINT_FAULT    V_RX_LINT_FAULT(1U)
60597 
60598 #define S_RX_EMPTY    6
60599 #define V_RX_EMPTY(x) ((x) << S_RX_EMPTY)
60600 #define F_RX_EMPTY    V_RX_EMPTY(1U)
60601 
60602 #define S_TX_EMPTY    5
60603 #define V_TX_EMPTY(x) ((x) << S_TX_EMPTY)
60604 #define F_TX_EMPTY    V_TX_EMPTY(1U)
60605 
60606 #define S_RX_LOWP    4
60607 #define V_RX_LOWP(x) ((x) << S_RX_LOWP)
60608 #define F_RX_LOWP    V_RX_LOWP(1U)
60609 
60610 #define A_MAC_PORT_MTIP_1G10G_TX_IPG_LENGTH 0xd44
60611 #define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_LO 0xd48
60612 
60613 #define S_COUNT_LO    0
60614 #define M_COUNT_LO    0xffffU
60615 #define V_COUNT_LO(x) ((x) << S_COUNT_LO)
60616 #define G_COUNT_LO(x) (((x) >> S_COUNT_LO) & M_COUNT_LO)
60617 
60618 #define A_MAC_PORT_MTIP_1G10G_CREDIT_TRIGGER 0xd48
60619 #define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 0xd4c
60620 
60621 #define S_COUNT_HI    0
60622 #define M_COUNT_HI    0x1fU
60623 #define V_COUNT_HI(x) ((x) << S_COUNT_HI)
60624 #define G_COUNT_HI(x) (((x) >> S_COUNT_HI) & M_COUNT_HI)
60625 
60626 #define A_MAC_PORT_MTIP_1G10G_INIT_CREDIT 0xd4c
60627 #define A_MAC_PORT_MTIP_SGMII_IF_MODE 0xd50
60628 
60629 #define S_SGMII_PCS_ENABLE    5
60630 #define V_SGMII_PCS_ENABLE(x) ((x) << S_SGMII_PCS_ENABLE)
60631 #define F_SGMII_PCS_ENABLE    V_SGMII_PCS_ENABLE(1U)
60632 
60633 #define S_SGMII_HDUPLEX    4
60634 #define V_SGMII_HDUPLEX(x) ((x) << S_SGMII_HDUPLEX)
60635 #define F_SGMII_HDUPLEX    V_SGMII_HDUPLEX(1U)
60636 
60637 #define S_SGMII_SPEED    2
60638 #define M_SGMII_SPEED    0x3U
60639 #define V_SGMII_SPEED(x) ((x) << S_SGMII_SPEED)
60640 #define G_SGMII_SPEED(x) (((x) >> S_SGMII_SPEED) & M_SGMII_SPEED)
60641 
60642 #define S_USE_SGMII_AN    1
60643 #define V_USE_SGMII_AN(x) ((x) << S_USE_SGMII_AN)
60644 #define F_USE_SGMII_AN    V_USE_SGMII_AN(1U)
60645 
60646 #define S_SGMII_ENA    0
60647 #define V_SGMII_ENA(x) ((x) << S_SGMII_ENA)
60648 #define F_SGMII_ENA    V_SGMII_ENA(1U)
60649 
60650 #define A_MAC_PORT_MTIP_1G10G_CL01_PAUSE_QUANTA 0xd54
60651 
60652 #define S_CL1_PAUSE_QUANTA    16
60653 #define M_CL1_PAUSE_QUANTA    0xffffU
60654 #define V_CL1_PAUSE_QUANTA(x) ((x) << S_CL1_PAUSE_QUANTA)
60655 #define G_CL1_PAUSE_QUANTA(x) (((x) >> S_CL1_PAUSE_QUANTA) & M_CL1_PAUSE_QUANTA)
60656 
60657 #define S_CL0_PAUSE_QUANTA    0
60658 #define M_CL0_PAUSE_QUANTA    0xffffU
60659 #define V_CL0_PAUSE_QUANTA(x) ((x) << S_CL0_PAUSE_QUANTA)
60660 #define G_CL0_PAUSE_QUANTA(x) (((x) >> S_CL0_PAUSE_QUANTA) & M_CL0_PAUSE_QUANTA)
60661 
60662 #define A_MAC_PORT_MTIP_1G10G_CL23_PAUSE_QUANTA 0xd58
60663 
60664 #define S_CL3_PAUSE_QUANTA    16
60665 #define M_CL3_PAUSE_QUANTA    0xffffU
60666 #define V_CL3_PAUSE_QUANTA(x) ((x) << S_CL3_PAUSE_QUANTA)
60667 #define G_CL3_PAUSE_QUANTA(x) (((x) >> S_CL3_PAUSE_QUANTA) & M_CL3_PAUSE_QUANTA)
60668 
60669 #define S_CL2_PAUSE_QUANTA    0
60670 #define M_CL2_PAUSE_QUANTA    0xffffU
60671 #define V_CL2_PAUSE_QUANTA(x) ((x) << S_CL2_PAUSE_QUANTA)
60672 #define G_CL2_PAUSE_QUANTA(x) (((x) >> S_CL2_PAUSE_QUANTA) & M_CL2_PAUSE_QUANTA)
60673 
60674 #define A_MAC_PORT_MTIP_1G10G_CL45_PAUSE_QUANTA 0xd5c
60675 
60676 #define S_CL5_PAUSE_QUANTA    16
60677 #define M_CL5_PAUSE_QUANTA    0xffffU
60678 #define V_CL5_PAUSE_QUANTA(x) ((x) << S_CL5_PAUSE_QUANTA)
60679 #define G_CL5_PAUSE_QUANTA(x) (((x) >> S_CL5_PAUSE_QUANTA) & M_CL5_PAUSE_QUANTA)
60680 
60681 #define S_CL4_PAUSE_QUANTA    0
60682 #define M_CL4_PAUSE_QUANTA    0xffffU
60683 #define V_CL4_PAUSE_QUANTA(x) ((x) << S_CL4_PAUSE_QUANTA)
60684 #define G_CL4_PAUSE_QUANTA(x) (((x) >> S_CL4_PAUSE_QUANTA) & M_CL4_PAUSE_QUANTA)
60685 
60686 #define A_MAC_PORT_MTIP_1G10G_CL67_PAUSE_QUANTA 0xd60
60687 
60688 #define S_CL7_PAUSE_QUANTA    16
60689 #define M_CL7_PAUSE_QUANTA    0xffffU
60690 #define V_CL7_PAUSE_QUANTA(x) ((x) << S_CL7_PAUSE_QUANTA)
60691 #define G_CL7_PAUSE_QUANTA(x) (((x) >> S_CL7_PAUSE_QUANTA) & M_CL7_PAUSE_QUANTA)
60692 
60693 #define S_CL6_PAUSE_QUANTA    0
60694 #define M_CL6_PAUSE_QUANTA    0xffffU
60695 #define V_CL6_PAUSE_QUANTA(x) ((x) << S_CL6_PAUSE_QUANTA)
60696 #define G_CL6_PAUSE_QUANTA(x) (((x) >> S_CL6_PAUSE_QUANTA) & M_CL6_PAUSE_QUANTA)
60697 
60698 #define A_MAC_PORT_MTIP_1G10G_CL01_QUANTA_THRESH 0xd64
60699 
60700 #define S_CL1_QUANTA_THRESH    16
60701 #define M_CL1_QUANTA_THRESH    0xffffU
60702 #define V_CL1_QUANTA_THRESH(x) ((x) << S_CL1_QUANTA_THRESH)
60703 #define G_CL1_QUANTA_THRESH(x) (((x) >> S_CL1_QUANTA_THRESH) & M_CL1_QUANTA_THRESH)
60704 
60705 #define S_CL0_QUANTA_THRESH    0
60706 #define M_CL0_QUANTA_THRESH    0xffffU
60707 #define V_CL0_QUANTA_THRESH(x) ((x) << S_CL0_QUANTA_THRESH)
60708 #define G_CL0_QUANTA_THRESH(x) (((x) >> S_CL0_QUANTA_THRESH) & M_CL0_QUANTA_THRESH)
60709 
60710 #define A_MAC_PORT_MTIP_1G10G_CL23_QUANTA_THRESH 0xd68
60711 
60712 #define S_CL3_QUANTA_THRESH    16
60713 #define M_CL3_QUANTA_THRESH    0xffffU
60714 #define V_CL3_QUANTA_THRESH(x) ((x) << S_CL3_QUANTA_THRESH)
60715 #define G_CL3_QUANTA_THRESH(x) (((x) >> S_CL3_QUANTA_THRESH) & M_CL3_QUANTA_THRESH)
60716 
60717 #define S_CL2_QUANTA_THRESH    0
60718 #define M_CL2_QUANTA_THRESH    0xffffU
60719 #define V_CL2_QUANTA_THRESH(x) ((x) << S_CL2_QUANTA_THRESH)
60720 #define G_CL2_QUANTA_THRESH(x) (((x) >> S_CL2_QUANTA_THRESH) & M_CL2_QUANTA_THRESH)
60721 
60722 #define A_MAC_PORT_MTIP_1G10G_CL45_QUANTA_THRESH 0xd6c
60723 
60724 #define S_CL5_QUANTA_THRESH    16
60725 #define M_CL5_QUANTA_THRESH    0xffffU
60726 #define V_CL5_QUANTA_THRESH(x) ((x) << S_CL5_QUANTA_THRESH)
60727 #define G_CL5_QUANTA_THRESH(x) (((x) >> S_CL5_QUANTA_THRESH) & M_CL5_QUANTA_THRESH)
60728 
60729 #define S_CL4_QUANTA_THRESH    0
60730 #define M_CL4_QUANTA_THRESH    0xffffU
60731 #define V_CL4_QUANTA_THRESH(x) ((x) << S_CL4_QUANTA_THRESH)
60732 #define G_CL4_QUANTA_THRESH(x) (((x) >> S_CL4_QUANTA_THRESH) & M_CL4_QUANTA_THRESH)
60733 
60734 #define A_MAC_PORT_MTIP_1G10G_CL67_QUANTA_THRESH 0xd70
60735 
60736 #define S_CL7_QUANTA_THRESH    16
60737 #define M_CL7_QUANTA_THRESH    0xffffU
60738 #define V_CL7_QUANTA_THRESH(x) ((x) << S_CL7_QUANTA_THRESH)
60739 #define G_CL7_QUANTA_THRESH(x) (((x) >> S_CL7_QUANTA_THRESH) & M_CL7_QUANTA_THRESH)
60740 
60741 #define S_CL6_QUANTA_THRESH    0
60742 #define M_CL6_QUANTA_THRESH    0xffffU
60743 #define V_CL6_QUANTA_THRESH(x) ((x) << S_CL6_QUANTA_THRESH)
60744 #define G_CL6_QUANTA_THRESH(x) (((x) >> S_CL6_QUANTA_THRESH) & M_CL6_QUANTA_THRESH)
60745 
60746 #define A_MAC_PORT_MTIP_1G10G_RX_PAUSE_STATUS 0xd74
60747 
60748 #define S_STATUS_BIT    0
60749 #define M_STATUS_BIT    0xffU
60750 #define V_STATUS_BIT(x) ((x) << S_STATUS_BIT)
60751 #define G_STATUS_BIT(x) (((x) >> S_STATUS_BIT) & M_STATUS_BIT)
60752 
60753 #define A_MAC_PORT_MTIP_1G10G_TS_TIMESTAMP 0xd7c
60754 #define A_MAC_PORT_MTIP_1G10G_STATN_CONFIG 0xde0
60755 
60756 #define S_CLEAR    2
60757 #define V_CLEAR(x) ((x) << S_CLEAR)
60758 #define F_CLEAR    V_CLEAR(1U)
60759 
60760 #define S_CLEAR_ON_READ    1
60761 #define V_CLEAR_ON_READ(x) ((x) << S_CLEAR_ON_READ)
60762 #define F_CLEAR_ON_READ    V_CLEAR_ON_READ(1U)
60763 
60764 #define S_SATURATE    0
60765 #define V_SATURATE(x) ((x) << S_SATURATE)
60766 #define F_SATURATE    V_SATURATE(1U)
60767 
60768 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETS 0xe00
60769 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETSHI 0xe04
60770 #define A_MAC_PORT_MTIP_1G10G_RX_OCTETSOK 0xe08
60771 #define A_MAC_PORT_MTIP_1G10G_RX_OCTETSOKHI 0xe0c
60772 #define A_MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORS 0xe10
60773 #define A_MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORSHI 0xe14
60774 #define A_MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMES 0xe18
60775 #define A_MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMESHI 0xe1c
60776 #define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOK 0xe20
60777 #define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOKHI 0xe24
60778 #define A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS 0xe28
60779 #define A_MAC_PORT_MTIP_1G10G_RX_CRCERRORSHI 0xe2c
60780 #define A_MAC_PORT_MTIP_1G10G_RX_VLANOK 0xe30
60781 #define A_MAC_PORT_MTIP_1G10G_RX_VLANOKHI 0xe34
60782 #define A_MAC_PORT_MTIP_1G10G_RX_IFINERRORS 0xe38
60783 #define A_MAC_PORT_MTIP_1G10G_RX_IFINERRORSHI 0xe3c
60784 #define A_MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTS 0xe40
60785 #define A_MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTSHI 0xe44
60786 #define A_MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTS 0xe48
60787 #define A_MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTSHI 0xe4c
60788 #define A_MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTS 0xe50
60789 #define A_MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTSHI 0xe54
60790 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTS 0xe58
60791 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTSHI 0xe5c
60792 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS 0xe60
60793 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTSHI 0xe64
60794 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTS 0xe68
60795 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTSHI 0xe6c
60796 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETS 0xe70
60797 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETSHI 0xe74
60798 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETS 0xe78
60799 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETSHI 0xe7c
60800 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETS 0xe80
60801 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETSHI 0xe84
60802 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETS 0xe88
60803 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETSHI 0xe8c
60804 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETS 0xe90
60805 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETSHI 0xe94
60806 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETS 0xe98
60807 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETSHI 0xe9c
60808 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAX 0xea0
60809 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAXHI 0xea4
60810 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTS 0xea8
60811 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTSHI 0xeac
60812 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERS 0xeb0
60813 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERSHI 0xeb4
60814 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTS 0xeb8
60815 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTSHI 0xebc
60816 #define A_MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVED 0xec0
60817 #define A_MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVEDHI 0xec4
60818 #define A_MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONG 0xec8
60819 #define A_MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONGHI 0xecc
60820 #define A_MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORS 0xed0
60821 #define A_MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORSHI 0xed4
60822 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETS 0xf00
60823 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETSHI 0xf04
60824 #define A_MAC_PORT_MTIP_1G10G_TX_OCTETSOK 0xf08
60825 #define A_MAC_PORT_MTIP_1G10G_TX_OCTETSOKHI 0xf0c
60826 #define A_MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORS 0xf10
60827 #define A_MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORSHI 0xf14
60828 #define A_MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMES 0xf18
60829 #define A_MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMESHI 0xf1c
60830 #define A_MAC_PORT_MTIP_1G10G_TX_FRAMESOK 0xf20
60831 #define A_MAC_PORT_MTIP_1G10G_TX_FRAMESOKHI 0xf24
60832 #define A_MAC_PORT_MTIP_1G10G_TX_CRCERRORS 0xf28
60833 #define A_MAC_PORT_MTIP_1G10G_TX_CRCERRORSHI 0xf2c
60834 #define A_MAC_PORT_MTIP_1G10G_TX_VLANOK 0xf30
60835 #define A_MAC_PORT_MTIP_1G10G_TX_VLANOKHI 0xf34
60836 #define A_MAC_PORT_MTIP_1G10G_TX_IFOUTERRORS 0xf38
60837 #define A_MAC_PORT_MTIP_1G10G_TX_IFOUTERRORSHI 0xf3c
60838 #define A_MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTS 0xf40
60839 #define A_MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTSHI 0xf44
60840 #define A_MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTS 0xf48
60841 #define A_MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTSHI 0xf4c
60842 #define A_MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTS 0xf50
60843 #define A_MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTSHI 0xf54
60844 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTS 0xf58
60845 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTSHI 0xf5c
60846 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS 0xf60
60847 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTSHI 0xf64
60848 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTS 0xf68
60849 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTSHI 0xf6c
60850 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETS 0xf70
60851 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETSHI 0xf74
60852 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETS 0xf78
60853 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETSHI 0xf7c
60854 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETS 0xf80
60855 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETSHI 0xf84
60856 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETS 0xf88
60857 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETSHI 0xf8c
60858 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETS 0xf90
60859 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETSHI 0xf94
60860 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETS 0xf98
60861 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETSHI 0xf9c
60862 #define A_MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTU 0xfa0
60863 #define A_MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTUHI 0xfa4
60864 #define A_MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMES 0xfc0
60865 #define A_MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMESHI 0xfc4
60866 #define A_MAC_PORT_MTIP_1G10G_IF_MODE 0x1000
60867 
60868 #define S_MII_ENA_10    4
60869 #define V_MII_ENA_10(x) ((x) << S_MII_ENA_10)
60870 #define F_MII_ENA_10    V_MII_ENA_10(1U)
60871 
60872 #define S_IF_MODE    0
60873 #define M_IF_MODE    0x3U
60874 #define V_IF_MODE(x) ((x) << S_IF_MODE)
60875 #define G_IF_MODE(x) (((x) >> S_IF_MODE) & M_IF_MODE)
60876 
60877 #define A_MAC_PORT_MTIP_1G10G_IF_STATUS 0x1004
60878 
60879 #define S_IF_STATUS_MODE    0
60880 #define M_IF_STATUS_MODE    0x3U
60881 #define V_IF_STATUS_MODE(x) ((x) << S_IF_STATUS_MODE)
60882 #define G_IF_STATUS_MODE(x) (((x) >> S_IF_STATUS_MODE) & M_IF_STATUS_MODE)
60883 
60884 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0 0x1080
60885 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0HI 0x1084
60886 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1 0x1088
60887 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1HI 0x108c
60888 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2 0x1090
60889 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2HI 0x1094
60890 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3 0x1098
60891 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3HI 0x109c
60892 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4 0x10a0
60893 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4HI 0x10a4
60894 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5 0x10a8
60895 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5HI 0x10ac
60896 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6 0x10b0
60897 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6HI 0x10b4
60898 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7 0x10b8
60899 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7HI 0x10bc
60900 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0 0x10c0
60901 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0HI 0x10c4
60902 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1 0x10c8
60903 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1HI 0x10cc
60904 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2 0x10d0
60905 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2HI 0x10d4
60906 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3 0x10d8
60907 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3HI 0x10dc
60908 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4 0x10e0
60909 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4HI 0x10e4
60910 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5 0x10e8
60911 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5HI 0x10ec
60912 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6 0x10f0
60913 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6HI 0x10f4
60914 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7 0x10f8
60915 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7HI 0x10fc
60916 #define A_MAC_PORT_MTIP_ACT_CTL_SEG 0x1200
60917 
60918 #define S_ACTIVE    0
60919 #define M_ACTIVE    0x3fU
60920 #define V_ACTIVE(x) ((x) << S_ACTIVE)
60921 #define G_ACTIVE(x) (((x) >> S_ACTIVE) & M_ACTIVE)
60922 
60923 #define A_T6_MAC_PORT_MTIP_SGMII_CONTROL 0x1200
60924 
60925 #define S_SPEED_SEL    13
60926 #define V_SPEED_SEL(x) ((x) << S_SPEED_SEL)
60927 #define F_SPEED_SEL    V_SPEED_SEL(1U)
60928 
60929 #define S_PWR_DWN    11
60930 #define V_PWR_DWN(x) ((x) << S_PWR_DWN)
60931 #define F_PWR_DWN    V_PWR_DWN(1U)
60932 
60933 #define S_DUPLEX_MODE    8
60934 #define V_DUPLEX_MODE(x) ((x) << S_DUPLEX_MODE)
60935 #define F_DUPLEX_MODE    V_DUPLEX_MODE(1U)
60936 
60937 #define S_COLLISION_TEST    7
60938 #define V_COLLISION_TEST(x) ((x) << S_COLLISION_TEST)
60939 #define F_COLLISION_TEST    V_COLLISION_TEST(1U)
60940 
60941 #define S_T6_SPEED_SEL1    6
60942 #define V_T6_SPEED_SEL1(x) ((x) << S_T6_SPEED_SEL1)
60943 #define F_T6_SPEED_SEL1    V_T6_SPEED_SEL1(1U)
60944 
60945 #define A_MAC_PORT_MTIP_MODE_CTL_SEG 0x1204
60946 
60947 #define S_MODE_CTL    0
60948 #define M_MODE_CTL    0x3U
60949 #define V_MODE_CTL(x) ((x) << S_MODE_CTL)
60950 #define G_MODE_CTL(x) (((x) >> S_MODE_CTL) & M_MODE_CTL)
60951 
60952 #define A_T6_MAC_PORT_MTIP_SGMII_STATUS 0x1204
60953 
60954 #define S_T6_REM_FAULT    4
60955 #define V_T6_REM_FAULT(x) ((x) << S_T6_REM_FAULT)
60956 #define F_T6_REM_FAULT    V_T6_REM_FAULT(1U)
60957 
60958 #define A_MAC_PORT_MTIP_TXCLK_CTL_SEG 0x1208
60959 
60960 #define S_TXCLK_CTL    0
60961 #define M_TXCLK_CTL    0xffffU
60962 #define V_TXCLK_CTL(x) ((x) << S_TXCLK_CTL)
60963 #define G_TXCLK_CTL(x) (((x) >> S_TXCLK_CTL) & M_TXCLK_CTL)
60964 
60965 #define A_T6_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 0x1208
60966 #define A_MAC_PORT_MTIP_TX_PRMBL_CTL_SEG 0x120c
60967 #define A_T6_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 0x120c
60968 #define A_T6_MAC_PORT_MTIP_SGMII_DEV_ABILITY 0x1210
60969 #define A_T6_MAC_PORT_MTIP_SGMII_PARTNER_ABILITY 0x1214
60970 #define A_T6_MAC_PORT_MTIP_SGMII_AN_EXPANSION 0x1218
60971 
60972 #define S_NEXT_PAGE_ABLE    2
60973 #define V_NEXT_PAGE_ABLE(x) ((x) << S_NEXT_PAGE_ABLE)
60974 #define F_NEXT_PAGE_ABLE    V_NEXT_PAGE_ABLE(1U)
60975 
60976 #define S_PAGE_RECEIVE    1
60977 #define V_PAGE_RECEIVE(x) ((x) << S_PAGE_RECEIVE)
60978 #define F_PAGE_RECEIVE    V_PAGE_RECEIVE(1U)
60979 
60980 #define A_MAC_PORT_MTIP_SGMII_NP_TX 0x121c
60981 
60982 #define S_NP_TX    0
60983 #define M_NP_TX    0xffffU
60984 #define V_NP_TX(x) ((x) << S_NP_TX)
60985 #define G_NP_TX(x) (((x) >> S_NP_TX) & M_NP_TX)
60986 
60987 #define A_MAC_PORT_MTIP_WAN_RS_COL_CNT 0x1220
60988 
60989 #define S_COL_CNT    0
60990 #define M_COL_CNT    0xffffU
60991 #define V_COL_CNT(x) ((x) << S_COL_CNT)
60992 #define G_COL_CNT(x) (((x) >> S_COL_CNT) & M_COL_CNT)
60993 
60994 #define A_MAC_PORT_MTIP_SGMII_LP_NP_RX 0x1220
60995 
60996 #define S_LP_NP_RX    0
60997 #define M_LP_NP_RX    0xffffU
60998 #define V_LP_NP_RX(x) ((x) << S_LP_NP_RX)
60999 #define G_LP_NP_RX(x) (((x) >> S_LP_NP_RX) & M_LP_NP_RX)
61000 
61001 #define A_T6_MAC_PORT_MTIP_SGMII_EXTENDED_STATUS 0x123c
61002 
61003 #define S_EXTENDED_STATUS    0
61004 #define M_EXTENDED_STATUS    0xffffU
61005 #define V_EXTENDED_STATUS(x) ((x) << S_EXTENDED_STATUS)
61006 #define G_EXTENDED_STATUS(x) (((x) >> S_EXTENDED_STATUS) & M_EXTENDED_STATUS)
61007 
61008 #define A_MAC_PORT_MTIP_VL_INTVL 0x1240
61009 
61010 #define S_VL_INTVL    1
61011 #define V_VL_INTVL(x) ((x) << S_VL_INTVL)
61012 #define F_VL_INTVL    V_VL_INTVL(1U)
61013 
61014 #define A_MAC_PORT_MTIP_SGMII_SCRATCH 0x1240
61015 
61016 #define S_SCRATCH    0
61017 #define M_SCRATCH    0xffffU
61018 #define V_SCRATCH(x) ((x) << S_SCRATCH)
61019 #define G_SCRATCH(x) (((x) >> S_SCRATCH) & M_SCRATCH)
61020 
61021 #define A_MAC_PORT_MTIP_SGMII_REV 0x1244
61022 
61023 #define S_SGMII_VER    8
61024 #define M_SGMII_VER    0xffU
61025 #define V_SGMII_VER(x) ((x) << S_SGMII_VER)
61026 #define G_SGMII_VER(x) (((x) >> S_SGMII_VER) & M_SGMII_VER)
61027 
61028 #define S_SGMII_REV    0
61029 #define M_SGMII_REV    0xffU
61030 #define V_SGMII_REV(x) ((x) << S_SGMII_REV)
61031 #define G_SGMII_REV(x) (((x) >> S_SGMII_REV) & M_SGMII_REV)
61032 
61033 #define A_T6_MAC_PORT_MTIP_SGMII_LINK_TIMER_LO 0x1248
61034 
61035 #define S_LINK_TIMER_LO    0
61036 #define M_LINK_TIMER_LO    0xffffU
61037 #define V_LINK_TIMER_LO(x) ((x) << S_LINK_TIMER_LO)
61038 #define G_LINK_TIMER_LO(x) (((x) >> S_LINK_TIMER_LO) & M_LINK_TIMER_LO)
61039 
61040 #define A_T6_MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 0x124c
61041 
61042 #define S_LINK_TIMER_HI    0
61043 #define M_LINK_TIMER_HI    0xffffU
61044 #define V_LINK_TIMER_HI(x) ((x) << S_LINK_TIMER_HI)
61045 #define G_LINK_TIMER_HI(x) (((x) >> S_LINK_TIMER_HI) & M_LINK_TIMER_HI)
61046 
61047 #define A_T6_MAC_PORT_MTIP_SGMII_IF_MODE 0x1250
61048 
61049 #define S_SGMII_DUPLEX    4
61050 #define V_SGMII_DUPLEX(x) ((x) << S_SGMII_DUPLEX)
61051 #define F_SGMII_DUPLEX    V_SGMII_DUPLEX(1U)
61052 
61053 #define A_MAC_PORT_MTIP_SGMII_DECODE_ERROR 0x1254
61054 
61055 #define S_T6_DECODE_ERROR    0
61056 #define M_T6_DECODE_ERROR    0xffffU
61057 #define V_T6_DECODE_ERROR(x) ((x) << S_T6_DECODE_ERROR)
61058 #define G_T6_DECODE_ERROR(x) (((x) >> S_T6_DECODE_ERROR) & M_T6_DECODE_ERROR)
61059 
61060 #define A_MAC_PORT_MTIP_KR_PCS_CONTROL_1 0x1300
61061 
61062 #define S_LOW_POWER    11
61063 #define V_LOW_POWER(x) ((x) << S_LOW_POWER)
61064 #define F_LOW_POWER    V_LOW_POWER(1U)
61065 
61066 #define S_SPEED_SEL2    2
61067 #define M_SPEED_SEL2    0xfU
61068 #define V_SPEED_SEL2(x) ((x) << S_SPEED_SEL2)
61069 #define G_SPEED_SEL2(x) (((x) >> S_SPEED_SEL2) & M_SPEED_SEL2)
61070 
61071 #define A_MAC_PORT_MTIP_KR_PCS_STATUS_1 0x1304
61072 
61073 #define S_TX_LPI    11
61074 #define V_TX_LPI(x) ((x) << S_TX_LPI)
61075 #define F_TX_LPI    V_TX_LPI(1U)
61076 
61077 #define S_RX_LPI    10
61078 #define V_RX_LPI(x) ((x) << S_RX_LPI)
61079 #define F_RX_LPI    V_RX_LPI(1U)
61080 
61081 #define S_TX_LPI_ACTIVE    9
61082 #define V_TX_LPI_ACTIVE(x) ((x) << S_TX_LPI_ACTIVE)
61083 #define F_TX_LPI_ACTIVE    V_TX_LPI_ACTIVE(1U)
61084 
61085 #define S_RX_LPI_ACTIVE    8
61086 #define V_RX_LPI_ACTIVE(x) ((x) << S_RX_LPI_ACTIVE)
61087 #define F_RX_LPI_ACTIVE    V_RX_LPI_ACTIVE(1U)
61088 
61089 #define S_FAULT    7
61090 #define V_FAULT(x) ((x) << S_FAULT)
61091 #define F_FAULT    V_FAULT(1U)
61092 
61093 #define S_PCS_RX_LINK_STAT    2
61094 #define V_PCS_RX_LINK_STAT(x) ((x) << S_PCS_RX_LINK_STAT)
61095 #define F_PCS_RX_LINK_STAT    V_PCS_RX_LINK_STAT(1U)
61096 
61097 #define S_LOW_POWER_ABILITY    1
61098 #define V_LOW_POWER_ABILITY(x) ((x) << S_LOW_POWER_ABILITY)
61099 #define F_LOW_POWER_ABILITY    V_LOW_POWER_ABILITY(1U)
61100 
61101 #define A_MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_1 0x1308
61102 #define A_MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_2 0x130c
61103 #define A_MAC_PORT_MTIP_KR_PCS_SPEED_ABILITY 0x1310
61104 
61105 #define S_10G_CAPABLE    0
61106 #define V_10G_CAPABLE(x) ((x) << S_10G_CAPABLE)
61107 #define F_10G_CAPABLE    V_10G_CAPABLE(1U)
61108 
61109 #define A_MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGELO 0x1314
61110 
61111 #define S_AUTO_NEGOTIATION_PRESENT    7
61112 #define V_AUTO_NEGOTIATION_PRESENT(x) ((x) << S_AUTO_NEGOTIATION_PRESENT)
61113 #define F_AUTO_NEGOTIATION_PRESENT    V_AUTO_NEGOTIATION_PRESENT(1U)
61114 
61115 #define S_DTE_XS_PRESENT    5
61116 #define V_DTE_XS_PRESENT(x) ((x) << S_DTE_XS_PRESENT)
61117 #define F_DTE_XS_PRESENT    V_DTE_XS_PRESENT(1U)
61118 
61119 #define S_PHY_XS_PRESENT    4
61120 #define V_PHY_XS_PRESENT(x) ((x) << S_PHY_XS_PRESENT)
61121 #define F_PHY_XS_PRESENT    V_PHY_XS_PRESENT(1U)
61122 
61123 #define S_PCS_PRESENT    3
61124 #define V_PCS_PRESENT(x) ((x) << S_PCS_PRESENT)
61125 #define F_PCS_PRESENT    V_PCS_PRESENT(1U)
61126 
61127 #define S_WIS_PRESENT    2
61128 #define V_WIS_PRESENT(x) ((x) << S_WIS_PRESENT)
61129 #define F_WIS_PRESENT    V_WIS_PRESENT(1U)
61130 
61131 #define S_PMD_PMA_PRESENT    1
61132 #define V_PMD_PMA_PRESENT(x) ((x) << S_PMD_PMA_PRESENT)
61133 #define F_PMD_PMA_PRESENT    V_PMD_PMA_PRESENT(1U)
61134 
61135 #define S_CLAUSE_22_REG_PRESENT    0
61136 #define V_CLAUSE_22_REG_PRESENT(x) ((x) << S_CLAUSE_22_REG_PRESENT)
61137 #define F_CLAUSE_22_REG_PRESENT    V_CLAUSE_22_REG_PRESENT(1U)
61138 
61139 #define A_MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGEHI 0x1318
61140 #define A_MAC_PORT_MTIP_KR_PCS_CONTROL_2 0x131c
61141 
61142 #define S_PCS_TYPE_SELECTION    0
61143 #define M_PCS_TYPE_SELECTION    0x3U
61144 #define V_PCS_TYPE_SELECTION(x) ((x) << S_PCS_TYPE_SELECTION)
61145 #define G_PCS_TYPE_SELECTION(x) (((x) >> S_PCS_TYPE_SELECTION) & M_PCS_TYPE_SELECTION)
61146 
61147 #define A_MAC_PORT_MTIP_KR_PCS_STATUS_2 0x1320
61148 
61149 #define S_DEVICE_PRESENT    14
61150 #define M_DEVICE_PRESENT    0x3U
61151 #define V_DEVICE_PRESENT(x) ((x) << S_DEVICE_PRESENT)
61152 #define G_DEVICE_PRESENT(x) (((x) >> S_DEVICE_PRESENT) & M_DEVICE_PRESENT)
61153 
61154 #define S_TRANSMIT_FAULT    11
61155 #define V_TRANSMIT_FAULT(x) ((x) << S_TRANSMIT_FAULT)
61156 #define F_TRANSMIT_FAULT    V_TRANSMIT_FAULT(1U)
61157 
61158 #define S_RECEIVE_FAULT    10
61159 #define V_RECEIVE_FAULT(x) ((x) << S_RECEIVE_FAULT)
61160 #define F_RECEIVE_FAULT    V_RECEIVE_FAULT(1U)
61161 
61162 #define S_10GBASE_W_CAPABLE    2
61163 #define V_10GBASE_W_CAPABLE(x) ((x) << S_10GBASE_W_CAPABLE)
61164 #define F_10GBASE_W_CAPABLE    V_10GBASE_W_CAPABLE(1U)
61165 
61166 #define S_10GBASE_X_CAPABLE    1
61167 #define V_10GBASE_X_CAPABLE(x) ((x) << S_10GBASE_X_CAPABLE)
61168 #define F_10GBASE_X_CAPABLE    V_10GBASE_X_CAPABLE(1U)
61169 
61170 #define S_10GBASE_R_CAPABLE    0
61171 #define V_10GBASE_R_CAPABLE(x) ((x) << S_10GBASE_R_CAPABLE)
61172 #define F_10GBASE_R_CAPABLE    V_10GBASE_R_CAPABLE(1U)
61173 
61174 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_LO 0x1338
61175 
61176 #define S_PCS_PACKAGE_IDENTIFIER_LO    0
61177 #define M_PCS_PACKAGE_IDENTIFIER_LO    0xffffU
61178 #define V_PCS_PACKAGE_IDENTIFIER_LO(x) ((x) << S_PCS_PACKAGE_IDENTIFIER_LO)
61179 #define G_PCS_PACKAGE_IDENTIFIER_LO(x) (((x) >> S_PCS_PACKAGE_IDENTIFIER_LO) & M_PCS_PACKAGE_IDENTIFIER_LO)
61180 
61181 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_HI 0x133c
61182 
61183 #define S_PCS_PACKAGE_IDENTIFIER_HI    0
61184 #define M_PCS_PACKAGE_IDENTIFIER_HI    0xffffU
61185 #define V_PCS_PACKAGE_IDENTIFIER_HI(x) ((x) << S_PCS_PACKAGE_IDENTIFIER_HI)
61186 #define G_PCS_PACKAGE_IDENTIFIER_HI(x) (((x) >> S_PCS_PACKAGE_IDENTIFIER_HI) & M_PCS_PACKAGE_IDENTIFIER_HI)
61187 
61188 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_1 0x1380
61189 
61190 #define S_10GBASE_R_RX_LINK_STATUS    12
61191 #define V_10GBASE_R_RX_LINK_STATUS(x) ((x) << S_10GBASE_R_RX_LINK_STATUS)
61192 #define F_10GBASE_R_RX_LINK_STATUS    V_10GBASE_R_RX_LINK_STATUS(1U)
61193 
61194 #define S_PRBS9_PTTRN_TSTNG_ABILITY    3
61195 #define V_PRBS9_PTTRN_TSTNG_ABILITY(x) ((x) << S_PRBS9_PTTRN_TSTNG_ABILITY)
61196 #define F_PRBS9_PTTRN_TSTNG_ABILITY    V_PRBS9_PTTRN_TSTNG_ABILITY(1U)
61197 
61198 #define S_PRBS31_PTTRN_TSTNG_ABILITY    2
61199 #define V_PRBS31_PTTRN_TSTNG_ABILITY(x) ((x) << S_PRBS31_PTTRN_TSTNG_ABILITY)
61200 #define F_PRBS31_PTTRN_TSTNG_ABILITY    V_PRBS31_PTTRN_TSTNG_ABILITY(1U)
61201 
61202 #define S_10GBASE_R_PCS_HIGH_BER    1
61203 #define V_10GBASE_R_PCS_HIGH_BER(x) ((x) << S_10GBASE_R_PCS_HIGH_BER)
61204 #define F_10GBASE_R_PCS_HIGH_BER    V_10GBASE_R_PCS_HIGH_BER(1U)
61205 
61206 #define S_10GBASE_R_PCS_BLOCK_LOCK    0
61207 #define V_10GBASE_R_PCS_BLOCK_LOCK(x) ((x) << S_10GBASE_R_PCS_BLOCK_LOCK)
61208 #define F_10GBASE_R_PCS_BLOCK_LOCK    V_10GBASE_R_PCS_BLOCK_LOCK(1U)
61209 
61210 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_2 0x1384
61211 
61212 #define S_LATCHED_BLOCK_LOCK    15
61213 #define V_LATCHED_BLOCK_LOCK(x) ((x) << S_LATCHED_BLOCK_LOCK)
61214 #define F_LATCHED_BLOCK_LOCK    V_LATCHED_BLOCK_LOCK(1U)
61215 
61216 #define S_LATCHED_HIGH_BER    14
61217 #define V_LATCHED_HIGH_BER(x) ((x) << S_LATCHED_HIGH_BER)
61218 #define F_LATCHED_HIGH_BER    V_LATCHED_HIGH_BER(1U)
61219 
61220 #define S_BERBER_COUNTER    8
61221 #define M_BERBER_COUNTER    0x3fU
61222 #define V_BERBER_COUNTER(x) ((x) << S_BERBER_COUNTER)
61223 #define G_BERBER_COUNTER(x) (((x) >> S_BERBER_COUNTER) & M_BERBER_COUNTER)
61224 
61225 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_0 0x1388
61226 
61227 #define S_TEST_PATTERN_SEED_A0    0
61228 #define M_TEST_PATTERN_SEED_A0    0xffffU
61229 #define V_TEST_PATTERN_SEED_A0(x) ((x) << S_TEST_PATTERN_SEED_A0)
61230 #define G_TEST_PATTERN_SEED_A0(x) (((x) >> S_TEST_PATTERN_SEED_A0) & M_TEST_PATTERN_SEED_A0)
61231 
61232 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_1 0x138c
61233 
61234 #define S_TEST_PATTERN_SEED_A1    0
61235 #define M_TEST_PATTERN_SEED_A1    0xffffU
61236 #define V_TEST_PATTERN_SEED_A1(x) ((x) << S_TEST_PATTERN_SEED_A1)
61237 #define G_TEST_PATTERN_SEED_A1(x) (((x) >> S_TEST_PATTERN_SEED_A1) & M_TEST_PATTERN_SEED_A1)
61238 
61239 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_2 0x1390
61240 
61241 #define S_TEST_PATTERN_SEED_A2    0
61242 #define M_TEST_PATTERN_SEED_A2    0xffffU
61243 #define V_TEST_PATTERN_SEED_A2(x) ((x) << S_TEST_PATTERN_SEED_A2)
61244 #define G_TEST_PATTERN_SEED_A2(x) (((x) >> S_TEST_PATTERN_SEED_A2) & M_TEST_PATTERN_SEED_A2)
61245 
61246 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_3 0x1394
61247 
61248 #define S_TEST_PATTERN_SEED_A3    0
61249 #define M_TEST_PATTERN_SEED_A3    0x3ffU
61250 #define V_TEST_PATTERN_SEED_A3(x) ((x) << S_TEST_PATTERN_SEED_A3)
61251 #define G_TEST_PATTERN_SEED_A3(x) (((x) >> S_TEST_PATTERN_SEED_A3) & M_TEST_PATTERN_SEED_A3)
61252 
61253 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_0 0x1398
61254 
61255 #define S_TEST_PATTERN_SEED_B0    0
61256 #define M_TEST_PATTERN_SEED_B0    0xffffU
61257 #define V_TEST_PATTERN_SEED_B0(x) ((x) << S_TEST_PATTERN_SEED_B0)
61258 #define G_TEST_PATTERN_SEED_B0(x) (((x) >> S_TEST_PATTERN_SEED_B0) & M_TEST_PATTERN_SEED_B0)
61259 
61260 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_1 0x139c
61261 
61262 #define S_TEST_PATTERN_SEED_B1    0
61263 #define M_TEST_PATTERN_SEED_B1    0xffffU
61264 #define V_TEST_PATTERN_SEED_B1(x) ((x) << S_TEST_PATTERN_SEED_B1)
61265 #define G_TEST_PATTERN_SEED_B1(x) (((x) >> S_TEST_PATTERN_SEED_B1) & M_TEST_PATTERN_SEED_B1)
61266 
61267 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_2 0x13a0
61268 
61269 #define S_TEST_PATTERN_SEED_B2    0
61270 #define M_TEST_PATTERN_SEED_B2    0xffffU
61271 #define V_TEST_PATTERN_SEED_B2(x) ((x) << S_TEST_PATTERN_SEED_B2)
61272 #define G_TEST_PATTERN_SEED_B2(x) (((x) >> S_TEST_PATTERN_SEED_B2) & M_TEST_PATTERN_SEED_B2)
61273 
61274 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_3 0x13a4
61275 
61276 #define S_TEST_PATTERN_SEED_B3    0
61277 #define M_TEST_PATTERN_SEED_B3    0x3ffU
61278 #define V_TEST_PATTERN_SEED_B3(x) ((x) << S_TEST_PATTERN_SEED_B3)
61279 #define G_TEST_PATTERN_SEED_B3(x) (((x) >> S_TEST_PATTERN_SEED_B3) & M_TEST_PATTERN_SEED_B3)
61280 
61281 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_CONTROL 0x13a8
61282 
61283 #define S_PRBS9_TX_TST_PTTRN_EN    6
61284 #define V_PRBS9_TX_TST_PTTRN_EN(x) ((x) << S_PRBS9_TX_TST_PTTRN_EN)
61285 #define F_PRBS9_TX_TST_PTTRN_EN    V_PRBS9_TX_TST_PTTRN_EN(1U)
61286 
61287 #define S_PRBS31_RX_TST_PTTRN_EN    5
61288 #define V_PRBS31_RX_TST_PTTRN_EN(x) ((x) << S_PRBS31_RX_TST_PTTRN_EN)
61289 #define F_PRBS31_RX_TST_PTTRN_EN    V_PRBS31_RX_TST_PTTRN_EN(1U)
61290 
61291 #define S_PRBS31_TX_TST_PTTRN_EN    4
61292 #define V_PRBS31_TX_TST_PTTRN_EN(x) ((x) << S_PRBS31_TX_TST_PTTRN_EN)
61293 #define F_PRBS31_TX_TST_PTTRN_EN    V_PRBS31_TX_TST_PTTRN_EN(1U)
61294 
61295 #define S_TX_TEST_PATTERN_EN    3
61296 #define V_TX_TEST_PATTERN_EN(x) ((x) << S_TX_TEST_PATTERN_EN)
61297 #define F_TX_TEST_PATTERN_EN    V_TX_TEST_PATTERN_EN(1U)
61298 
61299 #define S_RX_TEST_PATTERN_EN    2
61300 #define V_RX_TEST_PATTERN_EN(x) ((x) << S_RX_TEST_PATTERN_EN)
61301 #define F_RX_TEST_PATTERN_EN    V_RX_TEST_PATTERN_EN(1U)
61302 
61303 #define S_TEST_PATTERN_SELECT    1
61304 #define V_TEST_PATTERN_SELECT(x) ((x) << S_TEST_PATTERN_SELECT)
61305 #define F_TEST_PATTERN_SELECT    V_TEST_PATTERN_SELECT(1U)
61306 
61307 #define S_DATA_PATTERN_SELECT    0
61308 #define V_DATA_PATTERN_SELECT(x) ((x) << S_DATA_PATTERN_SELECT)
61309 #define F_DATA_PATTERN_SELECT    V_DATA_PATTERN_SELECT(1U)
61310 
61311 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_ERROR_COUNTER 0x13ac
61312 
61313 #define S_TEST_PATTERN_ERR_CNTR    0
61314 #define M_TEST_PATTERN_ERR_CNTR    0xffffU
61315 #define V_TEST_PATTERN_ERR_CNTR(x) ((x) << S_TEST_PATTERN_ERR_CNTR)
61316 #define G_TEST_PATTERN_ERR_CNTR(x) (((x) >> S_TEST_PATTERN_ERR_CNTR) & M_TEST_PATTERN_ERR_CNTR)
61317 
61318 #define A_MAC_PORT_MTIP_KR_VENDOR_SPECIFIC_PCS_STATUS 0x13b4
61319 
61320 #define S_TRANSMIT_FIFO_FAULT    1
61321 #define V_TRANSMIT_FIFO_FAULT(x) ((x) << S_TRANSMIT_FIFO_FAULT)
61322 #define F_TRANSMIT_FIFO_FAULT    V_TRANSMIT_FIFO_FAULT(1U)
61323 
61324 #define S_RECEIVE_FIFO_FAULT    0
61325 #define V_RECEIVE_FIFO_FAULT(x) ((x) << S_RECEIVE_FIFO_FAULT)
61326 #define F_RECEIVE_FIFO_FAULT    V_RECEIVE_FIFO_FAULT(1U)
61327 
61328 #define A_MAC_PORT_MTIP_KR4_CONTROL_1 0x1400
61329 
61330 #define S_SPEED_SELECTION    13
61331 #define V_SPEED_SELECTION(x) ((x) << S_SPEED_SELECTION)
61332 #define F_SPEED_SELECTION    V_SPEED_SELECTION(1U)
61333 
61334 #define S_SPEED_SELECTION1    6
61335 #define V_SPEED_SELECTION1(x) ((x) << S_SPEED_SELECTION1)
61336 #define F_SPEED_SELECTION1    V_SPEED_SELECTION1(1U)
61337 
61338 #define S_SPEED_SELECTION2    2
61339 #define M_SPEED_SELECTION2    0xfU
61340 #define V_SPEED_SELECTION2(x) ((x) << S_SPEED_SELECTION2)
61341 #define G_SPEED_SELECTION2(x) (((x) >> S_SPEED_SELECTION2) & M_SPEED_SELECTION2)
61342 
61343 #define A_MAC_PORT_MTIP_KR4_STATUS_1 0x1404
61344 
61345 #define S_RECEIVE_LINK_STAT    2
61346 #define V_RECEIVE_LINK_STAT(x) ((x) << S_RECEIVE_LINK_STAT)
61347 #define F_RECEIVE_LINK_STAT    V_RECEIVE_LINK_STAT(1U)
61348 
61349 #define A_MAC_PORT_MTIP_KR4_DEVICE_ID0 0x1408
61350 #define A_MAC_PORT_MTIP_KR4_DEVICE_ID1 0x140c
61351 
61352 #define S_T6_DEVICE_ID1    16
61353 #define M_T6_DEVICE_ID1    0xffffU
61354 #define V_T6_DEVICE_ID1(x) ((x) << S_T6_DEVICE_ID1)
61355 #define G_T6_DEVICE_ID1(x) (((x) >> S_T6_DEVICE_ID1) & M_T6_DEVICE_ID1)
61356 
61357 #define A_MAC_PORT_MTIP_KR4_SPEED_ABILITY 0x1410
61358 
61359 #define S_100G_CAPABLE    3
61360 #define V_100G_CAPABLE(x) ((x) << S_100G_CAPABLE)
61361 #define F_100G_CAPABLE    V_100G_CAPABLE(1U)
61362 
61363 #define S_40G_CAPABLE    2
61364 #define V_40G_CAPABLE(x) ((x) << S_40G_CAPABLE)
61365 #define F_40G_CAPABLE    V_40G_CAPABLE(1U)
61366 
61367 #define S_10PASS_TS_2BASE_TL_CAPABLE    1
61368 #define V_10PASS_TS_2BASE_TL_CAPABLE(x) ((x) << S_10PASS_TS_2BASE_TL_CAPABLE)
61369 #define F_10PASS_TS_2BASE_TL_CAPABLE    V_10PASS_TS_2BASE_TL_CAPABLE(1U)
61370 
61371 #define A_MAC_PORT_MTIP_KR4_DEVICES_IN_PKG1 0x1414
61372 
61373 #define S_CLAUSE_22_REG    0
61374 #define V_CLAUSE_22_REG(x) ((x) << S_CLAUSE_22_REG)
61375 #define F_CLAUSE_22_REG    V_CLAUSE_22_REG(1U)
61376 
61377 #define A_MAC_PORT_MTIP_KR4_DEVICES_IN_PKG2 0x1418
61378 
61379 #define S_VENDOR_SPECIFIC_DEVICE    15
61380 #define V_VENDOR_SPECIFIC_DEVICE(x) ((x) << S_VENDOR_SPECIFIC_DEVICE)
61381 #define F_VENDOR_SPECIFIC_DEVICE    V_VENDOR_SPECIFIC_DEVICE(1U)
61382 
61383 #define S_VENDOR_SPECIFIC_DEVICE1    14
61384 #define V_VENDOR_SPECIFIC_DEVICE1(x) ((x) << S_VENDOR_SPECIFIC_DEVICE1)
61385 #define F_VENDOR_SPECIFIC_DEVICE1    V_VENDOR_SPECIFIC_DEVICE1(1U)
61386 
61387 #define S_CLAUSE_22_EXT    13
61388 #define V_CLAUSE_22_EXT(x) ((x) << S_CLAUSE_22_EXT)
61389 #define F_CLAUSE_22_EXT    V_CLAUSE_22_EXT(1U)
61390 
61391 #define A_MAC_PORT_MTIP_KR4_CONTROL_2 0x141c
61392 
61393 #define S_PCS_TYPE_SEL    0
61394 #define M_PCS_TYPE_SEL    0x7U
61395 #define V_PCS_TYPE_SEL(x) ((x) << S_PCS_TYPE_SEL)
61396 #define G_PCS_TYPE_SEL(x) (((x) >> S_PCS_TYPE_SEL) & M_PCS_TYPE_SEL)
61397 
61398 #define A_MAC_PORT_MTIP_KR4_STATUS_2 0x1420
61399 
61400 #define S_100GBASE_R_CAPABLE    5
61401 #define V_100GBASE_R_CAPABLE(x) ((x) << S_100GBASE_R_CAPABLE)
61402 #define F_100GBASE_R_CAPABLE    V_100GBASE_R_CAPABLE(1U)
61403 
61404 #define S_40GBASE_R_CAPABLE    4
61405 #define V_40GBASE_R_CAPABLE(x) ((x) << S_40GBASE_R_CAPABLE)
61406 #define F_40GBASE_R_CAPABLE    V_40GBASE_R_CAPABLE(1U)
61407 
61408 #define S_10GBASE_T_CAPABLE    3
61409 #define V_10GBASE_T_CAPABLE(x) ((x) << S_10GBASE_T_CAPABLE)
61410 #define F_10GBASE_T_CAPABLE    V_10GBASE_T_CAPABLE(1U)
61411 
61412 #define A_MAC_PORT_MTIP_KR4_PKG_ID0 0x1438
61413 #define A_MAC_PORT_MTIP_KR4_PKG_ID1 0x143c
61414 #define A_MAC_PORT_MTIP_KR4_BASE_R_STATUS_1 0x1480
61415 
61416 #define S_T6_RX_LINK_STATUS    12
61417 #define V_T6_RX_LINK_STATUS(x) ((x) << S_T6_RX_LINK_STATUS)
61418 #define F_T6_RX_LINK_STATUS    V_T6_RX_LINK_STATUS(1U)
61419 
61420 #define S_HIGH_BER    1
61421 #define V_HIGH_BER(x) ((x) << S_HIGH_BER)
61422 #define F_HIGH_BER    V_HIGH_BER(1U)
61423 
61424 #define S_KR4_BLOCK_LOCK    0
61425 #define V_KR4_BLOCK_LOCK(x) ((x) << S_KR4_BLOCK_LOCK)
61426 #define F_KR4_BLOCK_LOCK    V_KR4_BLOCK_LOCK(1U)
61427 
61428 #define A_MAC_PORT_MTIP_KR4_BASE_R_STATUS_2 0x1484
61429 
61430 #define S_LATCHED_BL_LK    15
61431 #define V_LATCHED_BL_LK(x) ((x) << S_LATCHED_BL_LK)
61432 #define F_LATCHED_BL_LK    V_LATCHED_BL_LK(1U)
61433 
61434 #define S_LATCHED_HG_BR    14
61435 #define V_LATCHED_HG_BR(x) ((x) << S_LATCHED_HG_BR)
61436 #define F_LATCHED_HG_BR    V_LATCHED_HG_BR(1U)
61437 
61438 #define S_BER_CNT    8
61439 #define M_BER_CNT    0x3fU
61440 #define V_BER_CNT(x) ((x) << S_BER_CNT)
61441 #define G_BER_CNT(x) (((x) >> S_BER_CNT) & M_BER_CNT)
61442 
61443 #define S_ERR_BL_CNT    0
61444 #define M_ERR_BL_CNT    0xffU
61445 #define V_ERR_BL_CNT(x) ((x) << S_ERR_BL_CNT)
61446 #define G_ERR_BL_CNT(x) (((x) >> S_ERR_BL_CNT) & M_ERR_BL_CNT)
61447 
61448 #define A_MAC_PORT_MTIP_KR4_BASE_R_TEST_CONTROL 0x14a8
61449 
61450 #define S_TX_TP_EN    3
61451 #define V_TX_TP_EN(x) ((x) << S_TX_TP_EN)
61452 #define F_TX_TP_EN    V_TX_TP_EN(1U)
61453 
61454 #define S_RX_TP_EN    2
61455 #define V_RX_TP_EN(x) ((x) << S_RX_TP_EN)
61456 #define F_RX_TP_EN    V_RX_TP_EN(1U)
61457 
61458 #define A_MAC_PORT_MTIP_KR4_BASE_R_TEST_ERR_CNT 0x14ac
61459 
61460 #define S_TP_ERR_CNTR    0
61461 #define M_TP_ERR_CNTR    0xffffU
61462 #define V_TP_ERR_CNTR(x) ((x) << S_TP_ERR_CNTR)
61463 #define G_TP_ERR_CNTR(x) (((x) >> S_TP_ERR_CNTR) & M_TP_ERR_CNTR)
61464 
61465 #define A_MAC_PORT_MTIP_KR4_BER_HIGH_ORDER_CNT 0x14b0
61466 
61467 #define S_BER_HI_ORDER_CNT    0
61468 #define M_BER_HI_ORDER_CNT    0xffffU
61469 #define V_BER_HI_ORDER_CNT(x) ((x) << S_BER_HI_ORDER_CNT)
61470 #define G_BER_HI_ORDER_CNT(x) (((x) >> S_BER_HI_ORDER_CNT) & M_BER_HI_ORDER_CNT)
61471 
61472 #define A_MAC_PORT_MTIP_KR4_ERR_BLK_HIGH_ORDER_CNT 0x14b4
61473 
61474 #define S_HI_ORDER_CNT_EN    15
61475 #define V_HI_ORDER_CNT_EN(x) ((x) << S_HI_ORDER_CNT_EN)
61476 #define F_HI_ORDER_CNT_EN    V_HI_ORDER_CNT_EN(1U)
61477 
61478 #define S_ERR_BLK_CNTR    0
61479 #define M_ERR_BLK_CNTR    0x3fffU
61480 #define V_ERR_BLK_CNTR(x) ((x) << S_ERR_BLK_CNTR)
61481 #define G_ERR_BLK_CNTR(x) (((x) >> S_ERR_BLK_CNTR) & M_ERR_BLK_CNTR)
61482 
61483 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_1 0x14c8
61484 
61485 #define S_LANE_ALIGN_STATUS    12
61486 #define V_LANE_ALIGN_STATUS(x) ((x) << S_LANE_ALIGN_STATUS)
61487 #define F_LANE_ALIGN_STATUS    V_LANE_ALIGN_STATUS(1U)
61488 
61489 #define S_LANE_3_BLK_LCK    3
61490 #define V_LANE_3_BLK_LCK(x) ((x) << S_LANE_3_BLK_LCK)
61491 #define F_LANE_3_BLK_LCK    V_LANE_3_BLK_LCK(1U)
61492 
61493 #define S_LANE_2_BLK_LC32_6431K    2
61494 #define V_LANE_2_BLK_LC32_6431K(x) ((x) << S_LANE_2_BLK_LC32_6431K)
61495 #define F_LANE_2_BLK_LC32_6431K    V_LANE_2_BLK_LC32_6431K(1U)
61496 
61497 #define S_LANE_1_BLK_LCK    1
61498 #define V_LANE_1_BLK_LCK(x) ((x) << S_LANE_1_BLK_LCK)
61499 #define F_LANE_1_BLK_LCK    V_LANE_1_BLK_LCK(1U)
61500 
61501 #define S_LANE_0_BLK_LCK    0
61502 #define V_LANE_0_BLK_LCK(x) ((x) << S_LANE_0_BLK_LCK)
61503 #define F_LANE_0_BLK_LCK    V_LANE_0_BLK_LCK(1U)
61504 
61505 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_2 0x14cc
61506 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_3 0x14d0
61507 
61508 #define S_LANE_3_ALIGN_MRKR_LCK    3
61509 #define V_LANE_3_ALIGN_MRKR_LCK(x) ((x) << S_LANE_3_ALIGN_MRKR_LCK)
61510 #define F_LANE_3_ALIGN_MRKR_LCK    V_LANE_3_ALIGN_MRKR_LCK(1U)
61511 
61512 #define S_LANE_2_ALIGN_MRKR_LCK    2
61513 #define V_LANE_2_ALIGN_MRKR_LCK(x) ((x) << S_LANE_2_ALIGN_MRKR_LCK)
61514 #define F_LANE_2_ALIGN_MRKR_LCK    V_LANE_2_ALIGN_MRKR_LCK(1U)
61515 
61516 #define S_LANE_1_ALIGN_MRKR_LCK    1
61517 #define V_LANE_1_ALIGN_MRKR_LCK(x) ((x) << S_LANE_1_ALIGN_MRKR_LCK)
61518 #define F_LANE_1_ALIGN_MRKR_LCK    V_LANE_1_ALIGN_MRKR_LCK(1U)
61519 
61520 #define S_LANE_0_ALIGN_MRKR_LCK    0
61521 #define V_LANE_0_ALIGN_MRKR_LCK(x) ((x) << S_LANE_0_ALIGN_MRKR_LCK)
61522 #define F_LANE_0_ALIGN_MRKR_LCK    V_LANE_0_ALIGN_MRKR_LCK(1U)
61523 
61524 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_4 0x14d4
61525 #define A_MAC_PORT_MTIP_MDIO_CFG_STATUS 0x1600
61526 
61527 #define S_CLK_DIV    7
61528 #define M_CLK_DIV    0x1ffU
61529 #define V_CLK_DIV(x) ((x) << S_CLK_DIV)
61530 #define G_CLK_DIV(x) (((x) >> S_CLK_DIV) & M_CLK_DIV)
61531 
61532 #define S_CL45_EN    6
61533 #define V_CL45_EN(x) ((x) << S_CL45_EN)
61534 #define F_CL45_EN    V_CL45_EN(1U)
61535 
61536 #define S_DISABLE_PREAMBLE    5
61537 #define V_DISABLE_PREAMBLE(x) ((x) << S_DISABLE_PREAMBLE)
61538 #define F_DISABLE_PREAMBLE    V_DISABLE_PREAMBLE(1U)
61539 
61540 #define S_MDIO_HOLD_TIME    2
61541 #define M_MDIO_HOLD_TIME    0x7U
61542 #define V_MDIO_HOLD_TIME(x) ((x) << S_MDIO_HOLD_TIME)
61543 #define G_MDIO_HOLD_TIME(x) (((x) >> S_MDIO_HOLD_TIME) & M_MDIO_HOLD_TIME)
61544 
61545 #define S_MDIO_READ_ERR    1
61546 #define V_MDIO_READ_ERR(x) ((x) << S_MDIO_READ_ERR)
61547 #define F_MDIO_READ_ERR    V_MDIO_READ_ERR(1U)
61548 
61549 #define S_MDIO_BUSY    0
61550 #define V_MDIO_BUSY(x) ((x) << S_MDIO_BUSY)
61551 #define F_MDIO_BUSY    V_MDIO_BUSY(1U)
61552 
61553 #define A_MAC_PORT_MTIP_MDIO_COMMAND 0x1604
61554 
61555 #define S_MDIO_CMD_READ    15
61556 #define V_MDIO_CMD_READ(x) ((x) << S_MDIO_CMD_READ)
61557 #define F_MDIO_CMD_READ    V_MDIO_CMD_READ(1U)
61558 
61559 #define S_READ_INCR    14
61560 #define V_READ_INCR(x) ((x) << S_READ_INCR)
61561 #define F_READ_INCR    V_READ_INCR(1U)
61562 
61563 #define S_PORT_ADDR    5
61564 #define M_PORT_ADDR    0x1fU
61565 #define V_PORT_ADDR(x) ((x) << S_PORT_ADDR)
61566 #define G_PORT_ADDR(x) (((x) >> S_PORT_ADDR) & M_PORT_ADDR)
61567 
61568 #define S_DEV_ADDR    0
61569 #define M_DEV_ADDR    0x1fU
61570 #define V_DEV_ADDR(x) ((x) << S_DEV_ADDR)
61571 #define G_DEV_ADDR(x) (((x) >> S_DEV_ADDR) & M_DEV_ADDR)
61572 
61573 #define A_MAC_PORT_MTIP_MDIO_DATA 0x1608
61574 
61575 #define S_READBUSY    31
61576 #define V_READBUSY(x) ((x) << S_READBUSY)
61577 #define F_READBUSY    V_READBUSY(1U)
61578 
61579 #define S_DATA_WORD    0
61580 #define M_DATA_WORD    0xffffU
61581 #define V_DATA_WORD(x) ((x) << S_DATA_WORD)
61582 #define G_DATA_WORD(x) (((x) >> S_DATA_WORD) & M_DATA_WORD)
61583 
61584 #define A_MAC_PORT_MTIP_MDIO_REGADDR 0x160c
61585 
61586 #define S_MDIO_ADDR    0
61587 #define M_MDIO_ADDR    0xffffU
61588 #define V_MDIO_ADDR(x) ((x) << S_MDIO_ADDR)
61589 #define G_MDIO_ADDR(x) (((x) >> S_MDIO_ADDR) & M_MDIO_ADDR)
61590 
61591 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_0 0x1720
61592 
61593 #define S_BIP_ERR_CNT_LANE_0    0
61594 #define M_BIP_ERR_CNT_LANE_0    0xffffU
61595 #define V_BIP_ERR_CNT_LANE_0(x) ((x) << S_BIP_ERR_CNT_LANE_0)
61596 #define G_BIP_ERR_CNT_LANE_0(x) (((x) >> S_BIP_ERR_CNT_LANE_0) & M_BIP_ERR_CNT_LANE_0)
61597 
61598 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_1 0x1724
61599 
61600 #define S_BIP_ERR_CNT_LANE_1    0
61601 #define M_BIP_ERR_CNT_LANE_1    0xffffU
61602 #define V_BIP_ERR_CNT_LANE_1(x) ((x) << S_BIP_ERR_CNT_LANE_1)
61603 #define G_BIP_ERR_CNT_LANE_1(x) (((x) >> S_BIP_ERR_CNT_LANE_1) & M_BIP_ERR_CNT_LANE_1)
61604 
61605 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_2 0x1728
61606 
61607 #define S_BIP_ERR_CNT_LANE_2    0
61608 #define M_BIP_ERR_CNT_LANE_2    0xffffU
61609 #define V_BIP_ERR_CNT_LANE_2(x) ((x) << S_BIP_ERR_CNT_LANE_2)
61610 #define G_BIP_ERR_CNT_LANE_2(x) (((x) >> S_BIP_ERR_CNT_LANE_2) & M_BIP_ERR_CNT_LANE_2)
61611 
61612 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_3 0x172c
61613 
61614 #define S_BIP_ERR_CNT_LANE_3    0
61615 #define M_BIP_ERR_CNT_LANE_3    0xffffU
61616 #define V_BIP_ERR_CNT_LANE_3(x) ((x) << S_BIP_ERR_CNT_LANE_3)
61617 #define G_BIP_ERR_CNT_LANE_3(x) (((x) >> S_BIP_ERR_CNT_LANE_3) & M_BIP_ERR_CNT_LANE_3)
61618 
61619 #define A_MAC_PORT_MTIP_VLAN_TPID_0 0x1a00
61620 
61621 #define S_VLANTAG    0
61622 #define CXGBE_M_VLANTAG    0xffffU
61623 #define V_VLANTAG(x) ((x) << S_VLANTAG)
61624 #define G_VLANTAG(x) (((x) >> S_VLANTAG) & M_VLANTAG)
61625 
61626 #define A_MAC_PORT_MTIP_VLAN_TPID_1 0x1a04
61627 #define A_MAC_PORT_MTIP_VLAN_TPID_2 0x1a08
61628 #define A_MAC_PORT_MTIP_VLAN_TPID_3 0x1a0c
61629 #define A_MAC_PORT_MTIP_VLAN_TPID_4 0x1a10
61630 #define A_MAC_PORT_MTIP_VLAN_TPID_5 0x1a14
61631 #define A_MAC_PORT_MTIP_VLAN_TPID_6 0x1a18
61632 #define A_MAC_PORT_MTIP_VLAN_TPID_7 0x1a1c
61633 #define A_MAC_PORT_MTIP_KR4_LANE_0_MAPPING 0x1a40
61634 
61635 #define S_KR4_LANE_0_MAPPING    0
61636 #define M_KR4_LANE_0_MAPPING    0x3U
61637 #define V_KR4_LANE_0_MAPPING(x) ((x) << S_KR4_LANE_0_MAPPING)
61638 #define G_KR4_LANE_0_MAPPING(x) (((x) >> S_KR4_LANE_0_MAPPING) & M_KR4_LANE_0_MAPPING)
61639 
61640 #define A_MAC_PORT_MTIP_KR4_LANE_1_MAPPING 0x1a44
61641 
61642 #define S_KR4_LANE_1_MAPPING    0
61643 #define M_KR4_LANE_1_MAPPING    0x3U
61644 #define V_KR4_LANE_1_MAPPING(x) ((x) << S_KR4_LANE_1_MAPPING)
61645 #define G_KR4_LANE_1_MAPPING(x) (((x) >> S_KR4_LANE_1_MAPPING) & M_KR4_LANE_1_MAPPING)
61646 
61647 #define A_MAC_PORT_MTIP_KR4_LANE_2_MAPPING 0x1a48
61648 
61649 #define S_KR4_LANE_2_MAPPING    0
61650 #define M_KR4_LANE_2_MAPPING    0x3U
61651 #define V_KR4_LANE_2_MAPPING(x) ((x) << S_KR4_LANE_2_MAPPING)
61652 #define G_KR4_LANE_2_MAPPING(x) (((x) >> S_KR4_LANE_2_MAPPING) & M_KR4_LANE_2_MAPPING)
61653 
61654 #define A_MAC_PORT_MTIP_KR4_LANE_3_MAPPING 0x1a4c
61655 
61656 #define S_KR4_LANE_3_MAPPING    0
61657 #define M_KR4_LANE_3_MAPPING    0x3U
61658 #define V_KR4_LANE_3_MAPPING(x) ((x) << S_KR4_LANE_3_MAPPING)
61659 #define G_KR4_LANE_3_MAPPING(x) (((x) >> S_KR4_LANE_3_MAPPING) & M_KR4_LANE_3_MAPPING)
61660 
61661 #define A_MAC_PORT_MTIP_KR4_SCRATCH 0x1af0
61662 #define A_MAC_PORT_MTIP_KR4_CORE_REVISION 0x1af4
61663 #define A_MAC_PORT_MTIP_KR4_VL_INTVL 0x1af8
61664 
61665 #define S_SHRT_MRKR_CNFG    0
61666 #define V_SHRT_MRKR_CNFG(x) ((x) << S_SHRT_MRKR_CNFG)
61667 #define F_SHRT_MRKR_CNFG    V_SHRT_MRKR_CNFG(1U)
61668 
61669 #define A_MAC_PORT_MTIP_KR4_TX_LANE_THRESH 0x1afc
61670 #define A_MAC_PORT_MTIP_CR4_CONTROL_1 0x1b00
61671 #define A_MAC_PORT_MTIP_CR4_STATUS_1 0x1b04
61672 
61673 #define S_CR4_RX_LINK_STATUS    2
61674 #define V_CR4_RX_LINK_STATUS(x) ((x) << S_CR4_RX_LINK_STATUS)
61675 #define F_CR4_RX_LINK_STATUS    V_CR4_RX_LINK_STATUS(1U)
61676 
61677 #define A_MAC_PORT_MTIP_CR4_DEVICE_ID0 0x1b08
61678 
61679 #define S_CR4_DEVICE_ID0    0
61680 #define M_CR4_DEVICE_ID0    0xffffU
61681 #define V_CR4_DEVICE_ID0(x) ((x) << S_CR4_DEVICE_ID0)
61682 #define G_CR4_DEVICE_ID0(x) (((x) >> S_CR4_DEVICE_ID0) & M_CR4_DEVICE_ID0)
61683 
61684 #define A_MAC_PORT_MTIP_CR4_DEVICE_ID1 0x1b0c
61685 
61686 #define S_CR4_DEVICE_ID1    0
61687 #define M_CR4_DEVICE_ID1    0xffffU
61688 #define V_CR4_DEVICE_ID1(x) ((x) << S_CR4_DEVICE_ID1)
61689 #define G_CR4_DEVICE_ID1(x) (((x) >> S_CR4_DEVICE_ID1) & M_CR4_DEVICE_ID1)
61690 
61691 #define A_MAC_PORT_MTIP_CR4_SPEED_ABILITY 0x1b10
61692 
61693 #define S_CR4_100G_CAPABLE    8
61694 #define V_CR4_100G_CAPABLE(x) ((x) << S_CR4_100G_CAPABLE)
61695 #define F_CR4_100G_CAPABLE    V_CR4_100G_CAPABLE(1U)
61696 
61697 #define S_CR4_40G_CAPABLE    7
61698 #define V_CR4_40G_CAPABLE(x) ((x) << S_CR4_40G_CAPABLE)
61699 #define F_CR4_40G_CAPABLE    V_CR4_40G_CAPABLE(1U)
61700 
61701 #define A_MAC_PORT_MTIP_CR4_DEVICES_IN_PKG1 0x1b14
61702 
61703 #define S_CLAUSE22REG_PRESENT    0
61704 #define V_CLAUSE22REG_PRESENT(x) ((x) << S_CLAUSE22REG_PRESENT)
61705 #define F_CLAUSE22REG_PRESENT    V_CLAUSE22REG_PRESENT(1U)
61706 
61707 #define A_MAC_PORT_MTIP_CR4_DEVICES_IN_PKG2 0x1b18
61708 
61709 #define S_VSD_2_PRESENT    15
61710 #define V_VSD_2_PRESENT(x) ((x) << S_VSD_2_PRESENT)
61711 #define F_VSD_2_PRESENT    V_VSD_2_PRESENT(1U)
61712 
61713 #define S_VSD_1_PRESENT    14
61714 #define V_VSD_1_PRESENT(x) ((x) << S_VSD_1_PRESENT)
61715 #define F_VSD_1_PRESENT    V_VSD_1_PRESENT(1U)
61716 
61717 #define S_CLAUSE22_EXT_PRESENT    13
61718 #define V_CLAUSE22_EXT_PRESENT(x) ((x) << S_CLAUSE22_EXT_PRESENT)
61719 #define F_CLAUSE22_EXT_PRESENT    V_CLAUSE22_EXT_PRESENT(1U)
61720 
61721 #define A_MAC_PORT_MTIP_CR4_CONTROL_2 0x1b1c
61722 
61723 #define S_CR4_PCS_TYPE_SELECTION    0
61724 #define M_CR4_PCS_TYPE_SELECTION    0x7U
61725 #define V_CR4_PCS_TYPE_SELECTION(x) ((x) << S_CR4_PCS_TYPE_SELECTION)
61726 #define G_CR4_PCS_TYPE_SELECTION(x) (((x) >> S_CR4_PCS_TYPE_SELECTION) & M_CR4_PCS_TYPE_SELECTION)
61727 
61728 #define A_MAC_PORT_MTIP_CR4_STATUS_2 0x1b20
61729 #define A_MAC_PORT_MTIP_CR4_PKG_ID0 0x1b38
61730 #define A_MAC_PORT_MTIP_CR4_PKG_ID1 0x1b3c
61731 #define A_MAC_PORT_MTIP_CR4_BASE_R_STATUS_1 0x1b80
61732 
61733 #define S_RX_LINK_STAT    12
61734 #define V_RX_LINK_STAT(x) ((x) << S_RX_LINK_STAT)
61735 #define F_RX_LINK_STAT    V_RX_LINK_STAT(1U)
61736 
61737 #define S_BR_BLOCK_LOCK    0
61738 #define V_BR_BLOCK_LOCK(x) ((x) << S_BR_BLOCK_LOCK)
61739 #define F_BR_BLOCK_LOCK    V_BR_BLOCK_LOCK(1U)
61740 
61741 #define A_MAC_PORT_MTIP_CR4_BASE_R_STATUS_2 0x1b84
61742 
61743 #define S_BER_COUNTER    8
61744 #define M_BER_COUNTER    0x3fU
61745 #define V_BER_COUNTER(x) ((x) << S_BER_COUNTER)
61746 #define G_BER_COUNTER(x) (((x) >> S_BER_COUNTER) & M_BER_COUNTER)
61747 
61748 #define S_ERRORED_BLOCKS_CNTR    0
61749 #define M_ERRORED_BLOCKS_CNTR    0xffU
61750 #define V_ERRORED_BLOCKS_CNTR(x) ((x) << S_ERRORED_BLOCKS_CNTR)
61751 #define G_ERRORED_BLOCKS_CNTR(x) (((x) >> S_ERRORED_BLOCKS_CNTR) & M_ERRORED_BLOCKS_CNTR)
61752 
61753 #define A_MAC_PORT_MTIP_CR4_BASE_R_TEST_CONTROL 0x1ba8
61754 
61755 #define S_SCRAMBLED_ID_TP_EN    7
61756 #define V_SCRAMBLED_ID_TP_EN(x) ((x) << S_SCRAMBLED_ID_TP_EN)
61757 #define F_SCRAMBLED_ID_TP_EN    V_SCRAMBLED_ID_TP_EN(1U)
61758 
61759 #define A_MAC_PORT_MTIP_CR4_BASE_R_TEST_ERR_CNT 0x1bac
61760 
61761 #define S_BASE_R_TEST_ERR_CNT    0
61762 #define M_BASE_R_TEST_ERR_CNT    0xffffU
61763 #define V_BASE_R_TEST_ERR_CNT(x) ((x) << S_BASE_R_TEST_ERR_CNT)
61764 #define G_BASE_R_TEST_ERR_CNT(x) (((x) >> S_BASE_R_TEST_ERR_CNT) & M_BASE_R_TEST_ERR_CNT)
61765 
61766 #define A_MAC_PORT_MTIP_CR4_BER_HIGH_ORDER_CNT 0x1bb0
61767 
61768 #define S_BER_HIGH_ORDER_CNT    0
61769 #define M_BER_HIGH_ORDER_CNT    0xffffU
61770 #define V_BER_HIGH_ORDER_CNT(x) ((x) << S_BER_HIGH_ORDER_CNT)
61771 #define G_BER_HIGH_ORDER_CNT(x) (((x) >> S_BER_HIGH_ORDER_CNT) & M_BER_HIGH_ORDER_CNT)
61772 
61773 #define A_MAC_PORT_MTIP_CR4_ERR_BLK_HIGH_ORDER_CNT 0x1bb4
61774 
61775 #define S_HI_ORDER_CNT_PRESENT    15
61776 #define V_HI_ORDER_CNT_PRESENT(x) ((x) << S_HI_ORDER_CNT_PRESENT)
61777 #define F_HI_ORDER_CNT_PRESENT    V_HI_ORDER_CNT_PRESENT(1U)
61778 
61779 #define S_ERR_BLKS_CNTR    0
61780 #define M_ERR_BLKS_CNTR    0x3fffU
61781 #define V_ERR_BLKS_CNTR(x) ((x) << S_ERR_BLKS_CNTR)
61782 #define G_ERR_BLKS_CNTR(x) (((x) >> S_ERR_BLKS_CNTR) & M_ERR_BLKS_CNTR)
61783 
61784 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_1 0x1bc8
61785 
61786 #define S_LANE_ALIGN_STAT    12
61787 #define V_LANE_ALIGN_STAT(x) ((x) << S_LANE_ALIGN_STAT)
61788 #define F_LANE_ALIGN_STAT    V_LANE_ALIGN_STAT(1U)
61789 
61790 #define S_LANE_7_BLCK_LCK    7
61791 #define V_LANE_7_BLCK_LCK(x) ((x) << S_LANE_7_BLCK_LCK)
61792 #define F_LANE_7_BLCK_LCK    V_LANE_7_BLCK_LCK(1U)
61793 
61794 #define S_LANE_6_BLCK_LCK    6
61795 #define V_LANE_6_BLCK_LCK(x) ((x) << S_LANE_6_BLCK_LCK)
61796 #define F_LANE_6_BLCK_LCK    V_LANE_6_BLCK_LCK(1U)
61797 
61798 #define S_LANE_5_BLCK_LCK    5
61799 #define V_LANE_5_BLCK_LCK(x) ((x) << S_LANE_5_BLCK_LCK)
61800 #define F_LANE_5_BLCK_LCK    V_LANE_5_BLCK_LCK(1U)
61801 
61802 #define S_LANE_4_BLCK_LCK    4
61803 #define V_LANE_4_BLCK_LCK(x) ((x) << S_LANE_4_BLCK_LCK)
61804 #define F_LANE_4_BLCK_LCK    V_LANE_4_BLCK_LCK(1U)
61805 
61806 #define S_LANE_3_BLCK_LCK    3
61807 #define V_LANE_3_BLCK_LCK(x) ((x) << S_LANE_3_BLCK_LCK)
61808 #define F_LANE_3_BLCK_LCK    V_LANE_3_BLCK_LCK(1U)
61809 
61810 #define S_LANE_2_BLCK_LCK    2
61811 #define V_LANE_2_BLCK_LCK(x) ((x) << S_LANE_2_BLCK_LCK)
61812 #define F_LANE_2_BLCK_LCK    V_LANE_2_BLCK_LCK(1U)
61813 
61814 #define S_LANE_1_BLCK_LCK    1
61815 #define V_LANE_1_BLCK_LCK(x) ((x) << S_LANE_1_BLCK_LCK)
61816 #define F_LANE_1_BLCK_LCK    V_LANE_1_BLCK_LCK(1U)
61817 
61818 #define S_LANE_0_BLCK_LCK    0
61819 #define V_LANE_0_BLCK_LCK(x) ((x) << S_LANE_0_BLCK_LCK)
61820 #define F_LANE_0_BLCK_LCK    V_LANE_0_BLCK_LCK(1U)
61821 
61822 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_2 0x1bcc
61823 
61824 #define S_LANE_19_BLCK_LCK    11
61825 #define V_LANE_19_BLCK_LCK(x) ((x) << S_LANE_19_BLCK_LCK)
61826 #define F_LANE_19_BLCK_LCK    V_LANE_19_BLCK_LCK(1U)
61827 
61828 #define S_LANE_18_BLCK_LCK    10
61829 #define V_LANE_18_BLCK_LCK(x) ((x) << S_LANE_18_BLCK_LCK)
61830 #define F_LANE_18_BLCK_LCK    V_LANE_18_BLCK_LCK(1U)
61831 
61832 #define S_LANE_17_BLCK_LCK    9
61833 #define V_LANE_17_BLCK_LCK(x) ((x) << S_LANE_17_BLCK_LCK)
61834 #define F_LANE_17_BLCK_LCK    V_LANE_17_BLCK_LCK(1U)
61835 
61836 #define S_LANE_16_BLCK_LCK    8
61837 #define V_LANE_16_BLCK_LCK(x) ((x) << S_LANE_16_BLCK_LCK)
61838 #define F_LANE_16_BLCK_LCK    V_LANE_16_BLCK_LCK(1U)
61839 
61840 #define S_LANE_15_BLCK_LCK    7
61841 #define V_LANE_15_BLCK_LCK(x) ((x) << S_LANE_15_BLCK_LCK)
61842 #define F_LANE_15_BLCK_LCK    V_LANE_15_BLCK_LCK(1U)
61843 
61844 #define S_LANE_14_BLCK_LCK    6
61845 #define V_LANE_14_BLCK_LCK(x) ((x) << S_LANE_14_BLCK_LCK)
61846 #define F_LANE_14_BLCK_LCK    V_LANE_14_BLCK_LCK(1U)
61847 
61848 #define S_LANE_13_BLCK_LCK    5
61849 #define V_LANE_13_BLCK_LCK(x) ((x) << S_LANE_13_BLCK_LCK)
61850 #define F_LANE_13_BLCK_LCK    V_LANE_13_BLCK_LCK(1U)
61851 
61852 #define S_LANE_12_BLCK_LCK    4
61853 #define V_LANE_12_BLCK_LCK(x) ((x) << S_LANE_12_BLCK_LCK)
61854 #define F_LANE_12_BLCK_LCK    V_LANE_12_BLCK_LCK(1U)
61855 
61856 #define S_LANE_11_BLCK_LCK    3
61857 #define V_LANE_11_BLCK_LCK(x) ((x) << S_LANE_11_BLCK_LCK)
61858 #define F_LANE_11_BLCK_LCK    V_LANE_11_BLCK_LCK(1U)
61859 
61860 #define S_LANE_10_BLCK_LCK    2
61861 #define V_LANE_10_BLCK_LCK(x) ((x) << S_LANE_10_BLCK_LCK)
61862 #define F_LANE_10_BLCK_LCK    V_LANE_10_BLCK_LCK(1U)
61863 
61864 #define S_LANE_9_BLCK_LCK    1
61865 #define V_LANE_9_BLCK_LCK(x) ((x) << S_LANE_9_BLCK_LCK)
61866 #define F_LANE_9_BLCK_LCK    V_LANE_9_BLCK_LCK(1U)
61867 
61868 #define S_LANE_8_BLCK_LCK    0
61869 #define V_LANE_8_BLCK_LCK(x) ((x) << S_LANE_8_BLCK_LCK)
61870 #define F_LANE_8_BLCK_LCK    V_LANE_8_BLCK_LCK(1U)
61871 
61872 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_3 0x1bd0
61873 
61874 #define S_LANE7_ALGN_MRKR_LCK    7
61875 #define V_LANE7_ALGN_MRKR_LCK(x) ((x) << S_LANE7_ALGN_MRKR_LCK)
61876 #define F_LANE7_ALGN_MRKR_LCK    V_LANE7_ALGN_MRKR_LCK(1U)
61877 
61878 #define S_LANE6_ALGN_MRKR_LCK    6
61879 #define V_LANE6_ALGN_MRKR_LCK(x) ((x) << S_LANE6_ALGN_MRKR_LCK)
61880 #define F_LANE6_ALGN_MRKR_LCK    V_LANE6_ALGN_MRKR_LCK(1U)
61881 
61882 #define S_LANE5_ALGN_MRKR_LCK    5
61883 #define V_LANE5_ALGN_MRKR_LCK(x) ((x) << S_LANE5_ALGN_MRKR_LCK)
61884 #define F_LANE5_ALGN_MRKR_LCK    V_LANE5_ALGN_MRKR_LCK(1U)
61885 
61886 #define S_LANE4_ALGN_MRKR_LCK    4
61887 #define V_LANE4_ALGN_MRKR_LCK(x) ((x) << S_LANE4_ALGN_MRKR_LCK)
61888 #define F_LANE4_ALGN_MRKR_LCK    V_LANE4_ALGN_MRKR_LCK(1U)
61889 
61890 #define S_LANE3_ALGN_MRKR_LCK    3
61891 #define V_LANE3_ALGN_MRKR_LCK(x) ((x) << S_LANE3_ALGN_MRKR_LCK)
61892 #define F_LANE3_ALGN_MRKR_LCK    V_LANE3_ALGN_MRKR_LCK(1U)
61893 
61894 #define S_LANE2_ALGN_MRKR_LCK    2
61895 #define V_LANE2_ALGN_MRKR_LCK(x) ((x) << S_LANE2_ALGN_MRKR_LCK)
61896 #define F_LANE2_ALGN_MRKR_LCK    V_LANE2_ALGN_MRKR_LCK(1U)
61897 
61898 #define S_LANE1_ALGN_MRKR_LCK    1
61899 #define V_LANE1_ALGN_MRKR_LCK(x) ((x) << S_LANE1_ALGN_MRKR_LCK)
61900 #define F_LANE1_ALGN_MRKR_LCK    V_LANE1_ALGN_MRKR_LCK(1U)
61901 
61902 #define S_LANE0_ALGN_MRKR_LCK    0
61903 #define V_LANE0_ALGN_MRKR_LCK(x) ((x) << S_LANE0_ALGN_MRKR_LCK)
61904 #define F_LANE0_ALGN_MRKR_LCK    V_LANE0_ALGN_MRKR_LCK(1U)
61905 
61906 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_4 0x1bd4
61907 
61908 #define S_LANE19_ALGN_MRKR_LCK    11
61909 #define V_LANE19_ALGN_MRKR_LCK(x) ((x) << S_LANE19_ALGN_MRKR_LCK)
61910 #define F_LANE19_ALGN_MRKR_LCK    V_LANE19_ALGN_MRKR_LCK(1U)
61911 
61912 #define S_LANE18_ALGN_MRKR_LCK    10
61913 #define V_LANE18_ALGN_MRKR_LCK(x) ((x) << S_LANE18_ALGN_MRKR_LCK)
61914 #define F_LANE18_ALGN_MRKR_LCK    V_LANE18_ALGN_MRKR_LCK(1U)
61915 
61916 #define S_LANE17_ALGN_MRKR_LCK    9
61917 #define V_LANE17_ALGN_MRKR_LCK(x) ((x) << S_LANE17_ALGN_MRKR_LCK)
61918 #define F_LANE17_ALGN_MRKR_LCK    V_LANE17_ALGN_MRKR_LCK(1U)
61919 
61920 #define S_LANE16_ALGN_MRKR_LCK    8
61921 #define V_LANE16_ALGN_MRKR_LCK(x) ((x) << S_LANE16_ALGN_MRKR_LCK)
61922 #define F_LANE16_ALGN_MRKR_LCK    V_LANE16_ALGN_MRKR_LCK(1U)
61923 
61924 #define S_LANE15_ALGN_MRKR_LCK    7
61925 #define V_LANE15_ALGN_MRKR_LCK(x) ((x) << S_LANE15_ALGN_MRKR_LCK)
61926 #define F_LANE15_ALGN_MRKR_LCK    V_LANE15_ALGN_MRKR_LCK(1U)
61927 
61928 #define S_LANE14_ALGN_MRKR_LCK    6
61929 #define V_LANE14_ALGN_MRKR_LCK(x) ((x) << S_LANE14_ALGN_MRKR_LCK)
61930 #define F_LANE14_ALGN_MRKR_LCK    V_LANE14_ALGN_MRKR_LCK(1U)
61931 
61932 #define S_LANE13_ALGN_MRKR_LCK    5
61933 #define V_LANE13_ALGN_MRKR_LCK(x) ((x) << S_LANE13_ALGN_MRKR_LCK)
61934 #define F_LANE13_ALGN_MRKR_LCK    V_LANE13_ALGN_MRKR_LCK(1U)
61935 
61936 #define S_LANE12_ALGN_MRKR_LCK    4
61937 #define V_LANE12_ALGN_MRKR_LCK(x) ((x) << S_LANE12_ALGN_MRKR_LCK)
61938 #define F_LANE12_ALGN_MRKR_LCK    V_LANE12_ALGN_MRKR_LCK(1U)
61939 
61940 #define S_LANE11_ALGN_MRKR_LCK    3
61941 #define V_LANE11_ALGN_MRKR_LCK(x) ((x) << S_LANE11_ALGN_MRKR_LCK)
61942 #define F_LANE11_ALGN_MRKR_LCK    V_LANE11_ALGN_MRKR_LCK(1U)
61943 
61944 #define S_LANE10_ALGN_MRKR_LCK    2
61945 #define V_LANE10_ALGN_MRKR_LCK(x) ((x) << S_LANE10_ALGN_MRKR_LCK)
61946 #define F_LANE10_ALGN_MRKR_LCK    V_LANE10_ALGN_MRKR_LCK(1U)
61947 
61948 #define S_LANE9_ALGN_MRKR_LCK    1
61949 #define V_LANE9_ALGN_MRKR_LCK(x) ((x) << S_LANE9_ALGN_MRKR_LCK)
61950 #define F_LANE9_ALGN_MRKR_LCK    V_LANE9_ALGN_MRKR_LCK(1U)
61951 
61952 #define S_LANE8_ALGN_MRKR_LCK    0
61953 #define V_LANE8_ALGN_MRKR_LCK(x) ((x) << S_LANE8_ALGN_MRKR_LCK)
61954 #define F_LANE8_ALGN_MRKR_LCK    V_LANE8_ALGN_MRKR_LCK(1U)
61955 
61956 #define A_MAC_PORT_MTIP_PCS_CTL 0x1e00
61957 
61958 #define S_PCS_LPBK    14
61959 #define V_PCS_LPBK(x) ((x) << S_PCS_LPBK)
61960 #define F_PCS_LPBK    V_PCS_LPBK(1U)
61961 
61962 #define S_SPEED_SEL1    13
61963 #define V_SPEED_SEL1(x) ((x) << S_SPEED_SEL1)
61964 #define F_SPEED_SEL1    V_SPEED_SEL1(1U)
61965 
61966 #define S_LP_MODE    11
61967 #define V_LP_MODE(x) ((x) << S_LP_MODE)
61968 #define F_LP_MODE    V_LP_MODE(1U)
61969 
61970 #define S_SPEED_SEL0    6
61971 #define V_SPEED_SEL0(x) ((x) << S_SPEED_SEL0)
61972 #define F_SPEED_SEL0    V_SPEED_SEL0(1U)
61973 
61974 #define S_PCS_SPEED    2
61975 #define M_PCS_SPEED    0xfU
61976 #define V_PCS_SPEED(x) ((x) << S_PCS_SPEED)
61977 #define G_PCS_SPEED(x) (((x) >> S_PCS_SPEED) & M_PCS_SPEED)
61978 
61979 #define A_MAC_PORT_MTIP_PCS_STATUS1 0x1e04
61980 
61981 #define S_FAULTDET    7
61982 #define V_FAULTDET(x) ((x) << S_FAULTDET)
61983 #define F_FAULTDET    V_FAULTDET(1U)
61984 
61985 #define S_RX_LINK_STATUS    2
61986 #define V_RX_LINK_STATUS(x) ((x) << S_RX_LINK_STATUS)
61987 #define F_RX_LINK_STATUS    V_RX_LINK_STATUS(1U)
61988 
61989 #define S_LOPWRABL    1
61990 #define V_LOPWRABL(x) ((x) << S_LOPWRABL)
61991 #define F_LOPWRABL    V_LOPWRABL(1U)
61992 
61993 #define A_MAC_PORT_MTIP_PCS_DEVICE_ID0 0x1e08
61994 
61995 #define S_DEVICE_ID0    0
61996 #define M_DEVICE_ID0    0xffffU
61997 #define V_DEVICE_ID0(x) ((x) << S_DEVICE_ID0)
61998 #define G_DEVICE_ID0(x) (((x) >> S_DEVICE_ID0) & M_DEVICE_ID0)
61999 
62000 #define A_MAC_PORT_MTIP_PCS_DEVICE_ID1 0x1e0c
62001 
62002 #define S_DEVICE_ID1    0
62003 #define M_DEVICE_ID1    0xffffU
62004 #define V_DEVICE_ID1(x) ((x) << S_DEVICE_ID1)
62005 #define G_DEVICE_ID1(x) (((x) >> S_DEVICE_ID1) & M_DEVICE_ID1)
62006 
62007 #define A_MAC_PORT_MTIP_PCS_SPEED_ABILITY 0x1e10
62008 
62009 #define S_100G    8
62010 #define V_100G(x) ((x) << S_100G)
62011 #define F_100G    V_100G(1U)
62012 
62013 #define S_40G    7
62014 #define V_40G(x) ((x) << S_40G)
62015 #define F_40G    V_40G(1U)
62016 
62017 #define S_10BASE_TL    1
62018 #define V_10BASE_TL(x) ((x) << S_10BASE_TL)
62019 #define F_10BASE_TL    V_10BASE_TL(1U)
62020 
62021 #define S_10G    0
62022 #define V_10G(x) ((x) << S_10G)
62023 #define F_10G    V_10G(1U)
62024 
62025 #define A_MAC_PORT_MTIP_PCS_DEVICE_PKG1 0x1e14
62026 
62027 #define S_TC_PRESENT    6
62028 #define V_TC_PRESENT(x) ((x) << S_TC_PRESENT)
62029 #define F_TC_PRESENT    V_TC_PRESENT(1U)
62030 
62031 #define S_DTEXS    5
62032 #define V_DTEXS(x) ((x) << S_DTEXS)
62033 #define F_DTEXS    V_DTEXS(1U)
62034 
62035 #define S_PHYXS    4
62036 #define V_PHYXS(x) ((x) << S_PHYXS)
62037 #define F_PHYXS    V_PHYXS(1U)
62038 
62039 #define S_PCS    3
62040 #define V_PCS(x) ((x) << S_PCS)
62041 #define F_PCS    V_PCS(1U)
62042 
62043 #define S_WIS    2
62044 #define V_WIS(x) ((x) << S_WIS)
62045 #define F_WIS    V_WIS(1U)
62046 
62047 #define S_PMD_PMA    1
62048 #define V_PMD_PMA(x) ((x) << S_PMD_PMA)
62049 #define F_PMD_PMA    V_PMD_PMA(1U)
62050 
62051 #define S_CL22    0
62052 #define V_CL22(x) ((x) << S_CL22)
62053 #define F_CL22    V_CL22(1U)
62054 
62055 #define A_MAC_PORT_MTIP_PCS_DEVICE_PKG2 0x1e18
62056 
62057 #define S_VENDDEV2    15
62058 #define V_VENDDEV2(x) ((x) << S_VENDDEV2)
62059 #define F_VENDDEV2    V_VENDDEV2(1U)
62060 
62061 #define S_VENDDEV1    14
62062 #define V_VENDDEV1(x) ((x) << S_VENDDEV1)
62063 #define F_VENDDEV1    V_VENDDEV1(1U)
62064 
62065 #define S_CL22EXT    13
62066 #define V_CL22EXT(x) ((x) << S_CL22EXT)
62067 #define F_CL22EXT    V_CL22EXT(1U)
62068 
62069 #define A_MAC_PORT_MTIP_PCS_CTL2 0x1e1c
62070 
62071 #define S_PCSTYPE    0
62072 #define M_PCSTYPE    0x7U
62073 #define V_PCSTYPE(x) ((x) << S_PCSTYPE)
62074 #define G_PCSTYPE(x) (((x) >> S_PCSTYPE) & M_PCSTYPE)
62075 
62076 #define A_MAC_PORT_MTIP_PCS_STATUS2 0x1e20
62077 
62078 #define S_PCS_STAT2_DEVICE    15
62079 #define V_PCS_STAT2_DEVICE(x) ((x) << S_PCS_STAT2_DEVICE)
62080 #define F_PCS_STAT2_DEVICE    V_PCS_STAT2_DEVICE(1U)
62081 
62082 #define S_TXFAULT    7
62083 #define V_TXFAULT(x) ((x) << S_TXFAULT)
62084 #define F_TXFAULT    V_TXFAULT(1U)
62085 
62086 #define S_RXFAULT    6
62087 #define V_RXFAULT(x) ((x) << S_RXFAULT)
62088 #define F_RXFAULT    V_RXFAULT(1U)
62089 
62090 #define S_100BASE_R    5
62091 #define V_100BASE_R(x) ((x) << S_100BASE_R)
62092 #define F_100BASE_R    V_100BASE_R(1U)
62093 
62094 #define S_40GBASE_R    4
62095 #define V_40GBASE_R(x) ((x) << S_40GBASE_R)
62096 #define F_40GBASE_R    V_40GBASE_R(1U)
62097 
62098 #define S_10GBASE_T    3
62099 #define V_10GBASE_T(x) ((x) << S_10GBASE_T)
62100 #define F_10GBASE_T    V_10GBASE_T(1U)
62101 
62102 #define S_10GBASE_W    2
62103 #define V_10GBASE_W(x) ((x) << S_10GBASE_W)
62104 #define F_10GBASE_W    V_10GBASE_W(1U)
62105 
62106 #define S_10GBASE_X    1
62107 #define V_10GBASE_X(x) ((x) << S_10GBASE_X)
62108 #define F_10GBASE_X    V_10GBASE_X(1U)
62109 
62110 #define S_10GBASE_R    0
62111 #define V_10GBASE_R(x) ((x) << S_10GBASE_R)
62112 #define F_10GBASE_R    V_10GBASE_R(1U)
62113 
62114 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_0 0x1e20
62115 
62116 #define S_BIP_ERR_CNTLANE_0    0
62117 #define M_BIP_ERR_CNTLANE_0    0xffffU
62118 #define V_BIP_ERR_CNTLANE_0(x) ((x) << S_BIP_ERR_CNTLANE_0)
62119 #define G_BIP_ERR_CNTLANE_0(x) (((x) >> S_BIP_ERR_CNTLANE_0) & M_BIP_ERR_CNTLANE_0)
62120 
62121 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_1 0x1e24
62122 
62123 #define S_BIP_ERR_CNTLANE_1    0
62124 #define M_BIP_ERR_CNTLANE_1    0xffffU
62125 #define V_BIP_ERR_CNTLANE_1(x) ((x) << S_BIP_ERR_CNTLANE_1)
62126 #define G_BIP_ERR_CNTLANE_1(x) (((x) >> S_BIP_ERR_CNTLANE_1) & M_BIP_ERR_CNTLANE_1)
62127 
62128 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_2 0x1e28
62129 
62130 #define S_BIP_ERR_CNTLANE_2    0
62131 #define M_BIP_ERR_CNTLANE_2    0xffffU
62132 #define V_BIP_ERR_CNTLANE_2(x) ((x) << S_BIP_ERR_CNTLANE_2)
62133 #define G_BIP_ERR_CNTLANE_2(x) (((x) >> S_BIP_ERR_CNTLANE_2) & M_BIP_ERR_CNTLANE_2)
62134 
62135 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_3 0x1e2c
62136 
62137 #define S_BIP_ERR_CNTLANE_3    0
62138 #define M_BIP_ERR_CNTLANE_3    0xffffU
62139 #define V_BIP_ERR_CNTLANE_3(x) ((x) << S_BIP_ERR_CNTLANE_3)
62140 #define G_BIP_ERR_CNTLANE_3(x) (((x) >> S_BIP_ERR_CNTLANE_3) & M_BIP_ERR_CNTLANE_3)
62141 
62142 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_4 0x1e30
62143 
62144 #define S_BIP_ERR_CNTLANE_4    0
62145 #define M_BIP_ERR_CNTLANE_4    0xffffU
62146 #define V_BIP_ERR_CNTLANE_4(x) ((x) << S_BIP_ERR_CNTLANE_4)
62147 #define G_BIP_ERR_CNTLANE_4(x) (((x) >> S_BIP_ERR_CNTLANE_4) & M_BIP_ERR_CNTLANE_4)
62148 
62149 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_5 0x1e34
62150 
62151 #define S_BIP_ERR_CNTLANE_5    0
62152 #define M_BIP_ERR_CNTLANE_5    0xffffU
62153 #define V_BIP_ERR_CNTLANE_5(x) ((x) << S_BIP_ERR_CNTLANE_5)
62154 #define G_BIP_ERR_CNTLANE_5(x) (((x) >> S_BIP_ERR_CNTLANE_5) & M_BIP_ERR_CNTLANE_5)
62155 
62156 #define A_MAC_PORT_MTIP_PCS_PKG_ID0 0x1e38
62157 
62158 #define S_PKG_ID0    0
62159 #define M_PKG_ID0    0xffffU
62160 #define V_PKG_ID0(x) ((x) << S_PKG_ID0)
62161 #define G_PKG_ID0(x) (((x) >> S_PKG_ID0) & M_PKG_ID0)
62162 
62163 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_6 0x1e38
62164 
62165 #define S_BIP_ERR_CNTLANE_6    0
62166 #define M_BIP_ERR_CNTLANE_6    0xffffU
62167 #define V_BIP_ERR_CNTLANE_6(x) ((x) << S_BIP_ERR_CNTLANE_6)
62168 #define G_BIP_ERR_CNTLANE_6(x) (((x) >> S_BIP_ERR_CNTLANE_6) & M_BIP_ERR_CNTLANE_6)
62169 
62170 #define A_MAC_PORT_MTIP_PCS_PKG_ID1 0x1e3c
62171 
62172 #define S_PKG_ID1    0
62173 #define M_PKG_ID1    0xffffU
62174 #define V_PKG_ID1(x) ((x) << S_PKG_ID1)
62175 #define G_PKG_ID1(x) (((x) >> S_PKG_ID1) & M_PKG_ID1)
62176 
62177 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_7 0x1e3c
62178 
62179 #define S_BIP_ERR_CNTLANE_7    0
62180 #define M_BIP_ERR_CNTLANE_7    0xffffU
62181 #define V_BIP_ERR_CNTLANE_7(x) ((x) << S_BIP_ERR_CNTLANE_7)
62182 #define G_BIP_ERR_CNTLANE_7(x) (((x) >> S_BIP_ERR_CNTLANE_7) & M_BIP_ERR_CNTLANE_7)
62183 
62184 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_8 0x1e40
62185 
62186 #define S_BIP_ERR_CNTLANE_8    0
62187 #define M_BIP_ERR_CNTLANE_8    0xffffU
62188 #define V_BIP_ERR_CNTLANE_8(x) ((x) << S_BIP_ERR_CNTLANE_8)
62189 #define G_BIP_ERR_CNTLANE_8(x) (((x) >> S_BIP_ERR_CNTLANE_8) & M_BIP_ERR_CNTLANE_8)
62190 
62191 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_9 0x1e44
62192 
62193 #define S_BIP_ERR_CNTLANE_9    0
62194 #define M_BIP_ERR_CNTLANE_9    0xffffU
62195 #define V_BIP_ERR_CNTLANE_9(x) ((x) << S_BIP_ERR_CNTLANE_9)
62196 #define G_BIP_ERR_CNTLANE_9(x) (((x) >> S_BIP_ERR_CNTLANE_9) & M_BIP_ERR_CNTLANE_9)
62197 
62198 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_10 0x1e48
62199 
62200 #define S_BIP_ERR_CNTLANE_10    0
62201 #define M_BIP_ERR_CNTLANE_10    0xffffU
62202 #define V_BIP_ERR_CNTLANE_10(x) ((x) << S_BIP_ERR_CNTLANE_10)
62203 #define G_BIP_ERR_CNTLANE_10(x) (((x) >> S_BIP_ERR_CNTLANE_10) & M_BIP_ERR_CNTLANE_10)
62204 
62205 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_11 0x1e4c
62206 
62207 #define S_BIP_ERR_CNTLANE_11    0
62208 #define M_BIP_ERR_CNTLANE_11    0xffffU
62209 #define V_BIP_ERR_CNTLANE_11(x) ((x) << S_BIP_ERR_CNTLANE_11)
62210 #define G_BIP_ERR_CNTLANE_11(x) (((x) >> S_BIP_ERR_CNTLANE_11) & M_BIP_ERR_CNTLANE_11)
62211 
62212 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_12 0x1e50
62213 
62214 #define S_BIP_ERR_CNTLANE_12    0
62215 #define M_BIP_ERR_CNTLANE_12    0xffffU
62216 #define V_BIP_ERR_CNTLANE_12(x) ((x) << S_BIP_ERR_CNTLANE_12)
62217 #define G_BIP_ERR_CNTLANE_12(x) (((x) >> S_BIP_ERR_CNTLANE_12) & M_BIP_ERR_CNTLANE_12)
62218 
62219 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_13 0x1e54
62220 
62221 #define S_BIP_ERR_CNTLANE_13    0
62222 #define M_BIP_ERR_CNTLANE_13    0xffffU
62223 #define V_BIP_ERR_CNTLANE_13(x) ((x) << S_BIP_ERR_CNTLANE_13)
62224 #define G_BIP_ERR_CNTLANE_13(x) (((x) >> S_BIP_ERR_CNTLANE_13) & M_BIP_ERR_CNTLANE_13)
62225 
62226 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_14 0x1e58
62227 
62228 #define S_BIP_ERR_CNTLANE_14    0
62229 #define M_BIP_ERR_CNTLANE_14    0xffffU
62230 #define V_BIP_ERR_CNTLANE_14(x) ((x) << S_BIP_ERR_CNTLANE_14)
62231 #define G_BIP_ERR_CNTLANE_14(x) (((x) >> S_BIP_ERR_CNTLANE_14) & M_BIP_ERR_CNTLANE_14)
62232 
62233 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_15 0x1e5c
62234 
62235 #define S_BIP_ERR_CNTLANE_15    0
62236 #define M_BIP_ERR_CNTLANE_15    0xffffU
62237 #define V_BIP_ERR_CNTLANE_15(x) ((x) << S_BIP_ERR_CNTLANE_15)
62238 #define G_BIP_ERR_CNTLANE_15(x) (((x) >> S_BIP_ERR_CNTLANE_15) & M_BIP_ERR_CNTLANE_15)
62239 
62240 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_16 0x1e60
62241 
62242 #define S_BIP_ERR_CNTLANE_16    0
62243 #define M_BIP_ERR_CNTLANE_16    0xffffU
62244 #define V_BIP_ERR_CNTLANE_16(x) ((x) << S_BIP_ERR_CNTLANE_16)
62245 #define G_BIP_ERR_CNTLANE_16(x) (((x) >> S_BIP_ERR_CNTLANE_16) & M_BIP_ERR_CNTLANE_16)
62246 
62247 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_17 0x1e64
62248 
62249 #define S_BIP_ERR_CNTLANE_17    0
62250 #define M_BIP_ERR_CNTLANE_17    0xffffU
62251 #define V_BIP_ERR_CNTLANE_17(x) ((x) << S_BIP_ERR_CNTLANE_17)
62252 #define G_BIP_ERR_CNTLANE_17(x) (((x) >> S_BIP_ERR_CNTLANE_17) & M_BIP_ERR_CNTLANE_17)
62253 
62254 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_18 0x1e68
62255 
62256 #define S_BIP_ERR_CNTLANE_18    0
62257 #define M_BIP_ERR_CNTLANE_18    0xffffU
62258 #define V_BIP_ERR_CNTLANE_18(x) ((x) << S_BIP_ERR_CNTLANE_18)
62259 #define G_BIP_ERR_CNTLANE_18(x) (((x) >> S_BIP_ERR_CNTLANE_18) & M_BIP_ERR_CNTLANE_18)
62260 
62261 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_19 0x1e6c
62262 
62263 #define S_BIP_ERR_CNTLANE_19    0
62264 #define M_BIP_ERR_CNTLANE_19    0xffffU
62265 #define V_BIP_ERR_CNTLANE_19(x) ((x) << S_BIP_ERR_CNTLANE_19)
62266 #define G_BIP_ERR_CNTLANE_19(x) (((x) >> S_BIP_ERR_CNTLANE_19) & M_BIP_ERR_CNTLANE_19)
62267 
62268 #define A_MAC_PORT_MTIP_PCS_BASER_STATUS1 0x1e80
62269 
62270 #define S_RXLINKSTATUS    12
62271 #define V_RXLINKSTATUS(x) ((x) << S_RXLINKSTATUS)
62272 #define F_RXLINKSTATUS    V_RXLINKSTATUS(1U)
62273 
62274 #define S_RESEREVED    4
62275 #define M_RESEREVED    0xffU
62276 #define V_RESEREVED(x) ((x) << S_RESEREVED)
62277 #define G_RESEREVED(x) (((x) >> S_RESEREVED) & M_RESEREVED)
62278 
62279 #define S_10GPRBS9    3
62280 #define V_10GPRBS9(x) ((x) << S_10GPRBS9)
62281 #define F_10GPRBS9    V_10GPRBS9(1U)
62282 
62283 #define S_10GPRBS31    2
62284 #define V_10GPRBS31(x) ((x) << S_10GPRBS31)
62285 #define F_10GPRBS31    V_10GPRBS31(1U)
62286 
62287 #define S_HIBER    1
62288 #define V_HIBER(x) ((x) << S_HIBER)
62289 #define F_HIBER    V_HIBER(1U)
62290 
62291 #define S_BLOCKLOCK    0
62292 #define V_BLOCKLOCK(x) ((x) << S_BLOCKLOCK)
62293 #define F_BLOCKLOCK    V_BLOCKLOCK(1U)
62294 
62295 #define A_MAC_PORT_MTIP_PCS_BASER_STATUS2 0x1e84
62296 
62297 #define S_BLOCKLOCKLL    15
62298 #define V_BLOCKLOCKLL(x) ((x) << S_BLOCKLOCKLL)
62299 #define F_BLOCKLOCKLL    V_BLOCKLOCKLL(1U)
62300 
62301 #define S_HIBERLH    14
62302 #define V_HIBERLH(x) ((x) << S_HIBERLH)
62303 #define F_HIBERLH    V_HIBERLH(1U)
62304 
62305 #define S_HIBERCOUNT    8
62306 #define M_HIBERCOUNT    0x3fU
62307 #define V_HIBERCOUNT(x) ((x) << S_HIBERCOUNT)
62308 #define G_HIBERCOUNT(x) (((x) >> S_HIBERCOUNT) & M_HIBERCOUNT)
62309 
62310 #define S_ERRBLKCNT    0
62311 #define M_ERRBLKCNT    0xffU
62312 #define V_ERRBLKCNT(x) ((x) << S_ERRBLKCNT)
62313 #define G_ERRBLKCNT(x) (((x) >> S_ERRBLKCNT) & M_ERRBLKCNT)
62314 
62315 #define A_MAC_PORT_MTIP_10GBASER_SEED_A 0x1e88
62316 
62317 #define S_SEEDA    0
62318 #define M_SEEDA    0xffffU
62319 #define V_SEEDA(x) ((x) << S_SEEDA)
62320 #define G_SEEDA(x) (((x) >> S_SEEDA) & M_SEEDA)
62321 
62322 #define A_MAC_PORT_MTIP_10GBASER_SEED_A1 0x1e8c
62323 
62324 #define S_SEEDA1    0
62325 #define M_SEEDA1    0xffffU
62326 #define V_SEEDA1(x) ((x) << S_SEEDA1)
62327 #define G_SEEDA1(x) (((x) >> S_SEEDA1) & M_SEEDA1)
62328 
62329 #define A_MAC_PORT_MTIP_10GBASER_SEED_A2 0x1e90
62330 
62331 #define S_SEEDA2    0
62332 #define M_SEEDA2    0xffffU
62333 #define V_SEEDA2(x) ((x) << S_SEEDA2)
62334 #define G_SEEDA2(x) (((x) >> S_SEEDA2) & M_SEEDA2)
62335 
62336 #define A_MAC_PORT_MTIP_10GBASER_SEED_A3 0x1e94
62337 
62338 #define S_SEEDA3    0
62339 #define M_SEEDA3    0x3ffU
62340 #define V_SEEDA3(x) ((x) << S_SEEDA3)
62341 #define G_SEEDA3(x) (((x) >> S_SEEDA3) & M_SEEDA3)
62342 
62343 #define A_MAC_PORT_MTIP_10GBASER_SEED_B 0x1e98
62344 
62345 #define S_SEEDB    0
62346 #define M_SEEDB    0xffffU
62347 #define V_SEEDB(x) ((x) << S_SEEDB)
62348 #define G_SEEDB(x) (((x) >> S_SEEDB) & M_SEEDB)
62349 
62350 #define A_MAC_PORT_MTIP_10GBASER_SEED_B1 0x1e9c
62351 
62352 #define S_SEEDB1    0
62353 #define M_SEEDB1    0xffffU
62354 #define V_SEEDB1(x) ((x) << S_SEEDB1)
62355 #define G_SEEDB1(x) (((x) >> S_SEEDB1) & M_SEEDB1)
62356 
62357 #define A_MAC_PORT_MTIP_10GBASER_SEED_B2 0x1ea0
62358 
62359 #define S_SEEDB2    0
62360 #define M_SEEDB2    0xffffU
62361 #define V_SEEDB2(x) ((x) << S_SEEDB2)
62362 #define G_SEEDB2(x) (((x) >> S_SEEDB2) & M_SEEDB2)
62363 
62364 #define A_MAC_PORT_MTIP_10GBASER_SEED_B3 0x1ea4
62365 
62366 #define S_SEEDB3    0
62367 #define M_SEEDB3    0x3ffU
62368 #define V_SEEDB3(x) ((x) << S_SEEDB3)
62369 #define G_SEEDB3(x) (((x) >> S_SEEDB3) & M_SEEDB3)
62370 
62371 #define A_MAC_PORT_MTIP_BASER_TEST_CTRL 0x1ea8
62372 
62373 #define S_TXPRBS9    6
62374 #define V_TXPRBS9(x) ((x) << S_TXPRBS9)
62375 #define F_TXPRBS9    V_TXPRBS9(1U)
62376 
62377 #define S_RXPRBS31    5
62378 #define V_RXPRBS31(x) ((x) << S_RXPRBS31)
62379 #define F_RXPRBS31    V_RXPRBS31(1U)
62380 
62381 #define S_TXPRBS31    4
62382 #define V_TXPRBS31(x) ((x) << S_TXPRBS31)
62383 #define F_TXPRBS31    V_TXPRBS31(1U)
62384 
62385 #define S_TXTESTPATEN    3
62386 #define V_TXTESTPATEN(x) ((x) << S_TXTESTPATEN)
62387 #define F_TXTESTPATEN    V_TXTESTPATEN(1U)
62388 
62389 #define S_RXTESTPATEN    2
62390 #define V_RXTESTPATEN(x) ((x) << S_RXTESTPATEN)
62391 #define F_RXTESTPATEN    V_RXTESTPATEN(1U)
62392 
62393 #define S_TESTPATSEL    1
62394 #define V_TESTPATSEL(x) ((x) << S_TESTPATSEL)
62395 #define F_TESTPATSEL    V_TESTPATSEL(1U)
62396 
62397 #define S_DATAPATSEL    0
62398 #define V_DATAPATSEL(x) ((x) << S_DATAPATSEL)
62399 #define F_DATAPATSEL    V_DATAPATSEL(1U)
62400 
62401 #define A_MAC_PORT_MTIP_BASER_TEST_ERR_CNT 0x1eac
62402 
62403 #define S_TEST_ERR_CNT    0
62404 #define M_TEST_ERR_CNT    0xffffU
62405 #define V_TEST_ERR_CNT(x) ((x) << S_TEST_ERR_CNT)
62406 #define G_TEST_ERR_CNT(x) (((x) >> S_TEST_ERR_CNT) & M_TEST_ERR_CNT)
62407 
62408 #define A_MAC_PORT_MTIP_BER_HIGH_ORDER_CNT 0x1eb0
62409 
62410 #define S_BER_CNT_HI    0
62411 #define M_BER_CNT_HI    0xffffU
62412 #define V_BER_CNT_HI(x) ((x) << S_BER_CNT_HI)
62413 #define G_BER_CNT_HI(x) (((x) >> S_BER_CNT_HI) & M_BER_CNT_HI)
62414 
62415 #define A_MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT 0x1eb4
62416 
62417 #define S_HICOUNTPRSNT    15
62418 #define V_HICOUNTPRSNT(x) ((x) << S_HICOUNTPRSNT)
62419 #define F_HICOUNTPRSNT    V_HICOUNTPRSNT(1U)
62420 
62421 #define S_BLOCK_CNT_HI    0
62422 #define M_BLOCK_CNT_HI    0x3fffU
62423 #define V_BLOCK_CNT_HI(x) ((x) << S_BLOCK_CNT_HI)
62424 #define G_BLOCK_CNT_HI(x) (((x) >> S_BLOCK_CNT_HI) & M_BLOCK_CNT_HI)
62425 
62426 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1 0x1ec8
62427 
62428 #define S_ALIGNSTATUS    12
62429 #define V_ALIGNSTATUS(x) ((x) << S_ALIGNSTATUS)
62430 #define F_ALIGNSTATUS    V_ALIGNSTATUS(1U)
62431 
62432 #define S_LANE7    7
62433 #define V_LANE7(x) ((x) << S_LANE7)
62434 #define F_LANE7    V_LANE7(1U)
62435 
62436 #define S_LANE6    6
62437 #define V_LANE6(x) ((x) << S_LANE6)
62438 #define F_LANE6    V_LANE6(1U)
62439 
62440 #define S_LANE5    5
62441 #define V_LANE5(x) ((x) << S_LANE5)
62442 #define F_LANE5    V_LANE5(1U)
62443 
62444 #define S_LANE4    4
62445 #define V_LANE4(x) ((x) << S_LANE4)
62446 #define F_LANE4    V_LANE4(1U)
62447 
62448 #define S_LANE3    3
62449 #define V_LANE3(x) ((x) << S_LANE3)
62450 #define F_LANE3    V_LANE3(1U)
62451 
62452 #define S_LANE2    2
62453 #define V_LANE2(x) ((x) << S_LANE2)
62454 #define F_LANE2    V_LANE2(1U)
62455 
62456 #define S_LANE1    1
62457 #define V_LANE1(x) ((x) << S_LANE1)
62458 #define F_LANE1    V_LANE1(1U)
62459 
62460 #define S_LANE0    0
62461 #define V_LANE0(x) ((x) << S_LANE0)
62462 #define F_LANE0    V_LANE0(1U)
62463 
62464 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2 0x1ecc
62465 
62466 #define S_LANE19    11
62467 #define V_LANE19(x) ((x) << S_LANE19)
62468 #define F_LANE19    V_LANE19(1U)
62469 
62470 #define S_LANE18    10
62471 #define V_LANE18(x) ((x) << S_LANE18)
62472 #define F_LANE18    V_LANE18(1U)
62473 
62474 #define S_LANE17    9
62475 #define V_LANE17(x) ((x) << S_LANE17)
62476 #define F_LANE17    V_LANE17(1U)
62477 
62478 #define S_LANE16    8
62479 #define V_LANE16(x) ((x) << S_LANE16)
62480 #define F_LANE16    V_LANE16(1U)
62481 
62482 #define S_LANE15    7
62483 #define V_LANE15(x) ((x) << S_LANE15)
62484 #define F_LANE15    V_LANE15(1U)
62485 
62486 #define S_LANE14    6
62487 #define V_LANE14(x) ((x) << S_LANE14)
62488 #define F_LANE14    V_LANE14(1U)
62489 
62490 #define S_LANE13    5
62491 #define V_LANE13(x) ((x) << S_LANE13)
62492 #define F_LANE13    V_LANE13(1U)
62493 
62494 #define S_LANE12    4
62495 #define V_LANE12(x) ((x) << S_LANE12)
62496 #define F_LANE12    V_LANE12(1U)
62497 
62498 #define S_LANE11    3
62499 #define V_LANE11(x) ((x) << S_LANE11)
62500 #define F_LANE11    V_LANE11(1U)
62501 
62502 #define S_LANE10    2
62503 #define V_LANE10(x) ((x) << S_LANE10)
62504 #define F_LANE10    V_LANE10(1U)
62505 
62506 #define S_LANE9    1
62507 #define V_LANE9(x) ((x) << S_LANE9)
62508 #define F_LANE9    V_LANE9(1U)
62509 
62510 #define S_LANE8    0
62511 #define V_LANE8(x) ((x) << S_LANE8)
62512 #define F_LANE8    V_LANE8(1U)
62513 
62514 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3 0x1ed0
62515 
62516 #define S_AMLOCK7    7
62517 #define V_AMLOCK7(x) ((x) << S_AMLOCK7)
62518 #define F_AMLOCK7    V_AMLOCK7(1U)
62519 
62520 #define S_AMLOCK6    6
62521 #define V_AMLOCK6(x) ((x) << S_AMLOCK6)
62522 #define F_AMLOCK6    V_AMLOCK6(1U)
62523 
62524 #define S_AMLOCK5    5
62525 #define V_AMLOCK5(x) ((x) << S_AMLOCK5)
62526 #define F_AMLOCK5    V_AMLOCK5(1U)
62527 
62528 #define S_AMLOCK4    4
62529 #define V_AMLOCK4(x) ((x) << S_AMLOCK4)
62530 #define F_AMLOCK4    V_AMLOCK4(1U)
62531 
62532 #define S_AMLOCK3    3
62533 #define V_AMLOCK3(x) ((x) << S_AMLOCK3)
62534 #define F_AMLOCK3    V_AMLOCK3(1U)
62535 
62536 #define S_AMLOCK2    2
62537 #define V_AMLOCK2(x) ((x) << S_AMLOCK2)
62538 #define F_AMLOCK2    V_AMLOCK2(1U)
62539 
62540 #define S_AMLOCK1    1
62541 #define V_AMLOCK1(x) ((x) << S_AMLOCK1)
62542 #define F_AMLOCK1    V_AMLOCK1(1U)
62543 
62544 #define S_AMLOCK0    0
62545 #define V_AMLOCK0(x) ((x) << S_AMLOCK0)
62546 #define F_AMLOCK0    V_AMLOCK0(1U)
62547 
62548 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4 0x1ed4
62549 
62550 #define S_AMLOCK19    11
62551 #define V_AMLOCK19(x) ((x) << S_AMLOCK19)
62552 #define F_AMLOCK19    V_AMLOCK19(1U)
62553 
62554 #define S_AMLOCK18    10
62555 #define V_AMLOCK18(x) ((x) << S_AMLOCK18)
62556 #define F_AMLOCK18    V_AMLOCK18(1U)
62557 
62558 #define S_AMLOCK17    9
62559 #define V_AMLOCK17(x) ((x) << S_AMLOCK17)
62560 #define F_AMLOCK17    V_AMLOCK17(1U)
62561 
62562 #define S_AMLOCK16    8
62563 #define V_AMLOCK16(x) ((x) << S_AMLOCK16)
62564 #define F_AMLOCK16    V_AMLOCK16(1U)
62565 
62566 #define S_AMLOCK15    7
62567 #define V_AMLOCK15(x) ((x) << S_AMLOCK15)
62568 #define F_AMLOCK15    V_AMLOCK15(1U)
62569 
62570 #define S_AMLOCK14    6
62571 #define V_AMLOCK14(x) ((x) << S_AMLOCK14)
62572 #define F_AMLOCK14    V_AMLOCK14(1U)
62573 
62574 #define S_AMLOCK13    5
62575 #define V_AMLOCK13(x) ((x) << S_AMLOCK13)
62576 #define F_AMLOCK13    V_AMLOCK13(1U)
62577 
62578 #define S_AMLOCK12    4
62579 #define V_AMLOCK12(x) ((x) << S_AMLOCK12)
62580 #define F_AMLOCK12    V_AMLOCK12(1U)
62581 
62582 #define S_AMLOCK11    3
62583 #define V_AMLOCK11(x) ((x) << S_AMLOCK11)
62584 #define F_AMLOCK11    V_AMLOCK11(1U)
62585 
62586 #define S_AMLOCK10    2
62587 #define V_AMLOCK10(x) ((x) << S_AMLOCK10)
62588 #define F_AMLOCK10    V_AMLOCK10(1U)
62589 
62590 #define S_AMLOCK9    1
62591 #define V_AMLOCK9(x) ((x) << S_AMLOCK9)
62592 #define F_AMLOCK9    V_AMLOCK9(1U)
62593 
62594 #define S_AMLOCK8    0
62595 #define V_AMLOCK8(x) ((x) << S_AMLOCK8)
62596 #define F_AMLOCK8    V_AMLOCK8(1U)
62597 
62598 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0 0x1f68
62599 
62600 #define S_BIPERR_CNT    0
62601 #define M_BIPERR_CNT    0xffffU
62602 #define V_BIPERR_CNT(x) ((x) << S_BIPERR_CNT)
62603 #define G_BIPERR_CNT(x) (((x) >> S_BIPERR_CNT) & M_BIPERR_CNT)
62604 
62605 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1 0x1f6c
62606 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2 0x1f70
62607 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3 0x1f74
62608 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4 0x1f78
62609 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5 0x1f7c
62610 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6 0x1f80
62611 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7 0x1f84
62612 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8 0x1f88
62613 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9 0x1f8c
62614 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10 0x1f90
62615 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11 0x1f94
62616 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12 0x1f98
62617 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13 0x1f9c
62618 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14 0x1fa0
62619 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15 0x1fa4
62620 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16 0x1fa8
62621 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17 0x1fac
62622 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18 0x1fb0
62623 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19 0x1fb4
62624 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_0 0x1fb8
62625 
62626 #define S_MAP    0
62627 #define M_MAP    0x1fU
62628 #define V_MAP(x) ((x) << S_MAP)
62629 #define G_MAP(x) (((x) >> S_MAP) & M_MAP)
62630 
62631 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_1 0x1fbc
62632 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_2 0x1fc0
62633 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_3 0x1fc4
62634 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_4 0x1fc8
62635 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_5 0x1fcc
62636 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_6 0x1fd0
62637 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_7 0x1fd4
62638 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_8 0x1fd8
62639 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_9 0x1fdc
62640 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_10 0x1fe0
62641 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_11 0x1fe4
62642 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_12 0x1fe8
62643 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_13 0x1fec
62644 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_14 0x1ff0
62645 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_15 0x1ff4
62646 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_16 0x1ff8
62647 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_17 0x1ffc
62648 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_18 0x2000
62649 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_19 0x2004
62650 #define A_MAC_PORT_MTIP_CR4_LANE_0_MAPPING 0x2140
62651 
62652 #define S_LANE_0_MAPPING    0
62653 #define M_LANE_0_MAPPING    0x3fU
62654 #define V_LANE_0_MAPPING(x) ((x) << S_LANE_0_MAPPING)
62655 #define G_LANE_0_MAPPING(x) (((x) >> S_LANE_0_MAPPING) & M_LANE_0_MAPPING)
62656 
62657 #define A_MAC_PORT_MTIP_CR4_LANE_1_MAPPING 0x2144
62658 
62659 #define S_LANE_1_MAPPING    0
62660 #define M_LANE_1_MAPPING    0x3fU
62661 #define V_LANE_1_MAPPING(x) ((x) << S_LANE_1_MAPPING)
62662 #define G_LANE_1_MAPPING(x) (((x) >> S_LANE_1_MAPPING) & M_LANE_1_MAPPING)
62663 
62664 #define A_MAC_PORT_MTIP_CR4_LANE_2_MAPPING 0x2148
62665 
62666 #define S_LANE_2_MAPPING    0
62667 #define M_LANE_2_MAPPING    0x3fU
62668 #define V_LANE_2_MAPPING(x) ((x) << S_LANE_2_MAPPING)
62669 #define G_LANE_2_MAPPING(x) (((x) >> S_LANE_2_MAPPING) & M_LANE_2_MAPPING)
62670 
62671 #define A_MAC_PORT_MTIP_CR4_LANE_3_MAPPING 0x214c
62672 
62673 #define S_LANE_3_MAPPING    0
62674 #define M_LANE_3_MAPPING    0x3fU
62675 #define V_LANE_3_MAPPING(x) ((x) << S_LANE_3_MAPPING)
62676 #define G_LANE_3_MAPPING(x) (((x) >> S_LANE_3_MAPPING) & M_LANE_3_MAPPING)
62677 
62678 #define A_MAC_PORT_MTIP_CR4_LANE_4_MAPPING 0x2150
62679 
62680 #define S_LANE_4_MAPPING    0
62681 #define M_LANE_4_MAPPING    0x3fU
62682 #define V_LANE_4_MAPPING(x) ((x) << S_LANE_4_MAPPING)
62683 #define G_LANE_4_MAPPING(x) (((x) >> S_LANE_4_MAPPING) & M_LANE_4_MAPPING)
62684 
62685 #define A_MAC_PORT_MTIP_CR4_LANE_5_MAPPING 0x2154
62686 
62687 #define S_LANE_5_MAPPING    0
62688 #define M_LANE_5_MAPPING    0x3fU
62689 #define V_LANE_5_MAPPING(x) ((x) << S_LANE_5_MAPPING)
62690 #define G_LANE_5_MAPPING(x) (((x) >> S_LANE_5_MAPPING) & M_LANE_5_MAPPING)
62691 
62692 #define A_MAC_PORT_MTIP_CR4_LANE_6_MAPPING 0x2158
62693 
62694 #define S_LANE_6_MAPPING    0
62695 #define M_LANE_6_MAPPING    0x3fU
62696 #define V_LANE_6_MAPPING(x) ((x) << S_LANE_6_MAPPING)
62697 #define G_LANE_6_MAPPING(x) (((x) >> S_LANE_6_MAPPING) & M_LANE_6_MAPPING)
62698 
62699 #define A_MAC_PORT_MTIP_CR4_LANE_7_MAPPING 0x215c
62700 
62701 #define S_LANE_7_MAPPING    0
62702 #define M_LANE_7_MAPPING    0x3fU
62703 #define V_LANE_7_MAPPING(x) ((x) << S_LANE_7_MAPPING)
62704 #define G_LANE_7_MAPPING(x) (((x) >> S_LANE_7_MAPPING) & M_LANE_7_MAPPING)
62705 
62706 #define A_MAC_PORT_MTIP_CR4_LANE_8_MAPPING 0x2160
62707 
62708 #define S_LANE_8_MAPPING    0
62709 #define M_LANE_8_MAPPING    0x3fU
62710 #define V_LANE_8_MAPPING(x) ((x) << S_LANE_8_MAPPING)
62711 #define G_LANE_8_MAPPING(x) (((x) >> S_LANE_8_MAPPING) & M_LANE_8_MAPPING)
62712 
62713 #define A_MAC_PORT_MTIP_CR4_LANE_9_MAPPING 0x2164
62714 
62715 #define S_LANE_9_MAPPING    0
62716 #define M_LANE_9_MAPPING    0x3fU
62717 #define V_LANE_9_MAPPING(x) ((x) << S_LANE_9_MAPPING)
62718 #define G_LANE_9_MAPPING(x) (((x) >> S_LANE_9_MAPPING) & M_LANE_9_MAPPING)
62719 
62720 #define A_MAC_PORT_MTIP_CR4_LANE_10_MAPPING 0x2168
62721 
62722 #define S_LANE_10_MAPPING    0
62723 #define M_LANE_10_MAPPING    0x3fU
62724 #define V_LANE_10_MAPPING(x) ((x) << S_LANE_10_MAPPING)
62725 #define G_LANE_10_MAPPING(x) (((x) >> S_LANE_10_MAPPING) & M_LANE_10_MAPPING)
62726 
62727 #define A_MAC_PORT_MTIP_CR4_LANE_11_MAPPING 0x216c
62728 
62729 #define S_LANE_11_MAPPING    0
62730 #define M_LANE_11_MAPPING    0x3fU
62731 #define V_LANE_11_MAPPING(x) ((x) << S_LANE_11_MAPPING)
62732 #define G_LANE_11_MAPPING(x) (((x) >> S_LANE_11_MAPPING) & M_LANE_11_MAPPING)
62733 
62734 #define A_MAC_PORT_MTIP_CR4_LANE_12_MAPPING 0x2170
62735 
62736 #define S_LANE_12_MAPPING    0
62737 #define M_LANE_12_MAPPING    0x3fU
62738 #define V_LANE_12_MAPPING(x) ((x) << S_LANE_12_MAPPING)
62739 #define G_LANE_12_MAPPING(x) (((x) >> S_LANE_12_MAPPING) & M_LANE_12_MAPPING)
62740 
62741 #define A_MAC_PORT_MTIP_CR4_LANE_13_MAPPING 0x2174
62742 
62743 #define S_LANE_13_MAPPING    0
62744 #define M_LANE_13_MAPPING    0x3fU
62745 #define V_LANE_13_MAPPING(x) ((x) << S_LANE_13_MAPPING)
62746 #define G_LANE_13_MAPPING(x) (((x) >> S_LANE_13_MAPPING) & M_LANE_13_MAPPING)
62747 
62748 #define A_MAC_PORT_MTIP_CR4_LANE_14_MAPPING 0x2178
62749 
62750 #define S_LANE_14_MAPPING    0
62751 #define M_LANE_14_MAPPING    0x3fU
62752 #define V_LANE_14_MAPPING(x) ((x) << S_LANE_14_MAPPING)
62753 #define G_LANE_14_MAPPING(x) (((x) >> S_LANE_14_MAPPING) & M_LANE_14_MAPPING)
62754 
62755 #define A_MAC_PORT_MTIP_CR4_LANE_15_MAPPING 0x217c
62756 
62757 #define S_LANE_15_MAPPING    0
62758 #define M_LANE_15_MAPPING    0x3fU
62759 #define V_LANE_15_MAPPING(x) ((x) << S_LANE_15_MAPPING)
62760 #define G_LANE_15_MAPPING(x) (((x) >> S_LANE_15_MAPPING) & M_LANE_15_MAPPING)
62761 
62762 #define A_MAC_PORT_MTIP_CR4_LANE_16_MAPPING 0x2180
62763 
62764 #define S_LANE_16_MAPPING    0
62765 #define M_LANE_16_MAPPING    0x3fU
62766 #define V_LANE_16_MAPPING(x) ((x) << S_LANE_16_MAPPING)
62767 #define G_LANE_16_MAPPING(x) (((x) >> S_LANE_16_MAPPING) & M_LANE_16_MAPPING)
62768 
62769 #define A_MAC_PORT_MTIP_CR4_LANE_17_MAPPING 0x2184
62770 
62771 #define S_LANE_17_MAPPING    0
62772 #define M_LANE_17_MAPPING    0x3fU
62773 #define V_LANE_17_MAPPING(x) ((x) << S_LANE_17_MAPPING)
62774 #define G_LANE_17_MAPPING(x) (((x) >> S_LANE_17_MAPPING) & M_LANE_17_MAPPING)
62775 
62776 #define A_MAC_PORT_MTIP_CR4_LANE_18_MAPPING 0x2188
62777 
62778 #define S_LANE_18_MAPPING    0
62779 #define M_LANE_18_MAPPING    0x3fU
62780 #define V_LANE_18_MAPPING(x) ((x) << S_LANE_18_MAPPING)
62781 #define G_LANE_18_MAPPING(x) (((x) >> S_LANE_18_MAPPING) & M_LANE_18_MAPPING)
62782 
62783 #define A_MAC_PORT_MTIP_CR4_LANE_19_MAPPING 0x218c
62784 
62785 #define S_LANE_19_MAPPING    0
62786 #define M_LANE_19_MAPPING    0x3fU
62787 #define V_LANE_19_MAPPING(x) ((x) << S_LANE_19_MAPPING)
62788 #define G_LANE_19_MAPPING(x) (((x) >> S_LANE_19_MAPPING) & M_LANE_19_MAPPING)
62789 
62790 #define A_MAC_PORT_MTIP_CR4_SCRATCH 0x21f0
62791 #define A_MAC_PORT_MTIP_CR4_CORE_REVISION 0x21f4
62792 
62793 #define S_CORE_REVISION    0
62794 #define M_CORE_REVISION    0xffffU
62795 #define V_CORE_REVISION(x) ((x) << S_CORE_REVISION)
62796 #define G_CORE_REVISION(x) (((x) >> S_CORE_REVISION) & M_CORE_REVISION)
62797 
62798 #define A_MAC_PORT_BEAN_CTL 0x2200
62799 
62800 #define S_AN_RESET    15
62801 #define V_AN_RESET(x) ((x) << S_AN_RESET)
62802 #define F_AN_RESET    V_AN_RESET(1U)
62803 
62804 #define S_EXT_NXP_CTRL    13
62805 #define V_EXT_NXP_CTRL(x) ((x) << S_EXT_NXP_CTRL)
62806 #define F_EXT_NXP_CTRL    V_EXT_NXP_CTRL(1U)
62807 
62808 #define S_BEAN_EN    12
62809 #define V_BEAN_EN(x) ((x) << S_BEAN_EN)
62810 #define F_BEAN_EN    V_BEAN_EN(1U)
62811 
62812 #define S_RESTART_BEAN    9
62813 #define V_RESTART_BEAN(x) ((x) << S_RESTART_BEAN)
62814 #define F_RESTART_BEAN    V_RESTART_BEAN(1U)
62815 
62816 #define A_MAC_PORT_MTIP_RS_FEC_CONTROL 0x2200
62817 
62818 #define S_RS_FEC_BYPASS_ERROR_INDICATION    1
62819 #define V_RS_FEC_BYPASS_ERROR_INDICATION(x) ((x) << S_RS_FEC_BYPASS_ERROR_INDICATION)
62820 #define F_RS_FEC_BYPASS_ERROR_INDICATION    V_RS_FEC_BYPASS_ERROR_INDICATION(1U)
62821 
62822 #define S_RS_FEC_BYPASS_CORRECTION    0
62823 #define V_RS_FEC_BYPASS_CORRECTION(x) ((x) << S_RS_FEC_BYPASS_CORRECTION)
62824 #define F_RS_FEC_BYPASS_CORRECTION    V_RS_FEC_BYPASS_CORRECTION(1U)
62825 
62826 #define A_MAC_PORT_BEAN_STATUS 0x2204
62827 
62828 #define S_PDF    9
62829 #define V_PDF(x) ((x) << S_PDF)
62830 #define F_PDF    V_PDF(1U)
62831 
62832 #define S_EXT_NXP_STATUS    7
62833 #define V_EXT_NXP_STATUS(x) ((x) << S_EXT_NXP_STATUS)
62834 #define F_EXT_NXP_STATUS    V_EXT_NXP_STATUS(1U)
62835 
62836 #define S_PAGE_RCVD    6
62837 #define V_PAGE_RCVD(x) ((x) << S_PAGE_RCVD)
62838 #define F_PAGE_RCVD    V_PAGE_RCVD(1U)
62839 
62840 #define S_BEAN_COMPLETE    5
62841 #define V_BEAN_COMPLETE(x) ((x) << S_BEAN_COMPLETE)
62842 #define F_BEAN_COMPLETE    V_BEAN_COMPLETE(1U)
62843 
62844 #define S_REM_FAULT_STATUS    4
62845 #define V_REM_FAULT_STATUS(x) ((x) << S_REM_FAULT_STATUS)
62846 #define F_REM_FAULT_STATUS    V_REM_FAULT_STATUS(1U)
62847 
62848 #define S_BEAN_ABILITY    3
62849 #define V_BEAN_ABILITY(x) ((x) << S_BEAN_ABILITY)
62850 #define F_BEAN_ABILITY    V_BEAN_ABILITY(1U)
62851 
62852 #define S_LP_BEAN_ABILITY    0
62853 #define V_LP_BEAN_ABILITY(x) ((x) << S_LP_BEAN_ABILITY)
62854 #define F_LP_BEAN_ABILITY    V_LP_BEAN_ABILITY(1U)
62855 
62856 #define A_MAC_PORT_MTIP_RS_FEC_STATUS 0x2204
62857 
62858 #define S_RS_FEC_PCS_ALIGN_STATUS    15
62859 #define V_RS_FEC_PCS_ALIGN_STATUS(x) ((x) << S_RS_FEC_PCS_ALIGN_STATUS)
62860 #define F_RS_FEC_PCS_ALIGN_STATUS    V_RS_FEC_PCS_ALIGN_STATUS(1U)
62861 
62862 #define S_FEC_ALIGN_STATUS    14
62863 #define V_FEC_ALIGN_STATUS(x) ((x) << S_FEC_ALIGN_STATUS)
62864 #define F_FEC_ALIGN_STATUS    V_FEC_ALIGN_STATUS(1U)
62865 
62866 #define S_RS_FEC_HIGH_SER    2
62867 #define V_RS_FEC_HIGH_SER(x) ((x) << S_RS_FEC_HIGH_SER)
62868 #define F_RS_FEC_HIGH_SER    V_RS_FEC_HIGH_SER(1U)
62869 
62870 #define S_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY    1
62871 #define V_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY(x) ((x) << S_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY)
62872 #define F_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY    V_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY(1U)
62873 
62874 #define S_RS_FEC_BYPASS_CORRECTION_ABILITY    0
62875 #define V_RS_FEC_BYPASS_CORRECTION_ABILITY(x) ((x) << S_RS_FEC_BYPASS_CORRECTION_ABILITY)
62876 #define F_RS_FEC_BYPASS_CORRECTION_ABILITY    V_RS_FEC_BYPASS_CORRECTION_ABILITY(1U)
62877 
62878 #define A_MAC_PORT_BEAN_ABILITY_0 0x2208
62879 
62880 #define S_NXP    15
62881 #define V_NXP(x) ((x) << S_NXP)
62882 #define F_NXP    V_NXP(1U)
62883 
62884 #define S_REM_FAULT    13
62885 #define V_REM_FAULT(x) ((x) << S_REM_FAULT)
62886 #define F_REM_FAULT    V_REM_FAULT(1U)
62887 
62888 #define S_PAUSE_ABILITY    10
62889 #define M_PAUSE_ABILITY    0x7U
62890 #define V_PAUSE_ABILITY(x) ((x) << S_PAUSE_ABILITY)
62891 #define G_PAUSE_ABILITY(x) (((x) >> S_PAUSE_ABILITY) & M_PAUSE_ABILITY)
62892 
62893 #define S_ECHO_NONCE    5
62894 #define M_ECHO_NONCE    0x1fU
62895 #define V_ECHO_NONCE(x) ((x) << S_ECHO_NONCE)
62896 #define G_ECHO_NONCE(x) (((x) >> S_ECHO_NONCE) & M_ECHO_NONCE)
62897 
62898 #define S_SELECTOR    0
62899 #define M_SELECTOR    0x1fU
62900 #define V_SELECTOR(x) ((x) << S_SELECTOR)
62901 #define G_SELECTOR(x) (((x) >> S_SELECTOR) & M_SELECTOR)
62902 
62903 #define A_MAC_PORT_MTIP_RS_FEC_CCW_LO 0x2208
62904 
62905 #define S_RS_RS_FEC_CCW_LO    0
62906 #define M_RS_RS_FEC_CCW_LO    0xffffU
62907 #define V_RS_RS_FEC_CCW_LO(x) ((x) << S_RS_RS_FEC_CCW_LO)
62908 #define G_RS_RS_FEC_CCW_LO(x) (((x) >> S_RS_RS_FEC_CCW_LO) & M_RS_RS_FEC_CCW_LO)
62909 
62910 #define A_MAC_PORT_BEAN_ABILITY_1 0x220c
62911 
62912 #define S_TECH_ABILITY_1    5
62913 #define M_TECH_ABILITY_1    0x7ffU
62914 #define V_TECH_ABILITY_1(x) ((x) << S_TECH_ABILITY_1)
62915 #define G_TECH_ABILITY_1(x) (((x) >> S_TECH_ABILITY_1) & M_TECH_ABILITY_1)
62916 
62917 #define S_TX_NONCE    0
62918 #define M_TX_NONCE    0x1fU
62919 #define V_TX_NONCE(x) ((x) << S_TX_NONCE)
62920 #define G_TX_NONCE(x) (((x) >> S_TX_NONCE) & M_TX_NONCE)
62921 
62922 #define A_MAC_PORT_MTIP_RS_FEC_CCW_HI 0x220c
62923 
62924 #define S_RS_RS_FEC_CCW_HI    0
62925 #define M_RS_RS_FEC_CCW_HI    0xffffU
62926 #define V_RS_RS_FEC_CCW_HI(x) ((x) << S_RS_RS_FEC_CCW_HI)
62927 #define G_RS_RS_FEC_CCW_HI(x) (((x) >> S_RS_RS_FEC_CCW_HI) & M_RS_RS_FEC_CCW_HI)
62928 
62929 #define A_MAC_PORT_BEAN_ABILITY_2 0x2210
62930 
62931 #define S_T5_FEC_ABILITY    14
62932 #define M_T5_FEC_ABILITY    0x3U
62933 #define V_T5_FEC_ABILITY(x) ((x) << S_T5_FEC_ABILITY)
62934 #define G_T5_FEC_ABILITY(x) (((x) >> S_T5_FEC_ABILITY) & M_T5_FEC_ABILITY)
62935 
62936 #define S_TECH_ABILITY_2    0
62937 #define M_TECH_ABILITY_2    0x3fffU
62938 #define V_TECH_ABILITY_2(x) ((x) << S_TECH_ABILITY_2)
62939 #define G_TECH_ABILITY_2(x) (((x) >> S_TECH_ABILITY_2) & M_TECH_ABILITY_2)
62940 
62941 #define A_MAC_PORT_MTIP_RS_FEC_NCCW_LO 0x2210
62942 
62943 #define S_RS_RS_FEC_NCCW_LO    0
62944 #define M_RS_RS_FEC_NCCW_LO    0xffffU
62945 #define V_RS_RS_FEC_NCCW_LO(x) ((x) << S_RS_RS_FEC_NCCW_LO)
62946 #define G_RS_RS_FEC_NCCW_LO(x) (((x) >> S_RS_RS_FEC_NCCW_LO) & M_RS_RS_FEC_NCCW_LO)
62947 
62948 #define A_MAC_PORT_BEAN_REM_ABILITY_0 0x2214
62949 #define A_MAC_PORT_MTIP_RS_FEC_NCCW_HI 0x2214
62950 
62951 #define S_RS_RS_FEC_NCCW_HI    0
62952 #define M_RS_RS_FEC_NCCW_HI    0xffffU
62953 #define V_RS_RS_FEC_NCCW_HI(x) ((x) << S_RS_RS_FEC_NCCW_HI)
62954 #define G_RS_RS_FEC_NCCW_HI(x) (((x) >> S_RS_RS_FEC_NCCW_HI) & M_RS_RS_FEC_NCCW_HI)
62955 
62956 #define A_MAC_PORT_BEAN_REM_ABILITY_1 0x2218
62957 #define A_MAC_PORT_MTIP_RS_FEC_LANEMAPRS_FEC_NCCW_HI 0x2218
62958 
62959 #define S_PMA_MAPPING    0
62960 #define M_PMA_MAPPING    0xffU
62961 #define V_PMA_MAPPING(x) ((x) << S_PMA_MAPPING)
62962 #define G_PMA_MAPPING(x) (((x) >> S_PMA_MAPPING) & M_PMA_MAPPING)
62963 
62964 #define A_MAC_PORT_BEAN_REM_ABILITY_2 0x221c
62965 #define A_MAC_PORT_BEAN_MS_COUNT 0x2220
62966 
62967 #define S_MS_COUNT    0
62968 #define M_MS_COUNT    0xffffU
62969 #define V_MS_COUNT(x) ((x) << S_MS_COUNT)
62970 #define G_MS_COUNT(x) (((x) >> S_MS_COUNT) & M_MS_COUNT)
62971 
62972 #define A_MAC_PORT_BEAN_XNP_0 0x2224
62973 
62974 #define S_XNP    15
62975 #define V_XNP(x) ((x) << S_XNP)
62976 #define F_XNP    V_XNP(1U)
62977 
62978 #define S_ACKNOWLEDGE    14
62979 #define V_ACKNOWLEDGE(x) ((x) << S_ACKNOWLEDGE)
62980 #define F_ACKNOWLEDGE    V_ACKNOWLEDGE(1U)
62981 
62982 #define S_MP    13
62983 #define V_MP(x) ((x) << S_MP)
62984 #define F_MP    V_MP(1U)
62985 
62986 #define S_ACK2    12
62987 #define V_ACK2(x) ((x) << S_ACK2)
62988 #define F_ACK2    V_ACK2(1U)
62989 
62990 #define S_MU    0
62991 #define M_MU    0x7ffU
62992 #define V_MU(x) ((x) << S_MU)
62993 #define G_MU(x) (((x) >> S_MU) & M_MU)
62994 
62995 #define A_MAC_PORT_BEAN_XNP_1 0x2228
62996 
62997 #define S_UNFORMATED    0
62998 #define M_UNFORMATED    0xffffU
62999 #define V_UNFORMATED(x) ((x) << S_UNFORMATED)
63000 #define G_UNFORMATED(x) (((x) >> S_UNFORMATED) & M_UNFORMATED)
63001 
63002 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR0_LO 0x2228
63003 
63004 #define S_RS_FEC_SYMBLERR0_LO    0
63005 #define V_RS_FEC_SYMBLERR0_LO(x) ((x) << S_RS_FEC_SYMBLERR0_LO)
63006 #define F_RS_FEC_SYMBLERR0_LO    V_RS_FEC_SYMBLERR0_LO(1U)
63007 
63008 #define A_MAC_PORT_BEAN_XNP_2 0x222c
63009 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR0_HI 0x222c
63010 
63011 #define S_RS_FEC_SYMBLERR0_HI    0
63012 #define V_RS_FEC_SYMBLERR0_HI(x) ((x) << S_RS_FEC_SYMBLERR0_HI)
63013 #define F_RS_FEC_SYMBLERR0_HI    V_RS_FEC_SYMBLERR0_HI(1U)
63014 
63015 #define A_MAC_PORT_LP_BEAN_XNP_0 0x2230
63016 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR1_LO 0x2230
63017 
63018 #define S_RS_FEC_SYMBLERR1_LO    0
63019 #define V_RS_FEC_SYMBLERR1_LO(x) ((x) << S_RS_FEC_SYMBLERR1_LO)
63020 #define F_RS_FEC_SYMBLERR1_LO    V_RS_FEC_SYMBLERR1_LO(1U)
63021 
63022 #define A_MAC_PORT_LP_BEAN_XNP_1 0x2234
63023 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR1_HI 0x2234
63024 
63025 #define S_RS_FEC_SYMBLERR1_HI    0
63026 #define V_RS_FEC_SYMBLERR1_HI(x) ((x) << S_RS_FEC_SYMBLERR1_HI)
63027 #define F_RS_FEC_SYMBLERR1_HI    V_RS_FEC_SYMBLERR1_HI(1U)
63028 
63029 #define A_MAC_PORT_LP_BEAN_XNP_2 0x2238
63030 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR2_LO 0x2238
63031 
63032 #define S_RS_FEC_SYMBLERR2_LO    0
63033 #define V_RS_FEC_SYMBLERR2_LO(x) ((x) << S_RS_FEC_SYMBLERR2_LO)
63034 #define F_RS_FEC_SYMBLERR2_LO    V_RS_FEC_SYMBLERR2_LO(1U)
63035 
63036 #define A_MAC_PORT_BEAN_ETH_STATUS 0x223c
63037 
63038 #define S_100GCR10    8
63039 #define V_100GCR10(x) ((x) << S_100GCR10)
63040 #define F_100GCR10    V_100GCR10(1U)
63041 
63042 #define S_40GCR4    6
63043 #define V_40GCR4(x) ((x) << S_40GCR4)
63044 #define F_40GCR4    V_40GCR4(1U)
63045 
63046 #define S_40GKR4    5
63047 #define V_40GKR4(x) ((x) << S_40GKR4)
63048 #define F_40GKR4    V_40GKR4(1U)
63049 
63050 #define S_FEC    4
63051 #define V_FEC(x) ((x) << S_FEC)
63052 #define F_FEC    V_FEC(1U)
63053 
63054 #define S_10GKR    3
63055 #define V_10GKR(x) ((x) << S_10GKR)
63056 #define F_10GKR    V_10GKR(1U)
63057 
63058 #define S_10GKX4    2
63059 #define V_10GKX4(x) ((x) << S_10GKX4)
63060 #define F_10GKX4    V_10GKX4(1U)
63061 
63062 #define S_1GKX    1
63063 #define V_1GKX(x) ((x) << S_1GKX)
63064 #define F_1GKX    V_1GKX(1U)
63065 
63066 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR2_HI 0x223c
63067 
63068 #define S_RS_FEC_SYMBLERR2_HI    0
63069 #define V_RS_FEC_SYMBLERR2_HI(x) ((x) << S_RS_FEC_SYMBLERR2_HI)
63070 #define F_RS_FEC_SYMBLERR2_HI    V_RS_FEC_SYMBLERR2_HI(1U)
63071 
63072 #define A_MAC_PORT_BEAN_CTL_LANE1 0x2240
63073 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR3_LO 0x2240
63074 
63075 #define S_RS_FEC_SYMBLERR3_LO    0
63076 #define V_RS_FEC_SYMBLERR3_LO(x) ((x) << S_RS_FEC_SYMBLERR3_LO)
63077 #define F_RS_FEC_SYMBLERR3_LO    V_RS_FEC_SYMBLERR3_LO(1U)
63078 
63079 #define A_MAC_PORT_BEAN_STATUS_LANE1 0x2244
63080 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR3_HI 0x2244
63081 
63082 #define S_RS_FEC_SYMBLERR3_HI    0
63083 #define V_RS_FEC_SYMBLERR3_HI(x) ((x) << S_RS_FEC_SYMBLERR3_HI)
63084 #define F_RS_FEC_SYMBLERR3_HI    V_RS_FEC_SYMBLERR3_HI(1U)
63085 
63086 #define A_MAC_PORT_BEAN_ABILITY_0_LANE1 0x2248
63087 #define A_MAC_PORT_BEAN_ABILITY_1_LANE1 0x224c
63088 #define A_MAC_PORT_BEAN_ABILITY_2_LANE1 0x2250
63089 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE1 0x2254
63090 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE1 0x2258
63091 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE1 0x225c
63092 #define A_MAC_PORT_BEAN_MS_COUNT_LANE1 0x2260
63093 #define A_MAC_PORT_BEAN_XNP_0_LANE1 0x2264
63094 #define A_MAC_PORT_BEAN_XNP_1_LANE1 0x2268
63095 #define A_MAC_PORT_BEAN_XNP_2_LANE1 0x226c
63096 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE1 0x2270
63097 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE1 0x2274
63098 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE1 0x2278
63099 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE1 0x227c
63100 #define A_MAC_PORT_BEAN_CTL_LANE2 0x2280
63101 #define A_MAC_PORT_BEAN_STATUS_LANE2 0x2284
63102 #define A_MAC_PORT_BEAN_ABILITY_0_LANE2 0x2288
63103 #define A_MAC_PORT_BEAN_ABILITY_1_LANE2 0x228c
63104 #define A_MAC_PORT_BEAN_ABILITY_2_LANE2 0x2290
63105 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE2 0x2294
63106 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE2 0x2298
63107 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE2 0x229c
63108 #define A_MAC_PORT_BEAN_MS_COUNT_LANE2 0x22a0
63109 #define A_MAC_PORT_BEAN_XNP_0_LANE2 0x22a4
63110 #define A_MAC_PORT_BEAN_XNP_1_LANE2 0x22a8
63111 #define A_MAC_PORT_BEAN_XNP_2_LANE2 0x22ac
63112 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE2 0x22b0
63113 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE2 0x22b4
63114 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE2 0x22b8
63115 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE2 0x22bc
63116 #define A_MAC_PORT_BEAN_CTL_LANE3 0x22c0
63117 #define A_MAC_PORT_BEAN_STATUS_LANE3 0x22c4
63118 #define A_MAC_PORT_BEAN_ABILITY_0_LANE3 0x22c8
63119 #define A_MAC_PORT_BEAN_ABILITY_1_LANE3 0x22cc
63120 #define A_MAC_PORT_BEAN_ABILITY_2_LANE3 0x22d0
63121 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE3 0x22d4
63122 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE3 0x22d8
63123 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE3 0x22dc
63124 #define A_MAC_PORT_BEAN_MS_COUNT_LANE3 0x22e0
63125 #define A_MAC_PORT_BEAN_XNP_0_LANE3 0x22e4
63126 #define A_MAC_PORT_BEAN_XNP_1_LANE3 0x22e8
63127 #define A_MAC_PORT_BEAN_XNP_2_LANE3 0x22ec
63128 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE3 0x22f0
63129 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE3 0x22f4
63130 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE3 0x22f8
63131 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE3 0x22fc
63132 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_CONTROL 0x2400
63133 
63134 #define S_RS_FEC_ENABLED_STATUS    15
63135 #define V_RS_FEC_ENABLED_STATUS(x) ((x) << S_RS_FEC_ENABLED_STATUS)
63136 #define F_RS_FEC_ENABLED_STATUS    V_RS_FEC_ENABLED_STATUS(1U)
63137 
63138 #define S_RS_FEC_ENABLE    2
63139 #define V_RS_FEC_ENABLE(x) ((x) << S_RS_FEC_ENABLE)
63140 #define F_RS_FEC_ENABLE    V_RS_FEC_ENABLE(1U)
63141 
63142 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_1 0x2404
63143 
63144 #define S_DESKEW_EMPTY    12
63145 #define M_DESKEW_EMPTY    0xfU
63146 #define V_DESKEW_EMPTY(x) ((x) << S_DESKEW_EMPTY)
63147 #define G_DESKEW_EMPTY(x) (((x) >> S_DESKEW_EMPTY) & M_DESKEW_EMPTY)
63148 
63149 #define S_FEC_ALIGN_STATUS_LH    10
63150 #define V_FEC_ALIGN_STATUS_LH(x) ((x) << S_FEC_ALIGN_STATUS_LH)
63151 #define F_FEC_ALIGN_STATUS_LH    V_FEC_ALIGN_STATUS_LH(1U)
63152 
63153 #define S_TX_DP_OVERFLOW    9
63154 #define V_TX_DP_OVERFLOW(x) ((x) << S_TX_DP_OVERFLOW)
63155 #define F_TX_DP_OVERFLOW    V_TX_DP_OVERFLOW(1U)
63156 
63157 #define S_RX_DP_OVERFLOW    8
63158 #define V_RX_DP_OVERFLOW(x) ((x) << S_RX_DP_OVERFLOW)
63159 #define F_RX_DP_OVERFLOW    V_RX_DP_OVERFLOW(1U)
63160 
63161 #define S_TX_DATAPATH_RESTART    7
63162 #define V_TX_DATAPATH_RESTART(x) ((x) << S_TX_DATAPATH_RESTART)
63163 #define F_TX_DATAPATH_RESTART    V_TX_DATAPATH_RESTART(1U)
63164 
63165 #define S_RX_DATAPATH_RESTART    6
63166 #define V_RX_DATAPATH_RESTART(x) ((x) << S_RX_DATAPATH_RESTART)
63167 #define F_RX_DATAPATH_RESTART    V_RX_DATAPATH_RESTART(1U)
63168 
63169 #define S_MARKER_CHECK_RESTART    5
63170 #define V_MARKER_CHECK_RESTART(x) ((x) << S_MARKER_CHECK_RESTART)
63171 #define F_MARKER_CHECK_RESTART    V_MARKER_CHECK_RESTART(1U)
63172 
63173 #define S_FEC_ALIGN_STATUS_LL    4
63174 #define V_FEC_ALIGN_STATUS_LL(x) ((x) << S_FEC_ALIGN_STATUS_LL)
63175 #define F_FEC_ALIGN_STATUS_LL    V_FEC_ALIGN_STATUS_LL(1U)
63176 
63177 #define S_AMPS_LOCK    0
63178 #define M_AMPS_LOCK    0xfU
63179 #define V_AMPS_LOCK(x) ((x) << S_AMPS_LOCK)
63180 #define G_AMPS_LOCK(x) (((x) >> S_AMPS_LOCK) & M_AMPS_LOCK)
63181 
63182 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_2 0x2408
63183 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_REVISION 0x240c
63184 
63185 #define S_RS_FEC_VENDOR_REVISION    0
63186 #define M_RS_FEC_VENDOR_REVISION    0xffffU
63187 #define V_RS_FEC_VENDOR_REVISION(x) ((x) << S_RS_FEC_VENDOR_REVISION)
63188 #define G_RS_FEC_VENDOR_REVISION(x) (((x) >> S_RS_FEC_VENDOR_REVISION) & M_RS_FEC_VENDOR_REVISION)
63189 
63190 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_KEY 0x2410
63191 
63192 #define S_RS_FEC_VENDOR_TX_TEST_KEY    0
63193 #define M_RS_FEC_VENDOR_TX_TEST_KEY    0xffffU
63194 #define V_RS_FEC_VENDOR_TX_TEST_KEY(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_KEY)
63195 #define G_RS_FEC_VENDOR_TX_TEST_KEY(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_KEY) & M_RS_FEC_VENDOR_TX_TEST_KEY)
63196 
63197 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_SYMBOLS 0x2414
63198 
63199 #define S_RS_FEC_VENDOR_TX_TEST_SYMBOLS    0
63200 #define M_RS_FEC_VENDOR_TX_TEST_SYMBOLS    0xffffU
63201 #define V_RS_FEC_VENDOR_TX_TEST_SYMBOLS(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_SYMBOLS)
63202 #define G_RS_FEC_VENDOR_TX_TEST_SYMBOLS(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_SYMBOLS) & M_RS_FEC_VENDOR_TX_TEST_SYMBOLS)
63203 
63204 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_PATTERN 0x2418
63205 
63206 #define S_RS_FEC_VENDOR_TX_TEST_PATTERN    0
63207 #define M_RS_FEC_VENDOR_TX_TEST_PATTERN    0xffffU
63208 #define V_RS_FEC_VENDOR_TX_TEST_PATTERN(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_PATTERN)
63209 #define G_RS_FEC_VENDOR_TX_TEST_PATTERN(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_PATTERN) & M_RS_FEC_VENDOR_TX_TEST_PATTERN)
63210 
63211 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_TRIGGER 0x241c
63212 
63213 #define S_RS_FEC_VENDOR_TX_TEST_TRIGGER    0
63214 #define M_RS_FEC_VENDOR_TX_TEST_TRIGGER    0xffffU
63215 #define V_RS_FEC_VENDOR_TX_TEST_TRIGGER(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_TRIGGER)
63216 #define G_RS_FEC_VENDOR_TX_TEST_TRIGGER(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_TRIGGER) & M_RS_FEC_VENDOR_TX_TEST_TRIGGER)
63217 
63218 #define A_MAC_PORT_FEC_KR_CONTROL 0x2600
63219 
63220 #define S_ENABLE_TR    1
63221 #define V_ENABLE_TR(x) ((x) << S_ENABLE_TR)
63222 #define F_ENABLE_TR    V_ENABLE_TR(1U)
63223 
63224 #define S_RESTART_TR    0
63225 #define V_RESTART_TR(x) ((x) << S_RESTART_TR)
63226 #define F_RESTART_TR    V_RESTART_TR(1U)
63227 
63228 #define A_MAC_PORT_FEC_KR_STATUS 0x2604
63229 
63230 #define S_FECKRSIGDET    15
63231 #define V_FECKRSIGDET(x) ((x) << S_FECKRSIGDET)
63232 #define F_FECKRSIGDET    V_FECKRSIGDET(1U)
63233 
63234 #define S_TRAIN_FAIL    3
63235 #define V_TRAIN_FAIL(x) ((x) << S_TRAIN_FAIL)
63236 #define F_TRAIN_FAIL    V_TRAIN_FAIL(1U)
63237 
63238 #define S_STARTUP_STATUS    2
63239 #define V_STARTUP_STATUS(x) ((x) << S_STARTUP_STATUS)
63240 #define F_STARTUP_STATUS    V_STARTUP_STATUS(1U)
63241 
63242 #define S_RX_STATUS    0
63243 #define V_RX_STATUS(x) ((x) << S_RX_STATUS)
63244 #define F_RX_STATUS    V_RX_STATUS(1U)
63245 
63246 #define A_MAC_PORT_FEC_KR_LP_COEFF 0x2608
63247 
63248 #define S_PRESET    13
63249 #define V_PRESET(x) ((x) << S_PRESET)
63250 #define F_PRESET    V_PRESET(1U)
63251 
63252 #define S_INITIALIZE    12
63253 #define V_INITIALIZE(x) ((x) << S_INITIALIZE)
63254 #define F_INITIALIZE    V_INITIALIZE(1U)
63255 
63256 #define S_CP1_UPD    4
63257 #define M_CP1_UPD    0x3U
63258 #define V_CP1_UPD(x) ((x) << S_CP1_UPD)
63259 #define G_CP1_UPD(x) (((x) >> S_CP1_UPD) & M_CP1_UPD)
63260 
63261 #define S_C0_UPD    2
63262 #define M_C0_UPD    0x3U
63263 #define V_C0_UPD(x) ((x) << S_C0_UPD)
63264 #define G_C0_UPD(x) (((x) >> S_C0_UPD) & M_C0_UPD)
63265 
63266 #define S_CN1_UPD    0
63267 #define M_CN1_UPD    0x3U
63268 #define V_CN1_UPD(x) ((x) << S_CN1_UPD)
63269 #define G_CN1_UPD(x) (((x) >> S_CN1_UPD) & M_CN1_UPD)
63270 
63271 #define A_MAC_PORT_FEC_KR_LP_STAT 0x260c
63272 
63273 #define S_RX_READY    15
63274 #define V_RX_READY(x) ((x) << S_RX_READY)
63275 #define F_RX_READY    V_RX_READY(1U)
63276 
63277 #define S_CP1_STAT    4
63278 #define M_CP1_STAT    0x3U
63279 #define V_CP1_STAT(x) ((x) << S_CP1_STAT)
63280 #define G_CP1_STAT(x) (((x) >> S_CP1_STAT) & M_CP1_STAT)
63281 
63282 #define S_C0_STAT    2
63283 #define M_C0_STAT    0x3U
63284 #define V_C0_STAT(x) ((x) << S_C0_STAT)
63285 #define G_C0_STAT(x) (((x) >> S_C0_STAT) & M_C0_STAT)
63286 
63287 #define S_CN1_STAT    0
63288 #define M_CN1_STAT    0x3U
63289 #define V_CN1_STAT(x) ((x) << S_CN1_STAT)
63290 #define G_CN1_STAT(x) (((x) >> S_CN1_STAT) & M_CN1_STAT)
63291 
63292 #define A_MAC_PORT_FEC_KR_LD_COEFF 0x2610
63293 #define A_MAC_PORT_FEC_KR_LD_STAT 0x2614
63294 #define A_MAC_PORT_FEC_ABILITY 0x2618
63295 
63296 #define S_FEC_IND_ABILITY    1
63297 #define V_FEC_IND_ABILITY(x) ((x) << S_FEC_IND_ABILITY)
63298 #define F_FEC_IND_ABILITY    V_FEC_IND_ABILITY(1U)
63299 
63300 #define S_ABILITY    0
63301 #define V_ABILITY(x) ((x) << S_ABILITY)
63302 #define F_ABILITY    V_ABILITY(1U)
63303 
63304 #define A_MAC_PORT_MTIP_FEC_ABILITY 0x2618
63305 
63306 #define S_BASE_R_FEC_ERROR_INDICATION_ABILITY    1
63307 #define V_BASE_R_FEC_ERROR_INDICATION_ABILITY(x) ((x) << S_BASE_R_FEC_ERROR_INDICATION_ABILITY)
63308 #define F_BASE_R_FEC_ERROR_INDICATION_ABILITY    V_BASE_R_FEC_ERROR_INDICATION_ABILITY(1U)
63309 
63310 #define S_BASE_R_FEC_ABILITY    0
63311 #define V_BASE_R_FEC_ABILITY(x) ((x) << S_BASE_R_FEC_ABILITY)
63312 #define F_BASE_R_FEC_ABILITY    V_BASE_R_FEC_ABILITY(1U)
63313 
63314 #define A_MAC_PORT_FEC_CONTROL 0x261c
63315 
63316 #define S_FEC_EN_ERR_IND    1
63317 #define V_FEC_EN_ERR_IND(x) ((x) << S_FEC_EN_ERR_IND)
63318 #define F_FEC_EN_ERR_IND    V_FEC_EN_ERR_IND(1U)
63319 
63320 #define S_FEC_EN    0
63321 #define V_FEC_EN(x) ((x) << S_FEC_EN)
63322 #define F_FEC_EN    V_FEC_EN(1U)
63323 
63324 #define A_MAC_PORT_FEC_STATUS 0x2620
63325 
63326 #define S_FEC_LOCKED_100    1
63327 #define V_FEC_LOCKED_100(x) ((x) << S_FEC_LOCKED_100)
63328 #define F_FEC_LOCKED_100    V_FEC_LOCKED_100(1U)
63329 
63330 #define S_FEC_LOCKED    0
63331 #define V_FEC_LOCKED(x) ((x) << S_FEC_LOCKED)
63332 #define F_FEC_LOCKED    V_FEC_LOCKED(1U)
63333 
63334 #define S_FEC_LOCKED0    1
63335 #define M_FEC_LOCKED0    0xfU
63336 #define V_FEC_LOCKED0(x) ((x) << S_FEC_LOCKED0)
63337 #define G_FEC_LOCKED0(x) (((x) >> S_FEC_LOCKED0) & M_FEC_LOCKED0)
63338 
63339 #define A_MAC_PORT_FEC_CERR_CNT_0 0x2624
63340 
63341 #define S_FEC_CERR_CNT_0    0
63342 #define M_FEC_CERR_CNT_0    0xffffU
63343 #define V_FEC_CERR_CNT_0(x) ((x) << S_FEC_CERR_CNT_0)
63344 #define G_FEC_CERR_CNT_0(x) (((x) >> S_FEC_CERR_CNT_0) & M_FEC_CERR_CNT_0)
63345 
63346 #define A_MAC_PORT_MTIP_FEC0_CERR_CNT_0 0x2624
63347 #define A_MAC_PORT_FEC_CERR_CNT_1 0x2628
63348 
63349 #define S_FEC_CERR_CNT_1    0
63350 #define M_FEC_CERR_CNT_1    0xffffU
63351 #define V_FEC_CERR_CNT_1(x) ((x) << S_FEC_CERR_CNT_1)
63352 #define G_FEC_CERR_CNT_1(x) (((x) >> S_FEC_CERR_CNT_1) & M_FEC_CERR_CNT_1)
63353 
63354 #define A_MAC_PORT_MTIP_FEC0_CERR_CNT_1 0x2628
63355 #define A_MAC_PORT_FEC_NCERR_CNT_0 0x262c
63356 
63357 #define S_FEC_NCERR_CNT_0    0
63358 #define M_FEC_NCERR_CNT_0    0xffffU
63359 #define V_FEC_NCERR_CNT_0(x) ((x) << S_FEC_NCERR_CNT_0)
63360 #define G_FEC_NCERR_CNT_0(x) (((x) >> S_FEC_NCERR_CNT_0) & M_FEC_NCERR_CNT_0)
63361 
63362 #define A_MAC_PORT_MTIP_FEC0_NCERR_CNT_0 0x262c
63363 
63364 #define S_FEC0_NCERR_CNT_0    0
63365 #define M_FEC0_NCERR_CNT_0    0xffffU
63366 #define V_FEC0_NCERR_CNT_0(x) ((x) << S_FEC0_NCERR_CNT_0)
63367 #define G_FEC0_NCERR_CNT_0(x) (((x) >> S_FEC0_NCERR_CNT_0) & M_FEC0_NCERR_CNT_0)
63368 
63369 #define A_MAC_PORT_FEC_NCERR_CNT_1 0x2630
63370 
63371 #define S_FEC_NCERR_CNT_1    0
63372 #define M_FEC_NCERR_CNT_1    0xffffU
63373 #define V_FEC_NCERR_CNT_1(x) ((x) << S_FEC_NCERR_CNT_1)
63374 #define G_FEC_NCERR_CNT_1(x) (((x) >> S_FEC_NCERR_CNT_1) & M_FEC_NCERR_CNT_1)
63375 
63376 #define A_MAC_PORT_MTIP_FEC0_NCERR_CNT_1 0x2630
63377 
63378 #define S_FEC0_NCERR_CNT_1    0
63379 #define M_FEC0_NCERR_CNT_1    0xffffU
63380 #define V_FEC0_NCERR_CNT_1(x) ((x) << S_FEC0_NCERR_CNT_1)
63381 #define G_FEC0_NCERR_CNT_1(x) (((x) >> S_FEC0_NCERR_CNT_1) & M_FEC0_NCERR_CNT_1)
63382 
63383 #define A_MAC_PORT_MTIP_FEC_STATUS1 0x2664
63384 #define A_MAC_PORT_MTIP_FEC1_CERR_CNT_0 0x2668
63385 #define A_MAC_PORT_MTIP_FEC1_CERR_CNT_1 0x266c
63386 #define A_MAC_PORT_MTIP_FEC1_NCERR_CNT_0 0x2670
63387 #define A_MAC_PORT_MTIP_FEC1_NCERR_CNT_1 0x2674
63388 #define A_MAC_PORT_MTIP_FEC_STATUS2 0x26a8
63389 #define A_MAC_PORT_MTIP_FEC2_CERR_CNT_0 0x26ac
63390 #define A_MAC_PORT_MTIP_FEC2_CERR_CNT_1 0x26b0
63391 #define A_MAC_PORT_MTIP_FEC2_NCERR_CNT_0 0x26b4
63392 #define A_MAC_PORT_MTIP_FEC2_NCERR_CNT_1 0x26b8
63393 #define A_MAC_PORT_MTIP_FEC_STATUS3 0x26ec
63394 #define A_MAC_PORT_MTIP_FEC3_CERR_CNT_0 0x26f0
63395 #define A_MAC_PORT_MTIP_FEC3_CERR_CNT_1 0x26f4
63396 #define A_MAC_PORT_MTIP_FEC3_NCERR_CNT_0 0x26f8
63397 #define A_MAC_PORT_MTIP_FEC3_NCERR_CNT_1 0x26fc
63398 #define A_MAC_PORT_AE_RX_COEF_REQ 0x2a00
63399 
63400 #define S_T5_RXREQ_C2    4
63401 #define M_T5_RXREQ_C2    0x3U
63402 #define V_T5_RXREQ_C2(x) ((x) << S_T5_RXREQ_C2)
63403 #define G_T5_RXREQ_C2(x) (((x) >> S_T5_RXREQ_C2) & M_T5_RXREQ_C2)
63404 
63405 #define S_T5_RXREQ_C1    2
63406 #define M_T5_RXREQ_C1    0x3U
63407 #define V_T5_RXREQ_C1(x) ((x) << S_T5_RXREQ_C1)
63408 #define G_T5_RXREQ_C1(x) (((x) >> S_T5_RXREQ_C1) & M_T5_RXREQ_C1)
63409 
63410 #define S_T5_RXREQ_C0    0
63411 #define M_T5_RXREQ_C0    0x3U
63412 #define V_T5_RXREQ_C0(x) ((x) << S_T5_RXREQ_C0)
63413 #define G_T5_RXREQ_C0(x) (((x) >> S_T5_RXREQ_C0) & M_T5_RXREQ_C0)
63414 
63415 #define S_T5_RXREQ_C3    6
63416 #define M_T5_RXREQ_C3    0x3U
63417 #define V_T5_RXREQ_C3(x) ((x) << S_T5_RXREQ_C3)
63418 #define G_T5_RXREQ_C3(x) (((x) >> S_T5_RXREQ_C3) & M_T5_RXREQ_C3)
63419 
63420 #define A_MAC_PORT_AE_RX_COEF_STAT 0x2a04
63421 
63422 #define S_T5_AE0_RXSTAT_RDY    15
63423 #define V_T5_AE0_RXSTAT_RDY(x) ((x) << S_T5_AE0_RXSTAT_RDY)
63424 #define F_T5_AE0_RXSTAT_RDY    V_T5_AE0_RXSTAT_RDY(1U)
63425 
63426 #define S_T5_AE0_RXSTAT_C2    4
63427 #define M_T5_AE0_RXSTAT_C2    0x3U
63428 #define V_T5_AE0_RXSTAT_C2(x) ((x) << S_T5_AE0_RXSTAT_C2)
63429 #define G_T5_AE0_RXSTAT_C2(x) (((x) >> S_T5_AE0_RXSTAT_C2) & M_T5_AE0_RXSTAT_C2)
63430 
63431 #define S_T5_AE0_RXSTAT_C1    2
63432 #define M_T5_AE0_RXSTAT_C1    0x3U
63433 #define V_T5_AE0_RXSTAT_C1(x) ((x) << S_T5_AE0_RXSTAT_C1)
63434 #define G_T5_AE0_RXSTAT_C1(x) (((x) >> S_T5_AE0_RXSTAT_C1) & M_T5_AE0_RXSTAT_C1)
63435 
63436 #define S_T5_AE0_RXSTAT_C0    0
63437 #define M_T5_AE0_RXSTAT_C0    0x3U
63438 #define V_T5_AE0_RXSTAT_C0(x) ((x) << S_T5_AE0_RXSTAT_C0)
63439 #define G_T5_AE0_RXSTAT_C0(x) (((x) >> S_T5_AE0_RXSTAT_C0) & M_T5_AE0_RXSTAT_C0)
63440 
63441 #define S_T5_AE0_RXSTAT_LSNA    14
63442 #define V_T5_AE0_RXSTAT_LSNA(x) ((x) << S_T5_AE0_RXSTAT_LSNA)
63443 #define F_T5_AE0_RXSTAT_LSNA    V_T5_AE0_RXSTAT_LSNA(1U)
63444 
63445 #define S_T5_AE0_RXSTAT_FEC    13
63446 #define V_T5_AE0_RXSTAT_FEC(x) ((x) << S_T5_AE0_RXSTAT_FEC)
63447 #define F_T5_AE0_RXSTAT_FEC    V_T5_AE0_RXSTAT_FEC(1U)
63448 
63449 #define S_T5_AE0_RXSTAT_TF    12
63450 #define V_T5_AE0_RXSTAT_TF(x) ((x) << S_T5_AE0_RXSTAT_TF)
63451 #define F_T5_AE0_RXSTAT_TF    V_T5_AE0_RXSTAT_TF(1U)
63452 
63453 #define S_T5_AE0_RXSTAT_C3    6
63454 #define M_T5_AE0_RXSTAT_C3    0x3U
63455 #define V_T5_AE0_RXSTAT_C3(x) ((x) << S_T5_AE0_RXSTAT_C3)
63456 #define G_T5_AE0_RXSTAT_C3(x) (((x) >> S_T5_AE0_RXSTAT_C3) & M_T5_AE0_RXSTAT_C3)
63457 
63458 #define A_MAC_PORT_AE_TX_COEF_REQ 0x2a08
63459 
63460 #define S_T5_TXREQ_C2    4
63461 #define M_T5_TXREQ_C2    0x3U
63462 #define V_T5_TXREQ_C2(x) ((x) << S_T5_TXREQ_C2)
63463 #define G_T5_TXREQ_C2(x) (((x) >> S_T5_TXREQ_C2) & M_T5_TXREQ_C2)
63464 
63465 #define S_T5_TXREQ_C1    2
63466 #define M_T5_TXREQ_C1    0x3U
63467 #define V_T5_TXREQ_C1(x) ((x) << S_T5_TXREQ_C1)
63468 #define G_T5_TXREQ_C1(x) (((x) >> S_T5_TXREQ_C1) & M_T5_TXREQ_C1)
63469 
63470 #define S_T5_TXREQ_C0    0
63471 #define M_T5_TXREQ_C0    0x3U
63472 #define V_T5_TXREQ_C0(x) ((x) << S_T5_TXREQ_C0)
63473 #define G_T5_TXREQ_C0(x) (((x) >> S_T5_TXREQ_C0) & M_T5_TXREQ_C0)
63474 
63475 #define S_TXREQ_FEC    11
63476 #define V_TXREQ_FEC(x) ((x) << S_TXREQ_FEC)
63477 #define F_TXREQ_FEC    V_TXREQ_FEC(1U)
63478 
63479 #define S_T5_TXREQ_C3    6
63480 #define M_T5_TXREQ_C3    0x3U
63481 #define V_T5_TXREQ_C3(x) ((x) << S_T5_TXREQ_C3)
63482 #define G_T5_TXREQ_C3(x) (((x) >> S_T5_TXREQ_C3) & M_T5_TXREQ_C3)
63483 
63484 #define A_MAC_PORT_AE_TX_COEF_STAT 0x2a0c
63485 
63486 #define S_T5_TXSTAT_C2    4
63487 #define M_T5_TXSTAT_C2    0x3U
63488 #define V_T5_TXSTAT_C2(x) ((x) << S_T5_TXSTAT_C2)
63489 #define G_T5_TXSTAT_C2(x) (((x) >> S_T5_TXSTAT_C2) & M_T5_TXSTAT_C2)
63490 
63491 #define S_T5_TXSTAT_C1    2
63492 #define M_T5_TXSTAT_C1    0x3U
63493 #define V_T5_TXSTAT_C1(x) ((x) << S_T5_TXSTAT_C1)
63494 #define G_T5_TXSTAT_C1(x) (((x) >> S_T5_TXSTAT_C1) & M_T5_TXSTAT_C1)
63495 
63496 #define S_T5_TXSTAT_C0    0
63497 #define M_T5_TXSTAT_C0    0x3U
63498 #define V_T5_TXSTAT_C0(x) ((x) << S_T5_TXSTAT_C0)
63499 #define G_T5_TXSTAT_C0(x) (((x) >> S_T5_TXSTAT_C0) & M_T5_TXSTAT_C0)
63500 
63501 #define S_T5_TXSTAT_C3    6
63502 #define M_T5_TXSTAT_C3    0x3U
63503 #define V_T5_TXSTAT_C3(x) ((x) << S_T5_TXSTAT_C3)
63504 #define G_T5_TXSTAT_C3(x) (((x) >> S_T5_TXSTAT_C3) & M_T5_TXSTAT_C3)
63505 
63506 #define A_MAC_PORT_AE_REG_MODE 0x2a10
63507 
63508 #define S_AET_RSVD    7
63509 #define V_AET_RSVD(x) ((x) << S_AET_RSVD)
63510 #define F_AET_RSVD    V_AET_RSVD(1U)
63511 
63512 #define S_AET_ENABLE    6
63513 #define V_AET_ENABLE(x) ((x) << S_AET_ENABLE)
63514 #define F_AET_ENABLE    V_AET_ENABLE(1U)
63515 
63516 #define S_SET_WAIT_TIMER    13
63517 #define M_SET_WAIT_TIMER    0x3U
63518 #define V_SET_WAIT_TIMER(x) ((x) << S_SET_WAIT_TIMER)
63519 #define G_SET_WAIT_TIMER(x) (((x) >> S_SET_WAIT_TIMER) & M_SET_WAIT_TIMER)
63520 
63521 #define S_C2_C3_STATE_SEL    12
63522 #define V_C2_C3_STATE_SEL(x) ((x) << S_C2_C3_STATE_SEL)
63523 #define F_C2_C3_STATE_SEL    V_C2_C3_STATE_SEL(1U)
63524 
63525 #define S_FFE4_EN    11
63526 #define V_FFE4_EN(x) ((x) << S_FFE4_EN)
63527 #define F_FFE4_EN    V_FFE4_EN(1U)
63528 
63529 #define S_FEC_REQUEST    10
63530 #define V_FEC_REQUEST(x) ((x) << S_FEC_REQUEST)
63531 #define F_FEC_REQUEST    V_FEC_REQUEST(1U)
63532 
63533 #define S_FEC_SUPPORTED    9
63534 #define V_FEC_SUPPORTED(x) ((x) << S_FEC_SUPPORTED)
63535 #define F_FEC_SUPPORTED    V_FEC_SUPPORTED(1U)
63536 
63537 #define S_TX_FIXED    8
63538 #define V_TX_FIXED(x) ((x) << S_TX_FIXED)
63539 #define F_TX_FIXED    V_TX_FIXED(1U)
63540 
63541 #define A_MAC_PORT_AE_PRBS_CTL 0x2a14
63542 #define A_MAC_PORT_AE_FSM_CTL 0x2a18
63543 
63544 #define S_CIN_ENABLE    15
63545 #define V_CIN_ENABLE(x) ((x) << S_CIN_ENABLE)
63546 #define F_CIN_ENABLE    V_CIN_ENABLE(1U)
63547 
63548 #define A_MAC_PORT_AE_FSM_STATE 0x2a1c
63549 #define A_MAC_PORT_AE_RX_COEF_REQ_1 0x2a20
63550 #define A_MAC_PORT_AE_RX_COEF_STAT_1 0x2a24
63551 
63552 #define S_T5_AE1_RXSTAT_RDY    15
63553 #define V_T5_AE1_RXSTAT_RDY(x) ((x) << S_T5_AE1_RXSTAT_RDY)
63554 #define F_T5_AE1_RXSTAT_RDY    V_T5_AE1_RXSTAT_RDY(1U)
63555 
63556 #define S_T5_AE1_RXSTAT_C2    4
63557 #define M_T5_AE1_RXSTAT_C2    0x3U
63558 #define V_T5_AE1_RXSTAT_C2(x) ((x) << S_T5_AE1_RXSTAT_C2)
63559 #define G_T5_AE1_RXSTAT_C2(x) (((x) >> S_T5_AE1_RXSTAT_C2) & M_T5_AE1_RXSTAT_C2)
63560 
63561 #define S_T5_AE1_RXSTAT_C1    2
63562 #define M_T5_AE1_RXSTAT_C1    0x3U
63563 #define V_T5_AE1_RXSTAT_C1(x) ((x) << S_T5_AE1_RXSTAT_C1)
63564 #define G_T5_AE1_RXSTAT_C1(x) (((x) >> S_T5_AE1_RXSTAT_C1) & M_T5_AE1_RXSTAT_C1)
63565 
63566 #define S_T5_AE1_RXSTAT_C0    0
63567 #define M_T5_AE1_RXSTAT_C0    0x3U
63568 #define V_T5_AE1_RXSTAT_C0(x) ((x) << S_T5_AE1_RXSTAT_C0)
63569 #define G_T5_AE1_RXSTAT_C0(x) (((x) >> S_T5_AE1_RXSTAT_C0) & M_T5_AE1_RXSTAT_C0)
63570 
63571 #define S_T5_AE1_RXSTAT_LSNA    14
63572 #define V_T5_AE1_RXSTAT_LSNA(x) ((x) << S_T5_AE1_RXSTAT_LSNA)
63573 #define F_T5_AE1_RXSTAT_LSNA    V_T5_AE1_RXSTAT_LSNA(1U)
63574 
63575 #define S_T5_AE1_RXSTAT_FEC    13
63576 #define V_T5_AE1_RXSTAT_FEC(x) ((x) << S_T5_AE1_RXSTAT_FEC)
63577 #define F_T5_AE1_RXSTAT_FEC    V_T5_AE1_RXSTAT_FEC(1U)
63578 
63579 #define S_T5_AE1_RXSTAT_TF    12
63580 #define V_T5_AE1_RXSTAT_TF(x) ((x) << S_T5_AE1_RXSTAT_TF)
63581 #define F_T5_AE1_RXSTAT_TF    V_T5_AE1_RXSTAT_TF(1U)
63582 
63583 #define S_T5_AE1_RXSTAT_C3    6
63584 #define M_T5_AE1_RXSTAT_C3    0x3U
63585 #define V_T5_AE1_RXSTAT_C3(x) ((x) << S_T5_AE1_RXSTAT_C3)
63586 #define G_T5_AE1_RXSTAT_C3(x) (((x) >> S_T5_AE1_RXSTAT_C3) & M_T5_AE1_RXSTAT_C3)
63587 
63588 #define A_MAC_PORT_AE_TX_COEF_REQ_1 0x2a28
63589 #define A_MAC_PORT_AE_TX_COEF_STAT_1 0x2a2c
63590 #define A_MAC_PORT_AE_REG_MODE_1 0x2a30
63591 #define A_MAC_PORT_AE_PRBS_CTL_1 0x2a34
63592 #define A_MAC_PORT_AE_FSM_CTL_1 0x2a38
63593 #define A_MAC_PORT_AE_FSM_STATE_1 0x2a3c
63594 #define A_MAC_PORT_AE_RX_COEF_REQ_2 0x2a40
63595 #define A_MAC_PORT_AE_RX_COEF_STAT_2 0x2a44
63596 
63597 #define S_T5_AE2_RXSTAT_RDY    15
63598 #define V_T5_AE2_RXSTAT_RDY(x) ((x) << S_T5_AE2_RXSTAT_RDY)
63599 #define F_T5_AE2_RXSTAT_RDY    V_T5_AE2_RXSTAT_RDY(1U)
63600 
63601 #define S_T5_AE2_RXSTAT_C2    4
63602 #define M_T5_AE2_RXSTAT_C2    0x3U
63603 #define V_T5_AE2_RXSTAT_C2(x) ((x) << S_T5_AE2_RXSTAT_C2)
63604 #define G_T5_AE2_RXSTAT_C2(x) (((x) >> S_T5_AE2_RXSTAT_C2) & M_T5_AE2_RXSTAT_C2)
63605 
63606 #define S_T5_AE2_RXSTAT_C1    2
63607 #define M_T5_AE2_RXSTAT_C1    0x3U
63608 #define V_T5_AE2_RXSTAT_C1(x) ((x) << S_T5_AE2_RXSTAT_C1)
63609 #define G_T5_AE2_RXSTAT_C1(x) (((x) >> S_T5_AE2_RXSTAT_C1) & M_T5_AE2_RXSTAT_C1)
63610 
63611 #define S_T5_AE2_RXSTAT_C0    0
63612 #define M_T5_AE2_RXSTAT_C0    0x3U
63613 #define V_T5_AE2_RXSTAT_C0(x) ((x) << S_T5_AE2_RXSTAT_C0)
63614 #define G_T5_AE2_RXSTAT_C0(x) (((x) >> S_T5_AE2_RXSTAT_C0) & M_T5_AE2_RXSTAT_C0)
63615 
63616 #define S_T5_AE2_RXSTAT_LSNA    14
63617 #define V_T5_AE2_RXSTAT_LSNA(x) ((x) << S_T5_AE2_RXSTAT_LSNA)
63618 #define F_T5_AE2_RXSTAT_LSNA    V_T5_AE2_RXSTAT_LSNA(1U)
63619 
63620 #define S_T5_AE2_RXSTAT_FEC    13
63621 #define V_T5_AE2_RXSTAT_FEC(x) ((x) << S_T5_AE2_RXSTAT_FEC)
63622 #define F_T5_AE2_RXSTAT_FEC    V_T5_AE2_RXSTAT_FEC(1U)
63623 
63624 #define S_T5_AE2_RXSTAT_TF    12
63625 #define V_T5_AE2_RXSTAT_TF(x) ((x) << S_T5_AE2_RXSTAT_TF)
63626 #define F_T5_AE2_RXSTAT_TF    V_T5_AE2_RXSTAT_TF(1U)
63627 
63628 #define S_T5_AE2_RXSTAT_C3    6
63629 #define M_T5_AE2_RXSTAT_C3    0x3U
63630 #define V_T5_AE2_RXSTAT_C3(x) ((x) << S_T5_AE2_RXSTAT_C3)
63631 #define G_T5_AE2_RXSTAT_C3(x) (((x) >> S_T5_AE2_RXSTAT_C3) & M_T5_AE2_RXSTAT_C3)
63632 
63633 #define A_MAC_PORT_AE_TX_COEF_REQ_2 0x2a48
63634 #define A_MAC_PORT_AE_TX_COEF_STAT_2 0x2a4c
63635 #define A_MAC_PORT_AE_REG_MODE_2 0x2a50
63636 #define A_MAC_PORT_AE_PRBS_CTL_2 0x2a54
63637 #define A_MAC_PORT_AE_FSM_CTL_2 0x2a58
63638 #define A_MAC_PORT_AE_FSM_STATE_2 0x2a5c
63639 #define A_MAC_PORT_AE_RX_COEF_REQ_3 0x2a60
63640 #define A_MAC_PORT_AE_RX_COEF_STAT_3 0x2a64
63641 
63642 #define S_T5_AE3_RXSTAT_RDY    15
63643 #define V_T5_AE3_RXSTAT_RDY(x) ((x) << S_T5_AE3_RXSTAT_RDY)
63644 #define F_T5_AE3_RXSTAT_RDY    V_T5_AE3_RXSTAT_RDY(1U)
63645 
63646 #define S_T5_AE3_RXSTAT_C2    4
63647 #define M_T5_AE3_RXSTAT_C2    0x3U
63648 #define V_T5_AE3_RXSTAT_C2(x) ((x) << S_T5_AE3_RXSTAT_C2)
63649 #define G_T5_AE3_RXSTAT_C2(x) (((x) >> S_T5_AE3_RXSTAT_C2) & M_T5_AE3_RXSTAT_C2)
63650 
63651 #define S_T5_AE3_RXSTAT_C1    2
63652 #define M_T5_AE3_RXSTAT_C1    0x3U
63653 #define V_T5_AE3_RXSTAT_C1(x) ((x) << S_T5_AE3_RXSTAT_C1)
63654 #define G_T5_AE3_RXSTAT_C1(x) (((x) >> S_T5_AE3_RXSTAT_C1) & M_T5_AE3_RXSTAT_C1)
63655 
63656 #define S_T5_AE3_RXSTAT_C0    0
63657 #define M_T5_AE3_RXSTAT_C0    0x3U
63658 #define V_T5_AE3_RXSTAT_C0(x) ((x) << S_T5_AE3_RXSTAT_C0)
63659 #define G_T5_AE3_RXSTAT_C0(x) (((x) >> S_T5_AE3_RXSTAT_C0) & M_T5_AE3_RXSTAT_C0)
63660 
63661 #define S_T5_AE3_RXSTAT_LSNA    14
63662 #define V_T5_AE3_RXSTAT_LSNA(x) ((x) << S_T5_AE3_RXSTAT_LSNA)
63663 #define F_T5_AE3_RXSTAT_LSNA    V_T5_AE3_RXSTAT_LSNA(1U)
63664 
63665 #define S_T5_AE3_RXSTAT_FEC    13
63666 #define V_T5_AE3_RXSTAT_FEC(x) ((x) << S_T5_AE3_RXSTAT_FEC)
63667 #define F_T5_AE3_RXSTAT_FEC    V_T5_AE3_RXSTAT_FEC(1U)
63668 
63669 #define S_T5_AE3_RXSTAT_TF    12
63670 #define V_T5_AE3_RXSTAT_TF(x) ((x) << S_T5_AE3_RXSTAT_TF)
63671 #define F_T5_AE3_RXSTAT_TF    V_T5_AE3_RXSTAT_TF(1U)
63672 
63673 #define S_T5_AE3_RXSTAT_C3    6
63674 #define M_T5_AE3_RXSTAT_C3    0x3U
63675 #define V_T5_AE3_RXSTAT_C3(x) ((x) << S_T5_AE3_RXSTAT_C3)
63676 #define G_T5_AE3_RXSTAT_C3(x) (((x) >> S_T5_AE3_RXSTAT_C3) & M_T5_AE3_RXSTAT_C3)
63677 
63678 #define A_MAC_PORT_AE_TX_COEF_REQ_3 0x2a68
63679 #define A_MAC_PORT_AE_TX_COEF_STAT_3 0x2a6c
63680 #define A_MAC_PORT_AE_REG_MODE_3 0x2a70
63681 #define A_MAC_PORT_AE_PRBS_CTL_3 0x2a74
63682 #define A_MAC_PORT_AE_FSM_CTL_3 0x2a78
63683 #define A_MAC_PORT_AE_FSM_STATE_3 0x2a7c
63684 #define A_MAC_PORT_AE_TX_DIS 0x2a80
63685 #define A_MAC_PORT_AE_KR_CTRL 0x2a84
63686 #define A_MAC_PORT_AE_RX_SIGDET 0x2a88
63687 #define A_MAC_PORT_AE_KR_STATUS 0x2a8c
63688 #define A_MAC_PORT_AE_TX_DIS_1 0x2a90
63689 #define A_MAC_PORT_AE_KR_CTRL_1 0x2a94
63690 #define A_MAC_PORT_AE_RX_SIGDET_1 0x2a98
63691 #define A_MAC_PORT_AE_KR_STATUS_1 0x2a9c
63692 #define A_MAC_PORT_AE_TX_DIS_2 0x2aa0
63693 #define A_MAC_PORT_AE_KR_CTRL_2 0x2aa4
63694 #define A_MAC_PORT_AE_RX_SIGDET_2 0x2aa8
63695 #define A_MAC_PORT_AE_KR_STATUS_2 0x2aac
63696 #define A_MAC_PORT_AE_TX_DIS_3 0x2ab0
63697 #define A_MAC_PORT_AE_KR_CTRL_3 0x2ab4
63698 #define A_MAC_PORT_AE_RX_SIGDET_3 0x2ab8
63699 #define A_MAC_PORT_AE_KR_STATUS_3 0x2abc
63700 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_0 0x2b00
63701 
63702 #define S_EN_HOLD_FAIL    14
63703 #define V_EN_HOLD_FAIL(x) ((x) << S_EN_HOLD_FAIL)
63704 #define F_EN_HOLD_FAIL    V_EN_HOLD_FAIL(1U)
63705 
63706 #define S_INIT_METH    12
63707 #define M_INIT_METH    0x3U
63708 #define V_INIT_METH(x) ((x) << S_INIT_METH)
63709 #define G_INIT_METH(x) (((x) >> S_INIT_METH) & M_INIT_METH)
63710 
63711 #define S_CE_DECS    8
63712 #define M_CE_DECS    0xfU
63713 #define V_CE_DECS(x) ((x) << S_CE_DECS)
63714 #define G_CE_DECS(x) (((x) >> S_CE_DECS) & M_CE_DECS)
63715 
63716 #define S_EN_ZFE    7
63717 #define V_EN_ZFE(x) ((x) << S_EN_ZFE)
63718 #define F_EN_ZFE    V_EN_ZFE(1U)
63719 
63720 #define S_EN_GAIN_TOG    6
63721 #define V_EN_GAIN_TOG(x) ((x) << S_EN_GAIN_TOG)
63722 #define F_EN_GAIN_TOG    V_EN_GAIN_TOG(1U)
63723 
63724 #define S_EN_AI_C1    5
63725 #define V_EN_AI_C1(x) ((x) << S_EN_AI_C1)
63726 #define F_EN_AI_C1    V_EN_AI_C1(1U)
63727 
63728 #define S_EN_MAX_ST    4
63729 #define V_EN_MAX_ST(x) ((x) << S_EN_MAX_ST)
63730 #define F_EN_MAX_ST    V_EN_MAX_ST(1U)
63731 
63732 #define S_EN_H1T_EQ    3
63733 #define V_EN_H1T_EQ(x) ((x) << S_EN_H1T_EQ)
63734 #define F_EN_H1T_EQ    V_EN_H1T_EQ(1U)
63735 
63736 #define S_H1TEQ_GOAL    0
63737 #define M_H1TEQ_GOAL    0x7U
63738 #define V_H1TEQ_GOAL(x) ((x) << S_H1TEQ_GOAL)
63739 #define G_H1TEQ_GOAL(x) (((x) >> S_H1TEQ_GOAL) & M_H1TEQ_GOAL)
63740 
63741 #define S_T6_INIT_METH    12
63742 #define M_T6_INIT_METH    0xfU
63743 #define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH)
63744 #define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH)
63745 
63746 #define S_INIT_CNT    8
63747 #define M_INIT_CNT    0xfU
63748 #define V_INIT_CNT(x) ((x) << S_INIT_CNT)
63749 #define G_INIT_CNT(x) (((x) >> S_INIT_CNT) & M_INIT_CNT)
63750 
63751 #define S_EN_AI_N0    5
63752 #define V_EN_AI_N0(x) ((x) << S_EN_AI_N0)
63753 #define F_EN_AI_N0    V_EN_AI_N0(1U)
63754 
63755 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0 0x2b04
63756 
63757 #define S_GAIN_TH    6
63758 #define M_GAIN_TH    0x1fU
63759 #define V_GAIN_TH(x) ((x) << S_GAIN_TH)
63760 #define G_GAIN_TH(x) (((x) >> S_GAIN_TH) & M_GAIN_TH)
63761 
63762 #define S_EN_SD_TH    5
63763 #define V_EN_SD_TH(x) ((x) << S_EN_SD_TH)
63764 #define F_EN_SD_TH    V_EN_SD_TH(1U)
63765 
63766 #define S_EN_AMIN_TH    4
63767 #define V_EN_AMIN_TH(x) ((x) << S_EN_AMIN_TH)
63768 #define F_EN_AMIN_TH    V_EN_AMIN_TH(1U)
63769 
63770 #define S_AMIN_TH    0
63771 #define M_AMIN_TH    0xfU
63772 #define V_AMIN_TH(x) ((x) << S_AMIN_TH)
63773 #define G_AMIN_TH(x) (((x) >> S_AMIN_TH) & M_AMIN_TH)
63774 
63775 #define S_FEC_CNV    15
63776 #define V_FEC_CNV(x) ((x) << S_FEC_CNV)
63777 #define F_FEC_CNV    V_FEC_CNV(1U)
63778 
63779 #define S_EN_RETRY    14
63780 #define V_EN_RETRY(x) ((x) << S_EN_RETRY)
63781 #define F_EN_RETRY    V_EN_RETRY(1U)
63782 
63783 #define S_DPC_METH    12
63784 #define M_DPC_METH    0x3U
63785 #define V_DPC_METH(x) ((x) << S_DPC_METH)
63786 #define G_DPC_METH(x) (((x) >> S_DPC_METH) & M_DPC_METH)
63787 
63788 #define S_EN_P2    11
63789 #define V_EN_P2(x) ((x) << S_EN_P2)
63790 #define F_EN_P2    V_EN_P2(1U)
63791 
63792 #define A_MAC_PORT_AET_ZFE_LIMITS_0 0x2b08
63793 
63794 #define S_ACC_LIM    8
63795 #define M_ACC_LIM    0xfU
63796 #define V_ACC_LIM(x) ((x) << S_ACC_LIM)
63797 #define G_ACC_LIM(x) (((x) >> S_ACC_LIM) & M_ACC_LIM)
63798 
63799 #define S_CNV_LIM    4
63800 #define M_CNV_LIM    0xfU
63801 #define V_CNV_LIM(x) ((x) << S_CNV_LIM)
63802 #define G_CNV_LIM(x) (((x) >> S_CNV_LIM) & M_CNV_LIM)
63803 
63804 #define S_TOG_LIM    0
63805 #define M_TOG_LIM    0xfU
63806 #define V_TOG_LIM(x) ((x) << S_TOG_LIM)
63807 #define G_TOG_LIM(x) (((x) >> S_TOG_LIM) & M_TOG_LIM)
63808 
63809 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0 0x2b0c
63810 
63811 #define S_BOOT_LUT7    12
63812 #define M_BOOT_LUT7    0xfU
63813 #define V_BOOT_LUT7(x) ((x) << S_BOOT_LUT7)
63814 #define G_BOOT_LUT7(x) (((x) >> S_BOOT_LUT7) & M_BOOT_LUT7)
63815 
63816 #define S_BOOT_LUT6    8
63817 #define M_BOOT_LUT6    0xfU
63818 #define V_BOOT_LUT6(x) ((x) << S_BOOT_LUT6)
63819 #define G_BOOT_LUT6(x) (((x) >> S_BOOT_LUT6) & M_BOOT_LUT6)
63820 
63821 #define S_BOOT_LUT45    4
63822 #define M_BOOT_LUT45    0xfU
63823 #define V_BOOT_LUT45(x) ((x) << S_BOOT_LUT45)
63824 #define G_BOOT_LUT45(x) (((x) >> S_BOOT_LUT45) & M_BOOT_LUT45)
63825 
63826 #define S_BOOT_LUT0123    2
63827 #define M_BOOT_LUT0123    0x3U
63828 #define V_BOOT_LUT0123(x) ((x) << S_BOOT_LUT0123)
63829 #define G_BOOT_LUT0123(x) (((x) >> S_BOOT_LUT0123) & M_BOOT_LUT0123)
63830 
63831 #define S_BOOT_DEC_C0    1
63832 #define V_BOOT_DEC_C0(x) ((x) << S_BOOT_DEC_C0)
63833 #define F_BOOT_DEC_C0    V_BOOT_DEC_C0(1U)
63834 
63835 #define S_BOOT_LUT5    8
63836 #define M_BOOT_LUT5    0xfU
63837 #define V_BOOT_LUT5(x) ((x) << S_BOOT_LUT5)
63838 #define G_BOOT_LUT5(x) (((x) >> S_BOOT_LUT5) & M_BOOT_LUT5)
63839 
63840 #define A_MAC_PORT_AET_STATUS_0 0x2b10
63841 
63842 #define S_AET_STAT    9
63843 #define M_AET_STAT    0xfU
63844 #define V_AET_STAT(x) ((x) << S_AET_STAT)
63845 #define G_AET_STAT(x) (((x) >> S_AET_STAT) & M_AET_STAT)
63846 
63847 #define S_NEU_STATE    5
63848 #define M_NEU_STATE    0xfU
63849 #define V_NEU_STATE(x) ((x) << S_NEU_STATE)
63850 #define G_NEU_STATE(x) (((x) >> S_NEU_STATE) & M_NEU_STATE)
63851 
63852 #define S_CTRL_STATE    0
63853 #define M_CTRL_STATE    0x1fU
63854 #define V_CTRL_STATE(x) ((x) << S_CTRL_STATE)
63855 #define G_CTRL_STATE(x) (((x) >> S_CTRL_STATE) & M_CTRL_STATE)
63856 
63857 #define S_CTRL_STAT    8
63858 #define M_CTRL_STAT    0x1fU
63859 #define V_CTRL_STAT(x) ((x) << S_CTRL_STAT)
63860 #define G_CTRL_STAT(x) (((x) >> S_CTRL_STAT) & M_CTRL_STAT)
63861 
63862 #define S_T6_NEU_STATE    4
63863 #define M_T6_NEU_STATE    0xfU
63864 #define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE)
63865 #define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE)
63866 
63867 #define S_T6_CTRL_STATE    0
63868 #define M_T6_CTRL_STATE    0xfU
63869 #define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE)
63870 #define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE)
63871 
63872 #define A_MAC_PORT_AET_STATUS_20 0x2b14
63873 
63874 #define S_FRAME_LOCK_CNT    0
63875 #define M_FRAME_LOCK_CNT    0x7U
63876 #define V_FRAME_LOCK_CNT(x) ((x) << S_FRAME_LOCK_CNT)
63877 #define G_FRAME_LOCK_CNT(x) (((x) >> S_FRAME_LOCK_CNT) & M_FRAME_LOCK_CNT)
63878 
63879 #define A_MAC_PORT_AET_LIMITS0 0x2b18
63880 
63881 #define S_DPC_TIME_LIM    0
63882 #define M_DPC_TIME_LIM    0x3U
63883 #define V_DPC_TIME_LIM(x) ((x) << S_DPC_TIME_LIM)
63884 #define G_DPC_TIME_LIM(x) (((x) >> S_DPC_TIME_LIM) & M_DPC_TIME_LIM)
63885 
63886 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_1 0x2b20
63887 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1 0x2b24
63888 #define A_MAC_PORT_AET_ZFE_LIMITS_1 0x2b28
63889 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1 0x2b2c
63890 #define A_MAC_PORT_AET_STATUS_1 0x2b30
63891 #define A_MAC_PORT_AET_STATUS_21 0x2b34
63892 #define A_MAC_PORT_AET_LIMITS1 0x2b38
63893 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_2 0x2b40
63894 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2 0x2b44
63895 #define A_MAC_PORT_AET_ZFE_LIMITS_2 0x2b48
63896 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2 0x2b4c
63897 #define A_MAC_PORT_AET_STATUS_2 0x2b50
63898 #define A_MAC_PORT_AET_STATUS_22 0x2b54
63899 #define A_MAC_PORT_AET_LIMITS2 0x2b58
63900 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_3 0x2b60
63901 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3 0x2b64
63902 #define A_MAC_PORT_AET_ZFE_LIMITS_3 0x2b68
63903 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3 0x2b6c
63904 #define A_MAC_PORT_AET_STATUS_3 0x2b70
63905 #define A_MAC_PORT_AET_STATUS_23 0x2b74
63906 #define A_MAC_PORT_AET_LIMITS3 0x2b78
63907 #define A_T6_MAC_PORT_BEAN_CTL 0x2c00
63908 #define A_T6_MAC_PORT_BEAN_STATUS 0x2c04
63909 #define A_T6_MAC_PORT_BEAN_ABILITY_0 0x2c08
63910 
63911 #define S_BEAN_REM_FAULT    13
63912 #define V_BEAN_REM_FAULT(x) ((x) << S_BEAN_REM_FAULT)
63913 #define F_BEAN_REM_FAULT    V_BEAN_REM_FAULT(1U)
63914 
63915 #define A_T6_MAC_PORT_BEAN_ABILITY_1 0x2c0c
63916 #define A_T6_MAC_PORT_BEAN_ABILITY_2 0x2c10
63917 #define A_T6_MAC_PORT_BEAN_REM_ABILITY_0 0x2c14
63918 
63919 #define S_BEAN_ABL_REM_FAULT    13
63920 #define V_BEAN_ABL_REM_FAULT(x) ((x) << S_BEAN_ABL_REM_FAULT)
63921 #define F_BEAN_ABL_REM_FAULT    V_BEAN_ABL_REM_FAULT(1U)
63922 
63923 #define A_T6_MAC_PORT_BEAN_REM_ABILITY_1 0x2c18
63924 #define A_T6_MAC_PORT_BEAN_REM_ABILITY_2 0x2c1c
63925 #define A_T6_MAC_PORT_BEAN_MS_COUNT 0x2c20
63926 #define A_T6_MAC_PORT_BEAN_XNP_0 0x2c24
63927 #define A_T6_MAC_PORT_BEAN_XNP_1 0x2c28
63928 #define A_T6_MAC_PORT_BEAN_XNP_2 0x2c2c
63929 #define A_T6_MAC_PORT_LP_BEAN_XNP_0 0x2c30
63930 #define A_T6_MAC_PORT_LP_BEAN_XNP_1 0x2c34
63931 #define A_T6_MAC_PORT_LP_BEAN_XNP_2 0x2c38
63932 #define A_T6_MAC_PORT_BEAN_ETH_STATUS 0x2c3c
63933 
63934 #define S_100GCR4    11
63935 #define V_100GCR4(x) ((x) << S_100GCR4)
63936 #define F_100GCR4    V_100GCR4(1U)
63937 
63938 #define S_100GKR4    10
63939 #define V_100GKR4(x) ((x) << S_100GKR4)
63940 #define F_100GKR4    V_100GKR4(1U)
63941 
63942 #define S_100GKP4    9
63943 #define V_100GKP4(x) ((x) << S_100GKP4)
63944 #define F_100GKP4    V_100GKP4(1U)
63945 
63946 #define A_MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE 0x3000
63947 
63948 #define S_T5_TX_LINKEN    15
63949 #define V_T5_TX_LINKEN(x) ((x) << S_T5_TX_LINKEN)
63950 #define F_T5_TX_LINKEN    V_T5_TX_LINKEN(1U)
63951 
63952 #define S_T5_TX_LINKRST    14
63953 #define V_T5_TX_LINKRST(x) ((x) << S_T5_TX_LINKRST)
63954 #define F_T5_TX_LINKRST    V_T5_TX_LINKRST(1U)
63955 
63956 #define S_T5_TX_CFGWRT    13
63957 #define V_T5_TX_CFGWRT(x) ((x) << S_T5_TX_CFGWRT)
63958 #define F_T5_TX_CFGWRT    V_T5_TX_CFGWRT(1U)
63959 
63960 #define S_T5_TX_CFGPTR    11
63961 #define M_T5_TX_CFGPTR    0x3U
63962 #define V_T5_TX_CFGPTR(x) ((x) << S_T5_TX_CFGPTR)
63963 #define G_T5_TX_CFGPTR(x) (((x) >> S_T5_TX_CFGPTR) & M_T5_TX_CFGPTR)
63964 
63965 #define S_T5_TX_CFGEXT    10
63966 #define V_T5_TX_CFGEXT(x) ((x) << S_T5_TX_CFGEXT)
63967 #define F_T5_TX_CFGEXT    V_T5_TX_CFGEXT(1U)
63968 
63969 #define S_T5_TX_CFGACT    9
63970 #define V_T5_TX_CFGACT(x) ((x) << S_T5_TX_CFGACT)
63971 #define F_T5_TX_CFGACT    V_T5_TX_CFGACT(1U)
63972 
63973 #define S_T5_TX_RSYNCC    8
63974 #define V_T5_TX_RSYNCC(x) ((x) << S_T5_TX_RSYNCC)
63975 #define F_T5_TX_RSYNCC    V_T5_TX_RSYNCC(1U)
63976 
63977 #define S_T5_TX_PLLSEL    6
63978 #define M_T5_TX_PLLSEL    0x3U
63979 #define V_T5_TX_PLLSEL(x) ((x) << S_T5_TX_PLLSEL)
63980 #define G_T5_TX_PLLSEL(x) (((x) >> S_T5_TX_PLLSEL) & M_T5_TX_PLLSEL)
63981 
63982 #define S_T5_TX_EXTC16    5
63983 #define V_T5_TX_EXTC16(x) ((x) << S_T5_TX_EXTC16)
63984 #define F_T5_TX_EXTC16    V_T5_TX_EXTC16(1U)
63985 
63986 #define S_T5_TX_DCKSEL    4
63987 #define V_T5_TX_DCKSEL(x) ((x) << S_T5_TX_DCKSEL)
63988 #define F_T5_TX_DCKSEL    V_T5_TX_DCKSEL(1U)
63989 
63990 #define S_T5_TX_RXLOOP    3
63991 #define V_T5_TX_RXLOOP(x) ((x) << S_T5_TX_RXLOOP)
63992 #define F_T5_TX_RXLOOP    V_T5_TX_RXLOOP(1U)
63993 
63994 #define S_T5_TX_BWSEL    2
63995 #define V_T5_TX_BWSEL(x) ((x) << S_T5_TX_BWSEL)
63996 #define F_T5_TX_BWSEL    V_T5_TX_BWSEL(1U)
63997 
63998 #define S_T5_TX_RTSEL    0
63999 #define M_T5_TX_RTSEL    0x3U
64000 #define V_T5_TX_RTSEL(x) ((x) << S_T5_TX_RTSEL)
64001 #define G_T5_TX_RTSEL(x) (((x) >> S_T5_TX_RTSEL) & M_T5_TX_RTSEL)
64002 
64003 #define S_T6_T5_TX_RXLOOP    5
64004 #define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
64005 #define F_T6_T5_TX_RXLOOP    V_T6_T5_TX_RXLOOP(1U)
64006 
64007 #define S_T5_TX_ENFFE4    4
64008 #define V_T5_TX_ENFFE4(x) ((x) << S_T5_TX_ENFFE4)
64009 #define F_T5_TX_ENFFE4    V_T5_TX_ENFFE4(1U)
64010 
64011 #define S_T6_T5_TX_BWSEL    2
64012 #define M_T6_T5_TX_BWSEL    0x3U
64013 #define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
64014 #define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
64015 
64016 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL 0x3004
64017 
64018 #define S_SPSEL    11
64019 #define M_SPSEL    0x7U
64020 #define V_SPSEL(x) ((x) << S_SPSEL)
64021 #define G_SPSEL(x) (((x) >> S_SPSEL) & M_SPSEL)
64022 
64023 #define S_AFDWEN    7
64024 #define V_AFDWEN(x) ((x) << S_AFDWEN)
64025 #define F_AFDWEN    V_AFDWEN(1U)
64026 
64027 #define S_TPGMD    3
64028 #define V_TPGMD(x) ((x) << S_TPGMD)
64029 #define F_TPGMD    V_TPGMD(1U)
64030 
64031 #define S_TC_FRCERR    10
64032 #define V_TC_FRCERR(x) ((x) << S_TC_FRCERR)
64033 #define F_TC_FRCERR    V_TC_FRCERR(1U)
64034 
64035 #define S_T6_ERROR    9
64036 #define V_T6_ERROR(x) ((x) << S_T6_ERROR)
64037 #define F_T6_ERROR    V_T6_ERROR(1U)
64038 
64039 #define S_SYNC    8
64040 #define V_SYNC(x) ((x) << S_SYNC)
64041 #define F_SYNC    V_SYNC(1U)
64042 
64043 #define S_P7CHK    5
64044 #define V_P7CHK(x) ((x) << S_P7CHK)
64045 #define F_P7CHK    V_P7CHK(1U)
64046 
64047 #define A_MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL 0x3008
64048 
64049 #define S_ZCALOVRD    8
64050 #define V_ZCALOVRD(x) ((x) << S_ZCALOVRD)
64051 #define F_ZCALOVRD    V_ZCALOVRD(1U)
64052 
64053 #define S_AMMODE    7
64054 #define V_AMMODE(x) ((x) << S_AMMODE)
64055 #define F_AMMODE    V_AMMODE(1U)
64056 
64057 #define S_AEPOL    6
64058 #define V_AEPOL(x) ((x) << S_AEPOL)
64059 #define F_AEPOL    V_AEPOL(1U)
64060 
64061 #define S_AESRC    5
64062 #define V_AESRC(x) ((x) << S_AESRC)
64063 #define F_AESRC    V_AESRC(1U)
64064 
64065 #define S_SASMODE    7
64066 #define V_SASMODE(x) ((x) << S_SASMODE)
64067 #define F_SASMODE    V_SASMODE(1U)
64068 
64069 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL 0x300c
64070 
64071 #define S_T5DRVHIZ    5
64072 #define V_T5DRVHIZ(x) ((x) << S_T5DRVHIZ)
64073 #define F_T5DRVHIZ    V_T5DRVHIZ(1U)
64074 
64075 #define S_T5SASIMP    4
64076 #define V_T5SASIMP(x) ((x) << S_T5SASIMP)
64077 #define F_T5SASIMP    V_T5SASIMP(1U)
64078 
64079 #define S_T5SLEW    2
64080 #define M_T5SLEW    0x3U
64081 #define V_T5SLEW(x) ((x) << S_T5SLEW)
64082 #define G_T5SLEW(x) (((x) >> S_T5SLEW) & M_T5SLEW)
64083 
64084 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3010
64085 
64086 #define S_T5C2BUFDCEN    5
64087 #define V_T5C2BUFDCEN(x) ((x) << S_T5C2BUFDCEN)
64088 #define F_T5C2BUFDCEN    V_T5C2BUFDCEN(1U)
64089 
64090 #define S_T5DCCEN    4
64091 #define V_T5DCCEN(x) ((x) << S_T5DCCEN)
64092 #define F_T5DCCEN    V_T5DCCEN(1U)
64093 
64094 #define S_T5REGBYP    3
64095 #define V_T5REGBYP(x) ((x) << S_T5REGBYP)
64096 #define F_T5REGBYP    V_T5REGBYP(1U)
64097 
64098 #define S_T5REGAEN    2
64099 #define V_T5REGAEN(x) ((x) << S_T5REGAEN)
64100 #define F_T5REGAEN    V_T5REGAEN(1U)
64101 
64102 #define S_T5REGAMP    0
64103 #define M_T5REGAMP    0x3U
64104 #define V_T5REGAMP(x) ((x) << S_T5REGAMP)
64105 #define G_T5REGAMP(x) (((x) >> S_T5REGAMP) & M_T5REGAMP)
64106 
64107 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3014
64108 
64109 #define S_RSTEP    15
64110 #define V_RSTEP(x) ((x) << S_RSTEP)
64111 #define F_RSTEP    V_RSTEP(1U)
64112 
64113 #define S_RLOCK    14
64114 #define V_RLOCK(x) ((x) << S_RLOCK)
64115 #define F_RLOCK    V_RLOCK(1U)
64116 
64117 #define S_RPOS    8
64118 #define M_RPOS    0x3fU
64119 #define V_RPOS(x) ((x) << S_RPOS)
64120 #define G_RPOS(x) (((x) >> S_RPOS) & M_RPOS)
64121 
64122 #define S_DCLKSAM    7
64123 #define V_DCLKSAM(x) ((x) << S_DCLKSAM)
64124 #define F_DCLKSAM    V_DCLKSAM(1U)
64125 
64126 #define A_MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3018
64127 
64128 #define S_CALSSTN    3
64129 #define M_CALSSTN    0x7U
64130 #define V_CALSSTN(x) ((x) << S_CALSSTN)
64131 #define G_CALSSTN(x) (((x) >> S_CALSSTN) & M_CALSSTN)
64132 
64133 #define S_CALSSTP    0
64134 #define M_CALSSTP    0x7U
64135 #define V_CALSSTP(x) ((x) << S_CALSSTP)
64136 #define G_CALSSTP(x) (((x) >> S_CALSSTP) & M_CALSSTP)
64137 
64138 #define S_T6_CALSSTN    8
64139 #define M_T6_CALSSTN    0x3fU
64140 #define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
64141 #define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
64142 
64143 #define S_T6_CALSSTP    0
64144 #define M_T6_CALSSTP    0x3fU
64145 #define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
64146 #define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
64147 
64148 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x301c
64149 
64150 #define S_DRTOL    0
64151 #define M_DRTOL    0x1fU
64152 #define V_DRTOL(x) ((x) << S_DRTOL)
64153 #define G_DRTOL(x) (((x) >> S_DRTOL) & M_DRTOL)
64154 
64155 #define S_T6_DRTOL    2
64156 #define M_T6_DRTOL    0x7U
64157 #define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
64158 #define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
64159 
64160 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT 0x3020
64161 
64162 #define S_T5NXTT0    0
64163 #define M_T5NXTT0    0x1fU
64164 #define V_T5NXTT0(x) ((x) << S_T5NXTT0)
64165 #define G_T5NXTT0(x) (((x) >> S_T5NXTT0) & M_T5NXTT0)
64166 
64167 #define S_T6_NXTT0    0
64168 #define M_T6_NXTT0    0x3fU
64169 #define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
64170 #define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
64171 
64172 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT 0x3024
64173 
64174 #define S_T5NXTT1    0
64175 #define M_T5NXTT1    0x3fU
64176 #define V_T5NXTT1(x) ((x) << S_T5NXTT1)
64177 #define G_T5NXTT1(x) (((x) >> S_T5NXTT1) & M_T5NXTT1)
64178 
64179 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT 0x3028
64180 
64181 #define S_T5NXTT2    0
64182 #define M_T5NXTT2    0x3fU
64183 #define V_T5NXTT2(x) ((x) << S_T5NXTT2)
64184 #define G_T5NXTT2(x) (((x) >> S_T5NXTT2) & M_T5NXTT2)
64185 
64186 #define S_T6_NXTT2    0
64187 #define M_T6_NXTT2    0x3fU
64188 #define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
64189 #define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
64190 
64191 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_3_COEFFICIENT 0x302c
64192 
64193 #define S_NXTT3    0
64194 #define M_NXTT3    0x3fU
64195 #define V_NXTT3(x) ((x) << S_NXTT3)
64196 #define G_NXTT3(x) (((x) >> S_NXTT3) & M_NXTT3)
64197 
64198 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE 0x3030
64199 
64200 #define S_T5TXPWR    0
64201 #define M_T5TXPWR    0x3fU
64202 #define V_T5TXPWR(x) ((x) << S_T5TXPWR)
64203 #define G_T5TXPWR(x) (((x) >> S_T5TXPWR) & M_T5TXPWR)
64204 
64205 #define A_MAC_PORT_TX_LINKA_TRANSMIT_POLARITY 0x3034
64206 
64207 #define S_NXTPOL    0
64208 #define M_NXTPOL    0x7U
64209 #define V_NXTPOL(x) ((x) << S_NXTPOL)
64210 #define G_NXTPOL(x) (((x) >> S_NXTPOL) & M_NXTPOL)
64211 
64212 #define S_T6_NXTPOL    0
64213 #define M_T6_NXTPOL    0xfU
64214 #define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
64215 #define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
64216 
64217 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3038
64218 
64219 #define S_CPREST    13
64220 #define V_CPREST(x) ((x) << S_CPREST)
64221 #define F_CPREST    V_CPREST(1U)
64222 
64223 #define S_CINIT    12
64224 #define V_CINIT(x) ((x) << S_CINIT)
64225 #define F_CINIT    V_CINIT(1U)
64226 
64227 #define S_SASCMD    10
64228 #define M_SASCMD    0x3U
64229 #define V_SASCMD(x) ((x) << S_SASCMD)
64230 #define G_SASCMD(x) (((x) >> S_SASCMD) & M_SASCMD)
64231 
64232 #define S_T6_C0UPDT    6
64233 #define M_T6_C0UPDT    0x3U
64234 #define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
64235 #define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
64236 
64237 #define S_C3UPDT    4
64238 #define M_C3UPDT    0x3U
64239 #define V_C3UPDT(x) ((x) << S_C3UPDT)
64240 #define G_C3UPDT(x) (((x) >> S_C3UPDT) & M_C3UPDT)
64241 
64242 #define S_T6_C2UPDT    2
64243 #define M_T6_C2UPDT    0x3U
64244 #define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
64245 #define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
64246 
64247 #define S_T6_C1UPDT    0
64248 #define M_T6_C1UPDT    0x3U
64249 #define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
64250 #define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
64251 
64252 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x303c
64253 
64254 #define S_T6_C0STAT    6
64255 #define M_T6_C0STAT    0x3U
64256 #define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
64257 #define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
64258 
64259 #define S_C3STAT    4
64260 #define M_C3STAT    0x3U
64261 #define V_C3STAT(x) ((x) << S_C3STAT)
64262 #define G_C3STAT(x) (((x) >> S_C3STAT) & M_C3STAT)
64263 
64264 #define S_T6_C2STAT    2
64265 #define M_T6_C2STAT    0x3U
64266 #define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
64267 #define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
64268 
64269 #define S_T6_C1STAT    0
64270 #define M_T6_C1STAT    0x3U
64271 #define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
64272 #define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
64273 
64274 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3040
64275 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3040
64276 
64277 #define S_AETAP0    0
64278 #define M_AETAP0    0x7fU
64279 #define V_AETAP0(x) ((x) << S_AETAP0)
64280 #define G_AETAP0(x) (((x) >> S_AETAP0) & M_AETAP0)
64281 
64282 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3044
64283 
64284 #define S_T5NIDAC1    0
64285 #define M_T5NIDAC1    0x3fU
64286 #define V_T5NIDAC1(x) ((x) << S_T5NIDAC1)
64287 #define G_T5NIDAC1(x) (((x) >> S_T5NIDAC1) & M_T5NIDAC1)
64288 
64289 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3044
64290 
64291 #define S_AETAP1    0
64292 #define M_AETAP1    0x7fU
64293 #define V_AETAP1(x) ((x) << S_AETAP1)
64294 #define G_AETAP1(x) (((x) >> S_AETAP1) & M_AETAP1)
64295 
64296 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3048
64297 
64298 #define S_T5NIDAC2    0
64299 #define M_T5NIDAC2    0x3fU
64300 #define V_T5NIDAC2(x) ((x) << S_T5NIDAC2)
64301 #define G_T5NIDAC2(x) (((x) >> S_T5NIDAC2) & M_T5NIDAC2)
64302 
64303 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3048
64304 
64305 #define S_AETAP2    0
64306 #define M_AETAP2    0x7fU
64307 #define V_AETAP2(x) ((x) << S_AETAP2)
64308 #define G_AETAP2(x) (((x) >> S_AETAP2) & M_AETAP2)
64309 
64310 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x304c
64311 
64312 #define S_AETAP3    0
64313 #define M_AETAP3    0x7fU
64314 #define V_AETAP3(x) ((x) << S_AETAP3)
64315 #define G_AETAP3(x) (((x) >> S_AETAP3) & M_AETAP3)
64316 
64317 #define A_MAC_PORT_TX_LINKA_TRANSMIT_APPLIED_TUNE_REGISTER 0x3050
64318 
64319 #define S_ATUNEN    8
64320 #define M_ATUNEN    0xffU
64321 #define V_ATUNEN(x) ((x) << S_ATUNEN)
64322 #define G_ATUNEN(x) (((x) >> S_ATUNEN) & M_ATUNEN)
64323 
64324 #define S_ATUNEP    0
64325 #define M_ATUNEP    0xffU
64326 #define V_ATUNEP(x) ((x) << S_ATUNEP)
64327 #define G_ATUNEP(x) (((x) >> S_ATUNEP) & M_ATUNEP)
64328 
64329 #define A_MAC_PORT_TX_LINKA_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3058
64330 
64331 #define S_DCCCOMPINV    8
64332 #define V_DCCCOMPINV(x) ((x) << S_DCCCOMPINV)
64333 #define F_DCCCOMPINV    V_DCCCOMPINV(1U)
64334 
64335 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3060
64336 #define A_MAC_PORT_TX_LINKA_TRANSMIT_4X_SEGMENT_APPLIED 0x3060
64337 
64338 #define S_AS4X7    14
64339 #define M_AS4X7    0x3U
64340 #define V_AS4X7(x) ((x) << S_AS4X7)
64341 #define G_AS4X7(x) (((x) >> S_AS4X7) & M_AS4X7)
64342 
64343 #define S_AS4X6    12
64344 #define M_AS4X6    0x3U
64345 #define V_AS4X6(x) ((x) << S_AS4X6)
64346 #define G_AS4X6(x) (((x) >> S_AS4X6) & M_AS4X6)
64347 
64348 #define S_AS4X5    10
64349 #define M_AS4X5    0x3U
64350 #define V_AS4X5(x) ((x) << S_AS4X5)
64351 #define G_AS4X5(x) (((x) >> S_AS4X5) & M_AS4X5)
64352 
64353 #define S_AS4X4    8
64354 #define M_AS4X4    0x3U
64355 #define V_AS4X4(x) ((x) << S_AS4X4)
64356 #define G_AS4X4(x) (((x) >> S_AS4X4) & M_AS4X4)
64357 
64358 #define S_AS4X3    6
64359 #define M_AS4X3    0x3U
64360 #define V_AS4X3(x) ((x) << S_AS4X3)
64361 #define G_AS4X3(x) (((x) >> S_AS4X3) & M_AS4X3)
64362 
64363 #define S_AS4X2    4
64364 #define M_AS4X2    0x3U
64365 #define V_AS4X2(x) ((x) << S_AS4X2)
64366 #define G_AS4X2(x) (((x) >> S_AS4X2) & M_AS4X2)
64367 
64368 #define S_AS4X1    2
64369 #define M_AS4X1    0x3U
64370 #define V_AS4X1(x) ((x) << S_AS4X1)
64371 #define G_AS4X1(x) (((x) >> S_AS4X1) & M_AS4X1)
64372 
64373 #define S_AS4X0    0
64374 #define M_AS4X0    0x3U
64375 #define V_AS4X0(x) ((x) << S_AS4X0)
64376 #define G_AS4X0(x) (((x) >> S_AS4X0) & M_AS4X0)
64377 
64378 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3064
64379 
64380 #define S_T5AIDAC1    0
64381 #define M_T5AIDAC1    0x3fU
64382 #define V_T5AIDAC1(x) ((x) << S_T5AIDAC1)
64383 #define G_T5AIDAC1(x) (((x) >> S_T5AIDAC1) & M_T5AIDAC1)
64384 
64385 #define A_MAC_PORT_TX_LINKA_TRANSMIT_2X_SEGMENT_APPLIED 0x3064
64386 
64387 #define S_AS2X3    6
64388 #define M_AS2X3    0x3U
64389 #define V_AS2X3(x) ((x) << S_AS2X3)
64390 #define G_AS2X3(x) (((x) >> S_AS2X3) & M_AS2X3)
64391 
64392 #define S_AS2X2    4
64393 #define M_AS2X2    0x3U
64394 #define V_AS2X2(x) ((x) << S_AS2X2)
64395 #define G_AS2X2(x) (((x) >> S_AS2X2) & M_AS2X2)
64396 
64397 #define S_AS2X1    2
64398 #define M_AS2X1    0x3U
64399 #define V_AS2X1(x) ((x) << S_AS2X1)
64400 #define G_AS2X1(x) (((x) >> S_AS2X1) & M_AS2X1)
64401 
64402 #define S_AS2X0    0
64403 #define M_AS2X0    0x3U
64404 #define V_AS2X0(x) ((x) << S_AS2X0)
64405 #define G_AS2X0(x) (((x) >> S_AS2X0) & M_AS2X0)
64406 
64407 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3068
64408 #define A_MAC_PORT_TX_LINKA_TRANSMIT_1X_SEGMENT_APPLIED 0x3068
64409 
64410 #define S_AS1X7    14
64411 #define M_AS1X7    0x3U
64412 #define V_AS1X7(x) ((x) << S_AS1X7)
64413 #define G_AS1X7(x) (((x) >> S_AS1X7) & M_AS1X7)
64414 
64415 #define S_AS1X6    12
64416 #define M_AS1X6    0x3U
64417 #define V_AS1X6(x) ((x) << S_AS1X6)
64418 #define G_AS1X6(x) (((x) >> S_AS1X6) & M_AS1X6)
64419 
64420 #define S_AS1X5    10
64421 #define M_AS1X5    0x3U
64422 #define V_AS1X5(x) ((x) << S_AS1X5)
64423 #define G_AS1X5(x) (((x) >> S_AS1X5) & M_AS1X5)
64424 
64425 #define S_AS1X4    8
64426 #define M_AS1X4    0x3U
64427 #define V_AS1X4(x) ((x) << S_AS1X4)
64428 #define G_AS1X4(x) (((x) >> S_AS1X4) & M_AS1X4)
64429 
64430 #define S_AS1X3    6
64431 #define M_AS1X3    0x3U
64432 #define V_AS1X3(x) ((x) << S_AS1X3)
64433 #define G_AS1X3(x) (((x) >> S_AS1X3) & M_AS1X3)
64434 
64435 #define S_AS1X2    4
64436 #define M_AS1X2    0x3U
64437 #define V_AS1X2(x) ((x) << S_AS1X2)
64438 #define G_AS1X2(x) (((x) >> S_AS1X2) & M_AS1X2)
64439 
64440 #define S_AS1X1    2
64441 #define M_AS1X1    0x3U
64442 #define V_AS1X1(x) ((x) << S_AS1X1)
64443 #define G_AS1X1(x) (((x) >> S_AS1X1) & M_AS1X1)
64444 
64445 #define S_AS1X0    0
64446 #define M_AS1X0    0x3U
64447 #define V_AS1X0(x) ((x) << S_AS1X0)
64448 #define G_AS1X0(x) (((x) >> S_AS1X0) & M_AS1X0)
64449 
64450 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x306c
64451 
64452 #define S_AT4X    0
64453 #define M_AT4X    0xffU
64454 #define V_AT4X(x) ((x) << S_AT4X)
64455 #define G_AT4X(x) (((x) >> S_AT4X) & M_AT4X)
64456 
64457 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3070
64458 
64459 #define S_MAINSC    6
64460 #define M_MAINSC    0x3fU
64461 #define V_MAINSC(x) ((x) << S_MAINSC)
64462 #define G_MAINSC(x) (((x) >> S_MAINSC) & M_MAINSC)
64463 
64464 #define S_POSTSC    0
64465 #define M_POSTSC    0x3fU
64466 #define V_POSTSC(x) ((x) << S_POSTSC)
64467 #define G_POSTSC(x) (((x) >> S_POSTSC) & M_POSTSC)
64468 
64469 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3070
64470 
64471 #define S_AT2X    8
64472 #define M_AT2X    0xfU
64473 #define V_AT2X(x) ((x) << S_AT2X)
64474 #define G_AT2X(x) (((x) >> S_AT2X) & M_AT2X)
64475 
64476 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3074
64477 
64478 #define S_PRESC    0
64479 #define M_PRESC    0x1fU
64480 #define V_PRESC(x) ((x) << S_PRESC)
64481 #define G_PRESC(x) (((x) >> S_PRESC) & M_PRESC)
64482 
64483 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3074
64484 
64485 #define S_ATSIGN    0
64486 #define M_ATSIGN    0xfU
64487 #define V_ATSIGN(x) ((x) << S_ATSIGN)
64488 #define G_ATSIGN(x) (((x) >> S_ATSIGN) & M_ATSIGN)
64489 
64490 #define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3078
64491 #define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x307c
64492 
64493 #define S_T5XADDR    1
64494 #define M_T5XADDR    0x1fU
64495 #define V_T5XADDR(x) ((x) << S_T5XADDR)
64496 #define G_T5XADDR(x) (((x) >> S_T5XADDR) & M_T5XADDR)
64497 
64498 #define S_T5XWR    0
64499 #define V_T5XWR(x) ((x) << S_T5XWR)
64500 #define F_T5XWR    V_T5XWR(1U)
64501 
64502 #define S_T6_XADDR    1
64503 #define M_T6_XADDR    0x1fU
64504 #define V_T6_XADDR(x) ((x) << S_T6_XADDR)
64505 #define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
64506 
64507 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3080
64508 
64509 #define S_XDAT10    0
64510 #define M_XDAT10    0xffffU
64511 #define V_XDAT10(x) ((x) << S_XDAT10)
64512 #define G_XDAT10(x) (((x) >> S_XDAT10) & M_XDAT10)
64513 
64514 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3084
64515 
64516 #define S_XDAT32    0
64517 #define M_XDAT32    0xffffU
64518 #define V_XDAT32(x) ((x) << S_XDAT32)
64519 #define G_XDAT32(x) (((x) >> S_XDAT32) & M_XDAT32)
64520 
64521 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3088
64522 
64523 #define S_XDAT4    0
64524 #define M_XDAT4    0xffU
64525 #define V_XDAT4(x) ((x) << S_XDAT4)
64526 #define G_XDAT4(x) (((x) >> S_XDAT4) & M_XDAT4)
64527 
64528 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3088
64529 
64530 #define S_XDAT54    0
64531 #define M_XDAT54    0xffffU
64532 #define V_XDAT54(x) ((x) << S_XDAT54)
64533 #define G_XDAT54(x) (((x) >> S_XDAT54) & M_XDAT54)
64534 
64535 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL 0x308c
64536 
64537 #define S_DCCTIMEDOUT    15
64538 #define V_DCCTIMEDOUT(x) ((x) << S_DCCTIMEDOUT)
64539 #define F_DCCTIMEDOUT    V_DCCTIMEDOUT(1U)
64540 
64541 #define S_DCCTIMEEN    14
64542 #define V_DCCTIMEEN(x) ((x) << S_DCCTIMEEN)
64543 #define F_DCCTIMEEN    V_DCCTIMEEN(1U)
64544 
64545 #define S_DCCLOCK    13
64546 #define V_DCCLOCK(x) ((x) << S_DCCLOCK)
64547 #define F_DCCLOCK    V_DCCLOCK(1U)
64548 
64549 #define S_DCCOFFSET    8
64550 #define M_DCCOFFSET    0x1fU
64551 #define V_DCCOFFSET(x) ((x) << S_DCCOFFSET)
64552 #define G_DCCOFFSET(x) (((x) >> S_DCCOFFSET) & M_DCCOFFSET)
64553 
64554 #define S_DCCSTEP    6
64555 #define M_DCCSTEP    0x3U
64556 #define V_DCCSTEP(x) ((x) << S_DCCSTEP)
64557 #define G_DCCSTEP(x) (((x) >> S_DCCSTEP) & M_DCCSTEP)
64558 
64559 #define S_DCCASTEP    1
64560 #define M_DCCASTEP    0x1fU
64561 #define V_DCCASTEP(x) ((x) << S_DCCASTEP)
64562 #define G_DCCASTEP(x) (((x) >> S_DCCASTEP) & M_DCCASTEP)
64563 
64564 #define S_DCCAEN    0
64565 #define V_DCCAEN(x) ((x) << S_DCCAEN)
64566 #define F_DCCAEN    V_DCCAEN(1U)
64567 
64568 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x308c
64569 
64570 #define S_XDAT76    0
64571 #define M_XDAT76    0xffffU
64572 #define V_XDAT76(x) ((x) << S_XDAT76)
64573 #define G_XDAT76(x) (((x) >> S_XDAT76) & M_XDAT76)
64574 
64575 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE 0x3090
64576 
64577 #define S_DCCOUT    12
64578 #define V_DCCOUT(x) ((x) << S_DCCOUT)
64579 #define F_DCCOUT    V_DCCOUT(1U)
64580 
64581 #define S_DCCCLK    11
64582 #define V_DCCCLK(x) ((x) << S_DCCCLK)
64583 #define F_DCCCLK    V_DCCCLK(1U)
64584 
64585 #define S_DCCHOLD    10
64586 #define V_DCCHOLD(x) ((x) << S_DCCHOLD)
64587 #define F_DCCHOLD    V_DCCHOLD(1U)
64588 
64589 #define S_DCCSIGN    8
64590 #define M_DCCSIGN    0x3U
64591 #define V_DCCSIGN(x) ((x) << S_DCCSIGN)
64592 #define G_DCCSIGN(x) (((x) >> S_DCCSIGN) & M_DCCSIGN)
64593 
64594 #define S_DCCAMP    1
64595 #define M_DCCAMP    0x7fU
64596 #define V_DCCAMP(x) ((x) << S_DCCAMP)
64597 #define G_DCCAMP(x) (((x) >> S_DCCAMP) & M_DCCAMP)
64598 
64599 #define S_DCCOEN    0
64600 #define V_DCCOEN(x) ((x) << S_DCCOEN)
64601 #define F_DCCOEN    V_DCCOEN(1U)
64602 
64603 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED 0x3094
64604 
64605 #define S_DCCASIGN    7
64606 #define M_DCCASIGN    0x3U
64607 #define V_DCCASIGN(x) ((x) << S_DCCASIGN)
64608 #define G_DCCASIGN(x) (((x) >> S_DCCASIGN) & M_DCCASIGN)
64609 
64610 #define S_DCCAAMP    0
64611 #define M_DCCAAMP    0x7fU
64612 #define V_DCCAAMP(x) ((x) << S_DCCAAMP)
64613 #define G_DCCAAMP(x) (((x) >> S_DCCAAMP) & M_DCCAAMP)
64614 
64615 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT 0x3098
64616 
64617 #define S_DCCTIMEOUTVAL    0
64618 #define M_DCCTIMEOUTVAL    0xffffU
64619 #define V_DCCTIMEOUTVAL(x) ((x) << S_DCCTIMEOUTVAL)
64620 #define G_DCCTIMEOUTVAL(x) (((x) >> S_DCCTIMEOUTVAL) & M_DCCTIMEOUTVAL)
64621 
64622 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL 0x309c
64623 
64624 #define S_LPIDCLK    4
64625 #define V_LPIDCLK(x) ((x) << S_LPIDCLK)
64626 #define F_LPIDCLK    V_LPIDCLK(1U)
64627 
64628 #define S_LPITERM    2
64629 #define M_LPITERM    0x3U
64630 #define V_LPITERM(x) ((x) << S_LPITERM)
64631 #define G_LPITERM(x) (((x) >> S_LPITERM) & M_LPITERM)
64632 
64633 #define S_LPIPRCD    0
64634 #define M_LPIPRCD    0x3U
64635 #define V_LPIPRCD(x) ((x) << S_LPIPRCD)
64636 #define G_LPIPRCD(x) (((x) >> S_LPIPRCD) & M_LPIPRCD)
64637 
64638 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL 0x30a0
64639 
64640 #define S_T6_DCCTIMEEN    13
64641 #define M_T6_DCCTIMEEN    0x3U
64642 #define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
64643 #define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
64644 
64645 #define S_T6_DCCLOCK    11
64646 #define M_T6_DCCLOCK    0x3U
64647 #define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
64648 #define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
64649 
64650 #define S_T6_DCCOFFSET    8
64651 #define M_T6_DCCOFFSET    0x7U
64652 #define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
64653 #define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
64654 
64655 #define S_TX_LINKA_DCCSTEP_CTL    6
64656 #define M_TX_LINKA_DCCSTEP_CTL    0x3U
64657 #define V_TX_LINKA_DCCSTEP_CTL(x) ((x) << S_TX_LINKA_DCCSTEP_CTL)
64658 #define G_TX_LINKA_DCCSTEP_CTL(x) (((x) >> S_TX_LINKA_DCCSTEP_CTL) & M_TX_LINKA_DCCSTEP_CTL)
64659 
64660 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE 0x30a4
64661 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED 0x30a8
64662 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT 0x30ac
64663 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_OVERRIDE 0x30c0
64664 
64665 #define S_OSIGN    0
64666 #define M_OSIGN    0xfU
64667 #define V_OSIGN(x) ((x) << S_OSIGN)
64668 #define G_OSIGN(x) (((x) >> S_OSIGN) & M_OSIGN)
64669 
64670 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_OVERRIDE 0x30c8
64671 
64672 #define S_OS4X7    14
64673 #define M_OS4X7    0x3U
64674 #define V_OS4X7(x) ((x) << S_OS4X7)
64675 #define G_OS4X7(x) (((x) >> S_OS4X7) & M_OS4X7)
64676 
64677 #define S_OS4X6    12
64678 #define M_OS4X6    0x3U
64679 #define V_OS4X6(x) ((x) << S_OS4X6)
64680 #define G_OS4X6(x) (((x) >> S_OS4X6) & M_OS4X6)
64681 
64682 #define S_OS4X5    10
64683 #define M_OS4X5    0x3U
64684 #define V_OS4X5(x) ((x) << S_OS4X5)
64685 #define G_OS4X5(x) (((x) >> S_OS4X5) & M_OS4X5)
64686 
64687 #define S_OS4X4    8
64688 #define M_OS4X4    0x3U
64689 #define V_OS4X4(x) ((x) << S_OS4X4)
64690 #define G_OS4X4(x) (((x) >> S_OS4X4) & M_OS4X4)
64691 
64692 #define S_OS4X3    6
64693 #define M_OS4X3    0x3U
64694 #define V_OS4X3(x) ((x) << S_OS4X3)
64695 #define G_OS4X3(x) (((x) >> S_OS4X3) & M_OS4X3)
64696 
64697 #define S_OS4X2    4
64698 #define M_OS4X2    0x3U
64699 #define V_OS4X2(x) ((x) << S_OS4X2)
64700 #define G_OS4X2(x) (((x) >> S_OS4X2) & M_OS4X2)
64701 
64702 #define S_OS4X1    2
64703 #define M_OS4X1    0x3U
64704 #define V_OS4X1(x) ((x) << S_OS4X1)
64705 #define G_OS4X1(x) (((x) >> S_OS4X1) & M_OS4X1)
64706 
64707 #define S_OS4X0    0
64708 #define M_OS4X0    0x3U
64709 #define V_OS4X0(x) ((x) << S_OS4X0)
64710 #define G_OS4X0(x) (((x) >> S_OS4X0) & M_OS4X0)
64711 
64712 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X_OVERRIDE 0x30cc
64713 
64714 #define S_OS2X3    6
64715 #define M_OS2X3    0x3U
64716 #define V_OS2X3(x) ((x) << S_OS2X3)
64717 #define G_OS2X3(x) (((x) >> S_OS2X3) & M_OS2X3)
64718 
64719 #define S_OS2X2    4
64720 #define M_OS2X2    0x3U
64721 #define V_OS2X2(x) ((x) << S_OS2X2)
64722 #define G_OS2X2(x) (((x) >> S_OS2X2) & M_OS2X2)
64723 
64724 #define S_OS2X1    2
64725 #define M_OS2X1    0x3U
64726 #define V_OS2X1(x) ((x) << S_OS2X1)
64727 #define G_OS2X1(x) (((x) >> S_OS2X1) & M_OS2X1)
64728 
64729 #define S_OS2X0    0
64730 #define M_OS2X0    0x3U
64731 #define V_OS2X0(x) ((x) << S_OS2X0)
64732 #define G_OS2X0(x) (((x) >> S_OS2X0) & M_OS2X0)
64733 
64734 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_1X_OVERRIDE 0x30d0
64735 
64736 #define S_OS1X7    14
64737 #define M_OS1X7    0x3U
64738 #define V_OS1X7(x) ((x) << S_OS1X7)
64739 #define G_OS1X7(x) (((x) >> S_OS1X7) & M_OS1X7)
64740 
64741 #define S_OS1X6    12
64742 #define M_OS1X6    0x3U
64743 #define V_OS1X6(x) ((x) << S_OS1X6)
64744 #define G_OS1X6(x) (((x) >> S_OS1X6) & M_OS1X6)
64745 
64746 #define S_OS1X5    10
64747 #define M_OS1X5    0x3U
64748 #define V_OS1X5(x) ((x) << S_OS1X5)
64749 #define G_OS1X5(x) (((x) >> S_OS1X5) & M_OS1X5)
64750 
64751 #define S_OS1X4    8
64752 #define M_OS1X4    0x3U
64753 #define V_OS1X4(x) ((x) << S_OS1X4)
64754 #define G_OS1X4(x) (((x) >> S_OS1X4) & M_OS1X4)
64755 
64756 #define S_OS1X3    6
64757 #define M_OS1X3    0x3U
64758 #define V_OS1X3(x) ((x) << S_OS1X3)
64759 #define G_OS1X3(x) (((x) >> S_OS1X3) & M_OS1X3)
64760 
64761 #define S_OS1X2    4
64762 #define M_OS1X2    0x3U
64763 #define V_OS1X2(x) ((x) << S_OS1X2)
64764 #define G_OS1X2(x) (((x) >> S_OS1X2) & M_OS1X2)
64765 
64766 #define S_OS1X1    2
64767 #define M_OS1X1    0x3U
64768 #define V_OS1X1(x) ((x) << S_OS1X1)
64769 #define G_OS1X1(x) (((x) >> S_OS1X1) & M_OS1X1)
64770 
64771 #define S_OS1X0    0
64772 #define M_OS1X0    0x3U
64773 #define V_OS1X0(x) ((x) << S_OS1X0)
64774 #define G_OS1X0(x) (((x) >> S_OS1X0) & M_OS1X0)
64775 
64776 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x30d8
64777 
64778 #define S_OT4X    0
64779 #define M_OT4X    0xffU
64780 #define V_OT4X(x) ((x) << S_OT4X)
64781 #define G_OT4X(x) (((x) >> S_OT4X) & M_OT4X)
64782 
64783 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x30dc
64784 
64785 #define S_OT2X    0
64786 #define M_OT2X    0xfU
64787 #define V_OT2X(x) ((x) << S_OT2X)
64788 #define G_OT2X(x) (((x) >> S_OT2X) & M_OT2X)
64789 
64790 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x30e0
64791 
64792 #define S_OT1X    0
64793 #define M_OT1X    0xffU
64794 #define V_OT1X(x) ((x) << S_OT1X)
64795 #define G_OT1X(x) (((x) >> S_OT1X) & M_OT1X)
64796 
64797 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_5 0x30ec
64798 
64799 #define S_ERRORP    15
64800 #define V_ERRORP(x) ((x) << S_ERRORP)
64801 #define F_ERRORP    V_ERRORP(1U)
64802 
64803 #define S_ERRORN    14
64804 #define V_ERRORN(x) ((x) << S_ERRORN)
64805 #define F_ERRORN    V_ERRORN(1U)
64806 
64807 #define S_TESTENA    13
64808 #define V_TESTENA(x) ((x) << S_TESTENA)
64809 #define F_TESTENA    V_TESTENA(1U)
64810 
64811 #define S_TUNEBIT    10
64812 #define M_TUNEBIT    0x7U
64813 #define V_TUNEBIT(x) ((x) << S_TUNEBIT)
64814 #define G_TUNEBIT(x) (((x) >> S_TUNEBIT) & M_TUNEBIT)
64815 
64816 #define S_DATAPOS    8
64817 #define M_DATAPOS    0x3U
64818 #define V_DATAPOS(x) ((x) << S_DATAPOS)
64819 #define G_DATAPOS(x) (((x) >> S_DATAPOS) & M_DATAPOS)
64820 
64821 #define S_SEGSEL    3
64822 #define M_SEGSEL    0x1fU
64823 #define V_SEGSEL(x) ((x) << S_SEGSEL)
64824 #define G_SEGSEL(x) (((x) >> S_SEGSEL) & M_SEGSEL)
64825 
64826 #define S_TAPSEL    1
64827 #define M_TAPSEL    0x3U
64828 #define V_TAPSEL(x) ((x) << S_TAPSEL)
64829 #define G_TAPSEL(x) (((x) >> S_TAPSEL) & M_TAPSEL)
64830 
64831 #define S_DATASIGN    0
64832 #define V_DATASIGN(x) ((x) << S_DATASIGN)
64833 #define F_DATASIGN    V_DATASIGN(1U)
64834 
64835 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4 0x30f0
64836 
64837 #define S_SDOVRDEN    8
64838 #define V_SDOVRDEN(x) ((x) << S_SDOVRDEN)
64839 #define F_SDOVRDEN    V_SDOVRDEN(1U)
64840 
64841 #define S_SDOVRD    0
64842 #define M_SDOVRD    0xffU
64843 #define V_SDOVRD(x) ((x) << S_SDOVRD)
64844 #define G_SDOVRD(x) (((x) >> S_SDOVRD) & M_SDOVRD)
64845 
64846 #define S_T6_SDOVRD    0
64847 #define M_T6_SDOVRD    0xffffU
64848 #define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
64849 #define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
64850 
64851 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3 0x30f4
64852 
64853 #define S_SLEWCODE    1
64854 #define M_SLEWCODE    0x3U
64855 #define V_SLEWCODE(x) ((x) << S_SLEWCODE)
64856 #define G_SLEWCODE(x) (((x) >> S_SLEWCODE) & M_SLEWCODE)
64857 
64858 #define S_ASEGEN    0
64859 #define V_ASEGEN(x) ((x) << S_ASEGEN)
64860 #define F_ASEGEN    V_ASEGEN(1U)
64861 
64862 #define S_WCNT    0
64863 #define M_WCNT    0x3ffU
64864 #define V_WCNT(x) ((x) << S_WCNT)
64865 #define G_WCNT(x) (((x) >> S_WCNT) & M_WCNT)
64866 
64867 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2 0x30f8
64868 
64869 #define S_AECMDVAL    14
64870 #define V_AECMDVAL(x) ((x) << S_AECMDVAL)
64871 #define F_AECMDVAL    V_AECMDVAL(1U)
64872 
64873 #define S_AECMD1312    12
64874 #define M_AECMD1312    0x3U
64875 #define V_AECMD1312(x) ((x) << S_AECMD1312)
64876 #define G_AECMD1312(x) (((x) >> S_AECMD1312) & M_AECMD1312)
64877 
64878 #define S_AECMD70    0
64879 #define M_AECMD70    0xffU
64880 #define V_AECMD70(x) ((x) << S_AECMD70)
64881 #define G_AECMD70(x) (((x) >> S_AECMD70) & M_AECMD70)
64882 
64883 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1 0x30fc
64884 
64885 #define S_C48DIVCTL    12
64886 #define M_C48DIVCTL    0x7U
64887 #define V_C48DIVCTL(x) ((x) << S_C48DIVCTL)
64888 #define G_C48DIVCTL(x) (((x) >> S_C48DIVCTL) & M_C48DIVCTL)
64889 
64890 #define S_RATEDIVCTL    9
64891 #define M_RATEDIVCTL    0x7U
64892 #define V_RATEDIVCTL(x) ((x) << S_RATEDIVCTL)
64893 #define G_RATEDIVCTL(x) (((x) >> S_RATEDIVCTL) & M_RATEDIVCTL)
64894 
64895 #define S_ANLGFLSH    8
64896 #define V_ANLGFLSH(x) ((x) << S_ANLGFLSH)
64897 #define F_ANLGFLSH    V_ANLGFLSH(1U)
64898 
64899 #define S_DCCTSTOUT    7
64900 #define V_DCCTSTOUT(x) ((x) << S_DCCTSTOUT)
64901 #define F_DCCTSTOUT    V_DCCTSTOUT(1U)
64902 
64903 #define S_BSOUT    6
64904 #define V_BSOUT(x) ((x) << S_BSOUT)
64905 #define F_BSOUT    V_BSOUT(1U)
64906 
64907 #define S_BSIN    5
64908 #define V_BSIN(x) ((x) << S_BSIN)
64909 #define F_BSIN    V_BSIN(1U)
64910 
64911 #define S_JTAGAMPL    3
64912 #define M_JTAGAMPL    0x3U
64913 #define V_JTAGAMPL(x) ((x) << S_JTAGAMPL)
64914 #define G_JTAGAMPL(x) (((x) >> S_JTAGAMPL) & M_JTAGAMPL)
64915 
64916 #define S_JTAGTS    2
64917 #define V_JTAGTS(x) ((x) << S_JTAGTS)
64918 #define F_JTAGTS    V_JTAGTS(1U)
64919 
64920 #define S_TS    1
64921 #define V_TS(x) ((x) << S_TS)
64922 #define F_TS    V_TS(1U)
64923 
64924 #define S_OBS    0
64925 #define V_OBS(x) ((x) << S_OBS)
64926 #define F_OBS    V_OBS(1U)
64927 
64928 #define S_T6_SDOVRDEN    15
64929 #define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
64930 #define F_T6_SDOVRDEN    V_T6_SDOVRDEN(1U)
64931 
64932 #define S_BSOUTN    7
64933 #define V_BSOUTN(x) ((x) << S_BSOUTN)
64934 #define F_BSOUTN    V_BSOUTN(1U)
64935 
64936 #define S_BSOUTP    6
64937 #define V_BSOUTP(x) ((x) << S_BSOUTP)
64938 #define F_BSOUTP    V_BSOUTP(1U)
64939 
64940 #define A_MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE 0x3100
64941 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL 0x3104
64942 #define A_MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL 0x3108
64943 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL 0x310c
64944 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3110
64945 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3114
64946 #define A_MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3118
64947 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x311c
64948 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT 0x3120
64949 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT 0x3124
64950 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT 0x3128
64951 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_3_COEFFICIENT 0x312c
64952 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE 0x3130
64953 #define A_MAC_PORT_TX_LINKB_TRANSMIT_POLARITY 0x3134
64954 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3138
64955 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x313c
64956 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3140
64957 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3140
64958 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3144
64959 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3144
64960 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3148
64961 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3148
64962 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x314c
64963 #define A_MAC_PORT_TX_LINKB_TRANSMIT_APPLIED_TUNE_REGISTER 0x3150
64964 #define A_MAC_PORT_TX_LINKB_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3158
64965 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3160
64966 #define A_MAC_PORT_TX_LINKB_TRANSMIT_4X_SEGMENT_APPLIED 0x3160
64967 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3164
64968 #define A_MAC_PORT_TX_LINKB_TRANSMIT_2X_SEGMENT_APPLIED 0x3164
64969 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3168
64970 #define A_MAC_PORT_TX_LINKB_TRANSMIT_1X_SEGMENT_APPLIED 0x3168
64971 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x316c
64972 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3170
64973 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3170
64974 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3174
64975 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3174
64976 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3178
64977 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x317c
64978 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3180
64979 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3184
64980 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3188
64981 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3188
64982 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x318c
64983 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x318c
64984 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE 0x3190
64985 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED 0x3194
64986 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT 0x3198
64987 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL 0x319c
64988 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x31a0
64989 
64990 #define S_TX_LINKB_DCCSTEP_CTL    6
64991 #define M_TX_LINKB_DCCSTEP_CTL    0x3U
64992 #define V_TX_LINKB_DCCSTEP_CTL(x) ((x) << S_TX_LINKB_DCCSTEP_CTL)
64993 #define G_TX_LINKB_DCCSTEP_CTL(x) (((x) >> S_TX_LINKB_DCCSTEP_CTL) & M_TX_LINKB_DCCSTEP_CTL)
64994 
64995 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE 0x31a4
64996 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED 0x31a8
64997 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT 0x31ac
64998 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_OVERRIDE 0x31c0
64999 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_OVERRIDE 0x31c8
65000 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X_OVERRIDE 0x31cc
65001 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_1X_OVERRIDE 0x31d0
65002 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x31d8
65003 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x31dc
65004 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x31e0
65005 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_5 0x31ec
65006 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4 0x31f0
65007 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3 0x31f4
65008 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2 0x31f8
65009 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1 0x31fc
65010 #define A_MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE 0x3200
65011 
65012 #define S_T5_RX_LINKEN    15
65013 #define V_T5_RX_LINKEN(x) ((x) << S_T5_RX_LINKEN)
65014 #define F_T5_RX_LINKEN    V_T5_RX_LINKEN(1U)
65015 
65016 #define S_T5_RX_LINKRST    14
65017 #define V_T5_RX_LINKRST(x) ((x) << S_T5_RX_LINKRST)
65018 #define F_T5_RX_LINKRST    V_T5_RX_LINKRST(1U)
65019 
65020 #define S_T5_RX_CFGWRT    13
65021 #define V_T5_RX_CFGWRT(x) ((x) << S_T5_RX_CFGWRT)
65022 #define F_T5_RX_CFGWRT    V_T5_RX_CFGWRT(1U)
65023 
65024 #define S_T5_RX_CFGPTR    11
65025 #define M_T5_RX_CFGPTR    0x3U
65026 #define V_T5_RX_CFGPTR(x) ((x) << S_T5_RX_CFGPTR)
65027 #define G_T5_RX_CFGPTR(x) (((x) >> S_T5_RX_CFGPTR) & M_T5_RX_CFGPTR)
65028 
65029 #define S_T5_RX_CFGEXT    10
65030 #define V_T5_RX_CFGEXT(x) ((x) << S_T5_RX_CFGEXT)
65031 #define F_T5_RX_CFGEXT    V_T5_RX_CFGEXT(1U)
65032 
65033 #define S_T5_RX_CFGACT    9
65034 #define V_T5_RX_CFGACT(x) ((x) << S_T5_RX_CFGACT)
65035 #define F_T5_RX_CFGACT    V_T5_RX_CFGACT(1U)
65036 
65037 #define S_T5_RX_AUXCLK    8
65038 #define V_T5_RX_AUXCLK(x) ((x) << S_T5_RX_AUXCLK)
65039 #define F_T5_RX_AUXCLK    V_T5_RX_AUXCLK(1U)
65040 
65041 #define S_T5_RX_PLLSEL    6
65042 #define M_T5_RX_PLLSEL    0x3U
65043 #define V_T5_RX_PLLSEL(x) ((x) << S_T5_RX_PLLSEL)
65044 #define G_T5_RX_PLLSEL(x) (((x) >> S_T5_RX_PLLSEL) & M_T5_RX_PLLSEL)
65045 
65046 #define S_T5_RX_DMSEL    4
65047 #define M_T5_RX_DMSEL    0x3U
65048 #define V_T5_RX_DMSEL(x) ((x) << S_T5_RX_DMSEL)
65049 #define G_T5_RX_DMSEL(x) (((x) >> S_T5_RX_DMSEL) & M_T5_RX_DMSEL)
65050 
65051 #define S_T5_RX_BWSEL    2
65052 #define M_T5_RX_BWSEL    0x3U
65053 #define V_T5_RX_BWSEL(x) ((x) << S_T5_RX_BWSEL)
65054 #define G_T5_RX_BWSEL(x) (((x) >> S_T5_RX_BWSEL) & M_T5_RX_BWSEL)
65055 
65056 #define S_T5_RX_RTSEL    0
65057 #define M_T5_RX_RTSEL    0x3U
65058 #define V_T5_RX_RTSEL(x) ((x) << S_T5_RX_RTSEL)
65059 #define G_T5_RX_RTSEL(x) (((x) >> S_T5_RX_RTSEL) & M_T5_RX_RTSEL)
65060 
65061 #define S_T5_RX_MODE8023AZ    8
65062 #define V_T5_RX_MODE8023AZ(x) ((x) << S_T5_RX_MODE8023AZ)
65063 #define F_T5_RX_MODE8023AZ    V_T5_RX_MODE8023AZ(1U)
65064 
65065 #define A_MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL 0x3204
65066 
65067 #define S_FERRST    10
65068 #define V_FERRST(x) ((x) << S_FERRST)
65069 #define F_FERRST    V_FERRST(1U)
65070 
65071 #define S_ERRST    9
65072 #define V_ERRST(x) ((x) << S_ERRST)
65073 #define F_ERRST    V_ERRST(1U)
65074 
65075 #define S_SYNCST    8
65076 #define V_SYNCST(x) ((x) << S_SYNCST)
65077 #define F_SYNCST    V_SYNCST(1U)
65078 
65079 #define S_WRPSM    7
65080 #define V_WRPSM(x) ((x) << S_WRPSM)
65081 #define F_WRPSM    V_WRPSM(1U)
65082 
65083 #define S_WPLPEN    6
65084 #define V_WPLPEN(x) ((x) << S_WPLPEN)
65085 #define F_WPLPEN    V_WPLPEN(1U)
65086 
65087 #define S_WRPMD    5
65088 #define V_WRPMD(x) ((x) << S_WRPMD)
65089 #define F_WRPMD    V_WRPMD(1U)
65090 
65091 #define S_PATSEL    0
65092 #define M_PATSEL    0x7U
65093 #define V_PATSEL(x) ((x) << S_PATSEL)
65094 #define G_PATSEL(x) (((x) >> S_PATSEL) & M_PATSEL)
65095 
65096 #define S_APLYDCD    15
65097 #define V_APLYDCD(x) ((x) << S_APLYDCD)
65098 #define F_APLYDCD    V_APLYDCD(1U)
65099 
65100 #define S_PPOL    13
65101 #define M_PPOL    0x3U
65102 #define V_PPOL(x) ((x) << S_PPOL)
65103 #define G_PPOL(x) (((x) >> S_PPOL) & M_PPOL)
65104 
65105 #define S_PCLKSEL    11
65106 #define M_PCLKSEL    0x3U
65107 #define V_PCLKSEL(x) ((x) << S_PCLKSEL)
65108 #define G_PCLKSEL(x) (((x) >> S_PCLKSEL) & M_PCLKSEL)
65109 
65110 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL 0x3208
65111 
65112 #define S_RSTUCK    3
65113 #define V_RSTUCK(x) ((x) << S_RSTUCK)
65114 #define F_RSTUCK    V_RSTUCK(1U)
65115 
65116 #define S_FRZFW    2
65117 #define V_FRZFW(x) ((x) << S_FRZFW)
65118 #define F_FRZFW    V_FRZFW(1U)
65119 
65120 #define S_RSTFW    1
65121 #define V_RSTFW(x) ((x) << S_RSTFW)
65122 #define F_RSTFW    V_RSTFW(1U)
65123 
65124 #define S_SSCEN    0
65125 #define V_SSCEN(x) ((x) << S_SSCEN)
65126 #define F_SSCEN    V_SSCEN(1U)
65127 
65128 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL 0x320c
65129 
65130 #define S_H1ANOFST    12
65131 #define M_H1ANOFST    0xfU
65132 #define V_H1ANOFST(x) ((x) << S_H1ANOFST)
65133 #define G_H1ANOFST(x) (((x) >> S_H1ANOFST) & M_H1ANOFST)
65134 
65135 #define S_T6_TMSCAL    8
65136 #define M_T6_TMSCAL    0x3U
65137 #define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
65138 #define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
65139 
65140 #define S_T6_APADJ    7
65141 #define V_T6_APADJ(x) ((x) << S_T6_APADJ)
65142 #define F_T6_APADJ    V_T6_APADJ(1U)
65143 
65144 #define S_T6_RSEL    6
65145 #define V_T6_RSEL(x) ((x) << S_T6_RSEL)
65146 #define F_T6_RSEL    V_T6_RSEL(1U)
65147 
65148 #define S_T6_PHOFFS    0
65149 #define M_T6_PHOFFS    0x3fU
65150 #define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
65151 #define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
65152 
65153 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1 0x3210
65154 
65155 #define S_ROT00    0
65156 #define M_ROT00    0x3fU
65157 #define V_ROT00(x) ((x) << S_ROT00)
65158 #define G_ROT00(x) (((x) >> S_ROT00) & M_ROT00)
65159 
65160 #define S_ROTA    8
65161 #define M_ROTA    0x3fU
65162 #define V_ROTA(x) ((x) << S_ROTA)
65163 #define G_ROTA(x) (((x) >> S_ROTA) & M_ROTA)
65164 
65165 #define S_ROTD    0
65166 #define M_ROTD    0x3fU
65167 #define V_ROTD(x) ((x) << S_ROTD)
65168 #define G_ROTD(x) (((x) >> S_ROTD) & M_ROTD)
65169 
65170 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2 0x3214
65171 
65172 #define S_FREQFW    8
65173 #define M_FREQFW    0xffU
65174 #define V_FREQFW(x) ((x) << S_FREQFW)
65175 #define G_FREQFW(x) (((x) >> S_FREQFW) & M_FREQFW)
65176 
65177 #define S_FWSNAP    7
65178 #define V_FWSNAP(x) ((x) << S_FWSNAP)
65179 #define F_FWSNAP    V_FWSNAP(1U)
65180 
65181 #define S_ROTE    0
65182 #define M_ROTE    0x3fU
65183 #define V_ROTE(x) ((x) << S_ROTE)
65184 #define G_ROTE(x) (((x) >> S_ROTE) & M_ROTE)
65185 
65186 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3218
65187 
65188 #define S_RAOFFF    8
65189 #define M_RAOFFF    0xfU
65190 #define V_RAOFFF(x) ((x) << S_RAOFFF)
65191 #define G_RAOFFF(x) (((x) >> S_RAOFFF) & M_RAOFFF)
65192 
65193 #define S_RAOFF    0
65194 #define M_RAOFF    0x1fU
65195 #define V_RAOFF(x) ((x) << S_RAOFF)
65196 #define G_RAOFF(x) (((x) >> S_RAOFF) & M_RAOFF)
65197 
65198 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x321c
65199 
65200 #define S_RBOOFF    10
65201 #define M_RBOOFF    0x1fU
65202 #define V_RBOOFF(x) ((x) << S_RBOOFF)
65203 #define G_RBOOFF(x) (((x) >> S_RBOOFF) & M_RBOOFF)
65204 
65205 #define S_RBEOFF    5
65206 #define M_RBEOFF    0x1fU
65207 #define V_RBEOFF(x) ((x) << S_RBEOFF)
65208 #define G_RBEOFF(x) (((x) >> S_RBEOFF) & M_RBEOFF)
65209 
65210 #define A_MAC_PORT_RX_LINKA_DFE_CONTROL 0x3220
65211 
65212 #define S_T6_SPIFMT    8
65213 #define M_T6_SPIFMT    0xfU
65214 #define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
65215 #define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
65216 
65217 #define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1 0x3224
65218 
65219 #define S_T5BYTE1    8
65220 #define M_T5BYTE1    0xffU
65221 #define V_T5BYTE1(x) ((x) << S_T5BYTE1)
65222 #define G_T5BYTE1(x) (((x) >> S_T5BYTE1) & M_T5BYTE1)
65223 
65224 #define S_T5BYTE0    0
65225 #define M_T5BYTE0    0xffU
65226 #define V_T5BYTE0(x) ((x) << S_T5BYTE0)
65227 #define G_T5BYTE0(x) (((x) >> S_T5BYTE0) & M_T5BYTE0)
65228 
65229 #define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2 0x3228
65230 
65231 #define S_T5_RX_SMODE    8
65232 #define M_T5_RX_SMODE    0x7U
65233 #define V_T5_RX_SMODE(x) ((x) << S_T5_RX_SMODE)
65234 #define G_T5_RX_SMODE(x) (((x) >> S_T5_RX_SMODE) & M_T5_RX_SMODE)
65235 
65236 #define S_T5_RX_ADCORR    7
65237 #define V_T5_RX_ADCORR(x) ((x) << S_T5_RX_ADCORR)
65238 #define F_T5_RX_ADCORR    V_T5_RX_ADCORR(1U)
65239 
65240 #define S_T5_RX_TRAINEN    6
65241 #define V_T5_RX_TRAINEN(x) ((x) << S_T5_RX_TRAINEN)
65242 #define F_T5_RX_TRAINEN    V_T5_RX_TRAINEN(1U)
65243 
65244 #define S_T5_RX_ASAMPQ    3
65245 #define M_T5_RX_ASAMPQ    0x7U
65246 #define V_T5_RX_ASAMPQ(x) ((x) << S_T5_RX_ASAMPQ)
65247 #define G_T5_RX_ASAMPQ(x) (((x) >> S_T5_RX_ASAMPQ) & M_T5_RX_ASAMPQ)
65248 
65249 #define S_T5_RX_ASAMP    0
65250 #define M_T5_RX_ASAMP    0x7U
65251 #define V_T5_RX_ASAMP(x) ((x) << S_T5_RX_ASAMP)
65252 #define G_T5_RX_ASAMP(x) (((x) >> S_T5_RX_ASAMP) & M_T5_RX_ASAMP)
65253 
65254 #define S_REQWOV    15
65255 #define V_REQWOV(x) ((x) << S_REQWOV)
65256 #define F_REQWOV    V_REQWOV(1U)
65257 
65258 #define S_RASEL    11
65259 #define M_RASEL    0x7U
65260 #define V_RASEL(x) ((x) << S_RASEL)
65261 #define G_RASEL(x) (((x) >> S_RASEL) & M_RASEL)
65262 
65263 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1 0x322c
65264 
65265 #define S_T6_WRAPSEL    15
65266 #define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
65267 #define F_T6_WRAPSEL    V_T6_WRAPSEL(1U)
65268 
65269 #define S_ACTL    14
65270 #define V_ACTL(x) ((x) << S_ACTL)
65271 #define F_ACTL    V_ACTL(1U)
65272 
65273 #define S_T6_PEAK    9
65274 #define M_T6_PEAK    0x1fU
65275 #define V_T6_PEAK(x) ((x) << S_T6_PEAK)
65276 #define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
65277 
65278 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2 0x3230
65279 
65280 #define S_T5SHORTV    10
65281 #define V_T5SHORTV(x) ((x) << S_T5SHORTV)
65282 #define F_T5SHORTV    V_T5SHORTV(1U)
65283 
65284 #define S_T5VGAIN    0
65285 #define M_T5VGAIN    0x1fU
65286 #define V_T5VGAIN(x) ((x) << S_T5VGAIN)
65287 #define G_T5VGAIN(x) (((x) >> S_T5VGAIN) & M_T5VGAIN)
65288 
65289 #define S_FVOFFSKP    15
65290 #define V_FVOFFSKP(x) ((x) << S_FVOFFSKP)
65291 #define F_FVOFFSKP    V_FVOFFSKP(1U)
65292 
65293 #define S_FGAINCHK    14
65294 #define V_FGAINCHK(x) ((x) << S_FGAINCHK)
65295 #define F_FGAINCHK    V_FGAINCHK(1U)
65296 
65297 #define S_FH1ACAL    13
65298 #define V_FH1ACAL(x) ((x) << S_FH1ACAL)
65299 #define F_FH1ACAL    V_FH1ACAL(1U)
65300 
65301 #define S_FH1AFLTR    11
65302 #define M_FH1AFLTR    0x3U
65303 #define V_FH1AFLTR(x) ((x) << S_FH1AFLTR)
65304 #define G_FH1AFLTR(x) (((x) >> S_FH1AFLTR) & M_FH1AFLTR)
65305 
65306 #define S_WGAIN    8
65307 #define M_WGAIN    0x3U
65308 #define V_WGAIN(x) ((x) << S_WGAIN)
65309 #define G_WGAIN(x) (((x) >> S_WGAIN) & M_WGAIN)
65310 
65311 #define S_GAIN_STAT    7
65312 #define V_GAIN_STAT(x) ((x) << S_GAIN_STAT)
65313 #define F_GAIN_STAT    V_GAIN_STAT(1U)
65314 
65315 #define S_T6_T5VGAIN    0
65316 #define M_T6_T5VGAIN    0x7fU
65317 #define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
65318 #define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
65319 
65320 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3 0x3234
65321 #define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1 0x3238
65322 
65323 #define S_IQSEP    10
65324 #define M_IQSEP    0x1fU
65325 #define V_IQSEP(x) ((x) << S_IQSEP)
65326 #define G_IQSEP(x) (((x) >> S_IQSEP) & M_IQSEP)
65327 
65328 #define S_DUTYQ    5
65329 #define M_DUTYQ    0x1fU
65330 #define V_DUTYQ(x) ((x) << S_DUTYQ)
65331 #define G_DUTYQ(x) (((x) >> S_DUTYQ) & M_DUTYQ)
65332 
65333 #define S_DUTYI    0
65334 #define M_DUTYI    0x1fU
65335 #define V_DUTYI(x) ((x) << S_DUTYI)
65336 #define G_DUTYI(x) (((x) >> S_DUTYI) & M_DUTYI)
65337 
65338 #define A_MAC_PORT_RX_LINKA_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3238
65339 
65340 #define S_PMCFG    6
65341 #define M_PMCFG    0x3U
65342 #define V_PMCFG(x) ((x) << S_PMCFG)
65343 #define G_PMCFG(x) (((x) >> S_PMCFG) & M_PMCFG)
65344 
65345 #define S_PMOFFTIME    0
65346 #define M_PMOFFTIME    0x3fU
65347 #define V_PMOFFTIME(x) ((x) << S_PMOFFTIME)
65348 #define G_PMOFFTIME(x) (((x) >> S_PMOFFTIME) & M_PMOFFTIME)
65349 
65350 #define A_MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_1 0x323c
65351 
65352 #define S_SELI    9
65353 #define V_SELI(x) ((x) << S_SELI)
65354 #define F_SELI    V_SELI(1U)
65355 
65356 #define S_SERVREF    5
65357 #define M_SERVREF    0x7U
65358 #define V_SERVREF(x) ((x) << S_SERVREF)
65359 #define G_SERVREF(x) (((x) >> S_SERVREF) & M_SERVREF)
65360 
65361 #define S_IQAMP    0
65362 #define M_IQAMP    0x1fU
65363 #define V_IQAMP(x) ((x) << S_IQAMP)
65364 #define G_IQAMP(x) (((x) >> S_IQAMP) & M_IQAMP)
65365 
65366 #define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3 0x3240
65367 
65368 #define S_DTHR    8
65369 #define M_DTHR    0x3fU
65370 #define V_DTHR(x) ((x) << S_DTHR)
65371 #define G_DTHR(x) (((x) >> S_DTHR) & M_DTHR)
65372 
65373 #define S_SNUL    0
65374 #define M_SNUL    0x1fU
65375 #define V_SNUL(x) ((x) << S_SNUL)
65376 #define G_SNUL(x) (((x) >> S_SNUL) & M_SNUL)
65377 
65378 #define A_MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_2 0x3240
65379 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3244
65380 
65381 #define S_SAVEADAC    8
65382 #define V_SAVEADAC(x) ((x) << S_SAVEADAC)
65383 #define F_SAVEADAC    V_SAVEADAC(1U)
65384 
65385 #define S_LOAD2    7
65386 #define V_LOAD2(x) ((x) << S_LOAD2)
65387 #define F_LOAD2    V_LOAD2(1U)
65388 
65389 #define S_LOAD1    6
65390 #define V_LOAD1(x) ((x) << S_LOAD1)
65391 #define F_LOAD1    V_LOAD1(1U)
65392 
65393 #define S_WRTACC2    5
65394 #define V_WRTACC2(x) ((x) << S_WRTACC2)
65395 #define F_WRTACC2    V_WRTACC2(1U)
65396 
65397 #define S_WRTACC1    4
65398 #define V_WRTACC1(x) ((x) << S_WRTACC1)
65399 #define F_WRTACC1    V_WRTACC1(1U)
65400 
65401 #define S_SELAPAN    3
65402 #define V_SELAPAN(x) ((x) << S_SELAPAN)
65403 #define F_SELAPAN    V_SELAPAN(1U)
65404 
65405 #define S_DASEL    0
65406 #define M_DASEL    0x7U
65407 #define V_DASEL(x) ((x) << S_DASEL)
65408 #define G_DASEL(x) (((x) >> S_DASEL) & M_DASEL)
65409 
65410 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN 0x3248
65411 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ 0x324c
65412 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN 0x324c
65413 #define A_MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL 0x3250
65414 
65415 #define S_ADSN_READWRITE    8
65416 #define V_ADSN_READWRITE(x) ((x) << S_ADSN_READWRITE)
65417 #define F_ADSN_READWRITE    V_ADSN_READWRITE(1U)
65418 
65419 #define S_ADSN_READONLY    7
65420 #define V_ADSN_READONLY(x) ((x) << S_ADSN_READONLY)
65421 #define F_ADSN_READONLY    V_ADSN_READONLY(1U)
65422 
65423 #define S_ADAC2    8
65424 #define M_ADAC2    0xffU
65425 #define V_ADAC2(x) ((x) << S_ADAC2)
65426 #define G_ADAC2(x) (((x) >> S_ADAC2) & M_ADAC2)
65427 
65428 #define S_ADAC1    0
65429 #define M_ADAC1    0xffU
65430 #define V_ADAC1(x) ((x) << S_ADAC1)
65431 #define G_ADAC1(x) (((x) >> S_ADAC1) & M_ADAC1)
65432 
65433 #define A_MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_CONTROL 0x3254
65434 
65435 #define S_FACCPLDYN    13
65436 #define V_FACCPLDYN(x) ((x) << S_FACCPLDYN)
65437 #define F_FACCPLDYN    V_FACCPLDYN(1U)
65438 
65439 #define S_ACCPLGAIN    10
65440 #define M_ACCPLGAIN    0x7U
65441 #define V_ACCPLGAIN(x) ((x) << S_ACCPLGAIN)
65442 #define G_ACCPLGAIN(x) (((x) >> S_ACCPLGAIN) & M_ACCPLGAIN)
65443 
65444 #define S_ACCPLREF    8
65445 #define M_ACCPLREF    0x3U
65446 #define V_ACCPLREF(x) ((x) << S_ACCPLREF)
65447 #define G_ACCPLREF(x) (((x) >> S_ACCPLREF) & M_ACCPLREF)
65448 
65449 #define S_ACCPLSTEP    6
65450 #define M_ACCPLSTEP    0x3U
65451 #define V_ACCPLSTEP(x) ((x) << S_ACCPLSTEP)
65452 #define G_ACCPLSTEP(x) (((x) >> S_ACCPLSTEP) & M_ACCPLSTEP)
65453 
65454 #define S_ACCPLASTEP    1
65455 #define M_ACCPLASTEP    0x1fU
65456 #define V_ACCPLASTEP(x) ((x) << S_ACCPLASTEP)
65457 #define G_ACCPLASTEP(x) (((x) >> S_ACCPLASTEP) & M_ACCPLASTEP)
65458 
65459 #define S_FACCPL    0
65460 #define V_FACCPL(x) ((x) << S_FACCPL)
65461 #define F_FACCPL    V_FACCPL(1U)
65462 
65463 #define A_MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_VALUE 0x3258
65464 
65465 #define S_ACCPLMEANS    15
65466 #define V_ACCPLMEANS(x) ((x) << S_ACCPLMEANS)
65467 #define F_ACCPLMEANS    V_ACCPLMEANS(1U)
65468 
65469 #define S_CDROVREN    8
65470 #define V_CDROVREN(x) ((x) << S_CDROVREN)
65471 #define F_CDROVREN    V_CDROVREN(1U)
65472 
65473 #define S_ACCPLBIAS    0
65474 #define M_ACCPLBIAS    0xffU
65475 #define V_ACCPLBIAS(x) ((x) << S_ACCPLBIAS)
65476 #define G_ACCPLBIAS(x) (((x) >> S_ACCPLBIAS) & M_ACCPLBIAS)
65477 
65478 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x325c
65479 
65480 #define S_H1O2    8
65481 #define M_H1O2    0x3fU
65482 #define V_H1O2(x) ((x) << S_H1O2)
65483 #define G_H1O2(x) (((x) >> S_H1O2) & M_H1O2)
65484 
65485 #define S_H1E2    0
65486 #define M_H1E2    0x3fU
65487 #define V_H1E2(x) ((x) << S_H1E2)
65488 #define G_H1E2(x) (((x) >> S_H1E2) & M_H1E2)
65489 
65490 #define A_MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET 0x325c
65491 
65492 #define S_H123CH    0
65493 #define M_H123CH    0x3fU
65494 #define V_H123CH(x) ((x) << S_H123CH)
65495 #define G_H123CH(x) (((x) >> S_H123CH) & M_H123CH)
65496 
65497 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3260
65498 
65499 #define S_H1O3    8
65500 #define M_H1O3    0x3fU
65501 #define V_H1O3(x) ((x) << S_H1O3)
65502 #define G_H1O3(x) (((x) >> S_H1O3) & M_H1O3)
65503 
65504 #define S_H1E3    0
65505 #define M_H1E3    0x3fU
65506 #define V_H1E3(x) ((x) << S_H1E3)
65507 #define G_H1E3(x) (((x) >> S_H1E3) & M_H1E3)
65508 
65509 #define A_MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3260
65510 
65511 #define S_H1OX    8
65512 #define M_H1OX    0x3fU
65513 #define V_H1OX(x) ((x) << S_H1OX)
65514 #define G_H1OX(x) (((x) >> S_H1OX) & M_H1OX)
65515 
65516 #define S_H1EX    0
65517 #define M_H1EX    0x3fU
65518 #define V_H1EX(x) ((x) << S_H1EX)
65519 #define G_H1EX(x) (((x) >> S_H1EX) & M_H1EX)
65520 
65521 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3264
65522 
65523 #define S_H1O4    8
65524 #define M_H1O4    0x3fU
65525 #define V_H1O4(x) ((x) << S_H1O4)
65526 #define G_H1O4(x) (((x) >> S_H1O4) & M_H1O4)
65527 
65528 #define S_H1E4    0
65529 #define M_H1E4    0x3fU
65530 #define V_H1E4(x) ((x) << S_H1E4)
65531 #define G_H1E4(x) (((x) >> S_H1E4) & M_H1E4)
65532 
65533 #define A_MAC_PORT_RX_LINKA_PEAKED_INTEGRATOR 0x3264
65534 
65535 #define S_PILOCK    10
65536 #define V_PILOCK(x) ((x) << S_PILOCK)
65537 #define F_PILOCK    V_PILOCK(1U)
65538 
65539 #define S_UNPKPKA    2
65540 #define M_UNPKPKA    0x3fU
65541 #define V_UNPKPKA(x) ((x) << S_UNPKPKA)
65542 #define G_UNPKPKA(x) (((x) >> S_UNPKPKA) & M_UNPKPKA)
65543 
65544 #define S_UNPKVGA    0
65545 #define M_UNPKVGA    0x3U
65546 #define V_UNPKVGA(x) ((x) << S_UNPKVGA)
65547 #define G_UNPKVGA(x) (((x) >> S_UNPKVGA) & M_UNPKVGA)
65548 
65549 #define A_MAC_PORT_RX_LINKA_CDR_ANALOG_SWITCH 0x3268
65550 
65551 #define S_OVRAC    15
65552 #define V_OVRAC(x) ((x) << S_OVRAC)
65553 #define F_OVRAC    V_OVRAC(1U)
65554 
65555 #define S_OVRPK    14
65556 #define V_OVRPK(x) ((x) << S_OVRPK)
65557 #define F_OVRPK    V_OVRPK(1U)
65558 
65559 #define S_OVRTAILS    12
65560 #define M_OVRTAILS    0x3U
65561 #define V_OVRTAILS(x) ((x) << S_OVRTAILS)
65562 #define G_OVRTAILS(x) (((x) >> S_OVRTAILS) & M_OVRTAILS)
65563 
65564 #define S_OVRTAILV    9
65565 #define M_OVRTAILV    0x7U
65566 #define V_OVRTAILV(x) ((x) << S_OVRTAILV)
65567 #define G_OVRTAILV(x) (((x) >> S_OVRTAILV) & M_OVRTAILV)
65568 
65569 #define S_OVRCAP    8
65570 #define V_OVRCAP(x) ((x) << S_OVRCAP)
65571 #define F_OVRCAP    V_OVRCAP(1U)
65572 
65573 #define S_OVRDCDPRE    7
65574 #define V_OVRDCDPRE(x) ((x) << S_OVRDCDPRE)
65575 #define F_OVRDCDPRE    V_OVRDCDPRE(1U)
65576 
65577 #define S_OVRDCDPST    6
65578 #define V_OVRDCDPST(x) ((x) << S_OVRDCDPST)
65579 #define F_OVRDCDPST    V_OVRDCDPST(1U)
65580 
65581 #define S_DCVSCTMODE    2
65582 #define V_DCVSCTMODE(x) ((x) << S_DCVSCTMODE)
65583 #define F_DCVSCTMODE    V_DCVSCTMODE(1U)
65584 
65585 #define S_CDRANLGSW    0
65586 #define M_CDRANLGSW    0x3U
65587 #define V_CDRANLGSW(x) ((x) << S_CDRANLGSW)
65588 #define G_CDRANLGSW(x) (((x) >> S_CDRANLGSW) & M_CDRANLGSW)
65589 
65590 #define A_MAC_PORT_RX_LINKA_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x326c
65591 
65592 #define S_PFLAG    5
65593 #define M_PFLAG    0x3U
65594 #define V_PFLAG(x) ((x) << S_PFLAG)
65595 #define G_PFLAG(x) (((x) >> S_PFLAG) & M_PFLAG)
65596 
65597 #define A_MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3270
65598 
65599 #define S_DPCMD    14
65600 #define V_DPCMD(x) ((x) << S_DPCMD)
65601 #define F_DPCMD    V_DPCMD(1U)
65602 
65603 #define S_DACCLIP    15
65604 #define V_DACCLIP(x) ((x) << S_DACCLIP)
65605 #define F_DACCLIP    V_DACCLIP(1U)
65606 
65607 #define S_DPCFRZ    14
65608 #define V_DPCFRZ(x) ((x) << S_DPCFRZ)
65609 #define F_DPCFRZ    V_DPCFRZ(1U)
65610 
65611 #define S_DPCLKNQ    11
65612 #define V_DPCLKNQ(x) ((x) << S_DPCLKNQ)
65613 #define F_DPCLKNQ    V_DPCLKNQ(1U)
65614 
65615 #define S_DPCWDFE    10
65616 #define V_DPCWDFE(x) ((x) << S_DPCWDFE)
65617 #define F_DPCWDFE    V_DPCWDFE(1U)
65618 
65619 #define S_DPCWPK    9
65620 #define V_DPCWPK(x) ((x) << S_DPCWPK)
65621 #define F_DPCWPK    V_DPCWPK(1U)
65622 
65623 #define A_MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC 0x3274
65624 
65625 #define S_VIEWSCAN    4
65626 #define V_VIEWSCAN(x) ((x) << S_VIEWSCAN)
65627 #define F_VIEWSCAN    V_VIEWSCAN(1U)
65628 
65629 #define S_T6_ODEC    0
65630 #define M_T6_ODEC    0xfU
65631 #define V_T6_ODEC(x) ((x) << S_T6_ODEC)
65632 #define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
65633 
65634 #define A_MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS 0x3278
65635 
65636 #define S_T5BER6VAL    15
65637 #define V_T5BER6VAL(x) ((x) << S_T5BER6VAL)
65638 #define F_T5BER6VAL    V_T5BER6VAL(1U)
65639 
65640 #define S_T5BER6    14
65641 #define V_T5BER6(x) ((x) << S_T5BER6)
65642 #define F_T5BER6    V_T5BER6(1U)
65643 
65644 #define S_T5BER3VAL    13
65645 #define V_T5BER3VAL(x) ((x) << S_T5BER3VAL)
65646 #define F_T5BER3VAL    V_T5BER3VAL(1U)
65647 
65648 #define S_T5TOOFAST    12
65649 #define V_T5TOOFAST(x) ((x) << S_T5TOOFAST)
65650 #define F_T5TOOFAST    V_T5TOOFAST(1U)
65651 
65652 #define S_T5DPCCMP    9
65653 #define V_T5DPCCMP(x) ((x) << S_T5DPCCMP)
65654 #define F_T5DPCCMP    V_T5DPCCMP(1U)
65655 
65656 #define S_T5DACCMP    8
65657 #define V_T5DACCMP(x) ((x) << S_T5DACCMP)
65658 #define F_T5DACCMP    V_T5DACCMP(1U)
65659 
65660 #define S_T5DDCCMP    7
65661 #define V_T5DDCCMP(x) ((x) << S_T5DDCCMP)
65662 #define F_T5DDCCMP    V_T5DDCCMP(1U)
65663 
65664 #define S_T5AERRFLG    6
65665 #define V_T5AERRFLG(x) ((x) << S_T5AERRFLG)
65666 #define F_T5AERRFLG    V_T5AERRFLG(1U)
65667 
65668 #define S_T5WERRFLG    5
65669 #define V_T5WERRFLG(x) ((x) << S_T5WERRFLG)
65670 #define F_T5WERRFLG    V_T5WERRFLG(1U)
65671 
65672 #define S_T5TRCMP    4
65673 #define V_T5TRCMP(x) ((x) << S_T5TRCMP)
65674 #define F_T5TRCMP    V_T5TRCMP(1U)
65675 
65676 #define S_T5VLCKF    3
65677 #define V_T5VLCKF(x) ((x) << S_T5VLCKF)
65678 #define F_T5VLCKF    V_T5VLCKF(1U)
65679 
65680 #define S_T5ROCCMP    2
65681 #define V_T5ROCCMP(x) ((x) << S_T5ROCCMP)
65682 #define F_T5ROCCMP    V_T5ROCCMP(1U)
65683 
65684 #define S_T5DQCCCMP    1
65685 #define V_T5DQCCCMP(x) ((x) << S_T5DQCCCMP)
65686 #define F_T5DQCCCMP    V_T5DQCCCMP(1U)
65687 
65688 #define S_T5OCCMP    0
65689 #define V_T5OCCMP(x) ((x) << S_T5OCCMP)
65690 #define F_T5OCCMP    V_T5OCCMP(1U)
65691 
65692 #define S_RX_LINKA_ACCCMP_RIS    11
65693 #define V_RX_LINKA_ACCCMP_RIS(x) ((x) << S_RX_LINKA_ACCCMP_RIS)
65694 #define F_RX_LINKA_ACCCMP_RIS    V_RX_LINKA_ACCCMP_RIS(1U)
65695 
65696 #define S_DCCCMP    10
65697 #define V_DCCCMP(x) ((x) << S_DCCCMP)
65698 #define F_DCCCMP    V_DCCCMP(1U)
65699 
65700 #define S_T5IQCMP    1
65701 #define V_T5IQCMP(x) ((x) << S_T5IQCMP)
65702 #define F_T5IQCMP    V_T5IQCMP(1U)
65703 
65704 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1 0x327c
65705 
65706 #define S_FLOFF    1
65707 #define V_FLOFF(x) ((x) << S_FLOFF)
65708 #define F_FLOFF    V_FLOFF(1U)
65709 
65710 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2 0x3280
65711 
65712 #define S_H25SPC    15
65713 #define V_H25SPC(x) ((x) << S_H25SPC)
65714 #define F_H25SPC    V_H25SPC(1U)
65715 
65716 #define S_FTOOFAST    8
65717 #define V_FTOOFAST(x) ((x) << S_FTOOFAST)
65718 #define F_FTOOFAST    V_FTOOFAST(1U)
65719 
65720 #define S_FINTTRIM    7
65721 #define V_FINTTRIM(x) ((x) << S_FINTTRIM)
65722 #define F_FINTTRIM    V_FINTTRIM(1U)
65723 
65724 #define S_FDINV    6
65725 #define V_FDINV(x) ((x) << S_FDINV)
65726 #define F_FDINV    V_FDINV(1U)
65727 
65728 #define S_FHGS    5
65729 #define V_FHGS(x) ((x) << S_FHGS)
65730 #define F_FHGS    V_FHGS(1U)
65731 
65732 #define S_FH6H12    4
65733 #define V_FH6H12(x) ((x) << S_FH6H12)
65734 #define F_FH6H12    V_FH6H12(1U)
65735 
65736 #define S_FH1CAL    3
65737 #define V_FH1CAL(x) ((x) << S_FH1CAL)
65738 #define F_FH1CAL    V_FH1CAL(1U)
65739 
65740 #define S_FINTCAL    2
65741 #define V_FINTCAL(x) ((x) << S_FINTCAL)
65742 #define F_FINTCAL    V_FINTCAL(1U)
65743 
65744 #define S_FDCA    1
65745 #define V_FDCA(x) ((x) << S_FDCA)
65746 #define F_FDCA    V_FDCA(1U)
65747 
65748 #define S_FDQCC    0
65749 #define V_FDQCC(x) ((x) << S_FDQCC)
65750 #define F_FDQCC    V_FDQCC(1U)
65751 
65752 #define S_FDCCAL    14
65753 #define V_FDCCAL(x) ((x) << S_FDCCAL)
65754 #define F_FDCCAL    V_FDCCAL(1U)
65755 
65756 #define S_FROTCAL    13
65757 #define V_FROTCAL(x) ((x) << S_FROTCAL)
65758 #define F_FROTCAL    V_FROTCAL(1U)
65759 
65760 #define S_FIQAMP    12
65761 #define V_FIQAMP(x) ((x) << S_FIQAMP)
65762 #define F_FIQAMP    V_FIQAMP(1U)
65763 
65764 #define S_FRPTCALF    11
65765 #define V_FRPTCALF(x) ((x) << S_FRPTCALF)
65766 #define F_FRPTCALF    V_FRPTCALF(1U)
65767 
65768 #define S_FINTCALGS    10
65769 #define V_FINTCALGS(x) ((x) << S_FINTCALGS)
65770 #define F_FINTCALGS    V_FINTCALGS(1U)
65771 
65772 #define S_FDCC    9
65773 #define V_FDCC(x) ((x) << S_FDCC)
65774 #define F_FDCC    V_FDCC(1U)
65775 
65776 #define S_FDCD    7
65777 #define V_FDCD(x) ((x) << S_FDCD)
65778 #define F_FDCD    V_FDCD(1U)
65779 
65780 #define S_FINTRCALDYN    1
65781 #define V_FINTRCALDYN(x) ((x) << S_FINTRCALDYN)
65782 #define F_FINTRCALDYN    V_FINTRCALDYN(1U)
65783 
65784 #define S_FQCC    0
65785 #define V_FQCC(x) ((x) << S_FQCC)
65786 #define F_FQCC    V_FQCC(1U)
65787 
65788 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2 0x3284
65789 
65790 #define S_LOFE2S_READWRITE    16
65791 #define V_LOFE2S_READWRITE(x) ((x) << S_LOFE2S_READWRITE)
65792 #define F_LOFE2S_READWRITE    V_LOFE2S_READWRITE(1U)
65793 
65794 #define S_LOFE2S_READONLY    14
65795 #define M_LOFE2S_READONLY    0x3U
65796 #define V_LOFE2S_READONLY(x) ((x) << S_LOFE2S_READONLY)
65797 #define G_LOFE2S_READONLY(x) (((x) >> S_LOFE2S_READONLY) & M_LOFE2S_READONLY)
65798 
65799 #define S_LOFE2    8
65800 #define M_LOFE2    0x3fU
65801 #define V_LOFE2(x) ((x) << S_LOFE2)
65802 #define G_LOFE2(x) (((x) >> S_LOFE2) & M_LOFE2)
65803 
65804 #define S_LOFE1S_READWRITE    7
65805 #define V_LOFE1S_READWRITE(x) ((x) << S_LOFE1S_READWRITE)
65806 #define F_LOFE1S_READWRITE    V_LOFE1S_READWRITE(1U)
65807 
65808 #define S_LOFE1S_READONLY    6
65809 #define V_LOFE1S_READONLY(x) ((x) << S_LOFE1S_READONLY)
65810 #define F_LOFE1S_READONLY    V_LOFE1S_READONLY(1U)
65811 
65812 #define S_LOFE1    0
65813 #define M_LOFE1    0x3fU
65814 #define V_LOFE1(x) ((x) << S_LOFE1)
65815 #define G_LOFE1(x) (((x) >> S_LOFE1) & M_LOFE1)
65816 
65817 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_CHANNEL 0x3284
65818 
65819 #define S_QCCIND    13
65820 #define V_QCCIND(x) ((x) << S_QCCIND)
65821 #define F_QCCIND    V_QCCIND(1U)
65822 
65823 #define S_DCDIND    10
65824 #define M_DCDIND    0x7U
65825 #define V_DCDIND(x) ((x) << S_DCDIND)
65826 #define G_DCDIND(x) (((x) >> S_DCDIND) & M_DCDIND)
65827 
65828 #define S_DCCIND    8
65829 #define M_DCCIND    0x3U
65830 #define V_DCCIND(x) ((x) << S_DCCIND)
65831 #define G_DCCIND(x) (((x) >> S_DCCIND) & M_DCCIND)
65832 
65833 #define S_CFSEL    5
65834 #define V_CFSEL(x) ((x) << S_CFSEL)
65835 #define F_CFSEL    V_CFSEL(1U)
65836 
65837 #define S_LOFCH    0
65838 #define M_LOFCH    0x1fU
65839 #define V_LOFCH(x) ((x) << S_LOFCH)
65840 #define G_LOFCH(x) (((x) >> S_LOFCH) & M_LOFCH)
65841 
65842 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2 0x3288
65843 
65844 #define S_LOFO2S_READWRITE    15
65845 #define V_LOFO2S_READWRITE(x) ((x) << S_LOFO2S_READWRITE)
65846 #define F_LOFO2S_READWRITE    V_LOFO2S_READWRITE(1U)
65847 
65848 #define S_LOFO2S_READONLY    14
65849 #define V_LOFO2S_READONLY(x) ((x) << S_LOFO2S_READONLY)
65850 #define F_LOFO2S_READONLY    V_LOFO2S_READONLY(1U)
65851 
65852 #define S_LOFO2    8
65853 #define M_LOFO2    0x3fU
65854 #define V_LOFO2(x) ((x) << S_LOFO2)
65855 #define G_LOFO2(x) (((x) >> S_LOFO2) & M_LOFO2)
65856 
65857 #define S_LOFO1S_READWRITE    7
65858 #define V_LOFO1S_READWRITE(x) ((x) << S_LOFO1S_READWRITE)
65859 #define F_LOFO1S_READWRITE    V_LOFO1S_READWRITE(1U)
65860 
65861 #define S_LOFO1S_READONLY    6
65862 #define V_LOFO1S_READONLY(x) ((x) << S_LOFO1S_READONLY)
65863 #define F_LOFO1S_READONLY    V_LOFO1S_READONLY(1U)
65864 
65865 #define S_LOFO1    0
65866 #define M_LOFO1    0x3fU
65867 #define V_LOFO1(x) ((x) << S_LOFO1)
65868 #define G_LOFO1(x) (((x) >> S_LOFO1) & M_LOFO1)
65869 
65870 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_VALUE 0x3288
65871 
65872 #define S_LOFU    8
65873 #define M_LOFU    0x7fU
65874 #define V_LOFU(x) ((x) << S_LOFU)
65875 #define G_LOFU(x) (((x) >> S_LOFU) & M_LOFU)
65876 
65877 #define S_LOFL    0
65878 #define M_LOFL    0x7fU
65879 #define V_LOFL(x) ((x) << S_LOFL)
65880 #define G_LOFL(x) (((x) >> S_LOFL) & M_LOFL)
65881 
65882 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4 0x328c
65883 
65884 #define S_LOFE4S_READWRITE    15
65885 #define V_LOFE4S_READWRITE(x) ((x) << S_LOFE4S_READWRITE)
65886 #define F_LOFE4S_READWRITE    V_LOFE4S_READWRITE(1U)
65887 
65888 #define S_LOFE4S_READONLY    14
65889 #define V_LOFE4S_READONLY(x) ((x) << S_LOFE4S_READONLY)
65890 #define F_LOFE4S_READONLY    V_LOFE4S_READONLY(1U)
65891 
65892 #define S_LOFE    8
65893 #define M_LOFE    0x3fU
65894 #define V_LOFE(x) ((x) << S_LOFE)
65895 #define G_LOFE(x) (((x) >> S_LOFE) & M_LOFE)
65896 
65897 #define S_LOFE3S_READWRITE    7
65898 #define V_LOFE3S_READWRITE(x) ((x) << S_LOFE3S_READWRITE)
65899 #define F_LOFE3S_READWRITE    V_LOFE3S_READWRITE(1U)
65900 
65901 #define S_LOFE3S_READONLY    6
65902 #define V_LOFE3S_READONLY(x) ((x) << S_LOFE3S_READONLY)
65903 #define F_LOFE3S_READONLY    V_LOFE3S_READONLY(1U)
65904 
65905 #define S_LOFE3    0
65906 #define M_LOFE3    0x3fU
65907 #define V_LOFE3(x) ((x) << S_LOFE3)
65908 #define G_LOFE3(x) (((x) >> S_LOFE3) & M_LOFE3)
65909 
65910 #define A_MAC_PORT_RX_LINKA_H_COEFFICIENBT_BIST 0x328c
65911 
65912 #define S_HBISTMAN    12
65913 #define V_HBISTMAN(x) ((x) << S_HBISTMAN)
65914 #define F_HBISTMAN    V_HBISTMAN(1U)
65915 
65916 #define S_HBISTRES    11
65917 #define V_HBISTRES(x) ((x) << S_HBISTRES)
65918 #define F_HBISTRES    V_HBISTRES(1U)
65919 
65920 #define S_HBISTSP    8
65921 #define M_HBISTSP    0x7U
65922 #define V_HBISTSP(x) ((x) << S_HBISTSP)
65923 #define G_HBISTSP(x) (((x) >> S_HBISTSP) & M_HBISTSP)
65924 
65925 #define S_HBISTEN    7
65926 #define V_HBISTEN(x) ((x) << S_HBISTEN)
65927 #define F_HBISTEN    V_HBISTEN(1U)
65928 
65929 #define S_HBISTRST    6
65930 #define V_HBISTRST(x) ((x) << S_HBISTRST)
65931 #define F_HBISTRST    V_HBISTRST(1U)
65932 
65933 #define S_HCOMP    5
65934 #define V_HCOMP(x) ((x) << S_HCOMP)
65935 #define F_HCOMP    V_HCOMP(1U)
65936 
65937 #define S_HPASS    4
65938 #define V_HPASS(x) ((x) << S_HPASS)
65939 #define F_HPASS    V_HPASS(1U)
65940 
65941 #define S_HSEL    0
65942 #define M_HSEL    0xfU
65943 #define V_HSEL(x) ((x) << S_HSEL)
65944 #define G_HSEL(x) (((x) >> S_HSEL) & M_HSEL)
65945 
65946 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4 0x3290
65947 
65948 #define S_LOFO4S_READWRITE    15
65949 #define V_LOFO4S_READWRITE(x) ((x) << S_LOFO4S_READWRITE)
65950 #define F_LOFO4S_READWRITE    V_LOFO4S_READWRITE(1U)
65951 
65952 #define S_LOFO4S_READONLY    14
65953 #define V_LOFO4S_READONLY(x) ((x) << S_LOFO4S_READONLY)
65954 #define F_LOFO4S_READONLY    V_LOFO4S_READONLY(1U)
65955 
65956 #define S_LOFO4    8
65957 #define M_LOFO4    0x3fU
65958 #define V_LOFO4(x) ((x) << S_LOFO4)
65959 #define G_LOFO4(x) (((x) >> S_LOFO4) & M_LOFO4)
65960 
65961 #define S_LOFO3S_READWRITE    7
65962 #define V_LOFO3S_READWRITE(x) ((x) << S_LOFO3S_READWRITE)
65963 #define F_LOFO3S_READWRITE    V_LOFO3S_READWRITE(1U)
65964 
65965 #define S_LOFO3S_READONLY    6
65966 #define V_LOFO3S_READONLY(x) ((x) << S_LOFO3S_READONLY)
65967 #define F_LOFO3S_READONLY    V_LOFO3S_READONLY(1U)
65968 
65969 #define S_LOFO3    0
65970 #define M_LOFO3    0x3fU
65971 #define V_LOFO3(x) ((x) << S_LOFO3)
65972 #define G_LOFO3(x) (((x) >> S_LOFO3) & M_LOFO3)
65973 
65974 #define A_MAC_PORT_RX_LINKA_AC_CAPACITOR_BIST 0x3290
65975 
65976 #define S_RX_LINKA_ACCCMP_BIST    13
65977 #define V_RX_LINKA_ACCCMP_BIST(x) ((x) << S_RX_LINKA_ACCCMP_BIST)
65978 #define F_RX_LINKA_ACCCMP_BIST    V_RX_LINKA_ACCCMP_BIST(1U)
65979 
65980 #define S_ACCEN    12
65981 #define V_ACCEN(x) ((x) << S_ACCEN)
65982 #define F_ACCEN    V_ACCEN(1U)
65983 
65984 #define S_ACCRST    11
65985 #define V_ACCRST(x) ((x) << S_ACCRST)
65986 #define F_ACCRST    V_ACCRST(1U)
65987 
65988 #define S_ACCIND    8
65989 #define M_ACCIND    0x7U
65990 #define V_ACCIND(x) ((x) << S_ACCIND)
65991 #define G_ACCIND(x) (((x) >> S_ACCIND) & M_ACCIND)
65992 
65993 #define S_ACCRD    0
65994 #define M_ACCRD    0xffU
65995 #define V_ACCRD(x) ((x) << S_ACCRD)
65996 #define G_ACCRD(x) (((x) >> S_ACCRD) & M_ACCRD)
65997 
65998 #define A_MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET 0x3294
65999 
66000 #define S_T5E1SN_READWRITE    15
66001 #define V_T5E1SN_READWRITE(x) ((x) << S_T5E1SN_READWRITE)
66002 #define F_T5E1SN_READWRITE    V_T5E1SN_READWRITE(1U)
66003 
66004 #define S_T5E1SN_READONLY    14
66005 #define V_T5E1SN_READONLY(x) ((x) << S_T5E1SN_READONLY)
66006 #define F_T5E1SN_READONLY    V_T5E1SN_READONLY(1U)
66007 
66008 #define S_T5E1AMP    8
66009 #define M_T5E1AMP    0x3fU
66010 #define V_T5E1AMP(x) ((x) << S_T5E1AMP)
66011 #define G_T5E1AMP(x) (((x) >> S_T5E1AMP) & M_T5E1AMP)
66012 
66013 #define S_T5E0SN_READWRITE    7
66014 #define V_T5E0SN_READWRITE(x) ((x) << S_T5E0SN_READWRITE)
66015 #define F_T5E0SN_READWRITE    V_T5E0SN_READWRITE(1U)
66016 
66017 #define S_T5E0SN_READONLY    6
66018 #define V_T5E0SN_READONLY(x) ((x) << S_T5E0SN_READONLY)
66019 #define F_T5E0SN_READONLY    V_T5E0SN_READONLY(1U)
66020 
66021 #define S_T5E0AMP    0
66022 #define M_T5E0AMP    0x3fU
66023 #define V_T5E0AMP(x) ((x) << S_T5E0AMP)
66024 #define G_T5E0AMP(x) (((x) >> S_T5E0AMP) & M_T5E0AMP)
66025 
66026 #define A_MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL 0x3298
66027 
66028 #define S_T5LFREG    12
66029 #define V_T5LFREG(x) ((x) << S_T5LFREG)
66030 #define F_T5LFREG    V_T5LFREG(1U)
66031 
66032 #define S_T5LFRC    11
66033 #define V_T5LFRC(x) ((x) << S_T5LFRC)
66034 #define F_T5LFRC    V_T5LFRC(1U)
66035 
66036 #define S_T5LFSEL    8
66037 #define M_T5LFSEL    0x7U
66038 #define V_T5LFSEL(x) ((x) << S_T5LFSEL)
66039 #define G_T5LFSEL(x) (((x) >> S_T5LFSEL) & M_T5LFSEL)
66040 
66041 #define A_MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL_REGISTER 0x3298
66042 
66043 #define S_LFREG    15
66044 #define V_LFREG(x) ((x) << S_LFREG)
66045 #define F_LFREG    V_LFREG(1U)
66046 
66047 #define S_LFRC    14
66048 #define V_LFRC(x) ((x) << S_LFRC)
66049 #define F_LFRC    V_LFRC(1U)
66050 
66051 #define S_LGIDLE    13
66052 #define V_LGIDLE(x) ((x) << S_LGIDLE)
66053 #define F_LGIDLE    V_LGIDLE(1U)
66054 
66055 #define S_LFTGT    8
66056 #define M_LFTGT    0x1fU
66057 #define V_LFTGT(x) ((x) << S_LFTGT)
66058 #define G_LFTGT(x) (((x) >> S_LFTGT) & M_LFTGT)
66059 
66060 #define S_LGTGT    7
66061 #define V_LGTGT(x) ((x) << S_LGTGT)
66062 #define F_LGTGT    V_LGTGT(1U)
66063 
66064 #define S_LRDY    6
66065 #define V_LRDY(x) ((x) << S_LRDY)
66066 #define F_LRDY    V_LRDY(1U)
66067 
66068 #define S_LIDLE    5
66069 #define V_LIDLE(x) ((x) << S_LIDLE)
66070 #define F_LIDLE    V_LIDLE(1U)
66071 
66072 #define S_LCURR    0
66073 #define M_LCURR    0x1fU
66074 #define V_LCURR(x) ((x) << S_LCURR)
66075 #define G_LCURR(x) (((x) >> S_LCURR) & M_LCURR)
66076 
66077 #define A_MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL 0x329c
66078 
66079 #define S_OFFSN_READWRITE    14
66080 #define V_OFFSN_READWRITE(x) ((x) << S_OFFSN_READWRITE)
66081 #define F_OFFSN_READWRITE    V_OFFSN_READWRITE(1U)
66082 
66083 #define S_OFFSN_READONLY    13
66084 #define V_OFFSN_READONLY(x) ((x) << S_OFFSN_READONLY)
66085 #define F_OFFSN_READONLY    V_OFFSN_READONLY(1U)
66086 
66087 #define S_OFFAMP    8
66088 #define M_OFFAMP    0x1fU
66089 #define V_OFFAMP(x) ((x) << S_OFFAMP)
66090 #define G_OFFAMP(x) (((x) >> S_OFFAMP) & M_OFFAMP)
66091 
66092 #define S_SDACDC    7
66093 #define V_SDACDC(x) ((x) << S_SDACDC)
66094 #define F_SDACDC    V_SDACDC(1U)
66095 
66096 #define S_OFFSN    13
66097 #define M_OFFSN    0x3U
66098 #define V_OFFSN(x) ((x) << S_OFFSN)
66099 #define G_OFFSN(x) (((x) >> S_OFFSN) & M_OFFSN)
66100 
66101 #define A_MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH 0x32a0
66102 
66103 #define S_T5_RX_SETHDIS    7
66104 #define V_T5_RX_SETHDIS(x) ((x) << S_T5_RX_SETHDIS)
66105 #define F_T5_RX_SETHDIS    V_T5_RX_SETHDIS(1U)
66106 
66107 #define S_T5_RX_PDTERM    6
66108 #define V_T5_RX_PDTERM(x) ((x) << S_T5_RX_PDTERM)
66109 #define F_T5_RX_PDTERM    V_T5_RX_PDTERM(1U)
66110 
66111 #define S_T5_RX_BYPASS    5
66112 #define V_T5_RX_BYPASS(x) ((x) << S_T5_RX_BYPASS)
66113 #define F_T5_RX_BYPASS    V_T5_RX_BYPASS(1U)
66114 
66115 #define S_T5_RX_LPFEN    4
66116 #define V_T5_RX_LPFEN(x) ((x) << S_T5_RX_LPFEN)
66117 #define F_T5_RX_LPFEN    V_T5_RX_LPFEN(1U)
66118 
66119 #define S_T5_RX_VGABOD    3
66120 #define V_T5_RX_VGABOD(x) ((x) << S_T5_RX_VGABOD)
66121 #define F_T5_RX_VGABOD    V_T5_RX_VGABOD(1U)
66122 
66123 #define S_T5_RX_VTBYP    2
66124 #define V_T5_RX_VTBYP(x) ((x) << S_T5_RX_VTBYP)
66125 #define F_T5_RX_VTBYP    V_T5_RX_VTBYP(1U)
66126 
66127 #define S_T5_RX_VTERM    0
66128 #define M_T5_RX_VTERM    0x3U
66129 #define V_T5_RX_VTERM(x) ((x) << S_T5_RX_VTERM)
66130 #define G_T5_RX_VTERM(x) (((x) >> S_T5_RX_VTERM) & M_T5_RX_VTERM)
66131 
66132 #define S_RX_OVRSUMPD    15
66133 #define V_RX_OVRSUMPD(x) ((x) << S_RX_OVRSUMPD)
66134 #define F_RX_OVRSUMPD    V_RX_OVRSUMPD(1U)
66135 
66136 #define S_RX_OVRKBPD    14
66137 #define V_RX_OVRKBPD(x) ((x) << S_RX_OVRKBPD)
66138 #define F_RX_OVRKBPD    V_RX_OVRKBPD(1U)
66139 
66140 #define S_RX_OVRDIVPD    13
66141 #define V_RX_OVRDIVPD(x) ((x) << S_RX_OVRDIVPD)
66142 #define F_RX_OVRDIVPD    V_RX_OVRDIVPD(1U)
66143 
66144 #define S_RX_OFFVGADIS    12
66145 #define V_RX_OFFVGADIS(x) ((x) << S_RX_OFFVGADIS)
66146 #define F_RX_OFFVGADIS    V_RX_OFFVGADIS(1U)
66147 
66148 #define S_RX_OFFACDIS    11
66149 #define V_RX_OFFACDIS(x) ((x) << S_RX_OFFACDIS)
66150 #define F_RX_OFFACDIS    V_RX_OFFACDIS(1U)
66151 
66152 #define S_RX_VTERM    10
66153 #define V_RX_VTERM(x) ((x) << S_RX_VTERM)
66154 #define F_RX_VTERM    V_RX_VTERM(1U)
66155 
66156 #define S_RX_DISSPY2D    8
66157 #define V_RX_DISSPY2D(x) ((x) << S_RX_DISSPY2D)
66158 #define F_RX_DISSPY2D    V_RX_DISSPY2D(1U)
66159 
66160 #define S_RX_OBSOVEN    7
66161 #define V_RX_OBSOVEN(x) ((x) << S_RX_OBSOVEN)
66162 #define F_RX_OBSOVEN    V_RX_OBSOVEN(1U)
66163 
66164 #define S_RX_LINKANLGSW    0
66165 #define M_RX_LINKANLGSW    0x7fU
66166 #define V_RX_LINKANLGSW(x) ((x) << S_RX_LINKANLGSW)
66167 #define G_RX_LINKANLGSW(x) (((x) >> S_RX_LINKANLGSW) & M_RX_LINKANLGSW)
66168 
66169 #define A_MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET 0x32a4
66170 
66171 #define S_ISTRIMS    14
66172 #define M_ISTRIMS    0x3U
66173 #define V_ISTRIMS(x) ((x) << S_ISTRIMS)
66174 #define G_ISTRIMS(x) (((x) >> S_ISTRIMS) & M_ISTRIMS)
66175 
66176 #define S_ISTRIM    8
66177 #define M_ISTRIM    0x3fU
66178 #define V_ISTRIM(x) ((x) << S_ISTRIM)
66179 #define G_ISTRIM(x) (((x) >> S_ISTRIM) & M_ISTRIM)
66180 
66181 #define S_HALF1    7
66182 #define V_HALF1(x) ((x) << S_HALF1)
66183 #define F_HALF1    V_HALF1(1U)
66184 
66185 #define S_HALF2    6
66186 #define V_HALF2(x) ((x) << S_HALF2)
66187 #define F_HALF2    V_HALF2(1U)
66188 
66189 #define S_INTDAC    0
66190 #define M_INTDAC    0x3fU
66191 #define V_INTDAC(x) ((x) << S_INTDAC)
66192 #define G_INTDAC(x) (((x) >> S_INTDAC) & M_INTDAC)
66193 
66194 #define S_INTDACEGS    13
66195 #define M_INTDACEGS    0x7U
66196 #define V_INTDACEGS(x) ((x) << S_INTDACEGS)
66197 #define G_INTDACEGS(x) (((x) >> S_INTDACEGS) & M_INTDACEGS)
66198 
66199 #define S_INTDACE    8
66200 #define M_INTDACE    0x1fU
66201 #define V_INTDACE(x) ((x) << S_INTDACE)
66202 #define G_INTDACE(x) (((x) >> S_INTDACE) & M_INTDACE)
66203 
66204 #define S_INTDACGS    6
66205 #define M_INTDACGS    0x3U
66206 #define V_INTDACGS(x) ((x) << S_INTDACGS)
66207 #define G_INTDACGS(x) (((x) >> S_INTDACGS) & M_INTDACGS)
66208 
66209 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL 0x32a8
66210 
66211 #define S_MINWDTH    5
66212 #define M_MINWDTH    0x1fU
66213 #define V_MINWDTH(x) ((x) << S_MINWDTH)
66214 #define G_MINWDTH(x) (((x) >> S_MINWDTH) & M_MINWDTH)
66215 
66216 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS 0x32ac
66217 
66218 #define S_T5SMQM    13
66219 #define M_T5SMQM    0x7U
66220 #define V_T5SMQM(x) ((x) << S_T5SMQM)
66221 #define G_T5SMQM(x) (((x) >> S_T5SMQM) & M_T5SMQM)
66222 
66223 #define S_T5SMQ    5
66224 #define M_T5SMQ    0xffU
66225 #define V_T5SMQ(x) ((x) << S_T5SMQ)
66226 #define G_T5SMQ(x) (((x) >> S_T5SMQ) & M_T5SMQ)
66227 
66228 #define S_T5EMMD    3
66229 #define M_T5EMMD    0x3U
66230 #define V_T5EMMD(x) ((x) << S_T5EMMD)
66231 #define G_T5EMMD(x) (((x) >> S_T5EMMD) & M_T5EMMD)
66232 
66233 #define S_T5EMBRDY    2
66234 #define V_T5EMBRDY(x) ((x) << S_T5EMBRDY)
66235 #define F_T5EMBRDY    V_T5EMBRDY(1U)
66236 
66237 #define S_T5EMBUMP    1
66238 #define V_T5EMBUMP(x) ((x) << S_T5EMBUMP)
66239 #define F_T5EMBUMP    V_T5EMBUMP(1U)
66240 
66241 #define S_T5EMEN    0
66242 #define V_T5EMEN(x) ((x) << S_T5EMEN)
66243 #define F_T5EMEN    V_T5EMEN(1U)
66244 
66245 #define S_SMQM    13
66246 #define M_SMQM    0x7U
66247 #define V_SMQM(x) ((x) << S_SMQM)
66248 #define G_SMQM(x) (((x) >> S_SMQM) & M_SMQM)
66249 
66250 #define S_SMQ    5
66251 #define M_SMQ    0xffU
66252 #define V_SMQ(x) ((x) << S_SMQ)
66253 #define G_SMQ(x) (((x) >> S_SMQ) & M_SMQ)
66254 
66255 #define S_T6_EMMD    3
66256 #define M_T6_EMMD    0x3U
66257 #define V_T6_EMMD(x) ((x) << S_T6_EMMD)
66258 #define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
66259 
66260 #define S_T6_EMBRDY    2
66261 #define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
66262 #define F_T6_EMBRDY    V_T6_EMBRDY(1U)
66263 
66264 #define S_T6_EMBUMP    1
66265 #define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
66266 #define F_T6_EMBUMP    V_T6_EMBUMP(1U)
66267 
66268 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT 0x32b0
66269 
66270 #define S_EMF8    15
66271 #define V_EMF8(x) ((x) << S_EMF8)
66272 #define F_EMF8    V_EMF8(1U)
66273 
66274 #define S_EMCNT    4
66275 #define M_EMCNT    0xffU
66276 #define V_EMCNT(x) ((x) << S_EMCNT)
66277 #define G_EMCNT(x) (((x) >> S_EMCNT) & M_EMCNT)
66278 
66279 #define S_EMOFLO    2
66280 #define V_EMOFLO(x) ((x) << S_EMOFLO)
66281 #define F_EMOFLO    V_EMOFLO(1U)
66282 
66283 #define S_EMCRST    1
66284 #define V_EMCRST(x) ((x) << S_EMCRST)
66285 #define F_EMCRST    V_EMCRST(1U)
66286 
66287 #define S_EMCEN    0
66288 #define V_EMCEN(x) ((x) << S_EMCEN)
66289 #define F_EMCEN    V_EMCEN(1U)
66290 
66291 #define S_EMSF    13
66292 #define V_EMSF(x) ((x) << S_EMSF)
66293 #define F_EMSF    V_EMSF(1U)
66294 
66295 #define S_EMDATA59    12
66296 #define V_EMDATA59(x) ((x) << S_EMDATA59)
66297 #define F_EMDATA59    V_EMDATA59(1U)
66298 
66299 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x32b4
66300 
66301 #define S_SM2RDY    15
66302 #define V_SM2RDY(x) ((x) << S_SM2RDY)
66303 #define F_SM2RDY    V_SM2RDY(1U)
66304 
66305 #define S_SM2RST    14
66306 #define V_SM2RST(x) ((x) << S_SM2RST)
66307 #define F_SM2RST    V_SM2RST(1U)
66308 
66309 #define S_APDF    0
66310 #define M_APDF    0xfffU
66311 #define V_APDF(x) ((x) << S_APDF)
66312 #define G_APDF(x) (((x) >> S_APDF) & M_APDF)
66313 
66314 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x32b8
66315 
66316 #define S_SM0LEN    0
66317 #define M_SM0LEN    0x7fffU
66318 #define V_SM0LEN(x) ((x) << S_SM0LEN)
66319 #define G_SM0LEN(x) (((x) >> S_SM0LEN) & M_SM0LEN)
66320 
66321 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_3 0x32bc
66322 
66323 #define S_FTIMEOUT    15
66324 #define V_FTIMEOUT(x) ((x) << S_FTIMEOUT)
66325 #define F_FTIMEOUT    V_FTIMEOUT(1U)
66326 
66327 #define S_FROTCAL4    14
66328 #define V_FROTCAL4(x) ((x) << S_FROTCAL4)
66329 #define F_FROTCAL4    V_FROTCAL4(1U)
66330 
66331 #define S_FDCD2    13
66332 #define V_FDCD2(x) ((x) << S_FDCD2)
66333 #define F_FDCD2    V_FDCD2(1U)
66334 
66335 #define S_FPRBSPOLTOG    12
66336 #define V_FPRBSPOLTOG(x) ((x) << S_FPRBSPOLTOG)
66337 #define F_FPRBSPOLTOG    V_FPRBSPOLTOG(1U)
66338 
66339 #define S_FPRBSOFF2    11
66340 #define V_FPRBSOFF2(x) ((x) << S_FPRBSOFF2)
66341 #define F_FPRBSOFF2    V_FPRBSOFF2(1U)
66342 
66343 #define S_FDDCAL2    10
66344 #define V_FDDCAL2(x) ((x) << S_FDDCAL2)
66345 #define F_FDDCAL2    V_FDDCAL2(1U)
66346 
66347 #define S_FDDCFLTR    9
66348 #define V_FDDCFLTR(x) ((x) << S_FDDCFLTR)
66349 #define F_FDDCFLTR    V_FDDCFLTR(1U)
66350 
66351 #define S_FDAC6    8
66352 #define V_FDAC6(x) ((x) << S_FDAC6)
66353 #define F_FDAC6    V_FDAC6(1U)
66354 
66355 #define S_FDDC5    7
66356 #define V_FDDC5(x) ((x) << S_FDDC5)
66357 #define F_FDDC5    V_FDDC5(1U)
66358 
66359 #define S_FDDC3456    6
66360 #define V_FDDC3456(x) ((x) << S_FDDC3456)
66361 #define F_FDDC3456    V_FDDC3456(1U)
66362 
66363 #define S_FSPY2DATA    5
66364 #define V_FSPY2DATA(x) ((x) << S_FSPY2DATA)
66365 #define F_FSPY2DATA    V_FSPY2DATA(1U)
66366 
66367 #define S_FPHSLOCK    4
66368 #define V_FPHSLOCK(x) ((x) << S_FPHSLOCK)
66369 #define F_FPHSLOCK    V_FPHSLOCK(1U)
66370 
66371 #define S_FCLKALGN    3
66372 #define V_FCLKALGN(x) ((x) << S_FCLKALGN)
66373 #define F_FCLKALGN    V_FCLKALGN(1U)
66374 
66375 #define S_FCLKALDYN    2
66376 #define V_FCLKALDYN(x) ((x) << S_FCLKALDYN)
66377 #define F_FCLKALDYN    V_FCLKALDYN(1U)
66378 
66379 #define S_FDFE    1
66380 #define V_FDFE(x) ((x) << S_FDFE)
66381 #define F_FDFE    V_FDFE(1U)
66382 
66383 #define S_FPRBSOFF    0
66384 #define V_FPRBSOFF(x) ((x) << S_FPRBSOFF)
66385 #define F_FPRBSOFF    V_FPRBSOFF(1U)
66386 
66387 #define A_MAC_PORT_RX_LINKA_DFE_TAP_ENABLE 0x32c0
66388 
66389 #define S_H_EN    1
66390 #define M_H_EN    0xfffU
66391 #define V_H_EN(x) ((x) << S_H_EN)
66392 #define G_H_EN(x) (((x) >> S_H_EN) & M_H_EN)
66393 
66394 #define A_MAC_PORT_RX_LINKA_DFE_TAP_CONTROL 0x32c0
66395 
66396 #define S_RX_LINKA_INDEX_DFE_TC    0
66397 #define M_RX_LINKA_INDEX_DFE_TC    0xfU
66398 #define V_RX_LINKA_INDEX_DFE_TC(x) ((x) << S_RX_LINKA_INDEX_DFE_TC)
66399 #define G_RX_LINKA_INDEX_DFE_TC(x) (((x) >> S_RX_LINKA_INDEX_DFE_TC) & M_RX_LINKA_INDEX_DFE_TC)
66400 
66401 #define A_MAC_PORT_RX_LINKA_DFE_H1 0x32c4
66402 #define A_MAC_PORT_RX_LINKA_DFE_TAP 0x32c4
66403 
66404 #define S_RX_LINKA_INDEX_DFE_TAP    0
66405 #define M_RX_LINKA_INDEX_DFE_TAP    0xfU
66406 #define V_RX_LINKA_INDEX_DFE_TAP(x) ((x) << S_RX_LINKA_INDEX_DFE_TAP)
66407 #define G_RX_LINKA_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKA_INDEX_DFE_TAP) & M_RX_LINKA_INDEX_DFE_TAP)
66408 
66409 #define A_MAC_PORT_RX_LINKA_DFE_H2 0x32c8
66410 
66411 #define S_H2OSN_READWRITE    14
66412 #define V_H2OSN_READWRITE(x) ((x) << S_H2OSN_READWRITE)
66413 #define F_H2OSN_READWRITE    V_H2OSN_READWRITE(1U)
66414 
66415 #define S_H2OSN_READONLY    13
66416 #define V_H2OSN_READONLY(x) ((x) << S_H2OSN_READONLY)
66417 #define F_H2OSN_READONLY    V_H2OSN_READONLY(1U)
66418 
66419 #define S_H2ESN_READWRITE    6
66420 #define V_H2ESN_READWRITE(x) ((x) << S_H2ESN_READWRITE)
66421 #define F_H2ESN_READWRITE    V_H2ESN_READWRITE(1U)
66422 
66423 #define S_H2ESN_READONLY    5
66424 #define V_H2ESN_READONLY(x) ((x) << S_H2ESN_READONLY)
66425 #define F_H2ESN_READONLY    V_H2ESN_READONLY(1U)
66426 
66427 #define A_MAC_PORT_RX_LINKA_DFE_H3 0x32cc
66428 
66429 #define S_H3OSN_READWRITE    13
66430 #define V_H3OSN_READWRITE(x) ((x) << S_H3OSN_READWRITE)
66431 #define F_H3OSN_READWRITE    V_H3OSN_READWRITE(1U)
66432 
66433 #define S_H3OSN_READONLY    12
66434 #define V_H3OSN_READONLY(x) ((x) << S_H3OSN_READONLY)
66435 #define F_H3OSN_READONLY    V_H3OSN_READONLY(1U)
66436 
66437 #define S_H3ESN_READWRITE    5
66438 #define V_H3ESN_READWRITE(x) ((x) << S_H3ESN_READWRITE)
66439 #define F_H3ESN_READWRITE    V_H3ESN_READWRITE(1U)
66440 
66441 #define S_H3ESN_READONLY    4
66442 #define V_H3ESN_READONLY(x) ((x) << S_H3ESN_READONLY)
66443 #define F_H3ESN_READONLY    V_H3ESN_READONLY(1U)
66444 
66445 #define A_MAC_PORT_RX_LINKA_DFE_H4 0x32d0
66446 
66447 #define S_H4OGS    14
66448 #define M_H4OGS    0x3U
66449 #define V_H4OGS(x) ((x) << S_H4OGS)
66450 #define G_H4OGS(x) (((x) >> S_H4OGS) & M_H4OGS)
66451 
66452 #define S_H4OSN_READWRITE    13
66453 #define V_H4OSN_READWRITE(x) ((x) << S_H4OSN_READWRITE)
66454 #define F_H4OSN_READWRITE    V_H4OSN_READWRITE(1U)
66455 
66456 #define S_H4OSN_READONLY    12
66457 #define V_H4OSN_READONLY(x) ((x) << S_H4OSN_READONLY)
66458 #define F_H4OSN_READONLY    V_H4OSN_READONLY(1U)
66459 
66460 #define S_H4EGS    6
66461 #define M_H4EGS    0x3U
66462 #define V_H4EGS(x) ((x) << S_H4EGS)
66463 #define G_H4EGS(x) (((x) >> S_H4EGS) & M_H4EGS)
66464 
66465 #define S_H4ESN_READWRITE    5
66466 #define V_H4ESN_READWRITE(x) ((x) << S_H4ESN_READWRITE)
66467 #define F_H4ESN_READWRITE    V_H4ESN_READWRITE(1U)
66468 
66469 #define S_H4ESN_READONLY    4
66470 #define V_H4ESN_READONLY(x) ((x) << S_H4ESN_READONLY)
66471 #define F_H4ESN_READONLY    V_H4ESN_READONLY(1U)
66472 
66473 #define A_MAC_PORT_RX_LINKA_DFE_H5 0x32d4
66474 
66475 #define S_H5OGS    14
66476 #define M_H5OGS    0x3U
66477 #define V_H5OGS(x) ((x) << S_H5OGS)
66478 #define G_H5OGS(x) (((x) >> S_H5OGS) & M_H5OGS)
66479 
66480 #define S_H5OSN_READWRITE    13
66481 #define V_H5OSN_READWRITE(x) ((x) << S_H5OSN_READWRITE)
66482 #define F_H5OSN_READWRITE    V_H5OSN_READWRITE(1U)
66483 
66484 #define S_H5OSN_READONLY    12
66485 #define V_H5OSN_READONLY(x) ((x) << S_H5OSN_READONLY)
66486 #define F_H5OSN_READONLY    V_H5OSN_READONLY(1U)
66487 
66488 #define S_H5EGS    6
66489 #define M_H5EGS    0x3U
66490 #define V_H5EGS(x) ((x) << S_H5EGS)
66491 #define G_H5EGS(x) (((x) >> S_H5EGS) & M_H5EGS)
66492 
66493 #define S_H5ESN_READWRITE    5
66494 #define V_H5ESN_READWRITE(x) ((x) << S_H5ESN_READWRITE)
66495 #define F_H5ESN_READWRITE    V_H5ESN_READWRITE(1U)
66496 
66497 #define S_H5ESN_READONLY    4
66498 #define V_H5ESN_READONLY(x) ((x) << S_H5ESN_READONLY)
66499 #define F_H5ESN_READONLY    V_H5ESN_READONLY(1U)
66500 
66501 #define A_MAC_PORT_RX_LINKA_DFE_H6_AND_H7 0x32d8
66502 
66503 #define S_H7GS    14
66504 #define M_H7GS    0x3U
66505 #define V_H7GS(x) ((x) << S_H7GS)
66506 #define G_H7GS(x) (((x) >> S_H7GS) & M_H7GS)
66507 
66508 #define S_H7SN_READWRITE    13
66509 #define V_H7SN_READWRITE(x) ((x) << S_H7SN_READWRITE)
66510 #define F_H7SN_READWRITE    V_H7SN_READWRITE(1U)
66511 
66512 #define S_H7SN_READONLY    12
66513 #define V_H7SN_READONLY(x) ((x) << S_H7SN_READONLY)
66514 #define F_H7SN_READONLY    V_H7SN_READONLY(1U)
66515 
66516 #define S_H7MAG    8
66517 #define M_H7MAG    0xfU
66518 #define V_H7MAG(x) ((x) << S_H7MAG)
66519 #define G_H7MAG(x) (((x) >> S_H7MAG) & M_H7MAG)
66520 
66521 #define S_H6GS    6
66522 #define M_H6GS    0x3U
66523 #define V_H6GS(x) ((x) << S_H6GS)
66524 #define G_H6GS(x) (((x) >> S_H6GS) & M_H6GS)
66525 
66526 #define S_H6SN_READWRITE    5
66527 #define V_H6SN_READWRITE(x) ((x) << S_H6SN_READWRITE)
66528 #define F_H6SN_READWRITE    V_H6SN_READWRITE(1U)
66529 
66530 #define S_H6SN_READONLY    4
66531 #define V_H6SN_READONLY(x) ((x) << S_H6SN_READONLY)
66532 #define F_H6SN_READONLY    V_H6SN_READONLY(1U)
66533 
66534 #define S_H6MAG    0
66535 #define M_H6MAG    0xfU
66536 #define V_H6MAG(x) ((x) << S_H6MAG)
66537 #define G_H6MAG(x) (((x) >> S_H6MAG) & M_H6MAG)
66538 
66539 #define A_MAC_PORT_RX_LINKA_DFE_H8_AND_H9 0x32dc
66540 
66541 #define S_H9GS    14
66542 #define M_H9GS    0x3U
66543 #define V_H9GS(x) ((x) << S_H9GS)
66544 #define G_H9GS(x) (((x) >> S_H9GS) & M_H9GS)
66545 
66546 #define S_H9SN_READWRITE    13
66547 #define V_H9SN_READWRITE(x) ((x) << S_H9SN_READWRITE)
66548 #define F_H9SN_READWRITE    V_H9SN_READWRITE(1U)
66549 
66550 #define S_H9SN_READONLY    12
66551 #define V_H9SN_READONLY(x) ((x) << S_H9SN_READONLY)
66552 #define F_H9SN_READONLY    V_H9SN_READONLY(1U)
66553 
66554 #define S_H9MAG    8
66555 #define M_H9MAG    0xfU
66556 #define V_H9MAG(x) ((x) << S_H9MAG)
66557 #define G_H9MAG(x) (((x) >> S_H9MAG) & M_H9MAG)
66558 
66559 #define S_H8GS    6
66560 #define M_H8GS    0x3U
66561 #define V_H8GS(x) ((x) << S_H8GS)
66562 #define G_H8GS(x) (((x) >> S_H8GS) & M_H8GS)
66563 
66564 #define S_H8SN_READWRITE    5
66565 #define V_H8SN_READWRITE(x) ((x) << S_H8SN_READWRITE)
66566 #define F_H8SN_READWRITE    V_H8SN_READWRITE(1U)
66567 
66568 #define S_H8SN_READONLY    4
66569 #define V_H8SN_READONLY(x) ((x) << S_H8SN_READONLY)
66570 #define F_H8SN_READONLY    V_H8SN_READONLY(1U)
66571 
66572 #define S_H8MAG    0
66573 #define M_H8MAG    0xfU
66574 #define V_H8MAG(x) ((x) << S_H8MAG)
66575 #define G_H8MAG(x) (((x) >> S_H8MAG) & M_H8MAG)
66576 
66577 #define A_MAC_PORT_RX_LINKA_DFE_H10_AND_H11 0x32e0
66578 
66579 #define S_H11GS    14
66580 #define M_H11GS    0x3U
66581 #define V_H11GS(x) ((x) << S_H11GS)
66582 #define G_H11GS(x) (((x) >> S_H11GS) & M_H11GS)
66583 
66584 #define S_H11SN_READWRITE    13
66585 #define V_H11SN_READWRITE(x) ((x) << S_H11SN_READWRITE)
66586 #define F_H11SN_READWRITE    V_H11SN_READWRITE(1U)
66587 
66588 #define S_H11SN_READONLY    12
66589 #define V_H11SN_READONLY(x) ((x) << S_H11SN_READONLY)
66590 #define F_H11SN_READONLY    V_H11SN_READONLY(1U)
66591 
66592 #define S_H11MAG    8
66593 #define M_H11MAG    0xfU
66594 #define V_H11MAG(x) ((x) << S_H11MAG)
66595 #define G_H11MAG(x) (((x) >> S_H11MAG) & M_H11MAG)
66596 
66597 #define S_H10GS    6
66598 #define M_H10GS    0x3U
66599 #define V_H10GS(x) ((x) << S_H10GS)
66600 #define G_H10GS(x) (((x) >> S_H10GS) & M_H10GS)
66601 
66602 #define S_H10SN_READWRITE    5
66603 #define V_H10SN_READWRITE(x) ((x) << S_H10SN_READWRITE)
66604 #define F_H10SN_READWRITE    V_H10SN_READWRITE(1U)
66605 
66606 #define S_H10SN_READONLY    4
66607 #define V_H10SN_READONLY(x) ((x) << S_H10SN_READONLY)
66608 #define F_H10SN_READONLY    V_H10SN_READONLY(1U)
66609 
66610 #define S_H10MAG    0
66611 #define M_H10MAG    0xfU
66612 #define V_H10MAG(x) ((x) << S_H10MAG)
66613 #define G_H10MAG(x) (((x) >> S_H10MAG) & M_H10MAG)
66614 
66615 #define A_MAC_PORT_RX_LINKA_DFE_H12 0x32e4
66616 
66617 #define S_H12GS    6
66618 #define M_H12GS    0x3U
66619 #define V_H12GS(x) ((x) << S_H12GS)
66620 #define G_H12GS(x) (((x) >> S_H12GS) & M_H12GS)
66621 
66622 #define S_H12SN_READWRITE    5
66623 #define V_H12SN_READWRITE(x) ((x) << S_H12SN_READWRITE)
66624 #define F_H12SN_READWRITE    V_H12SN_READWRITE(1U)
66625 
66626 #define S_H12SN_READONLY    4
66627 #define V_H12SN_READONLY(x) ((x) << S_H12SN_READONLY)
66628 #define F_H12SN_READONLY    V_H12SN_READONLY(1U)
66629 
66630 #define S_H12MAG    0
66631 #define M_H12MAG    0xfU
66632 #define V_H12MAG(x) ((x) << S_H12MAG)
66633 #define G_H12MAG(x) (((x) >> S_H12MAG) & M_H12MAG)
66634 
66635 #define A_MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS_2 0x32e4
66636 
66637 #define S_STNDBYSTAT    15
66638 #define V_STNDBYSTAT(x) ((x) << S_STNDBYSTAT)
66639 #define F_STNDBYSTAT    V_STNDBYSTAT(1U)
66640 
66641 #define S_CALSDONE    14
66642 #define V_CALSDONE(x) ((x) << S_CALSDONE)
66643 #define F_CALSDONE    V_CALSDONE(1U)
66644 
66645 #define S_ACISRCCMP    5
66646 #define V_ACISRCCMP(x) ((x) << S_ACISRCCMP)
66647 #define F_ACISRCCMP    V_ACISRCCMP(1U)
66648 
66649 #define S_PRBSOFFCMP    4
66650 #define V_PRBSOFFCMP(x) ((x) << S_PRBSOFFCMP)
66651 #define F_PRBSOFFCMP    V_PRBSOFFCMP(1U)
66652 
66653 #define S_CLKALGNCMP    3
66654 #define V_CLKALGNCMP(x) ((x) << S_CLKALGNCMP)
66655 #define F_CLKALGNCMP    V_CLKALGNCMP(1U)
66656 
66657 #define S_ROTFCMP    2
66658 #define V_ROTFCMP(x) ((x) << S_ROTFCMP)
66659 #define F_ROTFCMP    V_ROTFCMP(1U)
66660 
66661 #define S_DCDCMP    1
66662 #define V_DCDCMP(x) ((x) << S_DCDCMP)
66663 #define F_DCDCMP    V_DCDCMP(1U)
66664 
66665 #define S_QCCCMP    0
66666 #define V_QCCCMP(x) ((x) << S_QCCCMP)
66667 #define F_QCCCMP    V_QCCCMP(1U)
66668 
66669 #define A_MAC_PORT_RX_LINKA_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x32e8
66670 
66671 #define S_FCSADJ    6
66672 #define V_FCSADJ(x) ((x) << S_FCSADJ)
66673 #define F_FCSADJ    V_FCSADJ(1U)
66674 
66675 #define S_CSIND    3
66676 #define M_CSIND    0x3U
66677 #define V_CSIND(x) ((x) << S_CSIND)
66678 #define G_CSIND(x) (((x) >> S_CSIND) & M_CSIND)
66679 
66680 #define S_CSVAL    0
66681 #define M_CSVAL    0x7U
66682 #define V_CSVAL(x) ((x) << S_CSVAL)
66683 #define G_CSVAL(x) (((x) >> S_CSVAL) & M_CSVAL)
66684 
66685 #define A_MAC_PORT_RX_LINKA_RECEIVER_DCD_CONTROL 0x32ec
66686 
66687 #define S_DCDTMDOUT    15
66688 #define V_DCDTMDOUT(x) ((x) << S_DCDTMDOUT)
66689 #define F_DCDTMDOUT    V_DCDTMDOUT(1U)
66690 
66691 #define S_DCDTOEN    14
66692 #define V_DCDTOEN(x) ((x) << S_DCDTOEN)
66693 #define F_DCDTOEN    V_DCDTOEN(1U)
66694 
66695 #define S_DCDLOCK    13
66696 #define V_DCDLOCK(x) ((x) << S_DCDLOCK)
66697 #define F_DCDLOCK    V_DCDLOCK(1U)
66698 
66699 #define S_DCDSTEP    11
66700 #define M_DCDSTEP    0x3U
66701 #define V_DCDSTEP(x) ((x) << S_DCDSTEP)
66702 #define G_DCDSTEP(x) (((x) >> S_DCDSTEP) & M_DCDSTEP)
66703 
66704 #define S_DCDALTWPDIS    10
66705 #define V_DCDALTWPDIS(x) ((x) << S_DCDALTWPDIS)
66706 #define F_DCDALTWPDIS    V_DCDALTWPDIS(1U)
66707 
66708 #define S_DCDOVRDEN    9
66709 #define V_DCDOVRDEN(x) ((x) << S_DCDOVRDEN)
66710 #define F_DCDOVRDEN    V_DCDOVRDEN(1U)
66711 
66712 #define S_DCCAOVRDEN    8
66713 #define V_DCCAOVRDEN(x) ((x) << S_DCCAOVRDEN)
66714 #define F_DCCAOVRDEN    V_DCCAOVRDEN(1U)
66715 
66716 #define S_DCDSIGN    6
66717 #define M_DCDSIGN    0x3U
66718 #define V_DCDSIGN(x) ((x) << S_DCDSIGN)
66719 #define G_DCDSIGN(x) (((x) >> S_DCDSIGN) & M_DCDSIGN)
66720 
66721 #define S_DCDAMP    0
66722 #define M_DCDAMP    0x3fU
66723 #define V_DCDAMP(x) ((x) << S_DCDAMP)
66724 #define G_DCDAMP(x) (((x) >> S_DCDAMP) & M_DCDAMP)
66725 
66726 #define A_MAC_PORT_RX_LINKA_RECEIVER_DCC_CONTROL 0x32f0
66727 
66728 #define S_PRBSMODE    14
66729 #define M_PRBSMODE    0x3U
66730 #define V_PRBSMODE(x) ((x) << S_PRBSMODE)
66731 #define G_PRBSMODE(x) (((x) >> S_PRBSMODE) & M_PRBSMODE)
66732 
66733 #define S_RX_LINKA_DCCSTEP_RXCTL    10
66734 #define M_RX_LINKA_DCCSTEP_RXCTL    0x3U
66735 #define V_RX_LINKA_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKA_DCCSTEP_RXCTL)
66736 #define G_RX_LINKA_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKA_DCCSTEP_RXCTL) & M_RX_LINKA_DCCSTEP_RXCTL)
66737 
66738 #define S_DCCOVRDEN    9
66739 #define V_DCCOVRDEN(x) ((x) << S_DCCOVRDEN)
66740 #define F_DCCOVRDEN    V_DCCOVRDEN(1U)
66741 
66742 #define S_RX_LINKA_DCCLOCK_RXCTL    8
66743 #define V_RX_LINKA_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKA_DCCLOCK_RXCTL)
66744 #define F_RX_LINKA_DCCLOCK_RXCTL    V_RX_LINKA_DCCLOCK_RXCTL(1U)
66745 
66746 #define A_MAC_PORT_RX_LINKA_RECEIVER_QCC_CONTROL 0x32f4
66747 
66748 #define S_DCCQCCMODE    15
66749 #define V_DCCQCCMODE(x) ((x) << S_DCCQCCMODE)
66750 #define F_DCCQCCMODE    V_DCCQCCMODE(1U)
66751 
66752 #define S_DCCQCCDYN    14
66753 #define V_DCCQCCDYN(x) ((x) << S_DCCQCCDYN)
66754 #define F_DCCQCCDYN    V_DCCQCCDYN(1U)
66755 
66756 #define S_DCCQCCHOLD    13
66757 #define V_DCCQCCHOLD(x) ((x) << S_DCCQCCHOLD)
66758 #define F_DCCQCCHOLD    V_DCCQCCHOLD(1U)
66759 
66760 #define S_QCCSTEP    10
66761 #define M_QCCSTEP    0x3U
66762 #define V_QCCSTEP(x) ((x) << S_QCCSTEP)
66763 #define G_QCCSTEP(x) (((x) >> S_QCCSTEP) & M_QCCSTEP)
66764 
66765 #define S_QCCOVRDEN    9
66766 #define V_QCCOVRDEN(x) ((x) << S_QCCOVRDEN)
66767 #define F_QCCOVRDEN    V_QCCOVRDEN(1U)
66768 
66769 #define S_QCCLOCK    8
66770 #define V_QCCLOCK(x) ((x) << S_QCCLOCK)
66771 #define F_QCCLOCK    V_QCCLOCK(1U)
66772 
66773 #define S_QCCSIGN    6
66774 #define M_QCCSIGN    0x3U
66775 #define V_QCCSIGN(x) ((x) << S_QCCSIGN)
66776 #define G_QCCSIGN(x) (((x) >> S_QCCSIGN) & M_QCCSIGN)
66777 
66778 #define S_QCDAMP    0
66779 #define M_QCDAMP    0x3fU
66780 #define V_QCDAMP(x) ((x) << S_QCDAMP)
66781 #define G_QCDAMP(x) (((x) >> S_QCDAMP) & M_QCDAMP)
66782 
66783 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2 0x32f8
66784 
66785 #define S_DFEDACLSSD    6
66786 #define V_DFEDACLSSD(x) ((x) << S_DFEDACLSSD)
66787 #define F_DFEDACLSSD    V_DFEDACLSSD(1U)
66788 
66789 #define S_SDLSSD    5
66790 #define V_SDLSSD(x) ((x) << S_SDLSSD)
66791 #define F_SDLSSD    V_SDLSSD(1U)
66792 
66793 #define S_DFEOBSBIAS    4
66794 #define V_DFEOBSBIAS(x) ((x) << S_DFEOBSBIAS)
66795 #define F_DFEOBSBIAS    V_DFEOBSBIAS(1U)
66796 
66797 #define S_GBOFSTLSSD    3
66798 #define V_GBOFSTLSSD(x) ((x) << S_GBOFSTLSSD)
66799 #define F_GBOFSTLSSD    V_GBOFSTLSSD(1U)
66800 
66801 #define S_RXDOBS    2
66802 #define V_RXDOBS(x) ((x) << S_RXDOBS)
66803 #define F_RXDOBS    V_RXDOBS(1U)
66804 
66805 #define S_ACJZPT    1
66806 #define V_ACJZPT(x) ((x) << S_ACJZPT)
66807 #define F_ACJZPT    V_ACJZPT(1U)
66808 
66809 #define S_ACJZNT    0
66810 #define V_ACJZNT(x) ((x) << S_ACJZNT)
66811 #define F_ACJZNT    V_ACJZNT(1U)
66812 
66813 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x32f8
66814 
66815 #define S_TSTCMP    15
66816 #define V_TSTCMP(x) ((x) << S_TSTCMP)
66817 #define F_TSTCMP    V_TSTCMP(1U)
66818 
66819 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1 0x32fc
66820 
66821 #define S_PHSLOCK    10
66822 #define V_PHSLOCK(x) ((x) << S_PHSLOCK)
66823 #define F_PHSLOCK    V_PHSLOCK(1U)
66824 
66825 #define S_TESTMODE    9
66826 #define V_TESTMODE(x) ((x) << S_TESTMODE)
66827 #define F_TESTMODE    V_TESTMODE(1U)
66828 
66829 #define S_CALMODE    8
66830 #define V_CALMODE(x) ((x) << S_CALMODE)
66831 #define F_CALMODE    V_CALMODE(1U)
66832 
66833 #define S_AMPSEL    7
66834 #define V_AMPSEL(x) ((x) << S_AMPSEL)
66835 #define F_AMPSEL    V_AMPSEL(1U)
66836 
66837 #define S_WHICHNRZ    6
66838 #define V_WHICHNRZ(x) ((x) << S_WHICHNRZ)
66839 #define F_WHICHNRZ    V_WHICHNRZ(1U)
66840 
66841 #define S_BANKA    5
66842 #define V_BANKA(x) ((x) << S_BANKA)
66843 #define F_BANKA    V_BANKA(1U)
66844 
66845 #define S_BANKB    4
66846 #define V_BANKB(x) ((x) << S_BANKB)
66847 #define F_BANKB    V_BANKB(1U)
66848 
66849 #define S_ACJPDP    3
66850 #define V_ACJPDP(x) ((x) << S_ACJPDP)
66851 #define F_ACJPDP    V_ACJPDP(1U)
66852 
66853 #define S_ACJPDN    2
66854 #define V_ACJPDN(x) ((x) << S_ACJPDN)
66855 #define F_ACJPDN    V_ACJPDN(1U)
66856 
66857 #define S_LSSDT    1
66858 #define V_LSSDT(x) ((x) << S_LSSDT)
66859 #define F_LSSDT    V_LSSDT(1U)
66860 
66861 #define S_MTHOLD    0
66862 #define V_MTHOLD(x) ((x) << S_MTHOLD)
66863 #define F_MTHOLD    V_MTHOLD(1U)
66864 
66865 #define S_CALMODEEDGE    14
66866 #define V_CALMODEEDGE(x) ((x) << S_CALMODEEDGE)
66867 #define F_CALMODEEDGE    V_CALMODEEDGE(1U)
66868 
66869 #define S_TESTCAP    13
66870 #define V_TESTCAP(x) ((x) << S_TESTCAP)
66871 #define F_TESTCAP    V_TESTCAP(1U)
66872 
66873 #define S_SNAPEN    12
66874 #define V_SNAPEN(x) ((x) << S_SNAPEN)
66875 #define F_SNAPEN    V_SNAPEN(1U)
66876 
66877 #define S_ASYNCDIR    11
66878 #define V_ASYNCDIR(x) ((x) << S_ASYNCDIR)
66879 #define F_ASYNCDIR    V_ASYNCDIR(1U)
66880 
66881 #define A_MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE 0x3300
66882 #define A_MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL 0x3304
66883 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL 0x3308
66884 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL 0x330c
66885 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1 0x3310
66886 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2 0x3314
66887 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3318
66888 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x331c
66889 #define A_MAC_PORT_RX_LINKB_DFE_CONTROL 0x3320
66890 #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1 0x3324
66891 #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2 0x3328
66892 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1 0x332c
66893 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2 0x3330
66894 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3 0x3334
66895 #define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1 0x3338
66896 #define A_MAC_PORT_RX_LINKB_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3338
66897 #define A_MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_1 0x333c
66898 #define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3 0x3340
66899 #define A_MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_2 0x3340
66900 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3344
66901 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN 0x3348
66902 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ 0x334c
66903 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN 0x334c
66904 #define A_MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL 0x3350
66905 #define A_MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_CONTROL 0x3354
66906 #define A_MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_VALUE 0x3358
66907 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x335c
66908 #define A_MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET 0x335c
66909 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3360
66910 #define A_MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3360
66911 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3364
66912 #define A_MAC_PORT_RX_LINKB_PEAKED_INTEGRATOR 0x3364
66913 #define A_MAC_PORT_RX_LINKB_CDR_ANALOG_SWITCH 0x3368
66914 #define A_MAC_PORT_RX_LINKB_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x336c
66915 #define A_MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3370
66916 #define A_MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC 0x3374
66917 #define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS 0x3378
66918 
66919 #define S_RX_LINKB_ACCCMP_RIS    11
66920 #define V_RX_LINKB_ACCCMP_RIS(x) ((x) << S_RX_LINKB_ACCCMP_RIS)
66921 #define F_RX_LINKB_ACCCMP_RIS    V_RX_LINKB_ACCCMP_RIS(1U)
66922 
66923 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1 0x337c
66924 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2 0x3380
66925 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2 0x3384
66926 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_CHANNEL 0x3384
66927 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2 0x3388
66928 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_VALUE 0x3388
66929 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4 0x338c
66930 #define A_MAC_PORT_RX_LINKB_H_COEFFICIENBT_BIST 0x338c
66931 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4 0x3390
66932 #define A_MAC_PORT_RX_LINKB_AC_CAPACITOR_BIST 0x3390
66933 
66934 #define S_RX_LINKB_ACCCMP_BIST    13
66935 #define V_RX_LINKB_ACCCMP_BIST(x) ((x) << S_RX_LINKB_ACCCMP_BIST)
66936 #define F_RX_LINKB_ACCCMP_BIST    V_RX_LINKB_ACCCMP_BIST(1U)
66937 
66938 #define A_MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET 0x3394
66939 #define A_MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL 0x3398
66940 #define A_MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL_REGISTER 0x3398
66941 #define A_MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL 0x339c
66942 #define A_MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH 0x33a0
66943 #define A_MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET 0x33a4
66944 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL 0x33a8
66945 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS 0x33ac
66946 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT 0x33b0
66947 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x33b4
66948 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x33b8
66949 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_3 0x33bc
66950 #define A_MAC_PORT_RX_LINKB_DFE_TAP_ENABLE 0x33c0
66951 #define A_MAC_PORT_RX_LINKB_DFE_TAP_CONTROL 0x33c0
66952 
66953 #define S_RX_LINKB_INDEX_DFE_TC    0
66954 #define M_RX_LINKB_INDEX_DFE_TC    0xfU
66955 #define V_RX_LINKB_INDEX_DFE_TC(x) ((x) << S_RX_LINKB_INDEX_DFE_TC)
66956 #define G_RX_LINKB_INDEX_DFE_TC(x) (((x) >> S_RX_LINKB_INDEX_DFE_TC) & M_RX_LINKB_INDEX_DFE_TC)
66957 
66958 #define A_MAC_PORT_RX_LINKB_DFE_H1 0x33c4
66959 #define A_MAC_PORT_RX_LINKB_DFE_TAP 0x33c4
66960 
66961 #define S_RX_LINKB_INDEX_DFE_TAP    0
66962 #define M_RX_LINKB_INDEX_DFE_TAP    0xfU
66963 #define V_RX_LINKB_INDEX_DFE_TAP(x) ((x) << S_RX_LINKB_INDEX_DFE_TAP)
66964 #define G_RX_LINKB_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKB_INDEX_DFE_TAP) & M_RX_LINKB_INDEX_DFE_TAP)
66965 
66966 #define A_MAC_PORT_RX_LINKB_DFE_H2 0x33c8
66967 #define A_MAC_PORT_RX_LINKB_DFE_H3 0x33cc
66968 #define A_MAC_PORT_RX_LINKB_DFE_H4 0x33d0
66969 #define A_MAC_PORT_RX_LINKB_DFE_H5 0x33d4
66970 #define A_MAC_PORT_RX_LINKB_DFE_H6_AND_H7 0x33d8
66971 #define A_MAC_PORT_RX_LINKB_DFE_H8_AND_H9 0x33dc
66972 #define A_MAC_PORT_RX_LINKB_DFE_H10_AND_H11 0x33e0
66973 #define A_MAC_PORT_RX_LINKB_DFE_H12 0x33e4
66974 #define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS_2 0x33e4
66975 #define A_MAC_PORT_RX_LINKB_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x33e8
66976 #define A_MAC_PORT_RX_LINKB_RECEIVER_DCD_CONTROL 0x33ec
66977 #define A_MAC_PORT_RX_LINKB_RECEIVER_DCC_CONTROL 0x33f0
66978 
66979 #define S_RX_LINKB_DCCSTEP_RXCTL    10
66980 #define M_RX_LINKB_DCCSTEP_RXCTL    0x3U
66981 #define V_RX_LINKB_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKB_DCCSTEP_RXCTL)
66982 #define G_RX_LINKB_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKB_DCCSTEP_RXCTL) & M_RX_LINKB_DCCSTEP_RXCTL)
66983 
66984 #define S_RX_LINKB_DCCLOCK_RXCTL    8
66985 #define V_RX_LINKB_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKB_DCCLOCK_RXCTL)
66986 #define F_RX_LINKB_DCCLOCK_RXCTL    V_RX_LINKB_DCCLOCK_RXCTL(1U)
66987 
66988 #define A_MAC_PORT_RX_LINKB_RECEIVER_QCC_CONTROL 0x33f4
66989 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2 0x33f8
66990 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x33f8
66991 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1 0x33fc
66992 #define A_MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE 0x3400
66993 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL 0x3404
66994 #define A_MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL 0x3408
66995 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL 0x340c
66996 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3410
66997 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3414
66998 #define A_MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3418
66999 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x341c
67000 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT 0x3420
67001 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT 0x3424
67002 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT 0x3428
67003 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_3_COEFFICIENT 0x342c
67004 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE 0x3430
67005 #define A_MAC_PORT_TX_LINKC_TRANSMIT_POLARITY 0x3434
67006 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3438
67007 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x343c
67008 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3440
67009 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3440
67010 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3444
67011 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3444
67012 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3448
67013 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3448
67014 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x344c
67015 #define A_MAC_PORT_TX_LINKC_TRANSMIT_APPLIED_TUNE_REGISTER 0x3450
67016 #define A_MAC_PORT_TX_LINKC_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3458
67017 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3460
67018 #define A_MAC_PORT_TX_LINKC_TRANSMIT_4X_SEGMENT_APPLIED 0x3460
67019 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3464
67020 #define A_MAC_PORT_TX_LINKC_TRANSMIT_2X_SEGMENT_APPLIED 0x3464
67021 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3468
67022 #define A_MAC_PORT_TX_LINKC_TRANSMIT_1X_SEGMENT_APPLIED 0x3468
67023 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x346c
67024 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3470
67025 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3470
67026 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3474
67027 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3474
67028 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3478
67029 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x347c
67030 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3480
67031 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3484
67032 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3488
67033 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3488
67034 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x348c
67035 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x348c
67036 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE 0x3490
67037 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED 0x3494
67038 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT 0x3498
67039 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL 0x349c
67040 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x34a0
67041 
67042 #define S_TX_LINKC_DCCSTEP_CTL    6
67043 #define M_TX_LINKC_DCCSTEP_CTL    0x3U
67044 #define V_TX_LINKC_DCCSTEP_CTL(x) ((x) << S_TX_LINKC_DCCSTEP_CTL)
67045 #define G_TX_LINKC_DCCSTEP_CTL(x) (((x) >> S_TX_LINKC_DCCSTEP_CTL) & M_TX_LINKC_DCCSTEP_CTL)
67046 
67047 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE 0x34a4
67048 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED 0x34a8
67049 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT 0x34ac
67050 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_OVERRIDE 0x34c0
67051 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_OVERRIDE 0x34c8
67052 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X_OVERRIDE 0x34cc
67053 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_1X_OVERRIDE 0x34d0
67054 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x34d8
67055 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x34dc
67056 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x34e0
67057 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_5 0x34ec
67058 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4 0x34f0
67059 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3 0x34f4
67060 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2 0x34f8
67061 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1 0x34fc
67062 #define A_MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE 0x3500
67063 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL 0x3504
67064 #define A_MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL 0x3508
67065 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL 0x350c
67066 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3510
67067 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3514
67068 #define A_MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3518
67069 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x351c
67070 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT 0x3520
67071 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT 0x3524
67072 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT 0x3528
67073 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_3_COEFFICIENT 0x352c
67074 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE 0x3530
67075 #define A_MAC_PORT_TX_LINKD_TRANSMIT_POLARITY 0x3534
67076 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3538
67077 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x353c
67078 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3540
67079 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3540
67080 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3544
67081 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3544
67082 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3548
67083 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3548
67084 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x354c
67085 #define A_MAC_PORT_TX_LINKD_TRANSMIT_APPLIED_TUNE_REGISTER 0x3550
67086 #define A_MAC_PORT_TX_LINKD_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3558
67087 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3560
67088 #define A_MAC_PORT_TX_LINKD_TRANSMIT_4X_SEGMENT_APPLIED 0x3560
67089 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3564
67090 #define A_MAC_PORT_TX_LINKD_TRANSMIT_2X_SEGMENT_APPLIED 0x3564
67091 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3568
67092 #define A_MAC_PORT_TX_LINKD_TRANSMIT_1X_SEGMENT_APPLIED 0x3568
67093 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x356c
67094 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3570
67095 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3570
67096 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3574
67097 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3574
67098 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3578
67099 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x357c
67100 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3580
67101 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3584
67102 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3588
67103 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3588
67104 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x358c
67105 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x358c
67106 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE 0x3590
67107 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED 0x3594
67108 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT 0x3598
67109 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL 0x359c
67110 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x35a0
67111 
67112 #define S_TX_LINKD_DCCSTEP_CTL    6
67113 #define M_TX_LINKD_DCCSTEP_CTL    0x3U
67114 #define V_TX_LINKD_DCCSTEP_CTL(x) ((x) << S_TX_LINKD_DCCSTEP_CTL)
67115 #define G_TX_LINKD_DCCSTEP_CTL(x) (((x) >> S_TX_LINKD_DCCSTEP_CTL) & M_TX_LINKD_DCCSTEP_CTL)
67116 
67117 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE 0x35a4
67118 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED 0x35a8
67119 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT 0x35ac
67120 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_OVERRIDE 0x35c0
67121 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_OVERRIDE 0x35c8
67122 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X_OVERRIDE 0x35cc
67123 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_1X_OVERRIDE 0x35d0
67124 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x35d8
67125 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x35dc
67126 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x35e0
67127 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_5 0x35ec
67128 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4 0x35f0
67129 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3 0x35f4
67130 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2 0x35f8
67131 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1 0x35fc
67132 #define A_MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE 0x3600
67133 #define A_MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL 0x3604
67134 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL 0x3608
67135 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL 0x360c
67136 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1 0x3610
67137 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2 0x3614
67138 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3618
67139 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x361c
67140 #define A_MAC_PORT_RX_LINKC_DFE_CONTROL 0x3620
67141 #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1 0x3624
67142 #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2 0x3628
67143 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1 0x362c
67144 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2 0x3630
67145 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3 0x3634
67146 #define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1 0x3638
67147 #define A_MAC_PORT_RX_LINKC_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3638
67148 #define A_MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_1 0x363c
67149 #define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3 0x3640
67150 #define A_MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_2 0x3640
67151 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3644
67152 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN 0x3648
67153 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ 0x364c
67154 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN 0x364c
67155 #define A_MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL 0x3650
67156 #define A_MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_CONTROL 0x3654
67157 #define A_MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_VALUE 0x3658
67158 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x365c
67159 #define A_MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET 0x365c
67160 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3660
67161 #define A_MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3660
67162 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3664
67163 #define A_MAC_PORT_RX_LINKC_PEAKED_INTEGRATOR 0x3664
67164 #define A_MAC_PORT_RX_LINKC_CDR_ANALOG_SWITCH 0x3668
67165 #define A_MAC_PORT_RX_LINKC_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x366c
67166 #define A_MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3670
67167 #define A_MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC 0x3674
67168 #define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS 0x3678
67169 
67170 #define S_RX_LINKC_ACCCMP_RIS    11
67171 #define V_RX_LINKC_ACCCMP_RIS(x) ((x) << S_RX_LINKC_ACCCMP_RIS)
67172 #define F_RX_LINKC_ACCCMP_RIS    V_RX_LINKC_ACCCMP_RIS(1U)
67173 
67174 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1 0x367c
67175 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2 0x3680
67176 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2 0x3684
67177 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_CHANNEL 0x3684
67178 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2 0x3688
67179 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_VALUE 0x3688
67180 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4 0x368c
67181 #define A_MAC_PORT_RX_LINKC_H_COEFFICIENBT_BIST 0x368c
67182 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4 0x3690
67183 #define A_MAC_PORT_RX_LINKC_AC_CAPACITOR_BIST 0x3690
67184 
67185 #define S_RX_LINKC_ACCCMP_BIST    13
67186 #define V_RX_LINKC_ACCCMP_BIST(x) ((x) << S_RX_LINKC_ACCCMP_BIST)
67187 #define F_RX_LINKC_ACCCMP_BIST    V_RX_LINKC_ACCCMP_BIST(1U)
67188 
67189 #define A_MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET 0x3694
67190 #define A_MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL 0x3698
67191 #define A_MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL_REGISTER 0x3698
67192 #define A_MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL 0x369c
67193 #define A_MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH 0x36a0
67194 #define A_MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET 0x36a4
67195 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL 0x36a8
67196 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS 0x36ac
67197 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT 0x36b0
67198 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x36b4
67199 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x36b8
67200 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_3 0x36bc
67201 #define A_MAC_PORT_RX_LINKC_DFE_TAP_ENABLE 0x36c0
67202 #define A_MAC_PORT_RX_LINKC_DFE_TAP_CONTROL 0x36c0
67203 
67204 #define S_RX_LINKC_INDEX_DFE_TC    0
67205 #define M_RX_LINKC_INDEX_DFE_TC    0xfU
67206 #define V_RX_LINKC_INDEX_DFE_TC(x) ((x) << S_RX_LINKC_INDEX_DFE_TC)
67207 #define G_RX_LINKC_INDEX_DFE_TC(x) (((x) >> S_RX_LINKC_INDEX_DFE_TC) & M_RX_LINKC_INDEX_DFE_TC)
67208 
67209 #define A_MAC_PORT_RX_LINKC_DFE_H1 0x36c4
67210 #define A_MAC_PORT_RX_LINKC_DFE_TAP 0x36c4
67211 
67212 #define S_RX_LINKC_INDEX_DFE_TAP    0
67213 #define M_RX_LINKC_INDEX_DFE_TAP    0xfU
67214 #define V_RX_LINKC_INDEX_DFE_TAP(x) ((x) << S_RX_LINKC_INDEX_DFE_TAP)
67215 #define G_RX_LINKC_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKC_INDEX_DFE_TAP) & M_RX_LINKC_INDEX_DFE_TAP)
67216 
67217 #define A_MAC_PORT_RX_LINKC_DFE_H2 0x36c8
67218 #define A_MAC_PORT_RX_LINKC_DFE_H3 0x36cc
67219 #define A_MAC_PORT_RX_LINKC_DFE_H4 0x36d0
67220 #define A_MAC_PORT_RX_LINKC_DFE_H5 0x36d4
67221 #define A_MAC_PORT_RX_LINKC_DFE_H6_AND_H7 0x36d8
67222 #define A_MAC_PORT_RX_LINKC_DFE_H8_AND_H9 0x36dc
67223 #define A_MAC_PORT_RX_LINKC_DFE_H10_AND_H11 0x36e0
67224 #define A_MAC_PORT_RX_LINKC_DFE_H12 0x36e4
67225 #define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS_2 0x36e4
67226 #define A_MAC_PORT_RX_LINKC_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x36e8
67227 #define A_MAC_PORT_RX_LINKC_RECEIVER_DCD_CONTROL 0x36ec
67228 #define A_MAC_PORT_RX_LINKC_RECEIVER_DCC_CONTROL 0x36f0
67229 
67230 #define S_RX_LINKC_DCCSTEP_RXCTL    10
67231 #define M_RX_LINKC_DCCSTEP_RXCTL    0x3U
67232 #define V_RX_LINKC_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKC_DCCSTEP_RXCTL)
67233 #define G_RX_LINKC_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKC_DCCSTEP_RXCTL) & M_RX_LINKC_DCCSTEP_RXCTL)
67234 
67235 #define S_RX_LINKC_DCCLOCK_RXCTL    8
67236 #define V_RX_LINKC_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKC_DCCLOCK_RXCTL)
67237 #define F_RX_LINKC_DCCLOCK_RXCTL    V_RX_LINKC_DCCLOCK_RXCTL(1U)
67238 
67239 #define A_MAC_PORT_RX_LINKC_RECEIVER_QCC_CONTROL 0x36f4
67240 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2 0x36f8
67241 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x36f8
67242 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1 0x36fc
67243 #define A_MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE 0x3700
67244 #define A_MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL 0x3704
67245 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL 0x3708
67246 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL 0x370c
67247 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1 0x3710
67248 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2 0x3714
67249 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3718
67250 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x371c
67251 #define A_MAC_PORT_RX_LINKD_DFE_CONTROL 0x3720
67252 #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1 0x3724
67253 #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2 0x3728
67254 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1 0x372c
67255 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2 0x3730
67256 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3 0x3734
67257 #define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1 0x3738
67258 #define A_MAC_PORT_RX_LINKD_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3738
67259 #define A_MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_1 0x373c
67260 #define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3 0x3740
67261 #define A_MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_2 0x3740
67262 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3744
67263 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN 0x3748
67264 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ 0x374c
67265 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN 0x374c
67266 #define A_MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL 0x3750
67267 #define A_MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_CONTROL 0x3754
67268 #define A_MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_VALUE 0x3758
67269 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x375c
67270 #define A_MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET 0x375c
67271 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3760
67272 #define A_MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3760
67273 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3764
67274 #define A_MAC_PORT_RX_LINKD_PEAKED_INTEGRATOR 0x3764
67275 #define A_MAC_PORT_RX_LINKD_CDR_ANALOG_SWITCH 0x3768
67276 #define A_MAC_PORT_RX_LINKD_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x376c
67277 #define A_MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3770
67278 #define A_MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC 0x3774
67279 #define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS 0x3778
67280 
67281 #define S_RX_LINKD_ACCCMP_RIS    11
67282 #define V_RX_LINKD_ACCCMP_RIS(x) ((x) << S_RX_LINKD_ACCCMP_RIS)
67283 #define F_RX_LINKD_ACCCMP_RIS    V_RX_LINKD_ACCCMP_RIS(1U)
67284 
67285 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1 0x377c
67286 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2 0x3780
67287 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2 0x3784
67288 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_CHANNEL 0x3784
67289 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2 0x3788
67290 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_VALUE 0x3788
67291 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4 0x378c
67292 #define A_MAC_PORT_RX_LINKD_H_COEFFICIENBT_BIST 0x378c
67293 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4 0x3790
67294 #define A_MAC_PORT_RX_LINKD_AC_CAPACITOR_BIST 0x3790
67295 
67296 #define S_RX_LINKD_ACCCMP_BIST    13
67297 #define V_RX_LINKD_ACCCMP_BIST(x) ((x) << S_RX_LINKD_ACCCMP_BIST)
67298 #define F_RX_LINKD_ACCCMP_BIST    V_RX_LINKD_ACCCMP_BIST(1U)
67299 
67300 #define A_MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET 0x3794
67301 #define A_MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL 0x3798
67302 #define A_MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL_REGISTER 0x3798
67303 #define A_MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL 0x379c
67304 #define A_MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH 0x37a0
67305 #define A_MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET 0x37a4
67306 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL 0x37a8
67307 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS 0x37ac
67308 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT 0x37b0
67309 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x37b4
67310 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x37b8
67311 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_3 0x37bc
67312 #define A_MAC_PORT_RX_LINKD_DFE_TAP_ENABLE 0x37c0
67313 #define A_MAC_PORT_RX_LINKD_DFE_TAP_CONTROL 0x37c0
67314 
67315 #define S_RX_LINKD_INDEX_DFE_TC    0
67316 #define M_RX_LINKD_INDEX_DFE_TC    0xfU
67317 #define V_RX_LINKD_INDEX_DFE_TC(x) ((x) << S_RX_LINKD_INDEX_DFE_TC)
67318 #define G_RX_LINKD_INDEX_DFE_TC(x) (((x) >> S_RX_LINKD_INDEX_DFE_TC) & M_RX_LINKD_INDEX_DFE_TC)
67319 
67320 #define A_MAC_PORT_RX_LINKD_DFE_H1 0x37c4
67321 #define A_MAC_PORT_RX_LINKD_DFE_TAP 0x37c4
67322 
67323 #define S_RX_LINKD_INDEX_DFE_TAP    0
67324 #define M_RX_LINKD_INDEX_DFE_TAP    0xfU
67325 #define V_RX_LINKD_INDEX_DFE_TAP(x) ((x) << S_RX_LINKD_INDEX_DFE_TAP)
67326 #define G_RX_LINKD_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKD_INDEX_DFE_TAP) & M_RX_LINKD_INDEX_DFE_TAP)
67327 
67328 #define A_MAC_PORT_RX_LINKD_DFE_H2 0x37c8
67329 #define A_MAC_PORT_RX_LINKD_DFE_H3 0x37cc
67330 #define A_MAC_PORT_RX_LINKD_DFE_H4 0x37d0
67331 #define A_MAC_PORT_RX_LINKD_DFE_H5 0x37d4
67332 #define A_MAC_PORT_RX_LINKD_DFE_H6_AND_H7 0x37d8
67333 #define A_MAC_PORT_RX_LINKD_DFE_H8_AND_H9 0x37dc
67334 #define A_MAC_PORT_RX_LINKD_DFE_H10_AND_H11 0x37e0
67335 #define A_MAC_PORT_RX_LINKD_DFE_H12 0x37e4
67336 #define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS_2 0x37e4
67337 #define A_MAC_PORT_RX_LINKD_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x37e8
67338 #define A_MAC_PORT_RX_LINKD_RECEIVER_DCD_CONTROL 0x37ec
67339 #define A_MAC_PORT_RX_LINKD_RECEIVER_DCC_CONTROL 0x37f0
67340 
67341 #define S_RX_LINKD_DCCSTEP_RXCTL    10
67342 #define M_RX_LINKD_DCCSTEP_RXCTL    0x3U
67343 #define V_RX_LINKD_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKD_DCCSTEP_RXCTL)
67344 #define G_RX_LINKD_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKD_DCCSTEP_RXCTL) & M_RX_LINKD_DCCSTEP_RXCTL)
67345 
67346 #define S_RX_LINKD_DCCLOCK_RXCTL    8
67347 #define V_RX_LINKD_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKD_DCCLOCK_RXCTL)
67348 #define F_RX_LINKD_DCCLOCK_RXCTL    V_RX_LINKD_DCCLOCK_RXCTL(1U)
67349 
67350 #define A_MAC_PORT_RX_LINKD_RECEIVER_QCC_CONTROL 0x37f4
67351 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2 0x37f8
67352 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x37f8
67353 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1 0x37fc
67354 #define A_MAC_PORT_ANALOG_TEST_MUX 0x3814
67355 #define A_MAC_PORT_BANDGAP_CONTROL 0x382c
67356 
67357 #define S_T5BGCTL    0
67358 #define M_T5BGCTL    0xfU
67359 #define V_T5BGCTL(x) ((x) << S_T5BGCTL)
67360 #define G_T5BGCTL(x) (((x) >> S_T5BGCTL) & M_T5BGCTL)
67361 
67362 #define A_MAC_PORT_PLLREFSEL_CONTROL 0x3854
67363 
67364 #define S_REFSEL    0
67365 #define M_REFSEL    0x7U
67366 #define V_REFSEL(x) ((x) << S_REFSEL)
67367 #define G_REFSEL(x) (((x) >> S_REFSEL) & M_REFSEL)
67368 
67369 #define A_MAC_PORT_REFISINK_CONTROL 0x3858
67370 
67371 #define S_REFISINK    0
67372 #define M_REFISINK    0x3fU
67373 #define V_REFISINK(x) ((x) << S_REFISINK)
67374 #define G_REFISINK(x) (((x) >> S_REFISINK) & M_REFISINK)
67375 
67376 #define A_MAC_PORT_REFISRC_CONTROL 0x385c
67377 
67378 #define S_REFISRC    0
67379 #define M_REFISRC    0x3fU
67380 #define V_REFISRC(x) ((x) << S_REFISRC)
67381 #define G_REFISRC(x) (((x) >> S_REFISRC) & M_REFISRC)
67382 
67383 #define A_MAC_PORT_REFVREG_CONTROL 0x3860
67384 
67385 #define S_REFVREG    0
67386 #define M_REFVREG    0x3fU
67387 #define V_REFVREG(x) ((x) << S_REFVREG)
67388 #define G_REFVREG(x) (((x) >> S_REFVREG) & M_REFVREG)
67389 
67390 #define A_MAC_PORT_VBGENDOC_CONTROL 0x3864
67391 
67392 #define S_BGCLKSEL    2
67393 #define V_BGCLKSEL(x) ((x) << S_BGCLKSEL)
67394 #define F_BGCLKSEL    V_BGCLKSEL(1U)
67395 
67396 #define S_VBGENDOC    0
67397 #define M_VBGENDOC    0x3U
67398 #define V_VBGENDOC(x) ((x) << S_VBGENDOC)
67399 #define G_VBGENDOC(x) (((x) >> S_VBGENDOC) & M_VBGENDOC)
67400 
67401 #define A_MAC_PORT_VREFTUNE_CONTROL 0x3868
67402 
67403 #define S_VREFTUNE    0
67404 #define M_VREFTUNE    0xfU
67405 #define V_VREFTUNE(x) ((x) << S_VREFTUNE)
67406 #define G_VREFTUNE(x) (((x) >> S_VREFTUNE) & M_VREFTUNE)
67407 
67408 #define A_MAC_PORT_RESISTOR_CALIBRATION_CONTROL 0x3880
67409 
67410 #define S_RCCTL1    5
67411 #define V_RCCTL1(x) ((x) << S_RCCTL1)
67412 #define F_RCCTL1    V_RCCTL1(1U)
67413 
67414 #define S_RCCTL0    4
67415 #define V_RCCTL0(x) ((x) << S_RCCTL0)
67416 #define F_RCCTL0    V_RCCTL0(1U)
67417 
67418 #define S_RCAMP1    3
67419 #define V_RCAMP1(x) ((x) << S_RCAMP1)
67420 #define F_RCAMP1    V_RCAMP1(1U)
67421 
67422 #define S_RCAMP0    2
67423 #define V_RCAMP0(x) ((x) << S_RCAMP0)
67424 #define F_RCAMP0    V_RCAMP0(1U)
67425 
67426 #define S_RCAMPEN    1
67427 #define V_RCAMPEN(x) ((x) << S_RCAMPEN)
67428 #define F_RCAMPEN    V_RCAMPEN(1U)
67429 
67430 #define S_RCRST    0
67431 #define V_RCRST(x) ((x) << S_RCRST)
67432 #define F_RCRST    V_RCRST(1U)
67433 
67434 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_CONTROL 0x3880
67435 
67436 #define S_FRCCAL_COMP    6
67437 #define V_FRCCAL_COMP(x) ((x) << S_FRCCAL_COMP)
67438 #define F_FRCCAL_COMP    V_FRCCAL_COMP(1U)
67439 
67440 #define S_IC_FRCERR    5
67441 #define V_IC_FRCERR(x) ((x) << S_IC_FRCERR)
67442 #define F_IC_FRCERR    V_IC_FRCERR(1U)
67443 
67444 #define S_CAL_BISTENAB    4
67445 #define V_CAL_BISTENAB(x) ((x) << S_CAL_BISTENAB)
67446 #define F_CAL_BISTENAB    V_CAL_BISTENAB(1U)
67447 
67448 #define S_RCAL_RESET    0
67449 #define V_RCAL_RESET(x) ((x) << S_RCAL_RESET)
67450 #define F_RCAL_RESET    V_RCAL_RESET(1U)
67451 
67452 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_1 0x3884
67453 
67454 #define S_RCERR    1
67455 #define V_RCERR(x) ((x) << S_RCERR)
67456 #define F_RCERR    V_RCERR(1U)
67457 
67458 #define S_RCCOMP    0
67459 #define V_RCCOMP(x) ((x) << S_RCCOMP)
67460 #define F_RCCOMP    V_RCCOMP(1U)
67461 
67462 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_1 0x3884
67463 
67464 #define S_RCALBENAB    3
67465 #define V_RCALBENAB(x) ((x) << S_RCALBENAB)
67466 #define F_RCALBENAB    V_RCALBENAB(1U)
67467 
67468 #define S_RCALBUSY    2
67469 #define V_RCALBUSY(x) ((x) << S_RCALBUSY)
67470 #define F_RCALBUSY    V_RCALBUSY(1U)
67471 
67472 #define S_RCALERR    1
67473 #define V_RCALERR(x) ((x) << S_RCALERR)
67474 #define F_RCALERR    V_RCALERR(1U)
67475 
67476 #define S_RCALCOMP    0
67477 #define V_RCALCOMP(x) ((x) << S_RCALCOMP)
67478 #define F_RCALCOMP    V_RCALCOMP(1U)
67479 
67480 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_2 0x3888
67481 
67482 #define S_RESREG2    0
67483 #define M_RESREG2    0xffU
67484 #define V_RESREG2(x) ((x) << S_RESREG2)
67485 #define G_RESREG2(x) (((x) >> S_RESREG2) & M_RESREG2)
67486 
67487 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_2 0x3888
67488 
67489 #define S_T6_RESREG2    0
67490 #define M_T6_RESREG2    0x3fU
67491 #define V_T6_RESREG2(x) ((x) << S_T6_RESREG2)
67492 #define G_T6_RESREG2(x) (((x) >> S_T6_RESREG2) & M_T6_RESREG2)
67493 
67494 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_3 0x388c
67495 
67496 #define S_RESREG3    0
67497 #define M_RESREG3    0xffU
67498 #define V_RESREG3(x) ((x) << S_RESREG3)
67499 #define G_RESREG3(x) (((x) >> S_RESREG3) & M_RESREG3)
67500 
67501 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_3 0x388c
67502 
67503 #define S_T6_RESREG3    0
67504 #define M_T6_RESREG3    0x3fU
67505 #define V_T6_RESREG3(x) ((x) << S_T6_RESREG3)
67506 #define G_T6_RESREG3(x) (((x) >> S_T6_RESREG3) & M_T6_RESREG3)
67507 
67508 #define A_MAC_PORT_INEQUALITY_CONTROL_AND_RESULT 0x38c0
67509 
67510 #define S_ISGT    7
67511 #define V_ISGT(x) ((x) << S_ISGT)
67512 #define F_ISGT    V_ISGT(1U)
67513 
67514 #define S_ISLT    6
67515 #define V_ISLT(x) ((x) << S_ISLT)
67516 #define F_ISLT    V_ISLT(1U)
67517 
67518 #define S_ISEQ    5
67519 #define V_ISEQ(x) ((x) << S_ISEQ)
67520 #define F_ISEQ    V_ISEQ(1U)
67521 
67522 #define S_ISVAL    3
67523 #define M_ISVAL    0x3U
67524 #define V_ISVAL(x) ((x) << S_ISVAL)
67525 #define G_ISVAL(x) (((x) >> S_ISVAL) & M_ISVAL)
67526 
67527 #define S_GTORLT    1
67528 #define M_GTORLT    0x3U
67529 #define V_GTORLT(x) ((x) << S_GTORLT)
67530 #define G_GTORLT(x) (((x) >> S_GTORLT) & M_GTORLT)
67531 
67532 #define S_INEQ    0
67533 #define V_INEQ(x) ((x) << S_INEQ)
67534 #define F_INEQ    V_INEQ(1U)
67535 
67536 #define A_MAC_PORT_INEQUALITY_LOW_LIMIT 0x38c4
67537 
67538 #define S_LLIM    0
67539 #define M_LLIM    0xffffU
67540 #define V_LLIM(x) ((x) << S_LLIM)
67541 #define G_LLIM(x) (((x) >> S_LLIM) & M_LLIM)
67542 
67543 #define A_MAC_PORT_INEQUALITY_LOW_LIMIT_MASK 0x38c8
67544 
67545 #define S_LMSK    0
67546 #define M_LMSK    0xffffU
67547 #define V_LMSK(x) ((x) << S_LMSK)
67548 #define G_LMSK(x) (((x) >> S_LMSK) & M_LMSK)
67549 
67550 #define A_MAC_PORT_INEQUALITY_HIGH_LIMIT 0x38cc
67551 
67552 #define S_HLIM    0
67553 #define M_HLIM    0xffffU
67554 #define V_HLIM(x) ((x) << S_HLIM)
67555 #define G_HLIM(x) (((x) >> S_HLIM) & M_HLIM)
67556 
67557 #define A_MAC_PORT_INEQUALITY_HIGH_LIMIT_MASK 0x38d0
67558 
67559 #define S_HMSK    0
67560 #define M_HMSK    0xffffU
67561 #define V_HMSK(x) ((x) << S_HMSK)
67562 #define G_HMSK(x) (((x) >> S_HMSK) & M_HMSK)
67563 
67564 #define A_MAC_PORT_MACRO_TEST_CONTROL_6 0x38e8
67565 
67566 #define S_LBIST    7
67567 #define V_LBIST(x) ((x) << S_LBIST)
67568 #define F_LBIST    V_LBIST(1U)
67569 
67570 #define S_LOGICTEST    6
67571 #define V_LOGICTEST(x) ((x) << S_LOGICTEST)
67572 #define F_LOGICTEST    V_LOGICTEST(1U)
67573 
67574 #define S_MAVDHI    5
67575 #define V_MAVDHI(x) ((x) << S_MAVDHI)
67576 #define F_MAVDHI    V_MAVDHI(1U)
67577 
67578 #define S_AUXEN    4
67579 #define V_AUXEN(x) ((x) << S_AUXEN)
67580 #define F_AUXEN    V_AUXEN(1U)
67581 
67582 #define S_JTAGMD    3
67583 #define V_JTAGMD(x) ((x) << S_JTAGMD)
67584 #define F_JTAGMD    V_JTAGMD(1U)
67585 
67586 #define S_RXACMODE    2
67587 #define V_RXACMODE(x) ((x) << S_RXACMODE)
67588 #define F_RXACMODE    V_RXACMODE(1U)
67589 
67590 #define S_HSSACJPC    1
67591 #define V_HSSACJPC(x) ((x) << S_HSSACJPC)
67592 #define F_HSSACJPC    V_HSSACJPC(1U)
67593 
67594 #define S_HSSACJAC    0
67595 #define V_HSSACJAC(x) ((x) << S_HSSACJAC)
67596 #define F_HSSACJAC    V_HSSACJAC(1U)
67597 
67598 #define A_MAC_PORT_MACRO_TEST_CONTROL_5 0x38ec
67599 
67600 #define S_REFVALIDD    6
67601 #define V_REFVALIDD(x) ((x) << S_REFVALIDD)
67602 #define F_REFVALIDD    V_REFVALIDD(1U)
67603 
67604 #define S_REFVALIDC    5
67605 #define V_REFVALIDC(x) ((x) << S_REFVALIDC)
67606 #define F_REFVALIDC    V_REFVALIDC(1U)
67607 
67608 #define S_REFVALIDB    4
67609 #define V_REFVALIDB(x) ((x) << S_REFVALIDB)
67610 #define F_REFVALIDB    V_REFVALIDB(1U)
67611 
67612 #define S_REFVALIDA    3
67613 #define V_REFVALIDA(x) ((x) << S_REFVALIDA)
67614 #define F_REFVALIDA    V_REFVALIDA(1U)
67615 
67616 #define S_REFSELRESET    2
67617 #define V_REFSELRESET(x) ((x) << S_REFSELRESET)
67618 #define F_REFSELRESET    V_REFSELRESET(1U)
67619 
67620 #define S_SOFTRESET    1
67621 #define V_SOFTRESET(x) ((x) << S_SOFTRESET)
67622 #define F_SOFTRESET    V_SOFTRESET(1U)
67623 
67624 #define S_MACROTEST    0
67625 #define V_MACROTEST(x) ((x) << S_MACROTEST)
67626 #define F_MACROTEST    V_MACROTEST(1U)
67627 
67628 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE 0x3900
67629 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL 0x3904
67630 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL 0x3908
67631 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL 0x390c
67632 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3910
67633 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3914
67634 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3918
67635 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x391c
67636 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT 0x3920
67637 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT 0x3924
67638 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT 0x3928
67639 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_3_COEFFICIENT 0x392c
67640 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE 0x3930
67641 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY 0x3934
67642 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3938
67643 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x393c
67644 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3940
67645 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3940
67646 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3944
67647 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3944
67648 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3948
67649 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3948
67650 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x394c
67651 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_APPLIED_TUNE_REGISTER 0x3950
67652 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3958
67653 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3960
67654 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_4X_SEGMENT_APPLIED 0x3960
67655 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3964
67656 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_2X_SEGMENT_APPLIED 0x3964
67657 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3968
67658 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_1X_SEGMENT_APPLIED 0x3968
67659 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x396c
67660 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3970
67661 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3970
67662 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3974
67663 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3974
67664 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3978
67665 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x397c
67666 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3980
67667 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3984
67668 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3988
67669 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3988
67670 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x398c
67671 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x398c
67672 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE 0x3990
67673 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED 0x3994
67674 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT 0x3998
67675 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL 0x399c
67676 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x39a0
67677 
67678 #define S_TX_LINK_BCST_DCCSTEP_CTL    6
67679 #define M_TX_LINK_BCST_DCCSTEP_CTL    0x3U
67680 #define V_TX_LINK_BCST_DCCSTEP_CTL(x) ((x) << S_TX_LINK_BCST_DCCSTEP_CTL)
67681 #define G_TX_LINK_BCST_DCCSTEP_CTL(x) (((x) >> S_TX_LINK_BCST_DCCSTEP_CTL) & M_TX_LINK_BCST_DCCSTEP_CTL)
67682 
67683 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE 0x39a4
67684 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED 0x39a8
67685 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT 0x39ac
67686 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_OVERRIDE 0x39c0
67687 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_OVERRIDE 0x39c8
67688 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X_OVERRIDE 0x39cc
67689 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_1X_OVERRIDE 0x39d0
67690 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x39d8
67691 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x39dc
67692 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x39e0
67693 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_5 0x39ec
67694 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4 0x39f0
67695 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3 0x39f4
67696 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2 0x39f8
67697 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1 0x39fc
67698 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE 0x3a00
67699 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL 0x3a04
67700 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL 0x3a08
67701 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL 0x3a0c
67702 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1 0x3a10
67703 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2 0x3a14
67704 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3a18
67705 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x3a1c
67706 #define A_MAC_PORT_RX_LINK_BCST_DFE_CONTROL 0x3a20
67707 #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1 0x3a24
67708 #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2 0x3a28
67709 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1 0x3a2c
67710 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2 0x3a30
67711 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3 0x3a34
67712 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1 0x3a38
67713 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3a38
67714 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_1 0x3a3c
67715 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3 0x3a40
67716 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_2 0x3a40
67717 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3a44
67718 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN 0x3a48
67719 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ 0x3a4c
67720 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN 0x3a4c
67721 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL 0x3a50
67722 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_CONTROL 0x3a54
67723 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_VALUE 0x3a58
67724 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x3a5c
67725 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET 0x3a5c
67726 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3a60
67727 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3a60
67728 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3a64
67729 #define A_MAC_PORT_RX_LINK_BCST_PEAKED_INTEGRATOR 0x3a64
67730 #define A_MAC_PORT_RX_LINK_BCST_CDR_ANALOG_SWITCH 0x3a68
67731 #define A_MAC_PORT_RX_LINK_BCST_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x3a6c
67732 #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3a70
67733 #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC 0x3a74
67734 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS 0x3a78
67735 
67736 #define S_RX_LINK_BCST_ACCCMP_RIS    11
67737 #define V_RX_LINK_BCST_ACCCMP_RIS(x) ((x) << S_RX_LINK_BCST_ACCCMP_RIS)
67738 #define F_RX_LINK_BCST_ACCCMP_RIS    V_RX_LINK_BCST_ACCCMP_RIS(1U)
67739 
67740 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1 0x3a7c
67741 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2 0x3a80
67742 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2 0x3a84
67743 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_CHANNEL 0x3a84
67744 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2 0x3a88
67745 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_VALUE 0x3a88
67746 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4 0x3a8c
67747 #define A_MAC_PORT_RX_LINK_BCST_H_COEFFICIENBT_BIST 0x3a8c
67748 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4 0x3a90
67749 #define A_MAC_PORT_RX_LINK_BCST_AC_CAPACITOR_BIST 0x3a90
67750 
67751 #define S_RX_LINK_BCST_ACCCMP_BIST    13
67752 #define V_RX_LINK_BCST_ACCCMP_BIST(x) ((x) << S_RX_LINK_BCST_ACCCMP_BIST)
67753 #define F_RX_LINK_BCST_ACCCMP_BIST    V_RX_LINK_BCST_ACCCMP_BIST(1U)
67754 
67755 #define A_MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET 0x3a94
67756 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL 0x3a98
67757 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL_REGISTER 0x3a98
67758 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL 0x3a9c
67759 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH 0x3aa0
67760 #define A_MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET 0x3aa4
67761 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL 0x3aa8
67762 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS 0x3aac
67763 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT 0x3ab0
67764 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x3ab4
67765 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x3ab8
67766 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_3 0x3abc
67767 #define A_MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE 0x3ac0
67768 #define A_MAC_PORT_RX_LINK_BCST_DFE_TAP_CONTROL 0x3ac0
67769 
67770 #define S_RX_LINK_BCST_INDEX_DFE_TC    0
67771 #define M_RX_LINK_BCST_INDEX_DFE_TC    0xfU
67772 #define V_RX_LINK_BCST_INDEX_DFE_TC(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_TC)
67773 #define G_RX_LINK_BCST_INDEX_DFE_TC(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_TC) & M_RX_LINK_BCST_INDEX_DFE_TC)
67774 
67775 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3ac4
67776 #define A_MAC_PORT_RX_LINK_BCST_DFE_TAP 0x3ac4
67777 
67778 #define S_RX_LINK_BCST_INDEX_DFE_TAP    0
67779 #define M_RX_LINK_BCST_INDEX_DFE_TAP    0xfU
67780 #define V_RX_LINK_BCST_INDEX_DFE_TAP(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_TAP)
67781 #define G_RX_LINK_BCST_INDEX_DFE_TAP(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_TAP) & M_RX_LINK_BCST_INDEX_DFE_TAP)
67782 
67783 #define A_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3ac8
67784 #define A_MAC_PORT_RX_LINK_BCST_DFE_H3 0x3acc
67785 #define A_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3ad0
67786 #define A_MAC_PORT_RX_LINK_BCST_DFE_H5 0x3ad4
67787 #define A_MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7 0x3ad8
67788 #define A_MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9 0x3adc
67789 #define A_MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11 0x3ae0
67790 #define A_MAC_PORT_RX_LINK_BCST_DFE_H12 0x3ae4
67791 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS_2 0x3ae4
67792 #define A_MAC_PORT_RX_LINK_BCST_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x3ae8
67793 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DCD_CONTROL 0x3aec
67794 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DCC_CONTROL 0x3af0
67795 
67796 #define S_RX_LINK_BCST_DCCSTEP_RXCTL    10
67797 #define M_RX_LINK_BCST_DCCSTEP_RXCTL    0x3U
67798 #define V_RX_LINK_BCST_DCCSTEP_RXCTL(x) ((x) << S_RX_LINK_BCST_DCCSTEP_RXCTL)
67799 #define G_RX_LINK_BCST_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINK_BCST_DCCSTEP_RXCTL) & M_RX_LINK_BCST_DCCSTEP_RXCTL)
67800 
67801 #define S_RX_LINK_BCST_DCCLOCK_RXCTL    8
67802 #define V_RX_LINK_BCST_DCCLOCK_RXCTL(x) ((x) << S_RX_LINK_BCST_DCCLOCK_RXCTL)
67803 #define F_RX_LINK_BCST_DCCLOCK_RXCTL    V_RX_LINK_BCST_DCCLOCK_RXCTL(1U)
67804 
67805 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_QCC_CONTROL 0x3af4
67806 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2 0x3af8
67807 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x3af8
67808 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1 0x3afc
67809 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0 0x3b00
67810 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1 0x3b04
67811 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2 0x3b08
67812 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3 0x3b0c
67813 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4 0x3b10
67814 #define A_MAC_PORT_PLLA_POWER_CONTROL 0x3b24
67815 
67816 #define S_SPWRENA    1
67817 #define V_SPWRENA(x) ((x) << S_SPWRENA)
67818 #define F_SPWRENA    V_SPWRENA(1U)
67819 
67820 #define S_NPWRENA    0
67821 #define V_NPWRENA(x) ((x) << S_NPWRENA)
67822 #define F_NPWRENA    V_NPWRENA(1U)
67823 
67824 #define A_MAC_PORT_PLLA_CHARGE_PUMP_CONTROL 0x3b28
67825 
67826 #define S_T5CPISEL    0
67827 #define M_T5CPISEL    0x7U
67828 #define V_T5CPISEL(x) ((x) << S_T5CPISEL)
67829 #define G_T5CPISEL(x) (((x) >> S_T5CPISEL) & M_T5CPISEL)
67830 
67831 #define A_MAC_PORT_PLLA_PLL_MICELLANEOUS_CONTROL 0x3b38
67832 #define A_MAC_PORT_PLLA_PCLK_CONTROL 0x3b3c
67833 
67834 #define S_SPEDIV    3
67835 #define M_SPEDIV    0x1fU
67836 #define V_SPEDIV(x) ((x) << S_SPEDIV)
67837 #define G_SPEDIV(x) (((x) >> S_SPEDIV) & M_SPEDIV)
67838 
67839 #define S_PCKSEL    0
67840 #define M_PCKSEL    0x7U
67841 #define V_PCKSEL(x) ((x) << S_PCKSEL)
67842 #define G_PCKSEL(x) (((x) >> S_PCKSEL) & M_PCKSEL)
67843 
67844 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL 0x3b40
67845 
67846 #define S_EMIL    2
67847 #define V_EMIL(x) ((x) << S_EMIL)
67848 #define F_EMIL    V_EMIL(1U)
67849 
67850 #define S_EMID    1
67851 #define V_EMID(x) ((x) << S_EMID)
67852 #define F_EMID    V_EMID(1U)
67853 
67854 #define S_EMIS    0
67855 #define V_EMIS(x) ((x) << S_EMIS)
67856 #define F_EMIS    V_EMIS(1U)
67857 
67858 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1 0x3b44
67859 
67860 #define S_EMIL1    0
67861 #define M_EMIL1    0xffU
67862 #define V_EMIL1(x) ((x) << S_EMIL1)
67863 #define G_EMIL1(x) (((x) >> S_EMIL1) & M_EMIL1)
67864 
67865 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2 0x3b48
67866 
67867 #define S_EMIL2    0
67868 #define M_EMIL2    0xffU
67869 #define V_EMIL2(x) ((x) << S_EMIL2)
67870 #define G_EMIL2(x) (((x) >> S_EMIL2) & M_EMIL2)
67871 
67872 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3 0x3b4c
67873 
67874 #define S_EMIL3    0
67875 #define M_EMIL3    0xffU
67876 #define V_EMIL3(x) ((x) << S_EMIL3)
67877 #define G_EMIL3(x) (((x) >> S_EMIL3) & M_EMIL3)
67878 
67879 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4 0x3b50
67880 
67881 #define S_EMIL4    0
67882 #define M_EMIL4    0xffU
67883 #define V_EMIL4(x) ((x) << S_EMIL4)
67884 #define G_EMIL4(x) (((x) >> S_EMIL4) & M_EMIL4)
67885 
67886 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_4 0x3bf0
67887 
67888 #define S_VBST    1
67889 #define M_VBST    0x7U
67890 #define V_VBST(x) ((x) << S_VBST)
67891 #define G_VBST(x) (((x) >> S_VBST) & M_VBST)
67892 
67893 #define S_PLLDIVA    4
67894 #define V_PLLDIVA(x) ((x) << S_PLLDIVA)
67895 #define F_PLLDIVA    V_PLLDIVA(1U)
67896 
67897 #define S_REFDIV    0
67898 #define M_REFDIV    0xfU
67899 #define V_REFDIV(x) ((x) << S_REFDIV)
67900 #define G_REFDIV(x) (((x) >> S_REFDIV) & M_REFDIV)
67901 
67902 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_3 0x3bf4
67903 
67904 #define S_RESYNC    6
67905 #define V_RESYNC(x) ((x) << S_RESYNC)
67906 #define F_RESYNC    V_RESYNC(1U)
67907 
67908 #define S_RXCLKSEL    5
67909 #define V_RXCLKSEL(x) ((x) << S_RXCLKSEL)
67910 #define F_RXCLKSEL    V_RXCLKSEL(1U)
67911 
67912 #define S_FRCBAND    4
67913 #define V_FRCBAND(x) ((x) << S_FRCBAND)
67914 #define F_FRCBAND    V_FRCBAND(1U)
67915 
67916 #define S_PLLBYP    3
67917 #define V_PLLBYP(x) ((x) << S_PLLBYP)
67918 #define F_PLLBYP    V_PLLBYP(1U)
67919 
67920 #define S_PDWNP    2
67921 #define V_PDWNP(x) ((x) << S_PDWNP)
67922 #define F_PDWNP    V_PDWNP(1U)
67923 
67924 #define S_VCOSEL    1
67925 #define V_VCOSEL(x) ((x) << S_VCOSEL)
67926 #define F_VCOSEL    V_VCOSEL(1U)
67927 
67928 #define S_DIVSEL8    0
67929 #define V_DIVSEL8(x) ((x) << S_DIVSEL8)
67930 #define F_DIVSEL8    V_DIVSEL8(1U)
67931 
67932 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_2 0x3bf8
67933 
67934 #define S_DIVSEL    0
67935 #define M_DIVSEL    0xffU
67936 #define V_DIVSEL(x) ((x) << S_DIVSEL)
67937 #define G_DIVSEL(x) (((x) >> S_DIVSEL) & M_DIVSEL)
67938 
67939 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_1 0x3bfc
67940 
67941 #define S_CONFIG    0
67942 #define M_CONFIG    0xffU
67943 #define V_CONFIG(x) ((x) << S_CONFIG)
67944 #define G_CONFIG(x) (((x) >> S_CONFIG) & M_CONFIG)
67945 
67946 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0 0x3c00
67947 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1 0x3c04
67948 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2 0x3c08
67949 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3 0x3c0c
67950 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4 0x3c10
67951 #define A_MAC_PORT_PLLB_POWER_CONTROL 0x3c24
67952 #define A_MAC_PORT_PLLB_CHARGE_PUMP_CONTROL 0x3c28
67953 #define A_MAC_PORT_PLLB_PLL_MICELLANEOUS_CONTROL 0x3c38
67954 #define A_MAC_PORT_PLLB_PCLK_CONTROL 0x3c3c
67955 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL 0x3c40
67956 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1 0x3c44
67957 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2 0x3c48
67958 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3 0x3c4c
67959 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4 0x3c50
67960 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_4 0x3cf0
67961 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_3 0x3cf4
67962 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_2 0x3cf8
67963 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_1 0x3cfc
67964 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
67965 
67966 #define S_STEP    0
67967 #define M_STEP    0x7U
67968 #define V_STEP(x) ((x) << S_STEP)
67969 #define G_STEP(x) (((x) >> S_STEP) & M_STEP)
67970 
67971 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
67972 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
67973 
67974 #define S_C0INIT    0
67975 #define M_C0INIT    0x1fU
67976 #define V_C0INIT(x) ((x) << S_C0INIT)
67977 #define G_C0INIT(x) (((x) >> S_C0INIT) & M_C0INIT)
67978 
67979 #define S_C0PRESET    8
67980 #define M_C0PRESET    0x7fU
67981 #define V_C0PRESET(x) ((x) << S_C0PRESET)
67982 #define G_C0PRESET(x) (((x) >> S_C0PRESET) & M_C0PRESET)
67983 
67984 #define S_C0INIT1    0
67985 #define M_C0INIT1    0x7fU
67986 #define V_C0INIT1(x) ((x) << S_C0INIT1)
67987 #define G_C0INIT1(x) (((x) >> S_C0INIT1) & M_C0INIT1)
67988 
67989 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
67990 
67991 #define S_C0MAX    8
67992 #define M_C0MAX    0x1fU
67993 #define V_C0MAX(x) ((x) << S_C0MAX)
67994 #define G_C0MAX(x) (((x) >> S_C0MAX) & M_C0MAX)
67995 
67996 #define S_C0MIN    0
67997 #define M_C0MIN    0x1fU
67998 #define V_C0MIN(x) ((x) << S_C0MIN)
67999 #define G_C0MIN(x) (((x) >> S_C0MIN) & M_C0MIN)
68000 
68001 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
68002 
68003 #define S_T6_C0MAX    8
68004 #define M_T6_C0MAX    0x7fU
68005 #define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
68006 #define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
68007 
68008 #define S_T6_C0MIN    0
68009 #define M_T6_C0MIN    0x7fU
68010 #define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
68011 #define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
68012 
68013 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
68014 
68015 #define S_C1INIT    0
68016 #define M_C1INIT    0x7fU
68017 #define V_C1INIT(x) ((x) << S_C1INIT)
68018 #define G_C1INIT(x) (((x) >> S_C1INIT) & M_C1INIT)
68019 
68020 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
68021 
68022 #define S_C1PRESET    8
68023 #define M_C1PRESET    0x7fU
68024 #define V_C1PRESET(x) ((x) << S_C1PRESET)
68025 #define G_C1PRESET(x) (((x) >> S_C1PRESET) & M_C1PRESET)
68026 
68027 #define S_C1INIT1    0
68028 #define M_C1INIT1    0x7fU
68029 #define V_C1INIT1(x) ((x) << S_C1INIT1)
68030 #define G_C1INIT1(x) (((x) >> S_C1INIT1) & M_C1INIT1)
68031 
68032 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
68033 
68034 #define S_C1MAX    8
68035 #define M_C1MAX    0x7fU
68036 #define V_C1MAX(x) ((x) << S_C1MAX)
68037 #define G_C1MAX(x) (((x) >> S_C1MAX) & M_C1MAX)
68038 
68039 #define S_C1MIN    0
68040 #define M_C1MIN    0x7fU
68041 #define V_C1MIN(x) ((x) << S_C1MIN)
68042 #define G_C1MIN(x) (((x) >> S_C1MIN) & M_C1MIN)
68043 
68044 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
68045 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
68046 
68047 #define S_C2INIT    0
68048 #define M_C2INIT    0x3fU
68049 #define V_C2INIT(x) ((x) << S_C2INIT)
68050 #define G_C2INIT(x) (((x) >> S_C2INIT) & M_C2INIT)
68051 
68052 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
68053 
68054 #define S_C2PRESET    8
68055 #define M_C2PRESET    0x7fU
68056 #define V_C2PRESET(x) ((x) << S_C2PRESET)
68057 #define G_C2PRESET(x) (((x) >> S_C2PRESET) & M_C2PRESET)
68058 
68059 #define S_C2INIT1    0
68060 #define M_C2INIT1    0x7fU
68061 #define V_C2INIT1(x) ((x) << S_C2INIT1)
68062 #define G_C2INIT1(x) (((x) >> S_C2INIT1) & M_C2INIT1)
68063 
68064 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
68065 
68066 #define S_C2MAX    8
68067 #define M_C2MAX    0x3fU
68068 #define V_C2MAX(x) ((x) << S_C2MAX)
68069 #define G_C2MAX(x) (((x) >> S_C2MAX) & M_C2MAX)
68070 
68071 #define S_C2MIN    0
68072 #define M_C2MIN    0x3fU
68073 #define V_C2MIN(x) ((x) << S_C2MIN)
68074 #define G_C2MIN(x) (((x) >> S_C2MIN) & M_C2MIN)
68075 
68076 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
68077 
68078 #define S_T6_C2MAX    8
68079 #define M_T6_C2MAX    0x7fU
68080 #define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
68081 #define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
68082 
68083 #define S_T6_C2MIN    0
68084 #define M_T6_C2MIN    0x7fU
68085 #define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
68086 #define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
68087 
68088 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
68089 
68090 #define S_VMMAX    0
68091 #define M_VMMAX    0x7fU
68092 #define V_VMMAX(x) ((x) << S_VMMAX)
68093 #define G_VMMAX(x) (((x) >> S_VMMAX) & M_VMMAX)
68094 
68095 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
68096 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
68097 
68098 #define S_V2MIN    0
68099 #define M_V2MIN    0x7fU
68100 #define V_V2MIN(x) ((x) << S_V2MIN)
68101 #define G_V2MIN(x) (((x) >> S_V2MIN) & M_V2MIN)
68102 
68103 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
68104 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
68105 
68106 #define S_C3PRESET    8
68107 #define M_C3PRESET    0x7fU
68108 #define V_C3PRESET(x) ((x) << S_C3PRESET)
68109 #define G_C3PRESET(x) (((x) >> S_C3PRESET) & M_C3PRESET)
68110 
68111 #define S_C3INIT1    0
68112 #define M_C3INIT1    0x7fU
68113 #define V_C3INIT1(x) ((x) << S_C3INIT1)
68114 #define G_C3INIT1(x) (((x) >> S_C3INIT1) & M_C3INIT1)
68115 
68116 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
68117 
68118 #define S_C3MAX    8
68119 #define M_C3MAX    0x7fU
68120 #define V_C3MAX(x) ((x) << S_C3MAX)
68121 #define G_C3MAX(x) (((x) >> S_C3MAX) & M_C3MAX)
68122 
68123 #define S_C3MIN    0
68124 #define M_C3MIN    0x7fU
68125 #define V_C3MIN(x) ((x) << S_C3MIN)
68126 #define G_C3MIN(x) (((x) >> S_C3MIN) & M_C3MIN)
68127 
68128 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
68129 
68130 #define S_C0INIT2    0
68131 #define M_C0INIT2    0x7fU
68132 #define V_C0INIT2(x) ((x) << S_C0INIT2)
68133 #define G_C0INIT2(x) (((x) >> S_C0INIT2) & M_C0INIT2)
68134 
68135 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
68136 
68137 #define S_C1INIT2    0
68138 #define M_C1INIT2    0x7fU
68139 #define V_C1INIT2(x) ((x) << S_C1INIT2)
68140 #define G_C1INIT2(x) (((x) >> S_C1INIT2) & M_C1INIT2)
68141 
68142 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
68143 
68144 #define S_C2INIT2    0
68145 #define M_C2INIT2    0x7fU
68146 #define V_C2INIT2(x) ((x) << S_C2INIT2)
68147 #define G_C2INIT2(x) (((x) >> S_C2INIT2) & M_C2INIT2)
68148 
68149 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
68150 
68151 #define S_C3INIT2    0
68152 #define M_C3INIT2    0x7fU
68153 #define V_C3INIT2(x) ((x) << S_C3INIT2)
68154 #define G_C3INIT2(x) (((x) >> S_C3INIT2) & M_C3INIT2)
68155 
68156 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
68157 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
68158 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
68159 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
68160 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
68161 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
68162 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
68163 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
68164 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
68165 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
68166 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
68167 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
68168 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
68169 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
68170 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
68171 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
68172 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
68173 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
68174 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
68175 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
68176 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
68177 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
68178 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
68179 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
68180 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
68181 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
68182 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
68183 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
68184 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
68185 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
68186 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
68187 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
68188 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
68189 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
68190 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
68191 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
68192 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
68193 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
68194 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
68195 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
68196 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
68197 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
68198 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
68199 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
68200 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
68201 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
68202 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
68203 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
68204 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
68205 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
68206 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
68207 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
68208 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
68209 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
68210 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
68211 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
68212 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
68213 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
68214 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
68215 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
68216 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
68217 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
68218 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
68219 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
68220 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
68221 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
68222 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
68223 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
68224 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
68225 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
68226 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
68227 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
68228 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
68229 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
68230 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
68231 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
68232 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
68233 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
68234 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
68235 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
68236 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
68237 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
68238 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
68239 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
68240 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
68241 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
68242 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
68243 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
68244 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
68245 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
68246 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
68247 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
68248 #define A_T6_MAC_PORT_RX_LINKA_DFE_TAP_ENABLE 0x2a00
68249 
68250 #define S_RX_LINKA_INDEX_DFE_EN    1
68251 #define M_RX_LINKA_INDEX_DFE_EN    0x7fffU
68252 #define V_RX_LINKA_INDEX_DFE_EN(x) ((x) << S_RX_LINKA_INDEX_DFE_EN)
68253 #define G_RX_LINKA_INDEX_DFE_EN(x) (((x) >> S_RX_LINKA_INDEX_DFE_EN) & M_RX_LINKA_INDEX_DFE_EN)
68254 
68255 #define A_T6_MAC_PORT_RX_LINKA_DFE_H1 0x2a04
68256 
68257 #define S_T6_H1OSN    13
68258 #define M_T6_H1OSN    0x7U
68259 #define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
68260 #define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
68261 
68262 #define S_T6_H1OMAG    8
68263 #define M_T6_H1OMAG    0x1fU
68264 #define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
68265 #define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
68266 
68267 #define A_T6_MAC_PORT_RX_LINKA_DFE_H2 0x2a08
68268 #define A_T6_MAC_PORT_RX_LINKA_DFE_H3 0x2a0c
68269 #define A_T6_MAC_PORT_RX_LINKA_DFE_H4 0x2a10
68270 
68271 #define S_H4SN    4
68272 #define M_H4SN    0x3U
68273 #define V_H4SN(x) ((x) << S_H4SN)
68274 #define G_H4SN(x) (((x) >> S_H4SN) & M_H4SN)
68275 
68276 #define S_H4MAG    0
68277 #define M_H4MAG    0xfU
68278 #define V_H4MAG(x) ((x) << S_H4MAG)
68279 #define G_H4MAG(x) (((x) >> S_H4MAG) & M_H4MAG)
68280 
68281 #define A_T6_MAC_PORT_RX_LINKA_DFE_H5 0x2a14
68282 
68283 #define S_H5GS    6
68284 #define M_H5GS    0x3U
68285 #define V_H5GS(x) ((x) << S_H5GS)
68286 #define G_H5GS(x) (((x) >> S_H5GS) & M_H5GS)
68287 
68288 #define S_H5SN    4
68289 #define M_H5SN    0x3U
68290 #define V_H5SN(x) ((x) << S_H5SN)
68291 #define G_H5SN(x) (((x) >> S_H5SN) & M_H5SN)
68292 
68293 #define S_H5MAG    0
68294 #define M_H5MAG    0xfU
68295 #define V_H5MAG(x) ((x) << S_H5MAG)
68296 #define G_H5MAG(x) (((x) >> S_H5MAG) & M_H5MAG)
68297 
68298 #define A_T6_MAC_PORT_RX_LINKA_DFE_H6_AND_H7 0x2a18
68299 
68300 #define S_H7SN    12
68301 #define M_H7SN    0x3U
68302 #define V_H7SN(x) ((x) << S_H7SN)
68303 #define G_H7SN(x) (((x) >> S_H7SN) & M_H7SN)
68304 
68305 #define S_H6SN    4
68306 #define M_H6SN    0x3U
68307 #define V_H6SN(x) ((x) << S_H6SN)
68308 #define G_H6SN(x) (((x) >> S_H6SN) & M_H6SN)
68309 
68310 #define A_T6_MAC_PORT_RX_LINKA_DFE_H8_AND_H9 0x2a1c
68311 
68312 #define S_H9SN    12
68313 #define M_H9SN    0x3U
68314 #define V_H9SN(x) ((x) << S_H9SN)
68315 #define G_H9SN(x) (((x) >> S_H9SN) & M_H9SN)
68316 
68317 #define S_H8SN    4
68318 #define M_H8SN    0x3U
68319 #define V_H8SN(x) ((x) << S_H8SN)
68320 #define G_H8SN(x) (((x) >> S_H8SN) & M_H8SN)
68321 
68322 #define A_T6_MAC_PORT_RX_LINKA_DFE_H10_AND_H11 0x2a20
68323 
68324 #define S_H11SN    12
68325 #define M_H11SN    0x3U
68326 #define V_H11SN(x) ((x) << S_H11SN)
68327 #define G_H11SN(x) (((x) >> S_H11SN) & M_H11SN)
68328 
68329 #define S_H10SN    4
68330 #define M_H10SN    0x3U
68331 #define V_H10SN(x) ((x) << S_H10SN)
68332 #define G_H10SN(x) (((x) >> S_H10SN) & M_H10SN)
68333 
68334 #define A_MAC_PORT_RX_LINKA_DFE_H12_13 0x2a24
68335 
68336 #define S_H13GS    13
68337 #define M_H13GS    0x7U
68338 #define V_H13GS(x) ((x) << S_H13GS)
68339 #define G_H13GS(x) (((x) >> S_H13GS) & M_H13GS)
68340 
68341 #define S_H13SN    10
68342 #define M_H13SN    0x7U
68343 #define V_H13SN(x) ((x) << S_H13SN)
68344 #define G_H13SN(x) (((x) >> S_H13SN) & M_H13SN)
68345 
68346 #define S_H13MAG    8
68347 #define M_H13MAG    0x3U
68348 #define V_H13MAG(x) ((x) << S_H13MAG)
68349 #define G_H13MAG(x) (((x) >> S_H13MAG) & M_H13MAG)
68350 
68351 #define S_H12SN    4
68352 #define M_H12SN    0x3U
68353 #define V_H12SN(x) ((x) << S_H12SN)
68354 #define G_H12SN(x) (((x) >> S_H12SN) & M_H12SN)
68355 
68356 #define A_MAC_PORT_RX_LINKA_DFE_H14_15 0x2a28
68357 
68358 #define S_H15GS    13
68359 #define M_H15GS    0x7U
68360 #define V_H15GS(x) ((x) << S_H15GS)
68361 #define G_H15GS(x) (((x) >> S_H15GS) & M_H15GS)
68362 
68363 #define S_H15SN    10
68364 #define M_H15SN    0x7U
68365 #define V_H15SN(x) ((x) << S_H15SN)
68366 #define G_H15SN(x) (((x) >> S_H15SN) & M_H15SN)
68367 
68368 #define S_H15MAG    8
68369 #define M_H15MAG    0x3U
68370 #define V_H15MAG(x) ((x) << S_H15MAG)
68371 #define G_H15MAG(x) (((x) >> S_H15MAG) & M_H15MAG)
68372 
68373 #define S_H14GS    6
68374 #define M_H14GS    0x3U
68375 #define V_H14GS(x) ((x) << S_H14GS)
68376 #define G_H14GS(x) (((x) >> S_H14GS) & M_H14GS)
68377 
68378 #define S_H14SN    4
68379 #define M_H14SN    0x3U
68380 #define V_H14SN(x) ((x) << S_H14SN)
68381 #define G_H14SN(x) (((x) >> S_H14SN) & M_H14SN)
68382 
68383 #define S_H14MAG    0
68384 #define M_H14MAG    0xfU
68385 #define V_H14MAG(x) ((x) << S_H14MAG)
68386 #define G_H14MAG(x) (((x) >> S_H14MAG) & M_H14MAG)
68387 
68388 #define A_MAC_PORT_RX_LINKA_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2a2c
68389 
68390 #define S_H1ODELTA    8
68391 #define M_H1ODELTA    0x1fU
68392 #define V_H1ODELTA(x) ((x) << S_H1ODELTA)
68393 #define G_H1ODELTA(x) (((x) >> S_H1ODELTA) & M_H1ODELTA)
68394 
68395 #define S_H1EDELTA    0
68396 #define M_H1EDELTA    0x3fU
68397 #define V_H1EDELTA(x) ((x) << S_H1EDELTA)
68398 #define G_H1EDELTA(x) (((x) >> S_H1EDELTA) & M_H1EDELTA)
68399 
68400 #define A_T6_MAC_PORT_RX_LINKB_DFE_TAP_ENABLE 0x2b00
68401 
68402 #define S_RX_LINKB_INDEX_DFE_EN    1
68403 #define M_RX_LINKB_INDEX_DFE_EN    0x7fffU
68404 #define V_RX_LINKB_INDEX_DFE_EN(x) ((x) << S_RX_LINKB_INDEX_DFE_EN)
68405 #define G_RX_LINKB_INDEX_DFE_EN(x) (((x) >> S_RX_LINKB_INDEX_DFE_EN) & M_RX_LINKB_INDEX_DFE_EN)
68406 
68407 #define A_T6_MAC_PORT_RX_LINKB_DFE_H1 0x2b04
68408 #define A_T6_MAC_PORT_RX_LINKB_DFE_H2 0x2b08
68409 #define A_T6_MAC_PORT_RX_LINKB_DFE_H3 0x2b0c
68410 #define A_T6_MAC_PORT_RX_LINKB_DFE_H4 0x2b10
68411 #define A_T6_MAC_PORT_RX_LINKB_DFE_H5 0x2b14
68412 #define A_T6_MAC_PORT_RX_LINKB_DFE_H6_AND_H7 0x2b18
68413 #define A_T6_MAC_PORT_RX_LINKB_DFE_H8_AND_H9 0x2b1c
68414 #define A_T6_MAC_PORT_RX_LINKB_DFE_H10_AND_H11 0x2b20
68415 #define A_MAC_PORT_RX_LINKB_DFE_H12_13 0x2b24
68416 #define A_MAC_PORT_RX_LINKB_DFE_H14_15 0x2b28
68417 #define A_MAC_PORT_RX_LINKB_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2b2c
68418 #define A_T6_MAC_PORT_RX_LINKC_DFE_TAP_ENABLE 0x2e00
68419 
68420 #define S_RX_LINKC_INDEX_DFE_EN    1
68421 #define M_RX_LINKC_INDEX_DFE_EN    0x7fffU
68422 #define V_RX_LINKC_INDEX_DFE_EN(x) ((x) << S_RX_LINKC_INDEX_DFE_EN)
68423 #define G_RX_LINKC_INDEX_DFE_EN(x) (((x) >> S_RX_LINKC_INDEX_DFE_EN) & M_RX_LINKC_INDEX_DFE_EN)
68424 
68425 #define A_T6_MAC_PORT_RX_LINKC_DFE_H1 0x2e04
68426 #define A_T6_MAC_PORT_RX_LINKC_DFE_H2 0x2e08
68427 #define A_T6_MAC_PORT_RX_LINKC_DFE_H3 0x2e0c
68428 #define A_T6_MAC_PORT_RX_LINKC_DFE_H4 0x2e10
68429 #define A_T6_MAC_PORT_RX_LINKC_DFE_H5 0x2e14
68430 #define A_T6_MAC_PORT_RX_LINKC_DFE_H6_AND_H7 0x2e18
68431 #define A_T6_MAC_PORT_RX_LINKC_DFE_H8_AND_H9 0x2e1c
68432 #define A_T6_MAC_PORT_RX_LINKC_DFE_H10_AND_H11 0x2e20
68433 #define A_MAC_PORT_RX_LINKC_DFE_H12_13 0x2e24
68434 #define A_MAC_PORT_RX_LINKC_DFE_H14_15 0x2e28
68435 #define A_MAC_PORT_RX_LINKC_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2e2c
68436 #define A_T6_MAC_PORT_RX_LINKD_DFE_TAP_ENABLE 0x2f00
68437 
68438 #define S_RX_LINKD_INDEX_DFE_EN    1
68439 #define M_RX_LINKD_INDEX_DFE_EN    0x7fffU
68440 #define V_RX_LINKD_INDEX_DFE_EN(x) ((x) << S_RX_LINKD_INDEX_DFE_EN)
68441 #define G_RX_LINKD_INDEX_DFE_EN(x) (((x) >> S_RX_LINKD_INDEX_DFE_EN) & M_RX_LINKD_INDEX_DFE_EN)
68442 
68443 #define A_T6_MAC_PORT_RX_LINKD_DFE_H1 0x2f04
68444 #define A_T6_MAC_PORT_RX_LINKD_DFE_H2 0x2f08
68445 #define A_T6_MAC_PORT_RX_LINKD_DFE_H3 0x2f0c
68446 #define A_T6_MAC_PORT_RX_LINKD_DFE_H4 0x2f10
68447 #define A_T6_MAC_PORT_RX_LINKD_DFE_H5 0x2f14
68448 #define A_T6_MAC_PORT_RX_LINKD_DFE_H6_AND_H7 0x2f18
68449 #define A_T6_MAC_PORT_RX_LINKD_DFE_H8_AND_H9 0x2f1c
68450 #define A_T6_MAC_PORT_RX_LINKD_DFE_H10_AND_H11 0x2f20
68451 #define A_MAC_PORT_RX_LINKD_DFE_H12_13 0x2f24
68452 #define A_MAC_PORT_RX_LINKD_DFE_H14_15 0x2f28
68453 #define A_MAC_PORT_RX_LINKD_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2f2c
68454 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE 0x3200
68455 
68456 #define S_RX_LINK_BCST_INDEX_DFE_EN    1
68457 #define M_RX_LINK_BCST_INDEX_DFE_EN    0x7fffU
68458 #define V_RX_LINK_BCST_INDEX_DFE_EN(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_EN)
68459 #define G_RX_LINK_BCST_INDEX_DFE_EN(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_EN) & M_RX_LINK_BCST_INDEX_DFE_EN)
68460 
68461 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3204
68462 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3208
68463 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H3 0x320c
68464 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3210
68465 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H5 0x3214
68466 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7 0x3218
68467 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9 0x321c
68468 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11 0x3220
68469 #define A_MAC_PORT_RX_LINK_BCST_DFE_H12_13 0x3224
68470 #define A_MAC_PORT_RX_LINK_BCST_DFE_H14_15 0x3228
68471 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x322c
68472 
68473 /* registers for module MC_0 */
68474 #define MC_0_BASE_ADDR 0x40000
68475 
68476 #define A_MC_UPCTL_SCFG 0x40000
68477 
68478 #define S_BBFLAGS_TIMING    8
68479 #define M_BBFLAGS_TIMING    0xfU
68480 #define V_BBFLAGS_TIMING(x) ((x) << S_BBFLAGS_TIMING)
68481 #define G_BBFLAGS_TIMING(x) (((x) >> S_BBFLAGS_TIMING) & M_BBFLAGS_TIMING)
68482 
68483 #define S_NFIFO_NIF1_DIS    6
68484 #define V_NFIFO_NIF1_DIS(x) ((x) << S_NFIFO_NIF1_DIS)
68485 #define F_NFIFO_NIF1_DIS    V_NFIFO_NIF1_DIS(1U)
68486 
68487 #define A_MC_UPCTL_SCTL 0x40004
68488 #define A_MC_UPCTL_STAT 0x40008
68489 
68490 #define S_LP_TRIG    4
68491 #define M_LP_TRIG    0x7U
68492 #define V_LP_TRIG(x) ((x) << S_LP_TRIG)
68493 #define G_LP_TRIG(x) (((x) >> S_LP_TRIG) & M_LP_TRIG)
68494 
68495 #define A_MC_UPCTL_INTRSTAT 0x4000c
68496 
68497 #define S_PARITY_INTR    1
68498 #define V_PARITY_INTR(x) ((x) << S_PARITY_INTR)
68499 #define F_PARITY_INTR    V_PARITY_INTR(1U)
68500 
68501 #define S_ECC_INTR    0
68502 #define V_ECC_INTR(x) ((x) << S_ECC_INTR)
68503 #define F_ECC_INTR    V_ECC_INTR(1U)
68504 
68505 #define A_MC_UPCTL_MCMD 0x40040
68506 
68507 #define S_CMD_OPCODE0    0
68508 #define M_CMD_OPCODE0    0xfU
68509 #define V_CMD_OPCODE0(x) ((x) << S_CMD_OPCODE0)
68510 #define G_CMD_OPCODE0(x) (((x) >> S_CMD_OPCODE0) & M_CMD_OPCODE0)
68511 
68512 #define A_MC_LMC_MCSTAT 0x40040
68513 
68514 #define S_INIT_COMPLETE    31
68515 #define V_INIT_COMPLETE(x) ((x) << S_INIT_COMPLETE)
68516 #define F_INIT_COMPLETE    V_INIT_COMPLETE(1U)
68517 
68518 #define S_SELF_REF_MODE    30
68519 #define V_SELF_REF_MODE(x) ((x) << S_SELF_REF_MODE)
68520 #define F_SELF_REF_MODE    V_SELF_REF_MODE(1U)
68521 
68522 #define S_IDLE    29
68523 #define V_IDLE(x) ((x) << S_IDLE)
68524 #define F_IDLE    V_IDLE(1U)
68525 
68526 #define S_T6_DFI_INIT_COMPLETE    28
68527 #define V_T6_DFI_INIT_COMPLETE(x) ((x) << S_T6_DFI_INIT_COMPLETE)
68528 #define F_T6_DFI_INIT_COMPLETE    V_T6_DFI_INIT_COMPLETE(1U)
68529 
68530 #define S_PREFILL_COMPLETE    27
68531 #define V_PREFILL_COMPLETE(x) ((x) << S_PREFILL_COMPLETE)
68532 #define F_PREFILL_COMPLETE    V_PREFILL_COMPLETE(1U)
68533 
68534 #define A_MC_UPCTL_POWCTL 0x40044
68535 #define A_MC_UPCTL_POWSTAT 0x40048
68536 #define A_MC_UPCTL_CMDTSTAT 0x4004c
68537 
68538 #define S_CMD_TSTAT    0
68539 #define V_CMD_TSTAT(x) ((x) << S_CMD_TSTAT)
68540 #define F_CMD_TSTAT    V_CMD_TSTAT(1U)
68541 
68542 #define A_MC_UPCTL_CMDTSTATEN 0x40050
68543 
68544 #define S_CMD_TSTAT_EN    0
68545 #define V_CMD_TSTAT_EN(x) ((x) << S_CMD_TSTAT_EN)
68546 #define F_CMD_TSTAT_EN    V_CMD_TSTAT_EN(1U)
68547 
68548 #define A_MC_UPCTL_MRRCFG0 0x40060
68549 
68550 #define S_MRR_BYTE_SEL    0
68551 #define M_MRR_BYTE_SEL    0xfU
68552 #define V_MRR_BYTE_SEL(x) ((x) << S_MRR_BYTE_SEL)
68553 #define G_MRR_BYTE_SEL(x) (((x) >> S_MRR_BYTE_SEL) & M_MRR_BYTE_SEL)
68554 
68555 #define A_MC_UPCTL_MRRSTAT0 0x40064
68556 
68557 #define S_MRRSTAT_BEAT3    24
68558 #define M_MRRSTAT_BEAT3    0xffU
68559 #define V_MRRSTAT_BEAT3(x) ((x) << S_MRRSTAT_BEAT3)
68560 #define G_MRRSTAT_BEAT3(x) (((x) >> S_MRRSTAT_BEAT3) & M_MRRSTAT_BEAT3)
68561 
68562 #define S_MRRSTAT_BEAT2    16
68563 #define M_MRRSTAT_BEAT2    0xffU
68564 #define V_MRRSTAT_BEAT2(x) ((x) << S_MRRSTAT_BEAT2)
68565 #define G_MRRSTAT_BEAT2(x) (((x) >> S_MRRSTAT_BEAT2) & M_MRRSTAT_BEAT2)
68566 
68567 #define S_MRRSTAT_BEAT1    8
68568 #define M_MRRSTAT_BEAT1    0xffU
68569 #define V_MRRSTAT_BEAT1(x) ((x) << S_MRRSTAT_BEAT1)
68570 #define G_MRRSTAT_BEAT1(x) (((x) >> S_MRRSTAT_BEAT1) & M_MRRSTAT_BEAT1)
68571 
68572 #define S_MRRSTAT_BEAT0    0
68573 #define M_MRRSTAT_BEAT0    0xffU
68574 #define V_MRRSTAT_BEAT0(x) ((x) << S_MRRSTAT_BEAT0)
68575 #define G_MRRSTAT_BEAT0(x) (((x) >> S_MRRSTAT_BEAT0) & M_MRRSTAT_BEAT0)
68576 
68577 #define A_MC_UPCTL_MRRSTAT1 0x40068
68578 
68579 #define S_MRRSTAT_BEAT7    24
68580 #define M_MRRSTAT_BEAT7    0xffU
68581 #define V_MRRSTAT_BEAT7(x) ((x) << S_MRRSTAT_BEAT7)
68582 #define G_MRRSTAT_BEAT7(x) (((x) >> S_MRRSTAT_BEAT7) & M_MRRSTAT_BEAT7)
68583 
68584 #define S_MRRSTAT_BEAT6    16
68585 #define M_MRRSTAT_BEAT6    0xffU
68586 #define V_MRRSTAT_BEAT6(x) ((x) << S_MRRSTAT_BEAT6)
68587 #define G_MRRSTAT_BEAT6(x) (((x) >> S_MRRSTAT_BEAT6) & M_MRRSTAT_BEAT6)
68588 
68589 #define S_MRRSTAT_BEAT5    8
68590 #define M_MRRSTAT_BEAT5    0xffU
68591 #define V_MRRSTAT_BEAT5(x) ((x) << S_MRRSTAT_BEAT5)
68592 #define G_MRRSTAT_BEAT5(x) (((x) >> S_MRRSTAT_BEAT5) & M_MRRSTAT_BEAT5)
68593 
68594 #define S_MRRSTAT_BEAT4    0
68595 #define M_MRRSTAT_BEAT4    0xffU
68596 #define V_MRRSTAT_BEAT4(x) ((x) << S_MRRSTAT_BEAT4)
68597 #define G_MRRSTAT_BEAT4(x) (((x) >> S_MRRSTAT_BEAT4) & M_MRRSTAT_BEAT4)
68598 
68599 #define A_MC_UPCTL_MCFG1 0x4007c
68600 
68601 #define S_HW_EXIT_IDLE_EN    31
68602 #define V_HW_EXIT_IDLE_EN(x) ((x) << S_HW_EXIT_IDLE_EN)
68603 #define F_HW_EXIT_IDLE_EN    V_HW_EXIT_IDLE_EN(1U)
68604 
68605 #define S_HW_IDLE    16
68606 #define M_HW_IDLE    0xffU
68607 #define V_HW_IDLE(x) ((x) << S_HW_IDLE)
68608 #define G_HW_IDLE(x) (((x) >> S_HW_IDLE) & M_HW_IDLE)
68609 
68610 #define S_SR_IDLE    0
68611 #define M_SR_IDLE    0xffU
68612 #define V_SR_IDLE(x) ((x) << S_SR_IDLE)
68613 #define G_SR_IDLE(x) (((x) >> S_SR_IDLE) & M_SR_IDLE)
68614 
68615 #define A_MC_UPCTL_MCFG 0x40080
68616 
68617 #define S_MDDR_LPDDR2_CLK_STOP_IDLE    24
68618 #define M_MDDR_LPDDR2_CLK_STOP_IDLE    0xffU
68619 #define V_MDDR_LPDDR2_CLK_STOP_IDLE(x) ((x) << S_MDDR_LPDDR2_CLK_STOP_IDLE)
68620 #define G_MDDR_LPDDR2_CLK_STOP_IDLE(x) (((x) >> S_MDDR_LPDDR2_CLK_STOP_IDLE) & M_MDDR_LPDDR2_CLK_STOP_IDLE)
68621 
68622 #define S_MDDR_LPDDR2_EN    22
68623 #define M_MDDR_LPDDR2_EN    0x3U
68624 #define V_MDDR_LPDDR2_EN(x) ((x) << S_MDDR_LPDDR2_EN)
68625 #define G_MDDR_LPDDR2_EN(x) (((x) >> S_MDDR_LPDDR2_EN) & M_MDDR_LPDDR2_EN)
68626 
68627 #define S_MDDR_LPDDR2_BL    20
68628 #define M_MDDR_LPDDR2_BL    0x3U
68629 #define V_MDDR_LPDDR2_BL(x) ((x) << S_MDDR_LPDDR2_BL)
68630 #define G_MDDR_LPDDR2_BL(x) (((x) >> S_MDDR_LPDDR2_BL) & M_MDDR_LPDDR2_BL)
68631 
68632 #define S_LPDDR2_S4    6
68633 #define V_LPDDR2_S4(x) ((x) << S_LPDDR2_S4)
68634 #define F_LPDDR2_S4    V_LPDDR2_S4(1U)
68635 
68636 #define S_STAGGER_CS    4
68637 #define V_STAGGER_CS(x) ((x) << S_STAGGER_CS)
68638 #define F_STAGGER_CS    V_STAGGER_CS(1U)
68639 
68640 #define S_CKE_OR_EN    1
68641 #define V_CKE_OR_EN(x) ((x) << S_CKE_OR_EN)
68642 #define F_CKE_OR_EN    V_CKE_OR_EN(1U)
68643 
68644 #define A_MC_LMC_MCOPT1 0x40080
68645 
68646 #define S_MC_PROTOCOL    31
68647 #define V_MC_PROTOCOL(x) ((x) << S_MC_PROTOCOL)
68648 #define F_MC_PROTOCOL    V_MC_PROTOCOL(1U)
68649 
68650 #define S_DM_ENABLE    30
68651 #define V_DM_ENABLE(x) ((x) << S_DM_ENABLE)
68652 #define F_DM_ENABLE    V_DM_ENABLE(1U)
68653 
68654 #define S_T6_ECC_EN    29
68655 #define V_T6_ECC_EN(x) ((x) << S_T6_ECC_EN)
68656 #define F_T6_ECC_EN    V_T6_ECC_EN(1U)
68657 
68658 #define S_ECC_COR    28
68659 #define V_ECC_COR(x) ((x) << S_ECC_COR)
68660 #define F_ECC_COR    V_ECC_COR(1U)
68661 
68662 #define S_RDIMM    27
68663 #define V_RDIMM(x) ((x) << S_RDIMM)
68664 #define F_RDIMM    V_RDIMM(1U)
68665 
68666 #define S_PMUM    25
68667 #define M_PMUM    0x3U
68668 #define V_PMUM(x) ((x) << S_PMUM)
68669 #define G_PMUM(x) (((x) >> S_PMUM) & M_PMUM)
68670 
68671 #define S_WIDTH0    24
68672 #define V_WIDTH0(x) ((x) << S_WIDTH0)
68673 #define F_WIDTH0    V_WIDTH0(1U)
68674 
68675 #define S_PORT_ID_CHK_EN    23
68676 #define V_PORT_ID_CHK_EN(x) ((x) << S_PORT_ID_CHK_EN)
68677 #define F_PORT_ID_CHK_EN    V_PORT_ID_CHK_EN(1U)
68678 
68679 #define S_UIOS    22
68680 #define V_UIOS(x) ((x) << S_UIOS)
68681 #define F_UIOS    V_UIOS(1U)
68682 
68683 #define S_QUADCS_RDIMM    21
68684 #define V_QUADCS_RDIMM(x) ((x) << S_QUADCS_RDIMM)
68685 #define F_QUADCS_RDIMM    V_QUADCS_RDIMM(1U)
68686 
68687 #define S_ZQCL_EN    20
68688 #define V_ZQCL_EN(x) ((x) << S_ZQCL_EN)
68689 #define F_ZQCL_EN    V_ZQCL_EN(1U)
68690 
68691 #define S_WIDTH1    19
68692 #define V_WIDTH1(x) ((x) << S_WIDTH1)
68693 #define F_WIDTH1    V_WIDTH1(1U)
68694 
68695 #define S_WD_DLY    18
68696 #define V_WD_DLY(x) ((x) << S_WD_DLY)
68697 #define F_WD_DLY    V_WD_DLY(1U)
68698 
68699 #define S_QDEPTH    16
68700 #define M_QDEPTH    0x3U
68701 #define V_QDEPTH(x) ((x) << S_QDEPTH)
68702 #define G_QDEPTH(x) (((x) >> S_QDEPTH) & M_QDEPTH)
68703 
68704 #define S_RWOO    15
68705 #define V_RWOO(x) ((x) << S_RWOO)
68706 #define F_RWOO    V_RWOO(1U)
68707 
68708 #define S_WOOO    14
68709 #define V_WOOO(x) ((x) << S_WOOO)
68710 #define F_WOOO    V_WOOO(1U)
68711 
68712 #define S_DCOO    13
68713 #define V_DCOO(x) ((x) << S_DCOO)
68714 #define F_DCOO    V_DCOO(1U)
68715 
68716 #define S_DEF_REF    12
68717 #define V_DEF_REF(x) ((x) << S_DEF_REF)
68718 #define F_DEF_REF    V_DEF_REF(1U)
68719 
68720 #define S_DEV_TYPE    11
68721 #define V_DEV_TYPE(x) ((x) << S_DEV_TYPE)
68722 #define F_DEV_TYPE    V_DEV_TYPE(1U)
68723 
68724 #define S_CA_PTY_DLY    10
68725 #define V_CA_PTY_DLY(x) ((x) << S_CA_PTY_DLY)
68726 #define F_CA_PTY_DLY    V_CA_PTY_DLY(1U)
68727 
68728 #define S_ECC_MUX    8
68729 #define M_ECC_MUX    0x3U
68730 #define V_ECC_MUX(x) ((x) << S_ECC_MUX)
68731 #define G_ECC_MUX(x) (((x) >> S_ECC_MUX) & M_ECC_MUX)
68732 
68733 #define S_CE_THRESHOLD    0
68734 #define M_CE_THRESHOLD    0xffU
68735 #define V_CE_THRESHOLD(x) ((x) << S_CE_THRESHOLD)
68736 #define G_CE_THRESHOLD(x) (((x) >> S_CE_THRESHOLD) & M_CE_THRESHOLD)
68737 
68738 #define A_MC_UPCTL_PPCFG 0x40084
68739 #define A_MC_LMC_MCOPT2 0x40084
68740 
68741 #define S_SELF_REF_EN    31
68742 #define V_SELF_REF_EN(x) ((x) << S_SELF_REF_EN)
68743 #define F_SELF_REF_EN    V_SELF_REF_EN(1U)
68744 
68745 #define S_XSR_PREVENT    30
68746 #define V_XSR_PREVENT(x) ((x) << S_XSR_PREVENT)
68747 #define F_XSR_PREVENT    V_XSR_PREVENT(1U)
68748 
68749 #define S_INIT_START    29
68750 #define V_INIT_START(x) ((x) << S_INIT_START)
68751 #define F_INIT_START    V_INIT_START(1U)
68752 
68753 #define S_MC_ENABLE    28
68754 #define V_MC_ENABLE(x) ((x) << S_MC_ENABLE)
68755 #define F_MC_ENABLE    V_MC_ENABLE(1U)
68756 
68757 #define S_CLK_DISABLE    24
68758 #define M_CLK_DISABLE    0xfU
68759 #define V_CLK_DISABLE(x) ((x) << S_CLK_DISABLE)
68760 #define G_CLK_DISABLE(x) (((x) >> S_CLK_DISABLE) & M_CLK_DISABLE)
68761 
68762 #define S_RESET_RANK    20
68763 #define M_RESET_RANK    0xfU
68764 #define V_RESET_RANK(x) ((x) << S_RESET_RANK)
68765 #define G_RESET_RANK(x) (((x) >> S_RESET_RANK) & M_RESET_RANK)
68766 
68767 #define S_MCIF_COMP_PTY_EN    19
68768 #define V_MCIF_COMP_PTY_EN(x) ((x) << S_MCIF_COMP_PTY_EN)
68769 #define F_MCIF_COMP_PTY_EN    V_MCIF_COMP_PTY_EN(1U)
68770 
68771 #define S_CKE_OE    17
68772 #define V_CKE_OE(x) ((x) << S_CKE_OE)
68773 #define F_CKE_OE    V_CKE_OE(1U)
68774 
68775 #define S_RESET_OE    16
68776 #define V_RESET_OE(x) ((x) << S_RESET_OE)
68777 #define F_RESET_OE    V_RESET_OE(1U)
68778 
68779 #define S_DFI_PHYUD_CNTL    14
68780 #define V_DFI_PHYUD_CNTL(x) ((x) << S_DFI_PHYUD_CNTL)
68781 #define F_DFI_PHYUD_CNTL    V_DFI_PHYUD_CNTL(1U)
68782 
68783 #define S_DFI_PHYUD_ACK    13
68784 #define V_DFI_PHYUD_ACK(x) ((x) << S_DFI_PHYUD_ACK)
68785 #define F_DFI_PHYUD_ACK    V_DFI_PHYUD_ACK(1U)
68786 
68787 #define S_T6_DFI_INIT_START    12
68788 #define V_T6_DFI_INIT_START(x) ((x) << S_T6_DFI_INIT_START)
68789 #define F_T6_DFI_INIT_START    V_T6_DFI_INIT_START(1U)
68790 
68791 #define S_PM_ENABLE    8
68792 #define M_PM_ENABLE    0xfU
68793 #define V_PM_ENABLE(x) ((x) << S_PM_ENABLE)
68794 #define G_PM_ENABLE(x) (((x) >> S_PM_ENABLE) & M_PM_ENABLE)
68795 
68796 #define S_RD_DEFREF_CNT    4
68797 #define M_RD_DEFREF_CNT    0xfU
68798 #define V_RD_DEFREF_CNT(x) ((x) << S_RD_DEFREF_CNT)
68799 #define G_RD_DEFREF_CNT(x) (((x) >> S_RD_DEFREF_CNT) & M_RD_DEFREF_CNT)
68800 
68801 #define A_MC_UPCTL_MSTAT 0x40088
68802 
68803 #define S_SELF_REFRESH    2
68804 #define V_SELF_REFRESH(x) ((x) << S_SELF_REFRESH)
68805 #define F_SELF_REFRESH    V_SELF_REFRESH(1U)
68806 
68807 #define S_CLOCK_STOP    1
68808 #define V_CLOCK_STOP(x) ((x) << S_CLOCK_STOP)
68809 #define F_CLOCK_STOP    V_CLOCK_STOP(1U)
68810 
68811 #define A_MC_UPCTL_LPDDR2ZQCFG 0x4008c
68812 
68813 #define S_ZQCL_OP    24
68814 #define M_ZQCL_OP    0xffU
68815 #define V_ZQCL_OP(x) ((x) << S_ZQCL_OP)
68816 #define G_ZQCL_OP(x) (((x) >> S_ZQCL_OP) & M_ZQCL_OP)
68817 
68818 #define S_ZQCL_MA    16
68819 #define M_ZQCL_MA    0xffU
68820 #define V_ZQCL_MA(x) ((x) << S_ZQCL_MA)
68821 #define G_ZQCL_MA(x) (((x) >> S_ZQCL_MA) & M_ZQCL_MA)
68822 
68823 #define S_ZQCS_OP    8
68824 #define M_ZQCS_OP    0xffU
68825 #define V_ZQCS_OP(x) ((x) << S_ZQCS_OP)
68826 #define G_ZQCS_OP(x) (((x) >> S_ZQCS_OP) & M_ZQCS_OP)
68827 
68828 #define S_ZQCS_MA    0
68829 #define M_ZQCS_MA    0xffU
68830 #define V_ZQCS_MA(x) ((x) << S_ZQCS_MA)
68831 #define G_ZQCS_MA(x) (((x) >> S_ZQCS_MA) & M_ZQCS_MA)
68832 
68833 #define A_MC_UPCTL_DTUPDES 0x40094
68834 
68835 #define S_DTU_ERR_B7    7
68836 #define V_DTU_ERR_B7(x) ((x) << S_DTU_ERR_B7)
68837 #define F_DTU_ERR_B7    V_DTU_ERR_B7(1U)
68838 
68839 #define A_MC_UPCTL_DTUNA 0x40098
68840 #define A_MC_UPCTL_DTUNE 0x4009c
68841 #define A_MC_UPCTL_DTUPRD0 0x400a0
68842 #define A_MC_UPCTL_DTUPRD1 0x400a4
68843 #define A_MC_UPCTL_DTUPRD2 0x400a8
68844 #define A_MC_UPCTL_DTUPRD3 0x400ac
68845 #define A_MC_UPCTL_DTUAWDT 0x400b0
68846 #define A_MC_UPCTL_TOGCNT1U 0x400c0
68847 #define A_MC_UPCTL_TINIT 0x400c4
68848 #define A_MC_UPCTL_TRSTH 0x400c8
68849 #define A_MC_UPCTL_TOGCNT100N 0x400cc
68850 #define A_MC_UPCTL_TREFI 0x400d0
68851 #define A_MC_UPCTL_TMRD 0x400d4
68852 #define A_MC_UPCTL_TRFC 0x400d8
68853 
68854 #define S_T_RFC0    0
68855 #define M_T_RFC0    0x1ffU
68856 #define V_T_RFC0(x) ((x) << S_T_RFC0)
68857 #define G_T_RFC0(x) (((x) >> S_T_RFC0) & M_T_RFC0)
68858 
68859 #define A_MC_UPCTL_TRP 0x400dc
68860 
68861 #define S_PREA_EXTRA    16
68862 #define M_PREA_EXTRA    0x3U
68863 #define V_PREA_EXTRA(x) ((x) << S_PREA_EXTRA)
68864 #define G_PREA_EXTRA(x) (((x) >> S_PREA_EXTRA) & M_PREA_EXTRA)
68865 
68866 #define A_MC_UPCTL_TRTW 0x400e0
68867 
68868 #define S_T_RTW0    0
68869 #define M_T_RTW0    0xfU
68870 #define V_T_RTW0(x) ((x) << S_T_RTW0)
68871 #define G_T_RTW0(x) (((x) >> S_T_RTW0) & M_T_RTW0)
68872 
68873 #define A_MC_UPCTL_TAL 0x400e4
68874 #define A_MC_UPCTL_TCL 0x400e8
68875 #define A_MC_UPCTL_TCWL 0x400ec
68876 #define A_MC_UPCTL_TRAS 0x400f0
68877 #define A_MC_UPCTL_TRC 0x400f4
68878 #define A_MC_UPCTL_TRCD 0x400f8
68879 #define A_MC_UPCTL_TRRD 0x400fc
68880 #define A_MC_UPCTL_TRTP 0x40100
68881 
68882 #define S_T_RTP0    0
68883 #define M_T_RTP0    0xfU
68884 #define V_T_RTP0(x) ((x) << S_T_RTP0)
68885 #define G_T_RTP0(x) (((x) >> S_T_RTP0) & M_T_RTP0)
68886 
68887 #define A_MC_LMC_CFGR0 0x40100
68888 
68889 #define S_ROW_WIDTH    12
68890 #define M_ROW_WIDTH    0x7U
68891 #define V_ROW_WIDTH(x) ((x) << S_ROW_WIDTH)
68892 #define G_ROW_WIDTH(x) (((x) >> S_ROW_WIDTH) & M_ROW_WIDTH)
68893 
68894 #define S_ADDR_MODE    8
68895 #define M_ADDR_MODE    0xfU
68896 #define V_ADDR_MODE(x) ((x) << S_ADDR_MODE)
68897 #define G_ADDR_MODE(x) (((x) >> S_ADDR_MODE) & M_ADDR_MODE)
68898 
68899 #define S_MIRROR    4
68900 #define V_MIRROR(x) ((x) << S_MIRROR)
68901 #define F_MIRROR    V_MIRROR(1U)
68902 
68903 #define S_RANK_ENABLE    0
68904 #define V_RANK_ENABLE(x) ((x) << S_RANK_ENABLE)
68905 #define F_RANK_ENABLE    V_RANK_ENABLE(1U)
68906 
68907 #define A_MC_UPCTL_TWR 0x40104
68908 
68909 #define S_U_T_WR    0
68910 #define M_U_T_WR    0x1fU
68911 #define V_U_T_WR(x) ((x) << S_U_T_WR)
68912 #define G_U_T_WR(x) (((x) >> S_U_T_WR) & M_U_T_WR)
68913 
68914 #define A_MC_UPCTL_TWTR 0x40108
68915 
68916 #define S_T_WTR0    0
68917 #define M_T_WTR0    0xfU
68918 #define V_T_WTR0(x) ((x) << S_T_WTR0)
68919 #define G_T_WTR0(x) (((x) >> S_T_WTR0) & M_T_WTR0)
68920 
68921 #define A_MC_UPCTL_TEXSR 0x4010c
68922 #define A_MC_UPCTL_TXP 0x40110
68923 #define A_MC_UPCTL_TXPDLL 0x40114
68924 #define A_MC_UPCTL_TZQCS 0x40118
68925 #define A_MC_UPCTL_TZQCSI 0x4011c
68926 #define A_MC_UPCTL_TDQS 0x40120
68927 #define A_MC_UPCTL_TCKSRE 0x40124
68928 
68929 #define S_T_CKSRE0    0
68930 #define M_T_CKSRE0    0x1fU
68931 #define V_T_CKSRE0(x) ((x) << S_T_CKSRE0)
68932 #define G_T_CKSRE0(x) (((x) >> S_T_CKSRE0) & M_T_CKSRE0)
68933 
68934 #define A_MC_UPCTL_TCKSRX 0x40128
68935 
68936 #define S_T_CKSRX0    0
68937 #define M_T_CKSRX0    0x1fU
68938 #define V_T_CKSRX0(x) ((x) << S_T_CKSRX0)
68939 #define G_T_CKSRX0(x) (((x) >> S_T_CKSRX0) & M_T_CKSRX0)
68940 
68941 #define A_MC_UPCTL_TCKE 0x4012c
68942 #define A_MC_UPCTL_TMOD 0x40130
68943 
68944 #define S_T_MOD0    0
68945 #define M_T_MOD0    0x1fU
68946 #define V_T_MOD0(x) ((x) << S_T_MOD0)
68947 #define G_T_MOD0(x) (((x) >> S_T_MOD0) & M_T_MOD0)
68948 
68949 #define A_MC_UPCTL_TRSTL 0x40134
68950 
68951 #define S_T_RSTL    0
68952 #define M_T_RSTL    0x7fU
68953 #define V_T_RSTL(x) ((x) << S_T_RSTL)
68954 #define G_T_RSTL(x) (((x) >> S_T_RSTL) & M_T_RSTL)
68955 
68956 #define A_MC_UPCTL_TZQCL 0x40138
68957 #define A_MC_UPCTL_TMRR 0x4013c
68958 
68959 #define S_T_MRR    0
68960 #define M_T_MRR    0xffU
68961 #define V_T_MRR(x) ((x) << S_T_MRR)
68962 #define G_T_MRR(x) (((x) >> S_T_MRR) & M_T_MRR)
68963 
68964 #define A_MC_UPCTL_TCKESR 0x40140
68965 
68966 #define S_T_CKESR    0
68967 #define M_T_CKESR    0xfU
68968 #define V_T_CKESR(x) ((x) << S_T_CKESR)
68969 #define G_T_CKESR(x) (((x) >> S_T_CKESR) & M_T_CKESR)
68970 
68971 #define A_MC_LMC_INITSEQ0 0x40140
68972 
68973 #define S_INIT_ENABLE    31
68974 #define V_INIT_ENABLE(x) ((x) << S_INIT_ENABLE)
68975 #define F_INIT_ENABLE    V_INIT_ENABLE(1U)
68976 
68977 #define S_WAIT    16
68978 #define M_WAIT    0xfffU
68979 #define CXGBE_V_WAIT(x) ((x) << S_WAIT)
68980 #define G_WAIT(x) (((x) >> S_WAIT) & M_WAIT)
68981 
68982 #define S_EN_MULTI_RANK_SEL    4
68983 #define V_EN_MULTI_RANK_SEL(x) ((x) << S_EN_MULTI_RANK_SEL)
68984 #define F_EN_MULTI_RANK_SEL    V_EN_MULTI_RANK_SEL(1U)
68985 
68986 #define S_T6_RANK    0
68987 #define M_T6_RANK    0xfU
68988 #define V_T6_RANK(x) ((x) << S_T6_RANK)
68989 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
68990 
68991 #define A_MC_UPCTL_TDPD 0x40144
68992 
68993 #define S_T_DPD    0
68994 #define M_T_DPD    0x3ffU
68995 #define V_T_DPD(x) ((x) << S_T_DPD)
68996 #define G_T_DPD(x) (((x) >> S_T_DPD) & M_T_DPD)
68997 
68998 #define A_MC_LMC_CMD0 0x40144
68999 
69000 #define S_CMD    29
69001 #define M_CMD    0x7U
69002 #define V_CMD(x) ((x) << S_CMD)
69003 #define G_CMD(x) (((x) >> S_CMD) & M_CMD)
69004 
69005 #define S_CMD_ACTN    28
69006 #define V_CMD_ACTN(x) ((x) << S_CMD_ACTN)
69007 #define F_CMD_ACTN    V_CMD_ACTN(1U)
69008 
69009 #define S_BG1    23
69010 #define V_BG1(x) ((x) << S_BG1)
69011 #define F_BG1    V_BG1(1U)
69012 
69013 #define S_BANK    20
69014 #define M_BANK    0x7U
69015 #define V_BANK(x) ((x) << S_BANK)
69016 #define G_BANK(x) (((x) >> S_BANK) & M_BANK)
69017 
69018 #define A_MC_LMC_INITSEQ1 0x40148
69019 #define A_MC_LMC_CMD1 0x4014c
69020 #define A_MC_LMC_INITSEQ2 0x40150
69021 #define A_MC_LMC_CMD2 0x40154
69022 #define A_MC_LMC_INITSEQ3 0x40158
69023 #define A_MC_LMC_CMD3 0x4015c
69024 #define A_MC_LMC_INITSEQ4 0x40160
69025 #define A_MC_LMC_CMD4 0x40164
69026 #define A_MC_LMC_INITSEQ5 0x40168
69027 #define A_MC_LMC_CMD5 0x4016c
69028 #define A_MC_LMC_INITSEQ6 0x40170
69029 #define A_MC_LMC_CMD6 0x40174
69030 #define A_MC_LMC_INITSEQ7 0x40178
69031 #define A_MC_LMC_CMD7 0x4017c
69032 #define A_MC_UPCTL_ECCCFG 0x40180
69033 #define A_MC_LMC_INITSEQ8 0x40180
69034 #define A_MC_UPCTL_ECCTST 0x40184
69035 
69036 #define S_ECC_TEST_MASK0    0
69037 #define M_ECC_TEST_MASK0    0x7fU
69038 #define V_ECC_TEST_MASK0(x) ((x) << S_ECC_TEST_MASK0)
69039 #define G_ECC_TEST_MASK0(x) (((x) >> S_ECC_TEST_MASK0) & M_ECC_TEST_MASK0)
69040 
69041 #define A_MC_LMC_CMD8 0x40184
69042 #define A_MC_UPCTL_ECCCLR 0x40188
69043 #define A_MC_LMC_INITSEQ9 0x40188
69044 #define A_MC_UPCTL_ECCLOG 0x4018c
69045 #define A_MC_LMC_CMD9 0x4018c
69046 #define A_MC_LMC_INITSEQ10 0x40190
69047 #define A_MC_LMC_CMD10 0x40194
69048 #define A_MC_LMC_INITSEQ11 0x40198
69049 #define A_MC_LMC_CMD11 0x4019c
69050 #define A_MC_LMC_INITSEQ12 0x401a0
69051 #define A_MC_LMC_CMD12 0x401a4
69052 #define A_MC_LMC_INITSEQ13 0x401a8
69053 #define A_MC_LMC_CMD13 0x401ac
69054 #define A_MC_LMC_INITSEQ14 0x401b0
69055 #define A_MC_LMC_CMD14 0x401b4
69056 #define A_MC_LMC_INITSEQ15 0x401b8
69057 #define A_MC_LMC_CMD15 0x401bc
69058 #define A_MC_UPCTL_DTUWACTL 0x40200
69059 
69060 #define S_DTU_WR_ROW0    13
69061 #define M_DTU_WR_ROW0    0xffffU
69062 #define V_DTU_WR_ROW0(x) ((x) << S_DTU_WR_ROW0)
69063 #define G_DTU_WR_ROW0(x) (((x) >> S_DTU_WR_ROW0) & M_DTU_WR_ROW0)
69064 
69065 #define A_MC_LMC_SDTR0 0x40200
69066 
69067 #define S_REFI    16
69068 #define M_REFI    0xffffU
69069 #define V_REFI(x) ((x) << S_REFI)
69070 #define G_REFI(x) (((x) >> S_REFI) & M_REFI)
69071 
69072 #define S_T_RFC_XPR    0
69073 #define M_T_RFC_XPR    0xfffU
69074 #define V_T_RFC_XPR(x) ((x) << S_T_RFC_XPR)
69075 #define G_T_RFC_XPR(x) (((x) >> S_T_RFC_XPR) & M_T_RFC_XPR)
69076 
69077 #define A_MC_UPCTL_DTURACTL 0x40204
69078 
69079 #define S_DTU_RD_ROW0    13
69080 #define M_DTU_RD_ROW0    0xffffU
69081 #define V_DTU_RD_ROW0(x) ((x) << S_DTU_RD_ROW0)
69082 #define G_DTU_RD_ROW0(x) (((x) >> S_DTU_RD_ROW0) & M_DTU_RD_ROW0)
69083 
69084 #define A_MC_LMC_SDTR1 0x40204
69085 
69086 #define S_T_LEADOFF    31
69087 #define V_T_LEADOFF(x) ((x) << S_T_LEADOFF)
69088 #define F_T_LEADOFF    V_T_LEADOFF(1U)
69089 
69090 #define S_ODT_DELAY    30
69091 #define V_ODT_DELAY(x) ((x) << S_ODT_DELAY)
69092 #define F_ODT_DELAY    V_ODT_DELAY(1U)
69093 
69094 #define S_ODT_WIDTH    29
69095 #define V_ODT_WIDTH(x) ((x) << S_ODT_WIDTH)
69096 #define F_ODT_WIDTH    V_ODT_WIDTH(1U)
69097 
69098 #define S_T_WTRO    24
69099 #define M_T_WTRO    0xfU
69100 #define V_T_WTRO(x) ((x) << S_T_WTRO)
69101 #define G_T_WTRO(x) (((x) >> S_T_WTRO) & M_T_WTRO)
69102 
69103 #define S_T_RTWO    16
69104 #define M_T_RTWO    0xfU
69105 #define V_T_RTWO(x) ((x) << S_T_RTWO)
69106 #define G_T_RTWO(x) (((x) >> S_T_RTWO) & M_T_RTWO)
69107 
69108 #define S_T_RTW_ADJ    12
69109 #define M_T_RTW_ADJ    0xfU
69110 #define V_T_RTW_ADJ(x) ((x) << S_T_RTW_ADJ)
69111 #define G_T_RTW_ADJ(x) (((x) >> S_T_RTW_ADJ) & M_T_RTW_ADJ)
69112 
69113 #define S_T_WTWO    8
69114 #define M_T_WTWO    0xfU
69115 #define V_T_WTWO(x) ((x) << S_T_WTWO)
69116 #define G_T_WTWO(x) (((x) >> S_T_WTWO) & M_T_WTWO)
69117 
69118 #define S_T_RTRO    0
69119 #define M_T_RTRO    0xfU
69120 #define V_T_RTRO(x) ((x) << S_T_RTRO)
69121 #define G_T_RTRO(x) (((x) >> S_T_RTRO) & M_T_RTRO)
69122 
69123 #define A_MC_UPCTL_DTUCFG 0x40208
69124 #define A_MC_LMC_SDTR2 0x40208
69125 
69126 #define S_T6_T_CWL    28
69127 #define M_T6_T_CWL    0xfU
69128 #define V_T6_T_CWL(x) ((x) << S_T6_T_CWL)
69129 #define G_T6_T_CWL(x) (((x) >> S_T6_T_CWL) & M_T6_T_CWL)
69130 
69131 #define S_T_RCD0    24
69132 #define M_T_RCD0    0xfU
69133 #define V_T_RCD0(x) ((x) << S_T_RCD0)
69134 #define G_T_RCD0(x) (((x) >> S_T_RCD0) & M_T_RCD0)
69135 
69136 #define S_T_PL    20
69137 #define M_T_PL    0xfU
69138 #define V_T_PL(x) ((x) << S_T_PL)
69139 #define G_T_PL(x) (((x) >> S_T_PL) & M_T_PL)
69140 
69141 #define S_T_RP0    16
69142 #define M_T_RP0    0xfU
69143 #define V_T_RP0(x) ((x) << S_T_RP0)
69144 #define G_T_RP0(x) (((x) >> S_T_RP0) & M_T_RP0)
69145 
69146 #define S_T_RP1    15
69147 #define V_T_RP1(x) ((x) << S_T_RP1)
69148 #define F_T_RP1    V_T_RP1(1U)
69149 
69150 #define S_T_RCD1    14
69151 #define V_T_RCD1(x) ((x) << S_T_RCD1)
69152 #define F_T_RCD1    V_T_RCD1(1U)
69153 
69154 #define S_T6_T_RC    8
69155 #define M_T6_T_RC    0x3fU
69156 #define V_T6_T_RC(x) ((x) << S_T6_T_RC)
69157 #define G_T6_T_RC(x) (((x) >> S_T6_T_RC) & M_T6_T_RC)
69158 
69159 #define A_MC_UPCTL_DTUECTL 0x4020c
69160 #define A_MC_LMC_SDTR3 0x4020c
69161 
69162 #define S_T_WTR_S    28
69163 #define M_T_WTR_S    0xfU
69164 #define V_T_WTR_S(x) ((x) << S_T_WTR_S)
69165 #define G_T_WTR_S(x) (((x) >> S_T_WTR_S) & M_T_WTR_S)
69166 
69167 #define S_T6_T_WTR    24
69168 #define M_T6_T_WTR    0xfU
69169 #define V_T6_T_WTR(x) ((x) << S_T6_T_WTR)
69170 #define G_T6_T_WTR(x) (((x) >> S_T6_T_WTR) & M_T6_T_WTR)
69171 
69172 #define S_FAW_ADJ    20
69173 #define M_FAW_ADJ    0x3U
69174 #define V_FAW_ADJ(x) ((x) << S_FAW_ADJ)
69175 #define G_FAW_ADJ(x) (((x) >> S_FAW_ADJ) & M_FAW_ADJ)
69176 
69177 #define S_T6_T_RTP    16
69178 #define M_T6_T_RTP    0xfU
69179 #define V_T6_T_RTP(x) ((x) << S_T6_T_RTP)
69180 #define G_T6_T_RTP(x) (((x) >> S_T6_T_RTP) & M_T6_T_RTP)
69181 
69182 #define S_T_RRD_L    12
69183 #define M_T_RRD_L    0xfU
69184 #define V_T_RRD_L(x) ((x) << S_T_RRD_L)
69185 #define G_T_RRD_L(x) (((x) >> S_T_RRD_L) & M_T_RRD_L)
69186 
69187 #define S_T6_T_RRD    8
69188 #define M_T6_T_RRD    0xfU
69189 #define V_T6_T_RRD(x) ((x) << S_T6_T_RRD)
69190 #define G_T6_T_RRD(x) (((x) >> S_T6_T_RRD) & M_T6_T_RRD)
69191 
69192 #define S_T_XSDLL    0
69193 #define M_T_XSDLL    0xffU
69194 #define V_T_XSDLL(x) ((x) << S_T_XSDLL)
69195 #define G_T_XSDLL(x) (((x) >> S_T_XSDLL) & M_T_XSDLL)
69196 
69197 #define A_MC_UPCTL_DTUWD0 0x40210
69198 #define A_MC_LMC_SDTR4 0x40210
69199 
69200 #define S_T_RDDATA_EN    24
69201 #define M_T_RDDATA_EN    0x7fU
69202 #define V_T_RDDATA_EN(x) ((x) << S_T_RDDATA_EN)
69203 #define G_T_RDDATA_EN(x) (((x) >> S_T_RDDATA_EN) & M_T_RDDATA_EN)
69204 
69205 #define S_T_SYS_RDLAT    16
69206 #define M_T_SYS_RDLAT    0x3fU
69207 #define V_T_SYS_RDLAT(x) ((x) << S_T_SYS_RDLAT)
69208 #define G_T_SYS_RDLAT(x) (((x) >> S_T_SYS_RDLAT) & M_T_SYS_RDLAT)
69209 
69210 #define S_T_CCD_L    12
69211 #define M_T_CCD_L    0xfU
69212 #define V_T_CCD_L(x) ((x) << S_T_CCD_L)
69213 #define G_T_CCD_L(x) (((x) >> S_T_CCD_L) & M_T_CCD_L)
69214 
69215 #define S_T_CCD    8
69216 #define M_T_CCD    0x7U
69217 #define V_T_CCD(x) ((x) << S_T_CCD)
69218 #define G_T_CCD(x) (((x) >> S_T_CCD) & M_T_CCD)
69219 
69220 #define S_T_CPDED    5
69221 #define M_T_CPDED    0x7U
69222 #define V_T_CPDED(x) ((x) << S_T_CPDED)
69223 #define G_T_CPDED(x) (((x) >> S_T_CPDED) & M_T_CPDED)
69224 
69225 #define S_T6_T_MOD    0
69226 #define M_T6_T_MOD    0x1fU
69227 #define V_T6_T_MOD(x) ((x) << S_T6_T_MOD)
69228 #define G_T6_T_MOD(x) (((x) >> S_T6_T_MOD) & M_T6_T_MOD)
69229 
69230 #define A_MC_UPCTL_DTUWD1 0x40214
69231 #define A_MC_LMC_SDTR5 0x40214
69232 
69233 #define S_T_PHY_WRDATA    24
69234 #define M_T_PHY_WRDATA    0x7U
69235 #define V_T_PHY_WRDATA(x) ((x) << S_T_PHY_WRDATA)
69236 #define G_T_PHY_WRDATA(x) (((x) >> S_T_PHY_WRDATA) & M_T_PHY_WRDATA)
69237 
69238 #define S_T_PHY_WRLAT    16
69239 #define M_T_PHY_WRLAT    0x1fU
69240 #define V_T_PHY_WRLAT(x) ((x) << S_T_PHY_WRLAT)
69241 #define G_T_PHY_WRLAT(x) (((x) >> S_T_PHY_WRLAT) & M_T_PHY_WRLAT)
69242 
69243 #define A_MC_UPCTL_DTUWD2 0x40218
69244 #define A_MC_UPCTL_DTUWD3 0x4021c
69245 #define A_MC_UPCTL_DTUWDM 0x40220
69246 #define A_MC_UPCTL_DTURD0 0x40224
69247 #define A_MC_UPCTL_DTURD1 0x40228
69248 #define A_MC_LMC_DBG0 0x40228
69249 
69250 #define S_T_SYS_RDLAT_DBG    16
69251 #define M_T_SYS_RDLAT_DBG    0x1fU
69252 #define V_T_SYS_RDLAT_DBG(x) ((x) << S_T_SYS_RDLAT_DBG)
69253 #define G_T_SYS_RDLAT_DBG(x) (((x) >> S_T_SYS_RDLAT_DBG) & M_T_SYS_RDLAT_DBG)
69254 
69255 #define A_MC_UPCTL_DTURD2 0x4022c
69256 #define A_MC_UPCTL_DTURD3 0x40230
69257 #define A_MC_UPCTL_DTULFSRWD 0x40234
69258 #define A_MC_UPCTL_DTULFSRRD 0x40238
69259 #define A_MC_UPCTL_DTUEAF 0x4023c
69260 
69261 #define S_EA_ROW0    13
69262 #define M_EA_ROW0    0xffffU
69263 #define V_EA_ROW0(x) ((x) << S_EA_ROW0)
69264 #define G_EA_ROW0(x) (((x) >> S_EA_ROW0) & M_EA_ROW0)
69265 
69266 #define A_MC_UPCTL_DFITCTRLDELAY 0x40240
69267 
69268 #define S_TCTRL_DELAY    0
69269 #define M_TCTRL_DELAY    0xfU
69270 #define V_TCTRL_DELAY(x) ((x) << S_TCTRL_DELAY)
69271 #define G_TCTRL_DELAY(x) (((x) >> S_TCTRL_DELAY) & M_TCTRL_DELAY)
69272 
69273 #define A_MC_LMC_SMR0 0x40240
69274 
69275 #define S_SMR0_RFU0    13
69276 #define M_SMR0_RFU0    0x7U
69277 #define V_SMR0_RFU0(x) ((x) << S_SMR0_RFU0)
69278 #define G_SMR0_RFU0(x) (((x) >> S_SMR0_RFU0) & M_SMR0_RFU0)
69279 
69280 #define S_PPD    12
69281 #define V_PPD(x) ((x) << S_PPD)
69282 #define F_PPD    V_PPD(1U)
69283 
69284 #define S_WR_RTP    9
69285 #define M_WR_RTP    0x7U
69286 #define V_WR_RTP(x) ((x) << S_WR_RTP)
69287 #define G_WR_RTP(x) (((x) >> S_WR_RTP) & M_WR_RTP)
69288 
69289 #define S_SMR0_DLL    8
69290 #define V_SMR0_DLL(x) ((x) << S_SMR0_DLL)
69291 #define F_SMR0_DLL    V_SMR0_DLL(1U)
69292 
69293 #define S_TM    7
69294 #define V_TM(x) ((x) << S_TM)
69295 #define F_TM    V_TM(1U)
69296 
69297 #define S_CL31    4
69298 #define M_CL31    0x7U
69299 #define V_CL31(x) ((x) << S_CL31)
69300 #define G_CL31(x) (((x) >> S_CL31) & M_CL31)
69301 
69302 #define S_RBT    3
69303 #define V_RBT(x) ((x) << S_RBT)
69304 #define F_RBT    V_RBT(1U)
69305 
69306 #define S_CL0    2
69307 #define V_CL0(x) ((x) << S_CL0)
69308 #define F_CL0    V_CL0(1U)
69309 
69310 #define S_BL    0
69311 #define M_BL    0x3U
69312 #define V_BL(x) ((x) << S_BL)
69313 #define G_BL(x) (((x) >> S_BL) & M_BL)
69314 
69315 #define A_MC_UPCTL_DFIODTCFG 0x40244
69316 
69317 #define S_RANK3_ODT_WRITE_NSEL    26
69318 #define V_RANK3_ODT_WRITE_NSEL(x) ((x) << S_RANK3_ODT_WRITE_NSEL)
69319 #define F_RANK3_ODT_WRITE_NSEL    V_RANK3_ODT_WRITE_NSEL(1U)
69320 
69321 #define A_MC_LMC_SMR1 0x40244
69322 
69323 #define S_QOFF    12
69324 #define V_QOFF(x) ((x) << S_QOFF)
69325 #define F_QOFF    V_QOFF(1U)
69326 
69327 #define S_TDQS    11
69328 #define V_TDQS(x) ((x) << S_TDQS)
69329 #define F_TDQS    V_TDQS(1U)
69330 
69331 #define S_SMR1_RFU0    10
69332 #define V_SMR1_RFU0(x) ((x) << S_SMR1_RFU0)
69333 #define F_SMR1_RFU0    V_SMR1_RFU0(1U)
69334 
69335 #define S_RTT_NOM0    9
69336 #define V_RTT_NOM0(x) ((x) << S_RTT_NOM0)
69337 #define F_RTT_NOM0    V_RTT_NOM0(1U)
69338 
69339 #define S_SMR1_RFU1    8
69340 #define V_SMR1_RFU1(x) ((x) << S_SMR1_RFU1)
69341 #define F_SMR1_RFU1    V_SMR1_RFU1(1U)
69342 
69343 #define S_WR_LEVEL    7
69344 #define V_WR_LEVEL(x) ((x) << S_WR_LEVEL)
69345 #define F_WR_LEVEL    V_WR_LEVEL(1U)
69346 
69347 #define S_RTT_NOM1    6
69348 #define V_RTT_NOM1(x) ((x) << S_RTT_NOM1)
69349 #define F_RTT_NOM1    V_RTT_NOM1(1U)
69350 
69351 #define S_DIC0    5
69352 #define V_DIC0(x) ((x) << S_DIC0)
69353 #define F_DIC0    V_DIC0(1U)
69354 
69355 #define S_AL    3
69356 #define M_AL    0x3U
69357 #define V_AL(x) ((x) << S_AL)
69358 #define G_AL(x) (((x) >> S_AL) & M_AL)
69359 
69360 #define S_RTT_NOM2    2
69361 #define V_RTT_NOM2(x) ((x) << S_RTT_NOM2)
69362 #define F_RTT_NOM2    V_RTT_NOM2(1U)
69363 
69364 #define S_DIC1    1
69365 #define V_DIC1(x) ((x) << S_DIC1)
69366 #define F_DIC1    V_DIC1(1U)
69367 
69368 #define S_SMR1_DLL    0
69369 #define V_SMR1_DLL(x) ((x) << S_SMR1_DLL)
69370 #define F_SMR1_DLL    V_SMR1_DLL(1U)
69371 
69372 #define A_MC_UPCTL_DFIODTCFG1 0x40248
69373 
69374 #define S_ODT_LEN_B8_R    24
69375 #define M_ODT_LEN_B8_R    0x7U
69376 #define V_ODT_LEN_B8_R(x) ((x) << S_ODT_LEN_B8_R)
69377 #define G_ODT_LEN_B8_R(x) (((x) >> S_ODT_LEN_B8_R) & M_ODT_LEN_B8_R)
69378 
69379 #define S_ODT_LEN_BL8_W    16
69380 #define M_ODT_LEN_BL8_W    0x7U
69381 #define V_ODT_LEN_BL8_W(x) ((x) << S_ODT_LEN_BL8_W)
69382 #define G_ODT_LEN_BL8_W(x) (((x) >> S_ODT_LEN_BL8_W) & M_ODT_LEN_BL8_W)
69383 
69384 #define S_ODT_LAT_R    8
69385 #define M_ODT_LAT_R    0x1fU
69386 #define V_ODT_LAT_R(x) ((x) << S_ODT_LAT_R)
69387 #define G_ODT_LAT_R(x) (((x) >> S_ODT_LAT_R) & M_ODT_LAT_R)
69388 
69389 #define S_ODT_LAT_W    0
69390 #define M_ODT_LAT_W    0x1fU
69391 #define V_ODT_LAT_W(x) ((x) << S_ODT_LAT_W)
69392 #define G_ODT_LAT_W(x) (((x) >> S_ODT_LAT_W) & M_ODT_LAT_W)
69393 
69394 #define A_MC_LMC_SMR2 0x40248
69395 
69396 #define S_WR_CRC    12
69397 #define V_WR_CRC(x) ((x) << S_WR_CRC)
69398 #define F_WR_CRC    V_WR_CRC(1U)
69399 
69400 #define S_RD_CRC    11
69401 #define V_RD_CRC(x) ((x) << S_RD_CRC)
69402 #define F_RD_CRC    V_RD_CRC(1U)
69403 
69404 #define S_RTT_WR    9
69405 #define M_RTT_WR    0x3U
69406 #define V_RTT_WR(x) ((x) << S_RTT_WR)
69407 #define G_RTT_WR(x) (((x) >> S_RTT_WR) & M_RTT_WR)
69408 
69409 #define S_SMR2_RFU0    8
69410 #define V_SMR2_RFU0(x) ((x) << S_SMR2_RFU0)
69411 #define F_SMR2_RFU0    V_SMR2_RFU0(1U)
69412 
69413 #define S_SRT_ASR1    7
69414 #define V_SRT_ASR1(x) ((x) << S_SRT_ASR1)
69415 #define F_SRT_ASR1    V_SRT_ASR1(1U)
69416 
69417 #define S_ASR0    6
69418 #define V_ASR0(x) ((x) << S_ASR0)
69419 #define F_ASR0    V_ASR0(1U)
69420 
69421 #define S_CWL    3
69422 #define M_CWL    0x7U
69423 #define V_CWL(x) ((x) << S_CWL)
69424 #define G_CWL(x) (((x) >> S_CWL) & M_CWL)
69425 
69426 #define S_PASR    0
69427 #define M_PASR    0x7U
69428 #define V_PASR(x) ((x) << S_PASR)
69429 #define G_PASR(x) (((x) >> S_PASR) & M_PASR)
69430 
69431 #define A_MC_UPCTL_DFIODTRANKMAP 0x4024c
69432 
69433 #define S_ODT_RANK_MAP3    12
69434 #define M_ODT_RANK_MAP3    0xfU
69435 #define V_ODT_RANK_MAP3(x) ((x) << S_ODT_RANK_MAP3)
69436 #define G_ODT_RANK_MAP3(x) (((x) >> S_ODT_RANK_MAP3) & M_ODT_RANK_MAP3)
69437 
69438 #define S_ODT_RANK_MAP2    8
69439 #define M_ODT_RANK_MAP2    0xfU
69440 #define V_ODT_RANK_MAP2(x) ((x) << S_ODT_RANK_MAP2)
69441 #define G_ODT_RANK_MAP2(x) (((x) >> S_ODT_RANK_MAP2) & M_ODT_RANK_MAP2)
69442 
69443 #define S_ODT_RANK_MAP1    4
69444 #define M_ODT_RANK_MAP1    0xfU
69445 #define V_ODT_RANK_MAP1(x) ((x) << S_ODT_RANK_MAP1)
69446 #define G_ODT_RANK_MAP1(x) (((x) >> S_ODT_RANK_MAP1) & M_ODT_RANK_MAP1)
69447 
69448 #define S_ODT_RANK_MAP0    0
69449 #define M_ODT_RANK_MAP0    0xfU
69450 #define V_ODT_RANK_MAP0(x) ((x) << S_ODT_RANK_MAP0)
69451 #define G_ODT_RANK_MAP0(x) (((x) >> S_ODT_RANK_MAP0) & M_ODT_RANK_MAP0)
69452 
69453 #define A_MC_LMC_SMR3 0x4024c
69454 
69455 #define S_MPR_RD_FMT    11
69456 #define M_MPR_RD_FMT    0x3U
69457 #define V_MPR_RD_FMT(x) ((x) << S_MPR_RD_FMT)
69458 #define G_MPR_RD_FMT(x) (((x) >> S_MPR_RD_FMT) & M_MPR_RD_FMT)
69459 
69460 #define S_SMR3_RFU0    9
69461 #define M_SMR3_RFU0    0x3U
69462 #define V_SMR3_RFU0(x) ((x) << S_SMR3_RFU0)
69463 #define G_SMR3_RFU0(x) (((x) >> S_SMR3_RFU0) & M_SMR3_RFU0)
69464 
69465 #define S_FGR_MODE    6
69466 #define M_FGR_MODE    0x7U
69467 #define V_FGR_MODE(x) ((x) << S_FGR_MODE)
69468 #define G_FGR_MODE(x) (((x) >> S_FGR_MODE) & M_FGR_MODE)
69469 
69470 #define S_MRS_RDO    5
69471 #define V_MRS_RDO(x) ((x) << S_MRS_RDO)
69472 #define F_MRS_RDO    V_MRS_RDO(1U)
69473 
69474 #define S_DRAM_ADR    4
69475 #define V_DRAM_ADR(x) ((x) << S_DRAM_ADR)
69476 #define F_DRAM_ADR    V_DRAM_ADR(1U)
69477 
69478 #define S_GD_MODE    3
69479 #define V_GD_MODE(x) ((x) << S_GD_MODE)
69480 #define F_GD_MODE    V_GD_MODE(1U)
69481 
69482 #define S_MPR    2
69483 #define V_MPR(x) ((x) << S_MPR)
69484 #define F_MPR    V_MPR(1U)
69485 
69486 #define S_MPR_SEL    0
69487 #define M_MPR_SEL    0x3U
69488 #define V_MPR_SEL(x) ((x) << S_MPR_SEL)
69489 #define G_MPR_SEL(x) (((x) >> S_MPR_SEL) & M_MPR_SEL)
69490 
69491 #define A_MC_UPCTL_DFITPHYWRDATA 0x40250
69492 
69493 #define S_TPHY_WRDATA    0
69494 #define M_TPHY_WRDATA    0x1fU
69495 #define V_TPHY_WRDATA(x) ((x) << S_TPHY_WRDATA)
69496 #define G_TPHY_WRDATA(x) (((x) >> S_TPHY_WRDATA) & M_TPHY_WRDATA)
69497 
69498 #define A_MC_LMC_SMR4 0x40250
69499 
69500 #define S_WR_PRE    12
69501 #define V_WR_PRE(x) ((x) << S_WR_PRE)
69502 #define F_WR_PRE    V_WR_PRE(1U)
69503 
69504 #define S_RD_PRE    11
69505 #define V_RD_PRE(x) ((x) << S_RD_PRE)
69506 #define F_RD_PRE    V_RD_PRE(1U)
69507 
69508 #define S_RPT_MODE    10
69509 #define V_RPT_MODE(x) ((x) << S_RPT_MODE)
69510 #define F_RPT_MODE    V_RPT_MODE(1U)
69511 
69512 #define S_FESR_MODE    9
69513 #define V_FESR_MODE(x) ((x) << S_FESR_MODE)
69514 #define F_FESR_MODE    V_FESR_MODE(1U)
69515 
69516 #define S_CS_LAT_MODE    6
69517 #define M_CS_LAT_MODE    0x7U
69518 #define V_CS_LAT_MODE(x) ((x) << S_CS_LAT_MODE)
69519 #define G_CS_LAT_MODE(x) (((x) >> S_CS_LAT_MODE) & M_CS_LAT_MODE)
69520 
69521 #define S_ALERT_STAT    5
69522 #define V_ALERT_STAT(x) ((x) << S_ALERT_STAT)
69523 #define F_ALERT_STAT    V_ALERT_STAT(1U)
69524 
69525 #define S_IVM_MODE    4
69526 #define V_IVM_MODE(x) ((x) << S_IVM_MODE)
69527 #define F_IVM_MODE    V_IVM_MODE(1U)
69528 
69529 #define S_TCR_MODE    3
69530 #define V_TCR_MODE(x) ((x) << S_TCR_MODE)
69531 #define F_TCR_MODE    V_TCR_MODE(1U)
69532 
69533 #define S_TCR_RANGE    2
69534 #define V_TCR_RANGE(x) ((x) << S_TCR_RANGE)
69535 #define F_TCR_RANGE    V_TCR_RANGE(1U)
69536 
69537 #define S_MPD_MODE    1
69538 #define V_MPD_MODE(x) ((x) << S_MPD_MODE)
69539 #define F_MPD_MODE    V_MPD_MODE(1U)
69540 
69541 #define S_SMR4_RFU    0
69542 #define V_SMR4_RFU(x) ((x) << S_SMR4_RFU)
69543 #define F_SMR4_RFU    V_SMR4_RFU(1U)
69544 
69545 #define A_MC_UPCTL_DFITPHYWRLAT 0x40254
69546 
69547 #define S_TPHY_WRLAT    0
69548 #define M_TPHY_WRLAT    0x1fU
69549 #define V_TPHY_WRLAT(x) ((x) << S_TPHY_WRLAT)
69550 #define G_TPHY_WRLAT(x) (((x) >> S_TPHY_WRLAT) & M_TPHY_WRLAT)
69551 
69552 #define A_MC_LMC_SMR5 0x40254
69553 
69554 #define S_RD_DBI    11
69555 #define V_RD_DBI(x) ((x) << S_RD_DBI)
69556 #define F_RD_DBI    V_RD_DBI(1U)
69557 
69558 #define S_WR_DBI    10
69559 #define V_WR_DBI(x) ((x) << S_WR_DBI)
69560 #define F_WR_DBI    V_WR_DBI(1U)
69561 
69562 #define S_DM_MODE    9
69563 #define V_DM_MODE(x) ((x) << S_DM_MODE)
69564 #define F_DM_MODE    V_DM_MODE(1U)
69565 
69566 #define S_RTT_PARK    6
69567 #define M_RTT_PARK    0x7U
69568 #define V_RTT_PARK(x) ((x) << S_RTT_PARK)
69569 #define G_RTT_PARK(x) (((x) >> S_RTT_PARK) & M_RTT_PARK)
69570 
69571 #define S_SMR5_RFU    5
69572 #define V_SMR5_RFU(x) ((x) << S_SMR5_RFU)
69573 #define F_SMR5_RFU    V_SMR5_RFU(1U)
69574 
69575 #define S_PAR_ERR_STAT    4
69576 #define V_PAR_ERR_STAT(x) ((x) << S_PAR_ERR_STAT)
69577 #define F_PAR_ERR_STAT    V_PAR_ERR_STAT(1U)
69578 
69579 #define S_CRC_CLEAR    3
69580 #define V_CRC_CLEAR(x) ((x) << S_CRC_CLEAR)
69581 #define F_CRC_CLEAR    V_CRC_CLEAR(1U)
69582 
69583 #define S_PAR_LAT_MODE    0
69584 #define M_PAR_LAT_MODE    0x7U
69585 #define V_PAR_LAT_MODE(x) ((x) << S_PAR_LAT_MODE)
69586 #define G_PAR_LAT_MODE(x) (((x) >> S_PAR_LAT_MODE) & M_PAR_LAT_MODE)
69587 
69588 #define A_MC_LMC_SMR6 0x40258
69589 
69590 #define S_TCCD_L    10
69591 #define M_TCCD_L    0x7U
69592 #define V_TCCD_L(x) ((x) << S_TCCD_L)
69593 #define G_TCCD_L(x) (((x) >> S_TCCD_L) & M_TCCD_L)
69594 
69595 #define S_SRM6_RFU    7
69596 #define M_SRM6_RFU    0x7U
69597 #define V_SRM6_RFU(x) ((x) << S_SRM6_RFU)
69598 #define G_SRM6_RFU(x) (((x) >> S_SRM6_RFU) & M_SRM6_RFU)
69599 
69600 #define S_VREF_DQ_RANGE    6
69601 #define V_VREF_DQ_RANGE(x) ((x) << S_VREF_DQ_RANGE)
69602 #define F_VREF_DQ_RANGE    V_VREF_DQ_RANGE(1U)
69603 
69604 #define S_VREF_DQ_VALUE    0
69605 #define M_VREF_DQ_VALUE    0x3fU
69606 #define V_VREF_DQ_VALUE(x) ((x) << S_VREF_DQ_VALUE)
69607 #define G_VREF_DQ_VALUE(x) (((x) >> S_VREF_DQ_VALUE) & M_VREF_DQ_VALUE)
69608 
69609 #define A_MC_UPCTL_DFITRDDATAEN 0x40260
69610 
69611 #define S_TRDDATA_EN    0
69612 #define M_TRDDATA_EN    0x1fU
69613 #define V_TRDDATA_EN(x) ((x) << S_TRDDATA_EN)
69614 #define G_TRDDATA_EN(x) (((x) >> S_TRDDATA_EN) & M_TRDDATA_EN)
69615 
69616 #define A_MC_UPCTL_DFITPHYRDLAT 0x40264
69617 
69618 #define S_TPHY_RDLAT    0
69619 #define M_TPHY_RDLAT    0x3fU
69620 #define V_TPHY_RDLAT(x) ((x) << S_TPHY_RDLAT)
69621 #define G_TPHY_RDLAT(x) (((x) >> S_TPHY_RDLAT) & M_TPHY_RDLAT)
69622 
69623 #define A_MC_UPCTL_DFITPHYUPDTYPE0 0x40270
69624 
69625 #define S_TPHYUPD_TYPE0    0
69626 #define M_TPHYUPD_TYPE0    0xfffU
69627 #define V_TPHYUPD_TYPE0(x) ((x) << S_TPHYUPD_TYPE0)
69628 #define G_TPHYUPD_TYPE0(x) (((x) >> S_TPHYUPD_TYPE0) & M_TPHYUPD_TYPE0)
69629 
69630 #define A_MC_UPCTL_DFITPHYUPDTYPE1 0x40274
69631 
69632 #define S_TPHYUPD_TYPE1    0
69633 #define M_TPHYUPD_TYPE1    0xfffU
69634 #define V_TPHYUPD_TYPE1(x) ((x) << S_TPHYUPD_TYPE1)
69635 #define G_TPHYUPD_TYPE1(x) (((x) >> S_TPHYUPD_TYPE1) & M_TPHYUPD_TYPE1)
69636 
69637 #define A_MC_UPCTL_DFITPHYUPDTYPE2 0x40278
69638 
69639 #define S_TPHYUPD_TYPE2    0
69640 #define M_TPHYUPD_TYPE2    0xfffU
69641 #define V_TPHYUPD_TYPE2(x) ((x) << S_TPHYUPD_TYPE2)
69642 #define G_TPHYUPD_TYPE2(x) (((x) >> S_TPHYUPD_TYPE2) & M_TPHYUPD_TYPE2)
69643 
69644 #define A_MC_UPCTL_DFITPHYUPDTYPE3 0x4027c
69645 
69646 #define S_TPHYUPD_TYPE3    0
69647 #define M_TPHYUPD_TYPE3    0xfffU
69648 #define V_TPHYUPD_TYPE3(x) ((x) << S_TPHYUPD_TYPE3)
69649 #define G_TPHYUPD_TYPE3(x) (((x) >> S_TPHYUPD_TYPE3) & M_TPHYUPD_TYPE3)
69650 
69651 #define A_MC_UPCTL_DFITCTRLUPDMIN 0x40280
69652 
69653 #define S_TCTRLUPD_MIN    0
69654 #define M_TCTRLUPD_MIN    0xffffU
69655 #define V_TCTRLUPD_MIN(x) ((x) << S_TCTRLUPD_MIN)
69656 #define G_TCTRLUPD_MIN(x) (((x) >> S_TCTRLUPD_MIN) & M_TCTRLUPD_MIN)
69657 
69658 #define A_MC_LMC_ODTR0 0x40280
69659 
69660 #define S_RK0W    25
69661 #define V_RK0W(x) ((x) << S_RK0W)
69662 #define F_RK0W    V_RK0W(1U)
69663 
69664 #define S_RK0R    24
69665 #define V_RK0R(x) ((x) << S_RK0R)
69666 #define F_RK0R    V_RK0R(1U)
69667 
69668 #define A_MC_UPCTL_DFITCTRLUPDMAX 0x40284
69669 
69670 #define S_TCTRLUPD_MAX    0
69671 #define M_TCTRLUPD_MAX    0xffffU
69672 #define V_TCTRLUPD_MAX(x) ((x) << S_TCTRLUPD_MAX)
69673 #define G_TCTRLUPD_MAX(x) (((x) >> S_TCTRLUPD_MAX) & M_TCTRLUPD_MAX)
69674 
69675 #define A_MC_UPCTL_DFITCTRLUPDDLY 0x40288
69676 
69677 #define S_TCTRLUPD_DLY    0
69678 #define M_TCTRLUPD_DLY    0xfU
69679 #define V_TCTRLUPD_DLY(x) ((x) << S_TCTRLUPD_DLY)
69680 #define G_TCTRLUPD_DLY(x) (((x) >> S_TCTRLUPD_DLY) & M_TCTRLUPD_DLY)
69681 
69682 #define A_MC_UPCTL_DFIUPDCFG 0x40290
69683 
69684 #define S_DFI_PHYUPD_EN    1
69685 #define V_DFI_PHYUPD_EN(x) ((x) << S_DFI_PHYUPD_EN)
69686 #define F_DFI_PHYUPD_EN    V_DFI_PHYUPD_EN(1U)
69687 
69688 #define S_DFI_CTRLUPD_EN    0
69689 #define V_DFI_CTRLUPD_EN(x) ((x) << S_DFI_CTRLUPD_EN)
69690 #define F_DFI_CTRLUPD_EN    V_DFI_CTRLUPD_EN(1U)
69691 
69692 #define A_MC_UPCTL_DFITREFMSKI 0x40294
69693 
69694 #define S_TREFMSKI    0
69695 #define M_TREFMSKI    0xffU
69696 #define V_TREFMSKI(x) ((x) << S_TREFMSKI)
69697 #define G_TREFMSKI(x) (((x) >> S_TREFMSKI) & M_TREFMSKI)
69698 
69699 #define A_MC_UPCTL_DFITCTRLUPDI 0x40298
69700 #define A_MC_UPCTL_DFITRCFG0 0x402ac
69701 
69702 #define S_DFI_WRLVL_RANK_SEL    16
69703 #define M_DFI_WRLVL_RANK_SEL    0xfU
69704 #define V_DFI_WRLVL_RANK_SEL(x) ((x) << S_DFI_WRLVL_RANK_SEL)
69705 #define G_DFI_WRLVL_RANK_SEL(x) (((x) >> S_DFI_WRLVL_RANK_SEL) & M_DFI_WRLVL_RANK_SEL)
69706 
69707 #define S_DFI_RDLVL_EDGE    4
69708 #define M_DFI_RDLVL_EDGE    0x1ffU
69709 #define V_DFI_RDLVL_EDGE(x) ((x) << S_DFI_RDLVL_EDGE)
69710 #define G_DFI_RDLVL_EDGE(x) (((x) >> S_DFI_RDLVL_EDGE) & M_DFI_RDLVL_EDGE)
69711 
69712 #define S_DFI_RDLVL_RANK_SEL    0
69713 #define M_DFI_RDLVL_RANK_SEL    0xfU
69714 #define V_DFI_RDLVL_RANK_SEL(x) ((x) << S_DFI_RDLVL_RANK_SEL)
69715 #define G_DFI_RDLVL_RANK_SEL(x) (((x) >> S_DFI_RDLVL_RANK_SEL) & M_DFI_RDLVL_RANK_SEL)
69716 
69717 #define A_MC_UPCTL_DFITRSTAT0 0x402b0
69718 
69719 #define S_DFI_WRLVL_MODE    16
69720 #define M_DFI_WRLVL_MODE    0x3U
69721 #define V_DFI_WRLVL_MODE(x) ((x) << S_DFI_WRLVL_MODE)
69722 #define G_DFI_WRLVL_MODE(x) (((x) >> S_DFI_WRLVL_MODE) & M_DFI_WRLVL_MODE)
69723 
69724 #define S_DFI_RDLVL_GATE_MODE    8
69725 #define M_DFI_RDLVL_GATE_MODE    0x3U
69726 #define V_DFI_RDLVL_GATE_MODE(x) ((x) << S_DFI_RDLVL_GATE_MODE)
69727 #define G_DFI_RDLVL_GATE_MODE(x) (((x) >> S_DFI_RDLVL_GATE_MODE) & M_DFI_RDLVL_GATE_MODE)
69728 
69729 #define S_DFI_RDLVL_MODE    0
69730 #define M_DFI_RDLVL_MODE    0x3U
69731 #define V_DFI_RDLVL_MODE(x) ((x) << S_DFI_RDLVL_MODE)
69732 #define G_DFI_RDLVL_MODE(x) (((x) >> S_DFI_RDLVL_MODE) & M_DFI_RDLVL_MODE)
69733 
69734 #define A_MC_UPCTL_DFITRWRLVLEN 0x402b4
69735 
69736 #define S_DFI_WRLVL_EN    0
69737 #define M_DFI_WRLVL_EN    0x1ffU
69738 #define V_DFI_WRLVL_EN(x) ((x) << S_DFI_WRLVL_EN)
69739 #define G_DFI_WRLVL_EN(x) (((x) >> S_DFI_WRLVL_EN) & M_DFI_WRLVL_EN)
69740 
69741 #define A_MC_UPCTL_DFITRRDLVLEN 0x402b8
69742 
69743 #define S_DFI_RDLVL_EN    0
69744 #define M_DFI_RDLVL_EN    0x1ffU
69745 #define V_DFI_RDLVL_EN(x) ((x) << S_DFI_RDLVL_EN)
69746 #define G_DFI_RDLVL_EN(x) (((x) >> S_DFI_RDLVL_EN) & M_DFI_RDLVL_EN)
69747 
69748 #define A_MC_UPCTL_DFITRRDLVLGATEEN 0x402bc
69749 
69750 #define S_DFI_RDLVL_GATE_EN    0
69751 #define M_DFI_RDLVL_GATE_EN    0x1ffU
69752 #define V_DFI_RDLVL_GATE_EN(x) ((x) << S_DFI_RDLVL_GATE_EN)
69753 #define G_DFI_RDLVL_GATE_EN(x) (((x) >> S_DFI_RDLVL_GATE_EN) & M_DFI_RDLVL_GATE_EN)
69754 
69755 #define A_MC_UPCTL_DFISTSTAT0 0x402c0
69756 
69757 #define S_DFI_DATA_BYTE_DISABLE    16
69758 #define M_DFI_DATA_BYTE_DISABLE    0x1ffU
69759 #define V_DFI_DATA_BYTE_DISABLE(x) ((x) << S_DFI_DATA_BYTE_DISABLE)
69760 #define G_DFI_DATA_BYTE_DISABLE(x) (((x) >> S_DFI_DATA_BYTE_DISABLE) & M_DFI_DATA_BYTE_DISABLE)
69761 
69762 #define S_DFI_FREQ_RATIO    4
69763 #define M_DFI_FREQ_RATIO    0x3U
69764 #define V_DFI_FREQ_RATIO(x) ((x) << S_DFI_FREQ_RATIO)
69765 #define G_DFI_FREQ_RATIO(x) (((x) >> S_DFI_FREQ_RATIO) & M_DFI_FREQ_RATIO)
69766 
69767 #define S_DFI_INIT_START0    1
69768 #define V_DFI_INIT_START0(x) ((x) << S_DFI_INIT_START0)
69769 #define F_DFI_INIT_START0    V_DFI_INIT_START0(1U)
69770 
69771 #define S_DFI_INIT_COMPLETE    0
69772 #define V_DFI_INIT_COMPLETE(x) ((x) << S_DFI_INIT_COMPLETE)
69773 #define F_DFI_INIT_COMPLETE    V_DFI_INIT_COMPLETE(1U)
69774 
69775 #define A_MC_UPCTL_DFISTCFG0 0x402c4
69776 
69777 #define S_DFI_DATA_BYTE_DISABLE_EN    2
69778 #define V_DFI_DATA_BYTE_DISABLE_EN(x) ((x) << S_DFI_DATA_BYTE_DISABLE_EN)
69779 #define F_DFI_DATA_BYTE_DISABLE_EN    V_DFI_DATA_BYTE_DISABLE_EN(1U)
69780 
69781 #define S_DFI_FREQ_RATIO_EN    1
69782 #define V_DFI_FREQ_RATIO_EN(x) ((x) << S_DFI_FREQ_RATIO_EN)
69783 #define F_DFI_FREQ_RATIO_EN    V_DFI_FREQ_RATIO_EN(1U)
69784 
69785 #define S_DFI_INIT_START    0
69786 #define V_DFI_INIT_START(x) ((x) << S_DFI_INIT_START)
69787 #define F_DFI_INIT_START    V_DFI_INIT_START(1U)
69788 
69789 #define A_MC_UPCTL_DFISTCFG1 0x402c8
69790 
69791 #define S_DFI_DRAM_CLK_DISABLE_EN_DPD    1
69792 #define V_DFI_DRAM_CLK_DISABLE_EN_DPD(x) ((x) << S_DFI_DRAM_CLK_DISABLE_EN_DPD)
69793 #define F_DFI_DRAM_CLK_DISABLE_EN_DPD    V_DFI_DRAM_CLK_DISABLE_EN_DPD(1U)
69794 
69795 #define S_DFI_DRAM_CLK_DISABLE_EN    0
69796 #define V_DFI_DRAM_CLK_DISABLE_EN(x) ((x) << S_DFI_DRAM_CLK_DISABLE_EN)
69797 #define F_DFI_DRAM_CLK_DISABLE_EN    V_DFI_DRAM_CLK_DISABLE_EN(1U)
69798 
69799 #define A_MC_UPCTL_DFITDRAMCLKEN 0x402d0
69800 
69801 #define S_TDRAM_CLK_ENABLE    0
69802 #define M_TDRAM_CLK_ENABLE    0xfU
69803 #define V_TDRAM_CLK_ENABLE(x) ((x) << S_TDRAM_CLK_ENABLE)
69804 #define G_TDRAM_CLK_ENABLE(x) (((x) >> S_TDRAM_CLK_ENABLE) & M_TDRAM_CLK_ENABLE)
69805 
69806 #define A_MC_UPCTL_DFITDRAMCLKDIS 0x402d4
69807 
69808 #define S_TDRAM_CLK_DISABLE    0
69809 #define M_TDRAM_CLK_DISABLE    0xfU
69810 #define V_TDRAM_CLK_DISABLE(x) ((x) << S_TDRAM_CLK_DISABLE)
69811 #define G_TDRAM_CLK_DISABLE(x) (((x) >> S_TDRAM_CLK_DISABLE) & M_TDRAM_CLK_DISABLE)
69812 
69813 #define A_MC_UPCTL_DFISTCFG2 0x402d8
69814 
69815 #define S_PARITY_EN    1
69816 #define V_PARITY_EN(x) ((x) << S_PARITY_EN)
69817 #define F_PARITY_EN    V_PARITY_EN(1U)
69818 
69819 #define S_PARITY_INTR_EN    0
69820 #define V_PARITY_INTR_EN(x) ((x) << S_PARITY_INTR_EN)
69821 #define F_PARITY_INTR_EN    V_PARITY_INTR_EN(1U)
69822 
69823 #define A_MC_UPCTL_DFISTPARCLR 0x402dc
69824 
69825 #define S_PARITY_LOG_CLR    1
69826 #define V_PARITY_LOG_CLR(x) ((x) << S_PARITY_LOG_CLR)
69827 #define F_PARITY_LOG_CLR    V_PARITY_LOG_CLR(1U)
69828 
69829 #define S_PARITY_INTR_CLR    0
69830 #define V_PARITY_INTR_CLR(x) ((x) << S_PARITY_INTR_CLR)
69831 #define F_PARITY_INTR_CLR    V_PARITY_INTR_CLR(1U)
69832 
69833 #define A_MC_UPCTL_DFISTPARLOG 0x402e0
69834 #define A_MC_UPCTL_DFILPCFG0 0x402f0
69835 
69836 #define S_DFI_LP_WAKEUP_DPD    28
69837 #define M_DFI_LP_WAKEUP_DPD    0xfU
69838 #define V_DFI_LP_WAKEUP_DPD(x) ((x) << S_DFI_LP_WAKEUP_DPD)
69839 #define G_DFI_LP_WAKEUP_DPD(x) (((x) >> S_DFI_LP_WAKEUP_DPD) & M_DFI_LP_WAKEUP_DPD)
69840 
69841 #define S_DFI_LP_EN_DPD    24
69842 #define V_DFI_LP_EN_DPD(x) ((x) << S_DFI_LP_EN_DPD)
69843 #define F_DFI_LP_EN_DPD    V_DFI_LP_EN_DPD(1U)
69844 
69845 #define S_DFI_TLP_RESP    16
69846 #define M_DFI_TLP_RESP    0xfU
69847 #define V_DFI_TLP_RESP(x) ((x) << S_DFI_TLP_RESP)
69848 #define G_DFI_TLP_RESP(x) (((x) >> S_DFI_TLP_RESP) & M_DFI_TLP_RESP)
69849 
69850 #define S_DFI_LP_EN_SR    8
69851 #define V_DFI_LP_EN_SR(x) ((x) << S_DFI_LP_EN_SR)
69852 #define F_DFI_LP_EN_SR    V_DFI_LP_EN_SR(1U)
69853 
69854 #define S_DFI_LP_WAKEUP_PD    4
69855 #define M_DFI_LP_WAKEUP_PD    0xfU
69856 #define V_DFI_LP_WAKEUP_PD(x) ((x) << S_DFI_LP_WAKEUP_PD)
69857 #define G_DFI_LP_WAKEUP_PD(x) (((x) >> S_DFI_LP_WAKEUP_PD) & M_DFI_LP_WAKEUP_PD)
69858 
69859 #define S_DFI_LP_EN_PD    0
69860 #define V_DFI_LP_EN_PD(x) ((x) << S_DFI_LP_EN_PD)
69861 #define F_DFI_LP_EN_PD    V_DFI_LP_EN_PD(1U)
69862 
69863 #define A_MC_UPCTL_DFITRWRLVLRESP0 0x40300
69864 #define A_MC_UPCTL_DFITRWRLVLRESP1 0x40304
69865 #define A_MC_LMC_CALSTAT 0x40304
69866 
69867 #define S_PHYUPD_ERR    28
69868 #define M_PHYUPD_ERR    0xfU
69869 #define V_PHYUPD_ERR(x) ((x) << S_PHYUPD_ERR)
69870 #define G_PHYUPD_ERR(x) (((x) >> S_PHYUPD_ERR) & M_PHYUPD_ERR)
69871 
69872 #define S_PHYUPD_BUSY    27
69873 #define V_PHYUPD_BUSY(x) ((x) << S_PHYUPD_BUSY)
69874 #define F_PHYUPD_BUSY    V_PHYUPD_BUSY(1U)
69875 
69876 #define A_MC_UPCTL_DFITRWRLVLRESP2 0x40308
69877 
69878 #define S_DFI_WRLVL_RESP2    0
69879 #define M_DFI_WRLVL_RESP2    0xffU
69880 #define V_DFI_WRLVL_RESP2(x) ((x) << S_DFI_WRLVL_RESP2)
69881 #define G_DFI_WRLVL_RESP2(x) (((x) >> S_DFI_WRLVL_RESP2) & M_DFI_WRLVL_RESP2)
69882 
69883 #define A_MC_UPCTL_DFITRRDLVLRESP0 0x4030c
69884 #define A_MC_UPCTL_DFITRRDLVLRESP1 0x40310
69885 #define A_MC_UPCTL_DFITRRDLVLRESP2 0x40314
69886 
69887 #define S_DFI_RDLVL_RESP2    0
69888 #define M_DFI_RDLVL_RESP2    0xffU
69889 #define V_DFI_RDLVL_RESP2(x) ((x) << S_DFI_RDLVL_RESP2)
69890 #define G_DFI_RDLVL_RESP2(x) (((x) >> S_DFI_RDLVL_RESP2) & M_DFI_RDLVL_RESP2)
69891 
69892 #define A_MC_UPCTL_DFITRWRLVLDELAY0 0x40318
69893 #define A_MC_UPCTL_DFITRWRLVLDELAY1 0x4031c
69894 #define A_MC_UPCTL_DFITRWRLVLDELAY2 0x40320
69895 
69896 #define S_DFI_WRLVL_DELAY2    0
69897 #define M_DFI_WRLVL_DELAY2    0xffU
69898 #define V_DFI_WRLVL_DELAY2(x) ((x) << S_DFI_WRLVL_DELAY2)
69899 #define G_DFI_WRLVL_DELAY2(x) (((x) >> S_DFI_WRLVL_DELAY2) & M_DFI_WRLVL_DELAY2)
69900 
69901 #define A_MC_UPCTL_DFITRRDLVLDELAY0 0x40324
69902 #define A_MC_UPCTL_DFITRRDLVLDELAY1 0x40328
69903 #define A_MC_UPCTL_DFITRRDLVLDELAY2 0x4032c
69904 
69905 #define S_DFI_RDLVL_DELAY2    0
69906 #define M_DFI_RDLVL_DELAY2    0xffU
69907 #define V_DFI_RDLVL_DELAY2(x) ((x) << S_DFI_RDLVL_DELAY2)
69908 #define G_DFI_RDLVL_DELAY2(x) (((x) >> S_DFI_RDLVL_DELAY2) & M_DFI_RDLVL_DELAY2)
69909 
69910 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY0 0x40330
69911 #define A_MC_LMC_T_PHYUPD0 0x40330
69912 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY1 0x40334
69913 #define A_MC_LMC_T_PHYUPD1 0x40334
69914 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY2 0x40338
69915 
69916 #define S_DFI_RDLVL_GATE_DELAY2    0
69917 #define M_DFI_RDLVL_GATE_DELAY2    0xffU
69918 #define V_DFI_RDLVL_GATE_DELAY2(x) ((x) << S_DFI_RDLVL_GATE_DELAY2)
69919 #define G_DFI_RDLVL_GATE_DELAY2(x) (((x) >> S_DFI_RDLVL_GATE_DELAY2) & M_DFI_RDLVL_GATE_DELAY2)
69920 
69921 #define A_MC_LMC_T_PHYUPD2 0x40338
69922 #define A_MC_UPCTL_DFITRCMD 0x4033c
69923 
69924 #define S_DFITRCMD_START    31
69925 #define V_DFITRCMD_START(x) ((x) << S_DFITRCMD_START)
69926 #define F_DFITRCMD_START    V_DFITRCMD_START(1U)
69927 
69928 #define S_DFITRCMD_EN    4
69929 #define M_DFITRCMD_EN    0x1ffU
69930 #define V_DFITRCMD_EN(x) ((x) << S_DFITRCMD_EN)
69931 #define G_DFITRCMD_EN(x) (((x) >> S_DFITRCMD_EN) & M_DFITRCMD_EN)
69932 
69933 #define S_DFITRCMD_OPCODE    0
69934 #define M_DFITRCMD_OPCODE    0x3U
69935 #define V_DFITRCMD_OPCODE(x) ((x) << S_DFITRCMD_OPCODE)
69936 #define G_DFITRCMD_OPCODE(x) (((x) >> S_DFITRCMD_OPCODE) & M_DFITRCMD_OPCODE)
69937 
69938 #define A_MC_LMC_T_PHYUPD3 0x4033c
69939 #define A_MC_UPCTL_IPVR 0x403f8
69940 #define A_MC_UPCTL_IPTR 0x403fc
69941 #define A_MC_P_DDRPHY_RST_CTRL 0x41300
69942 
69943 #define S_PHY_DRAM_WL    17
69944 #define M_PHY_DRAM_WL    0x1fU
69945 #define V_PHY_DRAM_WL(x) ((x) << S_PHY_DRAM_WL)
69946 #define G_PHY_DRAM_WL(x) (((x) >> S_PHY_DRAM_WL) & M_PHY_DRAM_WL)
69947 
69948 #define S_PHY_CALIB_DONE    5
69949 #define V_PHY_CALIB_DONE(x) ((x) << S_PHY_CALIB_DONE)
69950 #define F_PHY_CALIB_DONE    V_PHY_CALIB_DONE(1U)
69951 
69952 #define S_CTL_CAL_REQ    4
69953 #define V_CTL_CAL_REQ(x) ((x) << S_CTL_CAL_REQ)
69954 #define F_CTL_CAL_REQ    V_CTL_CAL_REQ(1U)
69955 
69956 #define S_CTL_CKE    3
69957 #define V_CTL_CKE(x) ((x) << S_CTL_CKE)
69958 #define F_CTL_CKE    V_CTL_CKE(1U)
69959 
69960 #define S_CTL_RST_N    2
69961 #define V_CTL_RST_N(x) ((x) << S_CTL_RST_N)
69962 #define F_CTL_RST_N    V_CTL_RST_N(1U)
69963 
69964 #define S_PHY_CAL_REQ    21
69965 #define V_PHY_CAL_REQ(x) ((x) << S_PHY_CAL_REQ)
69966 #define F_PHY_CAL_REQ    V_PHY_CAL_REQ(1U)
69967 
69968 #define S_T6_PHY_DRAM_WL    17
69969 #define M_T6_PHY_DRAM_WL    0xfU
69970 #define V_T6_PHY_DRAM_WL(x) ((x) << S_T6_PHY_DRAM_WL)
69971 #define G_T6_PHY_DRAM_WL(x) (((x) >> S_T6_PHY_DRAM_WL) & M_T6_PHY_DRAM_WL)
69972 
69973 #define A_MC_P_PERFORMANCE_CTRL 0x41304
69974 
69975 #define S_BUF_USE_TH    12
69976 #define M_BUF_USE_TH    0x7U
69977 #define V_BUF_USE_TH(x) ((x) << S_BUF_USE_TH)
69978 #define G_BUF_USE_TH(x) (((x) >> S_BUF_USE_TH) & M_BUF_USE_TH)
69979 
69980 #define S_MC_IDLE_TH    8
69981 #define M_MC_IDLE_TH    0xfU
69982 #define V_MC_IDLE_TH(x) ((x) << S_MC_IDLE_TH)
69983 #define G_MC_IDLE_TH(x) (((x) >> S_MC_IDLE_TH) & M_MC_IDLE_TH)
69984 
69985 #define S_RMW_DEFER_EN    7
69986 #define V_RMW_DEFER_EN(x) ((x) << S_RMW_DEFER_EN)
69987 #define F_RMW_DEFER_EN    V_RMW_DEFER_EN(1U)
69988 
69989 #define S_DDR3_BRBC_MODE    6
69990 #define V_DDR3_BRBC_MODE(x) ((x) << S_DDR3_BRBC_MODE)
69991 #define F_DDR3_BRBC_MODE    V_DDR3_BRBC_MODE(1U)
69992 
69993 #define S_RMW_DWRITE_EN    5
69994 #define V_RMW_DWRITE_EN(x) ((x) << S_RMW_DWRITE_EN)
69995 #define F_RMW_DWRITE_EN    V_RMW_DWRITE_EN(1U)
69996 
69997 #define S_RMW_MERGE_EN    4
69998 #define V_RMW_MERGE_EN(x) ((x) << S_RMW_MERGE_EN)
69999 #define F_RMW_MERGE_EN    V_RMW_MERGE_EN(1U)
70000 
70001 #define S_SYNC_PAB_EN    3
70002 #define V_SYNC_PAB_EN(x) ((x) << S_SYNC_PAB_EN)
70003 #define F_SYNC_PAB_EN    V_SYNC_PAB_EN(1U)
70004 
70005 #define A_MC_P_ECC_CTRL 0x41308
70006 #define A_MC_P_PAR_ENABLE 0x4130c
70007 #define A_MC_P_PAR_CAUSE 0x41310
70008 #define A_MC_P_INT_ENABLE 0x41314
70009 #define A_MC_P_INT_CAUSE 0x41318
70010 #define A_MC_P_ECC_STATUS 0x4131c
70011 #define A_MC_P_PHY_CTRL 0x41320
70012 #define A_MC_P_STATIC_CFG_STATUS 0x41324
70013 
70014 #define S_STATIC_AWEN    23
70015 #define V_STATIC_AWEN(x) ((x) << S_STATIC_AWEN)
70016 #define F_STATIC_AWEN    V_STATIC_AWEN(1U)
70017 
70018 #define S_STATIC_SWLAT    18
70019 #define M_STATIC_SWLAT    0x1fU
70020 #define V_STATIC_SWLAT(x) ((x) << S_STATIC_SWLAT)
70021 #define G_STATIC_SWLAT(x) (((x) >> S_STATIC_SWLAT) & M_STATIC_SWLAT)
70022 
70023 #define S_STATIC_WLAT    17
70024 #define V_STATIC_WLAT(x) ((x) << S_STATIC_WLAT)
70025 #define F_STATIC_WLAT    V_STATIC_WLAT(1U)
70026 
70027 #define S_STATIC_ALIGN    16
70028 #define V_STATIC_ALIGN(x) ((x) << S_STATIC_ALIGN)
70029 #define F_STATIC_ALIGN    V_STATIC_ALIGN(1U)
70030 
70031 #define S_STATIC_SLAT    11
70032 #define M_STATIC_SLAT    0x1fU
70033 #define V_STATIC_SLAT(x) ((x) << S_STATIC_SLAT)
70034 #define G_STATIC_SLAT(x) (((x) >> S_STATIC_SLAT) & M_STATIC_SLAT)
70035 
70036 #define S_STATIC_LAT    10
70037 #define V_STATIC_LAT(x) ((x) << S_STATIC_LAT)
70038 #define F_STATIC_LAT    V_STATIC_LAT(1U)
70039 
70040 #define S_STATIC_PP64    26
70041 #define V_STATIC_PP64(x) ((x) << S_STATIC_PP64)
70042 #define F_STATIC_PP64    V_STATIC_PP64(1U)
70043 
70044 #define S_STATIC_PPEN    25
70045 #define V_STATIC_PPEN(x) ((x) << S_STATIC_PPEN)
70046 #define F_STATIC_PPEN    V_STATIC_PPEN(1U)
70047 
70048 #define S_STATIC_OOOEN    24
70049 #define V_STATIC_OOOEN(x) ((x) << S_STATIC_OOOEN)
70050 #define F_STATIC_OOOEN    V_STATIC_OOOEN(1U)
70051 
70052 #define A_MC_P_CORE_PCTL_STAT 0x41328
70053 #define A_MC_P_DEBUG_CNT 0x4132c
70054 #define A_MC_CE_ERR_DATA_RDATA 0x41330
70055 #define A_MC_CE_COR_DATA_RDATA 0x41350
70056 #define A_MC_UE_ERR_DATA_RDATA 0x41370
70057 #define A_MC_UE_COR_DATA_RDATA 0x41390
70058 #define A_MC_CE_ADDR 0x413b0
70059 #define A_MC_UE_ADDR 0x413b4
70060 #define A_MC_P_DEEP_SLEEP 0x413b8
70061 
70062 #define S_SLEEPSTATUS    1
70063 #define V_SLEEPSTATUS(x) ((x) << S_SLEEPSTATUS)
70064 #define F_SLEEPSTATUS    V_SLEEPSTATUS(1U)
70065 
70066 #define S_SLEEPREQ    0
70067 #define V_SLEEPREQ(x) ((x) << S_SLEEPREQ)
70068 #define F_SLEEPREQ    V_SLEEPREQ(1U)
70069 
70070 #define A_MC_P_FPGA_BONUS 0x413bc
70071 #define A_MC_P_DEBUG_CFG 0x413c0
70072 #define A_MC_P_DEBUG_RPT 0x413c4
70073 #define A_MC_P_PHY_ADR_CK_EN 0x413c8
70074 
70075 #define S_ADR_CK_EN    0
70076 #define V_ADR_CK_EN(x) ((x) << S_ADR_CK_EN)
70077 #define F_ADR_CK_EN    V_ADR_CK_EN(1U)
70078 
70079 #define A_MC_CE_ERR_ECC_DATA0 0x413d0
70080 #define A_MC_CE_ERR_ECC_DATA1 0x413d4
70081 #define A_MC_UE_ERR_ECC_DATA0 0x413d8
70082 #define A_MC_UE_ERR_ECC_DATA1 0x413dc
70083 #define A_MC_P_RMW_PRIO 0x413f0
70084 
70085 #define S_WR_HI_TH    24
70086 #define M_WR_HI_TH    0xffU
70087 #define V_WR_HI_TH(x) ((x) << S_WR_HI_TH)
70088 #define G_WR_HI_TH(x) (((x) >> S_WR_HI_TH) & M_WR_HI_TH)
70089 
70090 #define S_WR_MID_TH    16
70091 #define M_WR_MID_TH    0xffU
70092 #define V_WR_MID_TH(x) ((x) << S_WR_MID_TH)
70093 #define G_WR_MID_TH(x) (((x) >> S_WR_MID_TH) & M_WR_MID_TH)
70094 
70095 #define S_RD_HI_TH    8
70096 #define M_RD_HI_TH    0xffU
70097 #define V_RD_HI_TH(x) ((x) << S_RD_HI_TH)
70098 #define G_RD_HI_TH(x) (((x) >> S_RD_HI_TH) & M_RD_HI_TH)
70099 
70100 #define S_RD_MID_TH    0
70101 #define M_RD_MID_TH    0xffU
70102 #define V_RD_MID_TH(x) ((x) << S_RD_MID_TH)
70103 #define G_RD_MID_TH(x) (((x) >> S_RD_MID_TH) & M_RD_MID_TH)
70104 
70105 #define A_MC_P_BIST_CMD 0x41400
70106 
70107 #define S_BURST_LEN    16
70108 #define M_BURST_LEN    0x3U
70109 #define V_BURST_LEN(x) ((x) << S_BURST_LEN)
70110 #define G_BURST_LEN(x) (((x) >> S_BURST_LEN) & M_BURST_LEN)
70111 
70112 #define A_MC_P_BIST_CMD_ADDR 0x41404
70113 #define A_MC_P_BIST_CMD_LEN 0x41408
70114 #define A_MC_P_BIST_DATA_PATTERN 0x4140c
70115 #define A_MC_P_BIST_USER_WDATA0 0x41414
70116 #define A_MC_P_BIST_USER_WMASK0 0x41414
70117 #define A_MC_P_BIST_USER_WDATA1 0x41418
70118 #define A_MC_P_BIST_USER_WMASK1 0x41418
70119 #define A_MC_P_BIST_USER_WDATA2 0x4141c
70120 
70121 #define S_USER_DATA_MASK    8
70122 #define M_USER_DATA_MASK    0x1ffU
70123 #define V_USER_DATA_MASK(x) ((x) << S_USER_DATA_MASK)
70124 #define G_USER_DATA_MASK(x) (((x) >> S_USER_DATA_MASK) & M_USER_DATA_MASK)
70125 
70126 #define A_MC_P_BIST_USER_WMASK2 0x4141c
70127 
70128 #define S_MASK_128_1    9
70129 #define V_MASK_128_1(x) ((x) << S_MASK_128_1)
70130 #define F_MASK_128_1    V_MASK_128_1(1U)
70131 
70132 #define S_MASK_128_0    8
70133 #define V_MASK_128_0(x) ((x) << S_MASK_128_0)
70134 #define F_MASK_128_0    V_MASK_128_0(1U)
70135 
70136 #define S_USER_MASK_ECC    0
70137 #define M_USER_MASK_ECC    0xffU
70138 #define V_USER_MASK_ECC(x) ((x) << S_USER_MASK_ECC)
70139 #define G_USER_MASK_ECC(x) (((x) >> S_USER_MASK_ECC) & M_USER_MASK_ECC)
70140 
70141 #define A_MC_P_BIST_NUM_ERR 0x41480
70142 #define A_MC_P_BIST_ERR_FIRST_ADDR 0x41484
70143 #define A_MC_P_BIST_STATUS_RDATA 0x41488
70144 #define A_MC_P_BIST_CRC_SEED 0x414d0
70145 #define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE0 0x44000
70146 
70147 #define S_DATA_BIT_ENABLE_0_15    0
70148 #define M_DATA_BIT_ENABLE_0_15    0xffffU
70149 #define V_DATA_BIT_ENABLE_0_15(x) ((x) << S_DATA_BIT_ENABLE_0_15)
70150 #define G_DATA_BIT_ENABLE_0_15(x) (((x) >> S_DATA_BIT_ENABLE_0_15) & M_DATA_BIT_ENABLE_0_15)
70151 
70152 #define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE1 0x44004
70153 
70154 #define S_DATA_BIT_ENABLE_16_23    8
70155 #define M_DATA_BIT_ENABLE_16_23    0xffU
70156 #define V_DATA_BIT_ENABLE_16_23(x) ((x) << S_DATA_BIT_ENABLE_16_23)
70157 #define G_DATA_BIT_ENABLE_16_23(x) (((x) >> S_DATA_BIT_ENABLE_16_23) & M_DATA_BIT_ENABLE_16_23)
70158 
70159 #define S_DFT_FORCE_OUTPUTS    7
70160 #define V_DFT_FORCE_OUTPUTS(x) ((x) << S_DFT_FORCE_OUTPUTS)
70161 #define F_DFT_FORCE_OUTPUTS    V_DFT_FORCE_OUTPUTS(1U)
70162 
70163 #define S_DFT_PRBS7_GEN_EN    6
70164 #define V_DFT_PRBS7_GEN_EN(x) ((x) << S_DFT_PRBS7_GEN_EN)
70165 #define F_DFT_PRBS7_GEN_EN    V_DFT_PRBS7_GEN_EN(1U)
70166 
70167 #define S_WRAPSEL    5
70168 #define V_WRAPSEL(x) ((x) << S_WRAPSEL)
70169 #define F_WRAPSEL    V_WRAPSEL(1U)
70170 
70171 #define S_MRS_CMD_DATA_N0    3
70172 #define V_MRS_CMD_DATA_N0(x) ((x) << S_MRS_CMD_DATA_N0)
70173 #define F_MRS_CMD_DATA_N0    V_MRS_CMD_DATA_N0(1U)
70174 
70175 #define S_MRS_CMD_DATA_N1    2
70176 #define V_MRS_CMD_DATA_N1(x) ((x) << S_MRS_CMD_DATA_N1)
70177 #define F_MRS_CMD_DATA_N1    V_MRS_CMD_DATA_N1(1U)
70178 
70179 #define S_MRS_CMD_DATA_N2    1
70180 #define V_MRS_CMD_DATA_N2(x) ((x) << S_MRS_CMD_DATA_N2)
70181 #define F_MRS_CMD_DATA_N2    V_MRS_CMD_DATA_N2(1U)
70182 
70183 #define S_MRS_CMD_DATA_N3    0
70184 #define V_MRS_CMD_DATA_N3(x) ((x) << S_MRS_CMD_DATA_N3)
70185 #define F_MRS_CMD_DATA_N3    V_MRS_CMD_DATA_N3(1U)
70186 
70187 #define S_DP18_WRAPSEL    5
70188 #define V_DP18_WRAPSEL(x) ((x) << S_DP18_WRAPSEL)
70189 #define F_DP18_WRAPSEL    V_DP18_WRAPSEL(1U)
70190 
70191 #define S_HW_VALUE    4
70192 #define V_HW_VALUE(x) ((x) << S_HW_VALUE)
70193 #define F_HW_VALUE    V_HW_VALUE(1U)
70194 
70195 #define A_MC_DDRPHY_DP18_DATA_BIT_DIR0 0x44008
70196 
70197 #define S_DATA_BIT_DIR_0_15    0
70198 #define M_DATA_BIT_DIR_0_15    0xffffU
70199 #define V_DATA_BIT_DIR_0_15(x) ((x) << S_DATA_BIT_DIR_0_15)
70200 #define G_DATA_BIT_DIR_0_15(x) (((x) >> S_DATA_BIT_DIR_0_15) & M_DATA_BIT_DIR_0_15)
70201 
70202 #define A_MC_DDRPHY_DP18_DATA_BIT_DIR1 0x4400c
70203 
70204 #define S_DATA_BIT_DIR_16_23    8
70205 #define M_DATA_BIT_DIR_16_23    0xffU
70206 #define V_DATA_BIT_DIR_16_23(x) ((x) << S_DATA_BIT_DIR_16_23)
70207 #define G_DATA_BIT_DIR_16_23(x) (((x) >> S_DATA_BIT_DIR_16_23) & M_DATA_BIT_DIR_16_23)
70208 
70209 #define S_WL_ADVANCE_DISABLE    7
70210 #define V_WL_ADVANCE_DISABLE(x) ((x) << S_WL_ADVANCE_DISABLE)
70211 #define F_WL_ADVANCE_DISABLE    V_WL_ADVANCE_DISABLE(1U)
70212 
70213 #define S_DISABLE_PING_PONG    6
70214 #define V_DISABLE_PING_PONG(x) ((x) << S_DISABLE_PING_PONG)
70215 #define F_DISABLE_PING_PONG    V_DISABLE_PING_PONG(1U)
70216 
70217 #define S_DELAY_PING_PONG_HALF    5
70218 #define V_DELAY_PING_PONG_HALF(x) ((x) << S_DELAY_PING_PONG_HALF)
70219 #define F_DELAY_PING_PONG_HALF    V_DELAY_PING_PONG_HALF(1U)
70220 
70221 #define S_ADVANCE_PING_PONG    4
70222 #define V_ADVANCE_PING_PONG(x) ((x) << S_ADVANCE_PING_PONG)
70223 #define F_ADVANCE_PING_PONG    V_ADVANCE_PING_PONG(1U)
70224 
70225 #define S_ATEST_MUX_CTL0    3
70226 #define V_ATEST_MUX_CTL0(x) ((x) << S_ATEST_MUX_CTL0)
70227 #define F_ATEST_MUX_CTL0    V_ATEST_MUX_CTL0(1U)
70228 
70229 #define S_ATEST_MUX_CTL1    2
70230 #define V_ATEST_MUX_CTL1(x) ((x) << S_ATEST_MUX_CTL1)
70231 #define F_ATEST_MUX_CTL1    V_ATEST_MUX_CTL1(1U)
70232 
70233 #define S_ATEST_MUX_CTL2    1
70234 #define V_ATEST_MUX_CTL2(x) ((x) << S_ATEST_MUX_CTL2)
70235 #define F_ATEST_MUX_CTL2    V_ATEST_MUX_CTL2(1U)
70236 
70237 #define S_ATEST_MUX_CTL3    0
70238 #define V_ATEST_MUX_CTL3(x) ((x) << S_ATEST_MUX_CTL3)
70239 #define F_ATEST_MUX_CTL3    V_ATEST_MUX_CTL3(1U)
70240 
70241 #define A_MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR 0x44010
70242 
70243 #define S_QUAD0_CLK16_BIT0    15
70244 #define V_QUAD0_CLK16_BIT0(x) ((x) << S_QUAD0_CLK16_BIT0)
70245 #define F_QUAD0_CLK16_BIT0    V_QUAD0_CLK16_BIT0(1U)
70246 
70247 #define S_QUAD1_CLK16_BIT1    14
70248 #define V_QUAD1_CLK16_BIT1(x) ((x) << S_QUAD1_CLK16_BIT1)
70249 #define F_QUAD1_CLK16_BIT1    V_QUAD1_CLK16_BIT1(1U)
70250 
70251 #define S_QUAD2_CLK16_BIT2    13
70252 #define V_QUAD2_CLK16_BIT2(x) ((x) << S_QUAD2_CLK16_BIT2)
70253 #define F_QUAD2_CLK16_BIT2    V_QUAD2_CLK16_BIT2(1U)
70254 
70255 #define S_QUAD3_CLK16_BIT3    12
70256 #define V_QUAD3_CLK16_BIT3(x) ((x) << S_QUAD3_CLK16_BIT3)
70257 #define F_QUAD3_CLK16_BIT3    V_QUAD3_CLK16_BIT3(1U)
70258 
70259 #define S_QUAD0_CLK18_BIT4    11
70260 #define V_QUAD0_CLK18_BIT4(x) ((x) << S_QUAD0_CLK18_BIT4)
70261 #define F_QUAD0_CLK18_BIT4    V_QUAD0_CLK18_BIT4(1U)
70262 
70263 #define S_QUAD1_CLK18_BIT5    10
70264 #define V_QUAD1_CLK18_BIT5(x) ((x) << S_QUAD1_CLK18_BIT5)
70265 #define F_QUAD1_CLK18_BIT5    V_QUAD1_CLK18_BIT5(1U)
70266 
70267 #define S_QUAD2_CLK20_BIT6    9
70268 #define V_QUAD2_CLK20_BIT6(x) ((x) << S_QUAD2_CLK20_BIT6)
70269 #define F_QUAD2_CLK20_BIT6    V_QUAD2_CLK20_BIT6(1U)
70270 
70271 #define S_QUAD3_CLK20_BIT7    8
70272 #define V_QUAD3_CLK20_BIT7(x) ((x) << S_QUAD3_CLK20_BIT7)
70273 #define F_QUAD3_CLK20_BIT7    V_QUAD3_CLK20_BIT7(1U)
70274 
70275 #define S_QUAD2_CLK22_BIT8    7
70276 #define V_QUAD2_CLK22_BIT8(x) ((x) << S_QUAD2_CLK22_BIT8)
70277 #define F_QUAD2_CLK22_BIT8    V_QUAD2_CLK22_BIT8(1U)
70278 
70279 #define S_QUAD3_CLK22_BIT9    6
70280 #define V_QUAD3_CLK22_BIT9(x) ((x) << S_QUAD3_CLK22_BIT9)
70281 #define F_QUAD3_CLK22_BIT9    V_QUAD3_CLK22_BIT9(1U)
70282 
70283 #define S_CLK16_SINGLE_ENDED_BIT10    5
70284 #define V_CLK16_SINGLE_ENDED_BIT10(x) ((x) << S_CLK16_SINGLE_ENDED_BIT10)
70285 #define F_CLK16_SINGLE_ENDED_BIT10    V_CLK16_SINGLE_ENDED_BIT10(1U)
70286 
70287 #define S_CLK18_SINGLE_ENDED_BIT11    4
70288 #define V_CLK18_SINGLE_ENDED_BIT11(x) ((x) << S_CLK18_SINGLE_ENDED_BIT11)
70289 #define F_CLK18_SINGLE_ENDED_BIT11    V_CLK18_SINGLE_ENDED_BIT11(1U)
70290 
70291 #define S_CLK20_SINGLE_ENDED_BIT12    3
70292 #define V_CLK20_SINGLE_ENDED_BIT12(x) ((x) << S_CLK20_SINGLE_ENDED_BIT12)
70293 #define F_CLK20_SINGLE_ENDED_BIT12    V_CLK20_SINGLE_ENDED_BIT12(1U)
70294 
70295 #define S_CLK22_SINGLE_ENDED_BIT13    2
70296 #define V_CLK22_SINGLE_ENDED_BIT13(x) ((x) << S_CLK22_SINGLE_ENDED_BIT13)
70297 #define F_CLK22_SINGLE_ENDED_BIT13    V_CLK22_SINGLE_ENDED_BIT13(1U)
70298 
70299 #define A_MC_DDRPHY_DP18_WRCLK_EN_RP 0x44014
70300 
70301 #define S_QUAD2_CLK18_BIT14    1
70302 #define V_QUAD2_CLK18_BIT14(x) ((x) << S_QUAD2_CLK18_BIT14)
70303 #define F_QUAD2_CLK18_BIT14    V_QUAD2_CLK18_BIT14(1U)
70304 
70305 #define S_QUAD3_CLK18_BIT15    0
70306 #define V_QUAD3_CLK18_BIT15(x) ((x) << S_QUAD3_CLK18_BIT15)
70307 #define F_QUAD3_CLK18_BIT15    V_QUAD3_CLK18_BIT15(1U)
70308 
70309 #define A_MC_DDRPHY_DP18_RX_PEAK_AMP 0x44018
70310 
70311 #define S_PEAK_AMP_CTL_SIDE0    13
70312 #define M_PEAK_AMP_CTL_SIDE0    0x7U
70313 #define V_PEAK_AMP_CTL_SIDE0(x) ((x) << S_PEAK_AMP_CTL_SIDE0)
70314 #define G_PEAK_AMP_CTL_SIDE0(x) (((x) >> S_PEAK_AMP_CTL_SIDE0) & M_PEAK_AMP_CTL_SIDE0)
70315 
70316 #define S_PEAK_AMP_CTL_SIDE1    9
70317 #define M_PEAK_AMP_CTL_SIDE1    0x7U
70318 #define V_PEAK_AMP_CTL_SIDE1(x) ((x) << S_PEAK_AMP_CTL_SIDE1)
70319 #define G_PEAK_AMP_CTL_SIDE1(x) (((x) >> S_PEAK_AMP_CTL_SIDE1) & M_PEAK_AMP_CTL_SIDE1)
70320 
70321 #define S_SXMCVREF_0_3    4
70322 #define M_SXMCVREF_0_3    0xfU
70323 #define V_SXMCVREF_0_3(x) ((x) << S_SXMCVREF_0_3)
70324 #define G_SXMCVREF_0_3(x) (((x) >> S_SXMCVREF_0_3) & M_SXMCVREF_0_3)
70325 
70326 #define S_SXPODVREF    3
70327 #define V_SXPODVREF(x) ((x) << S_SXPODVREF)
70328 #define F_SXPODVREF    V_SXPODVREF(1U)
70329 
70330 #define S_DISABLE_TERMINATION    2
70331 #define V_DISABLE_TERMINATION(x) ((x) << S_DISABLE_TERMINATION)
70332 #define F_DISABLE_TERMINATION    V_DISABLE_TERMINATION(1U)
70333 
70334 #define S_READ_CENTERING_MODE    0
70335 #define M_READ_CENTERING_MODE    0x3U
70336 #define V_READ_CENTERING_MODE(x) ((x) << S_READ_CENTERING_MODE)
70337 #define G_READ_CENTERING_MODE(x) (((x) >> S_READ_CENTERING_MODE) & M_READ_CENTERING_MODE)
70338 
70339 #define A_MC_DDRPHY_DP18_SYSCLK_PR 0x4401c
70340 
70341 #define S_SYSCLK_PHASE_ALIGN_RESET    6
70342 #define V_SYSCLK_PHASE_ALIGN_RESET(x) ((x) << S_SYSCLK_PHASE_ALIGN_RESET)
70343 #define F_SYSCLK_PHASE_ALIGN_RESET    V_SYSCLK_PHASE_ALIGN_RESET(1U)
70344 
70345 #define A_MC_DDRPHY_DP18_DFT_DIG_EYE 0x44020
70346 
70347 #define S_DIGITAL_EYE_EN    15
70348 #define V_DIGITAL_EYE_EN(x) ((x) << S_DIGITAL_EYE_EN)
70349 #define F_DIGITAL_EYE_EN    V_DIGITAL_EYE_EN(1U)
70350 
70351 #define S_BUMP    14
70352 #define V_BUMP(x) ((x) << S_BUMP)
70353 #define F_BUMP    V_BUMP(1U)
70354 
70355 #define S_TRIG_PERIOD    13
70356 #define V_TRIG_PERIOD(x) ((x) << S_TRIG_PERIOD)
70357 #define F_TRIG_PERIOD    V_TRIG_PERIOD(1U)
70358 
70359 #define S_CNTL_POL    12
70360 #define V_CNTL_POL(x) ((x) << S_CNTL_POL)
70361 #define F_CNTL_POL    V_CNTL_POL(1U)
70362 
70363 #define S_CNTL_SRC    8
70364 #define V_CNTL_SRC(x) ((x) << S_CNTL_SRC)
70365 #define F_CNTL_SRC    V_CNTL_SRC(1U)
70366 
70367 #define S_DIGITAL_EYE_VALUE    0
70368 #define M_DIGITAL_EYE_VALUE    0xffU
70369 #define V_DIGITAL_EYE_VALUE(x) ((x) << S_DIGITAL_EYE_VALUE)
70370 #define G_DIGITAL_EYE_VALUE(x) (((x) >> S_DIGITAL_EYE_VALUE) & M_DIGITAL_EYE_VALUE)
70371 
70372 #define A_MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR 0x44024
70373 
70374 #define S_DQSCLK_SELECT0    14
70375 #define M_DQSCLK_SELECT0    0x3U
70376 #define V_DQSCLK_SELECT0(x) ((x) << S_DQSCLK_SELECT0)
70377 #define G_DQSCLK_SELECT0(x) (((x) >> S_DQSCLK_SELECT0) & M_DQSCLK_SELECT0)
70378 
70379 #define S_RDCLK_SELECT0    12
70380 #define M_RDCLK_SELECT0    0x3U
70381 #define V_RDCLK_SELECT0(x) ((x) << S_RDCLK_SELECT0)
70382 #define G_RDCLK_SELECT0(x) (((x) >> S_RDCLK_SELECT0) & M_RDCLK_SELECT0)
70383 
70384 #define S_DQSCLK_SELECT1    10
70385 #define M_DQSCLK_SELECT1    0x3U
70386 #define V_DQSCLK_SELECT1(x) ((x) << S_DQSCLK_SELECT1)
70387 #define G_DQSCLK_SELECT1(x) (((x) >> S_DQSCLK_SELECT1) & M_DQSCLK_SELECT1)
70388 
70389 #define S_RDCLK_SELECT1    8
70390 #define M_RDCLK_SELECT1    0x3U
70391 #define V_RDCLK_SELECT1(x) ((x) << S_RDCLK_SELECT1)
70392 #define G_RDCLK_SELECT1(x) (((x) >> S_RDCLK_SELECT1) & M_RDCLK_SELECT1)
70393 
70394 #define S_DQSCLK_SELECT2    6
70395 #define M_DQSCLK_SELECT2    0x3U
70396 #define V_DQSCLK_SELECT2(x) ((x) << S_DQSCLK_SELECT2)
70397 #define G_DQSCLK_SELECT2(x) (((x) >> S_DQSCLK_SELECT2) & M_DQSCLK_SELECT2)
70398 
70399 #define S_RDCLK_SELECT2    4
70400 #define M_RDCLK_SELECT2    0x3U
70401 #define V_RDCLK_SELECT2(x) ((x) << S_RDCLK_SELECT2)
70402 #define G_RDCLK_SELECT2(x) (((x) >> S_RDCLK_SELECT2) & M_RDCLK_SELECT2)
70403 
70404 #define S_DQSCLK_SELECT3    2
70405 #define M_DQSCLK_SELECT3    0x3U
70406 #define V_DQSCLK_SELECT3(x) ((x) << S_DQSCLK_SELECT3)
70407 #define G_DQSCLK_SELECT3(x) (((x) >> S_DQSCLK_SELECT3) & M_DQSCLK_SELECT3)
70408 
70409 #define S_RDCLK_SELECT3    0
70410 #define M_RDCLK_SELECT3    0x3U
70411 #define V_RDCLK_SELECT3(x) ((x) << S_RDCLK_SELECT3)
70412 #define G_RDCLK_SELECT3(x) (((x) >> S_RDCLK_SELECT3) & M_RDCLK_SELECT3)
70413 
70414 #define A_MC_DDRPHY_DP18_DRIFT_LIMITS 0x44028
70415 
70416 #define S_MIN_RD_EYE_SIZE    8
70417 #define M_MIN_RD_EYE_SIZE    0x3fU
70418 #define V_MIN_RD_EYE_SIZE(x) ((x) << S_MIN_RD_EYE_SIZE)
70419 #define G_MIN_RD_EYE_SIZE(x) (((x) >> S_MIN_RD_EYE_SIZE) & M_MIN_RD_EYE_SIZE)
70420 
70421 #define S_MAX_DQS_DRIFT    0
70422 #define M_MAX_DQS_DRIFT    0x3fU
70423 #define V_MAX_DQS_DRIFT(x) ((x) << S_MAX_DQS_DRIFT)
70424 #define G_MAX_DQS_DRIFT(x) (((x) >> S_MAX_DQS_DRIFT) & M_MAX_DQS_DRIFT)
70425 
70426 #define A_MC_DDRPHY_DP18_DEBUG_SEL 0x4402c
70427 
70428 #define S_HS_PROBE_A_SEL    11
70429 #define M_HS_PROBE_A_SEL    0x1fU
70430 #define V_HS_PROBE_A_SEL(x) ((x) << S_HS_PROBE_A_SEL)
70431 #define G_HS_PROBE_A_SEL(x) (((x) >> S_HS_PROBE_A_SEL) & M_HS_PROBE_A_SEL)
70432 
70433 #define S_HS_PROBE_B_SEL    6
70434 #define M_HS_PROBE_B_SEL    0x1fU
70435 #define V_HS_PROBE_B_SEL(x) ((x) << S_HS_PROBE_B_SEL)
70436 #define G_HS_PROBE_B_SEL(x) (((x) >> S_HS_PROBE_B_SEL) & M_HS_PROBE_B_SEL)
70437 
70438 #define S_RD_DEBUG_SEL    3
70439 #define M_RD_DEBUG_SEL    0x7U
70440 #define V_RD_DEBUG_SEL(x) ((x) << S_RD_DEBUG_SEL)
70441 #define G_RD_DEBUG_SEL(x) (((x) >> S_RD_DEBUG_SEL) & M_RD_DEBUG_SEL)
70442 
70443 #define S_WR_DEBUG_SEL    0
70444 #define M_WR_DEBUG_SEL    0x7U
70445 #define V_WR_DEBUG_SEL(x) ((x) << S_WR_DEBUG_SEL)
70446 #define G_WR_DEBUG_SEL(x) (((x) >> S_WR_DEBUG_SEL) & M_WR_DEBUG_SEL)
70447 
70448 #define S_DP18_HS_PROBE_A_SEL    11
70449 #define M_DP18_HS_PROBE_A_SEL    0x1fU
70450 #define V_DP18_HS_PROBE_A_SEL(x) ((x) << S_DP18_HS_PROBE_A_SEL)
70451 #define G_DP18_HS_PROBE_A_SEL(x) (((x) >> S_DP18_HS_PROBE_A_SEL) & M_DP18_HS_PROBE_A_SEL)
70452 
70453 #define S_DP18_HS_PROBE_B_SEL    6
70454 #define M_DP18_HS_PROBE_B_SEL    0x1fU
70455 #define V_DP18_HS_PROBE_B_SEL(x) ((x) << S_DP18_HS_PROBE_B_SEL)
70456 #define G_DP18_HS_PROBE_B_SEL(x) (((x) >> S_DP18_HS_PROBE_B_SEL) & M_DP18_HS_PROBE_B_SEL)
70457 
70458 #define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR 0x44030
70459 
70460 #define S_OFFSET_BITS1_7    8
70461 #define M_OFFSET_BITS1_7    0x7fU
70462 #define V_OFFSET_BITS1_7(x) ((x) << S_OFFSET_BITS1_7)
70463 #define G_OFFSET_BITS1_7(x) (((x) >> S_OFFSET_BITS1_7) & M_OFFSET_BITS1_7)
70464 
70465 #define S_OFFSET_BITS9_15    0
70466 #define M_OFFSET_BITS9_15    0x7fU
70467 #define V_OFFSET_BITS9_15(x) ((x) << S_OFFSET_BITS9_15)
70468 #define G_OFFSET_BITS9_15(x) (((x) >> S_OFFSET_BITS9_15) & M_OFFSET_BITS9_15)
70469 
70470 #define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR 0x44034
70471 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS0 0x44038
70472 
70473 #define S_LEADING_EDGE_NOT_FOUND_0    0
70474 #define M_LEADING_EDGE_NOT_FOUND_0    0xffffU
70475 #define V_LEADING_EDGE_NOT_FOUND_0(x) ((x) << S_LEADING_EDGE_NOT_FOUND_0)
70476 #define G_LEADING_EDGE_NOT_FOUND_0(x) (((x) >> S_LEADING_EDGE_NOT_FOUND_0) & M_LEADING_EDGE_NOT_FOUND_0)
70477 
70478 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS1 0x4403c
70479 
70480 #define S_LEADING_EDGE_NOT_FOUND_1    8
70481 #define M_LEADING_EDGE_NOT_FOUND_1    0xffU
70482 #define V_LEADING_EDGE_NOT_FOUND_1(x) ((x) << S_LEADING_EDGE_NOT_FOUND_1)
70483 #define G_LEADING_EDGE_NOT_FOUND_1(x) (((x) >> S_LEADING_EDGE_NOT_FOUND_1) & M_LEADING_EDGE_NOT_FOUND_1)
70484 
70485 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS2 0x44040
70486 
70487 #define S_TRAILING_EDGE_NOT_FOUND    0
70488 #define M_TRAILING_EDGE_NOT_FOUND    0xffffU
70489 #define V_TRAILING_EDGE_NOT_FOUND(x) ((x) << S_TRAILING_EDGE_NOT_FOUND)
70490 #define G_TRAILING_EDGE_NOT_FOUND(x) (((x) >> S_TRAILING_EDGE_NOT_FOUND) & M_TRAILING_EDGE_NOT_FOUND)
70491 
70492 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS3 0x44044
70493 
70494 #define S_TRAILING_EDGE_NOT_FOUND_16_23    8
70495 #define M_TRAILING_EDGE_NOT_FOUND_16_23    0xffU
70496 #define V_TRAILING_EDGE_NOT_FOUND_16_23(x) ((x) << S_TRAILING_EDGE_NOT_FOUND_16_23)
70497 #define G_TRAILING_EDGE_NOT_FOUND_16_23(x) (((x) >> S_TRAILING_EDGE_NOT_FOUND_16_23) & M_TRAILING_EDGE_NOT_FOUND_16_23)
70498 
70499 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG5 0x44048
70500 
70501 #define S_DYN_POWER_CNTL_EN    15
70502 #define V_DYN_POWER_CNTL_EN(x) ((x) << S_DYN_POWER_CNTL_EN)
70503 #define F_DYN_POWER_CNTL_EN    V_DYN_POWER_CNTL_EN(1U)
70504 
70505 #define S_DYN_MCTERM_CNTL_EN    14
70506 #define V_DYN_MCTERM_CNTL_EN(x) ((x) << S_DYN_MCTERM_CNTL_EN)
70507 #define F_DYN_MCTERM_CNTL_EN    V_DYN_MCTERM_CNTL_EN(1U)
70508 
70509 #define S_DYN_RX_GATE_CNTL_EN    13
70510 #define V_DYN_RX_GATE_CNTL_EN(x) ((x) << S_DYN_RX_GATE_CNTL_EN)
70511 #define F_DYN_RX_GATE_CNTL_EN    V_DYN_RX_GATE_CNTL_EN(1U)
70512 
70513 #define S_CALGATE_ON    12
70514 #define V_CALGATE_ON(x) ((x) << S_CALGATE_ON)
70515 #define F_CALGATE_ON    V_CALGATE_ON(1U)
70516 
70517 #define S_PER_RDCLK_UPDATE_DIS    11
70518 #define V_PER_RDCLK_UPDATE_DIS(x) ((x) << S_PER_RDCLK_UPDATE_DIS)
70519 #define F_PER_RDCLK_UPDATE_DIS    V_PER_RDCLK_UPDATE_DIS(1U)
70520 
70521 #define S_DQS_ALIGN_BY_QUAD    4
70522 #define V_DQS_ALIGN_BY_QUAD(x) ((x) << S_DQS_ALIGN_BY_QUAD)
70523 #define F_DQS_ALIGN_BY_QUAD    V_DQS_ALIGN_BY_QUAD(1U)
70524 
70525 #define A_MC_DDRPHY_DP18_DQS_GATE_DELAY_RP 0x4404c
70526 
70527 #define S_DQS_GATE_DELAY_N0    12
70528 #define M_DQS_GATE_DELAY_N0    0x7U
70529 #define V_DQS_GATE_DELAY_N0(x) ((x) << S_DQS_GATE_DELAY_N0)
70530 #define G_DQS_GATE_DELAY_N0(x) (((x) >> S_DQS_GATE_DELAY_N0) & M_DQS_GATE_DELAY_N0)
70531 
70532 #define S_DQS_GATE_DELAY_N1    8
70533 #define M_DQS_GATE_DELAY_N1    0x7U
70534 #define V_DQS_GATE_DELAY_N1(x) ((x) << S_DQS_GATE_DELAY_N1)
70535 #define G_DQS_GATE_DELAY_N1(x) (((x) >> S_DQS_GATE_DELAY_N1) & M_DQS_GATE_DELAY_N1)
70536 
70537 #define S_DQS_GATE_DELAY_N2    4
70538 #define M_DQS_GATE_DELAY_N2    0x7U
70539 #define V_DQS_GATE_DELAY_N2(x) ((x) << S_DQS_GATE_DELAY_N2)
70540 #define G_DQS_GATE_DELAY_N2(x) (((x) >> S_DQS_GATE_DELAY_N2) & M_DQS_GATE_DELAY_N2)
70541 
70542 #define S_DQS_GATE_DELAY_N3    0
70543 #define M_DQS_GATE_DELAY_N3    0x7U
70544 #define V_DQS_GATE_DELAY_N3(x) ((x) << S_DQS_GATE_DELAY_N3)
70545 #define G_DQS_GATE_DELAY_N3(x) (((x) >> S_DQS_GATE_DELAY_N3) & M_DQS_GATE_DELAY_N3)
70546 
70547 #define A_MC_DDRPHY_DP18_RD_STATUS0 0x44050
70548 
70549 #define S_NO_EYE_DETECTED    15
70550 #define V_NO_EYE_DETECTED(x) ((x) << S_NO_EYE_DETECTED)
70551 #define F_NO_EYE_DETECTED    V_NO_EYE_DETECTED(1U)
70552 
70553 #define S_LEADING_EDGE_FOUND    14
70554 #define V_LEADING_EDGE_FOUND(x) ((x) << S_LEADING_EDGE_FOUND)
70555 #define F_LEADING_EDGE_FOUND    V_LEADING_EDGE_FOUND(1U)
70556 
70557 #define S_TRAILING_EDGE_FOUND    13
70558 #define V_TRAILING_EDGE_FOUND(x) ((x) << S_TRAILING_EDGE_FOUND)
70559 #define F_TRAILING_EDGE_FOUND    V_TRAILING_EDGE_FOUND(1U)
70560 
70561 #define S_INCOMPLETE_RD_CAL_N0    12
70562 #define V_INCOMPLETE_RD_CAL_N0(x) ((x) << S_INCOMPLETE_RD_CAL_N0)
70563 #define F_INCOMPLETE_RD_CAL_N0    V_INCOMPLETE_RD_CAL_N0(1U)
70564 
70565 #define S_INCOMPLETE_RD_CAL_N1    11
70566 #define V_INCOMPLETE_RD_CAL_N1(x) ((x) << S_INCOMPLETE_RD_CAL_N1)
70567 #define F_INCOMPLETE_RD_CAL_N1    V_INCOMPLETE_RD_CAL_N1(1U)
70568 
70569 #define S_INCOMPLETE_RD_CAL_N2    10
70570 #define V_INCOMPLETE_RD_CAL_N2(x) ((x) << S_INCOMPLETE_RD_CAL_N2)
70571 #define F_INCOMPLETE_RD_CAL_N2    V_INCOMPLETE_RD_CAL_N2(1U)
70572 
70573 #define S_INCOMPLETE_RD_CAL_N3    9
70574 #define V_INCOMPLETE_RD_CAL_N3(x) ((x) << S_INCOMPLETE_RD_CAL_N3)
70575 #define F_INCOMPLETE_RD_CAL_N3    V_INCOMPLETE_RD_CAL_N3(1U)
70576 
70577 #define S_COARSE_PATTERN_ERR_N0    8
70578 #define V_COARSE_PATTERN_ERR_N0(x) ((x) << S_COARSE_PATTERN_ERR_N0)
70579 #define F_COARSE_PATTERN_ERR_N0    V_COARSE_PATTERN_ERR_N0(1U)
70580 
70581 #define S_COARSE_PATTERN_ERR_N1    7
70582 #define V_COARSE_PATTERN_ERR_N1(x) ((x) << S_COARSE_PATTERN_ERR_N1)
70583 #define F_COARSE_PATTERN_ERR_N1    V_COARSE_PATTERN_ERR_N1(1U)
70584 
70585 #define S_COARSE_PATTERN_ERR_N2    6
70586 #define V_COARSE_PATTERN_ERR_N2(x) ((x) << S_COARSE_PATTERN_ERR_N2)
70587 #define F_COARSE_PATTERN_ERR_N2    V_COARSE_PATTERN_ERR_N2(1U)
70588 
70589 #define S_COARSE_PATTERN_ERR_N3    5
70590 #define V_COARSE_PATTERN_ERR_N3(x) ((x) << S_COARSE_PATTERN_ERR_N3)
70591 #define F_COARSE_PATTERN_ERR_N3    V_COARSE_PATTERN_ERR_N3(1U)
70592 
70593 #define S_EYE_CLIPPING    4
70594 #define V_EYE_CLIPPING(x) ((x) << S_EYE_CLIPPING)
70595 #define F_EYE_CLIPPING    V_EYE_CLIPPING(1U)
70596 
70597 #define S_NO_DQS    3
70598 #define V_NO_DQS(x) ((x) << S_NO_DQS)
70599 #define F_NO_DQS    V_NO_DQS(1U)
70600 
70601 #define S_NO_LOCK    2
70602 #define V_NO_LOCK(x) ((x) << S_NO_LOCK)
70603 #define F_NO_LOCK    V_NO_LOCK(1U)
70604 
70605 #define S_DRIFT_ERROR    1
70606 #define V_DRIFT_ERROR(x) ((x) << S_DRIFT_ERROR)
70607 #define F_DRIFT_ERROR    V_DRIFT_ERROR(1U)
70608 
70609 #define S_MIN_EYE    0
70610 #define V_MIN_EYE(x) ((x) << S_MIN_EYE)
70611 #define F_MIN_EYE    V_MIN_EYE(1U)
70612 
70613 #define A_MC_DDRPHY_DP18_RD_ERROR_MASK0 0x44054
70614 
70615 #define S_NO_EYE_DETECTED_MASK    15
70616 #define V_NO_EYE_DETECTED_MASK(x) ((x) << S_NO_EYE_DETECTED_MASK)
70617 #define F_NO_EYE_DETECTED_MASK    V_NO_EYE_DETECTED_MASK(1U)
70618 
70619 #define S_LEADING_EDGE_FOUND_MASK    14
70620 #define V_LEADING_EDGE_FOUND_MASK(x) ((x) << S_LEADING_EDGE_FOUND_MASK)
70621 #define F_LEADING_EDGE_FOUND_MASK    V_LEADING_EDGE_FOUND_MASK(1U)
70622 
70623 #define S_TRAILING_EDGE_FOUND_MASK    13
70624 #define V_TRAILING_EDGE_FOUND_MASK(x) ((x) << S_TRAILING_EDGE_FOUND_MASK)
70625 #define F_TRAILING_EDGE_FOUND_MASK    V_TRAILING_EDGE_FOUND_MASK(1U)
70626 
70627 #define S_INCOMPLETE_RD_CAL_N0_MASK    12
70628 #define V_INCOMPLETE_RD_CAL_N0_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N0_MASK)
70629 #define F_INCOMPLETE_RD_CAL_N0_MASK    V_INCOMPLETE_RD_CAL_N0_MASK(1U)
70630 
70631 #define S_INCOMPLETE_RD_CAL_N1_MASK    11
70632 #define V_INCOMPLETE_RD_CAL_N1_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N1_MASK)
70633 #define F_INCOMPLETE_RD_CAL_N1_MASK    V_INCOMPLETE_RD_CAL_N1_MASK(1U)
70634 
70635 #define S_INCOMPLETE_RD_CAL_N2_MASK    10
70636 #define V_INCOMPLETE_RD_CAL_N2_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N2_MASK)
70637 #define F_INCOMPLETE_RD_CAL_N2_MASK    V_INCOMPLETE_RD_CAL_N2_MASK(1U)
70638 
70639 #define S_INCOMPLETE_RD_CAL_N3_MASK    9
70640 #define V_INCOMPLETE_RD_CAL_N3_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N3_MASK)
70641 #define F_INCOMPLETE_RD_CAL_N3_MASK    V_INCOMPLETE_RD_CAL_N3_MASK(1U)
70642 
70643 #define S_COARSE_PATTERN_ERR_N0_MASK    8
70644 #define V_COARSE_PATTERN_ERR_N0_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N0_MASK)
70645 #define F_COARSE_PATTERN_ERR_N0_MASK    V_COARSE_PATTERN_ERR_N0_MASK(1U)
70646 
70647 #define S_COARSE_PATTERN_ERR_N1_MASK    7
70648 #define V_COARSE_PATTERN_ERR_N1_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N1_MASK)
70649 #define F_COARSE_PATTERN_ERR_N1_MASK    V_COARSE_PATTERN_ERR_N1_MASK(1U)
70650 
70651 #define S_COARSE_PATTERN_ERR_N2_MASK    6
70652 #define V_COARSE_PATTERN_ERR_N2_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N2_MASK)
70653 #define F_COARSE_PATTERN_ERR_N2_MASK    V_COARSE_PATTERN_ERR_N2_MASK(1U)
70654 
70655 #define S_COARSE_PATTERN_ERR_N3_MASK    5
70656 #define V_COARSE_PATTERN_ERR_N3_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N3_MASK)
70657 #define F_COARSE_PATTERN_ERR_N3_MASK    V_COARSE_PATTERN_ERR_N3_MASK(1U)
70658 
70659 #define S_EYE_CLIPPING_MASK    4
70660 #define V_EYE_CLIPPING_MASK(x) ((x) << S_EYE_CLIPPING_MASK)
70661 #define F_EYE_CLIPPING_MASK    V_EYE_CLIPPING_MASK(1U)
70662 
70663 #define S_NO_DQS_MASK    3
70664 #define V_NO_DQS_MASK(x) ((x) << S_NO_DQS_MASK)
70665 #define F_NO_DQS_MASK    V_NO_DQS_MASK(1U)
70666 
70667 #define S_NO_LOCK_MASK    2
70668 #define V_NO_LOCK_MASK(x) ((x) << S_NO_LOCK_MASK)
70669 #define F_NO_LOCK_MASK    V_NO_LOCK_MASK(1U)
70670 
70671 #define S_DRIFT_ERROR_MASK    1
70672 #define V_DRIFT_ERROR_MASK(x) ((x) << S_DRIFT_ERROR_MASK)
70673 #define F_DRIFT_ERROR_MASK    V_DRIFT_ERROR_MASK(1U)
70674 
70675 #define S_MIN_EYE_MASK    0
70676 #define V_MIN_EYE_MASK(x) ((x) << S_MIN_EYE_MASK)
70677 #define F_MIN_EYE_MASK    V_MIN_EYE_MASK(1U)
70678 
70679 #define A_MC_DDRPHY_DP18_WRCLK_CNTL 0x44058
70680 
70681 #define S_PRBS_WAIT    14
70682 #define M_PRBS_WAIT    0x3U
70683 #define V_PRBS_WAIT(x) ((x) << S_PRBS_WAIT)
70684 #define G_PRBS_WAIT(x) (((x) >> S_PRBS_WAIT) & M_PRBS_WAIT)
70685 
70686 #define S_PRBS_SYNC_EARLY    13
70687 #define V_PRBS_SYNC_EARLY(x) ((x) << S_PRBS_SYNC_EARLY)
70688 #define F_PRBS_SYNC_EARLY    V_PRBS_SYNC_EARLY(1U)
70689 
70690 #define S_RD_DELAY_EARLY    12
70691 #define V_RD_DELAY_EARLY(x) ((x) << S_RD_DELAY_EARLY)
70692 #define F_RD_DELAY_EARLY    V_RD_DELAY_EARLY(1U)
70693 
70694 #define S_SS_QUAD_CAL    10
70695 #define V_SS_QUAD_CAL(x) ((x) << S_SS_QUAD_CAL)
70696 #define F_SS_QUAD_CAL    V_SS_QUAD_CAL(1U)
70697 
70698 #define S_SS_QUAD    8
70699 #define M_SS_QUAD    0x3U
70700 #define V_SS_QUAD(x) ((x) << S_SS_QUAD)
70701 #define G_SS_QUAD(x) (((x) >> S_SS_QUAD) & M_SS_QUAD)
70702 
70703 #define S_SS_RD_DELAY    7
70704 #define V_SS_RD_DELAY(x) ((x) << S_SS_RD_DELAY)
70705 #define F_SS_RD_DELAY    V_SS_RD_DELAY(1U)
70706 
70707 #define S_FORCE_HI_Z    6
70708 #define V_FORCE_HI_Z(x) ((x) << S_FORCE_HI_Z)
70709 #define F_FORCE_HI_Z    V_FORCE_HI_Z(1U)
70710 
70711 #define A_MC_DDRPHY_DP18_WR_LVL_STATUS0 0x4405c
70712 
70713 #define S_CLK_LEVEL    14
70714 #define M_CLK_LEVEL    0x3U
70715 #define V_CLK_LEVEL(x) ((x) << S_CLK_LEVEL)
70716 #define G_CLK_LEVEL(x) (((x) >> S_CLK_LEVEL) & M_CLK_LEVEL)
70717 
70718 #define S_FINE_STEPPING    13
70719 #define V_FINE_STEPPING(x) ((x) << S_FINE_STEPPING)
70720 #define F_FINE_STEPPING    V_FINE_STEPPING(1U)
70721 
70722 #define S_DONE    12
70723 #define V_DONE(x) ((x) << S_DONE)
70724 #define F_DONE    V_DONE(1U)
70725 
70726 #define S_WL_ERR_CLK16_ST    11
70727 #define V_WL_ERR_CLK16_ST(x) ((x) << S_WL_ERR_CLK16_ST)
70728 #define F_WL_ERR_CLK16_ST    V_WL_ERR_CLK16_ST(1U)
70729 
70730 #define S_WL_ERR_CLK18_ST    10
70731 #define V_WL_ERR_CLK18_ST(x) ((x) << S_WL_ERR_CLK18_ST)
70732 #define F_WL_ERR_CLK18_ST    V_WL_ERR_CLK18_ST(1U)
70733 
70734 #define S_WL_ERR_CLK20_ST    9
70735 #define V_WL_ERR_CLK20_ST(x) ((x) << S_WL_ERR_CLK20_ST)
70736 #define F_WL_ERR_CLK20_ST    V_WL_ERR_CLK20_ST(1U)
70737 
70738 #define S_WL_ERR_CLK22_ST    8
70739 #define V_WL_ERR_CLK22_ST(x) ((x) << S_WL_ERR_CLK22_ST)
70740 #define F_WL_ERR_CLK22_ST    V_WL_ERR_CLK22_ST(1U)
70741 
70742 #define S_ZERO_DETECTED    7
70743 #define V_ZERO_DETECTED(x) ((x) << S_ZERO_DETECTED)
70744 #define F_ZERO_DETECTED    V_ZERO_DETECTED(1U)
70745 
70746 #define S_WR_LVL_DONE    12
70747 #define V_WR_LVL_DONE(x) ((x) << S_WR_LVL_DONE)
70748 #define F_WR_LVL_DONE    V_WR_LVL_DONE(1U)
70749 
70750 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS0 0x44060
70751 
70752 #define S_BIT_CENTERED    11
70753 #define M_BIT_CENTERED    0x1fU
70754 #define V_BIT_CENTERED(x) ((x) << S_BIT_CENTERED)
70755 #define G_BIT_CENTERED(x) (((x) >> S_BIT_CENTERED) & M_BIT_CENTERED)
70756 
70757 #define S_SMALL_STEP_LEFT    10
70758 #define V_SMALL_STEP_LEFT(x) ((x) << S_SMALL_STEP_LEFT)
70759 #define F_SMALL_STEP_LEFT    V_SMALL_STEP_LEFT(1U)
70760 
70761 #define S_BIG_STEP_RIGHT    9
70762 #define V_BIG_STEP_RIGHT(x) ((x) << S_BIG_STEP_RIGHT)
70763 #define F_BIG_STEP_RIGHT    V_BIG_STEP_RIGHT(1U)
70764 
70765 #define S_MATCH_STEP_RIGHT    8
70766 #define V_MATCH_STEP_RIGHT(x) ((x) << S_MATCH_STEP_RIGHT)
70767 #define F_MATCH_STEP_RIGHT    V_MATCH_STEP_RIGHT(1U)
70768 
70769 #define S_JUMP_BACK_RIGHT    7
70770 #define V_JUMP_BACK_RIGHT(x) ((x) << S_JUMP_BACK_RIGHT)
70771 #define F_JUMP_BACK_RIGHT    V_JUMP_BACK_RIGHT(1U)
70772 
70773 #define S_SMALL_STEP_RIGHT    6
70774 #define V_SMALL_STEP_RIGHT(x) ((x) << S_SMALL_STEP_RIGHT)
70775 #define F_SMALL_STEP_RIGHT    V_SMALL_STEP_RIGHT(1U)
70776 
70777 #define S_DDONE    5
70778 #define V_DDONE(x) ((x) << S_DDONE)
70779 #define F_DDONE    V_DDONE(1U)
70780 
70781 #define S_WR_CNTR_DONE    5
70782 #define V_WR_CNTR_DONE(x) ((x) << S_WR_CNTR_DONE)
70783 #define F_WR_CNTR_DONE    V_WR_CNTR_DONE(1U)
70784 
70785 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS1 0x44064
70786 
70787 #define S_FW_LEFT_SIDE    5
70788 #define M_FW_LEFT_SIDE    0x7ffU
70789 #define V_FW_LEFT_SIDE(x) ((x) << S_FW_LEFT_SIDE)
70790 #define G_FW_LEFT_SIDE(x) (((x) >> S_FW_LEFT_SIDE) & M_FW_LEFT_SIDE)
70791 
70792 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS2 0x44068
70793 
70794 #define S_FW_RIGHT_SIDE    5
70795 #define M_FW_RIGHT_SIDE    0x7ffU
70796 #define V_FW_RIGHT_SIDE(x) ((x) << S_FW_RIGHT_SIDE)
70797 #define G_FW_RIGHT_SIDE(x) (((x) >> S_FW_RIGHT_SIDE) & M_FW_RIGHT_SIDE)
70798 
70799 #define A_MC_DDRPHY_DP18_WR_ERROR0 0x4406c
70800 
70801 #define S_WL_ERR_CLK16    15
70802 #define V_WL_ERR_CLK16(x) ((x) << S_WL_ERR_CLK16)
70803 #define F_WL_ERR_CLK16    V_WL_ERR_CLK16(1U)
70804 
70805 #define S_WL_ERR_CLK18    14
70806 #define V_WL_ERR_CLK18(x) ((x) << S_WL_ERR_CLK18)
70807 #define F_WL_ERR_CLK18    V_WL_ERR_CLK18(1U)
70808 
70809 #define S_WL_ERR_CLK20    13
70810 #define V_WL_ERR_CLK20(x) ((x) << S_WL_ERR_CLK20)
70811 #define F_WL_ERR_CLK20    V_WL_ERR_CLK20(1U)
70812 
70813 #define S_WL_ERR_CLK22    12
70814 #define V_WL_ERR_CLK22(x) ((x) << S_WL_ERR_CLK22)
70815 #define F_WL_ERR_CLK22    V_WL_ERR_CLK22(1U)
70816 
70817 #define S_VALID_NS_BIG_L    7
70818 #define V_VALID_NS_BIG_L(x) ((x) << S_VALID_NS_BIG_L)
70819 #define F_VALID_NS_BIG_L    V_VALID_NS_BIG_L(1U)
70820 
70821 #define S_INVALID_NS_SMALL_L    6
70822 #define V_INVALID_NS_SMALL_L(x) ((x) << S_INVALID_NS_SMALL_L)
70823 #define F_INVALID_NS_SMALL_L    V_INVALID_NS_SMALL_L(1U)
70824 
70825 #define S_VALID_NS_BIG_R    5
70826 #define V_VALID_NS_BIG_R(x) ((x) << S_VALID_NS_BIG_R)
70827 #define F_VALID_NS_BIG_R    V_VALID_NS_BIG_R(1U)
70828 
70829 #define S_INVALID_NS_BIG_R    4
70830 #define V_INVALID_NS_BIG_R(x) ((x) << S_INVALID_NS_BIG_R)
70831 #define F_INVALID_NS_BIG_R    V_INVALID_NS_BIG_R(1U)
70832 
70833 #define S_VALID_NS_JUMP_BACK    3
70834 #define V_VALID_NS_JUMP_BACK(x) ((x) << S_VALID_NS_JUMP_BACK)
70835 #define F_VALID_NS_JUMP_BACK    V_VALID_NS_JUMP_BACK(1U)
70836 
70837 #define S_INVALID_NS_SMALL_R    2
70838 #define V_INVALID_NS_SMALL_R(x) ((x) << S_INVALID_NS_SMALL_R)
70839 #define F_INVALID_NS_SMALL_R    V_INVALID_NS_SMALL_R(1U)
70840 
70841 #define S_OFFSET_ERR    1
70842 #define V_OFFSET_ERR(x) ((x) << S_OFFSET_ERR)
70843 #define F_OFFSET_ERR    V_OFFSET_ERR(1U)
70844 
70845 #define A_MC_DDRPHY_DP18_WR_ERROR_MASK0 0x44070
70846 
70847 #define S_WL_ERR_CLK16_MASK    15
70848 #define V_WL_ERR_CLK16_MASK(x) ((x) << S_WL_ERR_CLK16_MASK)
70849 #define F_WL_ERR_CLK16_MASK    V_WL_ERR_CLK16_MASK(1U)
70850 
70851 #define S_WL_ERR_CLK18_MASK    14
70852 #define V_WL_ERR_CLK18_MASK(x) ((x) << S_WL_ERR_CLK18_MASK)
70853 #define F_WL_ERR_CLK18_MASK    V_WL_ERR_CLK18_MASK(1U)
70854 
70855 #define S_WL_ERR_CLK20_MASK    13
70856 #define V_WL_ERR_CLK20_MASK(x) ((x) << S_WL_ERR_CLK20_MASK)
70857 #define F_WL_ERR_CLK20_MASK    V_WL_ERR_CLK20_MASK(1U)
70858 
70859 #define S_WR_ERR_CLK22_MASK    12
70860 #define V_WR_ERR_CLK22_MASK(x) ((x) << S_WR_ERR_CLK22_MASK)
70861 #define F_WR_ERR_CLK22_MASK    V_WR_ERR_CLK22_MASK(1U)
70862 
70863 #define S_VALID_NS_BIG_L_MASK    7
70864 #define V_VALID_NS_BIG_L_MASK(x) ((x) << S_VALID_NS_BIG_L_MASK)
70865 #define F_VALID_NS_BIG_L_MASK    V_VALID_NS_BIG_L_MASK(1U)
70866 
70867 #define S_INVALID_NS_SMALL_L_MASK    6
70868 #define V_INVALID_NS_SMALL_L_MASK(x) ((x) << S_INVALID_NS_SMALL_L_MASK)
70869 #define F_INVALID_NS_SMALL_L_MASK    V_INVALID_NS_SMALL_L_MASK(1U)
70870 
70871 #define S_VALID_NS_BIG_R_MASK    5
70872 #define V_VALID_NS_BIG_R_MASK(x) ((x) << S_VALID_NS_BIG_R_MASK)
70873 #define F_VALID_NS_BIG_R_MASK    V_VALID_NS_BIG_R_MASK(1U)
70874 
70875 #define S_INVALID_NS_BIG_R_MASK    4
70876 #define V_INVALID_NS_BIG_R_MASK(x) ((x) << S_INVALID_NS_BIG_R_MASK)
70877 #define F_INVALID_NS_BIG_R_MASK    V_INVALID_NS_BIG_R_MASK(1U)
70878 
70879 #define S_VALID_NS_JUMP_BACK_MASK    3
70880 #define V_VALID_NS_JUMP_BACK_MASK(x) ((x) << S_VALID_NS_JUMP_BACK_MASK)
70881 #define F_VALID_NS_JUMP_BACK_MASK    V_VALID_NS_JUMP_BACK_MASK(1U)
70882 
70883 #define S_INVALID_NS_SMALL_R_MASK    2
70884 #define V_INVALID_NS_SMALL_R_MASK(x) ((x) << S_INVALID_NS_SMALL_R_MASK)
70885 #define F_INVALID_NS_SMALL_R_MASK    V_INVALID_NS_SMALL_R_MASK(1U)
70886 
70887 #define S_OFFSET_ERR_MASK    1
70888 #define V_OFFSET_ERR_MASK(x) ((x) << S_OFFSET_ERR_MASK)
70889 #define F_OFFSET_ERR_MASK    V_OFFSET_ERR_MASK(1U)
70890 
70891 #define S_DQS_REC_LOW_POWER    11
70892 #define V_DQS_REC_LOW_POWER(x) ((x) << S_DQS_REC_LOW_POWER)
70893 #define F_DQS_REC_LOW_POWER    V_DQS_REC_LOW_POWER(1U)
70894 
70895 #define S_DQ_REC_LOW_POWER    10
70896 #define V_DQ_REC_LOW_POWER(x) ((x) << S_DQ_REC_LOW_POWER)
70897 #define F_DQ_REC_LOW_POWER    V_DQ_REC_LOW_POWER(1U)
70898 
70899 #define S_ADVANCE_PR_VALUE    0
70900 #define V_ADVANCE_PR_VALUE(x) ((x) << S_ADVANCE_PR_VALUE)
70901 #define F_ADVANCE_PR_VALUE    V_ADVANCE_PR_VALUE(1U)
70902 
70903 #define A_MC_DDRPHY_DP18_DFT_WRAP_STATUS 0x44074
70904 
70905 #define S_CHECKER_RESET    14
70906 #define V_CHECKER_RESET(x) ((x) << S_CHECKER_RESET)
70907 #define F_CHECKER_RESET    V_CHECKER_RESET(1U)
70908 
70909 #define S_DP18_DFT_SYNC    6
70910 #define M_DP18_DFT_SYNC    0x3fU
70911 #define V_DP18_DFT_SYNC(x) ((x) << S_DP18_DFT_SYNC)
70912 #define G_DP18_DFT_SYNC(x) (((x) >> S_DP18_DFT_SYNC) & M_DP18_DFT_SYNC)
70913 
70914 #define S_ERROR    0
70915 #define M_ERROR    0x3fU
70916 #define V_ERROR(x) ((x) << S_ERROR)
70917 #define G_ERROR(x) (((x) >> S_ERROR) & M_ERROR)
70918 
70919 #define S_CHECKER_ENABLE    15
70920 #define V_CHECKER_ENABLE(x) ((x) << S_CHECKER_ENABLE)
70921 #define F_CHECKER_ENABLE    V_CHECKER_ENABLE(1U)
70922 
70923 #define S_DP18_DFT_ERROR    0
70924 #define M_DP18_DFT_ERROR    0x3fU
70925 #define V_DP18_DFT_ERROR(x) ((x) << S_DP18_DFT_ERROR)
70926 #define G_DP18_DFT_ERROR(x) (((x) >> S_DP18_DFT_ERROR) & M_DP18_DFT_ERROR)
70927 
70928 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG0 0x44078
70929 
70930 #define S_SYSCLK_RDCLK_OFFSET    8
70931 #define M_SYSCLK_RDCLK_OFFSET    0x7fU
70932 #define V_SYSCLK_RDCLK_OFFSET(x) ((x) << S_SYSCLK_RDCLK_OFFSET)
70933 #define G_SYSCLK_RDCLK_OFFSET(x) (((x) >> S_SYSCLK_RDCLK_OFFSET) & M_SYSCLK_RDCLK_OFFSET)
70934 
70935 #define S_SYSCLK_DQSCLK_OFFSET    0
70936 #define M_SYSCLK_DQSCLK_OFFSET    0x7fU
70937 #define V_SYSCLK_DQSCLK_OFFSET(x) ((x) << S_SYSCLK_DQSCLK_OFFSET)
70938 #define G_SYSCLK_DQSCLK_OFFSET(x) (((x) >> S_SYSCLK_DQSCLK_OFFSET) & M_SYSCLK_DQSCLK_OFFSET)
70939 
70940 #define S_T6_SYSCLK_DQSCLK_OFFSET    8
70941 #define M_T6_SYSCLK_DQSCLK_OFFSET    0x7fU
70942 #define V_T6_SYSCLK_DQSCLK_OFFSET(x) ((x) << S_T6_SYSCLK_DQSCLK_OFFSET)
70943 #define G_T6_SYSCLK_DQSCLK_OFFSET(x) (((x) >> S_T6_SYSCLK_DQSCLK_OFFSET) & M_T6_SYSCLK_DQSCLK_OFFSET)
70944 
70945 #define S_T6_SYSCLK_RDCLK_OFFSET    0
70946 #define M_T6_SYSCLK_RDCLK_OFFSET    0x7fU
70947 #define V_T6_SYSCLK_RDCLK_OFFSET(x) ((x) << S_T6_SYSCLK_RDCLK_OFFSET)
70948 #define G_T6_SYSCLK_RDCLK_OFFSET(x) (((x) >> S_T6_SYSCLK_RDCLK_OFFSET) & M_T6_SYSCLK_RDCLK_OFFSET)
70949 
70950 #define A_MC_DDRPHY_DP18_WRCLK_AUX_CNTL 0x4407c
70951 #define A_MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR 0x440c0
70952 
70953 #define S_DQSCLK_ROT_CLK_N0_N2    8
70954 #define M_DQSCLK_ROT_CLK_N0_N2    0x7fU
70955 #define V_DQSCLK_ROT_CLK_N0_N2(x) ((x) << S_DQSCLK_ROT_CLK_N0_N2)
70956 #define G_DQSCLK_ROT_CLK_N0_N2(x) (((x) >> S_DQSCLK_ROT_CLK_N0_N2) & M_DQSCLK_ROT_CLK_N0_N2)
70957 
70958 #define S_DQSCLK_ROT_CLK_N1_N3    0
70959 #define M_DQSCLK_ROT_CLK_N1_N3    0x7fU
70960 #define V_DQSCLK_ROT_CLK_N1_N3(x) ((x) << S_DQSCLK_ROT_CLK_N1_N3)
70961 #define G_DQSCLK_ROT_CLK_N1_N3(x) (((x) >> S_DQSCLK_ROT_CLK_N1_N3) & M_DQSCLK_ROT_CLK_N1_N3)
70962 
70963 #define A_MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR 0x440c4
70964 #define A_MC_DDRPHY_DP18_PATTERN_POS_0 0x440c8
70965 
70966 #define S_MEMINTD00_POS    14
70967 #define M_MEMINTD00_POS    0x3U
70968 #define V_MEMINTD00_POS(x) ((x) << S_MEMINTD00_POS)
70969 #define G_MEMINTD00_POS(x) (((x) >> S_MEMINTD00_POS) & M_MEMINTD00_POS)
70970 
70971 #define S_MEMINTD01_PO    12
70972 #define M_MEMINTD01_PO    0x3U
70973 #define V_MEMINTD01_PO(x) ((x) << S_MEMINTD01_PO)
70974 #define G_MEMINTD01_PO(x) (((x) >> S_MEMINTD01_PO) & M_MEMINTD01_PO)
70975 
70976 #define S_MEMINTD02_POS    10
70977 #define M_MEMINTD02_POS    0x3U
70978 #define V_MEMINTD02_POS(x) ((x) << S_MEMINTD02_POS)
70979 #define G_MEMINTD02_POS(x) (((x) >> S_MEMINTD02_POS) & M_MEMINTD02_POS)
70980 
70981 #define S_MEMINTD03_POS    8
70982 #define M_MEMINTD03_POS    0x3U
70983 #define V_MEMINTD03_POS(x) ((x) << S_MEMINTD03_POS)
70984 #define G_MEMINTD03_POS(x) (((x) >> S_MEMINTD03_POS) & M_MEMINTD03_POS)
70985 
70986 #define S_MEMINTD04_POS    6
70987 #define M_MEMINTD04_POS    0x3U
70988 #define V_MEMINTD04_POS(x) ((x) << S_MEMINTD04_POS)
70989 #define G_MEMINTD04_POS(x) (((x) >> S_MEMINTD04_POS) & M_MEMINTD04_POS)
70990 
70991 #define S_MEMINTD05_POS    4
70992 #define M_MEMINTD05_POS    0x3U
70993 #define V_MEMINTD05_POS(x) ((x) << S_MEMINTD05_POS)
70994 #define G_MEMINTD05_POS(x) (((x) >> S_MEMINTD05_POS) & M_MEMINTD05_POS)
70995 
70996 #define S_MEMINTD06_POS    2
70997 #define M_MEMINTD06_POS    0x3U
70998 #define V_MEMINTD06_POS(x) ((x) << S_MEMINTD06_POS)
70999 #define G_MEMINTD06_POS(x) (((x) >> S_MEMINTD06_POS) & M_MEMINTD06_POS)
71000 
71001 #define S_MEMINTD07_POS    0
71002 #define M_MEMINTD07_POS    0x3U
71003 #define V_MEMINTD07_POS(x) ((x) << S_MEMINTD07_POS)
71004 #define G_MEMINTD07_POS(x) (((x) >> S_MEMINTD07_POS) & M_MEMINTD07_POS)
71005 
71006 #define A_MC_DDRPHY_DP18_PATTERN_POS_1 0x440cc
71007 
71008 #define S_MEMINTD08_POS    14
71009 #define M_MEMINTD08_POS    0x3U
71010 #define V_MEMINTD08_POS(x) ((x) << S_MEMINTD08_POS)
71011 #define G_MEMINTD08_POS(x) (((x) >> S_MEMINTD08_POS) & M_MEMINTD08_POS)
71012 
71013 #define S_MEMINTD09_POS    12
71014 #define M_MEMINTD09_POS    0x3U
71015 #define V_MEMINTD09_POS(x) ((x) << S_MEMINTD09_POS)
71016 #define G_MEMINTD09_POS(x) (((x) >> S_MEMINTD09_POS) & M_MEMINTD09_POS)
71017 
71018 #define S_MEMINTD10_POS    10
71019 #define M_MEMINTD10_POS    0x3U
71020 #define V_MEMINTD10_POS(x) ((x) << S_MEMINTD10_POS)
71021 #define G_MEMINTD10_POS(x) (((x) >> S_MEMINTD10_POS) & M_MEMINTD10_POS)
71022 
71023 #define S_MEMINTD11_POS    8
71024 #define M_MEMINTD11_POS    0x3U
71025 #define V_MEMINTD11_POS(x) ((x) << S_MEMINTD11_POS)
71026 #define G_MEMINTD11_POS(x) (((x) >> S_MEMINTD11_POS) & M_MEMINTD11_POS)
71027 
71028 #define S_MEMINTD12_POS    6
71029 #define M_MEMINTD12_POS    0x3U
71030 #define V_MEMINTD12_POS(x) ((x) << S_MEMINTD12_POS)
71031 #define G_MEMINTD12_POS(x) (((x) >> S_MEMINTD12_POS) & M_MEMINTD12_POS)
71032 
71033 #define S_MEMINTD13_POS    4
71034 #define M_MEMINTD13_POS    0x3U
71035 #define V_MEMINTD13_POS(x) ((x) << S_MEMINTD13_POS)
71036 #define G_MEMINTD13_POS(x) (((x) >> S_MEMINTD13_POS) & M_MEMINTD13_POS)
71037 
71038 #define S_MEMINTD14_POS    2
71039 #define M_MEMINTD14_POS    0x3U
71040 #define V_MEMINTD14_POS(x) ((x) << S_MEMINTD14_POS)
71041 #define G_MEMINTD14_POS(x) (((x) >> S_MEMINTD14_POS) & M_MEMINTD14_POS)
71042 
71043 #define S_MEMINTD15_POS    0
71044 #define M_MEMINTD15_POS    0x3U
71045 #define V_MEMINTD15_POS(x) ((x) << S_MEMINTD15_POS)
71046 #define G_MEMINTD15_POS(x) (((x) >> S_MEMINTD15_POS) & M_MEMINTD15_POS)
71047 
71048 #define A_MC_DDRPHY_DP18_PATTERN_POS_2 0x440d0
71049 
71050 #define S_MEMINTD16_POS    14
71051 #define M_MEMINTD16_POS    0x3U
71052 #define V_MEMINTD16_POS(x) ((x) << S_MEMINTD16_POS)
71053 #define G_MEMINTD16_POS(x) (((x) >> S_MEMINTD16_POS) & M_MEMINTD16_POS)
71054 
71055 #define S_MEMINTD17_POS    12
71056 #define M_MEMINTD17_POS    0x3U
71057 #define V_MEMINTD17_POS(x) ((x) << S_MEMINTD17_POS)
71058 #define G_MEMINTD17_POS(x) (((x) >> S_MEMINTD17_POS) & M_MEMINTD17_POS)
71059 
71060 #define S_MEMINTD18_POS    10
71061 #define M_MEMINTD18_POS    0x3U
71062 #define V_MEMINTD18_POS(x) ((x) << S_MEMINTD18_POS)
71063 #define G_MEMINTD18_POS(x) (((x) >> S_MEMINTD18_POS) & M_MEMINTD18_POS)
71064 
71065 #define S_MEMINTD19_POS    8
71066 #define M_MEMINTD19_POS    0x3U
71067 #define V_MEMINTD19_POS(x) ((x) << S_MEMINTD19_POS)
71068 #define G_MEMINTD19_POS(x) (((x) >> S_MEMINTD19_POS) & M_MEMINTD19_POS)
71069 
71070 #define S_MEMINTD20_POS    6
71071 #define M_MEMINTD20_POS    0x3U
71072 #define V_MEMINTD20_POS(x) ((x) << S_MEMINTD20_POS)
71073 #define G_MEMINTD20_POS(x) (((x) >> S_MEMINTD20_POS) & M_MEMINTD20_POS)
71074 
71075 #define S_MEMINTD21_POS    4
71076 #define M_MEMINTD21_POS    0x3U
71077 #define V_MEMINTD21_POS(x) ((x) << S_MEMINTD21_POS)
71078 #define G_MEMINTD21_POS(x) (((x) >> S_MEMINTD21_POS) & M_MEMINTD21_POS)
71079 
71080 #define S_MEMINTD22_POS    2
71081 #define M_MEMINTD22_POS    0x3U
71082 #define V_MEMINTD22_POS(x) ((x) << S_MEMINTD22_POS)
71083 #define G_MEMINTD22_POS(x) (((x) >> S_MEMINTD22_POS) & M_MEMINTD22_POS)
71084 
71085 #define S_MEMINTD23_POS    0
71086 #define M_MEMINTD23_POS    0x3U
71087 #define V_MEMINTD23_POS(x) ((x) << S_MEMINTD23_POS)
71088 #define G_MEMINTD23_POS(x) (((x) >> S_MEMINTD23_POS) & M_MEMINTD23_POS)
71089 
71090 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG1 0x440d4
71091 
71092 #define S_DQS_ALIGN_SM    11
71093 #define M_DQS_ALIGN_SM    0x1fU
71094 #define V_DQS_ALIGN_SM(x) ((x) << S_DQS_ALIGN_SM)
71095 #define G_DQS_ALIGN_SM(x) (((x) >> S_DQS_ALIGN_SM) & M_DQS_ALIGN_SM)
71096 
71097 #define S_DQS_ALIGN_CNTR    7
71098 #define M_DQS_ALIGN_CNTR    0xfU
71099 #define V_DQS_ALIGN_CNTR(x) ((x) << S_DQS_ALIGN_CNTR)
71100 #define G_DQS_ALIGN_CNTR(x) (((x) >> S_DQS_ALIGN_CNTR) & M_DQS_ALIGN_CNTR)
71101 
71102 #define S_ITERATION_CNTR    6
71103 #define V_ITERATION_CNTR(x) ((x) << S_ITERATION_CNTR)
71104 #define F_ITERATION_CNTR    V_ITERATION_CNTR(1U)
71105 
71106 #define S_DQS_ALIGN_ITER_CNTR    0
71107 #define M_DQS_ALIGN_ITER_CNTR    0x3fU
71108 #define V_DQS_ALIGN_ITER_CNTR(x) ((x) << S_DQS_ALIGN_ITER_CNTR)
71109 #define G_DQS_ALIGN_ITER_CNTR(x) (((x) >> S_DQS_ALIGN_ITER_CNTR) & M_DQS_ALIGN_ITER_CNTR)
71110 
71111 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG2 0x440d8
71112 
71113 #define S_CALIBRATE_BIT    13
71114 #define M_CALIBRATE_BIT    0x7U
71115 #define V_CALIBRATE_BIT(x) ((x) << S_CALIBRATE_BIT)
71116 #define G_CALIBRATE_BIT(x) (((x) >> S_CALIBRATE_BIT) & M_CALIBRATE_BIT)
71117 
71118 #define S_DQS_ALIGN_QUAD    11
71119 #define M_DQS_ALIGN_QUAD    0x3U
71120 #define V_DQS_ALIGN_QUAD(x) ((x) << S_DQS_ALIGN_QUAD)
71121 #define G_DQS_ALIGN_QUAD(x) (((x) >> S_DQS_ALIGN_QUAD) & M_DQS_ALIGN_QUAD)
71122 
71123 #define S_DQS_QUAD_CONFIG    8
71124 #define M_DQS_QUAD_CONFIG    0x7U
71125 #define V_DQS_QUAD_CONFIG(x) ((x) << S_DQS_QUAD_CONFIG)
71126 #define G_DQS_QUAD_CONFIG(x) (((x) >> S_DQS_QUAD_CONFIG) & M_DQS_QUAD_CONFIG)
71127 
71128 #define S_OPERATE_MODE    4
71129 #define M_OPERATE_MODE    0xfU
71130 #define V_OPERATE_MODE(x) ((x) << S_OPERATE_MODE)
71131 #define G_OPERATE_MODE(x) (((x) >> S_OPERATE_MODE) & M_OPERATE_MODE)
71132 
71133 #define S_EN_DQS_OFFSET    3
71134 #define V_EN_DQS_OFFSET(x) ((x) << S_EN_DQS_OFFSET)
71135 #define F_EN_DQS_OFFSET    V_EN_DQS_OFFSET(1U)
71136 
71137 #define S_DQS_ALIGN_JITTER    2
71138 #define V_DQS_ALIGN_JITTER(x) ((x) << S_DQS_ALIGN_JITTER)
71139 #define F_DQS_ALIGN_JITTER    V_DQS_ALIGN_JITTER(1U)
71140 
71141 #define S_DIS_CLK_GATE    1
71142 #define V_DIS_CLK_GATE(x) ((x) << S_DIS_CLK_GATE)
71143 #define F_DIS_CLK_GATE    V_DIS_CLK_GATE(1U)
71144 
71145 #define S_MAX_DQS_ITER    0
71146 #define V_MAX_DQS_ITER(x) ((x) << S_MAX_DQS_ITER)
71147 #define F_MAX_DQS_ITER    V_MAX_DQS_ITER(1U)
71148 
71149 #define A_MC_DDRPHY_DP18_DQSCLK_OFFSET 0x440dc
71150 
71151 #define S_DQS_OFFSET    8
71152 #define M_DQS_OFFSET    0x7fU
71153 #define V_DQS_OFFSET(x) ((x) << S_DQS_OFFSET)
71154 #define G_DQS_OFFSET(x) (((x) >> S_DQS_OFFSET) & M_DQS_OFFSET)
71155 
71156 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP 0x440e0
71157 
71158 #define S_WR_DELAY    6
71159 #define M_WR_DELAY    0x3ffU
71160 #define V_WR_DELAY(x) ((x) << S_WR_DELAY)
71161 #define G_WR_DELAY(x) (((x) >> S_WR_DELAY) & M_WR_DELAY)
71162 
71163 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP 0x440e4
71164 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP 0x440e8
71165 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP 0x440ec
71166 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP 0x440f0
71167 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP 0x440f4
71168 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP 0x440f8
71169 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP 0x440fc
71170 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP 0x44100
71171 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP 0x44104
71172 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP 0x44108
71173 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP 0x4410c
71174 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP 0x44110
71175 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP 0x44114
71176 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP 0x44118
71177 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP 0x4411c
71178 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP 0x44120
71179 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP 0x44124
71180 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP 0x44128
71181 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP 0x4412c
71182 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP 0x44130
71183 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP 0x44134
71184 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP 0x44138
71185 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP 0x4413c
71186 #define A_MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR 0x44140
71187 
71188 #define S_RD_DELAY_BITS0_6    9
71189 #define M_RD_DELAY_BITS0_6    0x7fU
71190 #define V_RD_DELAY_BITS0_6(x) ((x) << S_RD_DELAY_BITS0_6)
71191 #define G_RD_DELAY_BITS0_6(x) (((x) >> S_RD_DELAY_BITS0_6) & M_RD_DELAY_BITS0_6)
71192 
71193 #define S_RD_DELAY_BITS8_14    1
71194 #define M_RD_DELAY_BITS8_14    0x7fU
71195 #define V_RD_DELAY_BITS8_14(x) ((x) << S_RD_DELAY_BITS8_14)
71196 #define G_RD_DELAY_BITS8_14(x) (((x) >> S_RD_DELAY_BITS8_14) & M_RD_DELAY_BITS8_14)
71197 
71198 #define A_MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR 0x44144
71199 #define A_MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR 0x44148
71200 #define A_MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR 0x4414c
71201 #define A_MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR 0x44150
71202 #define A_MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR 0x44154
71203 #define A_MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR 0x44158
71204 #define A_MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR 0x4415c
71205 #define A_MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR 0x44160
71206 #define A_MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR 0x44164
71207 #define A_MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR 0x44168
71208 #define A_MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR 0x4416c
71209 #define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR 0x44170
71210 
71211 #define S_INITIAL_DQS_ROT_N0_N2    8
71212 #define M_INITIAL_DQS_ROT_N0_N2    0x7fU
71213 #define V_INITIAL_DQS_ROT_N0_N2(x) ((x) << S_INITIAL_DQS_ROT_N0_N2)
71214 #define G_INITIAL_DQS_ROT_N0_N2(x) (((x) >> S_INITIAL_DQS_ROT_N0_N2) & M_INITIAL_DQS_ROT_N0_N2)
71215 
71216 #define S_INITIAL_DQS_ROT_N1_N3    0
71217 #define M_INITIAL_DQS_ROT_N1_N3    0x7fU
71218 #define V_INITIAL_DQS_ROT_N1_N3(x) ((x) << S_INITIAL_DQS_ROT_N1_N3)
71219 #define G_INITIAL_DQS_ROT_N1_N3(x) (((x) >> S_INITIAL_DQS_ROT_N1_N3) & M_INITIAL_DQS_ROT_N1_N3)
71220 
71221 #define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR 0x44174
71222 #define A_MC_DDRPHY_DP18_WRCLK_STATUS 0x44178
71223 
71224 #define S_WRCLK_CALIB_DONE    15
71225 #define V_WRCLK_CALIB_DONE(x) ((x) << S_WRCLK_CALIB_DONE)
71226 #define F_WRCLK_CALIB_DONE    V_WRCLK_CALIB_DONE(1U)
71227 
71228 #define S_VALUE_UPDATED    14
71229 #define V_VALUE_UPDATED(x) ((x) << S_VALUE_UPDATED)
71230 #define F_VALUE_UPDATED    V_VALUE_UPDATED(1U)
71231 
71232 #define S_FAIL_PASS_V    13
71233 #define V_FAIL_PASS_V(x) ((x) << S_FAIL_PASS_V)
71234 #define F_FAIL_PASS_V    V_FAIL_PASS_V(1U)
71235 
71236 #define S_PASS_FAIL_V    12
71237 #define V_PASS_FAIL_V(x) ((x) << S_PASS_FAIL_V)
71238 #define F_PASS_FAIL_V    V_PASS_FAIL_V(1U)
71239 
71240 #define S_FP_PF_EDGE_NF    11
71241 #define V_FP_PF_EDGE_NF(x) ((x) << S_FP_PF_EDGE_NF)
71242 #define F_FP_PF_EDGE_NF    V_FP_PF_EDGE_NF(1U)
71243 
71244 #define S_NON_SYMETRIC    10
71245 #define V_NON_SYMETRIC(x) ((x) << S_NON_SYMETRIC)
71246 #define F_NON_SYMETRIC    V_NON_SYMETRIC(1U)
71247 
71248 #define S_FULL_RANGE    8
71249 #define V_FULL_RANGE(x) ((x) << S_FULL_RANGE)
71250 #define F_FULL_RANGE    V_FULL_RANGE(1U)
71251 
71252 #define S_QUAD3_EDGES    7
71253 #define V_QUAD3_EDGES(x) ((x) << S_QUAD3_EDGES)
71254 #define F_QUAD3_EDGES    V_QUAD3_EDGES(1U)
71255 
71256 #define S_QUAD2_EDGES    6
71257 #define V_QUAD2_EDGES(x) ((x) << S_QUAD2_EDGES)
71258 #define F_QUAD2_EDGES    V_QUAD2_EDGES(1U)
71259 
71260 #define S_QUAD1_EDGES    5
71261 #define V_QUAD1_EDGES(x) ((x) << S_QUAD1_EDGES)
71262 #define F_QUAD1_EDGES    V_QUAD1_EDGES(1U)
71263 
71264 #define S_QUAD0_EDGES    4
71265 #define V_QUAD0_EDGES(x) ((x) << S_QUAD0_EDGES)
71266 #define F_QUAD0_EDGES    V_QUAD0_EDGES(1U)
71267 
71268 #define S_QUAD3_CAVEAT    3
71269 #define V_QUAD3_CAVEAT(x) ((x) << S_QUAD3_CAVEAT)
71270 #define F_QUAD3_CAVEAT    V_QUAD3_CAVEAT(1U)
71271 
71272 #define S_QUAD2_CAVEAT    2
71273 #define V_QUAD2_CAVEAT(x) ((x) << S_QUAD2_CAVEAT)
71274 #define F_QUAD2_CAVEAT    V_QUAD2_CAVEAT(1U)
71275 
71276 #define S_QUAD1_CAVEAT    1
71277 #define V_QUAD1_CAVEAT(x) ((x) << S_QUAD1_CAVEAT)
71278 #define F_QUAD1_CAVEAT    V_QUAD1_CAVEAT(1U)
71279 
71280 #define S_QUAD0_CAVEAT    0
71281 #define V_QUAD0_CAVEAT(x) ((x) << S_QUAD0_CAVEAT)
71282 #define F_QUAD0_CAVEAT    V_QUAD0_CAVEAT(1U)
71283 
71284 #define A_MC_DDRPHY_DP18_WRCLK_EDGE 0x4417c
71285 
71286 #define S_FAIL_PASS_VALUE    8
71287 #define M_FAIL_PASS_VALUE    0x7fU
71288 #define V_FAIL_PASS_VALUE(x) ((x) << S_FAIL_PASS_VALUE)
71289 #define G_FAIL_PASS_VALUE(x) (((x) >> S_FAIL_PASS_VALUE) & M_FAIL_PASS_VALUE)
71290 
71291 #define S_PASS_FAIL_VALUE    0
71292 #define M_PASS_FAIL_VALUE    0xffU
71293 #define V_PASS_FAIL_VALUE(x) ((x) << S_PASS_FAIL_VALUE)
71294 #define G_PASS_FAIL_VALUE(x) (((x) >> S_PASS_FAIL_VALUE) & M_PASS_FAIL_VALUE)
71295 
71296 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR 0x44180
71297 
71298 #define S_RD_EYE_SIZE_BITS2_7    8
71299 #define M_RD_EYE_SIZE_BITS2_7    0x3fU
71300 #define V_RD_EYE_SIZE_BITS2_7(x) ((x) << S_RD_EYE_SIZE_BITS2_7)
71301 #define G_RD_EYE_SIZE_BITS2_7(x) (((x) >> S_RD_EYE_SIZE_BITS2_7) & M_RD_EYE_SIZE_BITS2_7)
71302 
71303 #define S_RD_EYE_SIZE_BITS10_15    0
71304 #define M_RD_EYE_SIZE_BITS10_15    0x3fU
71305 #define V_RD_EYE_SIZE_BITS10_15(x) ((x) << S_RD_EYE_SIZE_BITS10_15)
71306 #define G_RD_EYE_SIZE_BITS10_15(x) (((x) >> S_RD_EYE_SIZE_BITS10_15) & M_RD_EYE_SIZE_BITS10_15)
71307 
71308 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR 0x44184
71309 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR 0x44188
71310 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR 0x4418c
71311 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR 0x44190
71312 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR 0x44194
71313 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR 0x44198
71314 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR 0x4419c
71315 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR 0x441a0
71316 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR 0x441a4
71317 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR 0x441a8
71318 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR 0x441ac
71319 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG3 0x441b4
71320 
71321 #define S_DESIRED_EDGE_CNTR_TARGET_HIGH    8
71322 #define M_DESIRED_EDGE_CNTR_TARGET_HIGH    0xffU
71323 #define V_DESIRED_EDGE_CNTR_TARGET_HIGH(x) ((x) << S_DESIRED_EDGE_CNTR_TARGET_HIGH)
71324 #define G_DESIRED_EDGE_CNTR_TARGET_HIGH(x) (((x) >> S_DESIRED_EDGE_CNTR_TARGET_HIGH) & M_DESIRED_EDGE_CNTR_TARGET_HIGH)
71325 
71326 #define S_DESIRED_EDGE_CNTR_TARGET_LOW    0
71327 #define M_DESIRED_EDGE_CNTR_TARGET_LOW    0xffU
71328 #define V_DESIRED_EDGE_CNTR_TARGET_LOW(x) ((x) << S_DESIRED_EDGE_CNTR_TARGET_LOW)
71329 #define G_DESIRED_EDGE_CNTR_TARGET_LOW(x) (((x) >> S_DESIRED_EDGE_CNTR_TARGET_LOW) & M_DESIRED_EDGE_CNTR_TARGET_LOW)
71330 
71331 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG4 0x441b8
71332 
71333 #define S_APPROACH_ALIGNMENT    15
71334 #define V_APPROACH_ALIGNMENT(x) ((x) << S_APPROACH_ALIGNMENT)
71335 #define F_APPROACH_ALIGNMENT    V_APPROACH_ALIGNMENT(1U)
71336 
71337 #define A_MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL 0x441bc
71338 
71339 #define S_QUAD0_PWR_CTL    12
71340 #define M_QUAD0_PWR_CTL    0xfU
71341 #define V_QUAD0_PWR_CTL(x) ((x) << S_QUAD0_PWR_CTL)
71342 #define G_QUAD0_PWR_CTL(x) (((x) >> S_QUAD0_PWR_CTL) & M_QUAD0_PWR_CTL)
71343 
71344 #define S_QUAD1_PWR_CTL    8
71345 #define M_QUAD1_PWR_CTL    0xfU
71346 #define V_QUAD1_PWR_CTL(x) ((x) << S_QUAD1_PWR_CTL)
71347 #define G_QUAD1_PWR_CTL(x) (((x) >> S_QUAD1_PWR_CTL) & M_QUAD1_PWR_CTL)
71348 
71349 #define S_QUAD2_PWR_CTL    4
71350 #define M_QUAD2_PWR_CTL    0xfU
71351 #define V_QUAD2_PWR_CTL(x) ((x) << S_QUAD2_PWR_CTL)
71352 #define G_QUAD2_PWR_CTL(x) (((x) >> S_QUAD2_PWR_CTL) & M_QUAD2_PWR_CTL)
71353 
71354 #define S_QUAD3_PWR_CTL    0
71355 #define M_QUAD3_PWR_CTL    0xfU
71356 #define V_QUAD3_PWR_CTL(x) ((x) << S_QUAD3_PWR_CTL)
71357 #define G_QUAD3_PWR_CTL(x) (((x) >> S_QUAD3_PWR_CTL) & M_QUAD3_PWR_CTL)
71358 
71359 #define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE0 0x441c0
71360 
71361 #define S_REFERENCE_BITS1_7    8
71362 #define M_REFERENCE_BITS1_7    0x7fU
71363 #define V_REFERENCE_BITS1_7(x) ((x) << S_REFERENCE_BITS1_7)
71364 #define G_REFERENCE_BITS1_7(x) (((x) >> S_REFERENCE_BITS1_7) & M_REFERENCE_BITS1_7)
71365 
71366 #define S_REFERENCE_BITS9_15    0
71367 #define M_REFERENCE_BITS9_15    0x7fU
71368 #define V_REFERENCE_BITS9_15(x) ((x) << S_REFERENCE_BITS9_15)
71369 #define G_REFERENCE_BITS9_15(x) (((x) >> S_REFERENCE_BITS9_15) & M_REFERENCE_BITS9_15)
71370 
71371 #define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE1 0x441c4
71372 #define A_MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE 0x441c8
71373 
71374 #define S_REFERENCE    8
71375 #define M_REFERENCE    0x7fU
71376 #define V_REFERENCE(x) ((x) << S_REFERENCE)
71377 #define G_REFERENCE(x) (((x) >> S_REFERENCE) & M_REFERENCE)
71378 
71379 #define A_MC_DDRPHY_DP18_SYSCLK_PR_VALUE 0x441cc
71380 #define A_MC_DDRPHY_DP18_WRCLK_PR 0x441d0
71381 #define A_MC_DDRPHY_DP18_IO_TX_CONFIG0 0x441d4
71382 
71383 #define S_INTERP_SIG_SLEW    12
71384 #define M_INTERP_SIG_SLEW    0xfU
71385 #define V_INTERP_SIG_SLEW(x) ((x) << S_INTERP_SIG_SLEW)
71386 #define G_INTERP_SIG_SLEW(x) (((x) >> S_INTERP_SIG_SLEW) & M_INTERP_SIG_SLEW)
71387 
71388 #define S_POST_CURSOR    8
71389 #define M_POST_CURSOR    0xfU
71390 #define V_POST_CURSOR(x) ((x) << S_POST_CURSOR)
71391 #define G_POST_CURSOR(x) (((x) >> S_POST_CURSOR) & M_POST_CURSOR)
71392 
71393 #define S_SLEW_CTL    4
71394 #define M_SLEW_CTL    0xfU
71395 #define V_SLEW_CTL(x) ((x) << S_SLEW_CTL)
71396 #define G_SLEW_CTL(x) (((x) >> S_SLEW_CTL) & M_SLEW_CTL)
71397 
71398 #define A_MC_DDRPHY_DP18_PLL_CONFIG0 0x441d8
71399 #define A_MC_DDRPHY_DP18_PLL_CONFIG1 0x441dc
71400 
71401 #define S_CE0DLTVCCA    7
71402 #define V_CE0DLTVCCA(x) ((x) << S_CE0DLTVCCA)
71403 #define F_CE0DLTVCCA    V_CE0DLTVCCA(1U)
71404 
71405 #define S_CE0DLTVCCD1    4
71406 #define V_CE0DLTVCCD1(x) ((x) << S_CE0DLTVCCD1)
71407 #define F_CE0DLTVCCD1    V_CE0DLTVCCD1(1U)
71408 
71409 #define S_CE0DLTVCCD2    3
71410 #define V_CE0DLTVCCD2(x) ((x) << S_CE0DLTVCCD2)
71411 #define F_CE0DLTVCCD2    V_CE0DLTVCCD2(1U)
71412 
71413 #define S_S0INSDLYTAP    2
71414 #define V_S0INSDLYTAP(x) ((x) << S_S0INSDLYTAP)
71415 #define F_S0INSDLYTAP    V_S0INSDLYTAP(1U)
71416 
71417 #define S_S1INSDLYTAP    1
71418 #define V_S1INSDLYTAP(x) ((x) << S_S1INSDLYTAP)
71419 #define F_S1INSDLYTAP    V_S1INSDLYTAP(1U)
71420 
71421 #define A_MC_DDRPHY_DP18_IO_TX_NFET_SLICE 0x441e0
71422 
71423 #define S_EN_SLICE_N_WR    8
71424 #define M_EN_SLICE_N_WR    0xffU
71425 #define V_EN_SLICE_N_WR(x) ((x) << S_EN_SLICE_N_WR)
71426 #define G_EN_SLICE_N_WR(x) (((x) >> S_EN_SLICE_N_WR) & M_EN_SLICE_N_WR)
71427 
71428 #define A_MC_DDRPHY_DP18_IO_TX_PFET_SLICE 0x441e4
71429 #define A_MC_DDRPHY_DP18_IO_TX_NFET_TERM 0x441e8
71430 
71431 #define S_EN_TERM_N_WR    8
71432 #define M_EN_TERM_N_WR    0xffU
71433 #define V_EN_TERM_N_WR(x) ((x) << S_EN_TERM_N_WR)
71434 #define G_EN_TERM_N_WR(x) (((x) >> S_EN_TERM_N_WR) & M_EN_TERM_N_WR)
71435 
71436 #define S_EN_TERM_N_WR_FFE    4
71437 #define M_EN_TERM_N_WR_FFE    0xfU
71438 #define V_EN_TERM_N_WR_FFE(x) ((x) << S_EN_TERM_N_WR_FFE)
71439 #define G_EN_TERM_N_WR_FFE(x) (((x) >> S_EN_TERM_N_WR_FFE) & M_EN_TERM_N_WR_FFE)
71440 
71441 #define A_MC_DDRPHY_DP18_IO_TX_PFET_TERM 0x441ec
71442 
71443 #define S_EN_TERM_P_WR    8
71444 #define M_EN_TERM_P_WR    0xffU
71445 #define V_EN_TERM_P_WR(x) ((x) << S_EN_TERM_P_WR)
71446 #define G_EN_TERM_P_WR(x) (((x) >> S_EN_TERM_P_WR) & M_EN_TERM_P_WR)
71447 
71448 #define S_EN_TERM_P_WR_FFE    4
71449 #define M_EN_TERM_P_WR_FFE    0xfU
71450 #define V_EN_TERM_P_WR_FFE(x) ((x) << S_EN_TERM_P_WR_FFE)
71451 #define G_EN_TERM_P_WR_FFE(x) (((x) >> S_EN_TERM_P_WR_FFE) & M_EN_TERM_P_WR_FFE)
71452 
71453 #define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP 0x441f0
71454 
71455 #define S_DATA_BIT_DISABLE_0_15    0
71456 #define M_DATA_BIT_DISABLE_0_15    0xffffU
71457 #define V_DATA_BIT_DISABLE_0_15(x) ((x) << S_DATA_BIT_DISABLE_0_15)
71458 #define G_DATA_BIT_DISABLE_0_15(x) (((x) >> S_DATA_BIT_DISABLE_0_15) & M_DATA_BIT_DISABLE_0_15)
71459 
71460 #define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP 0x441f4
71461 
71462 #define S_DATA_BIT_DISABLE_16_23    8
71463 #define M_DATA_BIT_DISABLE_16_23    0xffU
71464 #define V_DATA_BIT_DISABLE_16_23(x) ((x) << S_DATA_BIT_DISABLE_16_23)
71465 #define G_DATA_BIT_DISABLE_16_23(x) (((x) >> S_DATA_BIT_DISABLE_16_23) & M_DATA_BIT_DISABLE_16_23)
71466 
71467 #define A_MC_DDRPHY_DP18_DQ_WR_OFFSET_RP 0x441f8
71468 
71469 #define S_DQ_WR_OFFSET_N0    12
71470 #define M_DQ_WR_OFFSET_N0    0xfU
71471 #define V_DQ_WR_OFFSET_N0(x) ((x) << S_DQ_WR_OFFSET_N0)
71472 #define G_DQ_WR_OFFSET_N0(x) (((x) >> S_DQ_WR_OFFSET_N0) & M_DQ_WR_OFFSET_N0)
71473 
71474 #define S_DQ_WR_OFFSET_N1    8
71475 #define M_DQ_WR_OFFSET_N1    0xfU
71476 #define V_DQ_WR_OFFSET_N1(x) ((x) << S_DQ_WR_OFFSET_N1)
71477 #define G_DQ_WR_OFFSET_N1(x) (((x) >> S_DQ_WR_OFFSET_N1) & M_DQ_WR_OFFSET_N1)
71478 
71479 #define S_DQ_WR_OFFSET_N2    4
71480 #define M_DQ_WR_OFFSET_N2    0xfU
71481 #define V_DQ_WR_OFFSET_N2(x) ((x) << S_DQ_WR_OFFSET_N2)
71482 #define G_DQ_WR_OFFSET_N2(x) (((x) >> S_DQ_WR_OFFSET_N2) & M_DQ_WR_OFFSET_N2)
71483 
71484 #define S_DQ_WR_OFFSET_N3    0
71485 #define M_DQ_WR_OFFSET_N3    0xfU
71486 #define V_DQ_WR_OFFSET_N3(x) ((x) << S_DQ_WR_OFFSET_N3)
71487 #define G_DQ_WR_OFFSET_N3(x) (((x) >> S_DQ_WR_OFFSET_N3) & M_DQ_WR_OFFSET_N3)
71488 
71489 #define A_MC_DDRPHY_DP18_POWERDOWN_1 0x441fc
71490 
71491 #define S_EYEDAC_PD    13
71492 #define V_EYEDAC_PD(x) ((x) << S_EYEDAC_PD)
71493 #define F_EYEDAC_PD    V_EYEDAC_PD(1U)
71494 
71495 #define S_ANALOG_OUTPUT_STAB    9
71496 #define V_ANALOG_OUTPUT_STAB(x) ((x) << S_ANALOG_OUTPUT_STAB)
71497 #define F_ANALOG_OUTPUT_STAB    V_ANALOG_OUTPUT_STAB(1U)
71498 
71499 #define S_DP18_RX_PD    2
71500 #define M_DP18_RX_PD    0x3U
71501 #define V_DP18_RX_PD(x) ((x) << S_DP18_RX_PD)
71502 #define G_DP18_RX_PD(x) (((x) >> S_DP18_RX_PD) & M_DP18_RX_PD)
71503 
71504 #define S_DELAY_LINE_CTL_OVERRIDE    4
71505 #define V_DELAY_LINE_CTL_OVERRIDE(x) ((x) << S_DELAY_LINE_CTL_OVERRIDE)
71506 #define F_DELAY_LINE_CTL_OVERRIDE    V_DELAY_LINE_CTL_OVERRIDE(1U)
71507 
71508 #define S_VCC_REG_PD    0
71509 #define V_VCC_REG_PD(x) ((x) << S_VCC_REG_PD)
71510 #define F_VCC_REG_PD    V_VCC_REG_PD(1U)
71511 
71512 #define A_MC_ADR_DDRPHY_ADR_BIT_ENABLE 0x45000
71513 
71514 #define S_BIT_ENABLE_0_11    4
71515 #define M_BIT_ENABLE_0_11    0xfffU
71516 #define V_BIT_ENABLE_0_11(x) ((x) << S_BIT_ENABLE_0_11)
71517 #define G_BIT_ENABLE_0_11(x) (((x) >> S_BIT_ENABLE_0_11) & M_BIT_ENABLE_0_11)
71518 
71519 #define S_BIT_ENABLE_12_15    0
71520 #define M_BIT_ENABLE_12_15    0xfU
71521 #define V_BIT_ENABLE_12_15(x) ((x) << S_BIT_ENABLE_12_15)
71522 #define G_BIT_ENABLE_12_15(x) (((x) >> S_BIT_ENABLE_12_15) & M_BIT_ENABLE_12_15)
71523 
71524 #define A_MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE 0x45004
71525 
71526 #define S_DI_ADR0_ADR1    15
71527 #define V_DI_ADR0_ADR1(x) ((x) << S_DI_ADR0_ADR1)
71528 #define F_DI_ADR0_ADR1    V_DI_ADR0_ADR1(1U)
71529 
71530 #define S_DI_ADR2_ADR3    14
71531 #define V_DI_ADR2_ADR3(x) ((x) << S_DI_ADR2_ADR3)
71532 #define F_DI_ADR2_ADR3    V_DI_ADR2_ADR3(1U)
71533 
71534 #define S_DI_ADR4_ADR5    13
71535 #define V_DI_ADR4_ADR5(x) ((x) << S_DI_ADR4_ADR5)
71536 #define F_DI_ADR4_ADR5    V_DI_ADR4_ADR5(1U)
71537 
71538 #define S_DI_ADR6_ADR7    12
71539 #define V_DI_ADR6_ADR7(x) ((x) << S_DI_ADR6_ADR7)
71540 #define F_DI_ADR6_ADR7    V_DI_ADR6_ADR7(1U)
71541 
71542 #define S_DI_ADR8_ADR9    11
71543 #define V_DI_ADR8_ADR9(x) ((x) << S_DI_ADR8_ADR9)
71544 #define F_DI_ADR8_ADR9    V_DI_ADR8_ADR9(1U)
71545 
71546 #define S_DI_ADR10_ADR11    10
71547 #define V_DI_ADR10_ADR11(x) ((x) << S_DI_ADR10_ADR11)
71548 #define F_DI_ADR10_ADR11    V_DI_ADR10_ADR11(1U)
71549 
71550 #define S_DI_ADR12_ADR13    9
71551 #define V_DI_ADR12_ADR13(x) ((x) << S_DI_ADR12_ADR13)
71552 #define F_DI_ADR12_ADR13    V_DI_ADR12_ADR13(1U)
71553 
71554 #define S_DI_ADR14_ADR15    8
71555 #define V_DI_ADR14_ADR15(x) ((x) << S_DI_ADR14_ADR15)
71556 #define F_DI_ADR14_ADR15    V_DI_ADR14_ADR15(1U)
71557 
71558 #define A_MC_ADR_DDRPHY_ADR_DELAY0 0x45010
71559 
71560 #define S_ADR_DELAY_BITS1_7    8
71561 #define M_ADR_DELAY_BITS1_7    0x7fU
71562 #define V_ADR_DELAY_BITS1_7(x) ((x) << S_ADR_DELAY_BITS1_7)
71563 #define G_ADR_DELAY_BITS1_7(x) (((x) >> S_ADR_DELAY_BITS1_7) & M_ADR_DELAY_BITS1_7)
71564 
71565 #define S_ADR_DELAY_BITS9_15    0
71566 #define M_ADR_DELAY_BITS9_15    0x7fU
71567 #define V_ADR_DELAY_BITS9_15(x) ((x) << S_ADR_DELAY_BITS9_15)
71568 #define G_ADR_DELAY_BITS9_15(x) (((x) >> S_ADR_DELAY_BITS9_15) & M_ADR_DELAY_BITS9_15)
71569 
71570 #define A_MC_ADR_DDRPHY_ADR_DELAY1 0x45014
71571 #define A_MC_ADR_DDRPHY_ADR_DELAY2 0x45018
71572 #define A_MC_ADR_DDRPHY_ADR_DELAY3 0x4501c
71573 #define A_MC_ADR_DDRPHY_ADR_DELAY4 0x45020
71574 #define A_MC_ADR_DDRPHY_ADR_DELAY5 0x45024
71575 #define A_MC_ADR_DDRPHY_ADR_DELAY6 0x45028
71576 #define A_MC_ADR_DDRPHY_ADR_DELAY7 0x4502c
71577 #define A_MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL 0x45030
71578 
71579 #define S_ADR_TEST_LANE_PAIR_FAIL    8
71580 #define M_ADR_TEST_LANE_PAIR_FAIL    0xffU
71581 #define V_ADR_TEST_LANE_PAIR_FAIL(x) ((x) << S_ADR_TEST_LANE_PAIR_FAIL)
71582 #define G_ADR_TEST_LANE_PAIR_FAIL(x) (((x) >> S_ADR_TEST_LANE_PAIR_FAIL) & M_ADR_TEST_LANE_PAIR_FAIL)
71583 
71584 #define S_ADR_TEST_DATA_EN    7
71585 #define V_ADR_TEST_DATA_EN(x) ((x) << S_ADR_TEST_DATA_EN)
71586 #define F_ADR_TEST_DATA_EN    V_ADR_TEST_DATA_EN(1U)
71587 
71588 #define S_DADR_TEST_MODE    5
71589 #define M_DADR_TEST_MODE    0x3U
71590 #define V_DADR_TEST_MODE(x) ((x) << S_DADR_TEST_MODE)
71591 #define G_DADR_TEST_MODE(x) (((x) >> S_DADR_TEST_MODE) & M_DADR_TEST_MODE)
71592 
71593 #define S_ADR_TEST_4TO1_MODE    4
71594 #define V_ADR_TEST_4TO1_MODE(x) ((x) << S_ADR_TEST_4TO1_MODE)
71595 #define F_ADR_TEST_4TO1_MODE    V_ADR_TEST_4TO1_MODE(1U)
71596 
71597 #define S_ADR_TEST_RESET    3
71598 #define V_ADR_TEST_RESET(x) ((x) << S_ADR_TEST_RESET)
71599 #define F_ADR_TEST_RESET    V_ADR_TEST_RESET(1U)
71600 
71601 #define S_ADR_TEST_GEN_EN    2
71602 #define V_ADR_TEST_GEN_EN(x) ((x) << S_ADR_TEST_GEN_EN)
71603 #define F_ADR_TEST_GEN_EN    V_ADR_TEST_GEN_EN(1U)
71604 
71605 #define S_ADR_TEST_CLEAR_ERROR    1
71606 #define V_ADR_TEST_CLEAR_ERROR(x) ((x) << S_ADR_TEST_CLEAR_ERROR)
71607 #define F_ADR_TEST_CLEAR_ERROR    V_ADR_TEST_CLEAR_ERROR(1U)
71608 
71609 #define S_ADR_TEST_CHECK_EN    0
71610 #define V_ADR_TEST_CHECK_EN(x) ((x) << S_ADR_TEST_CHECK_EN)
71611 #define F_ADR_TEST_CHECK_EN    V_ADR_TEST_CHECK_EN(1U)
71612 
71613 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0 0x45040
71614 
71615 #define S_EN_SLICE_N_WR_0    8
71616 #define M_EN_SLICE_N_WR_0    0xffU
71617 #define V_EN_SLICE_N_WR_0(x) ((x) << S_EN_SLICE_N_WR_0)
71618 #define G_EN_SLICE_N_WR_0(x) (((x) >> S_EN_SLICE_N_WR_0) & M_EN_SLICE_N_WR_0)
71619 
71620 #define S_EN_SLICE_N_WR_FFE    4
71621 #define M_EN_SLICE_N_WR_FFE    0xfU
71622 #define V_EN_SLICE_N_WR_FFE(x) ((x) << S_EN_SLICE_N_WR_FFE)
71623 #define G_EN_SLICE_N_WR_FFE(x) (((x) >> S_EN_SLICE_N_WR_FFE) & M_EN_SLICE_N_WR_FFE)
71624 
71625 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1 0x45044
71626 
71627 #define S_EN_SLICE_N_WR_1    8
71628 #define M_EN_SLICE_N_WR_1    0xffU
71629 #define V_EN_SLICE_N_WR_1(x) ((x) << S_EN_SLICE_N_WR_1)
71630 #define G_EN_SLICE_N_WR_1(x) (((x) >> S_EN_SLICE_N_WR_1) & M_EN_SLICE_N_WR_1)
71631 
71632 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2 0x45048
71633 
71634 #define S_EN_SLICE_N_WR_2    8
71635 #define M_EN_SLICE_N_WR_2    0xffU
71636 #define V_EN_SLICE_N_WR_2(x) ((x) << S_EN_SLICE_N_WR_2)
71637 #define G_EN_SLICE_N_WR_2(x) (((x) >> S_EN_SLICE_N_WR_2) & M_EN_SLICE_N_WR_2)
71638 
71639 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3 0x4504c
71640 
71641 #define S_EN_SLICE_N_WR_3    8
71642 #define M_EN_SLICE_N_WR_3    0xffU
71643 #define V_EN_SLICE_N_WR_3(x) ((x) << S_EN_SLICE_N_WR_3)
71644 #define G_EN_SLICE_N_WR_3(x) (((x) >> S_EN_SLICE_N_WR_3) & M_EN_SLICE_N_WR_3)
71645 
71646 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0 0x45050
71647 
71648 #define S_EN_SLICE_P_WR    8
71649 #define M_EN_SLICE_P_WR    0xffU
71650 #define V_EN_SLICE_P_WR(x) ((x) << S_EN_SLICE_P_WR)
71651 #define G_EN_SLICE_P_WR(x) (((x) >> S_EN_SLICE_P_WR) & M_EN_SLICE_P_WR)
71652 
71653 #define S_EN_SLICE_P_WR_FFE    4
71654 #define M_EN_SLICE_P_WR_FFE    0xfU
71655 #define V_EN_SLICE_P_WR_FFE(x) ((x) << S_EN_SLICE_P_WR_FFE)
71656 #define G_EN_SLICE_P_WR_FFE(x) (((x) >> S_EN_SLICE_P_WR_FFE) & M_EN_SLICE_P_WR_FFE)
71657 
71658 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1 0x45054
71659 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2 0x45058
71660 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3 0x4505c
71661 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45060
71662 
71663 #define S_POST_CURSOR0    12
71664 #define M_POST_CURSOR0    0xfU
71665 #define V_POST_CURSOR0(x) ((x) << S_POST_CURSOR0)
71666 #define G_POST_CURSOR0(x) (((x) >> S_POST_CURSOR0) & M_POST_CURSOR0)
71667 
71668 #define S_POST_CURSOR1    8
71669 #define M_POST_CURSOR1    0xfU
71670 #define V_POST_CURSOR1(x) ((x) << S_POST_CURSOR1)
71671 #define G_POST_CURSOR1(x) (((x) >> S_POST_CURSOR1) & M_POST_CURSOR1)
71672 
71673 #define S_POST_CURSOR2    4
71674 #define M_POST_CURSOR2    0xfU
71675 #define V_POST_CURSOR2(x) ((x) << S_POST_CURSOR2)
71676 #define G_POST_CURSOR2(x) (((x) >> S_POST_CURSOR2) & M_POST_CURSOR2)
71677 
71678 #define S_POST_CURSOR3    0
71679 #define M_POST_CURSOR3    0xfU
71680 #define V_POST_CURSOR3(x) ((x) << S_POST_CURSOR3)
71681 #define G_POST_CURSOR3(x) (((x) >> S_POST_CURSOR3) & M_POST_CURSOR3)
71682 
71683 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE 0x45068
71684 
71685 #define S_SLEW_CTL0    12
71686 #define M_SLEW_CTL0    0xfU
71687 #define V_SLEW_CTL0(x) ((x) << S_SLEW_CTL0)
71688 #define G_SLEW_CTL0(x) (((x) >> S_SLEW_CTL0) & M_SLEW_CTL0)
71689 
71690 #define S_SLEW_CTL1    8
71691 #define M_SLEW_CTL1    0xfU
71692 #define V_SLEW_CTL1(x) ((x) << S_SLEW_CTL1)
71693 #define G_SLEW_CTL1(x) (((x) >> S_SLEW_CTL1) & M_SLEW_CTL1)
71694 
71695 #define S_SLEW_CTL2    4
71696 #define M_SLEW_CTL2    0xfU
71697 #define V_SLEW_CTL2(x) ((x) << S_SLEW_CTL2)
71698 #define G_SLEW_CTL2(x) (((x) >> S_SLEW_CTL2) & M_SLEW_CTL2)
71699 
71700 #define S_SLEW_CTL3    0
71701 #define M_SLEW_CTL3    0xfU
71702 #define V_SLEW_CTL3(x) ((x) << S_SLEW_CTL3)
71703 #define G_SLEW_CTL3(x) (((x) >> S_SLEW_CTL3) & M_SLEW_CTL3)
71704 
71705 #define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0 0x45080
71706 
71707 #define S_SLICE_SEL_REG_BITS0_1    14
71708 #define M_SLICE_SEL_REG_BITS0_1    0x3U
71709 #define V_SLICE_SEL_REG_BITS0_1(x) ((x) << S_SLICE_SEL_REG_BITS0_1)
71710 #define G_SLICE_SEL_REG_BITS0_1(x) (((x) >> S_SLICE_SEL_REG_BITS0_1) & M_SLICE_SEL_REG_BITS0_1)
71711 
71712 #define S_SLICE_SEL_REG_BITS2_3    12
71713 #define M_SLICE_SEL_REG_BITS2_3    0x3U
71714 #define V_SLICE_SEL_REG_BITS2_3(x) ((x) << S_SLICE_SEL_REG_BITS2_3)
71715 #define G_SLICE_SEL_REG_BITS2_3(x) (((x) >> S_SLICE_SEL_REG_BITS2_3) & M_SLICE_SEL_REG_BITS2_3)
71716 
71717 #define S_SLICE_SEL_REG_BITS4_5    10
71718 #define M_SLICE_SEL_REG_BITS4_5    0x3U
71719 #define V_SLICE_SEL_REG_BITS4_5(x) ((x) << S_SLICE_SEL_REG_BITS4_5)
71720 #define G_SLICE_SEL_REG_BITS4_5(x) (((x) >> S_SLICE_SEL_REG_BITS4_5) & M_SLICE_SEL_REG_BITS4_5)
71721 
71722 #define S_SLICE_SEL_REG_BITS6_7    8
71723 #define M_SLICE_SEL_REG_BITS6_7    0x3U
71724 #define V_SLICE_SEL_REG_BITS6_7(x) ((x) << S_SLICE_SEL_REG_BITS6_7)
71725 #define G_SLICE_SEL_REG_BITS6_7(x) (((x) >> S_SLICE_SEL_REG_BITS6_7) & M_SLICE_SEL_REG_BITS6_7)
71726 
71727 #define S_SLICE_SEL_REG_BITS8_9    6
71728 #define M_SLICE_SEL_REG_BITS8_9    0x3U
71729 #define V_SLICE_SEL_REG_BITS8_9(x) ((x) << S_SLICE_SEL_REG_BITS8_9)
71730 #define G_SLICE_SEL_REG_BITS8_9(x) (((x) >> S_SLICE_SEL_REG_BITS8_9) & M_SLICE_SEL_REG_BITS8_9)
71731 
71732 #define S_SLICE_SEL_REG_BITS10_11    4
71733 #define M_SLICE_SEL_REG_BITS10_11    0x3U
71734 #define V_SLICE_SEL_REG_BITS10_11(x) ((x) << S_SLICE_SEL_REG_BITS10_11)
71735 #define G_SLICE_SEL_REG_BITS10_11(x) (((x) >> S_SLICE_SEL_REG_BITS10_11) & M_SLICE_SEL_REG_BITS10_11)
71736 
71737 #define S_SLICE_SEL_REG_BITS12_13    2
71738 #define M_SLICE_SEL_REG_BITS12_13    0x3U
71739 #define V_SLICE_SEL_REG_BITS12_13(x) ((x) << S_SLICE_SEL_REG_BITS12_13)
71740 #define G_SLICE_SEL_REG_BITS12_13(x) (((x) >> S_SLICE_SEL_REG_BITS12_13) & M_SLICE_SEL_REG_BITS12_13)
71741 
71742 #define S_SLICE_SEL_REG_BITS14_15    0
71743 #define M_SLICE_SEL_REG_BITS14_15    0x3U
71744 #define V_SLICE_SEL_REG_BITS14_15(x) ((x) << S_SLICE_SEL_REG_BITS14_15)
71745 #define G_SLICE_SEL_REG_BITS14_15(x) (((x) >> S_SLICE_SEL_REG_BITS14_15) & M_SLICE_SEL_REG_BITS14_15)
71746 
71747 #define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1 0x45084
71748 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x450a0
71749 
71750 #define S_POST_CUR_SEL_BITS0_1    14
71751 #define M_POST_CUR_SEL_BITS0_1    0x3U
71752 #define V_POST_CUR_SEL_BITS0_1(x) ((x) << S_POST_CUR_SEL_BITS0_1)
71753 #define G_POST_CUR_SEL_BITS0_1(x) (((x) >> S_POST_CUR_SEL_BITS0_1) & M_POST_CUR_SEL_BITS0_1)
71754 
71755 #define S_POST_CUR_SEL_BITS2_3    12
71756 #define M_POST_CUR_SEL_BITS2_3    0x3U
71757 #define V_POST_CUR_SEL_BITS2_3(x) ((x) << S_POST_CUR_SEL_BITS2_3)
71758 #define G_POST_CUR_SEL_BITS2_3(x) (((x) >> S_POST_CUR_SEL_BITS2_3) & M_POST_CUR_SEL_BITS2_3)
71759 
71760 #define S_POST_CUR_SEL_BITS4_5    10
71761 #define M_POST_CUR_SEL_BITS4_5    0x3U
71762 #define V_POST_CUR_SEL_BITS4_5(x) ((x) << S_POST_CUR_SEL_BITS4_5)
71763 #define G_POST_CUR_SEL_BITS4_5(x) (((x) >> S_POST_CUR_SEL_BITS4_5) & M_POST_CUR_SEL_BITS4_5)
71764 
71765 #define S_POST_CUR_SEL_BITS6_7    8
71766 #define M_POST_CUR_SEL_BITS6_7    0x3U
71767 #define V_POST_CUR_SEL_BITS6_7(x) ((x) << S_POST_CUR_SEL_BITS6_7)
71768 #define G_POST_CUR_SEL_BITS6_7(x) (((x) >> S_POST_CUR_SEL_BITS6_7) & M_POST_CUR_SEL_BITS6_7)
71769 
71770 #define S_POST_CUR_SEL_BITS8_9    6
71771 #define M_POST_CUR_SEL_BITS8_9    0x3U
71772 #define V_POST_CUR_SEL_BITS8_9(x) ((x) << S_POST_CUR_SEL_BITS8_9)
71773 #define G_POST_CUR_SEL_BITS8_9(x) (((x) >> S_POST_CUR_SEL_BITS8_9) & M_POST_CUR_SEL_BITS8_9)
71774 
71775 #define S_POST_CUR_SEL_BITS10_11    4
71776 #define M_POST_CUR_SEL_BITS10_11    0x3U
71777 #define V_POST_CUR_SEL_BITS10_11(x) ((x) << S_POST_CUR_SEL_BITS10_11)
71778 #define G_POST_CUR_SEL_BITS10_11(x) (((x) >> S_POST_CUR_SEL_BITS10_11) & M_POST_CUR_SEL_BITS10_11)
71779 
71780 #define S_POST_CUR_SEL_BITS12_13    2
71781 #define M_POST_CUR_SEL_BITS12_13    0x3U
71782 #define V_POST_CUR_SEL_BITS12_13(x) ((x) << S_POST_CUR_SEL_BITS12_13)
71783 #define G_POST_CUR_SEL_BITS12_13(x) (((x) >> S_POST_CUR_SEL_BITS12_13) & M_POST_CUR_SEL_BITS12_13)
71784 
71785 #define S_POST_CUR_SEL_BITS14_15    0
71786 #define M_POST_CUR_SEL_BITS14_15    0x3U
71787 #define V_POST_CUR_SEL_BITS14_15(x) ((x) << S_POST_CUR_SEL_BITS14_15)
71788 #define G_POST_CUR_SEL_BITS14_15(x) (((x) >> S_POST_CUR_SEL_BITS14_15) & M_POST_CUR_SEL_BITS14_15)
71789 
71790 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x450a4
71791 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0 0x450a8
71792 
71793 #define S_SLEW_CTL_SEL_BITS0_1    14
71794 #define M_SLEW_CTL_SEL_BITS0_1    0x3U
71795 #define V_SLEW_CTL_SEL_BITS0_1(x) ((x) << S_SLEW_CTL_SEL_BITS0_1)
71796 #define G_SLEW_CTL_SEL_BITS0_1(x) (((x) >> S_SLEW_CTL_SEL_BITS0_1) & M_SLEW_CTL_SEL_BITS0_1)
71797 
71798 #define S_SLEW_CTL_SEL_BITS2_3    12
71799 #define M_SLEW_CTL_SEL_BITS2_3    0x3U
71800 #define V_SLEW_CTL_SEL_BITS2_3(x) ((x) << S_SLEW_CTL_SEL_BITS2_3)
71801 #define G_SLEW_CTL_SEL_BITS2_3(x) (((x) >> S_SLEW_CTL_SEL_BITS2_3) & M_SLEW_CTL_SEL_BITS2_3)
71802 
71803 #define S_SLEW_CTL_SEL_BITS4_5    10
71804 #define M_SLEW_CTL_SEL_BITS4_5    0x3U
71805 #define V_SLEW_CTL_SEL_BITS4_5(x) ((x) << S_SLEW_CTL_SEL_BITS4_5)
71806 #define G_SLEW_CTL_SEL_BITS4_5(x) (((x) >> S_SLEW_CTL_SEL_BITS4_5) & M_SLEW_CTL_SEL_BITS4_5)
71807 
71808 #define S_SLEW_CTL_SEL_BITS6_7    8
71809 #define M_SLEW_CTL_SEL_BITS6_7    0x3U
71810 #define V_SLEW_CTL_SEL_BITS6_7(x) ((x) << S_SLEW_CTL_SEL_BITS6_7)
71811 #define G_SLEW_CTL_SEL_BITS6_7(x) (((x) >> S_SLEW_CTL_SEL_BITS6_7) & M_SLEW_CTL_SEL_BITS6_7)
71812 
71813 #define S_SLEW_CTL_SEL_BITS8_9    6
71814 #define M_SLEW_CTL_SEL_BITS8_9    0x3U
71815 #define V_SLEW_CTL_SEL_BITS8_9(x) ((x) << S_SLEW_CTL_SEL_BITS8_9)
71816 #define G_SLEW_CTL_SEL_BITS8_9(x) (((x) >> S_SLEW_CTL_SEL_BITS8_9) & M_SLEW_CTL_SEL_BITS8_9)
71817 
71818 #define S_SLEW_CTL_SEL_BITS10_11    4
71819 #define M_SLEW_CTL_SEL_BITS10_11    0x3U
71820 #define V_SLEW_CTL_SEL_BITS10_11(x) ((x) << S_SLEW_CTL_SEL_BITS10_11)
71821 #define G_SLEW_CTL_SEL_BITS10_11(x) (((x) >> S_SLEW_CTL_SEL_BITS10_11) & M_SLEW_CTL_SEL_BITS10_11)
71822 
71823 #define S_SLEW_CTL_SEL_BITS12_13    2
71824 #define M_SLEW_CTL_SEL_BITS12_13    0x3U
71825 #define V_SLEW_CTL_SEL_BITS12_13(x) ((x) << S_SLEW_CTL_SEL_BITS12_13)
71826 #define G_SLEW_CTL_SEL_BITS12_13(x) (((x) >> S_SLEW_CTL_SEL_BITS12_13) & M_SLEW_CTL_SEL_BITS12_13)
71827 
71828 #define S_SLEW_CTL_SEL_BITS14_15    0
71829 #define M_SLEW_CTL_SEL_BITS14_15    0x3U
71830 #define V_SLEW_CTL_SEL_BITS14_15(x) ((x) << S_SLEW_CTL_SEL_BITS14_15)
71831 #define G_SLEW_CTL_SEL_BITS14_15(x) (((x) >> S_SLEW_CTL_SEL_BITS14_15) & M_SLEW_CTL_SEL_BITS14_15)
71832 
71833 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1 0x450ac
71834 #define A_MC_ADR_DDRPHY_ADR_POWERDOWN_2 0x450b0
71835 
71836 #define S_ADR_LANE_0_11_PD    4
71837 #define M_ADR_LANE_0_11_PD    0xfffU
71838 #define V_ADR_LANE_0_11_PD(x) ((x) << S_ADR_LANE_0_11_PD)
71839 #define G_ADR_LANE_0_11_PD(x) (((x) >> S_ADR_LANE_0_11_PD) & M_ADR_LANE_0_11_PD)
71840 
71841 #define S_ADR_LANE_12_15_PD    0
71842 #define M_ADR_LANE_12_15_PD    0xfU
71843 #define V_ADR_LANE_12_15_PD(x) ((x) << S_ADR_LANE_12_15_PD)
71844 #define G_ADR_LANE_12_15_PD(x) (((x) >> S_ADR_LANE_12_15_PD) & M_ADR_LANE_12_15_PD)
71845 
71846 #define A_T6_MC_ADR_DDRPHY_ADR_BIT_ENABLE 0x45800
71847 #define A_T6_MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE 0x45804
71848 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY0 0x45810
71849 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY1 0x45814
71850 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY2 0x45818
71851 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY3 0x4581c
71852 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY4 0x45820
71853 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY5 0x45824
71854 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY6 0x45828
71855 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY7 0x4582c
71856 #define A_T6_MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL 0x45830
71857 
71858 #define S_ADR_TEST_MODE    5
71859 #define M_ADR_TEST_MODE    0x3U
71860 #define V_ADR_TEST_MODE(x) ((x) << S_ADR_TEST_MODE)
71861 #define G_ADR_TEST_MODE(x) (((x) >> S_ADR_TEST_MODE) & M_ADR_TEST_MODE)
71862 
71863 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0 0x45840
71864 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1 0x45844
71865 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2 0x45848
71866 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3 0x4584c
71867 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0 0x45850
71868 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1 0x45854
71869 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2 0x45858
71870 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3 0x4585c
71871 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45860
71872 #define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE 0x45868
71873 #define A_T6_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0 0x45880
71874 #define A_T6_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1 0x45884
71875 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x458a0
71876 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x458a4
71877 #define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0 0x458a8
71878 #define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1 0x458ac
71879 #define A_T6_MC_ADR_DDRPHY_ADR_POWERDOWN_2 0x458b0
71880 #define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_0 0x460c0
71881 
71882 #define S_PLL_TUNE_0_2    13
71883 #define M_PLL_TUNE_0_2    0x7U
71884 #define V_PLL_TUNE_0_2(x) ((x) << S_PLL_TUNE_0_2)
71885 #define G_PLL_TUNE_0_2(x) (((x) >> S_PLL_TUNE_0_2) & M_PLL_TUNE_0_2)
71886 
71887 #define S_PLL_TUNECP_0_2    10
71888 #define M_PLL_TUNECP_0_2    0x7U
71889 #define V_PLL_TUNECP_0_2(x) ((x) << S_PLL_TUNECP_0_2)
71890 #define G_PLL_TUNECP_0_2(x) (((x) >> S_PLL_TUNECP_0_2) & M_PLL_TUNECP_0_2)
71891 
71892 #define S_PLL_TUNEF_0_5    4
71893 #define M_PLL_TUNEF_0_5    0x3fU
71894 #define V_PLL_TUNEF_0_5(x) ((x) << S_PLL_TUNEF_0_5)
71895 #define G_PLL_TUNEF_0_5(x) (((x) >> S_PLL_TUNEF_0_5) & M_PLL_TUNEF_0_5)
71896 
71897 #define S_PLL_TUNEVCO_0_1    2
71898 #define M_PLL_TUNEVCO_0_1    0x3U
71899 #define V_PLL_TUNEVCO_0_1(x) ((x) << S_PLL_TUNEVCO_0_1)
71900 #define G_PLL_TUNEVCO_0_1(x) (((x) >> S_PLL_TUNEVCO_0_1) & M_PLL_TUNEVCO_0_1)
71901 
71902 #define S_PLL_PLLXTR_0_1    0
71903 #define M_PLL_PLLXTR_0_1    0x3U
71904 #define V_PLL_PLLXTR_0_1(x) ((x) << S_PLL_PLLXTR_0_1)
71905 #define G_PLL_PLLXTR_0_1(x) (((x) >> S_PLL_PLLXTR_0_1) & M_PLL_PLLXTR_0_1)
71906 
71907 #define A_MC_DDRPHY_AD32S_PLL_VREG_CONFIG_0 0x460c0
71908 #define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_1 0x460c4
71909 
71910 #define S_PLL_TUNETDIV_0_2    13
71911 #define M_PLL_TUNETDIV_0_2    0x7U
71912 #define V_PLL_TUNETDIV_0_2(x) ((x) << S_PLL_TUNETDIV_0_2)
71913 #define G_PLL_TUNETDIV_0_2(x) (((x) >> S_PLL_TUNETDIV_0_2) & M_PLL_TUNETDIV_0_2)
71914 
71915 #define S_PLL_TUNEMDIV_0_1    11
71916 #define M_PLL_TUNEMDIV_0_1    0x3U
71917 #define V_PLL_TUNEMDIV_0_1(x) ((x) << S_PLL_TUNEMDIV_0_1)
71918 #define G_PLL_TUNEMDIV_0_1(x) (((x) >> S_PLL_TUNEMDIV_0_1) & M_PLL_TUNEMDIV_0_1)
71919 
71920 #define S_PLL_TUNEATST    10
71921 #define V_PLL_TUNEATST(x) ((x) << S_PLL_TUNEATST)
71922 #define F_PLL_TUNEATST    V_PLL_TUNEATST(1U)
71923 
71924 #define S_VREG_RANGE_0_1    8
71925 #define M_VREG_RANGE_0_1    0x3U
71926 #define V_VREG_RANGE_0_1(x) ((x) << S_VREG_RANGE_0_1)
71927 #define G_VREG_RANGE_0_1(x) (((x) >> S_VREG_RANGE_0_1) & M_VREG_RANGE_0_1)
71928 
71929 #define S_VREG_VREGSPARE    7
71930 #define V_VREG_VREGSPARE(x) ((x) << S_VREG_VREGSPARE)
71931 #define F_VREG_VREGSPARE    V_VREG_VREGSPARE(1U)
71932 
71933 #define S_VREG_VCCTUNE_0_1    5
71934 #define M_VREG_VCCTUNE_0_1    0x3U
71935 #define V_VREG_VCCTUNE_0_1(x) ((x) << S_VREG_VCCTUNE_0_1)
71936 #define G_VREG_VCCTUNE_0_1(x) (((x) >> S_VREG_VCCTUNE_0_1) & M_VREG_VCCTUNE_0_1)
71937 
71938 #define S_INTERP_SIG_SLEW_0_3    1
71939 #define M_INTERP_SIG_SLEW_0_3    0xfU
71940 #define V_INTERP_SIG_SLEW_0_3(x) ((x) << S_INTERP_SIG_SLEW_0_3)
71941 #define G_INTERP_SIG_SLEW_0_3(x) (((x) >> S_INTERP_SIG_SLEW_0_3) & M_INTERP_SIG_SLEW_0_3)
71942 
71943 #define S_ANALOG_WRAPON    0
71944 #define V_ANALOG_WRAPON(x) ((x) << S_ANALOG_WRAPON)
71945 #define F_ANALOG_WRAPON    V_ANALOG_WRAPON(1U)
71946 
71947 #define A_MC_DDRPHY_AD32S_PLL_VREG_CONFIG_1 0x460c4
71948 #define A_MC_DDRPHY_ADR_SYSCLK_CNTL_PR 0x460c8
71949 
71950 #define S_SYSCLK_ENABLE    15
71951 #define V_SYSCLK_ENABLE(x) ((x) << S_SYSCLK_ENABLE)
71952 #define F_SYSCLK_ENABLE    V_SYSCLK_ENABLE(1U)
71953 
71954 #define S_SYSCLK_ROT_OVERRIDE    8
71955 #define M_SYSCLK_ROT_OVERRIDE    0x7fU
71956 #define V_SYSCLK_ROT_OVERRIDE(x) ((x) << S_SYSCLK_ROT_OVERRIDE)
71957 #define G_SYSCLK_ROT_OVERRIDE(x) (((x) >> S_SYSCLK_ROT_OVERRIDE) & M_SYSCLK_ROT_OVERRIDE)
71958 
71959 #define S_SYSCLK_ROT_OVERRIDE_EN    7
71960 #define V_SYSCLK_ROT_OVERRIDE_EN(x) ((x) << S_SYSCLK_ROT_OVERRIDE_EN)
71961 #define F_SYSCLK_ROT_OVERRIDE_EN    V_SYSCLK_ROT_OVERRIDE_EN(1U)
71962 
71963 #define S_SYSCLK_PHASE_ALIGN_RESE    6
71964 #define V_SYSCLK_PHASE_ALIGN_RESE(x) ((x) << S_SYSCLK_PHASE_ALIGN_RESE)
71965 #define F_SYSCLK_PHASE_ALIGN_RESE    V_SYSCLK_PHASE_ALIGN_RESE(1U)
71966 
71967 #define S_SYSCLK_PHASE_CNTL_EN    5
71968 #define V_SYSCLK_PHASE_CNTL_EN(x) ((x) << S_SYSCLK_PHASE_CNTL_EN)
71969 #define F_SYSCLK_PHASE_CNTL_EN    V_SYSCLK_PHASE_CNTL_EN(1U)
71970 
71971 #define S_SYSCLK_PHASE_DEFAULT_EN    4
71972 #define V_SYSCLK_PHASE_DEFAULT_EN(x) ((x) << S_SYSCLK_PHASE_DEFAULT_EN)
71973 #define F_SYSCLK_PHASE_DEFAULT_EN    V_SYSCLK_PHASE_DEFAULT_EN(1U)
71974 
71975 #define S_SYSCLK_POS_EDGE_ALIGN    3
71976 #define V_SYSCLK_POS_EDGE_ALIGN(x) ((x) << S_SYSCLK_POS_EDGE_ALIGN)
71977 #define F_SYSCLK_POS_EDGE_ALIGN    V_SYSCLK_POS_EDGE_ALIGN(1U)
71978 
71979 #define S_CONTINUOUS_UPDATE    2
71980 #define V_CONTINUOUS_UPDATE(x) ((x) << S_CONTINUOUS_UPDATE)
71981 #define F_CONTINUOUS_UPDATE    V_CONTINUOUS_UPDATE(1U)
71982 
71983 #define S_CE0DLTVCC    0
71984 #define M_CE0DLTVCC    0x3U
71985 #define V_CE0DLTVCC(x) ((x) << S_CE0DLTVCC)
71986 #define G_CE0DLTVCC(x) (((x) >> S_CE0DLTVCC) & M_CE0DLTVCC)
71987 
71988 #define A_MC_DDRPHY_AD32S_SYSCLK_CNTL_PR 0x460c8
71989 #define A_MC_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET 0x460cc
71990 
71991 #define S_TSYS_WRCLK    8
71992 #define M_TSYS_WRCLK    0x7fU
71993 #define V_TSYS_WRCLK(x) ((x) << S_TSYS_WRCLK)
71994 #define G_TSYS_WRCLK(x) (((x) >> S_TSYS_WRCLK) & M_TSYS_WRCLK)
71995 
71996 #define A_MC_DDRPHY_AD32S_MCCLK_WRCLK_PR_STATIC_OFFSET 0x460cc
71997 #define A_MC_DDRPHY_ADR_SYSCLK_PR_VALUE_RO 0x460d0
71998 
71999 #define S_SLEW_LATE_SAMPLE    15
72000 #define V_SLEW_LATE_SAMPLE(x) ((x) << S_SLEW_LATE_SAMPLE)
72001 #define F_SLEW_LATE_SAMPLE    V_SLEW_LATE_SAMPLE(1U)
72002 
72003 #define S_SYSCLK_ROT    8
72004 #define M_SYSCLK_ROT    0x7fU
72005 #define V_SYSCLK_ROT(x) ((x) << S_SYSCLK_ROT)
72006 #define G_SYSCLK_ROT(x) (((x) >> S_SYSCLK_ROT) & M_SYSCLK_ROT)
72007 
72008 #define S_BB_LOCK    7
72009 #define V_BB_LOCK(x) ((x) << S_BB_LOCK)
72010 #define F_BB_LOCK    V_BB_LOCK(1U)
72011 
72012 #define S_SLEW_EARLY_SAMPLE    6
72013 #define V_SLEW_EARLY_SAMPLE(x) ((x) << S_SLEW_EARLY_SAMPLE)
72014 #define F_SLEW_EARLY_SAMPLE    V_SLEW_EARLY_SAMPLE(1U)
72015 
72016 #define S_SLEW_DONE_STATUS    4
72017 #define M_SLEW_DONE_STATUS    0x3U
72018 #define V_SLEW_DONE_STATUS(x) ((x) << S_SLEW_DONE_STATUS)
72019 #define G_SLEW_DONE_STATUS(x) (((x) >> S_SLEW_DONE_STATUS) & M_SLEW_DONE_STATUS)
72020 
72021 #define S_SLEW_CNTL    0
72022 #define M_SLEW_CNTL    0xfU
72023 #define V_SLEW_CNTL(x) ((x) << S_SLEW_CNTL)
72024 #define G_SLEW_CNTL(x) (((x) >> S_SLEW_CNTL) & M_SLEW_CNTL)
72025 
72026 #define A_MC_DDRPHY_AD32S_SYSCLK_PR_VALUE_RO 0x460d0
72027 #define A_MC_DDRPHY_ADR_GMTEST_ATEST_CNTL 0x460d4
72028 
72029 #define S_FLUSH    15
72030 #define V_FLUSH(x) ((x) << S_FLUSH)
72031 #define F_FLUSH    V_FLUSH(1U)
72032 
72033 #define S_GIANT_MUX_TEST_EN    14
72034 #define V_GIANT_MUX_TEST_EN(x) ((x) << S_GIANT_MUX_TEST_EN)
72035 #define F_GIANT_MUX_TEST_EN    V_GIANT_MUX_TEST_EN(1U)
72036 
72037 #define S_GIANT_MUX_TEST_VAL    13
72038 #define V_GIANT_MUX_TEST_VAL(x) ((x) << S_GIANT_MUX_TEST_VAL)
72039 #define F_GIANT_MUX_TEST_VAL    V_GIANT_MUX_TEST_VAL(1U)
72040 
72041 #define S_HS_PROBE_A_SEL_    8
72042 #define M_HS_PROBE_A_SEL_    0xfU
72043 #define V_HS_PROBE_A_SEL_(x) ((x) << S_HS_PROBE_A_SEL_)
72044 #define G_HS_PROBE_A_SEL_(x) (((x) >> S_HS_PROBE_A_SEL_) & M_HS_PROBE_A_SEL_)
72045 
72046 #define S_HS_PROBE_B_SEL_    4
72047 #define M_HS_PROBE_B_SEL_    0xfU
72048 #define V_HS_PROBE_B_SEL_(x) ((x) << S_HS_PROBE_B_SEL_)
72049 #define G_HS_PROBE_B_SEL_(x) (((x) >> S_HS_PROBE_B_SEL_) & M_HS_PROBE_B_SEL_)
72050 
72051 #define S_ATEST1CTL0    3
72052 #define V_ATEST1CTL0(x) ((x) << S_ATEST1CTL0)
72053 #define F_ATEST1CTL0    V_ATEST1CTL0(1U)
72054 
72055 #define S_ATEST1CTL1    2
72056 #define V_ATEST1CTL1(x) ((x) << S_ATEST1CTL1)
72057 #define F_ATEST1CTL1    V_ATEST1CTL1(1U)
72058 
72059 #define S_ATEST1CTL2    1
72060 #define V_ATEST1CTL2(x) ((x) << S_ATEST1CTL2)
72061 #define F_ATEST1CTL2    V_ATEST1CTL2(1U)
72062 
72063 #define S_ATEST1CTL3    0
72064 #define V_ATEST1CTL3(x) ((x) << S_ATEST1CTL3)
72065 #define F_ATEST1CTL3    V_ATEST1CTL3(1U)
72066 
72067 #define A_MC_DDRPHY_AD32S_OUTPUT_FORCE_ATEST_CNTL 0x460d4
72068 
72069 #define S_FORCE_EN    14
72070 #define V_FORCE_EN(x) ((x) << S_FORCE_EN)
72071 #define F_FORCE_EN    V_FORCE_EN(1U)
72072 
72073 #define S_AD32S_HS_PROBE_A_SEL    8
72074 #define M_AD32S_HS_PROBE_A_SEL    0xfU
72075 #define V_AD32S_HS_PROBE_A_SEL(x) ((x) << S_AD32S_HS_PROBE_A_SEL)
72076 #define G_AD32S_HS_PROBE_A_SEL(x) (((x) >> S_AD32S_HS_PROBE_A_SEL) & M_AD32S_HS_PROBE_A_SEL)
72077 
72078 #define S_AD32S_HS_PROBE_B_SEL    4
72079 #define M_AD32S_HS_PROBE_B_SEL    0xfU
72080 #define V_AD32S_HS_PROBE_B_SEL(x) ((x) << S_AD32S_HS_PROBE_B_SEL)
72081 #define G_AD32S_HS_PROBE_B_SEL(x) (((x) >> S_AD32S_HS_PROBE_B_SEL) & M_AD32S_HS_PROBE_B_SEL)
72082 
72083 #define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A0 0x460d8
72084 
72085 #define S_GIANT_MUX_TEST_RESULTS    0
72086 #define M_GIANT_MUX_TEST_RESULTS    0xffffU
72087 #define V_GIANT_MUX_TEST_RESULTS(x) ((x) << S_GIANT_MUX_TEST_RESULTS)
72088 #define G_GIANT_MUX_TEST_RESULTS(x) (((x) >> S_GIANT_MUX_TEST_RESULTS) & M_GIANT_MUX_TEST_RESULTS)
72089 
72090 #define A_MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE0 0x460d8
72091 
72092 #define S_OUTPUT_DRIVER_FORCE_VALUE    0
72093 #define M_OUTPUT_DRIVER_FORCE_VALUE    0xffffU
72094 #define V_OUTPUT_DRIVER_FORCE_VALUE(x) ((x) << S_OUTPUT_DRIVER_FORCE_VALUE)
72095 #define G_OUTPUT_DRIVER_FORCE_VALUE(x) (((x) >> S_OUTPUT_DRIVER_FORCE_VALUE) & M_OUTPUT_DRIVER_FORCE_VALUE)
72096 
72097 #define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A1 0x460dc
72098 #define A_MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE1 0x460dc
72099 #define A_MC_DDRPHY_ADR_POWERDOWN_1 0x460e0
72100 
72101 #define S_MASTER_PD_CNTL    15
72102 #define V_MASTER_PD_CNTL(x) ((x) << S_MASTER_PD_CNTL)
72103 #define F_MASTER_PD_CNTL    V_MASTER_PD_CNTL(1U)
72104 
72105 #define S_ANALOG_INPUT_STAB2    14
72106 #define V_ANALOG_INPUT_STAB2(x) ((x) << S_ANALOG_INPUT_STAB2)
72107 #define F_ANALOG_INPUT_STAB2    V_ANALOG_INPUT_STAB2(1U)
72108 
72109 #define S_ANALOG_INPUT_STAB1    8
72110 #define V_ANALOG_INPUT_STAB1(x) ((x) << S_ANALOG_INPUT_STAB1)
72111 #define F_ANALOG_INPUT_STAB1    V_ANALOG_INPUT_STAB1(1U)
72112 
72113 #define S_SYSCLK_CLK_GATE    6
72114 #define M_SYSCLK_CLK_GATE    0x3U
72115 #define V_SYSCLK_CLK_GATE(x) ((x) << S_SYSCLK_CLK_GATE)
72116 #define G_SYSCLK_CLK_GATE(x) (((x) >> S_SYSCLK_CLK_GATE) & M_SYSCLK_CLK_GATE)
72117 
72118 #define S_WR_FIFO_STAB    5
72119 #define V_WR_FIFO_STAB(x) ((x) << S_WR_FIFO_STAB)
72120 #define F_WR_FIFO_STAB    V_WR_FIFO_STAB(1U)
72121 
72122 #define S_ADR_RX_PD    4
72123 #define V_ADR_RX_PD(x) ((x) << S_ADR_RX_PD)
72124 #define F_ADR_RX_PD    V_ADR_RX_PD(1U)
72125 
72126 #define S_TX_TRISTATE_CNTL    1
72127 #define V_TX_TRISTATE_CNTL(x) ((x) << S_TX_TRISTATE_CNTL)
72128 #define F_TX_TRISTATE_CNTL    V_TX_TRISTATE_CNTL(1U)
72129 
72130 #define S_DVCC_REG_PD    0
72131 #define V_DVCC_REG_PD(x) ((x) << S_DVCC_REG_PD)
72132 #define F_DVCC_REG_PD    V_DVCC_REG_PD(1U)
72133 
72134 #define A_MC_DDRPHY_AD32S_POWERDOWN_1 0x460e0
72135 #define A_MC_DDRPHY_ADR_SLEW_CAL_CNTL 0x460e4
72136 
72137 #define S_SLEW_CAL_ENABLE    15
72138 #define V_SLEW_CAL_ENABLE(x) ((x) << S_SLEW_CAL_ENABLE)
72139 #define F_SLEW_CAL_ENABLE    V_SLEW_CAL_ENABLE(1U)
72140 
72141 #define S_SLEW_CAL_START    14
72142 #define V_SLEW_CAL_START(x) ((x) << S_SLEW_CAL_START)
72143 #define F_SLEW_CAL_START    V_SLEW_CAL_START(1U)
72144 
72145 #define S_SLEW_CAL_OVERRIDE_EN    12
72146 #define V_SLEW_CAL_OVERRIDE_EN(x) ((x) << S_SLEW_CAL_OVERRIDE_EN)
72147 #define F_SLEW_CAL_OVERRIDE_EN    V_SLEW_CAL_OVERRIDE_EN(1U)
72148 
72149 #define S_SLEW_CAL_OVERRIDE    8
72150 #define M_SLEW_CAL_OVERRIDE    0xfU
72151 #define V_SLEW_CAL_OVERRIDE(x) ((x) << S_SLEW_CAL_OVERRIDE)
72152 #define G_SLEW_CAL_OVERRIDE(x) (((x) >> S_SLEW_CAL_OVERRIDE) & M_SLEW_CAL_OVERRIDE)
72153 
72154 #define S_SLEW_TARGET_PR_OFFSET    0
72155 #define M_SLEW_TARGET_PR_OFFSET    0x1fU
72156 #define V_SLEW_TARGET_PR_OFFSET(x) ((x) << S_SLEW_TARGET_PR_OFFSET)
72157 #define G_SLEW_TARGET_PR_OFFSET(x) (((x) >> S_SLEW_TARGET_PR_OFFSET) & M_SLEW_TARGET_PR_OFFSET)
72158 
72159 #define A_MC_DDRPHY_AD32S_SLEW_CAL_CNTL 0x460e4
72160 #define A_MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS 0x47000
72161 
72162 #define S_DP18_PLL_LOCK    1
72163 #define M_DP18_PLL_LOCK    0x7fffU
72164 #define V_DP18_PLL_LOCK(x) ((x) << S_DP18_PLL_LOCK)
72165 #define G_DP18_PLL_LOCK(x) (((x) >> S_DP18_PLL_LOCK) & M_DP18_PLL_LOCK)
72166 
72167 #define A_MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS 0x47004
72168 
72169 #define S_AD32S_PLL_LOCK    14
72170 #define M_AD32S_PLL_LOCK    0x3U
72171 #define V_AD32S_PLL_LOCK(x) ((x) << S_AD32S_PLL_LOCK)
72172 #define G_AD32S_PLL_LOCK(x) (((x) >> S_AD32S_PLL_LOCK) & M_AD32S_PLL_LOCK)
72173 
72174 #define A_MC_DDRPHY_PC_RANK_PAIR0 0x47008
72175 
72176 #define S_RANK_PAIR0_PRI    13
72177 #define M_RANK_PAIR0_PRI    0x7U
72178 #define V_RANK_PAIR0_PRI(x) ((x) << S_RANK_PAIR0_PRI)
72179 #define G_RANK_PAIR0_PRI(x) (((x) >> S_RANK_PAIR0_PRI) & M_RANK_PAIR0_PRI)
72180 
72181 #define S_RANK_PAIR0_PRI_V    12
72182 #define V_RANK_PAIR0_PRI_V(x) ((x) << S_RANK_PAIR0_PRI_V)
72183 #define F_RANK_PAIR0_PRI_V    V_RANK_PAIR0_PRI_V(1U)
72184 
72185 #define S_RANK_PAIR0_SEC    9
72186 #define M_RANK_PAIR0_SEC    0x7U
72187 #define V_RANK_PAIR0_SEC(x) ((x) << S_RANK_PAIR0_SEC)
72188 #define G_RANK_PAIR0_SEC(x) (((x) >> S_RANK_PAIR0_SEC) & M_RANK_PAIR0_SEC)
72189 
72190 #define S_RANK_PAIR0_SEC_V    8
72191 #define V_RANK_PAIR0_SEC_V(x) ((x) << S_RANK_PAIR0_SEC_V)
72192 #define F_RANK_PAIR0_SEC_V    V_RANK_PAIR0_SEC_V(1U)
72193 
72194 #define S_RANK_PAIR1_PRI    5
72195 #define M_RANK_PAIR1_PRI    0x7U
72196 #define V_RANK_PAIR1_PRI(x) ((x) << S_RANK_PAIR1_PRI)
72197 #define G_RANK_PAIR1_PRI(x) (((x) >> S_RANK_PAIR1_PRI) & M_RANK_PAIR1_PRI)
72198 
72199 #define S_RANK_PAIR1_PRI_V    4
72200 #define V_RANK_PAIR1_PRI_V(x) ((x) << S_RANK_PAIR1_PRI_V)
72201 #define F_RANK_PAIR1_PRI_V    V_RANK_PAIR1_PRI_V(1U)
72202 
72203 #define S_RANK_PAIR1_SEC    1
72204 #define M_RANK_PAIR1_SEC    0x7U
72205 #define V_RANK_PAIR1_SEC(x) ((x) << S_RANK_PAIR1_SEC)
72206 #define G_RANK_PAIR1_SEC(x) (((x) >> S_RANK_PAIR1_SEC) & M_RANK_PAIR1_SEC)
72207 
72208 #define S_RANK_PAIR1_SEC_V    0
72209 #define V_RANK_PAIR1_SEC_V(x) ((x) << S_RANK_PAIR1_SEC_V)
72210 #define F_RANK_PAIR1_SEC_V    V_RANK_PAIR1_SEC_V(1U)
72211 
72212 #define A_MC_DDRPHY_PC_RANK_PAIR1 0x4700c
72213 
72214 #define S_RANK_PAIR2_PRI    13
72215 #define M_RANK_PAIR2_PRI    0x7U
72216 #define V_RANK_PAIR2_PRI(x) ((x) << S_RANK_PAIR2_PRI)
72217 #define G_RANK_PAIR2_PRI(x) (((x) >> S_RANK_PAIR2_PRI) & M_RANK_PAIR2_PRI)
72218 
72219 #define S_RANK_PAIR2_PRI_V    12
72220 #define V_RANK_PAIR2_PRI_V(x) ((x) << S_RANK_PAIR2_PRI_V)
72221 #define F_RANK_PAIR2_PRI_V    V_RANK_PAIR2_PRI_V(1U)
72222 
72223 #define S_RANK_PAIR2_SEC    9
72224 #define M_RANK_PAIR2_SEC    0x7U
72225 #define V_RANK_PAIR2_SEC(x) ((x) << S_RANK_PAIR2_SEC)
72226 #define G_RANK_PAIR2_SEC(x) (((x) >> S_RANK_PAIR2_SEC) & M_RANK_PAIR2_SEC)
72227 
72228 #define S_RANK_PAIR2_SEC_V    8
72229 #define V_RANK_PAIR2_SEC_V(x) ((x) << S_RANK_PAIR2_SEC_V)
72230 #define F_RANK_PAIR2_SEC_V    V_RANK_PAIR2_SEC_V(1U)
72231 
72232 #define S_RANK_PAIR3_PRI    5
72233 #define M_RANK_PAIR3_PRI    0x7U
72234 #define V_RANK_PAIR3_PRI(x) ((x) << S_RANK_PAIR3_PRI)
72235 #define G_RANK_PAIR3_PRI(x) (((x) >> S_RANK_PAIR3_PRI) & M_RANK_PAIR3_PRI)
72236 
72237 #define S_RANK_PAIR3_PRI_V    4
72238 #define V_RANK_PAIR3_PRI_V(x) ((x) << S_RANK_PAIR3_PRI_V)
72239 #define F_RANK_PAIR3_PRI_V    V_RANK_PAIR3_PRI_V(1U)
72240 
72241 #define S_RANK_PAIR3_SEC    1
72242 #define M_RANK_PAIR3_SEC    0x7U
72243 #define V_RANK_PAIR3_SEC(x) ((x) << S_RANK_PAIR3_SEC)
72244 #define G_RANK_PAIR3_SEC(x) (((x) >> S_RANK_PAIR3_SEC) & M_RANK_PAIR3_SEC)
72245 
72246 #define S_RANK_PAIR3_SEC_V    0
72247 #define V_RANK_PAIR3_SEC_V(x) ((x) << S_RANK_PAIR3_SEC_V)
72248 #define F_RANK_PAIR3_SEC_V    V_RANK_PAIR3_SEC_V(1U)
72249 
72250 #define A_MC_DDRPHY_PC_BASE_CNTR0 0x47010
72251 
72252 #define S_PERIODIC_BASE_CNTR0    0
72253 #define M_PERIODIC_BASE_CNTR0    0xffffU
72254 #define V_PERIODIC_BASE_CNTR0(x) ((x) << S_PERIODIC_BASE_CNTR0)
72255 #define G_PERIODIC_BASE_CNTR0(x) (((x) >> S_PERIODIC_BASE_CNTR0) & M_PERIODIC_BASE_CNTR0)
72256 
72257 #define A_MC_DDRPHY_PC_RELOAD_VALUE0 0x47014
72258 
72259 #define S_PERIODIC_CAL_REQ_EN    15
72260 #define V_PERIODIC_CAL_REQ_EN(x) ((x) << S_PERIODIC_CAL_REQ_EN)
72261 #define F_PERIODIC_CAL_REQ_EN    V_PERIODIC_CAL_REQ_EN(1U)
72262 
72263 #define S_PERIODIC_RELOAD_VALUE0    0
72264 #define M_PERIODIC_RELOAD_VALUE0    0x7fffU
72265 #define V_PERIODIC_RELOAD_VALUE0(x) ((x) << S_PERIODIC_RELOAD_VALUE0)
72266 #define G_PERIODIC_RELOAD_VALUE0(x) (((x) >> S_PERIODIC_RELOAD_VALUE0) & M_PERIODIC_RELOAD_VALUE0)
72267 
72268 #define A_MC_DDRPHY_PC_BASE_CNTR1 0x47018
72269 
72270 #define S_PERIODIC_BASE_CNTR1    0
72271 #define M_PERIODIC_BASE_CNTR1    0xffffU
72272 #define V_PERIODIC_BASE_CNTR1(x) ((x) << S_PERIODIC_BASE_CNTR1)
72273 #define G_PERIODIC_BASE_CNTR1(x) (((x) >> S_PERIODIC_BASE_CNTR1) & M_PERIODIC_BASE_CNTR1)
72274 
72275 #define A_MC_DDRPHY_PC_CAL_TIMER 0x4701c
72276 
72277 #define S_PERIODIC_CAL_TIMER    0
72278 #define M_PERIODIC_CAL_TIMER    0xffffU
72279 #define V_PERIODIC_CAL_TIMER(x) ((x) << S_PERIODIC_CAL_TIMER)
72280 #define G_PERIODIC_CAL_TIMER(x) (((x) >> S_PERIODIC_CAL_TIMER) & M_PERIODIC_CAL_TIMER)
72281 
72282 #define A_MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE 0x47020
72283 
72284 #define S_PERIODIC_TIMER_RELOAD_VALUE    0
72285 #define M_PERIODIC_TIMER_RELOAD_VALUE    0xffffU
72286 #define V_PERIODIC_TIMER_RELOAD_VALUE(x) ((x) << S_PERIODIC_TIMER_RELOAD_VALUE)
72287 #define G_PERIODIC_TIMER_RELOAD_VALUE(x) (((x) >> S_PERIODIC_TIMER_RELOAD_VALUE) & M_PERIODIC_TIMER_RELOAD_VALUE)
72288 
72289 #define A_MC_DDRPHY_PC_ZCAL_TIMER 0x47024
72290 
72291 #define S_PERIODIC_ZCAL_TIMER    0
72292 #define M_PERIODIC_ZCAL_TIMER    0xffffU
72293 #define V_PERIODIC_ZCAL_TIMER(x) ((x) << S_PERIODIC_ZCAL_TIMER)
72294 #define G_PERIODIC_ZCAL_TIMER(x) (((x) >> S_PERIODIC_ZCAL_TIMER) & M_PERIODIC_ZCAL_TIMER)
72295 
72296 #define A_MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE 0x47028
72297 #define A_MC_DDRPHY_PC_PER_CAL_CONFIG 0x4702c
72298 
72299 #define S_PER_ENA_RANK_PAIR    12
72300 #define M_PER_ENA_RANK_PAIR    0xfU
72301 #define V_PER_ENA_RANK_PAIR(x) ((x) << S_PER_ENA_RANK_PAIR)
72302 #define G_PER_ENA_RANK_PAIR(x) (((x) >> S_PER_ENA_RANK_PAIR) & M_PER_ENA_RANK_PAIR)
72303 
72304 #define S_PER_ENA_ZCAL    11
72305 #define V_PER_ENA_ZCAL(x) ((x) << S_PER_ENA_ZCAL)
72306 #define F_PER_ENA_ZCAL    V_PER_ENA_ZCAL(1U)
72307 
72308 #define S_PER_ENA_SYSCLK_ALIGN    10
72309 #define V_PER_ENA_SYSCLK_ALIGN(x) ((x) << S_PER_ENA_SYSCLK_ALIGN)
72310 #define F_PER_ENA_SYSCLK_ALIGN    V_PER_ENA_SYSCLK_ALIGN(1U)
72311 
72312 #define S_ENA_PER_READ_CTR    9
72313 #define V_ENA_PER_READ_CTR(x) ((x) << S_ENA_PER_READ_CTR)
72314 #define F_ENA_PER_READ_CTR    V_ENA_PER_READ_CTR(1U)
72315 
72316 #define S_ENA_PER_RDCLK_ALIGN    8
72317 #define V_ENA_PER_RDCLK_ALIGN(x) ((x) << S_ENA_PER_RDCLK_ALIGN)
72318 #define F_ENA_PER_RDCLK_ALIGN    V_ENA_PER_RDCLK_ALIGN(1U)
72319 
72320 #define S_ENA_PER_DQS_ALIGN    7
72321 #define V_ENA_PER_DQS_ALIGN(x) ((x) << S_ENA_PER_DQS_ALIGN)
72322 #define F_ENA_PER_DQS_ALIGN    V_ENA_PER_DQS_ALIGN(1U)
72323 
72324 #define S_PER_NEXT_RANK_PAIR    5
72325 #define M_PER_NEXT_RANK_PAIR    0x3U
72326 #define V_PER_NEXT_RANK_PAIR(x) ((x) << S_PER_NEXT_RANK_PAIR)
72327 #define G_PER_NEXT_RANK_PAIR(x) (((x) >> S_PER_NEXT_RANK_PAIR) & M_PER_NEXT_RANK_PAIR)
72328 
72329 #define S_FAST_SIM_PER_CNTR    4
72330 #define V_FAST_SIM_PER_CNTR(x) ((x) << S_FAST_SIM_PER_CNTR)
72331 #define F_FAST_SIM_PER_CNTR    V_FAST_SIM_PER_CNTR(1U)
72332 
72333 #define S_START_INIT_CAL    3
72334 #define V_START_INIT_CAL(x) ((x) << S_START_INIT_CAL)
72335 #define F_START_INIT_CAL    V_START_INIT_CAL(1U)
72336 
72337 #define S_START_PER_CAL    2
72338 #define V_START_PER_CAL(x) ((x) << S_START_PER_CAL)
72339 #define F_START_PER_CAL    V_START_PER_CAL(1U)
72340 
72341 #define S_ABORT_ON_ERR_EN    1
72342 #define V_ABORT_ON_ERR_EN(x) ((x) << S_ABORT_ON_ERR_EN)
72343 #define F_ABORT_ON_ERR_EN    V_ABORT_ON_ERR_EN(1U)
72344 
72345 #define S_ENA_PER_RD_CTR    9
72346 #define V_ENA_PER_RD_CTR(x) ((x) << S_ENA_PER_RD_CTR)
72347 #define F_ENA_PER_RD_CTR    V_ENA_PER_RD_CTR(1U)
72348 
72349 #define A_MC_DDRPHY_PC_CONFIG0 0x47030
72350 
72351 #define S_PROTOCOL_DDR    12
72352 #define M_PROTOCOL_DDR    0xfU
72353 #define V_PROTOCOL_DDR(x) ((x) << S_PROTOCOL_DDR)
72354 #define G_PROTOCOL_DDR(x) (((x) >> S_PROTOCOL_DDR) & M_PROTOCOL_DDR)
72355 
72356 #define S_DATA_MUX4_1MODE    11
72357 #define V_DATA_MUX4_1MODE(x) ((x) << S_DATA_MUX4_1MODE)
72358 #define F_DATA_MUX4_1MODE    V_DATA_MUX4_1MODE(1U)
72359 
72360 #define S_DDR4_CMD_SIG_REDUCTION    9
72361 #define V_DDR4_CMD_SIG_REDUCTION(x) ((x) << S_DDR4_CMD_SIG_REDUCTION)
72362 #define F_DDR4_CMD_SIG_REDUCTION    V_DDR4_CMD_SIG_REDUCTION(1U)
72363 
72364 #define S_SYSCLK_2X_MEMINTCLKO    8
72365 #define V_SYSCLK_2X_MEMINTCLKO(x) ((x) << S_SYSCLK_2X_MEMINTCLKO)
72366 #define F_SYSCLK_2X_MEMINTCLKO    V_SYSCLK_2X_MEMINTCLKO(1U)
72367 
72368 #define S_RANK_OVERRIDE    7
72369 #define V_RANK_OVERRIDE(x) ((x) << S_RANK_OVERRIDE)
72370 #define F_RANK_OVERRIDE    V_RANK_OVERRIDE(1U)
72371 
72372 #define S_RANK_OVERRIDE_VALUE    4
72373 #define M_RANK_OVERRIDE_VALUE    0x7U
72374 #define V_RANK_OVERRIDE_VALUE(x) ((x) << S_RANK_OVERRIDE_VALUE)
72375 #define G_RANK_OVERRIDE_VALUE(x) (((x) >> S_RANK_OVERRIDE_VALUE) & M_RANK_OVERRIDE_VALUE)
72376 
72377 #define S_LOW_LATENCY    3
72378 #define V_LOW_LATENCY(x) ((x) << S_LOW_LATENCY)
72379 #define F_LOW_LATENCY    V_LOW_LATENCY(1U)
72380 
72381 #define S_DDR4_BANK_REFRESH    2
72382 #define V_DDR4_BANK_REFRESH(x) ((x) << S_DDR4_BANK_REFRESH)
72383 #define F_DDR4_BANK_REFRESH    V_DDR4_BANK_REFRESH(1U)
72384 
72385 #define S_DDR4_VLEVEL_BANK_GROUP    1
72386 #define V_DDR4_VLEVEL_BANK_GROUP(x) ((x) << S_DDR4_VLEVEL_BANK_GROUP)
72387 #define F_DDR4_VLEVEL_BANK_GROUP    V_DDR4_VLEVEL_BANK_GROUP(1U)
72388 
72389 #define S_DDRPHY_PROTOCOL    12
72390 #define M_DDRPHY_PROTOCOL    0xfU
72391 #define V_DDRPHY_PROTOCOL(x) ((x) << S_DDRPHY_PROTOCOL)
72392 #define G_DDRPHY_PROTOCOL(x) (((x) >> S_DDRPHY_PROTOCOL) & M_DDRPHY_PROTOCOL)
72393 
72394 #define S_SPAM_EN    10
72395 #define V_SPAM_EN(x) ((x) << S_SPAM_EN)
72396 #define F_SPAM_EN    V_SPAM_EN(1U)
72397 
72398 #define S_DDR4_IPW_LOOP_DIS    2
72399 #define V_DDR4_IPW_LOOP_DIS(x) ((x) << S_DDR4_IPW_LOOP_DIS)
72400 #define F_DDR4_IPW_LOOP_DIS    V_DDR4_IPW_LOOP_DIS(1U)
72401 
72402 #define A_MC_DDRPHY_PC_CONFIG1 0x47034
72403 
72404 #define S_WRITE_LATENCY_OFFSET    12
72405 #define M_WRITE_LATENCY_OFFSET    0xfU
72406 #define V_WRITE_LATENCY_OFFSET(x) ((x) << S_WRITE_LATENCY_OFFSET)
72407 #define G_WRITE_LATENCY_OFFSET(x) (((x) >> S_WRITE_LATENCY_OFFSET) & M_WRITE_LATENCY_OFFSET)
72408 
72409 #define S_READ_LATENCY_OFFSET    8
72410 #define M_READ_LATENCY_OFFSET    0xfU
72411 #define V_READ_LATENCY_OFFSET(x) ((x) << S_READ_LATENCY_OFFSET)
72412 #define G_READ_LATENCY_OFFSET(x) (((x) >> S_READ_LATENCY_OFFSET) & M_READ_LATENCY_OFFSET)
72413 
72414 #define S_MEMCTL_CIC_FAST    7
72415 #define V_MEMCTL_CIC_FAST(x) ((x) << S_MEMCTL_CIC_FAST)
72416 #define F_MEMCTL_CIC_FAST    V_MEMCTL_CIC_FAST(1U)
72417 
72418 #define S_MEMCTL_CTRN_IGNORE    6
72419 #define V_MEMCTL_CTRN_IGNORE(x) ((x) << S_MEMCTL_CTRN_IGNORE)
72420 #define F_MEMCTL_CTRN_IGNORE    V_MEMCTL_CTRN_IGNORE(1U)
72421 
72422 #define S_DISABLE_MEMCTL_CAL    5
72423 #define V_DISABLE_MEMCTL_CAL(x) ((x) << S_DISABLE_MEMCTL_CAL)
72424 #define F_DISABLE_MEMCTL_CAL    V_DISABLE_MEMCTL_CAL(1U)
72425 
72426 #define S_MEMCTL_CIS_IGNORE    6
72427 #define V_MEMCTL_CIS_IGNORE(x) ((x) << S_MEMCTL_CIS_IGNORE)
72428 #define F_MEMCTL_CIS_IGNORE    V_MEMCTL_CIS_IGNORE(1U)
72429 
72430 #define S_MEMORY_TYPE    2
72431 #define M_MEMORY_TYPE    0x7U
72432 #define V_MEMORY_TYPE(x) ((x) << S_MEMORY_TYPE)
72433 #define G_MEMORY_TYPE(x) (((x) >> S_MEMORY_TYPE) & M_MEMORY_TYPE)
72434 
72435 #define S_DDR4_PDA_MODE    1
72436 #define V_DDR4_PDA_MODE(x) ((x) << S_DDR4_PDA_MODE)
72437 #define F_DDR4_PDA_MODE    V_DDR4_PDA_MODE(1U)
72438 
72439 #define A_MC_DDRPHY_PC_RESETS 0x47038
72440 
72441 #define S_PLL_RESET    15
72442 #define V_PLL_RESET(x) ((x) << S_PLL_RESET)
72443 #define F_PLL_RESET    V_PLL_RESET(1U)
72444 
72445 #define S_SYSCLK_RESET    14
72446 #define V_SYSCLK_RESET(x) ((x) << S_SYSCLK_RESET)
72447 #define F_SYSCLK_RESET    V_SYSCLK_RESET(1U)
72448 
72449 #define A_MC_DDRPHY_PC_PER_ZCAL_CONFIG 0x4703c
72450 
72451 #define S_PER_ZCAL_ENA_RANK    8
72452 #define M_PER_ZCAL_ENA_RANK    0xffU
72453 #define V_PER_ZCAL_ENA_RANK(x) ((x) << S_PER_ZCAL_ENA_RANK)
72454 #define G_PER_ZCAL_ENA_RANK(x) (((x) >> S_PER_ZCAL_ENA_RANK) & M_PER_ZCAL_ENA_RANK)
72455 
72456 #define S_PER_ZCAL_NEXT_RANK    5
72457 #define M_PER_ZCAL_NEXT_RANK    0x7U
72458 #define V_PER_ZCAL_NEXT_RANK(x) ((x) << S_PER_ZCAL_NEXT_RANK)
72459 #define G_PER_ZCAL_NEXT_RANK(x) (((x) >> S_PER_ZCAL_NEXT_RANK) & M_PER_ZCAL_NEXT_RANK)
72460 
72461 #define S_START_PER_ZCAL    4
72462 #define V_START_PER_ZCAL(x) ((x) << S_START_PER_ZCAL)
72463 #define F_START_PER_ZCAL    V_START_PER_ZCAL(1U)
72464 
72465 #define A_MC_DDRPHY_PC_RANK_GROUP 0x47044
72466 
72467 #define S_ADDR_MIRROR_RP0_PRI    15
72468 #define V_ADDR_MIRROR_RP0_PRI(x) ((x) << S_ADDR_MIRROR_RP0_PRI)
72469 #define F_ADDR_MIRROR_RP0_PRI    V_ADDR_MIRROR_RP0_PRI(1U)
72470 
72471 #define S_ADDR_MIRROR_RP0_SEC    14
72472 #define V_ADDR_MIRROR_RP0_SEC(x) ((x) << S_ADDR_MIRROR_RP0_SEC)
72473 #define F_ADDR_MIRROR_RP0_SEC    V_ADDR_MIRROR_RP0_SEC(1U)
72474 
72475 #define S_ADDR_MIRROR_RP1_PRI    13
72476 #define V_ADDR_MIRROR_RP1_PRI(x) ((x) << S_ADDR_MIRROR_RP1_PRI)
72477 #define F_ADDR_MIRROR_RP1_PRI    V_ADDR_MIRROR_RP1_PRI(1U)
72478 
72479 #define S_ADDR_MIRROR_RP1_SEC    12
72480 #define V_ADDR_MIRROR_RP1_SEC(x) ((x) << S_ADDR_MIRROR_RP1_SEC)
72481 #define F_ADDR_MIRROR_RP1_SEC    V_ADDR_MIRROR_RP1_SEC(1U)
72482 
72483 #define S_ADDR_MIRROR_RP2_PRI    11
72484 #define V_ADDR_MIRROR_RP2_PRI(x) ((x) << S_ADDR_MIRROR_RP2_PRI)
72485 #define F_ADDR_MIRROR_RP2_PRI    V_ADDR_MIRROR_RP2_PRI(1U)
72486 
72487 #define S_ADDR_MIRROR_RP2_SEC    10
72488 #define V_ADDR_MIRROR_RP2_SEC(x) ((x) << S_ADDR_MIRROR_RP2_SEC)
72489 #define F_ADDR_MIRROR_RP2_SEC    V_ADDR_MIRROR_RP2_SEC(1U)
72490 
72491 #define S_ADDR_MIRROR_RP3_PRI    9
72492 #define V_ADDR_MIRROR_RP3_PRI(x) ((x) << S_ADDR_MIRROR_RP3_PRI)
72493 #define F_ADDR_MIRROR_RP3_PRI    V_ADDR_MIRROR_RP3_PRI(1U)
72494 
72495 #define S_ADDR_MIRROR_RP3_SEC    8
72496 #define V_ADDR_MIRROR_RP3_SEC(x) ((x) << S_ADDR_MIRROR_RP3_SEC)
72497 #define F_ADDR_MIRROR_RP3_SEC    V_ADDR_MIRROR_RP3_SEC(1U)
72498 
72499 #define S_RANK_GROUPING    6
72500 #define M_RANK_GROUPING    0x3U
72501 #define V_RANK_GROUPING(x) ((x) << S_RANK_GROUPING)
72502 #define G_RANK_GROUPING(x) (((x) >> S_RANK_GROUPING) & M_RANK_GROUPING)
72503 
72504 #define S_ADDR_MIRROR_A3_A4    5
72505 #define V_ADDR_MIRROR_A3_A4(x) ((x) << S_ADDR_MIRROR_A3_A4)
72506 #define F_ADDR_MIRROR_A3_A4    V_ADDR_MIRROR_A3_A4(1U)
72507 
72508 #define S_ADDR_MIRROR_A5_A6    4
72509 #define V_ADDR_MIRROR_A5_A6(x) ((x) << S_ADDR_MIRROR_A5_A6)
72510 #define F_ADDR_MIRROR_A5_A6    V_ADDR_MIRROR_A5_A6(1U)
72511 
72512 #define S_ADDR_MIRROR_A7_A8    3
72513 #define V_ADDR_MIRROR_A7_A8(x) ((x) << S_ADDR_MIRROR_A7_A8)
72514 #define F_ADDR_MIRROR_A7_A8    V_ADDR_MIRROR_A7_A8(1U)
72515 
72516 #define S_ADDR_MIRROR_A11_A13    2
72517 #define V_ADDR_MIRROR_A11_A13(x) ((x) << S_ADDR_MIRROR_A11_A13)
72518 #define F_ADDR_MIRROR_A11_A13    V_ADDR_MIRROR_A11_A13(1U)
72519 
72520 #define S_ADDR_MIRROR_BA0_BA1    1
72521 #define V_ADDR_MIRROR_BA0_BA1(x) ((x) << S_ADDR_MIRROR_BA0_BA1)
72522 #define F_ADDR_MIRROR_BA0_BA1    V_ADDR_MIRROR_BA0_BA1(1U)
72523 
72524 #define S_ADDR_MIRROR_BG0_BG1    0
72525 #define V_ADDR_MIRROR_BG0_BG1(x) ((x) << S_ADDR_MIRROR_BG0_BG1)
72526 #define F_ADDR_MIRROR_BG0_BG1    V_ADDR_MIRROR_BG0_BG1(1U)
72527 
72528 #define A_MC_DDRPHY_PC_ERROR_STATUS0 0x47048
72529 
72530 #define S_RC_ERROR    15
72531 #define V_RC_ERROR(x) ((x) << S_RC_ERROR)
72532 #define F_RC_ERROR    V_RC_ERROR(1U)
72533 
72534 #define S_WC_ERROR    14
72535 #define V_WC_ERROR(x) ((x) << S_WC_ERROR)
72536 #define F_WC_ERROR    V_WC_ERROR(1U)
72537 
72538 #define S_SEQ_ERROR    13
72539 #define V_SEQ_ERROR(x) ((x) << S_SEQ_ERROR)
72540 #define F_SEQ_ERROR    V_SEQ_ERROR(1U)
72541 
72542 #define S_CC_ERROR    12
72543 #define V_CC_ERROR(x) ((x) << S_CC_ERROR)
72544 #define F_CC_ERROR    V_CC_ERROR(1U)
72545 
72546 #define S_APB_ERROR    11
72547 #define V_APB_ERROR(x) ((x) << S_APB_ERROR)
72548 #define F_APB_ERROR    V_APB_ERROR(1U)
72549 
72550 #define S_PC_ERROR    10
72551 #define V_PC_ERROR(x) ((x) << S_PC_ERROR)
72552 #define F_PC_ERROR    V_PC_ERROR(1U)
72553 
72554 #define A_MC_DDRPHY_PC_ERROR_MASK0 0x4704c
72555 
72556 #define S_RC_ERROR_MASK    15
72557 #define V_RC_ERROR_MASK(x) ((x) << S_RC_ERROR_MASK)
72558 #define F_RC_ERROR_MASK    V_RC_ERROR_MASK(1U)
72559 
72560 #define S_WC_ERROR_MASK    14
72561 #define V_WC_ERROR_MASK(x) ((x) << S_WC_ERROR_MASK)
72562 #define F_WC_ERROR_MASK    V_WC_ERROR_MASK(1U)
72563 
72564 #define S_SEQ_ERROR_MASK    13
72565 #define V_SEQ_ERROR_MASK(x) ((x) << S_SEQ_ERROR_MASK)
72566 #define F_SEQ_ERROR_MASK    V_SEQ_ERROR_MASK(1U)
72567 
72568 #define S_CC_ERROR_MASK    12
72569 #define V_CC_ERROR_MASK(x) ((x) << S_CC_ERROR_MASK)
72570 #define F_CC_ERROR_MASK    V_CC_ERROR_MASK(1U)
72571 
72572 #define S_APB_ERROR_MASK    11
72573 #define V_APB_ERROR_MASK(x) ((x) << S_APB_ERROR_MASK)
72574 #define F_APB_ERROR_MASK    V_APB_ERROR_MASK(1U)
72575 
72576 #define S_PC_ERROR_MASK    10
72577 #define V_PC_ERROR_MASK(x) ((x) << S_PC_ERROR_MASK)
72578 #define F_PC_ERROR_MASK    V_PC_ERROR_MASK(1U)
72579 
72580 #define A_MC_DDRPHY_PC_IO_PVT_FET_CONTROL 0x47050
72581 
72582 #define S_PVTP    11
72583 #define M_PVTP    0x1fU
72584 #define V_PVTP(x) ((x) << S_PVTP)
72585 #define G_PVTP(x) (((x) >> S_PVTP) & M_PVTP)
72586 
72587 #define S_PVTN    6
72588 #define M_PVTN    0x1fU
72589 #define V_PVTN(x) ((x) << S_PVTN)
72590 #define G_PVTN(x) (((x) >> S_PVTN) & M_PVTN)
72591 
72592 #define S_PVT_OVERRIDE    5
72593 #define V_PVT_OVERRIDE(x) ((x) << S_PVT_OVERRIDE)
72594 #define F_PVT_OVERRIDE    V_PVT_OVERRIDE(1U)
72595 
72596 #define S_ENABLE_ZCAL    4
72597 #define V_ENABLE_ZCAL(x) ((x) << S_ENABLE_ZCAL)
72598 #define F_ENABLE_ZCAL    V_ENABLE_ZCAL(1U)
72599 
72600 #define A_MC_DDRPHY_PC_VREF_DRV_CONTROL 0x47054
72601 
72602 #define S_VREFDQ0DSGN    15
72603 #define V_VREFDQ0DSGN(x) ((x) << S_VREFDQ0DSGN)
72604 #define F_VREFDQ0DSGN    V_VREFDQ0DSGN(1U)
72605 
72606 #define S_VREFDQ0D    11
72607 #define M_VREFDQ0D    0xfU
72608 #define V_VREFDQ0D(x) ((x) << S_VREFDQ0D)
72609 #define G_VREFDQ0D(x) (((x) >> S_VREFDQ0D) & M_VREFDQ0D)
72610 
72611 #define S_VREFDQ1DSGN    10
72612 #define V_VREFDQ1DSGN(x) ((x) << S_VREFDQ1DSGN)
72613 #define F_VREFDQ1DSGN    V_VREFDQ1DSGN(1U)
72614 
72615 #define S_VREFDQ1D    6
72616 #define M_VREFDQ1D    0xfU
72617 #define V_VREFDQ1D(x) ((x) << S_VREFDQ1D)
72618 #define G_VREFDQ1D(x) (((x) >> S_VREFDQ1D) & M_VREFDQ1D)
72619 
72620 #define S_EN_ANALOG_PD    3
72621 #define V_EN_ANALOG_PD(x) ((x) << S_EN_ANALOG_PD)
72622 #define F_EN_ANALOG_PD    V_EN_ANALOG_PD(1U)
72623 
72624 #define S_ANALOG_PD_DLY    2
72625 #define V_ANALOG_PD_DLY(x) ((x) << S_ANALOG_PD_DLY)
72626 #define F_ANALOG_PD_DLY    V_ANALOG_PD_DLY(1U)
72627 
72628 #define S_ANALOG_PD_DIV    0
72629 #define M_ANALOG_PD_DIV    0x3U
72630 #define V_ANALOG_PD_DIV(x) ((x) << S_ANALOG_PD_DIV)
72631 #define G_ANALOG_PD_DIV(x) (((x) >> S_ANALOG_PD_DIV) & M_ANALOG_PD_DIV)
72632 
72633 #define A_MC_DDRPHY_PC_INIT_CAL_CONFIG0 0x47058
72634 
72635 #define S_ENA_WR_LEVEL    15
72636 #define V_ENA_WR_LEVEL(x) ((x) << S_ENA_WR_LEVEL)
72637 #define F_ENA_WR_LEVEL    V_ENA_WR_LEVEL(1U)
72638 
72639 #define S_ENA_INITIAL_PAT_WR    14
72640 #define V_ENA_INITIAL_PAT_WR(x) ((x) << S_ENA_INITIAL_PAT_WR)
72641 #define F_ENA_INITIAL_PAT_WR    V_ENA_INITIAL_PAT_WR(1U)
72642 
72643 #define S_ENA_DQS_ALIGN    13
72644 #define V_ENA_DQS_ALIGN(x) ((x) << S_ENA_DQS_ALIGN)
72645 #define F_ENA_DQS_ALIGN    V_ENA_DQS_ALIGN(1U)
72646 
72647 #define S_ENA_RDCLK_ALIGN    12
72648 #define V_ENA_RDCLK_ALIGN(x) ((x) << S_ENA_RDCLK_ALIGN)
72649 #define F_ENA_RDCLK_ALIGN    V_ENA_RDCLK_ALIGN(1U)
72650 
72651 #define S_ENA_READ_CTR    11
72652 #define V_ENA_READ_CTR(x) ((x) << S_ENA_READ_CTR)
72653 #define F_ENA_READ_CTR    V_ENA_READ_CTR(1U)
72654 
72655 #define S_ENA_WRITE_CTR    10
72656 #define V_ENA_WRITE_CTR(x) ((x) << S_ENA_WRITE_CTR)
72657 #define F_ENA_WRITE_CTR    V_ENA_WRITE_CTR(1U)
72658 
72659 #define S_ENA_INITIAL_COARSE_WR    9
72660 #define V_ENA_INITIAL_COARSE_WR(x) ((x) << S_ENA_INITIAL_COARSE_WR)
72661 #define F_ENA_INITIAL_COARSE_WR    V_ENA_INITIAL_COARSE_WR(1U)
72662 
72663 #define S_ENA_COARSE_RD    8
72664 #define V_ENA_COARSE_RD(x) ((x) << S_ENA_COARSE_RD)
72665 #define F_ENA_COARSE_RD    V_ENA_COARSE_RD(1U)
72666 
72667 #define S_ENA_CUSTOM_RD    7
72668 #define V_ENA_CUSTOM_RD(x) ((x) << S_ENA_CUSTOM_RD)
72669 #define F_ENA_CUSTOM_RD    V_ENA_CUSTOM_RD(1U)
72670 
72671 #define S_ENA_CUSTOM_WR    6
72672 #define V_ENA_CUSTOM_WR(x) ((x) << S_ENA_CUSTOM_WR)
72673 #define F_ENA_CUSTOM_WR    V_ENA_CUSTOM_WR(1U)
72674 
72675 #define S_ABORT_ON_CAL_ERROR    5
72676 #define V_ABORT_ON_CAL_ERROR(x) ((x) << S_ABORT_ON_CAL_ERROR)
72677 #define F_ABORT_ON_CAL_ERROR    V_ABORT_ON_CAL_ERROR(1U)
72678 
72679 #define S_ENA_DIGITAL_EYE    4
72680 #define V_ENA_DIGITAL_EYE(x) ((x) << S_ENA_DIGITAL_EYE)
72681 #define F_ENA_DIGITAL_EYE    V_ENA_DIGITAL_EYE(1U)
72682 
72683 #define S_ENA_RANK_PAIR    0
72684 #define M_ENA_RANK_PAIR    0xfU
72685 #define V_ENA_RANK_PAIR(x) ((x) << S_ENA_RANK_PAIR)
72686 #define G_ENA_RANK_PAIR(x) (((x) >> S_ENA_RANK_PAIR) & M_ENA_RANK_PAIR)
72687 
72688 #define A_MC_DDRPHY_PC_INIT_CAL_CONFIG1 0x4705c
72689 
72690 #define S_REFRESH_COUNT    12
72691 #define M_REFRESH_COUNT    0xfU
72692 #define V_REFRESH_COUNT(x) ((x) << S_REFRESH_COUNT)
72693 #define G_REFRESH_COUNT(x) (((x) >> S_REFRESH_COUNT) & M_REFRESH_COUNT)
72694 
72695 #define S_REFRESH_CONTROL    10
72696 #define M_REFRESH_CONTROL    0x3U
72697 #define V_REFRESH_CONTROL(x) ((x) << S_REFRESH_CONTROL)
72698 #define G_REFRESH_CONTROL(x) (((x) >> S_REFRESH_CONTROL) & M_REFRESH_CONTROL)
72699 
72700 #define S_REFRESH_ALL_RANKS    9
72701 #define V_REFRESH_ALL_RANKS(x) ((x) << S_REFRESH_ALL_RANKS)
72702 #define F_REFRESH_ALL_RANKS    V_REFRESH_ALL_RANKS(1U)
72703 
72704 #define S_REFRESH_INTERVAL    0
72705 #define M_REFRESH_INTERVAL    0x7fU
72706 #define V_REFRESH_INTERVAL(x) ((x) << S_REFRESH_INTERVAL)
72707 #define G_REFRESH_INTERVAL(x) (((x) >> S_REFRESH_INTERVAL) & M_REFRESH_INTERVAL)
72708 
72709 #define A_MC_DDRPHY_PC_INIT_CAL_ERROR 0x47060
72710 
72711 #define S_ERROR_WR_LEVEL    15
72712 #define V_ERROR_WR_LEVEL(x) ((x) << S_ERROR_WR_LEVEL)
72713 #define F_ERROR_WR_LEVEL    V_ERROR_WR_LEVEL(1U)
72714 
72715 #define S_ERROR_INITIAL_PAT_WRITE    14
72716 #define V_ERROR_INITIAL_PAT_WRITE(x) ((x) << S_ERROR_INITIAL_PAT_WRITE)
72717 #define F_ERROR_INITIAL_PAT_WRITE    V_ERROR_INITIAL_PAT_WRITE(1U)
72718 
72719 #define S_ERROR_DQS_ALIGN    13
72720 #define V_ERROR_DQS_ALIGN(x) ((x) << S_ERROR_DQS_ALIGN)
72721 #define F_ERROR_DQS_ALIGN    V_ERROR_DQS_ALIGN(1U)
72722 
72723 #define S_ERROR_RDCLK_ALIGN    12
72724 #define V_ERROR_RDCLK_ALIGN(x) ((x) << S_ERROR_RDCLK_ALIGN)
72725 #define F_ERROR_RDCLK_ALIGN    V_ERROR_RDCLK_ALIGN(1U)
72726 
72727 #define S_ERROR_READ_CTR    11
72728 #define V_ERROR_READ_CTR(x) ((x) << S_ERROR_READ_CTR)
72729 #define F_ERROR_READ_CTR    V_ERROR_READ_CTR(1U)
72730 
72731 #define S_ERROR_WRITE_CTR    10
72732 #define V_ERROR_WRITE_CTR(x) ((x) << S_ERROR_WRITE_CTR)
72733 #define F_ERROR_WRITE_CTR    V_ERROR_WRITE_CTR(1U)
72734 
72735 #define S_ERROR_INITIAL_COARSE_WR    9
72736 #define V_ERROR_INITIAL_COARSE_WR(x) ((x) << S_ERROR_INITIAL_COARSE_WR)
72737 #define F_ERROR_INITIAL_COARSE_WR    V_ERROR_INITIAL_COARSE_WR(1U)
72738 
72739 #define S_ERROR_COARSE_RD    8
72740 #define V_ERROR_COARSE_RD(x) ((x) << S_ERROR_COARSE_RD)
72741 #define F_ERROR_COARSE_RD    V_ERROR_COARSE_RD(1U)
72742 
72743 #define S_ERROR_CUSTOM_RD    7
72744 #define V_ERROR_CUSTOM_RD(x) ((x) << S_ERROR_CUSTOM_RD)
72745 #define F_ERROR_CUSTOM_RD    V_ERROR_CUSTOM_RD(1U)
72746 
72747 #define S_ERROR_CUSTOM_WR    6
72748 #define V_ERROR_CUSTOM_WR(x) ((x) << S_ERROR_CUSTOM_WR)
72749 #define F_ERROR_CUSTOM_WR    V_ERROR_CUSTOM_WR(1U)
72750 
72751 #define S_ERROR_DIGITAL_EYE    5
72752 #define V_ERROR_DIGITAL_EYE(x) ((x) << S_ERROR_DIGITAL_EYE)
72753 #define F_ERROR_DIGITAL_EYE    V_ERROR_DIGITAL_EYE(1U)
72754 
72755 #define S_ERROR_RANK_PAIR    0
72756 #define M_ERROR_RANK_PAIR    0xfU
72757 #define V_ERROR_RANK_PAIR(x) ((x) << S_ERROR_RANK_PAIR)
72758 #define G_ERROR_RANK_PAIR(x) (((x) >> S_ERROR_RANK_PAIR) & M_ERROR_RANK_PAIR)
72759 
72760 #define A_MC_DDRPHY_PC_INIT_CAL_STATUS 0x47064
72761 
72762 #define S_INIT_CAL_COMPLETE    12
72763 #define M_INIT_CAL_COMPLETE    0xfU
72764 #define V_INIT_CAL_COMPLETE(x) ((x) << S_INIT_CAL_COMPLETE)
72765 #define G_INIT_CAL_COMPLETE(x) (((x) >> S_INIT_CAL_COMPLETE) & M_INIT_CAL_COMPLETE)
72766 
72767 #define S_PER_CAL_ABORT    6
72768 #define V_PER_CAL_ABORT(x) ((x) << S_PER_CAL_ABORT)
72769 #define F_PER_CAL_ABORT    V_PER_CAL_ABORT(1U)
72770 
72771 #define A_MC_DDRPHY_PC_INIT_CAL_MASK 0x47068
72772 
72773 #define S_ERROR_WR_LEVEL_MASK    15
72774 #define V_ERROR_WR_LEVEL_MASK(x) ((x) << S_ERROR_WR_LEVEL_MASK)
72775 #define F_ERROR_WR_LEVEL_MASK    V_ERROR_WR_LEVEL_MASK(1U)
72776 
72777 #define S_ERROR_INITIAL_PAT_WRITE_MASK    14
72778 #define V_ERROR_INITIAL_PAT_WRITE_MASK(x) ((x) << S_ERROR_INITIAL_PAT_WRITE_MASK)
72779 #define F_ERROR_INITIAL_PAT_WRITE_MASK    V_ERROR_INITIAL_PAT_WRITE_MASK(1U)
72780 
72781 #define S_ERROR_DQS_ALIGN_MASK    13
72782 #define V_ERROR_DQS_ALIGN_MASK(x) ((x) << S_ERROR_DQS_ALIGN_MASK)
72783 #define F_ERROR_DQS_ALIGN_MASK    V_ERROR_DQS_ALIGN_MASK(1U)
72784 
72785 #define S_ERROR_RDCLK_ALIGN_MASK    12
72786 #define V_ERROR_RDCLK_ALIGN_MASK(x) ((x) << S_ERROR_RDCLK_ALIGN_MASK)
72787 #define F_ERROR_RDCLK_ALIGN_MASK    V_ERROR_RDCLK_ALIGN_MASK(1U)
72788 
72789 #define S_ERROR_READ_CTR_MASK    11
72790 #define V_ERROR_READ_CTR_MASK(x) ((x) << S_ERROR_READ_CTR_MASK)
72791 #define F_ERROR_READ_CTR_MASK    V_ERROR_READ_CTR_MASK(1U)
72792 
72793 #define S_ERROR_WRITE_CTR_MASK    10
72794 #define V_ERROR_WRITE_CTR_MASK(x) ((x) << S_ERROR_WRITE_CTR_MASK)
72795 #define F_ERROR_WRITE_CTR_MASK    V_ERROR_WRITE_CTR_MASK(1U)
72796 
72797 #define S_ERROR_INITIAL_COARSE_WR_MASK    9
72798 #define V_ERROR_INITIAL_COARSE_WR_MASK(x) ((x) << S_ERROR_INITIAL_COARSE_WR_MASK)
72799 #define F_ERROR_INITIAL_COARSE_WR_MASK    V_ERROR_INITIAL_COARSE_WR_MASK(1U)
72800 
72801 #define S_ERROR_COARSE_RD_MASK    8
72802 #define V_ERROR_COARSE_RD_MASK(x) ((x) << S_ERROR_COARSE_RD_MASK)
72803 #define F_ERROR_COARSE_RD_MASK    V_ERROR_COARSE_RD_MASK(1U)
72804 
72805 #define S_ERROR_CUSTOM_RD_MASK    7
72806 #define V_ERROR_CUSTOM_RD_MASK(x) ((x) << S_ERROR_CUSTOM_RD_MASK)
72807 #define F_ERROR_CUSTOM_RD_MASK    V_ERROR_CUSTOM_RD_MASK(1U)
72808 
72809 #define S_ERROR_CUSTOM_WR_MASK    6
72810 #define V_ERROR_CUSTOM_WR_MASK(x) ((x) << S_ERROR_CUSTOM_WR_MASK)
72811 #define F_ERROR_CUSTOM_WR_MASK    V_ERROR_CUSTOM_WR_MASK(1U)
72812 
72813 #define S_ERROR_DIGITAL_EYE_MASK    5
72814 #define V_ERROR_DIGITAL_EYE_MASK(x) ((x) << S_ERROR_DIGITAL_EYE_MASK)
72815 #define F_ERROR_DIGITAL_EYE_MASK    V_ERROR_DIGITAL_EYE_MASK(1U)
72816 
72817 #define A_MC_DDRPHY_PC_IO_PVT_FET_STATUS 0x4706c
72818 #define A_MC_DDRPHY_PC_MR0_PRI_RP 0x47070
72819 
72820 #define S_MODEREGISTER0VALUE    0
72821 #define M_MODEREGISTER0VALUE    0xffffU
72822 #define V_MODEREGISTER0VALUE(x) ((x) << S_MODEREGISTER0VALUE)
72823 #define G_MODEREGISTER0VALUE(x) (((x) >> S_MODEREGISTER0VALUE) & M_MODEREGISTER0VALUE)
72824 
72825 #define A_MC_DDRPHY_PC_MR1_PRI_RP 0x47074
72826 
72827 #define S_MODEREGISTER1VALUE    0
72828 #define M_MODEREGISTER1VALUE    0xffffU
72829 #define V_MODEREGISTER1VALUE(x) ((x) << S_MODEREGISTER1VALUE)
72830 #define G_MODEREGISTER1VALUE(x) (((x) >> S_MODEREGISTER1VALUE) & M_MODEREGISTER1VALUE)
72831 
72832 #define A_MC_DDRPHY_PC_MR2_PRI_RP 0x47078
72833 
72834 #define S_MODEREGISTER2VALUE    0
72835 #define M_MODEREGISTER2VALUE    0xffffU
72836 #define V_MODEREGISTER2VALUE(x) ((x) << S_MODEREGISTER2VALUE)
72837 #define G_MODEREGISTER2VALUE(x) (((x) >> S_MODEREGISTER2VALUE) & M_MODEREGISTER2VALUE)
72838 
72839 #define A_MC_DDRPHY_PC_MR3_PRI_RP 0x4707c
72840 
72841 #define S_MODEREGISTER3VALUE    0
72842 #define M_MODEREGISTER3VALUE    0xffffU
72843 #define V_MODEREGISTER3VALUE(x) ((x) << S_MODEREGISTER3VALUE)
72844 #define G_MODEREGISTER3VALUE(x) (((x) >> S_MODEREGISTER3VALUE) & M_MODEREGISTER3VALUE)
72845 
72846 #define A_MC_DDRPHY_PC_MR0_SEC_RP 0x47080
72847 #define A_MC_DDRPHY_PC_MR1_SEC_RP 0x47084
72848 #define A_MC_DDRPHY_PC_MR2_SEC_RP 0x47088
72849 #define A_MC_DDRPHY_PC_MR3_SEC_RP 0x4708c
72850 
72851 #define S_MODE_REGISTER_3_VALUE    0
72852 #define M_MODE_REGISTER_3_VALUE    0xffffU
72853 #define V_MODE_REGISTER_3_VALUE(x) ((x) << S_MODE_REGISTER_3_VALUE)
72854 #define G_MODE_REGISTER_3_VALUE(x) (((x) >> S_MODE_REGISTER_3_VALUE) & M_MODE_REGISTER_3_VALUE)
72855 
72856 #define A_MC_DDRPHY_SEQ_RD_WR_DATA0 0x47200
72857 
72858 #define S_DRD_WR_DATA_REG    0
72859 #define M_DRD_WR_DATA_REG    0xffffU
72860 #define V_DRD_WR_DATA_REG(x) ((x) << S_DRD_WR_DATA_REG)
72861 #define G_DRD_WR_DATA_REG(x) (((x) >> S_DRD_WR_DATA_REG) & M_DRD_WR_DATA_REG)
72862 
72863 #define A_MC_DDRPHY_SEQ_RD_WR_DATA1 0x47204
72864 #define A_MC_DDRPHY_SEQ_CONFIG0 0x47208
72865 
72866 #define S_MPR_PATTERN_BIT    15
72867 #define V_MPR_PATTERN_BIT(x) ((x) << S_MPR_PATTERN_BIT)
72868 #define F_MPR_PATTERN_BIT    V_MPR_PATTERN_BIT(1U)
72869 
72870 #define S_TWO_CYCLE_ADDR_EN    14
72871 #define V_TWO_CYCLE_ADDR_EN(x) ((x) << S_TWO_CYCLE_ADDR_EN)
72872 #define F_TWO_CYCLE_ADDR_EN    V_TWO_CYCLE_ADDR_EN(1U)
72873 
72874 #define S_MR_MASK_EN    10
72875 #define M_MR_MASK_EN    0xfU
72876 #define V_MR_MASK_EN(x) ((x) << S_MR_MASK_EN)
72877 #define G_MR_MASK_EN(x) (((x) >> S_MR_MASK_EN) & M_MR_MASK_EN)
72878 
72879 #define S_PARITY_DLY    9
72880 #define V_PARITY_DLY(x) ((x) << S_PARITY_DLY)
72881 #define F_PARITY_DLY    V_PARITY_DLY(1U)
72882 
72883 #define S_FORCE_RESERVED    7
72884 #define V_FORCE_RESERVED(x) ((x) << S_FORCE_RESERVED)
72885 #define F_FORCE_RESERVED    V_FORCE_RESERVED(1U)
72886 
72887 #define S_HALT_ROTATION    6
72888 #define V_HALT_ROTATION(x) ((x) << S_HALT_ROTATION)
72889 #define F_HALT_ROTATION    V_HALT_ROTATION(1U)
72890 
72891 #define S_FORCE_MPR    5
72892 #define V_FORCE_MPR(x) ((x) << S_FORCE_MPR)
72893 #define F_FORCE_MPR    V_FORCE_MPR(1U)
72894 
72895 #define S_IPW_SIDEAB_SEL    2
72896 #define V_IPW_SIDEAB_SEL(x) ((x) << S_IPW_SIDEAB_SEL)
72897 #define F_IPW_SIDEAB_SEL    V_IPW_SIDEAB_SEL(1U)
72898 
72899 #define S_PARITY_A17_MASK    1
72900 #define V_PARITY_A17_MASK(x) ((x) << S_PARITY_A17_MASK)
72901 #define F_PARITY_A17_MASK    V_PARITY_A17_MASK(1U)
72902 
72903 #define S_X16_DEVICE    0
72904 #define V_X16_DEVICE(x) ((x) << S_X16_DEVICE)
72905 #define F_X16_DEVICE    V_X16_DEVICE(1U)
72906 
72907 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR0 0x4720c
72908 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR1 0x47210
72909 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR2 0x47214
72910 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR3 0x47218
72911 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR4 0x4721c
72912 #define A_MC_DDRPHY_SEQ_ERROR_STATUS0 0x47220
72913 
72914 #define S_MULTIPLE_REQ_ERROR    15
72915 #define V_MULTIPLE_REQ_ERROR(x) ((x) << S_MULTIPLE_REQ_ERROR)
72916 #define F_MULTIPLE_REQ_ERROR    V_MULTIPLE_REQ_ERROR(1U)
72917 
72918 #define S_INVALID_REQTYPE_ERRO    14
72919 #define V_INVALID_REQTYPE_ERRO(x) ((x) << S_INVALID_REQTYPE_ERRO)
72920 #define F_INVALID_REQTYPE_ERRO    V_INVALID_REQTYPE_ERRO(1U)
72921 
72922 #define S_EARLY_REQ_ERROR    13
72923 #define V_EARLY_REQ_ERROR(x) ((x) << S_EARLY_REQ_ERROR)
72924 #define F_EARLY_REQ_ERROR    V_EARLY_REQ_ERROR(1U)
72925 
72926 #define S_MULTIPLE_REQ_SOURCE    10
72927 #define M_MULTIPLE_REQ_SOURCE    0x7U
72928 #define V_MULTIPLE_REQ_SOURCE(x) ((x) << S_MULTIPLE_REQ_SOURCE)
72929 #define G_MULTIPLE_REQ_SOURCE(x) (((x) >> S_MULTIPLE_REQ_SOURCE) & M_MULTIPLE_REQ_SOURCE)
72930 
72931 #define S_INVALID_REQTYPE    6
72932 #define M_INVALID_REQTYPE    0xfU
72933 #define V_INVALID_REQTYPE(x) ((x) << S_INVALID_REQTYPE)
72934 #define G_INVALID_REQTYPE(x) (((x) >> S_INVALID_REQTYPE) & M_INVALID_REQTYPE)
72935 
72936 #define S_INVALID_REQ_SOURCE    3
72937 #define M_INVALID_REQ_SOURCE    0x7U
72938 #define V_INVALID_REQ_SOURCE(x) ((x) << S_INVALID_REQ_SOURCE)
72939 #define G_INVALID_REQ_SOURCE(x) (((x) >> S_INVALID_REQ_SOURCE) & M_INVALID_REQ_SOURCE)
72940 
72941 #define S_EARLY_REQ_SOURCE    0
72942 #define M_EARLY_REQ_SOURCE    0x7U
72943 #define V_EARLY_REQ_SOURCE(x) ((x) << S_EARLY_REQ_SOURCE)
72944 #define G_EARLY_REQ_SOURCE(x) (((x) >> S_EARLY_REQ_SOURCE) & M_EARLY_REQ_SOURCE)
72945 
72946 #define A_MC_DDRPHY_SEQ_ERROR_MASK0 0x47224
72947 
72948 #define S_MULT_REQ_ERR_MASK    15
72949 #define V_MULT_REQ_ERR_MASK(x) ((x) << S_MULT_REQ_ERR_MASK)
72950 #define F_MULT_REQ_ERR_MASK    V_MULT_REQ_ERR_MASK(1U)
72951 
72952 #define S_INVALID_REQTYPE_ERR_MASK    14
72953 #define V_INVALID_REQTYPE_ERR_MASK(x) ((x) << S_INVALID_REQTYPE_ERR_MASK)
72954 #define F_INVALID_REQTYPE_ERR_MASK    V_INVALID_REQTYPE_ERR_MASK(1U)
72955 
72956 #define S_EARLY_REQ_ERR_MASK    13
72957 #define V_EARLY_REQ_ERR_MASK(x) ((x) << S_EARLY_REQ_ERR_MASK)
72958 #define F_EARLY_REQ_ERR_MASK    V_EARLY_REQ_ERR_MASK(1U)
72959 
72960 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG0 0x47228
72961 
72962 #define S_ODT_WR_VALUES_BITS0_7    8
72963 #define M_ODT_WR_VALUES_BITS0_7    0xffU
72964 #define V_ODT_WR_VALUES_BITS0_7(x) ((x) << S_ODT_WR_VALUES_BITS0_7)
72965 #define G_ODT_WR_VALUES_BITS0_7(x) (((x) >> S_ODT_WR_VALUES_BITS0_7) & M_ODT_WR_VALUES_BITS0_7)
72966 
72967 #define S_ODT_WR_VALUES_BITS8_15    0
72968 #define M_ODT_WR_VALUES_BITS8_15    0xffU
72969 #define V_ODT_WR_VALUES_BITS8_15(x) ((x) << S_ODT_WR_VALUES_BITS8_15)
72970 #define G_ODT_WR_VALUES_BITS8_15(x) (((x) >> S_ODT_WR_VALUES_BITS8_15) & M_ODT_WR_VALUES_BITS8_15)
72971 
72972 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG1 0x4722c
72973 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG2 0x47230
72974 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG3 0x47234
72975 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG0 0x47238
72976 
72977 #define S_ODT_RD_VALUES_X2    8
72978 #define M_ODT_RD_VALUES_X2    0xffU
72979 #define V_ODT_RD_VALUES_X2(x) ((x) << S_ODT_RD_VALUES_X2)
72980 #define G_ODT_RD_VALUES_X2(x) (((x) >> S_ODT_RD_VALUES_X2) & M_ODT_RD_VALUES_X2)
72981 
72982 #define S_ODT_RD_VALUES_X2PLUS1    0
72983 #define M_ODT_RD_VALUES_X2PLUS1    0xffU
72984 #define V_ODT_RD_VALUES_X2PLUS1(x) ((x) << S_ODT_RD_VALUES_X2PLUS1)
72985 #define G_ODT_RD_VALUES_X2PLUS1(x) (((x) >> S_ODT_RD_VALUES_X2PLUS1) & M_ODT_RD_VALUES_X2PLUS1)
72986 
72987 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG1 0x4723c
72988 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG2 0x47240
72989 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG3 0x47244
72990 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM0 0x47248
72991 
72992 #define S_TMOD_CYCLES    12
72993 #define M_TMOD_CYCLES    0xfU
72994 #define V_TMOD_CYCLES(x) ((x) << S_TMOD_CYCLES)
72995 #define G_TMOD_CYCLES(x) (((x) >> S_TMOD_CYCLES) & M_TMOD_CYCLES)
72996 
72997 #define S_TRCD_CYCLES    8
72998 #define M_TRCD_CYCLES    0xfU
72999 #define V_TRCD_CYCLES(x) ((x) << S_TRCD_CYCLES)
73000 #define G_TRCD_CYCLES(x) (((x) >> S_TRCD_CYCLES) & M_TRCD_CYCLES)
73001 
73002 #define S_TRP_CYCLES    4
73003 #define M_TRP_CYCLES    0xfU
73004 #define V_TRP_CYCLES(x) ((x) << S_TRP_CYCLES)
73005 #define G_TRP_CYCLES(x) (((x) >> S_TRP_CYCLES) & M_TRP_CYCLES)
73006 
73007 #define S_TRFC_CYCLES    0
73008 #define M_TRFC_CYCLES    0xfU
73009 #define V_TRFC_CYCLES(x) ((x) << S_TRFC_CYCLES)
73010 #define G_TRFC_CYCLES(x) (((x) >> S_TRFC_CYCLES) & M_TRFC_CYCLES)
73011 
73012 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM1 0x4724c
73013 
73014 #define S_TZQINIT_CYCLES    12
73015 #define M_TZQINIT_CYCLES    0xfU
73016 #define V_TZQINIT_CYCLES(x) ((x) << S_TZQINIT_CYCLES)
73017 #define G_TZQINIT_CYCLES(x) (((x) >> S_TZQINIT_CYCLES) & M_TZQINIT_CYCLES)
73018 
73019 #define S_TZQCS_CYCLES    8
73020 #define M_TZQCS_CYCLES    0xfU
73021 #define V_TZQCS_CYCLES(x) ((x) << S_TZQCS_CYCLES)
73022 #define G_TZQCS_CYCLES(x) (((x) >> S_TZQCS_CYCLES) & M_TZQCS_CYCLES)
73023 
73024 #define S_TWLDQSEN_CYCLES    4
73025 #define M_TWLDQSEN_CYCLES    0xfU
73026 #define V_TWLDQSEN_CYCLES(x) ((x) << S_TWLDQSEN_CYCLES)
73027 #define G_TWLDQSEN_CYCLES(x) (((x) >> S_TWLDQSEN_CYCLES) & M_TWLDQSEN_CYCLES)
73028 
73029 #define S_TWRMRD_CYCLES    0
73030 #define M_TWRMRD_CYCLES    0xfU
73031 #define V_TWRMRD_CYCLES(x) ((x) << S_TWRMRD_CYCLES)
73032 #define G_TWRMRD_CYCLES(x) (((x) >> S_TWRMRD_CYCLES) & M_TWRMRD_CYCLES)
73033 
73034 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM2 0x47250
73035 
73036 #define S_TODTLON_OFF_CYCLES    12
73037 #define M_TODTLON_OFF_CYCLES    0xfU
73038 #define V_TODTLON_OFF_CYCLES(x) ((x) << S_TODTLON_OFF_CYCLES)
73039 #define G_TODTLON_OFF_CYCLES(x) (((x) >> S_TODTLON_OFF_CYCLES) & M_TODTLON_OFF_CYCLES)
73040 
73041 #define S_TRC_CYCLES    8
73042 #define M_TRC_CYCLES    0xfU
73043 #define V_TRC_CYCLES(x) ((x) << S_TRC_CYCLES)
73044 #define G_TRC_CYCLES(x) (((x) >> S_TRC_CYCLES) & M_TRC_CYCLES)
73045 
73046 #define S_TMRSC_CYCLES    4
73047 #define M_TMRSC_CYCLES    0xfU
73048 #define V_TMRSC_CYCLES(x) ((x) << S_TMRSC_CYCLES)
73049 #define G_TMRSC_CYCLES(x) (((x) >> S_TMRSC_CYCLES) & M_TMRSC_CYCLES)
73050 
73051 #define S_MRS_CMD_SPACE    0
73052 #define M_MRS_CMD_SPACE    0xfU
73053 #define V_MRS_CMD_SPACE(x) ((x) << S_MRS_CMD_SPACE)
73054 #define G_MRS_CMD_SPACE(x) (((x) >> S_MRS_CMD_SPACE) & M_MRS_CMD_SPACE)
73055 
73056 #define A_MC_DDRPHY_RC_CONFIG0 0x47400
73057 
73058 #define S_GLOBAL_PHY_OFFSET    12
73059 #define M_GLOBAL_PHY_OFFSET    0xfU
73060 #define V_GLOBAL_PHY_OFFSET(x) ((x) << S_GLOBAL_PHY_OFFSET)
73061 #define G_GLOBAL_PHY_OFFSET(x) (((x) >> S_GLOBAL_PHY_OFFSET) & M_GLOBAL_PHY_OFFSET)
73062 
73063 #define S_ADVANCE_RD_VALID    11
73064 #define V_ADVANCE_RD_VALID(x) ((x) << S_ADVANCE_RD_VALID)
73065 #define F_ADVANCE_RD_VALID    V_ADVANCE_RD_VALID(1U)
73066 
73067 #define S_SINGLE_BIT_MPR_RP0    6
73068 #define V_SINGLE_BIT_MPR_RP0(x) ((x) << S_SINGLE_BIT_MPR_RP0)
73069 #define F_SINGLE_BIT_MPR_RP0    V_SINGLE_BIT_MPR_RP0(1U)
73070 
73071 #define S_SINGLE_BIT_MPR_RP1    5
73072 #define V_SINGLE_BIT_MPR_RP1(x) ((x) << S_SINGLE_BIT_MPR_RP1)
73073 #define F_SINGLE_BIT_MPR_RP1    V_SINGLE_BIT_MPR_RP1(1U)
73074 
73075 #define S_SINGLE_BIT_MPR_RP2    4
73076 #define V_SINGLE_BIT_MPR_RP2(x) ((x) << S_SINGLE_BIT_MPR_RP2)
73077 #define F_SINGLE_BIT_MPR_RP2    V_SINGLE_BIT_MPR_RP2(1U)
73078 
73079 #define S_SINGLE_BIT_MPR_RP3    3
73080 #define V_SINGLE_BIT_MPR_RP3(x) ((x) << S_SINGLE_BIT_MPR_RP3)
73081 #define F_SINGLE_BIT_MPR_RP3    V_SINGLE_BIT_MPR_RP3(1U)
73082 
73083 #define S_ALIGN_ON_EVEN_CYCLES    2
73084 #define V_ALIGN_ON_EVEN_CYCLES(x) ((x) << S_ALIGN_ON_EVEN_CYCLES)
73085 #define F_ALIGN_ON_EVEN_CYCLES    V_ALIGN_ON_EVEN_CYCLES(1U)
73086 
73087 #define S_PERFORM_RDCLK_ALIGN    1
73088 #define V_PERFORM_RDCLK_ALIGN(x) ((x) << S_PERFORM_RDCLK_ALIGN)
73089 #define F_PERFORM_RDCLK_ALIGN    V_PERFORM_RDCLK_ALIGN(1U)
73090 
73091 #define S_STAGGERED_PATTERN    0
73092 #define V_STAGGERED_PATTERN(x) ((x) << S_STAGGERED_PATTERN)
73093 #define F_STAGGERED_PATTERN    V_STAGGERED_PATTERN(1U)
73094 
73095 #define S_ERS_MODE    10
73096 #define V_ERS_MODE(x) ((x) << S_ERS_MODE)
73097 #define F_ERS_MODE    V_ERS_MODE(1U)
73098 
73099 #define A_MC_DDRPHY_RC_CONFIG1 0x47404
73100 
73101 #define S_OUTER_LOOP_CNT    2
73102 #define M_OUTER_LOOP_CNT    0x3fffU
73103 #define V_OUTER_LOOP_CNT(x) ((x) << S_OUTER_LOOP_CNT)
73104 #define G_OUTER_LOOP_CNT(x) (((x) >> S_OUTER_LOOP_CNT) & M_OUTER_LOOP_CNT)
73105 
73106 #define A_MC_DDRPHY_RC_CONFIG2 0x47408
73107 
73108 #define S_CONSEQ_PASS    11
73109 #define M_CONSEQ_PASS    0x1fU
73110 #define V_CONSEQ_PASS(x) ((x) << S_CONSEQ_PASS)
73111 #define G_CONSEQ_PASS(x) (((x) >> S_CONSEQ_PASS) & M_CONSEQ_PASS)
73112 
73113 #define S_BURST_WINDOW    5
73114 #define M_BURST_WINDOW    0x3U
73115 #define V_BURST_WINDOW(x) ((x) << S_BURST_WINDOW)
73116 #define G_BURST_WINDOW(x) (((x) >> S_BURST_WINDOW) & M_BURST_WINDOW)
73117 
73118 #define S_ALLOW_RD_FIFO_AUTO_R_ESET    4
73119 #define V_ALLOW_RD_FIFO_AUTO_R_ESET(x) ((x) << S_ALLOW_RD_FIFO_AUTO_R_ESET)
73120 #define F_ALLOW_RD_FIFO_AUTO_R_ESET    V_ALLOW_RD_FIFO_AUTO_R_ESET(1U)
73121 
73122 #define S_DIS_LOW_PWR_PER_CAL    3
73123 #define V_DIS_LOW_PWR_PER_CAL(x) ((x) << S_DIS_LOW_PWR_PER_CAL)
73124 #define F_DIS_LOW_PWR_PER_CAL    V_DIS_LOW_PWR_PER_CAL(1U)
73125 
73126 #define A_MC_DDRPHY_RC_ERROR_STATUS0 0x47414
73127 
73128 #define S_RD_CNTL_ERROR    15
73129 #define V_RD_CNTL_ERROR(x) ((x) << S_RD_CNTL_ERROR)
73130 #define F_RD_CNTL_ERROR    V_RD_CNTL_ERROR(1U)
73131 
73132 #define A_MC_DDRPHY_RC_ERROR_MASK0 0x47418
73133 
73134 #define S_RD_CNTL_ERROR_MASK    15
73135 #define V_RD_CNTL_ERROR_MASK(x) ((x) << S_RD_CNTL_ERROR_MASK)
73136 #define F_RD_CNTL_ERROR_MASK    V_RD_CNTL_ERROR_MASK(1U)
73137 
73138 #define A_MC_DDRPHY_RC_CONFIG3 0x4741c
73139 
73140 #define S_FINE_CAL_STEP_SIZE    13
73141 #define M_FINE_CAL_STEP_SIZE    0x7U
73142 #define V_FINE_CAL_STEP_SIZE(x) ((x) << S_FINE_CAL_STEP_SIZE)
73143 #define G_FINE_CAL_STEP_SIZE(x) (((x) >> S_FINE_CAL_STEP_SIZE) & M_FINE_CAL_STEP_SIZE)
73144 
73145 #define S_COARSE_CAL_STEP_SIZE    9
73146 #define M_COARSE_CAL_STEP_SIZE    0xfU
73147 #define V_COARSE_CAL_STEP_SIZE(x) ((x) << S_COARSE_CAL_STEP_SIZE)
73148 #define G_COARSE_CAL_STEP_SIZE(x) (((x) >> S_COARSE_CAL_STEP_SIZE) & M_COARSE_CAL_STEP_SIZE)
73149 
73150 #define S_DQ_SEL_QUAD    7
73151 #define M_DQ_SEL_QUAD    0x3U
73152 #define V_DQ_SEL_QUAD(x) ((x) << S_DQ_SEL_QUAD)
73153 #define G_DQ_SEL_QUAD(x) (((x) >> S_DQ_SEL_QUAD) & M_DQ_SEL_QUAD)
73154 
73155 #define S_DQ_SEL_LANE    4
73156 #define M_DQ_SEL_LANE    0x7U
73157 #define V_DQ_SEL_LANE(x) ((x) << S_DQ_SEL_LANE)
73158 #define G_DQ_SEL_LANE(x) (((x) >> S_DQ_SEL_LANE) & M_DQ_SEL_LANE)
73159 
73160 #define A_MC_DDRPHY_RC_PERIODIC 0x47420
73161 #define A_MC_DDRPHY_WC_CONFIG0 0x47600
73162 
73163 #define S_TWLO_TWLOE    8
73164 #define M_TWLO_TWLOE    0xffU
73165 #define V_TWLO_TWLOE(x) ((x) << S_TWLO_TWLOE)
73166 #define G_TWLO_TWLOE(x) (((x) >> S_TWLO_TWLOE) & M_TWLO_TWLOE)
73167 
73168 #define S_WL_ONE_DQS_PULSE    7
73169 #define V_WL_ONE_DQS_PULSE(x) ((x) << S_WL_ONE_DQS_PULSE)
73170 #define F_WL_ONE_DQS_PULSE    V_WL_ONE_DQS_PULSE(1U)
73171 
73172 #define S_FW_WR_RD    1
73173 #define M_FW_WR_RD    0x3fU
73174 #define V_FW_WR_RD(x) ((x) << S_FW_WR_RD)
73175 #define G_FW_WR_RD(x) (((x) >> S_FW_WR_RD) & M_FW_WR_RD)
73176 
73177 #define S_CUSTOM_INIT_WRITE    0
73178 #define V_CUSTOM_INIT_WRITE(x) ((x) << S_CUSTOM_INIT_WRITE)
73179 #define F_CUSTOM_INIT_WRITE    V_CUSTOM_INIT_WRITE(1U)
73180 
73181 #define A_MC_DDRPHY_WC_CONFIG1 0x47604
73182 
73183 #define S_BIG_STEP    12
73184 #define M_BIG_STEP    0xfU
73185 #define V_BIG_STEP(x) ((x) << S_BIG_STEP)
73186 #define G_BIG_STEP(x) (((x) >> S_BIG_STEP) & M_BIG_STEP)
73187 
73188 #define S_SMALL_STEP    9
73189 #define M_SMALL_STEP    0x7U
73190 #define V_SMALL_STEP(x) ((x) << S_SMALL_STEP)
73191 #define G_SMALL_STEP(x) (((x) >> S_SMALL_STEP) & M_SMALL_STEP)
73192 
73193 #define S_WR_PRE_DLY    3
73194 #define M_WR_PRE_DLY    0x3fU
73195 #define V_WR_PRE_DLY(x) ((x) << S_WR_PRE_DLY)
73196 #define G_WR_PRE_DLY(x) (((x) >> S_WR_PRE_DLY) & M_WR_PRE_DLY)
73197 
73198 #define A_MC_DDRPHY_WC_CONFIG2 0x47608
73199 
73200 #define S_NUM_VALID_SAMPLES    12
73201 #define M_NUM_VALID_SAMPLES    0xfU
73202 #define V_NUM_VALID_SAMPLES(x) ((x) << S_NUM_VALID_SAMPLES)
73203 #define G_NUM_VALID_SAMPLES(x) (((x) >> S_NUM_VALID_SAMPLES) & M_NUM_VALID_SAMPLES)
73204 
73205 #define S_FW_RD_WR    6
73206 #define M_FW_RD_WR    0x3fU
73207 #define V_FW_RD_WR(x) ((x) << S_FW_RD_WR)
73208 #define G_FW_RD_WR(x) (((x) >> S_FW_RD_WR) & M_FW_RD_WR)
73209 
73210 #define S_EN_RESET_WR_DELAY_WL    0
73211 #define V_EN_RESET_WR_DELAY_WL(x) ((x) << S_EN_RESET_WR_DELAY_WL)
73212 #define F_EN_RESET_WR_DELAY_WL    V_EN_RESET_WR_DELAY_WL(1U)
73213 
73214 #define S_TWR_MPR    2
73215 #define M_TWR_MPR    0xfU
73216 #define V_TWR_MPR(x) ((x) << S_TWR_MPR)
73217 #define G_TWR_MPR(x) (((x) >> S_TWR_MPR) & M_TWR_MPR)
73218 
73219 #define A_MC_DDRPHY_WC_ERROR_STATUS0 0x4760c
73220 
73221 #define S_WR_CNTL_ERROR    15
73222 #define V_WR_CNTL_ERROR(x) ((x) << S_WR_CNTL_ERROR)
73223 #define F_WR_CNTL_ERROR    V_WR_CNTL_ERROR(1U)
73224 
73225 #define A_MC_DDRPHY_WC_ERROR_MASK0 0x47610
73226 
73227 #define S_WR_CNTL_ERROR_MASK    15
73228 #define V_WR_CNTL_ERROR_MASK(x) ((x) << S_WR_CNTL_ERROR_MASK)
73229 #define F_WR_CNTL_ERROR_MASK    V_WR_CNTL_ERROR_MASK(1U)
73230 
73231 #define A_MC_DDRPHY_WC_CONFIG3 0x47614
73232 
73233 #define S_DDR4_MRS_CMD_DQ_EN    15
73234 #define V_DDR4_MRS_CMD_DQ_EN(x) ((x) << S_DDR4_MRS_CMD_DQ_EN)
73235 #define F_DDR4_MRS_CMD_DQ_EN    V_DDR4_MRS_CMD_DQ_EN(1U)
73236 
73237 #define S_MRS_CMD_DQ_ON    9
73238 #define M_MRS_CMD_DQ_ON    0x3fU
73239 #define V_MRS_CMD_DQ_ON(x) ((x) << S_MRS_CMD_DQ_ON)
73240 #define G_MRS_CMD_DQ_ON(x) (((x) >> S_MRS_CMD_DQ_ON) & M_MRS_CMD_DQ_ON)
73241 
73242 #define S_MRS_CMD_DQ_OFF    3
73243 #define M_MRS_CMD_DQ_OFF    0x3fU
73244 #define V_MRS_CMD_DQ_OFF(x) ((x) << S_MRS_CMD_DQ_OFF)
73245 #define G_MRS_CMD_DQ_OFF(x) (((x) >> S_MRS_CMD_DQ_OFF) & M_MRS_CMD_DQ_OFF)
73246 
73247 #define A_MC_DDRPHY_WC_WRCLK_CNTL 0x47618
73248 
73249 #define S_WRCLK_CAL_START    15
73250 #define V_WRCLK_CAL_START(x) ((x) << S_WRCLK_CAL_START)
73251 #define F_WRCLK_CAL_START    V_WRCLK_CAL_START(1U)
73252 
73253 #define S_WRCLK_CAL_DONE    14
73254 #define V_WRCLK_CAL_DONE(x) ((x) << S_WRCLK_CAL_DONE)
73255 #define F_WRCLK_CAL_DONE    V_WRCLK_CAL_DONE(1U)
73256 
73257 #define A_MC_DDRPHY_APB_CONFIG0 0x47800
73258 
73259 #define S_DISABLE_PARITY_CHECKER    15
73260 #define V_DISABLE_PARITY_CHECKER(x) ((x) << S_DISABLE_PARITY_CHECKER)
73261 #define F_DISABLE_PARITY_CHECKER    V_DISABLE_PARITY_CHECKER(1U)
73262 
73263 #define S_GENERATE_EVEN_PARITY    14
73264 #define V_GENERATE_EVEN_PARITY(x) ((x) << S_GENERATE_EVEN_PARITY)
73265 #define F_GENERATE_EVEN_PARITY    V_GENERATE_EVEN_PARITY(1U)
73266 
73267 #define S_FORCE_ON_CLK_GATE    13
73268 #define V_FORCE_ON_CLK_GATE(x) ((x) << S_FORCE_ON_CLK_GATE)
73269 #define F_FORCE_ON_CLK_GATE    V_FORCE_ON_CLK_GATE(1U)
73270 
73271 #define S_DEBUG_BUS_SEL_LO    12
73272 #define V_DEBUG_BUS_SEL_LO(x) ((x) << S_DEBUG_BUS_SEL_LO)
73273 #define F_DEBUG_BUS_SEL_LO    V_DEBUG_BUS_SEL_LO(1U)
73274 
73275 #define S_DEBUG_BUS_SEL_HI    8
73276 #define M_DEBUG_BUS_SEL_HI    0xfU
73277 #define V_DEBUG_BUS_SEL_HI(x) ((x) << S_DEBUG_BUS_SEL_HI)
73278 #define G_DEBUG_BUS_SEL_HI(x) (((x) >> S_DEBUG_BUS_SEL_HI) & M_DEBUG_BUS_SEL_HI)
73279 
73280 #define A_MC_DDRPHY_APB_ERROR_STATUS0 0x47804
73281 
73282 #define S_INVALID_ADDRESS    15
73283 #define V_INVALID_ADDRESS(x) ((x) << S_INVALID_ADDRESS)
73284 #define F_INVALID_ADDRESS    V_INVALID_ADDRESS(1U)
73285 
73286 #define S_WR_PAR_ERR    14
73287 #define V_WR_PAR_ERR(x) ((x) << S_WR_PAR_ERR)
73288 #define F_WR_PAR_ERR    V_WR_PAR_ERR(1U)
73289 
73290 #define A_MC_DDRPHY_APB_ERROR_MASK0 0x47808
73291 
73292 #define S_INVALID_ADDRESS_MASK    15
73293 #define V_INVALID_ADDRESS_MASK(x) ((x) << S_INVALID_ADDRESS_MASK)
73294 #define F_INVALID_ADDRESS_MASK    V_INVALID_ADDRESS_MASK(1U)
73295 
73296 #define S_WR_PAR_ERR_MASK    14
73297 #define V_WR_PAR_ERR_MASK(x) ((x) << S_WR_PAR_ERR_MASK)
73298 #define F_WR_PAR_ERR_MASK    V_WR_PAR_ERR_MASK(1U)
73299 
73300 #define A_MC_DDRPHY_APB_DP18_POPULATION 0x4780c
73301 
73302 #define S_DP18_0_POPULATED    15
73303 #define V_DP18_0_POPULATED(x) ((x) << S_DP18_0_POPULATED)
73304 #define F_DP18_0_POPULATED    V_DP18_0_POPULATED(1U)
73305 
73306 #define S_DP18_1_POPULATED    14
73307 #define V_DP18_1_POPULATED(x) ((x) << S_DP18_1_POPULATED)
73308 #define F_DP18_1_POPULATED    V_DP18_1_POPULATED(1U)
73309 
73310 #define S_DP18_2_POPULATED    13
73311 #define V_DP18_2_POPULATED(x) ((x) << S_DP18_2_POPULATED)
73312 #define F_DP18_2_POPULATED    V_DP18_2_POPULATED(1U)
73313 
73314 #define S_DP18_3_POPULATED    12
73315 #define V_DP18_3_POPULATED(x) ((x) << S_DP18_3_POPULATED)
73316 #define F_DP18_3_POPULATED    V_DP18_3_POPULATED(1U)
73317 
73318 #define S_DP18_4_POPULATED    11
73319 #define V_DP18_4_POPULATED(x) ((x) << S_DP18_4_POPULATED)
73320 #define F_DP18_4_POPULATED    V_DP18_4_POPULATED(1U)
73321 
73322 #define S_DP18_5_POPULATED    10
73323 #define V_DP18_5_POPULATED(x) ((x) << S_DP18_5_POPULATED)
73324 #define F_DP18_5_POPULATED    V_DP18_5_POPULATED(1U)
73325 
73326 #define S_DP18_6_POPULATED    9
73327 #define V_DP18_6_POPULATED(x) ((x) << S_DP18_6_POPULATED)
73328 #define F_DP18_6_POPULATED    V_DP18_6_POPULATED(1U)
73329 
73330 #define S_DP18_7_POPULATED    8
73331 #define V_DP18_7_POPULATED(x) ((x) << S_DP18_7_POPULATED)
73332 #define F_DP18_7_POPULATED    V_DP18_7_POPULATED(1U)
73333 
73334 #define S_DP18_8_POPULATED    7
73335 #define V_DP18_8_POPULATED(x) ((x) << S_DP18_8_POPULATED)
73336 #define F_DP18_8_POPULATED    V_DP18_8_POPULATED(1U)
73337 
73338 #define S_DP18_9_POPULATED    6
73339 #define V_DP18_9_POPULATED(x) ((x) << S_DP18_9_POPULATED)
73340 #define F_DP18_9_POPULATED    V_DP18_9_POPULATED(1U)
73341 
73342 #define S_DP18_10_POPULATED    5
73343 #define V_DP18_10_POPULATED(x) ((x) << S_DP18_10_POPULATED)
73344 #define F_DP18_10_POPULATED    V_DP18_10_POPULATED(1U)
73345 
73346 #define S_DP18_11_POPULATED    4
73347 #define V_DP18_11_POPULATED(x) ((x) << S_DP18_11_POPULATED)
73348 #define F_DP18_11_POPULATED    V_DP18_11_POPULATED(1U)
73349 
73350 #define S_DP18_12_POPULATED    3
73351 #define V_DP18_12_POPULATED(x) ((x) << S_DP18_12_POPULATED)
73352 #define F_DP18_12_POPULATED    V_DP18_12_POPULATED(1U)
73353 
73354 #define S_DP18_13_POPULATED    2
73355 #define V_DP18_13_POPULATED(x) ((x) << S_DP18_13_POPULATED)
73356 #define F_DP18_13_POPULATED    V_DP18_13_POPULATED(1U)
73357 
73358 #define S_DP18_14_POPULATED    1
73359 #define V_DP18_14_POPULATED(x) ((x) << S_DP18_14_POPULATED)
73360 #define F_DP18_14_POPULATED    V_DP18_14_POPULATED(1U)
73361 
73362 #define A_MC_DDRPHY_APB_ADR_POPULATION 0x47810
73363 
73364 #define S_ADR16_0_POPULATED    15
73365 #define V_ADR16_0_POPULATED(x) ((x) << S_ADR16_0_POPULATED)
73366 #define F_ADR16_0_POPULATED    V_ADR16_0_POPULATED(1U)
73367 
73368 #define S_ADR16_1_POPULATED    14
73369 #define V_ADR16_1_POPULATED(x) ((x) << S_ADR16_1_POPULATED)
73370 #define F_ADR16_1_POPULATED    V_ADR16_1_POPULATED(1U)
73371 
73372 #define S_ADR16_2_POPULATED    13
73373 #define V_ADR16_2_POPULATED(x) ((x) << S_ADR16_2_POPULATED)
73374 #define F_ADR16_2_POPULATED    V_ADR16_2_POPULATED(1U)
73375 
73376 #define S_ADR16_3_POPULATED    12
73377 #define V_ADR16_3_POPULATED(x) ((x) << S_ADR16_3_POPULATED)
73378 #define F_ADR16_3_POPULATED    V_ADR16_3_POPULATED(1U)
73379 
73380 #define S_ADR12_0_POPULATED    7
73381 #define V_ADR12_0_POPULATED(x) ((x) << S_ADR12_0_POPULATED)
73382 #define F_ADR12_0_POPULATED    V_ADR12_0_POPULATED(1U)
73383 
73384 #define S_ADR12_1_POPULATED    6
73385 #define V_ADR12_1_POPULATED(x) ((x) << S_ADR12_1_POPULATED)
73386 #define F_ADR12_1_POPULATED    V_ADR12_1_POPULATED(1U)
73387 
73388 #define S_ADR12_2_POPULATED    5
73389 #define V_ADR12_2_POPULATED(x) ((x) << S_ADR12_2_POPULATED)
73390 #define F_ADR12_2_POPULATED    V_ADR12_2_POPULATED(1U)
73391 
73392 #define S_ADR12_3_POPULATED    4
73393 #define V_ADR12_3_POPULATED(x) ((x) << S_ADR12_3_POPULATED)
73394 #define F_ADR12_3_POPULATED    V_ADR12_3_POPULATED(1U)
73395 
73396 #define A_MC_DDRPHY_APB_ATEST_MUX_SEL 0x47814
73397 
73398 #define S_ATEST_CNTL    10
73399 #define M_ATEST_CNTL    0x3fU
73400 #define V_ATEST_CNTL(x) ((x) << S_ATEST_CNTL)
73401 #define G_ATEST_CNTL(x) (((x) >> S_ATEST_CNTL) & M_ATEST_CNTL)
73402 
73403 #define A_MC_DDRPHY_APB_MTCTL_REG0 0x47820
73404 
73405 #define S_MT_DATA_MUX4_1MODE    15
73406 #define V_MT_DATA_MUX4_1MODE(x) ((x) << S_MT_DATA_MUX4_1MODE)
73407 #define F_MT_DATA_MUX4_1MODE    V_MT_DATA_MUX4_1MODE(1U)
73408 
73409 #define S_MT_PLL_RESET    14
73410 #define V_MT_PLL_RESET(x) ((x) << S_MT_PLL_RESET)
73411 #define F_MT_PLL_RESET    V_MT_PLL_RESET(1U)
73412 
73413 #define S_MT_SYSCLK_RESET    13
73414 #define V_MT_SYSCLK_RESET(x) ((x) << S_MT_SYSCLK_RESET)
73415 #define F_MT_SYSCLK_RESET    V_MT_SYSCLK_RESET(1U)
73416 
73417 #define S_MT_GLOBAL_PHY_OFFSET    9
73418 #define M_MT_GLOBAL_PHY_OFFSET    0xfU
73419 #define V_MT_GLOBAL_PHY_OFFSET(x) ((x) << S_MT_GLOBAL_PHY_OFFSET)
73420 #define G_MT_GLOBAL_PHY_OFFSET(x) (((x) >> S_MT_GLOBAL_PHY_OFFSET) & M_MT_GLOBAL_PHY_OFFSET)
73421 
73422 #define S_MT_DQ_SEL_QUAD    7
73423 #define M_MT_DQ_SEL_QUAD    0x3U
73424 #define V_MT_DQ_SEL_QUAD(x) ((x) << S_MT_DQ_SEL_QUAD)
73425 #define G_MT_DQ_SEL_QUAD(x) (((x) >> S_MT_DQ_SEL_QUAD) & M_MT_DQ_SEL_QUAD)
73426 
73427 #define S_MT_PERFORM_RDCLK_ALIGN    6
73428 #define V_MT_PERFORM_RDCLK_ALIGN(x) ((x) << S_MT_PERFORM_RDCLK_ALIGN)
73429 #define F_MT_PERFORM_RDCLK_ALIGN    V_MT_PERFORM_RDCLK_ALIGN(1U)
73430 
73431 #define S_MT_ALIGN_ON_EVEN_CYCLES    5
73432 #define V_MT_ALIGN_ON_EVEN_CYCLES(x) ((x) << S_MT_ALIGN_ON_EVEN_CYCLES)
73433 #define F_MT_ALIGN_ON_EVEN_CYCLES    V_MT_ALIGN_ON_EVEN_CYCLES(1U)
73434 
73435 #define S_MT_WRCLK_CAL_START    4
73436 #define V_MT_WRCLK_CAL_START(x) ((x) << S_MT_WRCLK_CAL_START)
73437 #define F_MT_WRCLK_CAL_START    V_MT_WRCLK_CAL_START(1U)
73438 
73439 #define A_MC_DDRPHY_APB_MTCTL_REG1 0x47824
73440 
73441 #define S_MT_WPRD_ENABLE    15
73442 #define V_MT_WPRD_ENABLE(x) ((x) << S_MT_WPRD_ENABLE)
73443 #define F_MT_WPRD_ENABLE    V_MT_WPRD_ENABLE(1U)
73444 
73445 #define S_MT_PVTP    10
73446 #define M_MT_PVTP    0x1fU
73447 #define V_MT_PVTP(x) ((x) << S_MT_PVTP)
73448 #define G_MT_PVTP(x) (((x) >> S_MT_PVTP) & M_MT_PVTP)
73449 
73450 #define S_MT_PVTN    5
73451 #define M_MT_PVTN    0x1fU
73452 #define V_MT_PVTN(x) ((x) << S_MT_PVTN)
73453 #define G_MT_PVTN(x) (((x) >> S_MT_PVTN) & M_MT_PVTN)
73454 
73455 #define A_MC_DDRPHY_APB_MTSTAT_REG0 0x47828
73456 #define A_MC_DDRPHY_APB_MTSTAT_REG1 0x4782c
73457 
73458 #define S_MT_ADR32_PLL_LOCK_SUM    1
73459 #define V_MT_ADR32_PLL_LOCK_SUM(x) ((x) << S_MT_ADR32_PLL_LOCK_SUM)
73460 #define F_MT_ADR32_PLL_LOCK_SUM    V_MT_ADR32_PLL_LOCK_SUM(1U)
73461 
73462 #define S_MT_DP18_PLL_LOCK_SUM    0
73463 #define V_MT_DP18_PLL_LOCK_SUM(x) ((x) << S_MT_DP18_PLL_LOCK_SUM)
73464 #define F_MT_DP18_PLL_LOCK_SUM    V_MT_DP18_PLL_LOCK_SUM(1U)
73465 
73466 /* registers for module MC_1 */
73467 #define MC_1_BASE_ADDR 0x48000
73468 
73469 /* registers for module EDC_T50 */
73470 #define EDC_T50_BASE_ADDR 0x50000
73471 
73472 #define A_EDC_H_REF 0x50000
73473 
73474 #define S_EDC_SLEEPSTATUS    31
73475 #define V_EDC_SLEEPSTATUS(x) ((x) << S_EDC_SLEEPSTATUS)
73476 #define F_EDC_SLEEPSTATUS    V_EDC_SLEEPSTATUS(1U)
73477 
73478 #define S_EDC_SLEEPREQ    30
73479 #define V_EDC_SLEEPREQ(x) ((x) << S_EDC_SLEEPREQ)
73480 #define F_EDC_SLEEPREQ    V_EDC_SLEEPREQ(1U)
73481 
73482 #define S_PING_PONG    29
73483 #define V_PING_PONG(x) ((x) << S_PING_PONG)
73484 #define F_PING_PONG    V_PING_PONG(1U)
73485 
73486 #define A_EDC_H_BIST_CMD 0x50004
73487 #define A_EDC_H_BIST_CMD_ADDR 0x50008
73488 #define A_EDC_H_BIST_CMD_LEN 0x5000c
73489 #define A_EDC_H_BIST_DATA_PATTERN 0x50010
73490 #define A_EDC_H_BIST_USER_WDATA0 0x50014
73491 #define A_EDC_H_BIST_USER_WDATA1 0x50018
73492 #define A_EDC_H_BIST_USER_WDATA2 0x5001c
73493 #define A_EDC_H_BIST_NUM_ERR 0x50020
73494 #define A_EDC_H_BIST_ERR_FIRST_ADDR 0x50024
73495 #define A_EDC_H_BIST_STATUS_RDATA 0x50028
73496 #define A_EDC_H_PAR_ENABLE 0x50070
73497 
73498 #define S_PERR_PAR_ENABLE    0
73499 #define V_PERR_PAR_ENABLE(x) ((x) << S_PERR_PAR_ENABLE)
73500 #define F_PERR_PAR_ENABLE    V_PERR_PAR_ENABLE(1U)
73501 
73502 #define A_EDC_H_INT_ENABLE 0x50074
73503 #define A_EDC_H_INT_CAUSE 0x50078
73504 
73505 #define S_ECC_UE_INT0_CAUSE    5
73506 #define V_ECC_UE_INT0_CAUSE(x) ((x) << S_ECC_UE_INT0_CAUSE)
73507 #define F_ECC_UE_INT0_CAUSE    V_ECC_UE_INT0_CAUSE(1U)
73508 
73509 #define S_ECC_CE_INT0_CAUSE    4
73510 #define V_ECC_CE_INT0_CAUSE(x) ((x) << S_ECC_CE_INT0_CAUSE)
73511 #define F_ECC_CE_INT0_CAUSE    V_ECC_CE_INT0_CAUSE(1U)
73512 
73513 #define S_PERR_INT0_CAUSE    3
73514 #define V_PERR_INT0_CAUSE(x) ((x) << S_PERR_INT0_CAUSE)
73515 #define F_PERR_INT0_CAUSE    V_PERR_INT0_CAUSE(1U)
73516 
73517 #define A_EDC_H_ECC_STATUS 0x5007c
73518 #define A_EDC_H_ECC_ERR_SEL 0x50080
73519 
73520 #define S_CFG    0
73521 #define M_CFG    0x3U
73522 #define V_CFG(x) ((x) << S_CFG)
73523 #define G_CFG(x) (((x) >> S_CFG) & M_CFG)
73524 
73525 #define A_EDC_H_ECC_ERR_ADDR 0x50084
73526 
73527 #define S_ECC_ADDR    0
73528 #define M_ECC_ADDR    0x7fffffU
73529 #define V_ECC_ADDR(x) ((x) << S_ECC_ADDR)
73530 #define G_ECC_ADDR(x) (((x) >> S_ECC_ADDR) & M_ECC_ADDR)
73531 
73532 #define A_EDC_H_ECC_ERR_DATA_RDATA 0x50090
73533 #define A_EDC_H_BIST_CRC_SEED 0x50400
73534 
73535 /* registers for module EDC_T51 */
73536 #define EDC_T51_BASE_ADDR 0x50800
73537 
73538 /* registers for module HMA_T5 */
73539 #define HMA_T5_BASE_ADDR 0x51000
73540 
73541 #define A_HMA_TABLE_ACCESS 0x51000
73542 
73543 #define S_TRIG    31
73544 #define V_TRIG(x) ((x) << S_TRIG)
73545 #define F_TRIG    V_TRIG(1U)
73546 
73547 #define S_RW    30
73548 #define V_RW(x) ((x) << S_RW)
73549 #define F_RW    V_RW(1U)
73550 
73551 #define S_L_SEL    0
73552 #define M_L_SEL    0xfU
73553 #define V_L_SEL(x) ((x) << S_L_SEL)
73554 #define G_L_SEL(x) (((x) >> S_L_SEL) & M_L_SEL)
73555 
73556 #define A_HMA_TABLE_LINE0 0x51004
73557 
73558 #define S_CLIENT_EN    0
73559 #define M_CLIENT_EN    0x1fffU
73560 #define V_CLIENT_EN(x) ((x) << S_CLIENT_EN)
73561 #define G_CLIENT_EN(x) (((x) >> S_CLIENT_EN) & M_CLIENT_EN)
73562 
73563 #define A_HMA_TABLE_LINE1 0x51008
73564 #define A_HMA_TABLE_LINE2 0x5100c
73565 #define A_HMA_TABLE_LINE3 0x51010
73566 #define A_HMA_TABLE_LINE4 0x51014
73567 #define A_HMA_TABLE_LINE5 0x51018
73568 
73569 #define S_FID    16
73570 #define M_FID    0x7ffU
73571 #define V_FID(x) ((x) << S_FID)
73572 #define G_FID(x) (((x) >> S_FID) & M_FID)
73573 
73574 #define S_NOS    15
73575 #define V_NOS(x) ((x) << S_NOS)
73576 #define F_NOS    V_NOS(1U)
73577 
73578 #define S_RO    14
73579 #define V_RO(x) ((x) << S_RO)
73580 #define F_RO    V_RO(1U)
73581 
73582 #define A_HMA_COOKIE 0x5101c
73583 
73584 #define S_C_REQ    31
73585 #define V_C_REQ(x) ((x) << S_C_REQ)
73586 #define F_C_REQ    V_C_REQ(1U)
73587 
73588 #define S_C_FID    18
73589 #define M_C_FID    0x7ffU
73590 #define V_C_FID(x) ((x) << S_C_FID)
73591 #define G_C_FID(x) (((x) >> S_C_FID) & M_C_FID)
73592 
73593 #define S_C_VAL    8
73594 #define M_C_VAL    0x3ffU
73595 #define V_C_VAL(x) ((x) << S_C_VAL)
73596 #define G_C_VAL(x) (((x) >> S_C_VAL) & M_C_VAL)
73597 
73598 #define S_C_SEL    0
73599 #define M_C_SEL    0xfU
73600 #define V_C_SEL(x) ((x) << S_C_SEL)
73601 #define G_C_SEL(x) (((x) >> S_C_SEL) & M_C_SEL)
73602 
73603 #define A_HMA_PAR_ENABLE 0x51300
73604 #define A_HMA_INT_ENABLE 0x51304
73605 #define A_HMA_INT_CAUSE 0x51308
73606 
73607 /* registers for module EDC_T60 */
73608 #define EDC_T60_BASE_ADDR 0x50000
73609 
73610 #define S_QDR_CLKPHASE    24
73611 #define M_QDR_CLKPHASE    0x7U
73612 #define V_QDR_CLKPHASE(x) ((x) << S_QDR_CLKPHASE)
73613 #define G_QDR_CLKPHASE(x) (((x) >> S_QDR_CLKPHASE) & M_QDR_CLKPHASE)
73614 
73615 #define S_MAXOPSPERTRC    21
73616 #define M_MAXOPSPERTRC    0x7U
73617 #define V_MAXOPSPERTRC(x) ((x) << S_MAXOPSPERTRC)
73618 #define G_MAXOPSPERTRC(x) (((x) >> S_MAXOPSPERTRC) & M_MAXOPSPERTRC)
73619 
73620 #define S_NUMPIPESTAGES    19
73621 #define M_NUMPIPESTAGES    0x3U
73622 #define V_NUMPIPESTAGES(x) ((x) << S_NUMPIPESTAGES)
73623 #define G_NUMPIPESTAGES(x) (((x) >> S_NUMPIPESTAGES) & M_NUMPIPESTAGES)
73624 
73625 #define S_DRAMREFENABLE    27
73626 #define M_DRAMREFENABLE    0x3U
73627 #define V_DRAMREFENABLE(x) ((x) << S_DRAMREFENABLE)
73628 #define G_DRAMREFENABLE(x) (((x) >> S_DRAMREFENABLE) & M_DRAMREFENABLE)
73629 
73630 #define A_EDC_H_DBG_MA_CMD_INTF 0x50300
73631 
73632 #define S_MCMDADDR    12
73633 #define M_MCMDADDR    0xfffffU
73634 #define V_MCMDADDR(x) ((x) << S_MCMDADDR)
73635 #define G_MCMDADDR(x) (((x) >> S_MCMDADDR) & M_MCMDADDR)
73636 
73637 #define S_MCMDLEN    5
73638 #define M_MCMDLEN    0x7fU
73639 #define V_MCMDLEN(x) ((x) << S_MCMDLEN)
73640 #define G_MCMDLEN(x) (((x) >> S_MCMDLEN) & M_MCMDLEN)
73641 
73642 #define S_MCMDNRE    4
73643 #define V_MCMDNRE(x) ((x) << S_MCMDNRE)
73644 #define F_MCMDNRE    V_MCMDNRE(1U)
73645 
73646 #define S_MCMDNRB    3
73647 #define V_MCMDNRB(x) ((x) << S_MCMDNRB)
73648 #define F_MCMDNRB    V_MCMDNRB(1U)
73649 
73650 #define S_MCMDWR    2
73651 #define V_MCMDWR(x) ((x) << S_MCMDWR)
73652 #define F_MCMDWR    V_MCMDWR(1U)
73653 
73654 #define S_MCMDRDY    1
73655 #define V_MCMDRDY(x) ((x) << S_MCMDRDY)
73656 #define F_MCMDRDY    V_MCMDRDY(1U)
73657 
73658 #define S_MCMDVLD    0
73659 #define V_MCMDVLD(x) ((x) << S_MCMDVLD)
73660 #define F_MCMDVLD    V_MCMDVLD(1U)
73661 
73662 #define A_EDC_H_DBG_MA_WDATA_INTF 0x50304
73663 
73664 #define S_MWDATAVLD    31
73665 #define V_MWDATAVLD(x) ((x) << S_MWDATAVLD)
73666 #define F_MWDATAVLD    V_MWDATAVLD(1U)
73667 
73668 #define S_MWDATARDY    30
73669 #define V_MWDATARDY(x) ((x) << S_MWDATARDY)
73670 #define F_MWDATARDY    V_MWDATARDY(1U)
73671 
73672 #define S_MWDATA    0
73673 #define M_MWDATA    0x3fffffffU
73674 #define V_MWDATA(x) ((x) << S_MWDATA)
73675 #define G_MWDATA(x) (((x) >> S_MWDATA) & M_MWDATA)
73676 
73677 #define A_EDC_H_DBG_MA_RDATA_INTF 0x50308
73678 
73679 #define S_MRSPVLD    31
73680 #define V_MRSPVLD(x) ((x) << S_MRSPVLD)
73681 #define F_MRSPVLD    V_MRSPVLD(1U)
73682 
73683 #define S_MRSPRDY    30
73684 #define V_MRSPRDY(x) ((x) << S_MRSPRDY)
73685 #define F_MRSPRDY    V_MRSPRDY(1U)
73686 
73687 #define S_MRSPDATA    0
73688 #define M_MRSPDATA    0x3fffffffU
73689 #define V_MRSPDATA(x) ((x) << S_MRSPDATA)
73690 #define G_MRSPDATA(x) (((x) >> S_MRSPDATA) & M_MRSPDATA)
73691 
73692 #define A_EDC_H_DBG_BIST_CMD_INTF 0x5030c
73693 
73694 #define S_BCMDADDR    9
73695 #define M_BCMDADDR    0x7fffffU
73696 #define V_BCMDADDR(x) ((x) << S_BCMDADDR)
73697 #define G_BCMDADDR(x) (((x) >> S_BCMDADDR) & M_BCMDADDR)
73698 
73699 #define S_BCMDLEN    3
73700 #define M_BCMDLEN    0x3fU
73701 #define V_BCMDLEN(x) ((x) << S_BCMDLEN)
73702 #define G_BCMDLEN(x) (((x) >> S_BCMDLEN) & M_BCMDLEN)
73703 
73704 #define S_BCMDWR    2
73705 #define V_BCMDWR(x) ((x) << S_BCMDWR)
73706 #define F_BCMDWR    V_BCMDWR(1U)
73707 
73708 #define S_BCMDRDY    1
73709 #define V_BCMDRDY(x) ((x) << S_BCMDRDY)
73710 #define F_BCMDRDY    V_BCMDRDY(1U)
73711 
73712 #define S_BCMDVLD    0
73713 #define V_BCMDVLD(x) ((x) << S_BCMDVLD)
73714 #define F_BCMDVLD    V_BCMDVLD(1U)
73715 
73716 #define A_EDC_H_DBG_BIST_WDATA_INTF 0x50310
73717 
73718 #define S_BWDATAVLD    31
73719 #define V_BWDATAVLD(x) ((x) << S_BWDATAVLD)
73720 #define F_BWDATAVLD    V_BWDATAVLD(1U)
73721 
73722 #define S_BWDATARDY    30
73723 #define V_BWDATARDY(x) ((x) << S_BWDATARDY)
73724 #define F_BWDATARDY    V_BWDATARDY(1U)
73725 
73726 #define S_BWDATA    0
73727 #define M_BWDATA    0x3fffffffU
73728 #define V_BWDATA(x) ((x) << S_BWDATA)
73729 #define G_BWDATA(x) (((x) >> S_BWDATA) & M_BWDATA)
73730 
73731 #define A_EDC_H_DBG_BIST_RDATA_INTF 0x50314
73732 
73733 #define S_BRSPVLD    31
73734 #define V_BRSPVLD(x) ((x) << S_BRSPVLD)
73735 #define F_BRSPVLD    V_BRSPVLD(1U)
73736 
73737 #define S_BRSPRDY    30
73738 #define V_BRSPRDY(x) ((x) << S_BRSPRDY)
73739 #define F_BRSPRDY    V_BRSPRDY(1U)
73740 
73741 #define S_BRSPDATA    0
73742 #define M_BRSPDATA    0x3fffffffU
73743 #define V_BRSPDATA(x) ((x) << S_BRSPDATA)
73744 #define G_BRSPDATA(x) (((x) >> S_BRSPDATA) & M_BRSPDATA)
73745 
73746 #define A_EDC_H_DBG_EDRAM_CMD_INTF 0x50318
73747 
73748 #define S_EDRAMADDR    16
73749 #define M_EDRAMADDR    0xffffU
73750 #define V_EDRAMADDR(x) ((x) << S_EDRAMADDR)
73751 #define G_EDRAMADDR(x) (((x) >> S_EDRAMADDR) & M_EDRAMADDR)
73752 
73753 #define S_EDRAMDWSN    8
73754 #define M_EDRAMDWSN    0xffU
73755 #define V_EDRAMDWSN(x) ((x) << S_EDRAMDWSN)
73756 #define G_EDRAMDWSN(x) (((x) >> S_EDRAMDWSN) & M_EDRAMDWSN)
73757 
73758 #define S_EDRAMCRA    5
73759 #define M_EDRAMCRA    0x7U
73760 #define V_EDRAMCRA(x) ((x) << S_EDRAMCRA)
73761 #define G_EDRAMCRA(x) (((x) >> S_EDRAMCRA) & M_EDRAMCRA)
73762 
73763 #define S_EDRAMREFENLO    4
73764 #define V_EDRAMREFENLO(x) ((x) << S_EDRAMREFENLO)
73765 #define F_EDRAMREFENLO    V_EDRAMREFENLO(1U)
73766 
73767 #define S_EDRAM1WRENLO    3
73768 #define V_EDRAM1WRENLO(x) ((x) << S_EDRAM1WRENLO)
73769 #define F_EDRAM1WRENLO    V_EDRAM1WRENLO(1U)
73770 
73771 #define S_EDRAM1RDENLO    2
73772 #define V_EDRAM1RDENLO(x) ((x) << S_EDRAM1RDENLO)
73773 #define F_EDRAM1RDENLO    V_EDRAM1RDENLO(1U)
73774 
73775 #define S_EDRAM0WRENLO    1
73776 #define V_EDRAM0WRENLO(x) ((x) << S_EDRAM0WRENLO)
73777 #define F_EDRAM0WRENLO    V_EDRAM0WRENLO(1U)
73778 
73779 #define S_EDRAM0RDENLO    0
73780 #define V_EDRAM0RDENLO(x) ((x) << S_EDRAM0RDENLO)
73781 #define F_EDRAM0RDENLO    V_EDRAM0RDENLO(1U)
73782 
73783 #define A_EDC_H_DBG_EDRAM_WDATA_INTF 0x5031c
73784 
73785 #define S_EDRAMWDATA    9
73786 #define M_EDRAMWDATA    0x7fffffU
73787 #define V_EDRAMWDATA(x) ((x) << S_EDRAMWDATA)
73788 #define G_EDRAMWDATA(x) (((x) >> S_EDRAMWDATA) & M_EDRAMWDATA)
73789 
73790 #define S_EDRAMWBYTEEN    0
73791 #define M_EDRAMWBYTEEN    0x1ffU
73792 #define V_EDRAMWBYTEEN(x) ((x) << S_EDRAMWBYTEEN)
73793 #define G_EDRAMWBYTEEN(x) (((x) >> S_EDRAMWBYTEEN) & M_EDRAMWBYTEEN)
73794 
73795 #define A_EDC_H_DBG_EDRAM0_RDATA_INTF 0x50320
73796 #define A_EDC_H_DBG_EDRAM1_RDATA_INTF 0x50324
73797 #define A_EDC_H_DBG_MA_WR_REQ_CNT 0x50328
73798 #define A_EDC_H_DBG_MA_WR_EXP_DAT_CYC_CNT 0x5032c
73799 #define A_EDC_H_DBG_MA_WR_DAT_CYC_CNT 0x50330
73800 #define A_EDC_H_DBG_MA_RD_REQ_CNT 0x50334
73801 #define A_EDC_H_DBG_MA_RD_EXP_DAT_CYC_CNT 0x50338
73802 #define A_EDC_H_DBG_MA_RD_DAT_CYC_CNT 0x5033c
73803 #define A_EDC_H_DBG_BIST_WR_REQ_CNT 0x50340
73804 #define A_EDC_H_DBG_BIST_WR_EXP_DAT_CYC_CNT 0x50344
73805 #define A_EDC_H_DBG_BIST_WR_DAT_CYC_CNT 0x50348
73806 #define A_EDC_H_DBG_BIST_RD_REQ_CNT 0x5034c
73807 #define A_EDC_H_DBG_BIST_RD_EXP_DAT_CYC_CNT 0x50350
73808 #define A_EDC_H_DBG_BIST_RD_DAT_CYC_CNT 0x50354
73809 #define A_EDC_H_DBG_EDRAM0_WR_REQ_CNT 0x50358
73810 #define A_EDC_H_DBG_EDRAM0_RD_REQ_CNT 0x5035c
73811 #define A_EDC_H_DBG_EDRAM0_RMW_CNT 0x50360
73812 #define A_EDC_H_DBG_EDRAM1_WR_REQ_CNT 0x50364
73813 #define A_EDC_H_DBG_EDRAM1_RD_REQ_CNT 0x50368
73814 #define A_EDC_H_DBG_EDRAM1_RMW_CNT 0x5036c
73815 #define A_EDC_H_DBG_EDRAM_REF_BURST_CNT 0x50370
73816 #define A_EDC_H_DBG_FIFO_STATUS 0x50374
73817 
73818 #define S_RDTAG_NOTFULL    17
73819 #define V_RDTAG_NOTFULL(x) ((x) << S_RDTAG_NOTFULL)
73820 #define F_RDTAG_NOTFULL    V_RDTAG_NOTFULL(1U)
73821 
73822 #define S_RDTAG_NOTEMPTY    16
73823 #define V_RDTAG_NOTEMPTY(x) ((x) << S_RDTAG_NOTEMPTY)
73824 #define F_RDTAG_NOTEMPTY    V_RDTAG_NOTEMPTY(1U)
73825 
73826 #define S_INP_CMDQ_NOTFULL_ARB    15
73827 #define V_INP_CMDQ_NOTFULL_ARB(x) ((x) << S_INP_CMDQ_NOTFULL_ARB)
73828 #define F_INP_CMDQ_NOTFULL_ARB    V_INP_CMDQ_NOTFULL_ARB(1U)
73829 
73830 #define S_INP_CMDQ_NOTEMPTY    14
73831 #define V_INP_CMDQ_NOTEMPTY(x) ((x) << S_INP_CMDQ_NOTEMPTY)
73832 #define F_INP_CMDQ_NOTEMPTY    V_INP_CMDQ_NOTEMPTY(1U)
73833 
73834 #define S_INP_WRDQ_WRRDY    13
73835 #define V_INP_WRDQ_WRRDY(x) ((x) << S_INP_WRDQ_WRRDY)
73836 #define F_INP_WRDQ_WRRDY    V_INP_WRDQ_WRRDY(1U)
73837 
73838 #define S_INP_WRDQ_NOTEMPTY    12
73839 #define V_INP_WRDQ_NOTEMPTY(x) ((x) << S_INP_WRDQ_NOTEMPTY)
73840 #define F_INP_WRDQ_NOTEMPTY    V_INP_WRDQ_NOTEMPTY(1U)
73841 
73842 #define S_INP_BEQ_WRRDY_OPEN    11
73843 #define V_INP_BEQ_WRRDY_OPEN(x) ((x) << S_INP_BEQ_WRRDY_OPEN)
73844 #define F_INP_BEQ_WRRDY_OPEN    V_INP_BEQ_WRRDY_OPEN(1U)
73845 
73846 #define S_INP_BEQ_NOTEMPTY    10
73847 #define V_INP_BEQ_NOTEMPTY(x) ((x) << S_INP_BEQ_NOTEMPTY)
73848 #define F_INP_BEQ_NOTEMPTY    V_INP_BEQ_NOTEMPTY(1U)
73849 
73850 #define S_RDDQ_NOTFULL_OPEN    9
73851 #define V_RDDQ_NOTFULL_OPEN(x) ((x) << S_RDDQ_NOTFULL_OPEN)
73852 #define F_RDDQ_NOTFULL_OPEN    V_RDDQ_NOTFULL_OPEN(1U)
73853 
73854 #define S_RDDQ_RDCNT    4
73855 #define M_RDDQ_RDCNT    0x1fU
73856 #define V_RDDQ_RDCNT(x) ((x) << S_RDDQ_RDCNT)
73857 #define G_RDDQ_RDCNT(x) (((x) >> S_RDDQ_RDCNT) & M_RDDQ_RDCNT)
73858 
73859 #define S_RDSIDEQ_NOTFULL    3
73860 #define V_RDSIDEQ_NOTFULL(x) ((x) << S_RDSIDEQ_NOTFULL)
73861 #define F_RDSIDEQ_NOTFULL    V_RDSIDEQ_NOTFULL(1U)
73862 
73863 #define S_RDSIDEQ_NOTEMPTY    2
73864 #define V_RDSIDEQ_NOTEMPTY(x) ((x) << S_RDSIDEQ_NOTEMPTY)
73865 #define F_RDSIDEQ_NOTEMPTY    V_RDSIDEQ_NOTEMPTY(1U)
73866 
73867 #define S_STG_CMDQ_NOTEMPTY    1
73868 #define V_STG_CMDQ_NOTEMPTY(x) ((x) << S_STG_CMDQ_NOTEMPTY)
73869 #define F_STG_CMDQ_NOTEMPTY    V_STG_CMDQ_NOTEMPTY(1U)
73870 
73871 #define S_STG_WRDQ_NOTEMPTY    0
73872 #define V_STG_WRDQ_NOTEMPTY(x) ((x) << S_STG_WRDQ_NOTEMPTY)
73873 #define F_STG_WRDQ_NOTEMPTY    V_STG_WRDQ_NOTEMPTY(1U)
73874 
73875 #define A_EDC_H_DBG_FSM_STATE 0x50378
73876 
73877 #define S_CMDSPLITFSM    3
73878 #define V_CMDSPLITFSM(x) ((x) << S_CMDSPLITFSM)
73879 #define F_CMDSPLITFSM    V_CMDSPLITFSM(1U)
73880 
73881 #define S_CMDFSM    0
73882 #define M_CMDFSM    0x7U
73883 #define V_CMDFSM(x) ((x) << S_CMDFSM)
73884 #define G_CMDFSM(x) (((x) >> S_CMDFSM) & M_CMDFSM)
73885 
73886 #define A_EDC_H_DBG_STALL_CYCLES 0x5037c
73887 
73888 #define S_STALL_RMW    19
73889 #define V_STALL_RMW(x) ((x) << S_STALL_RMW)
73890 #define F_STALL_RMW    V_STALL_RMW(1U)
73891 
73892 #define S_STALL_EDC_CMD    18
73893 #define V_STALL_EDC_CMD(x) ((x) << S_STALL_EDC_CMD)
73894 #define F_STALL_EDC_CMD    V_STALL_EDC_CMD(1U)
73895 
73896 #define S_DEAD_CYCLE0    17
73897 #define V_DEAD_CYCLE0(x) ((x) << S_DEAD_CYCLE0)
73898 #define F_DEAD_CYCLE0    V_DEAD_CYCLE0(1U)
73899 
73900 #define S_DEAD_CYCLE1    16
73901 #define V_DEAD_CYCLE1(x) ((x) << S_DEAD_CYCLE1)
73902 #define F_DEAD_CYCLE1    V_DEAD_CYCLE1(1U)
73903 
73904 #define S_DEAD_CYCLE0_BBI    15
73905 #define V_DEAD_CYCLE0_BBI(x) ((x) << S_DEAD_CYCLE0_BBI)
73906 #define F_DEAD_CYCLE0_BBI    V_DEAD_CYCLE0_BBI(1U)
73907 
73908 #define S_DEAD_CYCLE1_BBI    14
73909 #define V_DEAD_CYCLE1_BBI(x) ((x) << S_DEAD_CYCLE1_BBI)
73910 #define F_DEAD_CYCLE1_BBI    V_DEAD_CYCLE1_BBI(1U)
73911 
73912 #define S_DEAD_CYCLE0_MAX_OP    13
73913 #define V_DEAD_CYCLE0_MAX_OP(x) ((x) << S_DEAD_CYCLE0_MAX_OP)
73914 #define F_DEAD_CYCLE0_MAX_OP    V_DEAD_CYCLE0_MAX_OP(1U)
73915 
73916 #define S_DEAD_CYCLE1_MAX_OP    12
73917 #define V_DEAD_CYCLE1_MAX_OP(x) ((x) << S_DEAD_CYCLE1_MAX_OP)
73918 #define F_DEAD_CYCLE1_MAX_OP    V_DEAD_CYCLE1_MAX_OP(1U)
73919 
73920 #define S_DEAD_CYCLE0_PRE_REF    11
73921 #define V_DEAD_CYCLE0_PRE_REF(x) ((x) << S_DEAD_CYCLE0_PRE_REF)
73922 #define F_DEAD_CYCLE0_PRE_REF    V_DEAD_CYCLE0_PRE_REF(1U)
73923 
73924 #define S_DEAD_CYCLE1_PRE_REF    10
73925 #define V_DEAD_CYCLE1_PRE_REF(x) ((x) << S_DEAD_CYCLE1_PRE_REF)
73926 #define F_DEAD_CYCLE1_PRE_REF    V_DEAD_CYCLE1_PRE_REF(1U)
73927 
73928 #define S_DEAD_CYCLE0_POST_REF    9
73929 #define V_DEAD_CYCLE0_POST_REF(x) ((x) << S_DEAD_CYCLE0_POST_REF)
73930 #define F_DEAD_CYCLE0_POST_REF    V_DEAD_CYCLE0_POST_REF(1U)
73931 
73932 #define S_DEAD_CYCLE1_POST_REF    8
73933 #define V_DEAD_CYCLE1_POST_REF(x) ((x) << S_DEAD_CYCLE1_POST_REF)
73934 #define F_DEAD_CYCLE1_POST_REF    V_DEAD_CYCLE1_POST_REF(1U)
73935 
73936 #define S_DEAD_CYCLE0_RMW    7
73937 #define V_DEAD_CYCLE0_RMW(x) ((x) << S_DEAD_CYCLE0_RMW)
73938 #define F_DEAD_CYCLE0_RMW    V_DEAD_CYCLE0_RMW(1U)
73939 
73940 #define S_DEAD_CYCLE1_RMW    6
73941 #define V_DEAD_CYCLE1_RMW(x) ((x) << S_DEAD_CYCLE1_RMW)
73942 #define F_DEAD_CYCLE1_RMW    V_DEAD_CYCLE1_RMW(1U)
73943 
73944 #define S_DEAD_CYCLE0_BBI_RMW    5
73945 #define V_DEAD_CYCLE0_BBI_RMW(x) ((x) << S_DEAD_CYCLE0_BBI_RMW)
73946 #define F_DEAD_CYCLE0_BBI_RMW    V_DEAD_CYCLE0_BBI_RMW(1U)
73947 
73948 #define S_DEAD_CYCLE1_BBI_RMW    4
73949 #define V_DEAD_CYCLE1_BBI_RMW(x) ((x) << S_DEAD_CYCLE1_BBI_RMW)
73950 #define F_DEAD_CYCLE1_BBI_RMW    V_DEAD_CYCLE1_BBI_RMW(1U)
73951 
73952 #define S_DEAD_CYCLE0_PRE_REF_RMW    3
73953 #define V_DEAD_CYCLE0_PRE_REF_RMW(x) ((x) << S_DEAD_CYCLE0_PRE_REF_RMW)
73954 #define F_DEAD_CYCLE0_PRE_REF_RMW    V_DEAD_CYCLE0_PRE_REF_RMW(1U)
73955 
73956 #define S_DEAD_CYCLE1_PRE_REF_RMW    2
73957 #define V_DEAD_CYCLE1_PRE_REF_RMW(x) ((x) << S_DEAD_CYCLE1_PRE_REF_RMW)
73958 #define F_DEAD_CYCLE1_PRE_REF_RMW    V_DEAD_CYCLE1_PRE_REF_RMW(1U)
73959 
73960 #define S_DEAD_CYCLE0_POST_REF_RMW    1
73961 #define V_DEAD_CYCLE0_POST_REF_RMW(x) ((x) << S_DEAD_CYCLE0_POST_REF_RMW)
73962 #define F_DEAD_CYCLE0_POST_REF_RMW    V_DEAD_CYCLE0_POST_REF_RMW(1U)
73963 
73964 #define S_DEAD_CYCLE1_POST_REF_RMW    0
73965 #define V_DEAD_CYCLE1_POST_REF_RMW(x) ((x) << S_DEAD_CYCLE1_POST_REF_RMW)
73966 #define F_DEAD_CYCLE1_POST_REF_RMW    V_DEAD_CYCLE1_POST_REF_RMW(1U)
73967 
73968 #define A_EDC_H_DBG_CMD_QUEUE 0x50380
73969 
73970 #define S_ECMDNRE    31
73971 #define V_ECMDNRE(x) ((x) << S_ECMDNRE)
73972 #define F_ECMDNRE    V_ECMDNRE(1U)
73973 
73974 #define S_ECMDNRB    30
73975 #define V_ECMDNRB(x) ((x) << S_ECMDNRB)
73976 #define F_ECMDNRB    V_ECMDNRB(1U)
73977 
73978 #define S_ECMDWR    29
73979 #define V_ECMDWR(x) ((x) << S_ECMDWR)
73980 #define F_ECMDWR    V_ECMDWR(1U)
73981 
73982 #define S_ECMDLEN    22
73983 #define M_ECMDLEN    0x7fU
73984 #define V_ECMDLEN(x) ((x) << S_ECMDLEN)
73985 #define G_ECMDLEN(x) (((x) >> S_ECMDLEN) & M_ECMDLEN)
73986 
73987 #define S_ECMDADDR    0
73988 #define M_ECMDADDR    0x3fffffU
73989 #define V_ECMDADDR(x) ((x) << S_ECMDADDR)
73990 #define G_ECMDADDR(x) (((x) >> S_ECMDADDR) & M_ECMDADDR)
73991 
73992 #define A_EDC_H_DBG_REFRESH 0x50384
73993 
73994 #define S_REFDONE    12
73995 #define V_REFDONE(x) ((x) << S_REFDONE)
73996 #define F_REFDONE    V_REFDONE(1U)
73997 
73998 #define S_REFCNTEXPR    11
73999 #define V_REFCNTEXPR(x) ((x) << S_REFCNTEXPR)
74000 #define F_REFCNTEXPR    V_REFCNTEXPR(1U)
74001 
74002 #define S_REFPTR    8
74003 #define M_REFPTR    0x7U
74004 #define V_REFPTR(x) ((x) << S_REFPTR)
74005 #define G_REFPTR(x) (((x) >> S_REFPTR) & M_REFPTR)
74006 
74007 #define S_REFCNT    0
74008 #define M_REFCNT    0xffU
74009 #define V_REFCNT(x) ((x) << S_REFCNT)
74010 #define G_REFCNT(x) (((x) >> S_REFCNT) & M_REFCNT)
74011 
74012 #define A_EDC_H_PAR_CAUSE 0x50404
74013 
74014 #define S_STG_CMDQ_PARERR_CAUSE    7
74015 #define V_STG_CMDQ_PARERR_CAUSE(x) ((x) << S_STG_CMDQ_PARERR_CAUSE)
74016 #define F_STG_CMDQ_PARERR_CAUSE    V_STG_CMDQ_PARERR_CAUSE(1U)
74017 
74018 #define S_STG_WRDQ_PARERR_CAUSE    6
74019 #define V_STG_WRDQ_PARERR_CAUSE(x) ((x) << S_STG_WRDQ_PARERR_CAUSE)
74020 #define F_STG_WRDQ_PARERR_CAUSE    V_STG_WRDQ_PARERR_CAUSE(1U)
74021 
74022 #define S_INP_CMDQ_PARERR_CAUSE    5
74023 #define V_INP_CMDQ_PARERR_CAUSE(x) ((x) << S_INP_CMDQ_PARERR_CAUSE)
74024 #define F_INP_CMDQ_PARERR_CAUSE    V_INP_CMDQ_PARERR_CAUSE(1U)
74025 
74026 #define S_INP_WRDQ_PARERR_CAUSE    4
74027 #define V_INP_WRDQ_PARERR_CAUSE(x) ((x) << S_INP_WRDQ_PARERR_CAUSE)
74028 #define F_INP_WRDQ_PARERR_CAUSE    V_INP_WRDQ_PARERR_CAUSE(1U)
74029 
74030 #define S_INP_BEQ_PARERR_CAUSE    3
74031 #define V_INP_BEQ_PARERR_CAUSE(x) ((x) << S_INP_BEQ_PARERR_CAUSE)
74032 #define F_INP_BEQ_PARERR_CAUSE    V_INP_BEQ_PARERR_CAUSE(1U)
74033 
74034 #define S_ECC_CE_PAR_ENABLE_CAUSE    2
74035 #define V_ECC_CE_PAR_ENABLE_CAUSE(x) ((x) << S_ECC_CE_PAR_ENABLE_CAUSE)
74036 #define F_ECC_CE_PAR_ENABLE_CAUSE    V_ECC_CE_PAR_ENABLE_CAUSE(1U)
74037 
74038 #define S_ECC_UE_PAR_ENABLE_CAUSE    1
74039 #define V_ECC_UE_PAR_ENABLE_CAUSE(x) ((x) << S_ECC_UE_PAR_ENABLE_CAUSE)
74040 #define F_ECC_UE_PAR_ENABLE_CAUSE    V_ECC_UE_PAR_ENABLE_CAUSE(1U)
74041 
74042 #define S_RDDQ_PARERR_CAUSE    0
74043 #define V_RDDQ_PARERR_CAUSE(x) ((x) << S_RDDQ_PARERR_CAUSE)
74044 #define F_RDDQ_PARERR_CAUSE    V_RDDQ_PARERR_CAUSE(1U)
74045 
74046 /* registers for module EDC_T61 */
74047 #define EDC_T61_BASE_ADDR 0x50800
74048 
74049 /* registers for module HMA_T6 */
74050 #define HMA_T6_BASE_ADDR 0x51000
74051 
74052 #define S_T7_CLIENT_EN    0
74053 #define M_T7_CLIENT_EN    0x7fffU
74054 #define V_T7_CLIENT_EN(x) ((x) << S_T7_CLIENT_EN)
74055 #define G_T7_CLIENT_EN(x) (((x) >> S_T7_CLIENT_EN) & M_T7_CLIENT_EN)
74056 
74057 #define S_TPH    12
74058 #define M_TPH    0x3U
74059 #define V_TPH(x) ((x) << S_TPH)
74060 #define G_TPH(x) (((x) >> S_TPH) & M_TPH)
74061 
74062 #define S_TPH_V    11
74063 #define V_TPH_V(x) ((x) << S_TPH_V)
74064 #define F_TPH_V    V_TPH_V(1U)
74065 
74066 #define S_DCA    0
74067 #define M_DCA    0x7ffU
74068 #define V_DCA(x) ((x) << S_DCA)
74069 #define G_DCA(x) (((x) >> S_DCA) & M_DCA)
74070 
74071 #define A_HMA_CFG 0x51020
74072 
74073 #define S_OP_MODE    31
74074 #define V_OP_MODE(x) ((x) << S_OP_MODE)
74075 #define F_OP_MODE    V_OP_MODE(1U)
74076 
74077 #define S_GK_ENABLE    30
74078 #define V_GK_ENABLE(x) ((x) << S_GK_ENABLE)
74079 #define F_GK_ENABLE    V_GK_ENABLE(1U)
74080 
74081 #define S_DBGCNTRST    29
74082 #define V_DBGCNTRST(x) ((x) << S_DBGCNTRST)
74083 #define F_DBGCNTRST    V_DBGCNTRST(1U)
74084 
74085 #define A_HMA_TLB_ACCESS 0x51028
74086 
74087 #define S_INV_ALL    29
74088 #define V_INV_ALL(x) ((x) << S_INV_ALL)
74089 #define F_INV_ALL    V_INV_ALL(1U)
74090 
74091 #define S_LOCK_ENTRY    28
74092 #define V_LOCK_ENTRY(x) ((x) << S_LOCK_ENTRY)
74093 #define F_LOCK_ENTRY    V_LOCK_ENTRY(1U)
74094 
74095 #define S_E_SEL    0
74096 #define M_E_SEL    0x1fU
74097 #define V_E_SEL(x) ((x) << S_E_SEL)
74098 #define G_E_SEL(x) (((x) >> S_E_SEL) & M_E_SEL)
74099 
74100 #define A_HMA_TLB_BITS 0x5102c
74101 
74102 #define S_VA    12
74103 #define M_VA    0xfffffU
74104 #define V_VA(x) ((x) << S_VA)
74105 #define G_VA(x) (((x) >> S_VA) & M_VA)
74106 
74107 #define S_VALID_E    4
74108 #define V_VALID_E(x) ((x) << S_VALID_E)
74109 #define F_VALID_E    V_VALID_E(1U)
74110 
74111 #define S_LOCK_HMA    3
74112 #define V_LOCK_HMA(x) ((x) << S_LOCK_HMA)
74113 #define F_LOCK_HMA    V_LOCK_HMA(1U)
74114 
74115 #define S_T6_USED    2
74116 #define V_T6_USED(x) ((x) << S_T6_USED)
74117 #define F_T6_USED    V_T6_USED(1U)
74118 
74119 #define S_REGION    0
74120 #define M_REGION    0x3U
74121 #define V_REGION(x) ((x) << S_REGION)
74122 #define G_REGION(x) (((x) >> S_REGION) & M_REGION)
74123 
74124 #define S_T7_VA    8
74125 #define M_T7_VA    0xffffffU
74126 #define V_T7_VA(x) ((x) << S_T7_VA)
74127 #define G_T7_VA(x) (((x) >> S_T7_VA) & M_T7_VA)
74128 
74129 #define A_HMA_TLB_DESC_0_H 0x51030
74130 #define A_HMA_TLB_DESC_0_L 0x51034
74131 #define A_HMA_TLB_DESC_1_H 0x51038
74132 #define A_HMA_TLB_DESC_1_L 0x5103c
74133 #define A_HMA_TLB_DESC_2_H 0x51040
74134 #define A_HMA_TLB_DESC_2_L 0x51044
74135 #define A_HMA_TLB_DESC_3_H 0x51048
74136 #define A_HMA_TLB_DESC_3_L 0x5104c
74137 #define A_HMA_TLB_DESC_4_H 0x51050
74138 #define A_HMA_TLB_DESC_4_L 0x51054
74139 #define A_HMA_TLB_DESC_5_H 0x51058
74140 #define A_HMA_TLB_DESC_5_L 0x5105c
74141 #define A_HMA_TLB_DESC_6_H 0x51060
74142 #define A_HMA_TLB_DESC_6_L 0x51064
74143 #define A_HMA_TLB_DESC_7_H 0x51068
74144 #define A_HMA_TLB_DESC_7_L 0x5106c
74145 #define A_HMA_REG0_MIN 0x51070
74146 
74147 #define S_ADDR0_MIN    12
74148 #define M_ADDR0_MIN    0xfffffU
74149 #define V_ADDR0_MIN(x) ((x) << S_ADDR0_MIN)
74150 #define G_ADDR0_MIN(x) (((x) >> S_ADDR0_MIN) & M_ADDR0_MIN)
74151 
74152 #define S_REG0MINADDR0MIN    8
74153 #define M_REG0MINADDR0MIN    0xffffffU
74154 #define V_REG0MINADDR0MIN(x) ((x) << S_REG0MINADDR0MIN)
74155 #define G_REG0MINADDR0MIN(x) (((x) >> S_REG0MINADDR0MIN) & M_REG0MINADDR0MIN)
74156 
74157 #define A_HMA_REG0_MAX 0x51074
74158 
74159 #define S_ADDR0_MAX    12
74160 #define M_ADDR0_MAX    0xfffffU
74161 #define V_ADDR0_MAX(x) ((x) << S_ADDR0_MAX)
74162 #define G_ADDR0_MAX(x) (((x) >> S_ADDR0_MAX) & M_ADDR0_MAX)
74163 
74164 #define S_REG0MAXADDR0MAX    8
74165 #define M_REG0MAXADDR0MAX    0xffffffU
74166 #define V_REG0MAXADDR0MAX(x) ((x) << S_REG0MAXADDR0MAX)
74167 #define G_REG0MAXADDR0MAX(x) (((x) >> S_REG0MAXADDR0MAX) & M_REG0MAXADDR0MAX)
74168 
74169 #define A_HMA_REG0_MASK 0x51078
74170 
74171 #define S_PAGE_SIZE0    12
74172 #define M_PAGE_SIZE0    0xfffffU
74173 #define V_PAGE_SIZE0(x) ((x) << S_PAGE_SIZE0)
74174 #define G_PAGE_SIZE0(x) (((x) >> S_PAGE_SIZE0) & M_PAGE_SIZE0)
74175 
74176 #define A_HMA_REG0_BASE 0x5107c
74177 #define A_HMA_REG0_BASE_LSB 0x5107c
74178 #define A_HMA_REG1_MIN 0x51080
74179 
74180 #define S_ADDR1_MIN    12
74181 #define M_ADDR1_MIN    0xfffffU
74182 #define V_ADDR1_MIN(x) ((x) << S_ADDR1_MIN)
74183 #define G_ADDR1_MIN(x) (((x) >> S_ADDR1_MIN) & M_ADDR1_MIN)
74184 
74185 #define S_REG1MINADDR1MIN    8
74186 #define M_REG1MINADDR1MIN    0xffffffU
74187 #define V_REG1MINADDR1MIN(x) ((x) << S_REG1MINADDR1MIN)
74188 #define G_REG1MINADDR1MIN(x) (((x) >> S_REG1MINADDR1MIN) & M_REG1MINADDR1MIN)
74189 
74190 #define A_HMA_REG1_MAX 0x51084
74191 
74192 #define S_ADDR1_MAX    12
74193 #define M_ADDR1_MAX    0xfffffU
74194 #define V_ADDR1_MAX(x) ((x) << S_ADDR1_MAX)
74195 #define G_ADDR1_MAX(x) (((x) >> S_ADDR1_MAX) & M_ADDR1_MAX)
74196 
74197 #define S_REG1MAXADDR1MAX    8
74198 #define M_REG1MAXADDR1MAX    0xffffffU
74199 #define V_REG1MAXADDR1MAX(x) ((x) << S_REG1MAXADDR1MAX)
74200 #define G_REG1MAXADDR1MAX(x) (((x) >> S_REG1MAXADDR1MAX) & M_REG1MAXADDR1MAX)
74201 
74202 #define A_HMA_REG1_MASK 0x51088
74203 
74204 #define S_PAGE_SIZE1    12
74205 #define M_PAGE_SIZE1    0xfffffU
74206 #define V_PAGE_SIZE1(x) ((x) << S_PAGE_SIZE1)
74207 #define G_PAGE_SIZE1(x) (((x) >> S_PAGE_SIZE1) & M_PAGE_SIZE1)
74208 
74209 #define A_HMA_REG1_BASE 0x5108c
74210 #define A_HMA_REG1_BASE_LSB 0x5108c
74211 #define A_HMA_REG2_MIN 0x51090
74212 
74213 #define S_ADDR2_MIN    12
74214 #define M_ADDR2_MIN    0xfffffU
74215 #define V_ADDR2_MIN(x) ((x) << S_ADDR2_MIN)
74216 #define G_ADDR2_MIN(x) (((x) >> S_ADDR2_MIN) & M_ADDR2_MIN)
74217 
74218 #define S_REG2MINADDR2MIN    8
74219 #define M_REG2MINADDR2MIN    0xffffffU
74220 #define V_REG2MINADDR2MIN(x) ((x) << S_REG2MINADDR2MIN)
74221 #define G_REG2MINADDR2MIN(x) (((x) >> S_REG2MINADDR2MIN) & M_REG2MINADDR2MIN)
74222 
74223 #define A_HMA_REG2_MAX 0x51094
74224 
74225 #define S_ADDR2_MAX    12
74226 #define M_ADDR2_MAX    0xfffffU
74227 #define V_ADDR2_MAX(x) ((x) << S_ADDR2_MAX)
74228 #define G_ADDR2_MAX(x) (((x) >> S_ADDR2_MAX) & M_ADDR2_MAX)
74229 
74230 #define S_REG2MAXADDR2MAX    8
74231 #define M_REG2MAXADDR2MAX    0xffffffU
74232 #define V_REG2MAXADDR2MAX(x) ((x) << S_REG2MAXADDR2MAX)
74233 #define G_REG2MAXADDR2MAX(x) (((x) >> S_REG2MAXADDR2MAX) & M_REG2MAXADDR2MAX)
74234 
74235 #define A_HMA_REG2_MASK 0x51098
74236 
74237 #define S_PAGE_SIZE2    12
74238 #define M_PAGE_SIZE2    0xfffffU
74239 #define V_PAGE_SIZE2(x) ((x) << S_PAGE_SIZE2)
74240 #define G_PAGE_SIZE2(x) (((x) >> S_PAGE_SIZE2) & M_PAGE_SIZE2)
74241 
74242 #define A_HMA_REG2_BASE 0x5109c
74243 #define A_HMA_REG2_BASE_LSB 0x5109c
74244 #define A_HMA_REG3_MIN 0x510a0
74245 
74246 #define S_ADDR3_MIN    12
74247 #define M_ADDR3_MIN    0xfffffU
74248 #define V_ADDR3_MIN(x) ((x) << S_ADDR3_MIN)
74249 #define G_ADDR3_MIN(x) (((x) >> S_ADDR3_MIN) & M_ADDR3_MIN)
74250 
74251 #define S_REG3MINADDR3MIN    8
74252 #define M_REG3MINADDR3MIN    0xffffffU
74253 #define V_REG3MINADDR3MIN(x) ((x) << S_REG3MINADDR3MIN)
74254 #define G_REG3MINADDR3MIN(x) (((x) >> S_REG3MINADDR3MIN) & M_REG3MINADDR3MIN)
74255 
74256 #define A_HMA_REG3_MAX 0x510a4
74257 
74258 #define S_ADDR3_MAX    12
74259 #define M_ADDR3_MAX    0xfffffU
74260 #define V_ADDR3_MAX(x) ((x) << S_ADDR3_MAX)
74261 #define G_ADDR3_MAX(x) (((x) >> S_ADDR3_MAX) & M_ADDR3_MAX)
74262 
74263 #define S_REG3MAXADDR3MAX    8
74264 #define M_REG3MAXADDR3MAX    0xffffffU
74265 #define V_REG3MAXADDR3MAX(x) ((x) << S_REG3MAXADDR3MAX)
74266 #define G_REG3MAXADDR3MAX(x) (((x) >> S_REG3MAXADDR3MAX) & M_REG3MAXADDR3MAX)
74267 
74268 #define A_HMA_REG3_MASK 0x510a8
74269 
74270 #define S_PAGE_SIZE3    12
74271 #define M_PAGE_SIZE3    0xfffffU
74272 #define V_PAGE_SIZE3(x) ((x) << S_PAGE_SIZE3)
74273 #define G_PAGE_SIZE3(x) (((x) >> S_PAGE_SIZE3) & M_PAGE_SIZE3)
74274 
74275 #define A_HMA_REG3_BASE 0x510ac
74276 #define A_HMA_REG3_BASE_LSB 0x510ac
74277 #define A_HMA_SW_SYNC 0x510b0
74278 
74279 #define S_ENTER_SYNC    31
74280 #define V_ENTER_SYNC(x) ((x) << S_ENTER_SYNC)
74281 #define F_ENTER_SYNC    V_ENTER_SYNC(1U)
74282 
74283 #define S_EXIT_SYNC    30
74284 #define V_EXIT_SYNC(x) ((x) << S_EXIT_SYNC)
74285 #define F_EXIT_SYNC    V_EXIT_SYNC(1U)
74286 
74287 #define A_HMA_GC_MODE_SEL 0x510b4
74288 
74289 #define S_MODE_SEL    8
74290 #define M_MODE_SEL    0x3U
74291 #define V_MODE_SEL(x) ((x) << S_MODE_SEL)
74292 #define G_MODE_SEL(x) (((x) >> S_MODE_SEL) & M_MODE_SEL)
74293 
74294 #define S_FLUSH_REQ    4
74295 #define V_FLUSH_REQ(x) ((x) << S_FLUSH_REQ)
74296 #define F_FLUSH_REQ    V_FLUSH_REQ(1U)
74297 
74298 #define S_CLEAR_REQ    0
74299 #define V_CLEAR_REQ(x) ((x) << S_CLEAR_REQ)
74300 #define F_CLEAR_REQ    V_CLEAR_REQ(1U)
74301 
74302 #define A_HMA_REG0_BASE_MSB 0x510b8
74303 
74304 #define S_BASE0_MSB    0
74305 #define M_BASE0_MSB    0xfU
74306 #define V_BASE0_MSB(x) ((x) << S_BASE0_MSB)
74307 #define G_BASE0_MSB(x) (((x) >> S_BASE0_MSB) & M_BASE0_MSB)
74308 
74309 #define A_HMA_REG1_BASE_MSB 0x510bc
74310 
74311 #define S_BASE1_MSB    0
74312 #define M_BASE1_MSB    0xfU
74313 #define V_BASE1_MSB(x) ((x) << S_BASE1_MSB)
74314 #define G_BASE1_MSB(x) (((x) >> S_BASE1_MSB) & M_BASE1_MSB)
74315 
74316 #define A_HMA_REG2_BASE_MSB 0x510c0
74317 
74318 #define S_BASE2_MSB    0
74319 #define M_BASE2_MSB    0xfU
74320 #define V_BASE2_MSB(x) ((x) << S_BASE2_MSB)
74321 #define G_BASE2_MSB(x) (((x) >> S_BASE2_MSB) & M_BASE2_MSB)
74322 
74323 #define A_HMA_REG3_BASE_MSB 0x510c4
74324 
74325 #define S_BASE3_MSB    0
74326 #define M_BASE3_MSB    0xfU
74327 #define V_BASE3_MSB(x) ((x) << S_BASE3_MSB)
74328 #define G_BASE3_MSB(x) (((x) >> S_BASE3_MSB) & M_BASE3_MSB)
74329 
74330 #define A_HMA_DBG_CTL 0x51104
74331 #define A_HMA_DBG_DATA 0x51108
74332 #define A_HMA_H_BIST_CMD 0x51200
74333 #define A_HMA_H_BIST_CMD_ADDR 0x51204
74334 #define A_HMA_H_BIST_CMD_LEN 0x51208
74335 #define A_HMA_H_BIST_DATA_PATTERN 0x5120c
74336 #define A_HMA_H_BIST_USER_WDATA0 0x51210
74337 #define A_HMA_H_BIST_USER_WDATA1 0x51214
74338 #define A_HMA_H_BIST_USER_WDATA2 0x51218
74339 #define A_HMA_H_BIST_NUM_ERR 0x5121c
74340 #define A_HMA_H_BIST_ERR_FIRST_ADDR 0x51220
74341 #define A_HMA_H_BIST_STATUS_RDATA 0x51224
74342 #define A_HMA_H_BIST_CRC_SEED 0x5126c
74343 #define A_HMA_TABLE_LINE1_MSB 0x51270
74344 
74345 #define S_STARTA    0
74346 #define M_STARTA    0xfU
74347 #define V_STARTA(x) ((x) << S_STARTA)
74348 #define G_STARTA(x) (((x) >> S_STARTA) & M_STARTA)
74349 
74350 #define A_HMA_TABLE_LINE2_MSB 0x51274
74351 
74352 #define S_ENDA    0
74353 #define M_ENDA    0xfU
74354 #define V_ENDA(x) ((x) << S_ENDA)
74355 #define G_ENDA(x) (((x) >> S_ENDA) & M_ENDA)
74356 
74357 #define S_GK_UF_PAR_ENABLE    6
74358 #define V_GK_UF_PAR_ENABLE(x) ((x) << S_GK_UF_PAR_ENABLE)
74359 #define F_GK_UF_PAR_ENABLE    V_GK_UF_PAR_ENABLE(1U)
74360 
74361 #define S_PCIEMST_PAR_ENABLE    2
74362 #define V_PCIEMST_PAR_ENABLE(x) ((x) << S_PCIEMST_PAR_ENABLE)
74363 #define F_PCIEMST_PAR_ENABLE    V_PCIEMST_PAR_ENABLE(1U)
74364 
74365 #define S_IDTF_INT_ENABLE    5
74366 #define V_IDTF_INT_ENABLE(x) ((x) << S_IDTF_INT_ENABLE)
74367 #define F_IDTF_INT_ENABLE    V_IDTF_INT_ENABLE(1U)
74368 
74369 #define S_OTF_INT_ENABLE    4
74370 #define V_OTF_INT_ENABLE(x) ((x) << S_OTF_INT_ENABLE)
74371 #define F_OTF_INT_ENABLE    V_OTF_INT_ENABLE(1U)
74372 
74373 #define S_RTF_INT_ENABLE    3
74374 #define V_RTF_INT_ENABLE(x) ((x) << S_RTF_INT_ENABLE)
74375 #define F_RTF_INT_ENABLE    V_RTF_INT_ENABLE(1U)
74376 
74377 #define S_PCIEMST_INT_ENABLE    2
74378 #define V_PCIEMST_INT_ENABLE(x) ((x) << S_PCIEMST_INT_ENABLE)
74379 #define F_PCIEMST_INT_ENABLE    V_PCIEMST_INT_ENABLE(1U)
74380 
74381 #define S_MAMST_INT_ENABLE    1
74382 #define V_MAMST_INT_ENABLE(x) ((x) << S_MAMST_INT_ENABLE)
74383 #define F_MAMST_INT_ENABLE    V_MAMST_INT_ENABLE(1U)
74384 
74385 #define S_GK_UF_INT_ENABLE    6
74386 #define V_GK_UF_INT_ENABLE(x) ((x) << S_GK_UF_INT_ENABLE)
74387 #define F_GK_UF_INT_ENABLE    V_GK_UF_INT_ENABLE(1U)
74388 
74389 #define S_IDTF_INT_CAUSE    5
74390 #define V_IDTF_INT_CAUSE(x) ((x) << S_IDTF_INT_CAUSE)
74391 #define F_IDTF_INT_CAUSE    V_IDTF_INT_CAUSE(1U)
74392 
74393 #define S_OTF_INT_CAUSE    4
74394 #define V_OTF_INT_CAUSE(x) ((x) << S_OTF_INT_CAUSE)
74395 #define F_OTF_INT_CAUSE    V_OTF_INT_CAUSE(1U)
74396 
74397 #define S_RTF_INT_CAUSE    3
74398 #define V_RTF_INT_CAUSE(x) ((x) << S_RTF_INT_CAUSE)
74399 #define F_RTF_INT_CAUSE    V_RTF_INT_CAUSE(1U)
74400 
74401 #define S_PCIEMST_INT_CAUSE    2
74402 #define V_PCIEMST_INT_CAUSE(x) ((x) << S_PCIEMST_INT_CAUSE)
74403 #define F_PCIEMST_INT_CAUSE    V_PCIEMST_INT_CAUSE(1U)
74404 
74405 #define S_MAMST_INT_CAUSE    1
74406 #define V_MAMST_INT_CAUSE(x) ((x) << S_MAMST_INT_CAUSE)
74407 #define F_MAMST_INT_CAUSE    V_MAMST_INT_CAUSE(1U)
74408 
74409 #define S_GK_UF_INT_CAUSE    6
74410 #define V_GK_UF_INT_CAUSE(x) ((x) << S_GK_UF_INT_CAUSE)
74411 #define F_GK_UF_INT_CAUSE    V_GK_UF_INT_CAUSE(1U)
74412 
74413 #define A_HMA_MA_MST_ERR 0x5130c
74414 #define A_HMA_RTF_ERR 0x51310
74415 #define A_HMA_OTF_ERR 0x51314
74416 #define A_HMA_IDTF_ERR 0x51318
74417 #define A_HMA_EXIT_TF 0x5131c
74418 
74419 #define S_RTF    30
74420 #define V_RTF(x) ((x) << S_RTF)
74421 #define F_RTF    V_RTF(1U)
74422 
74423 #define S_OTF    29
74424 #define V_OTF(x) ((x) << S_OTF)
74425 #define F_OTF    V_OTF(1U)
74426 
74427 #define S_IDTF    28
74428 #define V_IDTF(x) ((x) << S_IDTF)
74429 #define F_IDTF    V_IDTF(1U)
74430 
74431 #define A_HMA_LOCAL_DEBUG_CFG 0x51320
74432 #define A_HMA_LOCAL_DEBUG_RPT 0x51324
74433 #define A_HMA_DEBUG_FSM_0 0xa000
74434 
74435 #define S_EDC_FSM    18
74436 #define M_EDC_FSM    0x1fU
74437 #define V_EDC_FSM(x) ((x) << S_EDC_FSM)
74438 #define G_EDC_FSM(x) (((x) >> S_EDC_FSM) & M_EDC_FSM)
74439 
74440 #define S_RAS_FSM_SLV    15
74441 #define M_RAS_FSM_SLV    0x7U
74442 #define V_RAS_FSM_SLV(x) ((x) << S_RAS_FSM_SLV)
74443 #define G_RAS_FSM_SLV(x) (((x) >> S_RAS_FSM_SLV) & M_RAS_FSM_SLV)
74444 
74445 #define S_FC_FSM    10
74446 #define M_FC_FSM    0x1fU
74447 #define V_FC_FSM(x) ((x) << S_FC_FSM)
74448 #define G_FC_FSM(x) (((x) >> S_FC_FSM) & M_FC_FSM)
74449 
74450 #define S_COOKIE_ARB_FSM    8
74451 #define M_COOKIE_ARB_FSM    0x3U
74452 #define V_COOKIE_ARB_FSM(x) ((x) << S_COOKIE_ARB_FSM)
74453 #define G_COOKIE_ARB_FSM(x) (((x) >> S_COOKIE_ARB_FSM) & M_COOKIE_ARB_FSM)
74454 
74455 #define S_PCIE_CHUNK_FSM    6
74456 #define M_PCIE_CHUNK_FSM    0x3U
74457 #define V_PCIE_CHUNK_FSM(x) ((x) << S_PCIE_CHUNK_FSM)
74458 #define G_PCIE_CHUNK_FSM(x) (((x) >> S_PCIE_CHUNK_FSM) & M_PCIE_CHUNK_FSM)
74459 
74460 #define S_WTRANSFER_FSM    4
74461 #define M_WTRANSFER_FSM    0x3U
74462 #define V_WTRANSFER_FSM(x) ((x) << S_WTRANSFER_FSM)
74463 #define G_WTRANSFER_FSM(x) (((x) >> S_WTRANSFER_FSM) & M_WTRANSFER_FSM)
74464 
74465 #define S_WD_FSM    2
74466 #define M_WD_FSM    0x3U
74467 #define V_WD_FSM(x) ((x) << S_WD_FSM)
74468 #define G_WD_FSM(x) (((x) >> S_WD_FSM) & M_WD_FSM)
74469 
74470 #define S_RD_FSM    0
74471 #define M_RD_FSM    0x3U
74472 #define V_RD_FSM(x) ((x) << S_RD_FSM)
74473 #define G_RD_FSM(x) (((x) >> S_RD_FSM) & M_RD_FSM)
74474 
74475 #define A_HMA_DEBUG_FSM_1 0xa001
74476 
74477 #define S_SYNC_FSM    11
74478 #define M_SYNC_FSM    0x3ffU
74479 #define V_SYNC_FSM(x) ((x) << S_SYNC_FSM)
74480 #define G_SYNC_FSM(x) (((x) >> S_SYNC_FSM) & M_SYNC_FSM)
74481 
74482 #define S_OCHK_FSM    9
74483 #define M_OCHK_FSM    0x3U
74484 #define V_OCHK_FSM(x) ((x) << S_OCHK_FSM)
74485 #define G_OCHK_FSM(x) (((x) >> S_OCHK_FSM) & M_OCHK_FSM)
74486 
74487 #define S_TLB_FSM    5
74488 #define M_TLB_FSM    0xfU
74489 #define V_TLB_FSM(x) ((x) << S_TLB_FSM)
74490 #define G_TLB_FSM(x) (((x) >> S_TLB_FSM) & M_TLB_FSM)
74491 
74492 #define S_PIO_FSM    0
74493 #define M_PIO_FSM    0x1fU
74494 #define V_PIO_FSM(x) ((x) << S_PIO_FSM)
74495 #define G_PIO_FSM(x) (((x) >> S_PIO_FSM) & M_PIO_FSM)
74496 
74497 #define A_HMA_DEBUG_PCIE_INTF 0xa002
74498 
74499 #define S_T6_H_REQVLD    28
74500 #define V_T6_H_REQVLD(x) ((x) << S_T6_H_REQVLD)
74501 #define F_T6_H_REQVLD    V_T6_H_REQVLD(1U)
74502 
74503 #define S_H_REQFULL    27
74504 #define V_H_REQFULL(x) ((x) << S_H_REQFULL)
74505 #define F_H_REQFULL    V_H_REQFULL(1U)
74506 
74507 #define S_H_REQSOP    26
74508 #define V_H_REQSOP(x) ((x) << S_H_REQSOP)
74509 #define F_H_REQSOP    V_H_REQSOP(1U)
74510 
74511 #define S_H_REQEOP    25
74512 #define V_H_REQEOP(x) ((x) << S_H_REQEOP)
74513 #define F_H_REQEOP    V_H_REQEOP(1U)
74514 
74515 #define S_T6_H_RSPVLD    24
74516 #define V_T6_H_RSPVLD(x) ((x) << S_T6_H_RSPVLD)
74517 #define F_T6_H_RSPVLD    V_T6_H_RSPVLD(1U)
74518 
74519 #define S_H_RSPFULL    23
74520 #define V_H_RSPFULL(x) ((x) << S_H_RSPFULL)
74521 #define F_H_RSPFULL    V_H_RSPFULL(1U)
74522 
74523 #define S_H_RSPSOP    22
74524 #define V_H_RSPSOP(x) ((x) << S_H_RSPSOP)
74525 #define F_H_RSPSOP    V_H_RSPSOP(1U)
74526 
74527 #define S_H_RSPEOP    21
74528 #define V_H_RSPEOP(x) ((x) << S_H_RSPEOP)
74529 #define F_H_RSPEOP    V_H_RSPEOP(1U)
74530 
74531 #define S_H_RSPERR    20
74532 #define V_H_RSPERR(x) ((x) << S_H_RSPERR)
74533 #define F_H_RSPERR    V_H_RSPERR(1U)
74534 
74535 #define S_PCIE_CMD_AVAIL    19
74536 #define V_PCIE_CMD_AVAIL(x) ((x) << S_PCIE_CMD_AVAIL)
74537 #define F_PCIE_CMD_AVAIL    V_PCIE_CMD_AVAIL(1U)
74538 
74539 #define S_PCIE_CMD_RDY    18
74540 #define V_PCIE_CMD_RDY(x) ((x) << S_PCIE_CMD_RDY)
74541 #define F_PCIE_CMD_RDY    V_PCIE_CMD_RDY(1U)
74542 
74543 #define S_PCIE_WNR    17
74544 #define V_PCIE_WNR(x) ((x) << S_PCIE_WNR)
74545 #define F_PCIE_WNR    V_PCIE_WNR(1U)
74546 
74547 #define S_PCIE_LEN    9
74548 #define M_PCIE_LEN    0xffU
74549 #define V_PCIE_LEN(x) ((x) << S_PCIE_LEN)
74550 #define G_PCIE_LEN(x) (((x) >> S_PCIE_LEN) & M_PCIE_LEN)
74551 
74552 #define S_PCIE_TRWDAT_RDY    8
74553 #define V_PCIE_TRWDAT_RDY(x) ((x) << S_PCIE_TRWDAT_RDY)
74554 #define F_PCIE_TRWDAT_RDY    V_PCIE_TRWDAT_RDY(1U)
74555 
74556 #define S_PCIE_TRWDAT_AVAIL    7
74557 #define V_PCIE_TRWDAT_AVAIL(x) ((x) << S_PCIE_TRWDAT_AVAIL)
74558 #define F_PCIE_TRWDAT_AVAIL    V_PCIE_TRWDAT_AVAIL(1U)
74559 
74560 #define S_PCIE_TRWSOP    6
74561 #define V_PCIE_TRWSOP(x) ((x) << S_PCIE_TRWSOP)
74562 #define F_PCIE_TRWSOP    V_PCIE_TRWSOP(1U)
74563 
74564 #define S_PCIE_TRWEOP    5
74565 #define V_PCIE_TRWEOP(x) ((x) << S_PCIE_TRWEOP)
74566 #define F_PCIE_TRWEOP    V_PCIE_TRWEOP(1U)
74567 
74568 #define S_PCIE_TRRDAT_RDY    4
74569 #define V_PCIE_TRRDAT_RDY(x) ((x) << S_PCIE_TRRDAT_RDY)
74570 #define F_PCIE_TRRDAT_RDY    V_PCIE_TRRDAT_RDY(1U)
74571 
74572 #define S_PCIE_TRRDAT_AVAIL    3
74573 #define V_PCIE_TRRDAT_AVAIL(x) ((x) << S_PCIE_TRRDAT_AVAIL)
74574 #define F_PCIE_TRRDAT_AVAIL    V_PCIE_TRRDAT_AVAIL(1U)
74575 
74576 #define S_PCIE_TRRSOP    2
74577 #define V_PCIE_TRRSOP(x) ((x) << S_PCIE_TRRSOP)
74578 #define F_PCIE_TRRSOP    V_PCIE_TRRSOP(1U)
74579 
74580 #define S_PCIE_TRREOP    1
74581 #define V_PCIE_TRREOP(x) ((x) << S_PCIE_TRREOP)
74582 #define F_PCIE_TRREOP    V_PCIE_TRREOP(1U)
74583 
74584 #define S_PCIE_TRRERR    0
74585 #define V_PCIE_TRRERR(x) ((x) << S_PCIE_TRRERR)
74586 #define F_PCIE_TRRERR    V_PCIE_TRRERR(1U)
74587 
74588 #define A_HMA_DEBUG_PCIE_ADDR_INTERNAL_LO 0xa003
74589 #define A_HMA_DEBUG_PCIE_ADDR_INTERNAL_HI 0xa004
74590 #define A_HMA_DEBUG_PCIE_REQ_DATA_EXTERNAL 0xa005
74591 
74592 #define S_REQDATA2    24
74593 #define M_REQDATA2    0xffU
74594 #define V_REQDATA2(x) ((x) << S_REQDATA2)
74595 #define G_REQDATA2(x) (((x) >> S_REQDATA2) & M_REQDATA2)
74596 
74597 #define S_REQDATA1    21
74598 #define M_REQDATA1    0x7U
74599 #define V_REQDATA1(x) ((x) << S_REQDATA1)
74600 #define G_REQDATA1(x) (((x) >> S_REQDATA1) & M_REQDATA1)
74601 
74602 #define S_REQDATA0    0
74603 #define M_REQDATA0    0x1fffffU
74604 #define V_REQDATA0(x) ((x) << S_REQDATA0)
74605 #define G_REQDATA0(x) (((x) >> S_REQDATA0) & M_REQDATA0)
74606 
74607 #define A_HMA_DEBUG_PCIE_RSP_DATA_EXTERNAL 0xa006
74608 
74609 #define S_RSPDATA3    24
74610 #define M_RSPDATA3    0xffU
74611 #define V_RSPDATA3(x) ((x) << S_RSPDATA3)
74612 #define G_RSPDATA3(x) (((x) >> S_RSPDATA3) & M_RSPDATA3)
74613 
74614 #define S_RSPDATA2    16
74615 #define M_RSPDATA2    0xffU
74616 #define V_RSPDATA2(x) ((x) << S_RSPDATA2)
74617 #define G_RSPDATA2(x) (((x) >> S_RSPDATA2) & M_RSPDATA2)
74618 
74619 #define S_RSPDATA1    8
74620 #define M_RSPDATA1    0xffU
74621 #define V_RSPDATA1(x) ((x) << S_RSPDATA1)
74622 #define G_RSPDATA1(x) (((x) >> S_RSPDATA1) & M_RSPDATA1)
74623 
74624 #define S_RSPDATA0    0
74625 #define M_RSPDATA0    0xffU
74626 #define V_RSPDATA0(x) ((x) << S_RSPDATA0)
74627 #define G_RSPDATA0(x) (((x) >> S_RSPDATA0) & M_RSPDATA0)
74628 
74629 #define A_HMA_DEBUG_MA_SLV_CTL 0xa007
74630 
74631 #define S_MA_CMD_AVAIL    19
74632 #define V_MA_CMD_AVAIL(x) ((x) << S_MA_CMD_AVAIL)
74633 #define F_MA_CMD_AVAIL    V_MA_CMD_AVAIL(1U)
74634 
74635 #define S_MA_CLNT    15
74636 #define M_MA_CLNT    0xfU
74637 #define V_MA_CLNT(x) ((x) << S_MA_CLNT)
74638 #define G_MA_CLNT(x) (((x) >> S_MA_CLNT) & M_MA_CLNT)
74639 
74640 #define S_MA_WNR    14
74641 #define V_MA_WNR(x) ((x) << S_MA_WNR)
74642 #define F_MA_WNR    V_MA_WNR(1U)
74643 
74644 #define S_MA_LEN    6
74645 #define M_MA_LEN    0xffU
74646 #define V_MA_LEN(x) ((x) << S_MA_LEN)
74647 #define G_MA_LEN(x) (((x) >> S_MA_LEN) & M_MA_LEN)
74648 
74649 #define S_MA_MST_RD    5
74650 #define V_MA_MST_RD(x) ((x) << S_MA_MST_RD)
74651 #define F_MA_MST_RD    V_MA_MST_RD(1U)
74652 
74653 #define S_MA_MST_VLD    4
74654 #define V_MA_MST_VLD(x) ((x) << S_MA_MST_VLD)
74655 #define F_MA_MST_VLD    V_MA_MST_VLD(1U)
74656 
74657 #define S_MA_MST_ERR    3
74658 #define V_MA_MST_ERR(x) ((x) << S_MA_MST_ERR)
74659 #define F_MA_MST_ERR    V_MA_MST_ERR(1U)
74660 
74661 #define S_MAS_TLB_REQ    2
74662 #define V_MAS_TLB_REQ(x) ((x) << S_MAS_TLB_REQ)
74663 #define F_MAS_TLB_REQ    V_MAS_TLB_REQ(1U)
74664 
74665 #define S_MAS_TLB_ACK    1
74666 #define V_MAS_TLB_ACK(x) ((x) << S_MAS_TLB_ACK)
74667 #define F_MAS_TLB_ACK    V_MAS_TLB_ACK(1U)
74668 
74669 #define S_MAS_TLB_ERR    0
74670 #define V_MAS_TLB_ERR(x) ((x) << S_MAS_TLB_ERR)
74671 #define F_MAS_TLB_ERR    V_MAS_TLB_ERR(1U)
74672 
74673 #define A_HMA_DEBUG_MA_SLV_ADDR_INTERNAL 0xa008
74674 #define A_HMA_DEBUG_TLB_HIT_ENTRY 0xa009
74675 #define A_HMA_DEBUG_TLB_HIT_CNT 0xa00a
74676 #define A_HMA_DEBUG_TLB_MISS_CNT 0xa00b
74677 #define A_HMA_DEBUG_PAGE_TBL_LKP_CTL 0xa00c
74678 
74679 #define S_LKP_REQ_VLD    4
74680 #define V_LKP_REQ_VLD(x) ((x) << S_LKP_REQ_VLD)
74681 #define F_LKP_REQ_VLD    V_LKP_REQ_VLD(1U)
74682 
74683 #define S_LKP_DESC_SEL    1
74684 #define M_LKP_DESC_SEL    0x7U
74685 #define V_LKP_DESC_SEL(x) ((x) << S_LKP_DESC_SEL)
74686 #define G_LKP_DESC_SEL(x) (((x) >> S_LKP_DESC_SEL) & M_LKP_DESC_SEL)
74687 
74688 #define S_LKP_RSP_VLD    0
74689 #define V_LKP_RSP_VLD(x) ((x) << S_LKP_RSP_VLD)
74690 #define F_LKP_RSP_VLD    V_LKP_RSP_VLD(1U)
74691 
74692 #define A_HMA_DEBUG_PAGE_TBL_LKP_REQ_ADDR 0xa00d
74693 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_0 0xa00e
74694 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_1 0xa00f
74695 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_2 0xa010
74696 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_3 0xa011
74697 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_4 0xa012
74698 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_5 0xa013
74699 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_6 0xa014
74700 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_7 0xa015
74701 #define A_HMA_DEBUG_PHYS_DESC_INTERNAL_LO 0xa016
74702 #define A_HMA_DEBUG_PCIE_RD_REQ_CNT_LO 0xa017
74703 #define A_HMA_DEBUG_PCIE_RD_REQ_CNT_HI 0xa018
74704 #define A_HMA_DEBUG_PCIE_WR_REQ_CNT_LO 0xa019
74705 #define A_HMA_DEBUG_PCIE_WR_REQ_CNT_HI 0xa01a
74706 #define A_HMA_DEBUG_PCIE_RD_DATA_CYC_CNT_LO 0xa01b
74707 #define A_HMA_DEBUG_PCIE_RD_DATA_CYC_CNT_HI 0xa01c
74708 #define A_HMA_DEBUG_PCIE_WR_DATA_CYC_CNT_LO 0xa01d
74709 #define A_HMA_DEBUG_PCIE_WR_DATA_CYC_CNT_HI 0xa01e
74710 #define A_HMA_DEBUG_PCIE_SOP_EOP_CNT 0xa01f
74711 
74712 #define S_WR_EOP_CNT    16
74713 #define M_WR_EOP_CNT    0xffU
74714 #define V_WR_EOP_CNT(x) ((x) << S_WR_EOP_CNT)
74715 #define G_WR_EOP_CNT(x) (((x) >> S_WR_EOP_CNT) & M_WR_EOP_CNT)
74716 
74717 #define S_RD_SOP_CNT    8
74718 #define M_RD_SOP_CNT    0xffU
74719 #define V_RD_SOP_CNT(x) ((x) << S_RD_SOP_CNT)
74720 #define G_RD_SOP_CNT(x) (((x) >> S_RD_SOP_CNT) & M_RD_SOP_CNT)
74721 
74722 #define S_RD_EOP_CNT    0
74723 #define M_RD_EOP_CNT    0xffU
74724 #define V_RD_EOP_CNT(x) ((x) << S_RD_EOP_CNT)
74725 #define G_RD_EOP_CNT(x) (((x) >> S_RD_EOP_CNT) & M_RD_EOP_CNT)
74726 
74727 #define S_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT    16
74728 #define M_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT    0xffU
74729 #define V_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT(x) ((x) << S_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT)
74730 #define G_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT(x) (((x) >> S_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT) & M_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT)
74731 
74732 #define S_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT    8
74733 #define M_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT    0xffU
74734 #define V_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT(x) ((x) << S_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT)
74735 #define G_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT(x) (((x) >> S_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT) & M_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT)
74736 
74737 #define S_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT    0
74738 #define M_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT    0xffU
74739 #define V_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT(x) ((x) << S_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT)
74740 #define G_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT(x) (((x) >> S_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT) & M_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT)
74741 
74742 /* registers for module MAC_T7 */
74743 #define MAC_T7_BASE_ADDR 0x38000
74744 
74745 #define S_T7_PORT_MAP    21
74746 #define M_T7_PORT_MAP    0x7U
74747 #define V_T7_PORT_MAP(x) ((x) << S_T7_PORT_MAP)
74748 #define G_T7_PORT_MAP(x) (((x) >> S_T7_PORT_MAP) & M_T7_PORT_MAP)
74749 
74750 #define S_T7_SMUX_RX_LOOP    17
74751 #define M_T7_SMUX_RX_LOOP    0xfU
74752 #define V_T7_SMUX_RX_LOOP(x) ((x) << S_T7_SMUX_RX_LOOP)
74753 #define G_T7_SMUX_RX_LOOP(x) (((x) >> S_T7_SMUX_RX_LOOP) & M_T7_SMUX_RX_LOOP)
74754 
74755 #define S_T7_SIGNAL_DET    15
74756 #define V_T7_SIGNAL_DET(x) ((x) << S_T7_SIGNAL_DET)
74757 #define F_T7_SIGNAL_DET    V_T7_SIGNAL_DET(1U)
74758 
74759 #define S_CFG_MAC_2_MPS_FULL    13
74760 #define V_CFG_MAC_2_MPS_FULL(x) ((x) << S_CFG_MAC_2_MPS_FULL)
74761 #define F_CFG_MAC_2_MPS_FULL    V_CFG_MAC_2_MPS_FULL(1U)
74762 
74763 #define S_MPS_FULL_SEL    12
74764 #define V_MPS_FULL_SEL(x) ((x) << S_MPS_FULL_SEL)
74765 #define F_MPS_FULL_SEL    V_MPS_FULL_SEL(1U)
74766 
74767 #define S_T7_SMUXTXSEL    8
74768 #define M_T7_SMUXTXSEL    0xfU
74769 #define V_T7_SMUXTXSEL(x) ((x) << S_T7_SMUXTXSEL)
74770 #define G_T7_SMUXTXSEL(x) (((x) >> S_T7_SMUXTXSEL) & M_T7_SMUXTXSEL)
74771 
74772 #define S_T7_PORTSPEED    4
74773 #define M_T7_PORTSPEED    0xfU
74774 #define V_T7_PORTSPEED(x) ((x) << S_T7_PORTSPEED)
74775 #define G_T7_PORTSPEED(x) (((x) >> S_T7_PORTSPEED) & M_T7_PORTSPEED)
74776 
74777 #define S_MTIP_REG_RESET    25
74778 #define V_MTIP_REG_RESET(x) ((x) << S_MTIP_REG_RESET)
74779 #define F_MTIP_REG_RESET    V_MTIP_REG_RESET(1U)
74780 
74781 #define S_RESET_REG_CLK_I    24
74782 #define V_RESET_REG_CLK_I(x) ((x) << S_RESET_REG_CLK_I)
74783 #define F_RESET_REG_CLK_I    V_RESET_REG_CLK_I(1U)
74784 
74785 #define S_T7_LED1_CFG1    15
74786 #define M_T7_LED1_CFG1    0x7U
74787 #define V_T7_LED1_CFG1(x) ((x) << S_T7_LED1_CFG1)
74788 #define G_T7_LED1_CFG1(x) (((x) >> S_T7_LED1_CFG1) & M_T7_LED1_CFG1)
74789 
74790 #define S_T7_LED0_CFG1    12
74791 #define M_T7_LED0_CFG1    0x7U
74792 #define V_T7_LED0_CFG1(x) ((x) << S_T7_LED0_CFG1)
74793 #define G_T7_LED0_CFG1(x) (((x) >> S_T7_LED0_CFG1) & M_T7_LED0_CFG1)
74794 
74795 #define A_T7_MAC_PORT_MAGIC_MACID_LO 0x820
74796 #define A_T7_MAC_PORT_MAGIC_MACID_HI 0x824
74797 #define A_T7_MAC_PORT_LINK_STATUS 0x828
74798 
74799 #define S_EGR_SE_CNT_ERR    9
74800 #define V_EGR_SE_CNT_ERR(x) ((x) << S_EGR_SE_CNT_ERR)
74801 #define F_EGR_SE_CNT_ERR    V_EGR_SE_CNT_ERR(1U)
74802 
74803 #define S_INGR_SE_CNT_ERR    8
74804 #define V_INGR_SE_CNT_ERR(x) ((x) << S_INGR_SE_CNT_ERR)
74805 #define F_INGR_SE_CNT_ERR    V_INGR_SE_CNT_ERR(1U)
74806 
74807 #define A_T7_MAC_PORT_PERR_INT_EN_100G 0x82c
74808 
74809 #define S_PERR_PCSR_FDM_3    21
74810 #define V_PERR_PCSR_FDM_3(x) ((x) << S_PERR_PCSR_FDM_3)
74811 #define F_PERR_PCSR_FDM_3    V_PERR_PCSR_FDM_3(1U)
74812 
74813 #define S_PERR_PCSR_FDM_2    20
74814 #define V_PERR_PCSR_FDM_2(x) ((x) << S_PERR_PCSR_FDM_2)
74815 #define F_PERR_PCSR_FDM_2    V_PERR_PCSR_FDM_2(1U)
74816 
74817 #define S_PERR_PCSR_FDM_1    19
74818 #define V_PERR_PCSR_FDM_1(x) ((x) << S_PERR_PCSR_FDM_1)
74819 #define F_PERR_PCSR_FDM_1    V_PERR_PCSR_FDM_1(1U)
74820 
74821 #define S_PERR_PCSR_FDM_0    18
74822 #define V_PERR_PCSR_FDM_0(x) ((x) << S_PERR_PCSR_FDM_0)
74823 #define F_PERR_PCSR_FDM_0    V_PERR_PCSR_FDM_0(1U)
74824 
74825 #define S_PERR_PCSR_FM_3    17
74826 #define V_PERR_PCSR_FM_3(x) ((x) << S_PERR_PCSR_FM_3)
74827 #define F_PERR_PCSR_FM_3    V_PERR_PCSR_FM_3(1U)
74828 
74829 #define S_PERR_PCSR_FM_2    16
74830 #define V_PERR_PCSR_FM_2(x) ((x) << S_PERR_PCSR_FM_2)
74831 #define F_PERR_PCSR_FM_2    V_PERR_PCSR_FM_2(1U)
74832 
74833 #define S_PERR_PCSR_FM_1    15
74834 #define V_PERR_PCSR_FM_1(x) ((x) << S_PERR_PCSR_FM_1)
74835 #define F_PERR_PCSR_FM_1    V_PERR_PCSR_FM_1(1U)
74836 
74837 #define S_PERR_PCSR_FM_0    14
74838 #define V_PERR_PCSR_FM_0(x) ((x) << S_PERR_PCSR_FM_0)
74839 #define F_PERR_PCSR_FM_0    V_PERR_PCSR_FM_0(1U)
74840 
74841 #define S_PERR_PCSR_DM_1    13
74842 #define V_PERR_PCSR_DM_1(x) ((x) << S_PERR_PCSR_DM_1)
74843 #define F_PERR_PCSR_DM_1    V_PERR_PCSR_DM_1(1U)
74844 
74845 #define S_PERR_PCSR_DM_0    12
74846 #define V_PERR_PCSR_DM_0(x) ((x) << S_PERR_PCSR_DM_0)
74847 #define F_PERR_PCSR_DM_0    V_PERR_PCSR_DM_0(1U)
74848 
74849 #define S_PERR_PCSR_DK_3    11
74850 #define V_PERR_PCSR_DK_3(x) ((x) << S_PERR_PCSR_DK_3)
74851 #define F_PERR_PCSR_DK_3    V_PERR_PCSR_DK_3(1U)
74852 
74853 #define S_PERR_PCSR_DK_2    10
74854 #define V_PERR_PCSR_DK_2(x) ((x) << S_PERR_PCSR_DK_2)
74855 #define F_PERR_PCSR_DK_2    V_PERR_PCSR_DK_2(1U)
74856 
74857 #define S_PERR_PCSR_DK_1    9
74858 #define V_PERR_PCSR_DK_1(x) ((x) << S_PERR_PCSR_DK_1)
74859 #define F_PERR_PCSR_DK_1    V_PERR_PCSR_DK_1(1U)
74860 
74861 #define S_PERR_PCSR_DK_0    8
74862 #define V_PERR_PCSR_DK_0(x) ((x) << S_PERR_PCSR_DK_0)
74863 #define F_PERR_PCSR_DK_0    V_PERR_PCSR_DK_0(1U)
74864 
74865 #define S_PERR_F91RO_1    7
74866 #define V_PERR_F91RO_1(x) ((x) << S_PERR_F91RO_1)
74867 #define F_PERR_F91RO_1    V_PERR_F91RO_1(1U)
74868 
74869 #define S_PERR_F91RO_0    6
74870 #define V_PERR_F91RO_0(x) ((x) << S_PERR_F91RO_0)
74871 #define F_PERR_F91RO_0    V_PERR_F91RO_0(1U)
74872 
74873 #define S_PERR_PCSR_F91DM    5
74874 #define V_PERR_PCSR_F91DM(x) ((x) << S_PERR_PCSR_F91DM)
74875 #define F_PERR_PCSR_F91DM    V_PERR_PCSR_F91DM(1U)
74876 
74877 #define S_PERR_PCSR_F91TI    4
74878 #define V_PERR_PCSR_F91TI(x) ((x) << S_PERR_PCSR_F91TI)
74879 #define F_PERR_PCSR_F91TI    V_PERR_PCSR_F91TI(1U)
74880 
74881 #define S_PERR_PCSR_F91TO    3
74882 #define V_PERR_PCSR_F91TO(x) ((x) << S_PERR_PCSR_F91TO)
74883 #define F_PERR_PCSR_F91TO    V_PERR_PCSR_F91TO(1U)
74884 
74885 #define S_PERR_PCSR_F91M    2
74886 #define V_PERR_PCSR_F91M(x) ((x) << S_PERR_PCSR_F91M)
74887 #define F_PERR_PCSR_F91M    V_PERR_PCSR_F91M(1U)
74888 
74889 #define S_PERR_PCSR_80_16_1    1
74890 #define V_PERR_PCSR_80_16_1(x) ((x) << S_PERR_PCSR_80_16_1)
74891 #define F_PERR_PCSR_80_16_1    V_PERR_PCSR_80_16_1(1U)
74892 
74893 #define S_PERR_PCSR_80_16_0    0
74894 #define V_PERR_PCSR_80_16_0(x) ((x) << S_PERR_PCSR_80_16_0)
74895 #define F_PERR_PCSR_80_16_0    V_PERR_PCSR_80_16_0(1U)
74896 
74897 #define A_T7_MAC_PORT_PERR_INT_CAUSE_100G 0x830
74898 #define A_T7_MAC_PORT_PERR_ENABLE_100G 0x834
74899 #define A_MAC_PORT_MAC10G100G_CONFIG_0 0x838
74900 
74901 #define S_PEER_DELAY_VAL    31
74902 #define V_PEER_DELAY_VAL(x) ((x) << S_PEER_DELAY_VAL)
74903 #define F_PEER_DELAY_VAL    V_PEER_DELAY_VAL(1U)
74904 
74905 #define S_PEER_DELAY    1
74906 #define M_PEER_DELAY    0x3fffffffU
74907 #define V_PEER_DELAY(x) ((x) << S_PEER_DELAY)
74908 #define G_PEER_DELAY(x) (((x) >> S_PEER_DELAY) & M_PEER_DELAY)
74909 
74910 #define S_MODE1S_ENA    0
74911 #define V_MODE1S_ENA(x) ((x) << S_MODE1S_ENA)
74912 #define F_MODE1S_ENA    V_MODE1S_ENA(1U)
74913 
74914 #define A_MAC_PORT_MAC10G100G_CONFIG_1 0x83c
74915 
74916 #define S_TX_STOP    25
74917 #define V_TX_STOP(x) ((x) << S_TX_STOP)
74918 #define F_TX_STOP    V_TX_STOP(1U)
74919 
74920 #define S_T7_MODE1S_ENA    24
74921 #define V_T7_MODE1S_ENA(x) ((x) << S_T7_MODE1S_ENA)
74922 #define F_T7_MODE1S_ENA    V_T7_MODE1S_ENA(1U)
74923 
74924 #define S_TX_TS_ID    12
74925 #define M_TX_TS_ID    0xfffU
74926 #define V_TX_TS_ID(x) ((x) << S_TX_TS_ID)
74927 #define G_TX_TS_ID(x) (((x) >> S_TX_TS_ID) & M_TX_TS_ID)
74928 
74929 #define S_T7_TX_LI_FAULT    11
74930 #define V_T7_TX_LI_FAULT(x) ((x) << S_T7_TX_LI_FAULT)
74931 #define F_T7_TX_LI_FAULT    V_T7_TX_LI_FAULT(1U)
74932 
74933 #define S_XOFF_GEN    3
74934 #define M_XOFF_GEN    0xffU
74935 #define V_XOFF_GEN(x) ((x) << S_XOFF_GEN)
74936 #define G_XOFF_GEN(x) (((x) >> S_XOFF_GEN) & M_XOFF_GEN)
74937 
74938 #define S_TX_REM_FAULT    1
74939 #define V_TX_REM_FAULT(x) ((x) << S_TX_REM_FAULT)
74940 #define F_TX_REM_FAULT    V_TX_REM_FAULT(1U)
74941 
74942 #define S_TX_LOC_FAULT    0
74943 #define V_TX_LOC_FAULT(x) ((x) << S_TX_LOC_FAULT)
74944 #define F_TX_LOC_FAULT    V_TX_LOC_FAULT(1U)
74945 
74946 #define A_MAC_PORT_MAC10G100G_CONFIG_2 0x840
74947 
74948 #define S_FF_TX_RX_TS_NS    0
74949 #define M_FF_TX_RX_TS_NS    0x3fffffffU
74950 #define V_FF_TX_RX_TS_NS(x) ((x) << S_FF_TX_RX_TS_NS)
74951 #define G_FF_TX_RX_TS_NS(x) (((x) >> S_FF_TX_RX_TS_NS) & M_FF_TX_RX_TS_NS)
74952 
74953 #define A_MAC_PORT_MAC10G100G_STATUS 0x844
74954 
74955 #define S_REG_LOWP    21
74956 #define V_REG_LOWP(x) ((x) << S_REG_LOWP)
74957 #define F_REG_LOWP    V_REG_LOWP(1U)
74958 
74959 #define S_LI_FAULT    20
74960 #define V_LI_FAULT(x) ((x) << S_LI_FAULT)
74961 #define F_LI_FAULT    V_LI_FAULT(1U)
74962 
74963 #define S_TX_ISIDLE    19
74964 #define V_TX_ISIDLE(x) ((x) << S_TX_ISIDLE)
74965 #define F_TX_ISIDLE    V_TX_ISIDLE(1U)
74966 
74967 #define S_TX_UNDERFLOW    18
74968 #define V_TX_UNDERFLOW(x) ((x) << S_TX_UNDERFLOW)
74969 #define F_TX_UNDERFLOW    V_TX_UNDERFLOW(1U)
74970 
74971 #define S_T7_TX_EMPTY    17
74972 #define V_T7_TX_EMPTY(x) ((x) << S_T7_TX_EMPTY)
74973 #define F_T7_TX_EMPTY    V_T7_TX_EMPTY(1U)
74974 
74975 #define S_T7_1_REM_FAULT    16
74976 #define V_T7_1_REM_FAULT(x) ((x) << S_T7_1_REM_FAULT)
74977 #define F_T7_1_REM_FAULT    V_T7_1_REM_FAULT(1U)
74978 
74979 #define S_REG_TS_AVAIL    15
74980 #define V_REG_TS_AVAIL(x) ((x) << S_REG_TS_AVAIL)
74981 #define F_REG_TS_AVAIL    V_REG_TS_AVAIL(1U)
74982 
74983 #define S_T7_PHY_TXENA    14
74984 #define V_T7_PHY_TXENA(x) ((x) << S_T7_PHY_TXENA)
74985 #define F_T7_PHY_TXENA    V_T7_PHY_TXENA(1U)
74986 
74987 #define S_T7_PFC_MODE    13
74988 #define V_T7_PFC_MODE(x) ((x) << S_T7_PFC_MODE)
74989 #define F_T7_PFC_MODE    V_T7_PFC_MODE(1U)
74990 
74991 #define S_PAUSE_ON    5
74992 #define M_PAUSE_ON    0xffU
74993 #define V_PAUSE_ON(x) ((x) << S_PAUSE_ON)
74994 #define G_PAUSE_ON(x) (((x) >> S_PAUSE_ON) & M_PAUSE_ON)
74995 
74996 #define S_MAC_PAUSE_EN    4
74997 #define V_MAC_PAUSE_EN(x) ((x) << S_MAC_PAUSE_EN)
74998 #define F_MAC_PAUSE_EN    V_MAC_PAUSE_EN(1U)
74999 
75000 #define S_MAC_ENABLE    3
75001 #define V_MAC_ENABLE(x) ((x) << S_MAC_ENABLE)
75002 #define F_MAC_ENABLE    V_MAC_ENABLE(1U)
75003 
75004 #define S_LOOP_ENA    2
75005 #define V_LOOP_ENA(x) ((x) << S_LOOP_ENA)
75006 #define F_LOOP_ENA    V_LOOP_ENA(1U)
75007 
75008 #define S_LOC_FAULT    1
75009 #define V_LOC_FAULT(x) ((x) << S_LOC_FAULT)
75010 #define F_LOC_FAULT    V_LOC_FAULT(1U)
75011 
75012 #define S_FF_RX_EMPTY    0
75013 #define V_FF_RX_EMPTY(x) ((x) << S_FF_RX_EMPTY)
75014 #define F_FF_RX_EMPTY    V_FF_RX_EMPTY(1U)
75015 
75016 #define A_MAC_PORT_MAC_AN_STATE_STATUS0 0x848
75017 
75018 #define S_AN_VAL_AN    15
75019 #define V_AN_VAL_AN(x) ((x) << S_AN_VAL_AN)
75020 #define F_AN_VAL_AN    V_AN_VAL_AN(1U)
75021 
75022 #define S_AN_TR_DIS_STATUS_AN    14
75023 #define V_AN_TR_DIS_STATUS_AN(x) ((x) << S_AN_TR_DIS_STATUS_AN)
75024 #define F_AN_TR_DIS_STATUS_AN    V_AN_TR_DIS_STATUS_AN(1U)
75025 
75026 #define S_AN_STATUS_AN    13
75027 #define V_AN_STATUS_AN(x) ((x) << S_AN_STATUS_AN)
75028 #define F_AN_STATUS_AN    V_AN_STATUS_AN(1U)
75029 
75030 #define S_AN_SELECT_AN    8
75031 #define M_AN_SELECT_AN    0x1fU
75032 #define V_AN_SELECT_AN(x) ((x) << S_AN_SELECT_AN)
75033 #define G_AN_SELECT_AN(x) (((x) >> S_AN_SELECT_AN) & M_AN_SELECT_AN)
75034 
75035 #define S_AN_RS_FEC_ENA_AN    7
75036 #define V_AN_RS_FEC_ENA_AN(x) ((x) << S_AN_RS_FEC_ENA_AN)
75037 #define F_AN_RS_FEC_ENA_AN    V_AN_RS_FEC_ENA_AN(1U)
75038 
75039 #define S_AN_INT_AN    6
75040 #define V_AN_INT_AN(x) ((x) << S_AN_INT_AN)
75041 #define F_AN_INT_AN    V_AN_INT_AN(1U)
75042 
75043 #define S_AN_FEC_ENA_AN    5
75044 #define V_AN_FEC_ENA_AN(x) ((x) << S_AN_FEC_ENA_AN)
75045 #define F_AN_FEC_ENA_AN    V_AN_FEC_ENA_AN(1U)
75046 
75047 #define S_AN_DONE_AN    4
75048 #define V_AN_DONE_AN(x) ((x) << S_AN_DONE_AN)
75049 #define F_AN_DONE_AN    V_AN_DONE_AN(1U)
75050 
75051 #define S_AN_STATE    0
75052 #define M_AN_STATE    0xfU
75053 #define V_AN_STATE(x) ((x) << S_AN_STATE)
75054 #define G_AN_STATE(x) (((x) >> S_AN_STATE) & M_AN_STATE)
75055 
75056 #define A_MAC_PORT_MAC_AN_STATE_STATUS1 0x84c
75057 #define A_T7_MAC_PORT_EPIO_DATA0 0x850
75058 #define A_T7_MAC_PORT_EPIO_DATA1 0x854
75059 #define A_T7_MAC_PORT_EPIO_DATA2 0x858
75060 #define A_T7_MAC_PORT_EPIO_DATA3 0x85c
75061 #define A_T7_MAC_PORT_EPIO_OP 0x860
75062 #define A_T7_MAC_PORT_WOL_STATUS 0x864
75063 #define A_T7_MAC_PORT_INT_EN 0x868
75064 
75065 #define S_MAC2MPS_PERR    31
75066 #define V_MAC2MPS_PERR(x) ((x) << S_MAC2MPS_PERR)
75067 #define F_MAC2MPS_PERR    V_MAC2MPS_PERR(1U)
75068 
75069 #define S_MAC_PPS_INT_EN    30
75070 #define V_MAC_PPS_INT_EN(x) ((x) << S_MAC_PPS_INT_EN)
75071 #define F_MAC_PPS_INT_EN    V_MAC_PPS_INT_EN(1U)
75072 
75073 #define S_MAC_TX_TS_AVAIL_INT_EN    29
75074 #define V_MAC_TX_TS_AVAIL_INT_EN(x) ((x) << S_MAC_TX_TS_AVAIL_INT_EN)
75075 #define F_MAC_TX_TS_AVAIL_INT_EN    V_MAC_TX_TS_AVAIL_INT_EN(1U)
75076 
75077 #define S_MAC_SINGLE_ALARM_INT_EN    28
75078 #define V_MAC_SINGLE_ALARM_INT_EN(x) ((x) << S_MAC_SINGLE_ALARM_INT_EN)
75079 #define F_MAC_SINGLE_ALARM_INT_EN    V_MAC_SINGLE_ALARM_INT_EN(1U)
75080 
75081 #define S_MAC_PERIODIC_ALARM_INT_EN    27
75082 #define V_MAC_PERIODIC_ALARM_INT_EN(x) ((x) << S_MAC_PERIODIC_ALARM_INT_EN)
75083 #define F_MAC_PERIODIC_ALARM_INT_EN    V_MAC_PERIODIC_ALARM_INT_EN(1U)
75084 
75085 #define S_MAC_PATDETWAKE_INT_EN    26
75086 #define V_MAC_PATDETWAKE_INT_EN(x) ((x) << S_MAC_PATDETWAKE_INT_EN)
75087 #define F_MAC_PATDETWAKE_INT_EN    V_MAC_PATDETWAKE_INT_EN(1U)
75088 
75089 #define S_MAC_MAGIC_WAKE_INT_EN    25
75090 #define V_MAC_MAGIC_WAKE_INT_EN(x) ((x) << S_MAC_MAGIC_WAKE_INT_EN)
75091 #define F_MAC_MAGIC_WAKE_INT_EN    V_MAC_MAGIC_WAKE_INT_EN(1U)
75092 
75093 #define S_MAC_SIGDETCHG_INT_EN    24
75094 #define V_MAC_SIGDETCHG_INT_EN(x) ((x) << S_MAC_SIGDETCHG_INT_EN)
75095 #define F_MAC_SIGDETCHG_INT_EN    V_MAC_SIGDETCHG_INT_EN(1U)
75096 
75097 #define S_MAC_PCS_LINK_GOOD_EN    12
75098 #define V_MAC_PCS_LINK_GOOD_EN(x) ((x) << S_MAC_PCS_LINK_GOOD_EN)
75099 #define F_MAC_PCS_LINK_GOOD_EN    V_MAC_PCS_LINK_GOOD_EN(1U)
75100 
75101 #define S_MAC_PCS_LINK_FAIL_EN    11
75102 #define V_MAC_PCS_LINK_FAIL_EN(x) ((x) << S_MAC_PCS_LINK_FAIL_EN)
75103 #define F_MAC_PCS_LINK_FAIL_EN    V_MAC_PCS_LINK_FAIL_EN(1U)
75104 
75105 #define S_MAC_OVRFLOW_INT_EN    10
75106 #define V_MAC_OVRFLOW_INT_EN(x) ((x) << S_MAC_OVRFLOW_INT_EN)
75107 #define F_MAC_OVRFLOW_INT_EN    V_MAC_OVRFLOW_INT_EN(1U)
75108 
75109 #define S_MAC_REM_FAULT_INT_EN    7
75110 #define V_MAC_REM_FAULT_INT_EN(x) ((x) << S_MAC_REM_FAULT_INT_EN)
75111 #define F_MAC_REM_FAULT_INT_EN    V_MAC_REM_FAULT_INT_EN(1U)
75112 
75113 #define S_MAC_LOC_FAULT_INT_EN    6
75114 #define V_MAC_LOC_FAULT_INT_EN(x) ((x) << S_MAC_LOC_FAULT_INT_EN)
75115 #define F_MAC_LOC_FAULT_INT_EN    V_MAC_LOC_FAULT_INT_EN(1U)
75116 
75117 #define S_MAC_LINK_DOWN_INT_EN    5
75118 #define V_MAC_LINK_DOWN_INT_EN(x) ((x) << S_MAC_LINK_DOWN_INT_EN)
75119 #define F_MAC_LINK_DOWN_INT_EN    V_MAC_LINK_DOWN_INT_EN(1U)
75120 
75121 #define S_MAC_LINK_UP_INT_EN    4
75122 #define V_MAC_LINK_UP_INT_EN(x) ((x) << S_MAC_LINK_UP_INT_EN)
75123 #define F_MAC_LINK_UP_INT_EN    V_MAC_LINK_UP_INT_EN(1U)
75124 
75125 #define S_MAC_AN_DONE_INT_EN    3
75126 #define V_MAC_AN_DONE_INT_EN(x) ((x) << S_MAC_AN_DONE_INT_EN)
75127 #define F_MAC_AN_DONE_INT_EN    V_MAC_AN_DONE_INT_EN(1U)
75128 
75129 #define S_MAC_AN_PGRD_INT_EN    2
75130 #define V_MAC_AN_PGRD_INT_EN(x) ((x) << S_MAC_AN_PGRD_INT_EN)
75131 #define F_MAC_AN_PGRD_INT_EN    V_MAC_AN_PGRD_INT_EN(1U)
75132 
75133 #define S_MAC_TXFIFO_ERR_INT_EN    1
75134 #define V_MAC_TXFIFO_ERR_INT_EN(x) ((x) << S_MAC_TXFIFO_ERR_INT_EN)
75135 #define F_MAC_TXFIFO_ERR_INT_EN    V_MAC_TXFIFO_ERR_INT_EN(1U)
75136 
75137 #define S_MAC_RXFIFO_ERR_INT_EN    0
75138 #define V_MAC_RXFIFO_ERR_INT_EN(x) ((x) << S_MAC_RXFIFO_ERR_INT_EN)
75139 #define F_MAC_RXFIFO_ERR_INT_EN    V_MAC_RXFIFO_ERR_INT_EN(1U)
75140 
75141 #define A_T7_MAC_PORT_INT_CAUSE 0x86c
75142 
75143 #define S_MAC2MPS_PERR_CAUSE    31
75144 #define V_MAC2MPS_PERR_CAUSE(x) ((x) << S_MAC2MPS_PERR_CAUSE)
75145 #define F_MAC2MPS_PERR_CAUSE    V_MAC2MPS_PERR_CAUSE(1U)
75146 
75147 #define S_MAC_PPS_INT_CAUSE    30
75148 #define V_MAC_PPS_INT_CAUSE(x) ((x) << S_MAC_PPS_INT_CAUSE)
75149 #define F_MAC_PPS_INT_CAUSE    V_MAC_PPS_INT_CAUSE(1U)
75150 
75151 #define S_MAC_TX_TS_AVAIL_INT_CAUSE    29
75152 #define V_MAC_TX_TS_AVAIL_INT_CAUSE(x) ((x) << S_MAC_TX_TS_AVAIL_INT_CAUSE)
75153 #define F_MAC_TX_TS_AVAIL_INT_CAUSE    V_MAC_TX_TS_AVAIL_INT_CAUSE(1U)
75154 
75155 #define S_MAC_SINGLE_ALARM_INT_CAUSE    28
75156 #define V_MAC_SINGLE_ALARM_INT_CAUSE(x) ((x) << S_MAC_SINGLE_ALARM_INT_CAUSE)
75157 #define F_MAC_SINGLE_ALARM_INT_CAUSE    V_MAC_SINGLE_ALARM_INT_CAUSE(1U)
75158 
75159 #define S_MAC_PERIODIC_ALARM_INT_CAUSE    27
75160 #define V_MAC_PERIODIC_ALARM_INT_CAUSE(x) ((x) << S_MAC_PERIODIC_ALARM_INT_CAUSE)
75161 #define F_MAC_PERIODIC_ALARM_INT_CAUSE    V_MAC_PERIODIC_ALARM_INT_CAUSE(1U)
75162 
75163 #define S_MAC_PATDETWAKE_INT_CAUSE    26
75164 #define V_MAC_PATDETWAKE_INT_CAUSE(x) ((x) << S_MAC_PATDETWAKE_INT_CAUSE)
75165 #define F_MAC_PATDETWAKE_INT_CAUSE    V_MAC_PATDETWAKE_INT_CAUSE(1U)
75166 
75167 #define S_MAC_MAGIC_WAKE_INT_CAUSE    25
75168 #define V_MAC_MAGIC_WAKE_INT_CAUSE(x) ((x) << S_MAC_MAGIC_WAKE_INT_CAUSE)
75169 #define F_MAC_MAGIC_WAKE_INT_CAUSE    V_MAC_MAGIC_WAKE_INT_CAUSE(1U)
75170 
75171 #define S_MAC_SIGDETCHG_INT_CAUSE    24
75172 #define V_MAC_SIGDETCHG_INT_CAUSE(x) ((x) << S_MAC_SIGDETCHG_INT_CAUSE)
75173 #define F_MAC_SIGDETCHG_INT_CAUSE    V_MAC_SIGDETCHG_INT_CAUSE(1U)
75174 
75175 #define S_MAC_PCS_LINK_GOOD_CAUSE    12
75176 #define V_MAC_PCS_LINK_GOOD_CAUSE(x) ((x) << S_MAC_PCS_LINK_GOOD_CAUSE)
75177 #define F_MAC_PCS_LINK_GOOD_CAUSE    V_MAC_PCS_LINK_GOOD_CAUSE(1U)
75178 
75179 #define S_MAC_PCS_LINK_FAIL_CAUSE    11
75180 #define V_MAC_PCS_LINK_FAIL_CAUSE(x) ((x) << S_MAC_PCS_LINK_FAIL_CAUSE)
75181 #define F_MAC_PCS_LINK_FAIL_CAUSE    V_MAC_PCS_LINK_FAIL_CAUSE(1U)
75182 
75183 #define S_MAC_OVRFLOW_INT_CAUSE    10
75184 #define V_MAC_OVRFLOW_INT_CAUSE(x) ((x) << S_MAC_OVRFLOW_INT_CAUSE)
75185 #define F_MAC_OVRFLOW_INT_CAUSE    V_MAC_OVRFLOW_INT_CAUSE(1U)
75186 
75187 #define S_MAC_REM_FAULT_INT_CAUSE    7
75188 #define V_MAC_REM_FAULT_INT_CAUSE(x) ((x) << S_MAC_REM_FAULT_INT_CAUSE)
75189 #define F_MAC_REM_FAULT_INT_CAUSE    V_MAC_REM_FAULT_INT_CAUSE(1U)
75190 
75191 #define S_MAC_LOC_FAULT_INT_CAUSE    6
75192 #define V_MAC_LOC_FAULT_INT_CAUSE(x) ((x) << S_MAC_LOC_FAULT_INT_CAUSE)
75193 #define F_MAC_LOC_FAULT_INT_CAUSE    V_MAC_LOC_FAULT_INT_CAUSE(1U)
75194 
75195 #define S_MAC_LINK_DOWN_INT_CAUSE    5
75196 #define V_MAC_LINK_DOWN_INT_CAUSE(x) ((x) << S_MAC_LINK_DOWN_INT_CAUSE)
75197 #define F_MAC_LINK_DOWN_INT_CAUSE    V_MAC_LINK_DOWN_INT_CAUSE(1U)
75198 
75199 #define S_MAC_LINK_UP_INT_CAUSE    4
75200 #define V_MAC_LINK_UP_INT_CAUSE(x) ((x) << S_MAC_LINK_UP_INT_CAUSE)
75201 #define F_MAC_LINK_UP_INT_CAUSE    V_MAC_LINK_UP_INT_CAUSE(1U)
75202 
75203 #define S_MAC_AN_DONE_INT_CAUSE    3
75204 #define V_MAC_AN_DONE_INT_CAUSE(x) ((x) << S_MAC_AN_DONE_INT_CAUSE)
75205 #define F_MAC_AN_DONE_INT_CAUSE    V_MAC_AN_DONE_INT_CAUSE(1U)
75206 
75207 #define S_MAC_AN_PGRD_INT_CAUSE    2
75208 #define V_MAC_AN_PGRD_INT_CAUSE(x) ((x) << S_MAC_AN_PGRD_INT_CAUSE)
75209 #define F_MAC_AN_PGRD_INT_CAUSE    V_MAC_AN_PGRD_INT_CAUSE(1U)
75210 
75211 #define S_MAC_TXFIFO_ERR_INT_CAUSE    1
75212 #define V_MAC_TXFIFO_ERR_INT_CAUSE(x) ((x) << S_MAC_TXFIFO_ERR_INT_CAUSE)
75213 #define F_MAC_TXFIFO_ERR_INT_CAUSE    V_MAC_TXFIFO_ERR_INT_CAUSE(1U)
75214 
75215 #define S_MAC_RXFIFO_ERR_INT_CAUSE    0
75216 #define V_MAC_RXFIFO_ERR_INT_CAUSE(x) ((x) << S_MAC_RXFIFO_ERR_INT_CAUSE)
75217 #define F_MAC_RXFIFO_ERR_INT_CAUSE    V_MAC_RXFIFO_ERR_INT_CAUSE(1U)
75218 
75219 #define A_T7_MAC_PORT_PERR_INT_EN 0x870
75220 #define A_T7_MAC_PORT_PERR_INT_CAUSE 0x874
75221 #define A_T7_MAC_PORT_PERR_ENABLE 0x878
75222 #define A_T7_MAC_PORT_PERR_INJECT 0x87c
75223 
75224 #define S_T7_MEMSEL_PERR    1
75225 #define M_T7_MEMSEL_PERR    0xffU
75226 #define V_T7_MEMSEL_PERR(x) ((x) << S_T7_MEMSEL_PERR)
75227 #define G_T7_MEMSEL_PERR(x) (((x) >> S_T7_MEMSEL_PERR) & M_T7_MEMSEL_PERR)
75228 
75229 #define A_T7_MAC_PORT_RUNT_FRAME 0x880
75230 #define A_T7_MAC_PORT_EEE_STATUS 0x884
75231 #define A_T7_MAC_PORT_TX_TS_ID 0x888
75232 
75233 #define S_TS_ID_MSB    3
75234 #define V_TS_ID_MSB(x) ((x) << S_TS_ID_MSB)
75235 #define F_TS_ID_MSB    V_TS_ID_MSB(1U)
75236 
75237 #define A_T7_MAC_PORT_TX_TS_VAL_LO 0x88c
75238 #define A_T7_MAC_PORT_TX_TS_VAL_HI 0x890
75239 #define A_T7_MAC_PORT_EEE_CTL 0x894
75240 #define A_T7_MAC_PORT_EEE_TX_CTL 0x898
75241 #define A_T7_MAC_PORT_EEE_RX_CTL 0x89c
75242 #define A_T7_MAC_PORT_EEE_TX_10G_SLEEP_TIMER 0x8a0
75243 #define A_T7_MAC_PORT_EEE_TX_10G_QUIET_TIMER 0x8a4
75244 #define A_T7_MAC_PORT_EEE_TX_10G_WAKE_TIMER 0x8a8
75245 #define A_T7_MAC_PORT_EEE_RX_10G_QUIET_TIMER 0x8b8
75246 #define A_T7_MAC_PORT_EEE_RX_10G_WAKE_TIMER 0x8bc
75247 #define A_T7_MAC_PORT_EEE_RX_10G_WF_TIMER 0x8c0
75248 #define A_T7_MAC_PORT_EEE_WF_COUNT 0x8cc
75249 #define A_MAC_PORT_WOL_EN 0x8d0
75250 
75251 #define S_WOL_ENABLE    1
75252 #define V_WOL_ENABLE(x) ((x) << S_WOL_ENABLE)
75253 #define F_WOL_ENABLE    V_WOL_ENABLE(1U)
75254 
75255 #define S_WOL_INDICATOR    0
75256 #define V_WOL_INDICATOR(x) ((x) << S_WOL_INDICATOR)
75257 #define F_WOL_INDICATOR    V_WOL_INDICATOR(1U)
75258 
75259 #define A_MAC_PORT_INT_TRACE 0x8d4
75260 
75261 #define S_INTERRUPT    0
75262 #define M_INTERRUPT    0x7fffffffU
75263 #define V_INTERRUPT(x) ((x) << S_INTERRUPT)
75264 #define G_INTERRUPT(x) (((x) >> S_INTERRUPT) & M_INTERRUPT)
75265 
75266 #define A_MAC_PORT_TRACE_TS_LO 0x8d8
75267 #define A_MAC_PORT_TRACE_TS_HI 0x8dc
75268 #define A_MAC_PORT_MTIP_10G100G_REVISION 0x900
75269 
75270 #define S_VER_10G100G    8
75271 #define M_VER_10G100G    0xffU
75272 #define V_VER_10G100G(x) ((x) << S_VER_10G100G)
75273 #define G_VER_10G100G(x) (((x) >> S_VER_10G100G) & M_VER_10G100G)
75274 
75275 #define S_REV_10G100G    0
75276 #define M_REV_10G100G    0xffU
75277 #define V_REV_10G100G(x) ((x) << S_REV_10G100G)
75278 #define G_REV_10G100G(x) (((x) >> S_REV_10G100G) & M_REV_10G100G)
75279 
75280 #define A_MAC_PORT_MTIP_10G100G_SCRATCH 0x904
75281 #define A_MAC_PORT_MTIP_10G100G_COMMAND_CONFIG 0x908
75282 
75283 #define S_NO_PREAM    31
75284 #define V_NO_PREAM(x) ((x) << S_NO_PREAM)
75285 #define F_NO_PREAM    V_NO_PREAM(1U)
75286 
75287 #define S_SHORT_PREAM    30
75288 #define V_SHORT_PREAM(x) ((x) << S_SHORT_PREAM)
75289 #define F_SHORT_PREAM    V_SHORT_PREAM(1U)
75290 
75291 #define S_FLT_HDL_DIS    27
75292 #define V_FLT_HDL_DIS(x) ((x) << S_FLT_HDL_DIS)
75293 #define F_FLT_HDL_DIS    V_FLT_HDL_DIS(1U)
75294 
75295 #define S_TX_FIFO_RESET    26
75296 #define V_TX_FIFO_RESET(x) ((x) << S_TX_FIFO_RESET)
75297 #define F_TX_FIFO_RESET    V_TX_FIFO_RESET(1U)
75298 
75299 #define A_MAC_PORT_MTIP_10G100G_MAC_ADDR_0 0x90c
75300 #define A_MAC_PORT_MTIP_10G100G_MAC_ADDR_1 0x910
75301 #define A_MAC_PORT_MTIP_10G100G_FRM_LENGTH_TX_MTU 0x914
75302 #define A_MAC_PORT_MTIP_10G100G_RX_FIFO_SECTIONS 0x91c
75303 
75304 #define S_RX10G100G_EMPTY    16
75305 #define M_RX10G100G_EMPTY    0xffffU
75306 #define V_RX10G100G_EMPTY(x) ((x) << S_RX10G100G_EMPTY)
75307 #define G_RX10G100G_EMPTY(x) (((x) >> S_RX10G100G_EMPTY) & M_RX10G100G_EMPTY)
75308 
75309 #define S_RX10G100G_AVAIL    0
75310 #define M_RX10G100G_AVAIL    0xffffU
75311 #define V_RX10G100G_AVAIL(x) ((x) << S_RX10G100G_AVAIL)
75312 #define G_RX10G100G_AVAIL(x) (((x) >> S_RX10G100G_AVAIL) & M_RX10G100G_AVAIL)
75313 
75314 #define A_MAC_PORT_MTIP_10G100G_TX_FIFO_SECTIONS 0x920
75315 
75316 #define S_TX10G100G_EMPTY    16
75317 #define M_TX10G100G_EMPTY    0xffffU
75318 #define V_TX10G100G_EMPTY(x) ((x) << S_TX10G100G_EMPTY)
75319 #define G_TX10G100G_EMPTY(x) (((x) >> S_TX10G100G_EMPTY) & M_TX10G100G_EMPTY)
75320 
75321 #define S_TX10G100G_AVAIL    0
75322 #define M_TX10G100G_AVAIL    0xffffU
75323 #define V_TX10G100G_AVAIL(x) ((x) << S_TX10G100G_AVAIL)
75324 #define G_TX10G100G_AVAIL(x) (((x) >> S_TX10G100G_AVAIL) & M_TX10G100G_AVAIL)
75325 
75326 #define A_MAC_PORT_MTIP_10G100G_RX_FIFO_ALMOST_F_E 0x924
75327 #define A_MAC_PORT_MTIP_10G100G_TX_FIFO_ALMOST_F_E 0x928
75328 #define A_MAC_PORT_MTIP_10G100G_MDIO_CFG_STATUS 0x930
75329 #define A_MAC_PORT_MTIP_10G100G_MDIO_COMMAND 0x934
75330 #define A_MAC_PORT_MTIP_10G100G_MDIO_DATA 0x938
75331 #define A_MAC_PORT_MTIP_10G100G_MDIO_REGADDR 0x93c
75332 #define A_MAC_PORT_MTIP_10G100G_STATUS 0x940
75333 
75334 #define S_T7_TX_ISIDLE    8
75335 #define V_T7_TX_ISIDLE(x) ((x) << S_T7_TX_ISIDLE)
75336 #define F_T7_TX_ISIDLE    V_T7_TX_ISIDLE(1U)
75337 
75338 #define A_MAC_PORT_MTIP_10G100G_TX_IPG_LENGTH 0x944
75339 
75340 #define S_IPG_COMP_CNT    16
75341 #define M_IPG_COMP_CNT    0xffffU
75342 #define V_IPG_COMP_CNT(x) ((x) << S_IPG_COMP_CNT)
75343 #define G_IPG_COMP_CNT(x) (((x) >> S_IPG_COMP_CNT) & M_IPG_COMP_CNT)
75344 
75345 #define S_AVG_IPG_LEN    2
75346 #define M_AVG_IPG_LEN    0xfU
75347 #define V_AVG_IPG_LEN(x) ((x) << S_AVG_IPG_LEN)
75348 #define G_AVG_IPG_LEN(x) (((x) >> S_AVG_IPG_LEN) & M_AVG_IPG_LEN)
75349 
75350 #define S_DSBL_DIC    0
75351 #define V_DSBL_DIC(x) ((x) << S_DSBL_DIC)
75352 #define F_DSBL_DIC    V_DSBL_DIC(1U)
75353 
75354 #define A_MAC_PORT_MTIP_10G100G_CRC_MODE 0x948
75355 #define A_MAC_PORT_MTIP_10G100G_CL01_PAUSE_QUANTA 0x954
75356 #define A_MAC_PORT_MTIP_10G100G_CL23_PAUSE_QUANTA 0x958
75357 #define A_MAC_PORT_MTIP_10G100G_CL45_PAUSE_QUANTA 0x95c
75358 #define A_MAC_PORT_MTIP_10G100G_CL67_PAUSE_QUANTA 0x960
75359 #define A_MAC_PORT_MTIP_10G100G_CL01_QUANTA_THRESH 0x964
75360 #define A_MAC_PORT_MTIP_10G100G_CL23_QUANTA_THRESH 0x968
75361 #define A_MAC_PORT_MTIP_10G100G_CL45_QUANTA_THRESH 0x96c
75362 #define A_MAC_PORT_MTIP_10G100G_CL67_QUANTA_THRESH 0x970
75363 #define A_MAC_PORT_MTIP_10G100G_RX_PAUSE_STATUS 0x974
75364 #define A_MAC_PORT_MTIP_10G100G_TS_TIMESTAMP 0x97c
75365 #define A_MAC_PORT_MTIP_10G100G_XIF_MODE 0x980
75366 
75367 #define S_RX_CNT_MODE    16
75368 #define V_RX_CNT_MODE(x) ((x) << S_RX_CNT_MODE)
75369 #define F_RX_CNT_MODE    V_RX_CNT_MODE(1U)
75370 
75371 #define S_TS_UPD64_MODE    12
75372 #define V_TS_UPD64_MODE(x) ((x) << S_TS_UPD64_MODE)
75373 #define F_TS_UPD64_MODE    V_TS_UPD64_MODE(1U)
75374 
75375 #define S_TS_BINARY_MODE    11
75376 #define V_TS_BINARY_MODE(x) ((x) << S_TS_BINARY_MODE)
75377 #define F_TS_BINARY_MODE    V_TS_BINARY_MODE(1U)
75378 
75379 #define S_TS_DELAY_MODE    10
75380 #define V_TS_DELAY_MODE(x) ((x) << S_TS_DELAY_MODE)
75381 #define F_TS_DELAY_MODE    V_TS_DELAY_MODE(1U)
75382 
75383 #define S_TS_DELTA_MODE    9
75384 #define V_TS_DELTA_MODE(x) ((x) << S_TS_DELTA_MODE)
75385 #define F_TS_DELTA_MODE    V_TS_DELTA_MODE(1U)
75386 
75387 #define S_TX_MAC_RS_ERR    8
75388 #define V_TX_MAC_RS_ERR(x) ((x) << S_TX_MAC_RS_ERR)
75389 #define F_TX_MAC_RS_ERR    V_TX_MAC_RS_ERR(1U)
75390 
75391 #define S_RX_PAUSE_BYPASS    6
75392 #define V_RX_PAUSE_BYPASS(x) ((x) << S_RX_PAUSE_BYPASS)
75393 #define F_RX_PAUSE_BYPASS    V_RX_PAUSE_BYPASS(1U)
75394 
75395 #define S_ONE_STEP_ENA    5
75396 #define V_ONE_STEP_ENA(x) ((x) << S_ONE_STEP_ENA)
75397 #define F_ONE_STEP_ENA    V_ONE_STEP_ENA(1U)
75398 
75399 #define S_PAUSETIMERX8    4
75400 #define V_PAUSETIMERX8(x) ((x) << S_PAUSETIMERX8)
75401 #define F_PAUSETIMERX8    V_PAUSETIMERX8(1U)
75402 
75403 #define S_XGMII_ENA    0
75404 #define V_XGMII_ENA(x) ((x) << S_XGMII_ENA)
75405 #define F_XGMII_ENA    V_XGMII_ENA(1U)
75406 
75407 #define A_MAC_PORT_MTIP_CR4_0_CONTROL_1 0xa00
75408 #define A_MAC_PORT_MTIP_CR4_0_STATUS_1 0xa04
75409 
75410 #define S_CR4_0_RX_LINK_STATUS    2
75411 #define V_CR4_0_RX_LINK_STATUS(x) ((x) << S_CR4_0_RX_LINK_STATUS)
75412 #define F_CR4_0_RX_LINK_STATUS    V_CR4_0_RX_LINK_STATUS(1U)
75413 
75414 #define A_MAC_PORT_MTIP_CR4_0_DEVICE_ID0 0xa08
75415 
75416 #define S_CR4_0_DEVICE_ID0    0
75417 #define M_CR4_0_DEVICE_ID0    0xffffU
75418 #define V_CR4_0_DEVICE_ID0(x) ((x) << S_CR4_0_DEVICE_ID0)
75419 #define G_CR4_0_DEVICE_ID0(x) (((x) >> S_CR4_0_DEVICE_ID0) & M_CR4_0_DEVICE_ID0)
75420 
75421 #define A_MAC_PORT_MTIP_CR4_0_DEVICE_ID1 0xa0c
75422 
75423 #define S_CR4_0_DEVICE_ID1    0
75424 #define M_CR4_0_DEVICE_ID1    0xffffU
75425 #define V_CR4_0_DEVICE_ID1(x) ((x) << S_CR4_0_DEVICE_ID1)
75426 #define G_CR4_0_DEVICE_ID1(x) (((x) >> S_CR4_0_DEVICE_ID1) & M_CR4_0_DEVICE_ID1)
75427 
75428 #define A_MAC_PORT_MTIP_CR4_0_SPEED_ABILITY 0xa10
75429 
75430 #define S_50G_CAPABLE    5
75431 #define V_50G_CAPABLE(x) ((x) << S_50G_CAPABLE)
75432 #define F_50G_CAPABLE    V_50G_CAPABLE(1U)
75433 
75434 #define S_25G_CAPABLE    4
75435 #define V_25G_CAPABLE(x) ((x) << S_25G_CAPABLE)
75436 #define F_25G_CAPABLE    V_25G_CAPABLE(1U)
75437 
75438 #define A_MAC_PORT_MTIP_CR4_0_DEVICES_IN_PKG1 0xa14
75439 #define A_MAC_PORT_MTIP_CR4_0_DEVICES_IN_PKG2 0xa18
75440 #define A_MAC_PORT_MTIP_CR4_0_CONTROL_2 0xa1c
75441 
75442 #define S_T7_PCS_TYPE_SELECTION    0
75443 #define M_T7_PCS_TYPE_SELECTION    0xfU
75444 #define V_T7_PCS_TYPE_SELECTION(x) ((x) << S_T7_PCS_TYPE_SELECTION)
75445 #define G_T7_PCS_TYPE_SELECTION(x) (((x) >> S_T7_PCS_TYPE_SELECTION) & M_T7_PCS_TYPE_SELECTION)
75446 
75447 #define A_MAC_PORT_MTIP_CR4_0_STATUS_2 0xa20
75448 
75449 #define S_50GBASE_R_CAPABLE    8
75450 #define V_50GBASE_R_CAPABLE(x) ((x) << S_50GBASE_R_CAPABLE)
75451 #define F_50GBASE_R_CAPABLE    V_50GBASE_R_CAPABLE(1U)
75452 
75453 #define S_25GBASE_R_CAPABLE    7
75454 #define V_25GBASE_R_CAPABLE(x) ((x) << S_25GBASE_R_CAPABLE)
75455 #define F_25GBASE_R_CAPABLE    V_25GBASE_R_CAPABLE(1U)
75456 
75457 #define A_MAC_PORT_MTIP_CR4_0_PKG_ID0 0xa38
75458 #define A_MAC_PORT_MTIP_CR4_0_PKG_ID1 0xa3c
75459 #define A_MAC_PORT_MTIP_CR4_0_EEE_CTRL 0xa50
75460 
75461 #define S_50GBASE_R_FW    14
75462 #define V_50GBASE_R_FW(x) ((x) << S_50GBASE_R_FW)
75463 #define F_50GBASE_R_FW    V_50GBASE_R_FW(1U)
75464 
75465 #define S_100GBASE_R_DS    13
75466 #define V_100GBASE_R_DS(x) ((x) << S_100GBASE_R_DS)
75467 #define F_100GBASE_R_DS    V_100GBASE_R_DS(1U)
75468 
75469 #define S_100GBASE_R_FW    12
75470 #define V_100GBASE_R_FW(x) ((x) << S_100GBASE_R_FW)
75471 #define F_100GBASE_R_FW    V_100GBASE_R_FW(1U)
75472 
75473 #define S_25GBASE_R_DS    11
75474 #define V_25GBASE_R_DS(x) ((x) << S_25GBASE_R_DS)
75475 #define F_25GBASE_R_DS    V_25GBASE_R_DS(1U)
75476 
75477 #define S_25GBASE_R_FW    10
75478 #define V_25GBASE_R_FW(x) ((x) << S_25GBASE_R_FW)
75479 #define F_25GBASE_R_FW    V_25GBASE_R_FW(1U)
75480 
75481 #define S_40GBASE_R_DS    9
75482 #define V_40GBASE_R_DS(x) ((x) << S_40GBASE_R_DS)
75483 #define F_40GBASE_R_DS    V_40GBASE_R_DS(1U)
75484 
75485 #define S_40GBASE_R_FW    8
75486 #define V_40GBASE_R_FW(x) ((x) << S_40GBASE_R_FW)
75487 #define F_40GBASE_R_FW    V_40GBASE_R_FW(1U)
75488 
75489 #define S_10GBASE_KE_EEE    6
75490 #define V_10GBASE_KE_EEE(x) ((x) << S_10GBASE_KE_EEE)
75491 #define F_10GBASE_KE_EEE    V_10GBASE_KE_EEE(1U)
75492 
75493 #define S_FAST_WAKE    1
75494 #define M_FAST_WAKE    0x1fU
75495 #define V_FAST_WAKE(x) ((x) << S_FAST_WAKE)
75496 #define G_FAST_WAKE(x) (((x) >> S_FAST_WAKE) & M_FAST_WAKE)
75497 
75498 #define S_DEEP_SLEEP    0
75499 #define V_DEEP_SLEEP(x) ((x) << S_DEEP_SLEEP)
75500 #define F_DEEP_SLEEP    V_DEEP_SLEEP(1U)
75501 
75502 #define A_MAC_PORT_MTIP_CR4_0_WAKE_ERROR_COUNTER 0xa58
75503 
75504 #define S_WAKE_ERROR_COUNTER    0
75505 #define M_WAKE_ERROR_COUNTER    0x1ffffU
75506 #define V_WAKE_ERROR_COUNTER(x) ((x) << S_WAKE_ERROR_COUNTER)
75507 #define G_WAKE_ERROR_COUNTER(x) (((x) >> S_WAKE_ERROR_COUNTER) & M_WAKE_ERROR_COUNTER)
75508 
75509 #define A_MAC_PORT_MTIP_CR4_0_BASE_R_STATUS_1 0xa80
75510 
75511 #define S_CR4_0_BR_BLOCK_LOCK    0
75512 #define V_CR4_0_BR_BLOCK_LOCK(x) ((x) << S_CR4_0_BR_BLOCK_LOCK)
75513 #define F_CR4_0_BR_BLOCK_LOCK    V_CR4_0_BR_BLOCK_LOCK(1U)
75514 
75515 #define A_MAC_PORT_MTIP_CR4_0_BASE_R_STATUS_2 0xa84
75516 #define A_MAC_PORT_MTIP_CR4_0_SEED_A_0 0xa88
75517 
75518 #define S_SEED_A_0    0
75519 #define M_SEED_A_0    0xffffU
75520 #define V_SEED_A_0(x) ((x) << S_SEED_A_0)
75521 #define G_SEED_A_0(x) (((x) >> S_SEED_A_0) & M_SEED_A_0)
75522 
75523 #define A_MAC_PORT_MTIP_CR4_0_SEED_A_1 0xa8c
75524 
75525 #define S_SEED_A_1    0
75526 #define M_SEED_A_1    0xffffU
75527 #define V_SEED_A_1(x) ((x) << S_SEED_A_1)
75528 #define G_SEED_A_1(x) (((x) >> S_SEED_A_1) & M_SEED_A_1)
75529 
75530 #define A_MAC_PORT_MTIP_CR4_0_SEED_A_2 0xa90
75531 
75532 #define S_SEED_A_2    0
75533 #define M_SEED_A_2    0xffffU
75534 #define V_SEED_A_2(x) ((x) << S_SEED_A_2)
75535 #define G_SEED_A_2(x) (((x) >> S_SEED_A_2) & M_SEED_A_2)
75536 
75537 #define A_MAC_PORT_MTIP_CR4_0_SEED_A_3 0xa94
75538 
75539 #define S_SEED_A_3    0
75540 #define M_SEED_A_3    0xffffU
75541 #define V_SEED_A_3(x) ((x) << S_SEED_A_3)
75542 #define G_SEED_A_3(x) (((x) >> S_SEED_A_3) & M_SEED_A_3)
75543 
75544 #define A_MAC_PORT_MTIP_CR4_0_SEED_B_0 0xa98
75545 
75546 #define S_SEED_B_0    0
75547 #define M_SEED_B_0    0xffffU
75548 #define V_SEED_B_0(x) ((x) << S_SEED_B_0)
75549 #define G_SEED_B_0(x) (((x) >> S_SEED_B_0) & M_SEED_B_0)
75550 
75551 #define A_MAC_PORT_MTIP_CR4_0_SEED_B_1 0xa9c
75552 
75553 #define S_SEED_B_1    0
75554 #define M_SEED_B_1    0xffffU
75555 #define V_SEED_B_1(x) ((x) << S_SEED_B_1)
75556 #define G_SEED_B_1(x) (((x) >> S_SEED_B_1) & M_SEED_B_1)
75557 
75558 #define A_MAC_PORT_MTIP_CR4_0_SEED_B_2 0xaa0
75559 
75560 #define S_SEED_B_2    0
75561 #define M_SEED_B_2    0xffffU
75562 #define V_SEED_B_2(x) ((x) << S_SEED_B_2)
75563 #define G_SEED_B_2(x) (((x) >> S_SEED_B_2) & M_SEED_B_2)
75564 
75565 #define A_MAC_PORT_MTIP_CR4_0_SEED_B_3 0xaa4
75566 
75567 #define S_SEED_B_3    0
75568 #define M_SEED_B_3    0xffffU
75569 #define V_SEED_B_3(x) ((x) << S_SEED_B_3)
75570 #define G_SEED_B_3(x) (((x) >> S_SEED_B_3) & M_SEED_B_3)
75571 
75572 #define A_MAC_PORT_MTIP_CR4_0_BASE_R_TEST_PATTERN_CONTROL 0xaa8
75573 
75574 #define S_TEST_PATTERN_40G    7
75575 #define V_TEST_PATTERN_40G(x) ((x) << S_TEST_PATTERN_40G)
75576 #define F_TEST_PATTERN_40G    V_TEST_PATTERN_40G(1U)
75577 
75578 #define A_MAC_PORT_MTIP_CR4_0_BASE_R_TEST_ERR_CNT 0xaac
75579 #define A_MAC_PORT_MTIP_CR4_0_BER_HIGH_ORDER_CNT 0xab0
75580 
75581 #define S_BASE_R_BER_HIGH_ORDER_CNT    0
75582 #define M_BASE_R_BER_HIGH_ORDER_CNT    0xffffU
75583 #define V_BASE_R_BER_HIGH_ORDER_CNT(x) ((x) << S_BASE_R_BER_HIGH_ORDER_CNT)
75584 #define G_BASE_R_BER_HIGH_ORDER_CNT(x) (((x) >> S_BASE_R_BER_HIGH_ORDER_CNT) & M_BASE_R_BER_HIGH_ORDER_CNT)
75585 
75586 #define A_MAC_PORT_MTIP_CR4_0_ERR_BLK_HIGH_ORDER_CNT 0xab4
75587 #define A_MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_1 0xac8
75588 #define A_MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_2 0xacc
75589 #define A_MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_3 0xad0
75590 #define A_MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_4 0xad4
75591 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_0 0xad8
75592 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_1 0xadc
75593 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_2 0xae0
75594 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_3 0xae4
75595 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_4 0xae8
75596 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_5 0xaec
75597 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_6 0xaf0
75598 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_7 0xaf4
75599 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_8 0xaf8
75600 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_9 0xafc
75601 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_10 0xb00
75602 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_11 0xb04
75603 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_12 0xb08
75604 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_13 0xb0c
75605 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_14 0xb10
75606 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_15 0xb14
75607 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_16 0xb18
75608 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_17 0xb1c
75609 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_18 0xb20
75610 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_19 0xb24
75611 #define A_MAC_PORT_MTIP_CR4_0_LANE_0_MAPPING 0xb28
75612 #define A_MAC_PORT_MTIP_CR4_0_LANE_1_MAPPING 0xb2c
75613 #define A_MAC_PORT_MTIP_CR4_0_LANE_2_MAPPING 0xb30
75614 #define A_MAC_PORT_MTIP_CR4_0_LANE_3_MAPPING 0xb34
75615 #define A_MAC_PORT_MTIP_CR4_0_LANE_4_MAPPING 0xb38
75616 #define A_MAC_PORT_MTIP_CR4_0_LANE_5_MAPPING 0xb3c
75617 #define A_MAC_PORT_MTIP_CR4_0_LANE_6_MAPPING 0xb40
75618 #define A_MAC_PORT_MTIP_CR4_0_LANE_7_MAPPING 0xb44
75619 #define A_MAC_PORT_MTIP_CR4_0_LANE_8_MAPPING 0xb48
75620 #define A_MAC_PORT_MTIP_CR4_0_LANE_9_MAPPING 0xb4c
75621 #define A_MAC_PORT_MTIP_CR4_0_LANE_10_MAPPING 0xb50
75622 #define A_MAC_PORT_MTIP_CR4_0_LANE_11_MAPPING 0xb54
75623 #define A_MAC_PORT_MTIP_CR4_0_LANE_12_MAPPING 0xb58
75624 #define A_MAC_PORT_MTIP_CR4_0_LANE_13_MAPPING 0xb5c
75625 #define A_MAC_PORT_MTIP_CR4_0_LANE_14_MAPPING 0xb60
75626 #define A_MAC_PORT_MTIP_CR4_0_LANE_15_MAPPING 0xb64
75627 #define A_MAC_PORT_MTIP_CR4_0_LANE_16_MAPPING 0xb68
75628 #define A_MAC_PORT_MTIP_CR4_0_LANE_17_MAPPING 0xb6c
75629 #define A_MAC_PORT_MTIP_CR4_0_LANE_18_MAPPING 0xb70
75630 #define A_MAC_PORT_MTIP_CR4_0_LANE_19_MAPPING 0xb74
75631 #define A_MAC_PORT_MTIP_CR4_0_SCRATCH 0xb78
75632 #define A_MAC_PORT_MTIP_CR4_0_CORE_REVISION 0xb7c
75633 #define A_MAC_PORT_MTIP_CR4_0_VL_INTVL 0xb80
75634 
75635 #define S_VL_INTCL    0
75636 #define M_VL_INTCL    0xffffU
75637 #define V_VL_INTCL(x) ((x) << S_VL_INTCL)
75638 #define G_VL_INTCL(x) (((x) >> S_VL_INTCL) & M_VL_INTCL)
75639 
75640 #define A_MAC_PORT_MTIP_CR4_0_TX_LANE_THRESH 0xb84
75641 
75642 #define S_LANE6_LANE7    12
75643 #define M_LANE6_LANE7    0xfU
75644 #define V_LANE6_LANE7(x) ((x) << S_LANE6_LANE7)
75645 #define G_LANE6_LANE7(x) (((x) >> S_LANE6_LANE7) & M_LANE6_LANE7)
75646 
75647 #define S_LANE4_LANE5    8
75648 #define M_LANE4_LANE5    0xfU
75649 #define V_LANE4_LANE5(x) ((x) << S_LANE4_LANE5)
75650 #define G_LANE4_LANE5(x) (((x) >> S_LANE4_LANE5) & M_LANE4_LANE5)
75651 
75652 #define S_LANE2_LANE3    4
75653 #define M_LANE2_LANE3    0xfU
75654 #define V_LANE2_LANE3(x) ((x) << S_LANE2_LANE3)
75655 #define G_LANE2_LANE3(x) (((x) >> S_LANE2_LANE3) & M_LANE2_LANE3)
75656 
75657 #define S_LANE0_LANE1    0
75658 #define M_LANE0_LANE1    0xfU
75659 #define V_LANE0_LANE1(x) ((x) << S_LANE0_LANE1)
75660 #define G_LANE0_LANE1(x) (((x) >> S_LANE0_LANE1) & M_LANE0_LANE1)
75661 
75662 #define A_MAC_PORT_MTIP_CR4_0_VL0_0 0xb98
75663 
75664 #define S_M1    8
75665 #define M_M1    0xffU
75666 #define V_M1(x) ((x) << S_M1)
75667 #define G_M1(x) (((x) >> S_M1) & M_M1)
75668 
75669 #define S_M0    0
75670 #define M_M0    0xffU
75671 #define V_M0(x) ((x) << S_M0)
75672 #define G_M0(x) (((x) >> S_M0) & M_M0)
75673 
75674 #define A_MAC_PORT_MTIP_CR4_0_VL0_1 0xb9c
75675 
75676 #define S_M2    0
75677 #define M_M2    0xffU
75678 #define V_M2(x) ((x) << S_M2)
75679 #define G_M2(x) (((x) >> S_M2) & M_M2)
75680 
75681 #define A_MAC_PORT_MTIP_CR4_0_VL1_0 0xba0
75682 #define A_MAC_PORT_MTIP_CR4_0_VL1_1 0xba4
75683 #define A_MAC_PORT_MTIP_CR4_0_VL2_0 0xba8
75684 #define A_MAC_PORT_MTIP_CR4_0_VL2_1 0xbac
75685 #define A_MAC_PORT_MTIP_CR4_0_VL3_0 0xbb0
75686 #define A_MAC_PORT_MTIP_CR4_0_VL3_1 0xbb4
75687 #define A_MAC_PORT_MTIP_CR4_0_PCS_MODE 0xbb8
75688 
75689 #define S_ST_DISABLE_MLD    9
75690 #define V_ST_DISABLE_MLD(x) ((x) << S_ST_DISABLE_MLD)
75691 #define F_ST_DISABLE_MLD    V_ST_DISABLE_MLD(1U)
75692 
75693 #define S_ST_EN_CLAUSE49    8
75694 #define V_ST_EN_CLAUSE49(x) ((x) << S_ST_EN_CLAUSE49)
75695 #define F_ST_EN_CLAUSE49    V_ST_EN_CLAUSE49(1U)
75696 
75697 #define S_HI_BER25    2
75698 #define V_HI_BER25(x) ((x) << S_HI_BER25)
75699 #define F_HI_BER25    V_HI_BER25(1U)
75700 
75701 #define S_DISABLE_MLD    1
75702 #define V_DISABLE_MLD(x) ((x) << S_DISABLE_MLD)
75703 #define F_DISABLE_MLD    V_DISABLE_MLD(1U)
75704 
75705 #define S_ENA_CLAUSE49    0
75706 #define V_ENA_CLAUSE49(x) ((x) << S_ENA_CLAUSE49)
75707 #define F_ENA_CLAUSE49    V_ENA_CLAUSE49(1U)
75708 
75709 #define A_MAC_PORT_MTIP_CR4_0_VL4_0 0xc98
75710 #define A_MAC_PORT_MTIP_CR4_0_VL4_1 0xc9c
75711 #define A_MAC_PORT_MTIP_CR4_0_VL5_0 0xca0
75712 #define A_MAC_PORT_MTIP_CR4_0_VL5_1 0xca4
75713 #define A_MAC_PORT_MTIP_CR4_0_VL6_0 0xca8
75714 #define A_MAC_PORT_MTIP_CR4_0_VL6_1 0xcac
75715 #define A_MAC_PORT_MTIP_CR4_0_VL7_0 0xcb0
75716 #define A_MAC_PORT_MTIP_CR4_0_VL7_1 0xcb4
75717 #define A_MAC_PORT_MTIP_CR4_0_VL8_0 0xcb8
75718 #define A_MAC_PORT_MTIP_CR4_0_VL8_1 0xcbc
75719 #define A_MAC_PORT_MTIP_CR4_0_VL9_0 0xcc0
75720 #define A_MAC_PORT_MTIP_CR4_0_VL9_1 0xcc4
75721 #define A_MAC_PORT_MTIP_CR4_0_VL10_0 0xcc8
75722 #define A_MAC_PORT_MTIP_CR4_0_VL10_1 0xccc
75723 #define A_MAC_PORT_MTIP_CR4_0_VL11_0 0xcd0
75724 #define A_MAC_PORT_MTIP_CR4_0_VL11_1 0xcd4
75725 #define A_MAC_PORT_MTIP_CR4_0_VL12_0 0xcd8
75726 #define A_MAC_PORT_MTIP_CR4_0_VL12_1 0xcdc
75727 #define A_MAC_PORT_MTIP_CR4_0_VL13_0 0xce0
75728 #define A_MAC_PORT_MTIP_CR4_0_VL13_1 0xce4
75729 #define A_MAC_PORT_MTIP_CR4_0_VL14_0 0xce8
75730 #define A_MAC_PORT_MTIP_CR4_0_VL14_1 0xcec
75731 #define A_MAC_PORT_MTIP_CR4_0_VL15_0 0xcf0
75732 #define A_MAC_PORT_MTIP_CR4_0_VL15_1 0xcf4
75733 #define A_MAC_PORT_MTIP_CR4_0_VL16_0 0xcf8
75734 #define A_MAC_PORT_MTIP_CR4_0_VL16_1 0xcfc
75735 #define A_MAC_PORT_MTIP_CR4_0_VL17_0 0xd00
75736 #define A_MAC_PORT_MTIP_CR4_0_VL17_1 0xd04
75737 #define A_MAC_PORT_MTIP_CR4_0_VL18_0 0xd08
75738 #define A_MAC_PORT_MTIP_CR4_0_VL18_1 0xd0c
75739 #define A_MAC_PORT_MTIP_CR4_0_VL19_0 0xd10
75740 #define A_MAC_PORT_MTIP_CR4_0_VL19_1 0xd14
75741 #define A_MAC_PORT_MTIP_CR4_1_CONTROL_1 0x1000
75742 #define A_MAC_PORT_MTIP_CR4_1_STATUS_1 0x1004
75743 
75744 #define S_CR4_RX_LINK_STATUS_1    2
75745 #define V_CR4_RX_LINK_STATUS_1(x) ((x) << S_CR4_RX_LINK_STATUS_1)
75746 #define F_CR4_RX_LINK_STATUS_1    V_CR4_RX_LINK_STATUS_1(1U)
75747 
75748 #define A_MAC_PORT_MTIP_CR4_1_DEVICE_ID0 0x1008
75749 
75750 #define S_CR4_1_DEVICE_ID0    0
75751 #define M_CR4_1_DEVICE_ID0    0xffffU
75752 #define V_CR4_1_DEVICE_ID0(x) ((x) << S_CR4_1_DEVICE_ID0)
75753 #define G_CR4_1_DEVICE_ID0(x) (((x) >> S_CR4_1_DEVICE_ID0) & M_CR4_1_DEVICE_ID0)
75754 
75755 #define A_MAC_PORT_MTIP_CR4_1_DEVICE_ID1 0x100c
75756 
75757 #define S_CR4_1_DEVICE_ID1    0
75758 #define M_CR4_1_DEVICE_ID1    0xffffU
75759 #define V_CR4_1_DEVICE_ID1(x) ((x) << S_CR4_1_DEVICE_ID1)
75760 #define G_CR4_1_DEVICE_ID1(x) (((x) >> S_CR4_1_DEVICE_ID1) & M_CR4_1_DEVICE_ID1)
75761 
75762 #define A_MAC_PORT_MTIP_CR4_1_SPEED_ABILITY 0x1010
75763 #define A_MAC_PORT_MTIP_CR4_1_DEVICES_IN_PKG1 0x1014
75764 #define A_MAC_PORT_MTIP_CR4_1_DEVICES_IN_PKG2 0x1018
75765 #define A_MAC_PORT_MTIP_CR4_1_CONTROL_2 0x101c
75766 #define A_MAC_PORT_MTIP_CR4_1_STATUS_2 0x1020
75767 #define A_MAC_PORT_MTIP_CR4_1_PKG_ID0 0x1038
75768 #define A_MAC_PORT_MTIP_CR4_1_PKG_ID1 0x103c
75769 #define A_MAC_PORT_MTIP_CR4_1_EEE_CTRL 0x1050
75770 #define A_MAC_PORT_MTIP_CR4_1_WAKE_ERROR_COUNTER 0x1058
75771 #define A_MAC_PORT_MTIP_CR4_1_BASE_R_STATUS_1 0x1080
75772 
75773 #define S_CR4_1_BR_BLOCK_LOCK    0
75774 #define V_CR4_1_BR_BLOCK_LOCK(x) ((x) << S_CR4_1_BR_BLOCK_LOCK)
75775 #define F_CR4_1_BR_BLOCK_LOCK    V_CR4_1_BR_BLOCK_LOCK(1U)
75776 
75777 #define A_MAC_PORT_MTIP_CR4_1_BASE_R_STATUS_2 0x1084
75778 #define A_MAC_PORT_MTIP_CR4_1_SEED_A_0 0x1088
75779 #define A_MAC_PORT_MTIP_CR4_1_SEED_A_1 0x108c
75780 #define A_MAC_PORT_MTIP_CR4_1_SEED_A_2 0x1090
75781 #define A_MAC_PORT_MTIP_CR4_1_SEED_A_3 0x1094
75782 #define A_MAC_PORT_MTIP_CR4_1_SEED_B_0 0x1098
75783 #define A_MAC_PORT_MTIP_CR4_1_SEED_B_1 0x109c
75784 #define A_MAC_PORT_MTIP_CR4_1_SEED_B_2 0x10a0
75785 #define A_MAC_PORT_MTIP_CR4_1_SEED_B_3 0x10a4
75786 #define A_MAC_PORT_MTIP_CR4_1_BASE_R_TEST_PATTERN_CONTROL 0x10a8
75787 #define A_MAC_PORT_MTIP_CR4_1_BASE_R_TEST_ERR_CNT 0x10ac
75788 #define A_MAC_PORT_MTIP_CR4_1_BER_HIGH_ORDER_CNT 0x10b0
75789 #define A_MAC_PORT_MTIP_CR4_1_ERR_BLK_HIGH_ORDER_CNT 0x10b4
75790 #define A_MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_1 0x10c8
75791 #define A_MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_2 0x10cc
75792 #define A_MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_3 0x10d0
75793 #define A_MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_4 0x10d4
75794 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_0 0x10d8
75795 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_1 0x10dc
75796 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_2 0x10e0
75797 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_3 0x10e4
75798 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_4 0x10e8
75799 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_5 0x10ec
75800 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_6 0x10f0
75801 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_7 0x10f4
75802 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_8 0x10f8
75803 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_9 0x10fc
75804 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_10 0x1100
75805 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_11 0x1104
75806 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_12 0x1108
75807 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_13 0x110c
75808 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_14 0x1110
75809 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_15 0x1114
75810 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_16 0x1118
75811 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_17 0x111c
75812 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_18 0x1120
75813 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_19 0x1124
75814 #define A_MAC_PORT_MTIP_CR4_1_LANE_0_MAPPING 0x1128
75815 #define A_MAC_PORT_MTIP_CR4_1_LANE_1_MAPPING 0x112c
75816 #define A_MAC_PORT_MTIP_CR4_1_LANE_2_MAPPING 0x1130
75817 #define A_MAC_PORT_MTIP_CR4_1_LANE_3_MAPPING 0x1134
75818 #define A_MAC_PORT_MTIP_CR4_1_LANE_4_MAPPING 0x1138
75819 #define A_MAC_PORT_MTIP_CR4_1_LANE_5_MAPPING 0x113c
75820 #define A_MAC_PORT_MTIP_CR4_1_LANE_6_MAPPING 0x1140
75821 #define A_MAC_PORT_MTIP_CR4_1_LANE_7_MAPPING 0x1144
75822 #define A_MAC_PORT_MTIP_CR4_1_LANE_8_MAPPING 0x1148
75823 #define A_MAC_PORT_MTIP_CR4_1_LANE_9_MAPPING 0x114c
75824 #define A_MAC_PORT_MTIP_CR4_1_LANE_10_MAPPING 0x1150
75825 #define A_MAC_PORT_MTIP_CR4_1_LANE_11_MAPPING 0x1154
75826 #define A_MAC_PORT_MTIP_CR4_1_LANE_12_MAPPING 0x1158
75827 #define A_MAC_PORT_MTIP_CR4_1_LANE_13_MAPPING 0x115c
75828 #define A_MAC_PORT_MTIP_CR4_1_LANE_14_MAPPING 0x1160
75829 #define A_MAC_PORT_MTIP_CR4_1_LANE_15_MAPPING 0x1164
75830 #define A_MAC_PORT_MTIP_CR4_1_LANE_16_MAPPING 0x1168
75831 #define A_MAC_PORT_MTIP_CR4_1_LANE_17_MAPPING 0x116c
75832 #define A_MAC_PORT_MTIP_CR4_1_LANE_18_MAPPING 0x1170
75833 #define A_MAC_PORT_MTIP_CR4_1_LANE_19_MAPPING 0x1174
75834 #define A_MAC_PORT_MTIP_CR4_1_SCRATCH 0x1178
75835 #define A_MAC_PORT_MTIP_CR4_1_CORE_REVISION 0x117c
75836 #define A_MAC_PORT_MTIP_CR4_1_VL_INTVL 0x1180
75837 #define A_MAC_PORT_MTIP_CR4_1_TX_LANE_THRESH 0x1184
75838 #define A_MAC_PORT_MTIP_CR4_1_VL0_0 0x1198
75839 #define A_MAC_PORT_MTIP_CR4_1_VL0_1 0x119c
75840 #define A_MAC_PORT_MTIP_CR4_1_VL1_0 0x11a0
75841 #define A_MAC_PORT_MTIP_CR4_1_VL1_1 0x11a4
75842 #define A_MAC_PORT_MTIP_CR4_1_VL2_0 0x11a8
75843 #define A_MAC_PORT_MTIP_CR4_1_VL2_1 0x11ac
75844 #define A_MAC_PORT_MTIP_CR4_1_VL3_0 0x11b0
75845 #define A_MAC_PORT_MTIP_CR4_1_VL3_1 0x11b4
75846 #define A_MAC_PORT_MTIP_CR4_1_PCS_MODE 0x11b8
75847 #define A_MAC_COMMON_CFG_0 0x38000
75848 
75849 #define S_T7_RX_POLARITY_INV    24
75850 #define M_T7_RX_POLARITY_INV    0xffU
75851 #define V_T7_RX_POLARITY_INV(x) ((x) << S_T7_RX_POLARITY_INV)
75852 #define G_T7_RX_POLARITY_INV(x) (((x) >> S_T7_RX_POLARITY_INV) & M_T7_RX_POLARITY_INV)
75853 
75854 #define S_T7_TX_POLARITY_INV    16
75855 #define M_T7_TX_POLARITY_INV    0xffU
75856 #define V_T7_TX_POLARITY_INV(x) ((x) << S_T7_TX_POLARITY_INV)
75857 #define G_T7_TX_POLARITY_INV(x) (((x) >> S_T7_TX_POLARITY_INV) & M_T7_TX_POLARITY_INV)
75858 
75859 #define S_T7_DEBUG_PORT_SEL    14
75860 #define M_T7_DEBUG_PORT_SEL    0x3U
75861 #define V_T7_DEBUG_PORT_SEL(x) ((x) << S_T7_DEBUG_PORT_SEL)
75862 #define G_T7_DEBUG_PORT_SEL(x) (((x) >> S_T7_DEBUG_PORT_SEL) & M_T7_DEBUG_PORT_SEL)
75863 
75864 #define S_MAC_SEPTY_CTL    8
75865 #define M_MAC_SEPTY_CTL    0x3fU
75866 #define V_MAC_SEPTY_CTL(x) ((x) << S_MAC_SEPTY_CTL)
75867 #define G_MAC_SEPTY_CTL(x) (((x) >> S_MAC_SEPTY_CTL) & M_MAC_SEPTY_CTL)
75868 
75869 #define S_T7_DEBUG_TX_RX_SEL    7
75870 #define V_T7_DEBUG_TX_RX_SEL(x) ((x) << S_T7_DEBUG_TX_RX_SEL)
75871 #define F_T7_DEBUG_TX_RX_SEL    V_T7_DEBUG_TX_RX_SEL(1U)
75872 
75873 #define S_MAC_RDY_CTL    0
75874 #define M_MAC_RDY_CTL    0x3fU
75875 #define V_MAC_RDY_CTL(x) ((x) << S_MAC_RDY_CTL)
75876 #define G_MAC_RDY_CTL(x) (((x) >> S_MAC_RDY_CTL) & M_MAC_RDY_CTL)
75877 
75878 #define A_MAC_MTIP_RESET_CTRL_0 0x38004
75879 
75880 #define S_RESET_F91_REF_CLK_I    31
75881 #define V_RESET_F91_REF_CLK_I(x) ((x) << S_RESET_F91_REF_CLK_I)
75882 #define F_RESET_F91_REF_CLK_I    V_RESET_F91_REF_CLK_I(1U)
75883 
75884 #define S_RESET_PCS000_REF_CLK_I    30
75885 #define V_RESET_PCS000_REF_CLK_I(x) ((x) << S_RESET_PCS000_REF_CLK_I)
75886 #define F_RESET_PCS000_REF_CLK_I    V_RESET_PCS000_REF_CLK_I(1U)
75887 
75888 #define S_RESET_REF_CLK_I    29
75889 #define V_RESET_REF_CLK_I(x) ((x) << S_RESET_REF_CLK_I)
75890 #define F_RESET_REF_CLK_I    V_RESET_REF_CLK_I(1U)
75891 
75892 #define S_RESET_SD_RX_CLK_I_0    28
75893 #define V_RESET_SD_RX_CLK_I_0(x) ((x) << S_RESET_SD_RX_CLK_I_0)
75894 #define F_RESET_SD_RX_CLK_I_0    V_RESET_SD_RX_CLK_I_0(1U)
75895 
75896 #define S_RESET_SD_RX_CLK_I_1    27
75897 #define V_RESET_SD_RX_CLK_I_1(x) ((x) << S_RESET_SD_RX_CLK_I_1)
75898 #define F_RESET_SD_RX_CLK_I_1    V_RESET_SD_RX_CLK_I_1(1U)
75899 
75900 #define S_RESET_SD_RX_CLK_I_2    26
75901 #define V_RESET_SD_RX_CLK_I_2(x) ((x) << S_RESET_SD_RX_CLK_I_2)
75902 #define F_RESET_SD_RX_CLK_I_2    V_RESET_SD_RX_CLK_I_2(1U)
75903 
75904 #define S_RESET_SD_RX_CLK_I_3    25
75905 #define V_RESET_SD_RX_CLK_I_3(x) ((x) << S_RESET_SD_RX_CLK_I_3)
75906 #define F_RESET_SD_RX_CLK_I_3    V_RESET_SD_RX_CLK_I_3(1U)
75907 
75908 #define S_RESET_SD_RX_CLK_I_4    24
75909 #define V_RESET_SD_RX_CLK_I_4(x) ((x) << S_RESET_SD_RX_CLK_I_4)
75910 #define F_RESET_SD_RX_CLK_I_4    V_RESET_SD_RX_CLK_I_4(1U)
75911 
75912 #define S_RESET_SD_RX_CLK_I_5    23
75913 #define V_RESET_SD_RX_CLK_I_5(x) ((x) << S_RESET_SD_RX_CLK_I_5)
75914 #define F_RESET_SD_RX_CLK_I_5    V_RESET_SD_RX_CLK_I_5(1U)
75915 
75916 #define S_RESET_SD_RX_CLK_I_6    22
75917 #define V_RESET_SD_RX_CLK_I_6(x) ((x) << S_RESET_SD_RX_CLK_I_6)
75918 #define F_RESET_SD_RX_CLK_I_6    V_RESET_SD_RX_CLK_I_6(1U)
75919 
75920 #define S_RESET_SD_RX_CLK_I_7    21
75921 #define V_RESET_SD_RX_CLK_I_7(x) ((x) << S_RESET_SD_RX_CLK_I_7)
75922 #define F_RESET_SD_RX_CLK_I_7    V_RESET_SD_RX_CLK_I_7(1U)
75923 
75924 #define S_RESET_SD_TX_CLK_I_0    20
75925 #define V_RESET_SD_TX_CLK_I_0(x) ((x) << S_RESET_SD_TX_CLK_I_0)
75926 #define F_RESET_SD_TX_CLK_I_0    V_RESET_SD_TX_CLK_I_0(1U)
75927 
75928 #define S_RESET_SD_TX_CLK_I_1    19
75929 #define V_RESET_SD_TX_CLK_I_1(x) ((x) << S_RESET_SD_TX_CLK_I_1)
75930 #define F_RESET_SD_TX_CLK_I_1    V_RESET_SD_TX_CLK_I_1(1U)
75931 
75932 #define S_RESET_SD_TX_CLK_I_2    18
75933 #define V_RESET_SD_TX_CLK_I_2(x) ((x) << S_RESET_SD_TX_CLK_I_2)
75934 #define F_RESET_SD_TX_CLK_I_2    V_RESET_SD_TX_CLK_I_2(1U)
75935 
75936 #define S_RESET_SD_TX_CLK_I_3    17
75937 #define V_RESET_SD_TX_CLK_I_3(x) ((x) << S_RESET_SD_TX_CLK_I_3)
75938 #define F_RESET_SD_TX_CLK_I_3    V_RESET_SD_TX_CLK_I_3(1U)
75939 
75940 #define S_RESET_SD_TX_CLK_I_4    16
75941 #define V_RESET_SD_TX_CLK_I_4(x) ((x) << S_RESET_SD_TX_CLK_I_4)
75942 #define F_RESET_SD_TX_CLK_I_4    V_RESET_SD_TX_CLK_I_4(1U)
75943 
75944 #define S_RESET_SD_TX_CLK_I_5    15
75945 #define V_RESET_SD_TX_CLK_I_5(x) ((x) << S_RESET_SD_TX_CLK_I_5)
75946 #define F_RESET_SD_TX_CLK_I_5    V_RESET_SD_TX_CLK_I_5(1U)
75947 
75948 #define S_RESET_SD_TX_CLK_I_6    14
75949 #define V_RESET_SD_TX_CLK_I_6(x) ((x) << S_RESET_SD_TX_CLK_I_6)
75950 #define F_RESET_SD_TX_CLK_I_6    V_RESET_SD_TX_CLK_I_6(1U)
75951 
75952 #define S_RESET_SD_TX_CLK_I_7    13
75953 #define V_RESET_SD_TX_CLK_I_7(x) ((x) << S_RESET_SD_TX_CLK_I_7)
75954 #define F_RESET_SD_TX_CLK_I_7    V_RESET_SD_TX_CLK_I_7(1U)
75955 
75956 #define S_RESET_XPCS_REF_CLK_I_0    12
75957 #define V_RESET_XPCS_REF_CLK_I_0(x) ((x) << S_RESET_XPCS_REF_CLK_I_0)
75958 #define F_RESET_XPCS_REF_CLK_I_0    V_RESET_XPCS_REF_CLK_I_0(1U)
75959 
75960 #define S_RESET_XPCS_REF_CLK_I_1    11
75961 #define V_RESET_XPCS_REF_CLK_I_1(x) ((x) << S_RESET_XPCS_REF_CLK_I_1)
75962 #define F_RESET_XPCS_REF_CLK_I_1    V_RESET_XPCS_REF_CLK_I_1(1U)
75963 
75964 #define S_RESET_FF_RX_CLK_0_I    9
75965 #define V_RESET_FF_RX_CLK_0_I(x) ((x) << S_RESET_FF_RX_CLK_0_I)
75966 #define F_RESET_FF_RX_CLK_0_I    V_RESET_FF_RX_CLK_0_I(1U)
75967 
75968 #define S_RESET_FF_TX_CLK_0_I    8
75969 #define V_RESET_FF_TX_CLK_0_I(x) ((x) << S_RESET_FF_TX_CLK_0_I)
75970 #define F_RESET_FF_TX_CLK_0_I    V_RESET_FF_TX_CLK_0_I(1U)
75971 
75972 #define S_RESET_RXCLK_0_I    7
75973 #define V_RESET_RXCLK_0_I(x) ((x) << S_RESET_RXCLK_0_I)
75974 #define F_RESET_RXCLK_0_I    V_RESET_RXCLK_0_I(1U)
75975 
75976 #define S_RESET_TXCLK_0_I    6
75977 #define V_RESET_TXCLK_0_I(x) ((x) << S_RESET_TXCLK_0_I)
75978 #define F_RESET_TXCLK_0_I    V_RESET_TXCLK_0_I(1U)
75979 
75980 #define S_RESET_FF_RX_CLK_1_I    5
75981 #define V_RESET_FF_RX_CLK_1_I(x) ((x) << S_RESET_FF_RX_CLK_1_I)
75982 #define F_RESET_FF_RX_CLK_1_I    V_RESET_FF_RX_CLK_1_I(1U)
75983 
75984 #define S_RESET_FF_TX_CLK_1_I    4
75985 #define V_RESET_FF_TX_CLK_1_I(x) ((x) << S_RESET_FF_TX_CLK_1_I)
75986 #define F_RESET_FF_TX_CLK_1_I    V_RESET_FF_TX_CLK_1_I(1U)
75987 
75988 #define S_RESET_RXCLK_1_I    3
75989 #define V_RESET_RXCLK_1_I(x) ((x) << S_RESET_RXCLK_1_I)
75990 #define F_RESET_RXCLK_1_I    V_RESET_RXCLK_1_I(1U)
75991 
75992 #define S_RESET_TXCLK_1_I    2
75993 #define V_RESET_TXCLK_1_I(x) ((x) << S_RESET_TXCLK_1_I)
75994 #define F_RESET_TXCLK_1_I    V_RESET_TXCLK_1_I(1U)
75995 
75996 #define S_XGMII_CLK_RESET_0    0
75997 #define V_XGMII_CLK_RESET_0(x) ((x) << S_XGMII_CLK_RESET_0)
75998 #define F_XGMII_CLK_RESET_0    V_XGMII_CLK_RESET_0(1U)
75999 
76000 #define A_MAC_MTIP_RESET_CTRL_1 0x38008
76001 
76002 #define S_RESET_FF_RX_CLK_2_I    31
76003 #define V_RESET_FF_RX_CLK_2_I(x) ((x) << S_RESET_FF_RX_CLK_2_I)
76004 #define F_RESET_FF_RX_CLK_2_I    V_RESET_FF_RX_CLK_2_I(1U)
76005 
76006 #define S_RESET_FF_TX_CLK_2_I    30
76007 #define V_RESET_FF_TX_CLK_2_I(x) ((x) << S_RESET_FF_TX_CLK_2_I)
76008 #define F_RESET_FF_TX_CLK_2_I    V_RESET_FF_TX_CLK_2_I(1U)
76009 
76010 #define S_RESET_RXCLK_2_I    29
76011 #define V_RESET_RXCLK_2_I(x) ((x) << S_RESET_RXCLK_2_I)
76012 #define F_RESET_RXCLK_2_I    V_RESET_RXCLK_2_I(1U)
76013 
76014 #define S_RESET_TXCLK_2_I    28
76015 #define V_RESET_TXCLK_2_I(x) ((x) << S_RESET_TXCLK_2_I)
76016 #define F_RESET_TXCLK_2_I    V_RESET_TXCLK_2_I(1U)
76017 
76018 #define S_RESET_FF_RX_CLK_3_I    27
76019 #define V_RESET_FF_RX_CLK_3_I(x) ((x) << S_RESET_FF_RX_CLK_3_I)
76020 #define F_RESET_FF_RX_CLK_3_I    V_RESET_FF_RX_CLK_3_I(1U)
76021 
76022 #define S_RESET_FF_TX_CLK_3_I    26
76023 #define V_RESET_FF_TX_CLK_3_I(x) ((x) << S_RESET_FF_TX_CLK_3_I)
76024 #define F_RESET_FF_TX_CLK_3_I    V_RESET_FF_TX_CLK_3_I(1U)
76025 
76026 #define S_RESET_RXCLK_3_I    25
76027 #define V_RESET_RXCLK_3_I(x) ((x) << S_RESET_RXCLK_3_I)
76028 #define F_RESET_RXCLK_3_I    V_RESET_RXCLK_3_I(1U)
76029 
76030 #define S_RESET_TXCLK_3_I    24
76031 #define V_RESET_TXCLK_3_I(x) ((x) << S_RESET_TXCLK_3_I)
76032 #define F_RESET_TXCLK_3_I    V_RESET_TXCLK_3_I(1U)
76033 
76034 #define S_RESET_FF_RX_CLK_4_I    23
76035 #define V_RESET_FF_RX_CLK_4_I(x) ((x) << S_RESET_FF_RX_CLK_4_I)
76036 #define F_RESET_FF_RX_CLK_4_I    V_RESET_FF_RX_CLK_4_I(1U)
76037 
76038 #define S_RESET_FF_TX_CLK_4_I    22
76039 #define V_RESET_FF_TX_CLK_4_I(x) ((x) << S_RESET_FF_TX_CLK_4_I)
76040 #define F_RESET_FF_TX_CLK_4_I    V_RESET_FF_TX_CLK_4_I(1U)
76041 
76042 #define S_RESET_RXCLK_4_I    21
76043 #define V_RESET_RXCLK_4_I(x) ((x) << S_RESET_RXCLK_4_I)
76044 #define F_RESET_RXCLK_4_I    V_RESET_RXCLK_4_I(1U)
76045 
76046 #define S_RESET_TXCLK_4_I    20
76047 #define V_RESET_TXCLK_4_I(x) ((x) << S_RESET_TXCLK_4_I)
76048 #define F_RESET_TXCLK_4_I    V_RESET_TXCLK_4_I(1U)
76049 
76050 #define S_RESET_FF_RX_CLK_5_I    19
76051 #define V_RESET_FF_RX_CLK_5_I(x) ((x) << S_RESET_FF_RX_CLK_5_I)
76052 #define F_RESET_FF_RX_CLK_5_I    V_RESET_FF_RX_CLK_5_I(1U)
76053 
76054 #define S_RESET_FF_TX_CLK_5_I    18
76055 #define V_RESET_FF_TX_CLK_5_I(x) ((x) << S_RESET_FF_TX_CLK_5_I)
76056 #define F_RESET_FF_TX_CLK_5_I    V_RESET_FF_TX_CLK_5_I(1U)
76057 
76058 #define S_RESET_RXCLK_5_I    17
76059 #define V_RESET_RXCLK_5_I(x) ((x) << S_RESET_RXCLK_5_I)
76060 #define F_RESET_RXCLK_5_I    V_RESET_RXCLK_5_I(1U)
76061 
76062 #define S_RESET_TXCLK_5_I    16
76063 #define V_RESET_TXCLK_5_I(x) ((x) << S_RESET_TXCLK_5_I)
76064 #define F_RESET_TXCLK_5_I    V_RESET_TXCLK_5_I(1U)
76065 
76066 #define S_RESET_SD_RX_CLK_AN_0_I    15
76067 #define V_RESET_SD_RX_CLK_AN_0_I(x) ((x) << S_RESET_SD_RX_CLK_AN_0_I)
76068 #define F_RESET_SD_RX_CLK_AN_0_I    V_RESET_SD_RX_CLK_AN_0_I(1U)
76069 
76070 #define S_RESET_SD_TX_CLK_AN_0_I    14
76071 #define V_RESET_SD_TX_CLK_AN_0_I(x) ((x) << S_RESET_SD_TX_CLK_AN_0_I)
76072 #define F_RESET_SD_TX_CLK_AN_0_I    V_RESET_SD_TX_CLK_AN_0_I(1U)
76073 
76074 #define S_RESET_SD_RX_CLK_AN_1_I    13
76075 #define V_RESET_SD_RX_CLK_AN_1_I(x) ((x) << S_RESET_SD_RX_CLK_AN_1_I)
76076 #define F_RESET_SD_RX_CLK_AN_1_I    V_RESET_SD_RX_CLK_AN_1_I(1U)
76077 
76078 #define S_RESET_SD_TX_CLK_AN_1_I    12
76079 #define V_RESET_SD_TX_CLK_AN_1_I(x) ((x) << S_RESET_SD_TX_CLK_AN_1_I)
76080 #define F_RESET_SD_TX_CLK_AN_1_I    V_RESET_SD_TX_CLK_AN_1_I(1U)
76081 
76082 #define S_RESET_SD_RX_CLK_AN_2_I    11
76083 #define V_RESET_SD_RX_CLK_AN_2_I(x) ((x) << S_RESET_SD_RX_CLK_AN_2_I)
76084 #define F_RESET_SD_RX_CLK_AN_2_I    V_RESET_SD_RX_CLK_AN_2_I(1U)
76085 
76086 #define S_RESET_SD_TX_CLK_AN_2_I    10
76087 #define V_RESET_SD_TX_CLK_AN_2_I(x) ((x) << S_RESET_SD_TX_CLK_AN_2_I)
76088 #define F_RESET_SD_TX_CLK_AN_2_I    V_RESET_SD_TX_CLK_AN_2_I(1U)
76089 
76090 #define S_RESET_SD_RX_CLK_AN_3_I    9
76091 #define V_RESET_SD_RX_CLK_AN_3_I(x) ((x) << S_RESET_SD_RX_CLK_AN_3_I)
76092 #define F_RESET_SD_RX_CLK_AN_3_I    V_RESET_SD_RX_CLK_AN_3_I(1U)
76093 
76094 #define S_RESET_SD_TX_CLK_AN_3_I    8
76095 #define V_RESET_SD_TX_CLK_AN_3_I(x) ((x) << S_RESET_SD_TX_CLK_AN_3_I)
76096 #define F_RESET_SD_TX_CLK_AN_3_I    V_RESET_SD_TX_CLK_AN_3_I(1U)
76097 
76098 #define S_RESET_SD_RX_CLK_AN_4_I    7
76099 #define V_RESET_SD_RX_CLK_AN_4_I(x) ((x) << S_RESET_SD_RX_CLK_AN_4_I)
76100 #define F_RESET_SD_RX_CLK_AN_4_I    V_RESET_SD_RX_CLK_AN_4_I(1U)
76101 
76102 #define S_RESET_SD_TX_CLK_AN_4_I    6
76103 #define V_RESET_SD_TX_CLK_AN_4_I(x) ((x) << S_RESET_SD_TX_CLK_AN_4_I)
76104 #define F_RESET_SD_TX_CLK_AN_4_I    V_RESET_SD_TX_CLK_AN_4_I(1U)
76105 
76106 #define S_RESET_SD_RX_CLK_AN_5_I    5
76107 #define V_RESET_SD_RX_CLK_AN_5_I(x) ((x) << S_RESET_SD_RX_CLK_AN_5_I)
76108 #define F_RESET_SD_RX_CLK_AN_5_I    V_RESET_SD_RX_CLK_AN_5_I(1U)
76109 
76110 #define S_RESET_SD_TX_CLK_AN_5_I    4
76111 #define V_RESET_SD_TX_CLK_AN_5_I(x) ((x) << S_RESET_SD_TX_CLK_AN_5_I)
76112 #define F_RESET_SD_TX_CLK_AN_5_I    V_RESET_SD_TX_CLK_AN_5_I(1U)
76113 
76114 #define S_RESET_SD_RX_CLK_AN_6_I    3
76115 #define V_RESET_SD_RX_CLK_AN_6_I(x) ((x) << S_RESET_SD_RX_CLK_AN_6_I)
76116 #define F_RESET_SD_RX_CLK_AN_6_I    V_RESET_SD_RX_CLK_AN_6_I(1U)
76117 
76118 #define S_RESET_SD_TX_CLK_AN_6_I    2
76119 #define V_RESET_SD_TX_CLK_AN_6_I(x) ((x) << S_RESET_SD_TX_CLK_AN_6_I)
76120 #define F_RESET_SD_TX_CLK_AN_6_I    V_RESET_SD_TX_CLK_AN_6_I(1U)
76121 
76122 #define S_RESET_SD_RX_CLK_AN_7_I    1
76123 #define V_RESET_SD_RX_CLK_AN_7_I(x) ((x) << S_RESET_SD_RX_CLK_AN_7_I)
76124 #define F_RESET_SD_RX_CLK_AN_7_I    V_RESET_SD_RX_CLK_AN_7_I(1U)
76125 
76126 #define S_RESET_SD_TX_CLK_AN_7_I    0
76127 #define V_RESET_SD_TX_CLK_AN_7_I(x) ((x) << S_RESET_SD_TX_CLK_AN_7_I)
76128 #define F_RESET_SD_TX_CLK_AN_7_I    V_RESET_SD_TX_CLK_AN_7_I(1U)
76129 
76130 #define A_MAC_MTIP_RESET_CTRL_2 0x3800c
76131 
76132 #define S_RESET_SGMII_TXCLK_I_3    31
76133 #define V_RESET_SGMII_TXCLK_I_3(x) ((x) << S_RESET_SGMII_TXCLK_I_3)
76134 #define F_RESET_SGMII_TXCLK_I_3    V_RESET_SGMII_TXCLK_I_3(1U)
76135 
76136 #define S_RESET_SGMII_RXCLK_I_3    30
76137 #define V_RESET_SGMII_RXCLK_I_3(x) ((x) << S_RESET_SGMII_RXCLK_I_3)
76138 #define F_RESET_SGMII_RXCLK_I_3    V_RESET_SGMII_RXCLK_I_3(1U)
76139 
76140 #define S_RESET_SGMII_TXCLK_I_2    29
76141 #define V_RESET_SGMII_TXCLK_I_2(x) ((x) << S_RESET_SGMII_TXCLK_I_2)
76142 #define F_RESET_SGMII_TXCLK_I_2    V_RESET_SGMII_TXCLK_I_2(1U)
76143 
76144 #define S_RESET_SGMII_RXCLK_I_2    28
76145 #define V_RESET_SGMII_RXCLK_I_2(x) ((x) << S_RESET_SGMII_RXCLK_I_2)
76146 #define F_RESET_SGMII_RXCLK_I_2    V_RESET_SGMII_RXCLK_I_2(1U)
76147 
76148 #define S_RESET_SGMII_TXCLK_I_1    27
76149 #define V_RESET_SGMII_TXCLK_I_1(x) ((x) << S_RESET_SGMII_TXCLK_I_1)
76150 #define F_RESET_SGMII_TXCLK_I_1    V_RESET_SGMII_TXCLK_I_1(1U)
76151 
76152 #define S_RESET_SGMII_RXCLK_I_1    26
76153 #define V_RESET_SGMII_RXCLK_I_1(x) ((x) << S_RESET_SGMII_RXCLK_I_1)
76154 #define F_RESET_SGMII_RXCLK_I_1    V_RESET_SGMII_RXCLK_I_1(1U)
76155 
76156 #define S_RESET_SGMII_TXCLK_I_0    25
76157 #define V_RESET_SGMII_TXCLK_I_0(x) ((x) << S_RESET_SGMII_TXCLK_I_0)
76158 #define F_RESET_SGMII_TXCLK_I_0    V_RESET_SGMII_TXCLK_I_0(1U)
76159 
76160 #define S_RESET_SGMII_RXCLK_I_0    24
76161 #define V_RESET_SGMII_RXCLK_I_0(x) ((x) << S_RESET_SGMII_RXCLK_I_0)
76162 #define F_RESET_SGMII_RXCLK_I_0    V_RESET_SGMII_RXCLK_I_0(1U)
76163 
76164 #define S_MTIPSD7TXRST    23
76165 #define V_MTIPSD7TXRST(x) ((x) << S_MTIPSD7TXRST)
76166 #define F_MTIPSD7TXRST    V_MTIPSD7TXRST(1U)
76167 
76168 #define S_MTIPSD6TXRST    22
76169 #define V_MTIPSD6TXRST(x) ((x) << S_MTIPSD6TXRST)
76170 #define F_MTIPSD6TXRST    V_MTIPSD6TXRST(1U)
76171 
76172 #define S_MTIPSD5TXRST    21
76173 #define V_MTIPSD5TXRST(x) ((x) << S_MTIPSD5TXRST)
76174 #define F_MTIPSD5TXRST    V_MTIPSD5TXRST(1U)
76175 
76176 #define S_MTIPSD4TXRST    20
76177 #define V_MTIPSD4TXRST(x) ((x) << S_MTIPSD4TXRST)
76178 #define F_MTIPSD4TXRST    V_MTIPSD4TXRST(1U)
76179 
76180 #define S_T7_MTIPSD3TXRST    19
76181 #define V_T7_MTIPSD3TXRST(x) ((x) << S_T7_MTIPSD3TXRST)
76182 #define F_T7_MTIPSD3TXRST    V_T7_MTIPSD3TXRST(1U)
76183 
76184 #define S_T7_MTIPSD2TXRST    18
76185 #define V_T7_MTIPSD2TXRST(x) ((x) << S_T7_MTIPSD2TXRST)
76186 #define F_T7_MTIPSD2TXRST    V_T7_MTIPSD2TXRST(1U)
76187 
76188 #define S_T7_MTIPSD1TXRST    17
76189 #define V_T7_MTIPSD1TXRST(x) ((x) << S_T7_MTIPSD1TXRST)
76190 #define F_T7_MTIPSD1TXRST    V_T7_MTIPSD1TXRST(1U)
76191 
76192 #define S_T7_MTIPSD0TXRST    16
76193 #define V_T7_MTIPSD0TXRST(x) ((x) << S_T7_MTIPSD0TXRST)
76194 #define F_T7_MTIPSD0TXRST    V_T7_MTIPSD0TXRST(1U)
76195 
76196 #define S_MTIPSD7RXRST    15
76197 #define V_MTIPSD7RXRST(x) ((x) << S_MTIPSD7RXRST)
76198 #define F_MTIPSD7RXRST    V_MTIPSD7RXRST(1U)
76199 
76200 #define S_MTIPSD6RXRST    14
76201 #define V_MTIPSD6RXRST(x) ((x) << S_MTIPSD6RXRST)
76202 #define F_MTIPSD6RXRST    V_MTIPSD6RXRST(1U)
76203 
76204 #define S_MTIPSD5RXRST    13
76205 #define V_MTIPSD5RXRST(x) ((x) << S_MTIPSD5RXRST)
76206 #define F_MTIPSD5RXRST    V_MTIPSD5RXRST(1U)
76207 
76208 #define S_MTIPSD4RXRST    12
76209 #define V_MTIPSD4RXRST(x) ((x) << S_MTIPSD4RXRST)
76210 #define F_MTIPSD4RXRST    V_MTIPSD4RXRST(1U)
76211 
76212 #define S_T7_MTIPSD3RXRST    11
76213 #define V_T7_MTIPSD3RXRST(x) ((x) << S_T7_MTIPSD3RXRST)
76214 #define F_T7_MTIPSD3RXRST    V_T7_MTIPSD3RXRST(1U)
76215 
76216 #define S_T7_MTIPSD2RXRST    10
76217 #define V_T7_MTIPSD2RXRST(x) ((x) << S_T7_MTIPSD2RXRST)
76218 #define F_T7_MTIPSD2RXRST    V_T7_MTIPSD2RXRST(1U)
76219 
76220 #define S_T7_MTIPSD1RXRST    9
76221 #define V_T7_MTIPSD1RXRST(x) ((x) << S_T7_MTIPSD1RXRST)
76222 #define F_T7_MTIPSD1RXRST    V_T7_MTIPSD1RXRST(1U)
76223 
76224 #define S_T7_MTIPSD0RXRST    8
76225 #define V_T7_MTIPSD0RXRST(x) ((x) << S_T7_MTIPSD0RXRST)
76226 #define F_T7_MTIPSD0RXRST    V_T7_MTIPSD0RXRST(1U)
76227 
76228 #define S_RESET_REG_CLK_AN_0_I    7
76229 #define V_RESET_REG_CLK_AN_0_I(x) ((x) << S_RESET_REG_CLK_AN_0_I)
76230 #define F_RESET_REG_CLK_AN_0_I    V_RESET_REG_CLK_AN_0_I(1U)
76231 
76232 #define S_RESET_REG_CLK_AN_1_I    6
76233 #define V_RESET_REG_CLK_AN_1_I(x) ((x) << S_RESET_REG_CLK_AN_1_I)
76234 #define F_RESET_REG_CLK_AN_1_I    V_RESET_REG_CLK_AN_1_I(1U)
76235 
76236 #define S_RESET_REG_CLK_AN_2_I    5
76237 #define V_RESET_REG_CLK_AN_2_I(x) ((x) << S_RESET_REG_CLK_AN_2_I)
76238 #define F_RESET_REG_CLK_AN_2_I    V_RESET_REG_CLK_AN_2_I(1U)
76239 
76240 #define S_RESET_REG_CLK_AN_3_I    4
76241 #define V_RESET_REG_CLK_AN_3_I(x) ((x) << S_RESET_REG_CLK_AN_3_I)
76242 #define F_RESET_REG_CLK_AN_3_I    V_RESET_REG_CLK_AN_3_I(1U)
76243 
76244 #define S_RESET_REG_CLK_AN_4_I    3
76245 #define V_RESET_REG_CLK_AN_4_I(x) ((x) << S_RESET_REG_CLK_AN_4_I)
76246 #define F_RESET_REG_CLK_AN_4_I    V_RESET_REG_CLK_AN_4_I(1U)
76247 
76248 #define S_RESET_REG_CLK_AN_5_I    2
76249 #define V_RESET_REG_CLK_AN_5_I(x) ((x) << S_RESET_REG_CLK_AN_5_I)
76250 #define F_RESET_REG_CLK_AN_5_I    V_RESET_REG_CLK_AN_5_I(1U)
76251 
76252 #define S_RESET_REG_CLK_AN_6_I    1
76253 #define V_RESET_REG_CLK_AN_6_I(x) ((x) << S_RESET_REG_CLK_AN_6_I)
76254 #define F_RESET_REG_CLK_AN_6_I    V_RESET_REG_CLK_AN_6_I(1U)
76255 
76256 #define S_RESET_REG_CLK_AN_7_I    0
76257 #define V_RESET_REG_CLK_AN_7_I(x) ((x) << S_RESET_REG_CLK_AN_7_I)
76258 #define F_RESET_REG_CLK_AN_7_I    V_RESET_REG_CLK_AN_7_I(1U)
76259 
76260 #define A_MAC_MTIP_CLK_CTRL_0 0x38010
76261 
76262 #define S_F91_REF_CLK_I_G    31
76263 #define V_F91_REF_CLK_I_G(x) ((x) << S_F91_REF_CLK_I_G)
76264 #define F_F91_REF_CLK_I_G    V_F91_REF_CLK_I_G(1U)
76265 
76266 #define S_PCS000_REF_CLK_I_G    30
76267 #define V_PCS000_REF_CLK_I_G(x) ((x) << S_PCS000_REF_CLK_I_G)
76268 #define F_PCS000_REF_CLK_I_G    V_PCS000_REF_CLK_I_G(1U)
76269 
76270 #define S_REF_CLK_I_G    29
76271 #define V_REF_CLK_I_G(x) ((x) << S_REF_CLK_I_G)
76272 #define F_REF_CLK_I_G    V_REF_CLK_I_G(1U)
76273 
76274 #define S_SD_RX_CLK_I_0_G    28
76275 #define V_SD_RX_CLK_I_0_G(x) ((x) << S_SD_RX_CLK_I_0_G)
76276 #define F_SD_RX_CLK_I_0_G    V_SD_RX_CLK_I_0_G(1U)
76277 
76278 #define S_SD_RX_CLK_I_1_G    27
76279 #define V_SD_RX_CLK_I_1_G(x) ((x) << S_SD_RX_CLK_I_1_G)
76280 #define F_SD_RX_CLK_I_1_G    V_SD_RX_CLK_I_1_G(1U)
76281 
76282 #define S_SD_RX_CLK_I_2_G    26
76283 #define V_SD_RX_CLK_I_2_G(x) ((x) << S_SD_RX_CLK_I_2_G)
76284 #define F_SD_RX_CLK_I_2_G    V_SD_RX_CLK_I_2_G(1U)
76285 
76286 #define S_SD_RX_CLK_I_3_G    25
76287 #define V_SD_RX_CLK_I_3_G(x) ((x) << S_SD_RX_CLK_I_3_G)
76288 #define F_SD_RX_CLK_I_3_G    V_SD_RX_CLK_I_3_G(1U)
76289 
76290 #define S_SD_RX_CLK_I_4_G    24
76291 #define V_SD_RX_CLK_I_4_G(x) ((x) << S_SD_RX_CLK_I_4_G)
76292 #define F_SD_RX_CLK_I_4_G    V_SD_RX_CLK_I_4_G(1U)
76293 
76294 #define S_SD_RX_CLK_I_5_G    23
76295 #define V_SD_RX_CLK_I_5_G(x) ((x) << S_SD_RX_CLK_I_5_G)
76296 #define F_SD_RX_CLK_I_5_G    V_SD_RX_CLK_I_5_G(1U)
76297 
76298 #define S_SD_RX_CLK_I_6_G    22
76299 #define V_SD_RX_CLK_I_6_G(x) ((x) << S_SD_RX_CLK_I_6_G)
76300 #define F_SD_RX_CLK_I_6_G    V_SD_RX_CLK_I_6_G(1U)
76301 
76302 #define S_SD_RX_CLK_I_7_G    21
76303 #define V_SD_RX_CLK_I_7_G(x) ((x) << S_SD_RX_CLK_I_7_G)
76304 #define F_SD_RX_CLK_I_7_G    V_SD_RX_CLK_I_7_G(1U)
76305 
76306 #define S_SD_TX_CLK_I_0_G    20
76307 #define V_SD_TX_CLK_I_0_G(x) ((x) << S_SD_TX_CLK_I_0_G)
76308 #define F_SD_TX_CLK_I_0_G    V_SD_TX_CLK_I_0_G(1U)
76309 
76310 #define S_SD_TX_CLK_I_1_G    19
76311 #define V_SD_TX_CLK_I_1_G(x) ((x) << S_SD_TX_CLK_I_1_G)
76312 #define F_SD_TX_CLK_I_1_G    V_SD_TX_CLK_I_1_G(1U)
76313 
76314 #define S_SD_TX_CLK_I_2_G    18
76315 #define V_SD_TX_CLK_I_2_G(x) ((x) << S_SD_TX_CLK_I_2_G)
76316 #define F_SD_TX_CLK_I_2_G    V_SD_TX_CLK_I_2_G(1U)
76317 
76318 #define S_SD_TX_CLK_I_3_G    17
76319 #define V_SD_TX_CLK_I_3_G(x) ((x) << S_SD_TX_CLK_I_3_G)
76320 #define F_SD_TX_CLK_I_3_G    V_SD_TX_CLK_I_3_G(1U)
76321 
76322 #define S_SD_TX_CLK_I_4_G    16
76323 #define V_SD_TX_CLK_I_4_G(x) ((x) << S_SD_TX_CLK_I_4_G)
76324 #define F_SD_TX_CLK_I_4_G    V_SD_TX_CLK_I_4_G(1U)
76325 
76326 #define S_SD_TX_CLK_I_5_G    15
76327 #define V_SD_TX_CLK_I_5_G(x) ((x) << S_SD_TX_CLK_I_5_G)
76328 #define F_SD_TX_CLK_I_5_G    V_SD_TX_CLK_I_5_G(1U)
76329 
76330 #define S_SD_TX_CLK_I_6_G    14
76331 #define V_SD_TX_CLK_I_6_G(x) ((x) << S_SD_TX_CLK_I_6_G)
76332 #define F_SD_TX_CLK_I_6_G    V_SD_TX_CLK_I_6_G(1U)
76333 
76334 #define S_SD_TX_CLK_I_7_G    13
76335 #define V_SD_TX_CLK_I_7_G(x) ((x) << S_SD_TX_CLK_I_7_G)
76336 #define F_SD_TX_CLK_I_7_G    V_SD_TX_CLK_I_7_G(1U)
76337 
76338 #define S_XPCS_REF_CLK_I_0_G    12
76339 #define V_XPCS_REF_CLK_I_0_G(x) ((x) << S_XPCS_REF_CLK_I_0_G)
76340 #define F_XPCS_REF_CLK_I_0_G    V_XPCS_REF_CLK_I_0_G(1U)
76341 
76342 #define S_XPCS_REF_CLK_I_1_G    11
76343 #define V_XPCS_REF_CLK_I_1_G(x) ((x) << S_XPCS_REF_CLK_I_1_G)
76344 #define F_XPCS_REF_CLK_I_1_G    V_XPCS_REF_CLK_I_1_G(1U)
76345 
76346 #define S_REG_CLK_I_G    10
76347 #define V_REG_CLK_I_G(x) ((x) << S_REG_CLK_I_G)
76348 #define F_REG_CLK_I_G    V_REG_CLK_I_G(1U)
76349 
76350 #define S_FF_RX_CLK_0_I_G    9
76351 #define V_FF_RX_CLK_0_I_G(x) ((x) << S_FF_RX_CLK_0_I_G)
76352 #define F_FF_RX_CLK_0_I_G    V_FF_RX_CLK_0_I_G(1U)
76353 
76354 #define S_FF_TX_CLK_0_I_G    8
76355 #define V_FF_TX_CLK_0_I_G(x) ((x) << S_FF_TX_CLK_0_I_G)
76356 #define F_FF_TX_CLK_0_I_G    V_FF_TX_CLK_0_I_G(1U)
76357 
76358 #define S_RXCLK_0_I_G    7
76359 #define V_RXCLK_0_I_G(x) ((x) << S_RXCLK_0_I_G)
76360 #define F_RXCLK_0_I_G    V_RXCLK_0_I_G(1U)
76361 
76362 #define S_TXCLK_0_I_G    6
76363 #define V_TXCLK_0_I_G(x) ((x) << S_TXCLK_0_I_G)
76364 #define F_TXCLK_0_I_G    V_TXCLK_0_I_G(1U)
76365 
76366 #define S_FF_RX_CLK_1_I_G    5
76367 #define V_FF_RX_CLK_1_I_G(x) ((x) << S_FF_RX_CLK_1_I_G)
76368 #define F_FF_RX_CLK_1_I_G    V_FF_RX_CLK_1_I_G(1U)
76369 
76370 #define S_FF_TX_CLK_1_I_G    4
76371 #define V_FF_TX_CLK_1_I_G(x) ((x) << S_FF_TX_CLK_1_I_G)
76372 #define F_FF_TX_CLK_1_I_G    V_FF_TX_CLK_1_I_G(1U)
76373 
76374 #define S_RXCLK_1_I_G    3
76375 #define V_RXCLK_1_I_G(x) ((x) << S_RXCLK_1_I_G)
76376 #define F_RXCLK_1_I_G    V_RXCLK_1_I_G(1U)
76377 
76378 #define S_TXCLK_1_I_G    2
76379 #define V_TXCLK_1_I_G(x) ((x) << S_TXCLK_1_I_G)
76380 #define F_TXCLK_1_I_G    V_TXCLK_1_I_G(1U)
76381 
76382 #define A_MAC_MTIP_CLK_CTRL_1 0x38014
76383 
76384 #define S_FF_RX_CLK_2_I_G    31
76385 #define V_FF_RX_CLK_2_I_G(x) ((x) << S_FF_RX_CLK_2_I_G)
76386 #define F_FF_RX_CLK_2_I_G    V_FF_RX_CLK_2_I_G(1U)
76387 
76388 #define S_FF_TX_CLK_2_I_G    30
76389 #define V_FF_TX_CLK_2_I_G(x) ((x) << S_FF_TX_CLK_2_I_G)
76390 #define F_FF_TX_CLK_2_I_G    V_FF_TX_CLK_2_I_G(1U)
76391 
76392 #define S_RXCLK_2_I_G    29
76393 #define V_RXCLK_2_I_G(x) ((x) << S_RXCLK_2_I_G)
76394 #define F_RXCLK_2_I_G    V_RXCLK_2_I_G(1U)
76395 
76396 #define S_TXCLK_2_I_G    28
76397 #define V_TXCLK_2_I_G(x) ((x) << S_TXCLK_2_I_G)
76398 #define F_TXCLK_2_I_G    V_TXCLK_2_I_G(1U)
76399 
76400 #define S_FF_RX_CLK_3_I_G    27
76401 #define V_FF_RX_CLK_3_I_G(x) ((x) << S_FF_RX_CLK_3_I_G)
76402 #define F_FF_RX_CLK_3_I_G    V_FF_RX_CLK_3_I_G(1U)
76403 
76404 #define S_FF_TX_CLK_3_I_G    26
76405 #define V_FF_TX_CLK_3_I_G(x) ((x) << S_FF_TX_CLK_3_I_G)
76406 #define F_FF_TX_CLK_3_I_G    V_FF_TX_CLK_3_I_G(1U)
76407 
76408 #define S_RXCLK_3_I_G    25
76409 #define V_RXCLK_3_I_G(x) ((x) << S_RXCLK_3_I_G)
76410 #define F_RXCLK_3_I_G    V_RXCLK_3_I_G(1U)
76411 
76412 #define S_TXCLK_3_I_G    24
76413 #define V_TXCLK_3_I_G(x) ((x) << S_TXCLK_3_I_G)
76414 #define F_TXCLK_3_I_G    V_TXCLK_3_I_G(1U)
76415 
76416 #define S_FF_RX_CLK_4_I_G    23
76417 #define V_FF_RX_CLK_4_I_G(x) ((x) << S_FF_RX_CLK_4_I_G)
76418 #define F_FF_RX_CLK_4_I_G    V_FF_RX_CLK_4_I_G(1U)
76419 
76420 #define S_FF_TX_CLK_4_I_G    22
76421 #define V_FF_TX_CLK_4_I_G(x) ((x) << S_FF_TX_CLK_4_I_G)
76422 #define F_FF_TX_CLK_4_I_G    V_FF_TX_CLK_4_I_G(1U)
76423 
76424 #define S_RXCLK_4_I_G    21
76425 #define V_RXCLK_4_I_G(x) ((x) << S_RXCLK_4_I_G)
76426 #define F_RXCLK_4_I_G    V_RXCLK_4_I_G(1U)
76427 
76428 #define S_TXCLK_4_I_G    20
76429 #define V_TXCLK_4_I_G(x) ((x) << S_TXCLK_4_I_G)
76430 #define F_TXCLK_4_I_G    V_TXCLK_4_I_G(1U)
76431 
76432 #define S_FF_RX_CLK_5_I_G    19
76433 #define V_FF_RX_CLK_5_I_G(x) ((x) << S_FF_RX_CLK_5_I_G)
76434 #define F_FF_RX_CLK_5_I_G    V_FF_RX_CLK_5_I_G(1U)
76435 
76436 #define S_FF_TX_CLK_5_I_G    18
76437 #define V_FF_TX_CLK_5_I_G(x) ((x) << S_FF_TX_CLK_5_I_G)
76438 #define F_FF_TX_CLK_5_I_G    V_FF_TX_CLK_5_I_G(1U)
76439 
76440 #define S_RXCLK_5_I_G    17
76441 #define V_RXCLK_5_I_G(x) ((x) << S_RXCLK_5_I_G)
76442 #define F_RXCLK_5_I_G    V_RXCLK_5_I_G(1U)
76443 
76444 #define S_TXCLK_5_I_G    16
76445 #define V_TXCLK_5_I_G(x) ((x) << S_TXCLK_5_I_G)
76446 #define F_TXCLK_5_I_G    V_TXCLK_5_I_G(1U)
76447 
76448 #define S_SD_RX_CLK_AN_0_I_G    15
76449 #define V_SD_RX_CLK_AN_0_I_G(x) ((x) << S_SD_RX_CLK_AN_0_I_G)
76450 #define F_SD_RX_CLK_AN_0_I_G    V_SD_RX_CLK_AN_0_I_G(1U)
76451 
76452 #define S_SD_TX_CLK_AN_0_I_G    14
76453 #define V_SD_TX_CLK_AN_0_I_G(x) ((x) << S_SD_TX_CLK_AN_0_I_G)
76454 #define F_SD_TX_CLK_AN_0_I_G    V_SD_TX_CLK_AN_0_I_G(1U)
76455 
76456 #define S_SD_RX_CLK_AN_1_I_G    13
76457 #define V_SD_RX_CLK_AN_1_I_G(x) ((x) << S_SD_RX_CLK_AN_1_I_G)
76458 #define F_SD_RX_CLK_AN_1_I_G    V_SD_RX_CLK_AN_1_I_G(1U)
76459 
76460 #define S_SD_TX_CLK_AN_1_I_G    12
76461 #define V_SD_TX_CLK_AN_1_I_G(x) ((x) << S_SD_TX_CLK_AN_1_I_G)
76462 #define F_SD_TX_CLK_AN_1_I_G    V_SD_TX_CLK_AN_1_I_G(1U)
76463 
76464 #define S_SD_RX_CLK_AN_2_I_G    11
76465 #define V_SD_RX_CLK_AN_2_I_G(x) ((x) << S_SD_RX_CLK_AN_2_I_G)
76466 #define F_SD_RX_CLK_AN_2_I_G    V_SD_RX_CLK_AN_2_I_G(1U)
76467 
76468 #define S_SD_TX_CLK_AN_2_I_G    10
76469 #define V_SD_TX_CLK_AN_2_I_G(x) ((x) << S_SD_TX_CLK_AN_2_I_G)
76470 #define F_SD_TX_CLK_AN_2_I_G    V_SD_TX_CLK_AN_2_I_G(1U)
76471 
76472 #define S_SD_RX_CLK_AN_3_I_G    9
76473 #define V_SD_RX_CLK_AN_3_I_G(x) ((x) << S_SD_RX_CLK_AN_3_I_G)
76474 #define F_SD_RX_CLK_AN_3_I_G    V_SD_RX_CLK_AN_3_I_G(1U)
76475 
76476 #define S_SD_TX_CLK_AN_3_I_G    8
76477 #define V_SD_TX_CLK_AN_3_I_G(x) ((x) << S_SD_TX_CLK_AN_3_I_G)
76478 #define F_SD_TX_CLK_AN_3_I_G    V_SD_TX_CLK_AN_3_I_G(1U)
76479 
76480 #define S_SD_RX_CLK_AN_4_I_G    7
76481 #define V_SD_RX_CLK_AN_4_I_G(x) ((x) << S_SD_RX_CLK_AN_4_I_G)
76482 #define F_SD_RX_CLK_AN_4_I_G    V_SD_RX_CLK_AN_4_I_G(1U)
76483 
76484 #define S_SD_TX_CLK_AN_4_I_G    6
76485 #define V_SD_TX_CLK_AN_4_I_G(x) ((x) << S_SD_TX_CLK_AN_4_I_G)
76486 #define F_SD_TX_CLK_AN_4_I_G    V_SD_TX_CLK_AN_4_I_G(1U)
76487 
76488 #define S_SD_RX_CLK_AN_5_I_G    5
76489 #define V_SD_RX_CLK_AN_5_I_G(x) ((x) << S_SD_RX_CLK_AN_5_I_G)
76490 #define F_SD_RX_CLK_AN_5_I_G    V_SD_RX_CLK_AN_5_I_G(1U)
76491 
76492 #define S_SD_TX_CLK_AN_5_I_G    4
76493 #define V_SD_TX_CLK_AN_5_I_G(x) ((x) << S_SD_TX_CLK_AN_5_I_G)
76494 #define F_SD_TX_CLK_AN_5_I_G    V_SD_TX_CLK_AN_5_I_G(1U)
76495 
76496 #define S_SD_RX_CLK_AN_6_I_G    3
76497 #define V_SD_RX_CLK_AN_6_I_G(x) ((x) << S_SD_RX_CLK_AN_6_I_G)
76498 #define F_SD_RX_CLK_AN_6_I_G    V_SD_RX_CLK_AN_6_I_G(1U)
76499 
76500 #define S_SD_TX_CLK_AN_6_I_G    2
76501 #define V_SD_TX_CLK_AN_6_I_G(x) ((x) << S_SD_TX_CLK_AN_6_I_G)
76502 #define F_SD_TX_CLK_AN_6_I_G    V_SD_TX_CLK_AN_6_I_G(1U)
76503 
76504 #define S_SD_RX_CLK_AN_7_I_G    1
76505 #define V_SD_RX_CLK_AN_7_I_G(x) ((x) << S_SD_RX_CLK_AN_7_I_G)
76506 #define F_SD_RX_CLK_AN_7_I_G    V_SD_RX_CLK_AN_7_I_G(1U)
76507 
76508 #define S_SD_TX_CLK_AN_7_I_G    0
76509 #define V_SD_TX_CLK_AN_7_I_G(x) ((x) << S_SD_TX_CLK_AN_7_I_G)
76510 #define F_SD_TX_CLK_AN_7_I_G    V_SD_TX_CLK_AN_7_I_G(1U)
76511 
76512 #define A_MAC_MTIP_CLK_CTRL_2 0x38018
76513 
76514 #define S_SD_RX_CLK_0_G    31
76515 #define V_SD_RX_CLK_0_G(x) ((x) << S_SD_RX_CLK_0_G)
76516 #define F_SD_RX_CLK_0_G    V_SD_RX_CLK_0_G(1U)
76517 
76518 #define S_SD_RX_CLK_1_G    30
76519 #define V_SD_RX_CLK_1_G(x) ((x) << S_SD_RX_CLK_1_G)
76520 #define F_SD_RX_CLK_1_G    V_SD_RX_CLK_1_G(1U)
76521 
76522 #define S_SD_RX_CLK_2_G    29
76523 #define V_SD_RX_CLK_2_G(x) ((x) << S_SD_RX_CLK_2_G)
76524 #define F_SD_RX_CLK_2_G    V_SD_RX_CLK_2_G(1U)
76525 
76526 #define S_SD_RX_CLK_3_G    28
76527 #define V_SD_RX_CLK_3_G(x) ((x) << S_SD_RX_CLK_3_G)
76528 #define F_SD_RX_CLK_3_G    V_SD_RX_CLK_3_G(1U)
76529 
76530 #define S_SD_RX_CLK_4_G    27
76531 #define V_SD_RX_CLK_4_G(x) ((x) << S_SD_RX_CLK_4_G)
76532 #define F_SD_RX_CLK_4_G    V_SD_RX_CLK_4_G(1U)
76533 
76534 #define S_SD_RX_CLK_5_G    26
76535 #define V_SD_RX_CLK_5_G(x) ((x) << S_SD_RX_CLK_5_G)
76536 #define F_SD_RX_CLK_5_G    V_SD_RX_CLK_5_G(1U)
76537 
76538 #define S_SD_RX_CLK_6_G    25
76539 #define V_SD_RX_CLK_6_G(x) ((x) << S_SD_RX_CLK_6_G)
76540 #define F_SD_RX_CLK_6_G    V_SD_RX_CLK_6_G(1U)
76541 
76542 #define S_SD_RX_CLK_7_G    24
76543 #define V_SD_RX_CLK_7_G(x) ((x) << S_SD_RX_CLK_7_G)
76544 #define F_SD_RX_CLK_7_G    V_SD_RX_CLK_7_G(1U)
76545 
76546 #define S_SD_TX_CLK_0_G    23
76547 #define V_SD_TX_CLK_0_G(x) ((x) << S_SD_TX_CLK_0_G)
76548 #define F_SD_TX_CLK_0_G    V_SD_TX_CLK_0_G(1U)
76549 
76550 #define S_SD_TX_CLK_1_G    22
76551 #define V_SD_TX_CLK_1_G(x) ((x) << S_SD_TX_CLK_1_G)
76552 #define F_SD_TX_CLK_1_G    V_SD_TX_CLK_1_G(1U)
76553 
76554 #define S_SD_TX_CLK_2_G    21
76555 #define V_SD_TX_CLK_2_G(x) ((x) << S_SD_TX_CLK_2_G)
76556 #define F_SD_TX_CLK_2_G    V_SD_TX_CLK_2_G(1U)
76557 
76558 #define S_SD_TX_CLK_3_G    20
76559 #define V_SD_TX_CLK_3_G(x) ((x) << S_SD_TX_CLK_3_G)
76560 #define F_SD_TX_CLK_3_G    V_SD_TX_CLK_3_G(1U)
76561 
76562 #define S_SD_TX_CLK_4_G    19
76563 #define V_SD_TX_CLK_4_G(x) ((x) << S_SD_TX_CLK_4_G)
76564 #define F_SD_TX_CLK_4_G    V_SD_TX_CLK_4_G(1U)
76565 
76566 #define S_SD_TX_CLK_5_G    18
76567 #define V_SD_TX_CLK_5_G(x) ((x) << S_SD_TX_CLK_5_G)
76568 #define F_SD_TX_CLK_5_G    V_SD_TX_CLK_5_G(1U)
76569 
76570 #define S_SD_TX_CLK_6_G    17
76571 #define V_SD_TX_CLK_6_G(x) ((x) << S_SD_TX_CLK_6_G)
76572 #define F_SD_TX_CLK_6_G    V_SD_TX_CLK_6_G(1U)
76573 
76574 #define S_SD_TX_CLK_7_G    16
76575 #define V_SD_TX_CLK_7_G(x) ((x) << S_SD_TX_CLK_7_G)
76576 #define F_SD_TX_CLK_7_G    V_SD_TX_CLK_7_G(1U)
76577 
76578 #define S_SD_RX_CLK_AEC_0_G    15
76579 #define V_SD_RX_CLK_AEC_0_G(x) ((x) << S_SD_RX_CLK_AEC_0_G)
76580 #define F_SD_RX_CLK_AEC_0_G    V_SD_RX_CLK_AEC_0_G(1U)
76581 
76582 #define S_SD_RX_CLK_AEC_1_G    14
76583 #define V_SD_RX_CLK_AEC_1_G(x) ((x) << S_SD_RX_CLK_AEC_1_G)
76584 #define F_SD_RX_CLK_AEC_1_G    V_SD_RX_CLK_AEC_1_G(1U)
76585 
76586 #define S_SD_RX_CLK_AEC_2_G    13
76587 #define V_SD_RX_CLK_AEC_2_G(x) ((x) << S_SD_RX_CLK_AEC_2_G)
76588 #define F_SD_RX_CLK_AEC_2_G    V_SD_RX_CLK_AEC_2_G(1U)
76589 
76590 #define S_SD_RX_CLK_AEC_3_G    12
76591 #define V_SD_RX_CLK_AEC_3_G(x) ((x) << S_SD_RX_CLK_AEC_3_G)
76592 #define F_SD_RX_CLK_AEC_3_G    V_SD_RX_CLK_AEC_3_G(1U)
76593 
76594 #define S_SD_RX_CLK_AEC_4_G    11
76595 #define V_SD_RX_CLK_AEC_4_G(x) ((x) << S_SD_RX_CLK_AEC_4_G)
76596 #define F_SD_RX_CLK_AEC_4_G    V_SD_RX_CLK_AEC_4_G(1U)
76597 
76598 #define S_SD_RX_CLK_AEC_5_G    10
76599 #define V_SD_RX_CLK_AEC_5_G(x) ((x) << S_SD_RX_CLK_AEC_5_G)
76600 #define F_SD_RX_CLK_AEC_5_G    V_SD_RX_CLK_AEC_5_G(1U)
76601 
76602 #define S_SD_RX_CLK_AEC_6_G    9
76603 #define V_SD_RX_CLK_AEC_6_G(x) ((x) << S_SD_RX_CLK_AEC_6_G)
76604 #define F_SD_RX_CLK_AEC_6_G    V_SD_RX_CLK_AEC_6_G(1U)
76605 
76606 #define S_SD_RX_CLK_AEC_7_G    8
76607 #define V_SD_RX_CLK_AEC_7_G(x) ((x) << S_SD_RX_CLK_AEC_7_G)
76608 #define F_SD_RX_CLK_AEC_7_G    V_SD_RX_CLK_AEC_7_G(1U)
76609 
76610 #define S_SD_TX_CLK_AEC_0_G    7
76611 #define V_SD_TX_CLK_AEC_0_G(x) ((x) << S_SD_TX_CLK_AEC_0_G)
76612 #define F_SD_TX_CLK_AEC_0_G    V_SD_TX_CLK_AEC_0_G(1U)
76613 
76614 #define S_SD_TX_CLK_AEC_1_G    6
76615 #define V_SD_TX_CLK_AEC_1_G(x) ((x) << S_SD_TX_CLK_AEC_1_G)
76616 #define F_SD_TX_CLK_AEC_1_G    V_SD_TX_CLK_AEC_1_G(1U)
76617 
76618 #define S_SD_TX_CLK_AEC_2_G    5
76619 #define V_SD_TX_CLK_AEC_2_G(x) ((x) << S_SD_TX_CLK_AEC_2_G)
76620 #define F_SD_TX_CLK_AEC_2_G    V_SD_TX_CLK_AEC_2_G(1U)
76621 
76622 #define S_SD_TX_CLK_AEC_3_G    4
76623 #define V_SD_TX_CLK_AEC_3_G(x) ((x) << S_SD_TX_CLK_AEC_3_G)
76624 #define F_SD_TX_CLK_AEC_3_G    V_SD_TX_CLK_AEC_3_G(1U)
76625 
76626 #define S_SD_TX_CLK_AEC_4_G    3
76627 #define V_SD_TX_CLK_AEC_4_G(x) ((x) << S_SD_TX_CLK_AEC_4_G)
76628 #define F_SD_TX_CLK_AEC_4_G    V_SD_TX_CLK_AEC_4_G(1U)
76629 
76630 #define S_SD_TX_CLK_AEC_5_G    2
76631 #define V_SD_TX_CLK_AEC_5_G(x) ((x) << S_SD_TX_CLK_AEC_5_G)
76632 #define F_SD_TX_CLK_AEC_5_G    V_SD_TX_CLK_AEC_5_G(1U)
76633 
76634 #define S_SD_TX_CLK_AEC_6_G    1
76635 #define V_SD_TX_CLK_AEC_6_G(x) ((x) << S_SD_TX_CLK_AEC_6_G)
76636 #define F_SD_TX_CLK_AEC_6_G    V_SD_TX_CLK_AEC_6_G(1U)
76637 
76638 #define S_SD_TX_CLK_AEC_7_G    0
76639 #define V_SD_TX_CLK_AEC_7_G(x) ((x) << S_SD_TX_CLK_AEC_7_G)
76640 #define F_SD_TX_CLK_AEC_7_G    V_SD_TX_CLK_AEC_7_G(1U)
76641 
76642 #define A_MAC_MTIP_CLK_CTRL_3 0x3801c
76643 
76644 #define S_PCS_RX_CLK_0_G    31
76645 #define V_PCS_RX_CLK_0_G(x) ((x) << S_PCS_RX_CLK_0_G)
76646 #define F_PCS_RX_CLK_0_G    V_PCS_RX_CLK_0_G(1U)
76647 
76648 #define S_PCS_RX_CLK_1_G    30
76649 #define V_PCS_RX_CLK_1_G(x) ((x) << S_PCS_RX_CLK_1_G)
76650 #define F_PCS_RX_CLK_1_G    V_PCS_RX_CLK_1_G(1U)
76651 
76652 #define S_PCS_RX_CLK_2_G    29
76653 #define V_PCS_RX_CLK_2_G(x) ((x) << S_PCS_RX_CLK_2_G)
76654 #define F_PCS_RX_CLK_2_G    V_PCS_RX_CLK_2_G(1U)
76655 
76656 #define S_PCS_RX_CLK_3_G    28
76657 #define V_PCS_RX_CLK_3_G(x) ((x) << S_PCS_RX_CLK_3_G)
76658 #define F_PCS_RX_CLK_3_G    V_PCS_RX_CLK_3_G(1U)
76659 
76660 #define S_PCS_RX_CLK_4_G    27
76661 #define V_PCS_RX_CLK_4_G(x) ((x) << S_PCS_RX_CLK_4_G)
76662 #define F_PCS_RX_CLK_4_G    V_PCS_RX_CLK_4_G(1U)
76663 
76664 #define S_PCS_RX_CLK_5_G    26
76665 #define V_PCS_RX_CLK_5_G(x) ((x) << S_PCS_RX_CLK_5_G)
76666 #define F_PCS_RX_CLK_5_G    V_PCS_RX_CLK_5_G(1U)
76667 
76668 #define S_PCS_RX_CLK_6_G    25
76669 #define V_PCS_RX_CLK_6_G(x) ((x) << S_PCS_RX_CLK_6_G)
76670 #define F_PCS_RX_CLK_6_G    V_PCS_RX_CLK_6_G(1U)
76671 
76672 #define S_PCS_RX_CLK_7_G    24
76673 #define V_PCS_RX_CLK_7_G(x) ((x) << S_PCS_RX_CLK_7_G)
76674 #define F_PCS_RX_CLK_7_G    V_PCS_RX_CLK_7_G(1U)
76675 
76676 #define S_PCS_TX_CLK_0_G    23
76677 #define V_PCS_TX_CLK_0_G(x) ((x) << S_PCS_TX_CLK_0_G)
76678 #define F_PCS_TX_CLK_0_G    V_PCS_TX_CLK_0_G(1U)
76679 
76680 #define S_PCS_TX_CLK_1_G    22
76681 #define V_PCS_TX_CLK_1_G(x) ((x) << S_PCS_TX_CLK_1_G)
76682 #define F_PCS_TX_CLK_1_G    V_PCS_TX_CLK_1_G(1U)
76683 
76684 #define S_PCS_TX_CLK_2_G    21
76685 #define V_PCS_TX_CLK_2_G(x) ((x) << S_PCS_TX_CLK_2_G)
76686 #define F_PCS_TX_CLK_2_G    V_PCS_TX_CLK_2_G(1U)
76687 
76688 #define S_PCS_TX_CLK_3_G    20
76689 #define V_PCS_TX_CLK_3_G(x) ((x) << S_PCS_TX_CLK_3_G)
76690 #define F_PCS_TX_CLK_3_G    V_PCS_TX_CLK_3_G(1U)
76691 
76692 #define S_PCS_TX_CLK_4_G    19
76693 #define V_PCS_TX_CLK_4_G(x) ((x) << S_PCS_TX_CLK_4_G)
76694 #define F_PCS_TX_CLK_4_G    V_PCS_TX_CLK_4_G(1U)
76695 
76696 #define S_PCS_TX_CLK_5_G    18
76697 #define V_PCS_TX_CLK_5_G(x) ((x) << S_PCS_TX_CLK_5_G)
76698 #define F_PCS_TX_CLK_5_G    V_PCS_TX_CLK_5_G(1U)
76699 
76700 #define S_PCS_TX_CLK_6_G    17
76701 #define V_PCS_TX_CLK_6_G(x) ((x) << S_PCS_TX_CLK_6_G)
76702 #define F_PCS_TX_CLK_6_G    V_PCS_TX_CLK_6_G(1U)
76703 
76704 #define S_PCS_TX_CLK_7_G    16
76705 #define V_PCS_TX_CLK_7_G(x) ((x) << S_PCS_TX_CLK_7_G)
76706 #define F_PCS_TX_CLK_7_G    V_PCS_TX_CLK_7_G(1U)
76707 
76708 #define S_SD_RX_CLK_EN_0    15
76709 #define V_SD_RX_CLK_EN_0(x) ((x) << S_SD_RX_CLK_EN_0)
76710 #define F_SD_RX_CLK_EN_0    V_SD_RX_CLK_EN_0(1U)
76711 
76712 #define S_SD_RX_CLK_EN_1    14
76713 #define V_SD_RX_CLK_EN_1(x) ((x) << S_SD_RX_CLK_EN_1)
76714 #define F_SD_RX_CLK_EN_1    V_SD_RX_CLK_EN_1(1U)
76715 
76716 #define S_SD_RX_CLK_EN_2    13
76717 #define V_SD_RX_CLK_EN_2(x) ((x) << S_SD_RX_CLK_EN_2)
76718 #define F_SD_RX_CLK_EN_2    V_SD_RX_CLK_EN_2(1U)
76719 
76720 #define S_SD_RX_CLK_EN_3    12
76721 #define V_SD_RX_CLK_EN_3(x) ((x) << S_SD_RX_CLK_EN_3)
76722 #define F_SD_RX_CLK_EN_3    V_SD_RX_CLK_EN_3(1U)
76723 
76724 #define S_SD_RX_CLK_EN_4    11
76725 #define V_SD_RX_CLK_EN_4(x) ((x) << S_SD_RX_CLK_EN_4)
76726 #define F_SD_RX_CLK_EN_4    V_SD_RX_CLK_EN_4(1U)
76727 
76728 #define S_SD_RX_CLK_EN_5    10
76729 #define V_SD_RX_CLK_EN_5(x) ((x) << S_SD_RX_CLK_EN_5)
76730 #define F_SD_RX_CLK_EN_5    V_SD_RX_CLK_EN_5(1U)
76731 
76732 #define S_SD_RX_CLK_EN_6    9
76733 #define V_SD_RX_CLK_EN_6(x) ((x) << S_SD_RX_CLK_EN_6)
76734 #define F_SD_RX_CLK_EN_6    V_SD_RX_CLK_EN_6(1U)
76735 
76736 #define S_SD_RX_CLK_EN_7    8
76737 #define V_SD_RX_CLK_EN_7(x) ((x) << S_SD_RX_CLK_EN_7)
76738 #define F_SD_RX_CLK_EN_7    V_SD_RX_CLK_EN_7(1U)
76739 
76740 #define S_SD_TX_CLK_EN_0    7
76741 #define V_SD_TX_CLK_EN_0(x) ((x) << S_SD_TX_CLK_EN_0)
76742 #define F_SD_TX_CLK_EN_0    V_SD_TX_CLK_EN_0(1U)
76743 
76744 #define S_SD_TX_CLK_EN_1    6
76745 #define V_SD_TX_CLK_EN_1(x) ((x) << S_SD_TX_CLK_EN_1)
76746 #define F_SD_TX_CLK_EN_1    V_SD_TX_CLK_EN_1(1U)
76747 
76748 #define S_SD_TX_CLK_EN_2    5
76749 #define V_SD_TX_CLK_EN_2(x) ((x) << S_SD_TX_CLK_EN_2)
76750 #define F_SD_TX_CLK_EN_2    V_SD_TX_CLK_EN_2(1U)
76751 
76752 #define S_SD_TX_CLK_EN_3    4
76753 #define V_SD_TX_CLK_EN_3(x) ((x) << S_SD_TX_CLK_EN_3)
76754 #define F_SD_TX_CLK_EN_3    V_SD_TX_CLK_EN_3(1U)
76755 
76756 #define S_SD_TX_CLK_EN_4    3
76757 #define V_SD_TX_CLK_EN_4(x) ((x) << S_SD_TX_CLK_EN_4)
76758 #define F_SD_TX_CLK_EN_4    V_SD_TX_CLK_EN_4(1U)
76759 
76760 #define S_SD_TX_CLK_EN_5    2
76761 #define V_SD_TX_CLK_EN_5(x) ((x) << S_SD_TX_CLK_EN_5)
76762 #define F_SD_TX_CLK_EN_5    V_SD_TX_CLK_EN_5(1U)
76763 
76764 #define S_SD_TX_CLK_EN_6    1
76765 #define V_SD_TX_CLK_EN_6(x) ((x) << S_SD_TX_CLK_EN_6)
76766 #define F_SD_TX_CLK_EN_6    V_SD_TX_CLK_EN_6(1U)
76767 
76768 #define S_SD_TX_CLK_EN_7    0
76769 #define V_SD_TX_CLK_EN_7(x) ((x) << S_SD_TX_CLK_EN_7)
76770 #define F_SD_TX_CLK_EN_7    V_SD_TX_CLK_EN_7(1U)
76771 
76772 #define A_MAC_MTIP_CLK_CTRL_4 0x38020
76773 
76774 #define S_SGMII_TX_CLK_0_G    7
76775 #define V_SGMII_TX_CLK_0_G(x) ((x) << S_SGMII_TX_CLK_0_G)
76776 #define F_SGMII_TX_CLK_0_G    V_SGMII_TX_CLK_0_G(1U)
76777 
76778 #define S_SGMII_TX_CLK_1_G    6
76779 #define V_SGMII_TX_CLK_1_G(x) ((x) << S_SGMII_TX_CLK_1_G)
76780 #define F_SGMII_TX_CLK_1_G    V_SGMII_TX_CLK_1_G(1U)
76781 
76782 #define S_SGMII_TX_CLK_2_G    5
76783 #define V_SGMII_TX_CLK_2_G(x) ((x) << S_SGMII_TX_CLK_2_G)
76784 #define F_SGMII_TX_CLK_2_G    V_SGMII_TX_CLK_2_G(1U)
76785 
76786 #define S_SGMII_TX_CLK_3_G    4
76787 #define V_SGMII_TX_CLK_3_G(x) ((x) << S_SGMII_TX_CLK_3_G)
76788 #define F_SGMII_TX_CLK_3_G    V_SGMII_TX_CLK_3_G(1U)
76789 
76790 #define S_SGMII_RX_CLK_0_G    3
76791 #define V_SGMII_RX_CLK_0_G(x) ((x) << S_SGMII_RX_CLK_0_G)
76792 #define F_SGMII_RX_CLK_0_G    V_SGMII_RX_CLK_0_G(1U)
76793 
76794 #define S_SGMII_RX_CLK_1_G    2
76795 #define V_SGMII_RX_CLK_1_G(x) ((x) << S_SGMII_RX_CLK_1_G)
76796 #define F_SGMII_RX_CLK_1_G    V_SGMII_RX_CLK_1_G(1U)
76797 
76798 #define S_SGMII_RX_CLK_2_G    1
76799 #define V_SGMII_RX_CLK_2_G(x) ((x) << S_SGMII_RX_CLK_2_G)
76800 #define F_SGMII_RX_CLK_2_G    V_SGMII_RX_CLK_2_G(1U)
76801 
76802 #define S_SGMII_RX_CLK_3_G    0
76803 #define V_SGMII_RX_CLK_3_G(x) ((x) << S_SGMII_RX_CLK_3_G)
76804 #define F_SGMII_RX_CLK_3_G    V_SGMII_RX_CLK_3_G(1U)
76805 
76806 #define A_MAC_PCS_CONFIG_0 0x38024
76807 
76808 #define S_KP_MODE_IN    24
76809 #define M_KP_MODE_IN    0xffU
76810 #define V_KP_MODE_IN(x) ((x) << S_KP_MODE_IN)
76811 #define G_KP_MODE_IN(x) (((x) >> S_KP_MODE_IN) & M_KP_MODE_IN)
76812 
76813 #define S_FEC91_ENA_IN    16
76814 #define M_FEC91_ENA_IN    0xffU
76815 #define V_FEC91_ENA_IN(x) ((x) << S_FEC91_ENA_IN)
76816 #define G_FEC91_ENA_IN(x) (((x) >> S_FEC91_ENA_IN) & M_FEC91_ENA_IN)
76817 
76818 #define S_SD_8X    8
76819 #define M_SD_8X    0xffU
76820 #define V_SD_8X(x) ((x) << S_SD_8X)
76821 #define G_SD_8X(x) (((x) >> S_SD_8X) & M_SD_8X)
76822 
76823 #define S_SD_N2    0
76824 #define M_SD_N2    0xffU
76825 #define V_SD_N2(x) ((x) << S_SD_N2)
76826 #define G_SD_N2(x) (((x) >> S_SD_N2) & M_SD_N2)
76827 
76828 #define A_MAC_PCS_CONFIG_1 0x38028
76829 
76830 #define S_FAST_1LANE_MODE    24
76831 #define M_FAST_1LANE_MODE    0xffU
76832 #define V_FAST_1LANE_MODE(x) ((x) << S_FAST_1LANE_MODE)
76833 #define G_FAST_1LANE_MODE(x) (((x) >> S_FAST_1LANE_MODE) & M_FAST_1LANE_MODE)
76834 
76835 #define S_PACER_10G    16
76836 #define M_PACER_10G    0xffU
76837 #define V_PACER_10G(x) ((x) << S_PACER_10G)
76838 #define G_PACER_10G(x) (((x) >> S_PACER_10G) & M_PACER_10G)
76839 
76840 #define S_PCS400_ENA_IN    14
76841 #define M_PCS400_ENA_IN    0x3U
76842 #define V_PCS400_ENA_IN(x) ((x) << S_PCS400_ENA_IN)
76843 #define G_PCS400_ENA_IN(x) (((x) >> S_PCS400_ENA_IN) & M_PCS400_ENA_IN)
76844 
76845 #define S_MODE40_ENA_IN4    13
76846 #define V_MODE40_ENA_IN4(x) ((x) << S_MODE40_ENA_IN4)
76847 #define F_MODE40_ENA_IN4    V_MODE40_ENA_IN4(1U)
76848 
76849 #define S_MODE40_ENA_IN0    12
76850 #define V_MODE40_ENA_IN0(x) ((x) << S_MODE40_ENA_IN0)
76851 #define F_MODE40_ENA_IN0    V_MODE40_ENA_IN0(1U)
76852 
76853 #define S_PCS100_ENA_IN6    11
76854 #define V_PCS100_ENA_IN6(x) ((x) << S_PCS100_ENA_IN6)
76855 #define F_PCS100_ENA_IN6    V_PCS100_ENA_IN6(1U)
76856 
76857 #define S_PCS100_ENA_IN4    10
76858 #define V_PCS100_ENA_IN4(x) ((x) << S_PCS100_ENA_IN4)
76859 #define F_PCS100_ENA_IN4    V_PCS100_ENA_IN4(1U)
76860 
76861 #define S_PCS100_ENA_IN2    9
76862 #define V_PCS100_ENA_IN2(x) ((x) << S_PCS100_ENA_IN2)
76863 #define F_PCS100_ENA_IN2    V_PCS100_ENA_IN2(1U)
76864 
76865 #define S_PCS100_ENA_IN0    8
76866 #define V_PCS100_ENA_IN0(x) ((x) << S_PCS100_ENA_IN0)
76867 #define F_PCS100_ENA_IN0    V_PCS100_ENA_IN0(1U)
76868 
76869 #define S_RXLAUI_ENA_IN6    7
76870 #define V_RXLAUI_ENA_IN6(x) ((x) << S_RXLAUI_ENA_IN6)
76871 #define F_RXLAUI_ENA_IN6    V_RXLAUI_ENA_IN6(1U)
76872 
76873 #define S_RXLAUI_ENA_IN4    6
76874 #define V_RXLAUI_ENA_IN4(x) ((x) << S_RXLAUI_ENA_IN4)
76875 #define F_RXLAUI_ENA_IN4    V_RXLAUI_ENA_IN4(1U)
76876 
76877 #define S_RXLAUI_ENA_IN2    5
76878 #define V_RXLAUI_ENA_IN2(x) ((x) << S_RXLAUI_ENA_IN2)
76879 #define F_RXLAUI_ENA_IN2    V_RXLAUI_ENA_IN2(1U)
76880 
76881 #define S_RXLAUI_ENA_IN0    4
76882 #define V_RXLAUI_ENA_IN0(x) ((x) << S_RXLAUI_ENA_IN0)
76883 #define F_RXLAUI_ENA_IN0    V_RXLAUI_ENA_IN0(1U)
76884 
76885 #define S_FEC91_LANE_IN6    3
76886 #define V_FEC91_LANE_IN6(x) ((x) << S_FEC91_LANE_IN6)
76887 #define F_FEC91_LANE_IN6    V_FEC91_LANE_IN6(1U)
76888 
76889 #define S_FEC91_LANE_IN4    2
76890 #define V_FEC91_LANE_IN4(x) ((x) << S_FEC91_LANE_IN4)
76891 #define F_FEC91_LANE_IN4    V_FEC91_LANE_IN4(1U)
76892 
76893 #define S_FEC91_LANE_IN2    1
76894 #define V_FEC91_LANE_IN2(x) ((x) << S_FEC91_LANE_IN2)
76895 #define F_FEC91_LANE_IN2    V_FEC91_LANE_IN2(1U)
76896 
76897 #define S_FEC91_LANE_IN0    0
76898 #define V_FEC91_LANE_IN0(x) ((x) << S_FEC91_LANE_IN0)
76899 #define F_FEC91_LANE_IN0    V_FEC91_LANE_IN0(1U)
76900 
76901 #define A_MAC_PCS_CONFIG_2 0x3802c
76902 
76903 #define S_SGPCS_EN_3    29
76904 #define V_SGPCS_EN_3(x) ((x) << S_SGPCS_EN_3)
76905 #define F_SGPCS_EN_3    V_SGPCS_EN_3(1U)
76906 
76907 #define S_SGPCS_EN_2    28
76908 #define V_SGPCS_EN_2(x) ((x) << S_SGPCS_EN_2)
76909 #define F_SGPCS_EN_2    V_SGPCS_EN_2(1U)
76910 
76911 #define S_SGPCS_EN_1    27
76912 #define V_SGPCS_EN_1(x) ((x) << S_SGPCS_EN_1)
76913 #define F_SGPCS_EN_1    V_SGPCS_EN_1(1U)
76914 
76915 #define S_SGPCS_EN_0    26
76916 #define V_SGPCS_EN_0(x) ((x) << S_SGPCS_EN_0)
76917 #define F_SGPCS_EN_0    V_SGPCS_EN_0(1U)
76918 
76919 #define S_CFG_CLOCK_RATE    22
76920 #define M_CFG_CLOCK_RATE    0xfU
76921 #define V_CFG_CLOCK_RATE(x) ((x) << S_CFG_CLOCK_RATE)
76922 #define G_CFG_CLOCK_RATE(x) (((x) >> S_CFG_CLOCK_RATE) & M_CFG_CLOCK_RATE)
76923 
76924 #define S_FEC_ERR_ENA    14
76925 #define M_FEC_ERR_ENA    0xffU
76926 #define V_FEC_ERR_ENA(x) ((x) << S_FEC_ERR_ENA)
76927 #define G_FEC_ERR_ENA(x) (((x) >> S_FEC_ERR_ENA) & M_FEC_ERR_ENA)
76928 
76929 #define S_FEC_ENA    6
76930 #define M_FEC_ENA    0xffU
76931 #define V_FEC_ENA(x) ((x) << S_FEC_ENA)
76932 #define G_FEC_ENA(x) (((x) >> S_FEC_ENA) & M_FEC_ENA)
76933 
76934 #define S_PCS001_TX_AM_SF    3
76935 #define M_PCS001_TX_AM_SF    0x7U
76936 #define V_PCS001_TX_AM_SF(x) ((x) << S_PCS001_TX_AM_SF)
76937 #define G_PCS001_TX_AM_SF(x) (((x) >> S_PCS001_TX_AM_SF) & M_PCS001_TX_AM_SF)
76938 
76939 #define S_PCS000_TX_AM_SF    0
76940 #define M_PCS000_TX_AM_SF    0x7U
76941 #define V_PCS000_TX_AM_SF(x) ((x) << S_PCS000_TX_AM_SF)
76942 #define G_PCS000_TX_AM_SF(x) (((x) >> S_PCS000_TX_AM_SF) & M_PCS000_TX_AM_SF)
76943 
76944 #define A_MAC_PCS_STATUS_0 0x38030
76945 
76946 #define S_PCS000_ALIGN_LOCK    30
76947 #define M_PCS000_ALIGN_LOCK    0x3U
76948 #define V_PCS000_ALIGN_LOCK(x) ((x) << S_PCS000_ALIGN_LOCK)
76949 #define G_PCS000_ALIGN_LOCK(x) (((x) >> S_PCS000_ALIGN_LOCK) & M_PCS000_ALIGN_LOCK)
76950 
76951 #define S_PCS000_HI_SER    28
76952 #define M_PCS000_HI_SER    0x3U
76953 #define V_PCS000_HI_SER(x) ((x) << S_PCS000_HI_SER)
76954 #define G_PCS000_HI_SER(x) (((x) >> S_PCS000_HI_SER) & M_PCS000_HI_SER)
76955 
76956 #define S_BER_TIMER_DONE    20
76957 #define M_BER_TIMER_DONE    0xffU
76958 #define V_BER_TIMER_DONE(x) ((x) << S_BER_TIMER_DONE)
76959 #define G_BER_TIMER_DONE(x) (((x) >> S_BER_TIMER_DONE) & M_BER_TIMER_DONE)
76960 
76961 #define S_T7_AMPS_LOCK    4
76962 #define M_T7_AMPS_LOCK    0xffffU
76963 #define V_T7_AMPS_LOCK(x) ((x) << S_T7_AMPS_LOCK)
76964 #define G_T7_AMPS_LOCK(x) (((x) >> S_T7_AMPS_LOCK) & M_T7_AMPS_LOCK)
76965 
76966 #define S_T7_ALIGN_DONE    0
76967 #define M_T7_ALIGN_DONE    0xfU
76968 #define V_T7_ALIGN_DONE(x) ((x) << S_T7_ALIGN_DONE)
76969 #define G_T7_ALIGN_DONE(x) (((x) >> S_T7_ALIGN_DONE) & M_T7_ALIGN_DONE)
76970 
76971 #define A_MAC_PCS_STATUS_1 0x38034
76972 #define A_MAC_PCS_STATUS_2 0x38038
76973 
76974 #define S_RSFEC_ALIGNED    24
76975 #define M_RSFEC_ALIGNED    0xffU
76976 #define V_RSFEC_ALIGNED(x) ((x) << S_RSFEC_ALIGNED)
76977 #define G_RSFEC_ALIGNED(x) (((x) >> S_RSFEC_ALIGNED) & M_RSFEC_ALIGNED)
76978 
76979 #define S_T7_FEC_LOCKED    8
76980 #define M_T7_FEC_LOCKED    0xffffU
76981 #define V_T7_FEC_LOCKED(x) ((x) << S_T7_FEC_LOCKED)
76982 #define G_T7_FEC_LOCKED(x) (((x) >> S_T7_FEC_LOCKED) & M_T7_FEC_LOCKED)
76983 
76984 #define S_T7_BLOCK_LOCK    0
76985 #define M_T7_BLOCK_LOCK    0xffU
76986 #define V_T7_BLOCK_LOCK(x) ((x) << S_T7_BLOCK_LOCK)
76987 #define G_T7_BLOCK_LOCK(x) (((x) >> S_T7_BLOCK_LOCK) & M_T7_BLOCK_LOCK)
76988 
76989 #define A_MAC_PCS_STATUS_3 0x3803c
76990 
76991 #define S_FEC_NCERR    16
76992 #define M_FEC_NCERR    0xffffU
76993 #define V_FEC_NCERR(x) ((x) << S_FEC_NCERR)
76994 #define G_FEC_NCERR(x) (((x) >> S_FEC_NCERR) & M_FEC_NCERR)
76995 
76996 #define S_FEC_CERR    0
76997 #define M_FEC_CERR    0xffffU
76998 #define V_FEC_CERR(x) ((x) << S_FEC_CERR)
76999 #define G_FEC_CERR(x) (((x) >> S_FEC_CERR) & M_FEC_CERR)
77000 
77001 #define A_MAC_PCS_STATUS_4 0x38040
77002 
77003 #define S_MAC1_RES_SPEED    23
77004 #define M_MAC1_RES_SPEED    0xffU
77005 #define V_MAC1_RES_SPEED(x) ((x) << S_MAC1_RES_SPEED)
77006 #define G_MAC1_RES_SPEED(x) (((x) >> S_MAC1_RES_SPEED) & M_MAC1_RES_SPEED)
77007 
77008 #define S_MAC0_RES_SPEED    14
77009 #define M_MAC0_RES_SPEED    0xffU
77010 #define V_MAC0_RES_SPEED(x) ((x) << S_MAC0_RES_SPEED)
77011 #define G_MAC0_RES_SPEED(x) (((x) >> S_MAC0_RES_SPEED) & M_MAC0_RES_SPEED)
77012 
77013 #define S_PCS400_ENA_IN_REF    12
77014 #define M_PCS400_ENA_IN_REF    0x3U
77015 #define V_PCS400_ENA_IN_REF(x) ((x) << S_PCS400_ENA_IN_REF)
77016 #define G_PCS400_ENA_IN_REF(x) (((x) >> S_PCS400_ENA_IN_REF) & M_PCS400_ENA_IN_REF)
77017 
77018 #define S_PCS000_DEGRADE_SER    10
77019 #define M_PCS000_DEGRADE_SER    0x3U
77020 #define V_PCS000_DEGRADE_SER(x) ((x) << S_PCS000_DEGRADE_SER)
77021 #define G_PCS000_DEGRADE_SER(x) (((x) >> S_PCS000_DEGRADE_SER) & M_PCS000_DEGRADE_SER)
77022 
77023 #define S_P4X_SIGNAL_OK    8
77024 #define M_P4X_SIGNAL_OK    0x3U
77025 #define V_P4X_SIGNAL_OK(x) ((x) << S_P4X_SIGNAL_OK)
77026 #define G_P4X_SIGNAL_OK(x) (((x) >> S_P4X_SIGNAL_OK) & M_P4X_SIGNAL_OK)
77027 
77028 #define S_MODE200_IND_REF    7
77029 #define V_MODE200_IND_REF(x) ((x) << S_MODE200_IND_REF)
77030 #define F_MODE200_IND_REF    V_MODE200_IND_REF(1U)
77031 
77032 #define S_MODE200_8X26_IND_REF    6
77033 #define V_MODE200_8X26_IND_REF(x) ((x) << S_MODE200_8X26_IND_REF)
77034 #define F_MODE200_8X26_IND_REF    V_MODE200_8X26_IND_REF(1U)
77035 
77036 #define S_PCS001_RX_AM_SF    3
77037 #define M_PCS001_RX_AM_SF    0x7U
77038 #define V_PCS001_RX_AM_SF(x) ((x) << S_PCS001_RX_AM_SF)
77039 #define G_PCS001_RX_AM_SF(x) (((x) >> S_PCS001_RX_AM_SF) & M_PCS001_RX_AM_SF)
77040 
77041 #define S_PCS000_RX_AM_SF    0
77042 #define M_PCS000_RX_AM_SF    0x7U
77043 #define V_PCS000_RX_AM_SF(x) ((x) << S_PCS000_RX_AM_SF)
77044 #define G_PCS000_RX_AM_SF(x) (((x) >> S_PCS000_RX_AM_SF) & M_PCS000_RX_AM_SF)
77045 
77046 #define A_MAC_PCS_STATUS_5 0x38044
77047 
77048 #define S_MAC5_RES_SPEED    24
77049 #define M_MAC5_RES_SPEED    0xffU
77050 #define V_MAC5_RES_SPEED(x) ((x) << S_MAC5_RES_SPEED)
77051 #define G_MAC5_RES_SPEED(x) (((x) >> S_MAC5_RES_SPEED) & M_MAC5_RES_SPEED)
77052 
77053 #define S_MAC4_RES_SPEED    16
77054 #define M_MAC4_RES_SPEED    0xffU
77055 #define V_MAC4_RES_SPEED(x) ((x) << S_MAC4_RES_SPEED)
77056 #define G_MAC4_RES_SPEED(x) (((x) >> S_MAC4_RES_SPEED) & M_MAC4_RES_SPEED)
77057 
77058 #define S_MAC3_RES_SPEED    8
77059 #define M_MAC3_RES_SPEED    0xffU
77060 #define V_MAC3_RES_SPEED(x) ((x) << S_MAC3_RES_SPEED)
77061 #define G_MAC3_RES_SPEED(x) (((x) >> S_MAC3_RES_SPEED) & M_MAC3_RES_SPEED)
77062 
77063 #define S_MAC2_RES_SPEED    0
77064 #define M_MAC2_RES_SPEED    0xffU
77065 #define V_MAC2_RES_SPEED(x) ((x) << S_MAC2_RES_SPEED)
77066 #define G_MAC2_RES_SPEED(x) (((x) >> S_MAC2_RES_SPEED) & M_MAC2_RES_SPEED)
77067 
77068 #define A_MAC_PCS_STATUS_6 0x38048
77069 
77070 #define S_MARKER_INS_CNT_100_00    16
77071 #define M_MARKER_INS_CNT_100_00    0x7fffU
77072 #define V_MARKER_INS_CNT_100_00(x) ((x) << S_MARKER_INS_CNT_100_00)
77073 #define G_MARKER_INS_CNT_100_00(x) (((x) >> S_MARKER_INS_CNT_100_00) & M_MARKER_INS_CNT_100_00)
77074 
77075 #define S_MAC7_RES_SPEED    8
77076 #define M_MAC7_RES_SPEED    0xffU
77077 #define V_MAC7_RES_SPEED(x) ((x) << S_MAC7_RES_SPEED)
77078 #define G_MAC7_RES_SPEED(x) (((x) >> S_MAC7_RES_SPEED) & M_MAC7_RES_SPEED)
77079 
77080 #define S_MAC6_RES_SPEED    0
77081 #define M_MAC6_RES_SPEED    0xffU
77082 #define V_MAC6_RES_SPEED(x) ((x) << S_MAC6_RES_SPEED)
77083 #define G_MAC6_RES_SPEED(x) (((x) >> S_MAC6_RES_SPEED) & M_MAC6_RES_SPEED)
77084 
77085 #define A_MAC_PCS_STATUS_7 0x3804c
77086 
77087 #define S_PCS000_LINK_STATUS    30
77088 #define M_PCS000_LINK_STATUS    0x3U
77089 #define V_PCS000_LINK_STATUS(x) ((x) << S_PCS000_LINK_STATUS)
77090 #define G_PCS000_LINK_STATUS(x) (((x) >> S_PCS000_LINK_STATUS) & M_PCS000_LINK_STATUS)
77091 
77092 #define S_MARKER_INS_CNT_100_02    15
77093 #define M_MARKER_INS_CNT_100_02    0x7fffU
77094 #define V_MARKER_INS_CNT_100_02(x) ((x) << S_MARKER_INS_CNT_100_02)
77095 #define G_MARKER_INS_CNT_100_02(x) (((x) >> S_MARKER_INS_CNT_100_02) & M_MARKER_INS_CNT_100_02)
77096 
77097 #define S_MARKER_INS_CNT_100_01    0
77098 #define M_MARKER_INS_CNT_100_01    0x7fffU
77099 #define V_MARKER_INS_CNT_100_01(x) ((x) << S_MARKER_INS_CNT_100_01)
77100 #define G_MARKER_INS_CNT_100_01(x) (((x) >> S_MARKER_INS_CNT_100_01) & M_MARKER_INS_CNT_100_01)
77101 
77102 #define A_MAC_PCS_STATUS_8 0x38050
77103 
77104 #define S_MARKER_INS_CNT_25_1    15
77105 #define M_MARKER_INS_CNT_25_1    0xffffU
77106 #define V_MARKER_INS_CNT_25_1(x) ((x) << S_MARKER_INS_CNT_25_1)
77107 #define G_MARKER_INS_CNT_25_1(x) (((x) >> S_MARKER_INS_CNT_25_1) & M_MARKER_INS_CNT_25_1)
77108 
77109 #define S_MARKER_INS_CNT_100_03    0
77110 #define M_MARKER_INS_CNT_100_03    0x7fffU
77111 #define V_MARKER_INS_CNT_100_03(x) ((x) << S_MARKER_INS_CNT_100_03)
77112 #define G_MARKER_INS_CNT_100_03(x) (((x) >> S_MARKER_INS_CNT_100_03) & M_MARKER_INS_CNT_100_03)
77113 
77114 #define A_MAC_PCS_STATUS_9 0x38054
77115 
77116 #define S_MARKER_INS_CNT_25_5    16
77117 #define M_MARKER_INS_CNT_25_5    0xffffU
77118 #define V_MARKER_INS_CNT_25_5(x) ((x) << S_MARKER_INS_CNT_25_5)
77119 #define G_MARKER_INS_CNT_25_5(x) (((x) >> S_MARKER_INS_CNT_25_5) & M_MARKER_INS_CNT_25_5)
77120 
77121 #define S_MARKER_INS_CNT_25_3    0
77122 #define M_MARKER_INS_CNT_25_3    0xffffU
77123 #define V_MARKER_INS_CNT_25_3(x) ((x) << S_MARKER_INS_CNT_25_3)
77124 #define G_MARKER_INS_CNT_25_3(x) (((x) >> S_MARKER_INS_CNT_25_3) & M_MARKER_INS_CNT_25_3)
77125 
77126 #define A_MAC_PCS_STATUS_10 0x38058
77127 
77128 #define S_MARKER_INS_CNT_25_50_2    16
77129 #define M_MARKER_INS_CNT_25_50_2    0xffffU
77130 #define V_MARKER_INS_CNT_25_50_2(x) ((x) << S_MARKER_INS_CNT_25_50_2)
77131 #define G_MARKER_INS_CNT_25_50_2(x) (((x) >> S_MARKER_INS_CNT_25_50_2) & M_MARKER_INS_CNT_25_50_2)
77132 
77133 #define S_MARKER_INS_CNT_25_50_0    0
77134 #define M_MARKER_INS_CNT_25_50_0    0xffffU
77135 #define V_MARKER_INS_CNT_25_50_0(x) ((x) << S_MARKER_INS_CNT_25_50_0)
77136 #define G_MARKER_INS_CNT_25_50_0(x) (((x) >> S_MARKER_INS_CNT_25_50_0) & M_MARKER_INS_CNT_25_50_0)
77137 
77138 #define A_MAC_PCS_STATUS_11 0x3805c
77139 
77140 #define S_MARKER_INS_CNT_25_50_6    16
77141 #define M_MARKER_INS_CNT_25_50_6    0xffffU
77142 #define V_MARKER_INS_CNT_25_50_6(x) ((x) << S_MARKER_INS_CNT_25_50_6)
77143 #define G_MARKER_INS_CNT_25_50_6(x) (((x) >> S_MARKER_INS_CNT_25_50_6) & M_MARKER_INS_CNT_25_50_6)
77144 
77145 #define S_MARKER_INS_CNT_25_50_4    0
77146 #define M_MARKER_INS_CNT_25_50_4    0xffffU
77147 #define V_MARKER_INS_CNT_25_50_4(x) ((x) << S_MARKER_INS_CNT_25_50_4)
77148 #define G_MARKER_INS_CNT_25_50_4(x) (((x) >> S_MARKER_INS_CNT_25_50_4) & M_MARKER_INS_CNT_25_50_4)
77149 
77150 #define A_MAC_PCS_STATUS_12 0x38060
77151 
77152 #define S_T7_LINK_STATUS    24
77153 #define M_T7_LINK_STATUS    0xffU
77154 #define V_T7_LINK_STATUS(x) ((x) << S_T7_LINK_STATUS)
77155 #define G_T7_LINK_STATUS(x) (((x) >> S_T7_LINK_STATUS) & M_T7_LINK_STATUS)
77156 
77157 #define S_T7_HI_BER    16
77158 #define M_T7_HI_BER    0xffU
77159 #define V_T7_HI_BER(x) ((x) << S_T7_HI_BER)
77160 #define G_T7_HI_BER(x) (((x) >> S_T7_HI_BER) & M_T7_HI_BER)
77161 
77162 #define S_MARKER_INS_CNT_25_7    0
77163 #define M_MARKER_INS_CNT_25_7    0xffffU
77164 #define V_MARKER_INS_CNT_25_7(x) ((x) << S_MARKER_INS_CNT_25_7)
77165 #define G_MARKER_INS_CNT_25_7(x) (((x) >> S_MARKER_INS_CNT_25_7) & M_MARKER_INS_CNT_25_7)
77166 
77167 #define A_MAC_MAC200G400G_0_CONFIG_0 0x38064
77168 #define A_MAC_MAC200G400G_0_CONFIG_1 0x38068
77169 
77170 #define S_FF_TX_CRC_OVR    11
77171 #define V_FF_TX_CRC_OVR(x) ((x) << S_FF_TX_CRC_OVR)
77172 #define F_FF_TX_CRC_OVR    V_FF_TX_CRC_OVR(1U)
77173 
77174 #define S_TX_SMHOLD    2
77175 #define V_TX_SMHOLD(x) ((x) << S_TX_SMHOLD)
77176 #define F_TX_SMHOLD    V_TX_SMHOLD(1U)
77177 
77178 #define A_MAC_MAC200G400G_0_CONFIG_2 0x3806c
77179 #define A_MAC_MAC200G400G_0_CONFIG_3 0x38070
77180 #define A_MAC_MAC200G400G_0_CONFIG_4 0x38074
77181 
77182 #define S_FRC_DELTA    0
77183 #define M_FRC_DELTA    0xffffU
77184 #define V_FRC_DELTA(x) ((x) << S_FRC_DELTA)
77185 #define G_FRC_DELTA(x) (((x) >> S_FRC_DELTA) & M_FRC_DELTA)
77186 
77187 #define A_MAC_MAC200G400G_0_STATUS 0x38078
77188 
77189 #define S_T7_LOOP_ENA    4
77190 #define V_T7_LOOP_ENA(x) ((x) << S_T7_LOOP_ENA)
77191 #define F_T7_LOOP_ENA    V_T7_LOOP_ENA(1U)
77192 
77193 #define S_T7_LOC_FAULT    3
77194 #define V_T7_LOC_FAULT(x) ((x) << S_T7_LOC_FAULT)
77195 #define F_T7_LOC_FAULT    V_T7_LOC_FAULT(1U)
77196 
77197 #define S_FRM_DROP    2
77198 #define V_FRM_DROP(x) ((x) << S_FRM_DROP)
77199 #define F_FRM_DROP    V_FRM_DROP(1U)
77200 
77201 #define S_FF_TX_CREDIT    1
77202 #define V_FF_TX_CREDIT(x) ((x) << S_FF_TX_CREDIT)
77203 #define F_FF_TX_CREDIT    V_FF_TX_CREDIT(1U)
77204 
77205 #define A_MAC_MAC200G400G_1_CONFIG_0 0x3807c
77206 #define A_MAC_MAC200G400G_1_CONFIG_1 0x38080
77207 #define A_MAC_MAC200G400G_1_CONFIG_2 0x38084
77208 #define A_MAC_MAC200G400G_1_CONFIG_3 0x38088
77209 #define A_MAC_MAC200G400G_1_CONFIG_4 0x3808c
77210 #define A_MAC_MAC200G400G_1_STATUS 0x38090
77211 #define A_MAC_AN_CFG_0 0x38094
77212 
77213 #define S_T7_AN_DATA_CTL    24
77214 #define M_T7_AN_DATA_CTL    0xffU
77215 #define V_T7_AN_DATA_CTL(x) ((x) << S_T7_AN_DATA_CTL)
77216 #define G_T7_AN_DATA_CTL(x) (((x) >> S_T7_AN_DATA_CTL) & M_T7_AN_DATA_CTL)
77217 
77218 #define S_T7_AN_ENA    16
77219 #define M_T7_AN_ENA    0xffU
77220 #define V_T7_AN_ENA(x) ((x) << S_T7_AN_ENA)
77221 #define G_T7_AN_ENA(x) (((x) >> S_T7_AN_ENA) & M_T7_AN_ENA)
77222 
77223 #define A_MAC_AN_CFG_1 0x38098
77224 
77225 #define S_AN_DIS_TIMER_AN_7    7
77226 #define V_AN_DIS_TIMER_AN_7(x) ((x) << S_AN_DIS_TIMER_AN_7)
77227 #define F_AN_DIS_TIMER_AN_7    V_AN_DIS_TIMER_AN_7(1U)
77228 
77229 #define S_AN_DIS_TIMER_AN_6    6
77230 #define V_AN_DIS_TIMER_AN_6(x) ((x) << S_AN_DIS_TIMER_AN_6)
77231 #define F_AN_DIS_TIMER_AN_6    V_AN_DIS_TIMER_AN_6(1U)
77232 
77233 #define S_AN_DIS_TIMER_AN_5    5
77234 #define V_AN_DIS_TIMER_AN_5(x) ((x) << S_AN_DIS_TIMER_AN_5)
77235 #define F_AN_DIS_TIMER_AN_5    V_AN_DIS_TIMER_AN_5(1U)
77236 
77237 #define S_AN_DIS_TIMER_AN_4    4
77238 #define V_AN_DIS_TIMER_AN_4(x) ((x) << S_AN_DIS_TIMER_AN_4)
77239 #define F_AN_DIS_TIMER_AN_4    V_AN_DIS_TIMER_AN_4(1U)
77240 
77241 #define S_AN_DIS_TIMER_AN_3    3
77242 #define V_AN_DIS_TIMER_AN_3(x) ((x) << S_AN_DIS_TIMER_AN_3)
77243 #define F_AN_DIS_TIMER_AN_3    V_AN_DIS_TIMER_AN_3(1U)
77244 
77245 #define S_AN_DIS_TIMER_AN_2    2
77246 #define V_AN_DIS_TIMER_AN_2(x) ((x) << S_AN_DIS_TIMER_AN_2)
77247 #define F_AN_DIS_TIMER_AN_2    V_AN_DIS_TIMER_AN_2(1U)
77248 
77249 #define S_AN_DIS_TIMER_AN_1    1
77250 #define V_AN_DIS_TIMER_AN_1(x) ((x) << S_AN_DIS_TIMER_AN_1)
77251 #define F_AN_DIS_TIMER_AN_1    V_AN_DIS_TIMER_AN_1(1U)
77252 
77253 #define S_AN_DIS_TIMER_AN_0    0
77254 #define V_AN_DIS_TIMER_AN_0(x) ((x) << S_AN_DIS_TIMER_AN_0)
77255 #define F_AN_DIS_TIMER_AN_0    V_AN_DIS_TIMER_AN_0(1U)
77256 
77257 #define A_MAC_AN_SERDES25G_ENA 0x3809c
77258 
77259 #define S_AN_SD25_TX_ENA_7    15
77260 #define V_AN_SD25_TX_ENA_7(x) ((x) << S_AN_SD25_TX_ENA_7)
77261 #define F_AN_SD25_TX_ENA_7    V_AN_SD25_TX_ENA_7(1U)
77262 
77263 #define S_AN_SD25_TX_ENA_6    14
77264 #define V_AN_SD25_TX_ENA_6(x) ((x) << S_AN_SD25_TX_ENA_6)
77265 #define F_AN_SD25_TX_ENA_6    V_AN_SD25_TX_ENA_6(1U)
77266 
77267 #define S_AN_SD25_TX_ENA_5    13
77268 #define V_AN_SD25_TX_ENA_5(x) ((x) << S_AN_SD25_TX_ENA_5)
77269 #define F_AN_SD25_TX_ENA_5    V_AN_SD25_TX_ENA_5(1U)
77270 
77271 #define S_AN_SD25_TX_ENA_4    12
77272 #define V_AN_SD25_TX_ENA_4(x) ((x) << S_AN_SD25_TX_ENA_4)
77273 #define F_AN_SD25_TX_ENA_4    V_AN_SD25_TX_ENA_4(1U)
77274 
77275 #define S_AN_SD25_TX_ENA_3    11
77276 #define V_AN_SD25_TX_ENA_3(x) ((x) << S_AN_SD25_TX_ENA_3)
77277 #define F_AN_SD25_TX_ENA_3    V_AN_SD25_TX_ENA_3(1U)
77278 
77279 #define S_AN_SD25_TX_ENA_2    10
77280 #define V_AN_SD25_TX_ENA_2(x) ((x) << S_AN_SD25_TX_ENA_2)
77281 #define F_AN_SD25_TX_ENA_2    V_AN_SD25_TX_ENA_2(1U)
77282 
77283 #define S_AN_SD25_TX_ENA_1    9
77284 #define V_AN_SD25_TX_ENA_1(x) ((x) << S_AN_SD25_TX_ENA_1)
77285 #define F_AN_SD25_TX_ENA_1    V_AN_SD25_TX_ENA_1(1U)
77286 
77287 #define S_AN_SD25_TX_ENA_0    8
77288 #define V_AN_SD25_TX_ENA_0(x) ((x) << S_AN_SD25_TX_ENA_0)
77289 #define F_AN_SD25_TX_ENA_0    V_AN_SD25_TX_ENA_0(1U)
77290 
77291 #define S_AN_SD25_RX_ENA_7    7
77292 #define V_AN_SD25_RX_ENA_7(x) ((x) << S_AN_SD25_RX_ENA_7)
77293 #define F_AN_SD25_RX_ENA_7    V_AN_SD25_RX_ENA_7(1U)
77294 
77295 #define S_AN_SD25_RX_ENA_6    6
77296 #define V_AN_SD25_RX_ENA_6(x) ((x) << S_AN_SD25_RX_ENA_6)
77297 #define F_AN_SD25_RX_ENA_6    V_AN_SD25_RX_ENA_6(1U)
77298 
77299 #define S_AN_SD25_RX_ENA_5    5
77300 #define V_AN_SD25_RX_ENA_5(x) ((x) << S_AN_SD25_RX_ENA_5)
77301 #define F_AN_SD25_RX_ENA_5    V_AN_SD25_RX_ENA_5(1U)
77302 
77303 #define S_AN_SD25_RX_ENA_4    4
77304 #define V_AN_SD25_RX_ENA_4(x) ((x) << S_AN_SD25_RX_ENA_4)
77305 #define F_AN_SD25_RX_ENA_4    V_AN_SD25_RX_ENA_4(1U)
77306 
77307 #define S_AN_SD25_RX_ENA_3    3
77308 #define V_AN_SD25_RX_ENA_3(x) ((x) << S_AN_SD25_RX_ENA_3)
77309 #define F_AN_SD25_RX_ENA_3    V_AN_SD25_RX_ENA_3(1U)
77310 
77311 #define S_AN_SD25_RX_ENA_2    2
77312 #define V_AN_SD25_RX_ENA_2(x) ((x) << S_AN_SD25_RX_ENA_2)
77313 #define F_AN_SD25_RX_ENA_2    V_AN_SD25_RX_ENA_2(1U)
77314 
77315 #define S_AN_SD25_RX_ENA_1    1
77316 #define V_AN_SD25_RX_ENA_1(x) ((x) << S_AN_SD25_RX_ENA_1)
77317 #define F_AN_SD25_RX_ENA_1    V_AN_SD25_RX_ENA_1(1U)
77318 
77319 #define S_AN_SD25_RX_ENA_0    0
77320 #define V_AN_SD25_RX_ENA_0(x) ((x) << S_AN_SD25_RX_ENA_0)
77321 #define F_AN_SD25_RX_ENA_0    V_AN_SD25_RX_ENA_0(1U)
77322 
77323 #define A_MAC_PLL_CFG_0 0x380a0
77324 
77325 #define S_USE_RX_CDR_CLK_FOR_TX    7
77326 #define V_USE_RX_CDR_CLK_FOR_TX(x) ((x) << S_USE_RX_CDR_CLK_FOR_TX)
77327 #define F_USE_RX_CDR_CLK_FOR_TX    V_USE_RX_CDR_CLK_FOR_TX(1U)
77328 
77329 #define S_HSSPLLSEL0    5
77330 #define M_HSSPLLSEL0    0x3U
77331 #define V_HSSPLLSEL0(x) ((x) << S_HSSPLLSEL0)
77332 #define G_HSSPLLSEL0(x) (((x) >> S_HSSPLLSEL0) & M_HSSPLLSEL0)
77333 
77334 #define S_HSSTXDIV2CLK_SEL0    3
77335 #define M_HSSTXDIV2CLK_SEL0    0x3U
77336 #define V_HSSTXDIV2CLK_SEL0(x) ((x) << S_HSSTXDIV2CLK_SEL0)
77337 #define G_HSSTXDIV2CLK_SEL0(x) (((x) >> S_HSSTXDIV2CLK_SEL0) & M_HSSTXDIV2CLK_SEL0)
77338 
77339 #define S_HSS_RESET0    2
77340 #define V_HSS_RESET0(x) ((x) << S_HSS_RESET0)
77341 #define F_HSS_RESET0    V_HSS_RESET0(1U)
77342 
77343 #define S_APB_RESET0    1
77344 #define V_APB_RESET0(x) ((x) << S_APB_RESET0)
77345 #define F_APB_RESET0    V_APB_RESET0(1U)
77346 
77347 #define S_HSSCLK32DIV2_RESET0    0
77348 #define V_HSSCLK32DIV2_RESET0(x) ((x) << S_HSSCLK32DIV2_RESET0)
77349 #define F_HSSCLK32DIV2_RESET0    V_HSSCLK32DIV2_RESET0(1U)
77350 
77351 #define A_MAC_PLL_CFG_1 0x380a4
77352 
77353 #define S_HSSPLLSEL1    5
77354 #define M_HSSPLLSEL1    0x3U
77355 #define V_HSSPLLSEL1(x) ((x) << S_HSSPLLSEL1)
77356 #define G_HSSPLLSEL1(x) (((x) >> S_HSSPLLSEL1) & M_HSSPLLSEL1)
77357 
77358 #define S_HSSTXDIV2CLK_SEL1    3
77359 #define M_HSSTXDIV2CLK_SEL1    0x3U
77360 #define V_HSSTXDIV2CLK_SEL1(x) ((x) << S_HSSTXDIV2CLK_SEL1)
77361 #define G_HSSTXDIV2CLK_SEL1(x) (((x) >> S_HSSTXDIV2CLK_SEL1) & M_HSSTXDIV2CLK_SEL1)
77362 
77363 #define S_HSS_RESET1    2
77364 #define V_HSS_RESET1(x) ((x) << S_HSS_RESET1)
77365 #define F_HSS_RESET1    V_HSS_RESET1(1U)
77366 
77367 #define S_APB_RESET1    1
77368 #define V_APB_RESET1(x) ((x) << S_APB_RESET1)
77369 #define F_APB_RESET1    V_APB_RESET1(1U)
77370 
77371 #define S_HSSCLK32DIV2_RESET1    0
77372 #define V_HSSCLK32DIV2_RESET1(x) ((x) << S_HSSCLK32DIV2_RESET1)
77373 #define F_HSSCLK32DIV2_RESET1    V_HSSCLK32DIV2_RESET1(1U)
77374 
77375 #define A_MAC_PLL_CFG_2 0x380a8
77376 
77377 #define S_HSSPLLSEL2    5
77378 #define M_HSSPLLSEL2    0x3U
77379 #define V_HSSPLLSEL2(x) ((x) << S_HSSPLLSEL2)
77380 #define G_HSSPLLSEL2(x) (((x) >> S_HSSPLLSEL2) & M_HSSPLLSEL2)
77381 
77382 #define S_HSSTXDIV2CLK_SEL2    3
77383 #define M_HSSTXDIV2CLK_SEL2    0x3U
77384 #define V_HSSTXDIV2CLK_SEL2(x) ((x) << S_HSSTXDIV2CLK_SEL2)
77385 #define G_HSSTXDIV2CLK_SEL2(x) (((x) >> S_HSSTXDIV2CLK_SEL2) & M_HSSTXDIV2CLK_SEL2)
77386 
77387 #define S_HSS_RESET2    2
77388 #define V_HSS_RESET2(x) ((x) << S_HSS_RESET2)
77389 #define F_HSS_RESET2    V_HSS_RESET2(1U)
77390 
77391 #define S_APB_RESET2    1
77392 #define V_APB_RESET2(x) ((x) << S_APB_RESET2)
77393 #define F_APB_RESET2    V_APB_RESET2(1U)
77394 
77395 #define S_HSSCLK32DIV2_RESET2    0
77396 #define V_HSSCLK32DIV2_RESET2(x) ((x) << S_HSSCLK32DIV2_RESET2)
77397 #define F_HSSCLK32DIV2_RESET2    V_HSSCLK32DIV2_RESET2(1U)
77398 
77399 #define A_MAC_PLL_CFG_3 0x380ac
77400 
77401 #define S_HSSPLLSEL3    5
77402 #define M_HSSPLLSEL3    0x3U
77403 #define V_HSSPLLSEL3(x) ((x) << S_HSSPLLSEL3)
77404 #define G_HSSPLLSEL3(x) (((x) >> S_HSSPLLSEL3) & M_HSSPLLSEL3)
77405 
77406 #define S_HSSTXDIV2CLK_SEL3    3
77407 #define M_HSSTXDIV2CLK_SEL3    0x3U
77408 #define V_HSSTXDIV2CLK_SEL3(x) ((x) << S_HSSTXDIV2CLK_SEL3)
77409 #define G_HSSTXDIV2CLK_SEL3(x) (((x) >> S_HSSTXDIV2CLK_SEL3) & M_HSSTXDIV2CLK_SEL3)
77410 
77411 #define S_HSS_RESET3    2
77412 #define V_HSS_RESET3(x) ((x) << S_HSS_RESET3)
77413 #define F_HSS_RESET3    V_HSS_RESET3(1U)
77414 
77415 #define S_APB_RESET3    1
77416 #define V_APB_RESET3(x) ((x) << S_APB_RESET3)
77417 #define F_APB_RESET3    V_APB_RESET3(1U)
77418 
77419 #define S_HSSCLK32DIV2_RESET3    0
77420 #define V_HSSCLK32DIV2_RESET3(x) ((x) << S_HSSCLK32DIV2_RESET3)
77421 #define F_HSSCLK32DIV2_RESET3    V_HSSCLK32DIV2_RESET3(1U)
77422 
77423 #define A_MAC_HSS_STATUS 0x380b0
77424 
77425 #define S_TX_LANE_PLL_SEL_3    30
77426 #define M_TX_LANE_PLL_SEL_3    0x3U
77427 #define V_TX_LANE_PLL_SEL_3(x) ((x) << S_TX_LANE_PLL_SEL_3)
77428 #define G_TX_LANE_PLL_SEL_3(x) (((x) >> S_TX_LANE_PLL_SEL_3) & M_TX_LANE_PLL_SEL_3)
77429 
77430 #define S_TX_LANE_PLL_SEL_2    28
77431 #define M_TX_LANE_PLL_SEL_2    0x3U
77432 #define V_TX_LANE_PLL_SEL_2(x) ((x) << S_TX_LANE_PLL_SEL_2)
77433 #define G_TX_LANE_PLL_SEL_2(x) (((x) >> S_TX_LANE_PLL_SEL_2) & M_TX_LANE_PLL_SEL_2)
77434 
77435 #define S_TX_LANE_PLL_SEL_1    26
77436 #define M_TX_LANE_PLL_SEL_1    0x3U
77437 #define V_TX_LANE_PLL_SEL_1(x) ((x) << S_TX_LANE_PLL_SEL_1)
77438 #define G_TX_LANE_PLL_SEL_1(x) (((x) >> S_TX_LANE_PLL_SEL_1) & M_TX_LANE_PLL_SEL_1)
77439 
77440 #define S_TX_LANE_PLL_SEL_0    24
77441 #define M_TX_LANE_PLL_SEL_0    0x3U
77442 #define V_TX_LANE_PLL_SEL_0(x) ((x) << S_TX_LANE_PLL_SEL_0)
77443 #define G_TX_LANE_PLL_SEL_0(x) (((x) >> S_TX_LANE_PLL_SEL_0) & M_TX_LANE_PLL_SEL_0)
77444 
77445 #define S_HSSPLLLOCKB_HSS3    7
77446 #define V_HSSPLLLOCKB_HSS3(x) ((x) << S_HSSPLLLOCKB_HSS3)
77447 #define F_HSSPLLLOCKB_HSS3    V_HSSPLLLOCKB_HSS3(1U)
77448 
77449 #define S_HSSPLLLOCKA_HSS3    6
77450 #define V_HSSPLLLOCKA_HSS3(x) ((x) << S_HSSPLLLOCKA_HSS3)
77451 #define F_HSSPLLLOCKA_HSS3    V_HSSPLLLOCKA_HSS3(1U)
77452 
77453 #define S_HSSPLLLOCKB_HSS2    5
77454 #define V_HSSPLLLOCKB_HSS2(x) ((x) << S_HSSPLLLOCKB_HSS2)
77455 #define F_HSSPLLLOCKB_HSS2    V_HSSPLLLOCKB_HSS2(1U)
77456 
77457 #define S_HSSPLLLOCKA_HSS2    4
77458 #define V_HSSPLLLOCKA_HSS2(x) ((x) << S_HSSPLLLOCKA_HSS2)
77459 #define F_HSSPLLLOCKA_HSS2    V_HSSPLLLOCKA_HSS2(1U)
77460 
77461 #define S_HSSPLLLOCKB_HSS1    3
77462 #define V_HSSPLLLOCKB_HSS1(x) ((x) << S_HSSPLLLOCKB_HSS1)
77463 #define F_HSSPLLLOCKB_HSS1    V_HSSPLLLOCKB_HSS1(1U)
77464 
77465 #define S_HSSPLLLOCKA_HSS1    2
77466 #define V_HSSPLLLOCKA_HSS1(x) ((x) << S_HSSPLLLOCKA_HSS1)
77467 #define F_HSSPLLLOCKA_HSS1    V_HSSPLLLOCKA_HSS1(1U)
77468 
77469 #define S_HSSPLLLOCKB_HSS0    1
77470 #define V_HSSPLLLOCKB_HSS0(x) ((x) << S_HSSPLLLOCKB_HSS0)
77471 #define F_HSSPLLLOCKB_HSS0    V_HSSPLLLOCKB_HSS0(1U)
77472 
77473 #define S_HSSPLLLOCKA_HSS0    0
77474 #define V_HSSPLLLOCKA_HSS0(x) ((x) << S_HSSPLLLOCKA_HSS0)
77475 #define F_HSSPLLLOCKA_HSS0    V_HSSPLLLOCKA_HSS0(1U)
77476 
77477 #define A_MAC_HSS_SIGDET_STATUS 0x380b4
77478 
77479 #define S_HSS3_SIGDET    6
77480 #define M_HSS3_SIGDET    0x3U
77481 #define V_HSS3_SIGDET(x) ((x) << S_HSS3_SIGDET)
77482 #define G_HSS3_SIGDET(x) (((x) >> S_HSS3_SIGDET) & M_HSS3_SIGDET)
77483 
77484 #define S_HSS2_SIGDET    4
77485 #define M_HSS2_SIGDET    0x3U
77486 #define V_HSS2_SIGDET(x) ((x) << S_HSS2_SIGDET)
77487 #define G_HSS2_SIGDET(x) (((x) >> S_HSS2_SIGDET) & M_HSS2_SIGDET)
77488 
77489 #define S_HSS1_SIGDET    2
77490 #define M_HSS1_SIGDET    0x3U
77491 #define V_HSS1_SIGDET(x) ((x) << S_HSS1_SIGDET)
77492 #define G_HSS1_SIGDET(x) (((x) >> S_HSS1_SIGDET) & M_HSS1_SIGDET)
77493 
77494 #define S_HSS0_SIGDET    0
77495 #define M_HSS0_SIGDET    0x3U
77496 #define V_HSS0_SIGDET(x) ((x) << S_HSS0_SIGDET)
77497 #define G_HSS0_SIGDET(x) (((x) >> S_HSS0_SIGDET) & M_HSS0_SIGDET)
77498 
77499 #define A_MAC_FPGA_CFG_0 0x380b8
77500 #define A_MAC_PMD_STATUS 0x380bc
77501 
77502 #define S_SIGNAL_DETECT    0
77503 #define M_SIGNAL_DETECT    0xffU
77504 #define V_SIGNAL_DETECT(x) ((x) << S_SIGNAL_DETECT)
77505 #define G_SIGNAL_DETECT(x) (((x) >> S_SIGNAL_DETECT) & M_SIGNAL_DETECT)
77506 
77507 #define A_MAC_PMD_AN_CONFIG0 0x380c0
77508 
77509 #define S_AN3_RATE_SELECT    25
77510 #define M_AN3_RATE_SELECT    0x1fU
77511 #define V_AN3_RATE_SELECT(x) ((x) << S_AN3_RATE_SELECT)
77512 #define G_AN3_RATE_SELECT(x) (((x) >> S_AN3_RATE_SELECT) & M_AN3_RATE_SELECT)
77513 
77514 #define S_AN3_STATUS    24
77515 #define V_AN3_STATUS(x) ((x) << S_AN3_STATUS)
77516 #define F_AN3_STATUS    V_AN3_STATUS(1U)
77517 
77518 #define S_AN2_RATE_SELECT    17
77519 #define M_AN2_RATE_SELECT    0x1fU
77520 #define V_AN2_RATE_SELECT(x) ((x) << S_AN2_RATE_SELECT)
77521 #define G_AN2_RATE_SELECT(x) (((x) >> S_AN2_RATE_SELECT) & M_AN2_RATE_SELECT)
77522 
77523 #define S_AN2_STATUS    16
77524 #define V_AN2_STATUS(x) ((x) << S_AN2_STATUS)
77525 #define F_AN2_STATUS    V_AN2_STATUS(1U)
77526 
77527 #define S_AN1_RATE_SELECT    9
77528 #define M_AN1_RATE_SELECT    0x1fU
77529 #define V_AN1_RATE_SELECT(x) ((x) << S_AN1_RATE_SELECT)
77530 #define G_AN1_RATE_SELECT(x) (((x) >> S_AN1_RATE_SELECT) & M_AN1_RATE_SELECT)
77531 
77532 #define S_AN1_STATUS    8
77533 #define V_AN1_STATUS(x) ((x) << S_AN1_STATUS)
77534 #define F_AN1_STATUS    V_AN1_STATUS(1U)
77535 
77536 #define S_AN0_RATE_SELECT    1
77537 #define M_AN0_RATE_SELECT    0x1fU
77538 #define V_AN0_RATE_SELECT(x) ((x) << S_AN0_RATE_SELECT)
77539 #define G_AN0_RATE_SELECT(x) (((x) >> S_AN0_RATE_SELECT) & M_AN0_RATE_SELECT)
77540 
77541 #define S_AN0_STATUS    0
77542 #define V_AN0_STATUS(x) ((x) << S_AN0_STATUS)
77543 #define F_AN0_STATUS    V_AN0_STATUS(1U)
77544 
77545 #define A_MAC_PMD_AN_CONFIG1 0x380c4
77546 
77547 #define S_AN7_RATE_SELECT    25
77548 #define M_AN7_RATE_SELECT    0x1fU
77549 #define V_AN7_RATE_SELECT(x) ((x) << S_AN7_RATE_SELECT)
77550 #define G_AN7_RATE_SELECT(x) (((x) >> S_AN7_RATE_SELECT) & M_AN7_RATE_SELECT)
77551 
77552 #define S_AN7_STATUS    24
77553 #define V_AN7_STATUS(x) ((x) << S_AN7_STATUS)
77554 #define F_AN7_STATUS    V_AN7_STATUS(1U)
77555 
77556 #define S_AN6_RATE_SELECT    17
77557 #define M_AN6_RATE_SELECT    0x1fU
77558 #define V_AN6_RATE_SELECT(x) ((x) << S_AN6_RATE_SELECT)
77559 #define G_AN6_RATE_SELECT(x) (((x) >> S_AN6_RATE_SELECT) & M_AN6_RATE_SELECT)
77560 
77561 #define S_AN6_STATUS    16
77562 #define V_AN6_STATUS(x) ((x) << S_AN6_STATUS)
77563 #define F_AN6_STATUS    V_AN6_STATUS(1U)
77564 
77565 #define S_AN5_RATE_SELECT    9
77566 #define M_AN5_RATE_SELECT    0x1fU
77567 #define V_AN5_RATE_SELECT(x) ((x) << S_AN5_RATE_SELECT)
77568 #define G_AN5_RATE_SELECT(x) (((x) >> S_AN5_RATE_SELECT) & M_AN5_RATE_SELECT)
77569 
77570 #define S_AN5_STATUS    8
77571 #define V_AN5_STATUS(x) ((x) << S_AN5_STATUS)
77572 #define F_AN5_STATUS    V_AN5_STATUS(1U)
77573 
77574 #define S_AN4_RATE_SELECT    1
77575 #define M_AN4_RATE_SELECT    0x1fU
77576 #define V_AN4_RATE_SELECT(x) ((x) << S_AN4_RATE_SELECT)
77577 #define G_AN4_RATE_SELECT(x) (((x) >> S_AN4_RATE_SELECT) & M_AN4_RATE_SELECT)
77578 
77579 #define S_AN4_STATUS    0
77580 #define V_AN4_STATUS(x) ((x) << S_AN4_STATUS)
77581 #define F_AN4_STATUS    V_AN4_STATUS(1U)
77582 
77583 #define A_MAC_INT_EN_CMN 0x380c8
77584 
77585 #define S_HSS3PLL1_LOCK_LOST_INT_EN    21
77586 #define V_HSS3PLL1_LOCK_LOST_INT_EN(x) ((x) << S_HSS3PLL1_LOCK_LOST_INT_EN)
77587 #define F_HSS3PLL1_LOCK_LOST_INT_EN    V_HSS3PLL1_LOCK_LOST_INT_EN(1U)
77588 
77589 #define S_HSS3PLL1_LOCK_INT_EN    20
77590 #define V_HSS3PLL1_LOCK_INT_EN(x) ((x) << S_HSS3PLL1_LOCK_INT_EN)
77591 #define F_HSS3PLL1_LOCK_INT_EN    V_HSS3PLL1_LOCK_INT_EN(1U)
77592 
77593 #define S_HSS3PLL0_LOCK_LOST_INT_EN    19
77594 #define V_HSS3PLL0_LOCK_LOST_INT_EN(x) ((x) << S_HSS3PLL0_LOCK_LOST_INT_EN)
77595 #define F_HSS3PLL0_LOCK_LOST_INT_EN    V_HSS3PLL0_LOCK_LOST_INT_EN(1U)
77596 
77597 #define S_HSS3PLL0_LOCK_INT_EN    18
77598 #define V_HSS3PLL0_LOCK_INT_EN(x) ((x) << S_HSS3PLL0_LOCK_INT_EN)
77599 #define F_HSS3PLL0_LOCK_INT_EN    V_HSS3PLL0_LOCK_INT_EN(1U)
77600 
77601 #define S_HSS2PLL1_LOCK_LOST_INT_EN    17
77602 #define V_HSS2PLL1_LOCK_LOST_INT_EN(x) ((x) << S_HSS2PLL1_LOCK_LOST_INT_EN)
77603 #define F_HSS2PLL1_LOCK_LOST_INT_EN    V_HSS2PLL1_LOCK_LOST_INT_EN(1U)
77604 
77605 #define S_HSS2PLL1_LOCK_INT_EN    16
77606 #define V_HSS2PLL1_LOCK_INT_EN(x) ((x) << S_HSS2PLL1_LOCK_INT_EN)
77607 #define F_HSS2PLL1_LOCK_INT_EN    V_HSS2PLL1_LOCK_INT_EN(1U)
77608 
77609 #define S_HSS2PLL0_LOCK_LOST_INT_EN    15
77610 #define V_HSS2PLL0_LOCK_LOST_INT_EN(x) ((x) << S_HSS2PLL0_LOCK_LOST_INT_EN)
77611 #define F_HSS2PLL0_LOCK_LOST_INT_EN    V_HSS2PLL0_LOCK_LOST_INT_EN(1U)
77612 
77613 #define S_HSS2PLL0_LOCK_INT_EN    14
77614 #define V_HSS2PLL0_LOCK_INT_EN(x) ((x) << S_HSS2PLL0_LOCK_INT_EN)
77615 #define F_HSS2PLL0_LOCK_INT_EN    V_HSS2PLL0_LOCK_INT_EN(1U)
77616 
77617 #define S_HSS1PLL1_LOCK_LOST_INT_EN    13
77618 #define V_HSS1PLL1_LOCK_LOST_INT_EN(x) ((x) << S_HSS1PLL1_LOCK_LOST_INT_EN)
77619 #define F_HSS1PLL1_LOCK_LOST_INT_EN    V_HSS1PLL1_LOCK_LOST_INT_EN(1U)
77620 
77621 #define S_HSS1PLL1_LOCK_INT_EN    12
77622 #define V_HSS1PLL1_LOCK_INT_EN(x) ((x) << S_HSS1PLL1_LOCK_INT_EN)
77623 #define F_HSS1PLL1_LOCK_INT_EN    V_HSS1PLL1_LOCK_INT_EN(1U)
77624 
77625 #define S_HSS1PLL0_LOCK_LOST_INT_EN    11
77626 #define V_HSS1PLL0_LOCK_LOST_INT_EN(x) ((x) << S_HSS1PLL0_LOCK_LOST_INT_EN)
77627 #define F_HSS1PLL0_LOCK_LOST_INT_EN    V_HSS1PLL0_LOCK_LOST_INT_EN(1U)
77628 
77629 #define S_HSS1PLL0_LOCK_INT_EN    10
77630 #define V_HSS1PLL0_LOCK_INT_EN(x) ((x) << S_HSS1PLL0_LOCK_INT_EN)
77631 #define F_HSS1PLL0_LOCK_INT_EN    V_HSS1PLL0_LOCK_INT_EN(1U)
77632 
77633 #define S_HSS0PLL1_LOCK_LOST_INT_EN    9
77634 #define V_HSS0PLL1_LOCK_LOST_INT_EN(x) ((x) << S_HSS0PLL1_LOCK_LOST_INT_EN)
77635 #define F_HSS0PLL1_LOCK_LOST_INT_EN    V_HSS0PLL1_LOCK_LOST_INT_EN(1U)
77636 
77637 #define S_HSS0PLL1_LOCK_INT_EN    8
77638 #define V_HSS0PLL1_LOCK_INT_EN(x) ((x) << S_HSS0PLL1_LOCK_INT_EN)
77639 #define F_HSS0PLL1_LOCK_INT_EN    V_HSS0PLL1_LOCK_INT_EN(1U)
77640 
77641 #define S_HSS0PLL0_LOCK_LOST_INT_EN    7
77642 #define V_HSS0PLL0_LOCK_LOST_INT_EN(x) ((x) << S_HSS0PLL0_LOCK_LOST_INT_EN)
77643 #define F_HSS0PLL0_LOCK_LOST_INT_EN    V_HSS0PLL0_LOCK_LOST_INT_EN(1U)
77644 
77645 #define S_HSS0PLL0_LOCK_INT_EN    6
77646 #define V_HSS0PLL0_LOCK_INT_EN(x) ((x) << S_HSS0PLL0_LOCK_INT_EN)
77647 #define F_HSS0PLL0_LOCK_INT_EN    V_HSS0PLL0_LOCK_INT_EN(1U)
77648 
77649 #define S_FLOCK_ASSERTED    5
77650 #define V_FLOCK_ASSERTED(x) ((x) << S_FLOCK_ASSERTED)
77651 #define F_FLOCK_ASSERTED    V_FLOCK_ASSERTED(1U)
77652 
77653 #define S_FLOCK_LOST    4
77654 #define V_FLOCK_LOST(x) ((x) << S_FLOCK_LOST)
77655 #define F_FLOCK_LOST    V_FLOCK_LOST(1U)
77656 
77657 #define S_PHASE_LOCK_ASSERTED    3
77658 #define V_PHASE_LOCK_ASSERTED(x) ((x) << S_PHASE_LOCK_ASSERTED)
77659 #define F_PHASE_LOCK_ASSERTED    V_PHASE_LOCK_ASSERTED(1U)
77660 
77661 #define S_PHASE_LOCK_LOST    2
77662 #define V_PHASE_LOCK_LOST(x) ((x) << S_PHASE_LOCK_LOST)
77663 #define F_PHASE_LOCK_LOST    V_PHASE_LOCK_LOST(1U)
77664 
77665 #define S_LOCK_ASSERTED    1
77666 #define V_LOCK_ASSERTED(x) ((x) << S_LOCK_ASSERTED)
77667 #define F_LOCK_ASSERTED    V_LOCK_ASSERTED(1U)
77668 
77669 #define S_LOCK_LOST    0
77670 #define V_LOCK_LOST(x) ((x) << S_LOCK_LOST)
77671 #define F_LOCK_LOST    V_LOCK_LOST(1U)
77672 
77673 #define A_MAC_INT_CAUSE_CMN 0x380cc
77674 
77675 #define S_HSS3PLL1_LOCK_LOST_INT_CAUSE    21
77676 #define V_HSS3PLL1_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS3PLL1_LOCK_LOST_INT_CAUSE)
77677 #define F_HSS3PLL1_LOCK_LOST_INT_CAUSE    V_HSS3PLL1_LOCK_LOST_INT_CAUSE(1U)
77678 
77679 #define S_HSS3PLL1_LOCK_INT_CAUSE    20
77680 #define V_HSS3PLL1_LOCK_INT_CAUSE(x) ((x) << S_HSS3PLL1_LOCK_INT_CAUSE)
77681 #define F_HSS3PLL1_LOCK_INT_CAUSE    V_HSS3PLL1_LOCK_INT_CAUSE(1U)
77682 
77683 #define S_HSS3PLL0_LOCK_LOST_INT_CAUSE    19
77684 #define V_HSS3PLL0_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS3PLL0_LOCK_LOST_INT_CAUSE)
77685 #define F_HSS3PLL0_LOCK_LOST_INT_CAUSE    V_HSS3PLL0_LOCK_LOST_INT_CAUSE(1U)
77686 
77687 #define S_HSS3PLL0_LOCK_INT_CAUSE    18
77688 #define V_HSS3PLL0_LOCK_INT_CAUSE(x) ((x) << S_HSS3PLL0_LOCK_INT_CAUSE)
77689 #define F_HSS3PLL0_LOCK_INT_CAUSE    V_HSS3PLL0_LOCK_INT_CAUSE(1U)
77690 
77691 #define S_HSS2PLL1_LOCK_LOST_CAUSE    17
77692 #define V_HSS2PLL1_LOCK_LOST_CAUSE(x) ((x) << S_HSS2PLL1_LOCK_LOST_CAUSE)
77693 #define F_HSS2PLL1_LOCK_LOST_CAUSE    V_HSS2PLL1_LOCK_LOST_CAUSE(1U)
77694 
77695 #define S_HSS2PLL1_LOCK_INT_CAUSE    16
77696 #define V_HSS2PLL1_LOCK_INT_CAUSE(x) ((x) << S_HSS2PLL1_LOCK_INT_CAUSE)
77697 #define F_HSS2PLL1_LOCK_INT_CAUSE    V_HSS2PLL1_LOCK_INT_CAUSE(1U)
77698 
77699 #define S_HSS2PLL0_LOCK_LOST_INT_CAUSE    15
77700 #define V_HSS2PLL0_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS2PLL0_LOCK_LOST_INT_CAUSE)
77701 #define F_HSS2PLL0_LOCK_LOST_INT_CAUSE    V_HSS2PLL0_LOCK_LOST_INT_CAUSE(1U)
77702 
77703 #define S_HSS2PLL0_LOCK_INT_CAUSE    14
77704 #define V_HSS2PLL0_LOCK_INT_CAUSE(x) ((x) << S_HSS2PLL0_LOCK_INT_CAUSE)
77705 #define F_HSS2PLL0_LOCK_INT_CAUSE    V_HSS2PLL0_LOCK_INT_CAUSE(1U)
77706 
77707 #define S_HSS1PLL1_LOCK_LOST_INT_CAUSE    13
77708 #define V_HSS1PLL1_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS1PLL1_LOCK_LOST_INT_CAUSE)
77709 #define F_HSS1PLL1_LOCK_LOST_INT_CAUSE    V_HSS1PLL1_LOCK_LOST_INT_CAUSE(1U)
77710 
77711 #define S_HSS1PLL1_LOCK_INT_CAUSE    12
77712 #define V_HSS1PLL1_LOCK_INT_CAUSE(x) ((x) << S_HSS1PLL1_LOCK_INT_CAUSE)
77713 #define F_HSS1PLL1_LOCK_INT_CAUSE    V_HSS1PLL1_LOCK_INT_CAUSE(1U)
77714 
77715 #define S_HSS1PLL0_LOCK_LOST_INT_CAUSE    11
77716 #define V_HSS1PLL0_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS1PLL0_LOCK_LOST_INT_CAUSE)
77717 #define F_HSS1PLL0_LOCK_LOST_INT_CAUSE    V_HSS1PLL0_LOCK_LOST_INT_CAUSE(1U)
77718 
77719 #define S_HSS1PLL0_LOCK_INT_CAUSE    10
77720 #define V_HSS1PLL0_LOCK_INT_CAUSE(x) ((x) << S_HSS1PLL0_LOCK_INT_CAUSE)
77721 #define F_HSS1PLL0_LOCK_INT_CAUSE    V_HSS1PLL0_LOCK_INT_CAUSE(1U)
77722 
77723 #define S_HSS0PLL1_LOCK_LOST_INT_CAUSE    9
77724 #define V_HSS0PLL1_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS0PLL1_LOCK_LOST_INT_CAUSE)
77725 #define F_HSS0PLL1_LOCK_LOST_INT_CAUSE    V_HSS0PLL1_LOCK_LOST_INT_CAUSE(1U)
77726 
77727 #define S_HSS0PLL1_LOCK_INT_CAUSE    8
77728 #define V_HSS0PLL1_LOCK_INT_CAUSE(x) ((x) << S_HSS0PLL1_LOCK_INT_CAUSE)
77729 #define F_HSS0PLL1_LOCK_INT_CAUSE    V_HSS0PLL1_LOCK_INT_CAUSE(1U)
77730 
77731 #define S_HSS0PLL0_LOCK_LOST_INT_CAUSE    7
77732 #define V_HSS0PLL0_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS0PLL0_LOCK_LOST_INT_CAUSE)
77733 #define F_HSS0PLL0_LOCK_LOST_INT_CAUSE    V_HSS0PLL0_LOCK_LOST_INT_CAUSE(1U)
77734 
77735 #define S_HSS0PLL0_LOCK_INT_CAUSE    6
77736 #define V_HSS0PLL0_LOCK_INT_CAUSE(x) ((x) << S_HSS0PLL0_LOCK_INT_CAUSE)
77737 #define F_HSS0PLL0_LOCK_INT_CAUSE    V_HSS0PLL0_LOCK_INT_CAUSE(1U)
77738 
77739 #define A_MAC_PERR_INT_EN_MTIP 0x380d0
77740 
77741 #define S_PERR_MAC0_TX    19
77742 #define V_PERR_MAC0_TX(x) ((x) << S_PERR_MAC0_TX)
77743 #define F_PERR_MAC0_TX    V_PERR_MAC0_TX(1U)
77744 
77745 #define S_PERR_MAC1_TX    18
77746 #define V_PERR_MAC1_TX(x) ((x) << S_PERR_MAC1_TX)
77747 #define F_PERR_MAC1_TX    V_PERR_MAC1_TX(1U)
77748 
77749 #define S_PERR_MAC2_TX    17
77750 #define V_PERR_MAC2_TX(x) ((x) << S_PERR_MAC2_TX)
77751 #define F_PERR_MAC2_TX    V_PERR_MAC2_TX(1U)
77752 
77753 #define S_PERR_MAC3_TX    16
77754 #define V_PERR_MAC3_TX(x) ((x) << S_PERR_MAC3_TX)
77755 #define F_PERR_MAC3_TX    V_PERR_MAC3_TX(1U)
77756 
77757 #define S_PERR_MAC4_TX    15
77758 #define V_PERR_MAC4_TX(x) ((x) << S_PERR_MAC4_TX)
77759 #define F_PERR_MAC4_TX    V_PERR_MAC4_TX(1U)
77760 
77761 #define S_PERR_MAC5_TX    14
77762 #define V_PERR_MAC5_TX(x) ((x) << S_PERR_MAC5_TX)
77763 #define F_PERR_MAC5_TX    V_PERR_MAC5_TX(1U)
77764 
77765 #define S_PERR_MAC0_RX    13
77766 #define V_PERR_MAC0_RX(x) ((x) << S_PERR_MAC0_RX)
77767 #define F_PERR_MAC0_RX    V_PERR_MAC0_RX(1U)
77768 
77769 #define S_PERR_MAC1_RX    12
77770 #define V_PERR_MAC1_RX(x) ((x) << S_PERR_MAC1_RX)
77771 #define F_PERR_MAC1_RX    V_PERR_MAC1_RX(1U)
77772 
77773 #define S_PERR_MAC2_RX    11
77774 #define V_PERR_MAC2_RX(x) ((x) << S_PERR_MAC2_RX)
77775 #define F_PERR_MAC2_RX    V_PERR_MAC2_RX(1U)
77776 
77777 #define S_PERR_MAC3_RX    10
77778 #define V_PERR_MAC3_RX(x) ((x) << S_PERR_MAC3_RX)
77779 #define F_PERR_MAC3_RX    V_PERR_MAC3_RX(1U)
77780 
77781 #define S_PERR_MAC4_RX    9
77782 #define V_PERR_MAC4_RX(x) ((x) << S_PERR_MAC4_RX)
77783 #define F_PERR_MAC4_RX    V_PERR_MAC4_RX(1U)
77784 
77785 #define S_PERR_MAC5_RX    8
77786 #define V_PERR_MAC5_RX(x) ((x) << S_PERR_MAC5_RX)
77787 #define F_PERR_MAC5_RX    V_PERR_MAC5_RX(1U)
77788 
77789 #define S_PERR_MAC_STAT2_RX    7
77790 #define V_PERR_MAC_STAT2_RX(x) ((x) << S_PERR_MAC_STAT2_RX)
77791 #define F_PERR_MAC_STAT2_RX    V_PERR_MAC_STAT2_RX(1U)
77792 
77793 #define S_PERR_MAC_STAT3_RX    6
77794 #define V_PERR_MAC_STAT3_RX(x) ((x) << S_PERR_MAC_STAT3_RX)
77795 #define F_PERR_MAC_STAT3_RX    V_PERR_MAC_STAT3_RX(1U)
77796 
77797 #define S_PERR_MAC_STAT4_RX    5
77798 #define V_PERR_MAC_STAT4_RX(x) ((x) << S_PERR_MAC_STAT4_RX)
77799 #define F_PERR_MAC_STAT4_RX    V_PERR_MAC_STAT4_RX(1U)
77800 
77801 #define S_PERR_MAC_STAT5_RX    4
77802 #define V_PERR_MAC_STAT5_RX(x) ((x) << S_PERR_MAC_STAT5_RX)
77803 #define F_PERR_MAC_STAT5_RX    V_PERR_MAC_STAT5_RX(1U)
77804 
77805 #define S_PERR_MAC_STAT2_TX    3
77806 #define V_PERR_MAC_STAT2_TX(x) ((x) << S_PERR_MAC_STAT2_TX)
77807 #define F_PERR_MAC_STAT2_TX    V_PERR_MAC_STAT2_TX(1U)
77808 
77809 #define S_PERR_MAC_STAT3_TX    2
77810 #define V_PERR_MAC_STAT3_TX(x) ((x) << S_PERR_MAC_STAT3_TX)
77811 #define F_PERR_MAC_STAT3_TX    V_PERR_MAC_STAT3_TX(1U)
77812 
77813 #define S_PERR_MAC_STAT4_TX    1
77814 #define V_PERR_MAC_STAT4_TX(x) ((x) << S_PERR_MAC_STAT4_TX)
77815 #define F_PERR_MAC_STAT4_TX    V_PERR_MAC_STAT4_TX(1U)
77816 
77817 #define S_PERR_MAC_STAT5_TX    0
77818 #define V_PERR_MAC_STAT5_TX(x) ((x) << S_PERR_MAC_STAT5_TX)
77819 #define F_PERR_MAC_STAT5_TX    V_PERR_MAC_STAT5_TX(1U)
77820 
77821 #define A_MAC_PERR_INT_CAUSE_MTIP 0x380d4
77822 
77823 #define S_PERR_MAC_STAT_RX    7
77824 #define V_PERR_MAC_STAT_RX(x) ((x) << S_PERR_MAC_STAT_RX)
77825 #define F_PERR_MAC_STAT_RX    V_PERR_MAC_STAT_RX(1U)
77826 
77827 #define S_PERR_MAC_STAT_TX    3
77828 #define V_PERR_MAC_STAT_TX(x) ((x) << S_PERR_MAC_STAT_TX)
77829 #define F_PERR_MAC_STAT_TX    V_PERR_MAC_STAT_TX(1U)
77830 
77831 #define S_PERR_MAC_STAT_CAP    2
77832 #define V_PERR_MAC_STAT_CAP(x) ((x) << S_PERR_MAC_STAT_CAP)
77833 #define F_PERR_MAC_STAT_CAP    V_PERR_MAC_STAT_CAP(1U)
77834 
77835 #define A_MAC_PERR_ENABLE_MTIP 0x380d8
77836 #define A_MAC_PCS_1G_CONFIG_0 0x380dc
77837 
77838 #define S_SEQ_ENA_3    19
77839 #define V_SEQ_ENA_3(x) ((x) << S_SEQ_ENA_3)
77840 #define F_SEQ_ENA_3    V_SEQ_ENA_3(1U)
77841 
77842 #define S_SEQ_ENA_2    18
77843 #define V_SEQ_ENA_2(x) ((x) << S_SEQ_ENA_2)
77844 #define F_SEQ_ENA_2    V_SEQ_ENA_2(1U)
77845 
77846 #define S_SEQ_ENA_1    17
77847 #define V_SEQ_ENA_1(x) ((x) << S_SEQ_ENA_1)
77848 #define F_SEQ_ENA_1    V_SEQ_ENA_1(1U)
77849 
77850 #define S_SEQ_ENA_0    16
77851 #define V_SEQ_ENA_0(x) ((x) << S_SEQ_ENA_0)
77852 #define F_SEQ_ENA_0    V_SEQ_ENA_0(1U)
77853 
77854 #define S_TX_LANE_THRESH_3    12
77855 #define M_TX_LANE_THRESH_3    0xfU
77856 #define V_TX_LANE_THRESH_3(x) ((x) << S_TX_LANE_THRESH_3)
77857 #define G_TX_LANE_THRESH_3(x) (((x) >> S_TX_LANE_THRESH_3) & M_TX_LANE_THRESH_3)
77858 
77859 #define S_TX_LANE_THRESH_2    8
77860 #define M_TX_LANE_THRESH_2    0xfU
77861 #define V_TX_LANE_THRESH_2(x) ((x) << S_TX_LANE_THRESH_2)
77862 #define G_TX_LANE_THRESH_2(x) (((x) >> S_TX_LANE_THRESH_2) & M_TX_LANE_THRESH_2)
77863 
77864 #define S_TX_LANE_THRESH_1    4
77865 #define M_TX_LANE_THRESH_1    0xfU
77866 #define V_TX_LANE_THRESH_1(x) ((x) << S_TX_LANE_THRESH_1)
77867 #define G_TX_LANE_THRESH_1(x) (((x) >> S_TX_LANE_THRESH_1) & M_TX_LANE_THRESH_1)
77868 
77869 #define S_TX_LANE_THRESH_0    0
77870 #define M_TX_LANE_THRESH_0    0xfU
77871 #define V_TX_LANE_THRESH_0(x) ((x) << S_TX_LANE_THRESH_0)
77872 #define G_TX_LANE_THRESH_0(x) (((x) >> S_TX_LANE_THRESH_0) & M_TX_LANE_THRESH_0)
77873 
77874 #define A_MAC_PCS_1G_CONFIG_1 0x380e0
77875 
77876 #define S_TX_LANE_CKMULT_3    9
77877 #define M_TX_LANE_CKMULT_3    0x7U
77878 #define V_TX_LANE_CKMULT_3(x) ((x) << S_TX_LANE_CKMULT_3)
77879 #define G_TX_LANE_CKMULT_3(x) (((x) >> S_TX_LANE_CKMULT_3) & M_TX_LANE_CKMULT_3)
77880 
77881 #define S_TX_LANE_CKMULT_2    6
77882 #define M_TX_LANE_CKMULT_2    0x7U
77883 #define V_TX_LANE_CKMULT_2(x) ((x) << S_TX_LANE_CKMULT_2)
77884 #define G_TX_LANE_CKMULT_2(x) (((x) >> S_TX_LANE_CKMULT_2) & M_TX_LANE_CKMULT_2)
77885 
77886 #define S_TX_LANE_CKMULT_1    3
77887 #define M_TX_LANE_CKMULT_1    0x7U
77888 #define V_TX_LANE_CKMULT_1(x) ((x) << S_TX_LANE_CKMULT_1)
77889 #define G_TX_LANE_CKMULT_1(x) (((x) >> S_TX_LANE_CKMULT_1) & M_TX_LANE_CKMULT_1)
77890 
77891 #define S_TX_LANE_CKMULT_0    0
77892 #define M_TX_LANE_CKMULT_0    0x7U
77893 #define V_TX_LANE_CKMULT_0(x) ((x) << S_TX_LANE_CKMULT_0)
77894 #define G_TX_LANE_CKMULT_0(x) (((x) >> S_TX_LANE_CKMULT_0) & M_TX_LANE_CKMULT_0)
77895 
77896 #define A_MAC_PTP_TIMER_RD0_LO 0x380e4
77897 #define A_MAC_PTP_TIMER_RD0_HI 0x380e8
77898 #define A_MAC_PTP_TIMER_RD1_LO 0x380ec
77899 #define A_MAC_PTP_TIMER_RD1_HI 0x380f0
77900 #define A_MAC_PTP_TIMER_WR_LO 0x380f4
77901 #define A_MAC_PTP_TIMER_WR_HI 0x380f8
77902 #define A_MAC_PTP_TIMER_OFFSET_0 0x380fc
77903 #define A_MAC_PTP_TIMER_OFFSET_1 0x38100
77904 #define A_MAC_PTP_TIMER_OFFSET_2 0x38104
77905 #define A_MAC_PTP_SUM_LO 0x38108
77906 #define A_MAC_PTP_SUM_HI 0x3810c
77907 #define A_MAC_PTP_TIMER_INCR0 0x38110
77908 #define A_MAC_PTP_TIMER_INCR1 0x38114
77909 #define A_MAC_PTP_DRIFT_ADJUST_COUNT 0x38118
77910 #define A_MAC_PTP_OFFSET_ADJUST_FINE 0x3811c
77911 #define A_MAC_PTP_OFFSET_ADJUST_TOTAL 0x38120
77912 #define A_MAC_PTP_CFG 0x38124
77913 #define A_MAC_PTP_PPS 0x38128
77914 #define A_MAC_PTP_SINGLE_ALARM 0x3812c
77915 #define A_MAC_PTP_PERIODIC_ALARM 0x38130
77916 #define A_MAC_PTP_STATUS 0x38134
77917 #define A_MAC_STS_GPIO_SEL 0x38140
77918 
77919 #define S_STSOUTSEL    1
77920 #define V_STSOUTSEL(x) ((x) << S_STSOUTSEL)
77921 #define F_STSOUTSEL    V_STSOUTSEL(1U)
77922 
77923 #define S_STSINSEL    0
77924 #define V_STSINSEL(x) ((x) << S_STSINSEL)
77925 #define F_STSINSEL    V_STSINSEL(1U)
77926 
77927 #define A_MAC_CERR_INT_EN_MTIP 0x38150
77928 
77929 #define S_CERR_MAC0_TX    11
77930 #define V_CERR_MAC0_TX(x) ((x) << S_CERR_MAC0_TX)
77931 #define F_CERR_MAC0_TX    V_CERR_MAC0_TX(1U)
77932 
77933 #define S_CERR_MAC1_TX    10
77934 #define V_CERR_MAC1_TX(x) ((x) << S_CERR_MAC1_TX)
77935 #define F_CERR_MAC1_TX    V_CERR_MAC1_TX(1U)
77936 
77937 #define S_CERR_MAC2_TX    9
77938 #define V_CERR_MAC2_TX(x) ((x) << S_CERR_MAC2_TX)
77939 #define F_CERR_MAC2_TX    V_CERR_MAC2_TX(1U)
77940 
77941 #define S_CERR_MAC3_TX    8
77942 #define V_CERR_MAC3_TX(x) ((x) << S_CERR_MAC3_TX)
77943 #define F_CERR_MAC3_TX    V_CERR_MAC3_TX(1U)
77944 
77945 #define S_CERR_MAC4_TX    7
77946 #define V_CERR_MAC4_TX(x) ((x) << S_CERR_MAC4_TX)
77947 #define F_CERR_MAC4_TX    V_CERR_MAC4_TX(1U)
77948 
77949 #define S_CERR_MAC5_TX    6
77950 #define V_CERR_MAC5_TX(x) ((x) << S_CERR_MAC5_TX)
77951 #define F_CERR_MAC5_TX    V_CERR_MAC5_TX(1U)
77952 
77953 #define S_CERR_MAC0_RX    5
77954 #define V_CERR_MAC0_RX(x) ((x) << S_CERR_MAC0_RX)
77955 #define F_CERR_MAC0_RX    V_CERR_MAC0_RX(1U)
77956 
77957 #define S_CERR_MAC1_RX    4
77958 #define V_CERR_MAC1_RX(x) ((x) << S_CERR_MAC1_RX)
77959 #define F_CERR_MAC1_RX    V_CERR_MAC1_RX(1U)
77960 
77961 #define S_CERR_MAC2_RX    3
77962 #define V_CERR_MAC2_RX(x) ((x) << S_CERR_MAC2_RX)
77963 #define F_CERR_MAC2_RX    V_CERR_MAC2_RX(1U)
77964 
77965 #define S_CERR_MAC3_RX    2
77966 #define V_CERR_MAC3_RX(x) ((x) << S_CERR_MAC3_RX)
77967 #define F_CERR_MAC3_RX    V_CERR_MAC3_RX(1U)
77968 
77969 #define S_CERR_MAC4_RX    1
77970 #define V_CERR_MAC4_RX(x) ((x) << S_CERR_MAC4_RX)
77971 #define F_CERR_MAC4_RX    V_CERR_MAC4_RX(1U)
77972 
77973 #define S_CERR_MAC5_RX    0
77974 #define V_CERR_MAC5_RX(x) ((x) << S_CERR_MAC5_RX)
77975 #define F_CERR_MAC5_RX    V_CERR_MAC5_RX(1U)
77976 
77977 #define A_MAC_CERR_INT_CAUSE_MTIP 0x38154
77978 #define A_MAC_1G_PCS0_STATUS 0x38160
77979 
77980 #define S_1G_PCS0_LOOPBACK    12
77981 #define V_1G_PCS0_LOOPBACK(x) ((x) << S_1G_PCS0_LOOPBACK)
77982 #define F_1G_PCS0_LOOPBACK    V_1G_PCS0_LOOPBACK(1U)
77983 
77984 #define S_1G_PCS0_LINK_STATUS    11
77985 #define V_1G_PCS0_LINK_STATUS(x) ((x) << S_1G_PCS0_LINK_STATUS)
77986 #define F_1G_PCS0_LINK_STATUS    V_1G_PCS0_LINK_STATUS(1U)
77987 
77988 #define S_1G_PCS0_RX_SYNC    10
77989 #define V_1G_PCS0_RX_SYNC(x) ((x) << S_1G_PCS0_RX_SYNC)
77990 #define F_1G_PCS0_RX_SYNC    V_1G_PCS0_RX_SYNC(1U)
77991 
77992 #define S_1G_PCS0_AN_DONE    9
77993 #define V_1G_PCS0_AN_DONE(x) ((x) << S_1G_PCS0_AN_DONE)
77994 #define F_1G_PCS0_AN_DONE    V_1G_PCS0_AN_DONE(1U)
77995 
77996 #define S_1G_PCS0_PGRCVD    8
77997 #define V_1G_PCS0_PGRCVD(x) ((x) << S_1G_PCS0_PGRCVD)
77998 #define F_1G_PCS0_PGRCVD    V_1G_PCS0_PGRCVD(1U)
77999 
78000 #define S_1G_PCS0_SPEED_SEL    6
78001 #define M_1G_PCS0_SPEED_SEL    0x3U
78002 #define V_1G_PCS0_SPEED_SEL(x) ((x) << S_1G_PCS0_SPEED_SEL)
78003 #define G_1G_PCS0_SPEED_SEL(x) (((x) >> S_1G_PCS0_SPEED_SEL) & M_1G_PCS0_SPEED_SEL)
78004 
78005 #define S_1G_PCS0_HALF_DUPLEX    5
78006 #define V_1G_PCS0_HALF_DUPLEX(x) ((x) << S_1G_PCS0_HALF_DUPLEX)
78007 #define F_1G_PCS0_HALF_DUPLEX    V_1G_PCS0_HALF_DUPLEX(1U)
78008 
78009 #define S_1G_PCS0_TX_MODE_QUIET    4
78010 #define V_1G_PCS0_TX_MODE_QUIET(x) ((x) << S_1G_PCS0_TX_MODE_QUIET)
78011 #define F_1G_PCS0_TX_MODE_QUIET    V_1G_PCS0_TX_MODE_QUIET(1U)
78012 
78013 #define S_1G_PCS0_TX_LPI_ACTIVE    3
78014 #define V_1G_PCS0_TX_LPI_ACTIVE(x) ((x) << S_1G_PCS0_TX_LPI_ACTIVE)
78015 #define F_1G_PCS0_TX_LPI_ACTIVE    V_1G_PCS0_TX_LPI_ACTIVE(1U)
78016 
78017 #define S_1G_PCS0_RX_MODE_QUIET    2
78018 #define V_1G_PCS0_RX_MODE_QUIET(x) ((x) << S_1G_PCS0_RX_MODE_QUIET)
78019 #define F_1G_PCS0_RX_MODE_QUIET    V_1G_PCS0_RX_MODE_QUIET(1U)
78020 
78021 #define S_1G_PCS0_RX_LPI_ACTIVE    1
78022 #define V_1G_PCS0_RX_LPI_ACTIVE(x) ((x) << S_1G_PCS0_RX_LPI_ACTIVE)
78023 #define F_1G_PCS0_RX_LPI_ACTIVE    V_1G_PCS0_RX_LPI_ACTIVE(1U)
78024 
78025 #define S_1G_PCS0_RX_WAKE_ERR    0
78026 #define V_1G_PCS0_RX_WAKE_ERR(x) ((x) << S_1G_PCS0_RX_WAKE_ERR)
78027 #define F_1G_PCS0_RX_WAKE_ERR    V_1G_PCS0_RX_WAKE_ERR(1U)
78028 
78029 #define A_MAC_1G_PCS1_STATUS 0x38164
78030 
78031 #define S_1G_PCS1_LOOPBACK    12
78032 #define V_1G_PCS1_LOOPBACK(x) ((x) << S_1G_PCS1_LOOPBACK)
78033 #define F_1G_PCS1_LOOPBACK    V_1G_PCS1_LOOPBACK(1U)
78034 
78035 #define S_1G_PCS1_LINK_STATUS    11
78036 #define V_1G_PCS1_LINK_STATUS(x) ((x) << S_1G_PCS1_LINK_STATUS)
78037 #define F_1G_PCS1_LINK_STATUS    V_1G_PCS1_LINK_STATUS(1U)
78038 
78039 #define S_1G_PCS1_RX_SYNC    10
78040 #define V_1G_PCS1_RX_SYNC(x) ((x) << S_1G_PCS1_RX_SYNC)
78041 #define F_1G_PCS1_RX_SYNC    V_1G_PCS1_RX_SYNC(1U)
78042 
78043 #define S_1G_PCS1_AN_DONE    9
78044 #define V_1G_PCS1_AN_DONE(x) ((x) << S_1G_PCS1_AN_DONE)
78045 #define F_1G_PCS1_AN_DONE    V_1G_PCS1_AN_DONE(1U)
78046 
78047 #define S_1G_PCS1_PGRCVD    8
78048 #define V_1G_PCS1_PGRCVD(x) ((x) << S_1G_PCS1_PGRCVD)
78049 #define F_1G_PCS1_PGRCVD    V_1G_PCS1_PGRCVD(1U)
78050 
78051 #define S_1G_PCS1_SPEED_SEL    6
78052 #define M_1G_PCS1_SPEED_SEL    0x3U
78053 #define V_1G_PCS1_SPEED_SEL(x) ((x) << S_1G_PCS1_SPEED_SEL)
78054 #define G_1G_PCS1_SPEED_SEL(x) (((x) >> S_1G_PCS1_SPEED_SEL) & M_1G_PCS1_SPEED_SEL)
78055 
78056 #define S_1G_PCS1_HALF_DUPLEX    5
78057 #define V_1G_PCS1_HALF_DUPLEX(x) ((x) << S_1G_PCS1_HALF_DUPLEX)
78058 #define F_1G_PCS1_HALF_DUPLEX    V_1G_PCS1_HALF_DUPLEX(1U)
78059 
78060 #define S_1G_PCS1_TX_MODE_QUIET    4
78061 #define V_1G_PCS1_TX_MODE_QUIET(x) ((x) << S_1G_PCS1_TX_MODE_QUIET)
78062 #define F_1G_PCS1_TX_MODE_QUIET    V_1G_PCS1_TX_MODE_QUIET(1U)
78063 
78064 #define S_1G_PCS1_TX_LPI_ACTIVE    3
78065 #define V_1G_PCS1_TX_LPI_ACTIVE(x) ((x) << S_1G_PCS1_TX_LPI_ACTIVE)
78066 #define F_1G_PCS1_TX_LPI_ACTIVE    V_1G_PCS1_TX_LPI_ACTIVE(1U)
78067 
78068 #define S_1G_PCS1_RX_MODE_QUIET    2
78069 #define V_1G_PCS1_RX_MODE_QUIET(x) ((x) << S_1G_PCS1_RX_MODE_QUIET)
78070 #define F_1G_PCS1_RX_MODE_QUIET    V_1G_PCS1_RX_MODE_QUIET(1U)
78071 
78072 #define S_1G_PCS1_RX_LPI_ACTIVE    1
78073 #define V_1G_PCS1_RX_LPI_ACTIVE(x) ((x) << S_1G_PCS1_RX_LPI_ACTIVE)
78074 #define F_1G_PCS1_RX_LPI_ACTIVE    V_1G_PCS1_RX_LPI_ACTIVE(1U)
78075 
78076 #define S_1G_PCS1_RX_WAKE_ERR    0
78077 #define V_1G_PCS1_RX_WAKE_ERR(x) ((x) << S_1G_PCS1_RX_WAKE_ERR)
78078 #define F_1G_PCS1_RX_WAKE_ERR    V_1G_PCS1_RX_WAKE_ERR(1U)
78079 
78080 #define A_MAC_1G_PCS2_STATUS 0x38168
78081 
78082 #define S_1G_PCS2_LOOPBACK    12
78083 #define V_1G_PCS2_LOOPBACK(x) ((x) << S_1G_PCS2_LOOPBACK)
78084 #define F_1G_PCS2_LOOPBACK    V_1G_PCS2_LOOPBACK(1U)
78085 
78086 #define S_1G_PCS2_LINK_STATUS    11
78087 #define V_1G_PCS2_LINK_STATUS(x) ((x) << S_1G_PCS2_LINK_STATUS)
78088 #define F_1G_PCS2_LINK_STATUS    V_1G_PCS2_LINK_STATUS(1U)
78089 
78090 #define S_1G_PCS2_RX_SYNC    10
78091 #define V_1G_PCS2_RX_SYNC(x) ((x) << S_1G_PCS2_RX_SYNC)
78092 #define F_1G_PCS2_RX_SYNC    V_1G_PCS2_RX_SYNC(1U)
78093 
78094 #define S_1G_PCS2_AN_DONE    9
78095 #define V_1G_PCS2_AN_DONE(x) ((x) << S_1G_PCS2_AN_DONE)
78096 #define F_1G_PCS2_AN_DONE    V_1G_PCS2_AN_DONE(1U)
78097 
78098 #define S_1G_PCS2_PGRCVD    8
78099 #define V_1G_PCS2_PGRCVD(x) ((x) << S_1G_PCS2_PGRCVD)
78100 #define F_1G_PCS2_PGRCVD    V_1G_PCS2_PGRCVD(1U)
78101 
78102 #define S_1G_PCS2_SPEED_SEL    6
78103 #define M_1G_PCS2_SPEED_SEL    0x3U
78104 #define V_1G_PCS2_SPEED_SEL(x) ((x) << S_1G_PCS2_SPEED_SEL)
78105 #define G_1G_PCS2_SPEED_SEL(x) (((x) >> S_1G_PCS2_SPEED_SEL) & M_1G_PCS2_SPEED_SEL)
78106 
78107 #define S_1G_PCS2_HALF_DUPLEX    5
78108 #define V_1G_PCS2_HALF_DUPLEX(x) ((x) << S_1G_PCS2_HALF_DUPLEX)
78109 #define F_1G_PCS2_HALF_DUPLEX    V_1G_PCS2_HALF_DUPLEX(1U)
78110 
78111 #define S_1G_PCS2_TX_MODE_QUIET    4
78112 #define V_1G_PCS2_TX_MODE_QUIET(x) ((x) << S_1G_PCS2_TX_MODE_QUIET)
78113 #define F_1G_PCS2_TX_MODE_QUIET    V_1G_PCS2_TX_MODE_QUIET(1U)
78114 
78115 #define S_1G_PCS2_TX_LPI_ACTIVE    3
78116 #define V_1G_PCS2_TX_LPI_ACTIVE(x) ((x) << S_1G_PCS2_TX_LPI_ACTIVE)
78117 #define F_1G_PCS2_TX_LPI_ACTIVE    V_1G_PCS2_TX_LPI_ACTIVE(1U)
78118 
78119 #define S_1G_PCS2_RX_MODE_QUIET    2
78120 #define V_1G_PCS2_RX_MODE_QUIET(x) ((x) << S_1G_PCS2_RX_MODE_QUIET)
78121 #define F_1G_PCS2_RX_MODE_QUIET    V_1G_PCS2_RX_MODE_QUIET(1U)
78122 
78123 #define S_1G_PCS2_RX_LPI_ACTIVE    1
78124 #define V_1G_PCS2_RX_LPI_ACTIVE(x) ((x) << S_1G_PCS2_RX_LPI_ACTIVE)
78125 #define F_1G_PCS2_RX_LPI_ACTIVE    V_1G_PCS2_RX_LPI_ACTIVE(1U)
78126 
78127 #define S_1G_PCS2_RX_WAKE_ERR    0
78128 #define V_1G_PCS2_RX_WAKE_ERR(x) ((x) << S_1G_PCS2_RX_WAKE_ERR)
78129 #define F_1G_PCS2_RX_WAKE_ERR    V_1G_PCS2_RX_WAKE_ERR(1U)
78130 
78131 #define A_MAC_1G_PCS3_STATUS 0x3816c
78132 
78133 #define S_1G_PCS3_LOOPBACK    12
78134 #define V_1G_PCS3_LOOPBACK(x) ((x) << S_1G_PCS3_LOOPBACK)
78135 #define F_1G_PCS3_LOOPBACK    V_1G_PCS3_LOOPBACK(1U)
78136 
78137 #define S_1G_PCS3_LINK_STATUS    11
78138 #define V_1G_PCS3_LINK_STATUS(x) ((x) << S_1G_PCS3_LINK_STATUS)
78139 #define F_1G_PCS3_LINK_STATUS    V_1G_PCS3_LINK_STATUS(1U)
78140 
78141 #define S_1G_PCS3_RX_SYNC    10
78142 #define V_1G_PCS3_RX_SYNC(x) ((x) << S_1G_PCS3_RX_SYNC)
78143 #define F_1G_PCS3_RX_SYNC    V_1G_PCS3_RX_SYNC(1U)
78144 
78145 #define S_1G_PCS3_AN_DONE    9
78146 #define V_1G_PCS3_AN_DONE(x) ((x) << S_1G_PCS3_AN_DONE)
78147 #define F_1G_PCS3_AN_DONE    V_1G_PCS3_AN_DONE(1U)
78148 
78149 #define S_1G_PCS3_PGRCVD    8
78150 #define V_1G_PCS3_PGRCVD(x) ((x) << S_1G_PCS3_PGRCVD)
78151 #define F_1G_PCS3_PGRCVD    V_1G_PCS3_PGRCVD(1U)
78152 
78153 #define S_1G_PCS3_SPEED_SEL    6
78154 #define M_1G_PCS3_SPEED_SEL    0x3U
78155 #define V_1G_PCS3_SPEED_SEL(x) ((x) << S_1G_PCS3_SPEED_SEL)
78156 #define G_1G_PCS3_SPEED_SEL(x) (((x) >> S_1G_PCS3_SPEED_SEL) & M_1G_PCS3_SPEED_SEL)
78157 
78158 #define S_1G_PCS3_HALF_DUPLEX    5
78159 #define V_1G_PCS3_HALF_DUPLEX(x) ((x) << S_1G_PCS3_HALF_DUPLEX)
78160 #define F_1G_PCS3_HALF_DUPLEX    V_1G_PCS3_HALF_DUPLEX(1U)
78161 
78162 #define S_1G_PCS3_TX_MODE_QUIET    4
78163 #define V_1G_PCS3_TX_MODE_QUIET(x) ((x) << S_1G_PCS3_TX_MODE_QUIET)
78164 #define F_1G_PCS3_TX_MODE_QUIET    V_1G_PCS3_TX_MODE_QUIET(1U)
78165 
78166 #define S_1G_PCS3_TX_LPI_ACTIVE    3
78167 #define V_1G_PCS3_TX_LPI_ACTIVE(x) ((x) << S_1G_PCS3_TX_LPI_ACTIVE)
78168 #define F_1G_PCS3_TX_LPI_ACTIVE    V_1G_PCS3_TX_LPI_ACTIVE(1U)
78169 
78170 #define S_1G_PCS3_RX_MODE_QUIET    2
78171 #define V_1G_PCS3_RX_MODE_QUIET(x) ((x) << S_1G_PCS3_RX_MODE_QUIET)
78172 #define F_1G_PCS3_RX_MODE_QUIET    V_1G_PCS3_RX_MODE_QUIET(1U)
78173 
78174 #define S_1G_PCS3_RX_LPI_ACTIVE    1
78175 #define V_1G_PCS3_RX_LPI_ACTIVE(x) ((x) << S_1G_PCS3_RX_LPI_ACTIVE)
78176 #define F_1G_PCS3_RX_LPI_ACTIVE    V_1G_PCS3_RX_LPI_ACTIVE(1U)
78177 
78178 #define S_1G_PCS3_RX_WAKE_ERR    0
78179 #define V_1G_PCS3_RX_WAKE_ERR(x) ((x) << S_1G_PCS3_RX_WAKE_ERR)
78180 #define F_1G_PCS3_RX_WAKE_ERR    V_1G_PCS3_RX_WAKE_ERR(1U)
78181 
78182 #define A_MAC_PCS_LPI_STATUS_0 0x38170
78183 
78184 #define S_TX_LPI_STATE    0
78185 #define M_TX_LPI_STATE    0xffffffU
78186 #define V_TX_LPI_STATE(x) ((x) << S_TX_LPI_STATE)
78187 #define G_TX_LPI_STATE(x) (((x) >> S_TX_LPI_STATE) & M_TX_LPI_STATE)
78188 
78189 #define A_MAC_PCS_LPI_STATUS_1 0x38174
78190 
78191 #define S_TX_LPI_MODE    0
78192 #define M_TX_LPI_MODE    0xffffU
78193 #define V_TX_LPI_MODE(x) ((x) << S_TX_LPI_MODE)
78194 #define G_TX_LPI_MODE(x) (((x) >> S_TX_LPI_MODE) & M_TX_LPI_MODE)
78195 
78196 #define A_MAC_PCS_LPI_STATUS_2 0x38178
78197 
78198 #define S_RX_LPI_MODE    24
78199 #define M_RX_LPI_MODE    0xffU
78200 #define V_RX_LPI_MODE(x) ((x) << S_RX_LPI_MODE)
78201 #define G_RX_LPI_MODE(x) (((x) >> S_RX_LPI_MODE) & M_RX_LPI_MODE)
78202 
78203 #define S_RX_LPI_STATE    0
78204 #define M_RX_LPI_STATE    0xffffffU
78205 #define V_RX_LPI_STATE(x) ((x) << S_RX_LPI_STATE)
78206 #define G_RX_LPI_STATE(x) (((x) >> S_RX_LPI_STATE) & M_RX_LPI_STATE)
78207 
78208 #define A_MAC_PCS_LPI_STATUS_3 0x3817c
78209 
78210 #define S_T7_RX_LPI_ACTIVE    0
78211 #define M_T7_RX_LPI_ACTIVE    0xffU
78212 #define V_T7_RX_LPI_ACTIVE(x) ((x) << S_T7_RX_LPI_ACTIVE)
78213 #define G_T7_RX_LPI_ACTIVE(x) (((x) >> S_T7_RX_LPI_ACTIVE) & M_T7_RX_LPI_ACTIVE)
78214 
78215 #define A_MAC_TX0_CLK_DIV 0x38180
78216 #define A_MAC_TX1_CLK_DIV 0x38184
78217 #define A_MAC_TX2_CLK_DIV 0x38188
78218 #define A_MAC_TX3_CLK_DIV 0x3818c
78219 #define A_MAC_TX4_CLK_DIV 0x38190
78220 #define A_MAC_TX5_CLK_DIV 0x38194
78221 #define A_MAC_TX6_CLK_DIV 0x38198
78222 #define A_MAC_TX7_CLK_DIV 0x3819c
78223 #define A_MAC_RX0_CLK_DIV 0x381a0
78224 #define A_MAC_RX1_CLK_DIV 0x381a4
78225 #define A_MAC_RX2_CLK_DIV 0x381a8
78226 #define A_MAC_RX3_CLK_DIV 0x381ac
78227 #define A_MAC_RX4_CLK_DIV 0x381b0
78228 #define A_MAC_RX5_CLK_DIV 0x381b4
78229 #define A_MAC_RX6_CLK_DIV 0x381b8
78230 #define A_MAC_RX7_CLK_DIV 0x381bc
78231 #define A_MAC_SYNC_E_CDR_LANE_SEL 0x381c0
78232 
78233 #define S_CML_MUX_SEL    11
78234 #define V_CML_MUX_SEL(x) ((x) << S_CML_MUX_SEL)
78235 #define F_CML_MUX_SEL    V_CML_MUX_SEL(1U)
78236 
78237 #define S_CMOS_OUT_EN    10
78238 #define V_CMOS_OUT_EN(x) ((x) << S_CMOS_OUT_EN)
78239 #define F_CMOS_OUT_EN    V_CMOS_OUT_EN(1U)
78240 
78241 #define S_CML_OUT_EN    9
78242 #define V_CML_OUT_EN(x) ((x) << S_CML_OUT_EN)
78243 #define F_CML_OUT_EN    V_CML_OUT_EN(1U)
78244 
78245 #define S_LOC_FAULT_PORT_SEL    6
78246 #define M_LOC_FAULT_PORT_SEL    0x3U
78247 #define V_LOC_FAULT_PORT_SEL(x) ((x) << S_LOC_FAULT_PORT_SEL)
78248 #define G_LOC_FAULT_PORT_SEL(x) (((x) >> S_LOC_FAULT_PORT_SEL) & M_LOC_FAULT_PORT_SEL)
78249 
78250 #define S_TX_CDR_LANE_SEL    3
78251 #define M_TX_CDR_LANE_SEL    0x7U
78252 #define V_TX_CDR_LANE_SEL(x) ((x) << S_TX_CDR_LANE_SEL)
78253 #define G_TX_CDR_LANE_SEL(x) (((x) >> S_TX_CDR_LANE_SEL) & M_TX_CDR_LANE_SEL)
78254 
78255 #define S_RX_CDR_LANE_SEL    0
78256 #define M_RX_CDR_LANE_SEL    0x7U
78257 #define V_RX_CDR_LANE_SEL(x) ((x) << S_RX_CDR_LANE_SEL)
78258 #define G_RX_CDR_LANE_SEL(x) (((x) >> S_RX_CDR_LANE_SEL) & M_RX_CDR_LANE_SEL)
78259 
78260 #define A_MAC_DEBUG_PL_IF_1 0x381c4
78261 #define A_MAC_SIGNAL_DETECT_CTRL 0x381f0
78262 
78263 #define S_SIGNAL_DET_LN7    15
78264 #define V_SIGNAL_DET_LN7(x) ((x) << S_SIGNAL_DET_LN7)
78265 #define F_SIGNAL_DET_LN7    V_SIGNAL_DET_LN7(1U)
78266 
78267 #define S_SIGNAL_DET_LN6    14
78268 #define V_SIGNAL_DET_LN6(x) ((x) << S_SIGNAL_DET_LN6)
78269 #define F_SIGNAL_DET_LN6    V_SIGNAL_DET_LN6(1U)
78270 
78271 #define S_SIGNAL_DET_LN5    13
78272 #define V_SIGNAL_DET_LN5(x) ((x) << S_SIGNAL_DET_LN5)
78273 #define F_SIGNAL_DET_LN5    V_SIGNAL_DET_LN5(1U)
78274 
78275 #define S_SIGNAL_DET_LN4    12
78276 #define V_SIGNAL_DET_LN4(x) ((x) << S_SIGNAL_DET_LN4)
78277 #define F_SIGNAL_DET_LN4    V_SIGNAL_DET_LN4(1U)
78278 
78279 #define S_SIGNAL_DET_LN3    11
78280 #define V_SIGNAL_DET_LN3(x) ((x) << S_SIGNAL_DET_LN3)
78281 #define F_SIGNAL_DET_LN3    V_SIGNAL_DET_LN3(1U)
78282 
78283 #define S_SIGNAL_DET_LN2    10
78284 #define V_SIGNAL_DET_LN2(x) ((x) << S_SIGNAL_DET_LN2)
78285 #define F_SIGNAL_DET_LN2    V_SIGNAL_DET_LN2(1U)
78286 
78287 #define S_SIGNAL_DET_LN1    9
78288 #define V_SIGNAL_DET_LN1(x) ((x) << S_SIGNAL_DET_LN1)
78289 #define F_SIGNAL_DET_LN1    V_SIGNAL_DET_LN1(1U)
78290 
78291 #define S_SIGNAL_DET_LN0    8
78292 #define V_SIGNAL_DET_LN0(x) ((x) << S_SIGNAL_DET_LN0)
78293 #define F_SIGNAL_DET_LN0    V_SIGNAL_DET_LN0(1U)
78294 
78295 #define S_SIGDETCTRL_LN7    7
78296 #define V_SIGDETCTRL_LN7(x) ((x) << S_SIGDETCTRL_LN7)
78297 #define F_SIGDETCTRL_LN7    V_SIGDETCTRL_LN7(1U)
78298 
78299 #define S_SIGDETCTRL_LN6    6
78300 #define V_SIGDETCTRL_LN6(x) ((x) << S_SIGDETCTRL_LN6)
78301 #define F_SIGDETCTRL_LN6    V_SIGDETCTRL_LN6(1U)
78302 
78303 #define S_SIGDETCTRL_LN5    5
78304 #define V_SIGDETCTRL_LN5(x) ((x) << S_SIGDETCTRL_LN5)
78305 #define F_SIGDETCTRL_LN5    V_SIGDETCTRL_LN5(1U)
78306 
78307 #define S_SIGDETCTRL_LN4    4
78308 #define V_SIGDETCTRL_LN4(x) ((x) << S_SIGDETCTRL_LN4)
78309 #define F_SIGDETCTRL_LN4    V_SIGDETCTRL_LN4(1U)
78310 
78311 #define S_SIGDETCTRL_LN3    3
78312 #define V_SIGDETCTRL_LN3(x) ((x) << S_SIGDETCTRL_LN3)
78313 #define F_SIGDETCTRL_LN3    V_SIGDETCTRL_LN3(1U)
78314 
78315 #define S_SIGDETCTRL_LN2    2
78316 #define V_SIGDETCTRL_LN2(x) ((x) << S_SIGDETCTRL_LN2)
78317 #define F_SIGDETCTRL_LN2    V_SIGDETCTRL_LN2(1U)
78318 
78319 #define S_SIGDETCTRL_LN1    1
78320 #define V_SIGDETCTRL_LN1(x) ((x) << S_SIGDETCTRL_LN1)
78321 #define F_SIGDETCTRL_LN1    V_SIGDETCTRL_LN1(1U)
78322 
78323 #define S_SIGDETCTRL_LN0    0
78324 #define V_SIGDETCTRL_LN0(x) ((x) << S_SIGDETCTRL_LN0)
78325 #define F_SIGDETCTRL_LN0    V_SIGDETCTRL_LN0(1U)
78326 
78327 #define A_MAC_FPGA_STATUS_FRM_BOARD 0x381f4
78328 
78329 #define S_SFP3_RX_LOS    15
78330 #define V_SFP3_RX_LOS(x) ((x) << S_SFP3_RX_LOS)
78331 #define F_SFP3_RX_LOS    V_SFP3_RX_LOS(1U)
78332 
78333 #define S_SFP3_TX_FAULT    14
78334 #define V_SFP3_TX_FAULT(x) ((x) << S_SFP3_TX_FAULT)
78335 #define F_SFP3_TX_FAULT    V_SFP3_TX_FAULT(1U)
78336 
78337 #define S_SFP3_MOD_PRES    13
78338 #define V_SFP3_MOD_PRES(x) ((x) << S_SFP3_MOD_PRES)
78339 #define F_SFP3_MOD_PRES    V_SFP3_MOD_PRES(1U)
78340 
78341 #define S_SFP2_RX_LOS    12
78342 #define V_SFP2_RX_LOS(x) ((x) << S_SFP2_RX_LOS)
78343 #define F_SFP2_RX_LOS    V_SFP2_RX_LOS(1U)
78344 
78345 #define S_SFP2_TX_FAULT    11
78346 #define V_SFP2_TX_FAULT(x) ((x) << S_SFP2_TX_FAULT)
78347 #define F_SFP2_TX_FAULT    V_SFP2_TX_FAULT(1U)
78348 
78349 #define S_SFP2_MOD_PRES    10
78350 #define V_SFP2_MOD_PRES(x) ((x) << S_SFP2_MOD_PRES)
78351 #define F_SFP2_MOD_PRES    V_SFP2_MOD_PRES(1U)
78352 
78353 #define S_SFP1_RX_LOS    9
78354 #define V_SFP1_RX_LOS(x) ((x) << S_SFP1_RX_LOS)
78355 #define F_SFP1_RX_LOS    V_SFP1_RX_LOS(1U)
78356 
78357 #define S_SFP1_TX_FAULT    8
78358 #define V_SFP1_TX_FAULT(x) ((x) << S_SFP1_TX_FAULT)
78359 #define F_SFP1_TX_FAULT    V_SFP1_TX_FAULT(1U)
78360 
78361 #define S_SFP1_MOD_PRES    7
78362 #define V_SFP1_MOD_PRES(x) ((x) << S_SFP1_MOD_PRES)
78363 #define F_SFP1_MOD_PRES    V_SFP1_MOD_PRES(1U)
78364 
78365 #define S_SFP0_RX_LOS    6
78366 #define V_SFP0_RX_LOS(x) ((x) << S_SFP0_RX_LOS)
78367 #define F_SFP0_RX_LOS    V_SFP0_RX_LOS(1U)
78368 
78369 #define S_SFP0_TX_FAULT    5
78370 #define V_SFP0_TX_FAULT(x) ((x) << S_SFP0_TX_FAULT)
78371 #define F_SFP0_TX_FAULT    V_SFP0_TX_FAULT(1U)
78372 
78373 #define S_SFP0_MOD_PRES    4
78374 #define V_SFP0_MOD_PRES(x) ((x) << S_SFP0_MOD_PRES)
78375 #define F_SFP0_MOD_PRES    V_SFP0_MOD_PRES(1U)
78376 
78377 #define S_QSFP1_INT_L    3
78378 #define V_QSFP1_INT_L(x) ((x) << S_QSFP1_INT_L)
78379 #define F_QSFP1_INT_L    V_QSFP1_INT_L(1U)
78380 
78381 #define S_QSFP1_MOD_PRES    2
78382 #define V_QSFP1_MOD_PRES(x) ((x) << S_QSFP1_MOD_PRES)
78383 #define F_QSFP1_MOD_PRES    V_QSFP1_MOD_PRES(1U)
78384 
78385 #define S_QSFP0_INT_L    1
78386 #define V_QSFP0_INT_L(x) ((x) << S_QSFP0_INT_L)
78387 #define F_QSFP0_INT_L    V_QSFP0_INT_L(1U)
78388 
78389 #define S_QSFP0_MOD_PRES    0
78390 #define V_QSFP0_MOD_PRES(x) ((x) << S_QSFP0_MOD_PRES)
78391 #define F_QSFP0_MOD_PRES    V_QSFP0_MOD_PRES(1U)
78392 
78393 #define A_MAC_FPGA_CONTROL_TO_BOARD 0x381f8
78394 
78395 #define S_T7_1_LB_MODE    10
78396 #define M_T7_1_LB_MODE    0x3U
78397 #define V_T7_1_LB_MODE(x) ((x) << S_T7_1_LB_MODE)
78398 #define G_T7_1_LB_MODE(x) (((x) >> S_T7_1_LB_MODE) & M_T7_1_LB_MODE)
78399 
78400 #define S_SFP3_TX_DISABLE    9
78401 #define V_SFP3_TX_DISABLE(x) ((x) << S_SFP3_TX_DISABLE)
78402 #define F_SFP3_TX_DISABLE    V_SFP3_TX_DISABLE(1U)
78403 
78404 #define S_SFP2_TX_DISABLE    8
78405 #define V_SFP2_TX_DISABLE(x) ((x) << S_SFP2_TX_DISABLE)
78406 #define F_SFP2_TX_DISABLE    V_SFP2_TX_DISABLE(1U)
78407 
78408 #define S_SFP1_TX_DISABLE    7
78409 #define V_SFP1_TX_DISABLE(x) ((x) << S_SFP1_TX_DISABLE)
78410 #define F_SFP1_TX_DISABLE    V_SFP1_TX_DISABLE(1U)
78411 
78412 #define S_SFP0_TX_DISABLE    6
78413 #define V_SFP0_TX_DISABLE(x) ((x) << S_SFP0_TX_DISABLE)
78414 #define F_SFP0_TX_DISABLE    V_SFP0_TX_DISABLE(1U)
78415 
78416 #define S_QSFP1_LPMODE    5
78417 #define V_QSFP1_LPMODE(x) ((x) << S_QSFP1_LPMODE)
78418 #define F_QSFP1_LPMODE    V_QSFP1_LPMODE(1U)
78419 
78420 #define S_QSFP1_MODSEL_L    4
78421 #define V_QSFP1_MODSEL_L(x) ((x) << S_QSFP1_MODSEL_L)
78422 #define F_QSFP1_MODSEL_L    V_QSFP1_MODSEL_L(1U)
78423 
78424 #define S_QSFP1_RESET_L    3
78425 #define V_QSFP1_RESET_L(x) ((x) << S_QSFP1_RESET_L)
78426 #define F_QSFP1_RESET_L    V_QSFP1_RESET_L(1U)
78427 
78428 #define S_QSFP0_LPMODE    2
78429 #define V_QSFP0_LPMODE(x) ((x) << S_QSFP0_LPMODE)
78430 #define F_QSFP0_LPMODE    V_QSFP0_LPMODE(1U)
78431 
78432 #define S_QSFP0_MODSEL_L    1
78433 #define V_QSFP0_MODSEL_L(x) ((x) << S_QSFP0_MODSEL_L)
78434 #define F_QSFP0_MODSEL_L    V_QSFP0_MODSEL_L(1U)
78435 
78436 #define S_QSFP0_RESET_L    0
78437 #define V_QSFP0_RESET_L(x) ((x) << S_QSFP0_RESET_L)
78438 #define F_QSFP0_RESET_L    V_QSFP0_RESET_L(1U)
78439 
78440 #define A_MAC_FPGA_LINK_STATUS 0x381fc
78441 
78442 #define S_PORT3_FPGA_LINK_UP    3
78443 #define V_PORT3_FPGA_LINK_UP(x) ((x) << S_PORT3_FPGA_LINK_UP)
78444 #define F_PORT3_FPGA_LINK_UP    V_PORT3_FPGA_LINK_UP(1U)
78445 
78446 #define S_PORT2_FPGA_LINK_UP    2
78447 #define V_PORT2_FPGA_LINK_UP(x) ((x) << S_PORT2_FPGA_LINK_UP)
78448 #define F_PORT2_FPGA_LINK_UP    V_PORT2_FPGA_LINK_UP(1U)
78449 
78450 #define S_PORT1_FPGA_LINK_UP    1
78451 #define V_PORT1_FPGA_LINK_UP(x) ((x) << S_PORT1_FPGA_LINK_UP)
78452 #define F_PORT1_FPGA_LINK_UP    V_PORT1_FPGA_LINK_UP(1U)
78453 
78454 #define S_PORT0_FPGA_LINK_UP    0
78455 #define V_PORT0_FPGA_LINK_UP(x) ((x) << S_PORT0_FPGA_LINK_UP)
78456 #define F_PORT0_FPGA_LINK_UP    V_PORT0_FPGA_LINK_UP(1U)
78457 
78458 #define A_MAC_MTIP_MAC400G_0_MTIP_REVISION 0x38200
78459 
78460 #define S_MTIP_REV_400G_0    0
78461 #define M_MTIP_REV_400G_0    0xffU
78462 #define V_MTIP_REV_400G_0(x) ((x) << S_MTIP_REV_400G_0)
78463 #define G_MTIP_REV_400G_0(x) (((x) >> S_MTIP_REV_400G_0) & M_MTIP_REV_400G_0)
78464 
78465 #define A_MAC_MTIP_MAC400G_0_MTIP_SCRATCH 0x38204
78466 #define A_MAC_MTIP_MAC400G_0_MTIP_COMMAND_CONFIG 0x38208
78467 
78468 #define S_INV_LOOP    31
78469 #define V_INV_LOOP(x) ((x) << S_INV_LOOP)
78470 #define F_INV_LOOP    V_INV_LOOP(1U)
78471 
78472 #define S_TX_FLUSH_ENABLE_400G_0    22
78473 #define V_TX_FLUSH_ENABLE_400G_0(x) ((x) << S_TX_FLUSH_ENABLE_400G_0)
78474 #define F_TX_FLUSH_ENABLE_400G_0    V_TX_FLUSH_ENABLE_400G_0(1U)
78475 
78476 #define S_PHY_LOOPBACK_EN_400G    10
78477 #define V_PHY_LOOPBACK_EN_400G(x) ((x) << S_PHY_LOOPBACK_EN_400G)
78478 #define F_PHY_LOOPBACK_EN_400G    V_PHY_LOOPBACK_EN_400G(1U)
78479 
78480 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_ADDR_0 0x3820c
78481 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_ADDR_1 0x38210
78482 #define A_MAC_MTIP_MAC400G_0_MTIP_FRM_LENGTH 0x38214
78483 #define A_MAC_MTIP_MAC400G_0_MTIP_RX_FIFO_SECTIONS 0x3821c
78484 #define A_MAC_MTIP_MAC400G_0_MTIP_TX_FIFO_SECTIONS 0x38220
78485 #define A_MAC_MTIP_MAC400G_0_MTIP_RX_FIFO_ALMOST_F_E 0x38224
78486 #define A_MAC_MTIP_MAC400G_0_MTIP_TX_FIFO_ALMOST_F_E 0x38228
78487 #define A_MAC_MTIP_MAC400G_0_MTIP_HASHTABLE_LOAD 0x3822c
78488 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_STATUS 0x38240
78489 #define A_MAC_MTIP_MAC400G_0_MTIP_TX_IPG_LENGTH 0x38244
78490 
78491 #define S_T7_IPG    19
78492 #define M_T7_IPG    0x1fffU
78493 #define V_T7_IPG(x) ((x) << S_T7_IPG)
78494 #define G_T7_IPG(x) (((x) >> S_T7_IPG) & M_T7_IPG)
78495 
78496 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL01_PAUSE_QUANTA 0x38254
78497 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL23_PAUSE_QUANTA 0x38258
78498 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL45_PAUSE_QUANTA 0x3825c
78499 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL67_PAUSE_QUANTA 0x38260
78500 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL01_PAUSE_QUANTA_THRESH 0x38264
78501 
78502 #define S_CL1_PAUSE_QUANTA_THRESH    16
78503 #define M_CL1_PAUSE_QUANTA_THRESH    0xffffU
78504 #define V_CL1_PAUSE_QUANTA_THRESH(x) ((x) << S_CL1_PAUSE_QUANTA_THRESH)
78505 #define G_CL1_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL1_PAUSE_QUANTA_THRESH) & M_CL1_PAUSE_QUANTA_THRESH)
78506 
78507 #define S_CL0_PAUSE_QUANTA_THRESH    0
78508 #define M_CL0_PAUSE_QUANTA_THRESH    0xffffU
78509 #define V_CL0_PAUSE_QUANTA_THRESH(x) ((x) << S_CL0_PAUSE_QUANTA_THRESH)
78510 #define G_CL0_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL0_PAUSE_QUANTA_THRESH) & M_CL0_PAUSE_QUANTA_THRESH)
78511 
78512 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL23_PAUSE_QUANTA_THRESH 0x38268
78513 
78514 #define S_CL3_PAUSE_QUANTA_THRESH    16
78515 #define M_CL3_PAUSE_QUANTA_THRESH    0xffffU
78516 #define V_CL3_PAUSE_QUANTA_THRESH(x) ((x) << S_CL3_PAUSE_QUANTA_THRESH)
78517 #define G_CL3_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL3_PAUSE_QUANTA_THRESH) & M_CL3_PAUSE_QUANTA_THRESH)
78518 
78519 #define S_CL2_PAUSE_QUANTA_THRESH    0
78520 #define M_CL2_PAUSE_QUANTA_THRESH    0xffffU
78521 #define V_CL2_PAUSE_QUANTA_THRESH(x) ((x) << S_CL2_PAUSE_QUANTA_THRESH)
78522 #define G_CL2_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL2_PAUSE_QUANTA_THRESH) & M_CL2_PAUSE_QUANTA_THRESH)
78523 
78524 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL45_PAUSE_QUANTA_THRESH 0x3826c
78525 
78526 #define S_CL5_PAUSE_QUANTA_THRESH    16
78527 #define M_CL5_PAUSE_QUANTA_THRESH    0xffffU
78528 #define V_CL5_PAUSE_QUANTA_THRESH(x) ((x) << S_CL5_PAUSE_QUANTA_THRESH)
78529 #define G_CL5_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL5_PAUSE_QUANTA_THRESH) & M_CL5_PAUSE_QUANTA_THRESH)
78530 
78531 #define S_CL4_PAUSE_QUANTA_THRESH    0
78532 #define M_CL4_PAUSE_QUANTA_THRESH    0xffffU
78533 #define V_CL4_PAUSE_QUANTA_THRESH(x) ((x) << S_CL4_PAUSE_QUANTA_THRESH)
78534 #define G_CL4_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL4_PAUSE_QUANTA_THRESH) & M_CL4_PAUSE_QUANTA_THRESH)
78535 
78536 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL67_PAUSE_QUANTA_THRESH 0x38270
78537 
78538 #define S_CL7_PAUSE_QUANTA_THRESH    16
78539 #define M_CL7_PAUSE_QUANTA_THRESH    0xffffU
78540 #define V_CL7_PAUSE_QUANTA_THRESH(x) ((x) << S_CL7_PAUSE_QUANTA_THRESH)
78541 #define G_CL7_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL7_PAUSE_QUANTA_THRESH) & M_CL7_PAUSE_QUANTA_THRESH)
78542 
78543 #define S_CL6_PAUSE_QUANTA_THRESH    0
78544 #define M_CL6_PAUSE_QUANTA_THRESH    0xffffU
78545 #define V_CL6_PAUSE_QUANTA_THRESH(x) ((x) << S_CL6_PAUSE_QUANTA_THRESH)
78546 #define G_CL6_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL6_PAUSE_QUANTA_THRESH) & M_CL6_PAUSE_QUANTA_THRESH)
78547 
78548 #define A_MAC_MTIP_MAC400G_0_MTIP_RX_PAUSE_STATUS 0x38274
78549 
78550 #define S_RX_PAUSE_STATUS    0
78551 #define M_RX_PAUSE_STATUS    0xffU
78552 #define V_RX_PAUSE_STATUS(x) ((x) << S_RX_PAUSE_STATUS)
78553 #define G_RX_PAUSE_STATUS(x) (((x) >> S_RX_PAUSE_STATUS) & M_RX_PAUSE_STATUS)
78554 
78555 #define A_MAC_MTIP_MAC400G_0_MTIP_TS_TIMESTAMP 0x3827c
78556 #define A_MAC_MTIP_MAC400G_0_MTIP_XIF_MODE 0x38280
78557 #define A_MAC_MTIP_MAC400G_1_MTIP_REVISION 0x38300
78558 
78559 #define S_MTIP_REV_400G_1    0
78560 #define M_MTIP_REV_400G_1    0xffU
78561 #define V_MTIP_REV_400G_1(x) ((x) << S_MTIP_REV_400G_1)
78562 #define G_MTIP_REV_400G_1(x) (((x) >> S_MTIP_REV_400G_1) & M_MTIP_REV_400G_1)
78563 
78564 #define A_MAC_MTIP_MAC400G_1_MTIP_SCRATCH 0x38304
78565 #define A_MAC_MTIP_MAC400G_1_MTIP_COMMAND_CONFIG 0x38308
78566 
78567 #define S_TX_FLUSH_ENABLE_400G_1    22
78568 #define V_TX_FLUSH_ENABLE_400G_1(x) ((x) << S_TX_FLUSH_ENABLE_400G_1)
78569 #define F_TX_FLUSH_ENABLE_400G_1    V_TX_FLUSH_ENABLE_400G_1(1U)
78570 
78571 #define S_PHY_LOOPBACK_EN_400G_1    10
78572 #define V_PHY_LOOPBACK_EN_400G_1(x) ((x) << S_PHY_LOOPBACK_EN_400G_1)
78573 #define F_PHY_LOOPBACK_EN_400G_1    V_PHY_LOOPBACK_EN_400G_1(1U)
78574 
78575 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_ADDR_0 0x3830c
78576 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_ADDR_1 0x38310
78577 #define A_MAC_MTIP_MAC400G_1_MTIP_FRM_LENGTH 0x38314
78578 #define A_MAC_MTIP_MAC400G_1_MTIP_RX_FIFO_SECTIONS 0x3831c
78579 #define A_MAC_MTIP_MAC400G_1_MTIP_TX_FIFO_SECTIONS 0x38320
78580 #define A_MAC_MTIP_MAC400G_1_MTIP_RX_FIFO_ALMOST_F_E 0x38324
78581 #define A_MAC_MTIP_MAC400G_1_MTIP_TX_FIFO_ALMOST_F_E 0x38328
78582 #define A_MAC_MTIP_MAC400G_1_MTIP_HASHTABLE_LOAD 0x3832c
78583 
78584 #define S_ENABLE_MCAST_RX_400G_1    8
78585 #define V_ENABLE_MCAST_RX_400G_1(x) ((x) << S_ENABLE_MCAST_RX_400G_1)
78586 #define F_ENABLE_MCAST_RX_400G_1    V_ENABLE_MCAST_RX_400G_1(1U)
78587 
78588 #define S_HASHTABLE_ADDR_400G_1    0
78589 #define M_HASHTABLE_ADDR_400G_1    0x3fU
78590 #define V_HASHTABLE_ADDR_400G_1(x) ((x) << S_HASHTABLE_ADDR_400G_1)
78591 #define G_HASHTABLE_ADDR_400G_1(x) (((x) >> S_HASHTABLE_ADDR_400G_1) & M_HASHTABLE_ADDR_400G_1)
78592 
78593 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_STATUS 0x38340
78594 #define A_MAC_MTIP_MAC400G_1_MTIP_TX_IPG_LENGTH 0x38344
78595 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL01_PAUSE_QUANTA 0x38354
78596 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL23_PAUSE_QUANTA 0x38358
78597 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL45_PAUSE_QUANTA 0x3835c
78598 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL67_PAUSE_QUANTA 0x38360
78599 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL01_PAUSE_QUANTA_THRESH 0x38364
78600 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL23_PAUSE_QUANTA_THRESH 0x38368
78601 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL45_PAUSE_QUANTA_THRESH 0x3836c
78602 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL67_PAUSE_QUANTA_THRESH 0x38370
78603 #define A_MAC_MTIP_MAC400G_1_MTIP_RX_PAUSE_STATUS 0x38374
78604 #define A_MAC_MTIP_MAC400G_1_MTIP_TS_TIMESTAMP 0x3837c
78605 #define A_MAC_MTIP_MAC400G_1_MTIP_XIF_MODE 0x38380
78606 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_CONTROL_1 0x38400
78607 
78608 #define S_T7_SPEED_SELECTION    2
78609 #define V_T7_SPEED_SELECTION(x) ((x) << S_T7_SPEED_SELECTION)
78610 #define F_T7_SPEED_SELECTION    V_T7_SPEED_SELECTION(1U)
78611 
78612 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_STATUS_1 0x38404
78613 
78614 #define S_400G_RX_LINK_STATUS    2
78615 #define V_400G_RX_LINK_STATUS(x) ((x) << S_400G_RX_LINK_STATUS)
78616 #define F_400G_RX_LINK_STATUS    V_400G_RX_LINK_STATUS(1U)
78617 
78618 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_DEVICE_ID0 0x38408
78619 
78620 #define S_400G_DEVICE_ID0_0    0
78621 #define M_400G_DEVICE_ID0_0    0xffffU
78622 #define V_400G_DEVICE_ID0_0(x) ((x) << S_400G_DEVICE_ID0_0)
78623 #define G_400G_DEVICE_ID0_0(x) (((x) >> S_400G_DEVICE_ID0_0) & M_400G_DEVICE_ID0_0)
78624 
78625 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_DEVICE_ID1 0x3840c
78626 
78627 #define S_400G_DEVICE_ID1_0    0
78628 #define M_400G_DEVICE_ID1_0    0xffffU
78629 #define V_400G_DEVICE_ID1_0(x) ((x) << S_400G_DEVICE_ID1_0)
78630 #define G_400G_DEVICE_ID1_0(x) (((x) >> S_400G_DEVICE_ID1_0) & M_400G_DEVICE_ID1_0)
78631 
78632 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_SPEED_ABILITY 0x38410
78633 
78634 #define S_400G_CAPABLE_0    9
78635 #define V_400G_CAPABLE_0(x) ((x) << S_400G_CAPABLE_0)
78636 #define F_400G_CAPABLE_0    V_400G_CAPABLE_0(1U)
78637 
78638 #define S_200G_CAPABLE_0    8
78639 #define V_200G_CAPABLE_0(x) ((x) << S_200G_CAPABLE_0)
78640 #define F_200G_CAPABLE_0    V_200G_CAPABLE_0(1U)
78641 
78642 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_DEVICES_IN_PKG1 0x38414
78643 
78644 #define S_DEVICE_PACKAGE    3
78645 #define V_DEVICE_PACKAGE(x) ((x) << S_DEVICE_PACKAGE)
78646 #define F_DEVICE_PACKAGE    V_DEVICE_PACKAGE(1U)
78647 
78648 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_DEVICES_IN_PKG2 0x38418
78649 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_CONTROL_2 0x3841c
78650 
78651 #define S_400G_PCS_TYPE_SELECTION_0    0
78652 #define M_400G_PCS_TYPE_SELECTION_0    0xfU
78653 #define V_400G_PCS_TYPE_SELECTION_0(x) ((x) << S_400G_PCS_TYPE_SELECTION_0)
78654 #define G_400G_PCS_TYPE_SELECTION_0(x) (((x) >> S_400G_PCS_TYPE_SELECTION_0) & M_400G_PCS_TYPE_SELECTION_0)
78655 
78656 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_STATUS_2 0x38420
78657 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_STATUS_3 0x38424
78658 
78659 #define S_T7_DEVICE_PRESENT    2
78660 #define M_T7_DEVICE_PRESENT    0x3fffU
78661 #define V_T7_DEVICE_PRESENT(x) ((x) << S_T7_DEVICE_PRESENT)
78662 #define G_T7_DEVICE_PRESENT(x) (((x) >> S_T7_DEVICE_PRESENT) & M_T7_DEVICE_PRESENT)
78663 
78664 #define S_400GBASE_R    1
78665 #define V_400GBASE_R(x) ((x) << S_400GBASE_R)
78666 #define F_400GBASE_R    V_400GBASE_R(1U)
78667 
78668 #define S_200GBASE_R    0
78669 #define V_200GBASE_R(x) ((x) << S_200GBASE_R)
78670 #define F_200GBASE_R    V_200GBASE_R(1U)
78671 
78672 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_PKG_ID0 0x38438
78673 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_PKG_ID1 0x3843c
78674 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_STATUS_1 0x38480
78675 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_STATUS_2 0x38484
78676 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_TEST_CONTROL 0x384a8
78677 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_TEST_ERR_CNT 0x384ac
78678 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_BER_HIGH_ORDER_CNT 0x384b0
78679 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_ERR_BLK_HIGH_ORDER_CNT 0x384b4
78680 
78681 #define S_HIGH_ORDER    15
78682 #define V_HIGH_ORDER(x) ((x) << S_HIGH_ORDER)
78683 #define F_HIGH_ORDER    V_HIGH_ORDER(1U)
78684 
78685 #define S_ERROR_BLOCK_COUNTER    0
78686 #define M_ERROR_BLOCK_COUNTER    0x3fffU
78687 #define V_ERROR_BLOCK_COUNTER(x) ((x) << S_ERROR_BLOCK_COUNTER)
78688 #define G_ERROR_BLOCK_COUNTER(x) (((x) >> S_ERROR_BLOCK_COUNTER) & M_ERROR_BLOCK_COUNTER)
78689 
78690 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_1 0x384c8
78691 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_2 0x384cc
78692 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_3 0x384d0
78693 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_4 0x384d4
78694 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_0_MAPPING 0x384d8
78695 
78696 #define S_T7_LANE_0_MAPPING    0
78697 #define M_T7_LANE_0_MAPPING    0xfU
78698 #define V_T7_LANE_0_MAPPING(x) ((x) << S_T7_LANE_0_MAPPING)
78699 #define G_T7_LANE_0_MAPPING(x) (((x) >> S_T7_LANE_0_MAPPING) & M_T7_LANE_0_MAPPING)
78700 
78701 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_1_MAPPING 0x384dc
78702 
78703 #define S_T7_LANE_1_MAPPING    0
78704 #define M_T7_LANE_1_MAPPING    0xfU
78705 #define V_T7_LANE_1_MAPPING(x) ((x) << S_T7_LANE_1_MAPPING)
78706 #define G_T7_LANE_1_MAPPING(x) (((x) >> S_T7_LANE_1_MAPPING) & M_T7_LANE_1_MAPPING)
78707 
78708 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_2_MAPPING 0x384e0
78709 
78710 #define S_T7_LANE_2_MAPPING    0
78711 #define M_T7_LANE_2_MAPPING    0xfU
78712 #define V_T7_LANE_2_MAPPING(x) ((x) << S_T7_LANE_2_MAPPING)
78713 #define G_T7_LANE_2_MAPPING(x) (((x) >> S_T7_LANE_2_MAPPING) & M_T7_LANE_2_MAPPING)
78714 
78715 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_3_MAPPING 0x384e4
78716 
78717 #define S_T7_LANE_3_MAPPING    0
78718 #define M_T7_LANE_3_MAPPING    0xfU
78719 #define V_T7_LANE_3_MAPPING(x) ((x) << S_T7_LANE_3_MAPPING)
78720 #define G_T7_LANE_3_MAPPING(x) (((x) >> S_T7_LANE_3_MAPPING) & M_T7_LANE_3_MAPPING)
78721 
78722 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_4_MAPPING 0x384e8
78723 
78724 #define S_T7_LANE_4_MAPPING    0
78725 #define M_T7_LANE_4_MAPPING    0xfU
78726 #define V_T7_LANE_4_MAPPING(x) ((x) << S_T7_LANE_4_MAPPING)
78727 #define G_T7_LANE_4_MAPPING(x) (((x) >> S_T7_LANE_4_MAPPING) & M_T7_LANE_4_MAPPING)
78728 
78729 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_5_MAPPING 0x384ec
78730 
78731 #define S_T7_LANE_5_MAPPING    0
78732 #define M_T7_LANE_5_MAPPING    0xfU
78733 #define V_T7_LANE_5_MAPPING(x) ((x) << S_T7_LANE_5_MAPPING)
78734 #define G_T7_LANE_5_MAPPING(x) (((x) >> S_T7_LANE_5_MAPPING) & M_T7_LANE_5_MAPPING)
78735 
78736 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_6_MAPPING 0x384f0
78737 
78738 #define S_T7_LANE_6_MAPPING    0
78739 #define M_T7_LANE_6_MAPPING    0xfU
78740 #define V_T7_LANE_6_MAPPING(x) ((x) << S_T7_LANE_6_MAPPING)
78741 #define G_T7_LANE_6_MAPPING(x) (((x) >> S_T7_LANE_6_MAPPING) & M_T7_LANE_6_MAPPING)
78742 
78743 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_7_MAPPING 0x384f4
78744 
78745 #define S_T7_LANE_7_MAPPING    0
78746 #define M_T7_LANE_7_MAPPING    0xfU
78747 #define V_T7_LANE_7_MAPPING(x) ((x) << S_T7_LANE_7_MAPPING)
78748 #define G_T7_LANE_7_MAPPING(x) (((x) >> S_T7_LANE_7_MAPPING) & M_T7_LANE_7_MAPPING)
78749 
78750 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_8_MAPPING 0x384f8
78751 
78752 #define S_T7_LANE_8_MAPPING    0
78753 #define M_T7_LANE_8_MAPPING    0xfU
78754 #define V_T7_LANE_8_MAPPING(x) ((x) << S_T7_LANE_8_MAPPING)
78755 #define G_T7_LANE_8_MAPPING(x) (((x) >> S_T7_LANE_8_MAPPING) & M_T7_LANE_8_MAPPING)
78756 
78757 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_9_MAPPING 0x384fc
78758 
78759 #define S_T7_LANE_9_MAPPING    0
78760 #define M_T7_LANE_9_MAPPING    0xfU
78761 #define V_T7_LANE_9_MAPPING(x) ((x) << S_T7_LANE_9_MAPPING)
78762 #define G_T7_LANE_9_MAPPING(x) (((x) >> S_T7_LANE_9_MAPPING) & M_T7_LANE_9_MAPPING)
78763 
78764 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_10_MAPPING 0x38500
78765 
78766 #define S_T7_LANE_10_MAPPING    0
78767 #define M_T7_LANE_10_MAPPING    0xfU
78768 #define V_T7_LANE_10_MAPPING(x) ((x) << S_T7_LANE_10_MAPPING)
78769 #define G_T7_LANE_10_MAPPING(x) (((x) >> S_T7_LANE_10_MAPPING) & M_T7_LANE_10_MAPPING)
78770 
78771 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_11_MAPPING 0x38504
78772 
78773 #define S_T7_LANE_11_MAPPING    0
78774 #define M_T7_LANE_11_MAPPING    0xfU
78775 #define V_T7_LANE_11_MAPPING(x) ((x) << S_T7_LANE_11_MAPPING)
78776 #define G_T7_LANE_11_MAPPING(x) (((x) >> S_T7_LANE_11_MAPPING) & M_T7_LANE_11_MAPPING)
78777 
78778 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_12_MAPPING 0x38508
78779 
78780 #define S_T7_LANE_12_MAPPING    0
78781 #define M_T7_LANE_12_MAPPING    0xfU
78782 #define V_T7_LANE_12_MAPPING(x) ((x) << S_T7_LANE_12_MAPPING)
78783 #define G_T7_LANE_12_MAPPING(x) (((x) >> S_T7_LANE_12_MAPPING) & M_T7_LANE_12_MAPPING)
78784 
78785 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_13_MAPPING 0x3850c
78786 
78787 #define S_T7_LANE_13_MAPPING    0
78788 #define M_T7_LANE_13_MAPPING    0xfU
78789 #define V_T7_LANE_13_MAPPING(x) ((x) << S_T7_LANE_13_MAPPING)
78790 #define G_T7_LANE_13_MAPPING(x) (((x) >> S_T7_LANE_13_MAPPING) & M_T7_LANE_13_MAPPING)
78791 
78792 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_14_MAPPING 0x38510
78793 
78794 #define S_T7_LANE_14_MAPPING    0
78795 #define M_T7_LANE_14_MAPPING    0xfU
78796 #define V_T7_LANE_14_MAPPING(x) ((x) << S_T7_LANE_14_MAPPING)
78797 #define G_T7_LANE_14_MAPPING(x) (((x) >> S_T7_LANE_14_MAPPING) & M_T7_LANE_14_MAPPING)
78798 
78799 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_15_MAPPING 0x38514
78800 
78801 #define S_T7_LANE_15_MAPPING    0
78802 #define M_T7_LANE_15_MAPPING    0xfU
78803 #define V_T7_LANE_15_MAPPING(x) ((x) << S_T7_LANE_15_MAPPING)
78804 #define G_T7_LANE_15_MAPPING(x) (((x) >> S_T7_LANE_15_MAPPING) & M_T7_LANE_15_MAPPING)
78805 
78806 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_SCRATCH 0x38600
78807 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_CORE_REVISION 0x38604
78808 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_CL_INTVL 0x38608
78809 
78810 #define S_T7_VL_INTVL    0
78811 #define M_T7_VL_INTVL    0xffffU
78812 #define V_T7_VL_INTVL(x) ((x) << S_T7_VL_INTVL)
78813 #define G_T7_VL_INTVL(x) (((x) >> S_T7_VL_INTVL) & M_T7_VL_INTVL)
78814 
78815 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_TX_LANE_THRESH 0x3860c
78816 
78817 #define S_TX_LANE_THRESH    0
78818 #define M_TX_LANE_THRESH    0xfU
78819 #define V_TX_LANE_THRESH(x) ((x) << S_TX_LANE_THRESH)
78820 #define G_TX_LANE_THRESH(x) (((x) >> S_TX_LANE_THRESH) & M_TX_LANE_THRESH)
78821 
78822 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_TX_CDMII_PACE 0x3861c
78823 
78824 #define S_TX_CDMII_PACE    0
78825 #define M_TX_CDMII_PACE    0xfU
78826 #define V_TX_CDMII_PACE(x) ((x) << S_TX_CDMII_PACE)
78827 #define G_TX_CDMII_PACE(x) (((x) >> S_TX_CDMII_PACE) & M_TX_CDMII_PACE)
78828 
78829 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_AM_0 0x38620
78830 
78831 #define S_AM_0    0
78832 #define M_AM_0    0xffffU
78833 #define V_AM_0(x) ((x) << S_AM_0)
78834 #define G_AM_0(x) (((x) >> S_AM_0) & M_AM_0)
78835 
78836 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_AM_1 0x38624
78837 
78838 #define S_AM_1    0
78839 #define M_AM_1    0xffffU
78840 #define V_AM_1(x) ((x) << S_AM_1)
78841 #define G_AM_1(x) (((x) >> S_AM_1) & M_AM_1)
78842 
78843 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO0 0x38800
78844 
78845 #define S_DBGINFO0    0
78846 #define M_DBGINFO0    0xffffU
78847 #define V_DBGINFO0(x) ((x) << S_DBGINFO0)
78848 #define G_DBGINFO0(x) (((x) >> S_DBGINFO0) & M_DBGINFO0)
78849 
78850 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO1 0x38804
78851 
78852 #define S_DBGINFO1    0
78853 #define M_DBGINFO1    0xffffU
78854 #define V_DBGINFO1(x) ((x) << S_DBGINFO1)
78855 #define G_DBGINFO1(x) (((x) >> S_DBGINFO1) & M_DBGINFO1)
78856 
78857 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO2 0x38808
78858 
78859 #define S_DBGINFO2    0
78860 #define M_DBGINFO2    0xffffU
78861 #define V_DBGINFO2(x) ((x) << S_DBGINFO2)
78862 #define G_DBGINFO2(x) (((x) >> S_DBGINFO2) & M_DBGINFO2)
78863 
78864 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO3 0x3880c
78865 
78866 #define S_DBGINFO3    0
78867 #define M_DBGINFO3    0xffffU
78868 #define V_DBGINFO3(x) ((x) << S_DBGINFO3)
78869 #define G_DBGINFO3(x) (((x) >> S_DBGINFO3) & M_DBGINFO3)
78870 
78871 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_CONTROL_1 0x38900
78872 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_STATUS_1 0x38904
78873 
78874 #define S_400G_RX_LINK_STATUS_1    2
78875 #define V_400G_RX_LINK_STATUS_1(x) ((x) << S_400G_RX_LINK_STATUS_1)
78876 #define F_400G_RX_LINK_STATUS_1    V_400G_RX_LINK_STATUS_1(1U)
78877 
78878 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_DEVICE_ID0 0x38908
78879 
78880 #define S_400G_DEVICE_ID0_1    0
78881 #define M_400G_DEVICE_ID0_1    0xffffU
78882 #define V_400G_DEVICE_ID0_1(x) ((x) << S_400G_DEVICE_ID0_1)
78883 #define G_400G_DEVICE_ID0_1(x) (((x) >> S_400G_DEVICE_ID0_1) & M_400G_DEVICE_ID0_1)
78884 
78885 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_DEVICE_ID1 0x3890c
78886 
78887 #define S_400G_DEVICE_ID1_1    0
78888 #define M_400G_DEVICE_ID1_1    0xffffU
78889 #define V_400G_DEVICE_ID1_1(x) ((x) << S_400G_DEVICE_ID1_1)
78890 #define G_400G_DEVICE_ID1_1(x) (((x) >> S_400G_DEVICE_ID1_1) & M_400G_DEVICE_ID1_1)
78891 
78892 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_SPEED_ABILITY 0x38910
78893 
78894 #define S_400G_CAPABLE_1    9
78895 #define V_400G_CAPABLE_1(x) ((x) << S_400G_CAPABLE_1)
78896 #define F_400G_CAPABLE_1    V_400G_CAPABLE_1(1U)
78897 
78898 #define S_200G_CAPABLE_1    8
78899 #define V_200G_CAPABLE_1(x) ((x) << S_200G_CAPABLE_1)
78900 #define F_200G_CAPABLE_1    V_200G_CAPABLE_1(1U)
78901 
78902 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_DEVICES_IN_PKG1 0x38914
78903 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_DEVICES_IN_PKG2 0x38918
78904 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_CONTROL_2 0x3891c
78905 
78906 #define S_400G_PCS_TYPE_SELECTION_1    0
78907 #define M_400G_PCS_TYPE_SELECTION_1    0xfU
78908 #define V_400G_PCS_TYPE_SELECTION_1(x) ((x) << S_400G_PCS_TYPE_SELECTION_1)
78909 #define G_400G_PCS_TYPE_SELECTION_1(x) (((x) >> S_400G_PCS_TYPE_SELECTION_1) & M_400G_PCS_TYPE_SELECTION_1)
78910 
78911 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_STATUS_2 0x38920
78912 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_STATUS_3 0x38924
78913 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_PKG_ID0 0x38938
78914 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_PKG_ID1 0x3893c
78915 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_STATUS_1 0x38980
78916 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_STATUS_2 0x38984
78917 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_TEST_CONTROL 0x389a8
78918 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_TEST_ERR_CNT 0x389ac
78919 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_BER_HIGH_ORDER_CNT 0x389b0
78920 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_ERR_BLK_HIGH_ORDER_CNT 0x389b4
78921 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_1 0x389c8
78922 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_2 0x389cc
78923 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_3 0x389d0
78924 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_4 0x389d4
78925 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_0_MAPPING 0x389d8
78926 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_1_MAPPING 0x389dc
78927 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_2_MAPPING 0x389e0
78928 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_3_MAPPING 0x389e4
78929 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_4_MAPPING 0x389e8
78930 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_5_MAPPING 0x389ec
78931 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_6_MAPPING 0x389f0
78932 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_7_MAPPING 0x389f4
78933 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_8_MAPPING 0x389f8
78934 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_9_MAPPING 0x389fc
78935 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_10_MAPPING 0x38a00
78936 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_11_MAPPING 0x38a04
78937 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_12_MAPPING 0x38a08
78938 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_13_MAPPING 0x38a0c
78939 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_14_MAPPING 0x38a10
78940 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_15_MAPPING 0x38a14
78941 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_SCRATCH 0x38b00
78942 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_CORE_REVISION 0x38b04
78943 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_CL_INTVL 0x38b08
78944 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_TX_LANE_THRESH 0x38b0c
78945 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_TX_CDMII_PACE 0x38b1c
78946 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_AM_0 0x38b20
78947 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_AM_1 0x38b24
78948 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO0 0x38d00
78949 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO1 0x38d04
78950 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO2 0x38d08
78951 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO3 0x38d0c
78952 #define A_MAC_MTIP_RS_FEC_CONTROL_0_0 0x38e00
78953 
78954 #define S_TC_PAD_ALTER    10
78955 #define V_TC_PAD_ALTER(x) ((x) << S_TC_PAD_ALTER)
78956 #define F_TC_PAD_ALTER    V_TC_PAD_ALTER(1U)
78957 
78958 #define S_TC_PAD_VALUE    9
78959 #define V_TC_PAD_VALUE(x) ((x) << S_TC_PAD_VALUE)
78960 #define F_TC_PAD_VALUE    V_TC_PAD_VALUE(1U)
78961 
78962 #define S_KP_ENABLE    8
78963 #define V_KP_ENABLE(x) ((x) << S_KP_ENABLE)
78964 #define F_KP_ENABLE    V_KP_ENABLE(1U)
78965 
78966 #define S_AM16_COPY_DIS    3
78967 #define V_AM16_COPY_DIS(x) ((x) << S_AM16_COPY_DIS)
78968 #define F_AM16_COPY_DIS    V_AM16_COPY_DIS(1U)
78969 
78970 #define S_RS_FEC_DEGRADE_OPTION_ENA    2
78971 #define V_RS_FEC_DEGRADE_OPTION_ENA(x) ((x) << S_RS_FEC_DEGRADE_OPTION_ENA)
78972 #define F_RS_FEC_DEGRADE_OPTION_ENA    V_RS_FEC_DEGRADE_OPTION_ENA(1U)
78973 
78974 #define A_MAC_MTIP_RS_FEC_STATUS_0_0 0x38e04
78975 
78976 #define S_FEC_STATUS_0_14    14
78977 #define V_FEC_STATUS_0_14(x) ((x) << S_FEC_STATUS_0_14)
78978 #define F_FEC_STATUS_0_14    V_FEC_STATUS_0_14(1U)
78979 
78980 #define S_FEC_STATUS_0_11    8
78981 #define M_FEC_STATUS_0_11    0xfU
78982 #define V_FEC_STATUS_0_11(x) ((x) << S_FEC_STATUS_0_11)
78983 #define G_FEC_STATUS_0_11(x) (((x) >> S_FEC_STATUS_0_11) & M_FEC_STATUS_0_11)
78984 
78985 #define S_RS_FEC_DEGRADE_SER_RECEIVED0_0    7
78986 #define V_RS_FEC_DEGRADE_SER_RECEIVED0_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED0_0)
78987 #define F_RS_FEC_DEGRADE_SER_RECEIVED0_0    V_RS_FEC_DEGRADE_SER_RECEIVED0_0(1U)
78988 
78989 #define S_RS_FEC_DEGRADE_SER_RECEIVED0_1    6
78990 #define V_RS_FEC_DEGRADE_SER_RECEIVED0_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED0_1)
78991 #define F_RS_FEC_DEGRADE_SER_RECEIVED0_1    V_RS_FEC_DEGRADE_SER_RECEIVED0_1(1U)
78992 
78993 #define S_RS_FEC_DEGRADE_SER_RECEIVED0_2    5
78994 #define V_RS_FEC_DEGRADE_SER_RECEIVED0_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED0_2)
78995 #define F_RS_FEC_DEGRADE_SER_RECEIVED0_2    V_RS_FEC_DEGRADE_SER_RECEIVED0_2(1U)
78996 
78997 #define S_FEC_STATUS_0_4    4
78998 #define V_FEC_STATUS_0_4(x) ((x) << S_FEC_STATUS_0_4)
78999 #define F_FEC_STATUS_0_4    V_FEC_STATUS_0_4(1U)
79000 
79001 #define S_FEC_STATUS_0_3    3
79002 #define V_FEC_STATUS_0_3(x) ((x) << S_FEC_STATUS_0_3)
79003 #define F_FEC_STATUS_0_3    V_FEC_STATUS_0_3(1U)
79004 
79005 #define S_FEC_STATUS_0_2    2
79006 #define V_FEC_STATUS_0_2(x) ((x) << S_FEC_STATUS_0_2)
79007 #define F_FEC_STATUS_0_2    V_FEC_STATUS_0_2(1U)
79008 
79009 #define S_FEC_STATUS_0_1    1
79010 #define V_FEC_STATUS_0_1(x) ((x) << S_FEC_STATUS_0_1)
79011 #define F_FEC_STATUS_0_1    V_FEC_STATUS_0_1(1U)
79012 
79013 #define S_FEC_STATUS_0_0    0
79014 #define V_FEC_STATUS_0_0(x) ((x) << S_FEC_STATUS_0_0)
79015 #define F_FEC_STATUS_0_0    V_FEC_STATUS_0_0(1U)
79016 
79017 #define A_MAC_MTIP_RS_FEC_CCW_LO_0_0 0x38e08
79018 #define A_MAC_MTIP_RS_FEC_CCW_HI_0_0 0x38e0c
79019 #define A_MAC_MTIP_RS_FEC_NCCW_LO_0_0 0x38e10
79020 #define A_MAC_MTIP_RS_FEC_NCCW_HI_0_0 0x38e14
79021 #define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_0 0x38e18
79022 #define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_0 0x38e1c
79023 
79024 #define S_DEC_TRESH    0
79025 #define M_DEC_TRESH    0x3fU
79026 #define V_DEC_TRESH(x) ((x) << S_DEC_TRESH)
79027 #define G_DEC_TRESH(x) (((x) >> S_DEC_TRESH) & M_DEC_TRESH)
79028 
79029 #define A_MAC_MTIP_RS_FEC_CONTROL_0_1 0x38e20
79030 #define A_MAC_MTIP_RS_FEC_STATUS_0_1 0x38e24
79031 
79032 #define S_FEC_STATUS_1_14    14
79033 #define V_FEC_STATUS_1_14(x) ((x) << S_FEC_STATUS_1_14)
79034 #define F_FEC_STATUS_1_14    V_FEC_STATUS_1_14(1U)
79035 
79036 #define S_FEC_STATUS_1_11    8
79037 #define M_FEC_STATUS_1_11    0xfU
79038 #define V_FEC_STATUS_1_11(x) ((x) << S_FEC_STATUS_1_11)
79039 #define G_FEC_STATUS_1_11(x) (((x) >> S_FEC_STATUS_1_11) & M_FEC_STATUS_1_11)
79040 
79041 #define S_RS_FEC_DEGRADE_SER_RECEIVED1_0    7
79042 #define V_RS_FEC_DEGRADE_SER_RECEIVED1_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED1_0)
79043 #define F_RS_FEC_DEGRADE_SER_RECEIVED1_0    V_RS_FEC_DEGRADE_SER_RECEIVED1_0(1U)
79044 
79045 #define S_RS_FEC_DEGRADE_SER_RECEIVED1_1    6
79046 #define V_RS_FEC_DEGRADE_SER_RECEIVED1_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED1_1)
79047 #define F_RS_FEC_DEGRADE_SER_RECEIVED1_1    V_RS_FEC_DEGRADE_SER_RECEIVED1_1(1U)
79048 
79049 #define S_RS_FEC_DEGRADE_SER_RECEIVED1_2    5
79050 #define V_RS_FEC_DEGRADE_SER_RECEIVED1_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED1_2)
79051 #define F_RS_FEC_DEGRADE_SER_RECEIVED1_2    V_RS_FEC_DEGRADE_SER_RECEIVED1_2(1U)
79052 
79053 #define S_FEC_STATUS_1_4    4
79054 #define V_FEC_STATUS_1_4(x) ((x) << S_FEC_STATUS_1_4)
79055 #define F_FEC_STATUS_1_4    V_FEC_STATUS_1_4(1U)
79056 
79057 #define S_FEC_STATUS_1_3    3
79058 #define V_FEC_STATUS_1_3(x) ((x) << S_FEC_STATUS_1_3)
79059 #define F_FEC_STATUS_1_3    V_FEC_STATUS_1_3(1U)
79060 
79061 #define S_FEC_STATUS_1_2    2
79062 #define V_FEC_STATUS_1_2(x) ((x) << S_FEC_STATUS_1_2)
79063 #define F_FEC_STATUS_1_2    V_FEC_STATUS_1_2(1U)
79064 
79065 #define S_FEC_STATUS_1_1    1
79066 #define V_FEC_STATUS_1_1(x) ((x) << S_FEC_STATUS_1_1)
79067 #define F_FEC_STATUS_1_1    V_FEC_STATUS_1_1(1U)
79068 
79069 #define S_FEC_STATUS_1_0    0
79070 #define V_FEC_STATUS_1_0(x) ((x) << S_FEC_STATUS_1_0)
79071 #define F_FEC_STATUS_1_0    V_FEC_STATUS_1_0(1U)
79072 
79073 #define A_MAC_MTIP_RS_FEC_CCW_LO_0_1 0x38e28
79074 #define A_MAC_MTIP_RS_FEC_CCW_HI_0_1 0x38e2c
79075 #define A_MAC_MTIP_RS_FEC_NCCW_LO_0_1 0x38e30
79076 #define A_MAC_MTIP_RS_FEC_NCCW_HI_0_1 0x38e34
79077 #define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_1 0x38e38
79078 #define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_1 0x38e3c
79079 #define A_MAC_MTIP_RS_FEC_CONTROL_0_2 0x38e40
79080 #define A_MAC_MTIP_RS_FEC_STATUS_0_2 0x38e44
79081 
79082 #define S_FEC_STATUS_2_14    14
79083 #define V_FEC_STATUS_2_14(x) ((x) << S_FEC_STATUS_2_14)
79084 #define F_FEC_STATUS_2_14    V_FEC_STATUS_2_14(1U)
79085 
79086 #define S_FEC_STATUS_2_11    8
79087 #define M_FEC_STATUS_2_11    0xfU
79088 #define V_FEC_STATUS_2_11(x) ((x) << S_FEC_STATUS_2_11)
79089 #define G_FEC_STATUS_2_11(x) (((x) >> S_FEC_STATUS_2_11) & M_FEC_STATUS_2_11)
79090 
79091 #define S_RS_FEC_DEGRADE_SER_RECEIVED2_0    7
79092 #define V_RS_FEC_DEGRADE_SER_RECEIVED2_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED2_0)
79093 #define F_RS_FEC_DEGRADE_SER_RECEIVED2_0    V_RS_FEC_DEGRADE_SER_RECEIVED2_0(1U)
79094 
79095 #define S_RS_FEC_DEGRADE_SER_RECEIVED2_1    6
79096 #define V_RS_FEC_DEGRADE_SER_RECEIVED2_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED2_1)
79097 #define F_RS_FEC_DEGRADE_SER_RECEIVED2_1    V_RS_FEC_DEGRADE_SER_RECEIVED2_1(1U)
79098 
79099 #define S_RS_FEC_DEGRADE_SER_RECEIVED2_2    5
79100 #define V_RS_FEC_DEGRADE_SER_RECEIVED2_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED2_2)
79101 #define F_RS_FEC_DEGRADE_SER_RECEIVED2_2    V_RS_FEC_DEGRADE_SER_RECEIVED2_2(1U)
79102 
79103 #define S_FEC_STATUS_2_4    4
79104 #define V_FEC_STATUS_2_4(x) ((x) << S_FEC_STATUS_2_4)
79105 #define F_FEC_STATUS_2_4    V_FEC_STATUS_2_4(1U)
79106 
79107 #define S_FEC_STATUS_2_3    3
79108 #define V_FEC_STATUS_2_3(x) ((x) << S_FEC_STATUS_2_3)
79109 #define F_FEC_STATUS_2_3    V_FEC_STATUS_2_3(1U)
79110 
79111 #define S_FEC_STATUS_2_2    2
79112 #define V_FEC_STATUS_2_2(x) ((x) << S_FEC_STATUS_2_2)
79113 #define F_FEC_STATUS_2_2    V_FEC_STATUS_2_2(1U)
79114 
79115 #define S_FEC_STATUS_2_1    1
79116 #define V_FEC_STATUS_2_1(x) ((x) << S_FEC_STATUS_2_1)
79117 #define F_FEC_STATUS_2_1    V_FEC_STATUS_2_1(1U)
79118 
79119 #define S_FEC_STATUS_2_0    0
79120 #define V_FEC_STATUS_2_0(x) ((x) << S_FEC_STATUS_2_0)
79121 #define F_FEC_STATUS_2_0    V_FEC_STATUS_2_0(1U)
79122 
79123 #define A_MAC_MTIP_RS_FEC_CCW_LO_0_2 0x38e48
79124 #define A_MAC_MTIP_RS_FEC_CCW_HI_0_2 0x38e4c
79125 #define A_MAC_MTIP_RS_FEC_NCCW_LO_0_2 0x38e50
79126 #define A_MAC_MTIP_RS_FEC_NCCW_HI_0_2 0x38e54
79127 #define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_2 0x38e58
79128 #define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_2 0x38e5c
79129 #define A_MAC_MTIP_RS_FEC_CONTROL_0_3 0x38e60
79130 #define A_MAC_MTIP_RS_FEC_STATUS_0_3 0x38e64
79131 
79132 #define S_FEC_STATUS_3_14    14
79133 #define V_FEC_STATUS_3_14(x) ((x) << S_FEC_STATUS_3_14)
79134 #define F_FEC_STATUS_3_14    V_FEC_STATUS_3_14(1U)
79135 
79136 #define S_FEC_STATUS_3_11    8
79137 #define M_FEC_STATUS_3_11    0xfU
79138 #define V_FEC_STATUS_3_11(x) ((x) << S_FEC_STATUS_3_11)
79139 #define G_FEC_STATUS_3_11(x) (((x) >> S_FEC_STATUS_3_11) & M_FEC_STATUS_3_11)
79140 
79141 #define S_RS_FEC_DEGRADE_SER_RECEIVED3_0    7
79142 #define V_RS_FEC_DEGRADE_SER_RECEIVED3_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED3_0)
79143 #define F_RS_FEC_DEGRADE_SER_RECEIVED3_0    V_RS_FEC_DEGRADE_SER_RECEIVED3_0(1U)
79144 
79145 #define S_RS_FEC_DEGRADE_SER_RECEIVED3_1    6
79146 #define V_RS_FEC_DEGRADE_SER_RECEIVED3_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED3_1)
79147 #define F_RS_FEC_DEGRADE_SER_RECEIVED3_1    V_RS_FEC_DEGRADE_SER_RECEIVED3_1(1U)
79148 
79149 #define S_RS_FEC_DEGRADE_SER_RECEIVED3_2    5
79150 #define V_RS_FEC_DEGRADE_SER_RECEIVED3_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED3_2)
79151 #define F_RS_FEC_DEGRADE_SER_RECEIVED3_2    V_RS_FEC_DEGRADE_SER_RECEIVED3_2(1U)
79152 
79153 #define S_FEC_STATUS_3_4    4
79154 #define V_FEC_STATUS_3_4(x) ((x) << S_FEC_STATUS_3_4)
79155 #define F_FEC_STATUS_3_4    V_FEC_STATUS_3_4(1U)
79156 
79157 #define S_FEC_STATUS_3_3    3
79158 #define V_FEC_STATUS_3_3(x) ((x) << S_FEC_STATUS_3_3)
79159 #define F_FEC_STATUS_3_3    V_FEC_STATUS_3_3(1U)
79160 
79161 #define S_FEC_STATUS_3_2    2
79162 #define V_FEC_STATUS_3_2(x) ((x) << S_FEC_STATUS_3_2)
79163 #define F_FEC_STATUS_3_2    V_FEC_STATUS_3_2(1U)
79164 
79165 #define S_FEC_STATUS_3_1    1
79166 #define V_FEC_STATUS_3_1(x) ((x) << S_FEC_STATUS_3_1)
79167 #define F_FEC_STATUS_3_1    V_FEC_STATUS_3_1(1U)
79168 
79169 #define S_FEC_STATUS_3_0    0
79170 #define V_FEC_STATUS_3_0(x) ((x) << S_FEC_STATUS_3_0)
79171 #define F_FEC_STATUS_3_0    V_FEC_STATUS_3_0(1U)
79172 
79173 #define A_MAC_MTIP_RS_FEC_CCW_LO_0_3 0x38e68
79174 #define A_MAC_MTIP_RS_FEC_CCW_HI_0_3 0x38e6c
79175 #define A_MAC_MTIP_RS_FEC_NCCW_LO_0_3 0x38e70
79176 #define A_MAC_MTIP_RS_FEC_NCCW_HI_0_3 0x38e74
79177 #define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_3 0x38e78
79178 #define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_3 0x38e7c
79179 #define A_MAC_MTIP_RS_FEC_CONTROL_0_4 0x38e80
79180 #define A_MAC_MTIP_RS_FEC_STATUS_0_4 0x38e84
79181 
79182 #define S_FEC_STATUS_4_14    14
79183 #define V_FEC_STATUS_4_14(x) ((x) << S_FEC_STATUS_4_14)
79184 #define F_FEC_STATUS_4_14    V_FEC_STATUS_4_14(1U)
79185 
79186 #define S_FEC_STATUS_4_11    8
79187 #define M_FEC_STATUS_4_11    0xfU
79188 #define V_FEC_STATUS_4_11(x) ((x) << S_FEC_STATUS_4_11)
79189 #define G_FEC_STATUS_4_11(x) (((x) >> S_FEC_STATUS_4_11) & M_FEC_STATUS_4_11)
79190 
79191 #define S_RS_FEC_DEGRADE_SER_RECEIVED4_0    7
79192 #define V_RS_FEC_DEGRADE_SER_RECEIVED4_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED4_0)
79193 #define F_RS_FEC_DEGRADE_SER_RECEIVED4_0    V_RS_FEC_DEGRADE_SER_RECEIVED4_0(1U)
79194 
79195 #define S_RS_FEC_DEGRADE_SER_RECEIVED4_1    6
79196 #define V_RS_FEC_DEGRADE_SER_RECEIVED4_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED4_1)
79197 #define F_RS_FEC_DEGRADE_SER_RECEIVED4_1    V_RS_FEC_DEGRADE_SER_RECEIVED4_1(1U)
79198 
79199 #define S_RS_FEC_DEGRADE_SER_RECEIVED4_2    5
79200 #define V_RS_FEC_DEGRADE_SER_RECEIVED4_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED4_2)
79201 #define F_RS_FEC_DEGRADE_SER_RECEIVED4_2    V_RS_FEC_DEGRADE_SER_RECEIVED4_2(1U)
79202 
79203 #define S_FEC_STATUS_4_4    4
79204 #define V_FEC_STATUS_4_4(x) ((x) << S_FEC_STATUS_4_4)
79205 #define F_FEC_STATUS_4_4    V_FEC_STATUS_4_4(1U)
79206 
79207 #define S_FEC_STATUS_4_3    3
79208 #define V_FEC_STATUS_4_3(x) ((x) << S_FEC_STATUS_4_3)
79209 #define F_FEC_STATUS_4_3    V_FEC_STATUS_4_3(1U)
79210 
79211 #define S_FEC_STATUS_4_2    2
79212 #define V_FEC_STATUS_4_2(x) ((x) << S_FEC_STATUS_4_2)
79213 #define F_FEC_STATUS_4_2    V_FEC_STATUS_4_2(1U)
79214 
79215 #define S_FEC_STATUS_4_1    1
79216 #define V_FEC_STATUS_4_1(x) ((x) << S_FEC_STATUS_4_1)
79217 #define F_FEC_STATUS_4_1    V_FEC_STATUS_4_1(1U)
79218 
79219 #define S_FEC_STATUS_4_0    0
79220 #define V_FEC_STATUS_4_0(x) ((x) << S_FEC_STATUS_4_0)
79221 #define F_FEC_STATUS_4_0    V_FEC_STATUS_4_0(1U)
79222 
79223 #define A_MAC_MTIP_RS_FEC_CCW_LO_0_4 0x38e88
79224 #define A_MAC_MTIP_RS_FEC_CCW_HI_0_4 0x38e8c
79225 #define A_MAC_MTIP_RS_FEC_NCCW_LO_0_4 0x38e90
79226 #define A_MAC_MTIP_RS_FEC_NCCW_HI_0_4 0x38e94
79227 #define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_4 0x38e98
79228 #define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_4 0x38e9c
79229 #define A_MAC_MTIP_RS_FEC_CONTROL_0_5 0x38ea0
79230 #define A_MAC_MTIP_RS_FEC_STATUS_0_5 0x38ea4
79231 
79232 #define S_FEC_STATUS_5_14    14
79233 #define V_FEC_STATUS_5_14(x) ((x) << S_FEC_STATUS_5_14)
79234 #define F_FEC_STATUS_5_14    V_FEC_STATUS_5_14(1U)
79235 
79236 #define S_FEC_STATUS_5_11    8
79237 #define M_FEC_STATUS_5_11    0xfU
79238 #define V_FEC_STATUS_5_11(x) ((x) << S_FEC_STATUS_5_11)
79239 #define G_FEC_STATUS_5_11(x) (((x) >> S_FEC_STATUS_5_11) & M_FEC_STATUS_5_11)
79240 
79241 #define S_RS_FEC_DEGRADE_SER_RECEIVED5_0    7
79242 #define V_RS_FEC_DEGRADE_SER_RECEIVED5_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED5_0)
79243 #define F_RS_FEC_DEGRADE_SER_RECEIVED5_0    V_RS_FEC_DEGRADE_SER_RECEIVED5_0(1U)
79244 
79245 #define S_RS_FEC_DEGRADE_SER_RECEIVED5_1    6
79246 #define V_RS_FEC_DEGRADE_SER_RECEIVED5_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED5_1)
79247 #define F_RS_FEC_DEGRADE_SER_RECEIVED5_1    V_RS_FEC_DEGRADE_SER_RECEIVED5_1(1U)
79248 
79249 #define S_RS_FEC_DEGRADE_SER_RECEIVED5_2    5
79250 #define V_RS_FEC_DEGRADE_SER_RECEIVED5_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED5_2)
79251 #define F_RS_FEC_DEGRADE_SER_RECEIVED5_2    V_RS_FEC_DEGRADE_SER_RECEIVED5_2(1U)
79252 
79253 #define S_FEC_STATUS_5_4    4
79254 #define V_FEC_STATUS_5_4(x) ((x) << S_FEC_STATUS_5_4)
79255 #define F_FEC_STATUS_5_4    V_FEC_STATUS_5_4(1U)
79256 
79257 #define S_FEC_STATUS_5_3    3
79258 #define V_FEC_STATUS_5_3(x) ((x) << S_FEC_STATUS_5_3)
79259 #define F_FEC_STATUS_5_3    V_FEC_STATUS_5_3(1U)
79260 
79261 #define S_FEC_STATUS_5_2    2
79262 #define V_FEC_STATUS_5_2(x) ((x) << S_FEC_STATUS_5_2)
79263 #define F_FEC_STATUS_5_2    V_FEC_STATUS_5_2(1U)
79264 
79265 #define S_FEC_STATUS_5_1    1
79266 #define V_FEC_STATUS_5_1(x) ((x) << S_FEC_STATUS_5_1)
79267 #define F_FEC_STATUS_5_1    V_FEC_STATUS_5_1(1U)
79268 
79269 #define S_FEC_STATUS_5_0    0
79270 #define V_FEC_STATUS_5_0(x) ((x) << S_FEC_STATUS_5_0)
79271 #define F_FEC_STATUS_5_0    V_FEC_STATUS_5_0(1U)
79272 
79273 #define A_MAC_MTIP_RS_FEC_CCW_LO_0_5 0x38ea8
79274 #define A_MAC_MTIP_RS_FEC_CCW_HI_0_5 0x38eac
79275 #define A_MAC_MTIP_RS_FEC_NCCW_LO_0_5 0x38eb0
79276 #define A_MAC_MTIP_RS_FEC_NCCW_HI_0_5 0x38eb4
79277 #define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_5 0x38eb8
79278 #define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_5 0x38ebc
79279 #define A_MAC_MTIP_RS_FEC_CONTROL_0_6 0x38ec0
79280 #define A_MAC_MTIP_RS_FEC_STATUS_0_6 0x38ec4
79281 
79282 #define S_FEC_STATUS_6_14    14
79283 #define V_FEC_STATUS_6_14(x) ((x) << S_FEC_STATUS_6_14)
79284 #define F_FEC_STATUS_6_14    V_FEC_STATUS_6_14(1U)
79285 
79286 #define S_FEC_STATUS_6_11    8
79287 #define M_FEC_STATUS_6_11    0xfU
79288 #define V_FEC_STATUS_6_11(x) ((x) << S_FEC_STATUS_6_11)
79289 #define G_FEC_STATUS_6_11(x) (((x) >> S_FEC_STATUS_6_11) & M_FEC_STATUS_6_11)
79290 
79291 #define S_RS_FEC_DEGRADE_SER_RECEIVED6_0    7
79292 #define V_RS_FEC_DEGRADE_SER_RECEIVED6_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED6_0)
79293 #define F_RS_FEC_DEGRADE_SER_RECEIVED6_0    V_RS_FEC_DEGRADE_SER_RECEIVED6_0(1U)
79294 
79295 #define S_RS_FEC_DEGRADE_SER_RECEIVED6_1    6
79296 #define V_RS_FEC_DEGRADE_SER_RECEIVED6_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED6_1)
79297 #define F_RS_FEC_DEGRADE_SER_RECEIVED6_1    V_RS_FEC_DEGRADE_SER_RECEIVED6_1(1U)
79298 
79299 #define S_RS_FEC_DEGRADE_SER_RECEIVED6_2    5
79300 #define V_RS_FEC_DEGRADE_SER_RECEIVED6_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED6_2)
79301 #define F_RS_FEC_DEGRADE_SER_RECEIVED6_2    V_RS_FEC_DEGRADE_SER_RECEIVED6_2(1U)
79302 
79303 #define S_FEC_STATUS_6_4    4
79304 #define V_FEC_STATUS_6_4(x) ((x) << S_FEC_STATUS_6_4)
79305 #define F_FEC_STATUS_6_4    V_FEC_STATUS_6_4(1U)
79306 
79307 #define S_FEC_STATUS_6_3    3
79308 #define V_FEC_STATUS_6_3(x) ((x) << S_FEC_STATUS_6_3)
79309 #define F_FEC_STATUS_6_3    V_FEC_STATUS_6_3(1U)
79310 
79311 #define S_FEC_STATUS_6_2    2
79312 #define V_FEC_STATUS_6_2(x) ((x) << S_FEC_STATUS_6_2)
79313 #define F_FEC_STATUS_6_2    V_FEC_STATUS_6_2(1U)
79314 
79315 #define S_FEC_STATUS_6_1    1
79316 #define V_FEC_STATUS_6_1(x) ((x) << S_FEC_STATUS_6_1)
79317 #define F_FEC_STATUS_6_1    V_FEC_STATUS_6_1(1U)
79318 
79319 #define S_FEC_STATUS_6_0    0
79320 #define V_FEC_STATUS_6_0(x) ((x) << S_FEC_STATUS_6_0)
79321 #define F_FEC_STATUS_6_0    V_FEC_STATUS_6_0(1U)
79322 
79323 #define A_MAC_MTIP_RS_FEC_CCW_LO_0_6 0x38ec8
79324 #define A_MAC_MTIP_RS_FEC_CCW_HI_0_6 0x38ecc
79325 #define A_MAC_MTIP_RS_FEC_NCCW_LO_0_6 0x38ed0
79326 #define A_MAC_MTIP_RS_FEC_NCCW_HI_0_6 0x38ed4
79327 #define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_6 0x38ed8
79328 #define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_6 0x38edc
79329 #define A_MAC_MTIP_RS_FEC_CONTROL_0_7 0x38ee0
79330 #define A_MAC_MTIP_RS_FEC_STATUS_0_7 0x38ee4
79331 
79332 #define S_FEC_STATUS_7_14    14
79333 #define V_FEC_STATUS_7_14(x) ((x) << S_FEC_STATUS_7_14)
79334 #define F_FEC_STATUS_7_14    V_FEC_STATUS_7_14(1U)
79335 
79336 #define S_FEC_STATUS_7_11    8
79337 #define M_FEC_STATUS_7_11    0xfU
79338 #define V_FEC_STATUS_7_11(x) ((x) << S_FEC_STATUS_7_11)
79339 #define G_FEC_STATUS_7_11(x) (((x) >> S_FEC_STATUS_7_11) & M_FEC_STATUS_7_11)
79340 
79341 #define S_RS_FEC_DEGRADE_SER_RECEIVED7_0    7
79342 #define V_RS_FEC_DEGRADE_SER_RECEIVED7_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED7_0)
79343 #define F_RS_FEC_DEGRADE_SER_RECEIVED7_0    V_RS_FEC_DEGRADE_SER_RECEIVED7_0(1U)
79344 
79345 #define S_RS_FEC_DEGRADE_SER_RECEIVED7_1    6
79346 #define V_RS_FEC_DEGRADE_SER_RECEIVED7_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED7_1)
79347 #define F_RS_FEC_DEGRADE_SER_RECEIVED7_1    V_RS_FEC_DEGRADE_SER_RECEIVED7_1(1U)
79348 
79349 #define S_RS_FEC_DEGRADE_SER_RECEIVED7_2    5
79350 #define V_RS_FEC_DEGRADE_SER_RECEIVED7_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED7_2)
79351 #define F_RS_FEC_DEGRADE_SER_RECEIVED7_2    V_RS_FEC_DEGRADE_SER_RECEIVED7_2(1U)
79352 
79353 #define S_FEC_STATUS_7_4    4
79354 #define V_FEC_STATUS_7_4(x) ((x) << S_FEC_STATUS_7_4)
79355 #define F_FEC_STATUS_7_4    V_FEC_STATUS_7_4(1U)
79356 
79357 #define S_FEC_STATUS_7_3    3
79358 #define V_FEC_STATUS_7_3(x) ((x) << S_FEC_STATUS_7_3)
79359 #define F_FEC_STATUS_7_3    V_FEC_STATUS_7_3(1U)
79360 
79361 #define S_FEC_STATUS_7_2    2
79362 #define V_FEC_STATUS_7_2(x) ((x) << S_FEC_STATUS_7_2)
79363 #define F_FEC_STATUS_7_2    V_FEC_STATUS_7_2(1U)
79364 
79365 #define S_FEC_STATUS_7_1    1
79366 #define V_FEC_STATUS_7_1(x) ((x) << S_FEC_STATUS_7_1)
79367 #define F_FEC_STATUS_7_1    V_FEC_STATUS_7_1(1U)
79368 
79369 #define S_FEC_STATUS_7_0    0
79370 #define V_FEC_STATUS_7_0(x) ((x) << S_FEC_STATUS_7_0)
79371 #define F_FEC_STATUS_7_0    V_FEC_STATUS_7_0(1U)
79372 
79373 #define A_MAC_MTIP_RS_FEC_CCW_LO_0_7 0x38ee8
79374 #define A_MAC_MTIP_RS_FEC_CCW_HI_0_7 0x38eec
79375 #define A_MAC_MTIP_RS_FEC_NCCW_LO_0_7 0x38ef0
79376 #define A_MAC_MTIP_RS_FEC_NCCW_HI_0_7 0x38ef4
79377 #define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_7 0x38ef8
79378 #define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_7 0x38efc
79379 #define A_MAC_MTIP_RS_FEC_HISER_CW 0x38f00
79380 
79381 #define S_HISER_CW    0
79382 #define M_HISER_CW    0xffffU
79383 #define V_HISER_CW(x) ((x) << S_HISER_CW)
79384 #define G_HISER_CW(x) (((x) >> S_HISER_CW) & M_HISER_CW)
79385 
79386 #define A_MAC_MTIP_RS_FEC_HISER_THRESH 0x38f04
79387 
79388 #define S_HISER_THRESH    0
79389 #define M_HISER_THRESH    0xffffU
79390 #define V_HISER_THRESH(x) ((x) << S_HISER_THRESH)
79391 #define G_HISER_THRESH(x) (((x) >> S_HISER_THRESH) & M_HISER_THRESH)
79392 
79393 #define A_MAC_MTIP_RS_FEC_HISER_TIME 0x38f08
79394 
79395 #define S_HISER_TIME    0
79396 #define M_HISER_TIME    0xffffU
79397 #define V_HISER_TIME(x) ((x) << S_HISER_TIME)
79398 #define G_HISER_TIME(x) (((x) >> S_HISER_TIME) & M_HISER_TIME)
79399 
79400 #define A_MAC_MTIP_RS_DEGRADE_SET_CW 0x38f10
79401 
79402 #define S_DEGRADE_SET_CW    0
79403 #define M_DEGRADE_SET_CW    0xffffU
79404 #define V_DEGRADE_SET_CW(x) ((x) << S_DEGRADE_SET_CW)
79405 #define G_DEGRADE_SET_CW(x) (((x) >> S_DEGRADE_SET_CW) & M_DEGRADE_SET_CW)
79406 
79407 #define A_MAC_MTIP_RS_DEGRADE_SET_CW_HI 0x38f14
79408 
79409 #define S_DEGRADE_SET_CW_HI    0
79410 #define M_DEGRADE_SET_CW_HI    0xffffU
79411 #define V_DEGRADE_SET_CW_HI(x) ((x) << S_DEGRADE_SET_CW_HI)
79412 #define G_DEGRADE_SET_CW_HI(x) (((x) >> S_DEGRADE_SET_CW_HI) & M_DEGRADE_SET_CW_HI)
79413 
79414 #define A_MAC_MTIP_RS_DEGRADE_SET_THRESH 0x38f18
79415 
79416 #define S_DEGRADE_SET_THRESH    0
79417 #define M_DEGRADE_SET_THRESH    0xffffU
79418 #define V_DEGRADE_SET_THRESH(x) ((x) << S_DEGRADE_SET_THRESH)
79419 #define G_DEGRADE_SET_THRESH(x) (((x) >> S_DEGRADE_SET_THRESH) & M_DEGRADE_SET_THRESH)
79420 
79421 #define A_MAC_MTIP_RS_DEGRADE_SET_THRESH_HI 0x38f1c
79422 
79423 #define S_DEGRADE_SET_THRESH_HI    0
79424 #define M_DEGRADE_SET_THRESH_HI    0xffffU
79425 #define V_DEGRADE_SET_THRESH_HI(x) ((x) << S_DEGRADE_SET_THRESH_HI)
79426 #define G_DEGRADE_SET_THRESH_HI(x) (((x) >> S_DEGRADE_SET_THRESH_HI) & M_DEGRADE_SET_THRESH_HI)
79427 
79428 #define A_MAC_MTIP_RS_DEGRADE_CLEAR 0x38f20
79429 
79430 #define S_DEGRADE_SET_CLEAR    0
79431 #define M_DEGRADE_SET_CLEAR    0xffffU
79432 #define V_DEGRADE_SET_CLEAR(x) ((x) << S_DEGRADE_SET_CLEAR)
79433 #define G_DEGRADE_SET_CLEAR(x) (((x) >> S_DEGRADE_SET_CLEAR) & M_DEGRADE_SET_CLEAR)
79434 
79435 #define A_MAC_MTIP_RS_DEGRADE_SET_CLEAR_HI 0x38f24
79436 
79437 #define S_DEGRADE_SET_CLEAR_HI    0
79438 #define M_DEGRADE_SET_CLEAR_HI    0xffffU
79439 #define V_DEGRADE_SET_CLEAR_HI(x) ((x) << S_DEGRADE_SET_CLEAR_HI)
79440 #define G_DEGRADE_SET_CLEAR_HI(x) (((x) >> S_DEGRADE_SET_CLEAR_HI) & M_DEGRADE_SET_CLEAR_HI)
79441 
79442 #define A_MAC_MTIP_RS_DEGRADE_CLEAR_THRESH 0x38f28
79443 
79444 #define S_DEGRADE_SET_CLEAR_THRESH    0
79445 #define M_DEGRADE_SET_CLEAR_THRESH    0xffffU
79446 #define V_DEGRADE_SET_CLEAR_THRESH(x) ((x) << S_DEGRADE_SET_CLEAR_THRESH)
79447 #define G_DEGRADE_SET_CLEAR_THRESH(x) (((x) >> S_DEGRADE_SET_CLEAR_THRESH) & M_DEGRADE_SET_CLEAR_THRESH)
79448 
79449 #define A_MAC_MTIP_RS_DEGRADE_SET_CLEAR_THRESH_HI 0x38f2c
79450 
79451 #define S_DEGRADE_SET_CLEAR_THRESH_HI    0
79452 #define M_DEGRADE_SET_CLEAR_THRESH_HI    0xffffU
79453 #define V_DEGRADE_SET_CLEAR_THRESH_HI(x) ((x) << S_DEGRADE_SET_CLEAR_THRESH_HI)
79454 #define G_DEGRADE_SET_CLEAR_THRESH_HI(x) (((x) >> S_DEGRADE_SET_CLEAR_THRESH_HI) & M_DEGRADE_SET_CLEAR_THRESH_HI)
79455 
79456 #define A_MAC_MTIP_RS_VL0_0 0x38f80
79457 #define A_MAC_MTIP_RS_VL0_1 0x38f84
79458 #define A_MAC_MTIP_RS_VL1_0 0x38f88
79459 #define A_MAC_MTIP_RS_VL1_1 0x38f8c
79460 #define A_MAC_MTIP_RS_VL2_0 0x38f90
79461 #define A_MAC_MTIP_RS_VL2_1 0x38f94
79462 #define A_MAC_MTIP_RS_VL3_0 0x38f98
79463 #define A_MAC_MTIP_RS_VL3_1 0x38f9c
79464 #define A_MAC_MTIP_RS_VL4_0 0x38fa0
79465 #define A_MAC_MTIP_RS_VL4_1 0x38fa4
79466 #define A_MAC_MTIP_RS_VL5_0 0x38fa8
79467 #define A_MAC_MTIP_RS_VL5_1 0x38fac
79468 #define A_MAC_MTIP_RS_VL6_0 0x38fb0
79469 #define A_MAC_MTIP_RS_VL6_1 0x38fb4
79470 #define A_MAC_MTIP_RS_VL7_0 0x38fb8
79471 #define A_MAC_MTIP_RS_VL7_1 0x38fbc
79472 #define A_MAC_MTIP_RS_VL8_0 0x38fc0
79473 #define A_MAC_MTIP_RS_VL8_1 0x38fc4
79474 #define A_MAC_MTIP_RS_VL9_0 0x38fc8
79475 #define A_MAC_MTIP_RS_VL9_1 0x38fcc
79476 #define A_MAC_MTIP_RS_VL10_0 0x38fd0
79477 #define A_MAC_MTIP_RS_VL10_1 0x38fd4
79478 #define A_MAC_MTIP_RS_VL11_0 0x38fd8
79479 #define A_MAC_MTIP_RS_VL11_1 0x38fdc
79480 #define A_MAC_MTIP_RS_VL12_0 0x38fe0
79481 #define A_MAC_MTIP_RS_VL12_1 0x38fe4
79482 #define A_MAC_MTIP_RS_VL13_0 0x38fe8
79483 #define A_MAC_MTIP_RS_VL13_1 0x38fec
79484 #define A_MAC_MTIP_RS_VL14_0 0x38ff0
79485 #define A_MAC_MTIP_RS_VL14_1 0x38ff4
79486 #define A_MAC_MTIP_RS_VL15_0 0x38ff8
79487 #define A_MAC_MTIP_RS_VL15_1 0x38ffc
79488 #define A_MAC_MTIP_RS_FEC_SYMBLERR0_LO 0x39000
79489 #define A_MAC_MTIP_RS_FEC_SYMBLERR0_HI 0x39004
79490 #define A_MAC_MTIP_RS_FEC_SYMBLERR1_LO 0x39008
79491 #define A_MAC_MTIP_RS_FEC_SYMBLERR1_HI 0x3900c
79492 #define A_MAC_MTIP_RS_FEC_SYMBLERR2_LO 0x39010
79493 #define A_MAC_MTIP_RS_FEC_SYMBLERR2_HI 0x39014
79494 #define A_MAC_MTIP_RS_FEC_SYMBLERR3_LO 0x39018
79495 #define A_MAC_MTIP_RS_FEC_SYMBLERR3_HI 0x3901c
79496 #define A_MAC_MTIP_RS_FEC_SYMBLERR4_LO 0x39020
79497 
79498 #define S_RS_FEC_SYMBLERR4_LO    0
79499 #define V_RS_FEC_SYMBLERR4_LO(x) ((x) << S_RS_FEC_SYMBLERR4_LO)
79500 #define F_RS_FEC_SYMBLERR4_LO    V_RS_FEC_SYMBLERR4_LO(1U)
79501 
79502 #define A_MAC_MTIP_RS_FEC_SYMBLERR4_HI 0x39024
79503 
79504 #define S_RS_FEC_SYMBLERR4_HI    0
79505 #define V_RS_FEC_SYMBLERR4_HI(x) ((x) << S_RS_FEC_SYMBLERR4_HI)
79506 #define F_RS_FEC_SYMBLERR4_HI    V_RS_FEC_SYMBLERR4_HI(1U)
79507 
79508 #define A_MAC_MTIP_RS_FEC_SYMBLERR5_LO 0x39028
79509 
79510 #define S_RS_FEC_SYMBLERR5_LO    0
79511 #define V_RS_FEC_SYMBLERR5_LO(x) ((x) << S_RS_FEC_SYMBLERR5_LO)
79512 #define F_RS_FEC_SYMBLERR5_LO    V_RS_FEC_SYMBLERR5_LO(1U)
79513 
79514 #define A_MAC_MTIP_RS_FEC_SYMBLERR5_HI 0x3902c
79515 
79516 #define S_RS_FEC_SYMBLERR5_HI    0
79517 #define V_RS_FEC_SYMBLERR5_HI(x) ((x) << S_RS_FEC_SYMBLERR5_HI)
79518 #define F_RS_FEC_SYMBLERR5_HI    V_RS_FEC_SYMBLERR5_HI(1U)
79519 
79520 #define A_MAC_MTIP_RS_FEC_SYMBLERR6_LO 0x39030
79521 
79522 #define S_RS_FEC_SYMBLERR6_LO    0
79523 #define V_RS_FEC_SYMBLERR6_LO(x) ((x) << S_RS_FEC_SYMBLERR6_LO)
79524 #define F_RS_FEC_SYMBLERR6_LO    V_RS_FEC_SYMBLERR6_LO(1U)
79525 
79526 #define A_MAC_MTIP_RS_FEC_SYMBLERR6_HI 0x39034
79527 
79528 #define S_RS_FEC_SYMBLERR6_HI    0
79529 #define V_RS_FEC_SYMBLERR6_HI(x) ((x) << S_RS_FEC_SYMBLERR6_HI)
79530 #define F_RS_FEC_SYMBLERR6_HI    V_RS_FEC_SYMBLERR6_HI(1U)
79531 
79532 #define A_MAC_MTIP_RS_FEC_SYMBLERR7_LO 0x39038
79533 
79534 #define S_RS_FEC_SYMBLERR7_LO    0
79535 #define V_RS_FEC_SYMBLERR7_LO(x) ((x) << S_RS_FEC_SYMBLERR7_LO)
79536 #define F_RS_FEC_SYMBLERR7_LO    V_RS_FEC_SYMBLERR7_LO(1U)
79537 
79538 #define A_MAC_MTIP_RS_FEC_SYMBLERR7_HI 0x3903c
79539 
79540 #define S_RS_FEC_SYMBLERR7_HI    0
79541 #define V_RS_FEC_SYMBLERR7_HI(x) ((x) << S_RS_FEC_SYMBLERR7_HI)
79542 #define F_RS_FEC_SYMBLERR7_HI    V_RS_FEC_SYMBLERR7_HI(1U)
79543 
79544 #define A_MAC_MTIP_RS_FEC_SYMBLERR8_LO 0x39040
79545 
79546 #define S_RS_FEC_SYMBLERR8_LO    0
79547 #define V_RS_FEC_SYMBLERR8_LO(x) ((x) << S_RS_FEC_SYMBLERR8_LO)
79548 #define F_RS_FEC_SYMBLERR8_LO    V_RS_FEC_SYMBLERR8_LO(1U)
79549 
79550 #define A_MAC_MTIP_RS_FEC_SYMBLERR8_HI 0x39044
79551 
79552 #define S_RS_FEC_SYMBLERR8_HI    0
79553 #define V_RS_FEC_SYMBLERR8_HI(x) ((x) << S_RS_FEC_SYMBLERR8_HI)
79554 #define F_RS_FEC_SYMBLERR8_HI    V_RS_FEC_SYMBLERR8_HI(1U)
79555 
79556 #define A_MAC_MTIP_RS_FEC_SYMBLERR9_LO 0x39048
79557 
79558 #define S_RS_FEC_SYMBLERR9_LO    0
79559 #define V_RS_FEC_SYMBLERR9_LO(x) ((x) << S_RS_FEC_SYMBLERR9_LO)
79560 #define F_RS_FEC_SYMBLERR9_LO    V_RS_FEC_SYMBLERR9_LO(1U)
79561 
79562 #define A_MAC_MTIP_RS_FEC_SYMBLERR9_HI 0x3904c
79563 
79564 #define S_RS_FEC_SYMBLERR9_HI    0
79565 #define V_RS_FEC_SYMBLERR9_HI(x) ((x) << S_RS_FEC_SYMBLERR9_HI)
79566 #define F_RS_FEC_SYMBLERR9_HI    V_RS_FEC_SYMBLERR9_HI(1U)
79567 
79568 #define A_MAC_MTIP_RS_FEC_SYMBLERR10_LO 0x39050
79569 
79570 #define S_RS_FEC_SYMBLERR10_LO    0
79571 #define V_RS_FEC_SYMBLERR10_LO(x) ((x) << S_RS_FEC_SYMBLERR10_LO)
79572 #define F_RS_FEC_SYMBLERR10_LO    V_RS_FEC_SYMBLERR10_LO(1U)
79573 
79574 #define A_MAC_MTIP_RS_FEC_SYMBLERR10_HI 0x39054
79575 
79576 #define S_RS_FEC_SYMBLERR10_HI    0
79577 #define V_RS_FEC_SYMBLERR10_HI(x) ((x) << S_RS_FEC_SYMBLERR10_HI)
79578 #define F_RS_FEC_SYMBLERR10_HI    V_RS_FEC_SYMBLERR10_HI(1U)
79579 
79580 #define A_MAC_MTIP_RS_FEC_SYMBLERR11_LO 0x39058
79581 
79582 #define S_RS_FEC_SYMBLERR11_LO    0
79583 #define V_RS_FEC_SYMBLERR11_LO(x) ((x) << S_RS_FEC_SYMBLERR11_LO)
79584 #define F_RS_FEC_SYMBLERR11_LO    V_RS_FEC_SYMBLERR11_LO(1U)
79585 
79586 #define A_MAC_MTIP_RS_FEC_SYMBLERR11_HI 0x3905c
79587 
79588 #define S_RS_FEC_SYMBLERR11_HI    0
79589 #define V_RS_FEC_SYMBLERR11_HI(x) ((x) << S_RS_FEC_SYMBLERR11_HI)
79590 #define F_RS_FEC_SYMBLERR11_HI    V_RS_FEC_SYMBLERR11_HI(1U)
79591 
79592 #define A_MAC_MTIP_RS_FEC_SYMBLERR12_LO 0x39060
79593 
79594 #define S_RS_FEC_SYMBLERR12_LO    0
79595 #define V_RS_FEC_SYMBLERR12_LO(x) ((x) << S_RS_FEC_SYMBLERR12_LO)
79596 #define F_RS_FEC_SYMBLERR12_LO    V_RS_FEC_SYMBLERR12_LO(1U)
79597 
79598 #define A_MAC_MTIP_RS_FEC_SYMBLERR12_HI 0x39064
79599 
79600 #define S_RS_FEC_SYMBLERR12_HI    0
79601 #define V_RS_FEC_SYMBLERR12_HI(x) ((x) << S_RS_FEC_SYMBLERR12_HI)
79602 #define F_RS_FEC_SYMBLERR12_HI    V_RS_FEC_SYMBLERR12_HI(1U)
79603 
79604 #define A_MAC_MTIP_RS_FEC_SYMBLERR13_LO 0x39068
79605 
79606 #define S_RS_FEC_SYMBLERR13_LO    0
79607 #define V_RS_FEC_SYMBLERR13_LO(x) ((x) << S_RS_FEC_SYMBLERR13_LO)
79608 #define F_RS_FEC_SYMBLERR13_LO    V_RS_FEC_SYMBLERR13_LO(1U)
79609 
79610 #define A_MAC_MTIP_RS_FEC_SYMBLERR13_HI 0x3906c
79611 
79612 #define S_RS_FEC_SYMBLERR13_HI    0
79613 #define V_RS_FEC_SYMBLERR13_HI(x) ((x) << S_RS_FEC_SYMBLERR13_HI)
79614 #define F_RS_FEC_SYMBLERR13_HI    V_RS_FEC_SYMBLERR13_HI(1U)
79615 
79616 #define A_MAC_MTIP_RS_FEC_SYMBLERR14_LO 0x39070
79617 
79618 #define S_RS_FEC_SYMBLERR14_LO    0
79619 #define V_RS_FEC_SYMBLERR14_LO(x) ((x) << S_RS_FEC_SYMBLERR14_LO)
79620 #define F_RS_FEC_SYMBLERR14_LO    V_RS_FEC_SYMBLERR14_LO(1U)
79621 
79622 #define A_MAC_MTIP_RS_FEC_SYMBLERR14_HI 0x39074
79623 
79624 #define S_RS_FEC_SYMBLERR14_HI    0
79625 #define V_RS_FEC_SYMBLERR14_HI(x) ((x) << S_RS_FEC_SYMBLERR14_HI)
79626 #define F_RS_FEC_SYMBLERR14_HI    V_RS_FEC_SYMBLERR14_HI(1U)
79627 
79628 #define A_MAC_MTIP_RS_FEC_SYMBLERR15_LO 0x39078
79629 
79630 #define S_RS_FEC_SYMBLERR15_LO    0
79631 #define V_RS_FEC_SYMBLERR15_LO(x) ((x) << S_RS_FEC_SYMBLERR15_LO)
79632 #define F_RS_FEC_SYMBLERR15_LO    V_RS_FEC_SYMBLERR15_LO(1U)
79633 
79634 #define A_MAC_MTIP_RS_FEC_SYMBLERR15_HI 0x3907c
79635 
79636 #define S_RS_FEC_SYMBLERR15_HI    0
79637 #define V_RS_FEC_SYMBLERR15_HI(x) ((x) << S_RS_FEC_SYMBLERR15_HI)
79638 #define F_RS_FEC_SYMBLERR15_HI    V_RS_FEC_SYMBLERR15_HI(1U)
79639 
79640 #define A_MAC_MTIP_RS_FEC_VENDOR_CONTROL 0x39080
79641 #define A_MAC_MTIP_RS_FEC_VENDOR_INFO_1 0x39084
79642 
79643 #define S_VENDOR_INFO_1_AMPS_LOCK    0
79644 #define V_VENDOR_INFO_1_AMPS_LOCK(x) ((x) << S_VENDOR_INFO_1_AMPS_LOCK)
79645 #define F_VENDOR_INFO_1_AMPS_LOCK    V_VENDOR_INFO_1_AMPS_LOCK(1U)
79646 
79647 #define A_MAC_MTIP_RS_FEC_VENDOR_INFO_2 0x39088
79648 
79649 #define S_VENDOR_INFO_2_AMPS_LOCK    0
79650 #define M_VENDOR_INFO_2_AMPS_LOCK    0xffffU
79651 #define V_VENDOR_INFO_2_AMPS_LOCK(x) ((x) << S_VENDOR_INFO_2_AMPS_LOCK)
79652 #define G_VENDOR_INFO_2_AMPS_LOCK(x) (((x) >> S_VENDOR_INFO_2_AMPS_LOCK) & M_VENDOR_INFO_2_AMPS_LOCK)
79653 
79654 #define A_MAC_MTIP_RS_FEC_VENDOR_REVISION 0x3908c
79655 #define A_MAC_MTIP_RS_FEC_VENDOR_ALIGN_STATUS 0x39090
79656 
79657 #define S_RS_FEC_VENDOR_ALIGN_STATUS    0
79658 #define M_RS_FEC_VENDOR_ALIGN_STATUS    0xffffU
79659 #define V_RS_FEC_VENDOR_ALIGN_STATUS(x) ((x) << S_RS_FEC_VENDOR_ALIGN_STATUS)
79660 #define G_RS_FEC_VENDOR_ALIGN_STATUS(x) (((x) >> S_RS_FEC_VENDOR_ALIGN_STATUS) & M_RS_FEC_VENDOR_ALIGN_STATUS)
79661 
79662 #define A_MAC_MTIP_FEC74_FEC_ABILITY_0 0x39100
79663 
79664 #define S_FEC74_FEC_ABILITY_0_B1    1
79665 #define V_FEC74_FEC_ABILITY_0_B1(x) ((x) << S_FEC74_FEC_ABILITY_0_B1)
79666 #define F_FEC74_FEC_ABILITY_0_B1    V_FEC74_FEC_ABILITY_0_B1(1U)
79667 
79668 #define S_FEC74_FEC_ABILITY_0_B0    0
79669 #define V_FEC74_FEC_ABILITY_0_B0(x) ((x) << S_FEC74_FEC_ABILITY_0_B0)
79670 #define F_FEC74_FEC_ABILITY_0_B0    V_FEC74_FEC_ABILITY_0_B0(1U)
79671 
79672 #define A_MAC_MTIP_FEC74_FEC_CONTROL_0 0x39104
79673 
79674 #define S_FEC_ENABLE_ERROR_INDICATION    1
79675 #define V_FEC_ENABLE_ERROR_INDICATION(x) ((x) << S_FEC_ENABLE_ERROR_INDICATION)
79676 #define F_FEC_ENABLE_ERROR_INDICATION    V_FEC_ENABLE_ERROR_INDICATION(1U)
79677 
79678 #define S_T7_FEC_ENABLE    0
79679 #define V_T7_FEC_ENABLE(x) ((x) << S_T7_FEC_ENABLE)
79680 #define F_T7_FEC_ENABLE    V_T7_FEC_ENABLE(1U)
79681 
79682 #define A_MAC_MTIP_FEC74_FEC_STATUS_0 0x39108
79683 
79684 #define S_FEC_LOCKED_1    1
79685 #define V_FEC_LOCKED_1(x) ((x) << S_FEC_LOCKED_1)
79686 #define F_FEC_LOCKED_1    V_FEC_LOCKED_1(1U)
79687 
79688 #define A_MAC_MTIP_FEC74_VL0_CCW_LO_0 0x3910c
79689 
79690 #define S_VL0_CCW_LO    0
79691 #define M_VL0_CCW_LO    0xffffU
79692 #define V_VL0_CCW_LO(x) ((x) << S_VL0_CCW_LO)
79693 #define G_VL0_CCW_LO(x) (((x) >> S_VL0_CCW_LO) & M_VL0_CCW_LO)
79694 
79695 #define A_MAC_MTIP_FEC74_VL0_NCCW_LO_0 0x39110
79696 
79697 #define S_VL0_NCCW_LO    0
79698 #define M_VL0_NCCW_LO    0xffffU
79699 #define V_VL0_NCCW_LO(x) ((x) << S_VL0_NCCW_LO)
79700 #define G_VL0_NCCW_LO(x) (((x) >> S_VL0_NCCW_LO) & M_VL0_NCCW_LO)
79701 
79702 #define A_MAC_MTIP_FEC74_VL1_CCW_LO_0 0x39114
79703 
79704 #define S_VL1_CCW_LO    0
79705 #define M_VL1_CCW_LO    0xffffU
79706 #define V_VL1_CCW_LO(x) ((x) << S_VL1_CCW_LO)
79707 #define G_VL1_CCW_LO(x) (((x) >> S_VL1_CCW_LO) & M_VL1_CCW_LO)
79708 
79709 #define A_MAC_MTIP_FEC74_VL1_NCCW_LO_0 0x39118
79710 
79711 #define S_VL1_NCCW_LO    0
79712 #define M_VL1_NCCW_LO    0xffffU
79713 #define V_VL1_NCCW_LO(x) ((x) << S_VL1_NCCW_LO)
79714 #define G_VL1_NCCW_LO(x) (((x) >> S_VL1_NCCW_LO) & M_VL1_NCCW_LO)
79715 
79716 #define A_MAC_MTIP_FEC74_COUNTER_HI_0 0x3911c
79717 
79718 #define S_COUNTER_HI    0
79719 #define M_COUNTER_HI    0xffffU
79720 #define V_COUNTER_HI(x) ((x) << S_COUNTER_HI)
79721 #define G_COUNTER_HI(x) (((x) >> S_COUNTER_HI) & M_COUNTER_HI)
79722 
79723 #define A_MAC_MTIP_FEC74_FEC_ABILITY_1 0x39120
79724 
79725 #define S_FEC74_FEC_ABILITY_1_B1    1
79726 #define V_FEC74_FEC_ABILITY_1_B1(x) ((x) << S_FEC74_FEC_ABILITY_1_B1)
79727 #define F_FEC74_FEC_ABILITY_1_B1    V_FEC74_FEC_ABILITY_1_B1(1U)
79728 
79729 #define S_FEC74_FEC_ABILITY_1_B0    0
79730 #define V_FEC74_FEC_ABILITY_1_B0(x) ((x) << S_FEC74_FEC_ABILITY_1_B0)
79731 #define F_FEC74_FEC_ABILITY_1_B0    V_FEC74_FEC_ABILITY_1_B0(1U)
79732 
79733 #define A_MAC_MTIP_FEC74_FEC_CONTROL_1 0x39124
79734 #define A_MAC_MTIP_FEC74_FEC_STATUS_1 0x39128
79735 #define A_MAC_MTIP_FEC74_VL0_CCW_LO_1 0x3912c
79736 #define A_MAC_MTIP_FEC74_VL0_NCCW_LO_1 0x39130
79737 #define A_MAC_MTIP_FEC74_VL1_CCW_LO_1 0x39134
79738 #define A_MAC_MTIP_FEC74_VL1_NCCW_LO_1 0x39138
79739 #define A_MAC_MTIP_FEC74_COUNTER_HI_1 0x3913c
79740 #define A_MAC_MTIP_FEC74_FEC_ABILITY_2 0x39140
79741 
79742 #define S_FEC74_FEC_ABILITY_2_B1    1
79743 #define V_FEC74_FEC_ABILITY_2_B1(x) ((x) << S_FEC74_FEC_ABILITY_2_B1)
79744 #define F_FEC74_FEC_ABILITY_2_B1    V_FEC74_FEC_ABILITY_2_B1(1U)
79745 
79746 #define S_FEC74_FEC_ABILITY_2_B0    0
79747 #define V_FEC74_FEC_ABILITY_2_B0(x) ((x) << S_FEC74_FEC_ABILITY_2_B0)
79748 #define F_FEC74_FEC_ABILITY_2_B0    V_FEC74_FEC_ABILITY_2_B0(1U)
79749 
79750 #define A_MAC_MTIP_FEC74_FEC_CONTROL_2 0x39144
79751 #define A_MAC_MTIP_FEC74_FEC_STATUS_2 0x39148
79752 #define A_MAC_MTIP_FEC74_VL0_CCW_LO_2 0x3914c
79753 #define A_MAC_MTIP_FEC74_VL0_NCCW_LO_2 0x39150
79754 #define A_MAC_MTIP_FEC74_VL1_CCW_LO_2 0x39154
79755 #define A_MAC_MTIP_FEC74_VL1_NCCW_LO_2 0x39158
79756 #define A_MAC_MTIP_FEC74_COUNTER_HI_2 0x3915c
79757 #define A_MAC_MTIP_FEC74_FEC_ABILITY_3 0x39160
79758 
79759 #define S_FEC74_FEC_ABILITY_3_B1    1
79760 #define V_FEC74_FEC_ABILITY_3_B1(x) ((x) << S_FEC74_FEC_ABILITY_3_B1)
79761 #define F_FEC74_FEC_ABILITY_3_B1    V_FEC74_FEC_ABILITY_3_B1(1U)
79762 
79763 #define S_FEC74_FEC_ABILITY_3_B0    0
79764 #define V_FEC74_FEC_ABILITY_3_B0(x) ((x) << S_FEC74_FEC_ABILITY_3_B0)
79765 #define F_FEC74_FEC_ABILITY_3_B0    V_FEC74_FEC_ABILITY_3_B0(1U)
79766 
79767 #define A_MAC_MTIP_FEC74_FEC_CONTROL_3 0x39164
79768 #define A_MAC_MTIP_FEC74_FEC_STATUS_3 0x39168
79769 #define A_MAC_MTIP_FEC74_VL0_CCW_LO_3 0x3916c
79770 #define A_MAC_MTIP_FEC74_VL0_NCCW_LO_3 0x39170
79771 #define A_MAC_MTIP_FEC74_VL1_CCW_LO_3 0x39174
79772 #define A_MAC_MTIP_FEC74_VL1_NCCW_LO_3 0x39178
79773 #define A_MAC_MTIP_FEC74_COUNTER_HI_3 0x3917c
79774 #define A_MAC_MTIP_FEC74_FEC_ABILITY_4 0x39180
79775 
79776 #define S_FEC74_FEC_ABILITY_4_B1    1
79777 #define V_FEC74_FEC_ABILITY_4_B1(x) ((x) << S_FEC74_FEC_ABILITY_4_B1)
79778 #define F_FEC74_FEC_ABILITY_4_B1    V_FEC74_FEC_ABILITY_4_B1(1U)
79779 
79780 #define S_FEC74_FEC_ABILITY_4_B0    0
79781 #define V_FEC74_FEC_ABILITY_4_B0(x) ((x) << S_FEC74_FEC_ABILITY_4_B0)
79782 #define F_FEC74_FEC_ABILITY_4_B0    V_FEC74_FEC_ABILITY_4_B0(1U)
79783 
79784 #define A_MAC_MTIP_FEC74_FEC_CONTROL_4 0x39184
79785 #define A_MAC_MTIP_FEC74_FEC_STATUS_4 0x39188
79786 #define A_MAC_MTIP_FEC74_VL0_CCW_LO_4 0x3918c
79787 #define A_MAC_MTIP_FEC74_VL0_NCCW_LO_4 0x39190
79788 #define A_MAC_MTIP_FEC74_VL1_CCW_LO_4 0x39194
79789 #define A_MAC_MTIP_FEC74_VL1_NCCW_LO_4 0x39198
79790 #define A_MAC_MTIP_FEC74_COUNTER_HI_4 0x3919c
79791 #define A_MAC_MTIP_FEC74_FEC_ABILITY_5 0x391a0
79792 
79793 #define S_FEC74_FEC_ABILITY_5_B1    1
79794 #define V_FEC74_FEC_ABILITY_5_B1(x) ((x) << S_FEC74_FEC_ABILITY_5_B1)
79795 #define F_FEC74_FEC_ABILITY_5_B1    V_FEC74_FEC_ABILITY_5_B1(1U)
79796 
79797 #define S_FEC74_FEC_ABILITY_5_B0    0
79798 #define V_FEC74_FEC_ABILITY_5_B0(x) ((x) << S_FEC74_FEC_ABILITY_5_B0)
79799 #define F_FEC74_FEC_ABILITY_5_B0    V_FEC74_FEC_ABILITY_5_B0(1U)
79800 
79801 #define A_MAC_MTIP_FEC74_FEC_CONTROL_5 0x391a4
79802 #define A_MAC_MTIP_FEC74_FEC_STATUS_5 0x391a8
79803 #define A_MAC_MTIP_FEC74_VL0_CCW_LO_5 0x391ac
79804 #define A_MAC_MTIP_FEC74_VL0_NCCW_LO_5 0x391b0
79805 #define A_MAC_MTIP_FEC74_VL1_CCW_LO_5 0x391b4
79806 #define A_MAC_MTIP_FEC74_VL1_NCCW_LO_5 0x391b8
79807 #define A_MAC_MTIP_FEC74_COUNTER_HI_5 0x391bc
79808 #define A_MAC_MTIP_FEC74_FEC_ABILITY_6 0x391c0
79809 
79810 #define S_FEC74_FEC_ABILITY_6_B1    1
79811 #define V_FEC74_FEC_ABILITY_6_B1(x) ((x) << S_FEC74_FEC_ABILITY_6_B1)
79812 #define F_FEC74_FEC_ABILITY_6_B1    V_FEC74_FEC_ABILITY_6_B1(1U)
79813 
79814 #define S_FEC74_FEC_ABILITY_6_B0    0
79815 #define V_FEC74_FEC_ABILITY_6_B0(x) ((x) << S_FEC74_FEC_ABILITY_6_B0)
79816 #define F_FEC74_FEC_ABILITY_6_B0    V_FEC74_FEC_ABILITY_6_B0(1U)
79817 
79818 #define A_MAC_MTIP_FEC74_FEC_CONTROL_6 0x391c4
79819 #define A_MAC_MTIP_FEC74_FEC_STATUS_6 0x391c8
79820 #define A_MAC_MTIP_FEC74_VL0_CCW_LO_6 0x391cc
79821 #define A_MAC_MTIP_FEC74_VL0_NCCW_LO_6 0x391d0
79822 #define A_MAC_MTIP_FEC74_VL1_CCW_LO_6 0x391d4
79823 #define A_MAC_MTIP_FEC74_VL1_NCCW_LO_6 0x391d8
79824 #define A_MAC_MTIP_FEC74_COUNTER_HI_6 0x391dc
79825 #define A_MAC_MTIP_FEC74_FEC_ABILITY_7 0x391e0
79826 
79827 #define S_FEC74_FEC_ABILITY_7_B1    1
79828 #define V_FEC74_FEC_ABILITY_7_B1(x) ((x) << S_FEC74_FEC_ABILITY_7_B1)
79829 #define F_FEC74_FEC_ABILITY_7_B1    V_FEC74_FEC_ABILITY_7_B1(1U)
79830 
79831 #define S_FEC74_FEC_ABILITY_7_B0    0
79832 #define V_FEC74_FEC_ABILITY_7_B0(x) ((x) << S_FEC74_FEC_ABILITY_7_B0)
79833 #define F_FEC74_FEC_ABILITY_7_B0    V_FEC74_FEC_ABILITY_7_B0(1U)
79834 
79835 #define A_MAC_MTIP_FEC74_FEC_CONTROL_7 0x391e4
79836 #define A_MAC_MTIP_FEC74_FEC_STATUS_7 0x391e8
79837 #define A_MAC_MTIP_FEC74_VL0_CCW_LO_7 0x391ec
79838 #define A_MAC_MTIP_FEC74_VL0_NCCW_LO_7 0x391f0
79839 #define A_MAC_MTIP_FEC74_VL1_CCW_LO_7 0x391f4
79840 #define A_MAC_MTIP_FEC74_VL1_NCCW_LO_7 0x391f8
79841 #define A_MAC_MTIP_FEC74_COUNTER_HI_7 0x391fc
79842 #define A_MAC_BEAN0_CTL 0x39200
79843 #define A_MAC_BEAN0_STATUS 0x39204
79844 #define A_MAC_BEAN0_ABILITY_0 0x39208
79845 
79846 #define S_BEAN0_REM_FAULT    13
79847 #define V_BEAN0_REM_FAULT(x) ((x) << S_BEAN0_REM_FAULT)
79848 #define F_BEAN0_REM_FAULT    V_BEAN0_REM_FAULT(1U)
79849 
79850 #define A_MAC_BEAN0_ABILITY_1 0x3920c
79851 #define A_MAC_BEAN0_ABILITY_2 0x39210
79852 
79853 #define S_BEAN0_AB_2_15_12    12
79854 #define M_BEAN0_AB_2_15_12    0xfU
79855 #define V_BEAN0_AB_2_15_12(x) ((x) << S_BEAN0_AB_2_15_12)
79856 #define G_BEAN0_AB_2_15_12(x) (((x) >> S_BEAN0_AB_2_15_12) & M_BEAN0_AB_2_15_12)
79857 
79858 #define S_BEAN0_AB_2_11_0    0
79859 #define M_BEAN0_AB_2_11_0    0xfffU
79860 #define V_BEAN0_AB_2_11_0(x) ((x) << S_BEAN0_AB_2_11_0)
79861 #define G_BEAN0_AB_2_11_0(x) (((x) >> S_BEAN0_AB_2_11_0) & M_BEAN0_AB_2_11_0)
79862 
79863 #define A_MAC_BEAN0_REM_ABILITY_0 0x39214
79864 
79865 #define S_BEAN0_ABL_REM_FAULT    13
79866 #define V_BEAN0_ABL_REM_FAULT(x) ((x) << S_BEAN0_ABL_REM_FAULT)
79867 #define F_BEAN0_ABL_REM_FAULT    V_BEAN0_ABL_REM_FAULT(1U)
79868 
79869 #define A_MAC_BEAN0_REM_ABILITY_1 0x39218
79870 #define A_MAC_BEAN0_REM_ABILITY_2 0x3921c
79871 
79872 #define S_BEAN0_REM_AB_15_12    12
79873 #define M_BEAN0_REM_AB_15_12    0xfU
79874 #define V_BEAN0_REM_AB_15_12(x) ((x) << S_BEAN0_REM_AB_15_12)
79875 #define G_BEAN0_REM_AB_15_12(x) (((x) >> S_BEAN0_REM_AB_15_12) & M_BEAN0_REM_AB_15_12)
79876 
79877 #define S_BEAN0_REM_AB_11_0    0
79878 #define M_BEAN0_REM_AB_11_0    0xfffU
79879 #define V_BEAN0_REM_AB_11_0(x) ((x) << S_BEAN0_REM_AB_11_0)
79880 #define G_BEAN0_REM_AB_11_0(x) (((x) >> S_BEAN0_REM_AB_11_0) & M_BEAN0_REM_AB_11_0)
79881 
79882 #define A_MAC_BEAN0_MS_COUNT 0x39220
79883 #define A_MAC_BEAN0_XNP_0 0x39224
79884 #define A_MAC_BEAN0_XNP_1 0x39228
79885 #define A_MAC_BEAN0_XNP_2 0x3922c
79886 #define A_MAC_LP_BEAN0_XNP_0 0x39230
79887 #define A_MAC_LP_BEAN0_XNP_1 0x39234
79888 #define A_MAC_LP_BEAN0_XNP_2 0x39238
79889 #define A_MAC_BEAN0_ETH_STATUS 0x3923c
79890 
79891 #define S_5GKR    15
79892 #define V_5GKR(x) ((x) << S_5GKR)
79893 #define F_5GKR    V_5GKR(1U)
79894 
79895 #define S_2P5GKX    14
79896 #define V_2P5GKX(x) ((x) << S_2P5GKX)
79897 #define F_2P5GKX    V_2P5GKX(1U)
79898 
79899 #define S_25G_KR    13
79900 #define V_25G_KR(x) ((x) << S_25G_KR)
79901 #define F_25G_KR    V_25G_KR(1U)
79902 
79903 #define S_25G_KR_S    12
79904 #define V_25G_KR_S(x) ((x) << S_25G_KR_S)
79905 #define F_25G_KR_S    V_25G_KR_S(1U)
79906 
79907 #define S_RS_FEC    7
79908 #define V_RS_FEC(x) ((x) << S_RS_FEC)
79909 #define F_RS_FEC    V_RS_FEC(1U)
79910 
79911 #define S_FC_FEC    4
79912 #define V_FC_FEC(x) ((x) << S_FC_FEC)
79913 #define F_FC_FEC    V_FC_FEC(1U)
79914 
79915 #define A_MAC_BEAN0_ETH_STATUS_2 0x39240
79916 
79917 #define S_RS_FEC_NEGOTIATED    6
79918 #define V_RS_FEC_NEGOTIATED(x) ((x) << S_RS_FEC_NEGOTIATED)
79919 #define F_RS_FEC_NEGOTIATED    V_RS_FEC_NEGOTIATED(1U)
79920 
79921 #define S_400GKR4CR4    5
79922 #define V_400GKR4CR4(x) ((x) << S_400GKR4CR4)
79923 #define F_400GKR4CR4    V_400GKR4CR4(1U)
79924 
79925 #define S_200GKR2CR2    4
79926 #define V_200GKR2CR2(x) ((x) << S_200GKR2CR2)
79927 #define F_200GKR2CR2    V_200GKR2CR2(1U)
79928 
79929 #define S_100GKR1CR1    3
79930 #define V_100GKR1CR1(x) ((x) << S_100GKR1CR1)
79931 #define F_100GKR1CR1    V_100GKR1CR1(1U)
79932 
79933 #define S_200GKR4CR4    2
79934 #define V_200GKR4CR4(x) ((x) << S_200GKR4CR4)
79935 #define F_200GKR4CR4    V_200GKR4CR4(1U)
79936 
79937 #define S_100GKR2CR2    1
79938 #define V_100GKR2CR2(x) ((x) << S_100GKR2CR2)
79939 #define F_100GKR2CR2    V_100GKR2CR2(1U)
79940 
79941 #define S_50GKRCR    0
79942 #define V_50GKRCR(x) ((x) << S_50GKRCR)
79943 #define F_50GKRCR    V_50GKRCR(1U)
79944 
79945 #define A_MAC_BEAN1_CTL 0x39300
79946 #define A_MAC_BEAN1_STATUS 0x39304
79947 #define A_MAC_BEAN1_ABILITY_0 0x39308
79948 
79949 #define S_BEAN1_REM_FAULT    13
79950 #define V_BEAN1_REM_FAULT(x) ((x) << S_BEAN1_REM_FAULT)
79951 #define F_BEAN1_REM_FAULT    V_BEAN1_REM_FAULT(1U)
79952 
79953 #define A_MAC_BEAN1_ABILITY_1 0x3930c
79954 #define A_MAC_BEAN1_ABILITY_2 0x39310
79955 
79956 #define S_BEAN1_AB_2_15_12    12
79957 #define M_BEAN1_AB_2_15_12    0xfU
79958 #define V_BEAN1_AB_2_15_12(x) ((x) << S_BEAN1_AB_2_15_12)
79959 #define G_BEAN1_AB_2_15_12(x) (((x) >> S_BEAN1_AB_2_15_12) & M_BEAN1_AB_2_15_12)
79960 
79961 #define S_BEAN1_AB_2_11_0    0
79962 #define M_BEAN1_AB_2_11_0    0xfffU
79963 #define V_BEAN1_AB_2_11_0(x) ((x) << S_BEAN1_AB_2_11_0)
79964 #define G_BEAN1_AB_2_11_0(x) (((x) >> S_BEAN1_AB_2_11_0) & M_BEAN1_AB_2_11_0)
79965 
79966 #define A_MAC_BEAN1_REM_ABILITY_0 0x39314
79967 
79968 #define S_BEAN1_ABL_REM_FAULT    13
79969 #define V_BEAN1_ABL_REM_FAULT(x) ((x) << S_BEAN1_ABL_REM_FAULT)
79970 #define F_BEAN1_ABL_REM_FAULT    V_BEAN1_ABL_REM_FAULT(1U)
79971 
79972 #define A_MAC_BEAN1_REM_ABILITY_1 0x39318
79973 #define A_MAC_BEAN1_REM_ABILITY_2 0x3931c
79974 
79975 #define S_BEAN1_REM_AB_15_12    12
79976 #define M_BEAN1_REM_AB_15_12    0xfU
79977 #define V_BEAN1_REM_AB_15_12(x) ((x) << S_BEAN1_REM_AB_15_12)
79978 #define G_BEAN1_REM_AB_15_12(x) (((x) >> S_BEAN1_REM_AB_15_12) & M_BEAN1_REM_AB_15_12)
79979 
79980 #define S_BEAN1_REM_AB_11_0    0
79981 #define M_BEAN1_REM_AB_11_0    0xfffU
79982 #define V_BEAN1_REM_AB_11_0(x) ((x) << S_BEAN1_REM_AB_11_0)
79983 #define G_BEAN1_REM_AB_11_0(x) (((x) >> S_BEAN1_REM_AB_11_0) & M_BEAN1_REM_AB_11_0)
79984 
79985 #define A_MAC_BEAN1_MS_COUNT 0x39320
79986 #define A_MAC_BEAN1_XNP_0 0x39324
79987 #define A_MAC_BEAN1_XNP_1 0x39328
79988 #define A_MAC_BEAN1_XNP_2 0x3932c
79989 #define A_MAC_LP_BEAN1_XNP_0 0x39330
79990 #define A_MAC_LP_BEAN1_XNP_1 0x39334
79991 #define A_MAC_LP_BEAN1_XNP_2 0x39338
79992 #define A_MAC_BEAN1_ETH_STATUS 0x3933c
79993 #define A_MAC_BEAN1_ETH_STATUS_2 0x39340
79994 #define A_MAC_BEAN2_CTL 0x39400
79995 #define A_MAC_BEAN2_STATUS 0x39404
79996 #define A_MAC_BEAN2_ABILITY_0 0x39408
79997 
79998 #define S_BEAN2_REM_FAULT    13
79999 #define V_BEAN2_REM_FAULT(x) ((x) << S_BEAN2_REM_FAULT)
80000 #define F_BEAN2_REM_FAULT    V_BEAN2_REM_FAULT(1U)
80001 
80002 #define A_MAC_BEAN2_ABILITY_1 0x3940c
80003 #define A_MAC_BEAN2_ABILITY_2 0x39410
80004 
80005 #define S_BEAN2_AB_2_15_12    12
80006 #define M_BEAN2_AB_2_15_12    0xfU
80007 #define V_BEAN2_AB_2_15_12(x) ((x) << S_BEAN2_AB_2_15_12)
80008 #define G_BEAN2_AB_2_15_12(x) (((x) >> S_BEAN2_AB_2_15_12) & M_BEAN2_AB_2_15_12)
80009 
80010 #define S_BEAN2_AB_2_11_0    0
80011 #define M_BEAN2_AB_2_11_0    0xfffU
80012 #define V_BEAN2_AB_2_11_0(x) ((x) << S_BEAN2_AB_2_11_0)
80013 #define G_BEAN2_AB_2_11_0(x) (((x) >> S_BEAN2_AB_2_11_0) & M_BEAN2_AB_2_11_0)
80014 
80015 #define A_MAC_BEAN2_REM_ABILITY_0 0x39414
80016 
80017 #define S_BEAN2_ABL_REM_FAULT    13
80018 #define V_BEAN2_ABL_REM_FAULT(x) ((x) << S_BEAN2_ABL_REM_FAULT)
80019 #define F_BEAN2_ABL_REM_FAULT    V_BEAN2_ABL_REM_FAULT(1U)
80020 
80021 #define A_MAC_BEAN2_REM_ABILITY_1 0x39418
80022 #define A_MAC_BEAN2_REM_ABILITY_2 0x3941c
80023 
80024 #define S_BEAN2_REM_AB_15_12    12
80025 #define M_BEAN2_REM_AB_15_12    0xfU
80026 #define V_BEAN2_REM_AB_15_12(x) ((x) << S_BEAN2_REM_AB_15_12)
80027 #define G_BEAN2_REM_AB_15_12(x) (((x) >> S_BEAN2_REM_AB_15_12) & M_BEAN2_REM_AB_15_12)
80028 
80029 #define S_BEAN2_REM_AB_11_0    0
80030 #define M_BEAN2_REM_AB_11_0    0xfffU
80031 #define V_BEAN2_REM_AB_11_0(x) ((x) << S_BEAN2_REM_AB_11_0)
80032 #define G_BEAN2_REM_AB_11_0(x) (((x) >> S_BEAN2_REM_AB_11_0) & M_BEAN2_REM_AB_11_0)
80033 
80034 #define A_MAC_BEAN2_MS_COUNT 0x39420
80035 #define A_MAC_BEAN2_XNP_0 0x39424
80036 #define A_MAC_BEAN2_XNP_1 0x39428
80037 #define A_MAC_BEAN2_XNP_2 0x3942c
80038 #define A_MAC_LP_BEAN2_XNP_0 0x39430
80039 #define A_MAC_LP_BEAN2_XNP_1 0x39434
80040 #define A_MAC_LP_BEAN2_XNP_2 0x39438
80041 #define A_MAC_BEAN2_ETH_STATUS 0x3943c
80042 #define A_MAC_BEAN2_ETH_STATUS_2 0x39440
80043 #define A_MAC_BEAN3_CTL 0x39500
80044 #define A_MAC_BEAN3_STATUS 0x39504
80045 #define A_MAC_BEAN3_ABILITY_0 0x39508
80046 
80047 #define S_BEAN3_REM_FAULT    13
80048 #define V_BEAN3_REM_FAULT(x) ((x) << S_BEAN3_REM_FAULT)
80049 #define F_BEAN3_REM_FAULT    V_BEAN3_REM_FAULT(1U)
80050 
80051 #define A_MAC_BEAN3_ABILITY_1 0x3950c
80052 #define A_MAC_BEAN3_ABILITY_2 0x39510
80053 
80054 #define S_BEAN3_AB_2_15_12    12
80055 #define M_BEAN3_AB_2_15_12    0xfU
80056 #define V_BEAN3_AB_2_15_12(x) ((x) << S_BEAN3_AB_2_15_12)
80057 #define G_BEAN3_AB_2_15_12(x) (((x) >> S_BEAN3_AB_2_15_12) & M_BEAN3_AB_2_15_12)
80058 
80059 #define S_BEAN3_AB_2_11_0    0
80060 #define M_BEAN3_AB_2_11_0    0xfffU
80061 #define V_BEAN3_AB_2_11_0(x) ((x) << S_BEAN3_AB_2_11_0)
80062 #define G_BEAN3_AB_2_11_0(x) (((x) >> S_BEAN3_AB_2_11_0) & M_BEAN3_AB_2_11_0)
80063 
80064 #define A_MAC_BEAN3_REM_ABILITY_0 0x39514
80065 
80066 #define S_BEAN3_ABL_REM_FAULT    13
80067 #define V_BEAN3_ABL_REM_FAULT(x) ((x) << S_BEAN3_ABL_REM_FAULT)
80068 #define F_BEAN3_ABL_REM_FAULT    V_BEAN3_ABL_REM_FAULT(1U)
80069 
80070 #define A_MAC_BEAN3_REM_ABILITY_1 0x39518
80071 #define A_MAC_BEAN3_REM_ABILITY_2 0x3951c
80072 
80073 #define S_BEAN3_REM_AB_15_12    12
80074 #define M_BEAN3_REM_AB_15_12    0xfU
80075 #define V_BEAN3_REM_AB_15_12(x) ((x) << S_BEAN3_REM_AB_15_12)
80076 #define G_BEAN3_REM_AB_15_12(x) (((x) >> S_BEAN3_REM_AB_15_12) & M_BEAN3_REM_AB_15_12)
80077 
80078 #define S_BEAN3_REM_AB_11_0    0
80079 #define M_BEAN3_REM_AB_11_0    0xfffU
80080 #define V_BEAN3_REM_AB_11_0(x) ((x) << S_BEAN3_REM_AB_11_0)
80081 #define G_BEAN3_REM_AB_11_0(x) (((x) >> S_BEAN3_REM_AB_11_0) & M_BEAN3_REM_AB_11_0)
80082 
80083 #define A_MAC_BEAN3_MS_COUNT 0x39520
80084 #define A_MAC_BEAN3_XNP_0 0x39524
80085 #define A_MAC_BEAN3_XNP_1 0x39528
80086 #define A_MAC_BEAN3_XNP_2 0x3952c
80087 #define A_MAC_LP_BEAN3_XNP_0 0x39530
80088 #define A_MAC_LP_BEAN3_XNP_1 0x39534
80089 #define A_MAC_LP_BEAN3_XNP_2 0x39538
80090 #define A_MAC_BEAN3_ETH_STATUS 0x3953c
80091 #define A_MAC_BEAN3_ETH_STATUS_2 0x39540
80092 #define A_MAC_BEAN4_CTL 0x39600
80093 #define A_MAC_BEAN4_STATUS 0x39604
80094 #define A_MAC_BEAN4_ABILITY_0 0x39608
80095 
80096 #define S_BEAN4_REM_FAULT    13
80097 #define V_BEAN4_REM_FAULT(x) ((x) << S_BEAN4_REM_FAULT)
80098 #define F_BEAN4_REM_FAULT    V_BEAN4_REM_FAULT(1U)
80099 
80100 #define A_MAC_BEAN4_ABILITY_1 0x3960c
80101 #define A_MAC_BEAN4_ABILITY_2 0x39610
80102 
80103 #define S_BEAN4_AB_2_15_12    12
80104 #define M_BEAN4_AB_2_15_12    0xfU
80105 #define V_BEAN4_AB_2_15_12(x) ((x) << S_BEAN4_AB_2_15_12)
80106 #define G_BEAN4_AB_2_15_12(x) (((x) >> S_BEAN4_AB_2_15_12) & M_BEAN4_AB_2_15_12)
80107 
80108 #define S_BEAN4_AB_2_11_0    0
80109 #define M_BEAN4_AB_2_11_0    0xfffU
80110 #define V_BEAN4_AB_2_11_0(x) ((x) << S_BEAN4_AB_2_11_0)
80111 #define G_BEAN4_AB_2_11_0(x) (((x) >> S_BEAN4_AB_2_11_0) & M_BEAN4_AB_2_11_0)
80112 
80113 #define A_MAC_BEAN4_REM_ABILITY_0 0x39614
80114 
80115 #define S_BEAN4_ABL_REM_FAULT    13
80116 #define V_BEAN4_ABL_REM_FAULT(x) ((x) << S_BEAN4_ABL_REM_FAULT)
80117 #define F_BEAN4_ABL_REM_FAULT    V_BEAN4_ABL_REM_FAULT(1U)
80118 
80119 #define A_MAC_BEAN4_REM_ABILITY_1 0x39618
80120 #define A_MAC_BEAN4_REM_ABILITY_2 0x3961c
80121 
80122 #define S_BEAN4_REM_AB_15_12    12
80123 #define M_BEAN4_REM_AB_15_12    0xfU
80124 #define V_BEAN4_REM_AB_15_12(x) ((x) << S_BEAN4_REM_AB_15_12)
80125 #define G_BEAN4_REM_AB_15_12(x) (((x) >> S_BEAN4_REM_AB_15_12) & M_BEAN4_REM_AB_15_12)
80126 
80127 #define S_BEAN4_REM_AB_11_0    0
80128 #define M_BEAN4_REM_AB_11_0    0xfffU
80129 #define V_BEAN4_REM_AB_11_0(x) ((x) << S_BEAN4_REM_AB_11_0)
80130 #define G_BEAN4_REM_AB_11_0(x) (((x) >> S_BEAN4_REM_AB_11_0) & M_BEAN4_REM_AB_11_0)
80131 
80132 #define A_MAC_BEAN4_MS_COUNT 0x39620
80133 #define A_MAC_BEAN4_XNP_0 0x39624
80134 #define A_MAC_BEAN4_XNP_1 0x39628
80135 #define A_MAC_BEAN4_XNP_2 0x3962c
80136 #define A_MAC_LP_BEAN4_XNP_0 0x39630
80137 #define A_MAC_LP_BEAN4_XNP_1 0x39634
80138 #define A_MAC_LP_BEAN4_XNP_2 0x39638
80139 #define A_MAC_BEAN4_ETH_STATUS 0x3963c
80140 #define A_MAC_BEAN4_ETH_STATUS_2 0x39640
80141 #define A_MAC_BEAN5_CTL 0x39700
80142 #define A_MAC_BEAN5_STATUS 0x39704
80143 #define A_MAC_BEAN5_ABILITY_0 0x39708
80144 
80145 #define S_BEAN5_REM_FAULT    13
80146 #define V_BEAN5_REM_FAULT(x) ((x) << S_BEAN5_REM_FAULT)
80147 #define F_BEAN5_REM_FAULT    V_BEAN5_REM_FAULT(1U)
80148 
80149 #define A_MAC_BEAN5_ABILITY_1 0x3970c
80150 #define A_MAC_BEAN5_ABILITY_2 0x39710
80151 
80152 #define S_BEAN5_AB_2_15_12    12
80153 #define M_BEAN5_AB_2_15_12    0xfU
80154 #define V_BEAN5_AB_2_15_12(x) ((x) << S_BEAN5_AB_2_15_12)
80155 #define G_BEAN5_AB_2_15_12(x) (((x) >> S_BEAN5_AB_2_15_12) & M_BEAN5_AB_2_15_12)
80156 
80157 #define S_BEAN5_AB_2_11_0    0
80158 #define M_BEAN5_AB_2_11_0    0xfffU
80159 #define V_BEAN5_AB_2_11_0(x) ((x) << S_BEAN5_AB_2_11_0)
80160 #define G_BEAN5_AB_2_11_0(x) (((x) >> S_BEAN5_AB_2_11_0) & M_BEAN5_AB_2_11_0)
80161 
80162 #define A_MAC_BEAN5_REM_ABILITY_0 0x39714
80163 
80164 #define S_BEAN5_ABL_REM_FAULT    13
80165 #define V_BEAN5_ABL_REM_FAULT(x) ((x) << S_BEAN5_ABL_REM_FAULT)
80166 #define F_BEAN5_ABL_REM_FAULT    V_BEAN5_ABL_REM_FAULT(1U)
80167 
80168 #define A_MAC_BEAN5_REM_ABILITY_1 0x39718
80169 #define A_MAC_BEAN5_REM_ABILITY_2 0x3971c
80170 
80171 #define S_BEAN5_REM_AB_15_12    12
80172 #define M_BEAN5_REM_AB_15_12    0xfU
80173 #define V_BEAN5_REM_AB_15_12(x) ((x) << S_BEAN5_REM_AB_15_12)
80174 #define G_BEAN5_REM_AB_15_12(x) (((x) >> S_BEAN5_REM_AB_15_12) & M_BEAN5_REM_AB_15_12)
80175 
80176 #define S_BEAN5_REM_AB_11_0    0
80177 #define M_BEAN5_REM_AB_11_0    0xfffU
80178 #define V_BEAN5_REM_AB_11_0(x) ((x) << S_BEAN5_REM_AB_11_0)
80179 #define G_BEAN5_REM_AB_11_0(x) (((x) >> S_BEAN5_REM_AB_11_0) & M_BEAN5_REM_AB_11_0)
80180 
80181 #define A_MAC_BEAN5_MS_COUNT 0x39720
80182 #define A_MAC_BEAN5_XNP_0 0x39724
80183 #define A_MAC_BEAN5_XNP_1 0x39728
80184 #define A_MAC_BEAN5_XNP_2 0x3972c
80185 #define A_MAC_LP_BEAN5_XNP_0 0x39730
80186 #define A_MAC_LP_BEAN5_XNP_1 0x39734
80187 #define A_MAC_LP_BEAN5_XNP_2 0x39738
80188 #define A_MAC_BEAN5_ETH_STATUS 0x3973c
80189 #define A_MAC_BEAN5_ETH_STATUS_2 0x39740
80190 #define A_MAC_BEAN6_CTL 0x39800
80191 #define A_MAC_BEAN6_STATUS 0x39804
80192 #define A_MAC_BEAN6_ABILITY_0 0x39808
80193 
80194 #define S_BEAN6_REM_FAULT    13
80195 #define V_BEAN6_REM_FAULT(x) ((x) << S_BEAN6_REM_FAULT)
80196 #define F_BEAN6_REM_FAULT    V_BEAN6_REM_FAULT(1U)
80197 
80198 #define A_MAC_BEAN6_ABILITY_1 0x3980c
80199 #define A_MAC_BEAN6_ABILITY_2 0x39810
80200 
80201 #define S_BEAN6_AB_2_15_12    12
80202 #define M_BEAN6_AB_2_15_12    0xfU
80203 #define V_BEAN6_AB_2_15_12(x) ((x) << S_BEAN6_AB_2_15_12)
80204 #define G_BEAN6_AB_2_15_12(x) (((x) >> S_BEAN6_AB_2_15_12) & M_BEAN6_AB_2_15_12)
80205 
80206 #define S_BEAN6_AB_2_11_0    0
80207 #define M_BEAN6_AB_2_11_0    0xfffU
80208 #define V_BEAN6_AB_2_11_0(x) ((x) << S_BEAN6_AB_2_11_0)
80209 #define G_BEAN6_AB_2_11_0(x) (((x) >> S_BEAN6_AB_2_11_0) & M_BEAN6_AB_2_11_0)
80210 
80211 #define A_MAC_BEAN6_REM_ABILITY_0 0x39814
80212 
80213 #define S_BEAN6_ABL_REM_FAULT    13
80214 #define V_BEAN6_ABL_REM_FAULT(x) ((x) << S_BEAN6_ABL_REM_FAULT)
80215 #define F_BEAN6_ABL_REM_FAULT    V_BEAN6_ABL_REM_FAULT(1U)
80216 
80217 #define A_MAC_BEAN6_REM_ABILITY_1 0x39818
80218 #define A_MAC_BEAN6_REM_ABILITY_2 0x3981c
80219 
80220 #define S_BEAN6_REM_AB_15_12    12
80221 #define M_BEAN6_REM_AB_15_12    0xfU
80222 #define V_BEAN6_REM_AB_15_12(x) ((x) << S_BEAN6_REM_AB_15_12)
80223 #define G_BEAN6_REM_AB_15_12(x) (((x) >> S_BEAN6_REM_AB_15_12) & M_BEAN6_REM_AB_15_12)
80224 
80225 #define S_BEAN6_REM_AB_11_0    0
80226 #define M_BEAN6_REM_AB_11_0    0xfffU
80227 #define V_BEAN6_REM_AB_11_0(x) ((x) << S_BEAN6_REM_AB_11_0)
80228 #define G_BEAN6_REM_AB_11_0(x) (((x) >> S_BEAN6_REM_AB_11_0) & M_BEAN6_REM_AB_11_0)
80229 
80230 #define A_MAC_BEAN6_MS_COUNT 0x39820
80231 #define A_MAC_BEAN6_XNP_0 0x39824
80232 #define A_MAC_BEAN6_XNP_1 0x39828
80233 #define A_MAC_BEAN6_XNP_2 0x3982c
80234 #define A_MAC_LP_BEAN6_XNP_0 0x39830
80235 #define A_MAC_LP_BEAN6_XNP_1 0x39834
80236 #define A_MAC_LP_BEAN6_XNP_2 0x39838
80237 #define A_MAC_BEAN6_ETH_STATUS 0x3983c
80238 #define A_MAC_BEAN6_ETH_STATUS_2 0x39840
80239 #define A_MAC_BEAN7_CTL 0x39900
80240 #define A_MAC_BEAN7_STATUS 0x39904
80241 #define A_MAC_BEAN7_ABILITY_0 0x39908
80242 
80243 #define S_BEAN7_REM_FAULT    13
80244 #define V_BEAN7_REM_FAULT(x) ((x) << S_BEAN7_REM_FAULT)
80245 #define F_BEAN7_REM_FAULT    V_BEAN7_REM_FAULT(1U)
80246 
80247 #define A_MAC_BEAN7_ABILITY_1 0x3990c
80248 #define A_MAC_BEAN7_ABILITY_2 0x39910
80249 
80250 #define S_BEAN7_AB_2_15_12    12
80251 #define M_BEAN7_AB_2_15_12    0xfU
80252 #define V_BEAN7_AB_2_15_12(x) ((x) << S_BEAN7_AB_2_15_12)
80253 #define G_BEAN7_AB_2_15_12(x) (((x) >> S_BEAN7_AB_2_15_12) & M_BEAN7_AB_2_15_12)
80254 
80255 #define S_BEAN7_AB_2_11_0    0
80256 #define M_BEAN7_AB_2_11_0    0xfffU
80257 #define V_BEAN7_AB_2_11_0(x) ((x) << S_BEAN7_AB_2_11_0)
80258 #define G_BEAN7_AB_2_11_0(x) (((x) >> S_BEAN7_AB_2_11_0) & M_BEAN7_AB_2_11_0)
80259 
80260 #define A_MAC_BEAN7_REM_ABILITY_0 0x39914
80261 
80262 #define S_BEAN7_ABL_REM_FAULT    13
80263 #define V_BEAN7_ABL_REM_FAULT(x) ((x) << S_BEAN7_ABL_REM_FAULT)
80264 #define F_BEAN7_ABL_REM_FAULT    V_BEAN7_ABL_REM_FAULT(1U)
80265 
80266 #define A_MAC_BEAN7_REM_ABILITY_1 0x39918
80267 #define A_MAC_BEAN7_REM_ABILITY_2 0x3991c
80268 
80269 #define S_BEAN7_REM_AB_15_12    12
80270 #define M_BEAN7_REM_AB_15_12    0xfU
80271 #define V_BEAN7_REM_AB_15_12(x) ((x) << S_BEAN7_REM_AB_15_12)
80272 #define G_BEAN7_REM_AB_15_12(x) (((x) >> S_BEAN7_REM_AB_15_12) & M_BEAN7_REM_AB_15_12)
80273 
80274 #define S_BEAN7_REM_AB_11_0    0
80275 #define M_BEAN7_REM_AB_11_0    0xfffU
80276 #define V_BEAN7_REM_AB_11_0(x) ((x) << S_BEAN7_REM_AB_11_0)
80277 #define G_BEAN7_REM_AB_11_0(x) (((x) >> S_BEAN7_REM_AB_11_0) & M_BEAN7_REM_AB_11_0)
80278 
80279 #define A_MAC_BEAN7_MS_COUNT 0x39920
80280 #define A_MAC_BEAN7_XNP_0 0x39924
80281 #define A_MAC_BEAN7_XNP_1 0x39928
80282 #define A_MAC_BEAN7_XNP_2 0x3992c
80283 #define A_MAC_LP_BEAN7_XNP_0 0x39930
80284 #define A_MAC_LP_BEAN7_XNP_1 0x39934
80285 #define A_MAC_LP_BEAN7_XNP_2 0x39938
80286 #define A_MAC_BEAN7_ETH_STATUS 0x3993c
80287 #define A_MAC_BEAN7_ETH_STATUS_2 0x39940
80288 #define A_MAC_MTIP_ETHERSTATS_DATA_HI 0x39a00
80289 #define A_MAC_MTIP_ETHERSTATS_STATN_STATUS 0x39a04
80290 #define A_MAC_MTIP_ETHERSTATS_STATN_CONFIG 0x39a08
80291 
80292 #define S_T7_RESET    31
80293 #define V_T7_RESET(x) ((x) << S_T7_RESET)
80294 #define F_T7_RESET    V_T7_RESET(1U)
80295 
80296 #define A_MAC_MTIP_ETHERSTATS_STATN_CONTROL 0x39a0c
80297 
80298 #define S_CMD_CLEAR_TX    31
80299 #define V_CMD_CLEAR_TX(x) ((x) << S_CMD_CLEAR_TX)
80300 #define F_CMD_CLEAR_TX    V_CMD_CLEAR_TX(1U)
80301 
80302 #define S_CMD_CLEAR_RX    30
80303 #define V_CMD_CLEAR_RX(x) ((x) << S_CMD_CLEAR_RX)
80304 #define F_CMD_CLEAR_RX    V_CMD_CLEAR_RX(1U)
80305 
80306 #define S_CLEAR_PRE    29
80307 #define V_CLEAR_PRE(x) ((x) << S_CLEAR_PRE)
80308 #define F_CLEAR_PRE    V_CLEAR_PRE(1U)
80309 
80310 #define S_CMD_CAPTURE_TX    28
80311 #define V_CMD_CAPTURE_TX(x) ((x) << S_CMD_CAPTURE_TX)
80312 #define F_CMD_CAPTURE_TX    V_CMD_CAPTURE_TX(1U)
80313 
80314 #define S_CMD_CAPTURE_RX    27
80315 #define V_CMD_CAPTURE_RX(x) ((x) << S_CMD_CAPTURE_RX)
80316 #define F_CMD_CAPTURE_RX    V_CMD_CAPTURE_RX(1U)
80317 
80318 #define S_PORTMASK    0
80319 #define M_PORTMASK    0xffU
80320 #define V_PORTMASK(x) ((x) << S_PORTMASK)
80321 #define G_PORTMASK(x) (((x) >> S_PORTMASK) & M_PORTMASK)
80322 
80323 #define A_MAC_MTIP_ETHERSTATS_STATN_CLEARVALUE_LO 0x39a10
80324 
80325 #define S_STATN_CLEARVALUE_LO    0
80326 #define V_STATN_CLEARVALUE_LO(x) ((x) << S_STATN_CLEARVALUE_LO)
80327 #define F_STATN_CLEARVALUE_LO    V_STATN_CLEARVALUE_LO(1U)
80328 
80329 #define A_MAC_MTIP_ETHERSTATS_STATN_CLEARVALUE_HI 0x39a14
80330 
80331 #define S_STATN_CLEARVALUE_HI    0
80332 #define V_STATN_CLEARVALUE_HI(x) ((x) << S_STATN_CLEARVALUE_HI)
80333 #define F_STATN_CLEARVALUE_HI    V_STATN_CLEARVALUE_HI(1U)
80334 
80335 #define A_MAC_MTIP_ETHERSTATS_DATA_HI_1 0x39a1c
80336 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_0 0x39a20
80337 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_1 0x39a24
80338 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_2 0x39a28
80339 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_3 0x39a2c
80340 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_4 0x39a30
80341 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_5 0x39a34
80342 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_6 0x39a38
80343 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_7 0x39a3c
80344 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_8 0x39a40
80345 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_9 0x39a44
80346 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_10 0x39a48
80347 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_11 0x39a4c
80348 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_12 0x39a50
80349 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_13 0x39a54
80350 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_14 0x39a58
80351 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_15 0x39a5c
80352 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_16 0x39a60
80353 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_17 0x39a64
80354 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_18 0x39a68
80355 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_19 0x39a6c
80356 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_20 0x39a70
80357 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_21 0x39a74
80358 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_22 0x39a78
80359 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_23 0x39a7c
80360 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_24 0x39a80
80361 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_25 0x39a84
80362 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_26 0x39a88
80363 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_27 0x39a8c
80364 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_28 0x39a90
80365 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_29 0x39a94
80366 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_30 0x39a98
80367 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_31 0x39a9c
80368 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_32 0x39aa0
80369 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_33 0x39aa4
80370 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_34 0x39aa8
80371 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSOCTETS 0x39b00
80372 #define A_MAC_MTIP_ETHERSTATS0_OCTETSRECEIVEDOK 0x39b04
80373 #define A_MAC_MTIP_ETHERSTATS0_AALIGNMENTERRORS 0x39b08
80374 #define A_MAC_MTIP_ETHERSTATS0_APAUSEMACCTRLFRAMESRECEIVED 0x39b0c
80375 #define A_MAC_MTIP_ETHERSTATS0_AFRAMETOOLONGERRORS 0x39b10
80376 #define A_MAC_MTIP_ETHERSTATS0_AINRANGELENGTHERRORS 0x39b14
80377 #define A_MAC_MTIP_ETHERSTATS0_AFRAMESRECEIVEDOK 0x39b18
80378 #define A_MAC_MTIP_ETHERSTATS0_AFRAMECHECKSEQUENCEERRORS 0x39b1c
80379 #define A_MAC_MTIP_ETHERSTATS0_VLANRECEIVEDOK 0x39b20
80380 #define A_MAC_MTIP_ETHERSTATS0_IFINERRORS_RX 0x39b24
80381 #define A_MAC_MTIP_ETHERSTATS0_IFINUCASTPKTS_RX 0x39b28
80382 #define A_MAC_MTIP_ETHERSTATS0_IFINMULTICASTPKTS_RX 0x39b2c
80383 #define A_MAC_MTIP_ETHERSTATS0_IFINBROADCASTPKTS_RX 0x39b30
80384 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSDROPEVENTS_RX 0x39b34
80385 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS_RX 0x39b38
80386 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSUNDERSIZEPKTS_RX 0x39b3c
80387 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS64OCTETS_RX 0x39b40
80388 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS65TO127OCTETS_RX 0x39b44
80389 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS128TO255OCTETS_RX 0x39b48
80390 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS256TO511OCTETS_RX 0x39b4c
80391 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS512TO1023OCTETS_RX 0x39b50
80392 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1024TO1518OCTETS_RX 0x39b54
80393 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1519TOMAXOCTETS_RX 0x39b58
80394 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSOVERSIZEPKTS_RX 0x39b5c
80395 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSJABBERS_RX 0x39b60
80396 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSFRAGMENTS_RX 0x39b64
80397 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_0_RX 0x39b68
80398 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_1_RX 0x39b6c
80399 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_2_RX 0x39b70
80400 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_3_RX 0x39b74
80401 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_4_RX 0x39b78
80402 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_5_RX 0x39b7c
80403 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_6_RX 0x39b80
80404 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_7_RX 0x39b84
80405 #define A_MAC_MTIP_ETHERSTATS0_AMACCONTROLFRAMESRECEIVED_RX 0x39b88
80406 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSOCTETS 0x39b8c
80407 #define A_MAC_MTIP_ETHERSTATS1_OCTETSRECEIVEDOK 0x39b90
80408 #define A_MAC_MTIP_ETHERSTATS1_AALIGNMENTERRORS 0x39b94
80409 #define A_MAC_MTIP_ETHERSTATS1_APAUSEMACCTRLFRAMESRECEIVED 0x39b98
80410 #define A_MAC_MTIP_ETHERSTATS1_AFRAMETOOLONGERRORS 0x39b9c
80411 #define A_MAC_MTIP_ETHERSTATS1_AINRANGELENGTHERRORS 0x39ba0
80412 #define A_MAC_MTIP_ETHERSTATS1_AFRAMESRECEIVEDOK 0x39ba4
80413 #define A_MAC_MTIP_ETHERSTATS1_AFRAMECHECKSEQUENCEERRORS 0x39ba8
80414 #define A_MAC_MTIP_ETHERSTATS1_VLANRECEIVEDOK 0x39bac
80415 #define A_MAC_MTIP_ETHERSTATS1_IFINERRORS_RX 0x39bb0
80416 #define A_MAC_MTIP_ETHERSTATS1_IFINUCASTPKTS_RX 0x39bb4
80417 #define A_MAC_MTIP_ETHERSTATS1_IFINMULTICASTPKTS_RX 0x39bb8
80418 #define A_MAC_MTIP_ETHERSTATS1_IFINBROADCASTPKTS_RX 0x39bbc
80419 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSDROPEVENTS_RX 0x39bc0
80420 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS_RX 0x39bc4
80421 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSUNDERSIZEPKTS_RX 0x39bc8
80422 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS64OCTETS_RX 0x39bcc
80423 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS65TO127OCTETS_RX 0x39bd0
80424 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS128TO255OCTETS_RX 0x39bd4
80425 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS256TO511OCTETS_RX 0x39bd8
80426 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS512TO1023OCTETS_RX 0x39bdc
80427 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1024TO1518OCTETS_RX 0x39be0
80428 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1519TOMAXOCTETS_RX 0x39be4
80429 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSOVERSIZEPKTS_RX 0x39be8
80430 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSJABBERS_RX 0x39bec
80431 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSFRAGMENTS_RX 0x39bf0
80432 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_0_RX 0x39bf4
80433 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_1_RX 0x39bf8
80434 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_2_RX 0x39bfc
80435 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_3_RX 0x39c00
80436 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_4_RX 0x39c04
80437 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_5_RX 0x39c08
80438 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_6_RX 0x39c0c
80439 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_7_RX 0x39c10
80440 #define A_MAC_MTIP_ETHERSTATS1_AMACCONTROLFRAMESRECEIVED_RX 0x39c14
80441 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSOCTETS 0x39c18
80442 #define A_MAC_MTIP_ETHERSTATS2_OCTETSRECEIVEDOK 0x39c1c
80443 #define A_MAC_MTIP_ETHERSTATS2_AALIGNMENTERRORS 0x39c20
80444 #define A_MAC_MTIP_ETHERSTATS2_APAUSEMACCTRLFRAMESRECEIVED 0x39c24
80445 #define A_MAC_MTIP_ETHERSTATS2_AFRAMETOOLONGERRORS 0x39c28
80446 #define A_MAC_MTIP_ETHERSTATS2_AINRANGELENGTHERRORS 0x39c2c
80447 #define A_MAC_MTIP_ETHERSTATS2_AFRAMESRECEIVEDOK 0x39c30
80448 #define A_MAC_MTIP_ETHERSTATS2_AFRAMECHECKSEQUENCEERRORS 0x39c34
80449 #define A_MAC_MTIP_ETHERSTATS2_VLANRECEIVEDOK 0x39c38
80450 #define A_MAC_MTIP_ETHERSTATS2_IFINERRORS_RX 0x39c3c
80451 #define A_MAC_MTIP_ETHERSTATS2_IFINUCASTPKTS_RX 0x39c40
80452 #define A_MAC_MTIP_ETHERSTATS2_IFINMULTICASTPKTS_RX 0x39c44
80453 #define A_MAC_MTIP_ETHERSTATS2_IFINBROADCASTPKTS_RX 0x39c48
80454 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSDROPEVENTS_RX 0x39c4c
80455 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS_RX 0x39c50
80456 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSUNDERSIZEPKTS_RX 0x39c54
80457 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS64OCTETS_RX 0x39c58
80458 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS65TO127OCTETS_RX 0x39c5c
80459 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS128TO255OCTETS_RX 0x39c60
80460 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS256TO511OCTETS_RX 0x39c64
80461 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS512TO1023OCTETS_RX 0x39c68
80462 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1024TO1518OCTETS_RX 0x39c6c
80463 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1519TOMAXOCTETS_RX 0x39c70
80464 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSOVERSIZEPKTS_RX 0x39c74
80465 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSJABBERS_RX 0x39c78
80466 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSFRAGMENTS_RX 0x39c7c
80467 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_0_RX 0x39c80
80468 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_1_RX 0x39c84
80469 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_2_RX 0x39c88
80470 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_3_RX 0x39c8c
80471 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_4_RX 0x39c90
80472 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_5_RX 0x39c94
80473 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_6_RX 0x39c98
80474 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_7_RX 0x39c9c
80475 #define A_MAC_MTIP_ETHERSTATS2_AMACCONTROLFRAMESRECEIVED_RX 0x39ca0
80476 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSOCTETS 0x39ca4
80477 #define A_MAC_MTIP_ETHERSTATS3_OCTETSRECEIVEDOK 0x39ca8
80478 #define A_MAC_MTIP_ETHERSTATS3_AALIGNMENTERRORS 0x39cac
80479 #define A_MAC_MTIP_ETHERSTATS3_APAUSEMACCTRLFRAMESRECEIVED 0x39cb0
80480 #define A_MAC_MTIP_ETHERSTATS3_AFRAMETOOLONGERRORS 0x39cb4
80481 #define A_MAC_MTIP_ETHERSTATS3_AINRANGELENGTHERRORS 0x39cb8
80482 #define A_MAC_MTIP_ETHERSTATS3_AFRAMESRECEIVEDOK 0x39cbc
80483 #define A_MAC_MTIP_ETHERSTATS3_AFRAMECHECKSEQUENCEERRORS 0x39cc0
80484 #define A_MAC_MTIP_ETHERSTATS3_VLANRECEIVEDOK 0x39cc4
80485 #define A_MAC_MTIP_ETHERSTATS3_IFINERRORS_RX 0x39cc8
80486 #define A_MAC_MTIP_ETHERSTATS3_IFINUCASTPKTS_RX 0x39ccc
80487 #define A_MAC_MTIP_ETHERSTATS3_IFINMULTICASTPKTS_RX 0x39cd0
80488 #define A_MAC_MTIP_ETHERSTATS3_IFINBROADCASTPKTS_RX 0x39cd4
80489 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSDROPEVENTS_RX 0x39cd8
80490 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS_RX 0x39cdc
80491 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSUNDERSIZEPKTS_RX 0x39ce0
80492 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS64OCTETS_RX 0x39ce4
80493 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS65TO127OCTETS_RX 0x39ce8
80494 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS128TO255OCTETS_RX 0x39cec
80495 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS256TO511OCTETS_RX 0x39cf0
80496 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS512TO1023OCTETS_RX 0x39cf4
80497 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1024TO1518OCTETS_RX 0x39cf8
80498 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1519TOMAXOCTETS_RX 0x39cfc
80499 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSOVERSIZEPKTS_RX 0x39d00
80500 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSJABBERS_RX 0x39d04
80501 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSFRAGMENTS_RX 0x39d08
80502 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_0_RX 0x39d0c
80503 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_1_RX 0x39d10
80504 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_2_RX 0x39d14
80505 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_3_RX 0x39d18
80506 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_4_RX 0x39d1c
80507 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_5_RX 0x39d20
80508 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_6_RX 0x39d24
80509 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_7_RX 0x39d28
80510 #define A_MAC_MTIP_ETHERSTATS3_AMACCONTROLFRAMESRECEIVED_RX 0x39d2c
80511 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSOCTETS_TX 0x39d30
80512 #define A_MAC_MTIP_ETHERSTATS0_OCTETSTRANSMITTEDOK_TX 0x39d34
80513 #define A_MAC_MTIP_ETHERSTATS0_APAUSEMACCTRLFRAMESTRANSMITTED_TX 0x39d38
80514 #define A_MAC_MTIP_ETHERSTATS0_AFRAMESTRANSMITTEDOK_TX 0x39d3c
80515 #define A_MAC_MTIP_ETHERSTATS0_VLANTRANSMITTEDOK_TX 0x39d40
80516 #define A_MAC_MTIP_ETHERSTATS0_IFOUTERRORS_TX 0x39d44
80517 #define A_MAC_MTIP_ETHERSTATS0_IFOUTUCASTPKTS_TX 0x39d48
80518 #define A_MAC_MTIP_ETHERSTATS0IFOUTMULTICASTPKTS_TX 0x39d4c
80519 #define A_MAC_MTIP_ETHERSTATS0_IFOUTBROADCASTPKTS_TX 0x39d50
80520 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS64OCTETS_TX 0x39d54
80521 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS65TO127OCTETS_TX 0x39d58
80522 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS128TO255OCTETS_TX 0x39d5c
80523 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS256TO511OCTETS_TX 0x39d60
80524 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS512TO1023OCTETS_TX 0x39d64
80525 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1024TO1518OCTETS_TX 0x39d68
80526 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1519TOMAXOCTETS_TX 0x39d6c
80527 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_0_TX 0x39d70
80528 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_1_TX 0x39d74
80529 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_2_TX 0x39d78
80530 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_3_TX 0x39d7c
80531 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_4_TX 0x39d80
80532 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_5_TX 0x39d84
80533 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_6_TX 0x39d88
80534 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_7_TX 0x39d8c
80535 #define A_MAC_MTIP_ETHERSTATS0_AMACCONTROLFRAMESTRANSMITTED_TX 0x39d90
80536 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS_TX 0x39d94
80537 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSOCTETS_TX 0x39d98
80538 #define A_MAC_MTIP_ETHERSTATS1_OCTETSTRANSMITTEDOK_TX 0x39d9c
80539 #define A_MAC_MTIP_ETHERSTATS1_APAUSEMACCTRLFRAMESTRANSMITTED_TX 0x39da0
80540 #define A_MAC_MTIP_ETHERSTATS1_AFRAMESTRANSMITTEDOK_TX 0x39da4
80541 #define A_MAC_MTIP_ETHERSTATS1_VLANTRANSMITTEDOK_TX 0x39da8
80542 #define A_MAC_MTIP_ETHERSTATS1_IFOUTERRORS_TX 0x39dac
80543 #define A_MAC_MTIP_ETHERSTATS1_IFOUTUCASTPKTS_TX 0x39db0
80544 #define A_MAC_MTIP_ETHERSTATS1IFOUTMULTICASTPKTS_TX 0x39db4
80545 #define A_MAC_MTIP_ETHERSTATS1_IFOUTBROADCASTPKTS_TX 0x39db8
80546 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS64OCTETS_TX 0x39dbc
80547 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS65TO127OCTETS_TX 0x39dc0
80548 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS128TO255OCTETS_TX 0x39dc4
80549 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS256TO511OCTETS_TX 0x39dc8
80550 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS512TO1023OCTETS_TX 0x39dcc
80551 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1024TO1518OCTETS_TX 0x39dd0
80552 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1519TOMAXOCTETS_TX 0x39dd4
80553 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_0_TX 0x39dd8
80554 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_1_TX 0x39ddc
80555 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_2_TX 0x39de0
80556 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_3_TX 0x39de4
80557 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_4_TX 0x39de8
80558 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_5_TX 0x39dec
80559 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_6_TX 0x39df0
80560 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_7_TX 0x39df4
80561 #define A_MAC_MTIP_ETHERSTATS1_AMACCONTROLFRAMESTRANSMITTED_TX 0x39df8
80562 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS_TX 0x39dfc
80563 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSOCTETS_TX 0x39e00
80564 #define A_MAC_MTIP_ETHERSTATS2_OCTETSTRANSMITTEDOK_TX 0x39e04
80565 #define A_MAC_MTIP_ETHERSTATS2_APAUSEMACCTRLFRAMESTRANSMITTED_TX 0x39e08
80566 #define A_MAC_MTIP_ETHERSTATS2_AFRAMESTRANSMITTEDOK_TX 0x39e0c
80567 #define A_MAC_MTIP_ETHERSTATS2_VLANTRANSMITTEDOK_TX 0x39e10
80568 #define A_MAC_MTIP_ETHERSTATS2_IFOUTERRORS_TX 0x39e14
80569 #define A_MAC_MTIP_ETHERSTATS2_IFOUTUCASTPKTS_TX 0x39e18
80570 #define A_MAC_MTIP_ETHERSTATS2IFOUTMULTICASTPKTS_TX 0x39e1c
80571 #define A_MAC_MTIP_ETHERSTATS2_IFOUTBROADCASTPKTS_TX 0x39e20
80572 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS64OCTETS_TX 0x39e24
80573 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS65TO127OCTETS_TX 0x39e28
80574 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS128TO255OCTETS_TX 0x39e2c
80575 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS256TO511OCTETS_TX 0x39e30
80576 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS512TO1023OCTETS_TX 0x39e34
80577 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1024TO1518OCTETS_TX 0x39e38
80578 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1519TOMAXOCTETS_TX 0x39e3c
80579 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_0_TX 0x39e40
80580 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_1_TX 0x39e44
80581 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_2_TX 0x39e48
80582 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_3_TX 0x39e4c
80583 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_4_TX 0x39e50
80584 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_5_TX 0x39e54
80585 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_6_TX 0x39e58
80586 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_7_TX 0x39e5c
80587 #define A_MAC_MTIP_ETHERSTATS2_AMACCONTROLFRAMESTRANSMITTED_TX 0x39e60
80588 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS_TX 0x39e64
80589 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSOCTETS_TX 0x39e68
80590 #define A_MAC_MTIP_ETHERSTATS3_OCTETSTRANSMITTEDOK_TX 0x39e6c
80591 #define A_MAC_MTIP_ETHERSTATS3_APAUSEMACCTRLFRAMESTRANSMITTED_TX 0x39e70
80592 #define A_MAC_MTIP_ETHERSTATS3_AFRAMESTRANSMITTEDOK_TX 0x39e74
80593 #define A_MAC_MTIP_ETHERSTATS3_VLANTRANSMITTEDOK_TX 0x39e78
80594 #define A_MAC_MTIP_ETHERSTATS3_IFOUTERRORS_TX 0x39e7c
80595 #define A_MAC_MTIP_ETHERSTATS3_IFOUTUCASTPKTS_TX 0x39e80
80596 #define A_MAC_MTIP_ETHERSTATS3IFOUTMULTICASTPKTS_TX 0x39e84
80597 #define A_MAC_MTIP_ETHERSTATS3_IFOUTBROADCASTPKTS_TX 0x39e88
80598 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS64OCTETS_TX 0x39e8c
80599 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS65TO127OCTETS_TX 0x39e90
80600 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS128TO255OCTETS_TX 0x39e94
80601 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS256TO511OCTETS_TX 0x39e98
80602 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS512TO1023OCTETS_TX 0x39e9c
80603 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1024TO1518OCTETS_TX 0x39ea0
80604 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1519TOMAXOCTETS_TX 0x39ea4
80605 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_0_TX 0x39ea8
80606 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_1_TX 0x39eac
80607 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_2_TX 0x39eb0
80608 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_3_TX 0x39eb4
80609 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_4_TX 0x39eb8
80610 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_5_TX 0x39ebc
80611 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_6_TX 0x39ec0
80612 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_7_TX 0x39ec4
80613 #define A_MAC_MTIP_ETHERSTATS3_AMACCONTROLFRAMESTRANSMITTED_TX 0x39ec8
80614 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS_TX 0x39ecc
80615 #define A_MAC_IOS_CTRL 0x3a000
80616 
80617 #define S_SUB_BLOCK_SEL    28
80618 #define M_SUB_BLOCK_SEL    0x7U
80619 #define V_SUB_BLOCK_SEL(x) ((x) << S_SUB_BLOCK_SEL)
80620 #define G_SUB_BLOCK_SEL(x) (((x) >> S_SUB_BLOCK_SEL) & M_SUB_BLOCK_SEL)
80621 
80622 #define S_QUAD_BROADCAST_EN    24
80623 #define V_QUAD_BROADCAST_EN(x) ((x) << S_QUAD_BROADCAST_EN)
80624 #define F_QUAD_BROADCAST_EN    V_QUAD_BROADCAST_EN(1U)
80625 
80626 #define S_AUTO_INCR    20
80627 #define V_AUTO_INCR(x) ((x) << S_AUTO_INCR)
80628 #define F_AUTO_INCR    V_AUTO_INCR(1U)
80629 
80630 #define S_T7_2_ADDR    0
80631 #define M_T7_2_ADDR    0x7ffffU
80632 #define V_T7_2_ADDR(x) ((x) << S_T7_2_ADDR)
80633 #define G_T7_2_ADDR(x) (((x) >> S_T7_2_ADDR) & M_T7_2_ADDR)
80634 
80635 #define A_MAC_IOS_DATA 0x3a004
80636 #define A_MAC_IOS_BGR_RST 0x3a050
80637 
80638 #define S_BGR_RSTN    0
80639 #define V_BGR_RSTN(x) ((x) << S_BGR_RSTN)
80640 #define F_BGR_RSTN    V_BGR_RSTN(1U)
80641 
80642 #define A_MAC_IOS_BGR_CFG 0x3a054
80643 
80644 #define S_SOC_REFCLK_EN    0
80645 #define V_SOC_REFCLK_EN(x) ((x) << S_SOC_REFCLK_EN)
80646 #define F_SOC_REFCLK_EN    V_SOC_REFCLK_EN(1U)
80647 
80648 #define A_MAC_IOS_QUAD0_CFG 0x3a058
80649 
80650 #define S_QUAD0_CH3_RSTN    5
80651 #define V_QUAD0_CH3_RSTN(x) ((x) << S_QUAD0_CH3_RSTN)
80652 #define F_QUAD0_CH3_RSTN    V_QUAD0_CH3_RSTN(1U)
80653 
80654 #define S_QUAD0_CH2_RSTN    4
80655 #define V_QUAD0_CH2_RSTN(x) ((x) << S_QUAD0_CH2_RSTN)
80656 #define F_QUAD0_CH2_RSTN    V_QUAD0_CH2_RSTN(1U)
80657 
80658 #define S_QUAD0_CH1_RSTN    3
80659 #define V_QUAD0_CH1_RSTN(x) ((x) << S_QUAD0_CH1_RSTN)
80660 #define F_QUAD0_CH1_RSTN    V_QUAD0_CH1_RSTN(1U)
80661 
80662 #define S_QUAD0_CH0_RSTN    2
80663 #define V_QUAD0_CH0_RSTN(x) ((x) << S_QUAD0_CH0_RSTN)
80664 #define F_QUAD0_CH0_RSTN    V_QUAD0_CH0_RSTN(1U)
80665 
80666 #define S_QUAD0_RSTN    1
80667 #define V_QUAD0_RSTN(x) ((x) << S_QUAD0_RSTN)
80668 #define F_QUAD0_RSTN    V_QUAD0_RSTN(1U)
80669 
80670 #define S_PLL0_RSTN    0
80671 #define V_PLL0_RSTN(x) ((x) << S_PLL0_RSTN)
80672 #define F_PLL0_RSTN    V_PLL0_RSTN(1U)
80673 
80674 #define A_MAC_IOS_QUAD1_CFG 0x3a05c
80675 
80676 #define S_QUAD1_CH3_RSTN    5
80677 #define V_QUAD1_CH3_RSTN(x) ((x) << S_QUAD1_CH3_RSTN)
80678 #define F_QUAD1_CH3_RSTN    V_QUAD1_CH3_RSTN(1U)
80679 
80680 #define S_QUAD1_CH2_RSTN    4
80681 #define V_QUAD1_CH2_RSTN(x) ((x) << S_QUAD1_CH2_RSTN)
80682 #define F_QUAD1_CH2_RSTN    V_QUAD1_CH2_RSTN(1U)
80683 
80684 #define S_QUAD1_CH1_RSTN    3
80685 #define V_QUAD1_CH1_RSTN(x) ((x) << S_QUAD1_CH1_RSTN)
80686 #define F_QUAD1_CH1_RSTN    V_QUAD1_CH1_RSTN(1U)
80687 
80688 #define S_QUAD1_CH0_RSTN    2
80689 #define V_QUAD1_CH0_RSTN(x) ((x) << S_QUAD1_CH0_RSTN)
80690 #define F_QUAD1_CH0_RSTN    V_QUAD1_CH0_RSTN(1U)
80691 
80692 #define S_QUAD1_RSTN    1
80693 #define V_QUAD1_RSTN(x) ((x) << S_QUAD1_RSTN)
80694 #define F_QUAD1_RSTN    V_QUAD1_RSTN(1U)
80695 
80696 #define S_PLL1_RSTN    0
80697 #define V_PLL1_RSTN(x) ((x) << S_PLL1_RSTN)
80698 #define F_PLL1_RSTN    V_PLL1_RSTN(1U)
80699 
80700 #define A_MAC_IOS_SCRATCHPAD0 0x3a060
80701 #define A_MAC_IOS_SCRATCHPAD1 0x3a064
80702 #define A_MAC_IOS_SCRATCHPAD2 0x3a068
80703 #define A_MAC_IOS_SCRATCHPAD3 0x3a06c
80704 
80705 #define S_DATA0    1
80706 #define M_DATA0    0x7fffffffU
80707 #define V_DATA0(x) ((x) << S_DATA0)
80708 #define G_DATA0(x) (((x) >> S_DATA0) & M_DATA0)
80709 
80710 #define S_I2C_MODE    0
80711 #define V_I2C_MODE(x) ((x) << S_I2C_MODE)
80712 #define F_I2C_MODE    V_I2C_MODE(1U)
80713 
80714 #define A_MAC_IOS_BGR_DBG_COUNTER 0x3a070
80715 #define A_MAC_IOS_QUAD0_DBG_COUNTER 0x3a074
80716 #define A_MAC_IOS_PLL0_DBG_COUNTER 0x3a078
80717 #define A_MAC_IOS_QUAD1_DBG_COUNTER 0x3a07c
80718 #define A_MAC_IOS_PLL1_DBG_COUNTER 0x3a080
80719 #define A_MAC_IOS_DBG_CLK_CFG 0x3a084
80720 
80721 #define S_DBG_CLK_MUX_GPIO    3
80722 #define V_DBG_CLK_MUX_GPIO(x) ((x) << S_DBG_CLK_MUX_GPIO)
80723 #define F_DBG_CLK_MUX_GPIO    V_DBG_CLK_MUX_GPIO(1U)
80724 
80725 #define S_DBG_CLK_MUX_SEL    0
80726 #define M_DBG_CLK_MUX_SEL    0x7U
80727 #define V_DBG_CLK_MUX_SEL(x) ((x) << S_DBG_CLK_MUX_SEL)
80728 #define G_DBG_CLK_MUX_SEL(x) (((x) >> S_DBG_CLK_MUX_SEL) & M_DBG_CLK_MUX_SEL)
80729 
80730 #define A_MAC_IOS_INTR_EN_QUAD0 0x3a090
80731 
80732 #define S_Q0_MAILBOX_INT_ASSERT    24
80733 #define V_Q0_MAILBOX_INT_ASSERT(x) ((x) << S_Q0_MAILBOX_INT_ASSERT)
80734 #define F_Q0_MAILBOX_INT_ASSERT    V_Q0_MAILBOX_INT_ASSERT(1U)
80735 
80736 #define S_Q0_TRAINING_FAILURE_3_ASSERT    23
80737 #define V_Q0_TRAINING_FAILURE_3_ASSERT(x) ((x) << S_Q0_TRAINING_FAILURE_3_ASSERT)
80738 #define F_Q0_TRAINING_FAILURE_3_ASSERT    V_Q0_TRAINING_FAILURE_3_ASSERT(1U)
80739 
80740 #define S_Q0_TRAINING_FAILURE_2_ASSERT    22
80741 #define V_Q0_TRAINING_FAILURE_2_ASSERT(x) ((x) << S_Q0_TRAINING_FAILURE_2_ASSERT)
80742 #define F_Q0_TRAINING_FAILURE_2_ASSERT    V_Q0_TRAINING_FAILURE_2_ASSERT(1U)
80743 
80744 #define S_Q0_TRAINING_FAILURE_1_ASSERT    21
80745 #define V_Q0_TRAINING_FAILURE_1_ASSERT(x) ((x) << S_Q0_TRAINING_FAILURE_1_ASSERT)
80746 #define F_Q0_TRAINING_FAILURE_1_ASSERT    V_Q0_TRAINING_FAILURE_1_ASSERT(1U)
80747 
80748 #define S_Q0_TRAINING_FAILURE_0_ASSERT    20
80749 #define V_Q0_TRAINING_FAILURE_0_ASSERT(x) ((x) << S_Q0_TRAINING_FAILURE_0_ASSERT)
80750 #define F_Q0_TRAINING_FAILURE_0_ASSERT    V_Q0_TRAINING_FAILURE_0_ASSERT(1U)
80751 
80752 #define S_Q0_TRAINING_COMPLETE_3_ASSERT    19
80753 #define V_Q0_TRAINING_COMPLETE_3_ASSERT(x) ((x) << S_Q0_TRAINING_COMPLETE_3_ASSERT)
80754 #define F_Q0_TRAINING_COMPLETE_3_ASSERT    V_Q0_TRAINING_COMPLETE_3_ASSERT(1U)
80755 
80756 #define S_Q0_TRAINING_COMPLETE_2_ASSERT    18
80757 #define V_Q0_TRAINING_COMPLETE_2_ASSERT(x) ((x) << S_Q0_TRAINING_COMPLETE_2_ASSERT)
80758 #define F_Q0_TRAINING_COMPLETE_2_ASSERT    V_Q0_TRAINING_COMPLETE_2_ASSERT(1U)
80759 
80760 #define S_Q0_TRAINING_COMPLETE_1_ASSERT    17
80761 #define V_Q0_TRAINING_COMPLETE_1_ASSERT(x) ((x) << S_Q0_TRAINING_COMPLETE_1_ASSERT)
80762 #define F_Q0_TRAINING_COMPLETE_1_ASSERT    V_Q0_TRAINING_COMPLETE_1_ASSERT(1U)
80763 
80764 #define S_Q0_TRAINING_COMPLETE_0_ASSERT    16
80765 #define V_Q0_TRAINING_COMPLETE_0_ASSERT(x) ((x) << S_Q0_TRAINING_COMPLETE_0_ASSERT)
80766 #define F_Q0_TRAINING_COMPLETE_0_ASSERT    V_Q0_TRAINING_COMPLETE_0_ASSERT(1U)
80767 
80768 #define S_Q0_AN_TX_INT_3_ASSERT    15
80769 #define V_Q0_AN_TX_INT_3_ASSERT(x) ((x) << S_Q0_AN_TX_INT_3_ASSERT)
80770 #define F_Q0_AN_TX_INT_3_ASSERT    V_Q0_AN_TX_INT_3_ASSERT(1U)
80771 
80772 #define S_Q0_AN_TX_INT_2_ASSERT    14
80773 #define V_Q0_AN_TX_INT_2_ASSERT(x) ((x) << S_Q0_AN_TX_INT_2_ASSERT)
80774 #define F_Q0_AN_TX_INT_2_ASSERT    V_Q0_AN_TX_INT_2_ASSERT(1U)
80775 
80776 #define S_Q0_AN_TX_INT_1_ASSERT    13
80777 #define V_Q0_AN_TX_INT_1_ASSERT(x) ((x) << S_Q0_AN_TX_INT_1_ASSERT)
80778 #define F_Q0_AN_TX_INT_1_ASSERT    V_Q0_AN_TX_INT_1_ASSERT(1U)
80779 
80780 #define S_Q0_AN_TX_INT_0_ASSERT    12
80781 #define V_Q0_AN_TX_INT_0_ASSERT(x) ((x) << S_Q0_AN_TX_INT_0_ASSERT)
80782 #define F_Q0_AN_TX_INT_0_ASSERT    V_Q0_AN_TX_INT_0_ASSERT(1U)
80783 
80784 #define S_Q0_SIGNAL_DETECT_3_ASSERT    11
80785 #define V_Q0_SIGNAL_DETECT_3_ASSERT(x) ((x) << S_Q0_SIGNAL_DETECT_3_ASSERT)
80786 #define F_Q0_SIGNAL_DETECT_3_ASSERT    V_Q0_SIGNAL_DETECT_3_ASSERT(1U)
80787 
80788 #define S_Q0_SIGNAL_DETECT_2_ASSERT    10
80789 #define V_Q0_SIGNAL_DETECT_2_ASSERT(x) ((x) << S_Q0_SIGNAL_DETECT_2_ASSERT)
80790 #define F_Q0_SIGNAL_DETECT_2_ASSERT    V_Q0_SIGNAL_DETECT_2_ASSERT(1U)
80791 
80792 #define S_Q0_SIGNAL_DETECT_1_ASSERT    9
80793 #define V_Q0_SIGNAL_DETECT_1_ASSERT(x) ((x) << S_Q0_SIGNAL_DETECT_1_ASSERT)
80794 #define F_Q0_SIGNAL_DETECT_1_ASSERT    V_Q0_SIGNAL_DETECT_1_ASSERT(1U)
80795 
80796 #define S_Q0_SIGNAL_DETECT_0_ASSERT    8
80797 #define V_Q0_SIGNAL_DETECT_0_ASSERT(x) ((x) << S_Q0_SIGNAL_DETECT_0_ASSERT)
80798 #define F_Q0_SIGNAL_DETECT_0_ASSERT    V_Q0_SIGNAL_DETECT_0_ASSERT(1U)
80799 
80800 #define S_Q0_CDR_LOL_3_ASSERT    7
80801 #define V_Q0_CDR_LOL_3_ASSERT(x) ((x) << S_Q0_CDR_LOL_3_ASSERT)
80802 #define F_Q0_CDR_LOL_3_ASSERT    V_Q0_CDR_LOL_3_ASSERT(1U)
80803 
80804 #define S_Q0_CDR_LOL_2_ASSERT    6
80805 #define V_Q0_CDR_LOL_2_ASSERT(x) ((x) << S_Q0_CDR_LOL_2_ASSERT)
80806 #define F_Q0_CDR_LOL_2_ASSERT    V_Q0_CDR_LOL_2_ASSERT(1U)
80807 
80808 #define S_Q0_CDR_LOL_1_ASSERT    5
80809 #define V_Q0_CDR_LOL_1_ASSERT(x) ((x) << S_Q0_CDR_LOL_1_ASSERT)
80810 #define F_Q0_CDR_LOL_1_ASSERT    V_Q0_CDR_LOL_1_ASSERT(1U)
80811 
80812 #define S_Q0_CDR_LOL_0_ASSERT    4
80813 #define V_Q0_CDR_LOL_0_ASSERT(x) ((x) << S_Q0_CDR_LOL_0_ASSERT)
80814 #define F_Q0_CDR_LOL_0_ASSERT    V_Q0_CDR_LOL_0_ASSERT(1U)
80815 
80816 #define S_Q0_LOS_3_ASSERT    3
80817 #define V_Q0_LOS_3_ASSERT(x) ((x) << S_Q0_LOS_3_ASSERT)
80818 #define F_Q0_LOS_3_ASSERT    V_Q0_LOS_3_ASSERT(1U)
80819 
80820 #define S_Q0_LOS_2_ASSERT    2
80821 #define V_Q0_LOS_2_ASSERT(x) ((x) << S_Q0_LOS_2_ASSERT)
80822 #define F_Q0_LOS_2_ASSERT    V_Q0_LOS_2_ASSERT(1U)
80823 
80824 #define S_Q0_LOS_1_ASSERT    1
80825 #define V_Q0_LOS_1_ASSERT(x) ((x) << S_Q0_LOS_1_ASSERT)
80826 #define F_Q0_LOS_1_ASSERT    V_Q0_LOS_1_ASSERT(1U)
80827 
80828 #define S_Q0_LOS_0_ASSERT    0
80829 #define V_Q0_LOS_0_ASSERT(x) ((x) << S_Q0_LOS_0_ASSERT)
80830 #define F_Q0_LOS_0_ASSERT    V_Q0_LOS_0_ASSERT(1U)
80831 
80832 #define A_MAC_IOS_INTR_CAUSE_QUAD0 0x3a094
80833 #define A_MAC_IOS_INTR_EN_QUAD1 0x3a098
80834 
80835 #define S_Q1_MAILBOX_INT_ASSERT    24
80836 #define V_Q1_MAILBOX_INT_ASSERT(x) ((x) << S_Q1_MAILBOX_INT_ASSERT)
80837 #define F_Q1_MAILBOX_INT_ASSERT    V_Q1_MAILBOX_INT_ASSERT(1U)
80838 
80839 #define S_Q1_TRAINING_FAILURE_3_ASSERT    23
80840 #define V_Q1_TRAINING_FAILURE_3_ASSERT(x) ((x) << S_Q1_TRAINING_FAILURE_3_ASSERT)
80841 #define F_Q1_TRAINING_FAILURE_3_ASSERT    V_Q1_TRAINING_FAILURE_3_ASSERT(1U)
80842 
80843 #define S_Q1_TRAINING_FAILURE_2_ASSERT    22
80844 #define V_Q1_TRAINING_FAILURE_2_ASSERT(x) ((x) << S_Q1_TRAINING_FAILURE_2_ASSERT)
80845 #define F_Q1_TRAINING_FAILURE_2_ASSERT    V_Q1_TRAINING_FAILURE_2_ASSERT(1U)
80846 
80847 #define S_Q1_TRAINING_FAILURE_1_ASSERT    21
80848 #define V_Q1_TRAINING_FAILURE_1_ASSERT(x) ((x) << S_Q1_TRAINING_FAILURE_1_ASSERT)
80849 #define F_Q1_TRAINING_FAILURE_1_ASSERT    V_Q1_TRAINING_FAILURE_1_ASSERT(1U)
80850 
80851 #define S_Q1_TRAINING_FAILURE_0_ASSERT    20
80852 #define V_Q1_TRAINING_FAILURE_0_ASSERT(x) ((x) << S_Q1_TRAINING_FAILURE_0_ASSERT)
80853 #define F_Q1_TRAINING_FAILURE_0_ASSERT    V_Q1_TRAINING_FAILURE_0_ASSERT(1U)
80854 
80855 #define S_Q1_TRAINING_COMPLETE_3_ASSERT    19
80856 #define V_Q1_TRAINING_COMPLETE_3_ASSERT(x) ((x) << S_Q1_TRAINING_COMPLETE_3_ASSERT)
80857 #define F_Q1_TRAINING_COMPLETE_3_ASSERT    V_Q1_TRAINING_COMPLETE_3_ASSERT(1U)
80858 
80859 #define S_Q1_TRAINING_COMPLETE_2_ASSERT    18
80860 #define V_Q1_TRAINING_COMPLETE_2_ASSERT(x) ((x) << S_Q1_TRAINING_COMPLETE_2_ASSERT)
80861 #define F_Q1_TRAINING_COMPLETE_2_ASSERT    V_Q1_TRAINING_COMPLETE_2_ASSERT(1U)
80862 
80863 #define S_Q1_TRAINING_COMPLETE_1_ASSERT    17
80864 #define V_Q1_TRAINING_COMPLETE_1_ASSERT(x) ((x) << S_Q1_TRAINING_COMPLETE_1_ASSERT)
80865 #define F_Q1_TRAINING_COMPLETE_1_ASSERT    V_Q1_TRAINING_COMPLETE_1_ASSERT(1U)
80866 
80867 #define S_Q1_TRAINING_COMPLETE_0_ASSERT    16
80868 #define V_Q1_TRAINING_COMPLETE_0_ASSERT(x) ((x) << S_Q1_TRAINING_COMPLETE_0_ASSERT)
80869 #define F_Q1_TRAINING_COMPLETE_0_ASSERT    V_Q1_TRAINING_COMPLETE_0_ASSERT(1U)
80870 
80871 #define S_Q1_AN_TX_INT_3_ASSERT    15
80872 #define V_Q1_AN_TX_INT_3_ASSERT(x) ((x) << S_Q1_AN_TX_INT_3_ASSERT)
80873 #define F_Q1_AN_TX_INT_3_ASSERT    V_Q1_AN_TX_INT_3_ASSERT(1U)
80874 
80875 #define S_Q1_AN_TX_INT_2_ASSERT    14
80876 #define V_Q1_AN_TX_INT_2_ASSERT(x) ((x) << S_Q1_AN_TX_INT_2_ASSERT)
80877 #define F_Q1_AN_TX_INT_2_ASSERT    V_Q1_AN_TX_INT_2_ASSERT(1U)
80878 
80879 #define S_Q1_AN_TX_INT_1_ASSERT    13
80880 #define V_Q1_AN_TX_INT_1_ASSERT(x) ((x) << S_Q1_AN_TX_INT_1_ASSERT)
80881 #define F_Q1_AN_TX_INT_1_ASSERT    V_Q1_AN_TX_INT_1_ASSERT(1U)
80882 
80883 #define S_Q1_AN_TX_INT_0_ASSERT    12
80884 #define V_Q1_AN_TX_INT_0_ASSERT(x) ((x) << S_Q1_AN_TX_INT_0_ASSERT)
80885 #define F_Q1_AN_TX_INT_0_ASSERT    V_Q1_AN_TX_INT_0_ASSERT(1U)
80886 
80887 #define S_Q1_SIGNAL_DETECT_3_ASSERT    11
80888 #define V_Q1_SIGNAL_DETECT_3_ASSERT(x) ((x) << S_Q1_SIGNAL_DETECT_3_ASSERT)
80889 #define F_Q1_SIGNAL_DETECT_3_ASSERT    V_Q1_SIGNAL_DETECT_3_ASSERT(1U)
80890 
80891 #define S_Q1_SIGNAL_DETECT_2_ASSERT    10
80892 #define V_Q1_SIGNAL_DETECT_2_ASSERT(x) ((x) << S_Q1_SIGNAL_DETECT_2_ASSERT)
80893 #define F_Q1_SIGNAL_DETECT_2_ASSERT    V_Q1_SIGNAL_DETECT_2_ASSERT(1U)
80894 
80895 #define S_Q1_SIGNAL_DETECT_1_ASSERT    9
80896 #define V_Q1_SIGNAL_DETECT_1_ASSERT(x) ((x) << S_Q1_SIGNAL_DETECT_1_ASSERT)
80897 #define F_Q1_SIGNAL_DETECT_1_ASSERT    V_Q1_SIGNAL_DETECT_1_ASSERT(1U)
80898 
80899 #define S_Q1_SIGNAL_DETECT_0_ASSERT    8
80900 #define V_Q1_SIGNAL_DETECT_0_ASSERT(x) ((x) << S_Q1_SIGNAL_DETECT_0_ASSERT)
80901 #define F_Q1_SIGNAL_DETECT_0_ASSERT    V_Q1_SIGNAL_DETECT_0_ASSERT(1U)
80902 
80903 #define S_Q1_CDR_LOL_3_ASSERT    7
80904 #define V_Q1_CDR_LOL_3_ASSERT(x) ((x) << S_Q1_CDR_LOL_3_ASSERT)
80905 #define F_Q1_CDR_LOL_3_ASSERT    V_Q1_CDR_LOL_3_ASSERT(1U)
80906 
80907 #define S_Q1_CDR_LOL_2_ASSERT    6
80908 #define V_Q1_CDR_LOL_2_ASSERT(x) ((x) << S_Q1_CDR_LOL_2_ASSERT)
80909 #define F_Q1_CDR_LOL_2_ASSERT    V_Q1_CDR_LOL_2_ASSERT(1U)
80910 
80911 #define S_Q1_CDR_LOL_1_ASSERT    5
80912 #define V_Q1_CDR_LOL_1_ASSERT(x) ((x) << S_Q1_CDR_LOL_1_ASSERT)
80913 #define F_Q1_CDR_LOL_1_ASSERT    V_Q1_CDR_LOL_1_ASSERT(1U)
80914 
80915 #define S_Q1_CDR_LOL_0_ASSERT    4
80916 #define V_Q1_CDR_LOL_0_ASSERT(x) ((x) << S_Q1_CDR_LOL_0_ASSERT)
80917 #define F_Q1_CDR_LOL_0_ASSERT    V_Q1_CDR_LOL_0_ASSERT(1U)
80918 
80919 #define S_Q1_LOS_3_ASSERT    3
80920 #define V_Q1_LOS_3_ASSERT(x) ((x) << S_Q1_LOS_3_ASSERT)
80921 #define F_Q1_LOS_3_ASSERT    V_Q1_LOS_3_ASSERT(1U)
80922 
80923 #define S_Q1_LOS_2_ASSERT    2
80924 #define V_Q1_LOS_2_ASSERT(x) ((x) << S_Q1_LOS_2_ASSERT)
80925 #define F_Q1_LOS_2_ASSERT    V_Q1_LOS_2_ASSERT(1U)
80926 
80927 #define S_Q1_LOS_1_ASSERT    1
80928 #define V_Q1_LOS_1_ASSERT(x) ((x) << S_Q1_LOS_1_ASSERT)
80929 #define F_Q1_LOS_1_ASSERT    V_Q1_LOS_1_ASSERT(1U)
80930 
80931 #define S_Q1_LOS_0_ASSERT    0
80932 #define V_Q1_LOS_0_ASSERT(x) ((x) << S_Q1_LOS_0_ASSERT)
80933 #define F_Q1_LOS_0_ASSERT    V_Q1_LOS_0_ASSERT(1U)
80934 
80935 #define A_MAC_IOS_INTR_CAUSE_QUAD1 0x3a09c
80936 #define A_MAC_MTIP_PCS_1G_0_CONTROL 0x3e000
80937 
80938 #define S_SPEED_SEL_1    13
80939 #define V_SPEED_SEL_1(x) ((x) << S_SPEED_SEL_1)
80940 #define F_SPEED_SEL_1    V_SPEED_SEL_1(1U)
80941 
80942 #define S_AUTO_NEG_ENA    12
80943 #define V_AUTO_NEG_ENA(x) ((x) << S_AUTO_NEG_ENA)
80944 #define F_AUTO_NEG_ENA    V_AUTO_NEG_ENA(1U)
80945 
80946 #define S_T7_POWER_DOWN    11
80947 #define V_T7_POWER_DOWN(x) ((x) << S_T7_POWER_DOWN)
80948 #define F_T7_POWER_DOWN    V_T7_POWER_DOWN(1U)
80949 
80950 #define S_RESTART_AUTO_NEG    9
80951 #define V_RESTART_AUTO_NEG(x) ((x) << S_RESTART_AUTO_NEG)
80952 #define F_RESTART_AUTO_NEG    V_RESTART_AUTO_NEG(1U)
80953 
80954 #define S_SPEED_SEL_0    6
80955 #define V_SPEED_SEL_0(x) ((x) << S_SPEED_SEL_0)
80956 #define F_SPEED_SEL_0    V_SPEED_SEL_0(1U)
80957 
80958 #define A_MAC_MTIP_PCS_1G_0_STATUS 0x3e004
80959 
80960 #define S_100BASE_T4    15
80961 #define V_100BASE_T4(x) ((x) << S_100BASE_T4)
80962 #define F_100BASE_T4    V_100BASE_T4(1U)
80963 
80964 #define S_100BASE_X_FULL_DUPLEX    14
80965 #define V_100BASE_X_FULL_DUPLEX(x) ((x) << S_100BASE_X_FULL_DUPLEX)
80966 #define F_100BASE_X_FULL_DUPLEX    V_100BASE_X_FULL_DUPLEX(1U)
80967 
80968 #define S_100BASE_X_HALF_DUPLEX    13
80969 #define V_100BASE_X_HALF_DUPLEX(x) ((x) << S_100BASE_X_HALF_DUPLEX)
80970 #define F_100BASE_X_HALF_DUPLEX    V_100BASE_X_HALF_DUPLEX(1U)
80971 
80972 #define S_10MBPS_FULL_DUPLEX    12
80973 #define V_10MBPS_FULL_DUPLEX(x) ((x) << S_10MBPS_FULL_DUPLEX)
80974 #define F_10MBPS_FULL_DUPLEX    V_10MBPS_FULL_DUPLEX(1U)
80975 
80976 #define S_10MBPS_HALF_DUPLEX    11
80977 #define V_10MBPS_HALF_DUPLEX(x) ((x) << S_10MBPS_HALF_DUPLEX)
80978 #define F_10MBPS_HALF_DUPLEX    V_10MBPS_HALF_DUPLEX(1U)
80979 
80980 #define S_100BASE_T2_HALF_DUPLEX1    10
80981 #define V_100BASE_T2_HALF_DUPLEX1(x) ((x) << S_100BASE_T2_HALF_DUPLEX1)
80982 #define F_100BASE_T2_HALF_DUPLEX1    V_100BASE_T2_HALF_DUPLEX1(1U)
80983 
80984 #define S_100BASE_T2_HALF_DUPLEX0    9
80985 #define V_100BASE_T2_HALF_DUPLEX0(x) ((x) << S_100BASE_T2_HALF_DUPLEX0)
80986 #define F_100BASE_T2_HALF_DUPLEX0    V_100BASE_T2_HALF_DUPLEX0(1U)
80987 
80988 #define S_T7_EXTENDED_STATUS    8
80989 #define V_T7_EXTENDED_STATUS(x) ((x) << S_T7_EXTENDED_STATUS)
80990 #define F_T7_EXTENDED_STATUS    V_T7_EXTENDED_STATUS(1U)
80991 
80992 #define S_AUTO_NEG_COMPLETE    5
80993 #define V_AUTO_NEG_COMPLETE(x) ((x) << S_AUTO_NEG_COMPLETE)
80994 #define F_AUTO_NEG_COMPLETE    V_AUTO_NEG_COMPLETE(1U)
80995 
80996 #define S_T7_REMOTE_FAULT    4
80997 #define V_T7_REMOTE_FAULT(x) ((x) << S_T7_REMOTE_FAULT)
80998 #define F_T7_REMOTE_FAULT    V_T7_REMOTE_FAULT(1U)
80999 
81000 #define S_AUTO_NEG_ABILITY    3
81001 #define V_AUTO_NEG_ABILITY(x) ((x) << S_AUTO_NEG_ABILITY)
81002 #define F_AUTO_NEG_ABILITY    V_AUTO_NEG_ABILITY(1U)
81003 
81004 #define S_JABBER_DETECT    1
81005 #define V_JABBER_DETECT(x) ((x) << S_JABBER_DETECT)
81006 #define F_JABBER_DETECT    V_JABBER_DETECT(1U)
81007 
81008 #define S_EXTENDED_CAPABILITY    0
81009 #define V_EXTENDED_CAPABILITY(x) ((x) << S_EXTENDED_CAPABILITY)
81010 #define F_EXTENDED_CAPABILITY    V_EXTENDED_CAPABILITY(1U)
81011 
81012 #define A_MAC_MTIP_PCS_1G_0_PHY_IDENTIFIER_0 0x3e008
81013 #define A_MAC_MTIP_PCS_1G_0_PHY_IDENTIFIER_1 0x3e00c
81014 #define A_MAC_MTIP_PCS_1G_0_DEV_ABILITY 0x3e010
81015 
81016 #define S_EEE_CLOCK_STOP_ENABLE    8
81017 #define V_EEE_CLOCK_STOP_ENABLE(x) ((x) << S_EEE_CLOCK_STOP_ENABLE)
81018 #define F_EEE_CLOCK_STOP_ENABLE    V_EEE_CLOCK_STOP_ENABLE(1U)
81019 
81020 #define A_MAC_MTIP_PCS_1G_0_PARTNER_ABILITY 0x3e014
81021 
81022 #define S_COPPER_LINK_STATUS    15
81023 #define V_COPPER_LINK_STATUS(x) ((x) << S_COPPER_LINK_STATUS)
81024 #define F_COPPER_LINK_STATUS    V_COPPER_LINK_STATUS(1U)
81025 
81026 #define S_COPPER_DUPLEX_STATUS    12
81027 #define V_COPPER_DUPLEX_STATUS(x) ((x) << S_COPPER_DUPLEX_STATUS)
81028 #define F_COPPER_DUPLEX_STATUS    V_COPPER_DUPLEX_STATUS(1U)
81029 
81030 #define S_COPPER_SPEED    10
81031 #define M_COPPER_SPEED    0x3U
81032 #define V_COPPER_SPEED(x) ((x) << S_COPPER_SPEED)
81033 #define G_COPPER_SPEED(x) (((x) >> S_COPPER_SPEED) & M_COPPER_SPEED)
81034 
81035 #define S_EEE_CAPABILITY    9
81036 #define V_EEE_CAPABILITY(x) ((x) << S_EEE_CAPABILITY)
81037 #define F_EEE_CAPABILITY    V_EEE_CAPABILITY(1U)
81038 
81039 #define S_EEE_CLOCK_STOP_CAPABILITY    8
81040 #define V_EEE_CLOCK_STOP_CAPABILITY(x) ((x) << S_EEE_CLOCK_STOP_CAPABILITY)
81041 #define F_EEE_CLOCK_STOP_CAPABILITY    V_EEE_CLOCK_STOP_CAPABILITY(1U)
81042 
81043 #define A_MAC_MTIP_PCS_1G_0_AN_EXPANSION 0x3e018
81044 #define A_MAC_MTIP_PCS_1G_0_NP_TX 0x3e01c
81045 #define A_MAC_MTIP_PCS_1G_0_LP_NP_RX 0x3e020
81046 
81047 #define S_T7_DATA    0
81048 #define M_T7_DATA    0x7ffU
81049 #define V_T7_DATA(x) ((x) << S_T7_DATA)
81050 #define G_T7_DATA(x) (((x) >> S_T7_DATA) & M_T7_DATA)
81051 
81052 #define A_MAC_MTIP_PCS_1G_0_EXTENDED_STATUS 0x3e03c
81053 #define A_MAC_MTIP_PCS_1G_0_SCRATCH 0x3e040
81054 #define A_MAC_MTIP_PCS_1G_0_REV 0x3e044
81055 #define A_MAC_MTIP_PCS_1G_0_LINK_TIMER_0 0x3e048
81056 
81057 #define S_LINK_TIMER_VAL    0
81058 #define M_LINK_TIMER_VAL    0xffffU
81059 #define V_LINK_TIMER_VAL(x) ((x) << S_LINK_TIMER_VAL)
81060 #define G_LINK_TIMER_VAL(x) (((x) >> S_LINK_TIMER_VAL) & M_LINK_TIMER_VAL)
81061 
81062 #define A_MAC_MTIP_PCS_1G_0_LINK_TIMER_1 0x3e04c
81063 
81064 #define S_T7_LINK_TIMER_VAL    0
81065 #define M_T7_LINK_TIMER_VAL    0x1fU
81066 #define V_T7_LINK_TIMER_VAL(x) ((x) << S_T7_LINK_TIMER_VAL)
81067 #define G_T7_LINK_TIMER_VAL(x) (((x) >> S_T7_LINK_TIMER_VAL) & M_T7_LINK_TIMER_VAL)
81068 
81069 #define A_MAC_MTIP_PCS_1G_0_IF_MODE 0x3e050
81070 #define A_MAC_MTIP_PCS_1G_0_DEC_ERR_CNT 0x3e054
81071 #define A_MAC_MTIP_PCS_1G_0_VENDOR_CONTROL 0x3e058
81072 
81073 #define S_SGPCS_ENA_ST    15
81074 #define V_SGPCS_ENA_ST(x) ((x) << S_SGPCS_ENA_ST)
81075 #define F_SGPCS_ENA_ST    V_SGPCS_ENA_ST(1U)
81076 
81077 #define S_T7_CFG_CLOCK_RATE    4
81078 #define M_T7_CFG_CLOCK_RATE    0xfU
81079 #define V_T7_CFG_CLOCK_RATE(x) ((x) << S_T7_CFG_CLOCK_RATE)
81080 #define G_T7_CFG_CLOCK_RATE(x) (((x) >> S_T7_CFG_CLOCK_RATE) & M_T7_CFG_CLOCK_RATE)
81081 
81082 #define S_SGPCS_ENA_R    0
81083 #define V_SGPCS_ENA_R(x) ((x) << S_SGPCS_ENA_R)
81084 #define F_SGPCS_ENA_R    V_SGPCS_ENA_R(1U)
81085 
81086 #define A_MAC_MTIP_PCS_1G_0_SD_BIT_SLIP 0x3e05c
81087 
81088 #define S_SD_BIT_SLIP    0
81089 #define M_SD_BIT_SLIP    0xfU
81090 #define V_SD_BIT_SLIP(x) ((x) << S_SD_BIT_SLIP)
81091 #define G_SD_BIT_SLIP(x) (((x) >> S_SD_BIT_SLIP) & M_SD_BIT_SLIP)
81092 
81093 #define A_MAC_MTIP_PCS_1G_1_CONTROL 0x3e100
81094 #define A_MAC_MTIP_PCS_1G_1_STATUS 0x3e104
81095 #define A_MAC_MTIP_PCS_1G_1_PHY_IDENTIFIER_0 0x3e108
81096 #define A_MAC_MTIP_PCS_1G_1_PHY_IDENTIFIER_1 0x3e10c
81097 #define A_MAC_MTIP_PCS_1G_1_DEV_ABILITY 0x3e110
81098 #define A_MAC_MTIP_PCS_1G_1_PARTNER_ABILITY 0x3e114
81099 #define A_MAC_MTIP_PCS_1G_1_AN_EXPANSION 0x3e118
81100 #define A_MAC_MTIP_PCS_1G_1_NP_TX 0x3e11c
81101 #define A_MAC_MTIP_PCS_1G_1_LP_NP_RX 0x3e120
81102 #define A_MAC_MTIP_PCS_1G_1_EXTENDED_STATUS 0x3e13c
81103 #define A_MAC_MTIP_PCS_1G_1_SCRATCH 0x3e140
81104 #define A_MAC_MTIP_PCS_1G_1_REV 0x3e144
81105 #define A_MAC_MTIP_PCS_1G_1_LINK_TIMER_0 0x3e148
81106 #define A_MAC_MTIP_PCS_1G_1_LINK_TIMER_1 0x3e14c
81107 #define A_MAC_MTIP_PCS_1G_1_IF_MODE 0x3e150
81108 #define A_MAC_MTIP_PCS_1G_1_DEC_ERR_CNT 0x3e154
81109 #define A_MAC_MTIP_PCS_1G_1_VENDOR_CONTROL 0x3e158
81110 #define A_MAC_MTIP_PCS_1G_1_SD_BIT_SLIP 0x3e15c
81111 #define A_MAC_MTIP_PCS_1G_2_CONTROL 0x3e200
81112 #define A_MAC_MTIP_PCS_1G_2_STATUS 0x3e204
81113 #define A_MAC_MTIP_PCS_1G_2_PHY_IDENTIFIER_0 0x3e208
81114 #define A_MAC_MTIP_PCS_1G_2_PHY_IDENTIFIER_1 0x3e20c
81115 #define A_MAC_MTIP_PCS_1G_2_DEV_ABILITY 0x3e210
81116 #define A_MAC_MTIP_PCS_1G_2_PARTNER_ABILITY 0x3e214
81117 #define A_MAC_MTIP_PCS_1G_2_AN_EXPANSION 0x3e218
81118 #define A_MAC_MTIP_PCS_1G_2_NP_TX 0x3e21c
81119 #define A_MAC_MTIP_PCS_1G_2_LP_NP_RX 0x3e220
81120 #define A_MAC_MTIP_PCS_1G_2_EXTENDED_STATUS 0x3e23c
81121 #define A_MAC_MTIP_PCS_1G_2_SCRATCH 0x3e240
81122 #define A_MAC_MTIP_PCS_1G_2_REV 0x3e244
81123 #define A_MAC_MTIP_PCS_1G_2_LINK_TIMER_0 0x3e248
81124 #define A_MAC_MTIP_PCS_1G_2_LINK_TIMER_1 0x3e24c
81125 #define A_MAC_MTIP_PCS_1G_2_IF_MODE 0x3e250
81126 #define A_MAC_MTIP_PCS_1G_2_DEC_ERR_CNT 0x3e254
81127 #define A_MAC_MTIP_PCS_1G_2_VENDOR_CONTROL 0x3e258
81128 #define A_MAC_MTIP_PCS_1G_2_SD_BIT_SLIP 0x3e25c
81129 #define A_MAC_MTIP_PCS_1G_3_CONTROL 0x3e300
81130 #define A_MAC_MTIP_PCS_1G_3_STATUS 0x3e304
81131 #define A_MAC_MTIP_PCS_1G_3_PHY_IDENTIFIER_0 0x3e308
81132 #define A_MAC_MTIP_PCS_1G_3_PHY_IDENTIFIER_1 0x3e30c
81133 #define A_MAC_MTIP_PCS_1G_3_DEV_ABILITY 0x3e310
81134 #define A_MAC_MTIP_PCS_1G_3_PARTNER_ABILITY 0x3e314
81135 #define A_MAC_MTIP_PCS_1G_3_AN_EXPANSION 0x3e318
81136 #define A_MAC_MTIP_PCS_1G_3_NP_TX 0x3e31c
81137 #define A_MAC_MTIP_PCS_1G_3_LP_NP_RX 0x3e320
81138 #define A_MAC_MTIP_PCS_1G_3_EXTENDED_STATUS 0x3e33c
81139 #define A_MAC_MTIP_PCS_1G_3_SCRATCH 0x3e340
81140 #define A_MAC_MTIP_PCS_1G_3_REV 0x3e344
81141 #define A_MAC_MTIP_PCS_1G_3_LINK_TIMER_0 0x3e348
81142 #define A_MAC_MTIP_PCS_1G_3_LINK_TIMER_1 0x3e34c
81143 #define A_MAC_MTIP_PCS_1G_3_IF_MODE 0x3e350
81144 #define A_MAC_MTIP_PCS_1G_3_DEC_ERR_CNT 0x3e354
81145 #define A_MAC_MTIP_PCS_1G_3_VENDOR_CONTROL 0x3e358
81146 #define A_MAC_MTIP_PCS_1G_3_SD_BIT_SLIP 0x3e35c
81147 #define A_MAC_DPLL_CTRL_0 0x3f000
81148 
81149 #define S_LOCAL_FAULT_OVRD    18
81150 #define V_LOCAL_FAULT_OVRD(x) ((x) << S_LOCAL_FAULT_OVRD)
81151 #define F_LOCAL_FAULT_OVRD    V_LOCAL_FAULT_OVRD(1U)
81152 
81153 #define S_LOCAL_FAULT_HOLD_EN    17
81154 #define V_LOCAL_FAULT_HOLD_EN(x) ((x) << S_LOCAL_FAULT_HOLD_EN)
81155 #define F_LOCAL_FAULT_HOLD_EN    V_LOCAL_FAULT_HOLD_EN(1U)
81156 
81157 #define S_DPLL_RST    16
81158 #define V_DPLL_RST(x) ((x) << S_DPLL_RST)
81159 #define F_DPLL_RST    V_DPLL_RST(1U)
81160 
81161 #define S_CNTOFFSET    0
81162 #define M_CNTOFFSET    0xffffU
81163 #define V_CNTOFFSET(x) ((x) << S_CNTOFFSET)
81164 #define G_CNTOFFSET(x) (((x) >> S_CNTOFFSET) & M_CNTOFFSET)
81165 
81166 #define A_MAC_DPLL_CTRL_1 0x3f004
81167 
81168 #define S_DELAYK    0
81169 #define M_DELAYK    0xffffffU
81170 #define V_DELAYK(x) ((x) << S_DELAYK)
81171 #define G_DELAYK(x) (((x) >> S_DELAYK) & M_DELAYK)
81172 
81173 #define A_MAC_DPLL_CTRL_2 0x3f008
81174 
81175 #define S_DIVFFB    16
81176 #define M_DIVFFB    0xffffU
81177 #define V_DIVFFB(x) ((x) << S_DIVFFB)
81178 #define G_DIVFFB(x) (((x) >> S_DIVFFB) & M_DIVFFB)
81179 
81180 #define S_DIVFIN    0
81181 #define M_DIVFIN    0xffffU
81182 #define V_DIVFIN(x) ((x) << S_DIVFIN)
81183 #define G_DIVFIN(x) (((x) >> S_DIVFIN) & M_DIVFIN)
81184 
81185 #define A_MAC_DPLL_CTRL_3 0x3f00c
81186 
81187 #define S_ISHIFT_HOLD    28
81188 #define M_ISHIFT_HOLD    0xfU
81189 #define V_ISHIFT_HOLD(x) ((x) << S_ISHIFT_HOLD)
81190 #define G_ISHIFT_HOLD(x) (((x) >> S_ISHIFT_HOLD) & M_ISHIFT_HOLD)
81191 
81192 #define S_ISHIFT    24
81193 #define M_ISHIFT    0xfU
81194 #define V_ISHIFT(x) ((x) << S_ISHIFT)
81195 #define G_ISHIFT(x) (((x) >> S_ISHIFT) & M_ISHIFT)
81196 
81197 #define S_INT_PRESET    12
81198 #define M_INT_PRESET    0xfffU
81199 #define V_INT_PRESET(x) ((x) << S_INT_PRESET)
81200 #define G_INT_PRESET(x) (((x) >> S_INT_PRESET) & M_INT_PRESET)
81201 
81202 #define S_FMI    4
81203 #define M_FMI    0xffU
81204 #define V_FMI(x) ((x) << S_FMI)
81205 #define G_FMI(x) (((x) >> S_FMI) & M_FMI)
81206 
81207 #define S_DPLL_PROGRAM    3
81208 #define V_DPLL_PROGRAM(x) ((x) << S_DPLL_PROGRAM)
81209 #define F_DPLL_PROGRAM    V_DPLL_PROGRAM(1U)
81210 
81211 #define S_PRESET_EN    2
81212 #define V_PRESET_EN(x) ((x) << S_PRESET_EN)
81213 #define F_PRESET_EN    V_PRESET_EN(1U)
81214 
81215 #define S_ONTARGETOV    1
81216 #define V_ONTARGETOV(x) ((x) << S_ONTARGETOV)
81217 #define F_ONTARGETOV    V_ONTARGETOV(1U)
81218 
81219 #define S_FDONLY    0
81220 #define V_FDONLY(x) ((x) << S_FDONLY)
81221 #define F_FDONLY    V_FDONLY(1U)
81222 
81223 #define A_MAC_DPLL_CTRL_4 0x3f010
81224 
81225 #define S_FKI    24
81226 #define M_FKI    0x1fU
81227 #define V_FKI(x) ((x) << S_FKI)
81228 #define G_FKI(x) (((x) >> S_FKI) & M_FKI)
81229 
81230 #define S_FRAC_PRESET    0
81231 #define M_FRAC_PRESET    0xffffffU
81232 #define V_FRAC_PRESET(x) ((x) << S_FRAC_PRESET)
81233 #define G_FRAC_PRESET(x) (((x) >> S_FRAC_PRESET) & M_FRAC_PRESET)
81234 
81235 #define A_MAC_DPLL_CTRL_5 0x3f014
81236 
81237 #define S_PH_STEP_CNT_HOLD    24
81238 #define M_PH_STEP_CNT_HOLD    0x1fU
81239 #define V_PH_STEP_CNT_HOLD(x) ((x) << S_PH_STEP_CNT_HOLD)
81240 #define G_PH_STEP_CNT_HOLD(x) (((x) >> S_PH_STEP_CNT_HOLD) & M_PH_STEP_CNT_HOLD)
81241 
81242 #define S_CFG_RESET    23
81243 #define V_CFG_RESET(x) ((x) << S_CFG_RESET)
81244 #define F_CFG_RESET    V_CFG_RESET(1U)
81245 
81246 #define S_PH_STEP_CNT    16
81247 #define M_PH_STEP_CNT    0x1fU
81248 #define V_PH_STEP_CNT(x) ((x) << S_PH_STEP_CNT)
81249 #define G_PH_STEP_CNT(x) (((x) >> S_PH_STEP_CNT) & M_PH_STEP_CNT)
81250 
81251 #define S_OTDLY    0
81252 #define M_OTDLY    0xffffU
81253 #define V_OTDLY(x) ((x) << S_OTDLY)
81254 #define G_OTDLY(x) (((x) >> S_OTDLY) & M_OTDLY)
81255 
81256 #define A_MAC_DPLL_CTRL_6 0x3f018
81257 
81258 #define S_TARGETCNT    16
81259 #define M_TARGETCNT    0xffffU
81260 #define V_TARGETCNT(x) ((x) << S_TARGETCNT)
81261 #define G_TARGETCNT(x) (((x) >> S_TARGETCNT) & M_TARGETCNT)
81262 
81263 #define S_PKP    8
81264 #define M_PKP    0x1fU
81265 #define V_PKP(x) ((x) << S_PKP)
81266 #define G_PKP(x) (((x) >> S_PKP) & M_PKP)
81267 
81268 #define S_PMP    0
81269 #define M_PMP    0xffU
81270 #define V_PMP(x) ((x) << S_PMP)
81271 #define G_PMP(x) (((x) >> S_PMP) & M_PMP)
81272 
81273 #define A_MAC_DPLL_CTRL_7 0x3f01c
81274 #define A_MAC_DPLL_STATUS_0 0x3f020
81275 
81276 #define S_FRAC    0
81277 #define M_FRAC    0xffffffU
81278 #define V_FRAC(x) ((x) << S_FRAC)
81279 #define G_FRAC(x) (((x) >> S_FRAC) & M_FRAC)
81280 
81281 #define A_MAC_DPLL_STATUS_1 0x3f024
81282 
81283 #define S_FRAC_PD_OUT    0
81284 #define M_FRAC_PD_OUT    0xffffffU
81285 #define V_FRAC_PD_OUT(x) ((x) << S_FRAC_PD_OUT)
81286 #define G_FRAC_PD_OUT(x) (((x) >> S_FRAC_PD_OUT) & M_FRAC_PD_OUT)
81287 
81288 #define A_MAC_DPLL_STATUS_2 0x3f028
81289 
81290 #define S_INT    12
81291 #define M_INT    0xfffU
81292 #define V_INT(x) ((x) << S_INT)
81293 #define G_INT(x) (((x) >> S_INT) & M_INT)
81294 
81295 #define S_INT_PD_OUT    0
81296 #define M_INT_PD_OUT    0xfffU
81297 #define V_INT_PD_OUT(x) ((x) << S_INT_PD_OUT)
81298 #define G_INT_PD_OUT(x) (((x) >> S_INT_PD_OUT) & M_INT_PD_OUT)
81299 
81300 #define A_MAC_FRAC_N_PLL_CTRL_0 0x3f02c
81301 
81302 #define S_FRAC_N_DSKEWCALCNT    29
81303 #define M_FRAC_N_DSKEWCALCNT    0x7U
81304 #define V_FRAC_N_DSKEWCALCNT(x) ((x) << S_FRAC_N_DSKEWCALCNT)
81305 #define G_FRAC_N_DSKEWCALCNT(x) (((x) >> S_FRAC_N_DSKEWCALCNT) & M_FRAC_N_DSKEWCALCNT)
81306 
81307 #define S_PLLEN    28
81308 #define V_PLLEN(x) ((x) << S_PLLEN)
81309 #define F_PLLEN    V_PLLEN(1U)
81310 
81311 #define S_T7_BYPASS    24
81312 #define M_T7_BYPASS    0xfU
81313 #define V_T7_BYPASS(x) ((x) << S_T7_BYPASS)
81314 #define G_T7_BYPASS(x) (((x) >> S_T7_BYPASS) & M_T7_BYPASS)
81315 
81316 #define S_POSTDIV3A    21
81317 #define M_POSTDIV3A    0x7U
81318 #define V_POSTDIV3A(x) ((x) << S_POSTDIV3A)
81319 #define G_POSTDIV3A(x) (((x) >> S_POSTDIV3A) & M_POSTDIV3A)
81320 
81321 #define S_POSTDIV3B    18
81322 #define M_POSTDIV3B    0x7U
81323 #define V_POSTDIV3B(x) ((x) << S_POSTDIV3B)
81324 #define G_POSTDIV3B(x) (((x) >> S_POSTDIV3B) & M_POSTDIV3B)
81325 
81326 #define S_POSTDIV2A    15
81327 #define M_POSTDIV2A    0x7U
81328 #define V_POSTDIV2A(x) ((x) << S_POSTDIV2A)
81329 #define G_POSTDIV2A(x) (((x) >> S_POSTDIV2A) & M_POSTDIV2A)
81330 
81331 #define S_POSTDIV2B    12
81332 #define M_POSTDIV2B    0x7U
81333 #define V_POSTDIV2B(x) ((x) << S_POSTDIV2B)
81334 #define G_POSTDIV2B(x) (((x) >> S_POSTDIV2B) & M_POSTDIV2B)
81335 
81336 #define S_POSTDIV1A    9
81337 #define M_POSTDIV1A    0x7U
81338 #define V_POSTDIV1A(x) ((x) << S_POSTDIV1A)
81339 #define G_POSTDIV1A(x) (((x) >> S_POSTDIV1A) & M_POSTDIV1A)
81340 
81341 #define S_POSTDIV1B    6
81342 #define M_POSTDIV1B    0x7U
81343 #define V_POSTDIV1B(x) ((x) << S_POSTDIV1B)
81344 #define G_POSTDIV1B(x) (((x) >> S_POSTDIV1B) & M_POSTDIV1B)
81345 
81346 #define S_POSTDIV0A    3
81347 #define M_POSTDIV0A    0x7U
81348 #define V_POSTDIV0A(x) ((x) << S_POSTDIV0A)
81349 #define G_POSTDIV0A(x) (((x) >> S_POSTDIV0A) & M_POSTDIV0A)
81350 
81351 #define S_POSTDIV0B    0
81352 #define M_POSTDIV0B    0x7U
81353 #define V_POSTDIV0B(x) ((x) << S_POSTDIV0B)
81354 #define G_POSTDIV0B(x) (((x) >> S_POSTDIV0B) & M_POSTDIV0B)
81355 
81356 #define A_MAC_FRAC_N_PLL_CTRL_1 0x3f030
81357 
81358 #define S_FRAC_N_FRAC_N_FOUTEN    28
81359 #define M_FRAC_N_FRAC_N_FOUTEN    0xfU
81360 #define V_FRAC_N_FRAC_N_FOUTEN(x) ((x) << S_FRAC_N_FRAC_N_FOUTEN)
81361 #define G_FRAC_N_FRAC_N_FOUTEN(x) (((x) >> S_FRAC_N_FRAC_N_FOUTEN) & M_FRAC_N_FRAC_N_FOUTEN)
81362 
81363 #define S_FRAC_N_DSKEWCALIN    16
81364 #define M_FRAC_N_DSKEWCALIN    0xfffU
81365 #define V_FRAC_N_DSKEWCALIN(x) ((x) << S_FRAC_N_DSKEWCALIN)
81366 #define G_FRAC_N_DSKEWCALIN(x) (((x) >> S_FRAC_N_DSKEWCALIN) & M_FRAC_N_DSKEWCALIN)
81367 
81368 #define S_FRAC_N_REFDIV    10
81369 #define M_FRAC_N_REFDIV    0x3fU
81370 #define V_FRAC_N_REFDIV(x) ((x) << S_FRAC_N_REFDIV)
81371 #define G_FRAC_N_REFDIV(x) (((x) >> S_FRAC_N_REFDIV) & M_FRAC_N_REFDIV)
81372 
81373 #define S_FRAC_N_DSMEN    9
81374 #define V_FRAC_N_DSMEN(x) ((x) << S_FRAC_N_DSMEN)
81375 #define F_FRAC_N_DSMEN    V_FRAC_N_DSMEN(1U)
81376 
81377 #define S_FRAC_N_PLLEN    8
81378 #define V_FRAC_N_PLLEN(x) ((x) << S_FRAC_N_PLLEN)
81379 #define F_FRAC_N_PLLEN    V_FRAC_N_PLLEN(1U)
81380 
81381 #define S_FRAC_N_DACEN    7
81382 #define V_FRAC_N_DACEN(x) ((x) << S_FRAC_N_DACEN)
81383 #define F_FRAC_N_DACEN    V_FRAC_N_DACEN(1U)
81384 
81385 #define S_FRAC_N_POSTDIV0PRE    6
81386 #define V_FRAC_N_POSTDIV0PRE(x) ((x) << S_FRAC_N_POSTDIV0PRE)
81387 #define F_FRAC_N_POSTDIV0PRE    V_FRAC_N_POSTDIV0PRE(1U)
81388 
81389 #define S_FRAC_N_DSKEWCALBYP    5
81390 #define V_FRAC_N_DSKEWCALBYP(x) ((x) << S_FRAC_N_DSKEWCALBYP)
81391 #define F_FRAC_N_DSKEWCALBYP    V_FRAC_N_DSKEWCALBYP(1U)
81392 
81393 #define S_FRAC_N_DSKEWFASTCAL    4
81394 #define V_FRAC_N_DSKEWFASTCAL(x) ((x) << S_FRAC_N_DSKEWFASTCAL)
81395 #define F_FRAC_N_DSKEWFASTCAL    V_FRAC_N_DSKEWFASTCAL(1U)
81396 
81397 #define S_FRAC_N_DSKEWCALEN    3
81398 #define V_FRAC_N_DSKEWCALEN(x) ((x) << S_FRAC_N_DSKEWCALEN)
81399 #define F_FRAC_N_DSKEWCALEN    V_FRAC_N_DSKEWCALEN(1U)
81400 
81401 #define S_FRAC_N_FREFCMLEN    2
81402 #define V_FRAC_N_FREFCMLEN(x) ((x) << S_FRAC_N_FREFCMLEN)
81403 #define F_FRAC_N_FREFCMLEN    V_FRAC_N_FREFCMLEN(1U)
81404 
81405 #define A_MAC_FRAC_N_PLL_STATUS_0 0x3f034
81406 
81407 #define S_DSKEWCALLOCK    12
81408 #define V_DSKEWCALLOCK(x) ((x) << S_DSKEWCALLOCK)
81409 #define F_DSKEWCALLOCK    V_DSKEWCALLOCK(1U)
81410 
81411 #define S_DSKEWCALOUT    0
81412 #define M_DSKEWCALOUT    0xfffU
81413 #define V_DSKEWCALOUT(x) ((x) << S_DSKEWCALOUT)
81414 #define G_DSKEWCALOUT(x) (((x) >> S_DSKEWCALOUT) & M_DSKEWCALOUT)
81415 
81416 #define A_MAC_MTIP_PCS_STATUS_0 0x3f100
81417 
81418 #define S_XLGMII7_TX_TSU    22
81419 #define M_XLGMII7_TX_TSU    0x3U
81420 #define V_XLGMII7_TX_TSU(x) ((x) << S_XLGMII7_TX_TSU)
81421 #define G_XLGMII7_TX_TSU(x) (((x) >> S_XLGMII7_TX_TSU) & M_XLGMII7_TX_TSU)
81422 
81423 #define S_XLGMII6_TX_TSU    20
81424 #define M_XLGMII6_TX_TSU    0x3U
81425 #define V_XLGMII6_TX_TSU(x) ((x) << S_XLGMII6_TX_TSU)
81426 #define G_XLGMII6_TX_TSU(x) (((x) >> S_XLGMII6_TX_TSU) & M_XLGMII6_TX_TSU)
81427 
81428 #define S_XLGMII5_TX_TSU    18
81429 #define M_XLGMII5_TX_TSU    0x3U
81430 #define V_XLGMII5_TX_TSU(x) ((x) << S_XLGMII5_TX_TSU)
81431 #define G_XLGMII5_TX_TSU(x) (((x) >> S_XLGMII5_TX_TSU) & M_XLGMII5_TX_TSU)
81432 
81433 #define S_XLGMII4_TX_TSU    16
81434 #define M_XLGMII4_TX_TSU    0x3U
81435 #define V_XLGMII4_TX_TSU(x) ((x) << S_XLGMII4_TX_TSU)
81436 #define G_XLGMII4_TX_TSU(x) (((x) >> S_XLGMII4_TX_TSU) & M_XLGMII4_TX_TSU)
81437 
81438 #define S_XLGMII3_TX_TSU    14
81439 #define M_XLGMII3_TX_TSU    0x3U
81440 #define V_XLGMII3_TX_TSU(x) ((x) << S_XLGMII3_TX_TSU)
81441 #define G_XLGMII3_TX_TSU(x) (((x) >> S_XLGMII3_TX_TSU) & M_XLGMII3_TX_TSU)
81442 
81443 #define S_XLGMII2_TX_TSU    12
81444 #define M_XLGMII2_TX_TSU    0x3U
81445 #define V_XLGMII2_TX_TSU(x) ((x) << S_XLGMII2_TX_TSU)
81446 #define G_XLGMII2_TX_TSU(x) (((x) >> S_XLGMII2_TX_TSU) & M_XLGMII2_TX_TSU)
81447 
81448 #define S_XLGMII1_TX_TSU    10
81449 #define M_XLGMII1_TX_TSU    0x3U
81450 #define V_XLGMII1_TX_TSU(x) ((x) << S_XLGMII1_TX_TSU)
81451 #define G_XLGMII1_TX_TSU(x) (((x) >> S_XLGMII1_TX_TSU) & M_XLGMII1_TX_TSU)
81452 
81453 #define S_XLGMII0_TX_TSU    8
81454 #define M_XLGMII0_TX_TSU    0x3U
81455 #define V_XLGMII0_TX_TSU(x) ((x) << S_XLGMII0_TX_TSU)
81456 #define G_XLGMII0_TX_TSU(x) (((x) >> S_XLGMII0_TX_TSU) & M_XLGMII0_TX_TSU)
81457 
81458 #define S_CGMII3_TX_TSU    6
81459 #define M_CGMII3_TX_TSU    0x3U
81460 #define V_CGMII3_TX_TSU(x) ((x) << S_CGMII3_TX_TSU)
81461 #define G_CGMII3_TX_TSU(x) (((x) >> S_CGMII3_TX_TSU) & M_CGMII3_TX_TSU)
81462 
81463 #define S_CGMII2_TX_TSU    4
81464 #define M_CGMII2_TX_TSU    0x3U
81465 #define V_CGMII2_TX_TSU(x) ((x) << S_CGMII2_TX_TSU)
81466 #define G_CGMII2_TX_TSU(x) (((x) >> S_CGMII2_TX_TSU) & M_CGMII2_TX_TSU)
81467 
81468 #define S_CGMII1_TX_TSU    2
81469 #define M_CGMII1_TX_TSU    0x3U
81470 #define V_CGMII1_TX_TSU(x) ((x) << S_CGMII1_TX_TSU)
81471 #define G_CGMII1_TX_TSU(x) (((x) >> S_CGMII1_TX_TSU) & M_CGMII1_TX_TSU)
81472 
81473 #define S_CGMII0_TX_TSU    0
81474 #define M_CGMII0_TX_TSU    0x3U
81475 #define V_CGMII0_TX_TSU(x) ((x) << S_CGMII0_TX_TSU)
81476 #define G_CGMII0_TX_TSU(x) (((x) >> S_CGMII0_TX_TSU) & M_CGMII0_TX_TSU)
81477 
81478 #define A_MAC_MTIP_PCS_STATUS_1 0x3f104
81479 
81480 #define S_CDMII1_RX_TSU    26
81481 #define M_CDMII1_RX_TSU    0x3U
81482 #define V_CDMII1_RX_TSU(x) ((x) << S_CDMII1_RX_TSU)
81483 #define G_CDMII1_RX_TSU(x) (((x) >> S_CDMII1_RX_TSU) & M_CDMII1_RX_TSU)
81484 
81485 #define S_CDMII0_RX_TSU    24
81486 #define M_CDMII0_RX_TSU    0x3U
81487 #define V_CDMII0_RX_TSU(x) ((x) << S_CDMII0_RX_TSU)
81488 #define G_CDMII0_RX_TSU(x) (((x) >> S_CDMII0_RX_TSU) & M_CDMII0_RX_TSU)
81489 
81490 #define S_XLGMII7_RX_TSU    22
81491 #define M_XLGMII7_RX_TSU    0x3U
81492 #define V_XLGMII7_RX_TSU(x) ((x) << S_XLGMII7_RX_TSU)
81493 #define G_XLGMII7_RX_TSU(x) (((x) >> S_XLGMII7_RX_TSU) & M_XLGMII7_RX_TSU)
81494 
81495 #define S_XLGMII6_RX_TSU    20
81496 #define M_XLGMII6_RX_TSU    0x3U
81497 #define V_XLGMII6_RX_TSU(x) ((x) << S_XLGMII6_RX_TSU)
81498 #define G_XLGMII6_RX_TSU(x) (((x) >> S_XLGMII6_RX_TSU) & M_XLGMII6_RX_TSU)
81499 
81500 #define S_XLGMII5_RX_TSU    18
81501 #define M_XLGMII5_RX_TSU    0x3U
81502 #define V_XLGMII5_RX_TSU(x) ((x) << S_XLGMII5_RX_TSU)
81503 #define G_XLGMII5_RX_TSU(x) (((x) >> S_XLGMII5_RX_TSU) & M_XLGMII5_RX_TSU)
81504 
81505 #define S_XLGMII4_RX_TSU    16
81506 #define M_XLGMII4_RX_TSU    0x3U
81507 #define V_XLGMII4_RX_TSU(x) ((x) << S_XLGMII4_RX_TSU)
81508 #define G_XLGMII4_RX_TSU(x) (((x) >> S_XLGMII4_RX_TSU) & M_XLGMII4_RX_TSU)
81509 
81510 #define S_XLGMII3_RX_TSU    14
81511 #define M_XLGMII3_RX_TSU    0x3U
81512 #define V_XLGMII3_RX_TSU(x) ((x) << S_XLGMII3_RX_TSU)
81513 #define G_XLGMII3_RX_TSU(x) (((x) >> S_XLGMII3_RX_TSU) & M_XLGMII3_RX_TSU)
81514 
81515 #define S_XLGMII2_RX_TSU    12
81516 #define M_XLGMII2_RX_TSU    0x3U
81517 #define V_XLGMII2_RX_TSU(x) ((x) << S_XLGMII2_RX_TSU)
81518 #define G_XLGMII2_RX_TSU(x) (((x) >> S_XLGMII2_RX_TSU) & M_XLGMII2_RX_TSU)
81519 
81520 #define S_XLGMII1_RX_TSU    10
81521 #define M_XLGMII1_RX_TSU    0x3U
81522 #define V_XLGMII1_RX_TSU(x) ((x) << S_XLGMII1_RX_TSU)
81523 #define G_XLGMII1_RX_TSU(x) (((x) >> S_XLGMII1_RX_TSU) & M_XLGMII1_RX_TSU)
81524 
81525 #define S_XLGMII0_RX_TSU    8
81526 #define M_XLGMII0_RX_TSU    0x3U
81527 #define V_XLGMII0_RX_TSU(x) ((x) << S_XLGMII0_RX_TSU)
81528 #define G_XLGMII0_RX_TSU(x) (((x) >> S_XLGMII0_RX_TSU) & M_XLGMII0_RX_TSU)
81529 
81530 #define S_CGMII3_RX_TSU    6
81531 #define M_CGMII3_RX_TSU    0x3U
81532 #define V_CGMII3_RX_TSU(x) ((x) << S_CGMII3_RX_TSU)
81533 #define G_CGMII3_RX_TSU(x) (((x) >> S_CGMII3_RX_TSU) & M_CGMII3_RX_TSU)
81534 
81535 #define S_CGMII2_RX_TSU    4
81536 #define M_CGMII2_RX_TSU    0x3U
81537 #define V_CGMII2_RX_TSU(x) ((x) << S_CGMII2_RX_TSU)
81538 #define G_CGMII2_RX_TSU(x) (((x) >> S_CGMII2_RX_TSU) & M_CGMII2_RX_TSU)
81539 
81540 #define S_CGMII1_RX_TSU    2
81541 #define M_CGMII1_RX_TSU    0x3U
81542 #define V_CGMII1_RX_TSU(x) ((x) << S_CGMII1_RX_TSU)
81543 #define G_CGMII1_RX_TSU(x) (((x) >> S_CGMII1_RX_TSU) & M_CGMII1_RX_TSU)
81544 
81545 #define S_CGMII0_RX_TSU    0
81546 #define M_CGMII0_RX_TSU    0x3U
81547 #define V_CGMII0_RX_TSU(x) ((x) << S_CGMII0_RX_TSU)
81548 #define G_CGMII0_RX_TSU(x) (((x) >> S_CGMII0_RX_TSU) & M_CGMII0_RX_TSU)
81549 
81550 #define A_MAC_MTIP_PCS_STATUS_2 0x3f108
81551 
81552 #define S_SD_BIT_SLIP_0    0
81553 #define M_SD_BIT_SLIP_0    0x3fffffffU
81554 #define V_SD_BIT_SLIP_0(x) ((x) << S_SD_BIT_SLIP_0)
81555 #define G_SD_BIT_SLIP_0(x) (((x) >> S_SD_BIT_SLIP_0) & M_SD_BIT_SLIP_0)
81556 
81557 #define A_MAC_MTIP_PCS_STATUS_3 0x3f10c
81558 
81559 #define S_SD_BIT_SLIP_1    0
81560 #define M_SD_BIT_SLIP_1    0x3ffffU
81561 #define V_SD_BIT_SLIP_1(x) ((x) << S_SD_BIT_SLIP_1)
81562 #define G_SD_BIT_SLIP_1(x) (((x) >> S_SD_BIT_SLIP_1) & M_SD_BIT_SLIP_1)
81563 
81564 #define A_MAC_MTIP_PCS_STATUS_4 0x3f110
81565 
81566 #define S_TSU_RX_SD    0
81567 #define M_TSU_RX_SD    0xffffU
81568 #define V_TSU_RX_SD(x) ((x) << S_TSU_RX_SD)
81569 #define G_TSU_RX_SD(x) (((x) >> S_TSU_RX_SD) & M_TSU_RX_SD)
81570 
81571 #define A_MAC_MTIP_PCS_STATUS_5 0x3f114
81572 
81573 #define S_RSFEC_XSTATS_STRB    0
81574 #define M_RSFEC_XSTATS_STRB    0xffffffU
81575 #define V_RSFEC_XSTATS_STRB(x) ((x) << S_RSFEC_XSTATS_STRB)
81576 #define G_RSFEC_XSTATS_STRB(x) (((x) >> S_RSFEC_XSTATS_STRB) & M_RSFEC_XSTATS_STRB)
81577 
81578 #define A_MAC_MTIP_PCS_STATUS_6 0x3f118
81579 #define A_MAC_MTIP_PCS_STATUS_7 0x3f11c
81580 #define A_MAC_MTIP_MAC_10G_100G_STATUS_0 0x3f120
81581 
81582 #define S_TSV_XON_STB_2    24
81583 #define M_TSV_XON_STB_2    0xffU
81584 #define V_TSV_XON_STB_2(x) ((x) << S_TSV_XON_STB_2)
81585 #define G_TSV_XON_STB_2(x) (((x) >> S_TSV_XON_STB_2) & M_TSV_XON_STB_2)
81586 
81587 #define S_TSV_XOFF_STB_2    16
81588 #define M_TSV_XOFF_STB_2    0xffU
81589 #define V_TSV_XOFF_STB_2(x) ((x) << S_TSV_XOFF_STB_2)
81590 #define G_TSV_XOFF_STB_2(x) (((x) >> S_TSV_XOFF_STB_2) & M_TSV_XOFF_STB_2)
81591 
81592 #define S_RSV_XON_STB_2    8
81593 #define M_RSV_XON_STB_2    0xffU
81594 #define V_RSV_XON_STB_2(x) ((x) << S_RSV_XON_STB_2)
81595 #define G_RSV_XON_STB_2(x) (((x) >> S_RSV_XON_STB_2) & M_RSV_XON_STB_2)
81596 
81597 #define S_RSV_XOFF_STB_2    0
81598 #define M_RSV_XOFF_STB_2    0xffU
81599 #define V_RSV_XOFF_STB_2(x) ((x) << S_RSV_XOFF_STB_2)
81600 #define G_RSV_XOFF_STB_2(x) (((x) >> S_RSV_XOFF_STB_2) & M_RSV_XOFF_STB_2)
81601 
81602 #define A_MAC_MTIP_MAC_10G_100G_STATUS_1 0x3f124
81603 
81604 #define S_TSV_XON_STB_3    24
81605 #define M_TSV_XON_STB_3    0xffU
81606 #define V_TSV_XON_STB_3(x) ((x) << S_TSV_XON_STB_3)
81607 #define G_TSV_XON_STB_3(x) (((x) >> S_TSV_XON_STB_3) & M_TSV_XON_STB_3)
81608 
81609 #define S_TSV_XOFF_STB_3    16
81610 #define M_TSV_XOFF_STB_3    0xffU
81611 #define V_TSV_XOFF_STB_3(x) ((x) << S_TSV_XOFF_STB_3)
81612 #define G_TSV_XOFF_STB_3(x) (((x) >> S_TSV_XOFF_STB_3) & M_TSV_XOFF_STB_3)
81613 
81614 #define S_RSV_XON_STB_3    8
81615 #define M_RSV_XON_STB_3    0xffU
81616 #define V_RSV_XON_STB_3(x) ((x) << S_RSV_XON_STB_3)
81617 #define G_RSV_XON_STB_3(x) (((x) >> S_RSV_XON_STB_3) & M_RSV_XON_STB_3)
81618 
81619 #define S_RSV_XOFF_STB_3    0
81620 #define M_RSV_XOFF_STB_3    0xffU
81621 #define V_RSV_XOFF_STB_3(x) ((x) << S_RSV_XOFF_STB_3)
81622 #define G_RSV_XOFF_STB_3(x) (((x) >> S_RSV_XOFF_STB_3) & M_RSV_XOFF_STB_3)
81623 
81624 #define A_MAC_MTIP_MAC_10G_100G_STATUS_2 0x3f128
81625 
81626 #define S_TSV_XON_STB_4    24
81627 #define M_TSV_XON_STB_4    0xffU
81628 #define V_TSV_XON_STB_4(x) ((x) << S_TSV_XON_STB_4)
81629 #define G_TSV_XON_STB_4(x) (((x) >> S_TSV_XON_STB_4) & M_TSV_XON_STB_4)
81630 
81631 #define S_TSV_XOFF_STB_4    16
81632 #define M_TSV_XOFF_STB_4    0xffU
81633 #define V_TSV_XOFF_STB_4(x) ((x) << S_TSV_XOFF_STB_4)
81634 #define G_TSV_XOFF_STB_4(x) (((x) >> S_TSV_XOFF_STB_4) & M_TSV_XOFF_STB_4)
81635 
81636 #define S_RSV_XON_STB_4    8
81637 #define M_RSV_XON_STB_4    0xffU
81638 #define V_RSV_XON_STB_4(x) ((x) << S_RSV_XON_STB_4)
81639 #define G_RSV_XON_STB_4(x) (((x) >> S_RSV_XON_STB_4) & M_RSV_XON_STB_4)
81640 
81641 #define S_RSV_XOFF_STB_4    0
81642 #define M_RSV_XOFF_STB_4    0xffU
81643 #define V_RSV_XOFF_STB_4(x) ((x) << S_RSV_XOFF_STB_4)
81644 #define G_RSV_XOFF_STB_4(x) (((x) >> S_RSV_XOFF_STB_4) & M_RSV_XOFF_STB_4)
81645 
81646 #define A_MAC_MTIP_MAC_10G_100G_STATUS_3 0x3f12c
81647 
81648 #define S_TSV_XON_STB_5    24
81649 #define M_TSV_XON_STB_5    0xffU
81650 #define V_TSV_XON_STB_5(x) ((x) << S_TSV_XON_STB_5)
81651 #define G_TSV_XON_STB_5(x) (((x) >> S_TSV_XON_STB_5) & M_TSV_XON_STB_5)
81652 
81653 #define S_TSV_XOFF_STB_5    16
81654 #define M_TSV_XOFF_STB_5    0xffU
81655 #define V_TSV_XOFF_STB_5(x) ((x) << S_TSV_XOFF_STB_5)
81656 #define G_TSV_XOFF_STB_5(x) (((x) >> S_TSV_XOFF_STB_5) & M_TSV_XOFF_STB_5)
81657 
81658 #define S_RSV_XON_STB_5    8
81659 #define M_RSV_XON_STB_5    0xffU
81660 #define V_RSV_XON_STB_5(x) ((x) << S_RSV_XON_STB_5)
81661 #define G_RSV_XON_STB_5(x) (((x) >> S_RSV_XON_STB_5) & M_RSV_XON_STB_5)
81662 
81663 #define S_RSV_XOFF_STB_5    0
81664 #define M_RSV_XOFF_STB_5    0xffU
81665 #define V_RSV_XOFF_STB_5(x) ((x) << S_RSV_XOFF_STB_5)
81666 #define G_RSV_XOFF_STB_5(x) (((x) >> S_RSV_XOFF_STB_5) & M_RSV_XOFF_STB_5)
81667 
81668 #define A_MAC_MTIP_MAC_10G_100G_STATUS_4 0x3f130
81669 
81670 #define S_TX_SFD_O_5    19
81671 #define V_TX_SFD_O_5(x) ((x) << S_TX_SFD_O_5)
81672 #define F_TX_SFD_O_5    V_TX_SFD_O_5(1U)
81673 
81674 #define S_TX_SFD_O_4    18
81675 #define V_TX_SFD_O_4(x) ((x) << S_TX_SFD_O_4)
81676 #define F_TX_SFD_O_4    V_TX_SFD_O_4(1U)
81677 
81678 #define S_TX_SFD_O_3    17
81679 #define V_TX_SFD_O_3(x) ((x) << S_TX_SFD_O_3)
81680 #define F_TX_SFD_O_3    V_TX_SFD_O_3(1U)
81681 
81682 #define S_TX_SFD_O_2    16
81683 #define V_TX_SFD_O_2(x) ((x) << S_TX_SFD_O_2)
81684 #define F_TX_SFD_O_2    V_TX_SFD_O_2(1U)
81685 
81686 #define S_RX_SFD_O_5    15
81687 #define V_RX_SFD_O_5(x) ((x) << S_RX_SFD_O_5)
81688 #define F_RX_SFD_O_5    V_RX_SFD_O_5(1U)
81689 
81690 #define S_RX_SFD_O_4    14
81691 #define V_RX_SFD_O_4(x) ((x) << S_RX_SFD_O_4)
81692 #define F_RX_SFD_O_4    V_RX_SFD_O_4(1U)
81693 
81694 #define S_RX_SFD_O_3    13
81695 #define V_RX_SFD_O_3(x) ((x) << S_RX_SFD_O_3)
81696 #define F_RX_SFD_O_3    V_RX_SFD_O_3(1U)
81697 
81698 #define S_RX_SFD_O_2    12
81699 #define V_RX_SFD_O_2(x) ((x) << S_RX_SFD_O_2)
81700 #define F_RX_SFD_O_2    V_RX_SFD_O_2(1U)
81701 
81702 #define S_RX_SFD_SHIFT_O_5    11
81703 #define V_RX_SFD_SHIFT_O_5(x) ((x) << S_RX_SFD_SHIFT_O_5)
81704 #define F_RX_SFD_SHIFT_O_5    V_RX_SFD_SHIFT_O_5(1U)
81705 
81706 #define S_RX_SFD_SHIFT_O_4    10
81707 #define V_RX_SFD_SHIFT_O_4(x) ((x) << S_RX_SFD_SHIFT_O_4)
81708 #define F_RX_SFD_SHIFT_O_4    V_RX_SFD_SHIFT_O_4(1U)
81709 
81710 #define S_RX_SFD_SHIFT_O_3    9
81711 #define V_RX_SFD_SHIFT_O_3(x) ((x) << S_RX_SFD_SHIFT_O_3)
81712 #define F_RX_SFD_SHIFT_O_3    V_RX_SFD_SHIFT_O_3(1U)
81713 
81714 #define S_RX_SFD_SHIFT_O_2    8
81715 #define V_RX_SFD_SHIFT_O_2(x) ((x) << S_RX_SFD_SHIFT_O_2)
81716 #define F_RX_SFD_SHIFT_O_2    V_RX_SFD_SHIFT_O_2(1U)
81717 
81718 #define S_TX_SFD_SHIFT_O_5    7
81719 #define V_TX_SFD_SHIFT_O_5(x) ((x) << S_TX_SFD_SHIFT_O_5)
81720 #define F_TX_SFD_SHIFT_O_5    V_TX_SFD_SHIFT_O_5(1U)
81721 
81722 #define S_TX_SFD_SHIFT_O_4    6
81723 #define V_TX_SFD_SHIFT_O_4(x) ((x) << S_TX_SFD_SHIFT_O_4)
81724 #define F_TX_SFD_SHIFT_O_4    V_TX_SFD_SHIFT_O_4(1U)
81725 
81726 #define S_TX_SFD_SHIFT_O_3    5
81727 #define V_TX_SFD_SHIFT_O_3(x) ((x) << S_TX_SFD_SHIFT_O_3)
81728 #define F_TX_SFD_SHIFT_O_3    V_TX_SFD_SHIFT_O_3(1U)
81729 
81730 #define S_TX_SFD_SHIFT_O_2    4
81731 #define V_TX_SFD_SHIFT_O_2(x) ((x) << S_TX_SFD_SHIFT_O_2)
81732 #define F_TX_SFD_SHIFT_O_2    V_TX_SFD_SHIFT_O_2(1U)
81733 
81734 #define S_TS_SFD_ENA_5    3
81735 #define V_TS_SFD_ENA_5(x) ((x) << S_TS_SFD_ENA_5)
81736 #define F_TS_SFD_ENA_5    V_TS_SFD_ENA_5(1U)
81737 
81738 #define S_TS_SFD_ENA_4    2
81739 #define V_TS_SFD_ENA_4(x) ((x) << S_TS_SFD_ENA_4)
81740 #define F_TS_SFD_ENA_4    V_TS_SFD_ENA_4(1U)
81741 
81742 #define S_TS_SFD_ENA_3    1
81743 #define V_TS_SFD_ENA_3(x) ((x) << S_TS_SFD_ENA_3)
81744 #define F_TS_SFD_ENA_3    V_TS_SFD_ENA_3(1U)
81745 
81746 #define S_TS_SFD_ENA_2    0
81747 #define V_TS_SFD_ENA_2(x) ((x) << S_TS_SFD_ENA_2)
81748 #define F_TS_SFD_ENA_2    V_TS_SFD_ENA_2(1U)
81749 
81750 #define A_MAC_STS_CONFIG 0x3f200
81751 
81752 #define S_STS_ENA    30
81753 #define V_STS_ENA(x) ((x) << S_STS_ENA)
81754 #define F_STS_ENA    V_STS_ENA(1U)
81755 
81756 #define S_N_PPS_ENA    29
81757 #define V_N_PPS_ENA(x) ((x) << S_N_PPS_ENA)
81758 #define F_N_PPS_ENA    V_N_PPS_ENA(1U)
81759 
81760 #define S_STS_RESET    28
81761 #define V_STS_RESET(x) ((x) << S_STS_RESET)
81762 #define F_STS_RESET    V_STS_RESET(1U)
81763 
81764 #define S_DEBOUNCE_CNT    0
81765 #define M_DEBOUNCE_CNT    0xfffffffU
81766 #define V_DEBOUNCE_CNT(x) ((x) << S_DEBOUNCE_CNT)
81767 #define G_DEBOUNCE_CNT(x) (((x) >> S_DEBOUNCE_CNT) & M_DEBOUNCE_CNT)
81768 
81769 #define A_MAC_STS_COUNTER 0x3f204
81770 #define A_MAC_STS_COUNT_1 0x3f208
81771 #define A_MAC_STS_COUNT_2 0x3f20c
81772 #define A_MAC_STS_N_PPS_COUNT_HI 0x3f210
81773 #define A_MAC_STS_N_PPS_COUNT_LO 0x3f214
81774 #define A_MAC_STS_N_PPS_COUNTER 0x3f218
81775 #define A_MAC_BGR_PQ0_FIRMWARE_COMMON_0 0x4030
81776 
81777 #define S_MAC_BGR_BGR_REG_APB_SEL    0
81778 #define V_MAC_BGR_BGR_REG_APB_SEL(x) ((x) << S_MAC_BGR_BGR_REG_APB_SEL)
81779 #define F_MAC_BGR_BGR_REG_APB_SEL    V_MAC_BGR_BGR_REG_APB_SEL(1U)
81780 
81781 #define A_MAC_BGR_TOP_DIG_CTRL1_REG_LSB 0x4430
81782 
81783 #define S_MAC_BGR_BGR_REFCLK_CTRL_BYPASS    15
81784 #define V_MAC_BGR_BGR_REFCLK_CTRL_BYPASS(x) ((x) << S_MAC_BGR_BGR_REFCLK_CTRL_BYPASS)
81785 #define F_MAC_BGR_BGR_REFCLK_CTRL_BYPASS    V_MAC_BGR_BGR_REFCLK_CTRL_BYPASS(1U)
81786 
81787 #define S_MAC_BGR_BGR_COREREFCLK_SEL    14
81788 #define V_MAC_BGR_BGR_COREREFCLK_SEL(x) ((x) << S_MAC_BGR_BGR_COREREFCLK_SEL)
81789 #define F_MAC_BGR_BGR_COREREFCLK_SEL    V_MAC_BGR_BGR_COREREFCLK_SEL(1U)
81790 
81791 #define S_MAC_BGR_BGR_TEST_CLK_DIV    8
81792 #define M_MAC_BGR_BGR_TEST_CLK_DIV    0x7U
81793 #define V_MAC_BGR_BGR_TEST_CLK_DIV(x) ((x) << S_MAC_BGR_BGR_TEST_CLK_DIV)
81794 #define G_MAC_BGR_BGR_TEST_CLK_DIV(x) (((x) >> S_MAC_BGR_BGR_TEST_CLK_DIV) & M_MAC_BGR_BGR_TEST_CLK_DIV)
81795 
81796 #define S_MAC_BGR_BGR_TEST_CLK_EN    7
81797 #define V_MAC_BGR_BGR_TEST_CLK_EN(x) ((x) << S_MAC_BGR_BGR_TEST_CLK_EN)
81798 #define F_MAC_BGR_BGR_TEST_CLK_EN    V_MAC_BGR_BGR_TEST_CLK_EN(1U)
81799 
81800 #define S_MAC_BGR_BGR_TEST_CLK_BGRSEL    5
81801 #define M_MAC_BGR_BGR_TEST_CLK_BGRSEL    0x3U
81802 #define V_MAC_BGR_BGR_TEST_CLK_BGRSEL(x) ((x) << S_MAC_BGR_BGR_TEST_CLK_BGRSEL)
81803 #define G_MAC_BGR_BGR_TEST_CLK_BGRSEL(x) (((x) >> S_MAC_BGR_BGR_TEST_CLK_BGRSEL) & M_MAC_BGR_BGR_TEST_CLK_BGRSEL)
81804 
81805 #define S_MAC_BGR_BGR_TEST_CLK_SEL    0
81806 #define M_MAC_BGR_BGR_TEST_CLK_SEL    0x1fU
81807 #define V_MAC_BGR_BGR_TEST_CLK_SEL(x) ((x) << S_MAC_BGR_BGR_TEST_CLK_SEL)
81808 #define G_MAC_BGR_BGR_TEST_CLK_SEL(x) (((x) >> S_MAC_BGR_BGR_TEST_CLK_SEL) & M_MAC_BGR_BGR_TEST_CLK_SEL)
81809 
81810 #define A_MAC_BGR_PQ0_FIRMWARE_SEQ0_0 0x6000
81811 
81812 #define S_MAC_BGR_BGR_REG_PRG_EN    0
81813 #define V_MAC_BGR_BGR_REG_PRG_EN(x) ((x) << S_MAC_BGR_BGR_REG_PRG_EN)
81814 #define F_MAC_BGR_BGR_REG_PRG_EN    V_MAC_BGR_BGR_REG_PRG_EN(1U)
81815 
81816 #define A_MAC_BGR_PQ0_FIRMWARE_SEQ0_1 0x6020
81817 
81818 #define S_MAC_BGR_BGR_REG_GPO    0
81819 #define V_MAC_BGR_BGR_REG_GPO(x) ((x) << S_MAC_BGR_BGR_REG_GPO)
81820 #define F_MAC_BGR_BGR_REG_GPO    V_MAC_BGR_BGR_REG_GPO(1U)
81821 
81822 #define A_MAC_BGR_MGMT_SPINE_MACRO_PMA_0 0x40000
81823 
81824 #define S_MAC_BGR_CUREFCLKSEL1    0
81825 #define M_MAC_BGR_CUREFCLKSEL1    0x3U
81826 #define V_MAC_BGR_CUREFCLKSEL1(x) ((x) << S_MAC_BGR_CUREFCLKSEL1)
81827 #define G_MAC_BGR_CUREFCLKSEL1(x) (((x) >> S_MAC_BGR_CUREFCLKSEL1) & M_MAC_BGR_CUREFCLKSEL1)
81828 
81829 #define A_MAC_BGR_REFCLK_CONTROL_1 0x40004
81830 
81831 #define S_MAC_BGR_IM_CUREFCLKLR_EN    0
81832 #define V_MAC_BGR_IM_CUREFCLKLR_EN(x) ((x) << S_MAC_BGR_IM_CUREFCLKLR_EN)
81833 #define F_MAC_BGR_IM_CUREFCLKLR_EN    V_MAC_BGR_IM_CUREFCLKLR_EN(1U)
81834 
81835 #define A_MAC_BGR_REFCLK_CONTROL_2 0x40080
81836 
81837 #define S_MAC_BGR_IM_REF_EN    0
81838 #define V_MAC_BGR_IM_REF_EN(x) ((x) << S_MAC_BGR_IM_REF_EN)
81839 #define F_MAC_BGR_IM_REF_EN    V_MAC_BGR_IM_REF_EN(1U)
81840 
81841 #define A_MAC_PLL0_PLL_TOP_CUPLL_LOCK 0x4438
81842 
81843 #define S_MAC_PLL0_PLL2_LOCK_STATUS    2
81844 #define V_MAC_PLL0_PLL2_LOCK_STATUS(x) ((x) << S_MAC_PLL0_PLL2_LOCK_STATUS)
81845 #define F_MAC_PLL0_PLL2_LOCK_STATUS    V_MAC_PLL0_PLL2_LOCK_STATUS(1U)
81846 
81847 #define S_MAC_PLL0_PLL1_LOCK_STATUS    1
81848 #define V_MAC_PLL0_PLL1_LOCK_STATUS(x) ((x) << S_MAC_PLL0_PLL1_LOCK_STATUS)
81849 #define F_MAC_PLL0_PLL1_LOCK_STATUS    V_MAC_PLL0_PLL1_LOCK_STATUS(1U)
81850 
81851 #define S_MAC_PLL0_PLL0_LOCK_STATUS    0
81852 #define V_MAC_PLL0_PLL0_LOCK_STATUS(x) ((x) << S_MAC_PLL0_PLL0_LOCK_STATUS)
81853 #define F_MAC_PLL0_PLL0_LOCK_STATUS    V_MAC_PLL0_PLL0_LOCK_STATUS(1U)
81854 
81855 #define A_MAC_PLL0_PLL_PQ0_FIRMWARE_SEQ0_1 0x6020
81856 
81857 #define S_MAC_PLL0_PLL_PRG_EN    0
81858 #define M_MAC_PLL0_PLL_PRG_EN    0xfU
81859 #define V_MAC_PLL0_PLL_PRG_EN(x) ((x) << S_MAC_PLL0_PLL_PRG_EN)
81860 #define G_MAC_PLL0_PLL_PRG_EN(x) (((x) >> S_MAC_PLL0_PLL_PRG_EN) & M_MAC_PLL0_PLL_PRG_EN)
81861 
81862 #define A_MAC_PLL0_PLL_CMUTOP_KV16_MGMT_PLL_MACRO_SELECT_0 0x7fc00
81863 
81864 #define S_MAC_PLL0_PMA_MACRO_SELECT    0
81865 #define M_MAC_PLL0_PMA_MACRO_SELECT    0x3ffU
81866 #define V_MAC_PLL0_PMA_MACRO_SELECT(x) ((x) << S_MAC_PLL0_PMA_MACRO_SELECT)
81867 #define G_MAC_PLL0_PMA_MACRO_SELECT(x) (((x) >> S_MAC_PLL0_PMA_MACRO_SELECT) & M_MAC_PLL0_PMA_MACRO_SELECT)
81868 
81869 #define A_MAC_PLL1_PLL_TOP_CUPLL_LOCK 0x4438
81870 
81871 #define S_MAC_PLL1_PLL2_LOCK_STATUS    2
81872 #define V_MAC_PLL1_PLL2_LOCK_STATUS(x) ((x) << S_MAC_PLL1_PLL2_LOCK_STATUS)
81873 #define F_MAC_PLL1_PLL2_LOCK_STATUS    V_MAC_PLL1_PLL2_LOCK_STATUS(1U)
81874 
81875 #define S_MAC_PLL1_PLL1_LOCK_STATUS    1
81876 #define V_MAC_PLL1_PLL1_LOCK_STATUS(x) ((x) << S_MAC_PLL1_PLL1_LOCK_STATUS)
81877 #define F_MAC_PLL1_PLL1_LOCK_STATUS    V_MAC_PLL1_PLL1_LOCK_STATUS(1U)
81878 
81879 #define S_MAC_PLL1_PLL0_LOCK_STATUS    0
81880 #define V_MAC_PLL1_PLL0_LOCK_STATUS(x) ((x) << S_MAC_PLL1_PLL0_LOCK_STATUS)
81881 #define F_MAC_PLL1_PLL0_LOCK_STATUS    V_MAC_PLL1_PLL0_LOCK_STATUS(1U)
81882 
81883 #define A_MAC_PLL1_PLL_PQ0_FIRMWARE_SEQ0_1 0x6020
81884 
81885 #define S_MAC_PLL1_PLL_PRG_EN    0
81886 #define M_MAC_PLL1_PLL_PRG_EN    0xfU
81887 #define V_MAC_PLL1_PLL_PRG_EN(x) ((x) << S_MAC_PLL1_PLL_PRG_EN)
81888 #define G_MAC_PLL1_PLL_PRG_EN(x) (((x) >> S_MAC_PLL1_PLL_PRG_EN) & M_MAC_PLL1_PLL_PRG_EN)
81889 
81890 #define A_MAC_PLL1_PLL_CMUTOP_KV16_MGMT_PLL_MACRO_SELECT_0 0x7fc00
81891 
81892 #define S_MAC_PLL1_PMA_MACRO_SELECT    0
81893 #define M_MAC_PLL1_PMA_MACRO_SELECT    0x3ffU
81894 #define V_MAC_PLL1_PMA_MACRO_SELECT(x) ((x) << S_MAC_PLL1_PMA_MACRO_SELECT)
81895 #define G_MAC_PLL1_PMA_MACRO_SELECT(x) (((x) >> S_MAC_PLL1_PMA_MACRO_SELECT) & M_MAC_PLL1_PMA_MACRO_SELECT)
81896 
81897 /* registers for module CRYPTO_0 */
81898 #define CRYPTO_0_BASE_ADDR 0x44000
81899 
81900 #define A_TLS_TX_CH_CONFIG 0x44000
81901 
81902 #define S_SMALL_LEN_THRESH    16
81903 #define M_SMALL_LEN_THRESH    0xffffU
81904 #define V_SMALL_LEN_THRESH(x) ((x) << S_SMALL_LEN_THRESH)
81905 #define G_SMALL_LEN_THRESH(x) (((x) >> S_SMALL_LEN_THRESH) & M_SMALL_LEN_THRESH)
81906 
81907 #define S_CIPH0_CTL_SEL    12
81908 #define M_CIPH0_CTL_SEL    0x7U
81909 #define V_CIPH0_CTL_SEL(x) ((x) << S_CIPH0_CTL_SEL)
81910 #define G_CIPH0_CTL_SEL(x) (((x) >> S_CIPH0_CTL_SEL) & M_CIPH0_CTL_SEL)
81911 
81912 #define S_CIPHN_CTL_SEL    9
81913 #define M_CIPHN_CTL_SEL    0x7U
81914 #define V_CIPHN_CTL_SEL(x) ((x) << S_CIPHN_CTL_SEL)
81915 #define G_CIPHN_CTL_SEL(x) (((x) >> S_CIPHN_CTL_SEL) & M_CIPHN_CTL_SEL)
81916 
81917 #define S_MAC_CTL_SEL    6
81918 #define M_MAC_CTL_SEL    0x7U
81919 #define V_MAC_CTL_SEL(x) ((x) << S_MAC_CTL_SEL)
81920 #define G_MAC_CTL_SEL(x) (((x) >> S_MAC_CTL_SEL) & M_MAC_CTL_SEL)
81921 
81922 #define S_CIPH0_XOR_SEL    5
81923 #define V_CIPH0_XOR_SEL(x) ((x) << S_CIPH0_XOR_SEL)
81924 #define F_CIPH0_XOR_SEL    V_CIPH0_XOR_SEL(1U)
81925 
81926 #define S_CIPHN_XOR_SEL    4
81927 #define V_CIPHN_XOR_SEL(x) ((x) << S_CIPHN_XOR_SEL)
81928 #define F_CIPHN_XOR_SEL    V_CIPHN_XOR_SEL(1U)
81929 
81930 #define S_MAC_XOR_SEL    3
81931 #define V_MAC_XOR_SEL(x) ((x) << S_MAC_XOR_SEL)
81932 #define F_MAC_XOR_SEL    V_MAC_XOR_SEL(1U)
81933 
81934 #define S_CIPH0_DP_SEL    2
81935 #define V_CIPH0_DP_SEL(x) ((x) << S_CIPH0_DP_SEL)
81936 #define F_CIPH0_DP_SEL    V_CIPH0_DP_SEL(1U)
81937 
81938 #define S_CIPHN_DP_SEL    1
81939 #define V_CIPHN_DP_SEL(x) ((x) << S_CIPHN_DP_SEL)
81940 #define F_CIPHN_DP_SEL    V_CIPHN_DP_SEL(1U)
81941 
81942 #define S_MAC_DP_SEL    0
81943 #define V_MAC_DP_SEL(x) ((x) << S_MAC_DP_SEL)
81944 #define F_MAC_DP_SEL    V_MAC_DP_SEL(1U)
81945 
81946 #define A_TLS_TX_CH_PERR_INJECT 0x44004
81947 #define A_TLS_TX_CH_INT_ENABLE 0x44008
81948 
81949 #define S_KEYLENERR    3
81950 #define V_KEYLENERR(x) ((x) << S_KEYLENERR)
81951 #define F_KEYLENERR    V_KEYLENERR(1U)
81952 
81953 #define S_INTF1_PERR    2
81954 #define V_INTF1_PERR(x) ((x) << S_INTF1_PERR)
81955 #define F_INTF1_PERR    V_INTF1_PERR(1U)
81956 
81957 #define S_INTF0_PERR    1
81958 #define V_INTF0_PERR(x) ((x) << S_INTF0_PERR)
81959 #define F_INTF0_PERR    V_INTF0_PERR(1U)
81960 
81961 #define A_TLS_TX_CH_INT_CAUSE 0x4400c
81962 
81963 #define S_KEX_CERR    4
81964 #define V_KEX_CERR(x) ((x) << S_KEX_CERR)
81965 #define F_KEX_CERR    V_KEX_CERR(1U)
81966 
81967 #define A_TLS_TX_CH_PERR_ENABLE 0x44010
81968 #define A_TLS_TX_CH_DEBUG_FLAGS 0x44014
81969 #define A_TLS_TX_CH_HMACCTRL_CFG 0x44020
81970 #define A_TLS_TX_CH_ERR_RSP_HDR 0x44024
81971 #define A_TLS_TX_CH_HANG_TIMEOUT 0x44028
81972 
81973 #define S_T7_TIMEOUT    0
81974 #define M_T7_TIMEOUT    0xffU
81975 #define V_T7_TIMEOUT(x) ((x) << S_T7_TIMEOUT)
81976 #define G_T7_TIMEOUT(x) (((x) >> S_T7_TIMEOUT) & M_T7_TIMEOUT)
81977 
81978 #define A_TLS_TX_CH_DBG_STEP_CTRL 0x44030
81979 
81980 #define S_DBG_STEP_CTRL    1
81981 #define V_DBG_STEP_CTRL(x) ((x) << S_DBG_STEP_CTRL)
81982 #define F_DBG_STEP_CTRL    V_DBG_STEP_CTRL(1U)
81983 
81984 #define S_DBG_STEP_EN    0
81985 #define V_DBG_STEP_EN(x) ((x) << S_DBG_STEP_EN)
81986 #define F_DBG_STEP_EN    V_DBG_STEP_EN(1U)
81987 
81988 #define A_TLS_TX_DBG_SELL_DATA 0x44714
81989 #define A_TLS_TX_DBG_SELH_DATA 0x44718
81990 #define A_TLS_TX_DBG_SEL_CTRL 0x44730
81991 #define A_TLS_TX_GLOBAL_CONFIG 0x447c0
81992 
81993 #define S_QUIC_EN    2
81994 #define V_QUIC_EN(x) ((x) << S_QUIC_EN)
81995 #define F_QUIC_EN    V_QUIC_EN(1U)
81996 
81997 #define S_IPSEC_IDX_UPD_EN    1
81998 #define V_IPSEC_IDX_UPD_EN(x) ((x) << S_IPSEC_IDX_UPD_EN)
81999 #define F_IPSEC_IDX_UPD_EN    V_IPSEC_IDX_UPD_EN(1U)
82000 
82001 #define S_IPSEC_IDX_CTL    0
82002 #define V_IPSEC_IDX_CTL(x) ((x) << S_IPSEC_IDX_CTL)
82003 #define F_IPSEC_IDX_CTL    V_IPSEC_IDX_CTL(1U)
82004 
82005 #define A_TLS_TX_CGEN 0x447f0
82006 
82007 #define S_CHCGEN    0
82008 #define M_CHCGEN    0x3fU
82009 #define V_CHCGEN(x) ((x) << S_CHCGEN)
82010 #define G_CHCGEN(x) (((x) >> S_CHCGEN) & M_CHCGEN)
82011 
82012 #define A_TLS_TX_IND_ADDR 0x447f8
82013 
82014 #define S_T7_3_ADDR    0
82015 #define M_T7_3_ADDR    0xfffU
82016 #define V_T7_3_ADDR(x) ((x) << S_T7_3_ADDR)
82017 #define G_T7_3_ADDR(x) (((x) >> S_T7_3_ADDR) & M_T7_3_ADDR)
82018 
82019 #define A_TLS_TX_IND_DATA 0x447fc
82020 #define A_TLS_TX_CH_IND_ING_BYTE_CNT_LO 0x0
82021 #define A_TLS_TX_CH_IND_ING_BYTE_CNT_HI 0x1
82022 #define A_TLS_TX_CH_IND_ING_PKT_CNT 0x2
82023 #define A_TLS_TX_CH_IND_DISPATCH_PKT_CNT 0x4
82024 #define A_TLS_TX_CH_IND_ERROR_CNTS0 0x5
82025 #define A_TLS_TX_CH_IND_DEC_ERROR_CNTS 0x7
82026 #define A_TLS_TX_CH_IND_DBG_SPP_CFG 0x1f
82027 
82028 #define S_DIS_IF_ERR    11
82029 #define V_DIS_IF_ERR(x) ((x) << S_DIS_IF_ERR)
82030 #define F_DIS_IF_ERR    V_DIS_IF_ERR(1U)
82031 
82032 #define S_DIS_ERR_MSG    10
82033 #define V_DIS_ERR_MSG(x) ((x) << S_DIS_ERR_MSG)
82034 #define F_DIS_ERR_MSG    V_DIS_ERR_MSG(1U)
82035 
82036 #define S_DIS_BP_SEQF    9
82037 #define V_DIS_BP_SEQF(x) ((x) << S_DIS_BP_SEQF)
82038 #define F_DIS_BP_SEQF    V_DIS_BP_SEQF(1U)
82039 
82040 #define S_DIS_BP_LENF    8
82041 #define V_DIS_BP_LENF(x) ((x) << S_DIS_BP_LENF)
82042 #define F_DIS_BP_LENF    V_DIS_BP_LENF(1U)
82043 
82044 #define S_DIS_KEX_ERR    6
82045 #define V_DIS_KEX_ERR(x) ((x) << S_DIS_KEX_ERR)
82046 #define F_DIS_KEX_ERR    V_DIS_KEX_ERR(1U)
82047 
82048 #define S_CLR_STS    5
82049 #define V_CLR_STS(x) ((x) << S_CLR_STS)
82050 #define F_CLR_STS    V_CLR_STS(1U)
82051 
82052 #define S_TGL_CNT    4
82053 #define V_TGL_CNT(x) ((x) << S_TGL_CNT)
82054 #define F_TGL_CNT    V_TGL_CNT(1U)
82055 
82056 #define S_ENB_PAZ    3
82057 #define V_ENB_PAZ(x) ((x) << S_ENB_PAZ)
82058 #define F_ENB_PAZ    V_ENB_PAZ(1U)
82059 
82060 #define S_DIS_NOP    2
82061 #define V_DIS_NOP(x) ((x) << S_DIS_NOP)
82062 #define F_DIS_NOP    V_DIS_NOP(1U)
82063 
82064 #define S_DIS_CPL_ERR    1
82065 #define V_DIS_CPL_ERR(x) ((x) << S_DIS_CPL_ERR)
82066 #define F_DIS_CPL_ERR    V_DIS_CPL_ERR(1U)
82067 
82068 #define S_DIS_OFF_ERR    0
82069 #define V_DIS_OFF_ERR(x) ((x) << S_DIS_OFF_ERR)
82070 #define F_DIS_OFF_ERR    V_DIS_OFF_ERR(1U)
82071 
82072 #define A_TLS_TX_CH_IND_DBG_SPP_PKTID0 0x20
82073 #define A_TLS_TX_CH_IND_DBG_SPP_PKTID1 0x21
82074 #define A_TLS_TX_CH_IND_DBG_SPP_PKTID2 0x22
82075 #define A_TLS_TX_CH_IND_DBG_SPP_PKTID3 0x23
82076 #define A_TLS_TX_CH_IND_DBG_SPP_PKTID4 0x24
82077 #define A_TLS_TX_CH_IND_DBG_SPP_PKTID5 0x25
82078 #define A_TLS_TX_CH_IND_DBG_SPP_PKTID6 0x26
82079 #define A_TLS_TX_CH_IND_DBG_SPP_PKTID7 0x27
82080 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_CPL_W0 0x28
82081 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_CPL_W1 0x29
82082 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_CPL_W2 0x2a
82083 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_CPL_W3 0x2b
82084 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_SMD_W0 0x2c
82085 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_SMD_W1 0x2d
82086 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_SMD_W2 0x2e
82087 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_SMD_W3 0x2f
82088 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_ERR 0x30
82089 #define A_TLS_TX_CH_IND_DBG_SPP_SFO_BP 0x31
82090 #define A_TLS_TX_CH_IND_DBG_SPP_SFO_CTL_M 0x32
82091 #define A_TLS_TX_CH_IND_DBG_SPP_SFO_CTL_L 0x33
82092 #define A_TLS_TX_CH_IND_DBG_PKT_STAT 0x3f
82093 
82094 /* registers for module CRYPTO_1 */
82095 #define CRYPTO_1_BASE_ADDR 0x45000
82096 
82097 /* registers for module CRYPTO_KEY */
82098 #define CRYPTO_KEY_BASE_ADDR 0x46000
82099 
82100 #define A_CRYPTO_KEY_CONFIG 0x46000
82101 
82102 #define S_ESNWIN    1
82103 #define M_ESNWIN    0x7U
82104 #define V_ESNWIN(x) ((x) << S_ESNWIN)
82105 #define G_ESNWIN(x) (((x) >> S_ESNWIN) & M_ESNWIN)
82106 
82107 #define S_INGKEY96    0
82108 #define V_INGKEY96(x) ((x) << S_INGKEY96)
82109 #define F_INGKEY96    V_INGKEY96(1U)
82110 
82111 #define A_CRYPTO_KEY_RST 0x46004
82112 
82113 #define S_CORE1RST    1
82114 #define V_CORE1RST(x) ((x) << S_CORE1RST)
82115 #define F_CORE1RST    V_CORE1RST(1U)
82116 
82117 #define S_CORE0RST    0
82118 #define V_CORE0RST(x) ((x) << S_CORE0RST)
82119 #define F_CORE0RST    V_CORE0RST(1U)
82120 
82121 #define A_CRYPTO_KEY_INT_ENABLE 0x46008
82122 
82123 #define S_MA_FIFO_PERR    22
82124 #define V_MA_FIFO_PERR(x) ((x) << S_MA_FIFO_PERR)
82125 #define F_MA_FIFO_PERR    V_MA_FIFO_PERR(1U)
82126 
82127 #define S_MA_RSP_PERR    21
82128 #define V_MA_RSP_PERR(x) ((x) << S_MA_RSP_PERR)
82129 #define F_MA_RSP_PERR    V_MA_RSP_PERR(1U)
82130 
82131 #define S_ING_CACHE_DATA_PERR    19
82132 #define V_ING_CACHE_DATA_PERR(x) ((x) << S_ING_CACHE_DATA_PERR)
82133 #define F_ING_CACHE_DATA_PERR    V_ING_CACHE_DATA_PERR(1U)
82134 
82135 #define S_ING_CACHE_TAG_PERR    18
82136 #define V_ING_CACHE_TAG_PERR(x) ((x) << S_ING_CACHE_TAG_PERR)
82137 #define F_ING_CACHE_TAG_PERR    V_ING_CACHE_TAG_PERR(1U)
82138 
82139 #define S_LKP_KEY_REQ_PERR    17
82140 #define V_LKP_KEY_REQ_PERR(x) ((x) << S_LKP_KEY_REQ_PERR)
82141 #define F_LKP_KEY_REQ_PERR    V_LKP_KEY_REQ_PERR(1U)
82142 
82143 #define S_LKP_CLIP_TCAM_PERR    16
82144 #define V_LKP_CLIP_TCAM_PERR(x) ((x) << S_LKP_CLIP_TCAM_PERR)
82145 #define F_LKP_CLIP_TCAM_PERR    V_LKP_CLIP_TCAM_PERR(1U)
82146 
82147 #define S_LKP_MAIN_TCAM_PERR    15
82148 #define V_LKP_MAIN_TCAM_PERR(x) ((x) << S_LKP_MAIN_TCAM_PERR)
82149 #define F_LKP_MAIN_TCAM_PERR    V_LKP_MAIN_TCAM_PERR(1U)
82150 
82151 #define S_EGR_KEY_REQ_PERR    14
82152 #define V_EGR_KEY_REQ_PERR(x) ((x) << S_EGR_KEY_REQ_PERR)
82153 #define F_EGR_KEY_REQ_PERR    V_EGR_KEY_REQ_PERR(1U)
82154 
82155 #define S_EGR_CACHE_DATA_PERR    13
82156 #define V_EGR_CACHE_DATA_PERR(x) ((x) << S_EGR_CACHE_DATA_PERR)
82157 #define F_EGR_CACHE_DATA_PERR    V_EGR_CACHE_DATA_PERR(1U)
82158 
82159 #define S_EGR_CACHE_TAG_PERR    12
82160 #define V_EGR_CACHE_TAG_PERR(x) ((x) << S_EGR_CACHE_TAG_PERR)
82161 #define F_EGR_CACHE_TAG_PERR    V_EGR_CACHE_TAG_PERR(1U)
82162 
82163 #define S_CIM_PERR    11
82164 #define V_CIM_PERR(x) ((x) << S_CIM_PERR)
82165 #define F_CIM_PERR    V_CIM_PERR(1U)
82166 
82167 #define S_MA_INV_RSP_TAG    10
82168 #define V_MA_INV_RSP_TAG(x) ((x) << S_MA_INV_RSP_TAG)
82169 #define F_MA_INV_RSP_TAG    V_MA_INV_RSP_TAG(1U)
82170 
82171 #define S_ING_KEY_RANGE_ERR    9
82172 #define V_ING_KEY_RANGE_ERR(x) ((x) << S_ING_KEY_RANGE_ERR)
82173 #define F_ING_KEY_RANGE_ERR    V_ING_KEY_RANGE_ERR(1U)
82174 
82175 #define S_ING_MFIFO_OVFL    8
82176 #define V_ING_MFIFO_OVFL(x) ((x) << S_ING_MFIFO_OVFL)
82177 #define F_ING_MFIFO_OVFL    V_ING_MFIFO_OVFL(1U)
82178 
82179 #define S_LKP_REQ_OVFL    7
82180 #define V_LKP_REQ_OVFL(x) ((x) << S_LKP_REQ_OVFL)
82181 #define F_LKP_REQ_OVFL    V_LKP_REQ_OVFL(1U)
82182 
82183 #define S_EOK_WAIT_ERR    6
82184 #define V_EOK_WAIT_ERR(x) ((x) << S_EOK_WAIT_ERR)
82185 #define F_EOK_WAIT_ERR    V_EOK_WAIT_ERR(1U)
82186 
82187 #define S_EGR_KEY_RANGE_ERR    5
82188 #define V_EGR_KEY_RANGE_ERR(x) ((x) << S_EGR_KEY_RANGE_ERR)
82189 #define F_EGR_KEY_RANGE_ERR    V_EGR_KEY_RANGE_ERR(1U)
82190 
82191 #define S_EGR_MFIFO_OVFL    4
82192 #define V_EGR_MFIFO_OVFL(x) ((x) << S_EGR_MFIFO_OVFL)
82193 #define F_EGR_MFIFO_OVFL    V_EGR_MFIFO_OVFL(1U)
82194 
82195 #define S_SEQ_WRAP_HP_OVFL    3
82196 #define V_SEQ_WRAP_HP_OVFL(x) ((x) << S_SEQ_WRAP_HP_OVFL)
82197 #define F_SEQ_WRAP_HP_OVFL    V_SEQ_WRAP_HP_OVFL(1U)
82198 
82199 #define S_SEQ_WRAP_LP_OVFL    2
82200 #define V_SEQ_WRAP_LP_OVFL(x) ((x) << S_SEQ_WRAP_LP_OVFL)
82201 #define F_SEQ_WRAP_LP_OVFL    V_SEQ_WRAP_LP_OVFL(1U)
82202 
82203 #define S_EGR_SEQ_WRAP_HP    1
82204 #define V_EGR_SEQ_WRAP_HP(x) ((x) << S_EGR_SEQ_WRAP_HP)
82205 #define F_EGR_SEQ_WRAP_HP    V_EGR_SEQ_WRAP_HP(1U)
82206 
82207 #define S_EGR_SEQ_WRAP_LP    0
82208 #define V_EGR_SEQ_WRAP_LP(x) ((x) << S_EGR_SEQ_WRAP_LP)
82209 #define F_EGR_SEQ_WRAP_LP    V_EGR_SEQ_WRAP_LP(1U)
82210 
82211 #define A_CRYPTO_KEY_INT_CAUSE 0x4600c
82212 #define A_CRYPTO_KEY_PERR_ENABLE 0x46010
82213 #define A_CRYPTO_KEY_EGR_SEQ_WRAP_LP_KEY_ID 0x46018
82214 
82215 #define S_KEY_VALID    31
82216 #define V_KEY_VALID(x) ((x) << S_KEY_VALID)
82217 #define F_KEY_VALID    V_KEY_VALID(1U)
82218 
82219 #define S_KEY_ID    0
82220 #define M_KEY_ID    0x7fffffffU
82221 #define V_KEY_ID(x) ((x) << S_KEY_ID)
82222 #define G_KEY_ID(x) (((x) >> S_KEY_ID) & M_KEY_ID)
82223 
82224 #define A_CRYPTO_KEY_EGR_SEQ_WRAP_HP_KEY_ID 0x4601c
82225 #define A_CRYPTO_KEY_TCAM_DATA0 0x46020
82226 #define A_CRYPTO_KEY_TCAM_DATA1 0x46024
82227 #define A_CRYPTO_KEY_TCAM_DATA2 0x46028
82228 #define A_CRYPTO_KEY_TCAM_DATA3 0x4602c
82229 #define A_CRYPTO_KEY_TCAM_CTL 0x46030
82230 
82231 #define S_SRCHMHIT    21
82232 #define V_SRCHMHIT(x) ((x) << S_SRCHMHIT)
82233 #define F_SRCHMHIT    V_SRCHMHIT(1U)
82234 
82235 #define S_T7_BUSY    20
82236 #define V_T7_BUSY(x) ((x) << S_T7_BUSY)
82237 #define F_T7_BUSY    V_T7_BUSY(1U)
82238 
82239 #define S_SRCHHIT    19
82240 #define V_SRCHHIT(x) ((x) << S_SRCHHIT)
82241 #define F_SRCHHIT    V_SRCHHIT(1U)
82242 
82243 #define S_IPVERSION    18
82244 #define V_IPVERSION(x) ((x) << S_IPVERSION)
82245 #define F_IPVERSION    V_IPVERSION(1U)
82246 
82247 #define S_BITSEL    17
82248 #define V_BITSEL(x) ((x) << S_BITSEL)
82249 #define F_BITSEL    V_BITSEL(1U)
82250 
82251 #define S_TCAMSEL    16
82252 #define V_TCAMSEL(x) ((x) << S_TCAMSEL)
82253 #define F_TCAMSEL    V_TCAMSEL(1U)
82254 
82255 #define S_CMDTYPE    14
82256 #define M_CMDTYPE    0x3U
82257 #define V_CMDTYPE(x) ((x) << S_CMDTYPE)
82258 #define G_CMDTYPE(x) (((x) >> S_CMDTYPE) & M_CMDTYPE)
82259 
82260 #define S_TCAMINDEX    0
82261 #define M_TCAMINDEX    0x3fffU
82262 #define V_TCAMINDEX(x) ((x) << S_TCAMINDEX)
82263 #define G_TCAMINDEX(x) (((x) >> S_TCAMINDEX) & M_TCAMINDEX)
82264 
82265 #define A_CRYPTO_KEY_TCAM_CONFIG 0x46034
82266 
82267 #define S_T7_CLTCAMDEEPSLEEP_STAT    3
82268 #define V_T7_CLTCAMDEEPSLEEP_STAT(x) ((x) << S_T7_CLTCAMDEEPSLEEP_STAT)
82269 #define F_T7_CLTCAMDEEPSLEEP_STAT    V_T7_CLTCAMDEEPSLEEP_STAT(1U)
82270 
82271 #define S_T7_TCAMDEEPSLEEP_STAT    2
82272 #define V_T7_TCAMDEEPSLEEP_STAT(x) ((x) << S_T7_TCAMDEEPSLEEP_STAT)
82273 #define F_T7_TCAMDEEPSLEEP_STAT    V_T7_TCAMDEEPSLEEP_STAT(1U)
82274 
82275 #define S_T7_CLTCAMDEEPSLEEP    1
82276 #define V_T7_CLTCAMDEEPSLEEP(x) ((x) << S_T7_CLTCAMDEEPSLEEP)
82277 #define F_T7_CLTCAMDEEPSLEEP    V_T7_CLTCAMDEEPSLEEP(1U)
82278 
82279 #define S_T7_TCAMDEEPSLEEP    0
82280 #define V_T7_TCAMDEEPSLEEP(x) ((x) << S_T7_TCAMDEEPSLEEP)
82281 #define F_T7_TCAMDEEPSLEEP    V_T7_TCAMDEEPSLEEP(1U)
82282 
82283 #define A_CRYPTO_KEY_TX_CMM_CONFIG 0x46040
82284 #define A_CRYPTO_KEY_TX_TNL_BASE 0x46044
82285 #define A_CRYPTO_KEY_TX_TRN_BASE 0x46048
82286 #define A_CRYPTO_KEY_TX_MAX_KEYS 0x4604c
82287 
82288 #define S_TNL_MAX    16
82289 #define M_TNL_MAX    0xffffU
82290 #define V_TNL_MAX(x) ((x) << S_TNL_MAX)
82291 #define G_TNL_MAX(x) (((x) >> S_TNL_MAX) & M_TNL_MAX)
82292 
82293 #define S_TRN_MAX    0
82294 #define M_TRN_MAX    0xffffU
82295 #define V_TRN_MAX(x) ((x) << S_TRN_MAX)
82296 #define G_TRN_MAX(x) (((x) >> S_TRN_MAX) & M_TRN_MAX)
82297 
82298 #define A_CRYPTO_KEY_TX_SEQ_STAT 0x46050
82299 
82300 #define S_ESN    24
82301 #define V_ESN(x) ((x) << S_ESN)
82302 #define F_ESN    V_ESN(1U)
82303 
82304 #define S_SEQHI    20
82305 #define M_SEQHI    0xfU
82306 #define V_SEQHI(x) ((x) << S_SEQHI)
82307 #define G_SEQHI(x) (((x) >> S_SEQHI) & M_SEQHI)
82308 
82309 #define S_KEYID    0
82310 #define M_KEYID    0xfffffU
82311 #define V_KEYID(x) ((x) << S_KEYID)
82312 #define G_KEYID(x) (((x) >> S_KEYID) & M_KEYID)
82313 
82314 #define A_CRYPTO_KEY_RX_CMM_CONFIG 0x46060
82315 #define A_CRYPTO_KEY_RX_BASE 0x46064
82316 #define A_CRYPTO_KEY_RX_MAX_KEYS 0x46068
82317 
82318 #define S_MAXKEYS    0
82319 #define M_MAXKEYS    0xffffU
82320 #define V_MAXKEYS(x) ((x) << S_MAXKEYS)
82321 #define G_MAXKEYS(x) (((x) >> S_MAXKEYS) & M_MAXKEYS)
82322 
82323 #define A_CRYPTO_KEY_CRYPTO_REVISION 0x4606c
82324 #define A_CRYPTO_KEY_RX_SEQ_STAT 0x46070
82325 #define A_CRYPTO_KEY_TCAM_BIST_CTRL 0x46074
82326 #define A_CRYPTO_KEY_TCAM_BIST_CB_PASS 0x46078
82327 #define A_CRYPTO_KEY_TCAM_BIST_CB_BUSY 0x4607c
82328 #define A_CRYPTO_KEY_DBG_SEL_CTRL 0x46080
82329 
82330 #define S_SEL_OVR_EN    16
82331 #define V_SEL_OVR_EN(x) ((x) << S_SEL_OVR_EN)
82332 #define F_SEL_OVR_EN    V_SEL_OVR_EN(1U)
82333 
82334 #define S_T7_1_SELH    8
82335 #define M_T7_1_SELH    0xffU
82336 #define V_T7_1_SELH(x) ((x) << S_T7_1_SELH)
82337 #define G_T7_1_SELH(x) (((x) >> S_T7_1_SELH) & M_T7_1_SELH)
82338 
82339 #define S_T7_1_SELL    0
82340 #define M_T7_1_SELL    0xffU
82341 #define V_T7_1_SELL(x) ((x) << S_T7_1_SELL)
82342 #define G_T7_1_SELL(x) (((x) >> S_T7_1_SELL) & M_T7_1_SELL)
82343 
82344 #define A_CRYPTO_KEY_DBG_SELL_DATA 0x46084
82345 #define A_CRYPTO_KEY_DBG_SELH_DATA 0x46088
82346 
82347 /* registers for module ARM */
82348 #define ARM_BASE_ADDR 0x47000
82349 
82350 #define A_ARM_CPU_POR_RST 0x47000
82351 
82352 #define S_CPUPORRSTN3    3
82353 #define V_CPUPORRSTN3(x) ((x) << S_CPUPORRSTN3)
82354 #define F_CPUPORRSTN3    V_CPUPORRSTN3(1U)
82355 
82356 #define S_CPUPORRSTN2    2
82357 #define V_CPUPORRSTN2(x) ((x) << S_CPUPORRSTN2)
82358 #define F_CPUPORRSTN2    V_CPUPORRSTN2(1U)
82359 
82360 #define S_CPUPORRSTN1    1
82361 #define V_CPUPORRSTN1(x) ((x) << S_CPUPORRSTN1)
82362 #define F_CPUPORRSTN1    V_CPUPORRSTN1(1U)
82363 
82364 #define S_CPUPORRSTN0    0
82365 #define V_CPUPORRSTN0(x) ((x) << S_CPUPORRSTN0)
82366 #define F_CPUPORRSTN0    V_CPUPORRSTN0(1U)
82367 
82368 #define A_ARM_CPU_CORE_RST 0x47004
82369 
82370 #define S_CPUCORERSTN3    3
82371 #define V_CPUCORERSTN3(x) ((x) << S_CPUCORERSTN3)
82372 #define F_CPUCORERSTN3    V_CPUCORERSTN3(1U)
82373 
82374 #define S_CPUCORERSTN2    2
82375 #define V_CPUCORERSTN2(x) ((x) << S_CPUCORERSTN2)
82376 #define F_CPUCORERSTN2    V_CPUCORERSTN2(1U)
82377 
82378 #define S_CPUCORERSTN1    1
82379 #define V_CPUCORERSTN1(x) ((x) << S_CPUCORERSTN1)
82380 #define F_CPUCORERSTN1    V_CPUCORERSTN1(1U)
82381 
82382 #define S_CPUCORERSTN0    0
82383 #define V_CPUCORERSTN0(x) ((x) << S_CPUCORERSTN0)
82384 #define F_CPUCORERSTN0    V_CPUCORERSTN0(1U)
82385 
82386 #define A_ARM_CPU_WARM_RST_REQ 0x47008
82387 
82388 #define S_CPUWARMRSTREQ3    3
82389 #define V_CPUWARMRSTREQ3(x) ((x) << S_CPUWARMRSTREQ3)
82390 #define F_CPUWARMRSTREQ3    V_CPUWARMRSTREQ3(1U)
82391 
82392 #define S_CPUWARMRSTREQ2    2
82393 #define V_CPUWARMRSTREQ2(x) ((x) << S_CPUWARMRSTREQ2)
82394 #define F_CPUWARMRSTREQ2    V_CPUWARMRSTREQ2(1U)
82395 
82396 #define S_CPUWARMRSTREQ1    1
82397 #define V_CPUWARMRSTREQ1(x) ((x) << S_CPUWARMRSTREQ1)
82398 #define F_CPUWARMRSTREQ1    V_CPUWARMRSTREQ1(1U)
82399 
82400 #define S_CPUWARMRSTREQ0    0
82401 #define V_CPUWARMRSTREQ0(x) ((x) << S_CPUWARMRSTREQ0)
82402 #define F_CPUWARMRSTREQ0    V_CPUWARMRSTREQ0(1U)
82403 
82404 #define A_ARM_CPU_L2_RST 0x4700c
82405 
82406 #define S_CPUL2RSTN    0
82407 #define V_CPUL2RSTN(x) ((x) << S_CPUL2RSTN)
82408 #define F_CPUL2RSTN    V_CPUL2RSTN(1U)
82409 
82410 #define A_ARM_CPU_L2_RST_DIS 0x47010
82411 
82412 #define S_CPUL2RSTDISABLE    0
82413 #define V_CPUL2RSTDISABLE(x) ((x) << S_CPUL2RSTDISABLE)
82414 #define F_CPUL2RSTDISABLE    V_CPUL2RSTDISABLE(1U)
82415 
82416 #define A_ARM_CPU_PRESET_DBG 0x47014
82417 
82418 #define S_CPUPRESETDBGN    0
82419 #define V_CPUPRESETDBGN(x) ((x) << S_CPUPRESETDBGN)
82420 #define F_CPUPRESETDBGN    V_CPUPRESETDBGN(1U)
82421 
82422 #define A_ARM_PL_DMA_AW_OFFSET 0x47018
82423 
82424 #define S_PL_DMA_AW_OFFSET    0
82425 #define M_PL_DMA_AW_OFFSET    0x3fffffffU
82426 #define V_PL_DMA_AW_OFFSET(x) ((x) << S_PL_DMA_AW_OFFSET)
82427 #define G_PL_DMA_AW_OFFSET(x) (((x) >> S_PL_DMA_AW_OFFSET) & M_PL_DMA_AW_OFFSET)
82428 
82429 #define A_ARM_PL_DMA_AR_OFFSET 0x4701c
82430 
82431 #define S_PL_DMA_AR_OFFSET    0
82432 #define M_PL_DMA_AR_OFFSET    0x3fffffffU
82433 #define V_PL_DMA_AR_OFFSET(x) ((x) << S_PL_DMA_AR_OFFSET)
82434 #define G_PL_DMA_AR_OFFSET(x) (((x) >> S_PL_DMA_AR_OFFSET) & M_PL_DMA_AR_OFFSET)
82435 
82436 #define A_ARM_CPU_RESET_VECTOR_BASE_ADDR0 0x47020
82437 #define A_ARM_CPU_RESET_VECTOR_BASE_ADDR1 0x47024
82438 
82439 #define S_CPURESETVECBA1    0
82440 #define M_CPURESETVECBA1    0x3ffU
82441 #define V_CPURESETVECBA1(x) ((x) << S_CPURESETVECBA1)
82442 #define G_CPURESETVECBA1(x) (((x) >> S_CPURESETVECBA1) & M_CPURESETVECBA1)
82443 
82444 #define A_ARM_CPU_PMU_EVENT 0x47028
82445 
82446 #define S_CPUPMUEVENT    0
82447 #define M_CPUPMUEVENT    0x1ffffffU
82448 #define V_CPUPMUEVENT(x) ((x) << S_CPUPMUEVENT)
82449 #define G_CPUPMUEVENT(x) (((x) >> S_CPUPMUEVENT) & M_CPUPMUEVENT)
82450 
82451 #define A_ARM_DMA_RST 0x4702c
82452 
82453 #define S_DMA_PL_RST_N    0
82454 #define V_DMA_PL_RST_N(x) ((x) << S_DMA_PL_RST_N)
82455 #define F_DMA_PL_RST_N    V_DMA_PL_RST_N(1U)
82456 
82457 #define A_ARM_PLM_RID_CFG 0x4703c
82458 #define A_ARM_PLM_EROM_CFG 0x47040
82459 #define A_ARM_PL_ARM_HDR_CFG 0x4704c
82460 #define A_ARM_RC_INT_STATUS 0x4705c
82461 
82462 #define S_RC_INT_STATUS_REG    0
82463 #define M_RC_INT_STATUS_REG    0x3fU
82464 #define V_RC_INT_STATUS_REG(x) ((x) << S_RC_INT_STATUS_REG)
82465 #define G_RC_INT_STATUS_REG(x) (((x) >> S_RC_INT_STATUS_REG) & M_RC_INT_STATUS_REG)
82466 
82467 #define A_ARM_CPU_DBG_PWR_UP_REQ 0x47060
82468 
82469 #define S_CPUDBGPWRUPREQ3    3
82470 #define V_CPUDBGPWRUPREQ3(x) ((x) << S_CPUDBGPWRUPREQ3)
82471 #define F_CPUDBGPWRUPREQ3    V_CPUDBGPWRUPREQ3(1U)
82472 
82473 #define S_CPUDBGPWRUPREQ2    2
82474 #define V_CPUDBGPWRUPREQ2(x) ((x) << S_CPUDBGPWRUPREQ2)
82475 #define F_CPUDBGPWRUPREQ2    V_CPUDBGPWRUPREQ2(1U)
82476 
82477 #define S_CPUDBGPWRUPREQ1    1
82478 #define V_CPUDBGPWRUPREQ1(x) ((x) << S_CPUDBGPWRUPREQ1)
82479 #define F_CPUDBGPWRUPREQ1    V_CPUDBGPWRUPREQ1(1U)
82480 
82481 #define S_CPUDBGPWRUPREQ0    0
82482 #define V_CPUDBGPWRUPREQ0(x) ((x) << S_CPUDBGPWRUPREQ0)
82483 #define F_CPUDBGPWRUPREQ0    V_CPUDBGPWRUPREQ0(1U)
82484 
82485 #define A_ARM_CPU_STANDBY_WFE_WFI 0x47064
82486 
82487 #define S_CPUSTANDBYWFIL2    8
82488 #define V_CPUSTANDBYWFIL2(x) ((x) << S_CPUSTANDBYWFIL2)
82489 #define F_CPUSTANDBYWFIL2    V_CPUSTANDBYWFIL2(1U)
82490 
82491 #define S_CPUSTANDBYWFI3    7
82492 #define V_CPUSTANDBYWFI3(x) ((x) << S_CPUSTANDBYWFI3)
82493 #define F_CPUSTANDBYWFI3    V_CPUSTANDBYWFI3(1U)
82494 
82495 #define S_CPUSTANDBYWFI2    6
82496 #define V_CPUSTANDBYWFI2(x) ((x) << S_CPUSTANDBYWFI2)
82497 #define F_CPUSTANDBYWFI2    V_CPUSTANDBYWFI2(1U)
82498 
82499 #define S_CPUSTANDBYWFI1    5
82500 #define V_CPUSTANDBYWFI1(x) ((x) << S_CPUSTANDBYWFI1)
82501 #define F_CPUSTANDBYWFI1    V_CPUSTANDBYWFI1(1U)
82502 
82503 #define S_CPUSTANDBYWFI0    4
82504 #define V_CPUSTANDBYWFI0(x) ((x) << S_CPUSTANDBYWFI0)
82505 #define F_CPUSTANDBYWFI0    V_CPUSTANDBYWFI0(1U)
82506 
82507 #define S_CPUSTANDBYWFE3    3
82508 #define V_CPUSTANDBYWFE3(x) ((x) << S_CPUSTANDBYWFE3)
82509 #define F_CPUSTANDBYWFE3    V_CPUSTANDBYWFE3(1U)
82510 
82511 #define S_CPUSTANDBYWFE2    2
82512 #define V_CPUSTANDBYWFE2(x) ((x) << S_CPUSTANDBYWFE2)
82513 #define F_CPUSTANDBYWFE2    V_CPUSTANDBYWFE2(1U)
82514 
82515 #define S_CPUSTANDBYWFE1    1
82516 #define V_CPUSTANDBYWFE1(x) ((x) << S_CPUSTANDBYWFE1)
82517 #define F_CPUSTANDBYWFE1    V_CPUSTANDBYWFE1(1U)
82518 
82519 #define S_CPUSTANDBYWFE0    0
82520 #define V_CPUSTANDBYWFE0(x) ((x) << S_CPUSTANDBYWFE0)
82521 #define F_CPUSTANDBYWFE0    V_CPUSTANDBYWFE0(1U)
82522 
82523 #define A_ARM_CPU_SMPEN 0x47068
82524 
82525 #define S_CPUSMPEN3    3
82526 #define V_CPUSMPEN3(x) ((x) << S_CPUSMPEN3)
82527 #define F_CPUSMPEN3    V_CPUSMPEN3(1U)
82528 
82529 #define S_CPUSMPEN2    2
82530 #define V_CPUSMPEN2(x) ((x) << S_CPUSMPEN2)
82531 #define F_CPUSMPEN2    V_CPUSMPEN2(1U)
82532 
82533 #define S_CPUSMPEN1    1
82534 #define V_CPUSMPEN1(x) ((x) << S_CPUSMPEN1)
82535 #define F_CPUSMPEN1    V_CPUSMPEN1(1U)
82536 
82537 #define S_CPUSMPEN0    0
82538 #define V_CPUSMPEN0(x) ((x) << S_CPUSMPEN0)
82539 #define F_CPUSMPEN0    V_CPUSMPEN0(1U)
82540 
82541 #define A_ARM_CPU_QACTIVE 0x4706c
82542 
82543 #define S_CPUQACTIVE3    3
82544 #define V_CPUQACTIVE3(x) ((x) << S_CPUQACTIVE3)
82545 #define F_CPUQACTIVE3    V_CPUQACTIVE3(1U)
82546 
82547 #define S_CPUQACTIVE2    2
82548 #define V_CPUQACTIVE2(x) ((x) << S_CPUQACTIVE2)
82549 #define F_CPUQACTIVE2    V_CPUQACTIVE2(1U)
82550 
82551 #define S_CPUQACTIVE1    1
82552 #define V_CPUQACTIVE1(x) ((x) << S_CPUQACTIVE1)
82553 #define F_CPUQACTIVE1    V_CPUQACTIVE1(1U)
82554 
82555 #define S_CPUQACTIVE0    0
82556 #define V_CPUQACTIVE0(x) ((x) << S_CPUQACTIVE0)
82557 #define F_CPUQACTIVE0    V_CPUQACTIVE0(1U)
82558 
82559 #define A_ARM_CPU_QREQ 0x47070
82560 
82561 #define S_CPUL2FLUSHREQ    5
82562 #define V_CPUL2FLUSHREQ(x) ((x) << S_CPUL2FLUSHREQ)
82563 #define F_CPUL2FLUSHREQ    V_CPUL2FLUSHREQ(1U)
82564 
82565 #define S_CPUL2QREQN    4
82566 #define V_CPUL2QREQN(x) ((x) << S_CPUL2QREQN)
82567 #define F_CPUL2QREQN    V_CPUL2QREQN(1U)
82568 
82569 #define S_CPUQREQ3N    3
82570 #define V_CPUQREQ3N(x) ((x) << S_CPUQREQ3N)
82571 #define F_CPUQREQ3N    V_CPUQREQ3N(1U)
82572 
82573 #define S_CPUQREQ2N    2
82574 #define V_CPUQREQ2N(x) ((x) << S_CPUQREQ2N)
82575 #define F_CPUQREQ2N    V_CPUQREQ2N(1U)
82576 
82577 #define S_CPUQREQ1N    1
82578 #define V_CPUQREQ1N(x) ((x) << S_CPUQREQ1N)
82579 #define F_CPUQREQ1N    V_CPUQREQ1N(1U)
82580 
82581 #define S_CPUQREQ0N    0
82582 #define V_CPUQREQ0N(x) ((x) << S_CPUQREQ0N)
82583 #define F_CPUQREQ0N    V_CPUQREQ0N(1U)
82584 
82585 #define A_ARM_CPU_QREQ_STATUS 0x47074
82586 
82587 #define S_CPUL2FLUSHDONE    10
82588 #define V_CPUL2FLUSHDONE(x) ((x) << S_CPUL2FLUSHDONE)
82589 #define F_CPUL2FLUSHDONE    V_CPUL2FLUSHDONE(1U)
82590 
82591 #define S_CPUL2QDENY    9
82592 #define V_CPUL2QDENY(x) ((x) << S_CPUL2QDENY)
82593 #define F_CPUL2QDENY    V_CPUL2QDENY(1U)
82594 
82595 #define S_CPUL2QACCEPTN    8
82596 #define V_CPUL2QACCEPTN(x) ((x) << S_CPUL2QACCEPTN)
82597 #define F_CPUL2QACCEPTN    V_CPUL2QACCEPTN(1U)
82598 
82599 #define S_CPUQDENY3    7
82600 #define V_CPUQDENY3(x) ((x) << S_CPUQDENY3)
82601 #define F_CPUQDENY3    V_CPUQDENY3(1U)
82602 
82603 #define S_CPUQDENY2    6
82604 #define V_CPUQDENY2(x) ((x) << S_CPUQDENY2)
82605 #define F_CPUQDENY2    V_CPUQDENY2(1U)
82606 
82607 #define S_CPUQDENY1    5
82608 #define V_CPUQDENY1(x) ((x) << S_CPUQDENY1)
82609 #define F_CPUQDENY1    V_CPUQDENY1(1U)
82610 
82611 #define S_CPUQDENY0    4
82612 #define V_CPUQDENY0(x) ((x) << S_CPUQDENY0)
82613 #define F_CPUQDENY0    V_CPUQDENY0(1U)
82614 
82615 #define S_CPUQACCEPT3N    3
82616 #define V_CPUQACCEPT3N(x) ((x) << S_CPUQACCEPT3N)
82617 #define F_CPUQACCEPT3N    V_CPUQACCEPT3N(1U)
82618 
82619 #define S_CPUQACCEPT2N    2
82620 #define V_CPUQACCEPT2N(x) ((x) << S_CPUQACCEPT2N)
82621 #define F_CPUQACCEPT2N    V_CPUQACCEPT2N(1U)
82622 
82623 #define S_CPUQACCEPT1N    1
82624 #define V_CPUQACCEPT1N(x) ((x) << S_CPUQACCEPT1N)
82625 #define F_CPUQACCEPT1N    V_CPUQACCEPT1N(1U)
82626 
82627 #define S_CPUQACCEPT0N    0
82628 #define V_CPUQACCEPT0N(x) ((x) << S_CPUQACCEPT0N)
82629 #define F_CPUQACCEPT0N    V_CPUQACCEPT0N(1U)
82630 
82631 #define A_ARM_CPU_DBG_EN 0x47078
82632 
82633 #define S_CPUDBGL1RSTDISABLE    28
82634 #define V_CPUDBGL1RSTDISABLE(x) ((x) << S_CPUDBGL1RSTDISABLE)
82635 #define F_CPUDBGL1RSTDISABLE    V_CPUDBGL1RSTDISABLE(1U)
82636 
82637 #define S_CPUDBGRSTREQ3    27
82638 #define V_CPUDBGRSTREQ3(x) ((x) << S_CPUDBGRSTREQ3)
82639 #define F_CPUDBGRSTREQ3    V_CPUDBGRSTREQ3(1U)
82640 
82641 #define S_CPUDBGRSTREQ2    26
82642 #define V_CPUDBGRSTREQ2(x) ((x) << S_CPUDBGRSTREQ2)
82643 #define F_CPUDBGRSTREQ2    V_CPUDBGRSTREQ2(1U)
82644 
82645 #define S_CPUDBGRSTREQ1    25
82646 #define V_CPUDBGRSTREQ1(x) ((x) << S_CPUDBGRSTREQ1)
82647 #define F_CPUDBGRSTREQ1    V_CPUDBGRSTREQ1(1U)
82648 
82649 #define S_CPUDBGRSTREQ0    24
82650 #define V_CPUDBGRSTREQ0(x) ((x) << S_CPUDBGRSTREQ0)
82651 #define F_CPUDBGRSTREQ0    V_CPUDBGRSTREQ0(1U)
82652 
82653 #define S_CPUDBGPWRDUP3    23
82654 #define V_CPUDBGPWRDUP3(x) ((x) << S_CPUDBGPWRDUP3)
82655 #define F_CPUDBGPWRDUP3    V_CPUDBGPWRDUP3(1U)
82656 
82657 #define S_CPUDBGPWRDUP2    22
82658 #define V_CPUDBGPWRDUP2(x) ((x) << S_CPUDBGPWRDUP2)
82659 #define F_CPUDBGPWRDUP2    V_CPUDBGPWRDUP2(1U)
82660 
82661 #define S_CPUDBGPWRDUP1    21
82662 #define V_CPUDBGPWRDUP1(x) ((x) << S_CPUDBGPWRDUP1)
82663 #define F_CPUDBGPWRDUP1    V_CPUDBGPWRDUP1(1U)
82664 
82665 #define S_CPUDBGPWRDUP0    20
82666 #define V_CPUDBGPWRDUP0(x) ((x) << S_CPUDBGPWRDUP0)
82667 #define F_CPUDBGPWRDUP0    V_CPUDBGPWRDUP0(1U)
82668 
82669 #define S_CPUEXTDBGREQ3    19
82670 #define V_CPUEXTDBGREQ3(x) ((x) << S_CPUEXTDBGREQ3)
82671 #define F_CPUEXTDBGREQ3    V_CPUEXTDBGREQ3(1U)
82672 
82673 #define S_CPUEXTDBGREQ2    18
82674 #define V_CPUEXTDBGREQ2(x) ((x) << S_CPUEXTDBGREQ2)
82675 #define F_CPUEXTDBGREQ2    V_CPUEXTDBGREQ2(1U)
82676 
82677 #define S_CPUEXTDBGREQ1    17
82678 #define V_CPUEXTDBGREQ1(x) ((x) << S_CPUEXTDBGREQ1)
82679 #define F_CPUEXTDBGREQ1    V_CPUEXTDBGREQ1(1U)
82680 
82681 #define S_CPUEXTDBGREQ0    16
82682 #define V_CPUEXTDBGREQ0(x) ((x) << S_CPUEXTDBGREQ0)
82683 #define F_CPUEXTDBGREQ0    V_CPUEXTDBGREQ0(1U)
82684 
82685 #define S_CPUSPNIDEN3    15
82686 #define V_CPUSPNIDEN3(x) ((x) << S_CPUSPNIDEN3)
82687 #define F_CPUSPNIDEN3    V_CPUSPNIDEN3(1U)
82688 
82689 #define S_CPUSPNIDEN2    14
82690 #define V_CPUSPNIDEN2(x) ((x) << S_CPUSPNIDEN2)
82691 #define F_CPUSPNIDEN2    V_CPUSPNIDEN2(1U)
82692 
82693 #define S_CPUSPNIDEN1    13
82694 #define V_CPUSPNIDEN1(x) ((x) << S_CPUSPNIDEN1)
82695 #define F_CPUSPNIDEN1    V_CPUSPNIDEN1(1U)
82696 
82697 #define S_CPUSPNIDEN0    12
82698 #define V_CPUSPNIDEN0(x) ((x) << S_CPUSPNIDEN0)
82699 #define F_CPUSPNIDEN0    V_CPUSPNIDEN0(1U)
82700 
82701 #define S_CPUSPDBGEN3    11
82702 #define V_CPUSPDBGEN3(x) ((x) << S_CPUSPDBGEN3)
82703 #define F_CPUSPDBGEN3    V_CPUSPDBGEN3(1U)
82704 
82705 #define S_CPUSPDBGEN2    10
82706 #define V_CPUSPDBGEN2(x) ((x) << S_CPUSPDBGEN2)
82707 #define F_CPUSPDBGEN2    V_CPUSPDBGEN2(1U)
82708 
82709 #define S_CPUSPDBGEN1    9
82710 #define V_CPUSPDBGEN1(x) ((x) << S_CPUSPDBGEN1)
82711 #define F_CPUSPDBGEN1    V_CPUSPDBGEN1(1U)
82712 
82713 #define S_CPUSPDBGEN0    8
82714 #define V_CPUSPDBGEN0(x) ((x) << S_CPUSPDBGEN0)
82715 #define F_CPUSPDBGEN0    V_CPUSPDBGEN0(1U)
82716 
82717 #define S_CPUNIDEN3    7
82718 #define V_CPUNIDEN3(x) ((x) << S_CPUNIDEN3)
82719 #define F_CPUNIDEN3    V_CPUNIDEN3(1U)
82720 
82721 #define S_CPUNIDEN2    6
82722 #define V_CPUNIDEN2(x) ((x) << S_CPUNIDEN2)
82723 #define F_CPUNIDEN2    V_CPUNIDEN2(1U)
82724 
82725 #define S_CPUNIDEN1    5
82726 #define V_CPUNIDEN1(x) ((x) << S_CPUNIDEN1)
82727 #define F_CPUNIDEN1    V_CPUNIDEN1(1U)
82728 
82729 #define S_CPUNIDEN0    4
82730 #define V_CPUNIDEN0(x) ((x) << S_CPUNIDEN0)
82731 #define F_CPUNIDEN0    V_CPUNIDEN0(1U)
82732 
82733 #define S_CPUDBGEN3    3
82734 #define V_CPUDBGEN3(x) ((x) << S_CPUDBGEN3)
82735 #define F_CPUDBGEN3    V_CPUDBGEN3(1U)
82736 
82737 #define S_CPUDBGEN2    2
82738 #define V_CPUDBGEN2(x) ((x) << S_CPUDBGEN2)
82739 #define F_CPUDBGEN2    V_CPUDBGEN2(1U)
82740 
82741 #define S_CPUDBGEN1    1
82742 #define V_CPUDBGEN1(x) ((x) << S_CPUDBGEN1)
82743 #define F_CPUDBGEN1    V_CPUDBGEN1(1U)
82744 
82745 #define S_CPUDBGEN0    0
82746 #define V_CPUDBGEN0(x) ((x) << S_CPUDBGEN0)
82747 #define F_CPUDBGEN0    V_CPUDBGEN0(1U)
82748 
82749 #define A_ARM_CPU_DBG_ACK 0x4707c
82750 
82751 #define S_CPUDBGNOPWRDWN3    11
82752 #define V_CPUDBGNOPWRDWN3(x) ((x) << S_CPUDBGNOPWRDWN3)
82753 #define F_CPUDBGNOPWRDWN3    V_CPUDBGNOPWRDWN3(1U)
82754 
82755 #define S_CPUDBGNOPWRDWN2    10
82756 #define V_CPUDBGNOPWRDWN2(x) ((x) << S_CPUDBGNOPWRDWN2)
82757 #define F_CPUDBGNOPWRDWN2    V_CPUDBGNOPWRDWN2(1U)
82758 
82759 #define S_CPUDBGNOPWRDWN1    9
82760 #define V_CPUDBGNOPWRDWN1(x) ((x) << S_CPUDBGNOPWRDWN1)
82761 #define F_CPUDBGNOPWRDWN1    V_CPUDBGNOPWRDWN1(1U)
82762 
82763 #define S_CPUDBGNOPWRDWN0    8
82764 #define V_CPUDBGNOPWRDWN0(x) ((x) << S_CPUDBGNOPWRDWN0)
82765 #define F_CPUDBGNOPWRDWN0    V_CPUDBGNOPWRDWN0(1U)
82766 
82767 #define S_CPUDGNRSTREQ3    7
82768 #define V_CPUDGNRSTREQ3(x) ((x) << S_CPUDGNRSTREQ3)
82769 #define F_CPUDGNRSTREQ3    V_CPUDGNRSTREQ3(1U)
82770 
82771 #define S_CPUDGNRSTREQ2    6
82772 #define V_CPUDGNRSTREQ2(x) ((x) << S_CPUDGNRSTREQ2)
82773 #define F_CPUDGNRSTREQ2    V_CPUDGNRSTREQ2(1U)
82774 
82775 #define S_CPUDGNRSTREQ1    5
82776 #define V_CPUDGNRSTREQ1(x) ((x) << S_CPUDGNRSTREQ1)
82777 #define F_CPUDGNRSTREQ1    V_CPUDGNRSTREQ1(1U)
82778 
82779 #define S_CPUDGNRSTREQ0    4
82780 #define V_CPUDGNRSTREQ0(x) ((x) << S_CPUDGNRSTREQ0)
82781 #define F_CPUDGNRSTREQ0    V_CPUDGNRSTREQ0(1U)
82782 
82783 #define S_CPUDBGACK3    3
82784 #define V_CPUDBGACK3(x) ((x) << S_CPUDBGACK3)
82785 #define F_CPUDBGACK3    V_CPUDBGACK3(1U)
82786 
82787 #define S_CPUDBGACK2    2
82788 #define V_CPUDBGACK2(x) ((x) << S_CPUDBGACK2)
82789 #define F_CPUDBGACK2    V_CPUDBGACK2(1U)
82790 
82791 #define S_CPUDBGACK1    1
82792 #define V_CPUDBGACK1(x) ((x) << S_CPUDBGACK1)
82793 #define F_CPUDBGACK1    V_CPUDBGACK1(1U)
82794 
82795 #define S_CPUDBGACK0    0
82796 #define V_CPUDBGACK0(x) ((x) << S_CPUDBGACK0)
82797 #define F_CPUDBGACK0    V_CPUDBGACK0(1U)
82798 
82799 #define A_ARM_CPU_PMU_SNAPSHOT_REQ 0x47080
82800 
82801 #define S_CPUPMUSNAPSHOTREQ3    3
82802 #define V_CPUPMUSNAPSHOTREQ3(x) ((x) << S_CPUPMUSNAPSHOTREQ3)
82803 #define F_CPUPMUSNAPSHOTREQ3    V_CPUPMUSNAPSHOTREQ3(1U)
82804 
82805 #define S_CPUPMUSNAPSHOTREQ2    2
82806 #define V_CPUPMUSNAPSHOTREQ2(x) ((x) << S_CPUPMUSNAPSHOTREQ2)
82807 #define F_CPUPMUSNAPSHOTREQ2    V_CPUPMUSNAPSHOTREQ2(1U)
82808 
82809 #define S_CPUPMUSNAPSHOTREQ1    1
82810 #define V_CPUPMUSNAPSHOTREQ1(x) ((x) << S_CPUPMUSNAPSHOTREQ1)
82811 #define F_CPUPMUSNAPSHOTREQ1    V_CPUPMUSNAPSHOTREQ1(1U)
82812 
82813 #define S_CPUPMUSNAPSHOTREQ0    0
82814 #define V_CPUPMUSNAPSHOTREQ0(x) ((x) << S_CPUPMUSNAPSHOTREQ0)
82815 #define F_CPUPMUSNAPSHOTREQ0    V_CPUPMUSNAPSHOTREQ0(1U)
82816 
82817 #define A_ARM_CPU_PMU_SNAPSHOT_ACK 0x47084
82818 
82819 #define S_CPUPMUSNAPSHOTACK3    3
82820 #define V_CPUPMUSNAPSHOTACK3(x) ((x) << S_CPUPMUSNAPSHOTACK3)
82821 #define F_CPUPMUSNAPSHOTACK3    V_CPUPMUSNAPSHOTACK3(1U)
82822 
82823 #define S_CPUPMUSNAPSHOTACK2    2
82824 #define V_CPUPMUSNAPSHOTACK2(x) ((x) << S_CPUPMUSNAPSHOTACK2)
82825 #define F_CPUPMUSNAPSHOTACK2    V_CPUPMUSNAPSHOTACK2(1U)
82826 
82827 #define S_CPUPMUSNAPSHOTACK1    1
82828 #define V_CPUPMUSNAPSHOTACK1(x) ((x) << S_CPUPMUSNAPSHOTACK1)
82829 #define F_CPUPMUSNAPSHOTACK1    V_CPUPMUSNAPSHOTACK1(1U)
82830 
82831 #define S_CPUPMUSNAPSHOTACK0    0
82832 #define V_CPUPMUSNAPSHOTACK0(x) ((x) << S_CPUPMUSNAPSHOTACK0)
82833 #define F_CPUPMUSNAPSHOTACK0    V_CPUPMUSNAPSHOTACK0(1U)
82834 
82835 #define A_ARM_EMMC_CTRL 0x47088
82836 
82837 #define S_EMMC_DATA_P2    24
82838 #define M_EMMC_DATA_P2    0xffU
82839 #define V_EMMC_DATA_P2(x) ((x) << S_EMMC_DATA_P2)
82840 #define G_EMMC_DATA_P2(x) (((x) >> S_EMMC_DATA_P2) & M_EMMC_DATA_P2)
82841 
82842 #define S_EMMC_DATA_P1    16
82843 #define M_EMMC_DATA_P1    0xffU
82844 #define V_EMMC_DATA_P1(x) ((x) << S_EMMC_DATA_P1)
82845 #define G_EMMC_DATA_P1(x) (((x) >> S_EMMC_DATA_P1) & M_EMMC_DATA_P1)
82846 
82847 #define S_EMMC_CMD_P2    15
82848 #define V_EMMC_CMD_P2(x) ((x) << S_EMMC_CMD_P2)
82849 #define F_EMMC_CMD_P2    V_EMMC_CMD_P2(1U)
82850 
82851 #define S_EMMC_CMD_P1    14
82852 #define V_EMMC_CMD_P1(x) ((x) << S_EMMC_CMD_P1)
82853 #define F_EMMC_CMD_P1    V_EMMC_CMD_P1(1U)
82854 
82855 #define S_EMMC_RST_P2    13
82856 #define V_EMMC_RST_P2(x) ((x) << S_EMMC_RST_P2)
82857 #define F_EMMC_RST_P2    V_EMMC_RST_P2(1U)
82858 
82859 #define S_EMMC_RST_P1    12
82860 #define V_EMMC_RST_P1(x) ((x) << S_EMMC_RST_P1)
82861 #define F_EMMC_RST_P1    V_EMMC_RST_P1(1U)
82862 
82863 #define S_EMMC_GP_IN_P2    10
82864 #define M_EMMC_GP_IN_P2    0x3U
82865 #define V_EMMC_GP_IN_P2(x) ((x) << S_EMMC_GP_IN_P2)
82866 #define G_EMMC_GP_IN_P2(x) (((x) >> S_EMMC_GP_IN_P2) & M_EMMC_GP_IN_P2)
82867 
82868 #define S_EMMC_GP_IN_P1    8
82869 #define M_EMMC_GP_IN_P1    0x3U
82870 #define V_EMMC_GP_IN_P1(x) ((x) << S_EMMC_GP_IN_P1)
82871 #define G_EMMC_GP_IN_P1(x) (((x) >> S_EMMC_GP_IN_P1) & M_EMMC_GP_IN_P1)
82872 
82873 #define S_EMMC_CLK_SEL    0
82874 #define M_EMMC_CLK_SEL    0xffU
82875 #define V_EMMC_CLK_SEL(x) ((x) << S_EMMC_CLK_SEL)
82876 #define G_EMMC_CLK_SEL(x) (((x) >> S_EMMC_CLK_SEL) & M_EMMC_CLK_SEL)
82877 
82878 #define A_ARM_CPU_CFG_END_VINI_TE 0x4708c
82879 
82880 #define S_CPUSYSBARDISABLE    23
82881 #define V_CPUSYSBARDISABLE(x) ((x) << S_CPUSYSBARDISABLE)
82882 #define F_CPUSYSBARDISABLE    V_CPUSYSBARDISABLE(1U)
82883 
82884 #define S_CPUBROADCACHEMAIN    22
82885 #define V_CPUBROADCACHEMAIN(x) ((x) << S_CPUBROADCACHEMAIN)
82886 #define F_CPUBROADCACHEMAIN    V_CPUBROADCACHEMAIN(1U)
82887 
82888 #define S_CPUBROADOUTER    21
82889 #define V_CPUBROADOUTER(x) ((x) << S_CPUBROADOUTER)
82890 #define F_CPUBROADOUTER    V_CPUBROADOUTER(1U)
82891 
82892 #define S_CPUBROADINNER    20
82893 #define V_CPUBROADINNER(x) ((x) << S_CPUBROADINNER)
82894 #define F_CPUBROADINNER    V_CPUBROADINNER(1U)
82895 
82896 #define S_CPUCRYPTODISABLE3    19
82897 #define V_CPUCRYPTODISABLE3(x) ((x) << S_CPUCRYPTODISABLE3)
82898 #define F_CPUCRYPTODISABLE3    V_CPUCRYPTODISABLE3(1U)
82899 
82900 #define S_CPUCRYPTODISABLE2    18
82901 #define V_CPUCRYPTODISABLE2(x) ((x) << S_CPUCRYPTODISABLE2)
82902 #define F_CPUCRYPTODISABLE2    V_CPUCRYPTODISABLE2(1U)
82903 
82904 #define S_CPUCRYPTODISABLE1    17
82905 #define V_CPUCRYPTODISABLE1(x) ((x) << S_CPUCRYPTODISABLE1)
82906 #define F_CPUCRYPTODISABLE1    V_CPUCRYPTODISABLE1(1U)
82907 
82908 #define S_CPUCRYPTODISABLE0    16
82909 #define V_CPUCRYPTODISABLE0(x) ((x) << S_CPUCRYPTODISABLE0)
82910 #define F_CPUCRYPTODISABLE0    V_CPUCRYPTODISABLE0(1U)
82911 
82912 #define S_CPUAA64NAA323    15
82913 #define V_CPUAA64NAA323(x) ((x) << S_CPUAA64NAA323)
82914 #define F_CPUAA64NAA323    V_CPUAA64NAA323(1U)
82915 
82916 #define S_CPUAA64NAA322    14
82917 #define V_CPUAA64NAA322(x) ((x) << S_CPUAA64NAA322)
82918 #define F_CPUAA64NAA322    V_CPUAA64NAA322(1U)
82919 
82920 #define S_CPUAA64NAA321    13
82921 #define V_CPUAA64NAA321(x) ((x) << S_CPUAA64NAA321)
82922 #define F_CPUAA64NAA321    V_CPUAA64NAA321(1U)
82923 
82924 #define S_CPUAA64NAA320    12
82925 #define V_CPUAA64NAA320(x) ((x) << S_CPUAA64NAA320)
82926 #define F_CPUAA64NAA320    V_CPUAA64NAA320(1U)
82927 
82928 #define S_CPUCFGTE3    11
82929 #define V_CPUCFGTE3(x) ((x) << S_CPUCFGTE3)
82930 #define F_CPUCFGTE3    V_CPUCFGTE3(1U)
82931 
82932 #define S_CPUCFGTE2    10
82933 #define V_CPUCFGTE2(x) ((x) << S_CPUCFGTE2)
82934 #define F_CPUCFGTE2    V_CPUCFGTE2(1U)
82935 
82936 #define S_CPUCFGTE1    9
82937 #define V_CPUCFGTE1(x) ((x) << S_CPUCFGTE1)
82938 #define F_CPUCFGTE1    V_CPUCFGTE1(1U)
82939 
82940 #define S_CPUCFGTE0    8
82941 #define V_CPUCFGTE0(x) ((x) << S_CPUCFGTE0)
82942 #define F_CPUCFGTE0    V_CPUCFGTE0(1U)
82943 
82944 #define S_CPUVINIHI3    7
82945 #define V_CPUVINIHI3(x) ((x) << S_CPUVINIHI3)
82946 #define F_CPUVINIHI3    V_CPUVINIHI3(1U)
82947 
82948 #define S_CPUVINIHI2    6
82949 #define V_CPUVINIHI2(x) ((x) << S_CPUVINIHI2)
82950 #define F_CPUVINIHI2    V_CPUVINIHI2(1U)
82951 
82952 #define S_CPUVINIHI1    5
82953 #define V_CPUVINIHI1(x) ((x) << S_CPUVINIHI1)
82954 #define F_CPUVINIHI1    V_CPUVINIHI1(1U)
82955 
82956 #define S_CPUVINIHI0    4
82957 #define V_CPUVINIHI0(x) ((x) << S_CPUVINIHI0)
82958 #define F_CPUVINIHI0    V_CPUVINIHI0(1U)
82959 
82960 #define S_CPUCFGEND3    3
82961 #define V_CPUCFGEND3(x) ((x) << S_CPUCFGEND3)
82962 #define F_CPUCFGEND3    V_CPUCFGEND3(1U)
82963 
82964 #define S_CPUCFGEND2    2
82965 #define V_CPUCFGEND2(x) ((x) << S_CPUCFGEND2)
82966 #define F_CPUCFGEND2    V_CPUCFGEND2(1U)
82967 
82968 #define S_CPUCFGEND1    1
82969 #define V_CPUCFGEND1(x) ((x) << S_CPUCFGEND1)
82970 #define F_CPUCFGEND1    V_CPUCFGEND1(1U)
82971 
82972 #define S_CPUCFGEND0    0
82973 #define V_CPUCFGEND0(x) ((x) << S_CPUCFGEND0)
82974 #define F_CPUCFGEND0    V_CPUCFGEND0(1U)
82975 
82976 #define A_ARM_CPU_CP15_SDISABLE 0x47090
82977 
82978 #define S_CPUCP15SDISABLE3    3
82979 #define V_CPUCP15SDISABLE3(x) ((x) << S_CPUCP15SDISABLE3)
82980 #define F_CPUCP15SDISABLE3    V_CPUCP15SDISABLE3(1U)
82981 
82982 #define S_CPUCP15SDISABLE2    2
82983 #define V_CPUCP15SDISABLE2(x) ((x) << S_CPUCP15SDISABLE2)
82984 #define F_CPUCP15SDISABLE2    V_CPUCP15SDISABLE2(1U)
82985 
82986 #define S_CPUCP15SDISABLE1    1
82987 #define V_CPUCP15SDISABLE1(x) ((x) << S_CPUCP15SDISABLE1)
82988 #define F_CPUCP15SDISABLE1    V_CPUCP15SDISABLE1(1U)
82989 
82990 #define S_CPUCP15SDISABLE0    0
82991 #define V_CPUCP15SDISABLE0(x) ((x) << S_CPUCP15SDISABLE0)
82992 #define F_CPUCP15SDISABLE0    V_CPUCP15SDISABLE0(1U)
82993 
82994 #define A_ARM_CPU_CLUSTER_ID_AFF 0x47094
82995 
82996 #define S_CPUCLUSTERIDAFF2    8
82997 #define M_CPUCLUSTERIDAFF2    0xffU
82998 #define V_CPUCLUSTERIDAFF2(x) ((x) << S_CPUCLUSTERIDAFF2)
82999 #define G_CPUCLUSTERIDAFF2(x) (((x) >> S_CPUCLUSTERIDAFF2) & M_CPUCLUSTERIDAFF2)
83000 
83001 #define S_CPUCLUSTERIDAFF1    0
83002 #define M_CPUCLUSTERIDAFF1    0xffU
83003 #define V_CPUCLUSTERIDAFF1(x) ((x) << S_CPUCLUSTERIDAFF1)
83004 #define G_CPUCLUSTERIDAFF1(x) (((x) >> S_CPUCLUSTERIDAFF1) & M_CPUCLUSTERIDAFF1)
83005 
83006 #define A_ARM_CPU_CLK_CFG 0x47098
83007 
83008 #define S_CPUACINACTIVEM    1
83009 #define V_CPUACINACTIVEM(x) ((x) << S_CPUACINACTIVEM)
83010 #define F_CPUACINACTIVEM    V_CPUACINACTIVEM(1U)
83011 
83012 #define S_CPUACLKENM    0
83013 #define V_CPUACLKENM(x) ((x) << S_CPUACLKENM)
83014 #define F_CPUACLKENM    V_CPUACLKENM(1U)
83015 
83016 #define A_ARM_NVME_DB_EMU_INT_CAUSE 0x4709c
83017 
83018 #define S_INVALID_BRESP    3
83019 #define V_INVALID_BRESP(x) ((x) << S_INVALID_BRESP)
83020 #define F_INVALID_BRESP    V_INVALID_BRESP(1U)
83021 
83022 #define S_DATA_LEN_OF    2
83023 #define V_DATA_LEN_OF(x) ((x) << S_DATA_LEN_OF)
83024 #define F_DATA_LEN_OF    V_DATA_LEN_OF(1U)
83025 
83026 #define S_INVALID_EMU_ADDR    1
83027 #define V_INVALID_EMU_ADDR(x) ((x) << S_INVALID_EMU_ADDR)
83028 #define F_INVALID_EMU_ADDR    V_INVALID_EMU_ADDR(1U)
83029 
83030 #define S_INVALID_AXI_ADDR_CFG    0
83031 #define V_INVALID_AXI_ADDR_CFG(x) ((x) << S_INVALID_AXI_ADDR_CFG)
83032 #define F_INVALID_AXI_ADDR_CFG    V_INVALID_AXI_ADDR_CFG(1U)
83033 
83034 #define A_ARM_CS_RST 0x470c0
83035 
83036 #define S_ATCLKEN    9
83037 #define V_ATCLKEN(x) ((x) << S_ATCLKEN)
83038 #define F_ATCLKEN    V_ATCLKEN(1U)
83039 
83040 #define S_CXAPBICRSTN    8
83041 #define V_CXAPBICRSTN(x) ((x) << S_CXAPBICRSTN)
83042 #define F_CXAPBICRSTN    V_CXAPBICRSTN(1U)
83043 
83044 #define S_CSDBGEN    7
83045 #define V_CSDBGEN(x) ((x) << S_CSDBGEN)
83046 #define F_CSDBGEN    V_CSDBGEN(1U)
83047 
83048 #define S_JTAGNPOTRST    6
83049 #define V_JTAGNPOTRST(x) ((x) << S_JTAGNPOTRST)
83050 #define F_JTAGNPOTRST    V_JTAGNPOTRST(1U)
83051 
83052 #define S_JTAGNTRST    5
83053 #define V_JTAGNTRST(x) ((x) << S_JTAGNTRST)
83054 #define F_JTAGNTRST    V_JTAGNTRST(1U)
83055 
83056 #define S_PADDR31S0    4
83057 #define V_PADDR31S0(x) ((x) << S_PADDR31S0)
83058 #define F_PADDR31S0    V_PADDR31S0(1U)
83059 
83060 #define S_CTICLKEN    3
83061 #define V_CTICLKEN(x) ((x) << S_CTICLKEN)
83062 #define F_CTICLKEN    V_CTICLKEN(1U)
83063 
83064 #define S_PCLKENDBG    2
83065 #define V_PCLKENDBG(x) ((x) << S_PCLKENDBG)
83066 #define F_PCLKENDBG    V_PCLKENDBG(1U)
83067 
83068 #define S_CPU_NIDEN    1
83069 #define V_CPU_NIDEN(x) ((x) << S_CPU_NIDEN)
83070 #define F_CPU_NIDEN    V_CPU_NIDEN(1U)
83071 
83072 #define S_CPU_DBGEN    0
83073 #define V_CPU_DBGEN(x) ((x) << S_CPU_DBGEN)
83074 #define F_CPU_DBGEN    V_CPU_DBGEN(1U)
83075 
83076 #define A_ARM_CS_ADDRL 0x470c4
83077 #define A_ARM_CS_ADDRH 0x470c8
83078 #define A_ARM_CS_DFT_CONTROL 0x470cc
83079 
83080 #define S_DFTMBISTADDR    5
83081 #define M_DFTMBISTADDR    0x7ffU
83082 #define V_DFTMBISTADDR(x) ((x) << S_DFTMBISTADDR)
83083 #define G_DFTMBISTADDR(x) (((x) >> S_DFTMBISTADDR) & M_DFTMBISTADDR)
83084 
83085 #define S_DFTMTESTON    3
83086 #define V_DFTMTESTON(x) ((x) << S_DFTMTESTON)
83087 #define F_DFTMTESTON    V_DFTMTESTON(1U)
83088 
83089 #define S_DFTMBISTCE    2
83090 #define V_DFTMBISTCE(x) ((x) << S_DFTMBISTCE)
83091 #define F_DFTMBISTCE    V_DFTMBISTCE(1U)
83092 
83093 #define S_DFTMBITWR    1
83094 #define V_DFTMBITWR(x) ((x) << S_DFTMBITWR)
83095 #define F_DFTMBITWR    V_DFTMBITWR(1U)
83096 
83097 #define S_DFTSE    0
83098 #define V_DFTSE(x) ((x) << S_DFTSE)
83099 #define F_DFTSE    V_DFTSE(1U)
83100 
83101 #define A_ARM_CS_DFT_IN 0x470d0
83102 #define A_ARM_CS_DFT_OUT 0x470d4
83103 #define A_ARM_CPU_EVENT_I 0x47100
83104 
83105 #define S_CPUEVENTI    0
83106 #define V_CPUEVENTI(x) ((x) << S_CPUEVENTI)
83107 #define F_CPUEVENTI    V_CPUEVENTI(1U)
83108 
83109 #define A_ARM_CPU_EVENT_O 0x47104
83110 
83111 #define S_CPUEVENTO    0
83112 #define V_CPUEVENTO(x) ((x) << S_CPUEVENTO)
83113 #define F_CPUEVENTO    V_CPUEVENTO(1U)
83114 
83115 #define A_ARM_CPU_CLR_EXMON_REQ 0x47108
83116 
83117 #define S_CPUCLREXMONREQ    0
83118 #define V_CPUCLREXMONREQ(x) ((x) << S_CPUCLREXMONREQ)
83119 #define F_CPUCLREXMONREQ    V_CPUCLREXMONREQ(1U)
83120 
83121 #define A_ARM_CPU_CLR_EXMON_ACK 0x4710c
83122 
83123 #define S_CPUCLREXMONACK    0
83124 #define V_CPUCLREXMONACK(x) ((x) << S_CPUCLREXMONACK)
83125 #define F_CPUCLREXMONACK    V_CPUCLREXMONACK(1U)
83126 
83127 #define A_ARM_UART_MSTR_RXD 0x47110
83128 #define A_ARM_UART_MSTR_RXC 0x47114
83129 
83130 #define S_UART_MSTR_RXC    0
83131 #define V_UART_MSTR_RXC(x) ((x) << S_UART_MSTR_RXC)
83132 #define F_UART_MSTR_RXC    V_UART_MSTR_RXC(1U)
83133 
83134 #define A_ARM_UART_MSTR_TXD 0x47118
83135 #define A_ARM_UART_MSTR_TXC 0x4711c
83136 
83137 #define S_T7_INT    1
83138 #define V_T7_INT(x) ((x) << S_T7_INT)
83139 #define F_T7_INT    V_T7_INT(1U)
83140 
83141 #define S_UART_MSTC_TXC    0
83142 #define V_UART_MSTC_TXC(x) ((x) << S_UART_MSTC_TXC)
83143 #define F_UART_MSTC_TXC    V_UART_MSTC_TXC(1U)
83144 
83145 #define A_ARM_UART_SLV_SEL 0x47120
83146 
83147 #define S_UART_SLV_SEL    0
83148 #define V_UART_SLV_SEL(x) ((x) << S_UART_SLV_SEL)
83149 #define F_UART_SLV_SEL    V_UART_SLV_SEL(1U)
83150 
83151 #define A_ARM_CPU_PERIPH_BASE 0x47124
83152 #define A_ARM_PERR_INT_ENB2 0x47128
83153 #define A_ARM_PERR_ENABLE2 0x4712c
83154 #define A_ARM_UART_CONFIG 0x47130
83155 #define A_ARM_UART_STAT 0x47134
83156 
83157 #define S_RSV1    6
83158 #define M_RSV1    0x3ffffffU
83159 #define V_RSV1(x) ((x) << S_RSV1)
83160 #define G_RSV1(x) (((x) >> S_RSV1) & M_RSV1)
83161 
83162 #define S_RXFRMERR    5
83163 #define V_RXFRMERR(x) ((x) << S_RXFRMERR)
83164 #define F_RXFRMERR    V_RXFRMERR(1U)
83165 
83166 #define S_RXPARERR    4
83167 #define V_RXPARERR(x) ((x) << S_RXPARERR)
83168 #define F_RXPARERR    V_RXPARERR(1U)
83169 
83170 #define S_RXOVRN    3
83171 #define V_RXOVRN(x) ((x) << S_RXOVRN)
83172 #define F_RXOVRN    V_RXOVRN(1U)
83173 
83174 #define S_CTL_RXRDY    2
83175 #define V_CTL_RXRDY(x) ((x) << S_CTL_RXRDY)
83176 #define F_CTL_RXRDY    V_CTL_RXRDY(1U)
83177 
83178 #define S_TXOVRN    1
83179 #define V_TXOVRN(x) ((x) << S_TXOVRN)
83180 #define F_TXOVRN    V_TXOVRN(1U)
83181 
83182 #define S_CTL_TXRDY    0
83183 #define V_CTL_TXRDY(x) ((x) << S_CTL_TXRDY)
83184 #define F_CTL_TXRDY    V_CTL_TXRDY(1U)
83185 
83186 #define A_ARM_UART_TX_DATA 0x47138
83187 
83188 #define S_TX_DATA    0
83189 #define M_TX_DATA    0xffU
83190 #define V_TX_DATA(x) ((x) << S_TX_DATA)
83191 #define G_TX_DATA(x) (((x) >> S_TX_DATA) & M_TX_DATA)
83192 
83193 #define A_ARM_UART_RX_DATA 0x4713c
83194 
83195 #define S_RX_DATA    0
83196 #define M_RX_DATA    0xffU
83197 #define V_RX_DATA(x) ((x) << S_RX_DATA)
83198 #define G_RX_DATA(x) (((x) >> S_RX_DATA) & M_RX_DATA)
83199 
83200 #define A_ARM_UART_DBG0 0x47140
83201 #define A_ARM_UART_DBG1 0x47144
83202 #define A_ARM_UART_DBG2 0x47148
83203 #define A_ARM_UART_DBG3 0x4714c
83204 #define A_ARM_ARM_CPU_PC0 0x47150
83205 #define A_ARM_ARM_CPU_PC1 0x47154
83206 #define A_ARM_ARM_UART_INT_CAUSE 0x47158
83207 
83208 #define S_RX_FIFO_NOT_EMPTY    1
83209 #define V_RX_FIFO_NOT_EMPTY(x) ((x) << S_RX_FIFO_NOT_EMPTY)
83210 #define F_RX_FIFO_NOT_EMPTY    V_RX_FIFO_NOT_EMPTY(1U)
83211 
83212 #define S_TX_FIFO_EMPTY    0
83213 #define V_TX_FIFO_EMPTY(x) ((x) << S_TX_FIFO_EMPTY)
83214 #define F_TX_FIFO_EMPTY    V_TX_FIFO_EMPTY(1U)
83215 
83216 #define A_ARM_ARM_UART_INT_EN 0x4715c
83217 
83218 #define S_RX_FIFO_INT_NOT_EMPTY    1
83219 #define V_RX_FIFO_INT_NOT_EMPTY(x) ((x) << S_RX_FIFO_INT_NOT_EMPTY)
83220 #define F_RX_FIFO_INT_NOT_EMPTY    V_RX_FIFO_INT_NOT_EMPTY(1U)
83221 
83222 #define S_TX_FIFO_INT_EMPTY    0
83223 #define V_TX_FIFO_INT_EMPTY(x) ((x) << S_TX_FIFO_INT_EMPTY)
83224 #define F_TX_FIFO_INT_EMPTY    V_TX_FIFO_INT_EMPTY(1U)
83225 
83226 #define A_ARM_ARM_UART_GPIO_SEL 0x47160
83227 
83228 #define S_PC_SEL    1
83229 #define M_PC_SEL    0x7U
83230 #define V_PC_SEL(x) ((x) << S_PC_SEL)
83231 #define G_PC_SEL(x) (((x) >> S_PC_SEL) & M_PC_SEL)
83232 
83233 #define S_UART_GPIO_SEL    0
83234 #define V_UART_GPIO_SEL(x) ((x) << S_UART_GPIO_SEL)
83235 #define F_UART_GPIO_SEL    V_UART_GPIO_SEL(1U)
83236 
83237 #define A_ARM_ARM_SCRATCH_PAD0 0x47164
83238 #define A_ARM_ARM_SCRATCH_PAD1 0x47168
83239 #define A_ARM_ARM_SCRATCH_PAD2 0x4716c
83240 #define A_ARM_PERR_INT_CAUSE0 0x47170
83241 
83242 #define S_INIC_WRDATA_FIFO_PERR    31
83243 #define V_INIC_WRDATA_FIFO_PERR(x) ((x) << S_INIC_WRDATA_FIFO_PERR)
83244 #define F_INIC_WRDATA_FIFO_PERR    V_INIC_WRDATA_FIFO_PERR(1U)
83245 
83246 #define S_INIC_RDATA_FIFO_PERR    30
83247 #define V_INIC_RDATA_FIFO_PERR(x) ((x) << S_INIC_RDATA_FIFO_PERR)
83248 #define F_INIC_RDATA_FIFO_PERR    V_INIC_RDATA_FIFO_PERR(1U)
83249 
83250 #define S_MSI_MEM_PERR    29
83251 #define V_MSI_MEM_PERR(x) ((x) << S_MSI_MEM_PERR)
83252 #define F_MSI_MEM_PERR    V_MSI_MEM_PERR(1U)
83253 
83254 #define S_ARM_DB_SRAM_PERR    27
83255 #define M_ARM_DB_SRAM_PERR    0x3U
83256 #define V_ARM_DB_SRAM_PERR(x) ((x) << S_ARM_DB_SRAM_PERR)
83257 #define G_ARM_DB_SRAM_PERR(x) (((x) >> S_ARM_DB_SRAM_PERR) & M_ARM_DB_SRAM_PERR)
83258 
83259 #define S_EMMC_FIFOPARINT    26
83260 #define V_EMMC_FIFOPARINT(x) ((x) << S_EMMC_FIFOPARINT)
83261 #define F_EMMC_FIFOPARINT    V_EMMC_FIFOPARINT(1U)
83262 
83263 #define S_ICB_RAM_PERR    25
83264 #define V_ICB_RAM_PERR(x) ((x) << S_ICB_RAM_PERR)
83265 #define F_ICB_RAM_PERR    V_ICB_RAM_PERR(1U)
83266 
83267 #define S_MESS2AXI4_WRFIFO_PERR    24
83268 #define V_MESS2AXI4_WRFIFO_PERR(x) ((x) << S_MESS2AXI4_WRFIFO_PERR)
83269 #define F_MESS2AXI4_WRFIFO_PERR    V_MESS2AXI4_WRFIFO_PERR(1U)
83270 
83271 #define S_RC_WFIFO_OUTPERR    23
83272 #define V_RC_WFIFO_OUTPERR(x) ((x) << S_RC_WFIFO_OUTPERR)
83273 #define F_RC_WFIFO_OUTPERR    V_RC_WFIFO_OUTPERR(1U)
83274 
83275 #define S_RC_SRAM_PERR    21
83276 #define M_RC_SRAM_PERR    0x3U
83277 #define V_RC_SRAM_PERR(x) ((x) << S_RC_SRAM_PERR)
83278 #define G_RC_SRAM_PERR(x) (((x) >> S_RC_SRAM_PERR) & M_RC_SRAM_PERR)
83279 
83280 #define S_MSI_FIFO_PAR_ERR    20
83281 #define V_MSI_FIFO_PAR_ERR(x) ((x) << S_MSI_FIFO_PAR_ERR)
83282 #define F_MSI_FIFO_PAR_ERR    V_MSI_FIFO_PAR_ERR(1U)
83283 
83284 #define S_INIC2MA_INTFPERR    19
83285 #define V_INIC2MA_INTFPERR(x) ((x) << S_INIC2MA_INTFPERR)
83286 #define F_INIC2MA_INTFPERR    V_INIC2MA_INTFPERR(1U)
83287 
83288 #define S_RDATAFIFO0_PERR    18
83289 #define V_RDATAFIFO0_PERR(x) ((x) << S_RDATAFIFO0_PERR)
83290 #define F_RDATAFIFO0_PERR    V_RDATAFIFO0_PERR(1U)
83291 
83292 #define S_RDATAFIFO1_PERR    17
83293 #define V_RDATAFIFO1_PERR(x) ((x) << S_RDATAFIFO1_PERR)
83294 #define F_RDATAFIFO1_PERR    V_RDATAFIFO1_PERR(1U)
83295 
83296 #define S_WRDATAFIFO0_PERR    16
83297 #define V_WRDATAFIFO0_PERR(x) ((x) << S_WRDATAFIFO0_PERR)
83298 #define F_WRDATAFIFO0_PERR    V_WRDATAFIFO0_PERR(1U)
83299 
83300 #define S_WRDATAFIFO1_PERR    15
83301 #define V_WRDATAFIFO1_PERR(x) ((x) << S_WRDATAFIFO1_PERR)
83302 #define F_WRDATAFIFO1_PERR    V_WRDATAFIFO1_PERR(1U)
83303 
83304 #define S_WR512DATAFIFO0_PERR    14
83305 #define V_WR512DATAFIFO0_PERR(x) ((x) << S_WR512DATAFIFO0_PERR)
83306 #define F_WR512DATAFIFO0_PERR    V_WR512DATAFIFO0_PERR(1U)
83307 
83308 #define S_WR512DATAFIFO1_PERR    13
83309 #define V_WR512DATAFIFO1_PERR(x) ((x) << S_WR512DATAFIFO1_PERR)
83310 #define F_WR512DATAFIFO1_PERR    V_WR512DATAFIFO1_PERR(1U)
83311 
83312 #define S_ROBUFF_PARERR3    12
83313 #define V_ROBUFF_PARERR3(x) ((x) << S_ROBUFF_PARERR3)
83314 #define F_ROBUFF_PARERR3    V_ROBUFF_PARERR3(1U)
83315 
83316 #define S_ROBUFF_PARERR2    11
83317 #define V_ROBUFF_PARERR2(x) ((x) << S_ROBUFF_PARERR2)
83318 #define F_ROBUFF_PARERR2    V_ROBUFF_PARERR2(1U)
83319 
83320 #define S_ROBUFF_PARERR1    10
83321 #define V_ROBUFF_PARERR1(x) ((x) << S_ROBUFF_PARERR1)
83322 #define F_ROBUFF_PARERR1    V_ROBUFF_PARERR1(1U)
83323 
83324 #define S_ROBUFF_PARERR0    9
83325 #define V_ROBUFF_PARERR0(x) ((x) << S_ROBUFF_PARERR0)
83326 #define F_ROBUFF_PARERR0    V_ROBUFF_PARERR0(1U)
83327 
83328 #define S_MA2AXI_REQDATAPARERR    8
83329 #define V_MA2AXI_REQDATAPARERR(x) ((x) << S_MA2AXI_REQDATAPARERR)
83330 #define F_MA2AXI_REQDATAPARERR    V_MA2AXI_REQDATAPARERR(1U)
83331 
83332 #define S_MA2AXI_REQCTLPARERR    7
83333 #define V_MA2AXI_REQCTLPARERR(x) ((x) << S_MA2AXI_REQCTLPARERR)
83334 #define F_MA2AXI_REQCTLPARERR    V_MA2AXI_REQCTLPARERR(1U)
83335 
83336 #define S_MA_RSPPERR    6
83337 #define V_MA_RSPPERR(x) ((x) << S_MA_RSPPERR)
83338 #define F_MA_RSPPERR    V_MA_RSPPERR(1U)
83339 
83340 #define S_PCIE2MA_REQCTLPARERR    5
83341 #define V_PCIE2MA_REQCTLPARERR(x) ((x) << S_PCIE2MA_REQCTLPARERR)
83342 #define F_PCIE2MA_REQCTLPARERR    V_PCIE2MA_REQCTLPARERR(1U)
83343 
83344 #define S_PCIE2MA_REQDATAPARERR    4
83345 #define V_PCIE2MA_REQDATAPARERR(x) ((x) << S_PCIE2MA_REQDATAPARERR)
83346 #define F_PCIE2MA_REQDATAPARERR    V_PCIE2MA_REQDATAPARERR(1U)
83347 
83348 #define S_INIC2MA_REQCTLPARERR    3
83349 #define V_INIC2MA_REQCTLPARERR(x) ((x) << S_INIC2MA_REQCTLPARERR)
83350 #define F_INIC2MA_REQCTLPARERR    V_INIC2MA_REQCTLPARERR(1U)
83351 
83352 #define S_INIC2MA_REQDATAPARERR    2
83353 #define V_INIC2MA_REQDATAPARERR(x) ((x) << S_INIC2MA_REQDATAPARERR)
83354 #define F_INIC2MA_REQDATAPARERR    V_INIC2MA_REQDATAPARERR(1U)
83355 
83356 #define S_MA_RSPUE    1
83357 #define V_MA_RSPUE(x) ((x) << S_MA_RSPUE)
83358 #define F_MA_RSPUE    V_MA_RSPUE(1U)
83359 
83360 #define S_APB2PL_RSPDATAPERR    0
83361 #define V_APB2PL_RSPDATAPERR(x) ((x) << S_APB2PL_RSPDATAPERR)
83362 #define F_APB2PL_RSPDATAPERR    V_APB2PL_RSPDATAPERR(1U)
83363 
83364 #define A_ARM_PERR_INT_ENB0 0x47174
83365 #define A_ARM_SCRATCH_PAD3 0x47178
83366 
83367 #define S_ECO_43187    31
83368 #define V_ECO_43187(x) ((x) << S_ECO_43187)
83369 #define F_ECO_43187    V_ECO_43187(1U)
83370 
83371 #define S_TIMER_SEL    28
83372 #define M_TIMER_SEL    0x7U
83373 #define V_TIMER_SEL(x) ((x) << S_TIMER_SEL)
83374 #define G_TIMER_SEL(x) (((x) >> S_TIMER_SEL) & M_TIMER_SEL)
83375 
83376 #define S_TIMER    4
83377 #define M_TIMER    0xffffffU
83378 #define V_TIMER(x) ((x) << S_TIMER)
83379 #define G_TIMER(x) (((x) >> S_TIMER) & M_TIMER)
83380 
83381 #define S_T7_1_INT    0
83382 #define M_T7_1_INT    0x3U
83383 #define V_T7_1_INT(x) ((x) << S_T7_1_INT)
83384 #define G_T7_1_INT(x) (((x) >> S_T7_1_INT) & M_T7_1_INT)
83385 
83386 #define A_ARM_PERR_INT_CAUSE2 0x4717c
83387 
83388 #define S_INIC_WSTRB_FIFO_PERR    31
83389 #define V_INIC_WSTRB_FIFO_PERR(x) ((x) << S_INIC_WSTRB_FIFO_PERR)
83390 #define F_INIC_WSTRB_FIFO_PERR    V_INIC_WSTRB_FIFO_PERR(1U)
83391 
83392 #define S_INIC_BID_FIFO_PERR    30
83393 #define V_INIC_BID_FIFO_PERR(x) ((x) << S_INIC_BID_FIFO_PERR)
83394 #define F_INIC_BID_FIFO_PERR    V_INIC_BID_FIFO_PERR(1U)
83395 
83396 #define S_CC_SRAM_PKA_PERR    29
83397 #define V_CC_SRAM_PKA_PERR(x) ((x) << S_CC_SRAM_PKA_PERR)
83398 #define F_CC_SRAM_PKA_PERR    V_CC_SRAM_PKA_PERR(1U)
83399 
83400 #define S_CC_SRAM_SEC_PERR    28
83401 #define V_CC_SRAM_SEC_PERR(x) ((x) << S_CC_SRAM_SEC_PERR)
83402 #define F_CC_SRAM_SEC_PERR    V_CC_SRAM_SEC_PERR(1U)
83403 
83404 #define S_MESS2AXI4_PARERR    27
83405 #define V_MESS2AXI4_PARERR(x) ((x) << S_MESS2AXI4_PARERR)
83406 #define F_MESS2AXI4_PARERR    V_MESS2AXI4_PARERR(1U)
83407 
83408 #define S_CCI2INIC_INTF_PARERR    26
83409 #define V_CCI2INIC_INTF_PARERR(x) ((x) << S_CCI2INIC_INTF_PARERR)
83410 #define F_CCI2INIC_INTF_PARERR    V_CCI2INIC_INTF_PARERR(1U)
83411 
83412 #define A_ARM_MA2AXI_AW_ATTR 0x47180
83413 
83414 #define S_AWLOCKR1    29
83415 #define V_AWLOCKR1(x) ((x) << S_AWLOCKR1)
83416 #define F_AWLOCKR1    V_AWLOCKR1(1U)
83417 
83418 #define S_AWCACHER1    25
83419 #define M_AWCACHER1    0xfU
83420 #define V_AWCACHER1(x) ((x) << S_AWCACHER1)
83421 #define G_AWCACHER1(x) (((x) >> S_AWCACHER1) & M_AWCACHER1)
83422 
83423 #define S_AWPROTR1    21
83424 #define M_AWPROTR1    0xfU
83425 #define V_AWPROTR1(x) ((x) << S_AWPROTR1)
83426 #define G_AWPROTR1(x) (((x) >> S_AWPROTR1) & M_AWPROTR1)
83427 
83428 #define S_AWSNOOPR1    18
83429 #define M_AWSNOOPR1    0x7U
83430 #define V_AWSNOOPR1(x) ((x) << S_AWSNOOPR1)
83431 #define G_AWSNOOPR1(x) (((x) >> S_AWSNOOPR1) & M_AWSNOOPR1)
83432 
83433 #define S_AWDOMAINR1    16
83434 #define M_AWDOMAINR1    0x3U
83435 #define V_AWDOMAINR1(x) ((x) << S_AWDOMAINR1)
83436 #define G_AWDOMAINR1(x) (((x) >> S_AWDOMAINR1) & M_AWDOMAINR1)
83437 
83438 #define S_AWLOCKR0    13
83439 #define V_AWLOCKR0(x) ((x) << S_AWLOCKR0)
83440 #define F_AWLOCKR0    V_AWLOCKR0(1U)
83441 
83442 #define S_AWCACHER0    9
83443 #define M_AWCACHER0    0xfU
83444 #define V_AWCACHER0(x) ((x) << S_AWCACHER0)
83445 #define G_AWCACHER0(x) (((x) >> S_AWCACHER0) & M_AWCACHER0)
83446 
83447 #define S_AWPROTR0    5
83448 #define M_AWPROTR0    0xfU
83449 #define V_AWPROTR0(x) ((x) << S_AWPROTR0)
83450 #define G_AWPROTR0(x) (((x) >> S_AWPROTR0) & M_AWPROTR0)
83451 
83452 #define S_AWSNOOPR0    2
83453 #define M_AWSNOOPR0    0x7U
83454 #define V_AWSNOOPR0(x) ((x) << S_AWSNOOPR0)
83455 #define G_AWSNOOPR0(x) (((x) >> S_AWSNOOPR0) & M_AWSNOOPR0)
83456 
83457 #define S_AWDOMAINR0    0
83458 #define M_AWDOMAINR0    0x3U
83459 #define V_AWDOMAINR0(x) ((x) << S_AWDOMAINR0)
83460 #define G_AWDOMAINR0(x) (((x) >> S_AWDOMAINR0) & M_AWDOMAINR0)
83461 
83462 #define A_ARM_MA2AXI_AR_ATTR 0x47184
83463 
83464 #define S_ARLOCKR1    29
83465 #define V_ARLOCKR1(x) ((x) << S_ARLOCKR1)
83466 #define F_ARLOCKR1    V_ARLOCKR1(1U)
83467 
83468 #define S_ARCACHER1    25
83469 #define M_ARCACHER1    0xfU
83470 #define V_ARCACHER1(x) ((x) << S_ARCACHER1)
83471 #define G_ARCACHER1(x) (((x) >> S_ARCACHER1) & M_ARCACHER1)
83472 
83473 #define S_ARPROTR1    21
83474 #define M_ARPROTR1    0xfU
83475 #define V_ARPROTR1(x) ((x) << S_ARPROTR1)
83476 #define G_ARPROTR1(x) (((x) >> S_ARPROTR1) & M_ARPROTR1)
83477 
83478 #define S_ARSNOOPR1    18
83479 #define M_ARSNOOPR1    0x7U
83480 #define V_ARSNOOPR1(x) ((x) << S_ARSNOOPR1)
83481 #define G_ARSNOOPR1(x) (((x) >> S_ARSNOOPR1) & M_ARSNOOPR1)
83482 
83483 #define S_ARDOMAINR1    16
83484 #define M_ARDOMAINR1    0x3U
83485 #define V_ARDOMAINR1(x) ((x) << S_ARDOMAINR1)
83486 #define G_ARDOMAINR1(x) (((x) >> S_ARDOMAINR1) & M_ARDOMAINR1)
83487 
83488 #define S_ARLOCKR0    13
83489 #define V_ARLOCKR0(x) ((x) << S_ARLOCKR0)
83490 #define F_ARLOCKR0    V_ARLOCKR0(1U)
83491 
83492 #define S_ARCACHER0    9
83493 #define M_ARCACHER0    0xfU
83494 #define V_ARCACHER0(x) ((x) << S_ARCACHER0)
83495 #define G_ARCACHER0(x) (((x) >> S_ARCACHER0) & M_ARCACHER0)
83496 
83497 #define S_ARPROTR0    5
83498 #define M_ARPROTR0    0xfU
83499 #define V_ARPROTR0(x) ((x) << S_ARPROTR0)
83500 #define G_ARPROTR0(x) (((x) >> S_ARPROTR0) & M_ARPROTR0)
83501 
83502 #define S_ARSNOOPR0    2
83503 #define M_ARSNOOPR0    0x7U
83504 #define V_ARSNOOPR0(x) ((x) << S_ARSNOOPR0)
83505 #define G_ARSNOOPR0(x) (((x) >> S_ARSNOOPR0) & M_ARSNOOPR0)
83506 
83507 #define S_ARDOMAINR0    0
83508 #define M_ARDOMAINR0    0x3U
83509 #define V_ARDOMAINR0(x) ((x) << S_ARDOMAINR0)
83510 #define G_ARDOMAINR0(x) (((x) >> S_ARDOMAINR0) & M_ARDOMAINR0)
83511 
83512 #define A_ARM_MA2AXI_SNOOP_RGN 0x47188
83513 
83514 #define S_SNOOP_END    16
83515 #define M_SNOOP_END    0xffffU
83516 #define V_SNOOP_END(x) ((x) << S_SNOOP_END)
83517 #define G_SNOOP_END(x) (((x) >> S_SNOOP_END) & M_SNOOP_END)
83518 
83519 #define S_SNOOP_START    0
83520 #define M_SNOOP_START    0xffffU
83521 #define V_SNOOP_START(x) ((x) << S_SNOOP_START)
83522 #define G_SNOOP_START(x) (((x) >> S_SNOOP_START) & M_SNOOP_START)
83523 
83524 #define A_ARM_PERIPHERAL_INT_CAUSE 0x4718c
83525 
83526 #define S_TIMER_INT    5
83527 #define V_TIMER_INT(x) ((x) << S_TIMER_INT)
83528 #define F_TIMER_INT    V_TIMER_INT(1U)
83529 
83530 #define S_NVME_INT    4
83531 #define V_NVME_INT(x) ((x) << S_NVME_INT)
83532 #define F_NVME_INT    V_NVME_INT(1U)
83533 
83534 #define S_EMMC_WAKEUP_INT    3
83535 #define V_EMMC_WAKEUP_INT(x) ((x) << S_EMMC_WAKEUP_INT)
83536 #define F_EMMC_WAKEUP_INT    V_EMMC_WAKEUP_INT(1U)
83537 
83538 #define S_EMMC_INT    2
83539 #define V_EMMC_INT(x) ((x) << S_EMMC_INT)
83540 #define F_EMMC_INT    V_EMMC_INT(1U)
83541 
83542 #define S_USB_MC_INT    1
83543 #define V_USB_MC_INT(x) ((x) << S_USB_MC_INT)
83544 #define F_USB_MC_INT    V_USB_MC_INT(1U)
83545 
83546 #define S_USB_DMA_INT    0
83547 #define V_USB_DMA_INT(x) ((x) << S_USB_DMA_INT)
83548 #define F_USB_DMA_INT    V_USB_DMA_INT(1U)
83549 
83550 #define A_ARM_SCRATCH_PAD4 0x47190
83551 
83552 #define S_PAD4    15
83553 #define M_PAD4    0x1ffffU
83554 #define V_PAD4(x) ((x) << S_PAD4)
83555 #define G_PAD4(x) (((x) >> S_PAD4) & M_PAD4)
83556 
83557 #define S_ARM_DB_CNT    0
83558 #define M_ARM_DB_CNT    0x7fffU
83559 #define V_ARM_DB_CNT(x) ((x) << S_ARM_DB_CNT)
83560 #define G_ARM_DB_CNT(x) (((x) >> S_ARM_DB_CNT) & M_ARM_DB_CNT)
83561 
83562 #define A_ARM_SCRATCH_PAD5 0x47194
83563 #define A_ARM_SCRATCH_PAD6 0x47198
83564 #define A_ARM_SCRATCH_PAD7 0x4719c
83565 #define A_ARM_NVME_DB_EMU_INDEX 0x471a0
83566 #define A_ARM_NVME_DB_EMU_REGION_CTL 0x471a4
83567 
83568 #define S_WINDOW_EN    4
83569 #define V_WINDOW_EN(x) ((x) << S_WINDOW_EN)
83570 #define F_WINDOW_EN    V_WINDOW_EN(1U)
83571 
83572 #define S_RGN2_INT_EN    3
83573 #define V_RGN2_INT_EN(x) ((x) << S_RGN2_INT_EN)
83574 #define F_RGN2_INT_EN    V_RGN2_INT_EN(1U)
83575 
83576 #define S_RGN1_INT_EN    2
83577 #define V_RGN1_INT_EN(x) ((x) << S_RGN1_INT_EN)
83578 #define F_RGN1_INT_EN    V_RGN1_INT_EN(1U)
83579 
83580 #define S_QUEUE_EN    1
83581 #define V_QUEUE_EN(x) ((x) << S_QUEUE_EN)
83582 #define F_QUEUE_EN    V_QUEUE_EN(1U)
83583 
83584 #define S_RGN0_INT_EN    0
83585 #define V_RGN0_INT_EN(x) ((x) << S_RGN0_INT_EN)
83586 #define F_RGN0_INT_EN    V_RGN0_INT_EN(1U)
83587 
83588 #define A_ARM_NVME_DB_EMU_DEVICE_CTL 0x471a8
83589 
83590 #define S_DEVICE_SIZE    8
83591 #define M_DEVICE_SIZE    0xfU
83592 #define V_DEVICE_SIZE(x) ((x) << S_DEVICE_SIZE)
83593 #define G_DEVICE_SIZE(x) (((x) >> S_DEVICE_SIZE) & M_DEVICE_SIZE)
83594 
83595 #define S_RGN1_SIZE    4
83596 #define M_RGN1_SIZE    0xfU
83597 #define V_RGN1_SIZE(x) ((x) << S_RGN1_SIZE)
83598 #define G_RGN1_SIZE(x) (((x) >> S_RGN1_SIZE) & M_RGN1_SIZE)
83599 
83600 #define S_RGN0_SIZE    0
83601 #define M_RGN0_SIZE    0xfU
83602 #define V_RGN0_SIZE(x) ((x) << S_RGN0_SIZE)
83603 #define G_RGN0_SIZE(x) (((x) >> S_RGN0_SIZE) & M_RGN0_SIZE)
83604 
83605 #define A_ARM_NVME_DB_EMU_WINDOW_START_ADDR 0x471b0
83606 
83607 #define S_T7_4_ADDR    0
83608 #define M_T7_4_ADDR    0xfffffffU
83609 #define V_T7_4_ADDR(x) ((x) << S_T7_4_ADDR)
83610 #define G_T7_4_ADDR(x) (((x) >> S_T7_4_ADDR) & M_T7_4_ADDR)
83611 
83612 #define A_ARM_NVME_DB_EMU_WINDOW_END_ADDR 0x471b4
83613 #define A_ARM_NVME_DB_EMU_QBASE_ADDR 0x471b8
83614 #define A_ARM_NVME_DB_EMU_QUEUE_CID 0x471bc
83615 
83616 #define S_T7_CID    0
83617 #define M_T7_CID    0x1ffffU
83618 #define V_T7_CID(x) ((x) << S_T7_CID)
83619 #define G_T7_CID(x) (((x) >> S_T7_CID) & M_T7_CID)
83620 
83621 #define A_ARM_NVME_DB_EMU_QUEUE_CTL 0x471c0
83622 
83623 #define S_INT_EN    27
83624 #define V_INT_EN(x) ((x) << S_INT_EN)
83625 #define F_INT_EN    V_INT_EN(1U)
83626 
83627 #define S_THRESHOLD    10
83628 #define M_THRESHOLD    0x1ffffU
83629 #define V_THRESHOLD(x) ((x) << S_THRESHOLD)
83630 #define G_THRESHOLD(x) (((x) >> S_THRESHOLD) & M_THRESHOLD)
83631 
83632 #define S_T7_1_SIZE    0
83633 #define M_T7_1_SIZE    0x3ffU
83634 #define V_T7_1_SIZE(x) ((x) << S_T7_1_SIZE)
83635 #define G_T7_1_SIZE(x) (((x) >> S_T7_1_SIZE) & M_T7_1_SIZE)
83636 
83637 #define A_ARM_NVME_DB_EMU_MSIX_ADDR_L 0x471c4
83638 #define A_ARM_NVME_DB_EMU_MSIX_ADDR_H 0x471c8
83639 #define A_ARM_NVME_DB_EMU_MSIX_OFFSET 0x471cc
83640 #define A_ARM_NVME_DB_EMU_QUEUE_MSIX_ADDR_L 0x471d0
83641 #define A_ARM_NVME_DB_EMU_QUEUE_MSIX_ADDR_H 0x471d4
83642 #define A_ARM_NVME_DB_EMU_QUEUE_MSIX_OFFSET 0x471d8
83643 #define A_ARM_CERR_INT_CAUSE0 0x471dc
83644 
83645 #define S_WRDATA_FIFO0_CERR    31
83646 #define V_WRDATA_FIFO0_CERR(x) ((x) << S_WRDATA_FIFO0_CERR)
83647 #define F_WRDATA_FIFO0_CERR    V_WRDATA_FIFO0_CERR(1U)
83648 
83649 #define S_WRDATA_FIFO1_CERR    30
83650 #define V_WRDATA_FIFO1_CERR(x) ((x) << S_WRDATA_FIFO1_CERR)
83651 #define F_WRDATA_FIFO1_CERR    V_WRDATA_FIFO1_CERR(1U)
83652 
83653 #define S_WR512DATAFIFO0_CERR    29
83654 #define V_WR512DATAFIFO0_CERR(x) ((x) << S_WR512DATAFIFO0_CERR)
83655 #define F_WR512DATAFIFO0_CERR    V_WR512DATAFIFO0_CERR(1U)
83656 
83657 #define S_WR512DATAFIFO1_CERR    28
83658 #define V_WR512DATAFIFO1_CERR(x) ((x) << S_WR512DATAFIFO1_CERR)
83659 #define F_WR512DATAFIFO1_CERR    V_WR512DATAFIFO1_CERR(1U)
83660 
83661 #define S_RDATAFIFO0_CERR    27
83662 #define V_RDATAFIFO0_CERR(x) ((x) << S_RDATAFIFO0_CERR)
83663 #define F_RDATAFIFO0_CERR    V_RDATAFIFO0_CERR(1U)
83664 
83665 #define S_RDATAFIFO1_CERR    26
83666 #define V_RDATAFIFO1_CERR(x) ((x) << S_RDATAFIFO1_CERR)
83667 #define F_RDATAFIFO1_CERR    V_RDATAFIFO1_CERR(1U)
83668 
83669 #define S_ROBUFF_CORERR0    25
83670 #define V_ROBUFF_CORERR0(x) ((x) << S_ROBUFF_CORERR0)
83671 #define F_ROBUFF_CORERR0    V_ROBUFF_CORERR0(1U)
83672 
83673 #define S_ROBUFF_CORERR1    24
83674 #define V_ROBUFF_CORERR1(x) ((x) << S_ROBUFF_CORERR1)
83675 #define F_ROBUFF_CORERR1    V_ROBUFF_CORERR1(1U)
83676 
83677 #define S_ROBUFF_CORERR2    23
83678 #define V_ROBUFF_CORERR2(x) ((x) << S_ROBUFF_CORERR2)
83679 #define F_ROBUFF_CORERR2    V_ROBUFF_CORERR2(1U)
83680 
83681 #define S_ROBUFF_CORERR3    22
83682 #define V_ROBUFF_CORERR3(x) ((x) << S_ROBUFF_CORERR3)
83683 #define F_ROBUFF_CORERR3    V_ROBUFF_CORERR3(1U)
83684 
83685 #define S_MA2AXI_RSPDATACORERR    21
83686 #define V_MA2AXI_RSPDATACORERR(x) ((x) << S_MA2AXI_RSPDATACORERR)
83687 #define F_MA2AXI_RSPDATACORERR    V_MA2AXI_RSPDATACORERR(1U)
83688 
83689 #define S_RC_SRAM_CERR    19
83690 #define M_RC_SRAM_CERR    0x3U
83691 #define V_RC_SRAM_CERR(x) ((x) << S_RC_SRAM_CERR)
83692 #define G_RC_SRAM_CERR(x) (((x) >> S_RC_SRAM_CERR) & M_RC_SRAM_CERR)
83693 
83694 #define S_RC_WFIFO_OUTCERR    18
83695 #define V_RC_WFIFO_OUTCERR(x) ((x) << S_RC_WFIFO_OUTCERR)
83696 #define F_RC_WFIFO_OUTCERR    V_RC_WFIFO_OUTCERR(1U)
83697 
83698 #define S_RC_RSPFIFO_CERR    17
83699 #define V_RC_RSPFIFO_CERR(x) ((x) << S_RC_RSPFIFO_CERR)
83700 #define F_RC_RSPFIFO_CERR    V_RC_RSPFIFO_CERR(1U)
83701 
83702 #define S_MSI_MEM_CERR    16
83703 #define V_MSI_MEM_CERR(x) ((x) << S_MSI_MEM_CERR)
83704 #define F_MSI_MEM_CERR    V_MSI_MEM_CERR(1U)
83705 
83706 #define S_INIC_WRDATA_FIFO_CERR    15
83707 #define V_INIC_WRDATA_FIFO_CERR(x) ((x) << S_INIC_WRDATA_FIFO_CERR)
83708 #define F_INIC_WRDATA_FIFO_CERR    V_INIC_WRDATA_FIFO_CERR(1U)
83709 
83710 #define S_INIC_RDATAFIFO_CERR    14
83711 #define V_INIC_RDATAFIFO_CERR(x) ((x) << S_INIC_RDATAFIFO_CERR)
83712 #define F_INIC_RDATAFIFO_CERR    V_INIC_RDATAFIFO_CERR(1U)
83713 
83714 #define S_ARM_DB_SRAM_CERR    12
83715 #define M_ARM_DB_SRAM_CERR    0x3U
83716 #define V_ARM_DB_SRAM_CERR(x) ((x) << S_ARM_DB_SRAM_CERR)
83717 #define G_ARM_DB_SRAM_CERR(x) (((x) >> S_ARM_DB_SRAM_CERR) & M_ARM_DB_SRAM_CERR)
83718 
83719 #define S_ICB_RAM_CERR    11
83720 #define V_ICB_RAM_CERR(x) ((x) << S_ICB_RAM_CERR)
83721 #define F_ICB_RAM_CERR    V_ICB_RAM_CERR(1U)
83722 
83723 #define S_CC_SRAM_PKA_CERR    10
83724 #define V_CC_SRAM_PKA_CERR(x) ((x) << S_CC_SRAM_PKA_CERR)
83725 #define F_CC_SRAM_PKA_CERR    V_CC_SRAM_PKA_CERR(1U)
83726 
83727 #define S_CC_SRAM_SEC_CERR    9
83728 #define V_CC_SRAM_SEC_CERR(x) ((x) << S_CC_SRAM_SEC_CERR)
83729 #define F_CC_SRAM_SEC_CERR    V_CC_SRAM_SEC_CERR(1U)
83730 
83731 #define A_ARM_NVME_DB_EMU_QUEUE_CTL_2 0x471e0
83732 
83733 #define S_INTERRUPT_CLEAR    0
83734 #define V_INTERRUPT_CLEAR(x) ((x) << S_INTERRUPT_CLEAR)
83735 #define F_INTERRUPT_CLEAR    V_INTERRUPT_CLEAR(1U)
83736 
83737 #define A_ARM_PERIPHERAL_INT_ENB 0x471e4
83738 #define A_ARM_CERR_INT_ENB0 0x471e8
83739 #define A_ARM_CPU_DBG_ROM_ADDR0 0x47200
83740 
83741 #define S_CPUDBGROMADDR0    0
83742 #define M_CPUDBGROMADDR0    0xfffffU
83743 #define V_CPUDBGROMADDR0(x) ((x) << S_CPUDBGROMADDR0)
83744 #define G_CPUDBGROMADDR0(x) (((x) >> S_CPUDBGROMADDR0) & M_CPUDBGROMADDR0)
83745 
83746 #define A_ARM_CPU_DBG_ROM_ADDR1 0x47204
83747 
83748 #define S_CPUDBGROMADDR1    0
83749 #define M_CPUDBGROMADDR1    0x3ffU
83750 #define V_CPUDBGROMADDR1(x) ((x) << S_CPUDBGROMADDR1)
83751 #define G_CPUDBGROMADDR1(x) (((x) >> S_CPUDBGROMADDR1) & M_CPUDBGROMADDR1)
83752 
83753 #define A_ARM_CPU_DBG_ROM_ADDR_VALID 0x47208
83754 
83755 #define S_CPUDBGROMADDRVALID    0
83756 #define V_CPUDBGROMADDRVALID(x) ((x) << S_CPUDBGROMADDRVALID)
83757 #define F_CPUDBGROMADDRVALID    V_CPUDBGROMADDRVALID(1U)
83758 
83759 #define A_ARM_PERR_ENABLE0 0x4720c
83760 #define A_ARM_SRAM2_WRITE_DATA3 0x47210
83761 #define A_ARM_SRAM2_READ_DATA3 0x4721c
83762 #define A_ARM_CPU_DFT_CFG 0x47220
83763 
83764 #define S_CPUMBISTREQ    11
83765 #define V_CPUMBISTREQ(x) ((x) << S_CPUMBISTREQ)
83766 #define F_CPUMBISTREQ    V_CPUMBISTREQ(1U)
83767 
83768 #define S_CPUMBISTRSTN    10
83769 #define V_CPUMBISTRSTN(x) ((x) << S_CPUMBISTRSTN)
83770 #define F_CPUMBISTRSTN    V_CPUMBISTRSTN(1U)
83771 
83772 #define S_CPUDFTDFTSE    9
83773 #define V_CPUDFTDFTSE(x) ((x) << S_CPUDFTDFTSE)
83774 #define F_CPUDFTDFTSE    V_CPUDFTDFTSE(1U)
83775 
83776 #define S_CPUDFTRSTDISABLE    8
83777 #define V_CPUDFTRSTDISABLE(x) ((x) << S_CPUDFTRSTDISABLE)
83778 #define F_CPUDFTRSTDISABLE    V_CPUDFTRSTDISABLE(1U)
83779 
83780 #define S_CPUDFTRAMDISABLE    7
83781 #define V_CPUDFTRAMDISABLE(x) ((x) << S_CPUDFTRAMDISABLE)
83782 #define F_CPUDFTRAMDISABLE    V_CPUDFTRAMDISABLE(1U)
83783 
83784 #define S_CPUDFTMCPDISABLE    6
83785 #define V_CPUDFTMCPDISABLE(x) ((x) << S_CPUDFTMCPDISABLE)
83786 #define F_CPUDFTMCPDISABLE    V_CPUDFTMCPDISABLE(1U)
83787 
83788 #define S_CPUDFTL2CLKDISABLE    5
83789 #define V_CPUDFTL2CLKDISABLE(x) ((x) << S_CPUDFTL2CLKDISABLE)
83790 #define F_CPUDFTL2CLKDISABLE    V_CPUDFTL2CLKDISABLE(1U)
83791 
83792 #define S_CPUDFTCLKDISABLE3    4
83793 #define V_CPUDFTCLKDISABLE3(x) ((x) << S_CPUDFTCLKDISABLE3)
83794 #define F_CPUDFTCLKDISABLE3    V_CPUDFTCLKDISABLE3(1U)
83795 
83796 #define S_CPUDFTCLKDISABLE2    3
83797 #define V_CPUDFTCLKDISABLE2(x) ((x) << S_CPUDFTCLKDISABLE2)
83798 #define F_CPUDFTCLKDISABLE2    V_CPUDFTCLKDISABLE2(1U)
83799 
83800 #define S_CPUDFTCLKDISABLE1    2
83801 #define V_CPUDFTCLKDISABLE1(x) ((x) << S_CPUDFTCLKDISABLE1)
83802 #define F_CPUDFTCLKDISABLE1    V_CPUDFTCLKDISABLE1(1U)
83803 
83804 #define S_CPUDFTCLKDISABLE0    1
83805 #define V_CPUDFTCLKDISABLE0(x) ((x) << S_CPUDFTCLKDISABLE0)
83806 #define F_CPUDFTCLKDISABLE0    V_CPUDFTCLKDISABLE0(1U)
83807 
83808 #define S_CPUDFTCLKBYPASS    0
83809 #define V_CPUDFTCLKBYPASS(x) ((x) << S_CPUDFTCLKBYPASS)
83810 #define F_CPUDFTCLKBYPASS    V_CPUDFTCLKBYPASS(1U)
83811 
83812 #define A_ARM_APB_CFG 0x47224
83813 
83814 #define S_APB_CFG    0
83815 #define M_APB_CFG    0x3ffffU
83816 #define V_APB_CFG(x) ((x) << S_APB_CFG)
83817 #define G_APB_CFG(x) (((x) >> S_APB_CFG) & M_APB_CFG)
83818 
83819 #define A_ARM_EMMC_BUFS 0x47228
83820 
83821 #define S_EMMC_BUFS_OEN    2
83822 #define M_EMMC_BUFS_OEN    0x3U
83823 #define V_EMMC_BUFS_OEN(x) ((x) << S_EMMC_BUFS_OEN)
83824 #define G_EMMC_BUFS_OEN(x) (((x) >> S_EMMC_BUFS_OEN) & M_EMMC_BUFS_OEN)
83825 
83826 #define S_EMMC_BUFS_I    0
83827 #define M_EMMC_BUFS_I    0x3U
83828 #define V_EMMC_BUFS_I(x) ((x) << S_EMMC_BUFS_I)
83829 #define G_EMMC_BUFS_I(x) (((x) >> S_EMMC_BUFS_I) & M_EMMC_BUFS_I)
83830 
83831 #define A_ARM_SWP_EN 0x4722c
83832 #define A_ARM_ADB_PWR_DWN_REQ_N 0x47230
83833 
83834 #define S_ADBPWRDWNREQN    0
83835 #define V_ADBPWRDWNREQN(x) ((x) << S_ADBPWRDWNREQN)
83836 #define F_ADBPWRDWNREQN    V_ADBPWRDWNREQN(1U)
83837 
83838 #define A_ARM_GIC_USER 0x47238
83839 
83840 #define S_CPU_GIC_USER    0
83841 #define M_CPU_GIC_USER    0x7fU
83842 #define V_CPU_GIC_USER(x) ((x) << S_CPU_GIC_USER)
83843 #define G_CPU_GIC_USER(x) (((x) >> S_CPU_GIC_USER) & M_CPU_GIC_USER)
83844 
83845 #define A_ARM_DBPROC_SRAM_TH_ADDR 0x47240
83846 
83847 #define S_DBPROC_TH_ADDR    0
83848 #define M_DBPROC_TH_ADDR    0x1ffU
83849 #define V_DBPROC_TH_ADDR(x) ((x) << S_DBPROC_TH_ADDR)
83850 #define G_DBPROC_TH_ADDR(x) (((x) >> S_DBPROC_TH_ADDR) & M_DBPROC_TH_ADDR)
83851 
83852 #define A_ARM_DBPROC_SRAM_TH_READ_DATA0 0x47244
83853 #define A_ARM_DBPROC_SRAM_TH_READ_DATA1 0x47248
83854 #define A_ARM_DBPROC_SRAM_TH_READ_DATA2 0x4724c
83855 #define A_ARM_DBPROC_SRAM_TH_READ_DATA3 0x47250
83856 #define A_ARM_DBPROC_SRAM_TH_WR_DATA0 0x47254
83857 #define A_ARM_DBPROC_SRAM_TH_WR_DATA1 0x47258
83858 #define A_ARM_DBPROC_SRAM_TH_WR_DATA2 0x4725c
83859 #define A_ARM_DBPROC_SRAM_TH_WR_DATA3 0x47260
83860 #define A_ARM_SWP_EN_2 0x47264
83861 
83862 #define S_SWP_EN_2    0
83863 #define M_SWP_EN_2    0x3U
83864 #define V_SWP_EN_2(x) ((x) << S_SWP_EN_2)
83865 #define G_SWP_EN_2(x) (((x) >> S_SWP_EN_2) & M_SWP_EN_2)
83866 
83867 #define A_ARM_GIC_ERR 0x47268
83868 
83869 #define S_ECC_FATAL    1
83870 #define V_ECC_FATAL(x) ((x) << S_ECC_FATAL)
83871 #define F_ECC_FATAL    V_ECC_FATAL(1U)
83872 
83873 #define S_AXIM_ERR    0
83874 #define V_AXIM_ERR(x) ((x) << S_AXIM_ERR)
83875 #define F_AXIM_ERR    V_AXIM_ERR(1U)
83876 
83877 #define A_ARM_CPU_STAT 0x4726c
83878 
83879 #define S_CPU_L2_QACTIVE    12
83880 #define V_CPU_L2_QACTIVE(x) ((x) << S_CPU_L2_QACTIVE)
83881 #define F_CPU_L2_QACTIVE    V_CPU_L2_QACTIVE(1U)
83882 
83883 #define S_WAKEUPM_O_ADB    11
83884 #define V_WAKEUPM_O_ADB(x) ((x) << S_WAKEUPM_O_ADB)
83885 #define F_WAKEUPM_O_ADB    V_WAKEUPM_O_ADB(1U)
83886 
83887 #define S_PWRQACTIVEM_ADB    10
83888 #define V_PWRQACTIVEM_ADB(x) ((x) << S_PWRQACTIVEM_ADB)
83889 #define F_PWRQACTIVEM_ADB    V_PWRQACTIVEM_ADB(1U)
83890 
83891 #define S_CLKQACTIVEM_ADB    9
83892 #define V_CLKQACTIVEM_ADB(x) ((x) << S_CLKQACTIVEM_ADB)
83893 #define F_CLKQACTIVEM_ADB    V_CLKQACTIVEM_ADB(1U)
83894 
83895 #define S_CLKQDENYM_ADB    8
83896 #define V_CLKQDENYM_ADB(x) ((x) << S_CLKQDENYM_ADB)
83897 #define F_CLKQDENYM_ADB    V_CLKQDENYM_ADB(1U)
83898 
83899 #define S_CLKQACCEPTNM_ADB    7
83900 #define V_CLKQACCEPTNM_ADB(x) ((x) << S_CLKQACCEPTNM_ADB)
83901 #define F_CLKQACCEPTNM_ADB    V_CLKQACCEPTNM_ADB(1U)
83902 
83903 #define S_WAKEUPS_O_ADB    6
83904 #define V_WAKEUPS_O_ADB(x) ((x) << S_WAKEUPS_O_ADB)
83905 #define F_WAKEUPS_O_ADB    V_WAKEUPS_O_ADB(1U)
83906 
83907 #define S_PWRQACTIVES_ADB    5
83908 #define V_PWRQACTIVES_ADB(x) ((x) << S_PWRQACTIVES_ADB)
83909 #define F_PWRQACTIVES_ADB    V_PWRQACTIVES_ADB(1U)
83910 
83911 #define S_CLKQACTIVES_ADB    4
83912 #define V_CLKQACTIVES_ADB(x) ((x) << S_CLKQACTIVES_ADB)
83913 #define F_CLKQACTIVES_ADB    V_CLKQACTIVES_ADB(1U)
83914 
83915 #define S_CLKQDENYS_ADB    3
83916 #define V_CLKQDENYS_ADB(x) ((x) << S_CLKQDENYS_ADB)
83917 #define F_CLKQDENYS_ADB    V_CLKQDENYS_ADB(1U)
83918 
83919 #define S_CLKQACCEPTNS_ADB    2
83920 #define V_CLKQACCEPTNS_ADB(x) ((x) << S_CLKQACCEPTNS_ADB)
83921 #define F_CLKQACCEPTNS_ADB    V_CLKQACCEPTNS_ADB(1U)
83922 
83923 #define S_PWRQDENYS_ADB    1
83924 #define V_PWRQDENYS_ADB(x) ((x) << S_PWRQDENYS_ADB)
83925 #define F_PWRQDENYS_ADB    V_PWRQDENYS_ADB(1U)
83926 
83927 #define S_PWRQACCEPTNS_ADB    0
83928 #define V_PWRQACCEPTNS_ADB(x) ((x) << S_PWRQACCEPTNS_ADB)
83929 #define F_PWRQACCEPTNS_ADB    V_PWRQACCEPTNS_ADB(1U)
83930 
83931 #define A_ARM_DEBUG_INT_WRITE_DATA 0x47270
83932 
83933 #define S_DEBUG_INT_WRITE_DATA    0
83934 #define M_DEBUG_INT_WRITE_DATA    0xfffU
83935 #define V_DEBUG_INT_WRITE_DATA(x) ((x) << S_DEBUG_INT_WRITE_DATA)
83936 #define G_DEBUG_INT_WRITE_DATA(x) (((x) >> S_DEBUG_INT_WRITE_DATA) & M_DEBUG_INT_WRITE_DATA)
83937 
83938 #define A_ARM_DEBUG_INT_STAT 0x47274
83939 
83940 #define S_DEBUG_INT_STATUS_REG    0
83941 #define M_DEBUG_INT_STATUS_REG    0xfffU
83942 #define V_DEBUG_INT_STATUS_REG(x) ((x) << S_DEBUG_INT_STATUS_REG)
83943 #define G_DEBUG_INT_STATUS_REG(x) (((x) >> S_DEBUG_INT_STATUS_REG) & M_DEBUG_INT_STATUS_REG)
83944 
83945 #define A_ARM_DEBUG_STAT 0x47278
83946 
83947 #define S_ARM_DEBUG_STAT    0
83948 #define M_ARM_DEBUG_STAT    0x3fffU
83949 #define V_ARM_DEBUG_STAT(x) ((x) << S_ARM_DEBUG_STAT)
83950 #define G_ARM_DEBUG_STAT(x) (((x) >> S_ARM_DEBUG_STAT) & M_ARM_DEBUG_STAT)
83951 
83952 #define A_ARM_SIZE_STAT 0x4727c
83953 
83954 #define S_ARM_SIZE_STAT    0
83955 #define M_ARM_SIZE_STAT    0x3fffffffU
83956 #define V_ARM_SIZE_STAT(x) ((x) << S_ARM_SIZE_STAT)
83957 #define G_ARM_SIZE_STAT(x) (((x) >> S_ARM_SIZE_STAT) & M_ARM_SIZE_STAT)
83958 
83959 #define A_ARM_CCI_CFG0 0x47280
83960 
83961 #define S_CCIBROADCASTCACHEMAINT    28
83962 #define M_CCIBROADCASTCACHEMAINT    0x7U
83963 #define V_CCIBROADCASTCACHEMAINT(x) ((x) << S_CCIBROADCASTCACHEMAINT)
83964 #define G_CCIBROADCASTCACHEMAINT(x) (((x) >> S_CCIBROADCASTCACHEMAINT) & M_CCIBROADCASTCACHEMAINT)
83965 
83966 #define S_CCISTRIPINGGRANULE    25
83967 #define M_CCISTRIPINGGRANULE    0x7U
83968 #define V_CCISTRIPINGGRANULE(x) ((x) << S_CCISTRIPINGGRANULE)
83969 #define G_CCISTRIPINGGRANULE(x) (((x) >> S_CCISTRIPINGGRANULE) & M_CCISTRIPINGGRANULE)
83970 
83971 #define S_CCIPERIPHBASE    0
83972 #define M_CCIPERIPHBASE    0x1ffffffU
83973 #define V_CCIPERIPHBASE(x) ((x) << S_CCIPERIPHBASE)
83974 #define G_CCIPERIPHBASE(x) (((x) >> S_CCIPERIPHBASE) & M_CCIPERIPHBASE)
83975 
83976 #define A_ARM_CCI_CFG1 0x47284
83977 
83978 #define S_CCIDFTRSTDISABLE    18
83979 #define V_CCIDFTRSTDISABLE(x) ((x) << S_CCIDFTRSTDISABLE)
83980 #define F_CCIDFTRSTDISABLE    V_CCIDFTRSTDISABLE(1U)
83981 
83982 #define S_CCISPNIDEN    17
83983 #define V_CCISPNIDEN(x) ((x) << S_CCISPNIDEN)
83984 #define F_CCISPNIDEN    V_CCISPNIDEN(1U)
83985 
83986 #define S_CCINIDEN    16
83987 #define V_CCINIDEN(x) ((x) << S_CCINIDEN)
83988 #define F_CCINIDEN    V_CCINIDEN(1U)
83989 
83990 #define S_CCIACCHANNELN    11
83991 #define M_CCIACCHANNELN    0x1fU
83992 #define V_CCIACCHANNELN(x) ((x) << S_CCIACCHANNELN)
83993 #define G_CCIACCHANNELN(x) (((x) >> S_CCIACCHANNELN) & M_CCIACCHANNELN)
83994 
83995 #define S_CCIQOSOVERRIDE    6
83996 #define M_CCIQOSOVERRIDE    0x1fU
83997 #define V_CCIQOSOVERRIDE(x) ((x) << S_CCIQOSOVERRIDE)
83998 #define G_CCIQOSOVERRIDE(x) (((x) >> S_CCIQOSOVERRIDE) & M_CCIQOSOVERRIDE)
83999 
84000 #define S_CCIBUFFERABLEOVERRIDE    3
84001 #define M_CCIBUFFERABLEOVERRIDE    0x7U
84002 #define V_CCIBUFFERABLEOVERRIDE(x) ((x) << S_CCIBUFFERABLEOVERRIDE)
84003 #define G_CCIBUFFERABLEOVERRIDE(x) (((x) >> S_CCIBUFFERABLEOVERRIDE) & M_CCIBUFFERABLEOVERRIDE)
84004 
84005 #define S_CCIBARRIERTERMINATE    0
84006 #define M_CCIBARRIERTERMINATE    0x7U
84007 #define V_CCIBARRIERTERMINATE(x) ((x) << S_CCIBARRIERTERMINATE)
84008 #define G_CCIBARRIERTERMINATE(x) (((x) >> S_CCIBARRIERTERMINATE) & M_CCIBARRIERTERMINATE)
84009 
84010 #define A_ARM_CCI_CFG2 0x47288
84011 
84012 #define S_CCIADDRMAP15    30
84013 #define M_CCIADDRMAP15    0x3U
84014 #define V_CCIADDRMAP15(x) ((x) << S_CCIADDRMAP15)
84015 #define G_CCIADDRMAP15(x) (((x) >> S_CCIADDRMAP15) & M_CCIADDRMAP15)
84016 
84017 #define S_CCIADDRMAP14    28
84018 #define M_CCIADDRMAP14    0x3U
84019 #define V_CCIADDRMAP14(x) ((x) << S_CCIADDRMAP14)
84020 #define G_CCIADDRMAP14(x) (((x) >> S_CCIADDRMAP14) & M_CCIADDRMAP14)
84021 
84022 #define S_CCIADDRMAP13    26
84023 #define M_CCIADDRMAP13    0x3U
84024 #define V_CCIADDRMAP13(x) ((x) << S_CCIADDRMAP13)
84025 #define G_CCIADDRMAP13(x) (((x) >> S_CCIADDRMAP13) & M_CCIADDRMAP13)
84026 
84027 #define S_CCIADDRMAP12    24
84028 #define M_CCIADDRMAP12    0x3U
84029 #define V_CCIADDRMAP12(x) ((x) << S_CCIADDRMAP12)
84030 #define G_CCIADDRMAP12(x) (((x) >> S_CCIADDRMAP12) & M_CCIADDRMAP12)
84031 
84032 #define S_CCIADDRMAP11    22
84033 #define M_CCIADDRMAP11    0x3U
84034 #define V_CCIADDRMAP11(x) ((x) << S_CCIADDRMAP11)
84035 #define G_CCIADDRMAP11(x) (((x) >> S_CCIADDRMAP11) & M_CCIADDRMAP11)
84036 
84037 #define S_CCIADDRMAP10    20
84038 #define M_CCIADDRMAP10    0x3U
84039 #define V_CCIADDRMAP10(x) ((x) << S_CCIADDRMAP10)
84040 #define G_CCIADDRMAP10(x) (((x) >> S_CCIADDRMAP10) & M_CCIADDRMAP10)
84041 
84042 #define S_CCIADDRMAP9    18
84043 #define M_CCIADDRMAP9    0x3U
84044 #define V_CCIADDRMAP9(x) ((x) << S_CCIADDRMAP9)
84045 #define G_CCIADDRMAP9(x) (((x) >> S_CCIADDRMAP9) & M_CCIADDRMAP9)
84046 
84047 #define S_CCIADDRMAP8    16
84048 #define M_CCIADDRMAP8    0x3U
84049 #define V_CCIADDRMAP8(x) ((x) << S_CCIADDRMAP8)
84050 #define G_CCIADDRMAP8(x) (((x) >> S_CCIADDRMAP8) & M_CCIADDRMAP8)
84051 
84052 #define S_CCIADDRMAP7    14
84053 #define M_CCIADDRMAP7    0x3U
84054 #define V_CCIADDRMAP7(x) ((x) << S_CCIADDRMAP7)
84055 #define G_CCIADDRMAP7(x) (((x) >> S_CCIADDRMAP7) & M_CCIADDRMAP7)
84056 
84057 #define S_CCIADDRMAP6    12
84058 #define M_CCIADDRMAP6    0x3U
84059 #define V_CCIADDRMAP6(x) ((x) << S_CCIADDRMAP6)
84060 #define G_CCIADDRMAP6(x) (((x) >> S_CCIADDRMAP6) & M_CCIADDRMAP6)
84061 
84062 #define S_CCIADDRMAP5    10
84063 #define M_CCIADDRMAP5    0x3U
84064 #define V_CCIADDRMAP5(x) ((x) << S_CCIADDRMAP5)
84065 #define G_CCIADDRMAP5(x) (((x) >> S_CCIADDRMAP5) & M_CCIADDRMAP5)
84066 
84067 #define S_CCIADDRMAP4    8
84068 #define M_CCIADDRMAP4    0x3U
84069 #define V_CCIADDRMAP4(x) ((x) << S_CCIADDRMAP4)
84070 #define G_CCIADDRMAP4(x) (((x) >> S_CCIADDRMAP4) & M_CCIADDRMAP4)
84071 
84072 #define S_CCIADDRMAP3    6
84073 #define M_CCIADDRMAP3    0x3U
84074 #define V_CCIADDRMAP3(x) ((x) << S_CCIADDRMAP3)
84075 #define G_CCIADDRMAP3(x) (((x) >> S_CCIADDRMAP3) & M_CCIADDRMAP3)
84076 
84077 #define S_CCIADDRMAP2    4
84078 #define M_CCIADDRMAP2    0x3U
84079 #define V_CCIADDRMAP2(x) ((x) << S_CCIADDRMAP2)
84080 #define G_CCIADDRMAP2(x) (((x) >> S_CCIADDRMAP2) & M_CCIADDRMAP2)
84081 
84082 #define S_CCIADDRMAP1    2
84083 #define M_CCIADDRMAP1    0x3U
84084 #define V_CCIADDRMAP1(x) ((x) << S_CCIADDRMAP1)
84085 #define G_CCIADDRMAP1(x) (((x) >> S_CCIADDRMAP1) & M_CCIADDRMAP1)
84086 
84087 #define S_CCIADDRMAP0    0
84088 #define M_CCIADDRMAP0    0x3U
84089 #define V_CCIADDRMAP0(x) ((x) << S_CCIADDRMAP0)
84090 #define G_CCIADDRMAP0(x) (((x) >> S_CCIADDRMAP0) & M_CCIADDRMAP0)
84091 
84092 #define A_ARM_CCI_STATUS 0x4728c
84093 
84094 #define S_CCICACTIVE    6
84095 #define V_CCICACTIVE(x) ((x) << S_CCICACTIVE)
84096 #define F_CCICACTIVE    V_CCICACTIVE(1U)
84097 
84098 #define S_CCICSYSACK    5
84099 #define V_CCICSYSACK(x) ((x) << S_CCICSYSACK)
84100 #define F_CCICSYSACK    V_CCICSYSACK(1U)
84101 
84102 #define S_CCINEVNTCNTOVERFLOW    0
84103 #define M_CCINEVNTCNTOVERFLOW    0x1fU
84104 #define V_CCINEVNTCNTOVERFLOW(x) ((x) << S_CCINEVNTCNTOVERFLOW)
84105 #define G_CCINEVNTCNTOVERFLOW(x) (((x) >> S_CCINEVNTCNTOVERFLOW) & M_CCINEVNTCNTOVERFLOW)
84106 
84107 #define A_ARM_CCIM_CCI_QVN_MASTER_CFG 0x47290
84108 
84109 #define S_CCIVWREADYVN3M    20
84110 #define V_CCIVWREADYVN3M(x) ((x) << S_CCIVWREADYVN3M)
84111 #define F_CCIVWREADYVN3M    V_CCIVWREADYVN3M(1U)
84112 
84113 #define S_CCIVAWREADYVN3M    19
84114 #define V_CCIVAWREADYVN3M(x) ((x) << S_CCIVAWREADYVN3M)
84115 #define F_CCIVAWREADYVN3M    V_CCIVAWREADYVN3M(1U)
84116 
84117 #define S_CCIVARREADYVN3M    18
84118 #define V_CCIVARREADYVN3M(x) ((x) << S_CCIVARREADYVN3M)
84119 #define F_CCIVARREADYVN3M    V_CCIVARREADYVN3M(1U)
84120 
84121 #define S_CCIVWREADYVN2M    17
84122 #define V_CCIVWREADYVN2M(x) ((x) << S_CCIVWREADYVN2M)
84123 #define F_CCIVWREADYVN2M    V_CCIVWREADYVN2M(1U)
84124 
84125 #define S_CCIVAWREADYVN2M    16
84126 #define V_CCIVAWREADYVN2M(x) ((x) << S_CCIVAWREADYVN2M)
84127 #define F_CCIVAWREADYVN2M    V_CCIVAWREADYVN2M(1U)
84128 
84129 #define S_CCIVARREADYVN2M    15
84130 #define V_CCIVARREADYVN2M(x) ((x) << S_CCIVARREADYVN2M)
84131 #define F_CCIVARREADYVN2M    V_CCIVARREADYVN2M(1U)
84132 
84133 #define S_CCIVWREADYVN1M    14
84134 #define V_CCIVWREADYVN1M(x) ((x) << S_CCIVWREADYVN1M)
84135 #define F_CCIVWREADYVN1M    V_CCIVWREADYVN1M(1U)
84136 
84137 #define S_CCIVAWREADYVN1M    13
84138 #define V_CCIVAWREADYVN1M(x) ((x) << S_CCIVAWREADYVN1M)
84139 #define F_CCIVAWREADYVN1M    V_CCIVAWREADYVN1M(1U)
84140 
84141 #define S_CCIVARREADYVN1M    12
84142 #define V_CCIVARREADYVN1M(x) ((x) << S_CCIVARREADYVN1M)
84143 #define F_CCIVARREADYVN1M    V_CCIVARREADYVN1M(1U)
84144 
84145 #define S_CCIVWREADYVN0M    11
84146 #define V_CCIVWREADYVN0M(x) ((x) << S_CCIVWREADYVN0M)
84147 #define F_CCIVWREADYVN0M    V_CCIVWREADYVN0M(1U)
84148 
84149 #define S_CCIVAWREADYVN0M    10
84150 #define V_CCIVAWREADYVN0M(x) ((x) << S_CCIVAWREADYVN0M)
84151 #define F_CCIVAWREADYVN0M    V_CCIVAWREADYVN0M(1U)
84152 
84153 #define S_CCIVARREADYVN0M    9
84154 #define V_CCIVARREADYVN0M(x) ((x) << S_CCIVARREADYVN0M)
84155 #define F_CCIVARREADYVN0M    V_CCIVARREADYVN0M(1U)
84156 
84157 #define S_CCIQVNPREALLOCWM    5
84158 #define M_CCIQVNPREALLOCWM    0xfU
84159 #define V_CCIQVNPREALLOCWM(x) ((x) << S_CCIQVNPREALLOCWM)
84160 #define G_CCIQVNPREALLOCWM(x) (((x) >> S_CCIQVNPREALLOCWM) & M_CCIQVNPREALLOCWM)
84161 
84162 #define S_CCIQVNPREALLOCRM    1
84163 #define M_CCIQVNPREALLOCRM    0xfU
84164 #define V_CCIQVNPREALLOCRM(x) ((x) << S_CCIQVNPREALLOCRM)
84165 #define G_CCIQVNPREALLOCRM(x) (((x) >> S_CCIQVNPREALLOCRM) & M_CCIQVNPREALLOCRM)
84166 
84167 #define S_CCIQVNENABLEM    0
84168 #define V_CCIQVNENABLEM(x) ((x) << S_CCIQVNENABLEM)
84169 #define F_CCIQVNENABLEM    V_CCIQVNENABLEM(1U)
84170 
84171 #define A_ARM_CCIM_CCI_QVN_MASTER_STATUS 0x47294
84172 
84173 #define S_CCIVWVALIDN3M    31
84174 #define V_CCIVWVALIDN3M(x) ((x) << S_CCIVWVALIDN3M)
84175 #define F_CCIVWVALIDN3M    V_CCIVWVALIDN3M(1U)
84176 
84177 #define S_CCIVAWVALIDN3M    30
84178 #define V_CCIVAWVALIDN3M(x) ((x) << S_CCIVAWVALIDN3M)
84179 #define F_CCIVAWVALIDN3M    V_CCIVAWVALIDN3M(1U)
84180 
84181 #define S_CCIVAWQOSN3M    29
84182 #define V_CCIVAWQOSN3M(x) ((x) << S_CCIVAWQOSN3M)
84183 #define F_CCIVAWQOSN3M    V_CCIVAWQOSN3M(1U)
84184 
84185 #define S_CCIVARVALIDN3M    28
84186 #define V_CCIVARVALIDN3M(x) ((x) << S_CCIVARVALIDN3M)
84187 #define F_CCIVARVALIDN3M    V_CCIVARVALIDN3M(1U)
84188 
84189 #define S_CCIVARQOSN3M    24
84190 #define M_CCIVARQOSN3M    0xfU
84191 #define V_CCIVARQOSN3M(x) ((x) << S_CCIVARQOSN3M)
84192 #define G_CCIVARQOSN3M(x) (((x) >> S_CCIVARQOSN3M) & M_CCIVARQOSN3M)
84193 
84194 #define S_CCIVWVALIDN2M    23
84195 #define V_CCIVWVALIDN2M(x) ((x) << S_CCIVWVALIDN2M)
84196 #define F_CCIVWVALIDN2M    V_CCIVWVALIDN2M(1U)
84197 
84198 #define S_CCIVAWVALIDN2M    22
84199 #define V_CCIVAWVALIDN2M(x) ((x) << S_CCIVAWVALIDN2M)
84200 #define F_CCIVAWVALIDN2M    V_CCIVAWVALIDN2M(1U)
84201 
84202 #define S_CCIVAWQOSN2M    21
84203 #define V_CCIVAWQOSN2M(x) ((x) << S_CCIVAWQOSN2M)
84204 #define F_CCIVAWQOSN2M    V_CCIVAWQOSN2M(1U)
84205 
84206 #define S_CCIVARVALIDN2M    20
84207 #define V_CCIVARVALIDN2M(x) ((x) << S_CCIVARVALIDN2M)
84208 #define F_CCIVARVALIDN2M    V_CCIVARVALIDN2M(1U)
84209 
84210 #define S_CCIVARQOSN2M    16
84211 #define M_CCIVARQOSN2M    0xfU
84212 #define V_CCIVARQOSN2M(x) ((x) << S_CCIVARQOSN2M)
84213 #define G_CCIVARQOSN2M(x) (((x) >> S_CCIVARQOSN2M) & M_CCIVARQOSN2M)
84214 
84215 #define S_CCIVWVALIDN1M    15
84216 #define V_CCIVWVALIDN1M(x) ((x) << S_CCIVWVALIDN1M)
84217 #define F_CCIVWVALIDN1M    V_CCIVWVALIDN1M(1U)
84218 
84219 #define S_CCIVAWVALIDN1M    14
84220 #define V_CCIVAWVALIDN1M(x) ((x) << S_CCIVAWVALIDN1M)
84221 #define F_CCIVAWVALIDN1M    V_CCIVAWVALIDN1M(1U)
84222 
84223 #define S_CCIVAWQOSN1M    13
84224 #define V_CCIVAWQOSN1M(x) ((x) << S_CCIVAWQOSN1M)
84225 #define F_CCIVAWQOSN1M    V_CCIVAWQOSN1M(1U)
84226 
84227 #define S_CCIVARVALIDN1M    12
84228 #define V_CCIVARVALIDN1M(x) ((x) << S_CCIVARVALIDN1M)
84229 #define F_CCIVARVALIDN1M    V_CCIVARVALIDN1M(1U)
84230 
84231 #define S_CCIVARQOSN1M    8
84232 #define M_CCIVARQOSN1M    0xfU
84233 #define V_CCIVARQOSN1M(x) ((x) << S_CCIVARQOSN1M)
84234 #define G_CCIVARQOSN1M(x) (((x) >> S_CCIVARQOSN1M) & M_CCIVARQOSN1M)
84235 
84236 #define S_CCIVWVALIDN0M    7
84237 #define V_CCIVWVALIDN0M(x) ((x) << S_CCIVWVALIDN0M)
84238 #define F_CCIVWVALIDN0M    V_CCIVWVALIDN0M(1U)
84239 
84240 #define S_CCIVAWVALIDN0M    6
84241 #define V_CCIVAWVALIDN0M(x) ((x) << S_CCIVAWVALIDN0M)
84242 #define F_CCIVAWVALIDN0M    V_CCIVAWVALIDN0M(1U)
84243 
84244 #define S_CCIVAWQOSN0M    5
84245 #define V_CCIVAWQOSN0M(x) ((x) << S_CCIVAWQOSN0M)
84246 #define F_CCIVAWQOSN0M    V_CCIVAWQOSN0M(1U)
84247 
84248 #define S_CCIVARVALIDN0M    4
84249 #define V_CCIVARVALIDN0M(x) ((x) << S_CCIVARVALIDN0M)
84250 #define F_CCIVARVALIDN0M    V_CCIVARVALIDN0M(1U)
84251 
84252 #define S_CCIVARQOSN0M    0
84253 #define M_CCIVARQOSN0M    0xfU
84254 #define V_CCIVARQOSN0M(x) ((x) << S_CCIVARQOSN0M)
84255 #define G_CCIVARQOSN0M(x) (((x) >> S_CCIVARQOSN0M) & M_CCIVARQOSN0M)
84256 
84257 #define A_ARM_CCIS_CCI_QVN_SLAVE_CFG 0x472d0
84258 
84259 #define S_CCIQVNVNETS    0
84260 #define M_CCIQVNVNETS    0x3U
84261 #define V_CCIQVNVNETS(x) ((x) << S_CCIQVNVNETS)
84262 #define G_CCIQVNVNETS(x) (((x) >> S_CCIQVNVNETS) & M_CCIQVNVNETS)
84263 
84264 #define A_ARM_CCIS_CCI_QVN_SLAVE_STATUS 0x472d4
84265 
84266 #define S_CCIEVNTAWQOS    4
84267 #define M_CCIEVNTAWQOS    0xfU
84268 #define V_CCIEVNTAWQOS(x) ((x) << S_CCIEVNTAWQOS)
84269 #define G_CCIEVNTAWQOS(x) (((x) >> S_CCIEVNTAWQOS) & M_CCIEVNTAWQOS)
84270 
84271 #define S_CCIEVNTARQOS    0
84272 #define M_CCIEVNTARQOS    0xfU
84273 #define V_CCIEVNTARQOS(x) ((x) << S_CCIEVNTARQOS)
84274 #define G_CCIEVNTARQOS(x) (((x) >> S_CCIEVNTARQOS) & M_CCIEVNTARQOS)
84275 
84276 #define A_ARM_CCI_EVNTBUS 0x47300
84277 #define A_ARM_CCI_RST_N 0x47318
84278 
84279 #define S_CCIRSTN    0
84280 #define V_CCIRSTN(x) ((x) << S_CCIRSTN)
84281 #define F_CCIRSTN    V_CCIRSTN(1U)
84282 
84283 #define A_ARM_CCI_CSYREQ 0x4731c
84284 
84285 #define S_CCICSYSREQ    0
84286 #define V_CCICSYSREQ(x) ((x) << S_CCICSYSREQ)
84287 #define F_CCICSYSREQ    V_CCICSYSREQ(1U)
84288 
84289 #define A_ARM_CCI_TR_DEBUGS0 0x47320
84290 
84291 #define S_CCIS0RCNT    24
84292 #define M_CCIS0RCNT    0xffU
84293 #define V_CCIS0RCNT(x) ((x) << S_CCIS0RCNT)
84294 #define G_CCIS0RCNT(x) (((x) >> S_CCIS0RCNT) & M_CCIS0RCNT)
84295 
84296 #define S_CCIS0ARCNT    16
84297 #define M_CCIS0ARCNT    0xffU
84298 #define V_CCIS0ARCNT(x) ((x) << S_CCIS0ARCNT)
84299 #define G_CCIS0ARCNT(x) (((x) >> S_CCIS0ARCNT) & M_CCIS0ARCNT)
84300 
84301 #define S_CCIS0WCNT    8
84302 #define M_CCIS0WCNT    0xffU
84303 #define V_CCIS0WCNT(x) ((x) << S_CCIS0WCNT)
84304 #define G_CCIS0WCNT(x) (((x) >> S_CCIS0WCNT) & M_CCIS0WCNT)
84305 
84306 #define S_CCIS0AWCNT    0
84307 #define M_CCIS0AWCNT    0xffU
84308 #define V_CCIS0AWCNT(x) ((x) << S_CCIS0AWCNT)
84309 #define G_CCIS0AWCNT(x) (((x) >> S_CCIS0AWCNT) & M_CCIS0AWCNT)
84310 
84311 #define A_ARM_CCI_TR_DEBUGS1 0x47324
84312 
84313 #define S_CCIS1RCNT    24
84314 #define M_CCIS1RCNT    0xffU
84315 #define V_CCIS1RCNT(x) ((x) << S_CCIS1RCNT)
84316 #define G_CCIS1RCNT(x) (((x) >> S_CCIS1RCNT) & M_CCIS1RCNT)
84317 
84318 #define S_CCIS1ARCNT    16
84319 #define M_CCIS1ARCNT    0xffU
84320 #define V_CCIS1ARCNT(x) ((x) << S_CCIS1ARCNT)
84321 #define G_CCIS1ARCNT(x) (((x) >> S_CCIS1ARCNT) & M_CCIS1ARCNT)
84322 
84323 #define S_CCIS1WCNT    8
84324 #define M_CCIS1WCNT    0xffU
84325 #define V_CCIS1WCNT(x) ((x) << S_CCIS1WCNT)
84326 #define G_CCIS1WCNT(x) (((x) >> S_CCIS1WCNT) & M_CCIS1WCNT)
84327 
84328 #define S_CCIS1AWCNT    0
84329 #define M_CCIS1AWCNT    0xffU
84330 #define V_CCIS1AWCNT(x) ((x) << S_CCIS1AWCNT)
84331 #define G_CCIS1AWCNT(x) (((x) >> S_CCIS1AWCNT) & M_CCIS1AWCNT)
84332 
84333 #define A_ARM_CCI_TR_DEBUGS2 0x47328
84334 
84335 #define S_CCIS2RCNT    24
84336 #define M_CCIS2RCNT    0xffU
84337 #define V_CCIS2RCNT(x) ((x) << S_CCIS2RCNT)
84338 #define G_CCIS2RCNT(x) (((x) >> S_CCIS2RCNT) & M_CCIS2RCNT)
84339 
84340 #define S_CCIS2ARCNT    16
84341 #define M_CCIS2ARCNT    0xffU
84342 #define V_CCIS2ARCNT(x) ((x) << S_CCIS2ARCNT)
84343 #define G_CCIS2ARCNT(x) (((x) >> S_CCIS2ARCNT) & M_CCIS2ARCNT)
84344 
84345 #define S_CCIS2WCNT    8
84346 #define M_CCIS2WCNT    0xffU
84347 #define V_CCIS2WCNT(x) ((x) << S_CCIS2WCNT)
84348 #define G_CCIS2WCNT(x) (((x) >> S_CCIS2WCNT) & M_CCIS2WCNT)
84349 
84350 #define S_CCIS2AWCNT    0
84351 #define M_CCIS2AWCNT    0xffU
84352 #define V_CCIS2AWCNT(x) ((x) << S_CCIS2AWCNT)
84353 #define G_CCIS2AWCNT(x) (((x) >> S_CCIS2AWCNT) & M_CCIS2AWCNT)
84354 
84355 #define A_ARM_CCI_TR_DEBUGS3 0x4732c
84356 
84357 #define S_CCIS3RCNT    24
84358 #define M_CCIS3RCNT    0xffU
84359 #define V_CCIS3RCNT(x) ((x) << S_CCIS3RCNT)
84360 #define G_CCIS3RCNT(x) (((x) >> S_CCIS3RCNT) & M_CCIS3RCNT)
84361 
84362 #define S_CCIS3ARCNT    16
84363 #define M_CCIS3ARCNT    0xffU
84364 #define V_CCIS3ARCNT(x) ((x) << S_CCIS3ARCNT)
84365 #define G_CCIS3ARCNT(x) (((x) >> S_CCIS3ARCNT) & M_CCIS3ARCNT)
84366 
84367 #define S_CCIS3WCNT    8
84368 #define M_CCIS3WCNT    0xffU
84369 #define V_CCIS3WCNT(x) ((x) << S_CCIS3WCNT)
84370 #define G_CCIS3WCNT(x) (((x) >> S_CCIS3WCNT) & M_CCIS3WCNT)
84371 
84372 #define S_CCIS3AWCNT    0
84373 #define M_CCIS3AWCNT    0xffU
84374 #define V_CCIS3AWCNT(x) ((x) << S_CCIS3AWCNT)
84375 #define G_CCIS3AWCNT(x) (((x) >> S_CCIS3AWCNT) & M_CCIS3AWCNT)
84376 
84377 #define A_ARM_CCI_TR_DEBUGS4 0x47330
84378 
84379 #define S_CCIS4RCNT    24
84380 #define M_CCIS4RCNT    0xffU
84381 #define V_CCIS4RCNT(x) ((x) << S_CCIS4RCNT)
84382 #define G_CCIS4RCNT(x) (((x) >> S_CCIS4RCNT) & M_CCIS4RCNT)
84383 
84384 #define S_CCIS4ARCNT    16
84385 #define M_CCIS4ARCNT    0xffU
84386 #define V_CCIS4ARCNT(x) ((x) << S_CCIS4ARCNT)
84387 #define G_CCIS4ARCNT(x) (((x) >> S_CCIS4ARCNT) & M_CCIS4ARCNT)
84388 
84389 #define S_CCIS4WCNT    8
84390 #define M_CCIS4WCNT    0xffU
84391 #define V_CCIS4WCNT(x) ((x) << S_CCIS4WCNT)
84392 #define G_CCIS4WCNT(x) (((x) >> S_CCIS4WCNT) & M_CCIS4WCNT)
84393 
84394 #define S_CCIS4AWCNT    0
84395 #define M_CCIS4AWCNT    0xffU
84396 #define V_CCIS4AWCNT(x) ((x) << S_CCIS4AWCNT)
84397 #define G_CCIS4AWCNT(x) (((x) >> S_CCIS4AWCNT) & M_CCIS4AWCNT)
84398 
84399 #define A_ARM_CCI_TR_DEBUGS34 0x47334
84400 
84401 #define S_CCIS4RSPCNT    24
84402 #define M_CCIS4RSPCNT    0xffU
84403 #define V_CCIS4RSPCNT(x) ((x) << S_CCIS4RSPCNT)
84404 #define G_CCIS4RSPCNT(x) (((x) >> S_CCIS4RSPCNT) & M_CCIS4RSPCNT)
84405 
84406 #define S_CCIS4ACCNT    16
84407 #define M_CCIS4ACCNT    0xffU
84408 #define V_CCIS4ACCNT(x) ((x) << S_CCIS4ACCNT)
84409 #define G_CCIS4ACCNT(x) (((x) >> S_CCIS4ACCNT) & M_CCIS4ACCNT)
84410 
84411 #define S_CCIS3RSPCNT    8
84412 #define M_CCIS3RSPCNT    0xffU
84413 #define V_CCIS3RSPCNT(x) ((x) << S_CCIS3RSPCNT)
84414 #define G_CCIS3RSPCNT(x) (((x) >> S_CCIS3RSPCNT) & M_CCIS3RSPCNT)
84415 
84416 #define S_CCIS3ACCNT    0
84417 #define M_CCIS3ACCNT    0xffU
84418 #define V_CCIS3ACCNT(x) ((x) << S_CCIS3ACCNT)
84419 #define G_CCIS3ACCNT(x) (((x) >> S_CCIS3ACCNT) & M_CCIS3ACCNT)
84420 
84421 #define A_ARM_CCI_TR_DEBUGM0 0x47338
84422 
84423 #define S_CCIM0RCNT    24
84424 #define M_CCIM0RCNT    0xffU
84425 #define V_CCIM0RCNT(x) ((x) << S_CCIM0RCNT)
84426 #define G_CCIM0RCNT(x) (((x) >> S_CCIM0RCNT) & M_CCIM0RCNT)
84427 
84428 #define S_CCIM0ARCNT    16
84429 #define M_CCIM0ARCNT    0xffU
84430 #define V_CCIM0ARCNT(x) ((x) << S_CCIM0ARCNT)
84431 #define G_CCIM0ARCNT(x) (((x) >> S_CCIM0ARCNT) & M_CCIM0ARCNT)
84432 
84433 #define S_CCIM0WCNT    8
84434 #define M_CCIM0WCNT    0xffU
84435 #define V_CCIM0WCNT(x) ((x) << S_CCIM0WCNT)
84436 #define G_CCIM0WCNT(x) (((x) >> S_CCIM0WCNT) & M_CCIM0WCNT)
84437 
84438 #define S_CCIM0AWCNT    0
84439 #define M_CCIM0AWCNT    0xffU
84440 #define V_CCIM0AWCNT(x) ((x) << S_CCIM0AWCNT)
84441 #define G_CCIM0AWCNT(x) (((x) >> S_CCIM0AWCNT) & M_CCIM0AWCNT)
84442 
84443 #define A_ARM_CCI_TR_DEBUGM1 0x4733c
84444 
84445 #define S_CCIM1RCNT    24
84446 #define M_CCIM1RCNT    0xffU
84447 #define V_CCIM1RCNT(x) ((x) << S_CCIM1RCNT)
84448 #define G_CCIM1RCNT(x) (((x) >> S_CCIM1RCNT) & M_CCIM1RCNT)
84449 
84450 #define S_CCIM1ARCNT    16
84451 #define M_CCIM1ARCNT    0xffU
84452 #define V_CCIM1ARCNT(x) ((x) << S_CCIM1ARCNT)
84453 #define G_CCIM1ARCNT(x) (((x) >> S_CCIM1ARCNT) & M_CCIM1ARCNT)
84454 
84455 #define S_CCIM1WCNT    8
84456 #define M_CCIM1WCNT    0xffU
84457 #define V_CCIM1WCNT(x) ((x) << S_CCIM1WCNT)
84458 #define G_CCIM1WCNT(x) (((x) >> S_CCIM1WCNT) & M_CCIM1WCNT)
84459 
84460 #define S_CCIM1AWCNT    0
84461 #define M_CCIM1AWCNT    0xffU
84462 #define V_CCIM1AWCNT(x) ((x) << S_CCIM1AWCNT)
84463 #define G_CCIM1AWCNT(x) (((x) >> S_CCIM1AWCNT) & M_CCIM1AWCNT)
84464 
84465 #define A_ARM_CCI_TR_DEBUGM2 0x47340
84466 
84467 #define S_CCIM2RCNT    24
84468 #define M_CCIM2RCNT    0xffU
84469 #define V_CCIM2RCNT(x) ((x) << S_CCIM2RCNT)
84470 #define G_CCIM2RCNT(x) (((x) >> S_CCIM2RCNT) & M_CCIM2RCNT)
84471 
84472 #define S_CCIM2ARCNT    16
84473 #define M_CCIM2ARCNT    0xffU
84474 #define V_CCIM2ARCNT(x) ((x) << S_CCIM2ARCNT)
84475 #define G_CCIM2ARCNT(x) (((x) >> S_CCIM2ARCNT) & M_CCIM2ARCNT)
84476 
84477 #define S_CCIM2WCNT    8
84478 #define M_CCIM2WCNT    0xffU
84479 #define V_CCIM2WCNT(x) ((x) << S_CCIM2WCNT)
84480 #define G_CCIM2WCNT(x) (((x) >> S_CCIM2WCNT) & M_CCIM2WCNT)
84481 
84482 #define S_CCIM2AWCNT    0
84483 #define M_CCIM2AWCNT    0xffU
84484 #define V_CCIM2AWCNT(x) ((x) << S_CCIM2AWCNT)
84485 #define G_CCIM2AWCNT(x) (((x) >> S_CCIM2AWCNT) & M_CCIM2AWCNT)
84486 
84487 #define A_ARM_MA_TR_DEBUG 0x47344
84488 
84489 #define S_MA1_RD_CNT    24
84490 #define M_MA1_RD_CNT    0xffU
84491 #define V_MA1_RD_CNT(x) ((x) << S_MA1_RD_CNT)
84492 #define G_MA1_RD_CNT(x) (((x) >> S_MA1_RD_CNT) & M_MA1_RD_CNT)
84493 
84494 #define S_MA1_WR_CNT    16
84495 #define M_MA1_WR_CNT    0xffU
84496 #define V_MA1_WR_CNT(x) ((x) << S_MA1_WR_CNT)
84497 #define G_MA1_WR_CNT(x) (((x) >> S_MA1_WR_CNT) & M_MA1_WR_CNT)
84498 
84499 #define S_MA0_RD_CNT    8
84500 #define M_MA0_RD_CNT    0xffU
84501 #define V_MA0_RD_CNT(x) ((x) << S_MA0_RD_CNT)
84502 #define G_MA0_RD_CNT(x) (((x) >> S_MA0_RD_CNT) & M_MA0_RD_CNT)
84503 
84504 #define S_MA0_WR_CNT    0
84505 #define M_MA0_WR_CNT    0xffU
84506 #define V_MA0_WR_CNT(x) ((x) << S_MA0_WR_CNT)
84507 #define G_MA0_WR_CNT(x) (((x) >> S_MA0_WR_CNT) & M_MA0_WR_CNT)
84508 
84509 #define A_ARM_GP_INT 0x47348
84510 
84511 #define S_GP_INT    0
84512 #define M_GP_INT    0xffU
84513 #define V_GP_INT(x) ((x) << S_GP_INT)
84514 #define G_GP_INT(x) (((x) >> S_GP_INT) & M_GP_INT)
84515 
84516 #define A_ARM_DMA_CFG0 0x47350
84517 #define A_ARM_DMA_CFG1 0x47354
84518 
84519 #define S_DMABOOTPERIPHNS    16
84520 #define M_DMABOOTPERIPHNS    0x3ffU
84521 #define V_DMABOOTPERIPHNS(x) ((x) << S_DMABOOTPERIPHNS)
84522 #define G_DMABOOTPERIPHNS(x) (((x) >> S_DMABOOTPERIPHNS) & M_DMABOOTPERIPHNS)
84523 
84524 #define S_DMABOOTIRQNS    4
84525 #define M_DMABOOTIRQNS    0x3ffU
84526 #define V_DMABOOTIRQNS(x) ((x) << S_DMABOOTIRQNS)
84527 #define G_DMABOOTIRQNS(x) (((x) >> S_DMABOOTIRQNS) & M_DMABOOTIRQNS)
84528 
84529 #define S_DMABOOTMANAGERNS    1
84530 #define V_DMABOOTMANAGERNS(x) ((x) << S_DMABOOTMANAGERNS)
84531 #define F_DMABOOTMANAGERNS    V_DMABOOTMANAGERNS(1U)
84532 
84533 #define S_DMABOOTFROMPC    0
84534 #define V_DMABOOTFROMPC(x) ((x) << S_DMABOOTFROMPC)
84535 #define F_DMABOOTFROMPC    V_DMABOOTFROMPC(1U)
84536 
84537 #define A_ARM_ARM_CFG0 0x47380
84538 
84539 #define S_MESSAGEBYPASS_DATA    2
84540 #define V_MESSAGEBYPASS_DATA(x) ((x) << S_MESSAGEBYPASS_DATA)
84541 #define F_MESSAGEBYPASS_DATA    V_MESSAGEBYPASS_DATA(1U)
84542 
84543 #define S_MESSAGEBYPASS    1
84544 #define V_MESSAGEBYPASS(x) ((x) << S_MESSAGEBYPASS)
84545 #define F_MESSAGEBYPASS    V_MESSAGEBYPASS(1U)
84546 
84547 #define S_PCIEBYPASS    0
84548 #define V_PCIEBYPASS(x) ((x) << S_PCIEBYPASS)
84549 #define F_PCIEBYPASS    V_PCIEBYPASS(1U)
84550 
84551 #define A_ARM_ARM_CFG1 0x47384
84552 #define A_ARM_ARM_CFG2 0x47390
84553 #define A_ARM_PCIE_MA_ADDR_REGION0 0x47400
84554 
84555 #define S_ADDRREG0    0
84556 #define M_ADDRREG0    0xfffffffU
84557 #define V_ADDRREG0(x) ((x) << S_ADDRREG0)
84558 #define G_ADDRREG0(x) (((x) >> S_ADDRREG0) & M_ADDRREG0)
84559 
84560 #define A_ARM_PCIE_MA_ADDR_REGION1 0x47404
84561 
84562 #define S_ADDRREG1    0
84563 #define M_ADDRREG1    0xfffffffU
84564 #define V_ADDRREG1(x) ((x) << S_ADDRREG1)
84565 #define G_ADDRREG1(x) (((x) >> S_ADDRREG1) & M_ADDRREG1)
84566 
84567 #define A_ARM_PCIE_MA_ADDR_REGION2 0x47408
84568 
84569 #define S_ADDRREG2    0
84570 #define M_ADDRREG2    0xfffffffU
84571 #define V_ADDRREG2(x) ((x) << S_ADDRREG2)
84572 #define G_ADDRREG2(x) (((x) >> S_ADDRREG2) & M_ADDRREG2)
84573 
84574 #define A_ARM_PCIE_MA_ADDR_REGION3 0x4740c
84575 
84576 #define S_ADDRREG3    0
84577 #define M_ADDRREG3    0xfffffffU
84578 #define V_ADDRREG3(x) ((x) << S_ADDRREG3)
84579 #define G_ADDRREG3(x) (((x) >> S_ADDRREG3) & M_ADDRREG3)
84580 
84581 #define A_ARM_PCIE_MA_ADDR_REGION4 0x47410
84582 
84583 #define S_ADDRREG4    0
84584 #define M_ADDRREG4    0xfffffffU
84585 #define V_ADDRREG4(x) ((x) << S_ADDRREG4)
84586 #define G_ADDRREG4(x) (((x) >> S_ADDRREG4) & M_ADDRREG4)
84587 
84588 #define A_ARM_PCIE_MA_ADDR_REGION5 0x47414
84589 
84590 #define S_ADDRREG5    0
84591 #define M_ADDRREG5    0xfffffffU
84592 #define V_ADDRREG5(x) ((x) << S_ADDRREG5)
84593 #define G_ADDRREG5(x) (((x) >> S_ADDRREG5) & M_ADDRREG5)
84594 
84595 #define A_ARM_PCIE_MA_ADDR_REGION6 0x47418
84596 
84597 #define S_ADDRREG6    0
84598 #define M_ADDRREG6    0xfffffffU
84599 #define V_ADDRREG6(x) ((x) << S_ADDRREG6)
84600 #define G_ADDRREG6(x) (((x) >> S_ADDRREG6) & M_ADDRREG6)
84601 
84602 #define A_ARM_PCIE_MA_ADDR_REGION7 0x4741c
84603 
84604 #define S_ADDRREG7    0
84605 #define M_ADDRREG7    0xfffffffU
84606 #define V_ADDRREG7(x) ((x) << S_ADDRREG7)
84607 #define G_ADDRREG7(x) (((x) >> S_ADDRREG7) & M_ADDRREG7)
84608 
84609 #define A_ARM_INTERRUPT_GEN 0x47420
84610 
84611 #define S_INT_GEN    0
84612 #define M_INT_GEN    0x3U
84613 #define V_INT_GEN(x) ((x) << S_INT_GEN)
84614 #define G_INT_GEN(x) (((x) >> S_INT_GEN) & M_INT_GEN)
84615 
84616 #define A_ARM_INTERRUPT_CLEAR 0x47424
84617 
84618 #define S_INT_CLEAR    0
84619 #define M_INT_CLEAR    0x3U
84620 #define V_INT_CLEAR(x) ((x) << S_INT_CLEAR)
84621 #define G_INT_CLEAR(x) (((x) >> S_INT_CLEAR) & M_INT_CLEAR)
84622 
84623 #define A_ARM_DEBUG_STATUS_0 0x47428
84624 #define A_ARM_DBPROC_CONTROL 0x4742c
84625 
84626 #define S_NO_OF_INTERRUPTS    0
84627 #define M_NO_OF_INTERRUPTS    0x3U
84628 #define V_NO_OF_INTERRUPTS(x) ((x) << S_NO_OF_INTERRUPTS)
84629 #define G_NO_OF_INTERRUPTS(x) (((x) >> S_NO_OF_INTERRUPTS) & M_NO_OF_INTERRUPTS)
84630 
84631 #define A_ARM_PERR_INT_CAUSE1 0x47430
84632 
84633 #define S_ARWFIFO0_PERR    31
84634 #define V_ARWFIFO0_PERR(x) ((x) << S_ARWFIFO0_PERR)
84635 #define F_ARWFIFO0_PERR    V_ARWFIFO0_PERR(1U)
84636 
84637 #define S_ARWFIFO1_PERR    30
84638 #define V_ARWFIFO1_PERR(x) ((x) << S_ARWFIFO1_PERR)
84639 #define F_ARWFIFO1_PERR    V_ARWFIFO1_PERR(1U)
84640 
84641 #define S_ARWIDFIFO0_PERR    29
84642 #define V_ARWIDFIFO0_PERR(x) ((x) << S_ARWIDFIFO0_PERR)
84643 #define F_ARWIDFIFO0_PERR    V_ARWIDFIFO0_PERR(1U)
84644 
84645 #define S_ARWIDFIFO1_PERR    28
84646 #define V_ARWIDFIFO1_PERR(x) ((x) << S_ARWIDFIFO1_PERR)
84647 #define F_ARWIDFIFO1_PERR    V_ARWIDFIFO1_PERR(1U)
84648 
84649 #define S_ARIDFIFO0_PERR    27
84650 #define V_ARIDFIFO0_PERR(x) ((x) << S_ARIDFIFO0_PERR)
84651 #define F_ARIDFIFO0_PERR    V_ARIDFIFO0_PERR(1U)
84652 
84653 #define S_ARIDFIFO1_PERR    26
84654 #define V_ARIDFIFO1_PERR(x) ((x) << S_ARIDFIFO1_PERR)
84655 #define F_ARIDFIFO1_PERR    V_ARIDFIFO1_PERR(1U)
84656 
84657 #define S_RRSPADDR_FIFO0_PERR    25
84658 #define V_RRSPADDR_FIFO0_PERR(x) ((x) << S_RRSPADDR_FIFO0_PERR)
84659 #define F_RRSPADDR_FIFO0_PERR    V_RRSPADDR_FIFO0_PERR(1U)
84660 
84661 #define S_RRSPADDR_FIFO1_PERR    24
84662 #define V_RRSPADDR_FIFO1_PERR(x) ((x) << S_RRSPADDR_FIFO1_PERR)
84663 #define F_RRSPADDR_FIFO1_PERR    V_RRSPADDR_FIFO1_PERR(1U)
84664 
84665 #define S_WRSTRB_FIFO0_PERR    23
84666 #define V_WRSTRB_FIFO0_PERR(x) ((x) << S_WRSTRB_FIFO0_PERR)
84667 #define F_WRSTRB_FIFO0_PERR    V_WRSTRB_FIFO0_PERR(1U)
84668 
84669 #define S_WRSTRB_FIFO1_PERR    22
84670 #define V_WRSTRB_FIFO1_PERR(x) ((x) << S_WRSTRB_FIFO1_PERR)
84671 #define F_WRSTRB_FIFO1_PERR    V_WRSTRB_FIFO1_PERR(1U)
84672 
84673 #define S_MA2AXI_RSPDATAPARERR    21
84674 #define V_MA2AXI_RSPDATAPARERR(x) ((x) << S_MA2AXI_RSPDATAPARERR)
84675 #define F_MA2AXI_RSPDATAPARERR    V_MA2AXI_RSPDATAPARERR(1U)
84676 
84677 #define S_MA2AXI_DATA_PAR_ERR    20
84678 #define V_MA2AXI_DATA_PAR_ERR(x) ((x) << S_MA2AXI_DATA_PAR_ERR)
84679 #define F_MA2AXI_DATA_PAR_ERR    V_MA2AXI_DATA_PAR_ERR(1U)
84680 
84681 #define S_MA2AXI_WR_ORD_FIFO_PARERR    19
84682 #define V_MA2AXI_WR_ORD_FIFO_PARERR(x) ((x) << S_MA2AXI_WR_ORD_FIFO_PARERR)
84683 #define F_MA2AXI_WR_ORD_FIFO_PARERR    V_MA2AXI_WR_ORD_FIFO_PARERR(1U)
84684 
84685 #define S_NVME_DB_EMU_TRACKER_FIFO_PERR    18
84686 #define V_NVME_DB_EMU_TRACKER_FIFO_PERR(x) ((x) << S_NVME_DB_EMU_TRACKER_FIFO_PERR)
84687 #define F_NVME_DB_EMU_TRACKER_FIFO_PERR    V_NVME_DB_EMU_TRACKER_FIFO_PERR(1U)
84688 
84689 #define S_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR    17
84690 #define V_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR(x) ((x) << S_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR)
84691 #define F_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR    V_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR(1U)
84692 
84693 #define S_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR    16
84694 #define V_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR(x) ((x) << S_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR)
84695 #define F_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR    V_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR(1U)
84696 
84697 #define S_NVME_DB_EMU_ID_FIFO0_PERR    15
84698 #define V_NVME_DB_EMU_ID_FIFO0_PERR(x) ((x) << S_NVME_DB_EMU_ID_FIFO0_PERR)
84699 #define F_NVME_DB_EMU_ID_FIFO0_PERR    V_NVME_DB_EMU_ID_FIFO0_PERR(1U)
84700 
84701 #define S_NVME_DB_EMU_ID_FIFO1_PERR    14
84702 #define V_NVME_DB_EMU_ID_FIFO1_PERR(x) ((x) << S_NVME_DB_EMU_ID_FIFO1_PERR)
84703 #define F_NVME_DB_EMU_ID_FIFO1_PERR    V_NVME_DB_EMU_ID_FIFO1_PERR(1U)
84704 
84705 #define S_RC_ARWFIFO_PERR    13
84706 #define V_RC_ARWFIFO_PERR(x) ((x) << S_RC_ARWFIFO_PERR)
84707 #define F_RC_ARWFIFO_PERR    V_RC_ARWFIFO_PERR(1U)
84708 
84709 #define S_RC_ARIDBURSTADDRFIFO_PERR    12
84710 #define V_RC_ARIDBURSTADDRFIFO_PERR(x) ((x) << S_RC_ARIDBURSTADDRFIFO_PERR)
84711 #define F_RC_ARIDBURSTADDRFIFO_PERR    V_RC_ARIDBURSTADDRFIFO_PERR(1U)
84712 
84713 #define S_RC_CFG_FIFO_PERR    11
84714 #define V_RC_CFG_FIFO_PERR(x) ((x) << S_RC_CFG_FIFO_PERR)
84715 #define F_RC_CFG_FIFO_PERR    V_RC_CFG_FIFO_PERR(1U)
84716 
84717 #define S_RC_RSPFIFO_PERR    10
84718 #define V_RC_RSPFIFO_PERR(x) ((x) << S_RC_RSPFIFO_PERR)
84719 #define F_RC_RSPFIFO_PERR    V_RC_RSPFIFO_PERR(1U)
84720 
84721 #define S_INIC_ARIDFIFO_PERR    9
84722 #define V_INIC_ARIDFIFO_PERR(x) ((x) << S_INIC_ARIDFIFO_PERR)
84723 #define F_INIC_ARIDFIFO_PERR    V_INIC_ARIDFIFO_PERR(1U)
84724 
84725 #define S_INIC_ARWFIFO_PERR    8
84726 #define V_INIC_ARWFIFO_PERR(x) ((x) << S_INIC_ARWFIFO_PERR)
84727 #define F_INIC_ARWFIFO_PERR    V_INIC_ARWFIFO_PERR(1U)
84728 
84729 #define S_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR    7
84730 #define V_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR(x) ((x) << S_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR)
84731 #define F_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR    V_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR(1U)
84732 
84733 #define S_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR    6
84734 #define V_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR(x) ((x) << S_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR)
84735 #define F_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR    V_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR(1U)
84736 
84737 #define S_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR    5
84738 #define V_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR(x) ((x) << S_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR)
84739 #define F_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR    V_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR(1U)
84740 
84741 #define S_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR    4
84742 #define V_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR(x) ((x) << S_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR)
84743 #define F_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR    V_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR(1U)
84744 
84745 #define S_ARM_MA_512B_ARB_FIFO_PERR    3
84746 #define V_ARM_MA_512B_ARB_FIFO_PERR(x) ((x) << S_ARM_MA_512B_ARB_FIFO_PERR)
84747 #define F_ARM_MA_512B_ARB_FIFO_PERR    V_ARM_MA_512B_ARB_FIFO_PERR(1U)
84748 
84749 #define S_PCIE_INIC_MA_ARB_FIFO_PERR    2
84750 #define V_PCIE_INIC_MA_ARB_FIFO_PERR(x) ((x) << S_PCIE_INIC_MA_ARB_FIFO_PERR)
84751 #define F_PCIE_INIC_MA_ARB_FIFO_PERR    V_PCIE_INIC_MA_ARB_FIFO_PERR(1U)
84752 
84753 #define S_PCIE_INIC_ARB_RSPPERR    1
84754 #define V_PCIE_INIC_ARB_RSPPERR(x) ((x) << S_PCIE_INIC_ARB_RSPPERR)
84755 #define F_PCIE_INIC_ARB_RSPPERR    V_PCIE_INIC_ARB_RSPPERR(1U)
84756 
84757 #define S_ITE_CACHE_PERR    0
84758 #define V_ITE_CACHE_PERR(x) ((x) << S_ITE_CACHE_PERR)
84759 #define F_ITE_CACHE_PERR    V_ITE_CACHE_PERR(1U)
84760 
84761 #define A_ARM_PERR_INT_ENB1 0x47434
84762 #define A_ARM_PERR_ENABLE1 0x47438
84763 #define A_ARM_DEBUG_STATUS_1 0x4743c
84764 #define A_ARM_PCIE_MA_ADDR_REGION_DST 0x47440
84765 
84766 #define S_ADDRREGDST    0
84767 #define M_ADDRREGDST    0x1ffU
84768 #define V_ADDRREGDST(x) ((x) << S_ADDRREGDST)
84769 #define G_ADDRREGDST(x) (((x) >> S_ADDRREGDST) & M_ADDRREGDST)
84770 
84771 #define A_ARM_ERR_INT_CAUSE0 0x47444
84772 
84773 #define S_STRB0_ERROR    31
84774 #define V_STRB0_ERROR(x) ((x) << S_STRB0_ERROR)
84775 #define F_STRB0_ERROR    V_STRB0_ERROR(1U)
84776 
84777 #define S_STRB1_ERROR    30
84778 #define V_STRB1_ERROR(x) ((x) << S_STRB1_ERROR)
84779 #define F_STRB1_ERROR    V_STRB1_ERROR(1U)
84780 
84781 #define S_PCIE_INIC_MA_ARB_INV_RSP_TAG    29
84782 #define V_PCIE_INIC_MA_ARB_INV_RSP_TAG(x) ((x) << S_PCIE_INIC_MA_ARB_INV_RSP_TAG)
84783 #define F_PCIE_INIC_MA_ARB_INV_RSP_TAG    V_PCIE_INIC_MA_ARB_INV_RSP_TAG(1U)
84784 
84785 #define S_ERROR0_NOCMD_DATA    28
84786 #define V_ERROR0_NOCMD_DATA(x) ((x) << S_ERROR0_NOCMD_DATA)
84787 #define F_ERROR0_NOCMD_DATA    V_ERROR0_NOCMD_DATA(1U)
84788 
84789 #define S_ERROR1_NOCMD_DATA    27
84790 #define V_ERROR1_NOCMD_DATA(x) ((x) << S_ERROR1_NOCMD_DATA)
84791 #define F_ERROR1_NOCMD_DATA    V_ERROR1_NOCMD_DATA(1U)
84792 
84793 #define S_INIC_STRB_ERROR    26
84794 #define V_INIC_STRB_ERROR(x) ((x) << S_INIC_STRB_ERROR)
84795 #define F_INIC_STRB_ERROR    V_INIC_STRB_ERROR(1U)
84796 
84797 #define A_ARM_ERR_INT_ENB0 0x47448
84798 #define A_ARM_DEBUG_INDEX 0x47450
84799 #define A_ARM_DEBUG_DATA_HIGH 0x47454
84800 #define A_ARM_DEBUG_DATA_LOW 0x47458
84801 #define A_ARM_MSG_PCIE_MESSAGE2AXI_BA0 0x47500
84802 #define A_ARM_MSG_PCIE_MESSAGE2AXI_BA1 0x47504
84803 
84804 #define S_BASEADDRESS    0
84805 #define M_BASEADDRESS    0x3U
84806 #define V_BASEADDRESS(x) ((x) << S_BASEADDRESS)
84807 #define G_BASEADDRESS(x) (((x) >> S_BASEADDRESS) & M_BASEADDRESS)
84808 
84809 #define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG0 0x47508
84810 
84811 #define S_WATERMARK    16
84812 #define M_WATERMARK    0x3ffU
84813 #define V_WATERMARK(x) ((x) << S_WATERMARK)
84814 #define G_WATERMARK(x) (((x) >> S_WATERMARK) & M_WATERMARK)
84815 
84816 #define S_SIZEMAX    0
84817 #define M_SIZEMAX    0x3ffU
84818 #define V_SIZEMAX(x) ((x) << S_SIZEMAX)
84819 #define G_SIZEMAX(x) (((x) >> S_SIZEMAX) & M_SIZEMAX)
84820 
84821 #define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG1 0x4750c
84822 #define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG2 0x47510
84823 
84824 #define S_CPUREADADDRESS    0
84825 #define M_CPUREADADDRESS    0x3ffU
84826 #define V_CPUREADADDRESS(x) ((x) << S_CPUREADADDRESS)
84827 #define G_CPUREADADDRESS(x) (((x) >> S_CPUREADADDRESS) & M_CPUREADADDRESS)
84828 
84829 #define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG3 0x47514
84830 
84831 #define S_CPUREADADDRESSVLD    0
84832 #define V_CPUREADADDRESSVLD(x) ((x) << S_CPUREADADDRESSVLD)
84833 #define F_CPUREADADDRESSVLD    V_CPUREADADDRESSVLD(1U)
84834 
84835 #define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG4 0x47518
84836 #define A_ARM_APB2MSI_INTERRUPT_0_STATUS 0x47600
84837 #define A_ARM_APB2MSI_INTERRUPT_1_STATUS 0x47604
84838 #define A_ARM_APB2MSI_INTERRUPT_2_STATUS 0x47608
84839 #define A_ARM_APB2MSI_INTERRUPT_3_STATUS 0x4760c
84840 #define A_ARM_APB2MSI_INTERRUPT_0_ENABLE 0x47610
84841 #define A_ARM_APB2MSI_INTERRUPT_1_ENABLE 0x47614
84842 #define A_ARM_APB2MSI_INTERRUPT_2_ENABLE 0x47618
84843 #define A_ARM_APB2MSI_INTERRUPT_3_ENABLE 0x4761c
84844 #define A_ARM_APB2MSI_INTERRUPT_PRIORITY_LEVEL 0x47620
84845 
84846 #define S_ARM_APB2MSI_INT_PRIORITY_LEVEL    0
84847 #define M_ARM_APB2MSI_INT_PRIORITY_LEVEL    0x7U
84848 #define V_ARM_APB2MSI_INT_PRIORITY_LEVEL(x) ((x) << S_ARM_APB2MSI_INT_PRIORITY_LEVEL)
84849 #define G_ARM_APB2MSI_INT_PRIORITY_LEVEL(x) (((x) >> S_ARM_APB2MSI_INT_PRIORITY_LEVEL) & M_ARM_APB2MSI_INT_PRIORITY_LEVEL)
84850 
84851 #define A_ARM_APB2MSI_MEM_READ_ADDR 0x47624
84852 
84853 #define S_ARM_APB2MSI_MEM_READ_ADDR    0
84854 #define M_ARM_APB2MSI_MEM_READ_ADDR    0x7fU
84855 #define V_ARM_APB2MSI_MEM_READ_ADDR(x) ((x) << S_ARM_APB2MSI_MEM_READ_ADDR)
84856 #define G_ARM_APB2MSI_MEM_READ_ADDR(x) (((x) >> S_ARM_APB2MSI_MEM_READ_ADDR) & M_ARM_APB2MSI_MEM_READ_ADDR)
84857 
84858 #define A_ARM_MSI_MEMORY_DATA 0x47628
84859 #define A_ARM_MSI_MEMORY_ADDR 0x4762c
84860 #define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG5 0x47630
84861 
84862 #define S_CONFIGDONE    0
84863 #define V_CONFIGDONE(x) ((x) << S_CONFIGDONE)
84864 #define F_CONFIGDONE    V_CONFIGDONE(1U)
84865 
84866 #define A_ARM_AXI2MA_TIMERCNT 0x47640
84867 #define A_ARM_AXI2MA_TRTYPE 0x47644
84868 
84869 #define S_ARMMA2AXI1ARTRTYPE    3
84870 #define V_ARMMA2AXI1ARTRTYPE(x) ((x) << S_ARMMA2AXI1ARTRTYPE)
84871 #define F_ARMMA2AXI1ARTRTYPE    V_ARMMA2AXI1ARTRTYPE(1U)
84872 
84873 #define S_ARMMA2AXI1AWTRTYPE    2
84874 #define V_ARMMA2AXI1AWTRTYPE(x) ((x) << S_ARMMA2AXI1AWTRTYPE)
84875 #define F_ARMMA2AXI1AWTRTYPE    V_ARMMA2AXI1AWTRTYPE(1U)
84876 
84877 #define S_ARMMA2AXI0ARTRTYPE    1
84878 #define V_ARMMA2AXI0ARTRTYPE(x) ((x) << S_ARMMA2AXI0ARTRTYPE)
84879 #define F_ARMMA2AXI0ARTRTYPE    V_ARMMA2AXI0ARTRTYPE(1U)
84880 
84881 #define S_ARMMA2AXI0AWTRTYPE    0
84882 #define V_ARMMA2AXI0AWTRTYPE(x) ((x) << S_ARMMA2AXI0AWTRTYPE)
84883 #define F_ARMMA2AXI0AWTRTYPE    V_ARMMA2AXI0AWTRTYPE(1U)
84884 
84885 #define A_ARM_AXI2PCIE_VENDOR 0x47660
84886 
84887 #define S_T7_VENDORID    4
84888 #define M_T7_VENDORID    0xffffU
84889 #define V_T7_VENDORID(x) ((x) << S_T7_VENDORID)
84890 #define G_T7_VENDORID(x) (((x) >> S_T7_VENDORID) & M_T7_VENDORID)
84891 
84892 #define S_OBFFCODE    0
84893 #define M_OBFFCODE    0xfU
84894 #define V_OBFFCODE(x) ((x) << S_OBFFCODE)
84895 #define G_OBFFCODE(x) (((x) >> S_OBFFCODE) & M_OBFFCODE)
84896 
84897 #define A_ARM_AXI2PCIE_VENMSGHDR_DW3 0x47664
84898 #define A_ARM_CLUSTER_SEL 0x47668
84899 
84900 #define S_ARM_CLUSTER_SEL    0
84901 #define V_ARM_CLUSTER_SEL(x) ((x) << S_ARM_CLUSTER_SEL)
84902 #define F_ARM_CLUSTER_SEL    V_ARM_CLUSTER_SEL(1U)
84903 
84904 #define A_ARM_PWRREQ_PERMIT_ADB 0x4766c
84905 
84906 #define S_PWRQ_PERMIT_DENY_SAR    1
84907 #define V_PWRQ_PERMIT_DENY_SAR(x) ((x) << S_PWRQ_PERMIT_DENY_SAR)
84908 #define F_PWRQ_PERMIT_DENY_SAR    V_PWRQ_PERMIT_DENY_SAR(1U)
84909 
84910 #define S_PWRQREQNS_ADB    0
84911 #define V_PWRQREQNS_ADB(x) ((x) << S_PWRQREQNS_ADB)
84912 #define F_PWRQREQNS_ADB    V_PWRQREQNS_ADB(1U)
84913 
84914 #define A_ARM_CLK_REQ_ADB 0x47670
84915 
84916 #define S_CLKQREQNS_ADB    0
84917 #define V_CLKQREQNS_ADB(x) ((x) << S_CLKQREQNS_ADB)
84918 #define F_CLKQREQNS_ADB    V_CLKQREQNS_ADB(1U)
84919 
84920 #define A_ARM_WAKEUPM 0x47674
84921 
84922 #define S_DFTRSTDISABLEM_ADB    2
84923 #define V_DFTRSTDISABLEM_ADB(x) ((x) << S_DFTRSTDISABLEM_ADB)
84924 #define F_DFTRSTDISABLEM_ADB    V_DFTRSTDISABLEM_ADB(1U)
84925 
84926 #define S_DFTRSTDISABLES_ADB    1
84927 #define V_DFTRSTDISABLES_ADB(x) ((x) << S_DFTRSTDISABLES_ADB)
84928 #define F_DFTRSTDISABLES_ADB    V_DFTRSTDISABLES_ADB(1U)
84929 
84930 #define S_WAKEUPM_I_ADB    0
84931 #define V_WAKEUPM_I_ADB(x) ((x) << S_WAKEUPM_I_ADB)
84932 #define F_WAKEUPM_I_ADB    V_WAKEUPM_I_ADB(1U)
84933 
84934 #define A_ARM_CC_APB_FILTERING 0x47678
84935 
84936 #define S_CC_DFTSCANMODE    11
84937 #define V_CC_DFTSCANMODE(x) ((x) << S_CC_DFTSCANMODE)
84938 #define F_CC_DFTSCANMODE    V_CC_DFTSCANMODE(1U)
84939 
84940 #define S_CC_OTP_FILTERING_DISABLE    10
84941 #define V_CC_OTP_FILTERING_DISABLE(x) ((x) << S_CC_OTP_FILTERING_DISABLE)
84942 #define F_CC_OTP_FILTERING_DISABLE    V_CC_OTP_FILTERING_DISABLE(1U)
84943 
84944 #define S_CC_APB_FILTERING    0
84945 #define M_CC_APB_FILTERING    0x3ffU
84946 #define V_CC_APB_FILTERING(x) ((x) << S_CC_APB_FILTERING)
84947 #define G_CC_APB_FILTERING(x) (((x) >> S_CC_APB_FILTERING) & M_CC_APB_FILTERING)
84948 
84949 #define A_ARM_DCU_EN0 0x4767c
84950 #define A_ARM_DCU_EN1 0x47680
84951 #define A_ARM_DCU_EN2 0x47684
84952 #define A_ARM_DCU_EN3 0x47688
84953 #define A_ARM_DCU_LOCK0 0x4768c
84954 #define A_ARM_DCU_LOCK1 0x47690
84955 #define A_ARM_DCU_LOCK2 0x47694
84956 #define A_ARM_DCU_LOCK3 0x47698
84957 #define A_ARM_GPPC 0x4769c
84958 
84959 #define S_CC_SEC_DEBUG_RESET    24
84960 #define V_CC_SEC_DEBUG_RESET(x) ((x) << S_CC_SEC_DEBUG_RESET)
84961 #define F_CC_SEC_DEBUG_RESET    V_CC_SEC_DEBUG_RESET(1U)
84962 
84963 #define S_CC_DFTSE    23
84964 #define V_CC_DFTSE(x) ((x) << S_CC_DFTSE)
84965 #define F_CC_DFTSE    V_CC_DFTSE(1U)
84966 
84967 #define S_CC_DFTCGEN    22
84968 #define V_CC_DFTCGEN(x) ((x) << S_CC_DFTCGEN)
84969 #define F_CC_DFTCGEN    V_CC_DFTCGEN(1U)
84970 
84971 #define S_CC_DFTRAMHOLD    21
84972 #define V_CC_DFTRAMHOLD(x) ((x) << S_CC_DFTRAMHOLD)
84973 #define F_CC_DFTRAMHOLD    V_CC_DFTRAMHOLD(1U)
84974 
84975 #define S_CC_LOCK_BITS    12
84976 #define M_CC_LOCK_BITS    0x1ffU
84977 #define V_CC_LOCK_BITS(x) ((x) << S_CC_LOCK_BITS)
84978 #define G_CC_LOCK_BITS(x) (((x) >> S_CC_LOCK_BITS) & M_CC_LOCK_BITS)
84979 
84980 #define S_CC_LCS_IS_VALID    11
84981 #define V_CC_LCS_IS_VALID(x) ((x) << S_CC_LCS_IS_VALID)
84982 #define F_CC_LCS_IS_VALID    V_CC_LCS_IS_VALID(1U)
84983 
84984 #define S_CC_LCS    8
84985 #define M_CC_LCS    0x7U
84986 #define V_CC_LCS(x) ((x) << S_CC_LCS)
84987 #define G_CC_LCS(x) (((x) >> S_CC_LCS) & M_CC_LCS)
84988 
84989 #define S_CC_GPPC    0
84990 #define M_CC_GPPC    0xffU
84991 #define V_CC_GPPC(x) ((x) << S_CC_GPPC)
84992 #define G_CC_GPPC(x) (((x) >> S_CC_GPPC) & M_CC_GPPC)
84993 
84994 #define A_ARM_EMMC 0x47700
84995 
84996 #define S_EMMC_CARD_CLK_EN    31
84997 #define V_EMMC_CARD_CLK_EN(x) ((x) << S_EMMC_CARD_CLK_EN)
84998 #define F_EMMC_CARD_CLK_EN    V_EMMC_CARD_CLK_EN(1U)
84999 
85000 #define S_EMMC_LED_CONTROL    30
85001 #define V_EMMC_LED_CONTROL(x) ((x) << S_EMMC_LED_CONTROL)
85002 #define F_EMMC_LED_CONTROL    V_EMMC_LED_CONTROL(1U)
85003 
85004 #define S_EMMC_UHS1_SWVOLT_EN    29
85005 #define V_EMMC_UHS1_SWVOLT_EN(x) ((x) << S_EMMC_UHS1_SWVOLT_EN)
85006 #define F_EMMC_UHS1_SWVOLT_EN    V_EMMC_UHS1_SWVOLT_EN(1U)
85007 
85008 #define S_EMMC_UHS1_DRV_STH    27
85009 #define M_EMMC_UHS1_DRV_STH    0x3U
85010 #define V_EMMC_UHS1_DRV_STH(x) ((x) << S_EMMC_UHS1_DRV_STH)
85011 #define G_EMMC_UHS1_DRV_STH(x) (((x) >> S_EMMC_UHS1_DRV_STH) & M_EMMC_UHS1_DRV_STH)
85012 
85013 #define S_EMMC_SD_VDD1_ON    26
85014 #define V_EMMC_SD_VDD1_ON(x) ((x) << S_EMMC_SD_VDD1_ON)
85015 #define F_EMMC_SD_VDD1_ON    V_EMMC_SD_VDD1_ON(1U)
85016 
85017 #define S_EMMC_SD_VDD1_SEL    23
85018 #define M_EMMC_SD_VDD1_SEL    0x7U
85019 #define V_EMMC_SD_VDD1_SEL(x) ((x) << S_EMMC_SD_VDD1_SEL)
85020 #define G_EMMC_SD_VDD1_SEL(x) (((x) >> S_EMMC_SD_VDD1_SEL) & M_EMMC_SD_VDD1_SEL)
85021 
85022 #define S_EMMC_INTCLK_EN    22
85023 #define V_EMMC_INTCLK_EN(x) ((x) << S_EMMC_INTCLK_EN)
85024 #define F_EMMC_INTCLK_EN    V_EMMC_INTCLK_EN(1U)
85025 
85026 #define S_EMMC_CARD_CLK_FREQ_SEL    12
85027 #define M_EMMC_CARD_CLK_FREQ_SEL    0x3ffU
85028 #define V_EMMC_CARD_CLK_FREQ_SEL(x) ((x) << S_EMMC_CARD_CLK_FREQ_SEL)
85029 #define G_EMMC_CARD_CLK_FREQ_SEL(x) (((x) >> S_EMMC_CARD_CLK_FREQ_SEL) & M_EMMC_CARD_CLK_FREQ_SEL)
85030 
85031 #define S_EMMC_CARD_CLK_GEN_SEL    11
85032 #define V_EMMC_CARD_CLK_GEN_SEL(x) ((x) << S_EMMC_CARD_CLK_GEN_SEL)
85033 #define F_EMMC_CARD_CLK_GEN_SEL    V_EMMC_CARD_CLK_GEN_SEL(1U)
85034 
85035 #define S_EMMC_CLK2CARD_ON    10
85036 #define V_EMMC_CLK2CARD_ON(x) ((x) << S_EMMC_CLK2CARD_ON)
85037 #define F_EMMC_CLK2CARD_ON    V_EMMC_CLK2CARD_ON(1U)
85038 
85039 #define S_EMMC_CARD_CLK_STABLE    9
85040 #define V_EMMC_CARD_CLK_STABLE(x) ((x) << S_EMMC_CARD_CLK_STABLE)
85041 #define F_EMMC_CARD_CLK_STABLE    V_EMMC_CARD_CLK_STABLE(1U)
85042 
85043 #define S_EMMC_INT_BCLK_STABLE    8
85044 #define V_EMMC_INT_BCLK_STABLE(x) ((x) << S_EMMC_INT_BCLK_STABLE)
85045 #define F_EMMC_INT_BCLK_STABLE    V_EMMC_INT_BCLK_STABLE(1U)
85046 
85047 #define S_EMMC_INT_ACLK_STABLE    7
85048 #define V_EMMC_INT_ACLK_STABLE(x) ((x) << S_EMMC_INT_ACLK_STABLE)
85049 #define F_EMMC_INT_ACLK_STABLE    V_EMMC_INT_ACLK_STABLE(1U)
85050 
85051 #define S_EMMC_INT_TMCLK_STABLE    6
85052 #define V_EMMC_INT_TMCLK_STABLE(x) ((x) << S_EMMC_INT_TMCLK_STABLE)
85053 #define F_EMMC_INT_TMCLK_STABLE    V_EMMC_INT_TMCLK_STABLE(1U)
85054 
85055 #define S_EMMC_HOST_REG_VOL_STABLE    5
85056 #define V_EMMC_HOST_REG_VOL_STABLE(x) ((x) << S_EMMC_HOST_REG_VOL_STABLE)
85057 #define F_EMMC_HOST_REG_VOL_STABLE    V_EMMC_HOST_REG_VOL_STABLE(1U)
85058 
85059 #define S_EMMC_CARD_DETECT_N    4
85060 #define V_EMMC_CARD_DETECT_N(x) ((x) << S_EMMC_CARD_DETECT_N)
85061 #define F_EMMC_CARD_DETECT_N    V_EMMC_CARD_DETECT_N(1U)
85062 
85063 #define S_EMMC_CARD_WRITE_PROT    3
85064 #define V_EMMC_CARD_WRITE_PROT(x) ((x) << S_EMMC_CARD_WRITE_PROT)
85065 #define F_EMMC_CARD_WRITE_PROT    V_EMMC_CARD_WRITE_PROT(1U)
85066 
85067 #define S_EMMC_GP_IN    2
85068 #define V_EMMC_GP_IN(x) ((x) << S_EMMC_GP_IN)
85069 #define F_EMMC_GP_IN    V_EMMC_GP_IN(1U)
85070 
85071 #define S_EMMC_TEST_SCAN_MODE    1
85072 #define V_EMMC_TEST_SCAN_MODE(x) ((x) << S_EMMC_TEST_SCAN_MODE)
85073 #define F_EMMC_TEST_SCAN_MODE    V_EMMC_TEST_SCAN_MODE(1U)
85074 
85075 #define S_EMMC_FIFOINJDATAERR    0
85076 #define V_EMMC_FIFOINJDATAERR(x) ((x) << S_EMMC_FIFOINJDATAERR)
85077 #define F_EMMC_FIFOINJDATAERR    V_EMMC_FIFOINJDATAERR(1U)
85078 
85079 #define A_ARM_WAKEUPS 0x47704
85080 
85081 #define S_WAKEUPS_I_ADB    0
85082 #define V_WAKEUPS_I_ADB(x) ((x) << S_WAKEUPS_I_ADB)
85083 #define F_WAKEUPS_I_ADB    V_WAKEUPS_I_ADB(1U)
85084 
85085 #define A_ARM_CLKREQNM_ADB 0x47708
85086 
85087 #define S_CLKQREQNM_ADB    0
85088 #define V_CLKQREQNM_ADB(x) ((x) << S_CLKQREQNM_ADB)
85089 #define F_CLKQREQNM_ADB    V_CLKQREQNM_ADB(1U)
85090 
85091 #define A_ARM_ATOMICDATA0_0 0x4770c
85092 #define A_ARM_ATOMICDATA1_0 0x47710
85093 #define A_ARM_NVME_DB_EMU_INT_ENABLE 0x47740
85094 #define A_ARM_TCAM_WRITE_DATA 0x47744
85095 
85096 #define S_TCAM_WRITE_DATA    0
85097 #define M_TCAM_WRITE_DATA    0x3fffffffU
85098 #define V_TCAM_WRITE_DATA(x) ((x) << S_TCAM_WRITE_DATA)
85099 #define G_TCAM_WRITE_DATA(x) (((x) >> S_TCAM_WRITE_DATA) & M_TCAM_WRITE_DATA)
85100 
85101 #define A_ARM_TCAM_WRITE_ADDR 0x47748
85102 
85103 #define S_TCAM_WRITE_ADDR    0
85104 #define M_TCAM_WRITE_ADDR    0x1ffU
85105 #define V_TCAM_WRITE_ADDR(x) ((x) << S_TCAM_WRITE_ADDR)
85106 #define G_TCAM_WRITE_ADDR(x) (((x) >> S_TCAM_WRITE_ADDR) & M_TCAM_WRITE_ADDR)
85107 
85108 #define A_ARM_TCAM_READ_ADDR 0x4774c
85109 
85110 #define S_TCAM_READ_ADDR    0
85111 #define M_TCAM_READ_ADDR    0x1ffU
85112 #define V_TCAM_READ_ADDR(x) ((x) << S_TCAM_READ_ADDR)
85113 #define G_TCAM_READ_ADDR(x) (((x) >> S_TCAM_READ_ADDR) & M_TCAM_READ_ADDR)
85114 
85115 #define A_ARM_TCAM_CTL 0x47750
85116 
85117 #define S_TCAMCBBUSY    6
85118 #define V_TCAMCBBUSY(x) ((x) << S_TCAMCBBUSY)
85119 #define F_TCAMCBBUSY    V_TCAMCBBUSY(1U)
85120 
85121 #define S_TCAMCBPASS    5
85122 #define V_TCAMCBPASS(x) ((x) << S_TCAMCBPASS)
85123 #define F_TCAMCBPASS    V_TCAMCBPASS(1U)
85124 
85125 #define S_TCAMCBSTART    4
85126 #define V_TCAMCBSTART(x) ((x) << S_TCAMCBSTART)
85127 #define F_TCAMCBSTART    V_TCAMCBSTART(1U)
85128 
85129 #define S_TCAMRSTCB    3
85130 #define V_TCAMRSTCB(x) ((x) << S_TCAMRSTCB)
85131 #define F_TCAMRSTCB    V_TCAMRSTCB(1U)
85132 
85133 #define S_TCAM_REQBITPOS    2
85134 #define V_TCAM_REQBITPOS(x) ((x) << S_TCAM_REQBITPOS)
85135 #define F_TCAM_REQBITPOS    V_TCAM_REQBITPOS(1U)
85136 
85137 #define S_TCAM_WRITE    1
85138 #define V_TCAM_WRITE(x) ((x) << S_TCAM_WRITE)
85139 #define F_TCAM_WRITE    V_TCAM_WRITE(1U)
85140 
85141 #define S_TCAM_ENABLE    0
85142 #define V_TCAM_ENABLE(x) ((x) << S_TCAM_ENABLE)
85143 #define F_TCAM_ENABLE    V_TCAM_ENABLE(1U)
85144 
85145 #define A_ARM_TCAM_READ_DATA 0x4775c
85146 
85147 #define S_TCAM_READ_DATA    0
85148 #define M_TCAM_READ_DATA    0x3fffffffU
85149 #define V_TCAM_READ_DATA(x) ((x) << S_TCAM_READ_DATA)
85150 #define G_TCAM_READ_DATA(x) (((x) >> S_TCAM_READ_DATA) & M_TCAM_READ_DATA)
85151 
85152 #define A_ARM_SRAM1_WRITE_DATA 0x47760
85153 
85154 #define S_SRAM1_WRITE_DATA    0
85155 #define M_SRAM1_WRITE_DATA    0x7fffffU
85156 #define V_SRAM1_WRITE_DATA(x) ((x) << S_SRAM1_WRITE_DATA)
85157 #define G_SRAM1_WRITE_DATA(x) (((x) >> S_SRAM1_WRITE_DATA) & M_SRAM1_WRITE_DATA)
85158 
85159 #define A_ARM_SRAM1_WRITE_ADDR 0x47764
85160 
85161 #define S_SRAM1_WRITE_ADDR    0
85162 #define M_SRAM1_WRITE_ADDR    0x1ffU
85163 #define V_SRAM1_WRITE_ADDR(x) ((x) << S_SRAM1_WRITE_ADDR)
85164 #define G_SRAM1_WRITE_ADDR(x) (((x) >> S_SRAM1_WRITE_ADDR) & M_SRAM1_WRITE_ADDR)
85165 
85166 #define A_ARM_SRAM1_READ_ADDR 0x47768
85167 
85168 #define S_SRAM1_READ_ADDR    0
85169 #define M_SRAM1_READ_ADDR    0x1ffU
85170 #define V_SRAM1_READ_ADDR(x) ((x) << S_SRAM1_READ_ADDR)
85171 #define G_SRAM1_READ_ADDR(x) (((x) >> S_SRAM1_READ_ADDR) & M_SRAM1_READ_ADDR)
85172 
85173 #define A_ARM_SRAM1_CTL 0x4776c
85174 
85175 #define S_SRAM1_WRITE    1
85176 #define V_SRAM1_WRITE(x) ((x) << S_SRAM1_WRITE)
85177 #define F_SRAM1_WRITE    V_SRAM1_WRITE(1U)
85178 
85179 #define S_SRAM1_ENABLE    0
85180 #define V_SRAM1_ENABLE(x) ((x) << S_SRAM1_ENABLE)
85181 #define F_SRAM1_ENABLE    V_SRAM1_ENABLE(1U)
85182 
85183 #define A_ARM_SRAM1_READ_DATA 0x47770
85184 
85185 #define S_SRAM1_READ_DATA    0
85186 #define M_SRAM1_READ_DATA    0x7fffffU
85187 #define V_SRAM1_READ_DATA(x) ((x) << S_SRAM1_READ_DATA)
85188 #define G_SRAM1_READ_DATA(x) (((x) >> S_SRAM1_READ_DATA) & M_SRAM1_READ_DATA)
85189 
85190 #define A_ARM_SRAM2_WRITE_DATA0 0x47774
85191 #define A_ARM_SRAM2_WRITE_DATA1 0x47778
85192 #define A_ARM_SRAM2_WRITE_DATA2 0x4777c
85193 #define A_ARM_SRAM2_WRITE_ADDR 0x47780
85194 
85195 #define S_SRAM2_WRITE_ADDR    0
85196 #define M_SRAM2_WRITE_ADDR    0x1fffU
85197 #define V_SRAM2_WRITE_ADDR(x) ((x) << S_SRAM2_WRITE_ADDR)
85198 #define G_SRAM2_WRITE_ADDR(x) (((x) >> S_SRAM2_WRITE_ADDR) & M_SRAM2_WRITE_ADDR)
85199 
85200 #define A_ARM_SRAM2_READ_ADDR 0x47784
85201 
85202 #define S_SRAM2_READ_ADDR    0
85203 #define M_SRAM2_READ_ADDR    0x1fffU
85204 #define V_SRAM2_READ_ADDR(x) ((x) << S_SRAM2_READ_ADDR)
85205 #define G_SRAM2_READ_ADDR(x) (((x) >> S_SRAM2_READ_ADDR) & M_SRAM2_READ_ADDR)
85206 
85207 #define A_ARM_SRAM2_CTL 0x47788
85208 
85209 #define S_SRAM2_WRITE    1
85210 #define V_SRAM2_WRITE(x) ((x) << S_SRAM2_WRITE)
85211 #define F_SRAM2_WRITE    V_SRAM2_WRITE(1U)
85212 
85213 #define S_SRAM2_ENABLE    0
85214 #define V_SRAM2_ENABLE(x) ((x) << S_SRAM2_ENABLE)
85215 #define F_SRAM2_ENABLE    V_SRAM2_ENABLE(1U)
85216 
85217 #define A_ARM_SRAM2_READ_DATA0 0x4778c
85218 #define A_ARM_SRAM2_READ_DATA1 0x47790
85219 #define A_ARM_SRAM2_READ_DATA2 0x47794
85220 #define A_ARM_DBPROC_SRAM_CTL 0x47798
85221 
85222 #define S_DBPROC_RD_EN    0
85223 #define V_DBPROC_RD_EN(x) ((x) << S_DBPROC_RD_EN)
85224 #define F_DBPROC_RD_EN    V_DBPROC_RD_EN(1U)
85225 
85226 #define A_ARM_DBPROC_SRAM_READ_ADDR 0x4779c
85227 
85228 #define S_DBPROC_RD_ADDR    0
85229 #define M_DBPROC_RD_ADDR    0x1ffU
85230 #define V_DBPROC_RD_ADDR(x) ((x) << S_DBPROC_RD_ADDR)
85231 #define G_DBPROC_RD_ADDR(x) (((x) >> S_DBPROC_RD_ADDR) & M_DBPROC_RD_ADDR)
85232 
85233 #define A_ARM_DBPROC_SRAM_READ_DATA0 0x477a0
85234 #define A_ARM_DBPROC_SRAM_READ_DATA1 0x477a4
85235 #define A_ARM_DBPROC_SRAM_READ_DATA2 0x477a8
85236 #define A_ARM_DBPROC_SRAM_READ_DATA3 0x477ac
85237 #define A_ARM_ATOMICDATA0_1 0x477b0
85238 #define A_ARM_ATOMICDATA1_1 0x477b4
85239 #define A_ARM_SPIDEN 0x477b8
85240 
85241 #define S_SPIDEN    0
85242 #define V_SPIDEN(x) ((x) << S_SPIDEN)
85243 #define F_SPIDEN    V_SPIDEN(1U)
85244 
85245 #define A_ARM_RC_INT_WRITE_DATA 0x477bc
85246 
85247 #define S_RC_INT_STATUS_WRITE_DATA    0
85248 #define M_RC_INT_STATUS_WRITE_DATA    0x3fU
85249 #define V_RC_INT_STATUS_WRITE_DATA(x) ((x) << S_RC_INT_STATUS_WRITE_DATA)
85250 #define G_RC_INT_STATUS_WRITE_DATA(x) (((x) >> S_RC_INT_STATUS_WRITE_DATA) & M_RC_INT_STATUS_WRITE_DATA)
85251 
85252 #define A_ARM_DFT_MBI 0x477c4
85253 
85254 #define S_MBISTREQ    3
85255 #define V_MBISTREQ(x) ((x) << S_MBISTREQ)
85256 #define F_MBISTREQ    V_MBISTREQ(1U)
85257 
85258 #define S_MBISTRESETN    2
85259 #define V_MBISTRESETN(x) ((x) << S_MBISTRESETN)
85260 #define F_MBISTRESETN    V_MBISTRESETN(1U)
85261 
85262 #define S_DFTRAMHOLD    1
85263 #define V_DFTRAMHOLD(x) ((x) << S_DFTRAMHOLD)
85264 #define F_DFTRAMHOLD    V_DFTRAMHOLD(1U)
85265 
85266 #define S_DFTCGEN    0
85267 #define V_DFTCGEN(x) ((x) << S_DFTCGEN)
85268 #define F_DFTCGEN    V_DFTCGEN(1U)
85269 
85270 #define A_ARM_DBPROC_SRAM_TH_CTL 0x477c8
85271 
85272 #define S_DBPROC_TH_WR_EN    1
85273 #define V_DBPROC_TH_WR_EN(x) ((x) << S_DBPROC_TH_WR_EN)
85274 #define F_DBPROC_TH_WR_EN    V_DBPROC_TH_WR_EN(1U)
85275 
85276 #define S_DBPROC_TH_RD_EN    0
85277 #define V_DBPROC_TH_RD_EN(x) ((x) << S_DBPROC_TH_RD_EN)
85278 #define F_DBPROC_TH_RD_EN    V_DBPROC_TH_RD_EN(1U)
85279 
85280 #define A_ARM_MBISTACK 0x477d4
85281 
85282 #define S_MBISTACK    0
85283 #define V_MBISTACK(x) ((x) << S_MBISTACK)
85284 #define F_MBISTACK    V_MBISTACK(1U)
85285 
85286 #define A_ARM_MBISTADDR 0x477d8
85287 
85288 #define S_MBISTADDR    0
85289 #define M_MBISTADDR    0xfffU
85290 #define V_MBISTADDR(x) ((x) << S_MBISTADDR)
85291 #define G_MBISTADDR(x) (((x) >> S_MBISTADDR) & M_MBISTADDR)
85292 
85293 #define A_ARM_MBISTREADEN 0x477dc
85294 
85295 #define S_MBISTREADEN    0
85296 #define V_MBISTREADEN(x) ((x) << S_MBISTREADEN)
85297 #define F_MBISTREADEN    V_MBISTREADEN(1U)
85298 
85299 #define A_ARM_MBISTWRITEEN 0x477e0
85300 
85301 #define S_MBISTWRITEEN    0
85302 #define V_MBISTWRITEEN(x) ((x) << S_MBISTWRITEEN)
85303 #define F_MBISTWRITEEN    V_MBISTWRITEEN(1U)
85304 
85305 #define A_ARM_MBISTARRAY 0x477e4
85306 
85307 #define S_MBISTARRAY    0
85308 #define M_MBISTARRAY    0x3U
85309 #define V_MBISTARRAY(x) ((x) << S_MBISTARRAY)
85310 #define G_MBISTARRAY(x) (((x) >> S_MBISTARRAY) & M_MBISTARRAY)
85311 
85312 #define A_ARM_MBISTCFG 0x477e8
85313 
85314 #define S_MBISTCFG    0
85315 #define V_MBISTCFG(x) ((x) << S_MBISTCFG)
85316 #define F_MBISTCFG    V_MBISTCFG(1U)
85317 
85318 #define A_ARM_MBISTINDATA0 0x477ec
85319 #define A_ARM_MBISTINDATA1 0x477f0
85320 #define A_ARM_MBISTOUTDATA1 0x477f4
85321 #define A_ARM_MBISTOUTDATA0 0x477f8
85322 #define A_ARM_NVME_DB_EMU_EN 0x477fc
85323 
85324 #define S_NVME_DB_EN    0
85325 #define V_NVME_DB_EN(x) ((x) << S_NVME_DB_EN)
85326 #define F_NVME_DB_EN    V_NVME_DB_EN(1U)
85327 
85328 /* registers for module MC_T70 */
85329 #define MC_T70_BASE_ADDR 0x48000
85330 
85331 #define A_MC_IND_ADDR 0x48000
85332 
85333 #define S_T7_AUTOINCR    30
85334 #define M_T7_AUTOINCR    0x3U
85335 #define V_T7_AUTOINCR(x) ((x) << S_T7_AUTOINCR)
85336 #define G_T7_AUTOINCR(x) (((x) >> S_T7_AUTOINCR) & M_T7_AUTOINCR)
85337 
85338 #define S_IND_ADDR_ADDR    0
85339 #define M_IND_ADDR_ADDR    0x1ffffffU
85340 #define V_IND_ADDR_ADDR(x) ((x) << S_IND_ADDR_ADDR)
85341 #define G_IND_ADDR_ADDR(x) (((x) >> S_IND_ADDR_ADDR) & M_IND_ADDR_ADDR)
85342 
85343 #define A_MC_IND_DATA 0x48004
85344 #define A_MC_DBG_CTL 0x48018
85345 #define A_MC_DBG_DATA 0x4801c
85346 #define A_T7_MC_P_DDRPHY_RST_CTRL 0x49300
85347 #define A_T7_MC_P_PERFORMANCE_CTRL 0x49304
85348 #define A_T7_MC_P_ECC_CTRL 0x49308
85349 
85350 #define S_BISTECCHBWCTL    7
85351 #define M_BISTECCHBWCTL    0x3U
85352 #define V_BISTECCHBWCTL(x) ((x) << S_BISTECCHBWCTL)
85353 #define G_BISTECCHBWCTL(x) (((x) >> S_BISTECCHBWCTL) & M_BISTECCHBWCTL)
85354 
85355 #define S_BISTTESTMODE    6
85356 #define V_BISTTESTMODE(x) ((x) << S_BISTTESTMODE)
85357 #define F_BISTTESTMODE    V_BISTTESTMODE(1U)
85358 
85359 #define S_RMW_CTL_CFG    4
85360 #define M_RMW_CTL_CFG    0x3U
85361 #define V_RMW_CTL_CFG(x) ((x) << S_RMW_CTL_CFG)
85362 #define G_RMW_CTL_CFG(x) (((x) >> S_RMW_CTL_CFG) & M_RMW_CTL_CFG)
85363 
85364 #define A_MC_P_DDRCTL_INT_ENABLE 0x4930c
85365 
85366 #define S_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE    5
85367 #define V_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE(x) ((x) << S_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE)
85368 #define F_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE    V_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE(1U)
85369 
85370 #define S_HIF_RDATA_CRC_ERR_DCH1_ENABLE    4
85371 #define V_HIF_RDATA_CRC_ERR_DCH1_ENABLE(x) ((x) << S_HIF_RDATA_CRC_ERR_DCH1_ENABLE)
85372 #define F_HIF_RDATA_CRC_ERR_DCH1_ENABLE    V_HIF_RDATA_CRC_ERR_DCH1_ENABLE(1U)
85373 
85374 #define S_HIF_RDATA_ADDR_ERR_DCH1_ENABLE    3
85375 #define V_HIF_RDATA_ADDR_ERR_DCH1_ENABLE(x) ((x) << S_HIF_RDATA_ADDR_ERR_DCH1_ENABLE)
85376 #define F_HIF_RDATA_ADDR_ERR_DCH1_ENABLE    V_HIF_RDATA_ADDR_ERR_DCH1_ENABLE(1U)
85377 
85378 #define S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE    2
85379 #define V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE(x) ((x) << S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE)
85380 #define F_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE    V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE(1U)
85381 
85382 #define S_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE    1
85383 #define V_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE(x) ((x) << S_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE)
85384 #define F_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE    V_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE(1U)
85385 
85386 #define S_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE    0
85387 #define V_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE(x) ((x) << S_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE)
85388 #define F_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE    V_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE(1U)
85389 
85390 #define A_MC_P_DDRCTL_INT_CAUSE 0x49310
85391 
85392 #define S_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE    25
85393 #define V_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE(x) ((x) << S_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE)
85394 #define F_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE    V_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE(1U)
85395 
85396 #define S_WR_CRC_ERR_INTR_DCH1_CAUSE    24
85397 #define V_WR_CRC_ERR_INTR_DCH1_CAUSE(x) ((x) << S_WR_CRC_ERR_INTR_DCH1_CAUSE)
85398 #define F_WR_CRC_ERR_INTR_DCH1_CAUSE    V_WR_CRC_ERR_INTR_DCH1_CAUSE(1U)
85399 
85400 #define S_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE    23
85401 #define V_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE(x) ((x) << S_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE)
85402 #define F_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE    V_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE(1U)
85403 
85404 #define S_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE    22
85405 #define V_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE(x) ((x) << S_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE)
85406 #define F_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE    V_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE(1U)
85407 
85408 #define S_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE    21
85409 #define V_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE(x) ((x) << S_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE)
85410 #define F_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE    V_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE(1U)
85411 
85412 #define S_SWCMD_ERR_INTR_DCH1_CAUSE    20
85413 #define V_SWCMD_ERR_INTR_DCH1_CAUSE(x) ((x) << S_SWCMD_ERR_INTR_DCH1_CAUSE)
85414 #define F_SWCMD_ERR_INTR_DCH1_CAUSE    V_SWCMD_ERR_INTR_DCH1_CAUSE(1U)
85415 
85416 #define S_DUCMD_ERR_INTR_DCH1_CAUSE    19
85417 #define V_DUCMD_ERR_INTR_DCH1_CAUSE(x) ((x) << S_DUCMD_ERR_INTR_DCH1_CAUSE)
85418 #define F_DUCMD_ERR_INTR_DCH1_CAUSE    V_DUCMD_ERR_INTR_DCH1_CAUSE(1U)
85419 
85420 #define S_LCCMD_ERR_INTR_DCH1_CAUSE    18
85421 #define V_LCCMD_ERR_INTR_DCH1_CAUSE(x) ((x) << S_LCCMD_ERR_INTR_DCH1_CAUSE)
85422 #define F_LCCMD_ERR_INTR_DCH1_CAUSE    V_LCCMD_ERR_INTR_DCH1_CAUSE(1U)
85423 
85424 #define S_CTRLUPD_ERR_INTR_DCH1_CAUSE    17
85425 #define V_CTRLUPD_ERR_INTR_DCH1_CAUSE(x) ((x) << S_CTRLUPD_ERR_INTR_DCH1_CAUSE)
85426 #define F_CTRLUPD_ERR_INTR_DCH1_CAUSE    V_CTRLUPD_ERR_INTR_DCH1_CAUSE(1U)
85427 
85428 #define S_RFM_ALERT_INTR_DCH1_CAUSE    16
85429 #define V_RFM_ALERT_INTR_DCH1_CAUSE(x) ((x) << S_RFM_ALERT_INTR_DCH1_CAUSE)
85430 #define F_RFM_ALERT_INTR_DCH1_CAUSE    V_RFM_ALERT_INTR_DCH1_CAUSE(1U)
85431 
85432 #define S_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE    15
85433 #define V_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE(x) ((x) << S_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE)
85434 #define F_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE    V_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE(1U)
85435 
85436 #define S_WR_CRC_ERR_INTR_DCH0_CAUSE    14
85437 #define V_WR_CRC_ERR_INTR_DCH0_CAUSE(x) ((x) << S_WR_CRC_ERR_INTR_DCH0_CAUSE)
85438 #define F_WR_CRC_ERR_INTR_DCH0_CAUSE    V_WR_CRC_ERR_INTR_DCH0_CAUSE(1U)
85439 
85440 #define S_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE    13
85441 #define V_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE(x) ((x) << S_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE)
85442 #define F_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE    V_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE(1U)
85443 
85444 #define S_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE    12
85445 #define V_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE(x) ((x) << S_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE)
85446 #define F_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE    V_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE(1U)
85447 
85448 #define S_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE    11
85449 #define V_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE(x) ((x) << S_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE)
85450 #define F_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE    V_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE(1U)
85451 
85452 #define S_SWCMD_ERR_INTR_DCH0_CAUSE    10
85453 #define V_SWCMD_ERR_INTR_DCH0_CAUSE(x) ((x) << S_SWCMD_ERR_INTR_DCH0_CAUSE)
85454 #define F_SWCMD_ERR_INTR_DCH0_CAUSE    V_SWCMD_ERR_INTR_DCH0_CAUSE(1U)
85455 
85456 #define S_DUCMD_ERR_INTR_DCH0_CAUSE    9
85457 #define V_DUCMD_ERR_INTR_DCH0_CAUSE(x) ((x) << S_DUCMD_ERR_INTR_DCH0_CAUSE)
85458 #define F_DUCMD_ERR_INTR_DCH0_CAUSE    V_DUCMD_ERR_INTR_DCH0_CAUSE(1U)
85459 
85460 #define S_LCCMD_ERR_INTR_DCH0_CAUSE    8
85461 #define V_LCCMD_ERR_INTR_DCH0_CAUSE(x) ((x) << S_LCCMD_ERR_INTR_DCH0_CAUSE)
85462 #define F_LCCMD_ERR_INTR_DCH0_CAUSE    V_LCCMD_ERR_INTR_DCH0_CAUSE(1U)
85463 
85464 #define S_CTRLUPD_ERR_INTR_DCH0_CAUSE    7
85465 #define V_CTRLUPD_ERR_INTR_DCH0_CAUSE(x) ((x) << S_CTRLUPD_ERR_INTR_DCH0_CAUSE)
85466 #define F_CTRLUPD_ERR_INTR_DCH0_CAUSE    V_CTRLUPD_ERR_INTR_DCH0_CAUSE(1U)
85467 
85468 #define S_RFM_ALERT_INTR_DCH0_CAUSE    6
85469 #define V_RFM_ALERT_INTR_DCH0_CAUSE(x) ((x) << S_RFM_ALERT_INTR_DCH0_CAUSE)
85470 #define F_RFM_ALERT_INTR_DCH0_CAUSE    V_RFM_ALERT_INTR_DCH0_CAUSE(1U)
85471 
85472 #define S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE    5
85473 #define V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE(x) ((x) << S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE)
85474 #define F_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE    V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE(1U)
85475 
85476 #define S_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE    4
85477 #define V_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE(x) ((x) << S_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE)
85478 #define F_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE    V_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE(1U)
85479 
85480 #define S_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE    3
85481 #define V_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE(x) ((x) << S_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE)
85482 #define F_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE    V_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE(1U)
85483 
85484 #define S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE    2
85485 #define V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE(x) ((x) << S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE)
85486 #define F_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE    V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE(1U)
85487 
85488 #define S_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE    1
85489 #define V_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE(x) ((x) << S_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE)
85490 #define F_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE    V_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE(1U)
85491 
85492 #define S_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE    0
85493 #define V_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE(x) ((x) << S_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE)
85494 #define F_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE    V_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE(1U)
85495 
85496 #define A_T7_MC_P_PAR_ENABLE 0x49314
85497 
85498 #define S_HIF_WDATA_Q_PARERR_DCH1_ENABLE    13
85499 #define V_HIF_WDATA_Q_PARERR_DCH1_ENABLE(x) ((x) << S_HIF_WDATA_Q_PARERR_DCH1_ENABLE)
85500 #define F_HIF_WDATA_Q_PARERR_DCH1_ENABLE    V_HIF_WDATA_Q_PARERR_DCH1_ENABLE(1U)
85501 
85502 #define S_DDRCTL_ECC_CE_PAR_DCH1_ENABLE    12
85503 #define V_DDRCTL_ECC_CE_PAR_DCH1_ENABLE(x) ((x) << S_DDRCTL_ECC_CE_PAR_DCH1_ENABLE)
85504 #define F_DDRCTL_ECC_CE_PAR_DCH1_ENABLE    V_DDRCTL_ECC_CE_PAR_DCH1_ENABLE(1U)
85505 
85506 #define S_DDRCTL_ECC_CE_PAR_DCH0_ENABLE    11
85507 #define V_DDRCTL_ECC_CE_PAR_DCH0_ENABLE(x) ((x) << S_DDRCTL_ECC_CE_PAR_DCH0_ENABLE)
85508 #define F_DDRCTL_ECC_CE_PAR_DCH0_ENABLE    V_DDRCTL_ECC_CE_PAR_DCH0_ENABLE(1U)
85509 
85510 #define S_DDRCTL_ECC_UE_PAR_DCH1_ENABLE    10
85511 #define V_DDRCTL_ECC_UE_PAR_DCH1_ENABLE(x) ((x) << S_DDRCTL_ECC_UE_PAR_DCH1_ENABLE)
85512 #define F_DDRCTL_ECC_UE_PAR_DCH1_ENABLE    V_DDRCTL_ECC_UE_PAR_DCH1_ENABLE(1U)
85513 
85514 #define S_DDRCTL_ECC_UE_PAR_DCH0_ENABLE    9
85515 #define V_DDRCTL_ECC_UE_PAR_DCH0_ENABLE(x) ((x) << S_DDRCTL_ECC_UE_PAR_DCH0_ENABLE)
85516 #define F_DDRCTL_ECC_UE_PAR_DCH0_ENABLE    V_DDRCTL_ECC_UE_PAR_DCH0_ENABLE(1U)
85517 
85518 #define S_WDATARAM_PARERR_DCH1_ENABLE    8
85519 #define V_WDATARAM_PARERR_DCH1_ENABLE(x) ((x) << S_WDATARAM_PARERR_DCH1_ENABLE)
85520 #define F_WDATARAM_PARERR_DCH1_ENABLE    V_WDATARAM_PARERR_DCH1_ENABLE(1U)
85521 
85522 #define S_WDATARAM_PARERR_DCH0_ENABLE    7
85523 #define V_WDATARAM_PARERR_DCH0_ENABLE(x) ((x) << S_WDATARAM_PARERR_DCH0_ENABLE)
85524 #define F_WDATARAM_PARERR_DCH0_ENABLE    V_WDATARAM_PARERR_DCH0_ENABLE(1U)
85525 
85526 #define S_BIST_ADDR_FIFO_PARERR_ENABLE    6
85527 #define V_BIST_ADDR_FIFO_PARERR_ENABLE(x) ((x) << S_BIST_ADDR_FIFO_PARERR_ENABLE)
85528 #define F_BIST_ADDR_FIFO_PARERR_ENABLE    V_BIST_ADDR_FIFO_PARERR_ENABLE(1U)
85529 
85530 #define S_BIST_ERR_ADDR_FIFO_PARERR_ENABLE    5
85531 #define V_BIST_ERR_ADDR_FIFO_PARERR_ENABLE(x) ((x) << S_BIST_ERR_ADDR_FIFO_PARERR_ENABLE)
85532 #define F_BIST_ERR_ADDR_FIFO_PARERR_ENABLE    V_BIST_ERR_ADDR_FIFO_PARERR_ENABLE(1U)
85533 
85534 #define S_HIF_WDATA_Q_PARERR_DCH0_ENABLE    4
85535 #define V_HIF_WDATA_Q_PARERR_DCH0_ENABLE(x) ((x) << S_HIF_WDATA_Q_PARERR_DCH0_ENABLE)
85536 #define F_HIF_WDATA_Q_PARERR_DCH0_ENABLE    V_HIF_WDATA_Q_PARERR_DCH0_ENABLE(1U)
85537 
85538 #define S_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE    3
85539 #define V_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE(x) ((x) << S_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE)
85540 #define F_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE    V_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE(1U)
85541 
85542 #define S_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE    2
85543 #define V_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE(x) ((x) << S_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE)
85544 #define F_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE    V_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE(1U)
85545 
85546 #define S_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE    1
85547 #define V_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE(x) ((x) << S_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE)
85548 #define F_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE    V_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE(1U)
85549 
85550 #define S_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE    0
85551 #define V_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE(x) ((x) << S_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE)
85552 #define F_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE    V_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE(1U)
85553 
85554 #define A_T7_MC_P_PAR_CAUSE 0x49318
85555 
85556 #define S_HIF_WDATA_Q_PARERR_DCH1_CAUSE    13
85557 #define V_HIF_WDATA_Q_PARERR_DCH1_CAUSE(x) ((x) << S_HIF_WDATA_Q_PARERR_DCH1_CAUSE)
85558 #define F_HIF_WDATA_Q_PARERR_DCH1_CAUSE    V_HIF_WDATA_Q_PARERR_DCH1_CAUSE(1U)
85559 
85560 #define S_DDRCTL_ECC_CE_PAR_DCH1_CAUSE    12
85561 #define V_DDRCTL_ECC_CE_PAR_DCH1_CAUSE(x) ((x) << S_DDRCTL_ECC_CE_PAR_DCH1_CAUSE)
85562 #define F_DDRCTL_ECC_CE_PAR_DCH1_CAUSE    V_DDRCTL_ECC_CE_PAR_DCH1_CAUSE(1U)
85563 
85564 #define S_DDRCTL_ECC_CE_PAR_DCH0_CAUSE    11
85565 #define V_DDRCTL_ECC_CE_PAR_DCH0_CAUSE(x) ((x) << S_DDRCTL_ECC_CE_PAR_DCH0_CAUSE)
85566 #define F_DDRCTL_ECC_CE_PAR_DCH0_CAUSE    V_DDRCTL_ECC_CE_PAR_DCH0_CAUSE(1U)
85567 
85568 #define S_DDRCTL_ECC_UE_PAR_DCH1_CAUSE    10
85569 #define V_DDRCTL_ECC_UE_PAR_DCH1_CAUSE(x) ((x) << S_DDRCTL_ECC_UE_PAR_DCH1_CAUSE)
85570 #define F_DDRCTL_ECC_UE_PAR_DCH1_CAUSE    V_DDRCTL_ECC_UE_PAR_DCH1_CAUSE(1U)
85571 
85572 #define S_DDRCTL_ECC_UE_PAR_DCH0_CAUSE    9
85573 #define V_DDRCTL_ECC_UE_PAR_DCH0_CAUSE(x) ((x) << S_DDRCTL_ECC_UE_PAR_DCH0_CAUSE)
85574 #define F_DDRCTL_ECC_UE_PAR_DCH0_CAUSE    V_DDRCTL_ECC_UE_PAR_DCH0_CAUSE(1U)
85575 
85576 #define S_WDATARAM_PARERR_DCH1_CAUSE    8
85577 #define V_WDATARAM_PARERR_DCH1_CAUSE(x) ((x) << S_WDATARAM_PARERR_DCH1_CAUSE)
85578 #define F_WDATARAM_PARERR_DCH1_CAUSE    V_WDATARAM_PARERR_DCH1_CAUSE(1U)
85579 
85580 #define S_WDATARAM_PARERR_DCH0_CAUSE    7
85581 #define V_WDATARAM_PARERR_DCH0_CAUSE(x) ((x) << S_WDATARAM_PARERR_DCH0_CAUSE)
85582 #define F_WDATARAM_PARERR_DCH0_CAUSE    V_WDATARAM_PARERR_DCH0_CAUSE(1U)
85583 
85584 #define S_BIST_ADDR_FIFO_PARERR_CAUSE    6
85585 #define V_BIST_ADDR_FIFO_PARERR_CAUSE(x) ((x) << S_BIST_ADDR_FIFO_PARERR_CAUSE)
85586 #define F_BIST_ADDR_FIFO_PARERR_CAUSE    V_BIST_ADDR_FIFO_PARERR_CAUSE(1U)
85587 
85588 #define S_BIST_ERR_ADDR_FIFO_PARERR_CAUSE    5
85589 #define V_BIST_ERR_ADDR_FIFO_PARERR_CAUSE(x) ((x) << S_BIST_ERR_ADDR_FIFO_PARERR_CAUSE)
85590 #define F_BIST_ERR_ADDR_FIFO_PARERR_CAUSE    V_BIST_ERR_ADDR_FIFO_PARERR_CAUSE(1U)
85591 
85592 #define S_HIF_WDATA_Q_PARERR_DCH0_CAUSE    4
85593 #define V_HIF_WDATA_Q_PARERR_DCH0_CAUSE(x) ((x) << S_HIF_WDATA_Q_PARERR_DCH0_CAUSE)
85594 #define F_HIF_WDATA_Q_PARERR_DCH0_CAUSE    V_HIF_WDATA_Q_PARERR_DCH0_CAUSE(1U)
85595 
85596 #define S_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE    3
85597 #define V_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE(x) ((x) << S_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE)
85598 #define F_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE    V_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE(1U)
85599 
85600 #define S_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE    2
85601 #define V_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE(x) ((x) << S_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE)
85602 #define F_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE    V_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE(1U)
85603 
85604 #define S_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE    1
85605 #define V_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE(x) ((x) << S_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE)
85606 #define F_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE    V_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE(1U)
85607 
85608 #define S_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE    0
85609 #define V_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE(x) ((x) << S_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE)
85610 #define F_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE    V_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE(1U)
85611 
85612 #define A_T7_MC_P_INT_ENABLE 0x4931c
85613 
85614 #define S_DDRPHY_INT_ENABLE    4
85615 #define V_DDRPHY_INT_ENABLE(x) ((x) << S_DDRPHY_INT_ENABLE)
85616 #define F_DDRPHY_INT_ENABLE    V_DDRPHY_INT_ENABLE(1U)
85617 
85618 #define S_DDRCTL_INT_ENABLE    3
85619 #define V_DDRCTL_INT_ENABLE(x) ((x) << S_DDRCTL_INT_ENABLE)
85620 #define F_DDRCTL_INT_ENABLE    V_DDRCTL_INT_ENABLE(1U)
85621 
85622 #define S_T7_ECC_CE_INT_ENABLE    2
85623 #define V_T7_ECC_CE_INT_ENABLE(x) ((x) << S_T7_ECC_CE_INT_ENABLE)
85624 #define F_T7_ECC_CE_INT_ENABLE    V_T7_ECC_CE_INT_ENABLE(1U)
85625 
85626 #define S_T7_ECC_UE_INT_ENABLE    1
85627 #define V_T7_ECC_UE_INT_ENABLE(x) ((x) << S_T7_ECC_UE_INT_ENABLE)
85628 #define F_T7_ECC_UE_INT_ENABLE    V_T7_ECC_UE_INT_ENABLE(1U)
85629 
85630 #define A_T7_MC_P_INT_CAUSE 0x49320
85631 
85632 #define S_DDRPHY_INT_CAUSE    4
85633 #define V_DDRPHY_INT_CAUSE(x) ((x) << S_DDRPHY_INT_CAUSE)
85634 #define F_DDRPHY_INT_CAUSE    V_DDRPHY_INT_CAUSE(1U)
85635 
85636 #define S_DDRCTL_INT_CAUSE    3
85637 #define V_DDRCTL_INT_CAUSE(x) ((x) << S_DDRCTL_INT_CAUSE)
85638 #define F_DDRCTL_INT_CAUSE    V_DDRCTL_INT_CAUSE(1U)
85639 
85640 #define S_T7_ECC_CE_INT_CAUSE    2
85641 #define V_T7_ECC_CE_INT_CAUSE(x) ((x) << S_T7_ECC_CE_INT_CAUSE)
85642 #define F_T7_ECC_CE_INT_CAUSE    V_T7_ECC_CE_INT_CAUSE(1U)
85643 
85644 #define S_T7_ECC_UE_INT_CAUSE    1
85645 #define V_T7_ECC_UE_INT_CAUSE(x) ((x) << S_T7_ECC_UE_INT_CAUSE)
85646 #define F_T7_ECC_UE_INT_CAUSE    V_T7_ECC_UE_INT_CAUSE(1U)
85647 
85648 #define A_MC_P_ECC_UE_INT_ENABLE 0x49324
85649 
85650 #define S_BIST_RSP_SRAM_UERR_ENABLE    0
85651 #define V_BIST_RSP_SRAM_UERR_ENABLE(x) ((x) << S_BIST_RSP_SRAM_UERR_ENABLE)
85652 #define F_BIST_RSP_SRAM_UERR_ENABLE    V_BIST_RSP_SRAM_UERR_ENABLE(1U)
85653 
85654 #define A_MC_P_ECC_UE_INT_CAUSE 0x49328
85655 
85656 #define S_BIST_RSP_SRAM_UERR_CAUSE    0
85657 #define V_BIST_RSP_SRAM_UERR_CAUSE(x) ((x) << S_BIST_RSP_SRAM_UERR_CAUSE)
85658 #define F_BIST_RSP_SRAM_UERR_CAUSE    V_BIST_RSP_SRAM_UERR_CAUSE(1U)
85659 
85660 #define A_T7_MC_P_ECC_STATUS 0x4932c
85661 #define A_T7_MC_P_PHY_CTRL 0x49330
85662 #define A_T7_MC_P_STATIC_CFG_STATUS 0x49334
85663 
85664 #define S_DFIFREQRATIO    27
85665 #define V_DFIFREQRATIO(x) ((x) << S_DFIFREQRATIO)
85666 #define F_DFIFREQRATIO    V_DFIFREQRATIO(1U)
85667 
85668 #define S_STATIC_DDR5_HBW_CHANNEL    3
85669 #define V_STATIC_DDR5_HBW_CHANNEL(x) ((x) << S_STATIC_DDR5_HBW_CHANNEL)
85670 #define F_STATIC_DDR5_HBW_CHANNEL    V_STATIC_DDR5_HBW_CHANNEL(1U)
85671 
85672 #define S_STATIC_DDR5_HBW    2
85673 #define V_STATIC_DDR5_HBW(x) ((x) << S_STATIC_DDR5_HBW)
85674 #define F_STATIC_DDR5_HBW    V_STATIC_DDR5_HBW(1U)
85675 
85676 #define S_T7_STATIC_WIDTH    1
85677 #define V_T7_STATIC_WIDTH(x) ((x) << S_T7_STATIC_WIDTH)
85678 #define F_T7_STATIC_WIDTH    V_T7_STATIC_WIDTH(1U)
85679 
85680 #define A_T7_MC_P_CORE_PCTL_STAT 0x49338
85681 #define A_T7_MC_P_DEBUG_CNT 0x4933c
85682 #define A_T7_MC_CE_ERR_DATA_RDATA 0x49340
85683 #define A_T7_MC_UE_ERR_DATA_RDATA 0x49380
85684 #define A_T7_MC_CE_ADDR 0x493c0
85685 #define A_T7_MC_UE_ADDR 0x493c4
85686 #define A_T7_MC_P_DEEP_SLEEP 0x493c8
85687 #define A_T7_MC_P_FPGA_BONUS 0x493cc
85688 #define A_T7_MC_P_DEBUG_CFG 0x493d0
85689 #define A_T7_MC_P_DEBUG_RPT 0x493d4
85690 #define A_T7_MC_P_PHY_ADR_CK_EN 0x493d8
85691 #define A_MC_P_WDATARAM_INIT 0x493dc
85692 
85693 #define S_ENABLE_DCH1    1
85694 #define V_ENABLE_DCH1(x) ((x) << S_ENABLE_DCH1)
85695 #define F_ENABLE_DCH1    V_ENABLE_DCH1(1U)
85696 
85697 #define S_ENABLE_DCH0    0
85698 #define V_ENABLE_DCH0(x) ((x) << S_ENABLE_DCH0)
85699 #define F_ENABLE_DCH0    V_ENABLE_DCH0(1U)
85700 
85701 #define A_T7_MC_CE_ERR_ECC_DATA0 0x493e0
85702 #define A_T7_MC_CE_ERR_ECC_DATA1 0x493e4
85703 #define A_T7_MC_UE_ERR_ECC_DATA0 0x493e8
85704 #define A_T7_MC_UE_ERR_ECC_DATA1 0x493ec
85705 #define A_T7_MC_P_RMW_PRIO 0x493f0
85706 #define A_T7_MC_P_BIST_CMD 0x49400
85707 
85708 #define S_FIFO_ERROR_FLAG    30
85709 #define V_FIFO_ERROR_FLAG(x) ((x) << S_FIFO_ERROR_FLAG)
85710 #define F_FIFO_ERROR_FLAG    V_FIFO_ERROR_FLAG(1U)
85711 
85712 #define A_T7_MC_P_BIST_CMD_ADDR 0x49404
85713 
85714 #define S_T7_VALUE    0
85715 #define M_T7_VALUE    0x1fffffffU
85716 #define V_T7_VALUE(x) ((x) << S_T7_VALUE)
85717 #define G_T7_VALUE(x) (((x) >> S_T7_VALUE) & M_T7_VALUE)
85718 
85719 #define A_MC_P_BIST_NUM_BURST 0x49408
85720 #define A_T7_MC_P_BIST_DATA_PATTERN 0x4940c
85721 
85722 #define S_DATA_TYPE    0
85723 #define M_DATA_TYPE    0xfU
85724 #define V_DATA_TYPE(x) ((x) << S_DATA_TYPE)
85725 #define G_DATA_TYPE(x) (((x) >> S_DATA_TYPE) & M_DATA_TYPE)
85726 
85727 #define A_T7_MC_P_BIST_CRC_SEED 0x49410
85728 #define A_T7_MC_P_BIST_NUM_ERR 0x49460
85729 #define A_MC_P_BIST_ERR_ADDR 0x49464
85730 
85731 #define S_ERROR_ADDR    0
85732 #define M_ERROR_ADDR    0x3fffffffU
85733 #define V_ERROR_ADDR(x) ((x) << S_ERROR_ADDR)
85734 #define G_ERROR_ADDR(x) (((x) >> S_ERROR_ADDR) & M_ERROR_ADDR)
85735 
85736 #define A_MC_P_BIST_USER_RWEDATA 0x49468
85737 #define A_MC_REGB_DDRC_CH0_SCHED0 0x10380
85738 
85739 #define S_OPT_VPRW_SCH    31
85740 #define V_OPT_VPRW_SCH(x) ((x) << S_OPT_VPRW_SCH)
85741 #define F_OPT_VPRW_SCH    V_OPT_VPRW_SCH(1U)
85742 
85743 #define S_DIS_SPECULATIVE_ACT    30
85744 #define V_DIS_SPECULATIVE_ACT(x) ((x) << S_DIS_SPECULATIVE_ACT)
85745 #define F_DIS_SPECULATIVE_ACT    V_DIS_SPECULATIVE_ACT(1U)
85746 
85747 #define S_OPT_ACT_LAT    27
85748 #define V_OPT_ACT_LAT(x) ((x) << S_OPT_ACT_LAT)
85749 #define F_OPT_ACT_LAT    V_OPT_ACT_LAT(1U)
85750 
85751 #define S_LPR_NUM_ENTRIES    8
85752 #define M_LPR_NUM_ENTRIES    0x3fU
85753 #define V_LPR_NUM_ENTRIES(x) ((x) << S_LPR_NUM_ENTRIES)
85754 #define G_LPR_NUM_ENTRIES(x) (((x) >> S_LPR_NUM_ENTRIES) & M_LPR_NUM_ENTRIES)
85755 
85756 #define S_AUTOPRE_RMW    7
85757 #define V_AUTOPRE_RMW(x) ((x) << S_AUTOPRE_RMW)
85758 #define F_AUTOPRE_RMW    V_AUTOPRE_RMW(1U)
85759 
85760 #define S_DIS_OPT_NTT_BY_PRE    6
85761 #define V_DIS_OPT_NTT_BY_PRE(x) ((x) << S_DIS_OPT_NTT_BY_PRE)
85762 #define F_DIS_OPT_NTT_BY_PRE    V_DIS_OPT_NTT_BY_PRE(1U)
85763 
85764 #define S_DIS_OPT_NTT_BY_ACT    5
85765 #define V_DIS_OPT_NTT_BY_ACT(x) ((x) << S_DIS_OPT_NTT_BY_ACT)
85766 #define F_DIS_OPT_NTT_BY_ACT    V_DIS_OPT_NTT_BY_ACT(1U)
85767 
85768 #define S_OPT_WRCAM_FILL_LEVEL    4
85769 #define V_OPT_WRCAM_FILL_LEVEL(x) ((x) << S_OPT_WRCAM_FILL_LEVEL)
85770 #define F_OPT_WRCAM_FILL_LEVEL    V_OPT_WRCAM_FILL_LEVEL(1U)
85771 
85772 #define S_PAGECLOSE    2
85773 #define V_PAGECLOSE(x) ((x) << S_PAGECLOSE)
85774 #define F_PAGECLOSE    V_PAGECLOSE(1U)
85775 
85776 #define S_PREFER_WRITE    1
85777 #define V_PREFER_WRITE(x) ((x) << S_PREFER_WRITE)
85778 #define F_PREFER_WRITE    V_PREFER_WRITE(1U)
85779 
85780 #define A_MC_REGB_DDRC_CH0_ECCCFG0 0x10600
85781 
85782 #define S_DIS_SCRUB    23
85783 #define V_DIS_SCRUB(x) ((x) << S_DIS_SCRUB)
85784 #define F_DIS_SCRUB    V_DIS_SCRUB(1U)
85785 
85786 #define S_ECC_TYPE    4
85787 #define M_ECC_TYPE    0x3U
85788 #define V_ECC_TYPE(x) ((x) << S_ECC_TYPE)
85789 #define G_ECC_TYPE(x) (((x) >> S_ECC_TYPE) & M_ECC_TYPE)
85790 
85791 #define S_TEST_MODE    3
85792 #define V_TEST_MODE(x) ((x) << S_TEST_MODE)
85793 #define F_TEST_MODE    V_TEST_MODE(1U)
85794 
85795 #define S_ECC_MODE    0
85796 #define M_ECC_MODE    0x7U
85797 #define V_ECC_MODE(x) ((x) << S_ECC_MODE)
85798 #define G_ECC_MODE(x) (((x) >> S_ECC_MODE) & M_ECC_MODE)
85799 
85800 #define A_MC_REGB_DDRC_CH0_ECCCFG1 0x10604
85801 
85802 #define S_DATA_POISON_BIT    1
85803 #define V_DATA_POISON_BIT(x) ((x) << S_DATA_POISON_BIT)
85804 #define F_DATA_POISON_BIT    V_DATA_POISON_BIT(1U)
85805 
85806 #define S_DATA_POISON_EN    0
85807 #define V_DATA_POISON_EN(x) ((x) << S_DATA_POISON_EN)
85808 #define F_DATA_POISON_EN    V_DATA_POISON_EN(1U)
85809 
85810 #define A_MC_REGB_DDRC_CH0_ECCSTAT 0x10608
85811 
85812 #define S_ECC_UNCORRECTED_ERR    16
85813 #define M_ECC_UNCORRECTED_ERR    0xffU
85814 #define V_ECC_UNCORRECTED_ERR(x) ((x) << S_ECC_UNCORRECTED_ERR)
85815 #define G_ECC_UNCORRECTED_ERR(x) (((x) >> S_ECC_UNCORRECTED_ERR) & M_ECC_UNCORRECTED_ERR)
85816 
85817 #define S_ECC_CORRECTED_ERR    8
85818 #define M_ECC_CORRECTED_ERR    0xffU
85819 #define V_ECC_CORRECTED_ERR(x) ((x) << S_ECC_CORRECTED_ERR)
85820 #define G_ECC_CORRECTED_ERR(x) (((x) >> S_ECC_CORRECTED_ERR) & M_ECC_CORRECTED_ERR)
85821 
85822 #define S_ECC_CORRECTED_BIT_NUM    0
85823 #define M_ECC_CORRECTED_BIT_NUM    0x7fU
85824 #define V_ECC_CORRECTED_BIT_NUM(x) ((x) << S_ECC_CORRECTED_BIT_NUM)
85825 #define G_ECC_CORRECTED_BIT_NUM(x) (((x) >> S_ECC_CORRECTED_BIT_NUM) & M_ECC_CORRECTED_BIT_NUM)
85826 
85827 #define A_MC_REGB_DDRC_CH0_ECCCTL 0x1060c
85828 
85829 #define S_ECC_UNCORRECTED_ERR_INTR_FORCE    17
85830 #define V_ECC_UNCORRECTED_ERR_INTR_FORCE(x) ((x) << S_ECC_UNCORRECTED_ERR_INTR_FORCE)
85831 #define F_ECC_UNCORRECTED_ERR_INTR_FORCE    V_ECC_UNCORRECTED_ERR_INTR_FORCE(1U)
85832 
85833 #define S_ECC_CORRECTED_ERR_INTR_FORCE    16
85834 #define V_ECC_CORRECTED_ERR_INTR_FORCE(x) ((x) << S_ECC_CORRECTED_ERR_INTR_FORCE)
85835 #define F_ECC_CORRECTED_ERR_INTR_FORCE    V_ECC_CORRECTED_ERR_INTR_FORCE(1U)
85836 
85837 #define S_ECC_UNCORRECTED_ERR_INTR_EN    9
85838 #define V_ECC_UNCORRECTED_ERR_INTR_EN(x) ((x) << S_ECC_UNCORRECTED_ERR_INTR_EN)
85839 #define F_ECC_UNCORRECTED_ERR_INTR_EN    V_ECC_UNCORRECTED_ERR_INTR_EN(1U)
85840 
85841 #define S_ECC_CORRECTED_ERR_INTR_EN    8
85842 #define V_ECC_CORRECTED_ERR_INTR_EN(x) ((x) << S_ECC_CORRECTED_ERR_INTR_EN)
85843 #define F_ECC_CORRECTED_ERR_INTR_EN    V_ECC_CORRECTED_ERR_INTR_EN(1U)
85844 
85845 #define S_ECC_UNCORR_ERR_CNT_CLR    3
85846 #define V_ECC_UNCORR_ERR_CNT_CLR(x) ((x) << S_ECC_UNCORR_ERR_CNT_CLR)
85847 #define F_ECC_UNCORR_ERR_CNT_CLR    V_ECC_UNCORR_ERR_CNT_CLR(1U)
85848 
85849 #define S_ECC_CORR_ERR_CNT_CLR    2
85850 #define V_ECC_CORR_ERR_CNT_CLR(x) ((x) << S_ECC_CORR_ERR_CNT_CLR)
85851 #define F_ECC_CORR_ERR_CNT_CLR    V_ECC_CORR_ERR_CNT_CLR(1U)
85852 
85853 #define S_ECC_UNCORRECTED_ERR_CLR    1
85854 #define V_ECC_UNCORRECTED_ERR_CLR(x) ((x) << S_ECC_UNCORRECTED_ERR_CLR)
85855 #define F_ECC_UNCORRECTED_ERR_CLR    V_ECC_UNCORRECTED_ERR_CLR(1U)
85856 
85857 #define S_ECC_CORRECTED_ERR_CLR    0
85858 #define V_ECC_CORRECTED_ERR_CLR(x) ((x) << S_ECC_CORRECTED_ERR_CLR)
85859 #define F_ECC_CORRECTED_ERR_CLR    V_ECC_CORRECTED_ERR_CLR(1U)
85860 
85861 #define A_MC_REGB_DDRC_CH0_ECCERRCNT 0x10610
85862 
85863 #define S_ECC_UNCORR_ERR_CNT    16
85864 #define M_ECC_UNCORR_ERR_CNT    0xffffU
85865 #define V_ECC_UNCORR_ERR_CNT(x) ((x) << S_ECC_UNCORR_ERR_CNT)
85866 #define G_ECC_UNCORR_ERR_CNT(x) (((x) >> S_ECC_UNCORR_ERR_CNT) & M_ECC_UNCORR_ERR_CNT)
85867 
85868 #define S_ECC_CORR_ERR_CNT    0
85869 #define M_ECC_CORR_ERR_CNT    0xffffU
85870 #define V_ECC_CORR_ERR_CNT(x) ((x) << S_ECC_CORR_ERR_CNT)
85871 #define G_ECC_CORR_ERR_CNT(x) (((x) >> S_ECC_CORR_ERR_CNT) & M_ECC_CORR_ERR_CNT)
85872 
85873 #define A_MC_REGB_DDRC_CH0_ECCCADDR0 0x10614
85874 
85875 #define S_ECC_CORR_RANK    24
85876 #define V_ECC_CORR_RANK(x) ((x) << S_ECC_CORR_RANK)
85877 #define F_ECC_CORR_RANK    V_ECC_CORR_RANK(1U)
85878 
85879 #define S_ECC_CORR_ROW    0
85880 #define M_ECC_CORR_ROW    0x3ffffU
85881 #define V_ECC_CORR_ROW(x) ((x) << S_ECC_CORR_ROW)
85882 #define G_ECC_CORR_ROW(x) (((x) >> S_ECC_CORR_ROW) & M_ECC_CORR_ROW)
85883 
85884 #define A_MC_REGB_DDRC_CH0_ECCCADDR1 0x10618
85885 
85886 #define S_ECC_CORR_BG    24
85887 #define M_ECC_CORR_BG    0x7U
85888 #define V_ECC_CORR_BG(x) ((x) << S_ECC_CORR_BG)
85889 #define G_ECC_CORR_BG(x) (((x) >> S_ECC_CORR_BG) & M_ECC_CORR_BG)
85890 
85891 #define S_ECC_CORR_BANK    16
85892 #define M_ECC_CORR_BANK    0x3U
85893 #define V_ECC_CORR_BANK(x) ((x) << S_ECC_CORR_BANK)
85894 #define G_ECC_CORR_BANK(x) (((x) >> S_ECC_CORR_BANK) & M_ECC_CORR_BANK)
85895 
85896 #define S_ECC_CORR_COL    0
85897 #define M_ECC_CORR_COL    0x7ffU
85898 #define V_ECC_CORR_COL(x) ((x) << S_ECC_CORR_COL)
85899 #define G_ECC_CORR_COL(x) (((x) >> S_ECC_CORR_COL) & M_ECC_CORR_COL)
85900 
85901 #define A_MC_REGB_DDRC_CH0_ECCCSYN0 0x1061c
85902 #define A_MC_REGB_DDRC_CH0_ECCCSYN1 0x10620
85903 #define A_MC_REGB_DDRC_CH0_ECCCSYN2 0x10624
85904 
85905 #define S_CB_CORR_SYNDROME    16
85906 #define M_CB_CORR_SYNDROME    0xffU
85907 #define V_CB_CORR_SYNDROME(x) ((x) << S_CB_CORR_SYNDROME)
85908 #define G_CB_CORR_SYNDROME(x) (((x) >> S_CB_CORR_SYNDROME) & M_CB_CORR_SYNDROME)
85909 
85910 #define S_ECC_CORR_SYNDROMES_71_64    0
85911 #define M_ECC_CORR_SYNDROMES_71_64    0xffU
85912 #define V_ECC_CORR_SYNDROMES_71_64(x) ((x) << S_ECC_CORR_SYNDROMES_71_64)
85913 #define G_ECC_CORR_SYNDROMES_71_64(x) (((x) >> S_ECC_CORR_SYNDROMES_71_64) & M_ECC_CORR_SYNDROMES_71_64)
85914 
85915 #define A_MC_REGB_DDRC_CH0_ECCBITMASK0 0x10628
85916 #define A_MC_REGB_DDRC_CH0_ECCBITMASK1 0x1062c
85917 #define A_MC_REGB_DDRC_CH0_ECCBITMASK2 0x10630
85918 
85919 #define S_ECC_CORR_BIT_MASK_71_64    0
85920 #define M_ECC_CORR_BIT_MASK_71_64    0xffU
85921 #define V_ECC_CORR_BIT_MASK_71_64(x) ((x) << S_ECC_CORR_BIT_MASK_71_64)
85922 #define G_ECC_CORR_BIT_MASK_71_64(x) (((x) >> S_ECC_CORR_BIT_MASK_71_64) & M_ECC_CORR_BIT_MASK_71_64)
85923 
85924 #define A_MC_REGB_DDRC_CH0_ECCUADDR0 0x10634
85925 
85926 #define S_ECC_UNCORR_RANK    24
85927 #define V_ECC_UNCORR_RANK(x) ((x) << S_ECC_UNCORR_RANK)
85928 #define F_ECC_UNCORR_RANK    V_ECC_UNCORR_RANK(1U)
85929 
85930 #define S_ECC_UNCORR_ROW    0
85931 #define M_ECC_UNCORR_ROW    0x3ffffU
85932 #define V_ECC_UNCORR_ROW(x) ((x) << S_ECC_UNCORR_ROW)
85933 #define G_ECC_UNCORR_ROW(x) (((x) >> S_ECC_UNCORR_ROW) & M_ECC_UNCORR_ROW)
85934 
85935 #define A_MC_REGB_DDRC_CH0_ECCUADDR1 0x10638
85936 
85937 #define S_ECC_UNCORR_BG    24
85938 #define M_ECC_UNCORR_BG    0x7U
85939 #define V_ECC_UNCORR_BG(x) ((x) << S_ECC_UNCORR_BG)
85940 #define G_ECC_UNCORR_BG(x) (((x) >> S_ECC_UNCORR_BG) & M_ECC_UNCORR_BG)
85941 
85942 #define S_ECC_UNCORR_BANK    16
85943 #define M_ECC_UNCORR_BANK    0x3U
85944 #define V_ECC_UNCORR_BANK(x) ((x) << S_ECC_UNCORR_BANK)
85945 #define G_ECC_UNCORR_BANK(x) (((x) >> S_ECC_UNCORR_BANK) & M_ECC_UNCORR_BANK)
85946 
85947 #define S_ECC_UNCORR_COL    0
85948 #define M_ECC_UNCORR_COL    0x7ffU
85949 #define V_ECC_UNCORR_COL(x) ((x) << S_ECC_UNCORR_COL)
85950 #define G_ECC_UNCORR_COL(x) (((x) >> S_ECC_UNCORR_COL) & M_ECC_UNCORR_COL)
85951 
85952 #define A_MC_REGB_DDRC_CH0_ECCUSYN0 0x1063c
85953 #define A_MC_REGB_DDRC_CH0_ECCUSYN1 0x10640
85954 #define A_MC_REGB_DDRC_CH0_ECCUSYN2 0x10644
85955 
85956 #define S_CB_UNCORR_SYNDROME    16
85957 #define M_CB_UNCORR_SYNDROME    0xffU
85958 #define V_CB_UNCORR_SYNDROME(x) ((x) << S_CB_UNCORR_SYNDROME)
85959 #define G_CB_UNCORR_SYNDROME(x) (((x) >> S_CB_UNCORR_SYNDROME) & M_CB_UNCORR_SYNDROME)
85960 
85961 #define S_ECC_UNCORR_SYNDROMES_71_64    0
85962 #define M_ECC_UNCORR_SYNDROMES_71_64    0xffU
85963 #define V_ECC_UNCORR_SYNDROMES_71_64(x) ((x) << S_ECC_UNCORR_SYNDROMES_71_64)
85964 #define G_ECC_UNCORR_SYNDROMES_71_64(x) (((x) >> S_ECC_UNCORR_SYNDROMES_71_64) & M_ECC_UNCORR_SYNDROMES_71_64)
85965 
85966 #define A_MC_REGB_DDRC_CH0_ECCPOISONADDR0 0x10648
85967 
85968 #define S_ECC_POISON_RANK    24
85969 #define V_ECC_POISON_RANK(x) ((x) << S_ECC_POISON_RANK)
85970 #define F_ECC_POISON_RANK    V_ECC_POISON_RANK(1U)
85971 
85972 #define S_ECC_POISON_COL    0
85973 #define M_ECC_POISON_COL    0xfffU
85974 #define V_ECC_POISON_COL(x) ((x) << S_ECC_POISON_COL)
85975 #define G_ECC_POISON_COL(x) (((x) >> S_ECC_POISON_COL) & M_ECC_POISON_COL)
85976 
85977 #define A_MC_REGB_DDRC_CH0_ECCPOISONADDR1 0x1064c
85978 
85979 #define S_ECC_POISON_BG    28
85980 #define M_ECC_POISON_BG    0x7U
85981 #define V_ECC_POISON_BG(x) ((x) << S_ECC_POISON_BG)
85982 #define G_ECC_POISON_BG(x) (((x) >> S_ECC_POISON_BG) & M_ECC_POISON_BG)
85983 
85984 #define S_ECC_POISON_BANK    24
85985 #define M_ECC_POISON_BANK    0x3U
85986 #define V_ECC_POISON_BANK(x) ((x) << S_ECC_POISON_BANK)
85987 #define G_ECC_POISON_BANK(x) (((x) >> S_ECC_POISON_BANK) & M_ECC_POISON_BANK)
85988 
85989 #define S_ECC_POISON_ROW    0
85990 #define M_ECC_POISON_ROW    0x3ffffU
85991 #define V_ECC_POISON_ROW(x) ((x) << S_ECC_POISON_ROW)
85992 #define G_ECC_POISON_ROW(x) (((x) >> S_ECC_POISON_ROW) & M_ECC_POISON_ROW)
85993 
85994 #define A_MC_REGB_DDRC_CH0_ECCPOISONPAT0 0x10658
85995 #define A_MC_REGB_DDRC_CH0_ECCPOISONPAT1 0x1065c
85996 #define A_MC_REGB_DDRC_CH0_ECCPOISONPAT2 0x10660
85997 
85998 #define S_ECC_POISON_DATA_71_64    0
85999 #define M_ECC_POISON_DATA_71_64    0xffU
86000 #define V_ECC_POISON_DATA_71_64(x) ((x) << S_ECC_POISON_DATA_71_64)
86001 #define G_ECC_POISON_DATA_71_64(x) (((x) >> S_ECC_POISON_DATA_71_64) & M_ECC_POISON_DATA_71_64)
86002 
86003 #define A_MC_REGB_DDRC_CH0_ECCCFG2 0x10668
86004 
86005 #define S_FLIP_BIT_POS1    24
86006 #define M_FLIP_BIT_POS1    0x7fU
86007 #define V_FLIP_BIT_POS1(x) ((x) << S_FLIP_BIT_POS1)
86008 #define G_FLIP_BIT_POS1(x) (((x) >> S_FLIP_BIT_POS1) & M_FLIP_BIT_POS1)
86009 
86010 #define S_FLIP_BIT_POS0    16
86011 #define M_FLIP_BIT_POS0    0x7fU
86012 #define V_FLIP_BIT_POS0(x) ((x) << S_FLIP_BIT_POS0)
86013 #define G_FLIP_BIT_POS0(x) (((x) >> S_FLIP_BIT_POS0) & M_FLIP_BIT_POS0)
86014 
86015 #define A_MC_REGB_DDRC_CH1_ECCCTL 0x1160c
86016 #define A_MC_REGB_DDRC_CH1_ECCERRCNT 0x11610
86017 #define A_MC_REGB_DDRC_CH1_ECCCADDR0 0x11614
86018 #define A_MC_REGB_DDRC_CH1_ECCCADDR1 0x11618
86019 #define A_MC_REGB_DDRC_CH1_ECCCSYN0 0x1161c
86020 #define A_MC_REGB_DDRC_CH1_ECCCSYN1 0x11620
86021 #define A_MC_REGB_DDRC_CH1_ECCCSYN2 0x11624
86022 #define A_MC_REGB_DDRC_CH1_ECCBITMASK0 0x11628
86023 #define A_MC_REGB_DDRC_CH1_ECCBITMASK1 0x1162c
86024 #define A_MC_REGB_DDRC_CH1_ECCBITMASK2 0x11630
86025 #define A_MC_REGB_DDRC_CH1_ECCUADDR0 0x11634
86026 #define A_MC_REGB_DDRC_CH1_ECCUADDR1 0x11638
86027 #define A_MC_REGB_DDRC_CH1_ECCUSYN0 0x1163c
86028 #define A_MC_REGB_DDRC_CH1_ECCUSYN1 0x11640
86029 #define A_MC_REGB_DDRC_CH1_ECCUSYN2 0x11644
86030 #define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTENABLE 0x20100
86031 
86032 #define S_PHYSTICKYUNLOCKEN    15
86033 #define V_PHYSTICKYUNLOCKEN(x) ((x) << S_PHYSTICKYUNLOCKEN)
86034 #define F_PHYSTICKYUNLOCKEN    V_PHYSTICKYUNLOCKEN(1U)
86035 
86036 #define S_PHYBSIEN    14
86037 #define V_PHYBSIEN(x) ((x) << S_PHYBSIEN)
86038 #define F_PHYBSIEN    V_PHYBSIEN(1U)
86039 
86040 #define S_PHYANIBRCVERREN    13
86041 #define V_PHYANIBRCVERREN(x) ((x) << S_PHYANIBRCVERREN)
86042 #define F_PHYANIBRCVERREN    V_PHYANIBRCVERREN(1U)
86043 
86044 #define S_PHYD5ACSM1PARITYEN    12
86045 #define V_PHYD5ACSM1PARITYEN(x) ((x) << S_PHYD5ACSM1PARITYEN)
86046 #define F_PHYD5ACSM1PARITYEN    V_PHYD5ACSM1PARITYEN(1U)
86047 
86048 #define S_PHYD5ACSM0PARITYEN    11
86049 #define V_PHYD5ACSM0PARITYEN(x) ((x) << S_PHYD5ACSM0PARITYEN)
86050 #define F_PHYD5ACSM0PARITYEN    V_PHYD5ACSM0PARITYEN(1U)
86051 
86052 #define S_PHYRXFIFOCHECKEN    10
86053 #define V_PHYRXFIFOCHECKEN(x) ((x) << S_PHYRXFIFOCHECKEN)
86054 #define F_PHYRXFIFOCHECKEN    V_PHYRXFIFOCHECKEN(1U)
86055 
86056 #define S_PHYTXPPTEN    9
86057 #define V_PHYTXPPTEN(x) ((x) << S_PHYTXPPTEN)
86058 #define F_PHYTXPPTEN    V_PHYTXPPTEN(1U)
86059 
86060 #define S_PHYECCEN    8
86061 #define V_PHYECCEN(x) ((x) << S_PHYECCEN)
86062 #define F_PHYECCEN    V_PHYECCEN(1U)
86063 
86064 #define S_PHYFWRESERVEDEN    3
86065 #define M_PHYFWRESERVEDEN    0x1fU
86066 #define V_PHYFWRESERVEDEN(x) ((x) << S_PHYFWRESERVEDEN)
86067 #define G_PHYFWRESERVEDEN(x) (((x) >> S_PHYFWRESERVEDEN) & M_PHYFWRESERVEDEN)
86068 
86069 #define S_PHYTRNGFAILEN    2
86070 #define V_PHYTRNGFAILEN(x) ((x) << S_PHYTRNGFAILEN)
86071 #define F_PHYTRNGFAILEN    V_PHYTRNGFAILEN(1U)
86072 
86073 #define S_PHYINITCMPLTEN    1
86074 #define V_PHYINITCMPLTEN(x) ((x) << S_PHYINITCMPLTEN)
86075 #define F_PHYINITCMPLTEN    V_PHYINITCMPLTEN(1U)
86076 
86077 #define S_PHYTRNGCMPLTEN    0
86078 #define V_PHYTRNGCMPLTEN(x) ((x) << S_PHYTRNGCMPLTEN)
86079 #define F_PHYTRNGCMPLTEN    V_PHYTRNGCMPLTEN(1U)
86080 
86081 #define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTFWCONTROL 0x20101
86082 
86083 #define S_PHYFWRESERVEDFW    3
86084 #define M_PHYFWRESERVEDFW    0x1fU
86085 #define V_PHYFWRESERVEDFW(x) ((x) << S_PHYFWRESERVEDFW)
86086 #define G_PHYFWRESERVEDFW(x) (((x) >> S_PHYFWRESERVEDFW) & M_PHYFWRESERVEDFW)
86087 
86088 #define S_PHYTRNGFAILFW    2
86089 #define V_PHYTRNGFAILFW(x) ((x) << S_PHYTRNGFAILFW)
86090 #define F_PHYTRNGFAILFW    V_PHYTRNGFAILFW(1U)
86091 
86092 #define S_PHYINITCMPLTFW    1
86093 #define V_PHYINITCMPLTFW(x) ((x) << S_PHYINITCMPLTFW)
86094 #define F_PHYINITCMPLTFW    V_PHYINITCMPLTFW(1U)
86095 
86096 #define S_PHYTRNGCMPLTFW    0
86097 #define V_PHYTRNGCMPLTFW(x) ((x) << S_PHYTRNGCMPLTFW)
86098 #define F_PHYTRNGCMPLTFW    V_PHYTRNGCMPLTFW(1U)
86099 
86100 #define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTMASK 0x20102
86101 
86102 #define S_PHYSTICKYUNLOCKMSK    15
86103 #define V_PHYSTICKYUNLOCKMSK(x) ((x) << S_PHYSTICKYUNLOCKMSK)
86104 #define F_PHYSTICKYUNLOCKMSK    V_PHYSTICKYUNLOCKMSK(1U)
86105 
86106 #define S_PHYBSIMSK    14
86107 #define V_PHYBSIMSK(x) ((x) << S_PHYBSIMSK)
86108 #define F_PHYBSIMSK    V_PHYBSIMSK(1U)
86109 
86110 #define S_PHYANIBRCVERRMSK    13
86111 #define V_PHYANIBRCVERRMSK(x) ((x) << S_PHYANIBRCVERRMSK)
86112 #define F_PHYANIBRCVERRMSK    V_PHYANIBRCVERRMSK(1U)
86113 
86114 #define S_PHYD5ACSM1PARITYMSK    12
86115 #define V_PHYD5ACSM1PARITYMSK(x) ((x) << S_PHYD5ACSM1PARITYMSK)
86116 #define F_PHYD5ACSM1PARITYMSK    V_PHYD5ACSM1PARITYMSK(1U)
86117 
86118 #define S_PHYD5ACSM0PARITYMSK    11
86119 #define V_PHYD5ACSM0PARITYMSK(x) ((x) << S_PHYD5ACSM0PARITYMSK)
86120 #define F_PHYD5ACSM0PARITYMSK    V_PHYD5ACSM0PARITYMSK(1U)
86121 
86122 #define S_PHYRXFIFOCHECKMSK    10
86123 #define V_PHYRXFIFOCHECKMSK(x) ((x) << S_PHYRXFIFOCHECKMSK)
86124 #define F_PHYRXFIFOCHECKMSK    V_PHYRXFIFOCHECKMSK(1U)
86125 
86126 #define S_PHYTXPPTMSK    9
86127 #define V_PHYTXPPTMSK(x) ((x) << S_PHYTXPPTMSK)
86128 #define F_PHYTXPPTMSK    V_PHYTXPPTMSK(1U)
86129 
86130 #define S_PHYECCMSK    8
86131 #define V_PHYECCMSK(x) ((x) << S_PHYECCMSK)
86132 #define F_PHYECCMSK    V_PHYECCMSK(1U)
86133 
86134 #define S_PHYFWRESERVEDMSK    3
86135 #define M_PHYFWRESERVEDMSK    0x1fU
86136 #define V_PHYFWRESERVEDMSK(x) ((x) << S_PHYFWRESERVEDMSK)
86137 #define G_PHYFWRESERVEDMSK(x) (((x) >> S_PHYFWRESERVEDMSK) & M_PHYFWRESERVEDMSK)
86138 
86139 #define S_PHYTRNGFAILMSK    2
86140 #define V_PHYTRNGFAILMSK(x) ((x) << S_PHYTRNGFAILMSK)
86141 #define F_PHYTRNGFAILMSK    V_PHYTRNGFAILMSK(1U)
86142 
86143 #define S_PHYINITCMPLTMSK    1
86144 #define V_PHYINITCMPLTMSK(x) ((x) << S_PHYINITCMPLTMSK)
86145 #define F_PHYINITCMPLTMSK    V_PHYINITCMPLTMSK(1U)
86146 
86147 #define S_PHYTRNGCMPLTMSK    0
86148 #define V_PHYTRNGCMPLTMSK(x) ((x) << S_PHYTRNGCMPLTMSK)
86149 #define F_PHYTRNGCMPLTMSK    V_PHYTRNGCMPLTMSK(1U)
86150 
86151 #define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTCLEAR 0x20103
86152 
86153 #define S_PHYSTICKYUNLOCKCLR    15
86154 #define V_PHYSTICKYUNLOCKCLR(x) ((x) << S_PHYSTICKYUNLOCKCLR)
86155 #define F_PHYSTICKYUNLOCKCLR    V_PHYSTICKYUNLOCKCLR(1U)
86156 
86157 #define S_PHYBSICLR    14
86158 #define V_PHYBSICLR(x) ((x) << S_PHYBSICLR)
86159 #define F_PHYBSICLR    V_PHYBSICLR(1U)
86160 
86161 #define S_PHYANIBRCVERRCLR    13
86162 #define V_PHYANIBRCVERRCLR(x) ((x) << S_PHYANIBRCVERRCLR)
86163 #define F_PHYANIBRCVERRCLR    V_PHYANIBRCVERRCLR(1U)
86164 
86165 #define S_PHYD5ACSM1PARITYCLR    12
86166 #define V_PHYD5ACSM1PARITYCLR(x) ((x) << S_PHYD5ACSM1PARITYCLR)
86167 #define F_PHYD5ACSM1PARITYCLR    V_PHYD5ACSM1PARITYCLR(1U)
86168 
86169 #define S_PHYD5ACSM0PARITYCLR    11
86170 #define V_PHYD5ACSM0PARITYCLR(x) ((x) << S_PHYD5ACSM0PARITYCLR)
86171 #define F_PHYD5ACSM0PARITYCLR    V_PHYD5ACSM0PARITYCLR(1U)
86172 
86173 #define S_PHYRXFIFOCHECKCLR    10
86174 #define V_PHYRXFIFOCHECKCLR(x) ((x) << S_PHYRXFIFOCHECKCLR)
86175 #define F_PHYRXFIFOCHECKCLR    V_PHYRXFIFOCHECKCLR(1U)
86176 
86177 #define S_PHYTXPPTCLR    9
86178 #define V_PHYTXPPTCLR(x) ((x) << S_PHYTXPPTCLR)
86179 #define F_PHYTXPPTCLR    V_PHYTXPPTCLR(1U)
86180 
86181 #define S_PHYECCCLR    8
86182 #define V_PHYECCCLR(x) ((x) << S_PHYECCCLR)
86183 #define F_PHYECCCLR    V_PHYECCCLR(1U)
86184 
86185 #define S_PHYFWRESERVEDCLR    3
86186 #define M_PHYFWRESERVEDCLR    0x1fU
86187 #define V_PHYFWRESERVEDCLR(x) ((x) << S_PHYFWRESERVEDCLR)
86188 #define G_PHYFWRESERVEDCLR(x) (((x) >> S_PHYFWRESERVEDCLR) & M_PHYFWRESERVEDCLR)
86189 
86190 #define S_PHYTRNGFAILCLR    2
86191 #define V_PHYTRNGFAILCLR(x) ((x) << S_PHYTRNGFAILCLR)
86192 #define F_PHYTRNGFAILCLR    V_PHYTRNGFAILCLR(1U)
86193 
86194 #define S_PHYINITCMPLTCLR    1
86195 #define V_PHYINITCMPLTCLR(x) ((x) << S_PHYINITCMPLTCLR)
86196 #define F_PHYINITCMPLTCLR    V_PHYINITCMPLTCLR(1U)
86197 
86198 #define S_PHYTRNGCMPLTCLR    0
86199 #define V_PHYTRNGCMPLTCLR(x) ((x) << S_PHYTRNGCMPLTCLR)
86200 #define F_PHYTRNGCMPLTCLR    V_PHYTRNGCMPLTCLR(1U)
86201 
86202 #define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTSTATUS 0x20104
86203 
86204 #define S_PHYSTICKYUNLOCKERR    15
86205 #define V_PHYSTICKYUNLOCKERR(x) ((x) << S_PHYSTICKYUNLOCKERR)
86206 #define F_PHYSTICKYUNLOCKERR    V_PHYSTICKYUNLOCKERR(1U)
86207 
86208 #define S_PHYBSIINT    14
86209 #define V_PHYBSIINT(x) ((x) << S_PHYBSIINT)
86210 #define F_PHYBSIINT    V_PHYBSIINT(1U)
86211 
86212 #define S_PHYANIBRCVERR    13
86213 #define V_PHYANIBRCVERR(x) ((x) << S_PHYANIBRCVERR)
86214 #define F_PHYANIBRCVERR    V_PHYANIBRCVERR(1U)
86215 
86216 #define S_PHYD5ACSM1PARITYERR    12
86217 #define V_PHYD5ACSM1PARITYERR(x) ((x) << S_PHYD5ACSM1PARITYERR)
86218 #define F_PHYD5ACSM1PARITYERR    V_PHYD5ACSM1PARITYERR(1U)
86219 
86220 #define S_PHYD5ACSM0PARITYERR    11
86221 #define V_PHYD5ACSM0PARITYERR(x) ((x) << S_PHYD5ACSM0PARITYERR)
86222 #define F_PHYD5ACSM0PARITYERR    V_PHYD5ACSM0PARITYERR(1U)
86223 
86224 #define S_PHYRXFIFOCHECKERR    10
86225 #define V_PHYRXFIFOCHECKERR(x) ((x) << S_PHYRXFIFOCHECKERR)
86226 #define F_PHYRXFIFOCHECKERR    V_PHYRXFIFOCHECKERR(1U)
86227 
86228 #define S_PHYRXTXPPTERR    9
86229 #define V_PHYRXTXPPTERR(x) ((x) << S_PHYRXTXPPTERR)
86230 #define F_PHYRXTXPPTERR    V_PHYRXTXPPTERR(1U)
86231 
86232 #define S_PHYECCERR    8
86233 #define V_PHYECCERR(x) ((x) << S_PHYECCERR)
86234 #define F_PHYECCERR    V_PHYECCERR(1U)
86235 
86236 #define S_PHYFWRESERVED    3
86237 #define M_PHYFWRESERVED    0x1fU
86238 #define V_PHYFWRESERVED(x) ((x) << S_PHYFWRESERVED)
86239 #define G_PHYFWRESERVED(x) (((x) >> S_PHYFWRESERVED) & M_PHYFWRESERVED)
86240 
86241 #define S_PHYTRNGFAIL    2
86242 #define V_PHYTRNGFAIL(x) ((x) << S_PHYTRNGFAIL)
86243 #define F_PHYTRNGFAIL    V_PHYTRNGFAIL(1U)
86244 
86245 #define S_PHYINITCMPLT    1
86246 #define V_PHYINITCMPLT(x) ((x) << S_PHYINITCMPLT)
86247 #define F_PHYINITCMPLT    V_PHYINITCMPLT(1U)
86248 
86249 #define S_PHYTRNGCMPLT    0
86250 #define V_PHYTRNGCMPLT(x) ((x) << S_PHYTRNGCMPLT)
86251 #define F_PHYTRNGCMPLT    V_PHYTRNGCMPLT(1U)
86252 
86253 #define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTOVERRIDE 0x20107
86254 
86255 #define S_PHYINTERRUPTOVERRIDE    0
86256 #define M_PHYINTERRUPTOVERRIDE    0xffffU
86257 #define V_PHYINTERRUPTOVERRIDE(x) ((x) << S_PHYINTERRUPTOVERRIDE)
86258 #define G_PHYINTERRUPTOVERRIDE(x) (((x) >> S_PHYINTERRUPTOVERRIDE) & M_PHYINTERRUPTOVERRIDE)
86259 
86260 /* registers for module MC_T71 */
86261 #define MC_T71_BASE_ADDR 0x58000
86262 
86263 /* registers for module GCACHE */
86264 #define GCACHE_BASE_ADDR 0x51400
86265 
86266 #define A_GCACHE_MODE_SEL0 0x51400
86267 
86268 #define S_GC_MA_RSP    16
86269 #define V_GC_MA_RSP(x) ((x) << S_GC_MA_RSP)
86270 #define F_GC_MA_RSP    V_GC_MA_RSP(1U)
86271 
86272 #define A_GCACHE_MEMZONE0_REGION1 0x51404
86273 
86274 #define S_REGION_EN1    18
86275 #define V_REGION_EN1(x) ((x) << S_REGION_EN1)
86276 #define F_REGION_EN1    V_REGION_EN1(1U)
86277 
86278 #define S_EDC_REGION1    17
86279 #define V_EDC_REGION1(x) ((x) << S_EDC_REGION1)
86280 #define F_EDC_REGION1    V_EDC_REGION1(1U)
86281 
86282 #define S_CACHE_REGION1    16
86283 #define V_CACHE_REGION1(x) ((x) << S_CACHE_REGION1)
86284 #define F_CACHE_REGION1    V_CACHE_REGION1(1U)
86285 
86286 #define S_END1    0
86287 #define M_END1    0xffffU
86288 #define V_END1(x) ((x) << S_END1)
86289 #define G_END1(x) (((x) >> S_END1) & M_END1)
86290 
86291 #define A_GCACHE_MEMZONE0_REGION2 0x51408
86292 
86293 #define S_REGION_EN2    18
86294 #define V_REGION_EN2(x) ((x) << S_REGION_EN2)
86295 #define F_REGION_EN2    V_REGION_EN2(1U)
86296 
86297 #define S_EDC_REGION2    17
86298 #define V_EDC_REGION2(x) ((x) << S_EDC_REGION2)
86299 #define F_EDC_REGION2    V_EDC_REGION2(1U)
86300 
86301 #define S_CACHE_REGION2    16
86302 #define V_CACHE_REGION2(x) ((x) << S_CACHE_REGION2)
86303 #define F_CACHE_REGION2    V_CACHE_REGION2(1U)
86304 
86305 #define S_END2    0
86306 #define M_END2    0xffffU
86307 #define V_END2(x) ((x) << S_END2)
86308 #define G_END2(x) (((x) >> S_END2) & M_END2)
86309 
86310 #define A_GCACHE_MEMZONE0_REGION3 0x5140c
86311 
86312 #define S_REGION_EN3    18
86313 #define V_REGION_EN3(x) ((x) << S_REGION_EN3)
86314 #define F_REGION_EN3    V_REGION_EN3(1U)
86315 
86316 #define S_EDC_REGION3    17
86317 #define V_EDC_REGION3(x) ((x) << S_EDC_REGION3)
86318 #define F_EDC_REGION3    V_EDC_REGION3(1U)
86319 
86320 #define S_CACHE_REGION3    16
86321 #define V_CACHE_REGION3(x) ((x) << S_CACHE_REGION3)
86322 #define F_CACHE_REGION3    V_CACHE_REGION3(1U)
86323 
86324 #define S_END3    0
86325 #define M_END3    0xffffU
86326 #define V_END3(x) ((x) << S_END3)
86327 #define G_END3(x) (((x) >> S_END3) & M_END3)
86328 
86329 #define A_GCACHE_MEMZONE0_REGION4 0x51410
86330 
86331 #define S_REGION_EN4    18
86332 #define V_REGION_EN4(x) ((x) << S_REGION_EN4)
86333 #define F_REGION_EN4    V_REGION_EN4(1U)
86334 
86335 #define S_EDC_REGION4    17
86336 #define V_EDC_REGION4(x) ((x) << S_EDC_REGION4)
86337 #define F_EDC_REGION4    V_EDC_REGION4(1U)
86338 
86339 #define S_CACHE_REGION4    16
86340 #define V_CACHE_REGION4(x) ((x) << S_CACHE_REGION4)
86341 #define F_CACHE_REGION4    V_CACHE_REGION4(1U)
86342 
86343 #define S_END4    0
86344 #define M_END4    0xffffU
86345 #define V_END4(x) ((x) << S_END4)
86346 #define G_END4(x) (((x) >> S_END4) & M_END4)
86347 
86348 #define A_GCACHE_MEMZONE0_REGION5 0x51414
86349 
86350 #define S_REGION_EN5    18
86351 #define V_REGION_EN5(x) ((x) << S_REGION_EN5)
86352 #define F_REGION_EN5    V_REGION_EN5(1U)
86353 
86354 #define S_EDC_REGION5    17
86355 #define V_EDC_REGION5(x) ((x) << S_EDC_REGION5)
86356 #define F_EDC_REGION5    V_EDC_REGION5(1U)
86357 
86358 #define S_CACHE_REGION5    16
86359 #define V_CACHE_REGION5(x) ((x) << S_CACHE_REGION5)
86360 #define F_CACHE_REGION5    V_CACHE_REGION5(1U)
86361 
86362 #define S_END5    0
86363 #define M_END5    0xffffU
86364 #define V_END5(x) ((x) << S_END5)
86365 #define G_END5(x) (((x) >> S_END5) & M_END5)
86366 
86367 #define A_GCACHE_MEMZONE0_REGION6 0x51418
86368 
86369 #define S_REGION_EN6    18
86370 #define V_REGION_EN6(x) ((x) << S_REGION_EN6)
86371 #define F_REGION_EN6    V_REGION_EN6(1U)
86372 
86373 #define S_EDC_REGION6    17
86374 #define V_EDC_REGION6(x) ((x) << S_EDC_REGION6)
86375 #define F_EDC_REGION6    V_EDC_REGION6(1U)
86376 
86377 #define S_CACHE_REGION6    16
86378 #define V_CACHE_REGION6(x) ((x) << S_CACHE_REGION6)
86379 #define F_CACHE_REGION6    V_CACHE_REGION6(1U)
86380 
86381 #define S_END6    0
86382 #define M_END6    0xffffU
86383 #define V_END6(x) ((x) << S_END6)
86384 #define G_END6(x) (((x) >> S_END6) & M_END6)
86385 
86386 #define A_GCACHE_MEMZONE0_REGION7 0x5141c
86387 
86388 #define S_REGION_EN7    18
86389 #define V_REGION_EN7(x) ((x) << S_REGION_EN7)
86390 #define F_REGION_EN7    V_REGION_EN7(1U)
86391 
86392 #define S_EDC_REGION7    17
86393 #define V_EDC_REGION7(x) ((x) << S_EDC_REGION7)
86394 #define F_EDC_REGION7    V_EDC_REGION7(1U)
86395 
86396 #define S_CACHE_REGION7    16
86397 #define V_CACHE_REGION7(x) ((x) << S_CACHE_REGION7)
86398 #define F_CACHE_REGION7    V_CACHE_REGION7(1U)
86399 
86400 #define S_END7    0
86401 #define M_END7    0xffffU
86402 #define V_END7(x) ((x) << S_END7)
86403 #define G_END7(x) (((x) >> S_END7) & M_END7)
86404 
86405 #define A_GCACHE_MEMZONE0_REGION8 0x51420
86406 
86407 #define S_REGION_EN8    18
86408 #define V_REGION_EN8(x) ((x) << S_REGION_EN8)
86409 #define F_REGION_EN8    V_REGION_EN8(1U)
86410 
86411 #define S_EDC_REGION8    17
86412 #define V_EDC_REGION8(x) ((x) << S_EDC_REGION8)
86413 #define F_EDC_REGION8    V_EDC_REGION8(1U)
86414 
86415 #define S_CACHE_REGION8    16
86416 #define V_CACHE_REGION8(x) ((x) << S_CACHE_REGION8)
86417 #define F_CACHE_REGION8    V_CACHE_REGION8(1U)
86418 
86419 #define S_END8    0
86420 #define M_END8    0xffffU
86421 #define V_END8(x) ((x) << S_END8)
86422 #define G_END8(x) (((x) >> S_END8) & M_END8)
86423 
86424 #define A_GCACHE_REG0_BASE_MSB 0x51424
86425 #define A_GCACHE_MEMZONE0_REGION1_MSB 0x51428
86426 
86427 #define S_START1    0
86428 #define M_START1    0xffffU
86429 #define V_START1(x) ((x) << S_START1)
86430 #define G_START1(x) (((x) >> S_START1) & M_START1)
86431 
86432 #define A_GCACHE_MEMZONE0_REGION2_MSB 0x5142c
86433 
86434 #define S_START2    0
86435 #define M_START2    0xffffU
86436 #define V_START2(x) ((x) << S_START2)
86437 #define G_START2(x) (((x) >> S_START2) & M_START2)
86438 
86439 #define A_GCACHE_MEMZONE0_REGION3_MSB 0x51430
86440 
86441 #define S_START3    0
86442 #define M_START3    0xffffU
86443 #define V_START3(x) ((x) << S_START3)
86444 #define G_START3(x) (((x) >> S_START3) & M_START3)
86445 
86446 #define A_GCACHE_MEMZONE0_REGION4_MSB 0x51434
86447 
86448 #define S_START4    0
86449 #define M_START4    0xffffU
86450 #define V_START4(x) ((x) << S_START4)
86451 #define G_START4(x) (((x) >> S_START4) & M_START4)
86452 
86453 #define A_GCACHE_MEMZONE0_REGION5_MSB 0x51438
86454 
86455 #define S_START5    0
86456 #define M_START5    0xffffU
86457 #define V_START5(x) ((x) << S_START5)
86458 #define G_START5(x) (((x) >> S_START5) & M_START5)
86459 
86460 #define A_GCACHE_MEMZONE0_REGION6_MSB 0x5143c
86461 
86462 #define S_START6    0
86463 #define M_START6    0xffffU
86464 #define V_START6(x) ((x) << S_START6)
86465 #define G_START6(x) (((x) >> S_START6) & M_START6)
86466 
86467 #define A_GCACHE_MEMZONE0_REGION7_MSB 0x51440
86468 
86469 #define S_START7    0
86470 #define M_START7    0xffffU
86471 #define V_START7(x) ((x) << S_START7)
86472 #define G_START7(x) (((x) >> S_START7) & M_START7)
86473 
86474 #define A_GCACHE_MEMZONE0_REGION8_MSB 0x51444
86475 
86476 #define S_START8    0
86477 #define M_START8    0xffffU
86478 #define V_START8(x) ((x) << S_START8)
86479 #define G_START8(x) (((x) >> S_START8) & M_START8)
86480 
86481 #define A_GCACHE_MODE_SEL1 0x51448
86482 #define A_GCACHE_MEMZONE1_REGION1 0x5144c
86483 #define A_GCACHE_MEMZONE1_REGION2 0x51450
86484 #define A_GCACHE_MEMZONE1_REGION3 0x51454
86485 #define A_GCACHE_MEMZONE1_REGION4 0x51458
86486 #define A_GCACHE_MEMZONE1_REGION5 0x5145c
86487 #define A_GCACHE_MEMZONE1_REGION6 0x51460
86488 #define A_GCACHE_MEMZONE1_REGION7 0x51464
86489 #define A_GCACHE_MEMZONE1_REGION8 0x51468
86490 #define A_GCACHE_MEMZONE1_REGION1_MSB 0x5146c
86491 #define A_GCACHE_MEMZONE1_REGION2_MSB 0x51470
86492 #define A_GCACHE_MEMZONE1_REGION3_MSB 0x51474
86493 #define A_GCACHE_MEMZONE1_REGION4_MSB 0x51478
86494 #define A_GCACHE_MEMZONE1_REGION5_MSB 0x5147c
86495 #define A_GCACHE_MEMZONE1_REGION6_MSB 0x51480
86496 #define A_GCACHE_MEMZONE1_REGION7_MSB 0x51484
86497 #define A_GCACHE_MEMZONE1_REGION8_MSB 0x51488
86498 #define A_GCACHE_HMA_MC1_EN 0x5148c
86499 
86500 #define S_MC1_EN    1
86501 #define V_MC1_EN(x) ((x) << S_MC1_EN)
86502 #define F_MC1_EN    V_MC1_EN(1U)
86503 
86504 #define S_HMA_EN    0
86505 #define V_HMA_EN(x) ((x) << S_HMA_EN)
86506 #define F_HMA_EN    V_HMA_EN(1U)
86507 
86508 #define A_GCACHE_P_BIST_CMD 0x51490
86509 #define A_GCACHE_P_BIST_CMD_ADDR 0x51494
86510 #define A_GCACHE_P_BIST_CMD_LEN 0x51498
86511 #define A_GCACHE_P_BIST_DATA_PATTERN 0x5149c
86512 #define A_GCACHE_P_BIST_USER_WDATA0 0x514a0
86513 #define A_GCACHE_P_BIST_USER_WDATA1 0x514a4
86514 #define A_GCACHE_P_BIST_USER_WDATA2 0x514a8
86515 #define A_GCACHE_P_BIST_NUM_ERR 0x514ac
86516 #define A_GCACHE_P_BIST_ERR_FIRST_ADDR 0x514b0
86517 #define A_GCACHE_P_BIST_STATUS_RDATA 0x514b4
86518 #define A_GCACHE_P_BIST_CRC_SEED 0x514fc
86519 #define A_GCACHE_CACHE_SIZE 0x51500
86520 
86521 #define S_HMA_2MB    1
86522 #define V_HMA_2MB(x) ((x) << S_HMA_2MB)
86523 #define F_HMA_2MB    V_HMA_2MB(1U)
86524 
86525 #define S_MC0_2MB    0
86526 #define V_MC0_2MB(x) ((x) << S_MC0_2MB)
86527 #define F_MC0_2MB    V_MC0_2MB(1U)
86528 
86529 #define A_GCACHE_HINT_MAPPING 0x51504
86530 
86531 #define S_CLIENT_HINT_EN    16
86532 #define M_CLIENT_HINT_EN    0x7fffU
86533 #define V_CLIENT_HINT_EN(x) ((x) << S_CLIENT_HINT_EN)
86534 #define G_CLIENT_HINT_EN(x) (((x) >> S_CLIENT_HINT_EN) & M_CLIENT_HINT_EN)
86535 
86536 #define S_HINT_ADDR_SPLIT_EN    8
86537 #define V_HINT_ADDR_SPLIT_EN(x) ((x) << S_HINT_ADDR_SPLIT_EN)
86538 #define F_HINT_ADDR_SPLIT_EN    V_HINT_ADDR_SPLIT_EN(1U)
86539 
86540 #define S_TP_HINT_HMA_MC    2
86541 #define V_TP_HINT_HMA_MC(x) ((x) << S_TP_HINT_HMA_MC)
86542 #define F_TP_HINT_HMA_MC    V_TP_HINT_HMA_MC(1U)
86543 
86544 #define S_CIM_HINT_HMA_MC    1
86545 #define V_CIM_HINT_HMA_MC(x) ((x) << S_CIM_HINT_HMA_MC)
86546 #define F_CIM_HINT_HMA_MC    V_CIM_HINT_HMA_MC(1U)
86547 
86548 #define S_LE_HINT_HMA_MC    0
86549 #define V_LE_HINT_HMA_MC(x) ((x) << S_LE_HINT_HMA_MC)
86550 #define F_LE_HINT_HMA_MC    V_LE_HINT_HMA_MC(1U)
86551 
86552 #define A_GCACHE_PERF_EN 0x51508
86553 
86554 #define S_PERF_CLEAR_GC1    3
86555 #define V_PERF_CLEAR_GC1(x) ((x) << S_PERF_CLEAR_GC1)
86556 #define F_PERF_CLEAR_GC1    V_PERF_CLEAR_GC1(1U)
86557 
86558 #define S_PERF_CLEAR_GC0    2
86559 #define V_PERF_CLEAR_GC0(x) ((x) << S_PERF_CLEAR_GC0)
86560 #define F_PERF_CLEAR_GC0    V_PERF_CLEAR_GC0(1U)
86561 
86562 #define S_PERF_EN_GC1    1
86563 #define V_PERF_EN_GC1(x) ((x) << S_PERF_EN_GC1)
86564 #define F_PERF_EN_GC1    V_PERF_EN_GC1(1U)
86565 
86566 #define S_PERF_EN_GC0    0
86567 #define V_PERF_EN_GC0(x) ((x) << S_PERF_EN_GC0)
86568 #define F_PERF_EN_GC0    V_PERF_EN_GC0(1U)
86569 
86570 #define A_GCACHE_PERF_GC0_RD_HIT 0x5150c
86571 #define A_GCACHE_PERF_GC1_RD_HIT 0x51510
86572 #define A_GCACHE_PERF_GC0_WR_HIT 0x51514
86573 #define A_GCACHE_PERF_GC1_WR_HIT 0x51518
86574 #define A_GCACHE_PERF_GC0_RD_MISS 0x5151c
86575 #define A_GCACHE_PERF_GC1_RD_MISS 0x51520
86576 #define A_GCACHE_PERF_GC0_WR_MISS 0x51524
86577 #define A_GCACHE_PERF_GC1_WR_MISS 0x51528
86578 #define A_GCACHE_PERF_GC0_RD_REQ 0x5152c
86579 #define A_GCACHE_PERF_GC1_RD_REQ 0x51530
86580 #define A_GCACHE_PERF_GC0_WR_REQ 0x51534
86581 #define A_GCACHE_PERF_GC1_WR_REQ 0x51538
86582 #define A_GCACHE_PAR_CAUSE 0x5153c
86583 
86584 #define S_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE    27
86585 #define V_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE(x) ((x) << S_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE)
86586 #define F_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE    V_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE(1U)
86587 
86588 #define S_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE    26
86589 #define V_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE(x) ((x) << S_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE)
86590 #define F_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE    V_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE(1U)
86591 
86592 #define S_GC1_WQDATA_FIFO_PERR_PAR_CAUSE    25
86593 #define V_GC1_WQDATA_FIFO_PERR_PAR_CAUSE(x) ((x) << S_GC1_WQDATA_FIFO_PERR_PAR_CAUSE)
86594 #define F_GC1_WQDATA_FIFO_PERR_PAR_CAUSE    V_GC1_WQDATA_FIFO_PERR_PAR_CAUSE(1U)
86595 
86596 #define S_GC0_WQDATA_FIFO_PERR_PAR_CAUSE    24
86597 #define V_GC0_WQDATA_FIFO_PERR_PAR_CAUSE(x) ((x) << S_GC0_WQDATA_FIFO_PERR_PAR_CAUSE)
86598 #define F_GC0_WQDATA_FIFO_PERR_PAR_CAUSE    V_GC0_WQDATA_FIFO_PERR_PAR_CAUSE(1U)
86599 
86600 #define S_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE    23
86601 #define V_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE(x) ((x) << S_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE)
86602 #define F_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE    V_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE(1U)
86603 
86604 #define S_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE    22
86605 #define V_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE(x) ((x) << S_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE)
86606 #define F_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE    V_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE(1U)
86607 
86608 #define S_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE    21
86609 #define V_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE(x) ((x) << S_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE)
86610 #define F_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE    V_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE(1U)
86611 
86612 #define S_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE    20
86613 #define V_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE(x) ((x) << S_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE)
86614 #define F_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE    V_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE(1U)
86615 
86616 #define S_GC1_RSP_PERR_PAR_CAUSE    19
86617 #define V_GC1_RSP_PERR_PAR_CAUSE(x) ((x) << S_GC1_RSP_PERR_PAR_CAUSE)
86618 #define F_GC1_RSP_PERR_PAR_CAUSE    V_GC1_RSP_PERR_PAR_CAUSE(1U)
86619 
86620 #define S_GC0_RSP_PERR_PAR_CAUSE    18
86621 #define V_GC0_RSP_PERR_PAR_CAUSE(x) ((x) << S_GC0_RSP_PERR_PAR_CAUSE)
86622 #define F_GC0_RSP_PERR_PAR_CAUSE    V_GC0_RSP_PERR_PAR_CAUSE(1U)
86623 
86624 #define S_GC1_LRU_UERR_PAR_CAUSE    17
86625 #define V_GC1_LRU_UERR_PAR_CAUSE(x) ((x) << S_GC1_LRU_UERR_PAR_CAUSE)
86626 #define F_GC1_LRU_UERR_PAR_CAUSE    V_GC1_LRU_UERR_PAR_CAUSE(1U)
86627 
86628 #define S_GC0_LRU_UERR_PAR_CAUSE    16
86629 #define V_GC0_LRU_UERR_PAR_CAUSE(x) ((x) << S_GC0_LRU_UERR_PAR_CAUSE)
86630 #define F_GC0_LRU_UERR_PAR_CAUSE    V_GC0_LRU_UERR_PAR_CAUSE(1U)
86631 
86632 #define S_GC1_TAG_UERR_PAR_CAUSE    15
86633 #define V_GC1_TAG_UERR_PAR_CAUSE(x) ((x) << S_GC1_TAG_UERR_PAR_CAUSE)
86634 #define F_GC1_TAG_UERR_PAR_CAUSE    V_GC1_TAG_UERR_PAR_CAUSE(1U)
86635 
86636 #define S_GC0_TAG_UERR_PAR_CAUSE    14
86637 #define V_GC0_TAG_UERR_PAR_CAUSE(x) ((x) << S_GC0_TAG_UERR_PAR_CAUSE)
86638 #define F_GC0_TAG_UERR_PAR_CAUSE    V_GC0_TAG_UERR_PAR_CAUSE(1U)
86639 
86640 #define S_GC1_LRU_CERR_PAR_CAUSE    13
86641 #define V_GC1_LRU_CERR_PAR_CAUSE(x) ((x) << S_GC1_LRU_CERR_PAR_CAUSE)
86642 #define F_GC1_LRU_CERR_PAR_CAUSE    V_GC1_LRU_CERR_PAR_CAUSE(1U)
86643 
86644 #define S_GC0_LRU_CERR_PAR_CAUSE    12
86645 #define V_GC0_LRU_CERR_PAR_CAUSE(x) ((x) << S_GC0_LRU_CERR_PAR_CAUSE)
86646 #define F_GC0_LRU_CERR_PAR_CAUSE    V_GC0_LRU_CERR_PAR_CAUSE(1U)
86647 
86648 #define S_GC1_TAG_CERR_PAR_CAUSE    11
86649 #define V_GC1_TAG_CERR_PAR_CAUSE(x) ((x) << S_GC1_TAG_CERR_PAR_CAUSE)
86650 #define F_GC1_TAG_CERR_PAR_CAUSE    V_GC1_TAG_CERR_PAR_CAUSE(1U)
86651 
86652 #define S_GC0_TAG_CERR_PAR_CAUSE    10
86653 #define V_GC0_TAG_CERR_PAR_CAUSE(x) ((x) << S_GC0_TAG_CERR_PAR_CAUSE)
86654 #define F_GC0_TAG_CERR_PAR_CAUSE    V_GC0_TAG_CERR_PAR_CAUSE(1U)
86655 
86656 #define S_GC1_CE_PAR_CAUSE    9
86657 #define V_GC1_CE_PAR_CAUSE(x) ((x) << S_GC1_CE_PAR_CAUSE)
86658 #define F_GC1_CE_PAR_CAUSE    V_GC1_CE_PAR_CAUSE(1U)
86659 
86660 #define S_GC0_CE_PAR_CAUSE    8
86661 #define V_GC0_CE_PAR_CAUSE(x) ((x) << S_GC0_CE_PAR_CAUSE)
86662 #define F_GC0_CE_PAR_CAUSE    V_GC0_CE_PAR_CAUSE(1U)
86663 
86664 #define S_GC1_UE_PAR_CAUSE    7
86665 #define V_GC1_UE_PAR_CAUSE(x) ((x) << S_GC1_UE_PAR_CAUSE)
86666 #define F_GC1_UE_PAR_CAUSE    V_GC1_UE_PAR_CAUSE(1U)
86667 
86668 #define S_GC0_UE_PAR_CAUSE    6
86669 #define V_GC0_UE_PAR_CAUSE(x) ((x) << S_GC0_UE_PAR_CAUSE)
86670 #define F_GC0_UE_PAR_CAUSE    V_GC0_UE_PAR_CAUSE(1U)
86671 
86672 #define S_GC1_CMD_PAR_CAUSE    5
86673 #define V_GC1_CMD_PAR_CAUSE(x) ((x) << S_GC1_CMD_PAR_CAUSE)
86674 #define F_GC1_CMD_PAR_CAUSE    V_GC1_CMD_PAR_CAUSE(1U)
86675 
86676 #define S_GC1_DATA_PAR_CAUSE    4
86677 #define V_GC1_DATA_PAR_CAUSE(x) ((x) << S_GC1_DATA_PAR_CAUSE)
86678 #define F_GC1_DATA_PAR_CAUSE    V_GC1_DATA_PAR_CAUSE(1U)
86679 
86680 #define S_GC0_CMD_PAR_CAUSE    3
86681 #define V_GC0_CMD_PAR_CAUSE(x) ((x) << S_GC0_CMD_PAR_CAUSE)
86682 #define F_GC0_CMD_PAR_CAUSE    V_GC0_CMD_PAR_CAUSE(1U)
86683 
86684 #define S_GC0_DATA_PAR_CAUSE    2
86685 #define V_GC0_DATA_PAR_CAUSE(x) ((x) << S_GC0_DATA_PAR_CAUSE)
86686 #define F_GC0_DATA_PAR_CAUSE    V_GC0_DATA_PAR_CAUSE(1U)
86687 
86688 #define S_ILLADDRACCESS1_PAR_CAUSE    1
86689 #define V_ILLADDRACCESS1_PAR_CAUSE(x) ((x) << S_ILLADDRACCESS1_PAR_CAUSE)
86690 #define F_ILLADDRACCESS1_PAR_CAUSE    V_ILLADDRACCESS1_PAR_CAUSE(1U)
86691 
86692 #define S_ILLADDRACCESS0_PAR_CAUSE    0
86693 #define V_ILLADDRACCESS0_PAR_CAUSE(x) ((x) << S_ILLADDRACCESS0_PAR_CAUSE)
86694 #define F_ILLADDRACCESS0_PAR_CAUSE    V_ILLADDRACCESS0_PAR_CAUSE(1U)
86695 
86696 #define A_GCACHE_PAR_ENABLE 0x51540
86697 
86698 #define S_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE    27
86699 #define V_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE(x) ((x) << S_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE)
86700 #define F_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE    V_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE(1U)
86701 
86702 #define S_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE    26
86703 #define V_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE(x) ((x) << S_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE)
86704 #define F_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE    V_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE(1U)
86705 
86706 #define S_GC1_WQDATA_FIFO_PERR_PAR_ENABLE    25
86707 #define V_GC1_WQDATA_FIFO_PERR_PAR_ENABLE(x) ((x) << S_GC1_WQDATA_FIFO_PERR_PAR_ENABLE)
86708 #define F_GC1_WQDATA_FIFO_PERR_PAR_ENABLE    V_GC1_WQDATA_FIFO_PERR_PAR_ENABLE(1U)
86709 
86710 #define S_GC0_WQDATA_FIFO_PERR_PAR_ENABLE    24
86711 #define V_GC0_WQDATA_FIFO_PERR_PAR_ENABLE(x) ((x) << S_GC0_WQDATA_FIFO_PERR_PAR_ENABLE)
86712 #define F_GC0_WQDATA_FIFO_PERR_PAR_ENABLE    V_GC0_WQDATA_FIFO_PERR_PAR_ENABLE(1U)
86713 
86714 #define S_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE    23
86715 #define V_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE(x) ((x) << S_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE)
86716 #define F_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE    V_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE(1U)
86717 
86718 #define S_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE    22
86719 #define V_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE(x) ((x) << S_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE)
86720 #define F_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE    V_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE(1U)
86721 
86722 #define S_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE    21
86723 #define V_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE(x) ((x) << S_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE)
86724 #define F_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE    V_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE(1U)
86725 
86726 #define S_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE    20
86727 #define V_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE(x) ((x) << S_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE)
86728 #define F_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE    V_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE(1U)
86729 
86730 #define S_GC1_RSP_PERR_PAR_ENABLE    19
86731 #define V_GC1_RSP_PERR_PAR_ENABLE(x) ((x) << S_GC1_RSP_PERR_PAR_ENABLE)
86732 #define F_GC1_RSP_PERR_PAR_ENABLE    V_GC1_RSP_PERR_PAR_ENABLE(1U)
86733 
86734 #define S_GC0_RSP_PERR_PAR_ENABLE    18
86735 #define V_GC0_RSP_PERR_PAR_ENABLE(x) ((x) << S_GC0_RSP_PERR_PAR_ENABLE)
86736 #define F_GC0_RSP_PERR_PAR_ENABLE    V_GC0_RSP_PERR_PAR_ENABLE(1U)
86737 
86738 #define S_GC1_LRU_UERR_PAR_ENABLE    17
86739 #define V_GC1_LRU_UERR_PAR_ENABLE(x) ((x) << S_GC1_LRU_UERR_PAR_ENABLE)
86740 #define F_GC1_LRU_UERR_PAR_ENABLE    V_GC1_LRU_UERR_PAR_ENABLE(1U)
86741 
86742 #define S_GC0_LRU_UERR_PAR_ENABLE    16
86743 #define V_GC0_LRU_UERR_PAR_ENABLE(x) ((x) << S_GC0_LRU_UERR_PAR_ENABLE)
86744 #define F_GC0_LRU_UERR_PAR_ENABLE    V_GC0_LRU_UERR_PAR_ENABLE(1U)
86745 
86746 #define S_GC1_TAG_UERR_PAR_ENABLE    15
86747 #define V_GC1_TAG_UERR_PAR_ENABLE(x) ((x) << S_GC1_TAG_UERR_PAR_ENABLE)
86748 #define F_GC1_TAG_UERR_PAR_ENABLE    V_GC1_TAG_UERR_PAR_ENABLE(1U)
86749 
86750 #define S_GC0_TAG_UERR_PAR_ENABLE    14
86751 #define V_GC0_TAG_UERR_PAR_ENABLE(x) ((x) << S_GC0_TAG_UERR_PAR_ENABLE)
86752 #define F_GC0_TAG_UERR_PAR_ENABLE    V_GC0_TAG_UERR_PAR_ENABLE(1U)
86753 
86754 #define S_GC1_LRU_CERR_PAR_ENABLE    13
86755 #define V_GC1_LRU_CERR_PAR_ENABLE(x) ((x) << S_GC1_LRU_CERR_PAR_ENABLE)
86756 #define F_GC1_LRU_CERR_PAR_ENABLE    V_GC1_LRU_CERR_PAR_ENABLE(1U)
86757 
86758 #define S_GC0_LRU_CERR_PAR_ENABLE    12
86759 #define V_GC0_LRU_CERR_PAR_ENABLE(x) ((x) << S_GC0_LRU_CERR_PAR_ENABLE)
86760 #define F_GC0_LRU_CERR_PAR_ENABLE    V_GC0_LRU_CERR_PAR_ENABLE(1U)
86761 
86762 #define S_GC1_TAG_CERR_PAR_ENABLE    11
86763 #define V_GC1_TAG_CERR_PAR_ENABLE(x) ((x) << S_GC1_TAG_CERR_PAR_ENABLE)
86764 #define F_GC1_TAG_CERR_PAR_ENABLE    V_GC1_TAG_CERR_PAR_ENABLE(1U)
86765 
86766 #define S_GC0_TAG_CERR_PAR_ENABLE    10
86767 #define V_GC0_TAG_CERR_PAR_ENABLE(x) ((x) << S_GC0_TAG_CERR_PAR_ENABLE)
86768 #define F_GC0_TAG_CERR_PAR_ENABLE    V_GC0_TAG_CERR_PAR_ENABLE(1U)
86769 
86770 #define S_GC1_CE_PAR_ENABLE    9
86771 #define V_GC1_CE_PAR_ENABLE(x) ((x) << S_GC1_CE_PAR_ENABLE)
86772 #define F_GC1_CE_PAR_ENABLE    V_GC1_CE_PAR_ENABLE(1U)
86773 
86774 #define S_GC0_CE_PAR_ENABLE    8
86775 #define V_GC0_CE_PAR_ENABLE(x) ((x) << S_GC0_CE_PAR_ENABLE)
86776 #define F_GC0_CE_PAR_ENABLE    V_GC0_CE_PAR_ENABLE(1U)
86777 
86778 #define S_GC1_UE_PAR_ENABLE    7
86779 #define V_GC1_UE_PAR_ENABLE(x) ((x) << S_GC1_UE_PAR_ENABLE)
86780 #define F_GC1_UE_PAR_ENABLE    V_GC1_UE_PAR_ENABLE(1U)
86781 
86782 #define S_GC0_UE_PAR_ENABLE    6
86783 #define V_GC0_UE_PAR_ENABLE(x) ((x) << S_GC0_UE_PAR_ENABLE)
86784 #define F_GC0_UE_PAR_ENABLE    V_GC0_UE_PAR_ENABLE(1U)
86785 
86786 #define S_GC1_CMD_PAR_ENABLE    5
86787 #define V_GC1_CMD_PAR_ENABLE(x) ((x) << S_GC1_CMD_PAR_ENABLE)
86788 #define F_GC1_CMD_PAR_ENABLE    V_GC1_CMD_PAR_ENABLE(1U)
86789 
86790 #define S_GC1_DATA_PAR_ENABLE    4
86791 #define V_GC1_DATA_PAR_ENABLE(x) ((x) << S_GC1_DATA_PAR_ENABLE)
86792 #define F_GC1_DATA_PAR_ENABLE    V_GC1_DATA_PAR_ENABLE(1U)
86793 
86794 #define S_GC0_CMD_PAR_ENABLE    3
86795 #define V_GC0_CMD_PAR_ENABLE(x) ((x) << S_GC0_CMD_PAR_ENABLE)
86796 #define F_GC0_CMD_PAR_ENABLE    V_GC0_CMD_PAR_ENABLE(1U)
86797 
86798 #define S_GC0_DATA_PAR_ENABLE    2
86799 #define V_GC0_DATA_PAR_ENABLE(x) ((x) << S_GC0_DATA_PAR_ENABLE)
86800 #define F_GC0_DATA_PAR_ENABLE    V_GC0_DATA_PAR_ENABLE(1U)
86801 
86802 #define S_ILLADDRACCESS1_PAR_ENABLE    1
86803 #define V_ILLADDRACCESS1_PAR_ENABLE(x) ((x) << S_ILLADDRACCESS1_PAR_ENABLE)
86804 #define F_ILLADDRACCESS1_PAR_ENABLE    V_ILLADDRACCESS1_PAR_ENABLE(1U)
86805 
86806 #define S_ILLADDRACCESS0_PAR_ENABLE    0
86807 #define V_ILLADDRACCESS0_PAR_ENABLE(x) ((x) << S_ILLADDRACCESS0_PAR_ENABLE)
86808 #define F_ILLADDRACCESS0_PAR_ENABLE    V_ILLADDRACCESS0_PAR_ENABLE(1U)
86809 
86810 #define A_GCACHE_INT_ENABLE 0x51544
86811 
86812 #define S_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE    27
86813 #define V_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE(x) ((x) << S_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE)
86814 #define F_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE    V_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE(1U)
86815 
86816 #define S_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE    26
86817 #define V_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE(x) ((x) << S_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE)
86818 #define F_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE    V_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE(1U)
86819 
86820 #define S_GC1_WQDATA_FIFO_PERR_INT_ENABLE    25
86821 #define V_GC1_WQDATA_FIFO_PERR_INT_ENABLE(x) ((x) << S_GC1_WQDATA_FIFO_PERR_INT_ENABLE)
86822 #define F_GC1_WQDATA_FIFO_PERR_INT_ENABLE    V_GC1_WQDATA_FIFO_PERR_INT_ENABLE(1U)
86823 
86824 #define S_GC0_WQDATA_FIFO_PERR_INT_ENABLE    24
86825 #define V_GC0_WQDATA_FIFO_PERR_INT_ENABLE(x) ((x) << S_GC0_WQDATA_FIFO_PERR_INT_ENABLE)
86826 #define F_GC0_WQDATA_FIFO_PERR_INT_ENABLE    V_GC0_WQDATA_FIFO_PERR_INT_ENABLE(1U)
86827 
86828 #define S_GC1_RDTAG_QUEUE_PERR_INT_ENABLE    23
86829 #define V_GC1_RDTAG_QUEUE_PERR_INT_ENABLE(x) ((x) << S_GC1_RDTAG_QUEUE_PERR_INT_ENABLE)
86830 #define F_GC1_RDTAG_QUEUE_PERR_INT_ENABLE    V_GC1_RDTAG_QUEUE_PERR_INT_ENABLE(1U)
86831 
86832 #define S_GC0_RDTAG_QUEUE_PERR_INT_ENABLE    22
86833 #define V_GC0_RDTAG_QUEUE_PERR_INT_ENABLE(x) ((x) << S_GC0_RDTAG_QUEUE_PERR_INT_ENABLE)
86834 #define F_GC0_RDTAG_QUEUE_PERR_INT_ENABLE    V_GC0_RDTAG_QUEUE_PERR_INT_ENABLE(1U)
86835 
86836 #define S_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE    21
86837 #define V_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE(x) ((x) << S_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE)
86838 #define F_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE    V_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE(1U)
86839 
86840 #define S_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE    20
86841 #define V_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE(x) ((x) << S_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE)
86842 #define F_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE    V_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE(1U)
86843 
86844 #define S_GC1_RSP_PERR_INT_ENABLE    19
86845 #define V_GC1_RSP_PERR_INT_ENABLE(x) ((x) << S_GC1_RSP_PERR_INT_ENABLE)
86846 #define F_GC1_RSP_PERR_INT_ENABLE    V_GC1_RSP_PERR_INT_ENABLE(1U)
86847 
86848 #define S_GC0_RSP_PERR_INT_ENABLE    18
86849 #define V_GC0_RSP_PERR_INT_ENABLE(x) ((x) << S_GC0_RSP_PERR_INT_ENABLE)
86850 #define F_GC0_RSP_PERR_INT_ENABLE    V_GC0_RSP_PERR_INT_ENABLE(1U)
86851 
86852 #define S_GC1_LRU_UERR_INT_ENABLE    17
86853 #define V_GC1_LRU_UERR_INT_ENABLE(x) ((x) << S_GC1_LRU_UERR_INT_ENABLE)
86854 #define F_GC1_LRU_UERR_INT_ENABLE    V_GC1_LRU_UERR_INT_ENABLE(1U)
86855 
86856 #define S_GC0_LRU_UERR_INT_ENABLE    16
86857 #define V_GC0_LRU_UERR_INT_ENABLE(x) ((x) << S_GC0_LRU_UERR_INT_ENABLE)
86858 #define F_GC0_LRU_UERR_INT_ENABLE    V_GC0_LRU_UERR_INT_ENABLE(1U)
86859 
86860 #define S_GC1_TAG_UERR_INT_ENABLE    15
86861 #define V_GC1_TAG_UERR_INT_ENABLE(x) ((x) << S_GC1_TAG_UERR_INT_ENABLE)
86862 #define F_GC1_TAG_UERR_INT_ENABLE    V_GC1_TAG_UERR_INT_ENABLE(1U)
86863 
86864 #define S_GC0_TAG_UERR_INT_ENABLE    14
86865 #define V_GC0_TAG_UERR_INT_ENABLE(x) ((x) << S_GC0_TAG_UERR_INT_ENABLE)
86866 #define F_GC0_TAG_UERR_INT_ENABLE    V_GC0_TAG_UERR_INT_ENABLE(1U)
86867 
86868 #define S_GC1_LRU_CERR_INT_ENABLE    13
86869 #define V_GC1_LRU_CERR_INT_ENABLE(x) ((x) << S_GC1_LRU_CERR_INT_ENABLE)
86870 #define F_GC1_LRU_CERR_INT_ENABLE    V_GC1_LRU_CERR_INT_ENABLE(1U)
86871 
86872 #define S_GC0_LRU_CERR_INT_ENABLE    12
86873 #define V_GC0_LRU_CERR_INT_ENABLE(x) ((x) << S_GC0_LRU_CERR_INT_ENABLE)
86874 #define F_GC0_LRU_CERR_INT_ENABLE    V_GC0_LRU_CERR_INT_ENABLE(1U)
86875 
86876 #define S_GC1_TAG_CERR_INT_ENABLE    11
86877 #define V_GC1_TAG_CERR_INT_ENABLE(x) ((x) << S_GC1_TAG_CERR_INT_ENABLE)
86878 #define F_GC1_TAG_CERR_INT_ENABLE    V_GC1_TAG_CERR_INT_ENABLE(1U)
86879 
86880 #define S_GC0_TAG_CERR_INT_ENABLE    10
86881 #define V_GC0_TAG_CERR_INT_ENABLE(x) ((x) << S_GC0_TAG_CERR_INT_ENABLE)
86882 #define F_GC0_TAG_CERR_INT_ENABLE    V_GC0_TAG_CERR_INT_ENABLE(1U)
86883 
86884 #define S_GC1_CE_INT_ENABLE    9
86885 #define V_GC1_CE_INT_ENABLE(x) ((x) << S_GC1_CE_INT_ENABLE)
86886 #define F_GC1_CE_INT_ENABLE    V_GC1_CE_INT_ENABLE(1U)
86887 
86888 #define S_GC0_CE_INT_ENABLE    8
86889 #define V_GC0_CE_INT_ENABLE(x) ((x) << S_GC0_CE_INT_ENABLE)
86890 #define F_GC0_CE_INT_ENABLE    V_GC0_CE_INT_ENABLE(1U)
86891 
86892 #define S_GC1_UE_INT_ENABLE    7
86893 #define V_GC1_UE_INT_ENABLE(x) ((x) << S_GC1_UE_INT_ENABLE)
86894 #define F_GC1_UE_INT_ENABLE    V_GC1_UE_INT_ENABLE(1U)
86895 
86896 #define S_GC0_UE_INT_ENABLE    6
86897 #define V_GC0_UE_INT_ENABLE(x) ((x) << S_GC0_UE_INT_ENABLE)
86898 #define F_GC0_UE_INT_ENABLE    V_GC0_UE_INT_ENABLE(1U)
86899 
86900 #define S_GC1_CMD_PAR_INT_ENABLE    5
86901 #define V_GC1_CMD_PAR_INT_ENABLE(x) ((x) << S_GC1_CMD_PAR_INT_ENABLE)
86902 #define F_GC1_CMD_PAR_INT_ENABLE    V_GC1_CMD_PAR_INT_ENABLE(1U)
86903 
86904 #define S_GC1_DATA_PAR_INT_ENABLE    4
86905 #define V_GC1_DATA_PAR_INT_ENABLE(x) ((x) << S_GC1_DATA_PAR_INT_ENABLE)
86906 #define F_GC1_DATA_PAR_INT_ENABLE    V_GC1_DATA_PAR_INT_ENABLE(1U)
86907 
86908 #define S_GC0_CMD_PAR_INT_ENABLE    3
86909 #define V_GC0_CMD_PAR_INT_ENABLE(x) ((x) << S_GC0_CMD_PAR_INT_ENABLE)
86910 #define F_GC0_CMD_PAR_INT_ENABLE    V_GC0_CMD_PAR_INT_ENABLE(1U)
86911 
86912 #define S_GC0_DATA_PAR_INT_ENABLE    2
86913 #define V_GC0_DATA_PAR_INT_ENABLE(x) ((x) << S_GC0_DATA_PAR_INT_ENABLE)
86914 #define F_GC0_DATA_PAR_INT_ENABLE    V_GC0_DATA_PAR_INT_ENABLE(1U)
86915 
86916 #define S_ILLADDRACCESS1_INT_ENABLE    1
86917 #define V_ILLADDRACCESS1_INT_ENABLE(x) ((x) << S_ILLADDRACCESS1_INT_ENABLE)
86918 #define F_ILLADDRACCESS1_INT_ENABLE    V_ILLADDRACCESS1_INT_ENABLE(1U)
86919 
86920 #define S_ILLADDRACCESS0_INT_ENABLE    0
86921 #define V_ILLADDRACCESS0_INT_ENABLE(x) ((x) << S_ILLADDRACCESS0_INT_ENABLE)
86922 #define F_ILLADDRACCESS0_INT_ENABLE    V_ILLADDRACCESS0_INT_ENABLE(1U)
86923 
86924 #define A_GCACHE_INT_CAUSE 0x51548
86925 
86926 #define S_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE    27
86927 #define V_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE(x) ((x) << S_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE)
86928 #define F_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE    V_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE(1U)
86929 
86930 #define S_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE    26
86931 #define V_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE(x) ((x) << S_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE)
86932 #define F_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE    V_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE(1U)
86933 
86934 #define S_GC1_WQDATA_FIFO_PERR_INT_CAUSE    25
86935 #define V_GC1_WQDATA_FIFO_PERR_INT_CAUSE(x) ((x) << S_GC1_WQDATA_FIFO_PERR_INT_CAUSE)
86936 #define F_GC1_WQDATA_FIFO_PERR_INT_CAUSE    V_GC1_WQDATA_FIFO_PERR_INT_CAUSE(1U)
86937 
86938 #define S_GC0_WQDATA_FIFO_PERR_INT_CAUSE    24
86939 #define V_GC0_WQDATA_FIFO_PERR_INT_CAUSE(x) ((x) << S_GC0_WQDATA_FIFO_PERR_INT_CAUSE)
86940 #define F_GC0_WQDATA_FIFO_PERR_INT_CAUSE    V_GC0_WQDATA_FIFO_PERR_INT_CAUSE(1U)
86941 
86942 #define S_GC1_RDTAG_QUEUE_PERR_INT_CAUSE    23
86943 #define V_GC1_RDTAG_QUEUE_PERR_INT_CAUSE(x) ((x) << S_GC1_RDTAG_QUEUE_PERR_INT_CAUSE)
86944 #define F_GC1_RDTAG_QUEUE_PERR_INT_CAUSE    V_GC1_RDTAG_QUEUE_PERR_INT_CAUSE(1U)
86945 
86946 #define S_GC0_RDTAG_QUEUE_PERR_INT_CAUSE    22
86947 #define V_GC0_RDTAG_QUEUE_PERR_INT_CAUSE(x) ((x) << S_GC0_RDTAG_QUEUE_PERR_INT_CAUSE)
86948 #define F_GC0_RDTAG_QUEUE_PERR_INT_CAUSE    V_GC0_RDTAG_QUEUE_PERR_INT_CAUSE(1U)
86949 
86950 #define S_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE    21
86951 #define V_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE(x) ((x) << S_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE)
86952 #define F_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE    V_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE(1U)
86953 
86954 #define S_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE    20
86955 #define V_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE(x) ((x) << S_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE)
86956 #define F_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE    V_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE(1U)
86957 
86958 #define S_GC1_RSP_PERR_INT_CAUSE    19
86959 #define V_GC1_RSP_PERR_INT_CAUSE(x) ((x) << S_GC1_RSP_PERR_INT_CAUSE)
86960 #define F_GC1_RSP_PERR_INT_CAUSE    V_GC1_RSP_PERR_INT_CAUSE(1U)
86961 
86962 #define S_GC0_RSP_PERR_INT_CAUSE    18
86963 #define V_GC0_RSP_PERR_INT_CAUSE(x) ((x) << S_GC0_RSP_PERR_INT_CAUSE)
86964 #define F_GC0_RSP_PERR_INT_CAUSE    V_GC0_RSP_PERR_INT_CAUSE(1U)
86965 
86966 #define S_GC1_LRU_UERR_INT_CAUSE    17
86967 #define V_GC1_LRU_UERR_INT_CAUSE(x) ((x) << S_GC1_LRU_UERR_INT_CAUSE)
86968 #define F_GC1_LRU_UERR_INT_CAUSE    V_GC1_LRU_UERR_INT_CAUSE(1U)
86969 
86970 #define S_GC0_LRU_UERR_INT_CAUSE    16
86971 #define V_GC0_LRU_UERR_INT_CAUSE(x) ((x) << S_GC0_LRU_UERR_INT_CAUSE)
86972 #define F_GC0_LRU_UERR_INT_CAUSE    V_GC0_LRU_UERR_INT_CAUSE(1U)
86973 
86974 #define S_GC1_TAG_UERR_INT_CAUSE    15
86975 #define V_GC1_TAG_UERR_INT_CAUSE(x) ((x) << S_GC1_TAG_UERR_INT_CAUSE)
86976 #define F_GC1_TAG_UERR_INT_CAUSE    V_GC1_TAG_UERR_INT_CAUSE(1U)
86977 
86978 #define S_GC0_TAG_UERR_INT_CAUSE    14
86979 #define V_GC0_TAG_UERR_INT_CAUSE(x) ((x) << S_GC0_TAG_UERR_INT_CAUSE)
86980 #define F_GC0_TAG_UERR_INT_CAUSE    V_GC0_TAG_UERR_INT_CAUSE(1U)
86981 
86982 #define S_GC1_LRU_CERR_INT_CAUSE    13
86983 #define V_GC1_LRU_CERR_INT_CAUSE(x) ((x) << S_GC1_LRU_CERR_INT_CAUSE)
86984 #define F_GC1_LRU_CERR_INT_CAUSE    V_GC1_LRU_CERR_INT_CAUSE(1U)
86985 
86986 #define S_GC0_LRU_CERR_INT_CAUSE    12
86987 #define V_GC0_LRU_CERR_INT_CAUSE(x) ((x) << S_GC0_LRU_CERR_INT_CAUSE)
86988 #define F_GC0_LRU_CERR_INT_CAUSE    V_GC0_LRU_CERR_INT_CAUSE(1U)
86989 
86990 #define S_GC1_TAG_CERR_INT_CAUSE    11
86991 #define V_GC1_TAG_CERR_INT_CAUSE(x) ((x) << S_GC1_TAG_CERR_INT_CAUSE)
86992 #define F_GC1_TAG_CERR_INT_CAUSE    V_GC1_TAG_CERR_INT_CAUSE(1U)
86993 
86994 #define S_GC0_TAG_CERR_INT_CAUSE    10
86995 #define V_GC0_TAG_CERR_INT_CAUSE(x) ((x) << S_GC0_TAG_CERR_INT_CAUSE)
86996 #define F_GC0_TAG_CERR_INT_CAUSE    V_GC0_TAG_CERR_INT_CAUSE(1U)
86997 
86998 #define S_GC1_CE_INT_CAUSE    9
86999 #define V_GC1_CE_INT_CAUSE(x) ((x) << S_GC1_CE_INT_CAUSE)
87000 #define F_GC1_CE_INT_CAUSE    V_GC1_CE_INT_CAUSE(1U)
87001 
87002 #define S_GC0_CE_INT_CAUSE    8
87003 #define V_GC0_CE_INT_CAUSE(x) ((x) << S_GC0_CE_INT_CAUSE)
87004 #define F_GC0_CE_INT_CAUSE    V_GC0_CE_INT_CAUSE(1U)
87005 
87006 #define S_GC1_UE_INT_CAUSE    7
87007 #define V_GC1_UE_INT_CAUSE(x) ((x) << S_GC1_UE_INT_CAUSE)
87008 #define F_GC1_UE_INT_CAUSE    V_GC1_UE_INT_CAUSE(1U)
87009 
87010 #define S_GC0_UE_INT_CAUSE    6
87011 #define V_GC0_UE_INT_CAUSE(x) ((x) << S_GC0_UE_INT_CAUSE)
87012 #define F_GC0_UE_INT_CAUSE    V_GC0_UE_INT_CAUSE(1U)
87013 
87014 #define S_GC1_CMD_PAR_INT_CAUSE    5
87015 #define V_GC1_CMD_PAR_INT_CAUSE(x) ((x) << S_GC1_CMD_PAR_INT_CAUSE)
87016 #define F_GC1_CMD_PAR_INT_CAUSE    V_GC1_CMD_PAR_INT_CAUSE(1U)
87017 
87018 #define S_GC1_DATA_PAR_INT_CAUSE    4
87019 #define V_GC1_DATA_PAR_INT_CAUSE(x) ((x) << S_GC1_DATA_PAR_INT_CAUSE)
87020 #define F_GC1_DATA_PAR_INT_CAUSE    V_GC1_DATA_PAR_INT_CAUSE(1U)
87021 
87022 #define S_GC0_CMD_PAR_INT_CAUSE    3
87023 #define V_GC0_CMD_PAR_INT_CAUSE(x) ((x) << S_GC0_CMD_PAR_INT_CAUSE)
87024 #define F_GC0_CMD_PAR_INT_CAUSE    V_GC0_CMD_PAR_INT_CAUSE(1U)
87025 
87026 #define S_GC0_DATA_PAR_INT_CAUSE    2
87027 #define V_GC0_DATA_PAR_INT_CAUSE(x) ((x) << S_GC0_DATA_PAR_INT_CAUSE)
87028 #define F_GC0_DATA_PAR_INT_CAUSE    V_GC0_DATA_PAR_INT_CAUSE(1U)
87029 
87030 #define S_ILLADDRACCESS1_INT_CAUSE    1
87031 #define V_ILLADDRACCESS1_INT_CAUSE(x) ((x) << S_ILLADDRACCESS1_INT_CAUSE)
87032 #define F_ILLADDRACCESS1_INT_CAUSE    V_ILLADDRACCESS1_INT_CAUSE(1U)
87033 
87034 #define S_ILLADDRACCESS0_INT_CAUSE    0
87035 #define V_ILLADDRACCESS0_INT_CAUSE(x) ((x) << S_ILLADDRACCESS0_INT_CAUSE)
87036 #define F_ILLADDRACCESS0_INT_CAUSE    V_ILLADDRACCESS0_INT_CAUSE(1U)
87037 
87038 #define A_GCACHE_DBG_SEL_CTRL 0x51550
87039 
87040 #define S_DBG_SEL_CTRLSEL_OVR_EN    31
87041 #define V_DBG_SEL_CTRLSEL_OVR_EN(x) ((x) << S_DBG_SEL_CTRLSEL_OVR_EN)
87042 #define F_DBG_SEL_CTRLSEL_OVR_EN    V_DBG_SEL_CTRLSEL_OVR_EN(1U)
87043 
87044 #define S_T7_DEBUG_HI    16
87045 #define V_T7_DEBUG_HI(x) ((x) << S_T7_DEBUG_HI)
87046 #define F_T7_DEBUG_HI    V_T7_DEBUG_HI(1U)
87047 
87048 #define S_DBG_SEL_CTRLSELH    8
87049 #define M_DBG_SEL_CTRLSELH    0xffU
87050 #define V_DBG_SEL_CTRLSELH(x) ((x) << S_DBG_SEL_CTRLSELH)
87051 #define G_DBG_SEL_CTRLSELH(x) (((x) >> S_DBG_SEL_CTRLSELH) & M_DBG_SEL_CTRLSELH)
87052 
87053 #define S_DBG_SEL_CTRLSELL    0
87054 #define M_DBG_SEL_CTRLSELL    0xffU
87055 #define V_DBG_SEL_CTRLSELL(x) ((x) << S_DBG_SEL_CTRLSELL)
87056 #define G_DBG_SEL_CTRLSELL(x) (((x) >> S_DBG_SEL_CTRLSELL) & M_DBG_SEL_CTRLSELL)
87057 
87058 #define A_GCACHE_LOCAL_DEBUG_RPT 0x51554
87059 #define A_GCACHE_DBG_ILL_ACC 0x5155c
87060 #define A_GCACHE_DBG_ILL_ADDR0 0x51560
87061 #define A_GCACHE_DBG_ILL_ADDR1 0x51564
87062 #define A_GCACHE_GC0_DBG_ADDR_0_32 0x51568
87063 #define A_GCACHE_GC0_DBG_ADDR_32_32 0x5156c
87064 #define A_GCACHE_GC0_DBG_ADDR_64_32 0x51570
87065 #define A_GCACHE_GC0_DBG_ADDR_96_32 0x51574
87066 #define A_GCACHE_GC0_DBG_ADDR_0_64 0x51578
87067 #define A_GCACHE_GC0_DBG_ADDR_64_64 0x5157c
87068 #define A_GCACHE_GC0_DBG_ADDR_0_96 0x51580
87069 #define A_GCACHE_GC0_DBG_ADDR_32_96 0x51584
87070 #define A_GCACHE_GC1_DBG_ADDR_0_32 0x5158c
87071 #define A_GCACHE_GC1_DBG_ADDR_32_32 0x51590
87072 #define A_GCACHE_GC1_DBG_ADDR_64_32 0x51594
87073 #define A_GCACHE_GC1_DBG_ADDR_96_32 0x51598
87074 #define A_GCACHE_GC1_DBG_ADDR_0_64 0x5159c
87075 #define A_GCACHE_GC1_DBG_ADDR_64_64 0x515a0
87076 #define A_GCACHE_GC1_DBG_ADDR_0_96 0x515a4
87077 #define A_GCACHE_GC1_DBG_ADDR_32_96 0x515a8
87078 #define A_GCACHE_GC0_DBG_ADDR_32_64 0x515ac
87079 #define A_GCACHE_GC1_DBG_ADDR_32_64 0x515b0
87080 #define A_GCACHE_PERF_GC0_EVICT 0x515b4
87081 #define A_GCACHE_PERF_GC1_EVICT 0x515b8
87082 #define A_GCACHE_PERF_GC0_CE_COUNT 0x515bc
87083 #define A_GCACHE_PERF_GC1_CE_COUNT 0x515c0
87084 #define A_GCACHE_PERF_GC0_UE_COUNT 0x515c4
87085 #define A_GCACHE_PERF_GC1_UE_COUNT 0x515c8
87086 #define A_GCACHE_DBG_CTL 0x515f0
87087 #define A_GCACHE_DBG_DATA 0x515f4
87088