1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Register definitions for the VIA Rhine ethernet adapters 29 */ 30 #ifndef _VRREG_H 31 #define _VRREG_H 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /* 38 * MAC address 39 */ 40 #define VR_ETHERADDR 0x00 41 42 /* 43 * Receive Configuration 44 * The thresholds denote the level in the FIFO before transmission 45 * to host memory starts. 46 */ 47 #define VR_RXCFG 0x06 48 #define VR_RXCFG_ACCEPTERROR (1 << 0) 49 #define VR_RXCFG_ACCEPTRUNT (1 << 1) 50 #define VR_RXCFG_ACCEPTMULTI (1 << 2) 51 #define VR_RXCFG_ACCEPTBROAD (1 << 3) 52 #define VR_RXCFG_PROMISC (1 << 4) 53 #define VR_RXCFG_FIFO_THRESHOLD_0 (1 << 5) 54 #define VR_RXCFG_FIFO_THRESHOLD_1 (1 << 6) 55 #define VR_RXCFG_FIFO_THRESHOLD_2 (1 << 7) 56 #define VR_RXCFG_FIFO_THRESHOLD_BITS (VR_RXCFG_FIFO_THRESHOLD_0 | \ 57 VR_RXCFG_FIFO_THRESHOLD_1 | \ 58 VR_RXCFG_FIFO_THRESHOLD_2) 59 #define VR_RXCFG_FIFO_THRESHOLD_64 (0) 60 #define VR_RXCFG_FIFO_THRESHOLD_32 (VR_RXCFG_FIFO_THRESHOLD_0) 61 #define VR_RXCFG_FIFO_THRESHOLD_128 (VR_RXCFG_FIFO_THRESHOLD_1) 62 #define VR_RXCFG_FIFO_THRESHOLD_256 (VR_RXCFG_FIFO_THRESHOLD_0 | \ 63 VR_RXCFG_FIFO_THRESHOLD_1) 64 #define VR_RXCFG_FIFO_THRESHOLD_512 (VR_RXCFG_FIFO_THRESHOLD_2) 65 #define VR_RXCFG_FIFO_THRESHOLD_768 (VR_RXCFG_FIFO_THRESHOLD_0 | \ 66 VR_RXCFG_FIFO_THRESHOLD_2) 67 #define VR_RXCFG_FIFO_THRESHOLD_1024 (VR_RXCFG_FIFO_THRESHOLD_2 | \ 68 VR_RXCFG_FIFO_THRESHOLD_1) 69 #define VR_RXCFG_FIFO_THRESHOLD_STFW (VR_RXCFG_FIFO_THRESHOLD_BITS) 70 71 /* 72 * Transmit Configuration 73 * The transmission starts when the data in the FIFO reaches the threshold. 74 * Store and Forward means that a transmission starts when a complete frame 75 * is in the FIFO. 76 */ 77 #define VR_TXCFG 0x07 78 #define VR_TXCFG_8021PQ_EN (1 << 0) /* VT6105M */ 79 #define VR_TXCFG_LOOPBACK_0 (1 << 1) 80 #define VR_TXCFG_LOOPBACK_1 (2 << 2) 81 #define VR_TXCFG_BACKOFF_NATIONAL (1 << 3) /* < VT6105M */ 82 #define VR_TXCFG_FIFO_THRESHOLD_0 (1 << 5) 83 #define VR_TXCFG_FIFO_THRESHOLD_1 (1 << 6) 84 #define VR_TXCFG_FIFO_THRESHOLD_2 (1 << 7) 85 #define VR_TXCFG_FIFO_THRESHOLD_BITS (VR_TXCFG_FIFO_THRESHOLD_0 | \ 86 VR_TXCFG_FIFO_THRESHOLD_1 | \ 87 VR_TXCFG_FIFO_THRESHOLD_2) 88 #define VR_TXCFG_FIFO_THRESHOLD_128 (0) 89 #define VR_TXCFG_FIFO_THRESHOLD_256 (VR_TXCFG_FIFO_THRESHOLD_0) 90 #define VR_TXCFG_FIFO_THRESHOLD_512 (VR_TXCFG_FIFO_THRESHOLD_1) 91 #define VR_TXCFG_FIFO_THRESHOLD_1024 (VR_TXCFG_FIFO_THRESHOLD_0 | \ 92 VR_TXCFG_FIFO_THRESHOLD_1) 93 #define VR_TXCFG_FIFO_THRESHOLD_STFW (VR_TXCFG_FIFO_THRESHOLD_BITS) 94 95 /* 96 * Chip control 97 */ 98 #define VR_CTRL0 0x08 99 #define VR_CTRL0_RESERVED (1 << 0) 100 #define VR_CTRL0_DMA_ENABLE (1 << 1) 101 #define VR_CTRL0_DMA_STOP (1 << 2) 102 #define VR_CTRL0_RX_DMA_ENABLE (1 << 3) 103 #define VR_CTRL0_TX_DMA_ENABLE (1 << 4) 104 #define VR_CTRL0_TXPOLL (1 << 5) /* < 6105M */ 105 #define VR_CTRL0_RXPOLL (1 << 6) /* < 6105M */ 106 107 #define VR_CTRL0_DMA_GO (VR_CTRL0_DMA_ENABLE | \ 108 VR_CTRL0_RX_DMA_ENABLE | \ 109 VR_CTRL0_TX_DMA_ENABLE | \ 110 VR_CTRL0_TXPOLL) 111 #define VR_CTRL1 0x09 112 #define VR_CTRL1_RESERVED (1 << 0) 113 #define VR_CTRL1_UNICAST_EN (1 << 1) 114 #define VR_CTRL1_MACFULLDUPLEX (1 << 2) 115 #define VR_CTRL1_NOAUTOPOLL (1 << 3) 116 #define VR_CTRL1_RESERVED2 (1 << 4) 117 #define VR_CTRL1_TXPOLL (1 << 5) /* VT6105M */ 118 #define VR_CTRL1_RXPOLL (1 << 6) /* VT6105M */ 119 #define VR_CTRL1_RESET (1 << 7) 120 121 #define VR_T_XQNWAKE 0x0a /* VT6105M */ 122 123 /* 124 * Interrupt Status 125 * This register reflects NIC status 126 * The host reads it to determine the cause of the interrupt 127 * This register must be cleared after power-up 128 */ 129 #define VR_ISR0 0x0C 130 #define VR_ISR0_RX_DONE (1 << 0) 131 #define VR_ISR0_TX_DONE (1 << 1) 132 #define VR_ISR0_RX_ERR (1 << 2) 133 #define VR_ISR0_TX_ERR (1 << 3) 134 #define VR_ISR0_TX_BUF_UFLOW (1 << 4) 135 #define VR_ISR0_RX_LINKERR (1 << 5) 136 #define VR_ISR0_BUSERR (1 << 6) 137 #define VR_ISR0_STATSMAX (1 << 7) 138 #define VR_ISR0_RX_EARLY (1 << 8) 139 #define VR_ISR0_TX_FIFO_UFLOW (1 << 9) 140 #define VR_ISR0_RX_FIFO_OFLOW (1 << 10) 141 #define VR_ISR0_RX_DROPPED (1 << 11) 142 #define VR_ISR0_RX_NOBUF (1 << 12) 143 #define VR_ISR0_TX_ABORT (1 << 13) 144 #define VR_ISR0_LINKSTATUS (1 << 14) 145 #define VR_ISR0_GENERAL (1 << 15) 146 147 /* 148 * Interrupt Configuration 149 * All bits in this register correspond to the bits in the Interrupt Status 150 * register Setting individual bits will enable the corresponding interrupt 151 * This register defaults to all zeros on power up 152 */ 153 #define VR_ICR0 0x0E 154 #define VR_ICR0_RX_DONE VR_ISR0_RX_DONE 155 #define VR_ICR0_TX_DONE VR_ISR0_TX_DONE 156 #define VR_ICR0_RX_ERR VR_ISR0_RX_ERR 157 #define VR_ICR0_TX_ERR VR_ISR0_TX_ERR 158 #define VR_ICR0_TX_BUF_UFLOW VR_ISR0_TX_BUF_UFLOW 159 #define VR_ICR0_RX_LINKERR VR_ISR0_RX_LINKERR 160 #define VR_ICR0_BUSERR VR_ISR0_BUSERR 161 #define VR_ICR0_STATSMAX VR_ISR0_STATSMAX 162 #define VR_ICR0_RX_EARLY VR_ISR0_RX_EARLY 163 #define VR_ICR0_TX_FIFO_UFLOW VR_ISR0_TX_FIFO_UFLOW 164 #define VR_ICR0_RX_FIFO_OFLOW VR_ISR0_RX_FIFO_OFLOW 165 #define VR_ICR0_RX_DROPPED VR_ISR0_RX_DROPPED 166 #define VR_ICR0_RX_NOBUF VR_ISR0_RX_NOBUF 167 #define VR_ICR0_TX_ABORT VR_ISR0_TX_ABORT 168 #define VR_ICR0_LINKSTATUS VR_ISR0_LINKSTATUS 169 #define VR_ICR0_GENERAL VR_ISR0_GENERAL 170 171 /* 172 * Mulicast address registers (MAR), 8 bytes 173 */ 174 #define VR_MAR0 0x10 /* - 0x13 */ 175 #define VR_MAR1 0x14 /* - 0x17 */ 176 177 /* 178 * VT6105M has a multicast/vlan filter and the hash bits are also used as 179 * CAM data port 180 */ 181 #define VR_MCAM0 0x10 /* VT6105M */ 182 #define VR_MCAM1 0x11 183 #define VR_MCAM2 0x12 184 #define VR_MCAM3 0x13 185 #define VR_MCAM4 0x14 186 #define VR_MCAM5 0x15 187 #define VR_VCAM0 0x16 188 #define VR_VCAM1 0x17 189 190 /* 191 * Start addresses of receive and transmit ring 192 */ 193 #define VR_RXADDR 0x18 /* - 0x1B */ 194 #define VR_TXADDR 0x1C /* - 0x1F */ 195 196 /* 197 * VT6105M has 8 TX queues 198 */ 199 #define VR_TX7_ADDR 0x1C 200 #define VR_TX6_ADDR 0x20 201 #define VR_TX5_ADDR 0x24 202 #define VR_TX4_ADDR 0x28 203 #define VR_TX3_ADDR 0x2C 204 #define VR_TX2_ADDR 0x30 205 #define VR_TX1_ADDR 0x34 206 #define VR_TX0_ADDR 0x38 207 208 /* 209 * Current and receive- and transmit descriptors. 210 * These are listed in the VT6102 manual but not in the VT6105. 211 */ 212 #define VR_RXCUR_DES0 0x20 /* - 0x23 */ 213 #define VR_RXCUR_DES1 0x24 /* - 0x27 */ 214 #define VR_RXCUR_DES2 0x28 /* - 0x2B */ 215 #define VR_RXCUR_DES3 0x2C /* - 0x2F */ 216 217 /* VIA secrets here */ 218 219 #define VR_INTRLINE 0x3c 220 #define VR_INTRPIN 0x3d 221 222 /* VIA secrets here */ 223 224 #define VR_TXCUR_DES0 0x40 /* - 0x43 */ 225 #define VR_TXCUR_DES1 0x44 /* - 0x47 */ 226 #define VR_TXCUR_DES2 0x48 /* - 0x4B */ 227 #define VR_TXCUR_DES3 0x4C /* - 0x4F */ 228 229 #define VR_MODE0 0x50 230 #define VR_MODE0_QPKTDS 0x80 231 232 #define VR_MODE1 0x51 233 #define VR_FIFOTST 0x51 234 235 /* 236 * These are not in the datasheet but used in the 'fet' driver 237 */ 238 #define VR_MODE2 0x52 239 #define VR_MODE2_PCEROPT 0x80 /* VT6102 only */ 240 #define VR_MODE2_DISABT 0x40 241 #define VR_MODE2_MRDPL 0x08 /* VT6107A1 and above */ 242 #define VR_MODE2_MODE10T 0x02 243 244 #define VR_MODE3 0x53 245 #define VR_MODE3_XONOPT 0x80 246 #define VR_MODE3_TPACEN 0x40 247 #define VR_MODE3_BACKOPT 0x20 248 #define VR_MODE3_DLTSEL 0x10 249 #define VR_MODE3_MIIDMY 0x08 250 #define VR_MODE3_MIION 0x04 251 252 #define VR_PCI_DELAY_TIMER 0x54 253 #define VR_FIFOCMD 0x56 254 #define VR_FIFOSTA 0x57 255 256 /* VIA secrets here */ 257 258 /* 259 * MII Configuration 260 */ 261 #define VR_MIIPHYADDR 0x6C 262 #define VR_MIIPHYADDR_ADDR0 (1 << 0) 263 #define VR_MIIPHYADDR_ADDR1 (1 << 1) 264 #define VR_MIIPHYADDR_ADDR2 (1 << 2) 265 #define VR_MIIPHYADDR_ADDR3 (1 << 3) 266 #define VR_MIIPHYADDR_ADDR4 (1 << 4) 267 #define VR_MIIPHYADDR_ADDRBITS (VR_MIIPHYADDR_ADDR0 | \ 268 VR_MIIPHYADDR_ADDR1 | \ 269 VR_MIIPHYADDR_ADDR2 | \ 270 VR_MIIPHYADDR_ADDR3 | \ 271 VR_MIIPHYADDR_ADDR4) 272 #define VR_MIIPHYADDR_MD_CLOCK_FAST (1 << 5) 273 #define VR_MIIPHYADDR_POLLBITS ((1 << 7) | (1 << 6)) 274 #define VR_MIIPHYADDR_POLL1024 ((0 << 7) | (0 << 6)) 275 #define VR_MIIPHYADDR_POLL512 ((0 << 7) | (1 << 6)) 276 #define VR_MIIPHYADDR_POLL128 ((1 << 7) | (0 << 6)) 277 #define VR_MIIPHYADDR_POLL64 ((1 << 7) | (1 << 6)) 278 279 /* 280 * MII status 281 */ 282 #define VR_MIISR 0x6D 283 #define VR_MIISR_SPEED (1 << 0) /* VT6102 and VT6105 */ 284 #define VR_MIISR_LINKFAIL (1 << 1) /* VT6102 and VT6105 */ 285 #define VR_MIISR_DUPLEX (1 << 2) /* VT6105 only */ 286 #define VR_MIISR_PHYERR (1 << 3) /* VT6102 and VT6105 */ 287 #define VR_MIISR_PHYOPT (1 << 4) /* VT6102 only */ 288 #define VR_MIISR_NWAYLINKOK (1 << 4) /* VT6105 only */ 289 #define VR_MIISR_NWAYPAUSE (1 << 5) /* VT6105M */ 290 #define VR_MIISR_NWAYASMPAUSE (1 << 6) /* VT6105M */ 291 #define VR_MIISR_PHYRST (1 << 7) 292 293 /* 294 * Bus control 295 */ 296 #define VR_BCR0 0x6E /* receive */ 297 #define VR_BCR0_DMA0 (1 << 0) 298 #define VR_BCR0_DMA1 (1 << 1) 299 #define VR_BCR0_DMA2 (1 << 2) 300 #define VR_BCR0_DMABITS (VR_BCR0_DMA0|VR_BCR0_DMA1 | \ 301 VR_BCR0_DMA2) 302 #define VR_BCR0_DMA32 (0) 303 #define VR_BCR0_DMA64 (VR_BCR0_DMA0) 304 #define VR_BCR0_DMA128 (VR_BCR0_DMA1) 305 #define VR_BCR0_DMA256 (VR_BCR0_DMA0|VR_BCR0_DMA1) 306 #define VR_BCR0_DMA512 (VR_BCR0_DMA2) 307 #define VR_BCR0_DMA1024 (VR_BCR0_DMA0|VR_BCR0_DMA2) 308 #define VR_BCR0_DMASTFW (VR_BCR0_DMABITS) 309 #define VR_BCR0_RX_FIFO_THRESHOLD_0 (1 << 3) 310 #define VR_BCR0_RX_FIFO_THRESHOLD_1 (1 << 4) 311 #define VR_BCR0_RX_FIFO_THRESHOLD_2 (1 << 5) 312 #define VR_BCR0_RX_FIFO_THRESHOLD_BITS (VR_BCR0_RX_FIFO_THRESHOLD_0 | \ 313 VR_BCR0_RX_FIFO_THRESHOLD_1 | \ 314 VR_BCR0_RX_FIFO_THRESHOLD_2) 315 #define VR_BCR0_RX_FIFO_THRESHOLD_64 (0) 316 #define VR_BCR0_RX_FIFO_THRESHOLD_32 (VR_BCR0_RX_FIFO_THRESHOLD_0) 317 #define VR_BCR0_RX_FIFO_THRESHOLD_128 (VR_BCR0_RX_FIFO_THRESHOLD_1) 318 #define VR_BCR0_RX_FIFO_THRESHOLD_256 (VR_BCR0_RX_FIFO_THRESHOLD_0 | \ 319 VR_BCR0_RX_FIFO_THRESHOLD_1) 320 #define VR_BCR0_RX_FIFO_THRESHOLD_512 (VR_BCR0_RX_FIFO_THRESHOLD_2) 321 #define VR_BCR0_RX_FIFO_THRESHOLD_768 (VR_BCR0_RX_FIFO_THRESHOLD_0 | \ 322 VR_BCR0_RX_FIFO_THRESHOLD_2) 323 #define VR_BCR0_RX_FIFO_THRESHOLD_1024 (VR_BCR0_RX_FIFO_THRESHOLD_1 | \ 324 VR_BCR0_RX_FIFO_THRESHOLD_2) 325 #define VR_BCR0_RX_FIFO_THRESHOLD_STFW (VR_BCR0_RX_FIFO_THRESHOLD_BITS) 326 #define VR_BCR0_LEDCR (1 << 6) 327 #define VR_BCR0_MSEL (1 << 7) 328 329 #define VR_BCR1 0x6F /* transmit */ 330 #define VR_BCR1_POLLT_0 (1 << 0) 331 #define VR_BCR1_POLLT_1 (1 << 1) 332 #define VR_BCR1_POLLT_2 (1 << 2) 333 #define VR_BCR1_TX_FIFO_THRESHOLD_0 (1 << 3) 334 #define VR_BCR1_TX_FIFO_THRESHOLD_1 (1 << 4) 335 #define VR_BCR1_TX_FIFO_THRESHOLD_2 (1 << 5) 336 #define VR_BCR1_TX_FIFO_THRESHOLD_BITS (VR_BCR1_TX_FIFO_THRESHOLD_0 | \ 337 VR_BCR1_TX_FIFO_THRESHOLD_1 | \ 338 VR_BCR1_TX_FIFO_THRESHOLD_2) 339 #define VR_BCR1_TX_FIFO_THRESHOLD_128 (0) 340 #define VR_BCR1_TX_FIFO_THRESHOLD_256 (VR_BCR1_TX_FIFO_THRESHOLD_0) 341 #define VR_BCR1_TX_FIFO_THRESHOLD_512 (VR_BCR1_TX_FIFO_THRESHOLD_1) 342 #define VR_BCR1_TX_FIFO_THRESHOLD_1024 (VR_BCR1_TX_FIFO_THRESHOLD_0 | \ 343 VR_BCR1_FIFO_THRESHOLD_1) 344 #define VR_BCR1_TX_FIFO_THRESHOLD_STFW (VR_BCR1_FIFO_THRESHOLD_BITS) 345 #define VR_BCR1_TXQPRIO (1 << 6) /* VT6105M */ 346 #define VR_BCR1_VLANFILTER (1 << 7) /* VT6105M */ 347 348 /* 349 * MII Configuration 350 */ 351 #define VR_MIICMD 0x70 352 #define VR_MIICMD_MD_CLOCK (1 << 0) 353 #define VR_MIICMD_MD_CLOCK_READ (1 << 1) 354 #define VR_MIICMD_MD_CLOCK_WRITE (1 << 2) 355 #define VR_MIICMD_MD_OUT (1 << 3) 356 #define VR_MIICMD_MD_MODE_AUTO (1 << 4) 357 #define VR_MIICMD_MD_WRITE (1 << 5) 358 #define VR_MIICMD_MD_READ (1 << 6) 359 #define VR_MIICMD_MD_AUTO (1 << 7) 360 361 #define VR_MIIADDR 0x71 362 #define VR_MIIADDR_MAD0 (1 << 0) 363 #define VR_MIIADDR_MAD1 (1 << 1) 364 #define VR_MIIADDR_MAD2 (1 << 2) 365 #define VR_MIIADDR_MAD3 (1 << 3) 366 #define VR_MIIADDR_MAD4 (1 << 4) 367 #define VR_MIIADDR_BITS (VR_MIIADDR_MAD0 | \ 368 VR_MIIADDR_MAD1 | \ 369 VR_MIIADDR_MAD2 | \ 370 VR_MIIADDR_MAD3 | \ 371 VR_MIIADDR_MAD4) 372 #define VR_MIIADDR_MDONE (1 << 5) 373 #define VR_MIIADDR_MAUTO (1 << 6) 374 #define VR_MIIADDR_MIDLE (1 << 7) 375 376 #define VR_MIIDATA 0x72 377 #define VR_MIIDATA_1 0x72 378 #define VR_MIIDATA_2 0x73 379 380 /* 381 * EEPROM Config / Status 382 */ 383 #define VR_PROMCTL 0x74 384 #define VR_PROMCTL_DATAOUT (1 << 0) 385 #define VR_PROMCTL_DATAIN (1 << 1) 386 #define VR_PROMCTL_CLOCK (1 << 2) 387 #define VR_PROMCTL_CHIPSELECT (1 << 3) 388 #define VR_PROMCTL_DIRPROG (1 << 4) 389 #define VR_PROMCTL_RELOAD (1 << 5) 390 #define VR_PROMCTL_PROGRAM (1 << 6) 391 #define VR_PROMCTL_PRGSTATUS (1 << 7) 392 393 /* 394 * Chip Configuration A 395 */ 396 #define VR_CFGA 0x78 397 #define VR_CFGA_PRE_ACPI_WAKEUP (1 << 0) /* VT6105M */ 398 #define VR_CFGA_WAKEUP_PANIC (1 << 1) /* VT6105M */ 399 #define VR_CFGA_VLANTAG_INCRC (1 << 5) /* VT6105M */ 400 #define VR_CFGA_MIIOPT (1 << 6) 401 #define VR_CFGA_EELOAD (1 << 7) 402 403 /* 404 * Chip Configuration B 405 */ 406 #define VR_CFGB 0x79 407 #define VR_CFGB_LATENCYTIMER (1 << 0) 408 #define VR_CFGB_WWAIT (1 << 1) 409 #define VR_CFGB_RWAIT (1 << 2) 410 #define VR_CFGB_RXARBIT (1 << 3) 411 #define VR_CFGB_TXARBIT (1 << 4) 412 #define VR_CFGB_MRLDIS (1 << 5) 413 #define VR_CFGB_PERRDIS (1 << 6) 414 #define VR_CFGB_QPKTDIS (1 << 7) 415 416 /* 417 * Chip Configuration C 418 */ 419 #define VR_CFGC 0x7A 420 #define VR_CFGC_BPS0 (1 << 0) 421 #define VR_CFGC_BPS1 (1 << 1) 422 #define VR_CFGC_BPS2 (1 << 2) 423 #define VR_CFGC_BTSEL (1 << 3) 424 #define VR_CFGC_DLYEN (1 << 5) 425 #define VR_CFGC_BROPT (1 << 6) 426 #define VR_CFGC_MED3 (1 << 7) /* VT6102 */ 427 428 /* 429 * Chip Configuration D 430 */ 431 #define VR_CFGD 0x7B 432 #define VR_CFGD_BAKOPT (1 << 0) 433 #define VR_CFGD_MBA (1 << 1) 434 #define VR_CFGD_CAP (1 << 2) 435 #define VR_CFGD_CRADOM (1 << 3) 436 #define VR_CFGD_PMCDIG (1 << 4) 437 #define VR_CFGD_MRLEN (1 << 5) 438 #define VR_CFGD_TAG_ON_SNAP (1 << 5) /* VT6105M */ 439 #define VR_CFGD_DIAG (1 << 6) 440 #define VR_CFGD_MMIOEN (1 << 7) 441 442 /* 443 * Tally counters 444 */ 445 #define VR_TALLY_MPA 0x7c /* 16 bits */ 446 #define VR_TALLY_CRC 0x7e /* 16 bits */ 447 448 /* 449 * Misceleneous register 0 450 */ 451 #define VR_MISC0 0x80 452 #define VR_MISC0_TIMER0_EN (1 << 0) 453 #define VR_MISC0_TIMER0_SUSP (1 << 1) 454 #define VR_MISC0_HDXFEN (1 << 2) 455 #define VR_MISC0_FDXRFEN (1 << 3) 456 #define VR_MISC0_FDXTFEN (1 << 4) 457 #define VR_MISC0_TIMER0_USEC_EN (1 << 5) 458 459 /* 460 * Misceleneous register 1 461 */ 462 #define VR_MISC1 0x81 463 #define VR_MISC1_TIMER1_EN (1 << 0) 464 #define VR_MISC1_VAXJMP (1 << 5) 465 #define VR_MISC1_RESET (1 << 6) 466 467 /* 468 * Power management 469 */ 470 #define VR_PWR 0x83 471 #define VR_PWR_DS0 (1 << 0) 472 #define VR_PWR_DS1 (1 << 1) 473 #define VR_PWR_WOLEN (1 << 2) 474 #define VR_PWR_WOLSR (1 << 3) 475 #define VR_PWR_LGWOL (1 << 7) 476 477 /* 478 * Second interrupt register status 479 */ 480 #define VR_ISR1 0x84 481 #define VR_ISR1_TIMER0 (1 << 0) 482 #define VR_ISR1_TIMER1 (1 << 1) 483 #define VR_ISR1_PHYEVENT (1 << 2) 484 #define VR_ISR1_TDERR (1 << 3) 485 #define VR_ISR1_SSRCI (1 << 4) 486 #define VR_ISR1_UINTR_SET (1 << 5) 487 #define VR_ISR1_UINTR_CLR (1 << 6) 488 #define VR_ISR1_PWEI (1 << 7) 489 490 /* 491 * Second interrupt register configuration 492 */ 493 #define VR_ICR1 0x86 494 #define VR_ICR1_TIMER0 VR_ISR1_TIMER0 495 #define VR_ICR1_TIMER1 VR_ISR1_TIMER1 496 #define VR_ICR1_PHYEVENT VR_ISR1_PHYEVENT 497 #define VR_ICR1_TDERR VR_ISR1_TDERR 498 #define VR_ICR1_SSRCI VR_ISR1_SSRCI 499 #define VR_ICR1_UINTR_SET VR_ISR1_UINTR_SET 500 #define VR_ICR1_UINTR_CLR VR_ISR1_UINTR_CLR 501 #define VR_ICR1_PWEI VR_ISR1_PWEI 502 503 /* 504 * Content Addressable Memory (CAM) stuff for the VT6105M 505 */ 506 #define VR_CAM_MASK 0x88 507 508 #define VR_CAM_CTRL 0x92 509 #define VR_CAM_CTRL_RD (1 << 3) 510 #define VR_CAM_CTRL_WR (1 << 2) 511 #define VR_CAM_CTRL_SELECT_VLAN (1 << 1) 512 #define VR_CAM_CTRL_ENABLE (1 << 0) 513 #define VR_CAM_CTRL_WRITE (VR_CAM_CTRL_ENABLE | VR_CAM_CTRL_WR) 514 #define VR_CAM_CTRL_READ (VR_CAM_CTRL_ENABLE | VR_CAM_CTRL_RD) 515 #define VR_CAM_CTRL_RW (VR_CAM_CTRL_ENABLE | \ 516 VR_CAM_CTRL_RD | VR_CAM_CTRL_WR) 517 #define VR_CAM_CTRL_DONE (0) 518 519 #define VR_CAM_ADDR 0x93 520 521 /* 522 * MIB Control register 523 */ 524 #define VR_MIB_CTRL 0x94 525 #define VR_MIB_CTRL_ENABLE (1 << 4) 526 #define VR_MIB_CTRL_HDUPLEX (1 << 5) 527 #define VR_MIB_CTRL_INCR (1 << 6) 528 #define VR_MIB_CTRL_RTN (1 << 7) 529 530 /* 531 * MIB port 532 */ 533 #define VR_MIB_PORT 0x96 534 535 /* 536 * MIB data 537 */ 538 #define VR_MIB_DATA 0x97 539 540 541 /* 542 * Power configuration 543 */ 544 #define VR_PWRCFG 0xA1 /* VT6105LOM */ 545 #define VR_PWRCFG_WOLEN (1 << 0) 546 #define VR_PWRCFG_WOLSR (1 << 1) 547 #define VR_PWRCFG_PHYPOWERDOWN (7 << 1) 548 549 /* 550 * Flow control, VT6105 and above 551 */ 552 #define VR_FCR0 0x98 553 #define VR_FCR0_RXBUFCOUNT VR_FCR0 554 555 #define VR_FCR1 0x99 556 #define VR_FCR1_HD_EN (1 << 0) 557 #define VR_FCR1_FD_RX_EN (1 << 1) 558 #define VR_FCR1_FD_TX_EN (1 << 2) 559 #define VR_FCR1_XONXOFF_EN (1 << 3) 560 561 #define VR_FCR1_PAUSEOFFBITS ((1 << 5) | (1 << 4)) 562 #define VR_FCR1_PAUSEOFF_24 ((0 << 5) | (0 << 4)) 563 #define VR_FCR1_PAUSEOFF_32 ((0 << 5) | (1 << 4)) 564 #define VR_FCR1_PAUSEOFF_48 ((1 << 5) | (0 << 4)) 565 #define VR_FCR1_PAUSEOFF_64 ((1 << 5) | (1 << 4)) 566 567 #define VR_FCR1_PAUSEONBITS ((1 << 7) | (1 << 6)) 568 #define VR_FCR1_PAUSEON_04 ((0 << 7) | (0 << 6)) 569 #define VR_FCR1_PAUSEON_08 ((0 << 7) | (1 << 6)) 570 #define VR_FCR1_PAUSEON_16 ((1 << 7) | (0 << 6)) 571 #define VR_FCR1_PAUSEON_24 ((1 << 7) | (1 << 6)) 572 573 #define VR_FCR2 0x9a 574 #define VR_FCR2_PAUSE (VR_FCR2) 575 576 #define VR_TIMER0 0x9c 577 #define VR_TIMER0_TIMEOUT VR_TIMER0 /* 16 bits */ 578 579 #define VR_TIMER1 0x9e 580 #define VR_TIMER1_TIMEOUT VR_TIMER1 /* 16 bits */ 581 582 #define VR_CRC_PATTERN0 0xb0 /* 32 bits, VT6105M */ 583 #define VR_CRC_PATTERN1 0xb4 /* 32 bits, VT6105M */ 584 #define VR_CRC_PATTERN2 0xb8 /* 32 bits, VT6105M */ 585 #define VR_CRC_PATTERN3 0xbC /* 32 bits, VT6105M */ 586 587 /* 588 * Receive desctriptor 589 */ 590 #define VR_RDES0_RXERR (1 << 0) 591 #define VR_RDES0_CRCERR (1 << 1) 592 #define VR_RDES0_FAE (1 << 2) 593 #define VR_RDES0_FOV (1 << 3) 594 #define VR_RDES0_LONG (1 << 4) 595 #define VR_RDES0_RUNT (1 << 5) 596 #define VR_RDES0_SERR (1 << 6) 597 #define VR_RDES0_BUFF (1 << 7) 598 599 #define VR_RDES0_EDP (1 << 8) 600 #define VR_RDES0_STP (1 << 9) 601 #define VR_RDES0_CHN (1 << 10) 602 #define VR_RDES0_PHY (1 << 11) 603 #define VR_RDES0_BAR (1 << 12) 604 #define VR_RDES0_MAR (1 << 13) 605 #define VR_RDES0_VIDHIT (1 << 14) /* VT6105M or reserved */ 606 #define VR_RDES0_RXOK (1 << 15) 607 608 #define VR_RDES0_ABN ((1 << 27) | (1 << 28) | (1 << 29) | (1 << 30)) 609 #define VR_RDES0_OWN (1U << 31) 610 611 /* 612 * Transmit descriptor 613 */ 614 #define VR_TDES0_NCR ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) 615 #define VR_TDES0_COL (1 << 4) 616 #define VR_TDES0_CDH (1 << 7) 617 #define VR_TDES0_ABT (1 << 8) 618 #define VR_TDES0_OWC (1 << 9) 619 #define VR_TDES0_CRS (1 << 10) 620 #define VR_TDES0_UDF (1 << 11) 621 #define VR_TDES0_TERR (1 << 15) 622 /* VLAN stuff is for VT6105M only */ 623 #define VR_TDES0_VLANID ((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24) \ 624 (1 << 23) | (1 << 22) | (1 << 21) | \ 625 (1 << 20) | (1 << 19) | (1 << 18) | \ 626 (1 << 17) | (1 << 16)) 627 #define VR_TDES0_VLANPRI ((1 << 30) | (1 << 29) | (1 << 28)) 628 #define VR_TDES0_OWN (1U << 31) 629 630 #define VR_TDES1_LEN ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | \ 631 (1 << 4) | (1 << 5) | (1 << 6) | \ 632 (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10)) 633 634 #define VR_TDES1_CHN (1 << 15) 635 #define VR_TDES1_CRC (1 << 16) 636 #define VR_TDES1_STP (1 << 21) /* EDP/STP are flipped in DS6105! */ 637 #define VR_TDES1_EDP (1 << 22) 638 #define VR_TDES1_INTR (1 << 23) 639 640 #define VR_TDES3_SUPPRESS_INTR (1 << 0) 641 642 #endif /* _VRREG_H */ 643